aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6')
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/MIMX8UX6_cm4.h144416
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/MIMX8UX6_cm4_features.h587
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/driver_reset.cmake14
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_clock.c389
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_clock.h526
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/drivers/fsl_memory.h108
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/fsl_device_registers.h35
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/gcc/MIMX8UX6xxxxx_cm4_ddr_ram.ld247
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/gcc/MIMX8UX6xxxxx_cm4_ram.ld226
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/gcc/startup_MIMX8UX6_cm4.S3044
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/project_template/board.c213
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/project_template/board.h56
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/project_template/clock_config.c73
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/project_template/clock_config.h29
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/project_template/peripherals.c24
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/project_template/peripherals.h25
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/project_template/pin_mux.c58
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/project_template/pin_mux.h47
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/main/imx8qx_pads.h225
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/main/ipc.h92
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/main/ipc_imx8qx.c159
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/main/rpc.h175
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/main/scfw.h60
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/main/types.h918
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/irq/irq_api.h200
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/irq/irq_rpc.h72
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/irq/irq_rpc_clnt.c105
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/misc/misc_api.h489
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/misc/misc_rpc.h92
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/misc/misc_rpc_clnt.c530
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/pad/pad_api.h596
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/pad/pad_rpc.h86
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/pad/pad_rpc_clnt.c512
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/pm/pm_api.h896
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/pm/pm_rpc.h99
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/pm/pm_rpc_clnt.c683
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/rm/rm_api.h888
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/rm/rm_rpc.h103
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/rm/rm_rpc_clnt.c775
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/seco/seco_api.h803
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/seco/seco_rpc.h97
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/seco/seco_rpc_clnt.c659
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/timer/timer_api.h413
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/timer/timer_rpc.h89
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/scfw_api/svc/timer/timer_rpc_clnt.c479
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/system_MIMX8UX6_cm4.c175
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/system_MIMX8UX6_cm4.h127
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/template/RTE_Device.h212
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/utilities/fsl_notifier.c209
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/utilities/fsl_notifier.h237
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/utilities/fsl_shell.c1085
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/utilities/fsl_shell.h292
52 files changed, 162749 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/MIMX8UX6_cm4.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/MIMX8UX6_cm4.h
new file mode 100644
index 000000000..90eb0e9b9
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMX8UX6/MIMX8UX6_cm4.h
@@ -0,0 +1,144416 @@
1/*
2** ###################################################################
3** Processors: MIMX8UX6AVLFZ
4** MIMX8UX6AVOFZ
5** MIMX8UX6CVLDZ
6**
7** Compilers: GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10**
11** Reference manual: IMX8DQXPRM, Rev. E, 6/2019
12** Version: rev. 4.0, 2020-06-19
13** Build: b200825
14**
15** Abstract:
16** CMSIS Peripheral Access Layer for MIMX8UX6_cm4
17**
18** Copyright 1997-2016 Freescale Semiconductor, Inc.
19** Copyright 2016-2020 NXP
20** All rights reserved.
21**
22** SPDX-License-Identifier: BSD-3-Clause
23**
24** http: www.nxp.com
25** mail: [email protected]
26**
27** Revisions:
28** - rev. 1.0 (2016-06-02)
29** Initial version.
30** - rev. 2.0 (2017-08-23)
31** RevA Header EAR
32** - rev. 3.0 (2018-08-22)
33** RevB Header EAR
34** - rev. 4.0 (2020-06-19)
35** RevC Header RFP
36**
37** ###################################################################
38*/
39
40/*!
41 * @file MIMX8UX6_cm4.h
42 * @version 4.0
43 * @date 2020-06-19
44 * @brief CMSIS Peripheral Access Layer for MIMX8UX6_cm4
45 *
46 * CMSIS Peripheral Access Layer for MIMX8UX6_cm4
47 */
48
49#ifndef _MIMX8UX6_CM4_H_
50#define _MIMX8UX6_CM4_H_ /**< Symbol preventing repeated inclusion */
51
52/** Memory map major version (memory maps with equal major version number are
53 * compatible) */
54#define MCU_MEM_MAP_VERSION 0x0400U
55/** Memory map minor version */
56#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
57
58
59/* ----------------------------------------------------------------------------
60 -- Interrupt vector numbers
61 ---------------------------------------------------------------------------- */
62
63/*!
64 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
65 * @{
66 */
67
68/** Interrupt Number Definitions */
69#define NUMBER_OF_INT_VECTORS 611 /**< Number of interrupts in the Vector table */
70
71typedef enum IRQn {
72 /* Auxiliary constants */
73 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
74
75 /* Core interrupts */
76 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
77 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
78 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
79 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
80 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
81 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
82 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
83 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
84 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
85
86 /* Device specific interrupts */
87 Reserved16_IRQn = 0, /**< Reserved */
88 Reserved17_IRQn = 1, /**< Reserved */
89 Reserved18_IRQn = 2, /**< Reserved */
90 Reserved19_IRQn = 3, /**< Reserved */
91 Reserved20_IRQn = 4, /**< Reserved */
92 M4_MCM_IRQn = 5, /**< MCM IRQ */
93 Reserved22_IRQn = 6, /**< Reserved */
94 Reserved23_IRQn = 7, /**< Reserved */
95 Reserved24_IRQn = 8, /**< Reserved */
96 Reserved25_IRQn = 9, /**< Reserved */
97 Reserved26_IRQn = 10, /**< Reserved */
98 Reserved27_IRQn = 11, /**< Reserved */
99 Reserved28_IRQn = 12, /**< Reserved */
100 Reserved29_IRQn = 13, /**< Reserved */
101 Reserved30_IRQn = 14, /**< Reserved */
102 Reserved31_IRQn = 15, /**< Reserved */
103 Reserved32_IRQn = 16, /**< Reserved */
104 Reserved33_IRQn = 17, /**< Reserved */
105 Reserved34_IRQn = 18, /**< Reserved */
106 M4_TPM_IRQn = 19, /**< Timer PWM Module */
107 Reserved36_IRQn = 20, /**< Reserved */
108 Reserved37_IRQn = 21, /**< Reserved */
109 M4_LPIT_IRQn = 22, /**< Low-Power Periodic Interrupt Timer */
110 Reserved39_IRQn = 23, /**< Reserved */
111 Reserved40_IRQn = 24, /**< Reserved */
112 M4_LPUART_IRQn = 25, /**< Low Power UART */
113 Reserved42_IRQn = 26, /**< Reserved */
114 M4_LPI2C_IRQn = 27, /**< Low-Power I2C - Logical OR of master and slave interrupts */
115 Reserved44_IRQn = 28, /**< Reserved */
116 M4_MU0_B0_IRQn = 29, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 0, Logical OR of all general-purpose, TX, and RX interrupts */
117 Reserved46_IRQn = 30, /**< Reserved */
118 Reserved47_IRQn = 31, /**< Reserved */
119 IRQSTEER_0_IRQn = 32, /**< External interrupt 0 */
120 IRQSTEER_1_IRQn = 33, /**< External interrupt 1 */
121 IRQSTEER_2_IRQn = 34, /**< External interrupt 2 */
122 IRQSTEER_3_IRQn = 35, /**< External interrupt 3 */
123 IRQSTEER_4_IRQn = 36, /**< External interrupt 4 */
124 IRQSTEER_5_IRQn = 37, /**< External interrupt 5 */
125 IRQSTEER_6_IRQn = 38, /**< External interrupt 6 */
126 IRQSTEER_7_IRQn = 39, /**< External interrupt 7 */
127 Reserved56_IRQn = 40, /**< Reserved */
128 Reserved57_IRQn = 41, /**< Reserved */
129 Reserved58_IRQn = 42, /**< Reserved */
130 Reserved59_IRQn = 43, /**< Reserved */
131 M4_MU0_B1_IRQn = 44, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 1, Logical OR of all general-purpose, TX, and RX interrupts */
132 M4_MU0_B2_IRQn = 45, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 2, Logical OR of all general-purpose, TX, and RX interrupts */
133 M4_MU0_B3_IRQn = 46, /**< Messaging Unit 0 (IPC with other subsystems) - Side B (local), Port 3, Logical OR of all general-purpose, TX, and RX interrupts */
134 Reserved63_IRQn = 47, /**< Reserved */
135 Reserved64_IRQn = 48, /**< Reserved */
136 M4_MU1_A_IRQn = 49, /**< Messaging Unit 1 (IPC with System Controller) - Side A (MCU), Logical OR of all general-purpose, TX, and RX interrupts */
137 M4_SW_IRQn = 50, /**< Software interrupt (asserted/cleared via NVIC registers, INTISR[50] input tied low) */
138 A35_NINTERRIRQ_IRQn = 83, /**< Shared Int Source nINTERRIRQ from A35 Sub-System */
139 A35_NEXTERRIRQ_IRQn = 84, /**< Shared Int Source nEXTERRIRQ from A35 Sub-System */
140 M4_INT_OUT0_IRQn = 99, /**< Shared Int Source INT_OUT[0] from M4 Sub-System */
141 M4_INT_OUT1_IRQn = 100, /**< Shared Int Source INT_OUT[1] from M4 Sub-System */
142 M4_INT_OUT2_IRQn = 101, /**< Shared Int Source INT_OUT[2] from M4 Sub-System */
143 M4_INT_OUT3_IRQn = 102, /**< Shared Int Source INT_OUT[3] from M4 Sub-System */
144 M4_INT_OUT4_IRQn = 103, /**< Shared Int Source INT_OUT[4] from M4 Sub-System */
145 M4_INT_OUT5_IRQn = 104, /**< Shared Int Source INT_OUT[5] from M4 Sub-System */
146 M4_INT_OUT6_IRQn = 105, /**< Shared Int Source INT_OUT[6] from M4 Sub-System */
147 M4_INT_OUT7_IRQn = 106, /**< Shared Int Source INT_OUT[7] from M4 Sub-System */
148 DISPLAY0_INT_OUT0_IRQn = 123, /**< Shared Int Source INT_OUT[0] from Display0 Sub-System */
149 DISPLAY0_INT_OUT1_IRQn = 124, /**< Shared Int Source INT_OUT[1] from Display0 Sub-System */
150 DISPLAY0_INT_OUT2_IRQn = 125, /**< Shared Int Source INT_OUT[2] from Display0 Sub-System */
151 DISPLAY0_INT_OUT3_IRQn = 126, /**< Shared Int Source INT_OUT[3] from Display0 Sub-System */
152 DISPLAY0_INT_OUT4_IRQn = 127, /**< Shared Int Source INT_OUT[4] from Display0 Sub-System */
153 DISPLAY0_INT_OUT5_IRQn = 128, /**< Shared Int Source INT_OUT[5] from Display0 Sub-System */
154 DISPLAY0_INT_OUT6_IRQn = 129, /**< Shared Int Source INT_OUT[6] from Display0 Sub-System */
155 DISPLAY0_INT_OUT7_IRQn = 130, /**< Shared Int Source INT_OUT[7] from Display0 Sub-System */
156 DISPLAY0_RESERVED_IRQn = 131, /**< Shared Int Source Reserved from Display0 Sub-System */
157 DISPLAY0_INT_OUT9_IRQn = 132, /**< Shared Int Source INT_OUT[9] from Display0 Sub-System */
158 DISPLAY0_INT_OUT10_IRQn = 133, /**< Shared Int Source INT_OUT[10] from Display0 Sub-System */
159 DISPLAY0_INT_OUT11_IRQn = 134, /**< Shared Int Source INT_OUT[11] from Display0 Sub-System */
160 DISPLAY0_INT_OUT12_IRQn = 135, /**< Shared Int Source INT_OUT[12] from Display0 Sub-System */
161 MIPI_DSI0_INT_OUT_IRQn = 142, /**< Shared Int Source INT_OUT from MIPI_DSI0 Sub-System */
162 MIPI_DSI1_INT_OUT_IRQn = 143, /**< Shared Int Source INT_OUT from MIPI_DSI1 Sub-System */
163 LCD_MOD_INT_IRQn = 145, /**< Shared Int Source INT_OUT from ADMA Sub-System */
164 LCD_PWM_INT_IRQn = 146, /**< Shared Int Source INT_OUT from ADMA Sub-System */
165 GPU0_XAQ2_INTR_IRQn = 147, /**< Shared Int Source xaq2_intr from GPU0 Sub-System */
166 ADMA_EDMA2_INT_IRQn = 149, /**< Shared Int Source eDMA2_INT from ADMA Sub-System */
167 ADMA_EDMA2_ERR_INT_IRQn = 150, /**< Shared Int Source eDMA2_ERR_INT from ADMA Sub-System */
168 ADMA_EDMA3_INT_IRQn = 151, /**< Shared Int Source eDMA3_INT from ADMA Sub-System */
169 ADMA_EDMA3_ERR_INT_IRQn = 152, /**< Shared Int Source eDMA3_ERR_INT from ADMA Sub-System */
170 LSIO_GPT0_INT_IRQn = 163, /**< Shared Int Source GPT0_INT from LSIO Sub-System */
171 LSIO_GPT1_INT_IRQn = 164, /**< Shared Int Source GPT1_INT from LSIO Sub-System */
172 LSIO_GPT2_INT_IRQn = 165, /**< Shared Int Source GPT2_INT from LSIO Sub-System */
173 LSIO_GPT3_INT_IRQn = 166, /**< Shared Int Source GPT3_INT from LSIO Sub-System */
174 LSIO_GPT4_INT_IRQn = 167, /**< Shared Int Source GPT4_INT from LSIO Sub-System */
175 LSIO_KPP_INT_IRQn = 168, /**< Shared Int Source KPP_INT from LSIO Sub-System */
176 LSIO_OCTASPI0_INT_IRQn = 175, /**< Shared Int Source OctaSPI0_INT from LSIO Sub-System */
177 LSIO_OCTASPI1_INT_IRQn = 176, /**< Shared Int Source OctaSPI1_INT from LSIO Sub-System */
178 LSIO_PWM0_INT_IRQn = 177, /**< Shared Int Source PWM0_INT from LSIO Sub-System */
179 LSIO_PWM1_INT_IRQn = 178, /**< Shared Int Source PWM1_INT from LSIO Sub-System */
180 LSIO_PWM2_INT_IRQn = 179, /**< Shared Int Source PWM2_INT from LSIO Sub-System */
181 LSIO_PWM3_INT_IRQn = 180, /**< Shared Int Source PWM3_INT from LSIO Sub-System */
182 LSIO_PWM4_INT_IRQn = 181, /**< Shared Int Source PWM4_INT from LSIO Sub-System */
183 LSIO_PWM5_INT_IRQn = 182, /**< Shared Int Source PWM5_INT from LSIO Sub-System */
184 LSIO_PWM6_INT_IRQn = 183, /**< Shared Int Source PWM6_INT from LSIO Sub-System */
185 LSIO_PWM7_INT_IRQn = 184, /**< Shared Int Source PWM7_INT from LSIO Sub-System */
186 HSIO_PCIEB_MSI_CTRL_INT_IRQn = 185, /**< Shared Int Source PCIeB_MSI_CTRL_INT from HSIO Sub-System */
187 HSIO_PCIEB_CLK_REQ_INT_IRQn = 186, /**< Shared Int Source PCIeB_CLK_REQ_INT from HSIO Sub-System */
188 HSIO_PCIEB_DMA_INT_IRQn = 187, /**< Shared Int Source PCIeB_DMA_INT from HSIO Sub-System */
189 HSIO_PCIEB_INT_D_IRQn = 188, /**< Shared Int Source PCIeB_INT_D from HSIO Sub-System */
190 HSIO_PCIEB_INT_C_IRQn = 189, /**< Shared Int Source PCIeB_INT_C from HSIO Sub-System */
191 HSIO_PCIEB_INT_B_IRQn = 190, /**< Shared Int Source PCIeB_INT_B from HSIO Sub-System */
192 HSIO_PCIEB_INT_A_IRQn = 191, /**< Shared Int Source PCIeB_INT_A from HSIO Sub-System */
193 HSIO_PCIEB_SMLH_REQ_RST_IRQn = 192, /**< Shared Int Source PCIeB_SMLH_REQ_RST from HSIO Sub-System */
194 HSIO_PCIEB_GPIO_WAKEUP0_IRQn = 193, /**< Shared Int Source PCIeB_GPIO_WAKEUP[0] from HSIO Sub-System */
195 HSIO_PCIEB_GPIO_WAKEUP1_IRQn = 194, /**< Shared Int Source PCIeB_GPIO_WAKEUP[1] from HSIO Sub-System */
196 SCU_INT_OUT0_IRQn = 195, /**< Shared Int Source INT_OUT[0] from SCU Sub-System */
197 SCU_INT_OUT1_IRQn = 196, /**< Shared Int Source INT_OUT[1] from SCU Sub-System */
198 SCU_INT_OUT2_IRQn = 197, /**< Shared Int Source INT_OUT[2] from SCU Sub-System */
199 SCU_INT_OUT3_IRQn = 198, /**< Shared Int Source INT_OUT[3] from SCU Sub-System */
200 SCU_INT_OUT4_IRQn = 199, /**< Shared Int Source INT_OUT[4] from SCU Sub-System */
201 SCU_INT_OUT5_IRQn = 200, /**< Shared Int Source INT_OUT[5] from SCU Sub-System */
202 SCU_INT_OUT6_IRQn = 201, /**< Shared Int Source INT_OUT[6] from SCU Sub-System */
203 SCU_INT_OUT7_IRQn = 202, /**< Shared Int Source INT_OUT[7] from SCU Sub-System */
204 SCU_SYS_COUNT_INT0_IRQn = 203, /**< Shared Int Source SYS_COUNT_INT0 from SCU Sub-System */
205 SCU_SYS_COUNT_INT1_IRQn = 204, /**< Shared Int Source SYS_COUNT_INT1 from SCU Sub-System */
206 SCU_SYS_COUNT_INT2_IRQn = 205, /**< Shared Int Source SYS_COUNT_INT2 from SCU Sub-System */
207 SCU_SYS_COUNT_INT3_IRQn = 206, /**< Shared Int Source SYS_COUNT_INT3 from SCU Sub-System */
208 DRC_ECC_CORRECT_INT_IRQn = 211, /**< Shared Int Source ECC_CORRECT_INT from DRC Sub-System */
209 DRC_ECC_NCORRECT_INT_IRQn = 212, /**< Shared Int Source ECC_NCORRECT_INT from DRC Sub-System */
210 DRC_SBR_DONE_INT_IRQn = 213, /**< Shared Int Source SBR_DONE_INT from DRC Sub-System */
211 DRC_PERF_CNT_INT_IRQn = 214, /**< Shared Int Source PERF_CNT_INT from DRC Sub-System */
212 LSIO_GPIO_INT0_IRQn = 219, /**< Shared Int Source GPIO_INT[0] from LSIO Sub-System */
213 LSIO_GPIO_INT1_IRQn = 220, /**< Shared Int Source GPIO_INT[1] from LSIO Sub-System */
214 LSIO_GPIO_INT2_IRQn = 221, /**< Shared Int Source GPIO_INT[2] from LSIO Sub-System */
215 LSIO_GPIO_INT3_IRQn = 222, /**< Shared Int Source GPIO_INT[3] from LSIO Sub-System */
216 LSIO_GPIO_INT4_IRQn = 223, /**< Shared Int Source GPIO_INT[4] from LSIO Sub-System */
217 LSIO_GPIO_INT5_IRQn = 224, /**< Shared Int Source GPIO_INT[5] from LSIO Sub-System */
218 LSIO_GPIO_INT6_IRQn = 225, /**< Shared Int Source GPIO_INT[6] from LSIO Sub-System */
219 LSIO_GPIO_INT7_IRQn = 226, /**< Shared Int Source GPIO_INT[7] from LSIO Sub-System */
220 LSIO_MU0_INT_IRQn = 259, /**< Shared Int Source MU0_INT from LSIO Sub-System */
221 LSIO_MU1_INT_IRQn = 260, /**< Shared Int Source MU1_INT from LSIO Sub-System */
222 LSIO_MU2_INT_IRQn = 261, /**< Shared Int Source MU2_INT from LSIO Sub-System */
223 LSIO_MU3_INT_IRQn = 262, /**< Shared Int Source MU3_INT from LSIO Sub-System */
224 LSIO_MU4_INT_IRQn = 263, /**< Shared Int Source MU4_INT from LSIO Sub-System */
225 LSIO_MU5_INT_A_IRQn = 267, /**< Shared Int Source MU5_INT_A from LSIO Sub-System */
226 LSIO_MU6_INT_A_IRQn = 268, /**< Shared Int Source MU6_INT_A from LSIO Sub-System */
227 LSIO_MU7_INT_A_IRQn = 269, /**< Shared Int Source MU7_INT_A from LSIO Sub-System */
228 LSIO_MU8_INT_A_IRQn = 270, /**< Shared Int Source MU8_INT_A from LSIO Sub-System */
229 LSIO_MU9_INT_A_IRQn = 271, /**< Shared Int Source MU9_INT_A from LSIO Sub-System */
230 LSIO_MU10_INT_A_IRQn = 272, /**< Shared Int Source MU10_INT_A from LSIO Sub-System */
231 LSIO_MU11_INT_A_IRQn = 273, /**< Shared Int Source MU11_INT_A from LSIO Sub-System */
232 LSIO_MU12_INT_A_IRQn = 274, /**< Shared Int Source MU12_INT_A from LSIO Sub-System */
233 LSIO_MU13_INT_A_IRQn = 275, /**< Shared Int Source MU13_INT_A from LSIO Sub-System */
234 LSIO_MU5_INT_B_IRQn = 283, /**< Shared Int Source MU5_INT_B from LSIO Sub-System */
235 LSIO_MU6_INT_B_IRQn = 284, /**< Shared Int Source MU6_INT_B from LSIO Sub-System */
236 LSIO_MU7_INT_B_IRQn = 285, /**< Shared Int Source MU7_INT_B from LSIO Sub-System */
237 LSIO_MU8_INT_B_IRQn = 286, /**< Shared Int Source MU8_INT_B from LSIO Sub-System */
238 LSIO_MU9_INT_B_IRQn = 287, /**< Shared Int Source MU9_INT_B from LSIO Sub-System */
239 LSIO_MU10_INT_B_IRQn = 288, /**< Shared Int Source MU10_INT_B from LSIO Sub-System */
240 LSIO_MU11_INT_B_IRQn = 289, /**< Shared Int Source MU11_INT_B from LSIO Sub-System */
241 LSIO_MU12_INT_B_IRQn = 290, /**< Shared Int Source MU12_INT_B from LSIO Sub-System */
242 LSIO_MU13_INT_B_IRQn = 291, /**< Shared Int Source MU13_INT_B from LSIO Sub-System */
243 ADMA_SPI0_INT_IRQn = 299, /**< Shared Int Source SPI0_INT from ADMA Sub-System */
244 ADMA_SPI1_INT_IRQn = 300, /**< Shared Int Source SPI1_INT from ADMA Sub-System */
245 ADMA_SPI2_INT_IRQn = 301, /**< Shared Int Source SPI2_INT from ADMA Sub-System */
246 ADMA_SPI3_INT_IRQn = 302, /**< Shared Int Source SPI3_INT from ADMA Sub-System */
247 ADMA_I2C0_INT_IRQn = 303, /**< Shared Int Source I2C0_INT from ADMA Sub-System */
248 ADMA_I2C1_INT_IRQn = 304, /**< Shared Int Source I2C1_INT from ADMA Sub-System */
249 ADMA_I2C2_INT_IRQn = 305, /**< Shared Int Source I2C2_INT from ADMA Sub-System */
250 ADMA_I2C3_INT_IRQn = 306, /**< Shared Int Source I2C3_INT from ADMA Sub-System */
251 ADMA_UART0_INT_IRQn = 308, /**< Shared Int Source UART0_INT from ADMA Sub-System */
252 ADMA_UART1_INT_IRQn = 309, /**< Shared Int Source UART1_INT from ADMA Sub-System */
253 ADMA_UART2_INT_IRQn = 310, /**< Shared Int Source UART2_INT from ADMA Sub-System */
254 ADMA_UART3_INT_IRQn = 311, /**< Shared Int Source UART3_INT from ADMA Sub-System */
255 CONNECTIVITY_USDHC0_INT_IRQn = 315, /**< Shared Int Source uSDHC0_INT from Connectivity Sub-System */
256 CONNECTIVITY_USDHC1_INT_IRQn = 316, /**< Shared Int Source uSDHC1_INT from Connectivity Sub-System */
257 CONNECTIVITY_USDHC2_INT_IRQn = 317, /**< Shared Int Source uSDHC2_INT from Connectivity Sub-System */
258 ADMA_FLEXCAN0_INT_IRQn = 318, /**< Shared Int Source FlexCAN0_INT from ADMA Sub-System */
259 ADMA_FLEXCAN1_INT_IRQn = 319, /**< Shared Int Source FlexCAN1_INT from ADMA Sub-System */
260 ADMA_FLEXCAN2_INT_IRQn = 320, /**< Shared Int Source FlexCAN2_INT from ADMA Sub-System */
261 ADMA_FTM0_INT_IRQn = 321, /**< Shared Int Source FTM0_INT from ADMA Sub-System */
262 ADMA_FTM1_INT_IRQn = 322, /**< Shared Int Source FTM1_INT from ADMA Sub-System */
263 ADMA_ADC0_INT_IRQn = 323, /**< Shared Int Source ADC0_INT from ADMA Sub-System */
264 ADMA_EXTERNAL_DMA_INT_0_IRQn = 325, /**< Shared Int Source EXTERNAL_DMA_INT_0 from ADMA Sub-System */
265 ADMA_EXTERNAL_DMA_INT_1_IRQn = 326, /**< Shared Int Source EXTERNAL_DMA_INT_1 from ADMA Sub-System */
266 ADMA_EXTERNAL_DMA_INT_2_IRQn = 327, /**< Shared Int Source EXTERNAL_DMA_INT_2 from ADMA Sub-System */
267 ADMA_EXTERNAL_DMA_INT_3_IRQn = 328, /**< Shared Int Source EXTERNAL_DMA_INT_3 from ADMA Sub-System */
268 ADMA_EXTERNAL_DMA_INT_4_IRQn = 329, /**< Shared Int Source EXTERNAL_DMA_INT_4 from ADMA Sub-System */
269 ADMA_EXTERNAL_DMA_INT_5_IRQn = 330, /**< Shared Int Source EXTERNAL_DMA_INT_5 from ADMA Sub-System */
270 CONNECTIVITY_ENET0_FRAME1_INT_IRQn = 339, /**< Shared Int Source ENET0_FRAME1_INT from Connectivity Sub-System */
271 CONNECTIVITY_ENET0_FRAME2_INT_IRQn = 340, /**< Shared Int Source ENET0_FRAME2_INT from Connectivity Sub-System */
272 CONNECTIVITY_ENET0_FRAME0_EVENT_INT_IRQn = 341, /**< Shared Int Source ENET0_FRAME0_EVENT_INT from Connectivity Sub-System */
273 CONNECTIVITY_ENET0_TIMER_INT_IRQn = 342, /**< Shared Int Source ENET0_TIMER_INT from Connectivity Sub-System */
274 CONNECTIVITY_ENET1_FRAME1_INT_IRQn = 343, /**< Shared Int Source ENET1_FRAME1_INT from Connectivity Sub-System */
275 CONNECTIVITY_ENET1_FRAME2_INT_IRQn = 344, /**< Shared Int Source ENET1_FRAME2_INT from Connectivity Sub-System */
276 CONNECTIVITY_ENET1_FRAME0_EVENT_INT_IRQn = 345, /**< Shared Int Source ENET1_FRAME0_EVENT_INT from Connectivity Sub-System */
277 CONNECTIVITY_ENET1_TIMER_INT_IRQn = 346, /**< Shared Int Source ENET1_TIMER_INT from Connectivity Sub-System */
278 CONNECTIVITY_DTCP_INT_IRQn = 347, /**< Shared Int Source DTCP_INT from Connectivity Sub-System */
279 CONNECTIVITY_MLB_INT_IRQn = 348, /**< Shared Int Source MLB_INT from Connectivity Sub-System */
280 CONNECTIVITY_MLB_AHB_INT_IRQn = 349, /**< Shared Int Source MLB_AHB_INT from Connectivity Sub-System */
281 CONNECTIVITY_USB_OTG_INT_IRQn = 350, /**< Shared Int Source USB_OTG_INT from Connectivity Sub-System */
282 CONNECTIVITY_USB_HOST_INT_IRQn = 351, /**< Shared Int Source USB_HOST_INT from Connectivity Sub-System */
283 CONNECTIVITY_UTMI_INT_IRQn = 352, /**< Shared Int Source UTMI_INT from Connectivity Sub-System */
284 CONNECTIVITY_WAKEUP_INT_IRQn = 353, /**< Shared Int Source WAKEUP_INT from Connectivity Sub-System */
285 CONNECTIVITY_USB3_INT_IRQn = 354, /**< Shared Int Source USB3_INT from Connectivity Sub-System */
286 CONNECTIVITY_ND_FLASH_BCH_INT_IRQn = 355, /**< Shared Int Source ND_FLASH_BCH_INT from Connectivity Sub-System */
287 CONNECTIVITY_ND_FLASH_GPMI_INT_IRQn = 356, /**< Shared Int Source ND_FLASH_GPMI_INT from Connectivity Sub-System */
288 CONNECTIVITY_APBHDMA_IRQn = 357, /**< Shared Int Source APBHDMA from Connectivity Sub-System */
289 CONNECTIVITY_DMA_INT_IRQn = 358, /**< Shared Int Source DMA_INT from Connectivity Sub-System */
290 CONNECTIVITY_DMA_ERR_INT_IRQn = 359, /**< Shared Int Source DMA_ERR_INT from Connectivity Sub-System */
291 IMAGING_MSI_INT_IRQn = 371, /**< Shared Int Source MSI_INT from Imaging Sub-System */
292 IMAGING_PDMA_STREAM0_INT_IRQn = 380, /**< Shared Int Source PDMA_STREAM0_INT from Imaging Sub-System */
293 IMAGING_PDMA_STREAM1_INT_IRQn = 381, /**< Shared Int Source PDMA_STREAM1_INT from Imaging Sub-System */
294 IMAGING_PDMA_STREAM2_INT_IRQn = 382, /**< Shared Int Source PDMA_STREAM2_INT from Imaging Sub-System */
295 IMAGING_PDMA_STREAM3_INT_IRQn = 383, /**< Shared Int Source PDMA_STREAM3_INT from Imaging Sub-System */
296 IMAGING_PDMA_STREAM4_INT_IRQn = 384, /**< Shared Int Source PDMA_STREAM4_INT from Imaging Sub-System */
297 IMAGING_PDMA_STREAM5_INT_IRQn = 385, /**< Shared Int Source PDMA_STREAM5_INT from Imaging Sub-System */
298 IMAGING_PDMA_STREAM6_INT_IRQn = 386, /**< Shared Int Source PDMA_STREAM6_INT from Imaging Sub-System */
299 IMAGING_PDMA_STREAM7_INT_IRQn = 387, /**< Shared Int Source PDMA_STREAM7_INT from Imaging Sub-System */
300 IMAGING_MJPEG_ENC0_INT_IRQn = 388, /**< Shared Int Source MJPEG_ENC0_INT from Imaging Sub-System */
301 IMAGING_MJPEG_ENC1_INT_IRQn = 389, /**< Shared Int Source MJPEG_ENC1_INT from Imaging Sub-System */
302 IMAGING_MJPEG_ENC2_INT_IRQn = 390, /**< Shared Int Source MJPEG_ENC2_INT from Imaging Sub-System */
303 IMAGING_MJPEG_ENC3_INT_IRQn = 391, /**< Shared Int Source MJPEG_ENC3_INT from Imaging Sub-System */
304 IMAGING_MJPEG_DEC0_INT_IRQn = 392, /**< Shared Int Source MJPEG_DEC0_INT from Imaging Sub-System */
305 IMAGING_MJPEG_DEC1_INT_IRQn = 393, /**< Shared Int Source MJPEG_DEC1_INT from Imaging Sub-System */
306 IMAGING_MJPEG_DEC2_INT_IRQn = 394, /**< Shared Int Source MJPEG_DEC2_INT from Imaging Sub-System */
307 IMAGING_MJPEG_DEC3_INT_IRQn = 395, /**< Shared Int Source MJPEG_DEC3_INT from Imaging Sub-System */
308 ADMA_SAI0_MOD_INT_IRQn = 397, /**< Shared Int Source SAI0_MOD_INT from ADMA Sub-System */
309 ADMA_SAI0_DMA_INT_IRQn = 398, /**< Shared Int Source SAI0_DMA_INT from ADMA Sub-System */
310 ADMA_SAI1_MOD_INT_IRQn = 399, /**< Shared Int Source SAI1_MOD_INT from ADMA Sub-System */
311 ADMA_SAI1_DMA_INT_IRQn = 400, /**< Shared Int Source SAI1_DMA_INT from ADMA Sub-System */
312 ADMA_SAI2_MOD_INT_IRQn = 401, /**< Shared Int Source SAI2_MOD_INT from ADMA Sub-System */
313 ADMA_SAI2_DMA_INT_IRQn = 402, /**< Shared Int Source SAI2_DMA_INT from ADMA Sub-System */
314 MIPI_CSI0_OUT_INT_IRQn = 403, /**< Shared Int Source OUT_INT from MIPI_CSI0 Sub-System */
315 ADMA_SAI3_MOD_INT_IRQn = 406, /**< Shared Int Source SAI3_MOD_INT from ADMA Sub-System */
316 ADMA_SAI3_DMA_INT_IRQn = 407, /**< Shared Int Source SAI3_DMA_INT from ADMA Sub-System */
317 ADMA_SAI4_MOD_INT_IRQn = 412, /**< Shared Int Source SAI4_MOD_INT from ADMA Sub-System */
318 ADMA_SAI4_DMA_INT_IRQn = 413, /**< Shared Int Source SAI4_DMA_INT from ADMA Sub-System */
319 ADMA_SAI5_MOD_INT_IRQn = 414, /**< Shared Int Source SAI5_MOD_INT from ADMA Sub-System */
320 ADMA_SAI5_DMA_INT_IRQn = 415, /**< Shared Int Source SAI5_DMA_INT from ADMA Sub-System */
321 ADMA_SPI0_MOD_INT_IRQn = 419, /**< Shared Int Source SPI0_MOD_INT from ADMA Sub-System */
322 ADMA_SPI1_MOD_INT_IRQn = 420, /**< Shared Int Source SPI1_MOD_INT from ADMA Sub-System */
323 ADMA_SPI2_MOD_INT_IRQn = 421, /**< Shared Int Source SPI2_MOD_INT from ADMA Sub-System */
324 ADMA_SPI3_MOD_INT_IRQn = 422, /**< Shared Int Source SPI3_MOD_INT from ADMA Sub-System */
325 ADMA_I2C0_MOD_INT_IRQn = 423, /**< Shared Int Source I2C0_MOD_INT from ADMA Sub-System */
326 ADMA_I2C1_MOD_INT_IRQn = 424, /**< Shared Int Source I2C1_MOD_INT from ADMA Sub-System */
327 ADMA_I2C2_MOD_INT_IRQn = 425, /**< Shared Int Source I2C2_MOD_INT from ADMA Sub-System */
328 ADMA_I2C3_MOD_INT_IRQn = 426, /**< Shared Int Source I2C3_MOD_INT from ADMA Sub-System */
329 ADMA_UART0_MOD_INT_IRQn = 428, /**< Shared Int Source UART0_MOD_INT from ADMA Sub-System */
330 ADMA_UART1_MOD_INT_IRQn = 429, /**< Shared Int Source UART1_MOD_INT from ADMA Sub-System */
331 ADMA_UART2_MOD_INT_IRQn = 430, /**< Shared Int Source UART2_MOD_INT from ADMA Sub-System */
332 ADMA_UART3_MOD_INT_IRQn = 431, /**< Shared Int Source UART3_MOD_INT from ADMA Sub-System */
333 ADMA_FLEXCAN0_MOD_INT_IRQn = 435, /**< Shared Int Source FLEXCAN0_MOD_INT from ADMA Sub-System */
334 ADMA_FLEXCAN1_MOD_INT_IRQn = 436, /**< Shared Int Source FLEXCAN1_MOD_INT from ADMA Sub-System */
335 ADMA_FLEXCAN2_MOD_INT_IRQn = 437, /**< Shared Int Source FLEXCAN2_MOD_INT from ADMA Sub-System */
336 ADMA_FTM0_MOD_INT_IRQn = 438, /**< Shared Int Source FTM0_MOD_INT from ADMA Sub-System */
337 ADMA_FTM1_MOD_INT_IRQn = 439, /**< Shared Int Source FTM1_MOD_INT from ADMA Sub-System */
338 ADMA_ADC0_MOD_INT_IRQn = 440, /**< Shared Int Source ADC0_MOD_INT from ADMA Sub-System */
339 ADMA_FLEXCAN0_DMA_INT_IRQn = 442, /**< Shared Int Source FLEXCAN0_DMA_INT from ADMA Sub-System */
340 ADMA_FLEXCAN1_DMA_INT_IRQn = 443, /**< Shared Int Source FLEXCAN1_DMA_INT from ADMA Sub-System */
341 ADMA_FLEXCAN2_DMA_INT_IRQn = 444, /**< Shared Int Source FLEXCAN2_DMA_INT from ADMA Sub-System */
342 ADMA_FTM0_DMA_INT_IRQn = 445, /**< Shared Int Source FTM0_DMA_INT from ADMA Sub-System */
343 ADMA_FTM1_DMA_INT_IRQn = 446, /**< Shared Int Source FTM1_DMA_INT from ADMA Sub-System */
344 ADMA_ADC0_DMA_INT_IRQn = 447, /**< Shared Int Source ADC0_DMA_INT from ADMA Sub-System */
345 ADMA_EDMA0_INT_IRQn = 451, /**< Shared Int Source eDMA0_INT from ADMA Sub-System */
346 ADMA_EDMA0_ERR_INT_IRQn = 452, /**< Shared Int Source eDMA0_ERR_INT from ADMA Sub-System */
347 ADMA_EDMA1_INT_IRQn = 453, /**< Shared Int Source eDMA1_INT from ADMA Sub-System */
348 ADMA_EDMA1_ERR_INT_IRQn = 454, /**< Shared Int Source eDMA1_ERR_INT from ADMA Sub-System */
349 ADMA_ASRC0_INT1_IRQn = 455, /**< Shared Int Source ASRC0_INT1 from ADMA Sub-System */
350 ADMA_ASRC0_INT2_IRQn = 456, /**< Shared Int Source ASRC0_INT2 from ADMA Sub-System */
351 ADMA_DMA0_CH0_INT_IRQn = 457, /**< Shared Int Source DMA0_CH0_INT from ADMA Sub-System */
352 ADMA_DMA0_CH1_INT_IRQn = 458, /**< Shared Int Source DMA0_CH1_INT from ADMA Sub-System */
353 ADMA_DMA0_CH2_INT_IRQn = 459, /**< Shared Int Source DMA0_CH2_INT from ADMA Sub-System */
354 ADMA_DMA0_CH3_INT_IRQn = 460, /**< Shared Int Source DMA0_CH3_INT from ADMA Sub-System */
355 ADMA_DMA0_CH4_INT_IRQn = 461, /**< Shared Int Source DMA0_CH4_INT from ADMA Sub-System */
356 ADMA_DMA0_CH5_INT_IRQn = 462, /**< Shared Int Source DMA0_CH5_INT from ADMA Sub-System */
357 ADMA_ASRC1_INT1_IRQn = 463, /**< Shared Int Source ASRC1_INT1 from ADMA Sub-System */
358 ADMA_ASRC1_INT2_IRQn = 464, /**< Shared Int Source ASRC1_INT2 from ADMA Sub-System */
359 ADMA_DMA1_CH0_INT_IRQn = 465, /**< Shared Int Source DMA1_CH0_INT from ADMA Sub-System */
360 ADMA_DMA1_CH1_INT_IRQn = 466, /**< Shared Int Source DMA1_CH1_INT from ADMA Sub-System */
361 ADMA_DMA1_CH2_INT_IRQn = 467, /**< Shared Int Source DMA1_CH2_INT from ADMA Sub-System */
362 ADMA_DMA1_CH3_INT_IRQn = 468, /**< Shared Int Source DMA1_CH3_INT from ADMA Sub-System */
363 ADMA_DMA1_CH4_INT_IRQn = 469, /**< Shared Int Source DMA1_CH4_INT from ADMA Sub-System */
364 ADMA_DMA1_CH5_INT_IRQn = 470, /**< Shared Int Source DMA1_CH5_INT from ADMA Sub-System */
365 ADMA_ESAI0_INT_IRQn = 471, /**< Shared Int Source ESAI0_INT from ADMA Sub-System */
366 ADMA_GPT0_INT_IRQn = 474, /**< Shared Int Source GPT0_INT from ADMA Sub-System */
367 ADMA_GPT1_INT_IRQn = 475, /**< Shared Int Source GPT1_INT from ADMA Sub-System */
368 ADMA_GPT2_INT_IRQn = 476, /**< Shared Int Source GPT2_INT from ADMA Sub-System */
369 ADMA_GPT3_INT_IRQn = 477, /**< Shared Int Source GPT3_INT from ADMA Sub-System */
370 ADMA_GPT4_INT_IRQn = 478, /**< Shared Int Source GPT4_INT from ADMA Sub-System */
371 ADMA_GPT5_INT_IRQn = 479, /**< Shared Int Source GPT5_INT from ADMA Sub-System */
372 ADMA_SAI0_INT_IRQn = 480, /**< Shared Int Source SAI0_INT from ADMA Sub-System */
373 ADMA_SAI1_INT_IRQn = 481, /**< Shared Int Source SAI1_INT from ADMA Sub-System */
374 ADMA_SAI2_INT_IRQn = 482, /**< Shared Int Source SAI2_INT from ADMA Sub-System */
375 ADMA_SAI3_INT_IRQn = 483, /**< Shared Int Source SAI3_INT from ADMA Sub-System */
376 ADMA_SAI4_INT_IRQn = 486, /**< Shared Int Source SAI4_INT from ADMA Sub-System */
377 ADMA_SAI5_INT_IRQn = 487, /**< Shared Int Source SAI5_INT from ADMA Sub-System */
378 ADMA_SPDIF0_RX_INT_IRQn = 488, /**< Shared Int Source SPDIF0_RX_INT from ADMA Sub-System */
379 ADMA_SPDIF0_TX_INT_IRQn = 489, /**< Shared Int Source SPDIF0_TX_INT from ADMA Sub-System */
380 ADMA_ESAI0_MOD_INT_IRQn = 492, /**< Shared Int Source ESAI0_MOD_INT from ADMA Sub-System */
381 ADMA_ESAI0_DMA_INT_IRQn = 493, /**< Shared Int Source ESAI0_DMA_INT from ADMA Sub-System */
382 ADMA_SPI0_DMA_RX_INT_IRQn = 499, /**< Shared Int Source SPI0_DMA_RX_INT from ADMA Sub-System */
383 ADMA_SPI0_DMA_TX_INT_IRQn = 500, /**< Shared Int Source SPI0_DMA_TX_INT from ADMA Sub-System */
384 ADMA_SPI1_DMA_RX_INT_IRQn = 501, /**< Shared Int Source SPI1_DMA_RX_INT from ADMA Sub-System */
385 ADMA_SPI1_DMA_TX_INT_IRQn = 502, /**< Shared Int Source SPI1_DMA_TX_INT from ADMA Sub-System */
386 ADMA_SPI2_DMA_RX_INT_IRQn = 503, /**< Shared Int Source SPI2_DMA_RX_INT from ADMA Sub-System */
387 ADMA_SPI2_DMA_TX_INT_IRQn = 504, /**< Shared Int Source SPI2_DMA_TX_INT from ADMA Sub-System */
388 ADMA_SPI3_DMA_RX_INT_IRQn = 505, /**< Shared Int Source SPI3_DMA_RX_INT from ADMA Sub-System */
389 ADMA_SPI3_DMA_TX_INT_IRQn = 506, /**< Shared Int Source SPI3_DMA_TX_INT from ADMA Sub-System */
390 ADMA_I2C0_DMA_RX_INT_IRQn = 507, /**< Shared Int Source I2C0_DMA_RX_INT from ADMA Sub-System */
391 ADMA_I2C0_DMA_TX_INT_IRQn = 508, /**< Shared Int Source I2C0_DMA_TX_INT from ADMA Sub-System */
392 ADMA_I2C1_DMA_RX_INT_IRQn = 509, /**< Shared Int Source I2C1_DMA_RX_INT from ADMA Sub-System */
393 ADMA_I2C1_DMA_TX_INT_IRQn = 510, /**< Shared Int Source I2C1_DMA_TX_INT from ADMA Sub-System */
394 ADMA_I2C2_DMA_RX_INT_IRQn = 511, /**< Shared Int Source I2C2_DMA_RX_INT from ADMA Sub-System */
395 ADMA_I2C2_DMA_TX_INT_IRQn = 512, /**< Shared Int Source I2C2_DMA_TX_INT from ADMA Sub-System */
396 ADMA_I2C3_DMA_RX_INT_IRQn = 513, /**< Shared Int Source I2C3_DMA_RX_INT from ADMA Sub-System */
397 ADMA_I2C3_DMA_TX_INT_IRQn = 514, /**< Shared Int Source I2C3_DMA_TX_INT from ADMA Sub-System */
398 ADMA_UART0_DMA_RX_INT_IRQn = 517, /**< Shared Int Source UART0_DMA_RX_INT from ADMA Sub-System */
399 ADMA_UART0_DMA_TX_INT_IRQn = 518, /**< Shared Int Source UART0_DMA_TX_INT from ADMA Sub-System */
400 ADMA_UART1_DMA_RX_INT_IRQn = 519, /**< Shared Int Source UART1_DMA_RX_INT from ADMA Sub-System */
401 ADMA_UART1_DMA_TX_INT_IRQn = 520, /**< Shared Int Source UART1_DMA_TX_INT from ADMA Sub-System */
402 ADMA_UART2_DMA_RX_INT_IRQn = 521, /**< Shared Int Source UART2_DMA_RX_INT from ADMA Sub-System */
403 ADMA_UART2_DMA_TX_INT_IRQn = 522, /**< Shared Int Source UART2_DMA_TX_INT from ADMA Sub-System */
404 ADMA_UART3_DMA_RX_INT_IRQn = 523, /**< Shared Int Source UART3_DMA_RX_INT from ADMA Sub-System */
405 ADMA_UART3_DMA_TX_INT_IRQn = 524, /**< Shared Int Source UART3_DMA_TX_INT from ADMA Sub-System */
406 SECURITY_MU1_A_INT_IRQn = 531, /**< Shared Int Source MU1_A_INT from Security Sub-System */
407 SECURITY_MU2_A_INT_IRQn = 532, /**< Shared Int Source MU2_A_INT from Security Sub-System */
408 SECURITY_MU3_A_INT_IRQn = 533, /**< Shared Int Source MU3_A_INT from Security Sub-System */
409 SECURITY_CAAM_INT0_IRQn = 534, /**< Shared Int Source CAAM_INT0 from Security Sub-System */
410 SECURITY_CAAM_INT1_IRQn = 535, /**< Shared Int Source CAAM_INT1 from Security Sub-System */
411 SECURITY_CAAM_INT2_IRQn = 536, /**< Shared Int Source CAAM_INT2 from Security Sub-System */
412 SECURITY_CAAM_INT3_IRQn = 537, /**< Shared Int Source CAAM_INT3 from Security Sub-System */
413 SECURITY_CAAM_RTIC_INT_IRQn = 538, /**< Shared Int Source CAAM_RTIC_INT from Security Sub-System */
414 ADMA_SPDIF0_RX_MOD_INT_IRQn = 539, /**< Shared Int Source SPDIF0_RX_MOD_INT from ADMA Sub-System */
415 ADMA_SPDIF0_RX_DMA_INT_IRQn = 540, /**< Shared Int Source SPDIF0_RX_DMA_INT from ADMA Sub-System */
416 ADMA_SPDIF0_TX_MOD_INT_IRQn = 541, /**< Shared Int Source SPDIF0_TX_MOD_INT from ADMA Sub-System */
417 ADMA_SPDIF0_TX_DMA_INT_IRQn = 542, /**< Shared Int Source SPDIF0_TX_DMA_INT from ADMA Sub-System */
418 VPU_VPU_INT_0_IRQn = 547, /**< Shared Int Source VPU_INT_0 from VPU Sub-System */
419 VPU_VPU_INT_1_IRQn = 548, /**< Shared Int Source VPU_INT_1 from VPU Sub-System */
420 VPU_VPU_INT_2_IRQn = 549, /**< Shared Int Source VPU_INT_2 from VPU Sub-System */
421 VPU_VPU_INT_3_IRQn = 550, /**< Shared Int Source VPU_INT_3 from VPU Sub-System */
422 VPU_VPU_INT_4_IRQn = 551, /**< Shared Int Source VPU_INT_4 from VPU Sub-System */
423 M4_INTMUX_SOURCE_TPM_IRQn = 564, /**< INTMUX Input source: TPM Interrupt */
424 M4_INTMUX_SOURCE_LPIT_IRQn = 567, /**< INTMUX Input source: LPIT Interrupt */
425 M4_INTMUX_SOURCE_LPUART_IRQn = 570, /**< INTMUX Input source: LPUART Interrupt */
426 M4_INTMUX_SOURCE_LPI2C_IRQn = 572, /**< INTMUX Input source: LPI2C Interrupt */
427 M4_INTMUX_SOURCE_MU0_A3_IRQn = 591, /**< INTMUX Input source: MU0_A3 Interrupt */
428 M4_INTMUX_SOURCE_MU0_A2_IRQn = 592, /**< INTMUX Input source: MU0_A2 Interrupt */
429 M4_INTMUX_SOURCE_MU0_A1_IRQn = 593, /**< INTMUX Input source: MU0_A1 Interrupt */
430 M4_INTMUX_SOURCE_MU0_A0_IRQn = 594 /**< INTMUX Input source: MU0_A0 Interrupt */
431} IRQn_Type;
432
433/*!
434 * @}
435 */ /* end of group Interrupt_vector_numbers */
436
437
438/* ----------------------------------------------------------------------------
439 -- Configuration of the Cortex-M4 Processor and Core Peripherals
440 ---------------------------------------------------------------------------- */
441
442/*!
443 * @addtogroup Cortex_Core_Configuration Configuration of the Cortex-M4 Processor and Core Peripherals
444 * @{
445 */
446
447#define __CM4_REV 0x0001 /**< Core revision r0p1 */
448#define __MPU_PRESENT 1 /**< MPU present or not */
449#define __NVIC_PRIO_BITS 4 /**< Number of Bits used for Priority Levels */
450#define __Vendor_SysTickConfig 0 /**< Set to 1 if different SysTick Config is used */
451#define __FPU_PRESENT 1 /**< FPU present or not */
452
453#include "core_cm4.h" /* Core Peripheral Access Layer */
454#include "system_MIMX8UX6_cm4.h" /* Device specific configuration file */
455
456/*!
457 * @}
458 */ /* end of group Cortex_Core_Configuration */
459
460
461/* ----------------------------------------------------------------------------
462 -- Device Peripheral Access Layer
463 ---------------------------------------------------------------------------- */
464
465/*!
466 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
467 * @{
468 */
469
470
471/*
472** Start of section using anonymous unions
473*/
474
475#if defined(__ARMCC_VERSION)
476 #if (__ARMCC_VERSION >= 6010050)
477 #pragma clang diagnostic push
478 #else
479 #pragma push
480 #pragma anon_unions
481 #endif
482#elif defined(__GNUC__)
483 /* anonymous unions are enabled by default */
484#elif defined(__IAR_SYSTEMS_ICC__)
485 #pragma language=extended
486#else
487 #error Not supported compiler type
488#endif
489
490/* ----------------------------------------------------------------------------
491 -- ACM Peripheral Access Layer
492 ---------------------------------------------------------------------------- */
493
494/*!
495 * @addtogroup ACM_Peripheral_Access_Layer ACM Peripheral Access Layer
496 * @{
497 */
498
499/** ACM - Register Layout Typedef */
500typedef struct {
501 uint8_t RESERVED_0[14680064];
502 __IO uint32_t AUD_CLK0; /**< ACM_AUD_CLK0 Register, offset: 0xE00000 */
503 uint8_t RESERVED_1[65532];
504 __IO uint32_t AUD_CLK1; /**< ACM_AUD_CLK1 Register, offset: 0xE10000 */
505 uint8_t RESERVED_2[65532];
506 __IO uint32_t MCLKOUT0; /**< ACM_MCLKOUT0 Register, offset: 0xE20000 */
507 uint8_t RESERVED_3[65532];
508 __IO uint32_t MCLKOUT1; /**< ACM_MCLKOUT1 Register, offset: 0xE30000 */
509 uint8_t RESERVED_4[196604];
510 __IO uint32_t ESAI0_CLK; /**< ACM_ESAI0_CLK Register, offset: 0xE60000 */
511 uint8_t RESERVED_5[131068];
512 struct { /* offset: 0xE80000, array step: 0x10000 */
513 __IO uint32_t GPT_CLK; /**< ACM_GPT_CLK Register, array offset: 0xE80000, array step: 0x10000 */
514 uint8_t RESERVED_0[65532];
515 } GPT_CLK[6];
516 struct { /* offset: 0xEE0000, array step: 0x10000 */
517 __IO uint32_t SAI_MCLK; /**< ACM_SAI_MCLK Register, array offset: 0xEE0000, array step: 0x10000 */
518 uint8_t RESERVED_0[65532];
519 } SAI_MCLK[8];
520 uint8_t RESERVED_6[262144];
521 __IO uint32_t SPDIF0_TX_CLK; /**< ACM_SPDIF0_TX_CLK Register, offset: 0xFA0000 */
522 uint8_t RESERVED_7[131068];
523 __IO uint32_t MQS_HMCLK_CLK; /**< ACM_MQS_HMCLK_CLK Register, offset: 0xFC0000 */
524} ACM_Type;
525
526/* ----------------------------------------------------------------------------
527 -- ACM Register Masks
528 ---------------------------------------------------------------------------- */
529
530/*!
531 * @addtogroup ACM_Register_Masks ACM Register Masks
532 * @{
533 */
534
535/*! @name AUD_CLK0 - ACM_AUD_CLK0 Register */
536/*! @{ */
537#define ACM_AUD_CLK0_SEL_MASK (0x1FU)
538#define ACM_AUD_CLK0_SEL_SHIFT (0U)
539/*! SEL - Select
540 * 0b00000..ADMA_SLSLICE2
541 * 0b00001..ADMA_SLSLICE3
542 * 0b00010..EXT_AUD_MCLK0
543 * 0b00011..EXT_AUD_MCLK1
544 * 0b00100..ESAI0_RX_CLK
545 * 0b00101..ESAI0_RX_HF_CLKK
546 * 0b00110..ESAI0_TX_CLK
547 * 0b00111..ESAI0_TX_HF_CLK
548 * 0b01000..SPDIF0_RX
549 * 0b01001..SAI0_RX_BCLK
550 * 0b01010..SAI0_TX_BCLK
551 * 0b01011..SAI1_RX_BCLK
552 * 0b01100..SAI1_TX_BCLK
553 * 0b01101..SAI2_RX_BCLK
554 * 0b01110..SAI3_RX_BCLK
555 */
556#define ACM_AUD_CLK0_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK0_SEL_SHIFT)) & ACM_AUD_CLK0_SEL_MASK)
557/*! @} */
558
559/*! @name AUD_CLK1 - ACM_AUD_CLK1 Register */
560/*! @{ */
561#define ACM_AUD_CLK1_SEL_MASK (0x1FU)
562#define ACM_AUD_CLK1_SEL_SHIFT (0U)
563/*! SEL - Select
564 * 0b00000..ADMA_SLSLICE2
565 * 0b00001..ADMA_SLSLICE3
566 * 0b00010..EXT_AUD_MCLK0
567 * 0b00011..EXT_AUD_MCLK1
568 * 0b00100..ESAI0_RX_CLK
569 * 0b00101..ESAI0_RX_HF_CLKK
570 * 0b00110..ESAI0_TX_CLK
571 * 0b00111..ESAI0_TX_HF_CLK
572 * 0b01000..SPDIF0_RX
573 * 0b01001..SAI0_RX_BCLK
574 * 0b01010..SAI0_TX_BCLK
575 * 0b01011..SAI1_RX_BCLK
576 * 0b01100..SAI1_TX_BCLK
577 * 0b01101..SAI2_RX_BCLK
578 * 0b01110..SAI3_RX_BCLK
579 */
580#define ACM_AUD_CLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_AUD_CLK1_SEL_SHIFT)) & ACM_AUD_CLK1_SEL_MASK)
581/*! @} */
582
583/*! @name MCLKOUT0 - ACM_MCLKOUT0 Register */
584/*! @{ */
585#define ACM_MCLKOUT0_SEL_MASK (0x7U)
586#define ACM_MCLKOUT0_SEL_SHIFT (0U)
587/*! SEL - Select
588 * 0b000..ADMA_SLSLICE2
589 * 0b001..ADMA_SLSLICE3
590 * 0b010..Reserved
591 * 0b011..Reserved
592 * 0b100..SPDIF0_RX
593 * 0b101..Reserved
594 * 0b110..Reserved
595 * 0b111..SAI4_RX_BCLK
596 */
597#define ACM_MCLKOUT0_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT0_SEL_SHIFT)) & ACM_MCLKOUT0_SEL_MASK)
598/*! @} */
599
600/*! @name MCLKOUT1 - ACM_MCLKOUT1 Register */
601/*! @{ */
602#define ACM_MCLKOUT1_SEL_MASK (0x7U)
603#define ACM_MCLKOUT1_SEL_SHIFT (0U)
604/*! SEL - Select
605 * 0b000..ADMA_SLSLICE2
606 * 0b001..ADMA_SLSLICE3
607 * 0b010..Reserved
608 * 0b011..Reserved
609 * 0b100..SPDIF0_RX
610 * 0b101..Reserved
611 * 0b110..Reserved
612 * 0b111..SAI4_RX_BCLK
613 */
614#define ACM_MCLKOUT1_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MCLKOUT1_SEL_SHIFT)) & ACM_MCLKOUT1_SEL_MASK)
615/*! @} */
616
617/*! @name ESAI0_CLK - ACM_ESAI0_CLK Register */
618/*! @{ */
619#define ACM_ESAI0_CLK_SEL_MASK (0x3U)
620#define ACM_ESAI0_CLK_SEL_SHIFT (0U)
621/*! SEL - Select
622 * 0b00..AUD_PLL_DIV_CLK0
623 * 0b01..AUD_PLL_DIV_CLK1
624 * 0b10..AUD_CLK0
625 * 0b11..AUD_CLK1
626 */
627#define ACM_ESAI0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_ESAI0_CLK_SEL_SHIFT)) & ACM_ESAI0_CLK_SEL_MASK)
628/*! @} */
629
630/*! @name GPT_CLK - ACM_GPT_CLK Register */
631/*! @{ */
632#define ACM_GPT_CLK_SEL_MASK (0x7U)
633#define ACM_GPT_CLK_SEL_SHIFT (0U)
634/*! SEL - Select
635 * 0b000..AUD_PLL_DIV_CLK0
636 * 0b001..AUD_PLL_DIV_CLK1
637 * 0b010..AUD_CLK0
638 * 0b011..AUD_CLK1
639 * 0b100..24M_REF_CLK
640 */
641#define ACM_GPT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_GPT_CLK_SEL_SHIFT)) & ACM_GPT_CLK_SEL_MASK)
642/*! @} */
643
644/* The count of ACM_GPT_CLK */
645#define ACM_GPT_CLK_COUNT (6U)
646
647/*! @name SAI_MCLK - ACM_SAI_MCLK Register */
648/*! @{ */
649#define ACM_SAI_MCLK_SEL_MASK (0x3U)
650#define ACM_SAI_MCLK_SEL_SHIFT (0U)
651/*! SEL - Select
652 * 0b00..AUD_PLL_DIV_CLK0
653 * 0b01..AUD_PLL_DIV_CLK1
654 * 0b10..AUD_CLK0
655 * 0b11..AUD_CLK1
656 */
657#define ACM_SAI_MCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SAI_MCLK_SEL_SHIFT)) & ACM_SAI_MCLK_SEL_MASK)
658/*! @} */
659
660/* The count of ACM_SAI_MCLK */
661#define ACM_SAI_MCLK_COUNT (8U)
662
663/*! @name SPDIF0_TX_CLK - ACM_SPDIF0_TX_CLK Register */
664/*! @{ */
665#define ACM_SPDIF0_TX_CLK_SEL_MASK (0x3U)
666#define ACM_SPDIF0_TX_CLK_SEL_SHIFT (0U)
667/*! SEL - Select
668 * 0b00..AUD_PLL_DIV_CLK0
669 * 0b01..AUD_PLL_DIV_CLK1
670 * 0b10..AUD_CLK0
671 * 0b11..AUD_CLK1
672 */
673#define ACM_SPDIF0_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_SPDIF0_TX_CLK_SEL_SHIFT)) & ACM_SPDIF0_TX_CLK_SEL_MASK)
674/*! @} */
675
676/*! @name MQS_HMCLK_CLK - ACM_MQS_HMCLK_CLK Register */
677/*! @{ */
678#define ACM_MQS_HMCLK_CLK_SEL_MASK (0x3U)
679#define ACM_MQS_HMCLK_CLK_SEL_SHIFT (0U)
680/*! SEL - Select
681 * 0b00..AUD_PLL_DIV_CLK0
682 * 0b01..AUD_PLL_DIV_CLK1
683 * 0b10..AUD_CLK0
684 * 0b11..AUD_CLK1
685 */
686#define ACM_MQS_HMCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << ACM_MQS_HMCLK_CLK_SEL_SHIFT)) & ACM_MQS_HMCLK_CLK_SEL_MASK)
687/*! @} */
688
689
690/*!
691 * @}
692 */ /* end of group ACM_Register_Masks */
693
694
695/* ACM - Peripheral instance base addresses */
696/** Peripheral ADMA__ACM base address */
697#define ADMA__ACM_BASE (0x59000000u)
698/** Peripheral ADMA__ACM base pointer */
699#define ADMA__ACM ((ACM_Type *)ADMA__ACM_BASE)
700/** Array initializer of ACM peripheral base addresses */
701#define ACM_BASE_ADDRS { ADMA__ACM_BASE }
702/** Array initializer of ACM peripheral base pointers */
703#define ACM_BASE_PTRS { ADMA__ACM }
704
705/*!
706 * @}
707 */ /* end of group ACM_Peripheral_Access_Layer */
708
709
710/* ----------------------------------------------------------------------------
711 -- ADC Peripheral Access Layer
712 ---------------------------------------------------------------------------- */
713
714/*!
715 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
716 * @{
717 */
718
719/** ADC - Register Layout Typedef */
720typedef struct {
721 __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
722 __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
723 uint8_t RESERVED_0[8];
724 __IO uint32_t CTRL; /**< ADC Control Register, offset: 0x10 */
725 __IO uint32_t STAT; /**< ADC Status Register, offset: 0x14 */
726 __IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
727 __IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
728 __IO uint32_t CFG; /**< ADC Configuration Register, offset: 0x20 */
729 __IO uint32_t PAUSE; /**< ADC Pause Register, offset: 0x24 */
730 uint8_t RESERVED_1[8];
731 __IO uint32_t FCTRL; /**< ADC FIFO Control Register, offset: 0x30 */
732 __O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
733 uint8_t RESERVED_2[136];
734 __IO uint32_t TCTRL[8]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
735 uint8_t RESERVED_3[32];
736 struct { /* offset: 0x100, array step: 0x8 */
737 __IO uint32_t CMDL; /**< ADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
738 __IO uint32_t CMDH; /**< ADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
739 } CMD[15];
740 uint8_t RESERVED_4[136];
741 __IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
742 uint8_t RESERVED_5[240];
743 __I uint32_t RESFIFO; /**< ADC Data Result FIFO Register, offset: 0x300 */
744} ADC_Type;
745
746/* ----------------------------------------------------------------------------
747 -- ADC Register Masks
748 ---------------------------------------------------------------------------- */
749
750/*!
751 * @addtogroup ADC_Register_Masks ADC Register Masks
752 * @{
753 */
754
755/*! @name VERID - Version ID Register */
756/*! @{ */
757#define ADC_VERID_RES_MASK (0x1U)
758#define ADC_VERID_RES_SHIFT (0U)
759/*! RES - Resolution
760 * 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
761 * 0b1..Up to 16-bit differential/15-bit single ended resolution supported.
762 */
763#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
764#define ADC_VERID_DIFFEN_MASK (0x2U)
765#define ADC_VERID_DIFFEN_SHIFT (1U)
766/*! DIFFEN - Differential Supported
767 * 0b0..Differential operation not supported.
768 * 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
769 */
770#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
771#define ADC_VERID_MVI_MASK (0x8U)
772#define ADC_VERID_MVI_SHIFT (3U)
773/*! MVI - Multi Vref Implemented
774 * 0b0..Single voltage reference high (VREFH) input supported.
775 * 0b1..Multiple voltage reference high (VREFH) inputs supported.
776 */
777#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
778#define ADC_VERID_CSW_MASK (0x70U)
779#define ADC_VERID_CSW_SHIFT (4U)
780/*! CSW - Channel Scale Width
781 * 0b000..Channel scaling not supported.
782 * 0b001..Channel scaling supported. 1-bit CSCALE control field.
783 * 0b110..Channel scaling supported. 6-bit CSCALE control field.
784 */
785#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
786#define ADC_VERID_VR1RNGI_MASK (0x100U)
787#define ADC_VERID_VR1RNGI_SHIFT (8U)
788/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
789 * 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
790 * 0b1..Range control required. CFG[VREF1RNG] is implemented.
791 */
792#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
793#define ADC_VERID_IADCKI_MASK (0x200U)
794#define ADC_VERID_IADCKI_SHIFT (9U)
795/*! IADCKI - Internal ADC Clock implemented
796 * 0b0..Internal clock source not implemented.
797 * 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
798 */
799#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
800#define ADC_VERID_CALOFSI_MASK (0x400U)
801#define ADC_VERID_CALOFSI_SHIFT (10U)
802/*! CALOFSI - Calibration Offset Function Implemented
803 * 0b0..Offset calibration and offset trimming not implemented.
804 * 0b1..Offset calibration and offset trimming implemented.
805 */
806#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
807#define ADC_VERID_MINOR_MASK (0xFF0000U)
808#define ADC_VERID_MINOR_SHIFT (16U)
809/*! MINOR - Minor Version Number
810 */
811#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
812#define ADC_VERID_MAJOR_MASK (0xFF000000U)
813#define ADC_VERID_MAJOR_SHIFT (24U)
814/*! MAJOR - Major Version Number
815 */
816#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
817/*! @} */
818
819/*! @name PARAM - Parameter Register */
820/*! @{ */
821#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
822#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
823/*! TRIG_NUM - Trigger Number
824 */
825#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
826#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
827#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
828/*! FIFOSIZE - Result FIFO Depth
829 * 0b00000001..Result FIFO depth = 1 dataword.
830 * 0b00000100..Result FIFO depth = 4 datawords.
831 * 0b00001000..Result FIFO depth = 8 datawords.
832 * 0b00010000..Result FIFO depth = 16 datawords.
833 * 0b00100000..Result FIFO depth = 32 datawords.
834 * 0b01000000..Result FIFO depth = 64 datawords.
835 */
836#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
837#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
838#define ADC_PARAM_CV_NUM_SHIFT (16U)
839/*! CV_NUM - Compare Value Number
840 */
841#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
842#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
843#define ADC_PARAM_CMD_NUM_SHIFT (24U)
844/*! CMD_NUM - Command Buffer Number
845 */
846#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
847/*! @} */
848
849/*! @name CTRL - ADC Control Register */
850/*! @{ */
851#define ADC_CTRL_ADCEN_MASK (0x1U)
852#define ADC_CTRL_ADCEN_SHIFT (0U)
853/*! ADCEN - ADC Enable
854 * 0b0..ADC is disabled.
855 * 0b1..ADC is enabled.
856 */
857#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
858#define ADC_CTRL_RST_MASK (0x2U)
859#define ADC_CTRL_RST_SHIFT (1U)
860/*! RST - Software Reset
861 * 0b0..ADC logic is not reset.
862 * 0b1..ADC logic is reset.
863 */
864#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
865#define ADC_CTRL_DOZEN_MASK (0x4U)
866#define ADC_CTRL_DOZEN_SHIFT (2U)
867/*! DOZEN - Doze Enable
868 * 0b0..ADC is enabled in Doze mode.
869 * 0b1..ADC is disabled in Doze mode.
870 */
871#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
872#define ADC_CTRL_RSTFIFO_MASK (0x100U)
873#define ADC_CTRL_RSTFIFO_SHIFT (8U)
874/*! RSTFIFO - Reset FIFO
875 * 0b0..No effect.
876 * 0b1..FIFO is reset.
877 */
878#define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
879/*! @} */
880
881/*! @name STAT - ADC Status Register */
882/*! @{ */
883#define ADC_STAT_RDY_MASK (0x1U)
884#define ADC_STAT_RDY_SHIFT (0U)
885/*! RDY - Result FIFO Ready Flag
886 * 0b0..Result FIFO data level not above watermark level.
887 * 0b1..Result FIFO holding data above watermark level.
888 */
889#define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
890#define ADC_STAT_FOF_MASK (0x2U)
891#define ADC_STAT_FOF_SHIFT (1U)
892/*! FOF - Result FIFO Overflow Flag
893 * 0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
894 * 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
895 */
896#define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
897#define ADC_STAT_ADC_ACTIVE_MASK (0x100U)
898#define ADC_STAT_ADC_ACTIVE_SHIFT (8U)
899/*! ADC_ACTIVE - ADC Active
900 * 0b0..The ADC is IDLE. There are no pending triggers to service and no active commands are being processed.
901 * 0b1..The ADC is processing a conversion, running through the power up delay, or servicing a trigger.
902 */
903#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
904#define ADC_STAT_TRGACT_MASK (0x70000U)
905#define ADC_STAT_TRGACT_SHIFT (16U)
906/*! TRGACT - Trigger Active
907 * 0b000..Command (sequence) associated with Trigger 0 currently being executed.
908 * 0b001..Command (sequence) associated with Trigger 1 currently being executed.
909 * 0b010..Command (sequence) associated with Trigger 2 currently being executed.
910 * 0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.
911 */
912#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
913#define ADC_STAT_CMDACT_MASK (0xF000000U)
914#define ADC_STAT_CMDACT_SHIFT (24U)
915/*! CMDACT - Command Active
916 * 0b0000..No command is currently in progress.
917 * 0b0001..Command 1 currently being executed.
918 * 0b0010..Command 2 currently being executed.
919 * 0b0011-0b1111..Associated command number is currently being executed.
920 */
921#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
922/*! @} */
923
924/*! @name IE - Interrupt Enable Register */
925/*! @{ */
926#define ADC_IE_FWMIE_MASK (0x1U)
927#define ADC_IE_FWMIE_SHIFT (0U)
928/*! FWMIE - FIFO Watermark Interrupt Enable
929 * 0b0..FIFO watermark interrupts are not enabled.
930 * 0b1..FIFO watermark interrupts are enabled.
931 */
932#define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
933#define ADC_IE_FOFIE_MASK (0x2U)
934#define ADC_IE_FOFIE_SHIFT (1U)
935/*! FOFIE - Result FIFO Overflow Interrupt Enable
936 * 0b0..FIFO overflow interrupts are not enabled.
937 * 0b1..FIFO overflow interrupts are enabled.
938 */
939#define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
940/*! @} */
941
942/*! @name DE - DMA Enable Register */
943/*! @{ */
944#define ADC_DE_FWMDE_MASK (0x1U)
945#define ADC_DE_FWMDE_SHIFT (0U)
946/*! FWMDE - FIFO Watermark DMA Enable
947 * 0b0..DMA request disabled.
948 * 0b1..DMA request enabled.
949 */
950#define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
951/*! @} */
952
953/*! @name CFG - ADC Configuration Register */
954/*! @{ */
955#define ADC_CFG_TPRICTRL_MASK (0x1U)
956#define ADC_CFG_TPRICTRL_SHIFT (0U)
957/*! TPRICTRL - ADC trigger priority control
958 * 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and
959 * the new command specified by the trigger is started.
960 * 0b1..If a higher priority trigger is received during command processing, the current conversion is completed
961 * (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority
962 * trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true
963 * conversion.
964 */
965#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
966#define ADC_CFG_PWRSEL_MASK (0x30U)
967#define ADC_CFG_PWRSEL_SHIFT (4U)
968/*! PWRSEL - Power Configuration Select
969 * 0b00..Level 1 (Lowest power setting)
970 * 0b01..Level 2
971 * 0b10..Level 3
972 * 0b11..Level 4 (Highest power setting)
973 */
974#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
975#define ADC_CFG_REFSEL_MASK (0xC0U)
976#define ADC_CFG_REFSEL_SHIFT (6U)
977/*! REFSEL - Voltage Reference Selection
978 * 0b00..(Default) Option 1 setting.
979 * 0b01..Option 2 setting.
980 * 0b10..Option 3 setting.
981 * 0b11..Reserved
982 */
983#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
984#define ADC_CFG_PUDLY_MASK (0xFF0000U)
985#define ADC_CFG_PUDLY_SHIFT (16U)
986/*! PUDLY - Power Up Delay
987 */
988#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
989#define ADC_CFG_PWREN_MASK (0x10000000U)
990#define ADC_CFG_PWREN_SHIFT (28U)
991/*! PWREN - ADC Analog Pre-Enable
992 * 0b0..ADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
993 * 0b1..ADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the cost
994 * of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any
995 * detected trigger does not begin ADC operation until the power up delay time has passed.
996 */
997#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
998/*! @} */
999
1000/*! @name PAUSE - ADC Pause Register */
1001/*! @{ */
1002#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
1003#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
1004/*! PAUSEDLY - Pause Delay
1005 */
1006#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
1007#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
1008#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
1009/*! PAUSEEN - PAUSE Option Enable
1010 * 0b0..Pause operation disabled
1011 * 0b1..Pause operation enabled
1012 */
1013#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
1014/*! @} */
1015
1016/*! @name FCTRL - ADC FIFO Control Register */
1017/*! @{ */
1018#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
1019#define ADC_FCTRL_FCOUNT_SHIFT (0U)
1020/*! FCOUNT - Result FIFO counter
1021 */
1022#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
1023#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
1024#define ADC_FCTRL_FWMARK_SHIFT (16U)
1025/*! FWMARK - Watermark level selection
1026 */
1027#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
1028/*! @} */
1029
1030/*! @name SWTRIG - Software Trigger Register */
1031/*! @{ */
1032#define ADC_SWTRIG_SWT0_MASK (0x1U)
1033#define ADC_SWTRIG_SWT0_SHIFT (0U)
1034/*! SWT0 - Software trigger 0 event
1035 * 0b0..No trigger 0 event generated.
1036 * 0b1..Trigger 0 event generated.
1037 */
1038#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
1039#define ADC_SWTRIG_SWT1_MASK (0x2U)
1040#define ADC_SWTRIG_SWT1_SHIFT (1U)
1041/*! SWT1 - Software trigger 1 event
1042 * 0b0..No trigger 1 event generated.
1043 * 0b1..Trigger 1 event generated.
1044 */
1045#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
1046#define ADC_SWTRIG_SWT2_MASK (0x4U)
1047#define ADC_SWTRIG_SWT2_SHIFT (2U)
1048/*! SWT2 - Software trigger 2 event
1049 * 0b0..No trigger 2 event generated.
1050 * 0b1..Trigger 2 event generated.
1051 */
1052#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
1053#define ADC_SWTRIG_SWT3_MASK (0x8U)
1054#define ADC_SWTRIG_SWT3_SHIFT (3U)
1055/*! SWT3 - Software trigger 3 event
1056 * 0b0..No trigger 3 event generated.
1057 * 0b1..Trigger 3 event generated.
1058 */
1059#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
1060#define ADC_SWTRIG_SWT4_MASK (0x10U)
1061#define ADC_SWTRIG_SWT4_SHIFT (4U)
1062/*! SWT4 - Software trigger 4 event
1063 * 0b0..No trigger 4 event generated.
1064 * 0b1..Trigger 4 event generated.
1065 */
1066#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
1067#define ADC_SWTRIG_SWT5_MASK (0x20U)
1068#define ADC_SWTRIG_SWT5_SHIFT (5U)
1069/*! SWT5 - Software trigger 5 event
1070 * 0b0..No trigger 5 event generated.
1071 * 0b1..Trigger 5 event generated.
1072 */
1073#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
1074#define ADC_SWTRIG_SWT6_MASK (0x40U)
1075#define ADC_SWTRIG_SWT6_SHIFT (6U)
1076/*! SWT6 - Software trigger 6 event
1077 * 0b0..No trigger 6 event generated.
1078 * 0b1..Trigger 6 event generated.
1079 */
1080#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
1081#define ADC_SWTRIG_SWT7_MASK (0x80U)
1082#define ADC_SWTRIG_SWT7_SHIFT (7U)
1083/*! SWT7 - Software trigger 7 event
1084 * 0b0..No trigger 7 event generated.
1085 * 0b1..Trigger 7 event generated.
1086 */
1087#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
1088/*! @} */
1089
1090/*! @name TCTRL - Trigger Control Register */
1091/*! @{ */
1092#define ADC_TCTRL_HTEN_MASK (0x1U)
1093#define ADC_TCTRL_HTEN_SHIFT (0U)
1094/*! HTEN - Trigger enable
1095 * 0b0..Hardware trigger source disabled
1096 * 0b1..Hardware trigger source enabled
1097 */
1098#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
1099#define ADC_TCTRL_TPRI_MASK (0x700U)
1100#define ADC_TCTRL_TPRI_SHIFT (8U)
1101/*! TPRI - Trigger priority setting
1102 * 0b000..Set to highest priority, Level 1
1103 * 0b001-0b110..Set to corresponding priority level
1104 * 0b111..Set to lowest priority, Level 8
1105 */
1106#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
1107#define ADC_TCTRL_TDLY_MASK (0xF0000U)
1108#define ADC_TCTRL_TDLY_SHIFT (16U)
1109/*! TDLY - Trigger delay select
1110 */
1111#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
1112#define ADC_TCTRL_TCMD_MASK (0xF000000U)
1113#define ADC_TCTRL_TCMD_SHIFT (24U)
1114/*! TCMD - Trigger command select
1115 * 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
1116 * 0b0001..CMD1 is executed
1117 * 0b0010-0b1110..Corresponding CMD is executed
1118 * 0b1111..CMD15 is executed
1119 */
1120#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
1121/*! @} */
1122
1123/* The count of ADC_TCTRL */
1124#define ADC_TCTRL_COUNT (8U)
1125
1126/*! @name CMDL - ADC Command Low Buffer Register */
1127/*! @{ */
1128#define ADC_CMDL_ADCH_MASK (0x1FU)
1129#define ADC_CMDL_ADCH_SHIFT (0U)
1130/*! ADCH - Input channel select
1131 * 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
1132 * 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
1133 * 0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
1134 * 0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
1135 * 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
1136 * 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
1137 * 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
1138 */
1139#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
1140#define ADC_CMDL_ABSEL_MASK (0x20U)
1141#define ADC_CMDL_ABSEL_SHIFT (5U)
1142/*! ABSEL - A-side vs. B-side Select
1143 * 0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
1144 * 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
1145 */
1146#define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
1147#define ADC_CMDL_DIFF_MASK (0x40U)
1148#define ADC_CMDL_DIFF_SHIFT (6U)
1149/*! DIFF - Differential Mode Enable
1150 * 0b0..Single-ended mode.
1151 * 0b1..Differential mode.
1152 */
1153#define ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
1154#define ADC_CMDL_CSCALE_MASK (0x2000U)
1155#define ADC_CMDL_CSCALE_SHIFT (13U)
1156/*! CSCALE - Channel Scale
1157 * 0b0..Scale selected analog channel (Factor of 30/64)
1158 * 0b1..(Default) Full scale (Factor of 1)
1159 */
1160#define ADC_CMDL_CSCALE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
1161/*! @} */
1162
1163/* The count of ADC_CMDL */
1164#define ADC_CMDL_COUNT (15U)
1165
1166/*! @name CMDH - ADC Command High Buffer Register */
1167/*! @{ */
1168#define ADC_CMDH_CMPEN_MASK (0x3U)
1169#define ADC_CMDH_CMPEN_SHIFT (0U)
1170/*! CMPEN - Compare Function Enable
1171 * 0b00..Compare disabled.
1172 * 0b01..Reserved
1173 * 0b10..Compare enabled. Store on true.
1174 * 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
1175 */
1176#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
1177#define ADC_CMDH_LWI_MASK (0x80U)
1178#define ADC_CMDH_LWI_SHIFT (7U)
1179/*! LWI - Loop with Increment
1180 * 0b0..Auto channel increment disabled
1181 * 0b1..Auto channel increment enabled
1182 */
1183#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
1184#define ADC_CMDH_STS_MASK (0x700U)
1185#define ADC_CMDH_STS_SHIFT (8U)
1186/*! STS - Sample Time Select
1187 * 0b000..Minimum sample time of 3 ADCK cycles.
1188 * 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
1189 * 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
1190 * 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
1191 * 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
1192 * 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
1193 * 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
1194 * 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
1195 */
1196#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
1197#define ADC_CMDH_AVGS_MASK (0x7000U)
1198#define ADC_CMDH_AVGS_SHIFT (12U)
1199/*! AVGS - Hardware Average Select
1200 * 0b000..Single conversion.
1201 * 0b001..2 conversions averaged.
1202 * 0b010..4 conversions averaged.
1203 * 0b011..8 conversions averaged.
1204 * 0b100..16 conversions averaged.
1205 * 0b101..32 conversions averaged.
1206 * 0b110..64 conversions averaged.
1207 * 0b111..128 conversions averaged.
1208 */
1209#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
1210#define ADC_CMDH_LOOP_MASK (0xF0000U)
1211#define ADC_CMDH_LOOP_SHIFT (16U)
1212/*! LOOP - Loop Count Select
1213 * 0b0000..Looping not enabled. Command executes 1 time.
1214 * 0b0001..Loop 1 time. Command executes 2 times.
1215 * 0b0010..Loop 2 times. Command executes 3 times.
1216 * 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
1217 * 0b1111..Loop 15 times. Command executes 16 times.
1218 */
1219#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
1220#define ADC_CMDH_NEXT_MASK (0xF000000U)
1221#define ADC_CMDH_NEXT_SHIFT (24U)
1222/*! NEXT - Next Command Select
1223 * 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
1224 * trigger pending, begin command associated with lower priority trigger.
1225 * 0b0001..Select CMD1 command buffer register as next command.
1226 * 0b0010-0b1110..Select corresponding CMD command buffer register as next command
1227 * 0b1111..Select CMD15 command buffer register as next command.
1228 */
1229#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
1230/*! @} */
1231
1232/* The count of ADC_CMDH */
1233#define ADC_CMDH_COUNT (15U)
1234
1235/*! @name CV - Compare Value Register */
1236/*! @{ */
1237#define ADC_CV_CVL_MASK (0xFFFFU)
1238#define ADC_CV_CVL_SHIFT (0U)
1239/*! CVL - Compare Value Low.
1240 */
1241#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
1242#define ADC_CV_CVH_MASK (0xFFFF0000U)
1243#define ADC_CV_CVH_SHIFT (16U)
1244/*! CVH - Compare Value High.
1245 */
1246#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
1247/*! @} */
1248
1249/* The count of ADC_CV */
1250#define ADC_CV_COUNT (4U)
1251
1252/*! @name RESFIFO - ADC Data Result FIFO Register */
1253/*! @{ */
1254#define ADC_RESFIFO_D_MASK (0xFFFFU)
1255#define ADC_RESFIFO_D_SHIFT (0U)
1256/*! D - Data result
1257 */
1258#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
1259#define ADC_RESFIFO_TSRC_MASK (0x70000U)
1260#define ADC_RESFIFO_TSRC_SHIFT (16U)
1261/*! TSRC - Trigger Source
1262 * 0b000..Trigger source 0 initiated this conversion.
1263 * 0b001..Trigger source 1 initiated this conversion.
1264 * 0b010-0b110..Corresponding trigger source initiated this conversion.
1265 * 0b111..Trigger source 7 initiated this conversion.
1266 */
1267#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
1268#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
1269#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
1270/*! LOOPCNT - Loop count value
1271 * 0b0000..Result is from initial conversion in command.
1272 * 0b0001..Result is from second conversion in command.
1273 * 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
1274 * 0b1111..Result is from 16th conversion in command.
1275 */
1276#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
1277#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
1278#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
1279/*! CMDSRC - Command Buffer Source
1280 * 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
1281 * prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
1282 * 0b0001..CMD1 buffer used as control settings for this conversion.
1283 * 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
1284 * 0b1111..CMD15 buffer used as control settings for this conversion.
1285 */
1286#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
1287#define ADC_RESFIFO_VALID_MASK (0x80000000U)
1288#define ADC_RESFIFO_VALID_SHIFT (31U)
1289/*! VALID - FIFO entry is valid
1290 * 0b0..FIFO is empty. Discard any read from RESFIFO.
1291 * 0b1..FIFO record read from RESFIFO is valid.
1292 */
1293#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
1294/*! @} */
1295
1296
1297/*!
1298 * @}
1299 */ /* end of group ADC_Register_Masks */
1300
1301
1302/* ADC - Peripheral instance base addresses */
1303/** Peripheral ADMA__ADC0 base address */
1304#define ADMA__ADC0_BASE (0x5A880000u)
1305/** Peripheral ADMA__ADC0 base pointer */
1306#define ADMA__ADC0 ((ADC_Type *)ADMA__ADC0_BASE)
1307/** Array initializer of ADC peripheral base addresses */
1308#define ADC_BASE_ADDRS { ADMA__ADC0_BASE }
1309/** Array initializer of ADC peripheral base pointers */
1310#define ADC_BASE_PTRS { ADMA__ADC0 }
1311/** Interrupt vectors for the ADC peripheral type */
1312#define ADC_IRQS { ADMA_ADC0_INT_IRQn }
1313
1314/*!
1315 * @}
1316 */ /* end of group ADC_Peripheral_Access_Layer */
1317
1318
1319/* ----------------------------------------------------------------------------
1320 -- APBH Peripheral Access Layer
1321 ---------------------------------------------------------------------------- */
1322
1323/*!
1324 * @addtogroup APBH_Peripheral_Access_Layer APBH Peripheral Access Layer
1325 * @{
1326 */
1327
1328/** APBH - Register Layout Typedef */
1329typedef struct {
1330 struct { /* offset: 0x0 */
1331 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x0 */
1332 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x4 */
1333 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0x8 */
1334 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 0, offset: 0xC */
1335 } CTRL0;
1336 struct { /* offset: 0x10 */
1337 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x10 */
1338 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x14 */
1339 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x18 */
1340 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 1, offset: 0x1C */
1341 } CTRL1;
1342 struct { /* offset: 0x20 */
1343 __IO uint32_t RW; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x20 */
1344 __IO uint32_t SET; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x24 */
1345 __IO uint32_t CLR; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x28 */
1346 __IO uint32_t TOG; /**< AHB to APBH Bridge Control and Status Register 2, offset: 0x2C */
1347 } CTRL2;
1348 struct { /* offset: 0x30 */
1349 __IO uint32_t RW; /**< AHB to APBH Bridge Channel Register, offset: 0x30 */
1350 __IO uint32_t SET; /**< AHB to APBH Bridge Channel Register, offset: 0x34 */
1351 __IO uint32_t CLR; /**< AHB to APBH Bridge Channel Register, offset: 0x38 */
1352 __IO uint32_t TOG; /**< AHB to APBH Bridge Channel Register, offset: 0x3C */
1353 } CHANNEL_CTRL;
1354 uint32_t DEVSEL; /**< AHB to APBH DMA Device Assignment Register, offset: 0x40 */
1355 uint8_t RESERVED_0[12];
1356 __IO uint32_t DMA_BURST_SIZE; /**< AHB to APBH DMA burst size, offset: 0x50 */
1357 uint8_t RESERVED_1[12];
1358 __IO uint32_t DEBUGr; /**< AHB to APBH DMA Debug Register, offset: 0x60 */
1359 uint8_t RESERVED_2[156];
1360 struct { /* offset: 0x100, array step: 0x70 */
1361 __I uint32_t CH_CURCMDAR; /**< APBH DMA Channel n Current Command Address Register, array offset: 0x100, array step: 0x70 */
1362 uint8_t RESERVED_0[12];
1363 __IO uint32_t CH_NXTCMDAR; /**< APBH DMA Channel n Next Command Address Register, array offset: 0x110, array step: 0x70 */
1364 uint8_t RESERVED_1[12];
1365 __I uint32_t CH_CMD; /**< APBH DMA Channel n Command Register, array offset: 0x120, array step: 0x70 */
1366 uint8_t RESERVED_2[12];
1367 __I uint32_t CH_BAR; /**< APBH DMA Channel n Buffer Address Register, array offset: 0x130, array step: 0x70 */
1368 uint8_t RESERVED_3[12];
1369 __IO uint32_t CH_SEMA; /**< APBH DMA Channel n Semaphore Register, array offset: 0x140, array step: 0x70 */
1370 uint8_t RESERVED_4[12];
1371 __I uint32_t CH_DEBUG1; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x150, array step: 0x70 */
1372 uint8_t RESERVED_5[12];
1373 __I uint32_t CH_DEBUG2; /**< AHB to APBH DMA Channel n Debug Information, array offset: 0x160, array step: 0x70 */
1374 uint8_t RESERVED_6[12];
1375 } CH_CFGn[16];
1376 __I uint32_t VERSION; /**< APBH Bridge Version Register, offset: 0x800 */
1377} APBH_Type;
1378
1379/* ----------------------------------------------------------------------------
1380 -- APBH Register Masks
1381 ---------------------------------------------------------------------------- */
1382
1383/*!
1384 * @addtogroup APBH_Register_Masks APBH Register Masks
1385 * @{
1386 */
1387
1388/*! @name CTRL0 - AHB to APBH Bridge Control and Status Register 0 */
1389/*! @{ */
1390#define APBH_CTRL0_CLKGATE_CHANNEL_MASK (0xFFFFU)
1391#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT (0U)
1392/*! CLKGATE_CHANNEL - CLKGATE_CHANNEL
1393 * 0b0000000000000001..
1394 * 0b0000000000000010..
1395 * 0b0000000000000100..
1396 * 0b0000000000001000..
1397 * 0b0000000000010000..
1398 * 0b0000000000100000..
1399 * 0b0000000001000000..
1400 * 0b0000000010000000..
1401 * 0b0000000100000000..
1402 */
1403#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_CHANNEL_SHIFT)) & APBH_CTRL0_CLKGATE_CHANNEL_MASK)
1404#define APBH_CTRL0_APB_BURST_EN_MASK (0x10000000U)
1405#define APBH_CTRL0_APB_BURST_EN_SHIFT (28U)
1406/*! APB_BURST_EN - APB_BURST_EN
1407 */
1408#define APBH_CTRL0_APB_BURST_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_APB_BURST_EN_SHIFT)) & APBH_CTRL0_APB_BURST_EN_MASK)
1409#define APBH_CTRL0_AHB_BURST8_EN_MASK (0x20000000U)
1410#define APBH_CTRL0_AHB_BURST8_EN_SHIFT (29U)
1411/*! AHB_BURST8_EN - AHB_BURST8_EN
1412 */
1413#define APBH_CTRL0_AHB_BURST8_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_AHB_BURST8_EN_SHIFT)) & APBH_CTRL0_AHB_BURST8_EN_MASK)
1414#define APBH_CTRL0_CLKGATE_MASK (0x40000000U)
1415#define APBH_CTRL0_CLKGATE_SHIFT (30U)
1416/*! CLKGATE - CLKGATE
1417 */
1418#define APBH_CTRL0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_CLKGATE_SHIFT)) & APBH_CTRL0_CLKGATE_MASK)
1419#define APBH_CTRL0_SFTRST_MASK (0x80000000U)
1420#define APBH_CTRL0_SFTRST_SHIFT (31U)
1421/*! SFTRST - SFTRST
1422 */
1423#define APBH_CTRL0_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL0_SFTRST_SHIFT)) & APBH_CTRL0_SFTRST_MASK)
1424/*! @} */
1425
1426/*! @name CTRL1 - AHB to APBH Bridge Control and Status Register 1 */
1427/*! @{ */
1428#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK (0x1U)
1429#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT (0U)
1430/*! CH0_CMDCMPLT_IRQ - CH0_CMDCMPLT_IRQ
1431 */
1432#define APBH_CTRL1_CH0_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_MASK)
1433#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK (0x2U)
1434#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT (1U)
1435/*! CH1_CMDCMPLT_IRQ - CH1_CMDCMPLT_IRQ
1436 */
1437#define APBH_CTRL1_CH1_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_MASK)
1438#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK (0x4U)
1439#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT (2U)
1440/*! CH2_CMDCMPLT_IRQ - CH2_CMDCMPLT_IRQ
1441 */
1442#define APBH_CTRL1_CH2_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_MASK)
1443#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK (0x8U)
1444#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT (3U)
1445/*! CH3_CMDCMPLT_IRQ - CH3_CMDCMPLT_IRQ
1446 */
1447#define APBH_CTRL1_CH3_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_MASK)
1448#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK (0x10U)
1449#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT (4U)
1450/*! CH4_CMDCMPLT_IRQ - CH4_CMDCMPLT_IRQ
1451 */
1452#define APBH_CTRL1_CH4_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_MASK)
1453#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK (0x20U)
1454#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT (5U)
1455/*! CH5_CMDCMPLT_IRQ - CH5_CMDCMPLT_IRQ
1456 */
1457#define APBH_CTRL1_CH5_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_MASK)
1458#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK (0x40U)
1459#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT (6U)
1460/*! CH6_CMDCMPLT_IRQ - CH6_CMDCMPLT_IRQ
1461 */
1462#define APBH_CTRL1_CH6_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_MASK)
1463#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK (0x80U)
1464#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT (7U)
1465/*! CH7_CMDCMPLT_IRQ - CH7_CMDCMPLT_IRQ
1466 */
1467#define APBH_CTRL1_CH7_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_MASK)
1468#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK (0x100U)
1469#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT (8U)
1470/*! CH8_CMDCMPLT_IRQ - CH8_CMDCMPLT_IRQ
1471 */
1472#define APBH_CTRL1_CH8_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_MASK)
1473#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK (0x200U)
1474#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT (9U)
1475/*! CH9_CMDCMPLT_IRQ - CH9_CMDCMPLT_IRQ
1476 */
1477#define APBH_CTRL1_CH9_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_MASK)
1478#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK (0x400U)
1479#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT (10U)
1480/*! CH10_CMDCMPLT_IRQ - CH10_CMDCMPLT_IRQ
1481 */
1482#define APBH_CTRL1_CH10_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_MASK)
1483#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK (0x800U)
1484#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT (11U)
1485/*! CH11_CMDCMPLT_IRQ - CH11_CMDCMPLT_IRQ
1486 */
1487#define APBH_CTRL1_CH11_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_MASK)
1488#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK (0x1000U)
1489#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT (12U)
1490/*! CH12_CMDCMPLT_IRQ - CH12_CMDCMPLT_IRQ
1491 */
1492#define APBH_CTRL1_CH12_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_MASK)
1493#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK (0x2000U)
1494#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT (13U)
1495/*! CH13_CMDCMPLT_IRQ - CH13_CMDCMPLT_IRQ
1496 */
1497#define APBH_CTRL1_CH13_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_MASK)
1498#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK (0x4000U)
1499#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT (14U)
1500/*! CH14_CMDCMPLT_IRQ - CH14_CMDCMPLT_IRQ
1501 */
1502#define APBH_CTRL1_CH14_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_MASK)
1503#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK (0x8000U)
1504#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT (15U)
1505/*! CH15_CMDCMPLT_IRQ - CH15_CMDCMPLT_IRQ
1506 */
1507#define APBH_CTRL1_CH15_CMDCMPLT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_MASK)
1508#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK (0x10000U)
1509#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT (16U)
1510/*! CH0_CMDCMPLT_IRQ_EN - CH0_CMDCMPLT_IRQ_EN
1511 */
1512#define APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH0_CMDCMPLT_IRQ_EN_MASK)
1513#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK (0x20000U)
1514#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT (17U)
1515/*! CH1_CMDCMPLT_IRQ_EN - CH1_CMDCMPLT_IRQ_EN
1516 */
1517#define APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH1_CMDCMPLT_IRQ_EN_MASK)
1518#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK (0x40000U)
1519#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT (18U)
1520/*! CH2_CMDCMPLT_IRQ_EN - CH2_CMDCMPLT_IRQ_EN
1521 */
1522#define APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH2_CMDCMPLT_IRQ_EN_MASK)
1523#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK (0x80000U)
1524#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT (19U)
1525/*! CH3_CMDCMPLT_IRQ_EN - CH3_CMDCMPLT_IRQ_EN
1526 */
1527#define APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH3_CMDCMPLT_IRQ_EN_MASK)
1528#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK (0x100000U)
1529#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT (20U)
1530/*! CH4_CMDCMPLT_IRQ_EN - CH4_CMDCMPLT_IRQ_EN
1531 */
1532#define APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH4_CMDCMPLT_IRQ_EN_MASK)
1533#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK (0x200000U)
1534#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT (21U)
1535/*! CH5_CMDCMPLT_IRQ_EN - CH5_CMDCMPLT_IRQ_EN
1536 */
1537#define APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH5_CMDCMPLT_IRQ_EN_MASK)
1538#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK (0x400000U)
1539#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT (22U)
1540/*! CH6_CMDCMPLT_IRQ_EN - CH6_CMDCMPLT_IRQ_EN
1541 */
1542#define APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH6_CMDCMPLT_IRQ_EN_MASK)
1543#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK (0x800000U)
1544#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT (23U)
1545/*! CH7_CMDCMPLT_IRQ_EN - CH7_CMDCMPLT_IRQ_EN
1546 */
1547#define APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH7_CMDCMPLT_IRQ_EN_MASK)
1548#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK (0x1000000U)
1549#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT (24U)
1550/*! CH8_CMDCMPLT_IRQ_EN - CH8_CMDCMPLT_IRQ_EN
1551 */
1552#define APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH8_CMDCMPLT_IRQ_EN_MASK)
1553#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK (0x2000000U)
1554#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT (25U)
1555/*! CH9_CMDCMPLT_IRQ_EN - CH9_CMDCMPLT_IRQ_EN
1556 */
1557#define APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH9_CMDCMPLT_IRQ_EN_MASK)
1558#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK (0x4000000U)
1559#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT (26U)
1560/*! CH10_CMDCMPLT_IRQ_EN - CH10_CMDCMPLT_IRQ_EN
1561 */
1562#define APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH10_CMDCMPLT_IRQ_EN_MASK)
1563#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK (0x8000000U)
1564#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT (27U)
1565/*! CH11_CMDCMPLT_IRQ_EN - CH11_CMDCMPLT_IRQ_EN
1566 */
1567#define APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH11_CMDCMPLT_IRQ_EN_MASK)
1568#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK (0x10000000U)
1569#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT (28U)
1570/*! CH12_CMDCMPLT_IRQ_EN - CH12_CMDCMPLT_IRQ_EN
1571 */
1572#define APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH12_CMDCMPLT_IRQ_EN_MASK)
1573#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK (0x20000000U)
1574#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT (29U)
1575/*! CH13_CMDCMPLT_IRQ_EN - CH13_CMDCMPLT_IRQ_EN
1576 */
1577#define APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH13_CMDCMPLT_IRQ_EN_MASK)
1578#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK (0x40000000U)
1579#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT (30U)
1580/*! CH14_CMDCMPLT_IRQ_EN - CH14_CMDCMPLT_IRQ_EN
1581 */
1582#define APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH14_CMDCMPLT_IRQ_EN_MASK)
1583#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK (0x80000000U)
1584#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT (31U)
1585/*! CH15_CMDCMPLT_IRQ_EN - CH15_CMDCMPLT_IRQ_EN
1586 */
1587#define APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_SHIFT)) & APBH_CTRL1_CH15_CMDCMPLT_IRQ_EN_MASK)
1588/*! @} */
1589
1590/*! @name CTRL2 - AHB to APBH Bridge Control and Status Register 2 */
1591/*! @{ */
1592#define APBH_CTRL2_CH0_ERROR_IRQ_MASK (0x1U)
1593#define APBH_CTRL2_CH0_ERROR_IRQ_SHIFT (0U)
1594/*! CH0_ERROR_IRQ - CH0_ERROR_IRQ
1595 */
1596#define APBH_CTRL2_CH0_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH0_ERROR_IRQ_MASK)
1597#define APBH_CTRL2_CH1_ERROR_IRQ_MASK (0x2U)
1598#define APBH_CTRL2_CH1_ERROR_IRQ_SHIFT (1U)
1599/*! CH1_ERROR_IRQ - CH1_ERROR_IRQ
1600 */
1601#define APBH_CTRL2_CH1_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH1_ERROR_IRQ_MASK)
1602#define APBH_CTRL2_CH2_ERROR_IRQ_MASK (0x4U)
1603#define APBH_CTRL2_CH2_ERROR_IRQ_SHIFT (2U)
1604/*! CH2_ERROR_IRQ - CH2_ERROR_IRQ
1605 */
1606#define APBH_CTRL2_CH2_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH2_ERROR_IRQ_MASK)
1607#define APBH_CTRL2_CH3_ERROR_IRQ_MASK (0x8U)
1608#define APBH_CTRL2_CH3_ERROR_IRQ_SHIFT (3U)
1609/*! CH3_ERROR_IRQ - CH3_ERROR_IRQ
1610 */
1611#define APBH_CTRL2_CH3_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH3_ERROR_IRQ_MASK)
1612#define APBH_CTRL2_CH4_ERROR_IRQ_MASK (0x10U)
1613#define APBH_CTRL2_CH4_ERROR_IRQ_SHIFT (4U)
1614/*! CH4_ERROR_IRQ - CH4_ERROR_IRQ
1615 */
1616#define APBH_CTRL2_CH4_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH4_ERROR_IRQ_MASK)
1617#define APBH_CTRL2_CH5_ERROR_IRQ_MASK (0x20U)
1618#define APBH_CTRL2_CH5_ERROR_IRQ_SHIFT (5U)
1619/*! CH5_ERROR_IRQ - CH5_ERROR_IRQ
1620 */
1621#define APBH_CTRL2_CH5_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH5_ERROR_IRQ_MASK)
1622#define APBH_CTRL2_CH6_ERROR_IRQ_MASK (0x40U)
1623#define APBH_CTRL2_CH6_ERROR_IRQ_SHIFT (6U)
1624/*! CH6_ERROR_IRQ - CH6_ERROR_IRQ
1625 */
1626#define APBH_CTRL2_CH6_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH6_ERROR_IRQ_MASK)
1627#define APBH_CTRL2_CH7_ERROR_IRQ_MASK (0x80U)
1628#define APBH_CTRL2_CH7_ERROR_IRQ_SHIFT (7U)
1629/*! CH7_ERROR_IRQ - CH7_ERROR_IRQ
1630 */
1631#define APBH_CTRL2_CH7_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH7_ERROR_IRQ_MASK)
1632#define APBH_CTRL2_CH8_ERROR_IRQ_MASK (0x100U)
1633#define APBH_CTRL2_CH8_ERROR_IRQ_SHIFT (8U)
1634/*! CH8_ERROR_IRQ - CH8_ERROR_IRQ
1635 */
1636#define APBH_CTRL2_CH8_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH8_ERROR_IRQ_MASK)
1637#define APBH_CTRL2_CH9_ERROR_IRQ_MASK (0x200U)
1638#define APBH_CTRL2_CH9_ERROR_IRQ_SHIFT (9U)
1639/*! CH9_ERROR_IRQ - CH9_ERROR_IRQ
1640 */
1641#define APBH_CTRL2_CH9_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH9_ERROR_IRQ_MASK)
1642#define APBH_CTRL2_CH10_ERROR_IRQ_MASK (0x400U)
1643#define APBH_CTRL2_CH10_ERROR_IRQ_SHIFT (10U)
1644/*! CH10_ERROR_IRQ - CH10_ERROR_IRQ
1645 */
1646#define APBH_CTRL2_CH10_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH10_ERROR_IRQ_MASK)
1647#define APBH_CTRL2_CH11_ERROR_IRQ_MASK (0x800U)
1648#define APBH_CTRL2_CH11_ERROR_IRQ_SHIFT (11U)
1649/*! CH11_ERROR_IRQ - CH11_ERROR_IRQ
1650 */
1651#define APBH_CTRL2_CH11_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH11_ERROR_IRQ_MASK)
1652#define APBH_CTRL2_CH12_ERROR_IRQ_MASK (0x1000U)
1653#define APBH_CTRL2_CH12_ERROR_IRQ_SHIFT (12U)
1654/*! CH12_ERROR_IRQ - CH12_ERROR_IRQ
1655 */
1656#define APBH_CTRL2_CH12_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH12_ERROR_IRQ_MASK)
1657#define APBH_CTRL2_CH13_ERROR_IRQ_MASK (0x2000U)
1658#define APBH_CTRL2_CH13_ERROR_IRQ_SHIFT (13U)
1659/*! CH13_ERROR_IRQ - CH13_ERROR_IRQ
1660 */
1661#define APBH_CTRL2_CH13_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH13_ERROR_IRQ_MASK)
1662#define APBH_CTRL2_CH14_ERROR_IRQ_MASK (0x4000U)
1663#define APBH_CTRL2_CH14_ERROR_IRQ_SHIFT (14U)
1664/*! CH14_ERROR_IRQ - CH14_ERROR_IRQ
1665 */
1666#define APBH_CTRL2_CH14_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH14_ERROR_IRQ_MASK)
1667#define APBH_CTRL2_CH15_ERROR_IRQ_MASK (0x8000U)
1668#define APBH_CTRL2_CH15_ERROR_IRQ_SHIFT (15U)
1669/*! CH15_ERROR_IRQ - CH15_ERROR_IRQ
1670 */
1671#define APBH_CTRL2_CH15_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_IRQ_SHIFT)) & APBH_CTRL2_CH15_ERROR_IRQ_MASK)
1672#define APBH_CTRL2_CH0_ERROR_STATUS_MASK (0x10000U)
1673#define APBH_CTRL2_CH0_ERROR_STATUS_SHIFT (16U)
1674/*! CH0_ERROR_STATUS - CH0_ERROR_STATUS
1675 * 0b0..An early termination from the device causes error IRQ.
1676 * 0b1..An AHB bus error causes error IRQ.
1677 */
1678#define APBH_CTRL2_CH0_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH0_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH0_ERROR_STATUS_MASK)
1679#define APBH_CTRL2_CH1_ERROR_STATUS_MASK (0x20000U)
1680#define APBH_CTRL2_CH1_ERROR_STATUS_SHIFT (17U)
1681/*! CH1_ERROR_STATUS - CH1_ERROR_STATUS
1682 * 0b0..An early termination from the device causes error IRQ.
1683 * 0b1..An AHB bus error causes error IRQ.
1684 */
1685#define APBH_CTRL2_CH1_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH1_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH1_ERROR_STATUS_MASK)
1686#define APBH_CTRL2_CH2_ERROR_STATUS_MASK (0x40000U)
1687#define APBH_CTRL2_CH2_ERROR_STATUS_SHIFT (18U)
1688/*! CH2_ERROR_STATUS - CH2_ERROR_STATUS
1689 * 0b0..An early termination from the device causes error IRQ.
1690 * 0b1..An AHB bus error causes error IRQ.
1691 */
1692#define APBH_CTRL2_CH2_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH2_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH2_ERROR_STATUS_MASK)
1693#define APBH_CTRL2_CH3_ERROR_STATUS_MASK (0x80000U)
1694#define APBH_CTRL2_CH3_ERROR_STATUS_SHIFT (19U)
1695/*! CH3_ERROR_STATUS - CH3_ERROR_STATUS
1696 * 0b0..An early termination from the device causes error IRQ.
1697 * 0b1..An AHB bus error causes error IRQ.
1698 */
1699#define APBH_CTRL2_CH3_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH3_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH3_ERROR_STATUS_MASK)
1700#define APBH_CTRL2_CH4_ERROR_STATUS_MASK (0x100000U)
1701#define APBH_CTRL2_CH4_ERROR_STATUS_SHIFT (20U)
1702/*! CH4_ERROR_STATUS - CH4_ERROR_STATUS
1703 * 0b0..An early termination from the device causes error IRQ.
1704 * 0b1..An AHB bus error causes error IRQ.
1705 */
1706#define APBH_CTRL2_CH4_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH4_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH4_ERROR_STATUS_MASK)
1707#define APBH_CTRL2_CH5_ERROR_STATUS_MASK (0x200000U)
1708#define APBH_CTRL2_CH5_ERROR_STATUS_SHIFT (21U)
1709/*! CH5_ERROR_STATUS - CH5_ERROR_STATUS
1710 * 0b0..An early termination from the device causes error IRQ.
1711 * 0b1..An AHB bus error causes error IRQ.
1712 */
1713#define APBH_CTRL2_CH5_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH5_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH5_ERROR_STATUS_MASK)
1714#define APBH_CTRL2_CH6_ERROR_STATUS_MASK (0x400000U)
1715#define APBH_CTRL2_CH6_ERROR_STATUS_SHIFT (22U)
1716/*! CH6_ERROR_STATUS - CH6_ERROR_STATUS
1717 * 0b0..An early termination from the device causes error IRQ.
1718 * 0b1..An AHB bus error causes error IRQ.
1719 */
1720#define APBH_CTRL2_CH6_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH6_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH6_ERROR_STATUS_MASK)
1721#define APBH_CTRL2_CH7_ERROR_STATUS_MASK (0x800000U)
1722#define APBH_CTRL2_CH7_ERROR_STATUS_SHIFT (23U)
1723/*! CH7_ERROR_STATUS - CH7_ERROR_STATUS
1724 * 0b0..An early termination from the device causes error IRQ.
1725 * 0b1..An AHB bus error causes error IRQ.
1726 */
1727#define APBH_CTRL2_CH7_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH7_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH7_ERROR_STATUS_MASK)
1728#define APBH_CTRL2_CH8_ERROR_STATUS_MASK (0x1000000U)
1729#define APBH_CTRL2_CH8_ERROR_STATUS_SHIFT (24U)
1730/*! CH8_ERROR_STATUS - CH8_ERROR_STATUS
1731 * 0b0..An early termination from the device causes error IRQ.
1732 * 0b1..An AHB bus error causes error IRQ.
1733 */
1734#define APBH_CTRL2_CH8_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH8_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH8_ERROR_STATUS_MASK)
1735#define APBH_CTRL2_CH9_ERROR_STATUS_MASK (0x2000000U)
1736#define APBH_CTRL2_CH9_ERROR_STATUS_SHIFT (25U)
1737/*! CH9_ERROR_STATUS - CH9_ERROR_STATUS
1738 * 0b0..An early termination from the device causes error IRQ.
1739 * 0b1..An AHB bus error causes error IRQ.
1740 */
1741#define APBH_CTRL2_CH9_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH9_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH9_ERROR_STATUS_MASK)
1742#define APBH_CTRL2_CH10_ERROR_STATUS_MASK (0x4000000U)
1743#define APBH_CTRL2_CH10_ERROR_STATUS_SHIFT (26U)
1744/*! CH10_ERROR_STATUS - CH10_ERROR_STATUS
1745 * 0b0..An early termination from the device causes error IRQ.
1746 * 0b1..An AHB bus error causes error IRQ.
1747 */
1748#define APBH_CTRL2_CH10_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH10_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH10_ERROR_STATUS_MASK)
1749#define APBH_CTRL2_CH11_ERROR_STATUS_MASK (0x8000000U)
1750#define APBH_CTRL2_CH11_ERROR_STATUS_SHIFT (27U)
1751/*! CH11_ERROR_STATUS - CH11_ERROR_STATUS
1752 * 0b0..An early termination from the device causes error IRQ.
1753 * 0b1..An AHB bus error causes error IRQ.
1754 */
1755#define APBH_CTRL2_CH11_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH11_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH11_ERROR_STATUS_MASK)
1756#define APBH_CTRL2_CH12_ERROR_STATUS_MASK (0x10000000U)
1757#define APBH_CTRL2_CH12_ERROR_STATUS_SHIFT (28U)
1758/*! CH12_ERROR_STATUS - CH12_ERROR_STATUS
1759 * 0b0..An early termination from the device causes error IRQ.
1760 * 0b1..An AHB bus error causes error IRQ.
1761 */
1762#define APBH_CTRL2_CH12_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH12_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH12_ERROR_STATUS_MASK)
1763#define APBH_CTRL2_CH13_ERROR_STATUS_MASK (0x20000000U)
1764#define APBH_CTRL2_CH13_ERROR_STATUS_SHIFT (29U)
1765/*! CH13_ERROR_STATUS - CH13_ERROR_STATUS
1766 * 0b0..An early termination from the device causes error IRQ.
1767 * 0b1..An AHB bus error causes error IRQ.
1768 */
1769#define APBH_CTRL2_CH13_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH13_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH13_ERROR_STATUS_MASK)
1770#define APBH_CTRL2_CH14_ERROR_STATUS_MASK (0x40000000U)
1771#define APBH_CTRL2_CH14_ERROR_STATUS_SHIFT (30U)
1772/*! CH14_ERROR_STATUS - CH14_ERROR_STATUS
1773 * 0b0..An early termination from the device causes error IRQ.
1774 * 0b1..An AHB bus error causes error IRQ.
1775 */
1776#define APBH_CTRL2_CH14_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH14_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH14_ERROR_STATUS_MASK)
1777#define APBH_CTRL2_CH15_ERROR_STATUS_MASK (0x80000000U)
1778#define APBH_CTRL2_CH15_ERROR_STATUS_SHIFT (31U)
1779/*! CH15_ERROR_STATUS - CH15_ERROR_STATUS
1780 * 0b0..An early termination from the device causes error IRQ.
1781 * 0b1..An AHB bus error causes error IRQ.
1782 */
1783#define APBH_CTRL2_CH15_ERROR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CTRL2_CH15_ERROR_STATUS_SHIFT)) & APBH_CTRL2_CH15_ERROR_STATUS_MASK)
1784/*! @} */
1785
1786/*! @name CHANNEL_CTRL - AHB to APBH Bridge Channel Register */
1787/*! @{ */
1788#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK (0xFFFFU)
1789#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT (0U)
1790/*! FREEZE_CHANNEL - FREEZE_CHANNEL
1791 * 0b0000000000000001..
1792 * 0b0000000000000010..
1793 * 0b0000000000000100..
1794 * 0b0000000000001000..
1795 * 0b0000000000010000..
1796 * 0b0000000000100000..
1797 * 0b0000000001000000..
1798 * 0b0000000010000000..
1799 * 0b0000000100000000..
1800 */
1801#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_FREEZE_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_FREEZE_CHANNEL_MASK)
1802#define APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK (0xFFFF0000U)
1803#define APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT (16U)
1804/*! RESET_CHANNEL - RESET_CHANNEL
1805 * 0b0000000000000001..
1806 * 0b0000000000000010..
1807 * 0b0000000000000100..
1808 * 0b0000000000001000..
1809 * 0b0000000000010000..
1810 * 0b0000000000100000..
1811 * 0b0000000001000000..
1812 * 0b0000000010000000..
1813 * 0b0000000100000000..
1814 */
1815#define APBH_CHANNEL_CTRL_RESET_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CHANNEL_CTRL_RESET_CHANNEL_SHIFT)) & APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK)
1816/*! @} */
1817
1818/*! @name DMA_BURST_SIZE - AHB to APBH DMA burst size */
1819/*! @{ */
1820#define APBH_DMA_BURST_SIZE_CH0_MASK (0x3U)
1821#define APBH_DMA_BURST_SIZE_CH0_SHIFT (0U)
1822/*! CH0 - CH0
1823 */
1824#define APBH_DMA_BURST_SIZE_CH0(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH0_SHIFT)) & APBH_DMA_BURST_SIZE_CH0_MASK)
1825#define APBH_DMA_BURST_SIZE_CH1_MASK (0xCU)
1826#define APBH_DMA_BURST_SIZE_CH1_SHIFT (2U)
1827/*! CH1 - CH1
1828 */
1829#define APBH_DMA_BURST_SIZE_CH1(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH1_SHIFT)) & APBH_DMA_BURST_SIZE_CH1_MASK)
1830#define APBH_DMA_BURST_SIZE_CH2_MASK (0x30U)
1831#define APBH_DMA_BURST_SIZE_CH2_SHIFT (4U)
1832/*! CH2 - CH2
1833 */
1834#define APBH_DMA_BURST_SIZE_CH2(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH2_SHIFT)) & APBH_DMA_BURST_SIZE_CH2_MASK)
1835#define APBH_DMA_BURST_SIZE_CH3_MASK (0xC0U)
1836#define APBH_DMA_BURST_SIZE_CH3_SHIFT (6U)
1837/*! CH3 - CH3
1838 */
1839#define APBH_DMA_BURST_SIZE_CH3(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH3_SHIFT)) & APBH_DMA_BURST_SIZE_CH3_MASK)
1840#define APBH_DMA_BURST_SIZE_CH4_MASK (0x300U)
1841#define APBH_DMA_BURST_SIZE_CH4_SHIFT (8U)
1842/*! CH4 - CH4
1843 */
1844#define APBH_DMA_BURST_SIZE_CH4(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH4_SHIFT)) & APBH_DMA_BURST_SIZE_CH4_MASK)
1845#define APBH_DMA_BURST_SIZE_CH5_MASK (0xC00U)
1846#define APBH_DMA_BURST_SIZE_CH5_SHIFT (10U)
1847/*! CH5 - CH5
1848 */
1849#define APBH_DMA_BURST_SIZE_CH5(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH5_SHIFT)) & APBH_DMA_BURST_SIZE_CH5_MASK)
1850#define APBH_DMA_BURST_SIZE_CH6_MASK (0x3000U)
1851#define APBH_DMA_BURST_SIZE_CH6_SHIFT (12U)
1852/*! CH6 - CH6
1853 */
1854#define APBH_DMA_BURST_SIZE_CH6(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH6_SHIFT)) & APBH_DMA_BURST_SIZE_CH6_MASK)
1855#define APBH_DMA_BURST_SIZE_CH7_MASK (0xC000U)
1856#define APBH_DMA_BURST_SIZE_CH7_SHIFT (14U)
1857/*! CH7 - CH7
1858 */
1859#define APBH_DMA_BURST_SIZE_CH7(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH7_SHIFT)) & APBH_DMA_BURST_SIZE_CH7_MASK)
1860#define APBH_DMA_BURST_SIZE_CH8_MASK (0x30000U)
1861#define APBH_DMA_BURST_SIZE_CH8_SHIFT (16U)
1862/*! CH8 - CH8
1863 * 0b00..
1864 * 0b01..
1865 * 0b10..
1866 */
1867#define APBH_DMA_BURST_SIZE_CH8(x) (((uint32_t)(((uint32_t)(x)) << APBH_DMA_BURST_SIZE_CH8_SHIFT)) & APBH_DMA_BURST_SIZE_CH8_MASK)
1868/*! @} */
1869
1870/*! @name DEBUG - AHB to APBH DMA Debug Register */
1871/*! @{ */
1872#define APBH_DEBUG_GPMI_ONE_FIFO_MASK (0x1U)
1873#define APBH_DEBUG_GPMI_ONE_FIFO_SHIFT (0U)
1874/*! GPMI_ONE_FIFO - GPMI_ONE_FIFO
1875 */
1876#define APBH_DEBUG_GPMI_ONE_FIFO(x) (((uint32_t)(((uint32_t)(x)) << APBH_DEBUG_GPMI_ONE_FIFO_SHIFT)) & APBH_DEBUG_GPMI_ONE_FIFO_MASK)
1877/*! @} */
1878
1879/*! @name CH_CURCMDAR - APBH DMA Channel n Current Command Address Register */
1880/*! @{ */
1881#define APBH_CH_CURCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
1882#define APBH_CH_CURCMDAR_CMD_ADDR_SHIFT (0U)
1883/*! CMD_ADDR - CMD_ADDR
1884 */
1885#define APBH_CH_CURCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CURCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_CURCMDAR_CMD_ADDR_MASK)
1886/*! @} */
1887
1888/* The count of APBH_CH_CURCMDAR */
1889#define APBH_CH_CURCMDAR_COUNT (16U)
1890
1891/*! @name CH_NXTCMDAR - APBH DMA Channel n Next Command Address Register */
1892/*! @{ */
1893#define APBH_CH_NXTCMDAR_CMD_ADDR_MASK (0xFFFFFFFFU)
1894#define APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT (0U)
1895/*! CMD_ADDR - CMD_ADDR
1896 */
1897#define APBH_CH_NXTCMDAR_CMD_ADDR(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_NXTCMDAR_CMD_ADDR_SHIFT)) & APBH_CH_NXTCMDAR_CMD_ADDR_MASK)
1898/*! @} */
1899
1900/* The count of APBH_CH_NXTCMDAR */
1901#define APBH_CH_NXTCMDAR_COUNT (16U)
1902
1903/*! @name CH_CMD - APBH DMA Channel n Command Register */
1904/*! @{ */
1905#define APBH_CH_CMD_COMMAND_MASK (0x3U)
1906#define APBH_CH_CMD_COMMAND_SHIFT (0U)
1907/*! COMMAND - COMMAND
1908 * 0b00..Perform any requested PIO word transfers but terminate command before any DMA transfer.
1909 * 0b01..Perform any requested PIO word transfers and then perform a DMA transfer from the peripheral for the specified number of bytes.
1910 * 0b10..Perform any requested PIO word transfers and then perform a DMA transfer to the peripheral for the specified number of bytes.
1911 * 0b11..Perform any requested PIO word transfers and then perform a conditional branch to the next chained
1912 * device. Follow the NEXCMD_ADDR pointer if the perpheral sense is true. Follow the BUFFER_ADDRESS as a chain
1913 * pointer if the peripheral sense line is false.
1914 */
1915#define APBH_CH_CMD_COMMAND(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_COMMAND_SHIFT)) & APBH_CH_CMD_COMMAND_MASK)
1916#define APBH_CH_CMD_CHAIN_MASK (0x4U)
1917#define APBH_CH_CMD_CHAIN_SHIFT (2U)
1918/*! CHAIN - CHAIN
1919 */
1920#define APBH_CH_CMD_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CHAIN_SHIFT)) & APBH_CH_CMD_CHAIN_MASK)
1921#define APBH_CH_CMD_IRQONCMPLT_MASK (0x8U)
1922#define APBH_CH_CMD_IRQONCMPLT_SHIFT (3U)
1923/*! IRQONCMPLT - IRQONCMPLT
1924 */
1925#define APBH_CH_CMD_IRQONCMPLT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_IRQONCMPLT_SHIFT)) & APBH_CH_CMD_IRQONCMPLT_MASK)
1926#define APBH_CH_CMD_NANDLOCK_MASK (0x10U)
1927#define APBH_CH_CMD_NANDLOCK_SHIFT (4U)
1928/*! NANDLOCK - NANDLOCK
1929 */
1930#define APBH_CH_CMD_NANDLOCK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDLOCK_SHIFT)) & APBH_CH_CMD_NANDLOCK_MASK)
1931#define APBH_CH_CMD_NANDWAIT4READY_MASK (0x20U)
1932#define APBH_CH_CMD_NANDWAIT4READY_SHIFT (5U)
1933/*! NANDWAIT4READY - NANDWAIT4READY
1934 */
1935#define APBH_CH_CMD_NANDWAIT4READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_NANDWAIT4READY_SHIFT)) & APBH_CH_CMD_NANDWAIT4READY_MASK)
1936#define APBH_CH_CMD_SEMAPHORE_MASK (0x40U)
1937#define APBH_CH_CMD_SEMAPHORE_SHIFT (6U)
1938/*! SEMAPHORE - SEMAPHORE
1939 */
1940#define APBH_CH_CMD_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_SEMAPHORE_SHIFT)) & APBH_CH_CMD_SEMAPHORE_MASK)
1941#define APBH_CH_CMD_WAIT4ENDCMD_MASK (0x80U)
1942#define APBH_CH_CMD_WAIT4ENDCMD_SHIFT (7U)
1943/*! WAIT4ENDCMD - WAIT4ENDCMD
1944 */
1945#define APBH_CH_CMD_WAIT4ENDCMD(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_WAIT4ENDCMD_SHIFT)) & APBH_CH_CMD_WAIT4ENDCMD_MASK)
1946#define APBH_CH_CMD_HALTONTERMINATE_MASK (0x100U)
1947#define APBH_CH_CMD_HALTONTERMINATE_SHIFT (8U)
1948/*! HALTONTERMINATE - HALTONTERMINATE
1949 */
1950#define APBH_CH_CMD_HALTONTERMINATE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_HALTONTERMINATE_SHIFT)) & APBH_CH_CMD_HALTONTERMINATE_MASK)
1951#define APBH_CH_CMD_CMDWORDS_MASK (0xF000U)
1952#define APBH_CH_CMD_CMDWORDS_SHIFT (12U)
1953/*! CMDWORDS - CMDWORDS
1954 */
1955#define APBH_CH_CMD_CMDWORDS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_CMDWORDS_SHIFT)) & APBH_CH_CMD_CMDWORDS_MASK)
1956#define APBH_CH_CMD_XFER_COUNT_MASK (0xFFFF0000U)
1957#define APBH_CH_CMD_XFER_COUNT_SHIFT (16U)
1958/*! XFER_COUNT - XFER_COUNT
1959 */
1960#define APBH_CH_CMD_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_CMD_XFER_COUNT_SHIFT)) & APBH_CH_CMD_XFER_COUNT_MASK)
1961/*! @} */
1962
1963/* The count of APBH_CH_CMD */
1964#define APBH_CH_CMD_COUNT (16U)
1965
1966/*! @name CH_BAR - APBH DMA Channel n Buffer Address Register */
1967/*! @{ */
1968#define APBH_CH_BAR_ADDRESS_MASK (0xFFFFFFFFU)
1969#define APBH_CH_BAR_ADDRESS_SHIFT (0U)
1970/*! ADDRESS - ADDRESS
1971 */
1972#define APBH_CH_BAR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_BAR_ADDRESS_SHIFT)) & APBH_CH_BAR_ADDRESS_MASK)
1973/*! @} */
1974
1975/* The count of APBH_CH_BAR */
1976#define APBH_CH_BAR_COUNT (16U)
1977
1978/*! @name CH_SEMA - APBH DMA Channel n Semaphore Register */
1979/*! @{ */
1980#define APBH_CH_SEMA_INCREMENT_SEMA_MASK (0xFFU)
1981#define APBH_CH_SEMA_INCREMENT_SEMA_SHIFT (0U)
1982/*! INCREMENT_SEMA - INCREMENT_SEMA
1983 */
1984#define APBH_CH_SEMA_INCREMENT_SEMA(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_INCREMENT_SEMA_SHIFT)) & APBH_CH_SEMA_INCREMENT_SEMA_MASK)
1985#define APBH_CH_SEMA_PHORE_MASK (0xFF0000U)
1986#define APBH_CH_SEMA_PHORE_SHIFT (16U)
1987/*! PHORE - PHORE
1988 */
1989#define APBH_CH_SEMA_PHORE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_SEMA_PHORE_SHIFT)) & APBH_CH_SEMA_PHORE_MASK)
1990/*! @} */
1991
1992/* The count of APBH_CH_SEMA */
1993#define APBH_CH_SEMA_COUNT (16U)
1994
1995/*! @name CH_DEBUG1 - AHB to APBH DMA Channel n Debug Information */
1996/*! @{ */
1997#define APBH_CH_DEBUG1_STATEMACHINE_MASK (0x1FU)
1998#define APBH_CH_DEBUG1_STATEMACHINE_SHIFT (0U)
1999/*! STATEMACHINE - STATEMACHINE
2000 * 0b00000..This is the idle state of the DMA state machine.
2001 * 0b00001..State in which the DMA is waiting to receive the first word of a command.
2002 * 0b00010..State in which the DMA is waiting to receive the third word of a command.
2003 * 0b00011..State in which the DMA is waiting to receive the second word of a command.
2004 * 0b00100..The state machine processes the descriptor command field in this state and branches accordingly.
2005 * 0b00101..The state machine waits in this state for the PIO APB cycles to complete.
2006 * 0b00110..State in which the DMA is waiting to receive the fourth word of a command, or waiting to receive the
2007 * PIO words when PIO count is greater than 1.
2008 * 0b00111..This state determines whether another PIO cycle needs to occur before starting DMA transfers.
2009 * 0b01000..During a read transfers, the state machine enters this state waiting for the last bytes to be pushed out on the APB.
2010 * 0b01001..When an AHB read request occurs, the state machine waits in this state for the AHB transfer to complete.
2011 * 0b01100..During DMA Write transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2012 * 0b01101..During DMA Read transfers, the state machine waits in this state until the AHB master arbiter accepts the request from this channel.
2013 * 0b01110..Upon completion of the DMA transfers, this state checks the value of the Chain bit and branches accordingly.
2014 * 0b01111..The state machine goes to this state after the DMA transfers are complete, and determines what step to take next.
2015 * 0b10100..When a terminate signal is set, the state machine enters this state until the current AHB transfer is completed.
2016 * 0b10101..When the Wait for Command End bit is set, the state machine enters this state until the DMA device indicates that the command is complete.
2017 * 0b11100..During DMA Write transfers, the state machine waits in this state until the AHB master completes the write to the AHB memory space.
2018 * 0b11101..If HALTONTERMINATE is set and a terminate signal is set, the state machine enters this state and
2019 * effectively halts. A channel reset is required to exit this state
2020 * 0b11110..If the Chain bit is a 0, the state machine enters this state and effectively halts.
2021 * 0b11111..When the NAND Wait for Ready bit is set, the state machine enters this state until the GPMI device
2022 * indicates that the external device is ready.
2023 */
2024#define APBH_CH_DEBUG1_STATEMACHINE(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_STATEMACHINE_SHIFT)) & APBH_CH_DEBUG1_STATEMACHINE_MASK)
2025#define APBH_CH_DEBUG1_WR_FIFO_FULL_MASK (0x100000U)
2026#define APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT (20U)
2027/*! WR_FIFO_FULL - WR_FIFO_FULL
2028 */
2029#define APBH_CH_DEBUG1_WR_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_FULL_MASK)
2030#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK (0x200000U)
2031#define APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT (21U)
2032/*! WR_FIFO_EMPTY - WR_FIFO_EMPTY
2033 */
2034#define APBH_CH_DEBUG1_WR_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_WR_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_WR_FIFO_EMPTY_MASK)
2035#define APBH_CH_DEBUG1_RD_FIFO_FULL_MASK (0x400000U)
2036#define APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT (22U)
2037/*! RD_FIFO_FULL - RD_FIFO_FULL
2038 */
2039#define APBH_CH_DEBUG1_RD_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_FULL_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_FULL_MASK)
2040#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK (0x800000U)
2041#define APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT (23U)
2042/*! RD_FIFO_EMPTY - RD_FIFO_EMPTY
2043 */
2044#define APBH_CH_DEBUG1_RD_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_RD_FIFO_EMPTY_SHIFT)) & APBH_CH_DEBUG1_RD_FIFO_EMPTY_MASK)
2045#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK (0x1000000U)
2046#define APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT (24U)
2047/*! NEXTCMDADDRVALID - NEXTCMDADDRVALID
2048 */
2049#define APBH_CH_DEBUG1_NEXTCMDADDRVALID(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_NEXTCMDADDRVALID_SHIFT)) & APBH_CH_DEBUG1_NEXTCMDADDRVALID_MASK)
2050#define APBH_CH_DEBUG1_READY_MASK (0x4000000U)
2051#define APBH_CH_DEBUG1_READY_SHIFT (26U)
2052/*! READY - READY
2053 */
2054#define APBH_CH_DEBUG1_READY(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_READY_SHIFT)) & APBH_CH_DEBUG1_READY_MASK)
2055#define APBH_CH_DEBUG1_END_MASK (0x10000000U)
2056#define APBH_CH_DEBUG1_END_SHIFT (28U)
2057/*! END - END
2058 */
2059#define APBH_CH_DEBUG1_END(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_END_SHIFT)) & APBH_CH_DEBUG1_END_MASK)
2060#define APBH_CH_DEBUG1_KICK_MASK (0x20000000U)
2061#define APBH_CH_DEBUG1_KICK_SHIFT (29U)
2062/*! KICK - KICK
2063 */
2064#define APBH_CH_DEBUG1_KICK(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_KICK_SHIFT)) & APBH_CH_DEBUG1_KICK_MASK)
2065#define APBH_CH_DEBUG1_BURST_MASK (0x40000000U)
2066#define APBH_CH_DEBUG1_BURST_SHIFT (30U)
2067/*! BURST - BURST
2068 */
2069#define APBH_CH_DEBUG1_BURST(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_BURST_SHIFT)) & APBH_CH_DEBUG1_BURST_MASK)
2070#define APBH_CH_DEBUG1_REQ_MASK (0x80000000U)
2071#define APBH_CH_DEBUG1_REQ_SHIFT (31U)
2072/*! REQ - REQ
2073 */
2074#define APBH_CH_DEBUG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG1_REQ_SHIFT)) & APBH_CH_DEBUG1_REQ_MASK)
2075/*! @} */
2076
2077/* The count of APBH_CH_DEBUG1 */
2078#define APBH_CH_DEBUG1_COUNT (16U)
2079
2080/*! @name CH_DEBUG2 - AHB to APBH DMA Channel n Debug Information */
2081/*! @{ */
2082#define APBH_CH_DEBUG2_AHB_BYTES_MASK (0xFFFFU)
2083#define APBH_CH_DEBUG2_AHB_BYTES_SHIFT (0U)
2084/*! AHB_BYTES - AHB_BYTES
2085 */
2086#define APBH_CH_DEBUG2_AHB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_AHB_BYTES_SHIFT)) & APBH_CH_DEBUG2_AHB_BYTES_MASK)
2087#define APBH_CH_DEBUG2_APB_BYTES_MASK (0xFFFF0000U)
2088#define APBH_CH_DEBUG2_APB_BYTES_SHIFT (16U)
2089/*! APB_BYTES - APB_BYTES
2090 */
2091#define APBH_CH_DEBUG2_APB_BYTES(x) (((uint32_t)(((uint32_t)(x)) << APBH_CH_DEBUG2_APB_BYTES_SHIFT)) & APBH_CH_DEBUG2_APB_BYTES_MASK)
2092/*! @} */
2093
2094/* The count of APBH_CH_DEBUG2 */
2095#define APBH_CH_DEBUG2_COUNT (16U)
2096
2097/*! @name VERSION - APBH Bridge Version Register */
2098/*! @{ */
2099#define APBH_VERSION_STEP_MASK (0xFFFFU)
2100#define APBH_VERSION_STEP_SHIFT (0U)
2101/*! STEP - STEP
2102 */
2103#define APBH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_STEP_SHIFT)) & APBH_VERSION_STEP_MASK)
2104#define APBH_VERSION_MINOR_MASK (0xFF0000U)
2105#define APBH_VERSION_MINOR_SHIFT (16U)
2106/*! MINOR - MINOR
2107 */
2108#define APBH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MINOR_SHIFT)) & APBH_VERSION_MINOR_MASK)
2109#define APBH_VERSION_MAJOR_MASK (0xFF000000U)
2110#define APBH_VERSION_MAJOR_SHIFT (24U)
2111/*! MAJOR - MAJOR
2112 */
2113#define APBH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << APBH_VERSION_MAJOR_SHIFT)) & APBH_VERSION_MAJOR_MASK)
2114/*! @} */
2115
2116
2117/*!
2118 * @}
2119 */ /* end of group APBH_Register_Masks */
2120
2121
2122/* APBH - Peripheral instance base addresses */
2123/** Peripheral CONNECTIVITY__APBH base address */
2124#define CONNECTIVITY__APBH_BASE (0x5B810000u)
2125/** Peripheral CONNECTIVITY__APBH base pointer */
2126#define CONNECTIVITY__APBH ((APBH_Type *)CONNECTIVITY__APBH_BASE)
2127/** Array initializer of APBH peripheral base addresses */
2128#define APBH_BASE_ADDRS { CONNECTIVITY__APBH_BASE }
2129/** Array initializer of APBH peripheral base pointers */
2130#define APBH_BASE_PTRS { CONNECTIVITY__APBH }
2131/** Interrupt vectors for the APBH peripheral type */
2132#define APBH_IRQS { CONNECTIVITY_APBHDMA_IRQn }
2133
2134/*!
2135 * @}
2136 */ /* end of group APBH_Peripheral_Access_Layer */
2137
2138
2139/* ----------------------------------------------------------------------------
2140 -- ASMC Peripheral Access Layer
2141 ---------------------------------------------------------------------------- */
2142
2143/*!
2144 * @addtogroup ASMC_Peripheral_Access_Layer ASMC Peripheral Access Layer
2145 * @{
2146 */
2147
2148/** ASMC - Register Layout Typedef */
2149typedef struct {
2150 __I uint32_t SRS; /**< System Reset Status Register, offset: 0x0 */
2151 uint8_t RESERVED_0[4];
2152 __IO uint32_t PMPROT; /**< Power Mode Protection register, offset: 0x8 */
2153 __IO uint32_t PMCTRL; /**< Power Mode Control register, offset: 0xC */
2154 __IO uint32_t STOPCTRL; /**< Stop Control Register, offset: 0x10 */
2155 __I uint32_t PMSTAT; /**< Power Mode Status register, offset: 0x14 */
2156} ASMC_Type;
2157
2158/* ----------------------------------------------------------------------------
2159 -- ASMC Register Masks
2160 ---------------------------------------------------------------------------- */
2161
2162/*!
2163 * @addtogroup ASMC_Register_Masks ASMC Register Masks
2164 * @{
2165 */
2166
2167/*! @name SRS - System Reset Status Register */
2168/*! @{ */
2169#define ASMC_SRS_WAKEUP_MASK (0x1U)
2170#define ASMC_SRS_WAKEUP_SHIFT (0U)
2171/*! WAKEUP - Low Leakage Wakeup Reset
2172 * 0b0..Reset not caused by LLWU module wakeup source
2173 * 0b1..Reset caused by LLWU module wakeup source
2174 */
2175#define ASMC_SRS_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WAKEUP_SHIFT)) & ASMC_SRS_WAKEUP_MASK)
2176#define ASMC_SRS_WDOG1_MASK (0x20U)
2177#define ASMC_SRS_WDOG1_SHIFT (5U)
2178/*! WDOG1 - Watchdog
2179 * 0b0..Reset not caused by watchdog timeout
2180 * 0b1..Reset caused by watchdog timeout
2181 */
2182#define ASMC_SRS_WDOG1(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_WDOG1_SHIFT)) & ASMC_SRS_WDOG1_MASK)
2183#define ASMC_SRS_RES_MASK (0x40U)
2184#define ASMC_SRS_RES_SHIFT (6U)
2185/*! RES - Chip Reset not POR
2186 * 0b0..Chip Reset did not occur
2187 * 0b1..Chip Reset caused by a source other than POR occured
2188 */
2189#define ASMC_SRS_RES(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_RES_SHIFT)) & ASMC_SRS_RES_MASK)
2190#define ASMC_SRS_POR_MASK (0x80U)
2191#define ASMC_SRS_POR_SHIFT (7U)
2192/*! POR - Power-On Reset
2193 * 0b0..Reset not caused by POR
2194 * 0b1..Reset caused by POR
2195 */
2196#define ASMC_SRS_POR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_POR_SHIFT)) & ASMC_SRS_POR_MASK)
2197#define ASMC_SRS_LOCKUP_MASK (0x200U)
2198#define ASMC_SRS_LOCKUP_SHIFT (9U)
2199/*! LOCKUP - Core 1 Lockup
2200 * 0b0..Reset not caused by core LOCKUP event
2201 * 0b1..Reset caused by core LOCKUP event
2202 */
2203#define ASMC_SRS_LOCKUP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_LOCKUP_SHIFT)) & ASMC_SRS_LOCKUP_MASK)
2204#define ASMC_SRS_SW_MASK (0x400U)
2205#define ASMC_SRS_SW_SHIFT (10U)
2206/*! SW - Software
2207 * 0b0..Reset not caused by software setting of SYSRESETREQ bit
2208 * 0b1..Reset caused by software setting of SYSRESETREQ bit
2209 */
2210#define ASMC_SRS_SW(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SW_SHIFT)) & ASMC_SRS_SW_MASK)
2211#define ASMC_SRS_SACKERR_MASK (0x1000U)
2212#define ASMC_SRS_SACKERR_SHIFT (12U)
2213/*! SACKERR - Stop Mode Acknowledge Error Reset
2214 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
2215 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
2216 */
2217#define ASMC_SRS_SACKERR(x) (((uint32_t)(((uint32_t)(x)) << ASMC_SRS_SACKERR_SHIFT)) & ASMC_SRS_SACKERR_MASK)
2218/*! @} */
2219
2220/*! @name PMPROT - Power Mode Protection register */
2221/*! @{ */
2222#define ASMC_PMPROT_AVLLS_MASK (0x2U)
2223#define ASMC_PMPROT_AVLLS_SHIFT (1U)
2224/*! AVLLS - Allow Very-Low-Leakage Stop Mode
2225 * 0b0..Not Allowed
2226 * 0b1..Allowed
2227 */
2228#define ASMC_PMPROT_AVLLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLLS_SHIFT)) & ASMC_PMPROT_AVLLS_MASK)
2229#define ASMC_PMPROT_ALLS_MASK (0x8U)
2230#define ASMC_PMPROT_ALLS_SHIFT (3U)
2231/*! ALLS - Allow Low-Leakage Stop Mode
2232 * 0b0..Not Allowed
2233 * 0b1..Allowed
2234 */
2235#define ASMC_PMPROT_ALLS(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_ALLS_SHIFT)) & ASMC_PMPROT_ALLS_MASK)
2236#define ASMC_PMPROT_AVLP_MASK (0x20U)
2237#define ASMC_PMPROT_AVLP_SHIFT (5U)
2238/*! AVLP - Allow Very-Low-Power Modes
2239 * 0b0..VLPR, VLPW, and VLPS are not allowed.
2240 * 0b1..VLPR, VLPW, and VLPS are allowed.
2241 */
2242#define ASMC_PMPROT_AVLP(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AVLP_SHIFT)) & ASMC_PMPROT_AVLP_MASK)
2243#define ASMC_PMPROT_AHSRUN_MASK (0x80U)
2244#define ASMC_PMPROT_AHSRUN_SHIFT (7U)
2245/*! AHSRUN - Allow High Speed Run mode
2246 * 0b0..HSRUN is not allowed
2247 * 0b1..HSRUN is allowed
2248 */
2249#define ASMC_PMPROT_AHSRUN(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMPROT_AHSRUN_SHIFT)) & ASMC_PMPROT_AHSRUN_MASK)
2250/*! @} */
2251
2252/*! @name PMCTRL - Power Mode Control register */
2253/*! @{ */
2254#define ASMC_PMCTRL_STOPM_MASK (0x7U)
2255#define ASMC_PMCTRL_STOPM_SHIFT (0U)
2256/*! STOPM - Stop Mode Control
2257 * 0b000..Normal Stop (STOP)
2258 * 0b001..Reserved
2259 * 0b010..Very-Low-Power Stop (VLPS)
2260 * 0b011..Low-leakage stop
2261 * 0b100..Very-low-leakage stop
2262 * 0b101..Reserved
2263 * 0b110..Reseved
2264 * 0b111..Reserved
2265 */
2266#define ASMC_PMCTRL_STOPM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_STOPM_SHIFT)) & ASMC_PMCTRL_STOPM_MASK)
2267#define ASMC_PMCTRL_RUNM_MASK (0x60U)
2268#define ASMC_PMCTRL_RUNM_SHIFT (5U)
2269/*! RUNM - Run Mode Control
2270 * 0b00..Normal Run mode (RUN)
2271 * 0b01..Reserved
2272 * 0b10..Very-Low-Power Run mode (VLPR)
2273 * 0b11..High Speed Run mode (HSRUN)
2274 */
2275#define ASMC_PMCTRL_RUNM(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMCTRL_RUNM_SHIFT)) & ASMC_PMCTRL_RUNM_MASK)
2276/*! @} */
2277
2278/*! @name STOPCTRL - Stop Control Register */
2279/*! @{ */
2280#define ASMC_STOPCTRL_PSTOPO_MASK (0xC0U)
2281#define ASMC_STOPCTRL_PSTOPO_SHIFT (6U)
2282/*! PSTOPO - Partial Stop Option
2283 * 0b00..STOP - Normal Stop mode
2284 * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
2285 * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
2286 * 0b11..Reserved
2287 */
2288#define ASMC_STOPCTRL_PSTOPO(x) (((uint32_t)(((uint32_t)(x)) << ASMC_STOPCTRL_PSTOPO_SHIFT)) & ASMC_STOPCTRL_PSTOPO_MASK)
2289/*! @} */
2290
2291/*! @name PMSTAT - Power Mode Status register */
2292/*! @{ */
2293#define ASMC_PMSTAT_PMSTAT_MASK (0xFFU) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
2294#define ASMC_PMSTAT_PMSTAT_SHIFT (0U)
2295/*! PMSTAT - Power Mode Status
2296 * 0b00000001..Current power mode is RUN.
2297 * 0b00000010..Current power mode is STOP.
2298 * 0b00000100..Current power mode is VLPR.
2299 * 0b00001000..Current power mode is VLPW.
2300 * 0b00010000..Current power mode is VLPS.
2301 * 0b00100000..Current power mode is LLS.
2302 * 0b01000000..Current power mode is VLLS.
2303 * 0b10000000..Current power mode is HSRUN
2304 */
2305#define ASMC_PMSTAT_PMSTAT(x) (((uint32_t)(((uint32_t)(x)) << ASMC_PMSTAT_PMSTAT_SHIFT)) & ASMC_PMSTAT_PMSTAT_MASK) /* Merged from fields with different position or width, of widths (7, 8), largest definition used */
2306/*! @} */
2307
2308
2309/*!
2310 * @}
2311 */ /* end of group ASMC_Register_Masks */
2312
2313
2314/* ASMC - Peripheral instance base addresses */
2315/** Peripheral CM4__ASMC base address */
2316#define CM4__ASMC_BASE (0x41410000u)
2317/** Peripheral CM4__ASMC base pointer */
2318#define CM4__ASMC ((ASMC_Type *)CM4__ASMC_BASE)
2319/** Peripheral SCU__ASMC base address */
2320#define SCU__ASMC_BASE (0x33410000u)
2321/** Peripheral SCU__ASMC base pointer */
2322#define SCU__ASMC ((ASMC_Type *)SCU__ASMC_BASE)
2323/** Array initializer of ASMC peripheral base addresses */
2324#define ASMC_BASE_ADDRS { CM4__ASMC_BASE, SCU__ASMC_BASE }
2325/** Array initializer of ASMC peripheral base pointers */
2326#define ASMC_BASE_PTRS { CM4__ASMC, SCU__ASMC }
2327
2328/*!
2329 * @}
2330 */ /* end of group ASMC_Peripheral_Access_Layer */
2331
2332
2333/* ----------------------------------------------------------------------------
2334 -- ASRC Peripheral Access Layer
2335 ---------------------------------------------------------------------------- */
2336
2337/*!
2338 * @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
2339 * @{
2340 */
2341
2342/** ASRC - Register Layout Typedef */
2343typedef struct {
2344 __IO uint32_t ASRCTR; /**< ASRC Control Register, offset: 0x0 */
2345 __IO uint32_t ASRIER; /**< ASRC Interrupt Enable Register, offset: 0x4 */
2346 uint8_t RESERVED_0[4];
2347 __IO uint32_t ASRCNCR; /**< ASRC Channel Number Configuration Register, offset: 0xC */
2348 __IO uint32_t ASRCFG; /**< ASRC Filter Configuration Status Register, offset: 0x10 */
2349 __IO uint32_t ASRCSR; /**< ASRC Clock Source Register, offset: 0x14 */
2350 __IO uint32_t ASRCDR1; /**< ASRC Clock Divider Register 1, offset: 0x18 */
2351 __IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */
2352 __I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */
2353 uint8_t RESERVED_1[28];
2354 __IO uint32_t ASRPM[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
2355 __IO uint32_t ASRTFR1; /**< ASRC ASRC Task Queue FIFO Register 1, offset: 0x54 */
2356 uint8_t RESERVED_2[4];
2357 __IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */
2358 __O uint32_t ASRDIA; /**< ASRC Data Input Register for Pair x, offset: 0x60 */
2359 __I uint32_t ASRDOA; /**< ASRC Data Output Register for Pair x, offset: 0x64 */
2360 __O uint32_t ASRDIB; /**< ASRC Data Input Register for Pair x, offset: 0x68 */
2361 __I uint32_t ASRDOB; /**< ASRC Data Output Register for Pair x, offset: 0x6C */
2362 __O uint32_t ASRDIC; /**< ASRC Data Input Register for Pair x, offset: 0x70 */
2363 __I uint32_t ASRDOC; /**< ASRC Data Output Register for Pair x, offset: 0x74 */
2364 uint8_t RESERVED_3[8];
2365 __IO uint32_t ASRIDRHA; /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
2366 __IO uint32_t ASRIDRLA; /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
2367 __IO uint32_t ASRIDRHB; /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
2368 __IO uint32_t ASRIDRLB; /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
2369 __IO uint32_t ASRIDRHC; /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
2370 __IO uint32_t ASRIDRLC; /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
2371 __IO uint32_t ASR76K; /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */
2372 __IO uint32_t ASR56K; /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */
2373 __IO uint32_t ASRMCRA; /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
2374 __I uint32_t ASRFSTA; /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
2375 __IO uint32_t ASRMCRB; /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
2376 __I uint32_t ASRFSTB; /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
2377 __IO uint32_t ASRMCRC; /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
2378 __I uint32_t ASRFSTC; /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
2379 uint8_t RESERVED_4[8];
2380 __IO uint32_t ASRMCR1[3]; /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */
2381} ASRC_Type;
2382
2383/* ----------------------------------------------------------------------------
2384 -- ASRC Register Masks
2385 ---------------------------------------------------------------------------- */
2386
2387/*!
2388 * @addtogroup ASRC_Register_Masks ASRC Register Masks
2389 * @{
2390 */
2391
2392/*! @name ASRCTR - ASRC Control Register */
2393/*! @{ */
2394#define ASRC_ASRCTR_ASRCEN_MASK (0x1U)
2395#define ASRC_ASRCTR_ASRCEN_SHIFT (0U)
2396/*! ASRCEN - ASRCEN
2397 */
2398#define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
2399#define ASRC_ASRCTR_ASREA_MASK (0x2U)
2400#define ASRC_ASRCTR_ASREA_SHIFT (1U)
2401/*! ASREA - ASREA
2402 */
2403#define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
2404#define ASRC_ASRCTR_ASREB_MASK (0x4U)
2405#define ASRC_ASRCTR_ASREB_SHIFT (2U)
2406/*! ASREB - ASREB
2407 */
2408#define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
2409#define ASRC_ASRCTR_ASREC_MASK (0x8U)
2410#define ASRC_ASRCTR_ASREC_SHIFT (3U)
2411/*! ASREC - ASREC
2412 */
2413#define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
2414#define ASRC_ASRCTR_SRST_MASK (0x10U)
2415#define ASRC_ASRCTR_SRST_SHIFT (4U)
2416/*! SRST - SRST
2417 */
2418#define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
2419#define ASRC_ASRCTR_IDRA_MASK (0x2000U)
2420#define ASRC_ASRCTR_IDRA_SHIFT (13U)
2421/*! IDRA - IDRA
2422 */
2423#define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
2424#define ASRC_ASRCTR_USRA_MASK (0x4000U)
2425#define ASRC_ASRCTR_USRA_SHIFT (14U)
2426/*! USRA - USRA
2427 */
2428#define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
2429#define ASRC_ASRCTR_IDRB_MASK (0x8000U)
2430#define ASRC_ASRCTR_IDRB_SHIFT (15U)
2431/*! IDRB - IDRB
2432 */
2433#define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
2434#define ASRC_ASRCTR_USRB_MASK (0x10000U)
2435#define ASRC_ASRCTR_USRB_SHIFT (16U)
2436/*! USRB - USRB
2437 */
2438#define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
2439#define ASRC_ASRCTR_IDRC_MASK (0x20000U)
2440#define ASRC_ASRCTR_IDRC_SHIFT (17U)
2441/*! IDRC - IDRC
2442 */
2443#define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
2444#define ASRC_ASRCTR_USRC_MASK (0x40000U)
2445#define ASRC_ASRCTR_USRC_SHIFT (18U)
2446/*! USRC - USRC
2447 */
2448#define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
2449#define ASRC_ASRCTR_ATSA_MASK (0x100000U)
2450#define ASRC_ASRCTR_ATSA_SHIFT (20U)
2451/*! ATSA - ATSA
2452 */
2453#define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
2454#define ASRC_ASRCTR_ATSB_MASK (0x200000U)
2455#define ASRC_ASRCTR_ATSB_SHIFT (21U)
2456/*! ATSB - ATSB
2457 */
2458#define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
2459#define ASRC_ASRCTR_ATSC_MASK (0x400000U)
2460#define ASRC_ASRCTR_ATSC_SHIFT (22U)
2461/*! ATSC - ATSC
2462 */
2463#define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
2464/*! @} */
2465
2466/*! @name ASRIER - ASRC Interrupt Enable Register */
2467/*! @{ */
2468#define ASRC_ASRIER_ADIEA_MASK (0x1U)
2469#define ASRC_ASRIER_ADIEA_SHIFT (0U)
2470/*! ADIEA - ADIEA
2471 * 0b1..interrupt enabled
2472 * 0b0..interrupt disabled
2473 */
2474#define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
2475#define ASRC_ASRIER_ADIEB_MASK (0x2U)
2476#define ASRC_ASRIER_ADIEB_SHIFT (1U)
2477/*! ADIEB - ADIEB
2478 * 0b1..interrupt enabled
2479 * 0b0..interrupt disabled
2480 */
2481#define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
2482#define ASRC_ASRIER_ADIEC_MASK (0x4U)
2483#define ASRC_ASRIER_ADIEC_SHIFT (2U)
2484/*! ADIEC - ADIEC
2485 * 0b1..interrupt enabled
2486 * 0b0..interrupt disabled
2487 */
2488#define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
2489#define ASRC_ASRIER_ADOEA_MASK (0x8U)
2490#define ASRC_ASRIER_ADOEA_SHIFT (3U)
2491/*! ADOEA - ADOEA
2492 * 0b1..interrupt enabled
2493 * 0b0..interrupt disabled
2494 */
2495#define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
2496#define ASRC_ASRIER_ADOEB_MASK (0x10U)
2497#define ASRC_ASRIER_ADOEB_SHIFT (4U)
2498/*! ADOEB - ADOEB
2499 * 0b1..interrupt enabled
2500 * 0b0..interrupt disabled
2501 */
2502#define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
2503#define ASRC_ASRIER_ADOEC_MASK (0x20U)
2504#define ASRC_ASRIER_ADOEC_SHIFT (5U)
2505/*! ADOEC - ADOEC
2506 * 0b1..interrupt enabled
2507 * 0b0..interrupt disabled
2508 */
2509#define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
2510#define ASRC_ASRIER_AOLIE_MASK (0x40U)
2511#define ASRC_ASRIER_AOLIE_SHIFT (6U)
2512/*! AOLIE - AOLIE
2513 * 0b1..interrupt enabled
2514 * 0b0..interrupt disabled
2515 */
2516#define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
2517#define ASRC_ASRIER_AFPWE_MASK (0x80U)
2518#define ASRC_ASRIER_AFPWE_SHIFT (7U)
2519/*! AFPWE - AFPWE
2520 * 0b1..interrupt enabled
2521 * 0b0..interrupt disabled
2522 */
2523#define ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
2524/*! @} */
2525
2526/*! @name ASRCNCR - ASRC Channel Number Configuration Register */
2527/*! @{ */
2528#define ASRC_ASRCNCR_ANCA_MASK (0xFU)
2529#define ASRC_ASRCNCR_ANCA_SHIFT (0U)
2530/*! ANCA - ANCA
2531 * 0b0000..0 channels in A (Pair A is disabled)
2532 * 0b0001..1 channel in A
2533 * 0b0010..2 channels in A
2534 * 0b0011..3 channels in A
2535 * 0b0100..4 channels in A
2536 * 0b0101..5 channels in A
2537 * 0b0110..6 channels in A
2538 * 0b0111..7 channels in A
2539 * 0b1000..8 channels in A
2540 * 0b1001..9 channels in A
2541 * 0b1010..10 channels in A
2542 * 0b1011-0b1111..Should not be used.
2543 */
2544#define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
2545#define ASRC_ASRCNCR_ANCB_MASK (0xF0U)
2546#define ASRC_ASRCNCR_ANCB_SHIFT (4U)
2547/*! ANCB - ANCB
2548 * 0b0000..0 channels in B (Pair B is disabled)
2549 * 0b0001..1 channel in B
2550 * 0b0010..2 channels in B
2551 * 0b0011..3 channels in B
2552 * 0b0100..4 channels in B
2553 * 0b0101..5 channels in B
2554 * 0b0110..6 channels in B
2555 * 0b0111..7 channels in B
2556 * 0b1000..8 channels in B
2557 * 0b1001..9 channels in B
2558 * 0b1010..10 channels in B
2559 * 0b1011-0b1111..Should not be used.
2560 */
2561#define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
2562#define ASRC_ASRCNCR_ANCC_MASK (0xF00U)
2563#define ASRC_ASRCNCR_ANCC_SHIFT (8U)
2564/*! ANCC - ANCC
2565 * 0b0000..0 channels in C (Pair C is disabled)
2566 * 0b0001..1 channel in C
2567 * 0b0010..2 channels in C
2568 * 0b0011..3 channels in C
2569 * 0b0100..4 channels in C
2570 * 0b0101..5 channels in C
2571 * 0b0110..6 channels in C
2572 * 0b0111..7 channels in C
2573 * 0b1000..8 channels in C
2574 * 0b1001..9 channels in C
2575 * 0b1010..10 channels in C
2576 * 0b1011-0b1111..Should not be used.
2577 */
2578#define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
2579/*! @} */
2580
2581/*! @name ASRCFG - ASRC Filter Configuration Status Register */
2582/*! @{ */
2583#define ASRC_ASRCFG_PREMODA_MASK (0xC0U)
2584#define ASRC_ASRCFG_PREMODA_SHIFT (6U)
2585/*! PREMODA - PREMODA
2586 * 0b00..Select Upsampling-by-2 as defined in
2587 * 0b01..Select Direct-Connection as defined in
2588 * 0b10..Select Downsampling-by-2 as defined in
2589 * 0b11..Select passthrough mode. In this case, POSTMODA[1-0] have no use.
2590 */
2591#define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
2592#define ASRC_ASRCFG_POSTMODA_MASK (0x300U)
2593#define ASRC_ASRCFG_POSTMODA_SHIFT (8U)
2594/*! POSTMODA - POSTMODA
2595 * 0b00..Select Upsampling-by-2 as defined in
2596 * 0b01..Select Direct-Connection as defined in
2597 * 0b10..Select Downsampling-by-2 as defined in
2598 */
2599#define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
2600#define ASRC_ASRCFG_PREMODB_MASK (0xC00U)
2601#define ASRC_ASRCFG_PREMODB_SHIFT (10U)
2602/*! PREMODB - PREMODB
2603 * 0b00..Select Upsampling-by-2 as defined in
2604 * 0b01..Select Direct-Connection as defined in
2605 * 0b10..Select Downsampling-by-2 as defined in
2606 * 0b11..Select passthrough mode. In this case, POSTMODB[1-0] have no use.
2607 */
2608#define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
2609#define ASRC_ASRCFG_POSTMODB_MASK (0x3000U)
2610#define ASRC_ASRCFG_POSTMODB_SHIFT (12U)
2611/*! POSTMODB - POSTMODB
2612 * 0b00..Select Upsampling-by-2 as defined in
2613 * 0b01..Select Direct-Connection as defined in
2614 * 0b10..Select Downsampling-by-2 as defined in
2615 */
2616#define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
2617#define ASRC_ASRCFG_PREMODC_MASK (0xC000U)
2618#define ASRC_ASRCFG_PREMODC_SHIFT (14U)
2619/*! PREMODC - PREMODC
2620 * 0b00..Select Upsampling-by-2 as defined in
2621 * 0b01..Select Direct-Connection as defined in
2622 * 0b10..Select Downsampling-by-2 as defined in
2623 * 0b11..Select passthrough mode. In this case, POSTMODC[1-0] have no use.
2624 */
2625#define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
2626#define ASRC_ASRCFG_POSTMODC_MASK (0x30000U)
2627#define ASRC_ASRCFG_POSTMODC_SHIFT (16U)
2628/*! POSTMODC - POSTMODC
2629 * 0b00..Select Upsampling-by-2 as defined in Signal Processing Flow.
2630 * 0b01..Select Direct-Connection as defined in Signal Processing Flow.
2631 * 0b10..Select Downsampling-by-2 as defined in Signal Processing Flow.
2632 */
2633#define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
2634#define ASRC_ASRCFG_NDPRA_MASK (0x40000U)
2635#define ASRC_ASRCFG_NDPRA_SHIFT (18U)
2636/*! NDPRA - NDPRA
2637 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2638 * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
2639 */
2640#define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
2641#define ASRC_ASRCFG_NDPRB_MASK (0x80000U)
2642#define ASRC_ASRCFG_NDPRB_SHIFT (19U)
2643/*! NDPRB - NDPRB
2644 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2645 * 0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
2646 */
2647#define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
2648#define ASRC_ASRCFG_NDPRC_MASK (0x100000U)
2649#define ASRC_ASRCFG_NDPRC_SHIFT (20U)
2650/*! NDPRC - NDPRC
2651 * 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
2652 * 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
2653 */
2654#define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
2655#define ASRC_ASRCFG_INIRQA_MASK (0x200000U)
2656#define ASRC_ASRCFG_INIRQA_SHIFT (21U)
2657/*! INIRQA - INIRQA
2658 */
2659#define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
2660#define ASRC_ASRCFG_INIRQB_MASK (0x400000U)
2661#define ASRC_ASRCFG_INIRQB_SHIFT (22U)
2662/*! INIRQB - INIRQB
2663 */
2664#define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
2665#define ASRC_ASRCFG_INIRQC_MASK (0x800000U)
2666#define ASRC_ASRCFG_INIRQC_SHIFT (23U)
2667/*! INIRQC - INIRQC
2668 */
2669#define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
2670/*! @} */
2671
2672/*! @name ASRCSR - ASRC Clock Source Register */
2673/*! @{ */
2674#define ASRC_ASRCSR_AICSA_MASK (0xFU)
2675#define ASRC_ASRCSR_AICSA_SHIFT (0U)
2676/*! AICSA - AICSA
2677 * 0b0000..bit clock 0
2678 * 0b0001..bit clock 1
2679 * 0b0010..bit clock 2
2680 * 0b0011..bit clock 3
2681 * 0b0100..bit clock 4
2682 * 0b0101..bit clock 5
2683 * 0b0110..bit clock 6
2684 * 0b0111..bit clock 7
2685 * 0b1000..bit clock 8
2686 * 0b1001..bit clock 9
2687 * 0b1010..bit clock A
2688 * 0b1011..bit clock B
2689 * 0b1100..bit clock C
2690 * 0b1101..bit clock D
2691 * 0b1110..bit clock E
2692 * 0b1111..clock disabled, connected to zero
2693 */
2694#define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
2695#define ASRC_ASRCSR_AICSB_MASK (0xF0U)
2696#define ASRC_ASRCSR_AICSB_SHIFT (4U)
2697/*! AICSB - AICSB
2698 * 0b0000..bit clock 0
2699 * 0b0001..bit clock 1
2700 * 0b0010..bit clock 2
2701 * 0b0011..bit clock 3
2702 * 0b0100..bit clock 4
2703 * 0b0101..bit clock 5
2704 * 0b0110..bit clock 6
2705 * 0b0111..bit clock 7
2706 * 0b1000..bit clock 8
2707 * 0b1001..bit clock 9
2708 * 0b1010..bit clock A
2709 * 0b1011..bit clock B
2710 * 0b1100..bit clock C
2711 * 0b1101..bit clock D
2712 * 0b1110..bit clock E
2713 * 0b1111..clock disabled, connected to zero
2714 */
2715#define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
2716#define ASRC_ASRCSR_AICSC_MASK (0xF00U)
2717#define ASRC_ASRCSR_AICSC_SHIFT (8U)
2718/*! AICSC - AICSC
2719 * 0b0000..bit clock 0
2720 * 0b0001..bit clock 1
2721 * 0b0010..bit clock 2
2722 * 0b0011..bit clock 3
2723 * 0b0100..bit clock 4
2724 * 0b0101..bit clock 5
2725 * 0b0110..bit clock 6
2726 * 0b0111..bit clock 7
2727 * 0b1000..bit clock 8
2728 * 0b1001..bit clock 9
2729 * 0b1010..bit clock A
2730 * 0b1011..bit clock B
2731 * 0b1100..bit clock C
2732 * 0b1101..bit clock D
2733 * 0b1110..bit clock E
2734 * 0b1111..clock disabled, connected to zero
2735 */
2736#define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
2737#define ASRC_ASRCSR_AOCSA_MASK (0xF000U)
2738#define ASRC_ASRCSR_AOCSA_SHIFT (12U)
2739/*! AOCSA - AOCSA
2740 * 0b0000..bit clock 0
2741 * 0b0001..bit clock 1
2742 * 0b0010..bit clock 2
2743 * 0b0011..bit clock 3
2744 * 0b0100..bit clock 4
2745 * 0b0101..bit clock 5
2746 * 0b0110..bit clock 6
2747 * 0b0111..bit clock 7
2748 * 0b1000..bit clock 8
2749 * 0b1001..bit clock 9
2750 * 0b1010..bit clock A
2751 * 0b1011..bit clock B
2752 * 0b1100..bit clock C
2753 * 0b1101..bit clock D
2754 * 0b1110..bit clock E
2755 * 0b1111..clock disabled, connected to zero
2756 */
2757#define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
2758#define ASRC_ASRCSR_AOCSB_MASK (0xF0000U)
2759#define ASRC_ASRCSR_AOCSB_SHIFT (16U)
2760/*! AOCSB - AOCSB
2761 * 0b0000..bit clock 0
2762 * 0b0001..bit clock 1
2763 * 0b0010..bit clock 2
2764 * 0b0011..bit clock 3
2765 * 0b0100..bit clock 4
2766 * 0b0101..bit clock 5
2767 * 0b0110..bit clock 6
2768 * 0b0111..bit clock 7
2769 * 0b1000..bit clock 8
2770 * 0b1001..bit clock 9
2771 * 0b1010..bit clock A
2772 * 0b1011..bit clock B
2773 * 0b1100..bit clock C
2774 * 0b1101..bit clock D
2775 * 0b1110..bit clock E
2776 * 0b1111..clock disabled, connected to zero
2777 */
2778#define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
2779#define ASRC_ASRCSR_AOCSC_MASK (0xF00000U)
2780#define ASRC_ASRCSR_AOCSC_SHIFT (20U)
2781/*! AOCSC - AOCSC
2782 * 0b0000..bit clock 0
2783 * 0b0001..bit clock 1
2784 * 0b0010..bit clock 2
2785 * 0b0011..bit clock 3
2786 * 0b0100..bit clock 4
2787 * 0b0101..bit clock 5
2788 * 0b0110..bit clock 6
2789 * 0b0111..bit clock 7
2790 * 0b1000..bit clock 8
2791 * 0b1001..bit clock 9
2792 * 0b1010..bit clock A
2793 * 0b1011..bit clock B
2794 * 0b1100..bit clock C
2795 * 0b1101..bit clock D
2796 * 0b1110..bit clock E
2797 * 0b1111..clock disabled, connected to zero
2798 */
2799#define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
2800/*! @} */
2801
2802/*! @name ASRCDR1 - ASRC Clock Divider Register 1 */
2803/*! @{ */
2804#define ASRC_ASRCDR1_AICPA_MASK (0x7U)
2805#define ASRC_ASRCDR1_AICPA_SHIFT (0U)
2806/*! AICPA - AICPA
2807 */
2808#define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
2809#define ASRC_ASRCDR1_AICDA_MASK (0x38U)
2810#define ASRC_ASRCDR1_AICDA_SHIFT (3U)
2811/*! AICDA - AICDA
2812 */
2813#define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
2814#define ASRC_ASRCDR1_AICPB_MASK (0x1C0U)
2815#define ASRC_ASRCDR1_AICPB_SHIFT (6U)
2816/*! AICPB - AICPB
2817 */
2818#define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
2819#define ASRC_ASRCDR1_AICDB_MASK (0xE00U)
2820#define ASRC_ASRCDR1_AICDB_SHIFT (9U)
2821/*! AICDB - AICDB
2822 */
2823#define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
2824#define ASRC_ASRCDR1_AOCPA_MASK (0x7000U)
2825#define ASRC_ASRCDR1_AOCPA_SHIFT (12U)
2826/*! AOCPA - AOCPA
2827 */
2828#define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
2829#define ASRC_ASRCDR1_AOCDA_MASK (0x38000U)
2830#define ASRC_ASRCDR1_AOCDA_SHIFT (15U)
2831/*! AOCDA - AOCDA
2832 */
2833#define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
2834#define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U)
2835#define ASRC_ASRCDR1_AOCPB_SHIFT (18U)
2836/*! AOCPB - AOCPB
2837 */
2838#define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
2839#define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U)
2840#define ASRC_ASRCDR1_AOCDB_SHIFT (21U)
2841/*! AOCDB - AOCDB
2842 */
2843#define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
2844/*! @} */
2845
2846/*! @name ASRCDR2 - ASRC Clock Divider Register 2 */
2847/*! @{ */
2848#define ASRC_ASRCDR2_AICPC_MASK (0x7U)
2849#define ASRC_ASRCDR2_AICPC_SHIFT (0U)
2850/*! AICPC - AICPC
2851 */
2852#define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
2853#define ASRC_ASRCDR2_AICDC_MASK (0x38U)
2854#define ASRC_ASRCDR2_AICDC_SHIFT (3U)
2855/*! AICDC - AICDC
2856 */
2857#define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
2858#define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U)
2859#define ASRC_ASRCDR2_AOCPC_SHIFT (6U)
2860/*! AOCPC - AOCPC
2861 */
2862#define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
2863#define ASRC_ASRCDR2_AOCDC_MASK (0xE00U)
2864#define ASRC_ASRCDR2_AOCDC_SHIFT (9U)
2865/*! AOCDC - AOCDC
2866 */
2867#define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
2868/*! @} */
2869
2870/*! @name ASRSTR - ASRC Status Register */
2871/*! @{ */
2872#define ASRC_ASRSTR_AIDEA_MASK (0x1U)
2873#define ASRC_ASRSTR_AIDEA_SHIFT (0U)
2874/*! AIDEA - AIDEA
2875 */
2876#define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
2877#define ASRC_ASRSTR_AIDEB_MASK (0x2U)
2878#define ASRC_ASRSTR_AIDEB_SHIFT (1U)
2879/*! AIDEB - AIDEB
2880 */
2881#define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
2882#define ASRC_ASRSTR_AIDEC_MASK (0x4U)
2883#define ASRC_ASRSTR_AIDEC_SHIFT (2U)
2884/*! AIDEC - AIDEC
2885 */
2886#define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
2887#define ASRC_ASRSTR_AODFA_MASK (0x8U)
2888#define ASRC_ASRSTR_AODFA_SHIFT (3U)
2889/*! AODFA - AODFA
2890 */
2891#define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
2892#define ASRC_ASRSTR_AODFB_MASK (0x10U)
2893#define ASRC_ASRSTR_AODFB_SHIFT (4U)
2894/*! AODFB - AODFB
2895 */
2896#define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
2897#define ASRC_ASRSTR_AODFC_MASK (0x20U)
2898#define ASRC_ASRSTR_AODFC_SHIFT (5U)
2899/*! AODFC - AODFC
2900 */
2901#define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
2902#define ASRC_ASRSTR_AOLE_MASK (0x40U)
2903#define ASRC_ASRSTR_AOLE_SHIFT (6U)
2904/*! AOLE - AOLE
2905 */
2906#define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
2907#define ASRC_ASRSTR_FPWT_MASK (0x80U)
2908#define ASRC_ASRSTR_FPWT_SHIFT (7U)
2909/*! FPWT - FPWT
2910 */
2911#define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
2912#define ASRC_ASRSTR_AIDUA_MASK (0x100U)
2913#define ASRC_ASRSTR_AIDUA_SHIFT (8U)
2914/*! AIDUA - AIDUA
2915 */
2916#define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
2917#define ASRC_ASRSTR_AIDUB_MASK (0x200U)
2918#define ASRC_ASRSTR_AIDUB_SHIFT (9U)
2919/*! AIDUB - AIDUB
2920 */
2921#define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
2922#define ASRC_ASRSTR_AIDUC_MASK (0x400U)
2923#define ASRC_ASRSTR_AIDUC_SHIFT (10U)
2924/*! AIDUC - AIDUC
2925 */
2926#define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
2927#define ASRC_ASRSTR_AODOA_MASK (0x800U)
2928#define ASRC_ASRSTR_AODOA_SHIFT (11U)
2929/*! AODOA - AODOA
2930 */
2931#define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
2932#define ASRC_ASRSTR_AODOB_MASK (0x1000U)
2933#define ASRC_ASRSTR_AODOB_SHIFT (12U)
2934/*! AODOB - AODOB
2935 */
2936#define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
2937#define ASRC_ASRSTR_AODOC_MASK (0x2000U)
2938#define ASRC_ASRSTR_AODOC_SHIFT (13U)
2939/*! AODOC - AODOC
2940 */
2941#define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
2942#define ASRC_ASRSTR_AIOLA_MASK (0x4000U)
2943#define ASRC_ASRSTR_AIOLA_SHIFT (14U)
2944/*! AIOLA - AIOLA
2945 */
2946#define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
2947#define ASRC_ASRSTR_AIOLB_MASK (0x8000U)
2948#define ASRC_ASRSTR_AIOLB_SHIFT (15U)
2949/*! AIOLB - AIOLB
2950 */
2951#define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
2952#define ASRC_ASRSTR_AIOLC_MASK (0x10000U)
2953#define ASRC_ASRSTR_AIOLC_SHIFT (16U)
2954/*! AIOLC - AIOLC
2955 */
2956#define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
2957#define ASRC_ASRSTR_AOOLA_MASK (0x20000U)
2958#define ASRC_ASRSTR_AOOLA_SHIFT (17U)
2959/*! AOOLA - AOOLA
2960 */
2961#define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
2962#define ASRC_ASRSTR_AOOLB_MASK (0x40000U)
2963#define ASRC_ASRSTR_AOOLB_SHIFT (18U)
2964/*! AOOLB - AOOLB
2965 */
2966#define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
2967#define ASRC_ASRSTR_AOOLC_MASK (0x80000U)
2968#define ASRC_ASRSTR_AOOLC_SHIFT (19U)
2969/*! AOOLC - AOOLC
2970 */
2971#define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
2972#define ASRC_ASRSTR_ATQOL_MASK (0x100000U)
2973#define ASRC_ASRSTR_ATQOL_SHIFT (20U)
2974/*! ATQOL - ATQOL
2975 */
2976#define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
2977#define ASRC_ASRSTR_DSLCNT_MASK (0x200000U)
2978#define ASRC_ASRSTR_DSLCNT_SHIFT (21U)
2979/*! DSLCNT - DSLCNT
2980 */
2981#define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
2982/*! @} */
2983
2984/*! @name ASRPM - ASRC Parameter Register n */
2985/*! @{ */
2986#define ASRC_ASRPM_PARAMETER_VALUE_MASK (0xFFFFFFU)
2987#define ASRC_ASRPM_PARAMETER_VALUE_SHIFT (0U)
2988/*! PARAMETER_VALUE - PARAMETER_VALUE
2989 */
2990#define ASRC_ASRPM_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
2991/*! @} */
2992
2993/* The count of ASRC_ASRPM */
2994#define ASRC_ASRPM_COUNT (5U)
2995
2996/*! @name ASRTFR1 - ASRC ASRC Task Queue FIFO Register 1 */
2997/*! @{ */
2998#define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U)
2999#define ASRC_ASRTFR1_TF_BASE_SHIFT (6U)
3000/*! TF_BASE - TF_BASE
3001 */
3002#define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
3003#define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U)
3004#define ASRC_ASRTFR1_TF_FILL_SHIFT (13U)
3005/*! TF_FILL - TF_FILL
3006 */
3007#define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
3008/*! @} */
3009
3010/*! @name ASRCCR - ASRC Channel Counter Register */
3011/*! @{ */
3012#define ASRC_ASRCCR_ACIA_MASK (0xFU)
3013#define ASRC_ASRCCR_ACIA_SHIFT (0U)
3014/*! ACIA - ACIA
3015 */
3016#define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
3017#define ASRC_ASRCCR_ACIB_MASK (0xF0U)
3018#define ASRC_ASRCCR_ACIB_SHIFT (4U)
3019/*! ACIB - ACIB
3020 */
3021#define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
3022#define ASRC_ASRCCR_ACIC_MASK (0xF00U)
3023#define ASRC_ASRCCR_ACIC_SHIFT (8U)
3024/*! ACIC - ACIC
3025 */
3026#define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
3027#define ASRC_ASRCCR_ACOA_MASK (0xF000U)
3028#define ASRC_ASRCCR_ACOA_SHIFT (12U)
3029/*! ACOA - ACOA
3030 */
3031#define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
3032#define ASRC_ASRCCR_ACOB_MASK (0xF0000U)
3033#define ASRC_ASRCCR_ACOB_SHIFT (16U)
3034/*! ACOB - ACOB
3035 */
3036#define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
3037#define ASRC_ASRCCR_ACOC_MASK (0xF00000U)
3038#define ASRC_ASRCCR_ACOC_SHIFT (20U)
3039/*! ACOC - ACOC
3040 */
3041#define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
3042/*! @} */
3043
3044/*! @name ASRDIA - ASRC Data Input Register for Pair x */
3045/*! @{ */
3046#define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU)
3047#define ASRC_ASRDIA_DATA_SHIFT (0U)
3048/*! DATA - DATA
3049 */
3050#define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
3051/*! @} */
3052
3053/*! @name ASRDOA - ASRC Data Output Register for Pair x */
3054/*! @{ */
3055#define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU)
3056#define ASRC_ASRDOA_DATA_SHIFT (0U)
3057/*! DATA - DATA
3058 */
3059#define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
3060/*! @} */
3061
3062/*! @name ASRDIB - ASRC Data Input Register for Pair x */
3063/*! @{ */
3064#define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU)
3065#define ASRC_ASRDIB_DATA_SHIFT (0U)
3066/*! DATA - DATA
3067 */
3068#define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
3069/*! @} */
3070
3071/*! @name ASRDOB - ASRC Data Output Register for Pair x */
3072/*! @{ */
3073#define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU)
3074#define ASRC_ASRDOB_DATA_SHIFT (0U)
3075/*! DATA - DATA
3076 */
3077#define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
3078/*! @} */
3079
3080/*! @name ASRDIC - ASRC Data Input Register for Pair x */
3081/*! @{ */
3082#define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU)
3083#define ASRC_ASRDIC_DATA_SHIFT (0U)
3084/*! DATA - DATA
3085 */
3086#define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
3087/*! @} */
3088
3089/*! @name ASRDOC - ASRC Data Output Register for Pair x */
3090/*! @{ */
3091#define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU)
3092#define ASRC_ASRDOC_DATA_SHIFT (0U)
3093/*! DATA - DATA
3094 */
3095#define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
3096/*! @} */
3097
3098/*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */
3099/*! @{ */
3100#define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU)
3101#define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U)
3102/*! IDRATIOA_H - IDRATIOA_H
3103 */
3104#define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
3105/*! @} */
3106
3107/*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */
3108/*! @{ */
3109#define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU)
3110#define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U)
3111/*! IDRATIOA_L - IDRATIOA_L
3112 */
3113#define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
3114/*! @} */
3115
3116/*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */
3117/*! @{ */
3118#define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU)
3119#define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U)
3120/*! IDRATIOB_H - IDRATIOB_H
3121 */
3122#define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
3123/*! @} */
3124
3125/*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */
3126/*! @{ */
3127#define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU)
3128#define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U)
3129/*! IDRATIOB_L - IDRATIOB_L
3130 */
3131#define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
3132/*! @} */
3133
3134/*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */
3135/*! @{ */
3136#define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU)
3137#define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U)
3138/*! IDRATIOC_H - IDRATIOC_H
3139 */
3140#define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
3141/*! @} */
3142
3143/*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */
3144/*! @{ */
3145#define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU)
3146#define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U)
3147/*! IDRATIOC_L - IDRATIOC_L
3148 */
3149#define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
3150/*! @} */
3151
3152/*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */
3153/*! @{ */
3154#define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU)
3155#define ASRC_ASR76K_ASR76K_SHIFT (0U)
3156/*! ASR76K - ASR76K
3157 */
3158#define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
3159/*! @} */
3160
3161/*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */
3162/*! @{ */
3163#define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU)
3164#define ASRC_ASR56K_ASR56K_SHIFT (0U)
3165/*! ASR56K - ASR56K
3166 */
3167#define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
3168/*! @} */
3169
3170/*! @name ASRMCRA - ASRC Misc Control Register for Pair A */
3171/*! @{ */
3172#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU)
3173#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U)
3174/*! INFIFO_THRESHOLDA - INFIFO_THRESHOLDA
3175 */
3176#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
3177#define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U)
3178#define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U)
3179/*! RSYNOFA - RSYNOFA
3180 */
3181#define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
3182#define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U)
3183#define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U)
3184/*! RSYNIFA - RSYNIFA
3185 */
3186#define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
3187#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U)
3188#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U)
3189/*! OUTFIFO_THRESHOLDA - OUTFIFO_THRESHOLDA
3190 */
3191#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
3192#define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U)
3193#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U)
3194/*! BYPASSPOLYA - BYPASSPOLYA
3195 * 0b1..Bypass polyphase filtering.
3196 * 0b0..Don't bypass polyphase filtering.
3197 */
3198#define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
3199#define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U)
3200#define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U)
3201/*! BUFSTALLA - BUFSTALLA
3202 * 0b1..Stall Pair A conversion in case of near empty/full FIFO conditions.
3203 * 0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
3204 */
3205#define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
3206#define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U)
3207#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U)
3208/*! EXTTHRSHA - EXTTHRSHA
3209 * 0b1..Use external defined thresholds.
3210 * 0b0..Use default thresholds.
3211 */
3212#define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
3213#define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U)
3214#define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U)
3215/*! ZEROBUFA - ZEROBUFA
3216 * 0b1..Don't zeroize the buffer
3217 * 0b0..Zeroize the buffer
3218 */
3219#define ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
3220/*! @} */
3221
3222/*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */
3223/*! @{ */
3224#define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU)
3225#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U)
3226/*! INFIFO_FILLA - INFIFO_FILLA
3227 */
3228#define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
3229#define ASRC_ASRFSTA_IAEA_MASK (0x800U)
3230#define ASRC_ASRFSTA_IAEA_SHIFT (11U)
3231/*! IAEA - IAEA
3232 */
3233#define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
3234#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U)
3235#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U)
3236/*! OUTFIFO_FILLA - OUTFIFO_FILLA
3237 */
3238#define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
3239#define ASRC_ASRFSTA_OAFA_MASK (0x800000U)
3240#define ASRC_ASRFSTA_OAFA_SHIFT (23U)
3241/*! OAFA - OAFA
3242 */
3243#define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
3244/*! @} */
3245
3246/*! @name ASRMCRB - ASRC Misc Control Register for Pair B */
3247/*! @{ */
3248#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU)
3249#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U)
3250/*! INFIFO_THRESHOLDB - INFIFO_THRESHOLDB
3251 */
3252#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
3253#define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U)
3254#define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U)
3255/*! RSYNOFB - RSYNOFB
3256 */
3257#define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
3258#define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U)
3259#define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U)
3260/*! RSYNIFB - RSYNIFB
3261 */
3262#define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
3263#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U)
3264#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U)
3265/*! OUTFIFO_THRESHOLDB - OUTFIFO_THRESHOLDB
3266 */
3267#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
3268#define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U)
3269#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U)
3270/*! BYPASSPOLYB - BYPASSPOLYB
3271 * 0b1..Bypass polyphase filtering.
3272 * 0b0..Don't bypass polyphase filtering.
3273 */
3274#define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
3275#define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U)
3276#define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U)
3277/*! BUFSTALLB - BUFSTALLB
3278 * 0b1..Stall Pair B conversion in case of near empty/full FIFO conditions.
3279 * 0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
3280 */
3281#define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
3282#define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U)
3283#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U)
3284/*! EXTTHRSHB - EXTTHRSHB
3285 * 0b1..Use external defined thresholds.
3286 * 0b0..Use default thresholds.
3287 */
3288#define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
3289#define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U)
3290#define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U)
3291/*! ZEROBUFB - ZEROBUFB
3292 * 0b1..Don't zeroize the buffer
3293 * 0b0..Zeroize the buffer
3294 */
3295#define ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
3296/*! @} */
3297
3298/*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */
3299/*! @{ */
3300#define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU)
3301#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U)
3302/*! INFIFO_FILLB - INFIFO_FILLB
3303 */
3304#define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
3305#define ASRC_ASRFSTB_IAEB_MASK (0x800U)
3306#define ASRC_ASRFSTB_IAEB_SHIFT (11U)
3307/*! IAEB - IAEB
3308 */
3309#define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
3310#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U)
3311#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U)
3312/*! OUTFIFO_FILLB - OUTFIFO_FILLB
3313 */
3314#define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
3315#define ASRC_ASRFSTB_OAFB_MASK (0x800000U)
3316#define ASRC_ASRFSTB_OAFB_SHIFT (23U)
3317/*! OAFB - OAFB
3318 */
3319#define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
3320/*! @} */
3321
3322/*! @name ASRMCRC - ASRC Misc Control Register for Pair C */
3323/*! @{ */
3324#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU)
3325#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U)
3326/*! INFIFO_THRESHOLDC - INFIFO_THRESHOLDC
3327 */
3328#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
3329#define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U)
3330#define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U)
3331/*! RSYNOFC - RSYNOFC
3332 */
3333#define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
3334#define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U)
3335#define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U)
3336/*! RSYNIFC - RSYNIFC
3337 */
3338#define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
3339#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U)
3340#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U)
3341/*! OUTFIFO_THRESHOLDC - OUTFIFO_THRESHOLDC
3342 */
3343#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
3344#define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U)
3345#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U)
3346/*! BYPASSPOLYC - BYPASSPOLYC
3347 * 0b1..Bypass polyphase filtering.
3348 * 0b0..Don't bypass polyphase filtering.
3349 */
3350#define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
3351#define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U)
3352#define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U)
3353/*! BUFSTALLC - BUFSTALLC
3354 * 0b1..Stall Pair C conversion in case of near empty/full FIFO conditions.
3355 * 0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
3356 */
3357#define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
3358#define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U)
3359#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U)
3360/*! EXTTHRSHC - EXTTHRSHC
3361 * 0b1..Use external defined thresholds.
3362 * 0b0..Use default thresholds.
3363 */
3364#define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
3365#define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U)
3366#define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U)
3367/*! ZEROBUFC - ZEROBUFC
3368 * 0b1..Don't zeroize the buffer
3369 * 0b0..Zeroize the buffer
3370 */
3371#define ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
3372/*! @} */
3373
3374/*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */
3375/*! @{ */
3376#define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU)
3377#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U)
3378/*! INFIFO_FILLC - INFIFO_FILLC
3379 */
3380#define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
3381#define ASRC_ASRFSTC_IAEC_MASK (0x800U)
3382#define ASRC_ASRFSTC_IAEC_SHIFT (11U)
3383/*! IAEC - IAEC
3384 */
3385#define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
3386#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U)
3387#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U)
3388/*! OUTFIFO_FILLC - OUTFIFO_FILLC
3389 */
3390#define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
3391#define ASRC_ASRFSTC_OAFC_MASK (0x800000U)
3392#define ASRC_ASRFSTC_OAFC_SHIFT (23U)
3393/*! OAFC - OAFC
3394 */
3395#define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
3396/*! @} */
3397
3398/*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */
3399/*! @{ */
3400#define ASRC_ASRMCR1_OW16_MASK (0x1U)
3401#define ASRC_ASRMCR1_OW16_SHIFT (0U)
3402/*! OW16 - OW16
3403 * 0b1..16-bit output data
3404 * 0b0..24-bit output data.
3405 */
3406#define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
3407#define ASRC_ASRMCR1_OSGN_MASK (0x2U)
3408#define ASRC_ASRMCR1_OSGN_SHIFT (1U)
3409/*! OSGN - OSGN
3410 * 0b1..Sign extension.
3411 * 0b0..No sign extension.
3412 */
3413#define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
3414#define ASRC_ASRMCR1_OMSB_MASK (0x4U)
3415#define ASRC_ASRMCR1_OMSB_SHIFT (2U)
3416/*! OMSB - OMSB
3417 * 0b1..MSB aligned.
3418 * 0b0..LSB aligned.
3419 */
3420#define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
3421#define ASRC_ASRMCR1_IMSB_MASK (0x100U)
3422#define ASRC_ASRMCR1_IMSB_SHIFT (8U)
3423/*! IMSB - IMSB
3424 * 0b1..MSB aligned.
3425 * 0b0..LSB aligned.
3426 */
3427#define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
3428#define ASRC_ASRMCR1_IWD_MASK (0xE00U)
3429#define ASRC_ASRMCR1_IWD_SHIFT (9U)
3430/*! IWD - IWD
3431 */
3432#define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
3433/*! @} */
3434
3435/* The count of ASRC_ASRMCR1 */
3436#define ASRC_ASRMCR1_COUNT (3U)
3437
3438
3439/*!
3440 * @}
3441 */ /* end of group ASRC_Register_Masks */
3442
3443
3444/* ASRC - Peripheral instance base addresses */
3445/** Peripheral ADMA__ASRC0 base address */
3446#define ADMA__ASRC0_BASE (0x59000000u)
3447/** Peripheral ADMA__ASRC0 base pointer */
3448#define ADMA__ASRC0 ((ASRC_Type *)ADMA__ASRC0_BASE)
3449/** Peripheral ADMA__ASRC1 base address */
3450#define ADMA__ASRC1_BASE (0x59800000u)
3451/** Peripheral ADMA__ASRC1 base pointer */
3452#define ADMA__ASRC1 ((ASRC_Type *)ADMA__ASRC1_BASE)
3453/** Array initializer of ASRC peripheral base addresses */
3454#define ASRC_BASE_ADDRS { ADMA__ASRC0_BASE, ADMA__ASRC1_BASE }
3455/** Array initializer of ASRC peripheral base pointers */
3456#define ASRC_BASE_PTRS { ADMA__ASRC0, ADMA__ASRC1 }
3457
3458/*!
3459 * @}
3460 */ /* end of group ASRC_Peripheral_Access_Layer */
3461
3462
3463/* ----------------------------------------------------------------------------
3464 -- BCH Peripheral Access Layer
3465 ---------------------------------------------------------------------------- */
3466
3467/*!
3468 * @addtogroup BCH_Peripheral_Access_Layer BCH Peripheral Access Layer
3469 * @{
3470 */
3471
3472/** BCH - Register Layout Typedef */
3473typedef struct {
3474 struct { /* offset: 0x0 */
3475 __IO uint32_t RW; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x0 */
3476 __IO uint32_t SET; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x4 */
3477 __IO uint32_t CLR; /**< Hardware BCH ECC Accelerator Control Register, offset: 0x8 */
3478 __IO uint32_t TOG; /**< Hardware BCH ECC Accelerator Control Register, offset: 0xC */
3479 } CTRL;
3480 struct { /* offset: 0x10 */
3481 __I uint32_t RW; /**< Hardware ECC Accelerator Status Register 0, offset: 0x10 */
3482 __I uint32_t SET; /**< Hardware ECC Accelerator Status Register 0, offset: 0x14 */
3483 __I uint32_t CLR; /**< Hardware ECC Accelerator Status Register 0, offset: 0x18 */
3484 __I uint32_t TOG; /**< Hardware ECC Accelerator Status Register 0, offset: 0x1C */
3485 } STATUS0;
3486 struct { /* offset: 0x20 */
3487 __IO uint32_t RW; /**< Hardware ECC Accelerator Mode Register, offset: 0x20 */
3488 __IO uint32_t SET; /**< Hardware ECC Accelerator Mode Register, offset: 0x24 */
3489 __IO uint32_t CLR; /**< Hardware ECC Accelerator Mode Register, offset: 0x28 */
3490 __IO uint32_t TOG; /**< Hardware ECC Accelerator Mode Register, offset: 0x2C */
3491 } MODE;
3492 struct { /* offset: 0x30 */
3493 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x30 */
3494 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x34 */
3495 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x38 */
3496 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Encode Buffer Register, offset: 0x3C */
3497 } ENCODEPTR;
3498 struct { /* offset: 0x40 */
3499 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x40 */
3500 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x44 */
3501 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x48 */
3502 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Data Buffer Register, offset: 0x4C */
3503 } DATAPTR;
3504 struct { /* offset: 0x50 */
3505 __IO uint32_t RW; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x50 */
3506 __IO uint32_t SET; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x54 */
3507 __IO uint32_t CLR; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x58 */
3508 __IO uint32_t TOG; /**< Hardware BCH ECC Loopback Metadata Buffer Register, offset: 0x5C */
3509 } METAPTR;
3510 uint8_t RESERVED_0[16];
3511 struct { /* offset: 0x70 */
3512 __IO uint32_t RW; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x70 */
3513 __IO uint32_t SET; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x74 */
3514 __IO uint32_t CLR; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x78 */
3515 __IO uint32_t TOG; /**< Hardware ECC Accelerator Layout Select Register, offset: 0x7C */
3516 } LAYOUTSELECT;
3517 struct { /* offset: 0x80 */
3518 __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x80 */
3519 __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x84 */
3520 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x88 */
3521 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 0 Register, offset: 0x8C */
3522 } FLASH0LAYOUT0;
3523 struct { /* offset: 0x90 */
3524 __IO uint32_t RW; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x90 */
3525 __IO uint32_t SET; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x94 */
3526 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x98 */
3527 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 0 Layout 1 Register, offset: 0x9C */
3528 } FLASH0LAYOUT1;
3529 struct { /* offset: 0xA0 */
3530 __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA0 */
3531 __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA4 */
3532 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xA8 */
3533 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 0 Register, offset: 0xAC */
3534 } FLASH1LAYOUT0;
3535 struct { /* offset: 0xB0 */
3536 __IO uint32_t RW; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB0 */
3537 __IO uint32_t SET; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB4 */
3538 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xB8 */
3539 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 1 Layout 1 Register, offset: 0xBC */
3540 } FLASH1LAYOUT1;
3541 struct { /* offset: 0xC0 */
3542 __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC0 */
3543 __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC4 */
3544 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xC8 */
3545 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 0 Register, offset: 0xCC */
3546 } FLASH2LAYOUT0;
3547 struct { /* offset: 0xD0 */
3548 __IO uint32_t RW; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD0 */
3549 __IO uint32_t SET; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD4 */
3550 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xD8 */
3551 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 2 Layout 1 Register, offset: 0xDC */
3552 } FLASH2LAYOUT1;
3553 struct { /* offset: 0xE0 */
3554 __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE0 */
3555 __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE4 */
3556 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xE8 */
3557 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 0 Register, offset: 0xEC */
3558 } FLASH3LAYOUT0;
3559 struct { /* offset: 0xF0 */
3560 __IO uint32_t RW; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF0 */
3561 __IO uint32_t SET; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF4 */
3562 __IO uint32_t CLR; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xF8 */
3563 __IO uint32_t TOG; /**< Hardware BCH ECC Flash 3 Layout 1 Register, offset: 0xFC */
3564 } FLASH3LAYOUT1;
3565 struct { /* offset: 0x100 */
3566 __IO uint32_t RW; /**< Hardware BCH ECC Debug Register0, offset: 0x100 */
3567 __IO uint32_t SET; /**< Hardware BCH ECC Debug Register0, offset: 0x104 */
3568 __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register0, offset: 0x108 */
3569 __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register0, offset: 0x10C */
3570 } DEBUG0;
3571 struct { /* offset: 0x110 */
3572 __I uint32_t RW; /**< KES Debug Read Register, offset: 0x110 */
3573 __I uint32_t SET; /**< KES Debug Read Register, offset: 0x114 */
3574 __I uint32_t CLR; /**< KES Debug Read Register, offset: 0x118 */
3575 __I uint32_t TOG; /**< KES Debug Read Register, offset: 0x11C */
3576 } DBGKESREAD;
3577 struct { /* offset: 0x120 */
3578 __I uint32_t RW; /**< Chien Search Debug Read Register, offset: 0x120 */
3579 __I uint32_t SET; /**< Chien Search Debug Read Register, offset: 0x124 */
3580 __I uint32_t CLR; /**< Chien Search Debug Read Register, offset: 0x128 */
3581 __I uint32_t TOG; /**< Chien Search Debug Read Register, offset: 0x12C */
3582 } DBGCSFEREAD;
3583 struct { /* offset: 0x130 */
3584 __I uint32_t RW; /**< Syndrome Generator Debug Read Register, offset: 0x130 */
3585 __I uint32_t SET; /**< Syndrome Generator Debug Read Register, offset: 0x134 */
3586 __I uint32_t CLR; /**< Syndrome Generator Debug Read Register, offset: 0x138 */
3587 __I uint32_t TOG; /**< Syndrome Generator Debug Read Register, offset: 0x13C */
3588 } DBGSYNDGENREAD;
3589 struct { /* offset: 0x140 */
3590 __I uint32_t RW; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x140 */
3591 __I uint32_t SET; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x144 */
3592 __I uint32_t CLR; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x148 */
3593 __I uint32_t TOG; /**< Bus Master and ECC Controller Debug Read Register, offset: 0x14C */
3594 } DBGAHBMREAD;
3595 struct { /* offset: 0x150 */
3596 __I uint32_t RW; /**< Block Name Register, offset: 0x150 */
3597 __I uint32_t SET; /**< Block Name Register, offset: 0x154 */
3598 __I uint32_t CLR; /**< Block Name Register, offset: 0x158 */
3599 __I uint32_t TOG; /**< Block Name Register, offset: 0x15C */
3600 } BLOCKNAME;
3601 struct { /* offset: 0x160 */
3602 __I uint32_t RW; /**< BCH Version Register, offset: 0x160 */
3603 __I uint32_t SET; /**< BCH Version Register, offset: 0x164 */
3604 __I uint32_t CLR; /**< BCH Version Register, offset: 0x168 */
3605 __I uint32_t TOG; /**< BCH Version Register, offset: 0x16C */
3606 } VERSION;
3607 struct { /* offset: 0x170 */
3608 __IO uint32_t RW; /**< Hardware BCH ECC Debug Register 1, offset: 0x170 */
3609 __IO uint32_t SET; /**< Hardware BCH ECC Debug Register 1, offset: 0x174 */
3610 __IO uint32_t CLR; /**< Hardware BCH ECC Debug Register 1, offset: 0x178 */
3611 __IO uint32_t TOG; /**< Hardware BCH ECC Debug Register 1, offset: 0x17C */
3612 } DEBUG1;
3613} BCH_Type;
3614
3615/* ----------------------------------------------------------------------------
3616 -- BCH Register Masks
3617 ---------------------------------------------------------------------------- */
3618
3619/*!
3620 * @addtogroup BCH_Register_Masks BCH Register Masks
3621 * @{
3622 */
3623
3624/*! @name CTRL - Hardware BCH ECC Accelerator Control Register */
3625/*! @{ */
3626#define BCH_CTRL_COMPLETE_IRQ_MASK (0x1U)
3627#define BCH_CTRL_COMPLETE_IRQ_SHIFT (0U)
3628/*! COMPLETE_IRQ - COMPLETE_IRQ
3629 */
3630#define BCH_CTRL_COMPLETE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_MASK)
3631#define BCH_CTRL_RSVD0_MASK (0x2U)
3632#define BCH_CTRL_RSVD0_SHIFT (1U)
3633/*! RSVD0 - This field is reserved.
3634 */
3635#define BCH_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD0_SHIFT)) & BCH_CTRL_RSVD0_MASK)
3636#define BCH_CTRL_DEBUG_STALL_IRQ_MASK (0x4U)
3637#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT (2U)
3638/*! DEBUG_STALL_IRQ - DEBUG_STALL_IRQ
3639 */
3640#define BCH_CTRL_DEBUG_STALL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_MASK)
3641#define BCH_CTRL_BM_ERROR_IRQ_MASK (0x8U)
3642#define BCH_CTRL_BM_ERROR_IRQ_SHIFT (3U)
3643/*! BM_ERROR_IRQ - BM_ERROR_IRQ
3644 */
3645#define BCH_CTRL_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_BM_ERROR_IRQ_SHIFT)) & BCH_CTRL_BM_ERROR_IRQ_MASK)
3646#define BCH_CTRL_RSVD1_MASK (0xF0U)
3647#define BCH_CTRL_RSVD1_SHIFT (4U)
3648/*! RSVD1 - This field is reserved.
3649 */
3650#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD1_SHIFT)) & BCH_CTRL_RSVD1_MASK)
3651#define BCH_CTRL_COMPLETE_IRQ_EN_MASK (0x100U)
3652#define BCH_CTRL_COMPLETE_IRQ_EN_SHIFT (8U)
3653/*! COMPLETE_IRQ_EN - COMPLETE_IRQ_EN
3654 */
3655#define BCH_CTRL_COMPLETE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_COMPLETE_IRQ_EN_SHIFT)) & BCH_CTRL_COMPLETE_IRQ_EN_MASK)
3656#define BCH_CTRL_RSVD2_MASK (0x200U)
3657#define BCH_CTRL_RSVD2_SHIFT (9U)
3658/*! RSVD2 - This field is reserved.
3659 */
3660#define BCH_CTRL_RSVD2(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD2_SHIFT)) & BCH_CTRL_RSVD2_MASK)
3661#define BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK (0x400U)
3662#define BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT (10U)
3663/*! DEBUG_STALL_IRQ_EN - DEBUG_STALL_IRQ_EN
3664 */
3665#define BCH_CTRL_DEBUG_STALL_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUG_STALL_IRQ_EN_SHIFT)) & BCH_CTRL_DEBUG_STALL_IRQ_EN_MASK)
3666#define BCH_CTRL_RSVD3_MASK (0xF800U)
3667#define BCH_CTRL_RSVD3_SHIFT (11U)
3668/*! RSVD3 - This field is reserved.
3669 */
3670#define BCH_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD3_SHIFT)) & BCH_CTRL_RSVD3_MASK)
3671#define BCH_CTRL_M2M_ENABLE_MASK (0x10000U)
3672#define BCH_CTRL_M2M_ENABLE_SHIFT (16U)
3673/*! M2M_ENABLE - M2M_ENABLE
3674 */
3675#define BCH_CTRL_M2M_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENABLE_SHIFT)) & BCH_CTRL_M2M_ENABLE_MASK)
3676#define BCH_CTRL_M2M_ENCODE_MASK (0x20000U)
3677#define BCH_CTRL_M2M_ENCODE_SHIFT (17U)
3678/*! M2M_ENCODE - M2M_ENCODE
3679 */
3680#define BCH_CTRL_M2M_ENCODE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_ENCODE_SHIFT)) & BCH_CTRL_M2M_ENCODE_MASK)
3681#define BCH_CTRL_M2M_LAYOUT_MASK (0xC0000U)
3682#define BCH_CTRL_M2M_LAYOUT_SHIFT (18U)
3683/*! M2M_LAYOUT - M2M_LAYOUT
3684 */
3685#define BCH_CTRL_M2M_LAYOUT(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_M2M_LAYOUT_SHIFT)) & BCH_CTRL_M2M_LAYOUT_MASK)
3686#define BCH_CTRL_RSVD4_MASK (0x300000U)
3687#define BCH_CTRL_RSVD4_SHIFT (20U)
3688/*! RSVD4 - This field is reserved.
3689 */
3690#define BCH_CTRL_RSVD4(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD4_SHIFT)) & BCH_CTRL_RSVD4_MASK)
3691#define BCH_CTRL_DEBUGSYNDROME_MASK (0x400000U)
3692#define BCH_CTRL_DEBUGSYNDROME_SHIFT (22U)
3693/*! DEBUGSYNDROME - DEBUGSYNDROME
3694 */
3695#define BCH_CTRL_DEBUGSYNDROME(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_DEBUGSYNDROME_SHIFT)) & BCH_CTRL_DEBUGSYNDROME_MASK)
3696#define BCH_CTRL_RSVD5_MASK (0x3F800000U)
3697#define BCH_CTRL_RSVD5_SHIFT (23U)
3698/*! RSVD5 - This field is reserved.
3699 */
3700#define BCH_CTRL_RSVD5(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_RSVD5_SHIFT)) & BCH_CTRL_RSVD5_MASK)
3701#define BCH_CTRL_CLKGATE_MASK (0x40000000U)
3702#define BCH_CTRL_CLKGATE_SHIFT (30U)
3703/*! CLKGATE - CLKGATE
3704 * 0b0..Allow BCH to operate normally.
3705 * 0b1..Do not clock BCH gates in order to minimize power consumption.
3706 */
3707#define BCH_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_CLKGATE_SHIFT)) & BCH_CTRL_CLKGATE_MASK)
3708#define BCH_CTRL_SFTRST_MASK (0x80000000U)
3709#define BCH_CTRL_SFTRST_SHIFT (31U)
3710/*! SFTRST - SFTRST
3711 * 0b0..Allow BCH to operate normally.
3712 * 0b1..Hold BCH in reset.
3713 */
3714#define BCH_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << BCH_CTRL_SFTRST_SHIFT)) & BCH_CTRL_SFTRST_MASK)
3715/*! @} */
3716
3717/*! @name STATUS0 - Hardware ECC Accelerator Status Register 0 */
3718/*! @{ */
3719#define BCH_STATUS0_RSVD0_MASK (0x3U)
3720#define BCH_STATUS0_RSVD0_SHIFT (0U)
3721/*! RSVD0 - This field is reserved.
3722 */
3723#define BCH_STATUS0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD0_SHIFT)) & BCH_STATUS0_RSVD0_MASK)
3724#define BCH_STATUS0_UNCORRECTABLE_MASK (0x4U)
3725#define BCH_STATUS0_UNCORRECTABLE_SHIFT (2U)
3726/*! UNCORRECTABLE - UNCORRECTABLE
3727 */
3728#define BCH_STATUS0_UNCORRECTABLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_UNCORRECTABLE_SHIFT)) & BCH_STATUS0_UNCORRECTABLE_MASK)
3729#define BCH_STATUS0_CORRECTED_MASK (0x8U)
3730#define BCH_STATUS0_CORRECTED_SHIFT (3U)
3731/*! CORRECTED - CORRECTED
3732 */
3733#define BCH_STATUS0_CORRECTED(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_CORRECTED_SHIFT)) & BCH_STATUS0_CORRECTED_MASK)
3734#define BCH_STATUS0_ALLONES_MASK (0x10U)
3735#define BCH_STATUS0_ALLONES_SHIFT (4U)
3736/*! ALLONES - ALLONES
3737 */
3738#define BCH_STATUS0_ALLONES(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_ALLONES_SHIFT)) & BCH_STATUS0_ALLONES_MASK)
3739#define BCH_STATUS0_RSVD1_MASK (0xE0U)
3740#define BCH_STATUS0_RSVD1_SHIFT (5U)
3741/*! RSVD1 - This field is reserved.
3742 */
3743#define BCH_STATUS0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_RSVD1_SHIFT)) & BCH_STATUS0_RSVD1_MASK)
3744#define BCH_STATUS0_STATUS_BLK0_MASK (0xFF00U)
3745#define BCH_STATUS0_STATUS_BLK0_SHIFT (8U)
3746/*! STATUS_BLK0 - STATUS_BLK0
3747 * 0b00000000..No errors found on block.
3748 * 0b00000001..One error found on block.
3749 * 0b00000010..One errors found on block.
3750 * 0b00000011..One errors found on block.
3751 * 0b00000100..One errors found on block.
3752 * 0b11111110..Block exhibited uncorrectable errors.
3753 * 0b11111111..Page is erased.
3754 */
3755#define BCH_STATUS0_STATUS_BLK0(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_STATUS_BLK0_SHIFT)) & BCH_STATUS0_STATUS_BLK0_MASK)
3756#define BCH_STATUS0_COMPLETED_CE_MASK (0xF0000U)
3757#define BCH_STATUS0_COMPLETED_CE_SHIFT (16U)
3758/*! COMPLETED_CE - COMPLETED_CE
3759 */
3760#define BCH_STATUS0_COMPLETED_CE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_COMPLETED_CE_SHIFT)) & BCH_STATUS0_COMPLETED_CE_MASK)
3761#define BCH_STATUS0_HANDLE_MASK (0xFFF00000U)
3762#define BCH_STATUS0_HANDLE_SHIFT (20U)
3763/*! HANDLE - HANDLE
3764 */
3765#define BCH_STATUS0_HANDLE(x) (((uint32_t)(((uint32_t)(x)) << BCH_STATUS0_HANDLE_SHIFT)) & BCH_STATUS0_HANDLE_MASK)
3766/*! @} */
3767
3768/*! @name MODE - Hardware ECC Accelerator Mode Register */
3769/*! @{ */
3770#define BCH_MODE_ERASE_THRESHOLD_MASK (0xFFU)
3771#define BCH_MODE_ERASE_THRESHOLD_SHIFT (0U)
3772/*! ERASE_THRESHOLD - ERASE_THRESHOLD
3773 */
3774#define BCH_MODE_ERASE_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_ERASE_THRESHOLD_SHIFT)) & BCH_MODE_ERASE_THRESHOLD_MASK)
3775#define BCH_MODE_RSVD_MASK (0xFFFFFF00U)
3776#define BCH_MODE_RSVD_SHIFT (8U)
3777/*! RSVD - This field is reserved.
3778 */
3779#define BCH_MODE_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_MODE_RSVD_SHIFT)) & BCH_MODE_RSVD_MASK)
3780/*! @} */
3781
3782/*! @name ENCODEPTR - Hardware BCH ECC Loopback Encode Buffer Register */
3783/*! @{ */
3784#define BCH_ENCODEPTR_ADDR_MASK (0xFFFFFFFFU)
3785#define BCH_ENCODEPTR_ADDR_SHIFT (0U)
3786/*! ADDR - ADDR
3787 */
3788#define BCH_ENCODEPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_ENCODEPTR_ADDR_SHIFT)) & BCH_ENCODEPTR_ADDR_MASK)
3789/*! @} */
3790
3791/*! @name DATAPTR - Hardware BCH ECC Loopback Data Buffer Register */
3792/*! @{ */
3793#define BCH_DATAPTR_ADDR_MASK (0xFFFFFFFFU)
3794#define BCH_DATAPTR_ADDR_SHIFT (0U)
3795/*! ADDR - ADDR
3796 */
3797#define BCH_DATAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_DATAPTR_ADDR_SHIFT)) & BCH_DATAPTR_ADDR_MASK)
3798/*! @} */
3799
3800/*! @name METAPTR - Hardware BCH ECC Loopback Metadata Buffer Register */
3801/*! @{ */
3802#define BCH_METAPTR_ADDR_MASK (0xFFFFFFFFU)
3803#define BCH_METAPTR_ADDR_SHIFT (0U)
3804/*! ADDR - ADDR
3805 */
3806#define BCH_METAPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << BCH_METAPTR_ADDR_SHIFT)) & BCH_METAPTR_ADDR_MASK)
3807/*! @} */
3808
3809/*! @name LAYOUTSELECT - Hardware ECC Accelerator Layout Select Register */
3810/*! @{ */
3811#define BCH_LAYOUTSELECT_CS0_SELECT_MASK (0x3U)
3812#define BCH_LAYOUTSELECT_CS0_SELECT_SHIFT (0U)
3813/*! CS0_SELECT - CS0_SELECT
3814 */
3815#define BCH_LAYOUTSELECT_CS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS0_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS0_SELECT_MASK)
3816#define BCH_LAYOUTSELECT_CS1_SELECT_MASK (0xCU)
3817#define BCH_LAYOUTSELECT_CS1_SELECT_SHIFT (2U)
3818/*! CS1_SELECT - CS1_SELECT
3819 */
3820#define BCH_LAYOUTSELECT_CS1_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS1_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS1_SELECT_MASK)
3821#define BCH_LAYOUTSELECT_CS2_SELECT_MASK (0x30U)
3822#define BCH_LAYOUTSELECT_CS2_SELECT_SHIFT (4U)
3823/*! CS2_SELECT - CS2_SELECT
3824 */
3825#define BCH_LAYOUTSELECT_CS2_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS2_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS2_SELECT_MASK)
3826#define BCH_LAYOUTSELECT_CS3_SELECT_MASK (0xC0U)
3827#define BCH_LAYOUTSELECT_CS3_SELECT_SHIFT (6U)
3828/*! CS3_SELECT - CS3_SELECT
3829 */
3830#define BCH_LAYOUTSELECT_CS3_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS3_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS3_SELECT_MASK)
3831#define BCH_LAYOUTSELECT_CS4_SELECT_MASK (0x300U)
3832#define BCH_LAYOUTSELECT_CS4_SELECT_SHIFT (8U)
3833/*! CS4_SELECT - CS4_SELECT
3834 */
3835#define BCH_LAYOUTSELECT_CS4_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS4_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS4_SELECT_MASK)
3836#define BCH_LAYOUTSELECT_CS5_SELECT_MASK (0xC00U)
3837#define BCH_LAYOUTSELECT_CS5_SELECT_SHIFT (10U)
3838/*! CS5_SELECT - CS5_SELECT
3839 */
3840#define BCH_LAYOUTSELECT_CS5_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS5_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS5_SELECT_MASK)
3841#define BCH_LAYOUTSELECT_CS6_SELECT_MASK (0x3000U)
3842#define BCH_LAYOUTSELECT_CS6_SELECT_SHIFT (12U)
3843/*! CS6_SELECT - CS6_SELECT
3844 */
3845#define BCH_LAYOUTSELECT_CS6_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS6_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS6_SELECT_MASK)
3846#define BCH_LAYOUTSELECT_CS7_SELECT_MASK (0xC000U)
3847#define BCH_LAYOUTSELECT_CS7_SELECT_SHIFT (14U)
3848/*! CS7_SELECT - CS7_SELECT
3849 */
3850#define BCH_LAYOUTSELECT_CS7_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS7_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS7_SELECT_MASK)
3851#define BCH_LAYOUTSELECT_CS8_SELECT_MASK (0x30000U)
3852#define BCH_LAYOUTSELECT_CS8_SELECT_SHIFT (16U)
3853/*! CS8_SELECT - CS8_SELECT
3854 */
3855#define BCH_LAYOUTSELECT_CS8_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS8_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS8_SELECT_MASK)
3856#define BCH_LAYOUTSELECT_CS9_SELECT_MASK (0xC0000U)
3857#define BCH_LAYOUTSELECT_CS9_SELECT_SHIFT (18U)
3858/*! CS9_SELECT - CS9_SELECT
3859 */
3860#define BCH_LAYOUTSELECT_CS9_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS9_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS9_SELECT_MASK)
3861#define BCH_LAYOUTSELECT_CS10_SELECT_MASK (0x300000U)
3862#define BCH_LAYOUTSELECT_CS10_SELECT_SHIFT (20U)
3863/*! CS10_SELECT - CS10_SELECT
3864 */
3865#define BCH_LAYOUTSELECT_CS10_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS10_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS10_SELECT_MASK)
3866#define BCH_LAYOUTSELECT_CS11_SELECT_MASK (0xC00000U)
3867#define BCH_LAYOUTSELECT_CS11_SELECT_SHIFT (22U)
3868/*! CS11_SELECT - CS11_SELECT
3869 */
3870#define BCH_LAYOUTSELECT_CS11_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS11_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS11_SELECT_MASK)
3871#define BCH_LAYOUTSELECT_CS12_SELECT_MASK (0x3000000U)
3872#define BCH_LAYOUTSELECT_CS12_SELECT_SHIFT (24U)
3873/*! CS12_SELECT - CS12_SELECT
3874 */
3875#define BCH_LAYOUTSELECT_CS12_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS12_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS12_SELECT_MASK)
3876#define BCH_LAYOUTSELECT_CS13_SELECT_MASK (0xC000000U)
3877#define BCH_LAYOUTSELECT_CS13_SELECT_SHIFT (26U)
3878/*! CS13_SELECT - CS13_SELECT
3879 */
3880#define BCH_LAYOUTSELECT_CS13_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS13_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS13_SELECT_MASK)
3881#define BCH_LAYOUTSELECT_CS14_SELECT_MASK (0x30000000U)
3882#define BCH_LAYOUTSELECT_CS14_SELECT_SHIFT (28U)
3883/*! CS14_SELECT - CS14_SELECT
3884 */
3885#define BCH_LAYOUTSELECT_CS14_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS14_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS14_SELECT_MASK)
3886#define BCH_LAYOUTSELECT_CS15_SELECT_MASK (0xC0000000U)
3887#define BCH_LAYOUTSELECT_CS15_SELECT_SHIFT (30U)
3888/*! CS15_SELECT - CS15_SELECT
3889 */
3890#define BCH_LAYOUTSELECT_CS15_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_LAYOUTSELECT_CS15_SELECT_SHIFT)) & BCH_LAYOUTSELECT_CS15_SELECT_MASK)
3891/*! @} */
3892
3893/*! @name FLASH0LAYOUT0 - Hardware BCH ECC Flash 0 Layout 0 Register */
3894/*! @{ */
3895#define BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3896#define BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT (0U)
3897/*! DATA0_SIZE - DATA0_SIZE
3898 */
3899#define BCH_FLASH0LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_DATA0_SIZE_MASK)
3900#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3901#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3902/*! GF13_0_GF14_1 - GF13_0_GF14_1
3903 */
3904#define BCH_FLASH0LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT0_GF13_0_GF14_1_MASK)
3905#define BCH_FLASH0LAYOUT0_ECC0_MASK (0xF800U)
3906#define BCH_FLASH0LAYOUT0_ECC0_SHIFT (11U)
3907/*! ECC0 - ECC0
3908 * 0b00000..No ECC to be performed
3909 * 0b00001..ECC 2 to be performed
3910 * 0b00010..ECC 4 to be performed
3911 * 0b11110..ECC 60 to be performed
3912 * 0b11111..ECC 62 to be performed
3913 */
3914#define BCH_FLASH0LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_ECC0_SHIFT)) & BCH_FLASH0LAYOUT0_ECC0_MASK)
3915#define BCH_FLASH0LAYOUT0_META_SIZE_MASK (0xFF0000U)
3916#define BCH_FLASH0LAYOUT0_META_SIZE_SHIFT (16U)
3917/*! META_SIZE - META_SIZE
3918 */
3919#define BCH_FLASH0LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH0LAYOUT0_META_SIZE_MASK)
3920#define BCH_FLASH0LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3921#define BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT (24U)
3922/*! NBLOCKS - NBLOCKS
3923 */
3924#define BCH_FLASH0LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH0LAYOUT0_NBLOCKS_MASK)
3925/*! @} */
3926
3927/*! @name FLASH0LAYOUT1 - Hardware BCH ECC Flash 0 Layout 1 Register */
3928/*! @{ */
3929#define BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3930#define BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT (0U)
3931/*! DATAN_SIZE - DATAN_SIZE
3932 */
3933#define BCH_FLASH0LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_DATAN_SIZE_MASK)
3934#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3935#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3936/*! GF13_0_GF14_1 - GF13_0_GF14_1
3937 */
3938#define BCH_FLASH0LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH0LAYOUT1_GF13_0_GF14_1_MASK)
3939#define BCH_FLASH0LAYOUT1_ECCN_MASK (0xF800U)
3940#define BCH_FLASH0LAYOUT1_ECCN_SHIFT (11U)
3941/*! ECCN - ECCN
3942 * 0b00000..No ECC to be performed
3943 * 0b00001..ECC 2 to be performed
3944 * 0b00010..ECC 4 to be performed
3945 * 0b11110..ECC 60 to be performed
3946 * 0b11111..ECC 62 to be performed
3947 */
3948#define BCH_FLASH0LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_ECCN_SHIFT)) & BCH_FLASH0LAYOUT1_ECCN_MASK)
3949#define BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
3950#define BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT (16U)
3951/*! PAGE_SIZE - PAGE_SIZE
3952 */
3953#define BCH_FLASH0LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH0LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH0LAYOUT1_PAGE_SIZE_MASK)
3954/*! @} */
3955
3956/*! @name FLASH1LAYOUT0 - Hardware BCH ECC Flash 1 Layout 0 Register */
3957/*! @{ */
3958#define BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
3959#define BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT (0U)
3960/*! DATA0_SIZE - DATA0_SIZE
3961 */
3962#define BCH_FLASH1LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_DATA0_SIZE_MASK)
3963#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
3964#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
3965/*! GF13_0_GF14_1 - GF13_0_GF14_1
3966 */
3967#define BCH_FLASH1LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT0_GF13_0_GF14_1_MASK)
3968#define BCH_FLASH1LAYOUT0_ECC0_MASK (0xF800U)
3969#define BCH_FLASH1LAYOUT0_ECC0_SHIFT (11U)
3970/*! ECC0 - ECC0
3971 * 0b00000..No ECC to be performed
3972 * 0b00001..ECC 2 to be performed
3973 * 0b00010..ECC 4 to be performed
3974 * 0b11110..ECC 60 to be performed
3975 * 0b11111..ECC 62 to be performed
3976 */
3977#define BCH_FLASH1LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_ECC0_SHIFT)) & BCH_FLASH1LAYOUT0_ECC0_MASK)
3978#define BCH_FLASH1LAYOUT0_META_SIZE_MASK (0xFF0000U)
3979#define BCH_FLASH1LAYOUT0_META_SIZE_SHIFT (16U)
3980/*! META_SIZE - META_SIZE
3981 */
3982#define BCH_FLASH1LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH1LAYOUT0_META_SIZE_MASK)
3983#define BCH_FLASH1LAYOUT0_NBLOCKS_MASK (0xFF000000U)
3984#define BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT (24U)
3985/*! NBLOCKS - NBLOCKS
3986 */
3987#define BCH_FLASH1LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH1LAYOUT0_NBLOCKS_MASK)
3988/*! @} */
3989
3990/*! @name FLASH1LAYOUT1 - Hardware BCH ECC Flash 1 Layout 1 Register */
3991/*! @{ */
3992#define BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
3993#define BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT (0U)
3994/*! DATAN_SIZE - DATAN_SIZE
3995 */
3996#define BCH_FLASH1LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_DATAN_SIZE_MASK)
3997#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
3998#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
3999/*! GF13_0_GF14_1 - GF13_0_GF14_1
4000 */
4001#define BCH_FLASH1LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH1LAYOUT1_GF13_0_GF14_1_MASK)
4002#define BCH_FLASH1LAYOUT1_ECCN_MASK (0xF800U)
4003#define BCH_FLASH1LAYOUT1_ECCN_SHIFT (11U)
4004/*! ECCN - ECCN
4005 * 0b00000..No ECC to be performed
4006 * 0b00001..ECC 2 to be performed
4007 * 0b00010..ECC 4 to be performed
4008 * 0b11110..ECC 60 to be performed
4009 * 0b11111..ECC 62 to be performed
4010 */
4011#define BCH_FLASH1LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_ECCN_SHIFT)) & BCH_FLASH1LAYOUT1_ECCN_MASK)
4012#define BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4013#define BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT (16U)
4014/*! PAGE_SIZE - PAGE_SIZE
4015 */
4016#define BCH_FLASH1LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH1LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH1LAYOUT1_PAGE_SIZE_MASK)
4017/*! @} */
4018
4019/*! @name FLASH2LAYOUT0 - Hardware BCH ECC Flash 2 Layout 0 Register */
4020/*! @{ */
4021#define BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
4022#define BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT (0U)
4023/*! DATA0_SIZE - DATA0_SIZE
4024 */
4025#define BCH_FLASH2LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_DATA0_SIZE_MASK)
4026#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
4027#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
4028/*! GF13_0_GF14_1 - GF13_0_GF14_1
4029 */
4030#define BCH_FLASH2LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT0_GF13_0_GF14_1_MASK)
4031#define BCH_FLASH2LAYOUT0_ECC0_MASK (0xF800U)
4032#define BCH_FLASH2LAYOUT0_ECC0_SHIFT (11U)
4033/*! ECC0 - ECC0
4034 * 0b00000..No ECC to be performed
4035 * 0b00001..ECC 2 to be performed
4036 * 0b00010..ECC 4 to be performed
4037 * 0b11110..ECC 60 to be performed
4038 * 0b11111..ECC 62 to be performed
4039 */
4040#define BCH_FLASH2LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_ECC0_SHIFT)) & BCH_FLASH2LAYOUT0_ECC0_MASK)
4041#define BCH_FLASH2LAYOUT0_META_SIZE_MASK (0xFF0000U)
4042#define BCH_FLASH2LAYOUT0_META_SIZE_SHIFT (16U)
4043/*! META_SIZE - META_SIZE
4044 */
4045#define BCH_FLASH2LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH2LAYOUT0_META_SIZE_MASK)
4046#define BCH_FLASH2LAYOUT0_NBLOCKS_MASK (0xFF000000U)
4047#define BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT (24U)
4048/*! NBLOCKS - NBLOCKS
4049 */
4050#define BCH_FLASH2LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH2LAYOUT0_NBLOCKS_MASK)
4051/*! @} */
4052
4053/*! @name FLASH2LAYOUT1 - Hardware BCH ECC Flash 2 Layout 1 Register */
4054/*! @{ */
4055#define BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
4056#define BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT (0U)
4057/*! DATAN_SIZE - DATAN_SIZE
4058 */
4059#define BCH_FLASH2LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_DATAN_SIZE_MASK)
4060#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
4061#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
4062/*! GF13_0_GF14_1 - GF13_0_GF14_1
4063 */
4064#define BCH_FLASH2LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH2LAYOUT1_GF13_0_GF14_1_MASK)
4065#define BCH_FLASH2LAYOUT1_ECCN_MASK (0xF800U)
4066#define BCH_FLASH2LAYOUT1_ECCN_SHIFT (11U)
4067/*! ECCN - ECCN
4068 * 0b00000..No ECC to be performed
4069 * 0b00001..ECC 2 to be performed
4070 * 0b00010..ECC 4 to be performed
4071 * 0b11110..ECC 60 to be performed
4072 * 0b11111..ECC 62 to be performed
4073 */
4074#define BCH_FLASH2LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_ECCN_SHIFT)) & BCH_FLASH2LAYOUT1_ECCN_MASK)
4075#define BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4076#define BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT (16U)
4077/*! PAGE_SIZE - PAGE_SIZE
4078 */
4079#define BCH_FLASH2LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH2LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH2LAYOUT1_PAGE_SIZE_MASK)
4080/*! @} */
4081
4082/*! @name FLASH3LAYOUT0 - Hardware BCH ECC Flash 3 Layout 0 Register */
4083/*! @{ */
4084#define BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK (0x3FFU)
4085#define BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT (0U)
4086/*! DATA0_SIZE - DATA0_SIZE
4087 */
4088#define BCH_FLASH3LAYOUT0_DATA0_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_DATA0_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_DATA0_SIZE_MASK)
4089#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK (0x400U)
4090#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT (10U)
4091/*! GF13_0_GF14_1 - GF13_0_GF14_1
4092 */
4093#define BCH_FLASH3LAYOUT0_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT0_GF13_0_GF14_1_MASK)
4094#define BCH_FLASH3LAYOUT0_ECC0_MASK (0xF800U)
4095#define BCH_FLASH3LAYOUT0_ECC0_SHIFT (11U)
4096/*! ECC0 - ECC0
4097 * 0b00000..No ECC to be performed
4098 * 0b00001..ECC 2 to be performed
4099 * 0b00010..ECC 4 to be performed
4100 * 0b11110..ECC 60 to be performed
4101 * 0b11111..ECC 62 to be performed
4102 */
4103#define BCH_FLASH3LAYOUT0_ECC0(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_ECC0_SHIFT)) & BCH_FLASH3LAYOUT0_ECC0_MASK)
4104#define BCH_FLASH3LAYOUT0_META_SIZE_MASK (0xFF0000U)
4105#define BCH_FLASH3LAYOUT0_META_SIZE_SHIFT (16U)
4106/*! META_SIZE - META_SIZE
4107 */
4108#define BCH_FLASH3LAYOUT0_META_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_META_SIZE_SHIFT)) & BCH_FLASH3LAYOUT0_META_SIZE_MASK)
4109#define BCH_FLASH3LAYOUT0_NBLOCKS_MASK (0xFF000000U)
4110#define BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT (24U)
4111/*! NBLOCKS - NBLOCKS
4112 */
4113#define BCH_FLASH3LAYOUT0_NBLOCKS(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT0_NBLOCKS_SHIFT)) & BCH_FLASH3LAYOUT0_NBLOCKS_MASK)
4114/*! @} */
4115
4116/*! @name FLASH3LAYOUT1 - Hardware BCH ECC Flash 3 Layout 1 Register */
4117/*! @{ */
4118#define BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK (0x3FFU)
4119#define BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT (0U)
4120/*! DATAN_SIZE - DATAN_SIZE
4121 */
4122#define BCH_FLASH3LAYOUT1_DATAN_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_DATAN_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_DATAN_SIZE_MASK)
4123#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK (0x400U)
4124#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT (10U)
4125/*! GF13_0_GF14_1 - GF13_0_GF14_1
4126 */
4127#define BCH_FLASH3LAYOUT1_GF13_0_GF14_1(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_GF13_0_GF14_1_SHIFT)) & BCH_FLASH3LAYOUT1_GF13_0_GF14_1_MASK)
4128#define BCH_FLASH3LAYOUT1_ECCN_MASK (0xF800U)
4129#define BCH_FLASH3LAYOUT1_ECCN_SHIFT (11U)
4130/*! ECCN - ECCN
4131 * 0b00000..No ECC to be performed
4132 * 0b00001..ECC 2 to be performed
4133 * 0b00010..ECC 4 to be performed
4134 * 0b11110..ECC 60 to be performed
4135 * 0b11111..ECC 62 to be performed
4136 */
4137#define BCH_FLASH3LAYOUT1_ECCN(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_ECCN_SHIFT)) & BCH_FLASH3LAYOUT1_ECCN_MASK)
4138#define BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK (0xFFFF0000U)
4139#define BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT (16U)
4140/*! PAGE_SIZE - PAGE_SIZE
4141 */
4142#define BCH_FLASH3LAYOUT1_PAGE_SIZE(x) (((uint32_t)(((uint32_t)(x)) << BCH_FLASH3LAYOUT1_PAGE_SIZE_SHIFT)) & BCH_FLASH3LAYOUT1_PAGE_SIZE_MASK)
4143/*! @} */
4144
4145/*! @name DEBUG0 - Hardware BCH ECC Debug Register0 */
4146/*! @{ */
4147#define BCH_DEBUG0_DEBUG_REG_SELECT_MASK (0x3FU)
4148#define BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT (0U)
4149/*! DEBUG_REG_SELECT - DEBUG_REG_SELECT
4150 */
4151#define BCH_DEBUG0_DEBUG_REG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_DEBUG_REG_SELECT_SHIFT)) & BCH_DEBUG0_DEBUG_REG_SELECT_MASK)
4152#define BCH_DEBUG0_RSVD0_MASK (0xC0U)
4153#define BCH_DEBUG0_RSVD0_SHIFT (6U)
4154/*! RSVD0 - This field is reserved.
4155 */
4156#define BCH_DEBUG0_RSVD0(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD0_SHIFT)) & BCH_DEBUG0_RSVD0_MASK)
4157#define BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK (0x100U)
4158#define BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT (8U)
4159/*! BM_KES_TEST_BYPASS - BM_KES_TEST_BYPASS
4160 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
4161 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
4162 */
4163#define BCH_DEBUG0_BM_KES_TEST_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_BM_KES_TEST_BYPASS_SHIFT)) & BCH_DEBUG0_BM_KES_TEST_BYPASS_MASK)
4164#define BCH_DEBUG0_KES_DEBUG_STALL_MASK (0x200U)
4165#define BCH_DEBUG0_KES_DEBUG_STALL_SHIFT (9U)
4166/*! KES_DEBUG_STALL - KES_DEBUG_STALL
4167 * 0b0..KES FSM proceeds to next block supplied by bus master.
4168 * 0b1..KES FSM waits after current equations are solved and the search engine is started.
4169 */
4170#define BCH_DEBUG0_KES_DEBUG_STALL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STALL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STALL_MASK)
4171#define BCH_DEBUG0_KES_DEBUG_STEP_MASK (0x400U)
4172#define BCH_DEBUG0_KES_DEBUG_STEP_SHIFT (10U)
4173/*! KES_DEBUG_STEP - KES_DEBUG_STEP
4174 */
4175#define BCH_DEBUG0_KES_DEBUG_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_STEP_SHIFT)) & BCH_DEBUG0_KES_DEBUG_STEP_MASK)
4176#define BCH_DEBUG0_KES_STANDALONE_MASK (0x800U)
4177#define BCH_DEBUG0_KES_STANDALONE_SHIFT (11U)
4178/*! KES_STANDALONE - KES_STANDALONE
4179 * 0b0..Bus master address generator for SYND_GEN writes operates normally.
4180 * 0b1..Bus master address generator always addresses last four bytes in Auxiliary block.
4181 */
4182#define BCH_DEBUG0_KES_STANDALONE(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_STANDALONE_SHIFT)) & BCH_DEBUG0_KES_STANDALONE_MASK)
4183#define BCH_DEBUG0_KES_DEBUG_KICK_MASK (0x1000U)
4184#define BCH_DEBUG0_KES_DEBUG_KICK_SHIFT (12U)
4185/*! KES_DEBUG_KICK - KES_DEBUG_KICK
4186 */
4187#define BCH_DEBUG0_KES_DEBUG_KICK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_KICK_SHIFT)) & BCH_DEBUG0_KES_DEBUG_KICK_MASK)
4188#define BCH_DEBUG0_KES_DEBUG_MODE4K_MASK (0x2000U)
4189#define BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT (13U)
4190/*! KES_DEBUG_MODE4K - KES_DEBUG_MODE4K
4191 * 0b1..Mode is set for 4K NAND pages.
4192 * 0b1..Mode is set for 2K NAND pages.
4193 */
4194#define BCH_DEBUG0_KES_DEBUG_MODE4K(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_MODE4K_SHIFT)) & BCH_DEBUG0_KES_DEBUG_MODE4K_MASK)
4195#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK (0x4000U)
4196#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT (14U)
4197/*! KES_DEBUG_PAYLOAD_FLAG - KES_DEBUG_PAYLOAD_FLAG
4198 * 0b1..Payload is set for 512 bytes data block.
4199 * 0b1..Payload is set for 65 or 19 bytes auxiliary block.
4200 */
4201#define BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_SHIFT)) & BCH_DEBUG0_KES_DEBUG_PAYLOAD_FLAG_MASK)
4202#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK (0x8000U)
4203#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT (15U)
4204/*! KES_DEBUG_SHIFT_SYND - KES_DEBUG_SHIFT_SYND
4205 */
4206#define BCH_DEBUG0_KES_DEBUG_SHIFT_SYND(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SHIFT_SYND_MASK)
4207#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK (0x1FF0000U)
4208#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT (16U)
4209/*! KES_DEBUG_SYNDROME_SYMBOL - KES_DEBUG_SYNDROME_SYMBOL
4210 * 0b000000000..Bus master address generator for SYND_GEN writes operates normally.
4211 * 0b000000001..Bus master address generator always addresses last four bytes in Auxiliary block.
4212 */
4213#define BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_SHIFT)) & BCH_DEBUG0_KES_DEBUG_SYNDROME_SYMBOL_MASK)
4214#define BCH_DEBUG0_RSVD1_MASK (0xFE000000U)
4215#define BCH_DEBUG0_RSVD1_SHIFT (25U)
4216/*! RSVD1 - This field is reserved.
4217 */
4218#define BCH_DEBUG0_RSVD1(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG0_RSVD1_SHIFT)) & BCH_DEBUG0_RSVD1_MASK)
4219/*! @} */
4220
4221/*! @name DBGKESREAD - KES Debug Read Register */
4222/*! @{ */
4223#define BCH_DBGKESREAD_VALUES_MASK (0xFFFFFFFFU)
4224#define BCH_DBGKESREAD_VALUES_SHIFT (0U)
4225/*! VALUES - VALUES
4226 */
4227#define BCH_DBGKESREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGKESREAD_VALUES_SHIFT)) & BCH_DBGKESREAD_VALUES_MASK)
4228/*! @} */
4229
4230/*! @name DBGCSFEREAD - Chien Search Debug Read Register */
4231/*! @{ */
4232#define BCH_DBGCSFEREAD_VALUES_MASK (0xFFFFFFFFU)
4233#define BCH_DBGCSFEREAD_VALUES_SHIFT (0U)
4234/*! VALUES - VALUES
4235 */
4236#define BCH_DBGCSFEREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGCSFEREAD_VALUES_SHIFT)) & BCH_DBGCSFEREAD_VALUES_MASK)
4237/*! @} */
4238
4239/*! @name DBGSYNDGENREAD - Syndrome Generator Debug Read Register */
4240/*! @{ */
4241#define BCH_DBGSYNDGENREAD_VALUES_MASK (0xFFFFFFFFU)
4242#define BCH_DBGSYNDGENREAD_VALUES_SHIFT (0U)
4243/*! VALUES - VALUES
4244 */
4245#define BCH_DBGSYNDGENREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGSYNDGENREAD_VALUES_SHIFT)) & BCH_DBGSYNDGENREAD_VALUES_MASK)
4246/*! @} */
4247
4248/*! @name DBGAHBMREAD - Bus Master and ECC Controller Debug Read Register */
4249/*! @{ */
4250#define BCH_DBGAHBMREAD_VALUES_MASK (0xFFFFFFFFU)
4251#define BCH_DBGAHBMREAD_VALUES_SHIFT (0U)
4252/*! VALUES - VALUES
4253 */
4254#define BCH_DBGAHBMREAD_VALUES(x) (((uint32_t)(((uint32_t)(x)) << BCH_DBGAHBMREAD_VALUES_SHIFT)) & BCH_DBGAHBMREAD_VALUES_MASK)
4255/*! @} */
4256
4257/*! @name BLOCKNAME - Block Name Register */
4258/*! @{ */
4259#define BCH_BLOCKNAME_NAME_MASK (0xFFFFFFFFU)
4260#define BCH_BLOCKNAME_NAME_SHIFT (0U)
4261/*! NAME - NAME
4262 */
4263#define BCH_BLOCKNAME_NAME(x) (((uint32_t)(((uint32_t)(x)) << BCH_BLOCKNAME_NAME_SHIFT)) & BCH_BLOCKNAME_NAME_MASK)
4264/*! @} */
4265
4266/*! @name VERSION - BCH Version Register */
4267/*! @{ */
4268#define BCH_VERSION_STEP_MASK (0xFFFFU)
4269#define BCH_VERSION_STEP_SHIFT (0U)
4270/*! STEP - STEP
4271 */
4272#define BCH_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_STEP_SHIFT)) & BCH_VERSION_STEP_MASK)
4273#define BCH_VERSION_MINOR_MASK (0xFF0000U)
4274#define BCH_VERSION_MINOR_SHIFT (16U)
4275/*! MINOR - MINOR
4276 */
4277#define BCH_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MINOR_SHIFT)) & BCH_VERSION_MINOR_MASK)
4278#define BCH_VERSION_MAJOR_MASK (0xFF000000U)
4279#define BCH_VERSION_MAJOR_SHIFT (24U)
4280/*! MAJOR - MAJOR
4281 */
4282#define BCH_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << BCH_VERSION_MAJOR_SHIFT)) & BCH_VERSION_MAJOR_MASK)
4283/*! @} */
4284
4285/*! @name DEBUG1 - Hardware BCH ECC Debug Register 1 */
4286/*! @{ */
4287#define BCH_DEBUG1_ERASED_ZERO_COUNT_MASK (0x1FFU)
4288#define BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT (0U)
4289/*! ERASED_ZERO_COUNT - ERASED_ZERO_COUNT
4290 */
4291#define BCH_DEBUG1_ERASED_ZERO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_ERASED_ZERO_COUNT_SHIFT)) & BCH_DEBUG1_ERASED_ZERO_COUNT_MASK)
4292#define BCH_DEBUG1_RSVD_MASK (0x7FFFFE00U)
4293#define BCH_DEBUG1_RSVD_SHIFT (9U)
4294/*! RSVD - This field is reserved.
4295 */
4296#define BCH_DEBUG1_RSVD(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_RSVD_SHIFT)) & BCH_DEBUG1_RSVD_MASK)
4297#define BCH_DEBUG1_DEBUG1_PREERASECHK_MASK (0x80000000U)
4298#define BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT (31U)
4299/*! DEBUG1_PREERASECHK - DEBUG1_PREERASECHK
4300 * 0b0..Turn off pre-erase check
4301 * 0b1..Turn on pre-erase check
4302 */
4303#define BCH_DEBUG1_DEBUG1_PREERASECHK(x) (((uint32_t)(((uint32_t)(x)) << BCH_DEBUG1_DEBUG1_PREERASECHK_SHIFT)) & BCH_DEBUG1_DEBUG1_PREERASECHK_MASK)
4304/*! @} */
4305
4306
4307/*!
4308 * @}
4309 */ /* end of group BCH_Register_Masks */
4310
4311
4312/* BCH - Peripheral instance base addresses */
4313/** Peripheral CONNECTIVITY__BCH base address */
4314#define CONNECTIVITY__BCH_BASE (0x5B814000u)
4315/** Peripheral CONNECTIVITY__BCH base pointer */
4316#define CONNECTIVITY__BCH ((BCH_Type *)CONNECTIVITY__BCH_BASE)
4317/** Array initializer of BCH peripheral base addresses */
4318#define BCH_BASE_ADDRS { CONNECTIVITY__BCH_BASE }
4319/** Array initializer of BCH peripheral base pointers */
4320#define BCH_BASE_PTRS { CONNECTIVITY__BCH }
4321
4322/*!
4323 * @}
4324 */ /* end of group BCH_Peripheral_Access_Layer */
4325
4326
4327/* ----------------------------------------------------------------------------
4328 -- CAN Peripheral Access Layer
4329 ---------------------------------------------------------------------------- */
4330
4331/*!
4332 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
4333 * @{
4334 */
4335
4336/** CAN - Register Layout Typedef */
4337typedef struct {
4338 __IO uint32_t MCR; /**< Module Configuration register, offset: 0x0 */
4339 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
4340 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
4341 uint8_t RESERVED_0[4];
4342 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask register, offset: 0x10 */
4343 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
4344 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
4345 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
4346 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
4347 __IO uint32_t IMASK2; /**< Interrupt Masks 2 register, offset: 0x24 */
4348 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
4349 __IO uint32_t IFLAG2; /**< Interrupt Flags 2 register, offset: 0x2C */
4350 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
4351 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
4352 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
4353 uint8_t RESERVED_1[8];
4354 __I uint32_t CRCR; /**< CRC register, offset: 0x44 */
4355 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
4356 __I uint32_t RXFIR; /**< Rx FIFO Information register, offset: 0x4C */
4357 __IO uint32_t CBT; /**< CAN Bit Timing register, offset: 0x50 */
4358 uint8_t RESERVED_2[4];
4359 __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */
4360 __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */
4361 uint8_t RESERVED_3[32];
4362 struct { /* offset: 0x80, array step: 0x10 */
4363 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
4364 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
4365 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
4366 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
4367 } MB[64];
4368 uint8_t RESERVED_4[1024];
4369 __IO uint32_t RXIMR[64]; /**< Rx Individual Mask registers, array offset: 0x880, array step: 0x4 */
4370 uint8_t RESERVED_5[640];
4371 __IO uint32_t FDCTRL; /**< CAN FD Control register, offset: 0xC00 */
4372 __IO uint32_t FDCBT; /**< CAN FD Bit Timing register, offset: 0xC04 */
4373 __I uint32_t FDCRC; /**< CAN FD CRC register, offset: 0xC08 */
4374} CAN_Type;
4375
4376/* ----------------------------------------------------------------------------
4377 -- CAN Register Masks
4378 ---------------------------------------------------------------------------- */
4379
4380/*!
4381 * @addtogroup CAN_Register_Masks CAN Register Masks
4382 * @{
4383 */
4384
4385/*! @name MCR - Module Configuration register */
4386/*! @{ */
4387#define CAN_MCR_MAXMB_MASK (0x7FU)
4388#define CAN_MCR_MAXMB_SHIFT (0U)
4389/*! MAXMB - Number Of The Last Message Buffer
4390 */
4391#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
4392#define CAN_MCR_IDAM_MASK (0x300U)
4393#define CAN_MCR_IDAM_SHIFT (8U)
4394/*! IDAM - ID Acceptance Mode
4395 * 0b00..Format A: One full ID (standard and extended) per ID filter table element.
4396 * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
4397 * 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
4398 * 0b11..Format D: All frames rejected.
4399 */
4400#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
4401#define CAN_MCR_FDEN_MASK (0x800U)
4402#define CAN_MCR_FDEN_SHIFT (11U)
4403/*! FDEN - CAN FD operation enable
4404 * 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
4405 * 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
4406 */
4407#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
4408#define CAN_MCR_AEN_MASK (0x1000U)
4409#define CAN_MCR_AEN_SHIFT (12U)
4410/*! AEN - Abort Enable
4411 * 0b0..Abort disabled.
4412 * 0b1..Abort enabled.
4413 */
4414#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
4415#define CAN_MCR_LPRIOEN_MASK (0x2000U)
4416#define CAN_MCR_LPRIOEN_SHIFT (13U)
4417/*! LPRIOEN - Local Priority Enable
4418 * 0b0..Local Priority disabled.
4419 * 0b1..Local Priority enabled.
4420 */
4421#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
4422#define CAN_MCR_DMA_MASK (0x8000U)
4423#define CAN_MCR_DMA_SHIFT (15U)
4424/*! DMA - DMA Enable
4425 * 0b0..DMA feature for RX FIFO disabled.
4426 * 0b1..DMA feature for RX FIFO enabled.
4427 */
4428#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
4429#define CAN_MCR_IRMQ_MASK (0x10000U)
4430#define CAN_MCR_IRMQ_SHIFT (16U)
4431/*! IRMQ - Individual Rx Masking And Queue Enable
4432 * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
4433 * applications, the reading of C/S word locks the MB even if it is EMPTY.
4434 * 0b1..Individual Rx masking and queue feature are enabled.
4435 */
4436#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
4437#define CAN_MCR_SRXDIS_MASK (0x20000U)
4438#define CAN_MCR_SRXDIS_SHIFT (17U)
4439/*! SRXDIS - Self Reception Disable
4440 * 0b0..Self-reception enabled.
4441 * 0b1..Self-reception disabled.
4442 */
4443#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
4444#define CAN_MCR_DOZE_MASK (0x40000U)
4445#define CAN_MCR_DOZE_SHIFT (18U)
4446/*! DOZE - Doze Mode Enable
4447 * 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
4448 * 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
4449 */
4450#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
4451#define CAN_MCR_WAKSRC_MASK (0x80000U)
4452#define CAN_MCR_WAKSRC_SHIFT (19U)
4453/*! WAKSRC - Wake Up Source
4454 * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
4455 * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
4456 */
4457#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
4458#define CAN_MCR_LPMACK_MASK (0x100000U)
4459#define CAN_MCR_LPMACK_SHIFT (20U)
4460/*! LPMACK - Low-Power Mode Acknowledge
4461 * 0b0..FlexCAN is not in a low-power mode.
4462 * 0b1..FlexCAN is in a low-power mode.
4463 */
4464#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
4465#define CAN_MCR_WRNEN_MASK (0x200000U)
4466#define CAN_MCR_WRNEN_SHIFT (21U)
4467/*! WRNEN - Warning Interrupt Enable
4468 * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
4469 * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
4470 */
4471#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
4472#define CAN_MCR_SLFWAK_MASK (0x400000U)
4473#define CAN_MCR_SLFWAK_SHIFT (22U)
4474/*! SLFWAK - Self Wake Up
4475 * 0b0..FlexCAN Self Wake Up feature is disabled.
4476 * 0b1..FlexCAN Self Wake Up feature is enabled.
4477 */
4478#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
4479#define CAN_MCR_FRZACK_MASK (0x1000000U)
4480#define CAN_MCR_FRZACK_SHIFT (24U)
4481/*! FRZACK - Freeze Mode Acknowledge
4482 * 0b0..FlexCAN not in Freeze mode, prescaler running.
4483 * 0b1..FlexCAN in Freeze mode, prescaler stopped.
4484 */
4485#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
4486#define CAN_MCR_SOFTRST_MASK (0x2000000U)
4487#define CAN_MCR_SOFTRST_SHIFT (25U)
4488/*! SOFTRST - Soft Reset
4489 * 0b0..No reset request.
4490 * 0b1..Resets the registers affected by soft reset.
4491 */
4492#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
4493#define CAN_MCR_WAKMSK_MASK (0x4000000U)
4494#define CAN_MCR_WAKMSK_SHIFT (26U)
4495/*! WAKMSK - Wake Up Interrupt Mask
4496 * 0b0..Wake Up interrupt is disabled.
4497 * 0b1..Wake Up interrupt is enabled.
4498 */
4499#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
4500#define CAN_MCR_NOTRDY_MASK (0x8000000U)
4501#define CAN_MCR_NOTRDY_SHIFT (27U)
4502/*! NOTRDY - FlexCAN Not Ready
4503 * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
4504 * 0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
4505 */
4506#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
4507#define CAN_MCR_HALT_MASK (0x10000000U)
4508#define CAN_MCR_HALT_SHIFT (28U)
4509/*! HALT - Halt FlexCAN
4510 * 0b0..No Freeze mode request.
4511 * 0b1..Enters Freeze mode if the FRZ bit is asserted.
4512 */
4513#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
4514#define CAN_MCR_RFEN_MASK (0x20000000U)
4515#define CAN_MCR_RFEN_SHIFT (29U)
4516/*! RFEN - Rx FIFO Enable
4517 * 0b0..Rx FIFO not enabled.
4518 * 0b1..Rx FIFO enabled.
4519 */
4520#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
4521#define CAN_MCR_FRZ_MASK (0x40000000U)
4522#define CAN_MCR_FRZ_SHIFT (30U)
4523/*! FRZ - Freeze Enable
4524 * 0b0..Not enabled to enter Freeze mode.
4525 * 0b1..Enabled to enter Freeze mode.
4526 */
4527#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
4528#define CAN_MCR_MDIS_MASK (0x80000000U)
4529#define CAN_MCR_MDIS_SHIFT (31U)
4530/*! MDIS - Module Disable
4531 * 0b0..Enable the FlexCAN module.
4532 * 0b1..Disable the FlexCAN module.
4533 */
4534#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
4535/*! @} */
4536
4537/*! @name CTRL1 - Control 1 register */
4538/*! @{ */
4539#define CAN_CTRL1_PROPSEG_MASK (0x7U)
4540#define CAN_CTRL1_PROPSEG_SHIFT (0U)
4541/*! PROPSEG - Propagation Segment
4542 */
4543#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
4544#define CAN_CTRL1_LOM_MASK (0x8U)
4545#define CAN_CTRL1_LOM_SHIFT (3U)
4546/*! LOM - Listen-Only Mode
4547 * 0b0..Listen-Only mode is deactivated.
4548 * 0b1..FlexCAN module operates in Listen-Only mode.
4549 */
4550#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
4551#define CAN_CTRL1_LBUF_MASK (0x10U)
4552#define CAN_CTRL1_LBUF_SHIFT (4U)
4553/*! LBUF - Lowest Buffer Transmitted First
4554 * 0b0..Buffer with highest priority is transmitted first.
4555 * 0b1..Lowest number buffer is transmitted first.
4556 */
4557#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
4558#define CAN_CTRL1_TSYN_MASK (0x20U)
4559#define CAN_CTRL1_TSYN_SHIFT (5U)
4560/*! TSYN - Timer Sync
4561 * 0b0..Timer sync feature disabled
4562 * 0b1..Timer sync feature enabled
4563 */
4564#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
4565#define CAN_CTRL1_BOFFREC_MASK (0x40U)
4566#define CAN_CTRL1_BOFFREC_SHIFT (6U)
4567/*! BOFFREC - Bus Off Recovery
4568 * 0b0..Automatic recovering from Bus Off state enabled.
4569 * 0b1..Automatic recovering from Bus Off state disabled.
4570 */
4571#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
4572#define CAN_CTRL1_SMP_MASK (0x80U)
4573#define CAN_CTRL1_SMP_SHIFT (7U)
4574/*! SMP - CAN Bit Sampling
4575 * 0b0..Just one sample is used to determine the bit value.
4576 * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
4577 * preceding samples; a majority rule is used.
4578 */
4579#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
4580#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
4581#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
4582/*! RWRNMSK - Rx Warning Interrupt Mask
4583 * 0b0..Rx Warning interrupt disabled.
4584 * 0b1..Rx Warning interrupt enabled.
4585 */
4586#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
4587#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
4588#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
4589/*! TWRNMSK - Tx Warning Interrupt Mask
4590 * 0b0..Tx Warning interrupt disabled.
4591 * 0b1..Tx Warning interrupt enabled.
4592 */
4593#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
4594#define CAN_CTRL1_LPB_MASK (0x1000U)
4595#define CAN_CTRL1_LPB_SHIFT (12U)
4596/*! LPB - Loop Back Mode
4597 * 0b0..Loop Back disabled.
4598 * 0b1..Loop Back enabled.
4599 */
4600#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
4601#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
4602#define CAN_CTRL1_CLKSRC_SHIFT (13U)
4603/*! CLKSRC - CAN Engine Clock Source
4604 * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
4605 * 0b1..The CAN engine clock source is the peripheral clock.
4606 */
4607#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
4608#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
4609#define CAN_CTRL1_ERRMSK_SHIFT (14U)
4610/*! ERRMSK - Error Interrupt Mask
4611 * 0b0..Error interrupt disabled.
4612 * 0b1..Error interrupt enabled.
4613 */
4614#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
4615#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
4616#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
4617/*! BOFFMSK - Bus Off Interrupt Mask
4618 * 0b0..Bus Off interrupt disabled.
4619 * 0b1..Bus Off interrupt enabled.
4620 */
4621#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
4622#define CAN_CTRL1_PSEG2_MASK (0x70000U)
4623#define CAN_CTRL1_PSEG2_SHIFT (16U)
4624/*! PSEG2 - Phase Segment 2
4625 */
4626#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
4627#define CAN_CTRL1_PSEG1_MASK (0x380000U)
4628#define CAN_CTRL1_PSEG1_SHIFT (19U)
4629/*! PSEG1 - Phase Segment 1
4630 */
4631#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
4632#define CAN_CTRL1_RJW_MASK (0xC00000U)
4633#define CAN_CTRL1_RJW_SHIFT (22U)
4634/*! RJW - Resync Jump Width
4635 */
4636#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
4637#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
4638#define CAN_CTRL1_PRESDIV_SHIFT (24U)
4639/*! PRESDIV - Prescaler Division Factor
4640 */
4641#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
4642/*! @} */
4643
4644/*! @name TIMER - Free Running Timer */
4645/*! @{ */
4646#define CAN_TIMER_TIMER_MASK (0xFFFFU)
4647#define CAN_TIMER_TIMER_SHIFT (0U)
4648/*! TIMER - Timer Value
4649 */
4650#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
4651/*! @} */
4652
4653/*! @name RXMGMASK - Rx Mailboxes Global Mask register */
4654/*! @{ */
4655#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
4656#define CAN_RXMGMASK_MG_SHIFT (0U)
4657/*! MG - Rx Mailboxes Global Mask Bits
4658 */
4659#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
4660/*! @} */
4661
4662/*! @name RX14MASK - Rx 14 Mask register */
4663/*! @{ */
4664#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
4665#define CAN_RX14MASK_RX14M_SHIFT (0U)
4666/*! RX14M - Rx Buffer 14 Mask Bits
4667 */
4668#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
4669/*! @} */
4670
4671/*! @name RX15MASK - Rx 15 Mask register */
4672/*! @{ */
4673#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
4674#define CAN_RX15MASK_RX15M_SHIFT (0U)
4675/*! RX15M - Rx Buffer 15 Mask Bits
4676 */
4677#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
4678/*! @} */
4679
4680/*! @name ECR - Error Counter */
4681/*! @{ */
4682#define CAN_ECR_TXERRCNT_MASK (0xFFU)
4683#define CAN_ECR_TXERRCNT_SHIFT (0U)
4684/*! TXERRCNT - Transmit Error Counter
4685 */
4686#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
4687#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
4688#define CAN_ECR_RXERRCNT_SHIFT (8U)
4689/*! RXERRCNT - Receive Error Counter
4690 */
4691#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
4692#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)
4693#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U)
4694/*! TXERRCNT_FAST - Transmit Error Counter for fast bits
4695 */
4696#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
4697#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)
4698#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U)
4699/*! RXERRCNT_FAST - Receive Error Counter for fast bits
4700 */
4701#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
4702/*! @} */
4703
4704/*! @name ESR1 - Error and Status 1 register */
4705/*! @{ */
4706#define CAN_ESR1_WAKINT_MASK (0x1U)
4707#define CAN_ESR1_WAKINT_SHIFT (0U)
4708/*! WAKINT - Wake-Up Interrupt
4709 * 0b0..No such occurrence.
4710 * 0b1..Indicates a recessive to dominant transition was received on the CAN bus.
4711 */
4712#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
4713#define CAN_ESR1_ERRINT_MASK (0x2U)
4714#define CAN_ESR1_ERRINT_SHIFT (1U)
4715/*! ERRINT - Error Interrupt
4716 * 0b0..No such occurrence.
4717 * 0b1..Indicates setting of any error bit in the Error and Status register.
4718 */
4719#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
4720#define CAN_ESR1_BOFFINT_MASK (0x4U)
4721#define CAN_ESR1_BOFFINT_SHIFT (2U)
4722/*! BOFFINT - Bus Off Interrupt
4723 * 0b0..No such occurrence.
4724 * 0b1..FlexCAN module entered Bus Off state.
4725 */
4726#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
4727#define CAN_ESR1_RX_MASK (0x8U)
4728#define CAN_ESR1_RX_SHIFT (3U)
4729/*! RX - FlexCAN In Reception
4730 * 0b0..FlexCAN is not receiving a message.
4731 * 0b1..FlexCAN is receiving a message.
4732 */
4733#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
4734#define CAN_ESR1_FLTCONF_MASK (0x30U)
4735#define CAN_ESR1_FLTCONF_SHIFT (4U)
4736/*! FLTCONF - Fault Confinement State
4737 * 0b00..Error Active
4738 * 0b01..Error Passive
4739 * 0b1x..Bus Off
4740 */
4741#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
4742#define CAN_ESR1_TX_MASK (0x40U)
4743#define CAN_ESR1_TX_SHIFT (6U)
4744/*! TX - FlexCAN In Transmission
4745 * 0b0..FlexCAN is not transmitting a message.
4746 * 0b1..FlexCAN is transmitting a message.
4747 */
4748#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
4749#define CAN_ESR1_IDLE_MASK (0x80U)
4750#define CAN_ESR1_IDLE_SHIFT (7U)
4751/*! IDLE - IDLE
4752 * 0b0..No such occurrence.
4753 * 0b1..CAN bus is now IDLE.
4754 */
4755#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
4756#define CAN_ESR1_RXWRN_MASK (0x100U)
4757#define CAN_ESR1_RXWRN_SHIFT (8U)
4758/*! RXWRN - Rx Error Warning
4759 * 0b0..No such occurrence.
4760 * 0b1..RXERRCNT is greater than or equal to 96.
4761 */
4762#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
4763#define CAN_ESR1_TXWRN_MASK (0x200U)
4764#define CAN_ESR1_TXWRN_SHIFT (9U)
4765/*! TXWRN - TX Error Warning
4766 * 0b0..No such occurrence.
4767 * 0b1..TXERRCNT is greater than or equal to 96.
4768 */
4769#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
4770#define CAN_ESR1_STFERR_MASK (0x400U)
4771#define CAN_ESR1_STFERR_SHIFT (10U)
4772/*! STFERR - Stuffing Error
4773 * 0b0..No such occurrence.
4774 * 0b1..A stuffing error occurred since last read of this register.
4775 */
4776#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
4777#define CAN_ESR1_FRMERR_MASK (0x800U)
4778#define CAN_ESR1_FRMERR_SHIFT (11U)
4779/*! FRMERR - Form Error
4780 * 0b0..No such occurrence.
4781 * 0b1..A Form Error occurred since last read of this register.
4782 */
4783#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
4784#define CAN_ESR1_CRCERR_MASK (0x1000U)
4785#define CAN_ESR1_CRCERR_SHIFT (12U)
4786/*! CRCERR - Cyclic Redundancy Check Error
4787 * 0b0..No such occurrence.
4788 * 0b1..A CRC error occurred since last read of this register.
4789 */
4790#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
4791#define CAN_ESR1_ACKERR_MASK (0x2000U)
4792#define CAN_ESR1_ACKERR_SHIFT (13U)
4793/*! ACKERR - Acknowledge Error
4794 * 0b0..No such occurrence.
4795 * 0b1..An ACK error occurred since last read of this register.
4796 */
4797#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
4798#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
4799#define CAN_ESR1_BIT0ERR_SHIFT (14U)
4800/*! BIT0ERR - Bit0 Error
4801 * 0b0..No such occurrence.
4802 * 0b1..At least one bit sent as dominant is received as recessive.
4803 */
4804#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
4805#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
4806#define CAN_ESR1_BIT1ERR_SHIFT (15U)
4807/*! BIT1ERR - Bit1 Error
4808 * 0b0..No such occurrence.
4809 * 0b1..At least one bit sent as recessive is received as dominant.
4810 */
4811#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
4812#define CAN_ESR1_RWRNINT_MASK (0x10000U)
4813#define CAN_ESR1_RWRNINT_SHIFT (16U)
4814/*! RWRNINT - Rx Warning Interrupt Flag
4815 * 0b0..No such occurrence.
4816 * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
4817 */
4818#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
4819#define CAN_ESR1_TWRNINT_MASK (0x20000U)
4820#define CAN_ESR1_TWRNINT_SHIFT (17U)
4821/*! TWRNINT - Tx Warning Interrupt Flag
4822 * 0b0..No such occurrence.
4823 * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
4824 */
4825#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
4826#define CAN_ESR1_SYNCH_MASK (0x40000U)
4827#define CAN_ESR1_SYNCH_SHIFT (18U)
4828/*! SYNCH - CAN Synchronization Status
4829 * 0b0..FlexCAN is not synchronized to the CAN bus.
4830 * 0b1..FlexCAN is synchronized to the CAN bus.
4831 */
4832#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
4833#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U)
4834#define CAN_ESR1_BOFFDONEINT_SHIFT (19U)
4835/*! BOFFDONEINT - Bus Off Done Interrupt
4836 * 0b0..No such occurrence.
4837 * 0b1..FlexCAN module has completed Bus Off process.
4838 */
4839#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
4840#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U)
4841#define CAN_ESR1_ERRINT_FAST_SHIFT (20U)
4842/*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
4843 * 0b0..No such occurrence.
4844 * 0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
4845 */
4846#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
4847#define CAN_ESR1_ERROVR_MASK (0x200000U)
4848#define CAN_ESR1_ERROVR_SHIFT (21U)
4849/*! ERROVR - Error Overrun
4850 * 0b0..Overrun has not occurred.
4851 * 0b1..Overrun has occurred.
4852 */
4853#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
4854#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U)
4855#define CAN_ESR1_STFERR_FAST_SHIFT (26U)
4856/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
4857 * 0b0..No such occurrence.
4858 * 0b1..A stuffing error occurred since last read of this register.
4859 */
4860#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
4861#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U)
4862#define CAN_ESR1_FRMERR_FAST_SHIFT (27U)
4863/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
4864 * 0b0..No such occurrence.
4865 * 0b1..A form error occurred since last read of this register.
4866 */
4867#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
4868#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U)
4869#define CAN_ESR1_CRCERR_FAST_SHIFT (28U)
4870/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
4871 * 0b0..No such occurrence.
4872 * 0b1..A CRC error occurred since last read of this register.
4873 */
4874#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
4875#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U)
4876#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U)
4877/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
4878 * 0b0..No such occurrence.
4879 * 0b1..At least one bit sent as dominant is received as recessive.
4880 */
4881#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
4882#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U)
4883#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U)
4884/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
4885 * 0b0..No such occurrence.
4886 * 0b1..At least one bit sent as recessive is received as dominant.
4887 */
4888#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
4889/*! @} */
4890
4891/*! @name IMASK2 - Interrupt Masks 2 register */
4892/*! @{ */
4893#define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU)
4894#define CAN_IMASK2_BUF63TO32M_SHIFT (0U)
4895/*! BUF63TO32M - Buffer MBi Mask
4896 */
4897#define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
4898/*! @} */
4899
4900/*! @name IMASK1 - Interrupt Masks 1 register */
4901/*! @{ */
4902#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)
4903#define CAN_IMASK1_BUF31TO0M_SHIFT (0U)
4904/*! BUF31TO0M - Buffer MBi Mask
4905 */
4906#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
4907/*! @} */
4908
4909/*! @name IFLAG2 - Interrupt Flags 2 register */
4910/*! @{ */
4911#define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU)
4912#define CAN_IFLAG2_BUF63TO32I_SHIFT (0U)
4913/*! BUF63TO32I - Buffer MBi Interrupt
4914 */
4915#define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
4916/*! @} */
4917
4918/*! @name IFLAG1 - Interrupt Flags 1 register */
4919/*! @{ */
4920#define CAN_IFLAG1_BUF0I_MASK (0x1U)
4921#define CAN_IFLAG1_BUF0I_SHIFT (0U)
4922/*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit
4923 * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
4924 * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
4925 */
4926#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
4927#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
4928#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
4929/*! BUF4TO1I - Buffer MBi Interrupt Or Reserved
4930 */
4931#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
4932#define CAN_IFLAG1_BUF5I_MASK (0x20U)
4933#define CAN_IFLAG1_BUF5I_SHIFT (5U)
4934/*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO
4935 * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
4936 * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when
4937 * MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
4938 */
4939#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4940#define CAN_IFLAG1_BUF6I_MASK (0x40U)
4941#define CAN_IFLAG1_BUF6I_SHIFT (6U)
4942/*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning
4943 * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
4944 * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
4945 */
4946#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4947#define CAN_IFLAG1_BUF7I_MASK (0x80U)
4948#define CAN_IFLAG1_BUF7I_SHIFT (7U)
4949/*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow
4950 * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
4951 * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
4952 */
4953#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4954#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
4955#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
4956/*! BUF31TO8I - Buffer MBi Interrupt
4957 */
4958#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
4959/*! @} */
4960
4961/*! @name CTRL2 - Control 2 register */
4962/*! @{ */
4963#define CAN_CTRL2_EDFLTDIS_MASK (0x800U)
4964#define CAN_CTRL2_EDFLTDIS_SHIFT (11U)
4965/*! EDFLTDIS - Edge Filter Disable
4966 * 0b0..Edge filter is enabled
4967 * 0b1..Edge filter is disabled
4968 */
4969#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
4970#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U)
4971#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U)
4972/*! ISOCANFDEN - ISO CAN FD Enable
4973 * 0b0..FlexCAN operates using the non-ISO CAN FD protocol.
4974 * 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
4975 */
4976#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
4977#define CAN_CTRL2_PREXCEN_MASK (0x4000U)
4978#define CAN_CTRL2_PREXCEN_SHIFT (14U)
4979/*! PREXCEN - Protocol Exception Enable
4980 * 0b0..Protocol exception is disabled.
4981 * 0b1..Protocol exception is enabled.
4982 */
4983#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
4984#define CAN_CTRL2_EACEN_MASK (0x10000U)
4985#define CAN_CTRL2_EACEN_SHIFT (16U)
4986/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
4987 * 0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
4988 * 0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
4989 * the incoming frame. Mask bits do apply.
4990 */
4991#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
4992#define CAN_CTRL2_RRS_MASK (0x20000U)
4993#define CAN_CTRL2_RRS_SHIFT (17U)
4994/*! RRS - Remote Request Storing
4995 * 0b0..Remote response frame is generated.
4996 * 0b1..Remote request frame is stored.
4997 */
4998#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
4999#define CAN_CTRL2_MRP_MASK (0x40000U)
5000#define CAN_CTRL2_MRP_SHIFT (18U)
5001/*! MRP - Mailboxes Reception Priority
5002 * 0b0..Matching starts from Rx FIFO and continues on mailboxes.
5003 * 0b1..Matching starts from mailboxes and continues on Rx FIFO.
5004 */
5005#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
5006#define CAN_CTRL2_TASD_MASK (0xF80000U)
5007#define CAN_CTRL2_TASD_SHIFT (19U)
5008/*! TASD - Tx Arbitration Start Delay
5009 */
5010#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
5011#define CAN_CTRL2_RFFN_MASK (0xF000000U)
5012#define CAN_CTRL2_RFFN_SHIFT (24U)
5013/*! RFFN - Number Of Rx FIFO Filters
5014 */
5015#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
5016#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)
5017#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)
5018/*! BOFFDONEMSK - Bus Off Done Interrupt Mask
5019 * 0b0..Bus off done interrupt disabled.
5020 * 0b1..Bus off done interrupt enabled.
5021 */
5022#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
5023#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U)
5024#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U)
5025/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
5026 * 0b0..ERRINT_FAST error interrupt disabled.
5027 * 0b1..ERRINT_FAST error interrupt enabled.
5028 */
5029#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
5030/*! @} */
5031
5032/*! @name ESR2 - Error and Status 2 register */
5033/*! @{ */
5034#define CAN_ESR2_IMB_MASK (0x2000U)
5035#define CAN_ESR2_IMB_SHIFT (13U)
5036/*! IMB - Inactive Mailbox
5037 * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
5038 * 0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
5039 */
5040#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
5041#define CAN_ESR2_VPS_MASK (0x4000U)
5042#define CAN_ESR2_VPS_SHIFT (14U)
5043/*! VPS - Valid Priority Status
5044 * 0b0..Contents of IMB and LPTM are invalid.
5045 * 0b1..Contents of IMB and LPTM are valid.
5046 */
5047#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
5048#define CAN_ESR2_LPTM_MASK (0x7F0000U)
5049#define CAN_ESR2_LPTM_SHIFT (16U)
5050/*! LPTM - Lowest Priority Tx Mailbox
5051 */
5052#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
5053/*! @} */
5054
5055/*! @name CRCR - CRC register */
5056/*! @{ */
5057#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
5058#define CAN_CRCR_TXCRC_SHIFT (0U)
5059/*! TXCRC - Transmitted CRC value
5060 */
5061#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
5062#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
5063#define CAN_CRCR_MBCRC_SHIFT (16U)
5064/*! MBCRC - CRC Mailbox
5065 */
5066#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
5067/*! @} */
5068
5069/*! @name RXFGMASK - Rx FIFO Global Mask register */
5070/*! @{ */
5071#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
5072#define CAN_RXFGMASK_FGM_SHIFT (0U)
5073/*! FGM - Rx FIFO Global Mask Bits
5074 */
5075#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
5076/*! @} */
5077
5078/*! @name RXFIR - Rx FIFO Information register */
5079/*! @{ */
5080#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
5081#define CAN_RXFIR_IDHIT_SHIFT (0U)
5082/*! IDHIT - Identifier Acceptance Filter Hit Indicator
5083 */
5084#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
5085/*! @} */
5086
5087/*! @name CBT - CAN Bit Timing register */
5088/*! @{ */
5089#define CAN_CBT_EPSEG2_MASK (0x1FU)
5090#define CAN_CBT_EPSEG2_SHIFT (0U)
5091/*! EPSEG2 - Extended Phase Segment 2
5092 */
5093#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
5094#define CAN_CBT_EPSEG1_MASK (0x3E0U)
5095#define CAN_CBT_EPSEG1_SHIFT (5U)
5096/*! EPSEG1 - Extended Phase Segment 1
5097 */
5098#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
5099#define CAN_CBT_EPROPSEG_MASK (0xFC00U)
5100#define CAN_CBT_EPROPSEG_SHIFT (10U)
5101/*! EPROPSEG - Extended Propagation Segment
5102 */
5103#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
5104#define CAN_CBT_ERJW_MASK (0x1F0000U)
5105#define CAN_CBT_ERJW_SHIFT (16U)
5106/*! ERJW - Extended Resync Jump Width
5107 */
5108#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
5109#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U)
5110#define CAN_CBT_EPRESDIV_SHIFT (21U)
5111/*! EPRESDIV - Extended Prescaler Division Factor
5112 */
5113#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
5114#define CAN_CBT_BTF_MASK (0x80000000U)
5115#define CAN_CBT_BTF_SHIFT (31U)
5116/*! BTF - Bit Timing Format Enable
5117 * 0b0..Extended bit time definitions disabled.
5118 * 0b1..Extended bit time definitions enabled.
5119 */
5120#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
5121/*! @} */
5122
5123/*! @name DBG1 - Debug 1 register */
5124/*! @{ */
5125#define CAN_DBG1_CFSM_MASK (0x7FU)
5126#define CAN_DBG1_CFSM_SHIFT (0U)
5127/*! CFSM - CAN Finite State Machine
5128 */
5129#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
5130#define CAN_DBG1_CBN_MASK (0x3FF0000U)
5131#define CAN_DBG1_CBN_SHIFT (16U)
5132/*! CBN - CAN Bit Number
5133 */
5134#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
5135/*! @} */
5136
5137/*! @name DBG2 - Debug 2 register */
5138/*! @{ */
5139#define CAN_DBG2_RMP_MASK (0x7FU)
5140#define CAN_DBG2_RMP_SHIFT (0U)
5141/*! RMP - Rx Matching Pointer
5142 */
5143#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
5144#define CAN_DBG2_MPP_MASK (0x80U)
5145#define CAN_DBG2_MPP_SHIFT (7U)
5146/*! MPP - Matching Process in Progress
5147 * 0b0..No matching process ongoing
5148 * 0b1..Matching process is in progress.
5149 */
5150#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
5151#define CAN_DBG2_TAP_MASK (0x7F00U)
5152#define CAN_DBG2_TAP_SHIFT (8U)
5153/*! TAP - Tx Arbitration Pointer
5154 */
5155#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
5156#define CAN_DBG2_APP_MASK (0x8000U)
5157#define CAN_DBG2_APP_SHIFT (15U)
5158/*! APP - Arbitration Process in Progress
5159 * 0b0..No arbitration process ongoing
5160 * 0b1..Arbitration process is in progress.
5161 */
5162#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
5163/*! @} */
5164
5165/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
5166/*! @{ */
5167#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
5168#define CAN_CS_TIME_STAMP_SHIFT (0U)
5169/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
5170 * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
5171 * appears on the CAN bus.
5172 */
5173#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
5174#define CAN_CS_DLC_MASK (0xF0000U)
5175#define CAN_CS_DLC_SHIFT (16U)
5176/*! DLC - Length of the data to be stored/transmitted.
5177 */
5178#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
5179#define CAN_CS_RTR_MASK (0x100000U)
5180#define CAN_CS_RTR_SHIFT (20U)
5181/*! RTR - Remote Transmission Request. One/zero for remote/data frame.
5182 */
5183#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
5184#define CAN_CS_IDE_MASK (0x200000U)
5185#define CAN_CS_IDE_SHIFT (21U)
5186/*! IDE - ID Extended. One/zero for extended/standard format frame.
5187 */
5188#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
5189#define CAN_CS_SRR_MASK (0x400000U)
5190#define CAN_CS_SRR_SHIFT (22U)
5191/*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
5192 */
5193#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
5194#define CAN_CS_CODE_MASK (0xF000000U)
5195#define CAN_CS_CODE_SHIFT (24U)
5196/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
5197 * the FlexCAN module itself, as part of the message buffer matching and arbitration process.
5198 */
5199#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
5200#define CAN_CS_ESI_MASK (0x20000000U)
5201#define CAN_CS_ESI_SHIFT (29U)
5202/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
5203 */
5204#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
5205#define CAN_CS_BRS_MASK (0x40000000U)
5206#define CAN_CS_BRS_SHIFT (30U)
5207/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
5208 */
5209#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
5210#define CAN_CS_EDL_MASK (0x80000000U)
5211#define CAN_CS_EDL_SHIFT (31U)
5212/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
5213 * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
5214 */
5215#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
5216/*! @} */
5217
5218/* The count of CAN_CS */
5219#define CAN_CS_COUNT (64U)
5220
5221/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
5222/*! @{ */
5223#define CAN_ID_EXT_MASK (0x3FFFFU)
5224#define CAN_ID_EXT_SHIFT (0U)
5225/*! EXT - Contains extended (LOW word) identifier of message buffer.
5226 */
5227#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
5228#define CAN_ID_STD_MASK (0x1FFC0000U)
5229#define CAN_ID_STD_SHIFT (18U)
5230/*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
5231 */
5232#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
5233#define CAN_ID_PRIO_MASK (0xE0000000U)
5234#define CAN_ID_PRIO_SHIFT (29U)
5235/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
5236 * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
5237 * ID to define the transmission priority.
5238 */
5239#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
5240/*! @} */
5241
5242/* The count of CAN_ID */
5243#define CAN_ID_COUNT (64U)
5244
5245/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
5246/*! @{ */
5247#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
5248#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
5249/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
5250 */
5251#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
5252#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
5253#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
5254/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
5255 */
5256#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
5257#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
5258#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
5259/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
5260 */
5261#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
5262#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
5263#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
5264/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
5265 */
5266#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
5267/*! @} */
5268
5269/* The count of CAN_WORD0 */
5270#define CAN_WORD0_COUNT (64U)
5271
5272/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
5273/*! @{ */
5274#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
5275#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
5276/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
5277 */
5278#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
5279#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
5280#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
5281/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
5282 */
5283#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
5284#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
5285#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
5286/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
5287 */
5288#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
5289#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
5290#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
5291/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
5292 */
5293#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
5294/*! @} */
5295
5296/* The count of CAN_WORD1 */
5297#define CAN_WORD1_COUNT (64U)
5298
5299/*! @name RXIMR - Rx Individual Mask registers */
5300/*! @{ */
5301#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
5302#define CAN_RXIMR_MI_SHIFT (0U)
5303/*! MI - Individual Mask Bits
5304 */
5305#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
5306/*! @} */
5307
5308/* The count of CAN_RXIMR */
5309#define CAN_RXIMR_COUNT (64U)
5310
5311/*! @name FDCTRL - CAN FD Control register */
5312/*! @{ */
5313#define CAN_FDCTRL_TDCVAL_MASK (0x3FU)
5314#define CAN_FDCTRL_TDCVAL_SHIFT (0U)
5315/*! TDCVAL - Transceiver Delay Compensation Value
5316 */
5317#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
5318#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U)
5319#define CAN_FDCTRL_TDCOFF_SHIFT (8U)
5320/*! TDCOFF - Transceiver Delay Compensation Offset
5321 */
5322#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
5323#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U)
5324#define CAN_FDCTRL_TDCFAIL_SHIFT (14U)
5325/*! TDCFAIL - Transceiver Delay Compensation Fail
5326 * 0b0..Measured loop delay is in range.
5327 * 0b1..Measured loop delay is out of range.
5328 */
5329#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
5330#define CAN_FDCTRL_TDCEN_MASK (0x8000U)
5331#define CAN_FDCTRL_TDCEN_SHIFT (15U)
5332/*! TDCEN - Transceiver Delay Compensation Enable
5333 * 0b0..TDC is disabled
5334 * 0b1..TDC is enabled
5335 */
5336#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
5337#define CAN_FDCTRL_MBDSR0_MASK (0x30000U)
5338#define CAN_FDCTRL_MBDSR0_SHIFT (16U)
5339/*! MBDSR0 - Message Buffer Data Size for Region 0
5340 * 0b00..Selects 8 bytes per message buffer.
5341 * 0b01..Selects 16 bytes per message buffer.
5342 * 0b10..Selects 32 bytes per message buffer.
5343 * 0b11..Selects 64 bytes per message buffer.
5344 */
5345#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
5346#define CAN_FDCTRL_MBDSR1_MASK (0x180000U)
5347#define CAN_FDCTRL_MBDSR1_SHIFT (19U)
5348/*! MBDSR1 - Message Buffer Data Size for Region 1
5349 * 0b00..Selects 8 bytes per message buffer.
5350 * 0b01..Selects 16 bytes per message buffer.
5351 * 0b10..Selects 32 bytes per message buffer.
5352 * 0b11..Selects 64 bytes per message buffer.
5353 */
5354#define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
5355#define CAN_FDCTRL_FDRATE_MASK (0x80000000U)
5356#define CAN_FDCTRL_FDRATE_SHIFT (31U)
5357/*! FDRATE - Bit Rate Switch Enable
5358 * 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
5359 * 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
5360 */
5361#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
5362/*! @} */
5363
5364/*! @name FDCBT - CAN FD Bit Timing register */
5365/*! @{ */
5366#define CAN_FDCBT_FPSEG2_MASK (0x7U)
5367#define CAN_FDCBT_FPSEG2_SHIFT (0U)
5368/*! FPSEG2 - Fast Phase Segment 2
5369 */
5370#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
5371#define CAN_FDCBT_FPSEG1_MASK (0xE0U)
5372#define CAN_FDCBT_FPSEG1_SHIFT (5U)
5373/*! FPSEG1 - Fast Phase Segment 1
5374 */
5375#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
5376#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U)
5377#define CAN_FDCBT_FPROPSEG_SHIFT (10U)
5378/*! FPROPSEG - Fast Propagation Segment
5379 */
5380#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
5381#define CAN_FDCBT_FRJW_MASK (0x70000U)
5382#define CAN_FDCBT_FRJW_SHIFT (16U)
5383/*! FRJW - Fast Resync Jump Width
5384 */
5385#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
5386#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U)
5387#define CAN_FDCBT_FPRESDIV_SHIFT (20U)
5388/*! FPRESDIV - Fast Prescaler Division Factor
5389 */
5390#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
5391/*! @} */
5392
5393/*! @name FDCRC - CAN FD CRC register */
5394/*! @{ */
5395#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU)
5396#define CAN_FDCRC_FD_TXCRC_SHIFT (0U)
5397/*! FD_TXCRC - Extended Transmitted CRC value
5398 */
5399#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
5400#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U)
5401#define CAN_FDCRC_FD_MBCRC_SHIFT (24U)
5402/*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC
5403 */
5404#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
5405/*! @} */
5406
5407
5408/*!
5409 * @}
5410 */ /* end of group CAN_Register_Masks */
5411
5412
5413/* CAN - Peripheral instance base addresses */
5414/** Peripheral ADMA__CAN0 base address */
5415#define ADMA__CAN0_BASE (0x5A8D0000u)
5416/** Peripheral ADMA__CAN0 base pointer */
5417#define ADMA__CAN0 ((CAN_Type *)ADMA__CAN0_BASE)
5418/** Peripheral ADMA__CAN1 base address */
5419#define ADMA__CAN1_BASE (0x5A8E0000u)
5420/** Peripheral ADMA__CAN1 base pointer */
5421#define ADMA__CAN1 ((CAN_Type *)ADMA__CAN1_BASE)
5422/** Peripheral ADMA__CAN2 base address */
5423#define ADMA__CAN2_BASE (0x5A8F0000u)
5424/** Peripheral ADMA__CAN2 base pointer */
5425#define ADMA__CAN2 ((CAN_Type *)ADMA__CAN2_BASE)
5426/** Array initializer of CAN peripheral base addresses */
5427#define CAN_BASE_ADDRS { ADMA__CAN0_BASE, ADMA__CAN1_BASE, ADMA__CAN2_BASE }
5428/** Array initializer of CAN peripheral base pointers */
5429#define CAN_BASE_PTRS { ADMA__CAN0, ADMA__CAN1, ADMA__CAN2 }
5430/** Interrupt vectors for the CAN peripheral type */
5431#define CAN_Rx_Warning_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5432#define CAN_Tx_Warning_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5433#define CAN_Wake_Up_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5434#define CAN_Error_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5435#define CAN_Bus_Off_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5436#define CAN_ORed_Message_buffer_IRQS { ADMA_FLEXCAN0_INT_IRQn, ADMA_FLEXCAN1_INT_IRQn, ADMA_FLEXCAN2_INT_IRQn }
5437
5438/*!
5439 * @}
5440 */ /* end of group CAN_Peripheral_Access_Layer */
5441
5442
5443/* ----------------------------------------------------------------------------
5444 -- CI_PI_CSR Peripheral Access Layer
5445 ---------------------------------------------------------------------------- */
5446
5447/*!
5448 * @addtogroup CI_PI_CSR_Peripheral_Access_Layer CI_PI_CSR Peripheral Access Layer
5449 * @{
5450 */
5451
5452/** CI_PI_CSR - Register Layout Typedef */
5453typedef struct {
5454 struct { /* offset: 0x0 */
5455 __IO uint32_t RW; /**< CI_PI Interface Control Register, offset: 0x0 */
5456 __IO uint32_t SET; /**< CI_PI Interface Control Register, offset: 0x4 */
5457 __IO uint32_t CLR; /**< CI_PI Interface Control Register, offset: 0x8 */
5458 __IO uint32_t TOG; /**< CI_PI Interface Control Register, offset: 0xC */
5459 } IF_CTRL_REG;
5460 struct { /* offset: 0x10 */
5461 __IO uint32_t RW; /**< CSI Interface Control Register, offset: 0x10 */
5462 __IO uint32_t SET; /**< CSI Interface Control Register, offset: 0x14 */
5463 __IO uint32_t CLR; /**< CSI Interface Control Register, offset: 0x18 */
5464 __IO uint32_t TOG; /**< CSI Interface Control Register, offset: 0x1C */
5465 } CSI_CTRL_REG;
5466 struct { /* offset: 0x20 */
5467 __I uint32_t RW; /**< CSI Interface Status Register, offset: 0x20 */
5468 __I uint32_t SET; /**< CSI Interface Status Register, offset: 0x24 */
5469 __I uint32_t CLR; /**< CSI Interface Status Register, offset: 0x28 */
5470 __I uint32_t TOG; /**< CSI Interface Status Register, offset: 0x2C */
5471 } CSI_STATUS;
5472 struct { /* offset: 0x30 */
5473 __IO uint32_t RW; /**< CSI Interface Control Register1, offset: 0x30 */
5474 __IO uint32_t SET; /**< CSI Interface Control Register1, offset: 0x34 */
5475 __IO uint32_t CLR; /**< CSI Interface Control Register1, offset: 0x38 */
5476 __IO uint32_t TOG; /**< CSI Interface Control Register1, offset: 0x3C */
5477 } CSI_CTRL_REG1;
5478} CI_PI_CSR_Type;
5479
5480/* ----------------------------------------------------------------------------
5481 -- CI_PI_CSR Register Masks
5482 ---------------------------------------------------------------------------- */
5483
5484/*!
5485 * @addtogroup CI_PI_CSR_Register_Masks CI_PI_CSR Register Masks
5486 * @{
5487 */
5488
5489/*! @name IF_CTRL_REG - CI_PI Interface Control Register */
5490/*! @{ */
5491#define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK (0x1U)
5492#define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_SHIFT (0U)
5493#define CI_PI_CSR_IF_CTRL_REG_PL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_ENABLE_MASK)
5494#define CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK (0x2U)
5495#define CI_PI_CSR_IF_CTRL_REG_PL_VALID_SHIFT (1U)
5496#define CI_PI_CSR_IF_CTRL_REG_PL_VALID(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_VALID_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_VALID_MASK)
5497#define CI_PI_CSR_IF_CTRL_REG_PL_ADDR_MASK (0x1CU)
5498#define CI_PI_CSR_IF_CTRL_REG_PL_ADDR_SHIFT (2U)
5499#define CI_PI_CSR_IF_CTRL_REG_PL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_PL_ADDR_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_PL_ADDR_MASK)
5500#define CI_PI_CSR_IF_CTRL_REG_IF_FORCE_MASK (0xE0U)
5501#define CI_PI_CSR_IF_CTRL_REG_IF_FORCE_SHIFT (5U)
5502#define CI_PI_CSR_IF_CTRL_REG_IF_FORCE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_IF_FORCE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_IF_FORCE_MASK)
5503#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_MASK (0x100U)
5504#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT (8U)
5505/*! DATA_TYPE_SEL - Pixel link data type select
5506 * 0b0..PL data type comes from the csi_interface
5507 * 0b1..PL data type comes from IF_CTRL DATA_TYPE[4:0]
5508 */
5509#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SEL_MASK)
5510#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_MASK (0x3E00U)
5511#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SHIFT (9U)
5512/*! DATA_TYPE - Data type
5513 * 0b00000..Null data
5514 * 0b00100..RGB format
5515 * 0b01000..YUV444 Format
5516 * 0b10000..YYU420 odd line
5517 * 0b10010..YYU420 even line
5518 * 0b11000..YYY odd line
5519 * 0b11010..UYVY Even line
5520 * 0b11100..Raw
5521 */
5522#define CI_PI_CSR_IF_CTRL_REG_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_SHIFT)) & CI_PI_CSR_IF_CTRL_REG_DATA_TYPE_MASK)
5523/*! @} */
5524
5525/*! @name CSI_CTRL_REG - CSI Interface Control Register */
5526/*! @{ */
5527#define CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK (0x1U)
5528#define CI_PI_CSR_CSI_CTRL_REG_CSI_EN_SHIFT (0U)
5529/*! CSI_EN - CSI interface enable
5530 */
5531#define CI_PI_CSR_CSI_CTRL_REG_CSI_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CSI_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CSI_EN_MASK)
5532#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_MASK (0x2U)
5533#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_SHIFT (1U)
5534/*! PIXEL_CLK_POL - Pixel Clock polarity control
5535 * 0b0..Pixel Clock input is not inverted
5536 * 0b1..Pixel Clock input is inverted
5537 */
5538#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_MASK)
5539#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_MASK (0x4U)
5540#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_SHIFT (2U)
5541/*! HSYNC_POL - HSYNC polarity control
5542 * 0b0..HSYNC output to Pixel Link is not inverted
5543 * 0b1..HSYNC output to Pixel Link is inverted
5544 */
5545#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_MASK)
5546#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_MASK (0x8U)
5547#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_SHIFT (3U)
5548/*! VSYNC_POL - VSYNC polarity control
5549 * 0b0..VSYNC output to Pixel Link is not inverted
5550 * 0b1..VSYNC output to Pixel Link is inverted
5551 */
5552#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_MASK)
5553#define CI_PI_CSR_CSI_CTRL_REG_DE_POL_MASK (0x10U)
5554#define CI_PI_CSR_CSI_CTRL_REG_DE_POL_SHIFT (4U)
5555/*! DE_POL - DE polarity control
5556 * 0b0..DE output to Pixel Link is not inverted
5557 * 0b1..DE output to Pixel Link is inverted
5558 */
5559#define CI_PI_CSR_CSI_CTRL_REG_DE_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_DE_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_DE_POL_MASK)
5560#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_MASK (0x20U)
5561#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_SHIFT (5U)
5562/*! PIXEL_DATA_POL - PIXEL_DATA polarity control
5563 * 0b0..PIXEL_DATA output to Pixel Link is not inverted
5564 * 0b1..PIXEL_DATA output to Pixel Link is inverted
5565 */
5566#define CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_PIXEL_DATA_POL_MASK)
5567#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK (0x40U)
5568#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT (6U)
5569/*! CCIR_EXT_VSYNC_EN - External VSYNC enable
5570 */
5571#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_EXT_VSYNC_EN_MASK)
5572#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_MASK (0x80U)
5573#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_SHIFT (7U)
5574/*! CCIR_EN - CCIR mode enable
5575 * 0b0..CCIR mode disable
5576 * 0b1..CCIR mode enable
5577 */
5578#define CI_PI_CSR_CSI_CTRL_REG_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_MASK)
5579#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_MASK (0x100U)
5580#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_SHIFT (8U)
5581/*! CCIR_VIDEO_MODE - CCIR_VIDEO_MODE
5582 * 0b0..Progressive mode
5583 * 0b1..Interlace mode
5584 */
5585#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_VIDEO_MODE_MASK)
5586#define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_MASK (0x200U)
5587#define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_SHIFT (9U)
5588/*! CCIR_NTSC_EN - CCIR_NTSC enable
5589 * 0b0..PAL
5590 * 0b1..NTSC
5591 */
5592#define CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_NTSC_EN_MASK)
5593#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_MASK (0x400U)
5594#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_SHIFT (10U)
5595/*! CCIR_VSYNC_RESET_EN - CCIR_VSYNC_RESET_EN
5596 */
5597#define CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_VSYNC_RESET_EN_MASK)
5598#define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_MASK (0x800U)
5599#define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_SHIFT (11U)
5600/*! CCIR_ECC_ERR_CORRECT_EN - CCIR_ECC_ERR_CORRECT_EN
5601 * 0b0..ECC error correction is disabled.
5602 * 0b1..ECC error correction is enabled.
5603 */
5604#define CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_CCIR_ECC_ERR_CORRECT_EN_MASK)
5605#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK (0x1000U)
5606#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_SHIFT (12U)
5607/*! HSYNC_FORCE_EN - HSYNC_FORCE_EN
5608 * 0b0..Do not override HSYNC
5609 * 0b1..Override HSYNC
5610 */
5611#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_FORCE_EN_MASK)
5612#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_MASK (0x2000U)
5613#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_SHIFT (13U)
5614/*! VSYNC_FORCE_EN - VSYNC_FORCE_EN
5615 * 0b0..Do not override VSYNC
5616 * 0b1..Override VSYNC
5617 */
5618#define CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VSYNC_FORCE_EN_MASK)
5619#define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK (0x4000U)
5620#define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_SHIFT (14U)
5621/*! GCLK_MODE_EN - GCLK_MODE_EN
5622 * 0b0..Disable
5623 * 0b1..Enable
5624 */
5625#define CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK)
5626#define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_MASK (0x8000U)
5627#define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_SHIFT (15U)
5628/*! VALID_SEL - VALID_SEL
5629 */
5630#define CI_PI_CSR_CSI_CTRL_REG_VALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_MASK)
5631#define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_MASK (0x10000U)
5632#define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_SHIFT (16U)
5633/*! RAW_OUT_SEL - RAW_OUT_SEL
5634 * 0b0..Right justified output
5635 * 0b1..Left justified to 14bit output
5636 */
5637#define CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_RAW_OUT_SEL_MASK)
5638#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_MASK (0x20000U)
5639#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_SHIFT (17U)
5640/*! HSYNC_OUT_SEL - HSYNC_OUT_SEL
5641 * 0b0..HSYNC output level
5642 * 0b1..HSYNC output pulse
5643 */
5644#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_OUT_SEL_MASK)
5645#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_MASK (0x380000U)
5646#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_SHIFT (19U)
5647/*! HSYNC_PULSE - HSYNC_PULSE
5648 */
5649#define CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_HSYNC_PULSE_MASK)
5650#define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_MASK (0x400000U)
5651#define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_SHIFT (22U)
5652/*! UV_SWAP_EN - UV Swap enable
5653 * 0b0..UV swap disable
5654 * 0b1..UV swap enable
5655 */
5656#define CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_UV_SWAP_EN_MASK)
5657#define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_MASK (0x7800000U)
5658#define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_SHIFT (23U)
5659/*! DATA_TYPE_IN - CSI input data type
5660 * 0b0000..UYVY bt656 8bit
5661 * 0b0001..UYVY bt656 10bit
5662 * 0b0010..RGB 8bit
5663 * 0b0011..BGR 8bit
5664 * 0b0100..RGB 24bit
5665 * 0b0101..YVYU 8bit
5666 * 0b0110..YUV 8bit
5667 * 0b0111..YVYU 16bit
5668 * 0b1000..YUV 24bit
5669 * 0b1001..Bayer 8bit
5670 * 0b1010..Bayer 10bit
5671 * 0b1011..Bayer 12bit
5672 * 0b1100..Bayer 16bit
5673 */
5674#define CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_DATA_TYPE_IN_MASK)
5675#define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_MASK (0x18000000U)
5676#define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_SHIFT (27U)
5677/*! MASK_VSYNC_COUNTER - CSI mask VSYNC counter
5678 * 0b00..not mask
5679 * 0b01..mask 1 frame
5680 * 0b10..mask 2 frames
5681 * 0b11..mask 3 frames
5682 */
5683#define CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_MASK_VSYNC_COUNTER_MASK)
5684#define CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK (0x80000000U)
5685#define CI_PI_CSR_CSI_CTRL_REG_SOFTRST_SHIFT (31U)
5686/*! SOFTRST - SOFTRST
5687 */
5688#define CI_PI_CSR_CSI_CTRL_REG_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG_SOFTRST_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK)
5689/*! @} */
5690
5691/*! @name CSI_STATUS - CSI Interface Status Register */
5692/*! @{ */
5693#define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_MASK (0x1U)
5694#define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_SHIFT (0U)
5695#define CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_SHIFT)) & CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_MASK)
5696#define CI_PI_CSR_CSI_STATUS_ECC_ERROR_MASK (0x2U)
5697#define CI_PI_CSR_CSI_STATUS_ECC_ERROR_SHIFT (1U)
5698#define CI_PI_CSR_CSI_STATUS_ECC_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_STATUS_ECC_ERROR_SHIFT)) & CI_PI_CSR_CSI_STATUS_ECC_ERROR_MASK)
5699/*! @} */
5700
5701/*! @name CSI_CTRL_REG1 - CSI Interface Control Register1 */
5702/*! @{ */
5703#define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_MASK (0xFFFFU)
5704#define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_SHIFT (0U)
5705/*! PIXEL_WIDTH - CSI interface enable
5706 */
5707#define CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG1_PIXEL_WIDTH_MASK)
5708#define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_MASK (0xFFFF0000U)
5709#define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_SHIFT (16U)
5710/*! VSYNC_PULSE - VSYNC_PULSE
5711 */
5712#define CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE(x) (((uint32_t)(((uint32_t)(x)) << CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_SHIFT)) & CI_PI_CSR_CSI_CTRL_REG1_VSYNC_PULSE_MASK)
5713/*! @} */
5714
5715
5716/*!
5717 * @}
5718 */ /* end of group CI_PI_CSR_Register_Masks */
5719
5720
5721/* CI_PI_CSR - Peripheral instance base addresses */
5722/** Peripheral CI_PI_CSR base address */
5723#define CI_PI_CSR_BASE (0x58261000u)
5724/** Peripheral CI_PI_CSR base pointer */
5725#define CI_PI_CSR ((CI_PI_CSR_Type *)CI_PI_CSR_BASE)
5726/** Array initializer of CI_PI_CSR peripheral base addresses */
5727#define CI_PI_CSR_BASE_ADDRS { CI_PI_CSR_BASE }
5728/** Array initializer of CI_PI_CSR peripheral base pointers */
5729#define CI_PI_CSR_BASE_PTRS { CI_PI_CSR }
5730
5731/*!
5732 * @}
5733 */ /* end of group CI_PI_CSR_Peripheral_Access_Layer */
5734
5735
5736/* ----------------------------------------------------------------------------
5737 -- CM4_LPCG_LPI2C Peripheral Access Layer
5738 ---------------------------------------------------------------------------- */
5739
5740/*!
5741 * @addtogroup CM4_LPCG_LPI2C_Peripheral_Access_Layer CM4_LPCG_LPI2C Peripheral Access Layer
5742 * @{
5743 */
5744
5745/** CM4_LPCG_LPI2C - Register Layout Typedef */
5746typedef struct {
5747 __IO uint32_t LPCG_LPI2C_0; /**< na, offset: 0x0 */
5748} CM4_LPCG_LPI2C_Type;
5749
5750/* ----------------------------------------------------------------------------
5751 -- CM4_LPCG_LPI2C Register Masks
5752 ---------------------------------------------------------------------------- */
5753
5754/*!
5755 * @addtogroup CM4_LPCG_LPI2C_Register_Masks CM4_LPCG_LPI2C Register Masks
5756 * @{
5757 */
5758
5759/*! @name LPCG_LPI2C_0 - na */
5760/*! @{ */
5761#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK (0x1U)
5762#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT (0U)
5763/*! lpi2c1_lpi2c_div_clk_HWEN - Hardware Enable
5764 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
5765 * 0b1..Enable HW automatic gating
5766 */
5767#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_div_clk_HWEN_MASK)
5768#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK (0x2U)
5769#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT (1U)
5770/*! lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN - Software Enable
5771 * 0b0..Disable SW clock regardless of HWEN
5772 * 0b1..Enable SW clock gating
5773 */
5774#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_SWEN_AND_lpi2c1_lpi2c_div_clk_SWEN_MASK)
5775#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK (0x4U)
5776#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT (2U)
5777/*! LPCG_LPI2C_0_reserved_2_2 - reserved
5778 */
5779#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_2_2_MASK)
5780#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK (0x8U)
5781#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT (3U)
5782/*! lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP - show clock root status, 1 means clock stopped
5783 */
5784#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_lpi2c_clk_STOP_AND_lpi2c1_lpi2c_div_clk_STOP_MASK)
5785#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK (0x10U)
5786#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT (4U)
5787/*! LPCG_LPI2C_0_reserved_4_4 - reserved
5788 */
5789#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_4_4_MASK)
5790#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK (0x20U)
5791#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT (5U)
5792/*! lpi2c1_ipg_clk_SWEN - Software Enable
5793 * 0b0..Disable SW clock regardless of HWEN
5794 * 0b1..Enable SW clock gating
5795 */
5796#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_SWEN_MASK)
5797#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK (0x40U)
5798#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT (6U)
5799/*! LPCG_LPI2C_0_reserved_6_6 - reserved
5800 */
5801#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_6_6_MASK)
5802#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK (0x80U)
5803#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT (7U)
5804/*! lpi2c1_ipg_clk_STOP - show clock root status, 1 means clock stopped
5805 */
5806#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_lpi2c1_ipg_clk_STOP_MASK)
5807#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK (0xFFFFFF00U)
5808#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT (8U)
5809/*! LPCG_LPI2C_0_reserved_8_31 - reserved
5810 */
5811#define CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPI2C_LPCG_LPI2C_0_LPCG_LPI2C_0_reserved_8_31_MASK)
5812/*! @} */
5813
5814
5815/*!
5816 * @}
5817 */ /* end of group CM4_LPCG_LPI2C_Register_Masks */
5818
5819
5820/* CM4_LPCG_LPI2C - Peripheral instance base addresses */
5821/** Peripheral CM4__LPCG_LPI2C base address */
5822#define CM4__LPCG_LPI2C_BASE (0x41630000u)
5823/** Peripheral CM4__LPCG_LPI2C base pointer */
5824#define CM4__LPCG_LPI2C ((CM4_LPCG_LPI2C_Type *)CM4__LPCG_LPI2C_BASE)
5825/** Array initializer of CM4_LPCG_LPI2C peripheral base addresses */
5826#define CM4_LPCG_LPI2C_BASE_ADDRS { CM4__LPCG_LPI2C_BASE }
5827/** Array initializer of CM4_LPCG_LPI2C peripheral base pointers */
5828#define CM4_LPCG_LPI2C_BASE_PTRS { CM4__LPCG_LPI2C }
5829
5830/*!
5831 * @}
5832 */ /* end of group CM4_LPCG_LPI2C_Peripheral_Access_Layer */
5833
5834
5835/* ----------------------------------------------------------------------------
5836 -- CM4_LPCG_LPIT Peripheral Access Layer
5837 ---------------------------------------------------------------------------- */
5838
5839/*!
5840 * @addtogroup CM4_LPCG_LPIT_Peripheral_Access_Layer CM4_LPCG_LPIT Peripheral Access Layer
5841 * @{
5842 */
5843
5844/** CM4_LPCG_LPIT - Register Layout Typedef */
5845typedef struct {
5846 __IO uint32_t LPCG_LPIT_0; /**< na, offset: 0x0 */
5847} CM4_LPCG_LPIT_Type;
5848
5849/* ----------------------------------------------------------------------------
5850 -- CM4_LPCG_LPIT Register Masks
5851 ---------------------------------------------------------------------------- */
5852
5853/*!
5854 * @addtogroup CM4_LPCG_LPIT_Register_Masks CM4_LPCG_LPIT Register Masks
5855 * @{
5856 */
5857
5858/*! @name LPCG_LPIT_0 - na */
5859/*! @{ */
5860#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK (0x1U)
5861#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT (0U)
5862/*! lpit1_ipg_per_clk_HWEN - Hardware Enable
5863 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
5864 * 0b1..Enable HW automatic gating
5865 */
5866#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_HWEN_MASK)
5867#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK (0x2U)
5868#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT (1U)
5869/*! lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN - Software Enable
5870 * 0b0..Disable SW clock regardless of HWEN
5871 * 0b1..Enable SW clock gating
5872 */
5873#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_SWEN_AND_lpit1_ipg_ungated_per_clk_SWEN_MASK)
5874#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK (0x4U)
5875#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT (2U)
5876/*! LPCG_LPIT_0_reserved_2_2 - reserved
5877 */
5878#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_2_2_MASK)
5879#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK (0x8U)
5880#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT (3U)
5881/*! lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP - show clock root status, 1 means clock stopped
5882 */
5883#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_per_clk_STOP_AND_lpit1_ipg_ungated_per_clk_STOP_MASK)
5884#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK (0x10U)
5885#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT (4U)
5886/*! LPCG_LPIT_0_reserved_4_4 - reserved
5887 */
5888#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_4_4_MASK)
5889#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK (0x20U)
5890#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT (5U)
5891/*! lpit1_ipg_clk_SWEN - Software Enable
5892 * 0b0..Disable SW clock regardless of HWEN
5893 * 0b1..Enable SW clock gating
5894 */
5895#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_SWEN_MASK)
5896#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK (0x40U)
5897#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT (6U)
5898/*! LPCG_LPIT_0_reserved_6_6 - reserved
5899 */
5900#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_6_6_MASK)
5901#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK (0x80U)
5902#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT (7U)
5903/*! lpit1_ipg_clk_STOP - show clock root status, 1 means clock stopped
5904 */
5905#define CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_lpit1_ipg_clk_STOP_MASK)
5906#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK (0xFFFFFF00U)
5907#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT (8U)
5908/*! LPCG_LPIT_0_reserved_8_31 - reserved
5909 */
5910#define CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPIT_LPCG_LPIT_0_LPCG_LPIT_0_reserved_8_31_MASK)
5911/*! @} */
5912
5913
5914/*!
5915 * @}
5916 */ /* end of group CM4_LPCG_LPIT_Register_Masks */
5917
5918
5919/* CM4_LPCG_LPIT - Peripheral instance base addresses */
5920/** Peripheral CM4__LPCG_LPIT base address */
5921#define CM4__LPCG_LPIT_BASE (0x41610000u)
5922/** Peripheral CM4__LPCG_LPIT base pointer */
5923#define CM4__LPCG_LPIT ((CM4_LPCG_LPIT_Type *)CM4__LPCG_LPIT_BASE)
5924/** Array initializer of CM4_LPCG_LPIT peripheral base addresses */
5925#define CM4_LPCG_LPIT_BASE_ADDRS { CM4__LPCG_LPIT_BASE }
5926/** Array initializer of CM4_LPCG_LPIT peripheral base pointers */
5927#define CM4_LPCG_LPIT_BASE_PTRS { CM4__LPCG_LPIT }
5928
5929/*!
5930 * @}
5931 */ /* end of group CM4_LPCG_LPIT_Peripheral_Access_Layer */
5932
5933
5934/* ----------------------------------------------------------------------------
5935 -- CM4_LPCG_LPUART Peripheral Access Layer
5936 ---------------------------------------------------------------------------- */
5937
5938/*!
5939 * @addtogroup CM4_LPCG_LPUART_Peripheral_Access_Layer CM4_LPCG_LPUART Peripheral Access Layer
5940 * @{
5941 */
5942
5943/** CM4_LPCG_LPUART - Register Layout Typedef */
5944typedef struct {
5945 __IO uint32_t LPCG_LPUART_0; /**< na, offset: 0x0 */
5946} CM4_LPCG_LPUART_Type;
5947
5948/* ----------------------------------------------------------------------------
5949 -- CM4_LPCG_LPUART Register Masks
5950 ---------------------------------------------------------------------------- */
5951
5952/*!
5953 * @addtogroup CM4_LPCG_LPUART_Register_Masks CM4_LPCG_LPUART Register Masks
5954 * @{
5955 */
5956
5957/*! @name LPCG_LPUART_0 - na */
5958/*! @{ */
5959#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK (0x1U)
5960#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT (0U)
5961/*! lpuart1_lpuart_baud_gated_clk_HWEN - Hardware Enable
5962 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
5963 * 0b1..Enable HW automatic gating
5964 */
5965#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_gated_clk_HWEN_MASK)
5966#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK (0x2U)
5967#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT (1U)
5968/*! lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN - Software Enable
5969 * 0b0..Disable SW clock regardless of HWEN
5970 * 0b1..Enable SW clock gating
5971 */
5972#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_SWEN_AND_lpuart1_lpuart_baud_gated_clk_SWEN_MASK)
5973#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK (0x4U)
5974#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT (2U)
5975/*! LPCG_LPUART_0_reserved_2_2 - reserved
5976 */
5977#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_2_2_MASK)
5978#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK (0x8U)
5979#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT (3U)
5980/*! lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP - show clock root status, 1 means clock stopped
5981 */
5982#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_lpuart_baud_clk_STOP_AND_lpuart1_lpuart_baud_gated_clk_STOP_MASK)
5983#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK (0x10U)
5984#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT (4U)
5985/*! LPCG_LPUART_0_reserved_4_4 - reserved
5986 */
5987#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_4_4_MASK)
5988#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK (0x20U)
5989#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT (5U)
5990/*! lpuart1_ipg_clk_SWEN - Software Enable
5991 * 0b0..Disable SW clock regardless of HWEN
5992 * 0b1..Enable SW clock gating
5993 */
5994#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_SWEN_MASK)
5995#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK (0x40U)
5996#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT (6U)
5997/*! LPCG_LPUART_0_reserved_6_6 - reserved
5998 */
5999#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_6_6_MASK)
6000#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK (0x80U)
6001#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT (7U)
6002/*! lpuart1_ipg_clk_STOP - show clock root status, 1 means clock stopped
6003 */
6004#define CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_lpuart1_ipg_clk_STOP_MASK)
6005#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK (0xFFFFFF00U)
6006#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT (8U)
6007/*! LPCG_LPUART_0_reserved_8_31 - reserved
6008 */
6009#define CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_SHIFT)) & CM4_LPCG_LPUART_LPCG_LPUART_0_LPCG_LPUART_0_reserved_8_31_MASK)
6010/*! @} */
6011
6012
6013/*!
6014 * @}
6015 */ /* end of group CM4_LPCG_LPUART_Register_Masks */
6016
6017
6018/* CM4_LPCG_LPUART - Peripheral instance base addresses */
6019/** Peripheral CM4__LPCG_LPUART base address */
6020#define CM4__LPCG_LPUART_BASE (0x41620000u)
6021/** Peripheral CM4__LPCG_LPUART base pointer */
6022#define CM4__LPCG_LPUART ((CM4_LPCG_LPUART_Type *)CM4__LPCG_LPUART_BASE)
6023/** Array initializer of CM4_LPCG_LPUART peripheral base addresses */
6024#define CM4_LPCG_LPUART_BASE_ADDRS { CM4__LPCG_LPUART_BASE }
6025/** Array initializer of CM4_LPCG_LPUART peripheral base pointers */
6026#define CM4_LPCG_LPUART_BASE_PTRS { CM4__LPCG_LPUART }
6027
6028/*!
6029 * @}
6030 */ /* end of group CM4_LPCG_LPUART_Peripheral_Access_Layer */
6031
6032
6033/* ----------------------------------------------------------------------------
6034 -- CM4_LPCG_MMCAU_HCLK Peripheral Access Layer
6035 ---------------------------------------------------------------------------- */
6036
6037/*!
6038 * @addtogroup CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer CM4_LPCG_MMCAU_HCLK Peripheral Access Layer
6039 * @{
6040 */
6041
6042/** CM4_LPCG_MMCAU_HCLK - Register Layout Typedef */
6043typedef struct {
6044 __IO uint32_t LPCG_MMCAU_HCLK_0; /**< na, offset: 0x0 */
6045} CM4_LPCG_MMCAU_HCLK_Type;
6046
6047/* ----------------------------------------------------------------------------
6048 -- CM4_LPCG_MMCAU_HCLK Register Masks
6049 ---------------------------------------------------------------------------- */
6050
6051/*!
6052 * @addtogroup CM4_LPCG_MMCAU_HCLK_Register_Masks CM4_LPCG_MMCAU_HCLK Register Masks
6053 * @{
6054 */
6055
6056/*! @name LPCG_MMCAU_HCLK_0 - na */
6057/*! @{ */
6058#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK (0x1U)
6059#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT (0U)
6060/*! LPCG_MMCAU_HCLK_0_reserved_0_0 - reserved
6061 */
6062#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_0_0_MASK)
6063#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK (0x2U)
6064#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT (1U)
6065/*! cm4_mmcau_hclk_SWEN - Software Enable
6066 * 0b0..Disable SW clock regardless of HWEN
6067 * 0b1..Enable SW clock gating
6068 */
6069#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_SWEN_MASK)
6070#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK (0x4U)
6071#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT (2U)
6072/*! LPCG_MMCAU_HCLK_0_reserved_2_2 - reserved
6073 */
6074#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_2_2_MASK)
6075#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK (0x8U)
6076#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT (3U)
6077/*! cm4_mmcau_hclk_STOP - show clock root status, 1 means clock stopped
6078 */
6079#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_cm4_mmcau_hclk_STOP_MASK)
6080#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
6081#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT (4U)
6082/*! LPCG_MMCAU_HCLK_0_reserved_4_31 - reserved
6083 */
6084#define CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_MMCAU_HCLK_LPCG_MMCAU_HCLK_0_LPCG_MMCAU_HCLK_0_reserved_4_31_MASK)
6085/*! @} */
6086
6087
6088/*!
6089 * @}
6090 */ /* end of group CM4_LPCG_MMCAU_HCLK_Register_Masks */
6091
6092
6093/* CM4_LPCG_MMCAU_HCLK - Peripheral instance base addresses */
6094/** Peripheral CM4__LPCG_MMCAU_HCLK base address */
6095#define CM4__LPCG_MMCAU_HCLK_BASE (0x415F0000u)
6096/** Peripheral CM4__LPCG_MMCAU_HCLK base pointer */
6097#define CM4__LPCG_MMCAU_HCLK ((CM4_LPCG_MMCAU_HCLK_Type *)CM4__LPCG_MMCAU_HCLK_BASE)
6098/** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base addresses */
6099#define CM4_LPCG_MMCAU_HCLK_BASE_ADDRS { CM4__LPCG_MMCAU_HCLK_BASE }
6100/** Array initializer of CM4_LPCG_MMCAU_HCLK peripheral base pointers */
6101#define CM4_LPCG_MMCAU_HCLK_BASE_PTRS { CM4__LPCG_MMCAU_HCLK }
6102
6103/*!
6104 * @}
6105 */ /* end of group CM4_LPCG_MMCAU_HCLK_Peripheral_Access_Layer */
6106
6107
6108/* ----------------------------------------------------------------------------
6109 -- CM4_LPCG_TCMC_HCLK Peripheral Access Layer
6110 ---------------------------------------------------------------------------- */
6111
6112/*!
6113 * @addtogroup CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer CM4_LPCG_TCMC_HCLK Peripheral Access Layer
6114 * @{
6115 */
6116
6117/** CM4_LPCG_TCMC_HCLK - Register Layout Typedef */
6118typedef struct {
6119 __IO uint32_t LPCG_TCMC_HCLK_0; /**< na, offset: 0x0 */
6120} CM4_LPCG_TCMC_HCLK_Type;
6121
6122/* ----------------------------------------------------------------------------
6123 -- CM4_LPCG_TCMC_HCLK Register Masks
6124 ---------------------------------------------------------------------------- */
6125
6126/*!
6127 * @addtogroup CM4_LPCG_TCMC_HCLK_Register_Masks CM4_LPCG_TCMC_HCLK Register Masks
6128 * @{
6129 */
6130
6131/*! @name LPCG_TCMC_HCLK_0 - na */
6132/*! @{ */
6133#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK (0x1U)
6134#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT (0U)
6135/*! cm4_tcmc_hclk_HWEN - Hardware Enable
6136 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6137 * 0b1..Enable HW automatic gating
6138 */
6139#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_HWEN_MASK)
6140#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK (0x2U)
6141#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT (1U)
6142/*! cm4_tcmc_hclk_SWEN - Software Enable
6143 * 0b0..Disable SW clock regardless of HWEN
6144 * 0b1..Enable SW clock gating
6145 */
6146#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_SWEN_MASK)
6147#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK (0x4U)
6148#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT (2U)
6149/*! LPCG_TCMC_HCLK_0_reserved_2_2 - reserved
6150 */
6151#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_2_2_MASK)
6152#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK (0x8U)
6153#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT (3U)
6154/*! cm4_tcmc_hclk_STOP - show clock root status, 1 means clock stopped
6155 */
6156#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_cm4_tcmc_hclk_STOP_MASK)
6157#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK (0xFFFFFFF0U)
6158#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT (4U)
6159/*! LPCG_TCMC_HCLK_0_reserved_4_31 - reserved
6160 */
6161#define CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_SHIFT)) & CM4_LPCG_TCMC_HCLK_LPCG_TCMC_HCLK_0_LPCG_TCMC_HCLK_0_reserved_4_31_MASK)
6162/*! @} */
6163
6164
6165/*!
6166 * @}
6167 */ /* end of group CM4_LPCG_TCMC_HCLK_Register_Masks */
6168
6169
6170/* CM4_LPCG_TCMC_HCLK - Peripheral instance base addresses */
6171/** Peripheral CM4__LPCG_TCMC_HCLK base address */
6172#define CM4__LPCG_TCMC_HCLK_BASE (0x415E0000u)
6173/** Peripheral CM4__LPCG_TCMC_HCLK base pointer */
6174#define CM4__LPCG_TCMC_HCLK ((CM4_LPCG_TCMC_HCLK_Type *)CM4__LPCG_TCMC_HCLK_BASE)
6175/** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base addresses */
6176#define CM4_LPCG_TCMC_HCLK_BASE_ADDRS { CM4__LPCG_TCMC_HCLK_BASE }
6177/** Array initializer of CM4_LPCG_TCMC_HCLK peripheral base pointers */
6178#define CM4_LPCG_TCMC_HCLK_BASE_PTRS { CM4__LPCG_TCMC_HCLK }
6179
6180/*!
6181 * @}
6182 */ /* end of group CM4_LPCG_TCMC_HCLK_Peripheral_Access_Layer */
6183
6184
6185/* ----------------------------------------------------------------------------
6186 -- CM4_LPCG_TPM Peripheral Access Layer
6187 ---------------------------------------------------------------------------- */
6188
6189/*!
6190 * @addtogroup CM4_LPCG_TPM_Peripheral_Access_Layer CM4_LPCG_TPM Peripheral Access Layer
6191 * @{
6192 */
6193
6194/** CM4_LPCG_TPM - Register Layout Typedef */
6195typedef struct {
6196 __IO uint32_t LPCG_TPM_0; /**< na, offset: 0x0 */
6197} CM4_LPCG_TPM_Type;
6198
6199/* ----------------------------------------------------------------------------
6200 -- CM4_LPCG_TPM Register Masks
6201 ---------------------------------------------------------------------------- */
6202
6203/*!
6204 * @addtogroup CM4_LPCG_TPM_Register_Masks CM4_LPCG_TPM Register Masks
6205 * @{
6206 */
6207
6208/*! @name LPCG_TPM_0 - na */
6209/*! @{ */
6210#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK (0x1U)
6211#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT (0U)
6212/*! LPCG_TPM_0_reserved_0_0 - reserved
6213 */
6214#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_0_0_MASK)
6215#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK (0x2U)
6216#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT (1U)
6217/*! tpm1_lptpm_clk_SWEN - Software Enable
6218 * 0b0..Disable SW clock regardless of HWEN
6219 * 0b1..Enable SW clock gating
6220 */
6221#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_SWEN_MASK)
6222#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK (0x4U)
6223#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT (2U)
6224/*! LPCG_TPM_0_reserved_2_2 - reserved
6225 */
6226#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_2_2_MASK)
6227#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK (0x8U)
6228#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT (3U)
6229/*! tpm1_lptpm_clk_STOP - show clock root status, 1 means clock stopped
6230 */
6231#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_lptpm_clk_STOP_MASK)
6232#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK (0x10U)
6233#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT (4U)
6234/*! LPCG_TPM_0_reserved_4_4 - reserved
6235 */
6236#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_4_4_MASK)
6237#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK (0x20U)
6238#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT (5U)
6239/*! tpm1_ipg_clk_SWEN - Software Enable
6240 * 0b0..Disable SW clock regardless of HWEN
6241 * 0b1..Enable SW clock gating
6242 */
6243#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_SWEN_MASK)
6244#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK (0x40U)
6245#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT (6U)
6246/*! LPCG_TPM_0_reserved_6_6 - reserved
6247 */
6248#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_6_6_MASK)
6249#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK (0x80U)
6250#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT (7U)
6251/*! tpm1_ipg_clk_STOP - show clock root status, 1 means clock stopped
6252 */
6253#define CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_tpm1_ipg_clk_STOP_MASK)
6254#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK (0xFFFFFF00U)
6255#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT (8U)
6256/*! LPCG_TPM_0_reserved_8_31 - reserved
6257 */
6258#define CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_SHIFT)) & CM4_LPCG_TPM_LPCG_TPM_0_LPCG_TPM_0_reserved_8_31_MASK)
6259/*! @} */
6260
6261
6262/*!
6263 * @}
6264 */ /* end of group CM4_LPCG_TPM_Register_Masks */
6265
6266
6267/* CM4_LPCG_TPM - Peripheral instance base addresses */
6268/** Peripheral CM4__LPCG_TPM base address */
6269#define CM4__LPCG_TPM_BASE (0x41600000u)
6270/** Peripheral CM4__LPCG_TPM base pointer */
6271#define CM4__LPCG_TPM ((CM4_LPCG_TPM_Type *)CM4__LPCG_TPM_BASE)
6272/** Array initializer of CM4_LPCG_TPM peripheral base addresses */
6273#define CM4_LPCG_TPM_BASE_ADDRS { CM4__LPCG_TPM_BASE }
6274/** Array initializer of CM4_LPCG_TPM peripheral base pointers */
6275#define CM4_LPCG_TPM_BASE_PTRS { CM4__LPCG_TPM }
6276
6277/*!
6278 * @}
6279 */ /* end of group CM4_LPCG_TPM_Peripheral_Access_Layer */
6280
6281
6282/* ----------------------------------------------------------------------------
6283 -- CONNECTIVITY_LPCG_EDMA Peripheral Access Layer
6284 ---------------------------------------------------------------------------- */
6285
6286/*!
6287 * @addtogroup CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer CONNECTIVITY_LPCG_EDMA Peripheral Access Layer
6288 * @{
6289 */
6290
6291/** CONNECTIVITY_LPCG_EDMA - Register Layout Typedef */
6292typedef struct {
6293 __IO uint32_t LPCG_LPCG_EDMA_0; /**< na, offset: 0x0 */
6294} CONNECTIVITY_LPCG_EDMA_Type;
6295
6296/* ----------------------------------------------------------------------------
6297 -- CONNECTIVITY_LPCG_EDMA Register Masks
6298 ---------------------------------------------------------------------------- */
6299
6300/*!
6301 * @addtogroup CONNECTIVITY_LPCG_EDMA_Register_Masks CONNECTIVITY_LPCG_EDMA Register Masks
6302 * @{
6303 */
6304
6305/*! @name LPCG_LPCG_EDMA_0 - na */
6306/*! @{ */
6307#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK (0x1U)
6308#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT (0U)
6309/*! edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN - Hardware Enable
6310 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6311 * 0b1..Enable HW automatic gating
6312 */
6313#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_HWEN_AND_edma_mem_dma_clk_HWEN_MASK)
6314#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK (0x2U)
6315#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT (1U)
6316/*! edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN - Software Enable
6317 * 0b0..Disable SW clock regardless of HWEN
6318 * 0b1..Enable SW clock gating
6319 */
6320#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_SWEN_AND_edma_mem_dma_clk_SWEN_MASK)
6321#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK (0x4U)
6322#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT (2U)
6323/*! LPCG_lpcg_edma_0_reserved_2_2 - reserved
6324 */
6325#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_2_2_MASK)
6326#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK (0x8U)
6327#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT (3U)
6328/*! edma_hclk_STOP_AND_edma_mem_dma_clk_STOP - show clock root status, 1 means clock stopped
6329 */
6330#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_hclk_STOP_AND_edma_mem_dma_clk_STOP_MASK)
6331#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK (0x1FFF0U)
6332#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT (4U)
6333/*! LPCG_lpcg_edma_0_reserved_4_16 - reserved
6334 */
6335#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_4_16_MASK)
6336#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK (0x20000U)
6337#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT (17U)
6338/*! edma_ipg_clk_SWEN - Software Enable
6339 * 0b0..Disable SW clock regardless of HWEN
6340 * 0b1..Enable SW clock gating
6341 */
6342#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_SWEN_MASK)
6343#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK (0x40000U)
6344#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT (18U)
6345/*! LPCG_lpcg_edma_0_reserved_18_18 - reserved
6346 */
6347#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_18_18_MASK)
6348#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK (0x80000U)
6349#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT (19U)
6350/*! edma_ipg_clk_STOP - show clock root status, 1 means clock stopped
6351 */
6352#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_edma_ipg_clk_STOP_MASK)
6353#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK (0xFFF00000U)
6354#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT (20U)
6355/*! LPCG_lpcg_edma_0_reserved_20_31 - reserved
6356 */
6357#define CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_EDMA_LPCG_LPCG_EDMA_0_LPCG_lpcg_edma_0_reserved_20_31_MASK)
6358/*! @} */
6359
6360
6361/*!
6362 * @}
6363 */ /* end of group CONNECTIVITY_LPCG_EDMA_Register_Masks */
6364
6365
6366/* CONNECTIVITY_LPCG_EDMA - Peripheral instance base addresses */
6367/** Peripheral CONNECTIVITY__LPCG_EDMA base address */
6368#define CONNECTIVITY__LPCG_EDMA_BASE (0x5B2A0000u)
6369/** Peripheral CONNECTIVITY__LPCG_EDMA base pointer */
6370#define CONNECTIVITY__LPCG_EDMA ((CONNECTIVITY_LPCG_EDMA_Type *)CONNECTIVITY__LPCG_EDMA_BASE)
6371/** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base addresses */
6372#define CONNECTIVITY_LPCG_EDMA_BASE_ADDRS { CONNECTIVITY__LPCG_EDMA_BASE }
6373/** Array initializer of CONNECTIVITY_LPCG_EDMA peripheral base pointers */
6374#define CONNECTIVITY_LPCG_EDMA_BASE_PTRS { CONNECTIVITY__LPCG_EDMA }
6375
6376/*!
6377 * @}
6378 */ /* end of group CONNECTIVITY_LPCG_EDMA_Peripheral_Access_Layer */
6379
6380
6381/* ----------------------------------------------------------------------------
6382 -- CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer
6383 ---------------------------------------------------------------------------- */
6384
6385/*!
6386 * @addtogroup CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET0 Peripheral Access Layer
6387 * @{
6388 */
6389
6390/** CONNECTIVITY_LPCG_ENET0 - Register Layout Typedef */
6391typedef struct {
6392 __IO uint32_t LPCG_LPCG_ENET1_0; /**< na, offset: 0x0 */
6393 __IO uint32_t LPCG_LPCG_ENET1_4; /**< na, offset: 0x4 */
6394} CONNECTIVITY_LPCG_ENET0_Type;
6395
6396/* ----------------------------------------------------------------------------
6397 -- CONNECTIVITY_LPCG_ENET0 Register Masks
6398 ---------------------------------------------------------------------------- */
6399
6400/*!
6401 * @addtogroup CONNECTIVITY_LPCG_ENET0_Register_Masks CONNECTIVITY_LPCG_ENET0 Register Masks
6402 * @{
6403 */
6404
6405/*! @name LPCG_LPCG_ENET1_0 - na */
6406/*! @{ */
6407#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK (0x1U)
6408#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT (0U)
6409/*! enet1_ipg_clk_time_HWEN - Hardware Enable
6410 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6411 * 0b1..Enable HW automatic gating
6412 */
6413#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_HWEN_MASK)
6414#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK (0x2U)
6415#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT (1U)
6416/*! enet1_ipg_clk_time_SWEN - Software Enable
6417 * 0b0..Disable SW clock regardless of HWEN
6418 * 0b1..Enable SW clock gating
6419 */
6420#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_SWEN_MASK)
6421#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK (0x4U)
6422#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT (2U)
6423/*! LPCG_lpcg_enet1_0_reserved_2_2 - reserved
6424 */
6425#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_2_2_MASK)
6426#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK (0x8U)
6427#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT (3U)
6428/*! enet1_ipg_clk_time_STOP - show clock root status, 1 means clock stopped
6429 */
6430#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_time_STOP_MASK)
6431#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK (0x10U)
6432#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT (4U)
6433/*! LPCG_lpcg_enet1_0_reserved_4_4 - reserved
6434 */
6435#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_4_4_MASK)
6436#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK (0x20U)
6437#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT (5U)
6438/*! enet1_2x_txclk_SWEN - Software Enable
6439 * 0b0..Disable SW clock regardless of HWEN
6440 * 0b1..Enable SW clock gating
6441 */
6442#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_SWEN_MASK)
6443#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK (0x40U)
6444#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT (6U)
6445/*! LPCG_lpcg_enet1_0_reserved_6_6 - reserved
6446 */
6447#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_6_6_MASK)
6448#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK (0x80U)
6449#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT (7U)
6450/*! enet1_2x_txclk_STOP - show clock root status, 1 means clock stopped
6451 */
6452#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_2x_txclk_STOP_MASK)
6453#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK (0x100U)
6454#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT (8U)
6455/*! LPCG_lpcg_enet1_0_reserved_8_8 - reserved
6456 */
6457#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_8_8_MASK)
6458#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK (0x200U)
6459#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT (9U)
6460/*! enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN - Software Enable
6461 * 0b0..Disable SW clock regardless of HWEN
6462 * 0b1..Enable SW clock gating
6463 */
6464#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_SWEN_AND_enet_mem1_mac0_rxmem_clk_SWEN_AND_enet_mem1_mac0_rxpmem_clk_SWEN_MASK)
6465#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK (0x400U)
6466#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT (10U)
6467/*! LPCG_lpcg_enet1_0_reserved_10_10 - reserved
6468 */
6469#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_10_10_MASK)
6470#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK (0x800U)
6471#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT (11U)
6472/*! enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP - show clock root status, 1 means clock stopped
6473 */
6474#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet_mem1_mac0_txmem_clk_STOP_AND_enet_mem1_mac0_rxmem_clk_STOP_AND_enet_mem1_mac0_rxpmem_clk_STOP_MASK)
6475#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK (0x1000U)
6476#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT (12U)
6477/*! LPCG_lpcg_enet1_0_reserved_12_12 - reserved
6478 */
6479#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_12_12_MASK)
6480#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK (0x2000U)
6481#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT (13U)
6482/*! enet1_clkdiv_clk_in_SWEN - Software Enable
6483 * 0b0..Disable SW clock regardless of HWEN
6484 * 0b1..Enable SW clock gating
6485 */
6486#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_SWEN_MASK)
6487#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK (0x4000U)
6488#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT (14U)
6489/*! LPCG_lpcg_enet1_0_reserved_14_14 - reserved
6490 */
6491#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_14_14_MASK)
6492#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK (0x8000U)
6493#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT (15U)
6494/*! enet1_clkdiv_clk_in_STOP - show clock root status, 1 means clock stopped
6495 */
6496#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_clkdiv_clk_in_STOP_MASK)
6497#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK (0x10000U)
6498#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT (16U)
6499/*! enet1_ipg_clk_mac0_HWEN - Hardware Enable
6500 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6501 * 0b1..Enable HW automatic gating
6502 */
6503#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_HWEN_MASK)
6504#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK (0x20000U)
6505#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT (17U)
6506/*! enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN - Software Enable
6507 * 0b0..Disable SW clock regardless of HWEN
6508 * 0b1..Enable SW clock gating
6509 */
6510#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_SWEN_AND_enet1_ipg_clk_mac0_SWEN_MASK)
6511#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK (0x40000U)
6512#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT (18U)
6513/*! LPCG_lpcg_enet1_0_reserved_18_18 - reserved
6514 */
6515#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_18_18_MASK)
6516#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK (0x80000U)
6517#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT (19U)
6518/*! enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP - show clock root status, 1 means clock stopped
6519 */
6520#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_STOP_AND_enet1_ipg_clk_mac0_STOP_MASK)
6521#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK (0x100000U)
6522#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT (20U)
6523/*! enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN - Hardware Enable
6524 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6525 * 0b1..Enable HW automatic gating
6526 */
6527#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_HWEN_AND_enet1_ipg_clk_s_HWEN_MASK)
6528#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK (0x200000U)
6529#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT (21U)
6530/*! enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN - Software Enable
6531 * 0b0..Disable SW clock regardless of HWEN
6532 * 0b1..Enable SW clock gating
6533 */
6534#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_SWEN_AND_enet1_ipg_clk_s_SWEN_MASK)
6535#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK (0x400000U)
6536#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT (22U)
6537/*! LPCG_lpcg_enet1_0_reserved_22_22 - reserved
6538 */
6539#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_22_22_MASK)
6540#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK (0x800000U)
6541#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT (23U)
6542/*! enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
6543 */
6544#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_enet1_ipg_clk_mac0_s_STOP_AND_enet1_ipg_clk_s_STOP_MASK)
6545#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK (0xFF000000U)
6546#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT (24U)
6547/*! LPCG_lpcg_enet1_0_reserved_24_31 - reserved
6548 */
6549#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_0_LPCG_lpcg_enet1_0_reserved_24_31_MASK)
6550/*! @} */
6551
6552/*! @name LPCG_LPCG_ENET1_4 - na */
6553/*! @{ */
6554#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK (0x1U)
6555#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT (0U)
6556/*! LPCG_lpcg_enet1_4_reserved_0_0 - reserved
6557 */
6558#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_0_0_MASK)
6559#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK (0x2U)
6560#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT (1U)
6561/*! enet1_mac0_rxclk_SWEN - Software Enable
6562 * 0b0..Disable SW clock regardless of HWEN
6563 * 0b1..Enable SW clock gating
6564 */
6565#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_SWEN_MASK)
6566#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK (0x4U)
6567#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT (2U)
6568/*! LPCG_lpcg_enet1_4_reserved_2_2 - reserved
6569 */
6570#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_2_2_MASK)
6571#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK (0x8U)
6572#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT (3U)
6573/*! enet1_mac0_rxclk_STOP - show clock root status, 1 means clock stopped
6574 */
6575#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_enet1_mac0_rxclk_STOP_MASK)
6576#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK (0xFFFFFFF0U)
6577#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT (4U)
6578/*! LPCG_lpcg_enet1_4_reserved_4_31 - reserved
6579 */
6580#define CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET0_LPCG_LPCG_ENET1_4_LPCG_lpcg_enet1_4_reserved_4_31_MASK)
6581/*! @} */
6582
6583
6584/*!
6585 * @}
6586 */ /* end of group CONNECTIVITY_LPCG_ENET0_Register_Masks */
6587
6588
6589/* CONNECTIVITY_LPCG_ENET0 - Peripheral instance base addresses */
6590/** Peripheral CONNECTIVITY__LPCG_ENET0 base address */
6591#define CONNECTIVITY__LPCG_ENET0_BASE (0x5B230000u)
6592/** Peripheral CONNECTIVITY__LPCG_ENET0 base pointer */
6593#define CONNECTIVITY__LPCG_ENET0 ((CONNECTIVITY_LPCG_ENET0_Type *)CONNECTIVITY__LPCG_ENET0_BASE)
6594/** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base addresses */
6595#define CONNECTIVITY_LPCG_ENET0_BASE_ADDRS { CONNECTIVITY__LPCG_ENET0_BASE }
6596/** Array initializer of CONNECTIVITY_LPCG_ENET0 peripheral base pointers */
6597#define CONNECTIVITY_LPCG_ENET0_BASE_PTRS { CONNECTIVITY__LPCG_ENET0 }
6598
6599/*!
6600 * @}
6601 */ /* end of group CONNECTIVITY_LPCG_ENET0_Peripheral_Access_Layer */
6602
6603
6604/* ----------------------------------------------------------------------------
6605 -- CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer
6606 ---------------------------------------------------------------------------- */
6607
6608/*!
6609 * @addtogroup CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer CONNECTIVITY_LPCG_ENET1 Peripheral Access Layer
6610 * @{
6611 */
6612
6613/** CONNECTIVITY_LPCG_ENET1 - Register Layout Typedef */
6614typedef struct {
6615 __IO uint32_t LPCG_LPCG_ENET2_0; /**< na, offset: 0x0 */
6616 __IO uint32_t LPCG_LPCG_ENET2_4; /**< na, offset: 0x4 */
6617} CONNECTIVITY_LPCG_ENET1_Type;
6618
6619/* ----------------------------------------------------------------------------
6620 -- CONNECTIVITY_LPCG_ENET1 Register Masks
6621 ---------------------------------------------------------------------------- */
6622
6623/*!
6624 * @addtogroup CONNECTIVITY_LPCG_ENET1_Register_Masks CONNECTIVITY_LPCG_ENET1 Register Masks
6625 * @{
6626 */
6627
6628/*! @name LPCG_LPCG_ENET2_0 - na */
6629/*! @{ */
6630#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK (0x1U)
6631#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT (0U)
6632/*! enet2_ipg_clk_time_HWEN - Hardware Enable
6633 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6634 * 0b1..Enable HW automatic gating
6635 */
6636#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_HWEN_MASK)
6637#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK (0x2U)
6638#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT (1U)
6639/*! enet2_ipg_clk_time_SWEN - Software Enable
6640 * 0b0..Disable SW clock regardless of HWEN
6641 * 0b1..Enable SW clock gating
6642 */
6643#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_SWEN_MASK)
6644#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK (0x4U)
6645#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT (2U)
6646/*! LPCG_lpcg_enet2_0_reserved_2_2 - reserved
6647 */
6648#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_2_2_MASK)
6649#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK (0x8U)
6650#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT (3U)
6651/*! enet2_ipg_clk_time_STOP - show clock root status, 1 means clock stopped
6652 */
6653#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_time_STOP_MASK)
6654#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK (0x10U)
6655#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT (4U)
6656/*! LPCG_lpcg_enet2_0_reserved_4_4 - reserved
6657 */
6658#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_4_4_MASK)
6659#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK (0x20U)
6660#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT (5U)
6661/*! enet2_2x_txclk_SWEN - Software Enable
6662 * 0b0..Disable SW clock regardless of HWEN
6663 * 0b1..Enable SW clock gating
6664 */
6665#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_SWEN_MASK)
6666#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK (0x40U)
6667#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT (6U)
6668/*! LPCG_lpcg_enet2_0_reserved_6_6 - reserved
6669 */
6670#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_6_6_MASK)
6671#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK (0x80U)
6672#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT (7U)
6673/*! enet2_2x_txclk_STOP - show clock root status, 1 means clock stopped
6674 */
6675#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_2x_txclk_STOP_MASK)
6676#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK (0x100U)
6677#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT (8U)
6678/*! LPCG_lpcg_enet2_0_reserved_8_8 - reserved
6679 */
6680#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_8_8_MASK)
6681#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK (0x200U)
6682#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT (9U)
6683/*! enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN - Software Enable
6684 * 0b0..Disable SW clock regardless of HWEN
6685 * 0b1..Enable SW clock gating
6686 */
6687#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_SWEN_AND_enet_mem2_mac0_rxmem_clk_SWEN_AND_enet_mem2_mac0_rxpmem_clk_SWEN_MASK)
6688#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK (0x400U)
6689#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT (10U)
6690/*! LPCG_lpcg_enet2_0_reserved_10_10 - reserved
6691 */
6692#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_10_10_MASK)
6693#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK (0x800U)
6694#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT (11U)
6695/*! enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP - show clock root status, 1 means clock stopped
6696 */
6697#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet_mem2_mac0_txmem_clk_STOP_AND_enet_mem2_mac0_rxmem_clk_STOP_AND_enet_mem2_mac0_rxpmem_clk_STOP_MASK)
6698#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK (0x1000U)
6699#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT (12U)
6700/*! LPCG_lpcg_enet2_0_reserved_12_12 - reserved
6701 */
6702#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_12_12_MASK)
6703#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK (0x2000U)
6704#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT (13U)
6705/*! enet2_clkdiv_clk_in_SWEN - Software Enable
6706 * 0b0..Disable SW clock regardless of HWEN
6707 * 0b1..Enable SW clock gating
6708 */
6709#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_SWEN_MASK)
6710#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK (0x4000U)
6711#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT (14U)
6712/*! LPCG_lpcg_enet2_0_reserved_14_14 - reserved
6713 */
6714#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_14_14_MASK)
6715#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK (0x8000U)
6716#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT (15U)
6717/*! enet2_clkdiv_clk_in_STOP - show clock root status, 1 means clock stopped
6718 */
6719#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_clkdiv_clk_in_STOP_MASK)
6720#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK (0x10000U)
6721#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT (16U)
6722/*! enet2_ipg_clk_mac0_HWEN - Hardware Enable
6723 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6724 * 0b1..Enable HW automatic gating
6725 */
6726#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_HWEN_MASK)
6727#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK (0x20000U)
6728#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT (17U)
6729/*! enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN - Software Enable
6730 * 0b0..Disable SW clock regardless of HWEN
6731 * 0b1..Enable SW clock gating
6732 */
6733#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_SWEN_AND_enet2_ipg_clk_mac0_SWEN_MASK)
6734#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK (0x40000U)
6735#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT (18U)
6736/*! LPCG_lpcg_enet2_0_reserved_18_18 - reserved
6737 */
6738#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_18_18_MASK)
6739#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK (0x80000U)
6740#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT (19U)
6741/*! enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP - show clock root status, 1 means clock stopped
6742 */
6743#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_STOP_AND_enet2_ipg_clk_mac0_STOP_MASK)
6744#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK (0x100000U)
6745#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT (20U)
6746/*! enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN - Hardware Enable
6747 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6748 * 0b1..Enable HW automatic gating
6749 */
6750#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_HWEN_AND_enet2_ipg_clk_s_HWEN_MASK)
6751#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK (0x200000U)
6752#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT (21U)
6753/*! enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN - Software Enable
6754 * 0b0..Disable SW clock regardless of HWEN
6755 * 0b1..Enable SW clock gating
6756 */
6757#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_SWEN_AND_enet2_ipg_clk_s_SWEN_MASK)
6758#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK (0x400000U)
6759#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT (22U)
6760/*! LPCG_lpcg_enet2_0_reserved_22_22 - reserved
6761 */
6762#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_22_22_MASK)
6763#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK (0x800000U)
6764#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT (23U)
6765/*! enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
6766 */
6767#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_enet2_ipg_clk_mac0_s_STOP_AND_enet2_ipg_clk_s_STOP_MASK)
6768#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK (0xFF000000U)
6769#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT (24U)
6770/*! LPCG_lpcg_enet2_0_reserved_24_31 - reserved
6771 */
6772#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_0_LPCG_lpcg_enet2_0_reserved_24_31_MASK)
6773/*! @} */
6774
6775/*! @name LPCG_LPCG_ENET2_4 - na */
6776/*! @{ */
6777#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK (0x1U)
6778#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT (0U)
6779/*! LPCG_lpcg_enet2_4_reserved_0_0 - reserved
6780 */
6781#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_0_0_MASK)
6782#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK (0x2U)
6783#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT (1U)
6784/*! enet2_mac0_rxclk_SWEN - Software Enable
6785 * 0b0..Disable SW clock regardless of HWEN
6786 * 0b1..Enable SW clock gating
6787 */
6788#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_SWEN_MASK)
6789#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK (0x4U)
6790#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT (2U)
6791/*! LPCG_lpcg_enet2_4_reserved_2_2 - reserved
6792 */
6793#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_2_2_MASK)
6794#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK (0x8U)
6795#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT (3U)
6796/*! enet2_mac0_rxclk_STOP - show clock root status, 1 means clock stopped
6797 */
6798#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_enet2_mac0_rxclk_STOP_MASK)
6799#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK (0xFFFFFFF0U)
6800#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT (4U)
6801/*! LPCG_lpcg_enet2_4_reserved_4_31 - reserved
6802 */
6803#define CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_SHIFT)) & CONNECTIVITY_LPCG_ENET1_LPCG_LPCG_ENET2_4_LPCG_lpcg_enet2_4_reserved_4_31_MASK)
6804/*! @} */
6805
6806
6807/*!
6808 * @}
6809 */ /* end of group CONNECTIVITY_LPCG_ENET1_Register_Masks */
6810
6811
6812/* CONNECTIVITY_LPCG_ENET1 - Peripheral instance base addresses */
6813/** Peripheral CONNECTIVITY__LPCG_ENET1 base address */
6814#define CONNECTIVITY__LPCG_ENET1_BASE (0x5B240000u)
6815/** Peripheral CONNECTIVITY__LPCG_ENET1 base pointer */
6816#define CONNECTIVITY__LPCG_ENET1 ((CONNECTIVITY_LPCG_ENET1_Type *)CONNECTIVITY__LPCG_ENET1_BASE)
6817/** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base addresses */
6818#define CONNECTIVITY_LPCG_ENET1_BASE_ADDRS { CONNECTIVITY__LPCG_ENET1_BASE }
6819/** Array initializer of CONNECTIVITY_LPCG_ENET1 peripheral base pointers */
6820#define CONNECTIVITY_LPCG_ENET1_BASE_PTRS { CONNECTIVITY__LPCG_ENET1 }
6821
6822/*!
6823 * @}
6824 */ /* end of group CONNECTIVITY_LPCG_ENET1_Peripheral_Access_Layer */
6825
6826
6827/* ----------------------------------------------------------------------------
6828 -- CONNECTIVITY_LPCG_MLB Peripheral Access Layer
6829 ---------------------------------------------------------------------------- */
6830
6831/*!
6832 * @addtogroup CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer CONNECTIVITY_LPCG_MLB Peripheral Access Layer
6833 * @{
6834 */
6835
6836/** CONNECTIVITY_LPCG_MLB - Register Layout Typedef */
6837typedef struct {
6838 __IO uint32_t LPCG_LPCG_MLB_0; /**< na, offset: 0x0 */
6839} CONNECTIVITY_LPCG_MLB_Type;
6840
6841/* ----------------------------------------------------------------------------
6842 -- CONNECTIVITY_LPCG_MLB Register Masks
6843 ---------------------------------------------------------------------------- */
6844
6845/*!
6846 * @addtogroup CONNECTIVITY_LPCG_MLB_Register_Masks CONNECTIVITY_LPCG_MLB Register Masks
6847 * @{
6848 */
6849
6850/*! @name LPCG_LPCG_MLB_0 - na */
6851/*! @{ */
6852#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK (0x1U)
6853#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT (0U)
6854/*! LPCG_lpcg_mlb_0_reserved_0_0 - reserved
6855 */
6856#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_0_0_MASK)
6857#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK (0x2U)
6858#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT (1U)
6859/*! mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN - Software Enable
6860 * 0b0..Disable SW clock regardless of HWEN
6861 * 0b1..Enable SW clock gating
6862 */
6863#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_SWEN_AND_mlb150_mem_db_CLK_SWEN_AND_mlb150_mem_ct_CLK_SWEN_MASK)
6864#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK (0x4U)
6865#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT (2U)
6866/*! LPCG_lpcg_mlb_0_reserved_2_2 - reserved
6867 */
6868#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_2_2_MASK)
6869#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK (0x8U)
6870#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT (3U)
6871/*! mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP - show clock root status, 1 means clock stopped
6872 */
6873#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_sys_clk_STOP_AND_mlb150_mem_db_CLK_STOP_AND_mlb150_mem_ct_CLK_STOP_MASK)
6874#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK (0xFFF0U)
6875#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT (4U)
6876/*! LPCG_lpcg_mlb_0_reserved_4_15 - reserved
6877 */
6878#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_4_15_MASK)
6879#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK (0x10000U)
6880#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT (16U)
6881/*! mlb_ipg_clk_s_HWEN - Hardware Enable
6882 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
6883 * 0b1..Enable HW automatic gating
6884 */
6885#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_HWEN_MASK)
6886#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK (0x20000U)
6887#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT (17U)
6888/*! mlb_ipg_clk_s_SWEN - Software Enable
6889 * 0b0..Disable SW clock regardless of HWEN
6890 * 0b1..Enable SW clock gating
6891 */
6892#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_SWEN_MASK)
6893#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK (0x40000U)
6894#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT (18U)
6895/*! LPCG_lpcg_mlb_0_reserved_18_18 - reserved
6896 */
6897#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_18_18_MASK)
6898#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK (0x80000U)
6899#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT (19U)
6900/*! mlb_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
6901 */
6902#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_ipg_clk_s_STOP_MASK)
6903#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK (0x100000U)
6904#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT (20U)
6905/*! LPCG_lpcg_mlb_0_reserved_20_20 - reserved
6906 */
6907#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_20_20_MASK)
6908#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK (0x200000U)
6909#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT (21U)
6910/*! mlb_hclk_SWEN - Software Enable
6911 * 0b0..Disable SW clock regardless of HWEN
6912 * 0b1..Enable SW clock gating
6913 */
6914#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_SWEN_MASK)
6915#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK (0x400000U)
6916#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT (22U)
6917/*! LPCG_lpcg_mlb_0_reserved_22_22 - reserved
6918 */
6919#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_22_22_MASK)
6920#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK (0x800000U)
6921#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT (23U)
6922/*! mlb_hclk_STOP - show clock root status, 1 means clock stopped
6923 */
6924#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_mlb_hclk_STOP_MASK)
6925#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK (0xFF000000U)
6926#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT (24U)
6927/*! LPCG_lpcg_mlb_0_reserved_24_31 - reserved
6928 */
6929#define CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_MLB_LPCG_LPCG_MLB_0_LPCG_lpcg_mlb_0_reserved_24_31_MASK)
6930/*! @} */
6931
6932
6933/*!
6934 * @}
6935 */ /* end of group CONNECTIVITY_LPCG_MLB_Register_Masks */
6936
6937
6938/* CONNECTIVITY_LPCG_MLB - Peripheral instance base addresses */
6939/** Peripheral CONNECTIVITY__LPCG_MLB base address */
6940#define CONNECTIVITY__LPCG_MLB_BASE (0x5B260000u)
6941/** Peripheral CONNECTIVITY__LPCG_MLB base pointer */
6942#define CONNECTIVITY__LPCG_MLB ((CONNECTIVITY_LPCG_MLB_Type *)CONNECTIVITY__LPCG_MLB_BASE)
6943/** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base addresses */
6944#define CONNECTIVITY_LPCG_MLB_BASE_ADDRS { CONNECTIVITY__LPCG_MLB_BASE }
6945/** Array initializer of CONNECTIVITY_LPCG_MLB peripheral base pointers */
6946#define CONNECTIVITY_LPCG_MLB_BASE_PTRS { CONNECTIVITY__LPCG_MLB }
6947
6948/*!
6949 * @}
6950 */ /* end of group CONNECTIVITY_LPCG_MLB_Peripheral_Access_Layer */
6951
6952
6953/* ----------------------------------------------------------------------------
6954 -- CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer
6955 ---------------------------------------------------------------------------- */
6956
6957/*!
6958 * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer CONNECTIVITY_LPCG_RAWNAND Peripheral Access Layer
6959 * @{
6960 */
6961
6962/** CONNECTIVITY_LPCG_RAWNAND - Register Layout Typedef */
6963typedef struct {
6964 __IO uint32_t LPCG_LPCG_RAWNAND_0; /**< na, offset: 0x0 */
6965 __IO uint32_t LPCG_LPCG_RAWNAND_4; /**< na, offset: 0x4 */
6966} CONNECTIVITY_LPCG_RAWNAND_Type;
6967
6968/* ----------------------------------------------------------------------------
6969 -- CONNECTIVITY_LPCG_RAWNAND Register Masks
6970 ---------------------------------------------------------------------------- */
6971
6972/*!
6973 * @addtogroup CONNECTIVITY_LPCG_RAWNAND_Register_Masks CONNECTIVITY_LPCG_RAWNAND Register Masks
6974 * @{
6975 */
6976
6977/*! @name LPCG_LPCG_RAWNAND_0 - na */
6978/*! @{ */
6979#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK (0x1U)
6980#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT (0U)
6981/*! LPCG_lpcg_rawnand_0_reserved_0_0 - reserved
6982 */
6983#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_0_0_MASK)
6984#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK (0x2U)
6985#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT (1U)
6986/*! rawnand_u_gpmi_bch_input_bch_clk_SWEN - Software Enable
6987 * 0b0..Disable SW clock regardless of HWEN
6988 * 0b1..Enable SW clock gating
6989 */
6990#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_SWEN_MASK)
6991#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK (0x4U)
6992#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT (2U)
6993/*! LPCG_lpcg_rawnand_0_reserved_2_2 - reserved
6994 */
6995#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_2_2_MASK)
6996#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK (0x8U)
6997#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT (3U)
6998/*! rawnand_u_gpmi_bch_input_bch_clk_STOP - show clock root status, 1 means clock stopped
6999 */
7000#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_bch_clk_STOP_MASK)
7001#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK (0x10U)
7002#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT (4U)
7003/*! LPCG_lpcg_rawnand_0_reserved_4_4 - reserved
7004 */
7005#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_4_4_MASK)
7006#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK (0x20U)
7007#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT (5U)
7008/*! rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN - Software Enable
7009 * 0b0..Disable SW clock regardless of HWEN
7010 * 0b1..Enable SW clock gating
7011 */
7012#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_SWEN_MASK)
7013#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK (0x40U)
7014#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT (6U)
7015/*! LPCG_lpcg_rawnand_0_reserved_6_6 - reserved
7016 */
7017#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_6_6_MASK)
7018#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK (0x80U)
7019#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT (7U)
7020/*! rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP - show clock root status, 1 means clock stopped
7021 */
7022#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_bch_input_gpmi_io_clk_STOP_MASK)
7023#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK (0x1FF00U)
7024#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT (8U)
7025/*! LPCG_lpcg_rawnand_0_reserved_8_16 - reserved
7026 */
7027#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_8_16_MASK)
7028#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK (0x20000U)
7029#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT (17U)
7030/*! rawnand_u_gpmi_input_apb_clk_SWEN - Software Enable
7031 * 0b0..Disable SW clock regardless of HWEN
7032 * 0b1..Enable SW clock gating
7033 */
7034#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_SWEN_MASK)
7035#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK (0x40000U)
7036#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT (18U)
7037/*! LPCG_lpcg_rawnand_0_reserved_18_18 - reserved
7038 */
7039#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_18_18_MASK)
7040#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK (0x80000U)
7041#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT (19U)
7042/*! rawnand_u_gpmi_input_apb_clk_STOP - show clock root status, 1 means clock stopped
7043 */
7044#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_gpmi_input_apb_clk_STOP_MASK)
7045#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK (0x100000U)
7046#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT (20U)
7047/*! LPCG_lpcg_rawnand_0_reserved_20_20 - reserved
7048 */
7049#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_20_20_MASK)
7050#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK (0x200000U)
7051#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT (21U)
7052/*! rawnand_u_bch_input_apb_clk_SWEN - Software Enable
7053 * 0b0..Disable SW clock regardless of HWEN
7054 * 0b1..Enable SW clock gating
7055 */
7056#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_SWEN_MASK)
7057#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK (0x400000U)
7058#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT (22U)
7059/*! LPCG_lpcg_rawnand_0_reserved_22_22 - reserved
7060 */
7061#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_22_22_MASK)
7062#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK (0x800000U)
7063#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT (23U)
7064/*! rawnand_u_bch_input_apb_clk_STOP - show clock root status, 1 means clock stopped
7065 */
7066#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_rawnand_u_bch_input_apb_clk_STOP_MASK)
7067#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK (0xFF000000U)
7068#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT (24U)
7069/*! LPCG_lpcg_rawnand_0_reserved_24_31 - reserved
7070 */
7071#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_0_LPCG_lpcg_rawnand_0_reserved_24_31_MASK)
7072/*! @} */
7073
7074/*! @name LPCG_LPCG_RAWNAND_4 - na */
7075/*! @{ */
7076#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK (0x1FFFFU)
7077#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT (0U)
7078/*! LPCG_lpcg_rawnand_4_reserved_0_16 - reserved
7079 */
7080#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_0_16_MASK)
7081#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK (0x20000U)
7082#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT (17U)
7083/*! apbhdma_hclk_SWEN - Software Enable
7084 * 0b0..Disable SW clock regardless of HWEN
7085 * 0b1..Enable SW clock gating
7086 */
7087#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_SWEN_MASK)
7088#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK (0x40000U)
7089#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT (18U)
7090/*! LPCG_lpcg_rawnand_4_reserved_18_18 - reserved
7091 */
7092#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_18_18_MASK)
7093#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK (0x80000U)
7094#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT (19U)
7095/*! apbhdma_hclk_STOP - show clock root status, 1 means clock stopped
7096 */
7097#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_apbhdma_hclk_STOP_MASK)
7098#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK (0xFFF00000U)
7099#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT (20U)
7100/*! LPCG_lpcg_rawnand_4_reserved_20_31 - reserved
7101 */
7102#define CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_SHIFT)) & CONNECTIVITY_LPCG_RAWNAND_LPCG_LPCG_RAWNAND_4_LPCG_lpcg_rawnand_4_reserved_20_31_MASK)
7103/*! @} */
7104
7105
7106/*!
7107 * @}
7108 */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Register_Masks */
7109
7110
7111/* CONNECTIVITY_LPCG_RAWNAND - Peripheral instance base addresses */
7112/** Peripheral CONNECTIVITY__LPCG_RAWNAND base address */
7113#define CONNECTIVITY__LPCG_RAWNAND_BASE (0x5B290000u)
7114/** Peripheral CONNECTIVITY__LPCG_RAWNAND base pointer */
7115#define CONNECTIVITY__LPCG_RAWNAND ((CONNECTIVITY_LPCG_RAWNAND_Type *)CONNECTIVITY__LPCG_RAWNAND_BASE)
7116/** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base addresses */
7117#define CONNECTIVITY_LPCG_RAWNAND_BASE_ADDRS { CONNECTIVITY__LPCG_RAWNAND_BASE }
7118/** Array initializer of CONNECTIVITY_LPCG_RAWNAND peripheral base pointers */
7119#define CONNECTIVITY_LPCG_RAWNAND_BASE_PTRS { CONNECTIVITY__LPCG_RAWNAND }
7120
7121/*!
7122 * @}
7123 */ /* end of group CONNECTIVITY_LPCG_RAWNAND_Peripheral_Access_Layer */
7124
7125
7126/* ----------------------------------------------------------------------------
7127 -- CONNECTIVITY_LPCG_USB2 Peripheral Access Layer
7128 ---------------------------------------------------------------------------- */
7129
7130/*!
7131 * @addtogroup CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB2 Peripheral Access Layer
7132 * @{
7133 */
7134
7135/** CONNECTIVITY_LPCG_USB2 - Register Layout Typedef */
7136typedef struct {
7137 __IO uint32_t LPCG_LPCG_USB2_0; /**< na, offset: 0x0 */
7138} CONNECTIVITY_LPCG_USB2_Type;
7139
7140/* ----------------------------------------------------------------------------
7141 -- CONNECTIVITY_LPCG_USB2 Register Masks
7142 ---------------------------------------------------------------------------- */
7143
7144/*!
7145 * @addtogroup CONNECTIVITY_LPCG_USB2_Register_Masks CONNECTIVITY_LPCG_USB2 Register Masks
7146 * @{
7147 */
7148
7149/*! @name LPCG_LPCG_USB2_0 - na */
7150/*! @{ */
7151#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK (0x1FFFFU)
7152#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT (0U)
7153/*! LPCG_lpcg_usb2_0_reserved_0_16 - reserved
7154 */
7155#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_0_16_MASK)
7156#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK (0x20000U)
7157#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT (17U)
7158/*! usboh_ipg_clk_s_SWEN - Software Enable
7159 * 0b0..Disable SW clock regardless of HWEN
7160 * 0b1..Enable SW clock gating
7161 */
7162#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_SWEN_MASK)
7163#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK (0x40000U)
7164#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT (18U)
7165/*! LPCG_lpcg_usb2_0_reserved_18_18 - reserved
7166 */
7167#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_18_18_MASK)
7168#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK (0x80000U)
7169#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT (19U)
7170/*! usboh_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
7171 */
7172#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_STOP_MASK)
7173#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK (0x100000U)
7174#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT (20U)
7175/*! LPCG_lpcg_usb2_0_reserved_20_20 - reserved
7176 */
7177#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_20_20_MASK)
7178#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK (0x200000U)
7179#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT (21U)
7180/*! usboh_ipg_clk_s_pl301_SWEN - Software Enable
7181 * 0b0..Disable SW clock regardless of HWEN
7182 * 0b1..Enable SW clock gating
7183 */
7184#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_SWEN_MASK)
7185#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK (0x400000U)
7186#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT (22U)
7187/*! LPCG_lpcg_usb2_0_reserved_22_22 - reserved
7188 */
7189#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_22_22_MASK)
7190#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK (0x800000U)
7191#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT (23U)
7192/*! usboh_ipg_clk_s_pl301_STOP - show clock root status, 1 means clock stopped
7193 */
7194#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_clk_s_pl301_STOP_MASK)
7195#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK (0x1000000U)
7196#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT (24U)
7197/*! LPCG_lpcg_usb2_0_reserved_24_24 - reserved
7198 */
7199#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_24_24_MASK)
7200#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK (0x2000000U)
7201#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT (25U)
7202/*! usboh_ipg_ahb_clk_SWEN - Software Enable
7203 * 0b0..Disable SW clock regardless of HWEN
7204 * 0b1..Enable SW clock gating
7205 */
7206#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_SWEN_MASK)
7207#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK (0x4000000U)
7208#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT (26U)
7209/*! LPCG_lpcg_usb2_0_reserved_26_26 - reserved
7210 */
7211#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_26_26_MASK)
7212#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK (0x8000000U)
7213#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT (27U)
7214/*! usboh_ipg_ahb_clk_STOP - show clock root status, 1 means clock stopped
7215 */
7216#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_usboh_ipg_ahb_clk_STOP_MASK)
7217#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK (0x10000000U)
7218#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT (28U)
7219/*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN - Hardware Enable
7220 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7221 * 0b1..Enable HW automatic gating
7222 */
7223#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_HWEN_MASK)
7224#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK (0x20000000U)
7225#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT (29U)
7226/*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN - Software Enable
7227 * 0b0..Disable SW clock regardless of HWEN
7228 * 0b1..Enable SW clock gating
7229 */
7230#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_SWEN_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_SWEN_MASK)
7231#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK (0x40000000U)
7232#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT (30U)
7233/*! LPCG_lpcg_usb2_0_reserved_30_30 - reserved
7234 */
7235#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_LPCG_lpcg_usb2_0_reserved_30_30_MASK)
7236#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK (0x80000000U)
7237#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT (31U)
7238/*! da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP - show clock root status, 1 means clock stopped
7239 */
7240#define CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB2_LPCG_LPCG_USB2_0_da_ip_hs_usb2phy_28fdsoi_ipg_clk_STOP_AND_da_ip_hs_usb2phy_28fdsoi_ipg_clk_s_STOP_MASK)
7241/*! @} */
7242
7243
7244/*!
7245 * @}
7246 */ /* end of group CONNECTIVITY_LPCG_USB2_Register_Masks */
7247
7248
7249/* CONNECTIVITY_LPCG_USB2 - Peripheral instance base addresses */
7250/** Peripheral CONNECTIVITY__LPCG_USB2 base address */
7251#define CONNECTIVITY__LPCG_USB2_BASE (0x5B270000u)
7252/** Peripheral CONNECTIVITY__LPCG_USB2 base pointer */
7253#define CONNECTIVITY__LPCG_USB2 ((CONNECTIVITY_LPCG_USB2_Type *)CONNECTIVITY__LPCG_USB2_BASE)
7254/** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base addresses */
7255#define CONNECTIVITY_LPCG_USB2_BASE_ADDRS { CONNECTIVITY__LPCG_USB2_BASE }
7256/** Array initializer of CONNECTIVITY_LPCG_USB2 peripheral base pointers */
7257#define CONNECTIVITY_LPCG_USB2_BASE_PTRS { CONNECTIVITY__LPCG_USB2 }
7258
7259/*!
7260 * @}
7261 */ /* end of group CONNECTIVITY_LPCG_USB2_Peripheral_Access_Layer */
7262
7263
7264/* ----------------------------------------------------------------------------
7265 -- CONNECTIVITY_LPCG_USB3 Peripheral Access Layer
7266 ---------------------------------------------------------------------------- */
7267
7268/*!
7269 * @addtogroup CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer CONNECTIVITY_LPCG_USB3 Peripheral Access Layer
7270 * @{
7271 */
7272
7273/** CONNECTIVITY_LPCG_USB3 - Register Layout Typedef */
7274typedef struct {
7275 __IO uint32_t LPCG_LPCG_USB3_0; /**< na, offset: 0x0 */
7276} CONNECTIVITY_LPCG_USB3_Type;
7277
7278/* ----------------------------------------------------------------------------
7279 -- CONNECTIVITY_LPCG_USB3 Register Masks
7280 ---------------------------------------------------------------------------- */
7281
7282/*!
7283 * @addtogroup CONNECTIVITY_LPCG_USB3_Register_Masks CONNECTIVITY_LPCG_USB3 Register Masks
7284 * @{
7285 */
7286
7287/*! @name LPCG_LPCG_USB3_0 - na */
7288/*! @{ */
7289#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK (0x1U)
7290#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT (0U)
7291/*! LPCG_lpcg_usb3_0_reserved_0_0 - reserved
7292 */
7293#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_0_0_MASK)
7294#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK (0x2U)
7295#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT (1U)
7296/*! da_ip_usb3_wrap_app_clk_125_predft_SWEN - Software Enable
7297 * 0b0..Disable SW clock regardless of HWEN
7298 * 0b1..Enable SW clock gating
7299 */
7300#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_SWEN_MASK)
7301#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK (0x4U)
7302#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT (2U)
7303/*! LPCG_lpcg_usb3_0_reserved_2_2 - reserved
7304 */
7305#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_2_2_MASK)
7306#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK (0x8U)
7307#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT (3U)
7308/*! da_ip_usb3_wrap_app_clk_125_predft_STOP - show clock root status, 1 means clock stopped
7309 */
7310#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_app_clk_125_predft_STOP_MASK)
7311#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK (0x10U)
7312#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT (4U)
7313/*! LPCG_lpcg_usb3_0_reserved_4_4 - reserved
7314 */
7315#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_4_4_MASK)
7316#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK (0x20U)
7317#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT (5U)
7318/*! da_ip_usb3_wrap_lpm_clk_predft_SWEN - Software Enable
7319 * 0b0..Disable SW clock regardless of HWEN
7320 * 0b1..Enable SW clock gating
7321 */
7322#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_SWEN_MASK)
7323#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK (0x40U)
7324#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT (6U)
7325/*! LPCG_lpcg_usb3_0_reserved_6_6 - reserved
7326 */
7327#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_6_6_MASK)
7328#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK (0x80U)
7329#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT (7U)
7330/*! da_ip_usb3_wrap_lpm_clk_predft_STOP - show clock root status, 1 means clock stopped
7331 */
7332#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_lpm_clk_predft_STOP_MASK)
7333#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK (0x1FF00U)
7334#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT (8U)
7335/*! LPCG_lpcg_usb3_0_reserved_8_16 - reserved
7336 */
7337#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_8_16_MASK)
7338#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK (0x20000U)
7339#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT (17U)
7340/*! da_ip_usb3_wrap_ipg_clk_SWEN - Software Enable
7341 * 0b0..Disable SW clock regardless of HWEN
7342 * 0b1..Enable SW clock gating
7343 */
7344#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_SWEN_MASK)
7345#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK (0x40000U)
7346#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT (18U)
7347/*! LPCG_lpcg_usb3_0_reserved_18_18 - reserved
7348 */
7349#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_18_18_MASK)
7350#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK (0x80000U)
7351#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT (19U)
7352/*! da_ip_usb3_wrap_ipg_clk_STOP - show clock root status, 1 means clock stopped
7353 */
7354#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_ipg_clk_STOP_MASK)
7355#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK (0x100000U)
7356#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT (20U)
7357/*! LPCG_lpcg_usb3_0_reserved_20_20 - reserved
7358 */
7359#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_20_20_MASK)
7360#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK (0x200000U)
7361#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT (21U)
7362/*! da_ip_usb3_wrap_usb3_core_pclk_SWEN - Software Enable
7363 * 0b0..Disable SW clock regardless of HWEN
7364 * 0b1..Enable SW clock gating
7365 */
7366#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_SWEN_MASK)
7367#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK (0x400000U)
7368#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT (22U)
7369/*! LPCG_lpcg_usb3_0_reserved_22_22 - reserved
7370 */
7371#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_22_22_MASK)
7372#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK (0x800000U)
7373#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT (23U)
7374/*! da_ip_usb3_wrap_usb3_core_pclk_STOP - show clock root status, 1 means clock stopped
7375 */
7376#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_core_pclk_STOP_MASK)
7377#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK (0x1000000U)
7378#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT (24U)
7379/*! LPCG_lpcg_usb3_0_reserved_24_24 - reserved
7380 */
7381#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_24_24_MASK)
7382#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK (0x2000000U)
7383#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT (25U)
7384/*! da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN - Software Enable
7385 * 0b0..Disable SW clock regardless of HWEN
7386 * 0b1..Enable SW clock gating
7387 */
7388#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_SWEN_MASK)
7389#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK (0x4000000U)
7390#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT (26U)
7391/*! LPCG_lpcg_usb3_0_reserved_26_26 - reserved
7392 */
7393#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_26_26_MASK)
7394#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK (0x8000000U)
7395#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT (27U)
7396/*! da_ip_usb3_wrap_usb3_ssphy_pclk_STOP - show clock root status, 1 means clock stopped
7397 */
7398#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_ssphy_pclk_STOP_MASK)
7399#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK (0x10000000U)
7400#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT (28U)
7401/*! LPCG_lpcg_usb3_0_reserved_28_28 - reserved
7402 */
7403#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_28_28_MASK)
7404#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK (0x20000000U)
7405#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT (29U)
7406/*! da_ip_usb3_wrap_usb3_aclk_SWEN - Software Enable
7407 * 0b0..Disable SW clock regardless of HWEN
7408 * 0b1..Enable SW clock gating
7409 */
7410#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_SWEN_MASK)
7411#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK (0x40000000U)
7412#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT (30U)
7413/*! LPCG_lpcg_usb3_0_reserved_30_30 - reserved
7414 */
7415#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_LPCG_lpcg_usb3_0_reserved_30_30_MASK)
7416#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK (0x80000000U)
7417#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT (31U)
7418/*! da_ip_usb3_wrap_usb3_aclk_STOP - show clock root status, 1 means clock stopped
7419 */
7420#define CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USB3_LPCG_LPCG_USB3_0_da_ip_usb3_wrap_usb3_aclk_STOP_MASK)
7421/*! @} */
7422
7423
7424/*!
7425 * @}
7426 */ /* end of group CONNECTIVITY_LPCG_USB3_Register_Masks */
7427
7428
7429/* CONNECTIVITY_LPCG_USB3 - Peripheral instance base addresses */
7430/** Peripheral CONNECTIVITY__LPCG_USB3 base address */
7431#define CONNECTIVITY__LPCG_USB3_BASE (0x5B280000u)
7432/** Peripheral CONNECTIVITY__LPCG_USB3 base pointer */
7433#define CONNECTIVITY__LPCG_USB3 ((CONNECTIVITY_LPCG_USB3_Type *)CONNECTIVITY__LPCG_USB3_BASE)
7434/** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base addresses */
7435#define CONNECTIVITY_LPCG_USB3_BASE_ADDRS { CONNECTIVITY__LPCG_USB3_BASE }
7436/** Array initializer of CONNECTIVITY_LPCG_USB3 peripheral base pointers */
7437#define CONNECTIVITY_LPCG_USB3_BASE_PTRS { CONNECTIVITY__LPCG_USB3 }
7438
7439/*!
7440 * @}
7441 */ /* end of group CONNECTIVITY_LPCG_USB3_Peripheral_Access_Layer */
7442
7443
7444/* ----------------------------------------------------------------------------
7445 -- CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer
7446 ---------------------------------------------------------------------------- */
7447
7448/*!
7449 * @addtogroup CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC0 Peripheral Access Layer
7450 * @{
7451 */
7452
7453/** CONNECTIVITY_LPCG_USDHC0 - Register Layout Typedef */
7454typedef struct {
7455 __IO uint32_t LPCG_LPCG_USDHC1_0; /**< na, offset: 0x0 */
7456} CONNECTIVITY_LPCG_USDHC0_Type;
7457
7458/* ----------------------------------------------------------------------------
7459 -- CONNECTIVITY_LPCG_USDHC0 Register Masks
7460 ---------------------------------------------------------------------------- */
7461
7462/*!
7463 * @addtogroup CONNECTIVITY_LPCG_USDHC0_Register_Masks CONNECTIVITY_LPCG_USDHC0 Register Masks
7464 * @{
7465 */
7466
7467/*! @name LPCG_LPCG_USDHC1_0 - na */
7468/*! @{ */
7469#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK (0x1U)
7470#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT (0U)
7471/*! LPCG_lpcg_usdhc1_0_reserved_0_0 - reserved
7472 */
7473#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_0_0_MASK)
7474#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK (0x2U)
7475#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT (1U)
7476/*! usdhc1_ipg_clk_perclk_SWEN - Software Enable
7477 * 0b0..Disable SW clock regardless of HWEN
7478 * 0b1..Enable SW clock gating
7479 */
7480#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_SWEN_MASK)
7481#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK (0x4U)
7482#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT (2U)
7483/*! LPCG_lpcg_usdhc1_0_reserved_2_2 - reserved
7484 */
7485#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_2_2_MASK)
7486#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK (0x8U)
7487#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT (3U)
7488/*! usdhc1_ipg_clk_perclk_STOP - show clock root status, 1 means clock stopped
7489 */
7490#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_perclk_STOP_MASK)
7491#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK (0xFFF0U)
7492#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT (4U)
7493/*! LPCG_lpcg_usdhc1_0_reserved_4_15 - reserved
7494 */
7495#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_4_15_MASK)
7496#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK (0x10000U)
7497#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT (16U)
7498/*! usdhc1_ipg_clk_s_HWEN - Hardware Enable
7499 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7500 * 0b1..Enable HW automatic gating
7501 */
7502#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_HWEN_MASK)
7503#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK (0x20000U)
7504#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT (17U)
7505/*! usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN - Software Enable
7506 * 0b0..Disable SW clock regardless of HWEN
7507 * 0b1..Enable SW clock gating
7508 */
7509#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_SWEN_AND_usdhc1_ipg_clk_SWEN_MASK)
7510#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK (0x40000U)
7511#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT (18U)
7512/*! LPCG_lpcg_usdhc1_0_reserved_18_18 - reserved
7513 */
7514#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_18_18_MASK)
7515#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK (0x80000U)
7516#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT (19U)
7517/*! usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP - show clock root status, 1 means clock stopped
7518 */
7519#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_ipg_clk_s_STOP_AND_usdhc1_ipg_clk_STOP_MASK)
7520#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK (0x100000U)
7521#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT (20U)
7522/*! LPCG_lpcg_usdhc1_0_reserved_20_20 - reserved
7523 */
7524#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_20_20_MASK)
7525#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK (0x200000U)
7526#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT (21U)
7527/*! usdhc1_hclk_SWEN - Software Enable
7528 * 0b0..Disable SW clock regardless of HWEN
7529 * 0b1..Enable SW clock gating
7530 */
7531#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_SWEN_MASK)
7532#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK (0x400000U)
7533#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT (22U)
7534/*! LPCG_lpcg_usdhc1_0_reserved_22_22 - reserved
7535 */
7536#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_22_22_MASK)
7537#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK (0x800000U)
7538#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT (23U)
7539/*! usdhc1_hclk_STOP - show clock root status, 1 means clock stopped
7540 */
7541#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_usdhc1_hclk_STOP_MASK)
7542#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK (0xFF000000U)
7543#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT (24U)
7544/*! LPCG_lpcg_usdhc1_0_reserved_24_31 - reserved
7545 */
7546#define CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC0_LPCG_LPCG_USDHC1_0_LPCG_lpcg_usdhc1_0_reserved_24_31_MASK)
7547/*! @} */
7548
7549
7550/*!
7551 * @}
7552 */ /* end of group CONNECTIVITY_LPCG_USDHC0_Register_Masks */
7553
7554
7555/* CONNECTIVITY_LPCG_USDHC0 - Peripheral instance base addresses */
7556/** Peripheral CONNECTIVITY__LPCG_USDHC0 base address */
7557#define CONNECTIVITY__LPCG_USDHC0_BASE (0x5B200000u)
7558/** Peripheral CONNECTIVITY__LPCG_USDHC0 base pointer */
7559#define CONNECTIVITY__LPCG_USDHC0 ((CONNECTIVITY_LPCG_USDHC0_Type *)CONNECTIVITY__LPCG_USDHC0_BASE)
7560/** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base addresses */
7561#define CONNECTIVITY_LPCG_USDHC0_BASE_ADDRS { CONNECTIVITY__LPCG_USDHC0_BASE }
7562/** Array initializer of CONNECTIVITY_LPCG_USDHC0 peripheral base pointers */
7563#define CONNECTIVITY_LPCG_USDHC0_BASE_PTRS { CONNECTIVITY__LPCG_USDHC0 }
7564
7565/*!
7566 * @}
7567 */ /* end of group CONNECTIVITY_LPCG_USDHC0_Peripheral_Access_Layer */
7568
7569
7570/* ----------------------------------------------------------------------------
7571 -- CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer
7572 ---------------------------------------------------------------------------- */
7573
7574/*!
7575 * @addtogroup CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer CONNECTIVITY_LPCG_USDHC1 Peripheral Access Layer
7576 * @{
7577 */
7578
7579/** CONNECTIVITY_LPCG_USDHC1 - Register Layout Typedef */
7580typedef struct {
7581 __IO uint32_t LPCG_LPCG_USDHC2_0; /**< na, offset: 0x0 */
7582} CONNECTIVITY_LPCG_USDHC1_Type;
7583
7584/* ----------------------------------------------------------------------------
7585 -- CONNECTIVITY_LPCG_USDHC1 Register Masks
7586 ---------------------------------------------------------------------------- */
7587
7588/*!
7589 * @addtogroup CONNECTIVITY_LPCG_USDHC1_Register_Masks CONNECTIVITY_LPCG_USDHC1 Register Masks
7590 * @{
7591 */
7592
7593/*! @name LPCG_LPCG_USDHC2_0 - na */
7594/*! @{ */
7595#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK (0x1U)
7596#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT (0U)
7597/*! LPCG_lpcg_usdhc2_0_reserved_0_0 - reserved
7598 */
7599#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_0_0_MASK)
7600#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK (0x2U)
7601#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT (1U)
7602/*! usdhc2_ipg_clk_perclk_SWEN - Software Enable
7603 * 0b0..Disable SW clock regardless of HWEN
7604 * 0b1..Enable SW clock gating
7605 */
7606#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_SWEN_MASK)
7607#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK (0x4U)
7608#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT (2U)
7609/*! LPCG_lpcg_usdhc2_0_reserved_2_2 - reserved
7610 */
7611#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_2_2_MASK)
7612#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK (0x8U)
7613#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT (3U)
7614/*! usdhc2_ipg_clk_perclk_STOP - show clock root status, 1 means clock stopped
7615 */
7616#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_perclk_STOP_MASK)
7617#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK (0xFFF0U)
7618#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT (4U)
7619/*! LPCG_lpcg_usdhc2_0_reserved_4_15 - reserved
7620 */
7621#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_4_15_MASK)
7622#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK (0x10000U)
7623#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT (16U)
7624/*! usdhc2_ipg_clk_s_HWEN - Hardware Enable
7625 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7626 * 0b1..Enable HW automatic gating
7627 */
7628#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_HWEN_MASK)
7629#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK (0x20000U)
7630#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT (17U)
7631/*! usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN - Software Enable
7632 * 0b0..Disable SW clock regardless of HWEN
7633 * 0b1..Enable SW clock gating
7634 */
7635#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_SWEN_AND_usdhc2_ipg_clk_SWEN_MASK)
7636#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK (0x40000U)
7637#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT (18U)
7638/*! LPCG_lpcg_usdhc2_0_reserved_18_18 - reserved
7639 */
7640#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_18_18_MASK)
7641#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK (0x80000U)
7642#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT (19U)
7643/*! usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP - show clock root status, 1 means clock stopped
7644 */
7645#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_ipg_clk_s_STOP_AND_usdhc2_ipg_clk_STOP_MASK)
7646#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK (0x100000U)
7647#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT (20U)
7648/*! LPCG_lpcg_usdhc2_0_reserved_20_20 - reserved
7649 */
7650#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_20_20_MASK)
7651#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK (0x200000U)
7652#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT (21U)
7653/*! usdhc2_hclk_SWEN - Software Enable
7654 * 0b0..Disable SW clock regardless of HWEN
7655 * 0b1..Enable SW clock gating
7656 */
7657#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_SWEN_MASK)
7658#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK (0x400000U)
7659#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT (22U)
7660/*! LPCG_lpcg_usdhc2_0_reserved_22_22 - reserved
7661 */
7662#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_22_22_MASK)
7663#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK (0x800000U)
7664#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT (23U)
7665/*! usdhc2_hclk_STOP - show clock root status, 1 means clock stopped
7666 */
7667#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_usdhc2_hclk_STOP_MASK)
7668#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK (0xFF000000U)
7669#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT (24U)
7670/*! LPCG_lpcg_usdhc2_0_reserved_24_31 - reserved
7671 */
7672#define CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_SHIFT)) & CONNECTIVITY_LPCG_USDHC1_LPCG_LPCG_USDHC2_0_LPCG_lpcg_usdhc2_0_reserved_24_31_MASK)
7673/*! @} */
7674
7675
7676/*!
7677 * @}
7678 */ /* end of group CONNECTIVITY_LPCG_USDHC1_Register_Masks */
7679
7680
7681/* CONNECTIVITY_LPCG_USDHC1 - Peripheral instance base addresses */
7682/** Peripheral CONNECTIVITY__LPCG_USDHC1 base address */
7683#define CONNECTIVITY__LPCG_USDHC1_BASE (0x5B210000u)
7684/** Peripheral CONNECTIVITY__LPCG_USDHC1 base pointer */
7685#define CONNECTIVITY__LPCG_USDHC1 ((CONNECTIVITY_LPCG_USDHC1_Type *)CONNECTIVITY__LPCG_USDHC1_BASE)
7686/** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base addresses */
7687#define CONNECTIVITY_LPCG_USDHC1_BASE_ADDRS { CONNECTIVITY__LPCG_USDHC1_BASE }
7688/** Array initializer of CONNECTIVITY_LPCG_USDHC1 peripheral base pointers */
7689#define CONNECTIVITY_LPCG_USDHC1_BASE_PTRS { CONNECTIVITY__LPCG_USDHC1 }
7690
7691/*!
7692 * @}
7693 */ /* end of group CONNECTIVITY_LPCG_USDHC1_Peripheral_Access_Layer */
7694
7695
7696/* ----------------------------------------------------------------------------
7697 -- DC_LPCG Peripheral Access Layer
7698 ---------------------------------------------------------------------------- */
7699
7700/*!
7701 * @addtogroup DC_LPCG_Peripheral_Access_Layer DC_LPCG Peripheral Access Layer
7702 * @{
7703 */
7704
7705/** DC_LPCG - Register Layout Typedef */
7706typedef struct {
7707 __IO uint32_t LPCG_DC_LPCG_0; /**< na, offset: 0x0 */
7708 __IO uint32_t LPCG_DC_LPCG_4; /**< na, offset: 0x4 */
7709 __IO uint32_t LPCG_DC_LPCG_8; /**< na, offset: 0x8 */
7710 uint8_t RESERVED_0[4];
7711 __IO uint32_t LPCG_DC_LPCG_16; /**< na, offset: 0x10 */
7712 __IO uint32_t LPCG_DC_LPCG_20; /**< na, offset: 0x14 */
7713 __IO uint32_t LPCG_DC_LPCG_24; /**< na, offset: 0x18 */
7714 __IO uint32_t LPCG_DC_LPCG_28; /**< na, offset: 0x1C */
7715 __IO uint32_t LPCG_DC_LPCG_32; /**< na, offset: 0x20 */
7716 __IO uint32_t LPCG_DC_LPCG_36; /**< na, offset: 0x24 */
7717 __IO uint32_t LPCG_DC_LPCG_40; /**< na, offset: 0x28 */
7718 __IO uint32_t LPCG_DC_LPCG_44; /**< na, offset: 0x2C */
7719 __IO uint32_t LPCG_DC_LPCG_48; /**< na, offset: 0x30 */
7720 __IO uint32_t LPCG_DC_LPCG_52; /**< na, offset: 0x34 */
7721 __IO uint32_t LPCG_DC_LPCG_56; /**< na, offset: 0x38 */
7722 __IO uint32_t LPCG_DC_LPCG_60; /**< na, offset: 0x3C */
7723 __IO uint32_t LPCG_DC_LPCG_64; /**< na, offset: 0x40 */
7724 __IO uint32_t LPCG_DC_LPCG_68; /**< na, offset: 0x44 */
7725 __IO uint32_t LPCG_DC_LPCG_72; /**< na, offset: 0x48 */
7726} DC_LPCG_Type;
7727
7728/* ----------------------------------------------------------------------------
7729 -- DC_LPCG Register Masks
7730 ---------------------------------------------------------------------------- */
7731
7732/*!
7733 * @addtogroup DC_LPCG_Register_Masks DC_LPCG Register Masks
7734 * @{
7735 */
7736
7737/*! @name LPCG_DC_LPCG_0 - na */
7738/*! @{ */
7739#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK (0x1U)
7740#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT (0U)
7741/*! LPCG_dc_lpcg_0_reserved_0_0 - reserved
7742 */
7743#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_0_0_MASK)
7744#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK (0x2U)
7745#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT (1U)
7746/*! dsp0_clk_SWEN - Software Enable
7747 * 0b0..Disable SW clock regardless of HWEN
7748 * 0b1..Enable SW clock gating
7749 */
7750#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_SWEN_MASK)
7751#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK (0x4U)
7752#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT (2U)
7753/*! LPCG_dc_lpcg_0_reserved_2_2 - reserved
7754 */
7755#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_2_2_MASK)
7756#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK (0x8U)
7757#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT (3U)
7758/*! dsp0_clk_STOP - show clock root status, 1 means clock stopped
7759 */
7760#define DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp0_clk_STOP_MASK)
7761#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK (0x10U)
7762#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT (4U)
7763/*! LPCG_dc_lpcg_0_reserved_4_4 - reserved
7764 */
7765#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_4_4_MASK)
7766#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK (0x20U)
7767#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT (5U)
7768/*! dsp1_clk_SWEN - Software Enable
7769 * 0b0..Disable SW clock regardless of HWEN
7770 * 0b1..Enable SW clock gating
7771 */
7772#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_SWEN_MASK)
7773#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK (0x40U)
7774#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT (6U)
7775/*! LPCG_dc_lpcg_0_reserved_6_6 - reserved
7776 */
7777#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_6_6_MASK)
7778#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK (0x80U)
7779#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT (7U)
7780/*! dsp1_clk_STOP - show clock root status, 1 means clock stopped
7781 */
7782#define DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_dsp1_clk_STOP_MASK)
7783#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK (0xFFFFFF00U)
7784#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT (8U)
7785/*! LPCG_dc_lpcg_0_reserved_8_31 - reserved
7786 */
7787#define DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_0_LPCG_dc_lpcg_0_reserved_8_31_MASK)
7788/*! @} */
7789
7790/*! @name LPCG_DC_LPCG_4 - na */
7791/*! @{ */
7792#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK (0xFFFFU)
7793#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT (0U)
7794/*! LPCG_dc_lpcg_4_reserved_0_15 - reserved
7795 */
7796#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_0_15_MASK)
7797#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK (0x10000U)
7798#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT (16U)
7799/*! lis_ipg_clk_HWEN - Hardware Enable
7800 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7801 * 0b1..Enable HW automatic gating
7802 */
7803#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_HWEN_MASK)
7804#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK (0x20000U)
7805#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT (17U)
7806/*! lis_ipg_clk_SWEN - Software Enable
7807 * 0b0..Disable SW clock regardless of HWEN
7808 * 0b1..Enable SW clock gating
7809 */
7810#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_SWEN_MASK)
7811#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK (0x40000U)
7812#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT (18U)
7813/*! LPCG_dc_lpcg_4_reserved_18_18 - reserved
7814 */
7815#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_18_18_MASK)
7816#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK (0x80000U)
7817#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT (19U)
7818/*! lis_ipg_clk_STOP - show clock root status, 1 means clock stopped
7819 */
7820#define DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_lis_ipg_clk_STOP_MASK)
7821#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK (0xFFF00000U)
7822#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT (20U)
7823/*! LPCG_dc_lpcg_4_reserved_20_31 - reserved
7824 */
7825#define DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_4_LPCG_dc_lpcg_4_reserved_20_31_MASK)
7826/*! @} */
7827
7828/*! @name LPCG_DC_LPCG_8 - na */
7829/*! @{ */
7830#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK (0xFFFFU)
7831#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT (0U)
7832/*! LPCG_dc_lpcg_8_reserved_0_15 - reserved
7833 */
7834#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_0_15_MASK)
7835#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK (0x10000U)
7836#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT (16U)
7837/*! display_ctrl_link_mst0_msi_clk_HWEN - Hardware Enable
7838 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7839 * 0b1..Enable HW automatic gating
7840 */
7841#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_HWEN_MASK)
7842#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK (0x20000U)
7843#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT (17U)
7844/*! display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN - Software Enable
7845 * 0b0..Disable SW clock regardless of HWEN
7846 * 0b1..Enable SW clock gating
7847 */
7848#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_SWEN_AND_display_ctrl_link_mst0_hclk_SWEN_MASK)
7849#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK (0x40000U)
7850#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT (18U)
7851/*! LPCG_dc_lpcg_8_reserved_18_18 - reserved
7852 */
7853#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_18_18_MASK)
7854#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK (0x80000U)
7855#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT (19U)
7856/*! display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP - show clock root status, 1 means clock stopped
7857 */
7858#define DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_display_ctrl_link_mst0_msi_clk_STOP_AND_display_ctrl_link_mst0_hclk_STOP_MASK)
7859#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK (0xFFF00000U)
7860#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT (20U)
7861/*! LPCG_dc_lpcg_8_reserved_20_31 - reserved
7862 */
7863#define DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_8_LPCG_dc_lpcg_8_reserved_20_31_MASK)
7864/*! @} */
7865
7866/*! @name LPCG_DC_LPCG_16 - na */
7867/*! @{ */
7868#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK (0xFFFFU)
7869#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT (0U)
7870/*! LPCG_dc_lpcg_16_reserved_0_15 - reserved
7871 */
7872#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_0_15_MASK)
7873#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK (0x10000U)
7874#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT (16U)
7875/*! pixel_combiner_apb_clk_HWEN - Hardware Enable
7876 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7877 * 0b1..Enable HW automatic gating
7878 */
7879#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_HWEN_MASK)
7880#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK (0x20000U)
7881#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT (17U)
7882/*! pixel_combiner_apb_clk_SWEN - Software Enable
7883 * 0b0..Disable SW clock regardless of HWEN
7884 * 0b1..Enable SW clock gating
7885 */
7886#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_SWEN_MASK)
7887#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK (0x40000U)
7888#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT (18U)
7889/*! LPCG_dc_lpcg_16_reserved_18_18 - reserved
7890 */
7891#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_18_18_MASK)
7892#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK (0x80000U)
7893#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT (19U)
7894/*! pixel_combiner_apb_clk_STOP - show clock root status, 1 means clock stopped
7895 */
7896#define DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_pixel_combiner_apb_clk_STOP_MASK)
7897#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK (0xFFF00000U)
7898#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT (20U)
7899/*! LPCG_dc_lpcg_16_reserved_20_31 - reserved
7900 */
7901#define DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_16_LPCG_dc_lpcg_16_reserved_20_31_MASK)
7902/*! @} */
7903
7904/*! @name LPCG_DC_LPCG_20 - na */
7905/*! @{ */
7906#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK (0xFFFFU)
7907#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT (0U)
7908/*! LPCG_dc_lpcg_20_reserved_0_15 - reserved
7909 */
7910#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_0_15_MASK)
7911#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK (0x10000U)
7912#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT (16U)
7913/*! iris_mvpl_cfg_clk_HWEN - Hardware Enable
7914 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7915 * 0b1..Enable HW automatic gating
7916 */
7917#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_HWEN_MASK)
7918#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK (0x20000U)
7919#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT (17U)
7920/*! iris_mvpl_cfg_clk_SWEN - Software Enable
7921 * 0b0..Disable SW clock regardless of HWEN
7922 * 0b1..Enable SW clock gating
7923 */
7924#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_SWEN_MASK)
7925#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK (0x40000U)
7926#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT (18U)
7927/*! LPCG_dc_lpcg_20_reserved_18_18 - reserved
7928 */
7929#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_18_18_MASK)
7930#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK (0x80000U)
7931#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT (19U)
7932/*! iris_mvpl_cfg_clk_STOP - show clock root status, 1 means clock stopped
7933 */
7934#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_cfg_clk_STOP_MASK)
7935#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK (0x100000U)
7936#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT (20U)
7937/*! LPCG_dc_lpcg_20_reserved_20_20 - reserved
7938 */
7939#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_20_20_MASK)
7940#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK (0x200000U)
7941#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT (21U)
7942/*! iris_mvpl_axi_clk_SWEN - Software Enable
7943 * 0b0..Disable SW clock regardless of HWEN
7944 * 0b1..Enable SW clock gating
7945 */
7946#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_SWEN_MASK)
7947#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK (0x400000U)
7948#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT (22U)
7949/*! LPCG_dc_lpcg_20_reserved_22_22 - reserved
7950 */
7951#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_22_22_MASK)
7952#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK (0x800000U)
7953#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT (23U)
7954/*! iris_mvpl_axi_clk_STOP - show clock root status, 1 means clock stopped
7955 */
7956#define DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_iris_mvpl_axi_clk_STOP_MASK)
7957#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK (0xFF000000U)
7958#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT (24U)
7959/*! LPCG_dc_lpcg_20_reserved_24_31 - reserved
7960 */
7961#define DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_20_LPCG_dc_lpcg_20_reserved_24_31_MASK)
7962/*! @} */
7963
7964/*! @name LPCG_DC_LPCG_24 - na */
7965/*! @{ */
7966#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK (0xFFFFU)
7967#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT (0U)
7968/*! LPCG_dc_lpcg_24_reserved_0_15 - reserved
7969 */
7970#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_0_15_MASK)
7971#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK (0x10000U)
7972#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT (16U)
7973/*! dpr0_dpr_apb_clkg_HWEN - Hardware Enable
7974 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7975 * 0b1..Enable HW automatic gating
7976 */
7977#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_HWEN_MASK)
7978#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK (0x20000U)
7979#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT (17U)
7980/*! dpr0_dpr_apb_clkg_SWEN - Software Enable
7981 * 0b0..Disable SW clock regardless of HWEN
7982 * 0b1..Enable SW clock gating
7983 */
7984#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_SWEN_MASK)
7985#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK (0x40000U)
7986#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT (18U)
7987/*! LPCG_dc_lpcg_24_reserved_18_18 - reserved
7988 */
7989#define DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_LPCG_dc_lpcg_24_reserved_18_18_MASK)
7990#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK (0x80000U)
7991#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT (19U)
7992/*! dpr0_dpr_apb_clkg_STOP - show clock root status, 1 means clock stopped
7993 */
7994#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP(x) (((uint32_t)(((uint32_t)(x)) << DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_SHIFT)) & DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_apb_clkg_STOP_MASK)
7995#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_MASK (0x100000U)
7996#define DC_LPCG_LPCG_DC_LPCG_24_dpr0_dpr_b_clkg_HWEN_SHIFT (20U)
7997/*! dpr0_dpr_b_clkg_HWEN - Hardware Enable
7998 * 0b0..Ignore all HW signal (if swen!=0 it&apos;s always on)
7999 * 0b1..Enable HW automatic gating
8000 */