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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1011/MIMXRT1011.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1011/MIMXRT1011.h
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@@ -0,0 +1,31446 @@
1/*
2** ###################################################################
3** Processors: MIMXRT1011CAE4A
4** MIMXRT1011DAE5A
5**
6** Compilers: Freescale C/C++ for Embedded ARM
7** GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10** MCUXpresso Compiler
11**
12** Reference manual: IMXRT1010RM Rev.0, 09/2019
13** Version: rev. 1.1, 2019-08-06
14** Build: b201019
15**
16** Abstract:
17** CMSIS Peripheral Access Layer for MIMXRT1011
18**
19** Copyright 1997-2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2020 NXP
21** All rights reserved.
22**
23** SPDX-License-Identifier: BSD-3-Clause
24**
25** http: www.nxp.com
26** mail: [email protected]
27**
28** Revisions:
29** - rev. 0.1 (2019-02-14)
30** Initial version.
31** - rev. 1.0 (2019-08-01)
32** Rev.0 Header GA
33** - rev. 1.1 (2019-08-06)
34** Update header files to align with IMXRT1010RM Rev.B.
35**
36** ###################################################################
37*/
38
39/*!
40 * @file MIMXRT1011.h
41 * @version 1.1
42 * @date 2019-08-06
43 * @brief CMSIS Peripheral Access Layer for MIMXRT1011
44 *
45 * CMSIS Peripheral Access Layer for MIMXRT1011
46 */
47
48#ifndef _MIMXRT1011_H_
49#define _MIMXRT1011_H_ /**< Symbol preventing repeated inclusion */
50
51/** Memory map major version (memory maps with equal major version number are
52 * compatible) */
53#define MCU_MEM_MAP_VERSION 0x0100U
54/** Memory map minor version */
55#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
56
57
58/* ----------------------------------------------------------------------------
59 -- Interrupt vector numbers
60 ---------------------------------------------------------------------------- */
61
62/*!
63 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
64 * @{
65 */
66
67/** Interrupt Number Definitions */
68#define NUMBER_OF_INT_VECTORS 96 /**< Number of interrupts in the Vector table */
69
70typedef enum IRQn {
71 /* Auxiliary constants */
72 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
73
74 /* Core interrupts */
75 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
76 HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */
77 MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */
78 BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */
79 UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */
80 SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */
81 DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */
82 PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */
83 SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */
84
85 /* Device specific interrupts */
86 DMA0_IRQn = 0, /**< DMA channel 0 transfer complete */
87 DMA1_IRQn = 1, /**< DMA channel 1 transfer complete */
88 DMA2_IRQn = 2, /**< DMA channel 2 transfer complete */
89 DMA3_IRQn = 3, /**< DMA channel 3 transfer complete */
90 DMA4_IRQn = 4, /**< DMA channel 4 transfer complete */
91 DMA5_IRQn = 5, /**< DMA channel 5 transfer complete */
92 DMA6_IRQn = 6, /**< DMA channel 6 transfer complete */
93 DMA7_IRQn = 7, /**< DMA channel 7 transfer complete */
94 DMA8_IRQn = 8, /**< DMA channel 8 transfer complete */
95 DMA9_IRQn = 9, /**< DMA channel 9 transfer complete */
96 DMA10_IRQn = 10, /**< DMA channel 10 transfer complete */
97 DMA11_IRQn = 11, /**< DMA channel 11 transfer complete */
98 DMA12_IRQn = 12, /**< DMA channel 12 transfer complete */
99 DMA13_IRQn = 13, /**< DMA channel 13 transfer complete */
100 DMA14_IRQn = 14, /**< DMA channel 14 transfer complete */
101 DMA15_IRQn = 15, /**< DMA channel 15 transfer complete */
102 DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 */
103 CTI0_ERROR_IRQn = 17, /**< CTI trigger outputs */
104 CTI1_ERROR_IRQn = 18, /**< CTI trigger outputs */
105 CORE_IRQn = 19, /**< CorePlatform exception IRQ */
106 LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */
107 LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */
108 LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */
109 LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */
110 PIT_IRQn = 24, /**< PIT interrupt */
111 USB_OTG1_IRQn = 25, /**< USBO2 USB OTG1 */
112 FLEXSPI_IRQn = 26, /**< FlexSPI0 interrupt */
113 FLEXRAM_IRQn = 27, /**< FlexRAM address out of range Or access hit IRQ */
114 LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */
115 LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */
116 GPT1_IRQn = 30, /**< GPT1 interrupt */
117 GPT2_IRQn = 31, /**< GPT2 interrupt */
118 LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */
119 LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */
120 PWM1_0_IRQn = 34, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
121 PWM1_1_IRQn = 35, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */
122 PWM1_2_IRQn = 36, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */
123 PWM1_3_IRQn = 37, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */
124 PWM1_FAULT_IRQn = 38, /**< PWM1 fault or reload error interrupt */
125 KPP_IRQn = 39, /**< Keypad nterrupt */
126 SRC_IRQn = 40, /**< SRC interrupt */
127 GPR_IRQ_IRQn = 41, /**< Used to notify cores on exception condition while boot */
128 CCM_1_IRQn = 42, /**< CCM IRQ1 interrupt */
129 CCM_2_IRQn = 43, /**< CCM IRQ2 interrupt */
130 EWM_IRQn = 44, /**< EWM interrupt */
131 WDOG2_IRQn = 45, /**< WDOG2 interrupt */
132 SNVS_HP_WRAPPER_IRQn = 46, /**< SNVS Functional Interrupt */
133 SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SNVS Security Interrupt */
134 SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */
135 CSU_IRQn = 49, /**< CSU interrupt */
136 DCP_IRQn = 50, /**< Combined DCP channel interrupts(except channel 0) and CRC interrupt */
137 DCP_VMI_IRQn = 51, /**< IRQ of DCP channel 0 */
138 Reserved68_IRQn = 52, /**< Reserved interrupt */
139 TRNG_IRQn = 53, /**< TRNG interrupt */
140 Reserved70_IRQn = 54, /**< Reserved interrupt */
141 Reserved71_IRQn = 55, /**< Reserved interrupt */
142 SAI1_IRQn = 56, /**< SAI1 interrupt */
143 RTWDOG_IRQn = 57, /**< RTWDOG interrupt */
144 SAI3_RX_IRQn = 58, /**< SAI3 interrupt */
145 SAI3_TX_IRQn = 59, /**< SAI3 interrupt */
146 SPDIF_IRQn = 60, /**< SPDIF interrupt */
147 PMU_IRQn = 61, /**< PMU interrupt */
148 XBAR1_IRQ_0_1_2_3_IRQn = 62, /**< XBAR1 interrupt */
149 TEMP_LOW_HIGH_IRQn = 63, /**< TEMPMON interrupt */
150 TEMP_PANIC_IRQn = 64, /**< TEMPMON interrupt */
151 USB_PHY_IRQn = 65, /**< USBPHY (OTG1 UTMI), Interrupt */
152 GPC_IRQn = 66, /**< GPC interrupt */
153 ADC1_IRQn = 67, /**< ADC1 interrupt */
154 FLEXIO1_IRQn = 68, /**< FLEXIO1 interrupt */
155 DCDC_IRQn = 69, /**< DCDC interrupt */
156 GPIO1_Combined_0_15_IRQn = 70, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
157 GPIO1_Combined_16_31_IRQn = 71, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
158 GPIO2_Combined_0_15_IRQn = 72, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
159 GPIO5_Combined_0_15_IRQn = 73, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
160 WDOG1_IRQn = 74, /**< WDOG1 interrupt */
161 ADC_ETC_IRQ0_IRQn = 75, /**< ADCETC IRQ0 interrupt */
162 ADC_ETC_IRQ1_IRQn = 76, /**< ADCETC IRQ1 interrupt */
163 ADC_ETC_IRQ2_IRQn = 77, /**< ADCETC IRQ2 interrupt */
164 ADC_ETC_IRQ3_IRQn = 78, /**< ADCETC IRQ3 interrupt */
165 ADC_ETC_ERROR_IRQ_IRQn = 79 /**< ADCETC Error IRQ interrupt */
166} IRQn_Type;
167
168/*!
169 * @}
170 */ /* end of group Interrupt_vector_numbers */
171
172
173/* ----------------------------------------------------------------------------
174 -- Cortex M7 Core Configuration
175 ---------------------------------------------------------------------------- */
176
177/*!
178 * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
179 * @{
180 */
181
182#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
183#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */
184#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */
185#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */
186#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
187#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
188#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
189
190#include "core_cm7.h" /* Core Peripheral Access Layer */
191#include "system_MIMXRT1011.h" /* Device specific configuration file */
192
193/*!
194 * @}
195 */ /* end of group Cortex_Core_Configuration */
196
197
198/* ----------------------------------------------------------------------------
199 -- Mapping Information
200 ---------------------------------------------------------------------------- */
201
202/*!
203 * @addtogroup Mapping_Information Mapping Information
204 * @{
205 */
206
207/** Mapping Information */
208/*!
209 * @addtogroup edma_request
210 * @{
211 */
212
213/*******************************************************************************
214 * Definitions
215 ******************************************************************************/
216
217/*!
218 * @brief Structure for the DMA hardware request
219 *
220 * Defines the structure for the DMA hardware request collections. The user can configure the
221 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
222 * of the hardware request varies according to the to SoC.
223 */
224typedef enum _dma_request_source
225{
226 kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */
227 kDmaRequestMuxFlexIO1Request4Request5 = 1|0x100U, /**< FlexIO1 Request4 and Request5 */
228 kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */
229 kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */
230 kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */
231 kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */
232 kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */
233 kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */
234 kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */
235 kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */
236 kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */
237 kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */
238 kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */
239 kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FLEXSPI Receive */
240 kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FLEXSPI Transmit */
241 kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR Request 0 */
242 kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR Request 1 */
243 kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */
244 kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */
245 kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */
246 kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */
247 kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */
248 kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */
249 kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */
250 kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */
251 kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */
252 kDmaRequestMuxFlexIO1Request6Request7 = 65|0x100U, /**< FlexIO1 Request6 and Request7 */
253 kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */
254 kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */
255 kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */
256 kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */
257 kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */
258 kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */
259 kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */
260 kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */
261 kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */
262 kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */
263 kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */
264 kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR Request 2 */
265 kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR Request 3 */
266} dma_request_source_t;
267
268/* @} */
269
270/*!
271 * @addtogroup iomuxc_pads
272 * @{ */
273
274/*******************************************************************************
275 * Definitions
276*******************************************************************************/
277
278/*!
279 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
280 *
281 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
282 */
283typedef enum _iomuxc_sw_mux_ctl_pad
284{
285 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
286 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
287 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
288 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
289 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
290 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
291 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
292 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
293 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
294 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
295 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
296 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
297 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
298 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
299 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
300 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_14 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
301 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_13 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
302 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_12 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
303 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_11 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
304 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_10 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
305 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_09 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
306 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_08 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
307 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_07 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
308 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_06 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
309 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_05 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
310 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_04 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
311 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_03 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
312 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_02 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
313 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_01 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
314 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_00 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
315 kIOMUXC_SW_MUX_CTL_PAD_GPIO_13 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
316 kIOMUXC_SW_MUX_CTL_PAD_GPIO_12 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
317 kIOMUXC_SW_MUX_CTL_PAD_GPIO_11 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
318 kIOMUXC_SW_MUX_CTL_PAD_GPIO_10 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
319 kIOMUXC_SW_MUX_CTL_PAD_GPIO_09 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
320 kIOMUXC_SW_MUX_CTL_PAD_GPIO_08 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
321 kIOMUXC_SW_MUX_CTL_PAD_GPIO_07 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
322 kIOMUXC_SW_MUX_CTL_PAD_GPIO_06 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
323 kIOMUXC_SW_MUX_CTL_PAD_GPIO_05 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
324 kIOMUXC_SW_MUX_CTL_PAD_GPIO_04 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
325 kIOMUXC_SW_MUX_CTL_PAD_GPIO_03 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
326 kIOMUXC_SW_MUX_CTL_PAD_GPIO_02 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
327 kIOMUXC_SW_MUX_CTL_PAD_GPIO_01 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
328 kIOMUXC_SW_MUX_CTL_PAD_GPIO_00 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
329} iomuxc_sw_mux_ctl_pad_t;
330
331/* @} */
332
333/*!
334 * @addtogroup iomuxc_pads
335 * @{ */
336
337/*******************************************************************************
338 * Definitions
339*******************************************************************************/
340
341/*!
342 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
343 *
344 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
345 */
346typedef enum _iomuxc_sw_pad_ctl_pad
347{
348 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
349 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
350 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
351 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
352 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
353 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
354 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
355 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
356 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
357 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
358 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
359 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
360 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
361 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
362 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
363 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_14 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
364 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_13 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
365 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_12 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
366 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_11 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
367 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_10 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
368 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_09 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
369 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_08 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
370 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_07 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
371 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_06 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
372 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_05 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
373 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_04 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
374 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_03 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
375 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_02 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
376 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_01 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
377 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_00 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
378 kIOMUXC_SW_PAD_CTL_PAD_GPIO_13 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
379 kIOMUXC_SW_PAD_CTL_PAD_GPIO_12 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
380 kIOMUXC_SW_PAD_CTL_PAD_GPIO_11 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
381 kIOMUXC_SW_PAD_CTL_PAD_GPIO_10 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
382 kIOMUXC_SW_PAD_CTL_PAD_GPIO_09 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
383 kIOMUXC_SW_PAD_CTL_PAD_GPIO_08 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
384 kIOMUXC_SW_PAD_CTL_PAD_GPIO_07 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
385 kIOMUXC_SW_PAD_CTL_PAD_GPIO_06 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
386 kIOMUXC_SW_PAD_CTL_PAD_GPIO_05 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
387 kIOMUXC_SW_PAD_CTL_PAD_GPIO_04 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
388 kIOMUXC_SW_PAD_CTL_PAD_GPIO_03 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
389 kIOMUXC_SW_PAD_CTL_PAD_GPIO_02 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
390 kIOMUXC_SW_PAD_CTL_PAD_GPIO_01 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
391 kIOMUXC_SW_PAD_CTL_PAD_GPIO_00 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
392} iomuxc_sw_pad_ctl_pad_t;
393
394/* @} */
395
396/*!
397 * @brief Enumeration for the IOMUXC select input
398 *
399 * Defines the enumeration for the IOMUXC select input collections.
400 */
401typedef enum _iomuxc_select_input
402{
403 kIOMUXC_USB_OTG_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */
404 kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 = 1U, /**< IOMUXC select input index */
405 kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 = 2U, /**< IOMUXC select input index */
406 kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 = 3U, /**< IOMUXC select input index */
407 kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_3 = 4U, /**< IOMUXC select input index */
408 kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 = 5U, /**< IOMUXC select input index */
409 kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 = 6U, /**< IOMUXC select input index */
410 kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 = 7U, /**< IOMUXC select input index */
411 kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_3 = 8U, /**< IOMUXC select input index */
412 kIOMUXC_FLEXSPI_DQS_FA_SELECT_INPUT = 9U, /**< IOMUXC select input index */
413 kIOMUXC_FLEXSPI_DQS_FB_SELECT_INPUT = 10U, /**< IOMUXC select input index */
414 kIOMUXC_KPP_COL_SELECT_INPUT_0 = 11U, /**< IOMUXC select input index */
415 kIOMUXC_KPP_COL_SELECT_INPUT_1 = 12U, /**< IOMUXC select input index */
416 kIOMUXC_KPP_COL_SELECT_INPUT_2 = 13U, /**< IOMUXC select input index */
417 kIOMUXC_KPP_COL_SELECT_INPUT_3 = 14U, /**< IOMUXC select input index */
418 kIOMUXC_KPP_ROW_SELECT_INPUT_0 = 15U, /**< IOMUXC select input index */
419 kIOMUXC_KPP_ROW_SELECT_INPUT_1 = 16U, /**< IOMUXC select input index */
420 kIOMUXC_KPP_ROW_SELECT_INPUT_2 = 17U, /**< IOMUXC select input index */
421 kIOMUXC_KPP_ROW_SELECT_INPUT_3 = 18U, /**< IOMUXC select input index */
422 kIOMUXC_LPI2C1_HREQ_SELECT_INPUT = 19U, /**< IOMUXC select input index */
423 kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 20U, /**< IOMUXC select input index */
424 kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 21U, /**< IOMUXC select input index */
425 kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 22U, /**< IOMUXC select input index */
426 kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 23U, /**< IOMUXC select input index */
427 kIOMUXC_LPSPI1_PCS_SELECT_INPUT_0 = 24U, /**< IOMUXC select input index */
428 kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 25U, /**< IOMUXC select input index */
429 kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 26U, /**< IOMUXC select input index */
430 kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 27U, /**< IOMUXC select input index */
431 kIOMUXC_LPSPI2_PCS_SELECT_INPUT_0 = 28U, /**< IOMUXC select input index */
432 kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 29U, /**< IOMUXC select input index */
433 kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 30U, /**< IOMUXC select input index */
434 kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 31U, /**< IOMUXC select input index */
435 kIOMUXC_LPUART1_RXD_SELECT_INPUT = 32U, /**< IOMUXC select input index */
436 kIOMUXC_LPUART1_TXD_SELECT_INPUT = 33U, /**< IOMUXC select input index */
437 kIOMUXC_LPUART2_RXD_SELECT_INPUT = 34U, /**< IOMUXC select input index */
438 kIOMUXC_LPUART2_TXD_SELECT_INPUT = 35U, /**< IOMUXC select input index */
439 kIOMUXC_LPUART3_RXD_SELECT_INPUT = 36U, /**< IOMUXC select input index */
440 kIOMUXC_LPUART3_TXD_SELECT_INPUT = 37U, /**< IOMUXC select input index */
441 kIOMUXC_LPUART4_RXD_SELECT_INPUT = 38U, /**< IOMUXC select input index */
442 kIOMUXC_LPUART4_TXD_SELECT_INPUT = 39U, /**< IOMUXC select input index */
443 kIOMUXC_NMI_GLUE_NMI_SELECT_INPUT = 40U, /**< IOMUXC select input index */
444 kIOMUXC_SPDIF_IN1_SELECT_INPUT = 41U, /**< IOMUXC select input index */
445 kIOMUXC_SPDIF_TX_CLK2_SELECT_INPUT = 42U, /**< IOMUXC select input index */
446 kIOMUXC_USB_OTG_OC_SELECT_INPUT = 43U, /**< IOMUXC select input index */
447 kIOMUXC_XEV_GLUE_RXEV_SELECT_INPUT = 44U, /**< IOMUXC select input index */
448} iomuxc_select_input_t;
449
450typedef enum _xbar_input_signal
451{
452 kXBARA1_InputRESERVED0 = 0|0x100U, /**< XBARA_IN0 input is reserved. */
453 kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA_IN1 input. */
454 kXBARA1_InputIomuxXbarInout02 = 2|0x100U, /**< IOMUX_XBAR_INOUT02 output assigned to XBARA_IN2 input. */
455 kXBARA1_InputIomuxXbarInout03 = 3|0x100U, /**< IOMUX_XBAR_INOUT03 output assigned to XBARA_IN3 input. */
456 kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 4|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA_IN4 input. */
457 kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 5|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA_IN5 input. */
458 kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 6|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA_IN6 input. */
459 kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 7|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA_IN7 input. */
460 kXBARA1_InputPitTrigger0 = 8|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA_IN8 input. */
461 kXBARA1_InputPitTrigger1 = 9|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA_IN9 input. */
462 kXBARA1_InputPitTrigger2 = 10|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA_IN10 input. */
463 kXBARA1_InputPitTrigger3 = 11|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA_IN11 input. */
464 kXBARA1_InputDmaDone0 = 12|0x100U, /**< DMA_DONE0 output assigned to XBARA_IN12 input. */
465 kXBARA1_InputDmaDone1 = 13|0x100U, /**< DMA_DONE1 output assigned to XBARA_IN13 input. */
466 kXBARA1_InputDmaDone2 = 14|0x100U, /**< DMA_DONE2 output assigned to XBARA_IN14 input. */
467 kXBARA1_InputDmaDone3 = 15|0x100U, /**< DMA_DONE3 output assigned to XBARA_IN15 input. */
468 kXBARA1_InputDmaDone4 = 16|0x100U, /**< DMA_DONE4 output assigned to XBARA_IN16 input. */
469 kXBARA1_InputDmaDone5 = 17|0x100U, /**< DMA_DONE5 output assigned to XBARA_IN17 input. */
470 kXBARA1_InputDmaDone6 = 18|0x100U, /**< DMA_DONE6 output assigned to XBARA_IN18 input. */
471 kXBARA1_InputDmaDone7 = 19|0x100U, /**< DMA_DONE7 output assigned to XBARA_IN19 input. */
472 kXBARA1_InputAoi1Out0 = 20|0x100U, /**< AOI1_OUT0 output assigned to XBARA_IN20 input. */
473 kXBARA1_InputAoi1Out1 = 21|0x100U, /**< AOI1_OUT1 output assigned to XBARA_IN21 input. */
474 kXBARA1_InputAoi1Out2 = 22|0x100U, /**< AOI1_OUT2 output assigned to XBARA_IN22 input. */
475 kXBARA1_InputAoi1Out3 = 23|0x100U, /**< AOI1_OUT3 output assigned to XBARA_IN23 input. */
476 kXBARA1_InputAdcEtc0Coco0 = 24|0x100U, /**< ADC_ETC0_COCO0 output assigned to XBARA_IN24 input. */
477 kXBARA1_InputAdcEtc0Coco1 = 25|0x100U, /**< ADC_ETC0_COCO1 output assigned to XBARA_IN25 input. */
478 kXBARA1_InputAdcEtc0Coco2 = 26|0x100U, /**< ADC_ETC0_COCO2 output assigned to XBARA_IN26 input. */
479 kXBARA1_InputAdcEtc0Coco3 = 27|0x100U, /**< ADC_ETC0_COCO3 output assigned to XBARA_IN27 input. */
480} xbar_input_signal_t;
481
482typedef enum _xbar_output_signal
483{
484 kXBARA1_OutputFlexio1TriggerIn0 = 0|0x100U, /**< XBARA_OUT0 output assigned to FLEXIO1_TRIGGER_IN0 */
485 kXBARA1_OutputFlexio1TriggerIn1 = 1|0x100U, /**< XBARA_OUT1 output assigned to FLEXIO1_TRIGGER_IN1 */
486 kXBARA1_OutputIomuxXbarInout02 = 2|0x100U, /**< XBARA_OUT2 output assigned to IOMUX_XBAR_INOUT02 */
487 kXBARA1_OutputIomuxXbarInout03 = 3|0x100U, /**< XBARA_OUT3 output assigned to IOMUX_XBAR_INOUT03 */
488 kXBARA1_OutputFlexpwm1Exta0 = 4|0x100U, /**< XBARA_OUT4 output assigned to FLEXPWM1_EXTA0 */
489 kXBARA1_OutputFlexpwm1Exta1 = 5|0x100U, /**< XBARA_OUT5 output assigned to FLEXPWM1_EXTA1 */
490 kXBARA1_OutputFlexpwm1Exta2 = 6|0x100U, /**< XBARA_OUT6 output assigned to FLEXPWM1_EXTA2 */
491 kXBARA1_OutputFlexpwm1Exta3 = 7|0x100U, /**< XBARA_OUT7 output assigned to FLEXPWM1_EXTA3 */
492 kXBARA1_OutputFlexpwm1ExtSync0 = 8|0x100U, /**< XBARA_OUT8 output assigned to FLEXPWM1_EXT_SYNC0 */
493 kXBARA1_OutputFlexpwm1ExtSync1 = 9|0x100U, /**< XBARA_OUT9 output assigned to FLEXPWM1_EXT_SYNC1 */
494 kXBARA1_OutputFlexpwm1ExtSync2 = 10|0x100U, /**< XBARA_OUT10 output assigned to FLEXPWM1_EXT_SYNC2 */
495 kXBARA1_OutputFlexpwm1ExtSync3 = 11|0x100U, /**< XBARA_OUT11 output assigned to FLEXPWM1_EXT_SYNC3 */
496 kXBARA1_OutputFlexpwm1ExtClk = 12|0x100U, /**< XBARA_OUT12 output assigned to FLEXPWM1_EXT_CLK */
497 kXBARA1_OutputFlexpwm1Fault0 = 13|0x100U, /**< XBARA_OUT13 output assigned to FLEXPWM1_FAULT0 */
498 kXBARA1_OutputFlexpwm1Fault1 = 14|0x100U, /**< XBARA_OUT14 output assigned to FLEXPWM1_FAULT1 */
499 kXBARA1_OutputFlexpwm1Fault2 = 15|0x100U, /**< XBARA_OUT15 output assigned to FLEXPWM1_FAULT2 */
500 kXBARA1_OutputFlexpwm1Fault3 = 16|0x100U, /**< XBARA_OUT16 output assigned to FLEXPWM1_FAULT3 */
501 kXBARA1_OutputFlexpwm1ExtForce = 17|0x100U, /**< XBARA_OUT17 output assigned to FLEXPWM1_EXT_FORCE */
502 kXBARA1_OutputEwmEwmIn = 18|0x100U, /**< XBARA_OUT18 output assigned to EWM_EWM_IN */
503 kXBARA1_OutputAdcEtcTrig00 = 19|0x100U, /**< XBARA_OUT19 output assigned to ADC_ETC_TRIG00 */
504 kXBARA1_OutputAdcEtcTrig01 = 20|0x100U, /**< XBARA_OUT20 output assigned to ADC_ETC_TRIG01 */
505 kXBARA1_OutputAdcEtcTrig02 = 21|0x100U, /**< XBARA_OUT21 output assigned to ADC_ETC_TRIG02 */
506 kXBARA1_OutputAdcEtcTrig03 = 22|0x100U, /**< XBARA_OUT22 output assigned to ADC_ETC_TRIG03 */
507 kXBARA1_OutputLpi2c1TrgInput = 23|0x100U, /**< XBARA_OUT23 output assigned to LPI2C1_TRG_INPUT */
508 kXBARA1_OutputLpi2c2TrgInput = 24|0x100U, /**< XBARA_OUT24 output assigned to LPI2C2_TRG_INPUT */
509 kXBARA1_OutputLpspi1TrgInput = 25|0x100U, /**< XBARA_OUT25 output assigned to LPSPI1_TRG_INPUT */
510 kXBARA1_OutputLpspi2TrgInput = 26|0x100U, /**< XBARA_OUT26 output assigned to LPSPI2_TRG_INPUT */
511 kXBARA1_OutputLpuart1TrgInput = 27|0x100U, /**< XBARA_OUT27 output assigned to LPUART1_TRG_INPUT */
512 kXBARA1_OutputLpuart2TrgInput = 28|0x100U, /**< XBARA_OUT28 output assigned to LPUART2_TRG_INPUT */
513 kXBARA1_OutputLpuart3TrgInput = 29|0x100U, /**< XBARA_OUT29 output assigned to LPUART3_TRG_INPUT */
514 kXBARA1_OutputLpuart4TrgInput = 30|0x100U, /**< XBARA_OUT30 output assigned to LPUART4_TRG_INPUT */
515} xbar_output_signal_t;
516
517
518/*!
519 * @}
520 */ /* end of group Mapping_Information */
521
522
523/* ----------------------------------------------------------------------------
524 -- Device Peripheral Access Layer
525 ---------------------------------------------------------------------------- */
526
527/*!
528 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
529 * @{
530 */
531
532
533/*
534** Start of section using anonymous unions
535*/
536
537#if defined(__ARMCC_VERSION)
538 #if (__ARMCC_VERSION >= 6010050)
539 #pragma clang diagnostic push
540 #else
541 #pragma push
542 #pragma anon_unions
543 #endif
544#elif defined(__CWCC__)
545 #pragma push
546 #pragma cpp_extensions on
547#elif defined(__GNUC__)
548 /* anonymous unions are enabled by default */
549#elif defined(__IAR_SYSTEMS_ICC__)
550 #pragma language=extended
551#else
552 #error Not supported compiler type
553#endif
554
555/* ----------------------------------------------------------------------------
556 -- ADC Peripheral Access Layer
557 ---------------------------------------------------------------------------- */
558
559/*!
560 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
561 * @{
562 */
563
564/** ADC - Register Layout Typedef */
565typedef struct {
566 __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */
567 __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */
568 __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */
569 __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */
570 __IO uint32_t GC; /**< General control register, offset: 0x48 */
571 __IO uint32_t GS; /**< General status register, offset: 0x4C */
572 __IO uint32_t CV; /**< Compare value register, offset: 0x50 */
573 __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */
574 __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */
575} ADC_Type;
576
577/* ----------------------------------------------------------------------------
578 -- ADC Register Masks
579 ---------------------------------------------------------------------------- */
580
581/*!
582 * @addtogroup ADC_Register_Masks ADC Register Masks
583 * @{
584 */
585
586/*! @name HC - Control register for hardware triggers */
587/*! @{ */
588#define ADC_HC_ADCH_MASK (0x1FU)
589#define ADC_HC_ADCH_SHIFT (0U)
590/*! ADCH - Input Channel Select
591 * 0b10000..External channel selection from ADC_ETC
592 * 0b11000..Reserved.
593 * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally
594 * 0b11010..Reserved.
595 * 0b11011..Reserved.
596 * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion.
597 */
598#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
599#define ADC_HC_AIEN_MASK (0x80U)
600#define ADC_HC_AIEN_SHIFT (7U)
601/*! AIEN - Conversion Complete Interrupt Enable/Disable Control
602 * 0b1..Conversion complete interrupt enabled
603 * 0b0..Conversion complete interrupt disabled
604 */
605#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
606/*! @} */
607
608/* The count of ADC_HC */
609#define ADC_HC_COUNT (8U)
610
611/*! @name HS - Status register for HW triggers */
612/*! @{ */
613#define ADC_HS_COCO0_MASK (0x1U)
614#define ADC_HS_COCO0_SHIFT (0U)
615/*! COCO0 - Conversion Complete Flag
616 */
617#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
618/*! @} */
619
620/*! @name R - Data result register for HW triggers */
621/*! @{ */
622#define ADC_R_CDATA_MASK (0xFFFU)
623#define ADC_R_CDATA_SHIFT (0U)
624/*! CDATA - Data (result of an ADC conversion)
625 */
626#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
627/*! @} */
628
629/* The count of ADC_R */
630#define ADC_R_COUNT (8U)
631
632/*! @name CFG - Configuration register */
633/*! @{ */
634#define ADC_CFG_ADICLK_MASK (0x3U)
635#define ADC_CFG_ADICLK_SHIFT (0U)
636/*! ADICLK - Input Clock Select
637 * 0b00..IPG clock
638 * 0b01..IPG clock divided by 2
639 * 0b10..Alternate clock (ALTCLK)
640 * 0b11..Asynchronous clock (ADACK)
641 */
642#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
643#define ADC_CFG_MODE_MASK (0xCU)
644#define ADC_CFG_MODE_SHIFT (2U)
645/*! MODE - Conversion Mode Selection
646 * 0b00..8-bit conversion
647 * 0b01..10-bit conversion
648 * 0b10..12-bit conversion
649 * 0b11..Reserved
650 */
651#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
652#define ADC_CFG_ADLSMP_MASK (0x10U)
653#define ADC_CFG_ADLSMP_SHIFT (4U)
654/*! ADLSMP - Long Sample Time Configuration
655 * 0b0..Short sample mode.
656 * 0b1..Long sample mode.
657 */
658#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
659#define ADC_CFG_ADIV_MASK (0x60U)
660#define ADC_CFG_ADIV_SHIFT (5U)
661/*! ADIV - Clock Divide Select
662 * 0b00..Input clock
663 * 0b01..Input clock / 2
664 * 0b10..Input clock / 4
665 * 0b11..Input clock / 8
666 */
667#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
668#define ADC_CFG_ADLPC_MASK (0x80U)
669#define ADC_CFG_ADLPC_SHIFT (7U)
670/*! ADLPC - Low-Power Configuration
671 * 0b0..ADC hard block not in low power mode.
672 * 0b1..ADC hard block in low power mode.
673 */
674#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
675#define ADC_CFG_ADSTS_MASK (0x300U)
676#define ADC_CFG_ADSTS_SHIFT (8U)
677/*! ADSTS
678 * 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b
679 * 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b
680 * 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b
681 * 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b
682 */
683#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
684#define ADC_CFG_ADHSC_MASK (0x400U)
685#define ADC_CFG_ADHSC_SHIFT (10U)
686/*! ADHSC - High Speed Configuration
687 * 0b0..Normal conversion selected.
688 * 0b1..High speed conversion selected.
689 */
690#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
691#define ADC_CFG_REFSEL_MASK (0x1800U)
692#define ADC_CFG_REFSEL_SHIFT (11U)
693/*! REFSEL - Voltage Reference Selection
694 * 0b00..Selects VREFH/VREFL as reference voltage.
695 * 0b01..Reserved
696 * 0b10..Reserved
697 * 0b11..Reserved
698 */
699#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
700#define ADC_CFG_ADTRG_MASK (0x2000U)
701#define ADC_CFG_ADTRG_SHIFT (13U)
702/*! ADTRG - Conversion Trigger Select
703 * 0b0..Software trigger selected
704 * 0b1..Hardware trigger selected
705 */
706#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
707#define ADC_CFG_AVGS_MASK (0xC000U)
708#define ADC_CFG_AVGS_SHIFT (14U)
709/*! AVGS - Hardware Average select
710 * 0b00..4 samples averaged
711 * 0b01..8 samples averaged
712 * 0b10..16 samples averaged
713 * 0b11..32 samples averaged
714 */
715#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
716#define ADC_CFG_OVWREN_MASK (0x10000U)
717#define ADC_CFG_OVWREN_SHIFT (16U)
718/*! OVWREN - Data Overwrite Enable
719 * 0b1..Enable the overwriting.
720 * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.
721 */
722#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
723/*! @} */
724
725/*! @name GC - General control register */
726/*! @{ */
727#define ADC_GC_ADACKEN_MASK (0x1U)
728#define ADC_GC_ADACKEN_SHIFT (0U)
729/*! ADACKEN - Asynchronous clock output enable
730 * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.
731 * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC
732 */
733#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
734#define ADC_GC_DMAEN_MASK (0x2U)
735#define ADC_GC_DMAEN_SHIFT (1U)
736/*! DMAEN - DMA Enable
737 * 0b0..DMA disabled (default)
738 * 0b1..DMA enabled
739 */
740#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
741#define ADC_GC_ACREN_MASK (0x4U)
742#define ADC_GC_ACREN_SHIFT (2U)
743/*! ACREN - Compare Function Range Enable
744 * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared.
745 * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.
746 */
747#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
748#define ADC_GC_ACFGT_MASK (0x8U)
749#define ADC_GC_ACFGT_SHIFT (3U)
750/*! ACFGT - Compare Function Greater Than Enable
751 * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive"
752 * functionality based on the values placed in the ADC_CV register.
753 * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive"
754 * functionality based on the values placed in the ADC_CV registers.
755 */
756#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
757#define ADC_GC_ACFE_MASK (0x10U)
758#define ADC_GC_ACFE_SHIFT (4U)
759/*! ACFE - Compare Function Enable
760 * 0b0..Compare function disabled
761 * 0b1..Compare function enabled
762 */
763#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
764#define ADC_GC_AVGE_MASK (0x20U)
765#define ADC_GC_AVGE_SHIFT (5U)
766/*! AVGE - Hardware average enable
767 * 0b0..Hardware average function disabled
768 * 0b1..Hardware average function enabled
769 */
770#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
771#define ADC_GC_ADCO_MASK (0x40U)
772#define ADC_GC_ADCO_SHIFT (6U)
773/*! ADCO - Continuous Conversion Enable
774 * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
775 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
776 */
777#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
778#define ADC_GC_CAL_MASK (0x80U)
779#define ADC_GC_CAL_SHIFT (7U)
780/*! CAL - Calibration
781 */
782#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
783/*! @} */
784
785/*! @name GS - General status register */
786/*! @{ */
787#define ADC_GS_ADACT_MASK (0x1U)
788#define ADC_GS_ADACT_SHIFT (0U)
789/*! ADACT - Conversion Active
790 * 0b0..Conversion not in progress.
791 * 0b1..Conversion in progress.
792 */
793#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
794#define ADC_GS_CALF_MASK (0x2U)
795#define ADC_GS_CALF_SHIFT (1U)
796/*! CALF - Calibration Failed Flag
797 * 0b0..Calibration completed normally.
798 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
799 */
800#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
801#define ADC_GS_AWKST_MASK (0x4U)
802#define ADC_GS_AWKST_SHIFT (2U)
803/*! AWKST - Asynchronous wakeup interrupt status
804 * 0b1..Asynchronous wake up interrupt occurred in stop mode.
805 * 0b0..No asynchronous interrupt.
806 */
807#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
808/*! @} */
809
810/*! @name CV - Compare value register */
811/*! @{ */
812#define ADC_CV_CV1_MASK (0xFFFU)
813#define ADC_CV_CV1_SHIFT (0U)
814/*! CV1 - Compare Value 1
815 */
816#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
817#define ADC_CV_CV2_MASK (0xFFF0000U)
818#define ADC_CV_CV2_SHIFT (16U)
819/*! CV2 - Compare Value 2
820 */
821#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
822/*! @} */
823
824/*! @name OFS - Offset correction value register */
825/*! @{ */
826#define ADC_OFS_OFS_MASK (0xFFFU)
827#define ADC_OFS_OFS_SHIFT (0U)
828/*! OFS - Offset value
829 */
830#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
831#define ADC_OFS_SIGN_MASK (0x1000U)
832#define ADC_OFS_SIGN_SHIFT (12U)
833/*! SIGN - Sign bit
834 * 0b0..The offset value is added with the raw result
835 * 0b1..The offset value is subtracted from the raw converted value
836 */
837#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
838/*! @} */
839
840/*! @name CAL - Calibration value register */
841/*! @{ */
842#define ADC_CAL_CAL_CODE_MASK (0xFU)
843#define ADC_CAL_CAL_CODE_SHIFT (0U)
844/*! CAL_CODE - Calibration Result Value
845 */
846#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)
847/*! @} */
848
849
850/*!
851 * @}
852 */ /* end of group ADC_Register_Masks */
853
854
855/* ADC - Peripheral instance base addresses */
856/** Peripheral ADC1 base address */
857#define ADC1_BASE (0x400C4000u)
858/** Peripheral ADC1 base pointer */
859#define ADC1 ((ADC_Type *)ADC1_BASE)
860/** Array initializer of ADC peripheral base addresses */
861#define ADC_BASE_ADDRS { 0u, ADC1_BASE }
862/** Array initializer of ADC peripheral base pointers */
863#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1 }
864/** Interrupt vectors for the ADC peripheral type */
865#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn }
866
867/*!
868 * @}
869 */ /* end of group ADC_Peripheral_Access_Layer */
870
871
872/* ----------------------------------------------------------------------------
873 -- ADC_ETC Peripheral Access Layer
874 ---------------------------------------------------------------------------- */
875
876/*!
877 * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
878 * @{
879 */
880
881/** ADC_ETC - Register Layout Typedef */
882typedef struct {
883 __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */
884 __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */
885 __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */
886 __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */
887 struct { /* offset: 0x10, array step: 0x28 */
888 __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG Control Register, array offset: 0x10, array step: 0x28 */
889 __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28 */
890 __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */
891 __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */
892 __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */
893 __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */
894 __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */
895 __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */
896 __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */
897 __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */
898 } TRIG[4];
899} ADC_ETC_Type;
900
901/* ----------------------------------------------------------------------------
902 -- ADC_ETC Register Masks
903 ---------------------------------------------------------------------------- */
904
905/*!
906 * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
907 * @{
908 */
909
910/*! @name CTRL - ADC_ETC Global Control Register */
911/*! @{ */
912#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
913#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
914#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
915#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
916#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
917#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
918#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
919#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
920#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
921#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
922#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
923#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
924#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
925#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
926#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
927#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
928#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
929#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
930#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
931#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
932#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
933#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
934#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
935#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
936#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
937#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
938#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
939/*! @} */
940
941/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
942/*! @{ */
943#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
944#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
945#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
946#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
947#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
948#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
949#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
950#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
951#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
952#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
953#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
954#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
955#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
956#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
957#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
958#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
959#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
960#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
961#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
962#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
963#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
964#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
965#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
966#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
967#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
968#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
969#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
970#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
971#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
972#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
973#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
974#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
975#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
976#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
977#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
978#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
979#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
980#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
981#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
982#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
983#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
984#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
985#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
986#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
987#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
988#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
989#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
990#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
991/*! @} */
992
993/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */
994/*! @{ */
995#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
996#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
997#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)
998#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
999#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
1000#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)
1001#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
1002#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
1003#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)
1004#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
1005#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
1006#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)
1007#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
1008#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
1009#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)
1010#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
1011#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
1012#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)
1013#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
1014#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
1015#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)
1016#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
1017#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
1018#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)
1019#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE3_MASK (0x100U)
1020#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE3_SHIFT (8U)
1021#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE3_MASK)
1022#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE3_MASK (0x200U)
1023#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE3_SHIFT (9U)
1024#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE3_MASK)
1025#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE3_MASK (0x400U)
1026#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE3_SHIFT (10U)
1027#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE3_MASK)
1028#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE3_MASK (0x800U)
1029#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE3_SHIFT (11U)
1030#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE3_MASK)
1031#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE3_MASK (0x1000U)
1032#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE3_SHIFT (12U)
1033#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE3_MASK)
1034#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE3_MASK (0x2000U)
1035#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE3_SHIFT (13U)
1036#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE3_MASK)
1037#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE3_MASK (0x4000U)
1038#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE3_SHIFT (14U)
1039#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE3_MASK)
1040#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE3_MASK (0x8000U)
1041#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE3_SHIFT (15U)
1042#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE3_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE3_MASK)
1043#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
1044#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
1045#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)
1046#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
1047#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
1048#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)
1049#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
1050#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
1051#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)
1052#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
1053#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
1054#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)
1055#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
1056#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
1057#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)
1058#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
1059#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
1060#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)
1061#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
1062#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
1063#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)
1064#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
1065#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
1066#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)
1067/*! @} */
1068
1069/*! @name DMA_CTRL - ETC DMA control Register */
1070/*! @{ */
1071#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
1072#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
1073#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
1074#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
1075#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
1076#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
1077#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
1078#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
1079#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
1080#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
1081#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
1082#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
1083#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
1084#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
1085#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
1086#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
1087#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
1088#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
1089#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
1090#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
1091#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
1092#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
1093#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
1094#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
1095#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
1096#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
1097#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
1098#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
1099#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
1100#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
1101#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
1102#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
1103#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
1104#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
1105#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
1106#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
1107#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
1108#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
1109#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
1110#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
1111#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
1112#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
1113#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
1114#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
1115#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
1116#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
1117#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
1118#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
1119/*! @} */
1120
1121/*! @name TRIGn_CTRL - ETC_TRIG Control Register */
1122/*! @{ */
1123#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
1124#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
1125#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
1126#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
1127#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
1128#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
1129#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
1130#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
1131#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
1132#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
1133#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
1134#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
1135#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
1136#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
1137#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
1138#define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK (0xFF000000U)
1139#define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT (24U)
1140#define ADC_ETC_TRIGn_CTRL_CHAINx_DONE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT)) & ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK)
1141/*! @} */
1142
1143/* The count of ADC_ETC_TRIGn_CTRL */
1144#define ADC_ETC_TRIGn_CTRL_COUNT (4U)
1145
1146/*! @name TRIGn_COUNTER - ETC_TRIG Counter Register */
1147/*! @{ */
1148#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
1149#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
1150#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
1151#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
1152#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
1153#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
1154/*! @} */
1155
1156/* The count of ADC_ETC_TRIGn_COUNTER */
1157#define ADC_ETC_TRIGn_COUNTER_COUNT (4U)
1158
1159/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
1160/*! @{ */
1161#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
1162#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
1163#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
1164#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
1165#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
1166#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
1167#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
1168#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
1169#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
1170#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
1171#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
1172#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
1173#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK (0x8000U)
1174#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT (15U)
1175#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK)
1176#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
1177#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
1178#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
1179#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
1180#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
1181#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
1182#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
1183#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
1184#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
1185#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
1186#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
1187#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
1188#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK (0x80000000U)
1189#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT (31U)
1190#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK)
1191/*! @} */
1192
1193/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
1194#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (4U)
1195
1196/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
1197/*! @{ */
1198#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
1199#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
1200#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
1201#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
1202#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
1203#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
1204#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
1205#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
1206#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
1207#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
1208#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
1209#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
1210#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK (0x8000U)
1211#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT (15U)
1212#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK)
1213#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
1214#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
1215#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
1216#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
1217#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
1218#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
1219#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
1220#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
1221#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
1222#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
1223#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
1224#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
1225#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK (0x80000000U)
1226#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT (31U)
1227#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK)
1228/*! @} */
1229
1230/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
1231#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (4U)
1232
1233/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
1234/*! @{ */
1235#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
1236#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
1237#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
1238#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
1239#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
1240#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
1241#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
1242#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
1243#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
1244#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
1245#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
1246#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
1247#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK (0x8000U)
1248#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT (15U)
1249#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK)
1250#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
1251#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
1252#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
1253#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
1254#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
1255#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
1256#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
1257#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
1258#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
1259#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
1260#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
1261#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
1262#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK (0x80000000U)
1263#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT (31U)
1264#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK)
1265/*! @} */
1266
1267/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
1268#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (4U)
1269
1270/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
1271/*! @{ */
1272#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
1273#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
1274#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
1275#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
1276#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
1277#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
1278#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
1279#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
1280#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
1281#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
1282#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
1283#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
1284#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK (0x8000U)
1285#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT (15U)
1286#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK)
1287#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
1288#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
1289#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
1290#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
1291#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
1292#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
1293#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
1294#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
1295#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
1296#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
1297#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
1298#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
1299#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK (0x80000000U)
1300#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT (31U)
1301#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK)
1302/*! @} */
1303
1304/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
1305#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (4U)
1306
1307/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
1308/*! @{ */
1309#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
1310#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
1311#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
1312#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
1313#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
1314#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
1315/*! @} */
1316
1317/* The count of ADC_ETC_TRIGn_RESULT_1_0 */
1318#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (4U)
1319
1320/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
1321/*! @{ */
1322#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
1323#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
1324#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
1325#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
1326#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
1327#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
1328/*! @} */
1329
1330/* The count of ADC_ETC_TRIGn_RESULT_3_2 */
1331#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (4U)
1332
1333/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
1334/*! @{ */
1335#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
1336#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
1337#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
1338#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
1339#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
1340#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
1341/*! @} */
1342
1343/* The count of ADC_ETC_TRIGn_RESULT_5_4 */
1344#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (4U)
1345
1346/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
1347/*! @{ */
1348#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
1349#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
1350#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
1351#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
1352#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
1353#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
1354/*! @} */
1355
1356/* The count of ADC_ETC_TRIGn_RESULT_7_6 */
1357#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (4U)
1358
1359
1360/*!
1361 * @}
1362 */ /* end of group ADC_ETC_Register_Masks */
1363
1364
1365/* ADC_ETC - Peripheral instance base addresses */
1366/** Peripheral ADC_ETC base address */
1367#define ADC_ETC_BASE (0x40088000u)
1368/** Peripheral ADC_ETC base pointer */
1369#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
1370/** Array initializer of ADC_ETC peripheral base addresses */
1371#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
1372/** Array initializer of ADC_ETC peripheral base pointers */
1373#define ADC_ETC_BASE_PTRS { ADC_ETC }
1374/** Interrupt vectors for the ADC_ETC peripheral type */
1375#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn, ADC_ETC_IRQ3_IRQn } }
1376#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
1377
1378/*!
1379 * @}
1380 */ /* end of group ADC_ETC_Peripheral_Access_Layer */
1381
1382
1383/* ----------------------------------------------------------------------------
1384 -- AIPSTZ Peripheral Access Layer
1385 ---------------------------------------------------------------------------- */
1386
1387/*!
1388 * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
1389 * @{
1390 */
1391
1392/** AIPSTZ - Register Layout Typedef */
1393typedef struct {
1394 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */
1395 uint8_t RESERVED_0[60];
1396 __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
1397 __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
1398 __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
1399 __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
1400 __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
1401} AIPSTZ_Type;
1402
1403/* ----------------------------------------------------------------------------
1404 -- AIPSTZ Register Masks
1405 ---------------------------------------------------------------------------- */
1406
1407/*!
1408 * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
1409 * @{
1410 */
1411
1412/*! @name MPR - Master Priviledge Registers */
1413/*! @{ */
1414#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
1415#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
1416/*! MPROT5
1417 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1418 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1419 * 0bxx0x..This master is not trusted for write accesses.
1420 * 0bxx1x..This master is trusted for write accesses.
1421 * 0bx0xx..This master is not trusted for read accesses.
1422 * 0bx1xx..This master is trusted for read accesses.
1423 * 0b1xxx..Write accesses from this master are allowed to be buffered
1424 */
1425#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
1426#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
1427#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
1428/*! MPROT3
1429 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1430 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1431 * 0bxx0x..This master is not trusted for write accesses.
1432 * 0bxx1x..This master is trusted for write accesses.
1433 * 0bx0xx..This master is not trusted for read accesses.
1434 * 0bx1xx..This master is trusted for read accesses.
1435 * 0b1xxx..Write accesses from this master are allowed to be buffered
1436 */
1437#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
1438#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
1439#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
1440/*! MPROT2
1441 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1442 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1443 * 0bxx0x..This master is not trusted for write accesses.
1444 * 0bxx1x..This master is trusted for write accesses.
1445 * 0bx0xx..This master is not trusted for read accesses.
1446 * 0bx1xx..This master is trusted for read accesses.
1447 * 0b1xxx..Write accesses from this master are allowed to be buffered
1448 */
1449#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
1450#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
1451#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
1452/*! MPROT1
1453 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1454 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1455 * 0bxx0x..This master is not trusted for write accesses.
1456 * 0bxx1x..This master is trusted for write accesses.
1457 * 0bx0xx..This master is not trusted for read accesses.
1458 * 0bx1xx..This master is trusted for read accesses.
1459 * 0b1xxx..Write accesses from this master are allowed to be buffered
1460 */
1461#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
1462#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
1463#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
1464/*! MPROT0
1465 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1466 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1467 * 0bxx0x..This master is not trusted for write accesses.
1468 * 0bxx1x..This master is trusted for write accesses.
1469 * 0bx0xx..This master is not trusted for read accesses.
1470 * 0bx1xx..This master is trusted for read accesses.
1471 * 0b1xxx..Write accesses from this master are allowed to be buffered
1472 */
1473#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
1474/*! @} */
1475
1476/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
1477/*! @{ */
1478#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
1479#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
1480/*! OPAC7
1481 * 0bxxx0..Accesses from an untrusted master are allowed.
1482 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1483 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1484 * 0bxx0x..This peripheral allows write accesses.
1485 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1486 * error response and no peripheral access is initiated on the IPS bus.
1487 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1488 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1489 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1490 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1491 * on the IPS bus.
1492 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1493 */
1494#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
1495#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
1496#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
1497/*! OPAC6
1498 * 0bxxx0..Accesses from an untrusted master are allowed.
1499 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1500 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1501 * 0bxx0x..This peripheral allows write accesses.
1502 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1503 * error response and no peripheral access is initiated on the IPS bus.
1504 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1505 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1506 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1507 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1508 * on the IPS bus.
1509 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1510 */
1511#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
1512#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
1513#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
1514/*! OPAC5
1515 * 0bxxx0..Accesses from an untrusted master are allowed.
1516 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1517 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1518 * 0bxx0x..This peripheral allows write accesses.
1519 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1520 * error response and no peripheral access is initiated on the IPS bus.
1521 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1522 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1523 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1524 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1525 * on the IPS bus.
1526 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1527 */
1528#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
1529#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
1530#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
1531/*! OPAC4
1532 * 0bxxx0..Accesses from an untrusted master are allowed.
1533 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1534 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1535 * 0bxx0x..This peripheral allows write accesses.
1536 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1537 * error response and no peripheral access is initiated on the IPS bus.
1538 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1539 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1540 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1541 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1542 * on the IPS bus.
1543 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1544 */
1545#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
1546#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
1547#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
1548/*! OPAC3
1549 * 0bxxx0..Accesses from an untrusted master are allowed.
1550 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1551 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1552 * 0bxx0x..This peripheral allows write accesses.
1553 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1554 * error response and no peripheral access is initiated on the IPS bus.
1555 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1556 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1557 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1558 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1559 * on the IPS bus.
1560 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1561 */
1562#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
1563#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
1564#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
1565/*! OPAC2
1566 * 0bxxx0..Accesses from an untrusted master are allowed.
1567 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1568 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1569 * 0bxx0x..This peripheral allows write accesses.
1570 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1571 * error response and no peripheral access is initiated on the IPS bus.
1572 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1573 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1574 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1575 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1576 * on the IPS bus.
1577 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1578 */
1579#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
1580#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
1581#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
1582/*! OPAC1
1583 * 0bxxx0..Accesses from an untrusted master are allowed.
1584 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1585 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1586 * 0bxx0x..This peripheral allows write accesses.
1587 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1588 * error response and no peripheral access is initiated on the IPS bus.
1589 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1590 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1591 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1592 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1593 * on the IPS bus.
1594 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1595 */
1596#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
1597#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
1598#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
1599/*! OPAC0
1600 * 0bxxx0..Accesses from an untrusted master are allowed.
1601 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1602 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1603 * 0bxx0x..This peripheral allows write accesses.
1604 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1605 * error response and no peripheral access is initiated on the IPS bus.
1606 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1607 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1608 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1609 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1610 * on the IPS bus.
1611 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1612 */
1613#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
1614/*! @} */
1615
1616/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
1617/*! @{ */
1618#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
1619#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
1620/*! OPAC15
1621 * 0bxxx0..Accesses from an untrusted master are allowed.
1622 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1623 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1624 * 0bxx0x..This peripheral allows write accesses.
1625 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1626 * error response and no peripheral access is initiated on the IPS bus.
1627 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1628 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1629 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1630 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1631 * on the IPS bus.
1632 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1633 */
1634#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
1635#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
1636#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
1637/*! OPAC14
1638 * 0bxxx0..Accesses from an untrusted master are allowed.
1639 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1640 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1641 * 0bxx0x..This peripheral allows write accesses.
1642 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1643 * error response and no peripheral access is initiated on the IPS bus.
1644 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1645 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1646 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1647 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1648 * on the IPS bus.
1649 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1650 */
1651#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
1652#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
1653#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
1654/*! OPAC13
1655 * 0bxxx0..Accesses from an untrusted master are allowed.
1656 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1657 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1658 * 0bxx0x..This peripheral allows write accesses.
1659 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1660 * error response and no peripheral access is initiated on the IPS bus.
1661 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1662 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1663 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1664 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1665 * on the IPS bus.
1666 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1667 */
1668#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
1669#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
1670#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
1671/*! OPAC12
1672 * 0bxxx0..Accesses from an untrusted master are allowed.
1673 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1674 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1675 * 0bxx0x..This peripheral allows write accesses.
1676 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1677 * error response and no peripheral access is initiated on the IPS bus.
1678 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1679 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1680 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1681 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1682 * on the IPS bus.
1683 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1684 */
1685#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
1686#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
1687#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
1688/*! OPAC11
1689 * 0bxxx0..Accesses from an untrusted master are allowed.
1690 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1691 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1692 * 0bxx0x..This peripheral allows write accesses.
1693 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1694 * error response and no peripheral access is initiated on the IPS bus.
1695 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1696 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1697 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1698 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1699 * on the IPS bus.
1700 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1701 */
1702#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
1703#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
1704#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
1705/*! OPAC10
1706 * 0bxxx0..Accesses from an untrusted master are allowed.
1707 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1708 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1709 * 0bxx0x..This peripheral allows write accesses.
1710 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1711 * error response and no peripheral access is initiated on the IPS bus.
1712 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1713 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1714 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1715 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1716 * on the IPS bus.
1717 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1718 */
1719#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
1720#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
1721#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
1722/*! OPAC9
1723 * 0bxxx0..Accesses from an untrusted master are allowed.
1724 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1725 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1726 * 0bxx0x..This peripheral allows write accesses.
1727 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1728 * error response and no peripheral access is initiated on the IPS bus.
1729 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1730 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1731 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1732 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1733 * on the IPS bus.
1734 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1735 */
1736#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
1737#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
1738#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
1739/*! OPAC8
1740 * 0bxxx0..Accesses from an untrusted master are allowed.
1741 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1742 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1743 * 0bxx0x..This peripheral allows write accesses.
1744 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1745 * error response and no peripheral access is initiated on the IPS bus.
1746 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1747 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1748 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1749 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1750 * on the IPS bus.
1751 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1752 */
1753#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
1754/*! @} */
1755
1756/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
1757/*! @{ */
1758#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
1759#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
1760/*! OPAC23
1761 * 0bxxx0..Accesses from an untrusted master are allowed.
1762 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1763 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1764 * 0bxx0x..This peripheral allows write accesses.
1765 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1766 * error response and no peripheral access is initiated on the IPS bus.
1767 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1768 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1769 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1770 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1771 * on the IPS bus.
1772 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1773 */
1774#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
1775#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
1776#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
1777/*! OPAC22
1778 * 0bxxx0..Accesses from an untrusted master are allowed.
1779 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1780 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1781 * 0bxx0x..This peripheral allows write accesses.
1782 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1783 * error response and no peripheral access is initiated on the IPS bus.
1784 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1785 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1786 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1787 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1788 * on the IPS bus.
1789 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1790 */
1791#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
1792#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
1793#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
1794/*! OPAC21
1795 * 0bxxx0..Accesses from an untrusted master are allowed.
1796 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1797 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1798 * 0bxx0x..This peripheral allows write accesses.
1799 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1800 * error response and no peripheral access is initiated on the IPS bus.
1801 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1802 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1803 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1804 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1805 * on the IPS bus.
1806 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1807 */
1808#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
1809#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
1810#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
1811/*! OPAC20
1812 * 0bxxx0..Accesses from an untrusted master are allowed.
1813 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1814 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1815 * 0bxx0x..This peripheral allows write accesses.
1816 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1817 * error response and no peripheral access is initiated on the IPS bus.
1818 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1819 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1820 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1821 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1822 * on the IPS bus.
1823 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1824 */
1825#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
1826#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
1827#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
1828/*! OPAC19
1829 * 0bxxx0..Accesses from an untrusted master are allowed.
1830 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1831 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1832 * 0bxx0x..This peripheral allows write accesses.
1833 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1834 * error response and no peripheral access is initiated on the IPS bus.
1835 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1836 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1837 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1838 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1839 * on the IPS bus.
1840 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1841 */
1842#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
1843#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
1844#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
1845/*! OPAC18
1846 * 0bxxx0..Accesses from an untrusted master are allowed.
1847 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1848 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1849 * 0bxx0x..This peripheral allows write accesses.
1850 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1851 * error response and no peripheral access is initiated on the IPS bus.
1852 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1853 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1854 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1855 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1856 * on the IPS bus.
1857 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1858 */
1859#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
1860#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
1861#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
1862/*! OPAC17
1863 * 0bxxx0..Accesses from an untrusted master are allowed.
1864 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1865 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1866 * 0bxx0x..This peripheral allows write accesses.
1867 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1868 * error response and no peripheral access is initiated on the IPS bus.
1869 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1870 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1871 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1872 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1873 * on the IPS bus.
1874 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1875 */
1876#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
1877#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
1878#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
1879/*! OPAC16
1880 * 0bxxx0..Accesses from an untrusted master are allowed.
1881 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1882 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1883 * 0bxx0x..This peripheral allows write accesses.
1884 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1885 * error response and no peripheral access is initiated on the IPS bus.
1886 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1887 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1888 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1889 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1890 * on the IPS bus.
1891 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1892 */
1893#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
1894/*! @} */
1895
1896/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
1897/*! @{ */
1898#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
1899#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
1900/*! OPAC31
1901 * 0bxxx0..Accesses from an untrusted master are allowed.
1902 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1903 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1904 * 0bxx0x..This peripheral allows write accesses.
1905 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1906 * error response and no peripheral access is initiated on the IPS bus.
1907 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1908 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1909 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1910 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1911 * on the IPS bus.
1912 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1913 */
1914#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
1915#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
1916#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
1917/*! OPAC30
1918 * 0bxxx0..Accesses from an untrusted master are allowed.
1919 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1920 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1921 * 0bxx0x..This peripheral allows write accesses.
1922 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1923 * error response and no peripheral access is initiated on the IPS bus.
1924 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1925 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1926 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1927 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1928 * on the IPS bus.
1929 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1930 */
1931#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
1932#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
1933#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
1934/*! OPAC29
1935 * 0bxxx0..Accesses from an untrusted master are allowed.
1936 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1937 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1938 * 0bxx0x..This peripheral allows write accesses.
1939 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1940 * error response and no peripheral access is initiated on the IPS bus.
1941 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1942 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1943 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1944 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1945 * on the IPS bus.
1946 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1947 */
1948#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
1949#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
1950#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
1951/*! OPAC28
1952 * 0bxxx0..Accesses from an untrusted master are allowed.
1953 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1954 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1955 * 0bxx0x..This peripheral allows write accesses.
1956 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1957 * error response and no peripheral access is initiated on the IPS bus.
1958 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1959 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1960 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1961 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1962 * on the IPS bus.
1963 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1964 */
1965#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
1966#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
1967#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
1968/*! OPAC27
1969 * 0bxxx0..Accesses from an untrusted master are allowed.
1970 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1971 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1972 * 0bxx0x..This peripheral allows write accesses.
1973 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1974 * error response and no peripheral access is initiated on the IPS bus.
1975 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1976 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1977 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1978 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1979 * on the IPS bus.
1980 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1981 */
1982#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
1983#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
1984#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
1985/*! OPAC26
1986 * 0bxxx0..Accesses from an untrusted master are allowed.
1987 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1988 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1989 * 0bxx0x..This peripheral allows write accesses.
1990 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1991 * error response and no peripheral access is initiated on the IPS bus.
1992 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1993 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1994 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1995 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1996 * on the IPS bus.
1997 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1998 */
1999#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
2000#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
2001#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
2002/*! OPAC25
2003 * 0bxxx0..Accesses from an untrusted master are allowed.
2004 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2005 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2006 * 0bxx0x..This peripheral allows write accesses.
2007 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2008 * error response and no peripheral access is initiated on the IPS bus.
2009 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2010 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2011 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2012 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2013 * on the IPS bus.
2014 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2015 */
2016#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
2017#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
2018#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
2019/*! OPAC24
2020 * 0bxxx0..Accesses from an untrusted master are allowed.
2021 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2022 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2023 * 0bxx0x..This peripheral allows write accesses.
2024 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2025 * error response and no peripheral access is initiated on the IPS bus.
2026 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2027 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2028 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2029 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2030 * on the IPS bus.
2031 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2032 */
2033#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
2034/*! @} */
2035
2036/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
2037/*! @{ */
2038#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
2039#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
2040/*! OPAC33
2041 * 0bxxx0..Accesses from an untrusted master are allowed.
2042 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2043 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2044 * 0bxx0x..This peripheral allows write accesses.
2045 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2046 * error response and no peripheral access is initiated on the IPS bus.
2047 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2048 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2049 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2050 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2051 * on the IPS bus.
2052 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2053 */
2054#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
2055#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
2056#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
2057/*! OPAC32
2058 * 0bxxx0..Accesses from an untrusted master are allowed.
2059 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2060 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2061 * 0bxx0x..This peripheral allows write accesses.
2062 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2063 * error response and no peripheral access is initiated on the IPS bus.
2064 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2065 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2066 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2067 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2068 * on the IPS bus.
2069 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2070 */
2071#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
2072/*! @} */
2073
2074
2075/*!
2076 * @}
2077 */ /* end of group AIPSTZ_Register_Masks */
2078
2079
2080/* AIPSTZ - Peripheral instance base addresses */
2081/** Peripheral AIPSTZ1 base address */
2082#define AIPSTZ1_BASE (0x4007C000u)
2083/** Peripheral AIPSTZ1 base pointer */
2084#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
2085/** Peripheral AIPSTZ2 base address */
2086#define AIPSTZ2_BASE (0x4017C000u)
2087/** Peripheral AIPSTZ2 base pointer */
2088#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
2089/** Array initializer of AIPSTZ peripheral base addresses */
2090#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE }
2091/** Array initializer of AIPSTZ peripheral base pointers */
2092#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2 }
2093
2094/*!
2095 * @}
2096 */ /* end of group AIPSTZ_Peripheral_Access_Layer */
2097
2098
2099/* ----------------------------------------------------------------------------
2100 -- AOI Peripheral Access Layer
2101 ---------------------------------------------------------------------------- */
2102
2103/*!
2104 * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
2105 * @{
2106 */
2107
2108/** AOI - Register Layout Typedef */
2109typedef struct {
2110 struct { /* offset: 0x0, array step: 0x4 */
2111 __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
2112 __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
2113 } BFCRT[4];
2114} AOI_Type;
2115
2116/* ----------------------------------------------------------------------------
2117 -- AOI Register Masks
2118 ---------------------------------------------------------------------------- */
2119
2120/*!
2121 * @addtogroup AOI_Register_Masks AOI Register Masks
2122 * @{
2123 */
2124
2125/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
2126/*! @{ */
2127#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
2128#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
2129/*! PT1_DC - Product term 1, D input configuration
2130 * 0b00..Force the D input in this product term to a logical zero
2131 * 0b01..Pass the D input in this product term
2132 * 0b10..Complement the D input in this product term
2133 * 0b11..Force the D input in this product term to a logical one
2134 */
2135#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
2136#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
2137#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
2138/*! PT1_CC - Product term 1, C input configuration
2139 * 0b00..Force the C input in this product term to a logical zero
2140 * 0b01..Pass the C input in this product term
2141 * 0b10..Complement the C input in this product term
2142 * 0b11..Force the C input in this product term to a logical one
2143 */
2144#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
2145#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
2146#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
2147/*! PT1_BC - Product term 1, B input configuration
2148 * 0b00..Force the B input in this product term to a logical zero
2149 * 0b01..Pass the B input in this product term
2150 * 0b10..Complement the B input in this product term
2151 * 0b11..Force the B input in this product term to a logical one
2152 */
2153#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
2154#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
2155#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
2156/*! PT1_AC - Product term 1, A input configuration
2157 * 0b00..Force the A input in this product term to a logical zero
2158 * 0b01..Pass the A input in this product term
2159 * 0b10..Complement the A input in this product term
2160 * 0b11..Force the A input in this product term to a logical one
2161 */
2162#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
2163#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
2164#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
2165/*! PT0_DC - Product term 0, D input configuration
2166 * 0b00..Force the D input in this product term to a logical zero
2167 * 0b01..Pass the D input in this product term
2168 * 0b10..Complement the D input in this product term
2169 * 0b11..Force the D input in this product term to a logical one
2170 */
2171#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
2172#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
2173#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
2174/*! PT0_CC - Product term 0, C input configuration
2175 * 0b00..Force the C input in this product term to a logical zero
2176 * 0b01..Pass the C input in this product term
2177 * 0b10..Complement the C input in this product term
2178 * 0b11..Force the C input in this product term to a logical one
2179 */
2180#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
2181#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
2182#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
2183/*! PT0_BC - Product term 0, B input configuration
2184 * 0b00..Force the B input in this product term to a logical zero
2185 * 0b01..Pass the B input in this product term
2186 * 0b10..Complement the B input in this product term
2187 * 0b11..Force the B input in this product term to a logical one
2188 */
2189#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
2190#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
2191#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
2192/*! PT0_AC - Product term 0, A input configuration
2193 * 0b00..Force the A input in this product term to a logical zero
2194 * 0b01..Pass the A input in this product term
2195 * 0b10..Complement the A input in this product term
2196 * 0b11..Force the A input in this product term to a logical one
2197 */
2198#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
2199/*! @} */
2200
2201/* The count of AOI_BFCRT01 */
2202#define AOI_BFCRT01_COUNT (4U)
2203
2204/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
2205/*! @{ */
2206#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
2207#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
2208/*! PT3_DC - Product term 3, D input configuration
2209 * 0b00..Force the D input in this product term to a logical zero
2210 * 0b01..Pass the D input in this product term
2211 * 0b10..Complement the D input in this product term
2212 * 0b11..Force the D input in this product term to a logical one
2213 */
2214#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
2215#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
2216#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
2217/*! PT3_CC - Product term 3, C input configuration
2218 * 0b00..Force the C input in this product term to a logical zero
2219 * 0b01..Pass the C input in this product term
2220 * 0b10..Complement the C input in this product term
2221 * 0b11..Force the C input in this product term to a logical one
2222 */
2223#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
2224#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
2225#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
2226/*! PT3_BC - Product term 3, B input configuration
2227 * 0b00..Force the B input in this product term to a logical zero
2228 * 0b01..Pass the B input in this product term
2229 * 0b10..Complement the B input in this product term
2230 * 0b11..Force the B input in this product term to a logical one
2231 */
2232#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
2233#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
2234#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
2235/*! PT3_AC - Product term 3, A input configuration
2236 * 0b00..Force the A input in this product term to a logical zero
2237 * 0b01..Pass the A input in this product term
2238 * 0b10..Complement the A input in this product term
2239 * 0b11..Force the A input in this product term to a logical one
2240 */
2241#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
2242#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
2243#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
2244/*! PT2_DC - Product term 2, D input configuration
2245 * 0b00..Force the D input in this product term to a logical zero
2246 * 0b01..Pass the D input in this product term
2247 * 0b10..Complement the D input in this product term
2248 * 0b11..Force the D input in this product term to a logical one
2249 */
2250#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
2251#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
2252#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
2253/*! PT2_CC - Product term 2, C input configuration
2254 * 0b00..Force the C input in this product term to a logical zero
2255 * 0b01..Pass the C input in this product term
2256 * 0b10..Complement the C input in this product term
2257 * 0b11..Force the C input in this product term to a logical one
2258 */
2259#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
2260#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
2261#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
2262/*! PT2_BC - Product term 2, B input configuration
2263 * 0b00..Force the B input in this product term to a logical zero
2264 * 0b01..Pass the B input in this product term
2265 * 0b10..Complement the B input in this product term
2266 * 0b11..Force the B input in this product term to a logical one
2267 */
2268#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
2269#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
2270#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
2271/*! PT2_AC - Product term 2, A input configuration
2272 * 0b00..Force the A input in this product term to a logical zero
2273 * 0b01..Pass the A input in this product term
2274 * 0b10..Complement the A input in this product term
2275 * 0b11..Force the A input in this product term to a logical one
2276 */
2277#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
2278/*! @} */
2279
2280/* The count of AOI_BFCRT23 */
2281#define AOI_BFCRT23_COUNT (4U)
2282
2283
2284/*!
2285 * @}
2286 */ /* end of group AOI_Register_Masks */
2287
2288
2289/* AOI - Peripheral instance base addresses */
2290/** Peripheral AOI base address */
2291#define AOI_BASE (0x40094000u)
2292/** Peripheral AOI base pointer */
2293#define AOI ((AOI_Type *)AOI_BASE)
2294/** Array initializer of AOI peripheral base addresses */
2295#define AOI_BASE_ADDRS { AOI_BASE }
2296/** Array initializer of AOI peripheral base pointers */
2297#define AOI_BASE_PTRS { AOI }
2298
2299/*!
2300 * @}
2301 */ /* end of group AOI_Peripheral_Access_Layer */
2302
2303
2304/* ----------------------------------------------------------------------------
2305 -- CCM Peripheral Access Layer
2306 ---------------------------------------------------------------------------- */
2307
2308/*!
2309 * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
2310 * @{
2311 */
2312
2313/** CCM - Register Layout Typedef */
2314typedef struct {
2315 __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */
2316 uint8_t RESERVED_0[4];
2317 __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */
2318 __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */
2319 uint8_t RESERVED_1[4];
2320 __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */
2321 __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */
2322 __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */
2323 __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */
2324 __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */
2325 __IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */
2326 uint8_t RESERVED_2[4];
2327 __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */
2328 uint8_t RESERVED_3[4];
2329 __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */
2330 uint8_t RESERVED_4[12];
2331 __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */
2332 uint8_t RESERVED_5[8];
2333 __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */
2334 __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */
2335 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */
2336 __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */
2337 __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */
2338 __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */
2339 __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */
2340 __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */
2341 __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */
2342 __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */
2343 __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */
2344 __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */
2345 uint8_t RESERVED_6[4];
2346 __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */
2347} CCM_Type;
2348
2349/* ----------------------------------------------------------------------------
2350 -- CCM Register Masks
2351 ---------------------------------------------------------------------------- */
2352
2353/*!
2354 * @addtogroup CCM_Register_Masks CCM Register Masks
2355 * @{
2356 */
2357
2358/*! @name CCR - CCM Control Register */
2359/*! @{ */
2360#define CCM_CCR_OSCNT_MASK (0xFFU)
2361#define CCM_CCR_OSCNT_SHIFT (0U)
2362/*! OSCNT - Oscillator ready counter value. These bits define value of 32KHz counter, that serve as
2363 * counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time.
2364 * Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from
2365 * stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for
2366 * the dpll_ip to use and only then the gate in dpll_ip can be opened.
2367 */
2368#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
2369#define CCM_CCR_COSC_EN_MASK (0x1000U)
2370#define CCM_CCR_COSC_EN_SHIFT (12U)
2371/*! COSC_EN
2372 * 0b0..disable on chip oscillator
2373 * 0b1..enable on chip oscillator
2374 */
2375#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
2376#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
2377#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
2378/*! REG_BYPASS_COUNT
2379 * 0b000000..no delay
2380 * 0b000001..1 CKIL clock period delay
2381 * 0b111111..63 CKIL clock periods delay
2382 */
2383#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
2384#define CCM_CCR_RBC_EN_MASK (0x8000000U)
2385#define CCM_CCR_RBC_EN_SHIFT (27U)
2386/*! RBC_EN
2387 * 0b1..REG_BYPASS_COUNTER enabled.
2388 * 0b0..REG_BYPASS_COUNTER disabled
2389 */
2390#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
2391/*! @} */
2392
2393/*! @name CSR - CCM Status Register */
2394/*! @{ */
2395#define CCM_CSR_REF_EN_B_MASK (0x1U)
2396#define CCM_CSR_REF_EN_B_SHIFT (0U)
2397/*! REF_EN_B
2398 * 0b0..value of CCM_REF_EN_B is '0'
2399 * 0b1..value of CCM_REF_EN_B is '1'
2400 */
2401#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
2402#define CCM_CSR_CAMP2_READY_MASK (0x8U)
2403#define CCM_CSR_CAMP2_READY_SHIFT (3U)
2404/*! CAMP2_READY
2405 * 0b0..CAMP2 is not ready.
2406 * 0b1..CAMP2 is ready.
2407 */
2408#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
2409#define CCM_CSR_COSC_READY_MASK (0x20U)
2410#define CCM_CSR_COSC_READY_SHIFT (5U)
2411/*! COSC_READY
2412 * 0b0..on board oscillator is not ready.
2413 * 0b1..on board oscillator is ready.
2414 */
2415#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
2416/*! @} */
2417
2418/*! @name CCSR - CCM Clock Switcher Register */
2419/*! @{ */
2420#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
2421#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
2422/*! PLL3_SW_CLK_SEL
2423 * 0b0..pll3_main_clk
2424 * 0b1..pll3 bypass clock
2425 */
2426#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
2427/*! @} */
2428
2429/*! @name CBCDR - CCM Bus Clock Divider Register */
2430/*! @{ */
2431#define CCM_CBCDR_IPG_PODF_MASK (0x300U)
2432#define CCM_CBCDR_IPG_PODF_SHIFT (8U)
2433/*! IPG_PODF
2434 * 0b00..divide by 1
2435 * 0b01..divide by 2
2436 * 0b10..divide by 3
2437 * 0b11..divide by 4
2438 */
2439#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
2440#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
2441#define CCM_CBCDR_AHB_PODF_SHIFT (10U)
2442/*! AHB_PODF
2443 * 0b000..divide by 1
2444 * 0b001..divide by 2
2445 * 0b010..divide by 3
2446 * 0b011..divide by 4
2447 * 0b100..divide by 5
2448 * 0b101..divide by 6
2449 * 0b110..divide by 7
2450 * 0b111..divide by 8
2451 */
2452#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
2453#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
2454#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
2455/*! PERIPH_CLK_SEL
2456 * 0b0..derive clock selected by CCM_CBCMR[CORE_CLK_PRE_SEL]
2457 * 0b1..derive clock selected by CCM_CBCMR[PERIPH_CLK2_SEL]
2458 */
2459#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
2460/*! @} */
2461
2462/*! @name CBCMR - CCM Bus Clock Multiplexer Register */
2463/*! @{ */
2464#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
2465#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
2466/*! LPSPI_CLK_SEL
2467 * 0b00..derive clock from PLL3 PFD1 clk
2468 * 0b01..derive clock from PLL3 PFD0
2469 * 0b10..derive clock from PLL2
2470 * 0b11..derive clock from PLL2 PFD2
2471 */
2472#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
2473#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
2474#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
2475/*! PERIPH_CLK2_SEL
2476 * 0b00..derive clock from pll3_sw_clk
2477 * 0b01..derive clock from osc_clk
2478 * 0b10..derive clock from pll2_bypass_clk
2479 * 0b11..reserved
2480 */
2481#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
2482#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
2483#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
2484/*! TRACE_CLK_SEL
2485 * 0b00..derive clock from PLL2
2486 * 0b01..derive clock from PLL2 PFD2
2487 * 0b10..derive clock from PLL2 PFD0
2488 * 0b11..derive clock from PLL2 PFD1
2489 */
2490#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
2491#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
2492#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
2493/*! PRE_PERIPH_CLK_SEL
2494 * 0b00..derive clock from PLL2
2495 * 0b01..derive clock from PLL3 PFD3
2496 * 0b10..derive clock from PLL2 PFD3
2497 * 0b11..derive clock from PLL6
2498 */
2499#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
2500#define CCM_CBCMR_LPSPI_PODF_MASK (0x3C000000U)
2501#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
2502/*! LPSPI_PODF
2503 * 0b0000..divide by 1
2504 * 0b0001..divide by 2
2505 * 0b0010..divide by 3
2506 * 0b0011..divide by 4
2507 * 0b0100..divide by 5
2508 * 0b0101..divide by 6
2509 * 0b0110..divide by 7
2510 * 0b0111..divide by 8
2511 * 0b1000..divide by 9
2512 * 0b1001..divide by 10
2513 * 0b1010..divide by 11
2514 * 0b1011..divide by 12
2515 * 0b1100..divide by 13
2516 * 0b1101..divide by 14
2517 * 0b1110..divide by 15
2518 * 0b1111..divide by 16
2519 */
2520#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
2521/*! @} */
2522
2523/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */
2524/*! @{ */
2525#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
2526#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
2527/*! PERCLK_PODF - Divider for perclk podf.
2528 * 0b000000..Divide by 1
2529 * 0b000001..Divide by 2
2530 * 0b000010..Divide by 3
2531 * 0b000011..Divide by 4
2532 * 0b000100..Divide by 5
2533 * 0b000101..Divide by 6
2534 * 0b000110..Divide by 7
2535 * 0b000111..Divide by 8
2536 * 0b001000..Divide by 9
2537 * 0b001001..Divide by 10
2538 * 0b001010..Divide by 11
2539 * 0b001011..Divide by 12
2540 * 0b001100..Divide by 13
2541 * 0b001101..Divide by 14
2542 * 0b001110..Divide by 15
2543 * 0b001111..Divide by 16
2544 * 0b010000..Divide by 17
2545 * 0b010001..Divide by 18
2546 * 0b010010..Divide by 19
2547 * 0b010011..Divide by 20
2548 * 0b010100..Divide by 21
2549 * 0b010101..Divide by 22
2550 * 0b010110..Divide by 23
2551 * 0b010111..Divide by 24
2552 * 0b011000..Divide by 25
2553 * 0b011001..Divide by 26
2554 * 0b011010..Divide by 27
2555 * 0b011011..Divide by 28
2556 * 0b011100..Divide by 29
2557 * 0b011101..Divide by 30
2558 * 0b011110..Divide by 31
2559 * 0b011111..Divide by 32
2560 * 0b100000..Divide by 33
2561 * 0b100001..Divide by 34
2562 * 0b100010..Divide by 35
2563 * 0b100011..Divide by 36
2564 * 0b100100..Divide by 37
2565 * 0b100101..Divide by 38
2566 * 0b100110..Divide by 39
2567 * 0b100111..Divide by 40
2568 * 0b101000..Divide by 41
2569 * 0b101001..Divide by 42
2570 * 0b101010..Divide by 43
2571 * 0b101011..Divide by 44
2572 * 0b101100..Divide by 45
2573 * 0b101101..Divide by 46
2574 * 0b101110..Divide by 47
2575 * 0b101111..Divide by 48
2576 * 0b110000..Divide by 49
2577 * 0b110001..Divide by 50
2578 * 0b110010..Divide by 51
2579 * 0b110011..Divide by 52
2580 * 0b110100..Divide by 53
2581 * 0b110101..Divide by 54
2582 * 0b110110..Divide by 55
2583 * 0b110111..Divide by 56
2584 * 0b111000..Divide by 57
2585 * 0b111001..Divide by 58
2586 * 0b111010..Divide by 59
2587 * 0b111011..Divide by 60
2588 * 0b111100..Divide by 61
2589 * 0b111101..Divide by 62
2590 * 0b111110..Divide by 63
2591 * 0b111111..Divide by 64
2592 */
2593#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
2594#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
2595#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
2596/*! PERCLK_CLK_SEL
2597 * 0b0..derive clock from ipg clk root
2598 * 0b1..derive clock from osc_clk
2599 */
2600#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
2601#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
2602#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
2603/*! SAI1_CLK_SEL
2604 * 0b00..derive clock from PLL3 PFD2
2605 * 0b01..derive from pll3_sw_clk
2606 * 0b10..derive clock from PLL4
2607 * 0b11..Reserved
2608 */
2609#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
2610#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
2611#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
2612/*! SAI3_CLK_SEL
2613 * 0b00..derive clock from PLL3 PFD2
2614 * 0b01..derive from pll3_sw_clk
2615 * 0b10..derive clock from PLL4
2616 * 0b11..Reserved
2617 */
2618#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
2619#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
2620#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
2621/*! FLEXSPI_PODF
2622 * 0b000..divide by 1
2623 * 0b001..divide by 2
2624 * 0b010..divide by 3
2625 * 0b011..divide by 4
2626 * 0b100..divide by 5
2627 * 0b101..divide by 6
2628 * 0b110..divide by 7
2629 * 0b111..divide by 8
2630 */
2631#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
2632#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
2633#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
2634/*! FLEXSPI_CLK_SEL
2635 * 0b00..derive clock from PLL2
2636 * 0b01..derive clock from pll3_sw_clk
2637 * 0b10..derive clock from PLL2 PFD2
2638 * 0b11..derive clock from PLL3 PFD0
2639 */
2640#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
2641#define CCM_CSCMR1_FLEXSPI_CLK_SRC_MASK (0x80000000U)
2642#define CCM_CSCMR1_FLEXSPI_CLK_SRC_SHIFT (31U)
2643/*! FLEXSPI_CLK_SRC
2644 * 0b0..derive clock selected by CCM_CSCMR1[FLEXSPI_CLK_SEL]
2645 * 0b1..derive clock selected by CCM_CBCMR[PERIPH_CLK2_ SEL]
2646 */
2647#define CCM_CSCMR1_FLEXSPI_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SRC_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SRC_MASK)
2648/*! @} */
2649
2650/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */
2651/*! @{ */
2652#define CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK (0x180000U)
2653#define CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT (19U)
2654/*! FLEXIO1_CLK_SEL
2655 * 0b00..derive clock from PLL4 divided clock
2656 * 0b01..derive clock from PLL3 PFD2 clock
2657 * 0b10..derive from PLL2
2658 * 0b11..derive clock from pll3_sw_clk
2659 */
2660#define CCM_CSCMR2_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK)
2661#define CCM_CSCMR2_ADC_ACLK_PODF_MASK (0x78000000U)
2662#define CCM_CSCMR2_ADC_ACLK_PODF_SHIFT (27U)
2663/*! ADC_ACLK_PODF - Divider for ADC alt_clk, as the list below (other values reserved).
2664 * 0b0111..pll3_sw_clk / 8
2665 * 0b1011..pll3_sw_clk / 12
2666 * 0b1111..pll3_sw_clk / 16
2667 */
2668#define CCM_CSCMR2_ADC_ACLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_ADC_ACLK_PODF_SHIFT)) & CCM_CSCMR2_ADC_ACLK_PODF_MASK)
2669#define CCM_CSCMR2_ADC_ACLK_EN_MASK (0x80000000U)
2670#define CCM_CSCMR2_ADC_ACLK_EN_SHIFT (31U)
2671/*! ADC_ACLK_EN
2672 * 0b0..ADC alt_clk source is disabled
2673 * 0b1..ADC alt_clk source is enabled
2674 */
2675#define CCM_CSCMR2_ADC_ACLK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_ADC_ACLK_EN_SHIFT)) & CCM_CSCMR2_ADC_ACLK_EN_MASK)
2676/*! @} */
2677
2678/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */
2679/*! @{ */
2680#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
2681#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
2682/*! UART_CLK_PODF - Divider for uart clock podf.
2683 * 0b000000..Divide by 1
2684 * 0b000001..Divide by 2
2685 * 0b000010..Divide by 3
2686 * 0b000011..Divide by 4
2687 * 0b000100..Divide by 5
2688 * 0b000101..Divide by 6
2689 * 0b000110..Divide by 7
2690 * 0b000111..Divide by 8
2691 * 0b001000..Divide by 9
2692 * 0b001001..Divide by 10
2693 * 0b001010..Divide by 11
2694 * 0b001011..Divide by 12
2695 * 0b001100..Divide by 13
2696 * 0b001101..Divide by 14
2697 * 0b001110..Divide by 15
2698 * 0b001111..Divide by 16
2699 * 0b010000..Divide by 17
2700 * 0b010001..Divide by 18
2701 * 0b010010..Divide by 19
2702 * 0b010011..Divide by 20
2703 * 0b010100..Divide by 21
2704 * 0b010101..Divide by 22
2705 * 0b010110..Divide by 23
2706 * 0b010111..Divide by 24
2707 * 0b011000..Divide by 25
2708 * 0b011001..Divide by 26
2709 * 0b011010..Divide by 27
2710 * 0b011011..Divide by 28
2711 * 0b011100..Divide by 29
2712 * 0b011101..Divide by 30
2713 * 0b011110..Divide by 31
2714 * 0b011111..Divide by 32
2715 * 0b100000..Divide by 33
2716 * 0b100001..Divide by 34
2717 * 0b100010..Divide by 35
2718 * 0b100011..Divide by 36
2719 * 0b100100..Divide by 37
2720 * 0b100101..Divide by 38
2721 * 0b100110..Divide by 39
2722 * 0b100111..Divide by 40
2723 * 0b101000..Divide by 41
2724 * 0b101001..Divide by 42
2725 * 0b101010..Divide by 43
2726 * 0b101011..Divide by 44
2727 * 0b101100..Divide by 45
2728 * 0b101101..Divide by 46
2729 * 0b101110..Divide by 47
2730 * 0b101111..Divide by 48
2731 * 0b110000..Divide by 49
2732 * 0b110001..Divide by 50
2733 * 0b110010..Divide by 51
2734 * 0b110011..Divide by 52
2735 * 0b110100..Divide by 53
2736 * 0b110101..Divide by 54
2737 * 0b110110..Divide by 55
2738 * 0b110111..Divide by 56
2739 * 0b111000..Divide by 57
2740 * 0b111001..Divide by 58
2741 * 0b111010..Divide by 59
2742 * 0b111011..Divide by 60
2743 * 0b111100..Divide by 61
2744 * 0b111101..Divide by 62
2745 * 0b111110..Divide by 63
2746 * 0b111111..Divide by 64
2747 */
2748#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
2749#define CCM_CSCDR1_UART_CLK_SEL_MASK (0xC0U)
2750#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
2751/*! UART_CLK_SEL
2752 * 0b00..derive clock from pll3_80m
2753 * 0b01..derive clock from osc_clk
2754 * 0b10..derive clock from per_clk_root
2755 * 0b11..Reserved
2756 */
2757#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
2758#define CCM_CSCDR1_TRACE_PODF_MASK (0x1E000000U)
2759#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
2760/*! TRACE_PODF
2761 * 0b0000..divide by 1
2762 * 0b0001..divide by 2
2763 * 0b0010..divide by 3
2764 * 0b0011..divide by 4
2765 * 0b0100..divide by 5
2766 * 0b0101..divide by 6
2767 * 0b0110..divide by 7
2768 * 0b0111..divide by 8
2769 * 0b1000..divide by 9
2770 * 0b1001..divide by 10
2771 * 0b1010..divide by 11
2772 * 0b1011..divide by 12
2773 * 0b1100..divide by 13
2774 * 0b1101..divide by 14
2775 * 0b1110..divide by 15
2776 * 0b1111..divide by 16
2777 */
2778#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
2779/*! @} */
2780
2781/*! @name CS1CDR - CCM Clock Divider Register */
2782/*! @{ */
2783#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
2784#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
2785/*! SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower
2786 * than 300Mhz, the predivider can be used to achieve this.
2787 * 0b000000..Divide by 1
2788 * 0b000001..Divide by 2
2789 * 0b000010..Divide by 3
2790 * 0b000011..Divide by 4
2791 * 0b000100..Divide by 5
2792 * 0b000101..Divide by 6
2793 * 0b000110..Divide by 7
2794 * 0b000111..Divide by 8
2795 * 0b001000..Divide by 9
2796 * 0b001001..Divide by 10
2797 * 0b001010..Divide by 11
2798 * 0b001011..Divide by 12
2799 * 0b001100..Divide by 13
2800 * 0b001101..Divide by 14
2801 * 0b001110..Divide by 15
2802 * 0b001111..Divide by 16
2803 * 0b010000..Divide by 17
2804 * 0b010001..Divide by 18
2805 * 0b010010..Divide by 19
2806 * 0b010011..Divide by 20
2807 * 0b010100..Divide by 21
2808 * 0b010101..Divide by 22
2809 * 0b010110..Divide by 23
2810 * 0b010111..Divide by 24
2811 * 0b011000..Divide by 25
2812 * 0b011001..Divide by 26
2813 * 0b011010..Divide by 27
2814 * 0b011011..Divide by 28
2815 * 0b011100..Divide by 29
2816 * 0b011101..Divide by 30
2817 * 0b011110..Divide by 31
2818 * 0b011111..Divide by 32
2819 * 0b100000..Divide by 33
2820 * 0b100001..Divide by 34
2821 * 0b100010..Divide by 35
2822 * 0b100011..Divide by 36
2823 * 0b100100..Divide by 37
2824 * 0b100101..Divide by 38
2825 * 0b100110..Divide by 39
2826 * 0b100111..Divide by 40
2827 * 0b101000..Divide by 41
2828 * 0b101001..Divide by 42
2829 * 0b101010..Divide by 43
2830 * 0b101011..Divide by 44
2831 * 0b101100..Divide by 45
2832 * 0b101101..Divide by 46
2833 * 0b101110..Divide by 47
2834 * 0b101111..Divide by 48
2835 * 0b110000..Divide by 49
2836 * 0b110001..Divide by 50
2837 * 0b110010..Divide by 51
2838 * 0b110011..Divide by 52
2839 * 0b110100..Divide by 53
2840 * 0b110101..Divide by 54
2841 * 0b110110..Divide by 55
2842 * 0b110111..Divide by 56
2843 * 0b111000..Divide by 57
2844 * 0b111001..Divide by 58
2845 * 0b111010..Divide by 59
2846 * 0b111011..Divide by 60
2847 * 0b111100..Divide by 61
2848 * 0b111101..Divide by 62
2849 * 0b111110..Divide by 63
2850 * 0b111111..Divide by 64
2851 */
2852#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
2853#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
2854#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
2855/*! SAI1_CLK_PRED
2856 * 0b000..divide by 1
2857 * 0b001..divide by 2
2858 * 0b010..divide by 3
2859 * 0b011..divide by 4
2860 * 0b100..divide by 5
2861 * 0b101..divide by 6
2862 * 0b110..divide by 7
2863 * 0b111..divide by 8
2864 */
2865#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
2866#define CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK (0xE00U)
2867#define CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT (9U)
2868/*! FLEXIO1_CLK_PRED
2869 * 0b000..divide by 1
2870 * 0b001..divide by 2
2871 * 0b010..divide by 3
2872 * 0b011..divide by 4
2873 * 0b100..divide by 5
2874 * 0b101..divide by 6
2875 * 0b110..divide by 7
2876 * 0b111..divide by 8
2877 */
2878#define CCM_CS1CDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK)
2879#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
2880#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
2881/*! SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower
2882 * than 300Mhz, the predivider can be used to achieve this.
2883 * 0b000000..Divide by 1
2884 * 0b000001..Divide by 2
2885 * 0b000010..Divide by 3
2886 * 0b000011..Divide by 4
2887 * 0b000100..Divide by 5
2888 * 0b000101..Divide by 6
2889 * 0b000110..Divide by 7
2890 * 0b000111..Divide by 8
2891 * 0b001000..Divide by 9
2892 * 0b001001..Divide by 10
2893 * 0b001010..Divide by 11
2894 * 0b001011..Divide by 12
2895 * 0b001100..Divide by 13
2896 * 0b001101..Divide by 14
2897 * 0b001110..Divide by 15
2898 * 0b001111..Divide by 16
2899 * 0b010000..Divide by 17
2900 * 0b010001..Divide by 18
2901 * 0b010010..Divide by 19
2902 * 0b010011..Divide by 20
2903 * 0b010100..Divide by 21
2904 * 0b010101..Divide by 22
2905 * 0b010110..Divide by 23
2906 * 0b010111..Divide by 24
2907 * 0b011000..Divide by 25
2908 * 0b011001..Divide by 26
2909 * 0b011010..Divide by 27
2910 * 0b011011..Divide by 28
2911 * 0b011100..Divide by 29
2912 * 0b011101..Divide by 30
2913 * 0b011110..Divide by 31
2914 * 0b011111..Divide by 32
2915 * 0b100000..Divide by 33
2916 * 0b100001..Divide by 34
2917 * 0b100010..Divide by 35
2918 * 0b100011..Divide by 36
2919 * 0b100100..Divide by 37
2920 * 0b100101..Divide by 38
2921 * 0b100110..Divide by 39
2922 * 0b100111..Divide by 40
2923 * 0b101000..Divide by 41
2924 * 0b101001..Divide by 42
2925 * 0b101010..Divide by 43
2926 * 0b101011..Divide by 44
2927 * 0b101100..Divide by 45
2928 * 0b101101..Divide by 46
2929 * 0b101110..Divide by 47
2930 * 0b101111..Divide by 48
2931 * 0b110000..Divide by 49
2932 * 0b110001..Divide by 50
2933 * 0b110010..Divide by 51
2934 * 0b110011..Divide by 52
2935 * 0b110100..Divide by 53
2936 * 0b110101..Divide by 54
2937 * 0b110110..Divide by 55
2938 * 0b110111..Divide by 56
2939 * 0b111000..Divide by 57
2940 * 0b111001..Divide by 58
2941 * 0b111010..Divide by 59
2942 * 0b111011..Divide by 60
2943 * 0b111100..Divide by 61
2944 * 0b111101..Divide by 62
2945 * 0b111110..Divide by 63
2946 * 0b111111..Divide by 64
2947 */
2948#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
2949#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
2950#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
2951/*! SAI3_CLK_PRED
2952 * 0b000..divide by 1
2953 * 0b001..divide by 2
2954 * 0b010..divide by 3
2955 * 0b011..divide by 4
2956 * 0b100..divide by 5
2957 * 0b101..divide by 6
2958 * 0b110..divide by 7
2959 * 0b111..divide by 8
2960 */
2961#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
2962#define CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK (0x1E000000U)
2963#define CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT (25U)
2964/*! FLEXIO1_CLK_PODF - Divider for flexio1 clock. Divider should be updated when output clock is gated.
2965 * 0b0000..Divide by 1
2966 * 0b0001..Divide by 2
2967 * 0b0010..Divide by 3
2968 * 0b0011..Divide by 4
2969 * 0b0100..Divide by 5
2970 * 0b0101..Divide by 6
2971 * 0b0110..Divide by 7
2972 * 0b0111..Divide by 8
2973 * 0b1000..Divide by 9
2974 * 0b1001..Divide by 10
2975 * 0b1010..Divide by 11
2976 * 0b1011..Divide by 12
2977 * 0b1100..Divide by 13
2978 * 0b1101..Divide by 14
2979 * 0b1110..Divide by 15
2980 * 0b1111..Divide by 16
2981 */
2982#define CCM_CS1CDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK)
2983/*! @} */
2984
2985/*! @name CDCDR - CCM D1 Clock Divider Register */
2986/*! @{ */
2987#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
2988#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
2989/*! SPDIF0_CLK_SEL
2990 * 0b00..derive clock from PLL4
2991 * 0b01..derive clock from PLL3 PFD2
2992 * 0b10..Reserved
2993 * 0b11..derive clock from pll3_sw_clk
2994 */
2995#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
2996#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
2997#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
2998/*! SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
2999 * 0b000..Divide by 1
3000 * 0b001..Divide by 2
3001 * 0b010..Divide by 3
3002 * 0b011..Divide by 4
3003 * 0b100..Divide by 5
3004 * 0b101..Divide by 6
3005 * 0b110..Divide by 7
3006 * 0b111..Divide by 8
3007 */
3008#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
3009#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
3010#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
3011/*! SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated.
3012 * 0b000..Divide by 1
3013 * 0b001..Divide by 2
3014 * 0b010..Divide by 3
3015 * 0b011..Divide by 4
3016 * 0b100..Divide by 5
3017 * 0b101..Divide by 6
3018 * 0b110..Divide by 7
3019 * 0b111..Divide by 8
3020 */
3021#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
3022/*! @} */
3023
3024/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */
3025/*! @{ */
3026#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
3027#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
3028/*! LPI2C_CLK_SEL
3029 * 0b0..derive clock from pll3_60m
3030 * 0b1..derive clock from osc_clk
3031 */
3032#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
3033#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
3034#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
3035/*! LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is
3036 * gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used
3037 * to achieve this.
3038 * 0b000000..Divide by 1
3039 * 0b000001..Divide by 2
3040 * 0b000010..Divide by 3
3041 * 0b000011..Divide by 4
3042 * 0b000100..Divide by 5
3043 * 0b000101..Divide by 6
3044 * 0b000110..Divide by 7
3045 * 0b000111..Divide by 8
3046 * 0b001000..Divide by 9
3047 * 0b001001..Divide by 10
3048 * 0b001010..Divide by 11
3049 * 0b001011..Divide by 12
3050 * 0b001100..Divide by 13
3051 * 0b001101..Divide by 14
3052 * 0b001110..Divide by 15
3053 * 0b001111..Divide by 16
3054 * 0b010000..Divide by 17
3055 * 0b010001..Divide by 18
3056 * 0b010010..Divide by 19
3057 * 0b010011..Divide by 20
3058 * 0b010100..Divide by 21
3059 * 0b010101..Divide by 22
3060 * 0b010110..Divide by 23
3061 * 0b010111..Divide by 24
3062 * 0b011000..Divide by 25
3063 * 0b011001..Divide by 26
3064 * 0b011010..Divide by 27
3065 * 0b011011..Divide by 28
3066 * 0b011100..Divide by 29
3067 * 0b011101..Divide by 30
3068 * 0b011110..Divide by 31
3069 * 0b011111..Divide by 32
3070 * 0b100000..Divide by 33
3071 * 0b100001..Divide by 34
3072 * 0b100010..Divide by 35
3073 * 0b100011..Divide by 36
3074 * 0b100100..Divide by 37
3075 * 0b100101..Divide by 38
3076 * 0b100110..Divide by 39
3077 * 0b100111..Divide by 40
3078 * 0b101000..Divide by 41
3079 * 0b101001..Divide by 42
3080 * 0b101010..Divide by 43
3081 * 0b101011..Divide by 44
3082 * 0b101100..Divide by 45
3083 * 0b101101..Divide by 46
3084 * 0b101110..Divide by 47
3085 * 0b101111..Divide by 48
3086 * 0b110000..Divide by 49
3087 * 0b110001..Divide by 50
3088 * 0b110010..Divide by 51
3089 * 0b110011..Divide by 52
3090 * 0b110100..Divide by 53
3091 * 0b110101..Divide by 54
3092 * 0b110110..Divide by 55
3093 * 0b110111..Divide by 56
3094 * 0b111000..Divide by 57
3095 * 0b111001..Divide by 58
3096 * 0b111010..Divide by 59
3097 * 0b111011..Divide by 60
3098 * 0b111100..Divide by 61
3099 * 0b111101..Divide by 62
3100 * 0b111110..Divide by 63
3101 * 0b111111..Divide by 64
3102 */
3103#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
3104/*! @} */
3105
3106/*! @name CDHIPR - CCM Divider Handshake In-Process Register */
3107/*! @{ */
3108#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
3109#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
3110/*! AHB_PODF_BUSY
3111 * 0b0..divider is not busy and its value represents the actual division.
3112 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
3113 * value of the division factor, and after the handshake the written value of the ahb_podf will be applied.
3114 */
3115#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
3116#define CCM_CDHIPR_FLEXSPI_PODF_BUSY_MASK (0x8U)
3117#define CCM_CDHIPR_FLEXSPI_PODF_BUSY_SHIFT (3U)
3118/*! FLEXSPI_PODF_BUSY
3119 * 0b0..divider is not busy and its value represents the actual division.
3120 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
3121 * value of the division factor, and after the handshake the written value of the flexspi_podf will be
3122 * applied.
3123 */
3124#define CCM_CDHIPR_FLEXSPI_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_FLEXSPI_PODF_BUSY_SHIFT)) & CCM_CDHIPR_FLEXSPI_PODF_BUSY_MASK)
3125#define CCM_CDHIPR_PERCLK_PODF_BUSY_MASK (0x10U)
3126#define CCM_CDHIPR_PERCLK_PODF_BUSY_SHIFT (4U)
3127/*! PERCLK_PODF_BUSY
3128 * 0b0..divider is not busy and its value represents the actual division.
3129 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
3130 * value of the division factor, and after the handshake the written value of the perclk_podf will be
3131 * applied.
3132 */
3133#define CCM_CDHIPR_PERCLK_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERCLK_PODF_BUSY_SHIFT)) & CCM_CDHIPR_PERCLK_PODF_BUSY_MASK)
3134#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
3135#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
3136/*! PERIPH_CLK_SEL_BUSY
3137 * 0b0..mux is not busy and its value represents the actual division.
3138 * 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the
3139 * previous value of select, and after the handshake periph_clk_sel value will be applied.
3140 */
3141#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
3142/*! @} */
3143
3144/*! @name CLPCR - CCM Low Power Control Register */
3145/*! @{ */
3146#define CCM_CLPCR_LPM_MASK (0x3U)
3147#define CCM_CLPCR_LPM_SHIFT (0U)
3148/*! LPM
3149 * 0b00..Remain in run mode
3150 * 0b01..Transfer to wait mode
3151 * 0b10..Transfer to stop mode
3152 * 0b11..Reserved
3153 */
3154#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
3155#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
3156#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
3157/*! ARM_CLK_DIS_ON_LPM
3158 * 0b0..ARM clock enabled on wait mode.
3159 * 0b1..ARM clock disabled on wait mode. .
3160 */
3161#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
3162#define CCM_CLPCR_SBYOS_MASK (0x40U)
3163#define CCM_CLPCR_SBYOS_SHIFT (6U)
3164/*! SBYOS
3165 * 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain
3166 * asserted - '0' and cosc_pwrdown will remain de asserted - '0')
3167 * 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be
3168 * deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will
3169 * be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will
3170 * continue with the exit from the STOP mode process.
3171 */
3172#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
3173#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
3174#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
3175/*! DIS_REF_OSC
3176 * 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.
3177 * 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'
3178 */
3179#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
3180#define CCM_CLPCR_VSTBY_MASK (0x100U)
3181#define CCM_CLPCR_VSTBY_SHIFT (8U)
3182/*! VSTBY
3183 * 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')
3184 * 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').
3185 */
3186#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
3187#define CCM_CLPCR_STBY_COUNT_MASK (0x600U)
3188#define CCM_CLPCR_STBY_COUNT_SHIFT (9U)
3189/*! STBY_COUNT
3190 * 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles
3191 * 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles
3192 * 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles
3193 * 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles
3194 */
3195#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
3196#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
3197#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
3198/*! COSC_PWRDOWN
3199 * 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.
3200 * 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.
3201 */
3202#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
3203#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
3204#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
3205/*! MASK_CORE0_WFI
3206 * 0b0..WFI of core0 is not masked
3207 * 0b1..WFI of core0 is masked
3208 */
3209#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
3210#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
3211#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
3212/*! MASK_SCU_IDLE
3213 * 0b1..SCU IDLE is masked
3214 * 0b0..SCU IDLE is not masked
3215 */
3216#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
3217#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
3218#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
3219/*! MASK_L2CC_IDLE
3220 * 0b1..L2CC IDLE is masked
3221 * 0b0..L2CC IDLE is not masked
3222 */
3223#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
3224/*! @} */
3225
3226/*! @name CISR - CCM Interrupt Status Register */
3227/*! @{ */
3228#define CCM_CISR_LRF_PLL_MASK (0x1U)
3229#define CCM_CISR_LRF_PLL_SHIFT (0U)
3230/*! LRF_PLL
3231 * 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs
3232 * 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs
3233 */
3234#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
3235#define CCM_CISR_COSC_READY_MASK (0x40U)
3236#define CCM_CISR_COSC_READY_SHIFT (6U)
3237/*! COSC_READY
3238 * 0b0..interrupt is not generated due to on board oscillator ready
3239 * 0b1..interrupt generated due to on board oscillator ready
3240 */
3241#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
3242#define CCM_CISR_FLEXSPI_PODF_LOADED_MASK (0x10000U)
3243#define CCM_CISR_FLEXSPI_PODF_LOADED_SHIFT (16U)
3244/*! FLEXSPI_PODF_LOADED
3245 * 0b0..interrupt is not generated due to frequency change of flexspi_podf
3246 * 0b1..interrupt generated due to frequency change of flexspi_podf
3247 */
3248#define CCM_CISR_FLEXSPI_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_FLEXSPI_PODF_LOADED_SHIFT)) & CCM_CISR_FLEXSPI_PODF_LOADED_MASK)
3249#define CCM_CISR_PERCLK_PODF_LOADED_MASK (0x40000U)
3250#define CCM_CISR_PERCLK_PODF_LOADED_SHIFT (18U)
3251/*! PERCLK_PODF_LOADED
3252 * 0b0..interrupt is not generated due to frequency change of perclk_podf
3253 * 0b1..interrupt generated due to frequency change of perclk_podf
3254 */
3255#define CCM_CISR_PERCLK_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERCLK_PODF_LOADED_SHIFT)) & CCM_CISR_PERCLK_PODF_LOADED_MASK)
3256#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
3257#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
3258/*! AHB_PODF_LOADED
3259 * 0b0..interrupt is not generated due to frequency change of ahb_podf
3260 * 0b1..interrupt generated due to frequency change of ahb_podf
3261 */
3262#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
3263#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
3264#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
3265/*! PERIPH_CLK_SEL_LOADED
3266 * 0b0..interrupt is not generated due to update of periph_clk_sel.
3267 * 0b1..interrupt generated due to update of periph_clk_sel.
3268 */
3269#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
3270/*! @} */
3271
3272/*! @name CIMR - CCM Interrupt Mask Register */
3273/*! @{ */
3274#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
3275#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
3276/*! MASK_LRF_PLL
3277 * 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created
3278 * 0b1..mask interrupt due to lrf of PLLs
3279 */
3280#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
3281#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
3282#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
3283/*! MASK_COSC_READY
3284 * 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created
3285 * 0b1..mask interrupt due to on board oscillator ready
3286 */
3287#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
3288#define CCM_CIMR_MASK_FLEXSPI_PODF_LOADED_MASK (0x10000U)
3289#define CCM_CIMR_MASK_FLEXSPI_PODF_LOADED_SHIFT (16U)
3290/*! MASK_FLEXSPI_PODF_LOADED
3291 * 0b0..don't mask interrupt due to update of flexspi_podf
3292 * 0b1..mask interrupt due to update of flexspi_podf
3293 */
3294#define CCM_CIMR_MASK_FLEXSPI_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_FLEXSPI_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_FLEXSPI_PODF_LOADED_MASK)
3295#define CCM_CIMR_MASK_PERCLK_PODF_LOADED_MASK (0x40000U)
3296#define CCM_CIMR_MASK_PERCLK_PODF_LOADED_SHIFT (18U)
3297/*! MASK_PERCLK_PODF_LOADED
3298 * 0b0..don't mask interrupt due to update of perclk_podf
3299 * 0b1..mask interrupt due to update of perclk_podf
3300 */
3301#define CCM_CIMR_MASK_PERCLK_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERCLK_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_PERCLK_PODF_LOADED_MASK)
3302#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
3303#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
3304/*! MASK_AHB_PODF_LOADED
3305 * 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created
3306 * 0b1..mask interrupt due to frequency change of ahb_podf
3307 */
3308#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
3309#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
3310#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
3311/*! MASK_PERIPH_CLK_SEL_LOADED
3312 * 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created
3313 * 0b1..mask interrupt due to update of periph_clk_sel
3314 */
3315#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
3316/*! @} */
3317
3318/*! @name CCOSR - CCM Clock Output Source Register */
3319/*! @{ */
3320#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
3321#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
3322/*! CLKO1_SEL
3323 * 0b0000..pll3_sw_clk (divided by 2)
3324 * 0b0001..PLL2 (divided by 2)
3325 * 0b0010..ENET PLL (divided by 2)
3326 * 0b0011..Reserved
3327 * 0b0101..Reserved
3328 * 0b0110..Reserved
3329 * 0b1010..Reserved
3330 * 0b1011..core_clk_root
3331 * 0b1100..ipg_clk_root
3332 * 0b1101..perclk_root
3333 * 0b1110..Reserved
3334 * 0b1111..pll4_main_clk
3335 */
3336#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
3337#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
3338#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
3339/*! CLKO1_DIV
3340 * 0b000..divide by 1
3341 * 0b001..divide by 2
3342 * 0b010..divide by 3
3343 * 0b011..divide by 4
3344 * 0b100..divide by 5
3345 * 0b101..divide by 6
3346 * 0b110..divide by 7
3347 * 0b111..divide by 8
3348 */
3349#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
3350#define CCM_CCOSR_CLKO1_EN_MASK (0x80U)
3351#define CCM_CCOSR_CLKO1_EN_SHIFT (7U)
3352/*! CLKO1_EN
3353 * 0b0..CCM_CLKO1 disabled.
3354 * 0b1..CCM_CLKO1 enabled.
3355 */
3356#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
3357#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
3358#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
3359/*! CLK_OUT_SEL
3360 * 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock
3361 * 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock
3362 */
3363#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
3364#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
3365#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
3366/*! CLKO2_SEL
3367 * 0b00101..Reserved
3368 * 0b00110..lpi2c_clk_root
3369 * 0b01110..osc_clk
3370 * 0b10000..lpspi_clk_root
3371 * 0b10010..sai1_clk_root
3372 * 0b10100..sai3_clk_root
3373 * 0b10110..trace_clk_root
3374 * 0b11011..flexspi_clk_root
3375 * 0b11100..uart_clk_root
3376 * 0b11101..spdif0_clk_root
3377 * 0b11111..Reserved
3378 */
3379#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
3380#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
3381#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
3382/*! CLKO2_DIV
3383 * 0b000..divide by 1
3384 * 0b001..divide by 2
3385 * 0b010..divide by 3
3386 * 0b011..divide by 4
3387 * 0b100..divide by 5
3388 * 0b101..divide by 6
3389 * 0b110..divide by 7
3390 * 0b111..divide by 8
3391 */
3392#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
3393#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
3394#define CCM_CCOSR_CLKO2_EN_SHIFT (24U)
3395/*! CLKO2_EN
3396 * 0b0..CCM_CLKO2 disabled.
3397 * 0b1..CCM_CLKO2 enabled.
3398 */
3399#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
3400/*! @} */
3401
3402/*! @name CGPR - CCM General Purpose Register */
3403/*! @{ */
3404#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
3405#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
3406/*! PMIC_DELAY_SCALER
3407 * 0b0..clock is not divided
3408 * 0b1..clock is divided /8
3409 */
3410#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
3411#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
3412#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
3413/*! EFUSE_PROG_SUPPLY_GATE
3414 * 0b0..fuse programing supply voltage is gated off to the efuse module
3415 * 0b1..allow fuse programing.
3416 */
3417#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
3418#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
3419#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
3420/*! SYS_MEM_DS_CTRL
3421 * 0b00..Disable memory DS mode always
3422 * 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled
3423 * 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode
3424 */
3425#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
3426#define CCM_CGPR_FPL_MASK (0x10000U)
3427#define CCM_CGPR_FPL_SHIFT (16U)
3428/*! FPL - Fast PLL enable.
3429 * 0b0..Engage PLL enable default way.
3430 * 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.
3431 */
3432#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
3433#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
3434#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
3435/*! INT_MEM_CLK_LPM
3436 * 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode
3437 * 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low
3438 * Power Modes (WAIT and STOP without power gating)
3439 */
3440#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
3441/*! @} */
3442
3443/*! @name CCGR0 - CCM Clock Gating Register 0 */
3444/*! @{ */
3445#define CCM_CCGR0_CG0_MASK (0x3U)
3446#define CCM_CCGR0_CG0_SHIFT (0U)
3447#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
3448#define CCM_CCGR0_CG1_MASK (0xCU)
3449#define CCM_CCGR0_CG1_SHIFT (2U)
3450#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
3451#define CCM_CCGR0_CG2_MASK (0x30U)
3452#define CCM_CCGR0_CG2_SHIFT (4U)
3453#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
3454#define CCM_CCGR0_CG3_MASK (0xC0U)
3455#define CCM_CCGR0_CG3_SHIFT (6U)
3456#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
3457#define CCM_CCGR0_CG4_MASK (0x300U)
3458#define CCM_CCGR0_CG4_SHIFT (8U)
3459#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
3460#define CCM_CCGR0_CG5_MASK (0xC00U)
3461#define CCM_CCGR0_CG5_SHIFT (10U)
3462#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
3463#define CCM_CCGR0_CG6_MASK (0x3000U)
3464#define CCM_CCGR0_CG6_SHIFT (12U)
3465#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
3466#define CCM_CCGR0_CG7_MASK (0xC000U)
3467#define CCM_CCGR0_CG7_SHIFT (14U)
3468#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
3469#define CCM_CCGR0_CG8_MASK (0x30000U)
3470#define CCM_CCGR0_CG8_SHIFT (16U)
3471#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
3472#define CCM_CCGR0_CG9_MASK (0xC0000U)
3473#define CCM_CCGR0_CG9_SHIFT (18U)
3474#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
3475#define CCM_CCGR0_CG10_MASK (0x300000U)
3476#define CCM_CCGR0_CG10_SHIFT (20U)
3477#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
3478#define CCM_CCGR0_CG11_MASK (0xC00000U)
3479#define CCM_CCGR0_CG11_SHIFT (22U)
3480#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
3481#define CCM_CCGR0_CG12_MASK (0x3000000U)
3482#define CCM_CCGR0_CG12_SHIFT (24U)
3483#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
3484#define CCM_CCGR0_CG13_MASK (0xC000000U)
3485#define CCM_CCGR0_CG13_SHIFT (26U)
3486#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
3487#define CCM_CCGR0_CG14_MASK (0x30000000U)
3488#define CCM_CCGR0_CG14_SHIFT (28U)
3489#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
3490#define CCM_CCGR0_CG15_MASK (0xC0000000U)
3491#define CCM_CCGR0_CG15_SHIFT (30U)
3492#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
3493/*! @} */
3494
3495/*! @name CCGR1 - CCM Clock Gating Register 1 */
3496/*! @{ */
3497#define CCM_CCGR1_CG0_MASK (0x3U)
3498#define CCM_CCGR1_CG0_SHIFT (0U)
3499#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
3500#define CCM_CCGR1_CG1_MASK (0xCU)
3501#define CCM_CCGR1_CG1_SHIFT (2U)
3502#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
3503#define CCM_CCGR1_CG2_MASK (0x30U)
3504#define CCM_CCGR1_CG2_SHIFT (4U)
3505#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
3506#define CCM_CCGR1_CG3_MASK (0xC0U)
3507#define CCM_CCGR1_CG3_SHIFT (6U)
3508#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
3509#define CCM_CCGR1_CG4_MASK (0x300U)
3510#define CCM_CCGR1_CG4_SHIFT (8U)
3511#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
3512#define CCM_CCGR1_CG5_MASK (0xC00U)
3513#define CCM_CCGR1_CG5_SHIFT (10U)
3514#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
3515#define CCM_CCGR1_CG6_MASK (0x3000U)
3516#define CCM_CCGR1_CG6_SHIFT (12U)
3517#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
3518#define CCM_CCGR1_CG7_MASK (0xC000U)
3519#define CCM_CCGR1_CG7_SHIFT (14U)
3520#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
3521#define CCM_CCGR1_CG8_MASK (0x30000U)
3522#define CCM_CCGR1_CG8_SHIFT (16U)
3523#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
3524#define CCM_CCGR1_CG9_MASK (0xC0000U)
3525#define CCM_CCGR1_CG9_SHIFT (18U)
3526#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
3527#define CCM_CCGR1_CG10_MASK (0x300000U)
3528#define CCM_CCGR1_CG10_SHIFT (20U)
3529#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
3530#define CCM_CCGR1_CG11_MASK (0xC00000U)
3531#define CCM_CCGR1_CG11_SHIFT (22U)
3532#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
3533#define CCM_CCGR1_CG12_MASK (0x3000000U)
3534#define CCM_CCGR1_CG12_SHIFT (24U)
3535#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
3536#define CCM_CCGR1_CG13_MASK (0xC000000U)
3537#define CCM_CCGR1_CG13_SHIFT (26U)
3538#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
3539#define CCM_CCGR1_CG14_MASK (0x30000000U)
3540#define CCM_CCGR1_CG14_SHIFT (28U)
3541#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
3542#define CCM_CCGR1_CG15_MASK (0xC0000000U)
3543#define CCM_CCGR1_CG15_SHIFT (30U)
3544#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
3545/*! @} */
3546
3547/*! @name CCGR2 - CCM Clock Gating Register 2 */
3548/*! @{ */
3549#define CCM_CCGR2_CG0_MASK (0x3U)
3550#define CCM_CCGR2_CG0_SHIFT (0U)
3551#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
3552#define CCM_CCGR2_CG1_MASK (0xCU)
3553#define CCM_CCGR2_CG1_SHIFT (2U)
3554#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
3555#define CCM_CCGR2_CG2_MASK (0x30U)
3556#define CCM_CCGR2_CG2_SHIFT (4U)
3557#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
3558#define CCM_CCGR2_CG3_MASK (0xC0U)
3559#define CCM_CCGR2_CG3_SHIFT (6U)
3560#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
3561#define CCM_CCGR2_CG4_MASK (0x300U)
3562#define CCM_CCGR2_CG4_SHIFT (8U)
3563#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
3564#define CCM_CCGR2_CG5_MASK (0xC00U)
3565#define CCM_CCGR2_CG5_SHIFT (10U)
3566#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
3567#define CCM_CCGR2_CG6_MASK (0x3000U)
3568#define CCM_CCGR2_CG6_SHIFT (12U)
3569#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
3570#define CCM_CCGR2_CG7_MASK (0xC000U)
3571#define CCM_CCGR2_CG7_SHIFT (14U)
3572#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
3573#define CCM_CCGR2_CG8_MASK (0x30000U)
3574#define CCM_CCGR2_CG8_SHIFT (16U)
3575#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
3576#define CCM_CCGR2_CG9_MASK (0xC0000U)
3577#define CCM_CCGR2_CG9_SHIFT (18U)
3578#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
3579#define CCM_CCGR2_CG10_MASK (0x300000U)
3580#define CCM_CCGR2_CG10_SHIFT (20U)
3581#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
3582#define CCM_CCGR2_CG11_MASK (0xC00000U)
3583#define CCM_CCGR2_CG11_SHIFT (22U)
3584#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
3585#define CCM_CCGR2_CG12_MASK (0x3000000U)
3586#define CCM_CCGR2_CG12_SHIFT (24U)
3587#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
3588#define CCM_CCGR2_CG13_MASK (0xC000000U)
3589#define CCM_CCGR2_CG13_SHIFT (26U)
3590#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
3591#define CCM_CCGR2_CG14_MASK (0x30000000U)
3592#define CCM_CCGR2_CG14_SHIFT (28U)
3593#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
3594#define CCM_CCGR2_CG15_MASK (0xC0000000U)
3595#define CCM_CCGR2_CG15_SHIFT (30U)
3596#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
3597/*! @} */
3598
3599/*! @name CCGR3 - CCM Clock Gating Register 3 */
3600/*! @{ */
3601#define CCM_CCGR3_CG0_MASK (0x3U)
3602#define CCM_CCGR3_CG0_SHIFT (0U)
3603#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
3604#define CCM_CCGR3_CG1_MASK (0xCU)
3605#define CCM_CCGR3_CG1_SHIFT (2U)
3606#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
3607#define CCM_CCGR3_CG2_MASK (0x30U)
3608#define CCM_CCGR3_CG2_SHIFT (4U)
3609#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
3610#define CCM_CCGR3_CG3_MASK (0xC0U)
3611#define CCM_CCGR3_CG3_SHIFT (6U)
3612#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
3613#define CCM_CCGR3_CG4_MASK (0x300U)
3614#define CCM_CCGR3_CG4_SHIFT (8U)
3615#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
3616#define CCM_CCGR3_CG5_MASK (0xC00U)
3617#define CCM_CCGR3_CG5_SHIFT (10U)
3618#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
3619#define CCM_CCGR3_CG6_MASK (0x3000U)
3620#define CCM_CCGR3_CG6_SHIFT (12U)
3621#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
3622#define CCM_CCGR3_CG7_MASK (0xC000U)
3623#define CCM_CCGR3_CG7_SHIFT (14U)
3624#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
3625#define CCM_CCGR3_CG8_MASK (0x30000U)
3626#define CCM_CCGR3_CG8_SHIFT (16U)
3627#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
3628#define CCM_CCGR3_CG9_MASK (0xC0000U)
3629#define CCM_CCGR3_CG9_SHIFT (18U)
3630#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
3631#define CCM_CCGR3_CG10_MASK (0x300000U)
3632#define CCM_CCGR3_CG10_SHIFT (20U)
3633#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
3634#define CCM_CCGR3_CG11_MASK (0xC00000U)
3635#define CCM_CCGR3_CG11_SHIFT (22U)
3636#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
3637#define CCM_CCGR3_CG12_MASK (0x3000000U)
3638#define CCM_CCGR3_CG12_SHIFT (24U)
3639#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
3640#define CCM_CCGR3_CG13_MASK (0xC000000U)
3641#define CCM_CCGR3_CG13_SHIFT (26U)
3642#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
3643#define CCM_CCGR3_CG14_MASK (0x30000000U)
3644#define CCM_CCGR3_CG14_SHIFT (28U)
3645/*! CG14 - The OCRAM clock cannot be turned off when the CM cache is running on this device.
3646 */
3647#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
3648#define CCM_CCGR3_CG15_MASK (0xC0000000U)
3649#define CCM_CCGR3_CG15_SHIFT (30U)
3650#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
3651/*! @} */
3652
3653/*! @name CCGR4 - CCM Clock Gating Register 4 */
3654/*! @{ */
3655#define CCM_CCGR4_CG0_MASK (0x3U)
3656#define CCM_CCGR4_CG0_SHIFT (0U)
3657#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
3658#define CCM_CCGR4_CG1_MASK (0xCU)
3659#define CCM_CCGR4_CG1_SHIFT (2U)
3660#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
3661#define CCM_CCGR4_CG2_MASK (0x30U)
3662#define CCM_CCGR4_CG2_SHIFT (4U)
3663#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
3664#define CCM_CCGR4_CG3_MASK (0xC0U)
3665#define CCM_CCGR4_CG3_SHIFT (6U)
3666#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
3667#define CCM_CCGR4_CG4_MASK (0x300U)
3668#define CCM_CCGR4_CG4_SHIFT (8U)
3669#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
3670#define CCM_CCGR4_CG5_MASK (0xC00U)
3671#define CCM_CCGR4_CG5_SHIFT (10U)
3672#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
3673#define CCM_CCGR4_CG6_MASK (0x3000U)
3674#define CCM_CCGR4_CG6_SHIFT (12U)
3675#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
3676#define CCM_CCGR4_CG7_MASK (0xC000U)
3677#define CCM_CCGR4_CG7_SHIFT (14U)
3678#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
3679#define CCM_CCGR4_CG8_MASK (0x30000U)
3680#define CCM_CCGR4_CG8_SHIFT (16U)
3681#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
3682#define CCM_CCGR4_CG9_MASK (0xC0000U)
3683#define CCM_CCGR4_CG9_SHIFT (18U)
3684#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
3685#define CCM_CCGR4_CG10_MASK (0x300000U)
3686#define CCM_CCGR4_CG10_SHIFT (20U)
3687#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
3688#define CCM_CCGR4_CG11_MASK (0xC00000U)
3689#define CCM_CCGR4_CG11_SHIFT (22U)
3690#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
3691#define CCM_CCGR4_CG12_MASK (0x3000000U)
3692#define CCM_CCGR4_CG12_SHIFT (24U)
3693#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
3694#define CCM_CCGR4_CG13_MASK (0xC000000U)
3695#define CCM_CCGR4_CG13_SHIFT (26U)
3696#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
3697#define CCM_CCGR4_CG14_MASK (0x30000000U)
3698#define CCM_CCGR4_CG14_SHIFT (28U)
3699#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
3700#define CCM_CCGR4_CG15_MASK (0xC0000000U)
3701#define CCM_CCGR4_CG15_SHIFT (30U)
3702#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
3703/*! @} */
3704
3705/*! @name CCGR5 - CCM Clock Gating Register 5 */
3706/*! @{ */
3707#define CCM_CCGR5_CG0_MASK (0x3U)
3708#define CCM_CCGR5_CG0_SHIFT (0U)
3709#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
3710#define CCM_CCGR5_CG1_MASK (0xCU)
3711#define CCM_CCGR5_CG1_SHIFT (2U)
3712#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
3713#define CCM_CCGR5_CG2_MASK (0x30U)
3714#define CCM_CCGR5_CG2_SHIFT (4U)
3715#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
3716#define CCM_CCGR5_CG3_MASK (0xC0U)
3717#define CCM_CCGR5_CG3_SHIFT (6U)
3718#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
3719#define CCM_CCGR5_CG4_MASK (0x300U)
3720#define CCM_CCGR5_CG4_SHIFT (8U)
3721#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
3722#define CCM_CCGR5_CG5_MASK (0xC00U)
3723#define CCM_CCGR5_CG5_SHIFT (10U)
3724#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
3725#define CCM_CCGR5_CG6_MASK (0x3000U)
3726#define CCM_CCGR5_CG6_SHIFT (12U)
3727#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
3728#define CCM_CCGR5_CG7_MASK (0xC000U)
3729#define CCM_CCGR5_CG7_SHIFT (14U)
3730#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
3731#define CCM_CCGR5_CG8_MASK (0x30000U)
3732#define CCM_CCGR5_CG8_SHIFT (16U)
3733#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
3734#define CCM_CCGR5_CG9_MASK (0xC0000U)
3735#define CCM_CCGR5_CG9_SHIFT (18U)
3736#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
3737#define CCM_CCGR5_CG10_MASK (0x300000U)
3738#define CCM_CCGR5_CG10_SHIFT (20U)
3739#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
3740#define CCM_CCGR5_CG11_MASK (0xC00000U)
3741#define CCM_CCGR5_CG11_SHIFT (22U)
3742#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
3743#define CCM_CCGR5_CG12_MASK (0x3000000U)
3744#define CCM_CCGR5_CG12_SHIFT (24U)
3745#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
3746#define CCM_CCGR5_CG13_MASK (0xC000000U)
3747#define CCM_CCGR5_CG13_SHIFT (26U)
3748#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
3749#define CCM_CCGR5_CG14_MASK (0x30000000U)
3750#define CCM_CCGR5_CG14_SHIFT (28U)
3751#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
3752#define CCM_CCGR5_CG15_MASK (0xC0000000U)
3753#define CCM_CCGR5_CG15_SHIFT (30U)
3754#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
3755/*! @} */
3756
3757/*! @name CCGR6 - CCM Clock Gating Register 6 */
3758/*! @{ */
3759#define CCM_CCGR6_CG0_MASK (0x3U)
3760#define CCM_CCGR6_CG0_SHIFT (0U)
3761#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
3762#define CCM_CCGR6_CG1_MASK (0xCU)
3763#define CCM_CCGR6_CG1_SHIFT (2U)
3764#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
3765#define CCM_CCGR6_CG2_MASK (0x30U)
3766#define CCM_CCGR6_CG2_SHIFT (4U)
3767#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
3768#define CCM_CCGR6_CG3_MASK (0xC0U)
3769#define CCM_CCGR6_CG3_SHIFT (6U)
3770#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
3771#define CCM_CCGR6_CG4_MASK (0x300U)
3772#define CCM_CCGR6_CG4_SHIFT (8U)
3773#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
3774#define CCM_CCGR6_CG5_MASK (0xC00U)
3775#define CCM_CCGR6_CG5_SHIFT (10U)
3776#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
3777#define CCM_CCGR6_CG6_MASK (0x3000U)
3778#define CCM_CCGR6_CG6_SHIFT (12U)
3779#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
3780#define CCM_CCGR6_CG7_MASK (0xC000U)
3781#define CCM_CCGR6_CG7_SHIFT (14U)
3782#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
3783#define CCM_CCGR6_CG8_MASK (0x30000U)
3784#define CCM_CCGR6_CG8_SHIFT (16U)
3785#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
3786#define CCM_CCGR6_CG9_MASK (0xC0000U)
3787#define CCM_CCGR6_CG9_SHIFT (18U)
3788#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
3789#define CCM_CCGR6_CG10_MASK (0x300000U)
3790#define CCM_CCGR6_CG10_SHIFT (20U)
3791#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
3792#define CCM_CCGR6_CG11_MASK (0xC00000U)
3793#define CCM_CCGR6_CG11_SHIFT (22U)
3794#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
3795#define CCM_CCGR6_CG12_MASK (0x3000000U)
3796#define CCM_CCGR6_CG12_SHIFT (24U)
3797#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
3798#define CCM_CCGR6_CG13_MASK (0xC000000U)
3799#define CCM_CCGR6_CG13_SHIFT (26U)
3800#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
3801#define CCM_CCGR6_CG14_MASK (0x30000000U)
3802#define CCM_CCGR6_CG14_SHIFT (28U)
3803#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
3804#define CCM_CCGR6_CG15_MASK (0xC0000000U)
3805#define CCM_CCGR6_CG15_SHIFT (30U)
3806#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
3807/*! @} */
3808
3809/*! @name CMEOR - CCM Module Enable Overide Register */
3810/*! @{ */
3811#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
3812#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
3813/*! MOD_EN_OV_GPT
3814 * 0b0..don't override module enable signal
3815 * 0b1..override module enable signal
3816 */
3817#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
3818#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
3819#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
3820/*! MOD_EN_OV_PIT
3821 * 0b0..don't override module enable signal
3822 * 0b1..override module enable signal
3823 */
3824#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
3825#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
3826#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
3827/*! MOD_EN_OV_TRNG
3828 * 0b0..don't override module enable signal
3829 * 0b1..override module enable signal
3830 */
3831#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
3832/*! @} */
3833
3834
3835/*!
3836 * @}
3837 */ /* end of group CCM_Register_Masks */
3838
3839
3840/* CCM - Peripheral instance base addresses */
3841/** Peripheral CCM base address */
3842#define CCM_BASE (0x400FC000u)
3843/** Peripheral CCM base pointer */
3844#define CCM ((CCM_Type *)CCM_BASE)
3845/** Array initializer of CCM peripheral base addresses */
3846#define CCM_BASE_ADDRS { CCM_BASE }
3847/** Array initializer of CCM peripheral base pointers */
3848#define CCM_BASE_PTRS { CCM }
3849/** Interrupt vectors for the CCM peripheral type */
3850#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }
3851
3852/*!
3853 * @}
3854 */ /* end of group CCM_Peripheral_Access_Layer */
3855
3856
3857/* ----------------------------------------------------------------------------
3858 -- CCM_ANALOG Peripheral Access Layer
3859 ---------------------------------------------------------------------------- */
3860
3861/*!
3862 * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
3863 * @{
3864 */
3865
3866/** CCM_ANALOG - Register Layout Typedef */
3867typedef struct {
3868 uint8_t RESERVED_0[16];
3869 __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */
3870 __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */
3871 __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */
3872 __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */
3873 uint8_t RESERVED_1[16];
3874 __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */
3875 __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */
3876 __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */
3877 __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */
3878 __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */
3879 uint8_t RESERVED_2[12];
3880 __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */
3881 uint8_t RESERVED_3[12];
3882 __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */
3883 uint8_t RESERVED_4[12];
3884 __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */
3885 __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */
3886 __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */
3887 __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */
3888 __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */
3889 uint8_t RESERVED_5[12];
3890 __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */
3891 uint8_t RESERVED_6[76];
3892 __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */
3893 __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */
3894 __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */
3895 __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */
3896 __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */
3897 __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */
3898 __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */
3899 __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */
3900 __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */
3901 __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */
3902 __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */
3903 __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */
3904 uint8_t RESERVED_7[64];
3905 __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */
3906 __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */
3907 __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */
3908 __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */
3909 __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */
3910 __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */
3911 __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */
3912 __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */
3913 __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */
3914 __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */
3915 __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */
3916 __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */
3917} CCM_ANALOG_Type;
3918
3919/* ----------------------------------------------------------------------------
3920 -- CCM_ANALOG Register Masks
3921 ---------------------------------------------------------------------------- */
3922
3923/*!
3924 * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
3925 * @{
3926 */
3927
3928/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */
3929/*! @{ */
3930#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)
3931#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)
3932#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
3933#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)
3934#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)
3935/*! EN_USB_CLKS
3936 * 0b0..PLL outputs for USBPHYn off.
3937 * 0b1..PLL outputs for USBPHYn on.
3938 */
3939#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
3940#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)
3941#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)
3942#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
3943#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)
3944#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)
3945#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
3946#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)
3947#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
3948/*! BYPASS_CLK_SRC
3949 * 0b00..Select the 24MHz oscillator as source.
3950 */
3951#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
3952#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)
3953#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)
3954#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
3955#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)
3956#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)
3957#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
3958/*! @} */
3959
3960/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */
3961/*! @{ */
3962#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)
3963#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
3964#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
3965#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
3966#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
3967/*! EN_USB_CLKS
3968 * 0b0..PLL outputs for USBPHYn off.
3969 * 0b1..PLL outputs for USBPHYn on.
3970 */
3971#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
3972#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)
3973#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)
3974#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
3975#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)
3976#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)
3977#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
3978#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
3979#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
3980/*! BYPASS_CLK_SRC
3981 * 0b00..Select the 24MHz oscillator as source.
3982 */
3983#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
3984#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)
3985#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)
3986#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
3987#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)
3988#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)
3989#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
3990/*! @} */
3991
3992/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */
3993/*! @{ */
3994#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)
3995#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
3996#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
3997#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
3998#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
3999/*! EN_USB_CLKS
4000 * 0b0..PLL outputs for USBPHYn off.
4001 * 0b1..PLL outputs for USBPHYn on.
4002 */
4003#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
4004#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)
4005#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)
4006#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
4007#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)
4008#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)
4009#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
4010#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
4011#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
4012/*! BYPASS_CLK_SRC
4013 * 0b00..Select the 24MHz oscillator as source.
4014 */
4015#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
4016#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)
4017#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)
4018#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
4019#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)
4020#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)
4021#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
4022/*! @} */
4023
4024/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */
4025/*! @{ */
4026#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)
4027#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
4028#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
4029#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
4030#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
4031/*! EN_USB_CLKS
4032 * 0b0..PLL outputs for USBPHYn off.
4033 * 0b1..PLL outputs for USBPHYn on.
4034 */
4035#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
4036#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)
4037#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)
4038#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
4039#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)
4040#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)
4041#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
4042#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
4043#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
4044/*! BYPASS_CLK_SRC
4045 * 0b00..Select the 24MHz oscillator as source.
4046 */
4047#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
4048#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)
4049#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)
4050#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
4051#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)
4052#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)
4053#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
4054/*! @} */
4055
4056/*! @name PLL_SYS - Analog System PLL Control Register */
4057/*! @{ */
4058#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)
4059#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)
4060#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
4061#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)
4062#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)
4063#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
4064#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)
4065#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)
4066#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
4067#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)
4068#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)
4069/*! BYPASS_CLK_SRC
4070 * 0b00..Select the 24MHz oscillator as source.
4071 */
4072#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
4073#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)
4074#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)
4075#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
4076#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)
4077#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)
4078#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
4079/*! @} */
4080
4081/*! @name PLL_SYS_SET - Analog System PLL Control Register */
4082/*! @{ */
4083#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)
4084#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)
4085#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
4086#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)
4087#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)
4088#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
4089#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)
4090#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)
4091#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
4092#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
4093#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
4094/*! BYPASS_CLK_SRC
4095 * 0b00..Select the 24MHz oscillator as source.
4096 */
4097#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
4098#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)
4099#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)
4100#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
4101#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)
4102#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)
4103#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
4104/*! @} */
4105
4106/*! @name PLL_SYS_CLR - Analog System PLL Control Register */
4107/*! @{ */
4108#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)
4109#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)
4110#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
4111#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)
4112#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)
4113#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
4114#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)
4115#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)
4116#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
4117#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
4118#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
4119/*! BYPASS_CLK_SRC
4120 * 0b00..Select the 24MHz oscillator as source.
4121 */
4122#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
4123#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)
4124#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)
4125#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
4126#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)
4127#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)
4128#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
4129/*! @} */
4130
4131/*! @name PLL_SYS_TOG - Analog System PLL Control Register */
4132/*! @{ */
4133#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)
4134#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)
4135#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
4136#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)
4137#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)
4138#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
4139#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)
4140#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)
4141#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
4142#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
4143#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
4144/*! BYPASS_CLK_SRC
4145 * 0b00..Select the 24MHz oscillator as source.
4146 */
4147#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
4148#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)
4149#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)
4150#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
4151#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)
4152#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)
4153#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
4154/*! @} */
4155
4156/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */
4157/*! @{ */
4158#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)
4159#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)
4160#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
4161#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)
4162#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)
4163/*! ENABLE - Enable bit
4164 * 0b0..Spread spectrum modulation disabled
4165 * 0b1..Soread spectrum modulation enabled
4166 */
4167#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
4168#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)
4169#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)
4170#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
4171/*! @} */
4172
4173/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */
4174/*! @{ */
4175#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)
4176#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)
4177#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
4178/*! @} */
4179
4180/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */
4181/*! @{ */
4182#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)
4183#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)
4184#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
4185/*! @} */
4186
4187/*! @name PLL_AUDIO - Analog Audio PLL control Register */
4188/*! @{ */
4189#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
4190#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
4191#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
4192#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)
4193#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)
4194#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
4195#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)
4196#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)
4197#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
4198#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
4199#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
4200/*! BYPASS_CLK_SRC
4201 * 0b00..Select the 24MHz oscillator as source.
4202 * 0b10..Reserved1
4203 * 0b11..Reserved2
4204 */
4205#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
4206#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)
4207#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)
4208#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
4209#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
4210#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
4211/*! POST_DIV_SELECT
4212 * 0b00..Divide by 4.
4213 * 0b01..Divide by 2.
4214 * 0b10..Divide by 1.
4215 * 0b11..Reserved
4216 */
4217#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
4218#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)
4219#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)
4220#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
4221/*! @} */
4222
4223/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */
4224/*! @{ */
4225#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
4226#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
4227#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
4228#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)
4229#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
4230#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
4231#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)
4232#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)
4233#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
4234#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
4235#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
4236/*! BYPASS_CLK_SRC
4237 * 0b00..Select the 24MHz oscillator as source.
4238 * 0b10..Reserved1
4239 * 0b11..Reserved2
4240 */
4241#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
4242#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)
4243#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)
4244#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
4245#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
4246#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
4247/*! POST_DIV_SELECT
4248 * 0b00..Divide by 4.
4249 * 0b01..Divide by 2.
4250 * 0b10..Divide by 1.
4251 * 0b11..Reserved
4252 */
4253#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
4254#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)
4255#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)