aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1011/drivers/fsl_clock.h
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1011/drivers/fsl_clock.h')
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1011/drivers/fsl_clock.h1368
1 files changed, 1368 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1011/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1011/drivers/fsl_clock.h
new file mode 100644
index 000000000..a3d369512
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1011/drivers/fsl_clock.h
@@ -0,0 +1,1368 @@
1/*
2 * Copyright 2019-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
13/*! @addtogroup clock */
14/*! @{ */
15
16/*! @file */
17
18/*******************************************************************************
19 * Configurations
20 ******************************************************************************/
21
22/*! @brief Configure whether driver controls clock
23 *
24 * When set to 0, peripheral drivers will enable clock in initialize function
25 * and disable clock in de-initialize function. When set to 1, peripheral
26 * driver will not control the clock, application could control the clock out of
27 * the driver.
28 *
29 * @note All drivers share this feature switcher. If it is set to 1, application
30 * should handle clock enable and disable for all drivers.
31 */
32#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34#endif
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*! @name Driver version */
41/*@{*/
42/*! @brief CLOCK driver version 2.4.0. */
43#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
44
45/* analog pll definition */
46#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
47#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
48#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
49
50/* Definition for delay API in clock driver, users can redefine it to the real application. */
51#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
52#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (500000000UL)
53#endif
54
55/*@}*/
56
57/*!
58 * @brief CCM registers offset.
59 */
60#define CCSR_OFFSET 0x0C
61#define CBCDR_OFFSET 0x14
62#define CBCMR_OFFSET 0x18
63#define CSCMR1_OFFSET 0x1C
64#define CSCMR2_OFFSET 0x20
65#define CSCDR1_OFFSET 0x24
66#define CDCDR_OFFSET 0x30
67#define CSCDR2_OFFSET 0x38
68#define CS1CDR_OFFSET 0x28
69
70/*!
71 * @brief CCM Analog registers offset.
72 */
73#define PLL_SYS_OFFSET 0x30
74#define PLL_USB1_OFFSET 0x10
75#define PLL_AUDIO_OFFSET 0x70
76#define PLL_ENET_OFFSET 0xE0
77
78#define CCM_TUPLE(reg, shift, mask, busyShift) \
79 (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
80#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + (((uint32_t)tuple) & 0xFFU))))
81#define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
82#define CCM_TUPLE_MASK(tuple) \
83 ((uint32_t)(((((uint32_t)tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
84#define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
85
86#define CCM_NO_BUSY_WAIT (0x20U)
87
88/*!
89 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
90 */
91#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
92#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)(tuple)) & 0x1FU)
93#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
94 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
95#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
96
97#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
98#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
99#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
100
101/*!
102 * @brief clock1PN frequency.
103 */
104#define CLKPN_FREQ 0U
105
106/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
107 *
108 * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
109 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
110 * if XTAL is 24MHz,
111 * @code
112 * CLOCK_InitExternalClk(false);
113 * CLOCK_SetXtalFreq(240000000);
114 * @endcode
115 */
116extern volatile uint32_t g_xtalFreq;
117
118/*! @brief External RTC XTAL (32K OSC) clock frequency.
119 *
120 * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
121 * function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
122 */
123extern volatile uint32_t g_rtcXtalFreq;
124
125/* For compatible with other platforms */
126#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
127#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
128
129/*! @brief Clock ip name array for ADC. */
130#define ADC_CLOCKS \
131 { \
132 kCLOCK_IpInvalid, kCLOCK_Adc1 \
133 }
134
135/*! @brief Clock ip name array for AOI. */
136#define AOI_CLOCKS \
137 { \
138 kCLOCK_Aoi \
139 }
140
141/*! @brief Clock ip name array for DCDC. */
142#define DCDC_CLOCKS \
143 { \
144 kCLOCK_Dcdc \
145 }
146
147/*! @brief Clock ip name array for DCP. */
148#define DCP_CLOCKS \
149 { \
150 kCLOCK_Dcp \
151 }
152
153/*! @brief Clock ip name array for DMAMUX_CLOCKS. */
154#define DMAMUX_CLOCKS \
155 { \
156 kCLOCK_Dma \
157 }
158
159/*! @brief Clock ip name array for DMA. */
160#define EDMA_CLOCKS \
161 { \
162 kCLOCK_Dma \
163 }
164
165/*! @brief Clock ip name array for EWM. */
166#define EWM_CLOCKS \
167 { \
168 kCLOCK_Ewm0 \
169 }
170
171/*! @brief Clock ip name array for FLEXIO. */
172#define FLEXIO_CLOCKS \
173 { \
174 kCLOCK_IpInvalid, kCLOCK_Flexio1 \
175 }
176
177/*! @brief Clock ip name array for FLEXRAM. */
178#define FLEXRAM_CLOCKS \
179 { \
180 kCLOCK_FlexRam \
181 }
182
183/*! @brief Clock ip name array for FLEXSPI. */
184#define FLEXSPI_CLOCKS \
185 { \
186 kCLOCK_FlexSpi \
187 }
188
189/*! @brief Clock ip name array for GPIO. */
190#define GPIO_CLOCKS \
191 { \
192 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Gpio5 \
193 }
194
195/*! @brief Clock ip name array for GPT. */
196#define GPT_CLOCKS \
197 { \
198 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
199 }
200
201/*! @brief Clock ip name array for KPP. */
202#define KPP_CLOCKS \
203 { \
204 kCLOCK_Kpp \
205 }
206
207/*! @brief Clock ip name array for LPI2C. */
208#define LPI2C_CLOCKS \
209 { \
210 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2 \
211 }
212
213/*! @brief Clock ip name array for LPSPI. */
214#define LPSPI_CLOCKS \
215 { \
216 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2 \
217 }
218
219/*! @brief Clock ip name array for LPUART. */
220#define LPUART_CLOCKS \
221 { \
222 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4 \
223 }
224
225/*! @brief Clock ip name array for OCRAM EXSC. */
226#define OCRAM_EXSC_CLOCKS \
227 { \
228 kCLOCK_OcramExsc \
229 }
230
231/*! @brief Clock ip name array for PIT. */
232#define PIT_CLOCKS \
233 { \
234 kCLOCK_Pit \
235 }
236
237/*! @brief Clock ip name array for PWM. */
238#define PWM_CLOCKS \
239 { \
240 {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
241 { \
242 kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1 \
243 } \
244 }
245
246/*! @brief Clock ip name array for RTWDOG. */
247#define RTWDOG_CLOCKS \
248 { \
249 kCLOCK_Wdog3 \
250 }
251
252/*! @brief Clock ip name array for SAI. */
253#define SAI_CLOCKS \
254 { \
255 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_IpInvalid, kCLOCK_Sai3 \
256 }
257
258/*! @brief Clock ip name array for TRNG. */
259#define TRNG_CLOCKS \
260 { \
261 kCLOCK_Trng \
262 }
263
264/*! @brief Clock ip name array for WDOG. */
265#define WDOG_CLOCKS \
266 { \
267 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
268 }
269
270/*! @brief Clock ip name array for SPDIF. */
271#define SPDIF_CLOCKS \
272 { \
273 kCLOCK_Spdif \
274 }
275
276/*! @brief Clock ip name array for XBARA. */
277#define XBARA_CLOCKS \
278 { \
279 kCLOCK_Xbar1 \
280 }
281
282#define CLOCK_SOURCE_NONE (0xFFU)
283
284#define CLOCK_ROOT_SOUCE \
285 { \
286 {kCLOCK_FlexspiSel, kCLOCK_PeriphClk2, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< FLEXSPI clock root */ \
287 {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \
288 kCLOCK_SysPllPfd2Clk}, /*!< LPSPI clock root. */ \
289 {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \
290 kCLOCK_SysPllPfd1Clk}, /*!< Trace clock root. */ \
291 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_Usb1SwClk, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI1 clock root. */ \
292 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_Usb1SwClk, kCLOCK_AudioPllClk, kCLOCK_NoneName}, /*!< SAI3 clock root. */ \
293 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, kCLOCK_NoneName}, /*!< LPI2C clock root. */ \
294 {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_PerClk, kCLOCK_NoneName}, /*!< UART clock root. */ \
295 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_NoneName, kCLOCK_Usb1SwClk}, /*!< SPDIF clock root. */ \
296 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_SysPllClk, \
297 kCLOCK_Usb1SwClk}, /*!< FLEXIO1 clock root. */ \
298 }
299
300#define CLOCK_ROOT_MUX_TUPLE \
301 { \
302 kCLOCK_FlexspiMux, kCLOCK_LpspiMux, kCLOCK_TraceMux, kCLOCK_Sai1Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, \
303 kCLOCK_UartMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, \
304 }
305
306#define CLOCK_ROOT_NONE_PRE_DIV 0UL
307
308#define CLOCK_ROOT_DIV_TUPLE \
309 { \
310 {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, /*!< FLEXSPI clock root */ \
311 {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, /*!< LPSPI clock root. */ \
312 {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, /*!< Trace clock root. */ \
313 {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, /*!< SAI1 clock root. */ \
314 {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, /*!< SAI3 clock root. */ \
315 {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, /*!< LPI2C clock root. */ \
316 {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, /*!< UART clock root. */ \
317 {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, /*!< SPDIF clock root. */ \
318 {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, /*!< FLEXIO1 clock root. */ \
319 }
320
321/*! @brief Clock name used to get clock frequency. */
322typedef enum _clock_name
323{
324 kCLOCK_CpuClk = 0x0U, /*!< CPU clock */
325 kCLOCK_CoreClk = 0x1U, /*!< CORE clock */
326 kCLOCK_IpgClk = 0x2U, /*!< IPG clock */
327 kCLOCK_PerClk = 0x3U, /*!< PER clock */
328
329 kCLOCK_OscClk = 0x4U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
330 kCLOCK_RtcClk = 0x5U, /*!< RTC clock. (RTCCLK) */
331
332 kCLOCK_Usb1PllClk = 0x6U, /*!< USB1PLLCLK. */
333 kCLOCK_Usb1PllPfd0Clk = 0x7U, /*!< USB1PLLPDF0CLK. */
334 kCLOCK_Usb1PllPfd1Clk = 0x8U, /*!< USB1PLLPFD1CLK. */
335 kCLOCK_Usb1PllPfd2Clk = 0x9U, /*!< USB1PLLPFD2CLK. */
336 kCLOCK_Usb1PllPfd3Clk = 0xAU, /*!< USB1PLLPFD3CLK. */
337 kCLOCK_Usb1SwClk = 0x12U, /*!< USB1PLLSWCLK */
338 kCLOCK_Usb1Sw60MClk = 0x13U, /*!< USB1PLLSw60MCLK */
339 kCLOCK_Usb1Sw80MClk = 0x14U, /*!< USB1PLLSw80MCLK */
340
341 kCLOCK_SysPllClk = 0xBU, /*!< SYSPLLCLK. */
342 kCLOCK_SysPllPfd0Clk = 0xCU, /*!< SYSPLLPDF0CLK. */
343 kCLOCK_SysPllPfd1Clk = 0xDU, /*!< SYSPLLPFD1CLK. */
344 kCLOCK_SysPllPfd2Clk = 0xEU, /*!< SYSPLLPFD2CLK. */
345 kCLOCK_SysPllPfd3Clk = 0xFU, /*!< SYSPLLPFD3CLK. */
346
347 kCLOCK_EnetPll500MClk = 0x10U, /*!< Enet PLLCLK ref_enetpll500M. */
348
349 kCLOCK_AudioPllClk = 0x11U, /*!< Audio PLLCLK. */
350
351 kCLOCK_PeriphClk2 = 0x15U, /*!< Periph CLK2 selection. */
352 kCLOCK_FlexspiSel = 0x16U, /*!< Flexspi selection. */
353 kCLOCK_NoneName = CLOCK_SOURCE_NONE, /*!< None Clock Name. */
354} clock_name_t;
355
356#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */
357#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */
358
359/*!
360 * @brief CCM CCGR gate control for each module independently.
361 */
362typedef enum _clock_ip_name
363{
364 kCLOCK_IpInvalid = -1,
365
366 /* CCM CCGR0 */
367 kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */
368 kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */
369 kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */
370 kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */
371 kCLOCK_Sim_m_clk_r = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */
372 kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */
373 kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */
374 kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */
375 kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */
376 kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */
377 kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */
378 kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */
379
380 /* CCM CCGR1 */
381 kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */
382 kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */
383 kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */
384 /*!< CCGR1, CG7, Reserved */
385 kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */
386 kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */
387 kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */
388 kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */
389 kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */
390 kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */
391 kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */
392
393 /* CCM CCGR2 */
394 kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */
395 /*!< CCGR2, CG1, Reserved */
396 kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */
397 kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */
398 kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */
399 kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */
400 /*!< CCGR2, CG7, Reserved */
401 /*!< CCGR2, CG8, Reserved */
402 /*!< CCGR2, CG9, Reserved */
403 /*!< CCGR2, CG10, Reserved */
404 kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */
405 /*!< CCGR2, CG12, Reserved */
406 /*!< CCGR2, CG13, Reserved */
407 /*!< CCGR2, CG14, Reserved */
408 /*!< CCGR2, CG15, Reserved */
409
410 /* CCM CCGR3 */
411 /*!< CCGR3, CG0, Reserved */
412 kCLOCK_Aoi = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */
413 /*!< CCGR3, CG5, Reserved */
414 /*!< CCGR3, CG6, Reserved */
415 kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */
416 kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */
417 kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */
418 /*!< CCGR3, CG14, Reserved */
419 kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */
420
421 /* CCM CCGR4 */
422 kCLOCK_Sim_m7_clk_r = (4U << 8U) | CCM_CCGR4_CG0_SHIFT, /*!< CCGR4, CG0 */
423 kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */
424 kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */
425 /*!< CCGR4, CG3, Reserved */
426 kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */
427 kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */
428 kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */
429 kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */
430 /*!< CCGR4, CG10, Reserved */
431 /*!< CCGR4, CG11, Reserved */
432 /*!< CCGR4, CG12, Reserved */
433 /*!< CCGR4, CG14, Reserved */
434 kCLOCK_Dma_ps = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15, */
435
436 /* CCM CCGR5 */
437 kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */
438 kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */
439 kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */
440 kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */
441 kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */
442 kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */
443 /*!< CCGR5, CG6, Reserved */
444 kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */
445 /*!< CCGR5, CG8, Reserved */
446 kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */
447 /*!< CCGR5, CG10, Reserved */
448 kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */
449 kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */
450 kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */
451 kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */
452
453 /* CCM CCGR6 */
454 kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */
455 kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */
456 kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */
457 kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */
458 /*!< CCGR6, CG9, Reserved */
459 kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */
460 kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */
461 /*!< CCGR6, CG13, Reserved */
462 /*!< CCGR6, CG15, Reserved */
463
464} clock_ip_name_t;
465
466/*! @brief OSC 24M sorce select */
467typedef enum _clock_osc
468{
469 kCLOCK_RcOsc = 0U, /*!< On chip OSC. */
470 kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
471} clock_osc_t;
472
473/*! @brief Clock gate value */
474typedef enum _clock_gate_value
475{
476 kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */
477 kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */
478 kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */
479} clock_gate_value_t;
480
481/*! @brief System clock mode */
482typedef enum _clock_mode_t
483{
484 kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */
485 kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
486 kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
487} clock_mode_t;
488
489/*!
490 * @brief MUX control names for clock mux setting.
491 *
492 * These constants define the mux control names for clock mux setting.\n
493 * - 0:7: REG offset to CCM_BASE in bytes.
494 * - 8:15: Root clock setting bit field shift.
495 * - 16:31: Root clock setting bit field width.
496 */
497typedef enum _clock_mux
498{
499 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
500 CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
501 CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
502 CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */
503
504 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
505 CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
506 CCM_CBCDR_PERIPH_CLK_SEL_MASK,
507 CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */
508
509 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
510 CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
511 CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
512 CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */
513 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
514 CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
515 CCM_CBCMR_TRACE_CLK_SEL_MASK,
516 CCM_NO_BUSY_WAIT), /*!< trace mux name */
517 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
518 CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
519 CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
520 CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
521 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
522 CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
523 CCM_CBCMR_LPSPI_CLK_SEL_MASK,
524 CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
525
526 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
527 CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
528 CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
529 CCM_NO_BUSY_WAIT), /*!< flexspi mux name */
530 kCLOCK_FlexspiSrcMux = CCM_TUPLE(CSCMR1_OFFSET,
531 CCM_CSCMR1_FLEXSPI_CLK_SRC_SHIFT,
532 CCM_CSCMR1_FLEXSPI_CLK_SRC_MASK,
533 CCM_NO_BUSY_WAIT), /*!< flexspi SRC mux name */
534 kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET,
535 CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
536 CCM_CSCMR1_SAI3_CLK_SEL_MASK,
537 CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
538 kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET,
539 CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
540 CCM_CSCMR1_SAI1_CLK_SEL_MASK,
541 CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
542 kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
543 CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
544 CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
545 CCM_NO_BUSY_WAIT), /*!< perclk mux name */
546
547 kCLOCK_Flexio1Mux = CCM_TUPLE(CSCMR2_OFFSET,
548 CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT,
549 CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK,
550 CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */
551
552 kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
553 CCM_CSCDR1_UART_CLK_SEL_SHIFT,
554 CCM_CSCDR1_UART_CLK_SEL_MASK,
555 CCM_NO_BUSY_WAIT), /*!< uart mux name */
556
557 kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET,
558 CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
559 CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
560 CCM_NO_BUSY_WAIT), /*!< spdif mux name */
561
562 kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET,
563 CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
564 CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
565 CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
566} clock_mux_t;
567
568/*!
569 * @brief DIV control names for clock div setting.
570 *
571 * These constants define div control names for clock div setting.\n
572 * - 0:7: REG offset to CCM_BASE in bytes.
573 * - 8:15: Root clock setting bit field shift.
574 * - 16:31: Root clock setting bit field width.
575 */
576typedef enum _clock_div
577{
578 kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET,
579 CCM_CBCDR_AHB_PODF_SHIFT,
580 CCM_CBCDR_AHB_PODF_MASK,
581 CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
582 kCLOCK_IpgDiv = CCM_TUPLE(
583 CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
584
585 kCLOCK_LpspiDiv = CCM_TUPLE(
586 CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
587
588 kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
589 CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
590 CCM_CSCMR1_FLEXSPI_PODF_MASK,
591 CCM_NO_BUSY_WAIT), /*!< flexspi div name */
592 kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET,
593 CCM_CSCMR1_PERCLK_PODF_SHIFT,
594 CCM_CSCMR1_PERCLK_PODF_MASK,
595 CCM_NO_BUSY_WAIT), /*!< perclk div name */
596 kCLOCK_AdcDiv = CCM_TUPLE(CSCMR2_OFFSET,
597 CCM_CSCMR2_ADC_ACLK_PODF_SHIFT,
598 CCM_CSCMR2_ADC_ACLK_PODF_MASK,
599 CCM_NO_BUSY_WAIT), /*!< perclk div name */
600
601 kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET,
602 CCM_CSCDR1_TRACE_PODF_SHIFT,
603 CCM_CSCDR1_TRACE_PODF_MASK,
604 CCM_NO_BUSY_WAIT), /*!< trace div name */
605 kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET,
606 CCM_CSCDR1_UART_CLK_PODF_SHIFT,
607 CCM_CSCDR1_UART_CLK_PODF_MASK,
608 CCM_NO_BUSY_WAIT), /*!< uart div name */
609
610 kCLOCK_Flexio1Div = CCM_TUPLE(CS1CDR_OFFSET,
611 CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT,
612 CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK,
613 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
614 kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
615 CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
616 CCM_CS1CDR_SAI3_CLK_PRED_MASK,
617 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
618 kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET,
619 CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
620 CCM_CS1CDR_SAI3_CLK_PODF_MASK,
621 CCM_NO_BUSY_WAIT), /*!< sai3 div name */
622 kCLOCK_Flexio1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
623 CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT,
624 CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK,
625 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
626 kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
627 CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
628 CCM_CS1CDR_SAI1_CLK_PRED_MASK,
629 CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */
630 kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET,
631 CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
632 CCM_CS1CDR_SAI1_CLK_PODF_MASK,
633 CCM_NO_BUSY_WAIT), /*!< sai1 div name */
634
635 kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
636 CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
637 CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
638 CCM_NO_BUSY_WAIT), /*!< spdif pre div name */
639 kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
640 CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
641 CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
642 CCM_NO_BUSY_WAIT), /*!< spdif div name */
643
644 kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
645 CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
646 CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
647 CCM_NO_BUSY_WAIT), /*!< lpi2c div name */
648 kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV, /*!< None Pre div. */
649} clock_div_t;
650
651/*! @brief USB clock source definition. */
652typedef enum _clock_usb_src
653{
654 kCLOCK_Usb480M = 0, /*!< Use 480M. */
655 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
656 care the clock source. */
657} clock_usb_src_t;
658
659/*! @brief Source of the USB HS PHY. */
660typedef enum _clock_usb_phy_src
661{
662 kCLOCK_Usbphy480M = 0, /*!< Use 480M. */
663} clock_usb_phy_src_t;
664
665/*!@brief PLL clock source, bypass cloco source also */
666enum _clock_pll_clk_src
667{
668 kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
669 kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
670};
671
672/*! @brief PLL configuration for USB */
673typedef struct _clock_usb_pll_config
674{
675 uint8_t loopDivider; /*!< PLL loop divider.
676 0 - Fout=Fref*20;
677 1 - Fout=Fref*22 */
678 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
679
680} clock_usb_pll_config_t;
681
682/*! @brief PLL configuration for System */
683typedef struct _clock_sys_pll_config
684{
685 uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M).
686 0 - Fout=Fref*20;
687 1 - Fout=Fref*22 */
688 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
689 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
690 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
691 uint16_t ss_stop; /*!< Stop value to get frequency change. */
692 uint8_t ss_enable; /*!< Enable spread spectrum modulation */
693 uint16_t ss_step; /*!< Step value to get frequency change step. */
694
695} clock_sys_pll_config_t;
696
697/*! @brief PLL configuration for AUDIO and VIDEO */
698typedef struct _clock_audio_pll_config
699{
700 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
701 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
702 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
703 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
704 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
705} clock_audio_pll_config_t;
706
707/*! @brief PLL configuration for ENET */
708typedef struct _clock_enet_pll_config
709{
710 bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
711
712 bool enableClkOutput500M; /*!< Power on and enable PLL clock output for ENET (ref_enetpll500M). */
713
714 bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
715 uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock.
716 b00 25MHz
717 b01 50MHz
718 b10 100MHz (not 50% duty cycle)
719 b11 125MHz */
720 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
721
722} clock_enet_pll_config_t;
723
724/*! @brief PLL name */
725typedef enum _clock_pll
726{
727 kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
728 kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
729 kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
730 kCLOCK_PllEnet500M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT), /*!< PLL ENET */
731} clock_pll_t;
732
733/*! @brief PLL PFD name */
734typedef enum _clock_pfd
735{
736 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
737 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
738 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
739 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
740} clock_pfd_t;
741
742/*!
743 * @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
744 */
745typedef enum _clock_output1_selection
746{
747 kCLOCK_OutputPllUsb1Sw = 0U, /*!< Selects USB1 PLL SW clock(Divided by 2) output. */
748 kCLOCK_OutputPllSys = 1U, /*!< Selects SYS PLL clock(Divided by 2) output. */
749 kCLOCK_OutputPllENET = 2U, /*!< Selects ENET PLL clock(Divided by 2) output. */
750 kCLOCK_OutputCoreClk = 0xBU, /*!< Selects Core clock root output. */
751 kCLOCK_OutputIpgClk = 0xCU, /*!< Selects IPG clock root output. */
752 kCLOCK_OutputPerClk = 0xDU, /*!< Selects PERCLK clock root output. */
753 kCLOCK_OutputPll4MainClk = 0xFU, /*!< Selects PLL4 main clock output. */
754 kCLOCK_DisableClockOutput1 = 0x10U, /*!< Disables CLKO1. */
755} clock_output1_selection_t;
756
757/*!
758 * @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
759 *
760 */
761typedef enum _clock_output2_selection
762{
763 kCLOCK_OutputLpi2cClk = 6U, /*!< Selects LPI2C clock root output. */
764 kCLOCK_OutputOscClk = 0xEU, /*!< Selects OSC output. */
765 kCLOCK_OutputLpspiClk = 0x10U, /*!< Selects LPSPI clock root output. */
766 kCLOCK_OutputSai1Clk = 0x12U, /*!< Selects SAI1 clock root output. */
767 kCLOCK_OutputSai3Clk = 0x14U, /*!< Selects SAI3 clock root output. */
768 kCLOCK_OutputTraceClk = 0x16U, /*!< Selects Trace clock root output. */
769 kCLOCK_OutputFlexspiClk = 0x1BU, /*!< Selects FLEXSPI clock root output. */
770 kCLOCK_OutputUartClk = 0x1CU, /*!< Selects UART clock root output. */
771 kCLOCK_OutputSpdif0Clk = 0x1DU, /*!< Selects SPDIF0 clock root output. */
772 kCLOCK_DisableClockOutput2 = 0x1FU, /*!< Disables CLKO2. */
773} clock_output2_selection_t;
774
775/*!
776 * @brief The enumerator of clock output's divider.
777 */
778typedef enum _clock_output_divider
779{
780 kCLOCK_DivideBy1 = 0U, /*!< Output clock divided by 1. */
781 kCLOCK_DivideBy2, /*!< Output clock divided by 2. */
782 kCLOCK_DivideBy3, /*!< Output clock divided by 3. */
783 kCLOCK_DivideBy4, /*!< Output clock divided by 4. */
784 kCLOCK_DivideBy5, /*!< Output clock divided by 5. */
785 kCLOCK_DivideBy6, /*!< Output clock divided by 6. */
786 kCLOCK_DivideBy7, /*!< Output clock divided by 7. */
787 kCLOCK_DivideBy8, /*!< Output clock divided by 8. */
788} clock_output_divider_t;
789
790/*!
791 * @brief The enumerator of clock root.
792 */
793typedef enum _clock_root
794{
795 kCLOCK_FlexspiClkRoot = 0U, /*!< FLEXSPI clock root. */
796 kCLOCK_LpspiClkRoot, /*!< LPSPI clock root. */
797 kCLOCK_TraceClkRoot, /*!< Trace clock root. */
798 kCLOCK_Sai1ClkRoot, /*!< SAI1 clock root. */
799 kCLOCK_Sai3ClkRoot, /*!< SAI3 clock root. */
800 kCLOCK_Lpi2cClkRoot, /*!< LPI2C clock root. */
801 kCLOCK_UartClkRoot, /*!< UART clock root. */
802 kCLOCK_SpdifClkRoot, /*!< SPDIF clock root. */
803 kCLOCK_Flexio1ClkRoot, /*!< FLEXIO1 clock root. */
804} clock_root_t;
805
806/*******************************************************************************
807 * API
808 ******************************************************************************/
809
810#if defined(__cplusplus)
811extern "C" {
812#endif /* __cplusplus */
813
814/*!
815 * @brief Set CCM MUX node to certain value.
816 *
817 * @param mux Which mux node to set, see \ref clock_mux_t.
818 * @param value Clock mux value to set, different mux has different value range.
819 */
820static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
821{
822 uint32_t busyShift;
823
824 busyShift = CCM_TUPLE_BUSY_SHIFT(mux);
825 CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
826 (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
827
828 assert(busyShift <= CCM_NO_BUSY_WAIT);
829
830 /* Clock switch need Handshake? */
831 if (CCM_NO_BUSY_WAIT != busyShift)
832 {
833 /* Wait until CCM internal handshake finish. */
834 while ((CCM->CDHIPR & (1UL << busyShift)) != 0UL)
835 {
836 }
837 }
838}
839
840/*!
841 * @brief Get CCM MUX value.
842 *
843 * @param mux Which mux node to get, see \ref clock_mux_t.
844 * @return Clock mux value.
845 */
846static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
847{
848 return (CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux)) >> CCM_TUPLE_SHIFT(mux);
849}
850
851/*!
852 * @brief Set CCM DIV node to certain value.
853 *
854 * @param divider Which div node to set, see \ref clock_div_t.
855 * @param value Clock div value to set, different divider has different value range.
856 */
857static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
858{
859 uint32_t busyShift;
860
861 busyShift = CCM_TUPLE_BUSY_SHIFT((uint32_t)divider);
862 CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
863 (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
864
865 assert(busyShift <= CCM_NO_BUSY_WAIT);
866
867 /* Clock switch need Handshake? */
868 if (CCM_NO_BUSY_WAIT != busyShift)
869 {
870 /* Wait until CCM internal handshake finish. */
871 while ((CCM->CDHIPR & (1UL << busyShift)) != 0UL)
872 {
873 }
874 }
875}
876
877/*!
878 * @brief Get CCM DIV node value.
879 *
880 * @param divider Which div node to get, see \ref clock_div_t.
881 */
882static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
883{
884 return ((CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
885}
886
887/*!
888 * @brief Control the clock gate for specific IP.
889 *
890 * @param name Which clock to enable, see \ref clock_ip_name_t.
891 * @param value Clock gate value to set, see \ref clock_gate_value_t.
892 */
893static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
894{
895 uint32_t index = ((uint32_t)name) >> 8U;
896 uint32_t shift = ((uint32_t)name) & 0x1FU;
897 volatile uint32_t *reg;
898
899 assert(index <= 6UL);
900
901 reg = (volatile uint32_t *)(&(((volatile uint32_t *)&CCM->CCGR0)[index]));
902 *reg = ((*reg) & ~(3UL << shift)) | (((uint32_t)value) << shift);
903}
904
905/*!
906 * @brief Enable the clock for specific IP.
907 *
908 * @param name Which clock to enable, see \ref clock_ip_name_t.
909 */
910static inline void CLOCK_EnableClock(clock_ip_name_t name)
911{
912 CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
913}
914
915/*!
916 * @brief Disable the clock for specific IP.
917 *
918 * @param name Which clock to disable, see \ref clock_ip_name_t.
919 */
920static inline void CLOCK_DisableClock(clock_ip_name_t name)
921{
922 CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
923}
924
925/*!
926 * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal.
927 *
928 * @param mode Which mode to enter, see \ref clock_mode_t.
929 */
930static inline void CLOCK_SetMode(clock_mode_t mode)
931{
932 CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode);
933}
934
935/*!
936 * @brief Gets the OSC clock frequency.
937 *
938 * This function will return the external XTAL OSC frequency if it is selected as the source of OSC,
939 * otherwise internal 24MHz RC OSC frequency will be returned.
940 *
941 * @return Clock frequency; If the clock is invalid, returns 0.
942 */
943static inline uint32_t CLOCK_GetOscFreq(void)
944{
945 return ((XTALOSC24M->LOWPWR_CTRL & (uint32_t)XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
946}
947
948/*!
949 * @brief Gets the CORE clock frequency.
950 *
951 * @return The CORE clock frequency value in hertz.
952 */
953uint32_t CLOCK_GetCoreFreq(void);
954
955/*!
956 * @brief Gets the IPG clock frequency.
957 *
958 * @return The IPG clock frequency value in hertz.
959 */
960uint32_t CLOCK_GetIpgFreq(void);
961
962/*!
963 * @brief Gets the PER clock frequency.
964 *
965 * @return The PER clock frequency value in hertz.
966 */
967uint32_t CLOCK_GetPerClkFreq(void);
968
969/*!
970 * @brief Gets the clock frequency for a specific clock name.
971 *
972 * This function checks the current clock configurations and then calculates
973 * the clock frequency for a specific clock name defined in clock_name_t.
974 *
975 * @param name Clock names defined in clock_name_t
976 * @return Clock frequency value in hertz
977 */
978uint32_t CLOCK_GetFreq(clock_name_t name);
979
980/*!
981 * @brief Get the CCM CPU/core/system frequency.
982 *
983 * @return Clock frequency; If the clock is invalid, returns 0.
984 */
985static inline uint32_t CLOCK_GetCpuClkFreq(void)
986{
987 return CLOCK_GetFreq(kCLOCK_CpuClk);
988}
989
990/*!
991 * @brief Gets the frequency of selected clock root.
992 *
993 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
994 * @return The frequency of selected clock root.
995 */
996uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
997
998/*!
999 * @name OSC operations
1000 * @{
1001 */
1002
1003/*!
1004 * @brief Initialize the external 24MHz clock.
1005 *
1006 * This function supports two modes:
1007 * 1. Use external crystal oscillator.
1008 * 2. Bypass the external crystal oscillator, using input source clock directly.
1009 *
1010 * After this function, please call CLOCK_SetXtal0Freq to inform clock driver
1011 * the external clock frequency.
1012 *
1013 * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
1014 * @note This device does not support bypass external crystal oscillator, so
1015 * the input parameter should always be false.
1016 */
1017void CLOCK_InitExternalClk(bool bypassXtalOsc);
1018
1019/*!
1020 * @brief Deinitialize the external 24MHz clock.
1021 *
1022 * This function disables the external 24MHz clock.
1023 *
1024 * After this function, please call CLOCK_SetXtal0Freq to set external clock
1025 * frequency to 0.
1026 */
1027void CLOCK_DeinitExternalClk(void);
1028
1029/*!
1030 * @brief Switch the OSC.
1031 *
1032 * This function switches the OSC source for SoC.
1033 *
1034 * @param osc OSC source to switch to.
1035 */
1036void CLOCK_SwitchOsc(clock_osc_t osc);
1037
1038/*!
1039 * @brief Gets the RTC clock frequency.
1040 *
1041 * @return Clock frequency; If the clock is invalid, returns 0.
1042 */
1043static inline uint32_t CLOCK_GetRtcFreq(void)
1044{
1045 return 32768U;
1046}
1047
1048/*!
1049 * @brief Set the XTAL (24M OSC) frequency based on board setting.
1050 *
1051 * @param freq The XTAL input clock frequency in Hz.
1052 */
1053static inline void CLOCK_SetXtalFreq(uint32_t freq)
1054{
1055 g_xtalFreq = freq;
1056}
1057
1058/*!
1059 * @brief Set the RTC XTAL (32K OSC) frequency based on board setting.
1060 *
1061 * @param freq The RTC XTAL input clock frequency in Hz.
1062 */
1063static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
1064{
1065 g_rtcXtalFreq = freq;
1066}
1067
1068/*!
1069 * @brief Initialize the RC oscillator 24MHz clock.
1070 */
1071void CLOCK_InitRcOsc24M(void);
1072
1073/*!
1074 * @brief Power down the RCOSC 24M clock.
1075 */
1076void CLOCK_DeinitRcOsc24M(void);
1077/* @} */
1078
1079/*! @brief Enable USB HS clock.
1080 *
1081 * This function only enables the access to USB HS prepheral, upper layer
1082 * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1083 * clock to use USB HS.
1084 *
1085 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1086 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1087 * @retval true The clock is set successfully.
1088 * @retval false The clock source is invalid to get proper USB HS clock.
1089 */
1090bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
1091
1092/* @} */
1093
1094/*!
1095 * @name PLL/PFD operations
1096 * @{
1097 */
1098/*!
1099 * @brief PLL bypass setting
1100 *
1101 * @param base CCM_ANALOG base pointer.
1102 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1103 * @param bypass Bypass the PLL.
1104 * - true: Bypass the PLL.
1105 * - false:Not bypass the PLL.
1106 */
1107static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
1108{
1109 if (bypass)
1110 {
1111 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1112 }
1113 else
1114 {
1115 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1116 }
1117}
1118
1119/*!
1120 * @brief Check if PLL is bypassed
1121 *
1122 * @param base CCM_ANALOG base pointer.
1123 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1124 * @return PLL bypass status.
1125 * - true: The PLL is bypassed.
1126 * - false: The PLL is not bypassed.
1127 */
1128static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
1129{
1130 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
1131}
1132
1133/*!
1134 * @brief Check if PLL is enabled
1135 *
1136 * @param base CCM_ANALOG base pointer.
1137 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1138 * @return PLL bypass status.
1139 * - true: The PLL is enabled.
1140 * - false: The PLL is not enabled.
1141 */
1142static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
1143{
1144 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll)));
1145}
1146
1147/*!
1148 * @brief PLL bypass clock source setting.
1149 * Note: change the bypass clock source also change the pll reference clock source.
1150 *
1151 * @param base CCM_ANALOG base pointer.
1152 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1153 * @param src Bypass clock source, reference _clock_pll_bypass_clk_src.
1154 */
1155static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
1156{
1157 CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src;
1158}
1159
1160/*!
1161 * @brief Get PLL bypass clock value, it is PLL reference clock actually.
1162 * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0
1163 * will be returned.
1164 * @param base CCM_ANALOG base pointer.
1165 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1166 * @retval bypass reference clock frequency value.
1167 */
1168static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
1169{
1170 return ((((uint32_t)(CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) >>
1171 CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
1172 CLOCK_GetOscFreq() :
1173 CLKPN_FREQ;
1174}
1175
1176/*!
1177 * @brief Initialize the System PLL.
1178 *
1179 * This function initializes the System PLL with specific settings
1180 *
1181 * @param config Configuration to set to PLL.
1182 */
1183void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1184
1185/*!
1186 * @brief De-initialize the System PLL.
1187 */
1188void CLOCK_DeinitSysPll(void);
1189
1190/*!
1191 * @brief Initialize the USB1 PLL.
1192 *
1193 * This function initializes the USB1 PLL with specific settings
1194 *
1195 * @param config Configuration to set to PLL.
1196 */
1197void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config);
1198
1199/*!
1200 * @brief Deinitialize the USB1 PLL.
1201 */
1202void CLOCK_DeinitUsb1Pll(void);
1203
1204/*!
1205 * @brief Initializes the Audio PLL.
1206 *
1207 * This function initializes the Audio PLL with specific settings
1208 *
1209 * @param config Configuration to set to PLL.
1210 */
1211void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1212
1213/*!
1214 * @brief De-initialize the Audio PLL.
1215 */
1216void CLOCK_DeinitAudioPll(void);
1217
1218/*!
1219 * @brief Initialize the ENET PLL.
1220 *
1221 * This function initializes the ENET PLL with specific settings.
1222 *
1223 * @param config Configuration to set to PLL.
1224 */
1225void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config);
1226
1227/*!
1228 * @brief Deinitialize the ENET PLL.
1229 *
1230 * This function disables the ENET PLL.
1231 */
1232void CLOCK_DeinitEnetPll(void);
1233
1234/*!
1235 * @brief Get current PLL output frequency.
1236 *
1237 * This function get current output frequency of specific PLL
1238 *
1239 * @param pll pll name to get frequency.
1240 * @return The PLL output frequency in hertz.
1241 */
1242uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
1243
1244/*!
1245 * @brief Initialize the System PLL PFD.
1246 *
1247 * This function initializes the System PLL PFD. During new value setting,
1248 * the clock output is disabled to prevent glitch.
1249 *
1250 * @param pfd Which PFD clock to enable.
1251 * @param pfdFrac The PFD FRAC value.
1252 * @note It is recommended that PFD settings are kept between 12-35.
1253 */
1254void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
1255
1256/*!
1257 * @brief De-initialize the System PLL PFD.
1258 *
1259 * This function disables the System PLL PFD.
1260 *
1261 * @param pfd Which PFD clock to disable.
1262 */
1263void CLOCK_DeinitSysPfd(clock_pfd_t pfd);
1264
1265/*!
1266 * @brief Initialize the USB1 PLL PFD.
1267 *
1268 * This function initializes the USB1 PLL PFD. During new value setting,
1269 * the clock output is disabled to prevent glitch.
1270 *
1271 * @param pfd Which PFD clock to enable.
1272 * @param pfdFrac The PFD FRAC value.
1273 * @note It is recommended that PFD settings are kept between 12-35.
1274 */
1275void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
1276
1277/*!
1278 * @brief De-initialize the USB1 PLL PFD.
1279 *
1280 * This function disables the USB1 PLL PFD.
1281 *
1282 * @param pfd Which PFD clock to disable.
1283 */
1284void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd);
1285
1286/*!
1287 * @brief Get current System PLL PFD output frequency.
1288 *
1289 * This function get current output frequency of specific System PLL PFD
1290 *
1291 * @param pfd pfd name to get frequency.
1292 * @return The PFD output frequency in hertz.
1293 */
1294uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
1295
1296/*!
1297 * @brief Get current USB1 PLL PFD output frequency.
1298 *
1299 * This function get current output frequency of specific USB1 PLL PFD
1300 *
1301 * @param pfd pfd name to get frequency.
1302 * @return The PFD output frequency in hertz.
1303 */
1304uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
1305
1306/*! @brief Enable USB HS PHY PLL clock.
1307 *
1308 * This function enables the internal 480MHz USB PHY PLL clock.
1309 *
1310 * @param src USB HS PHY PLL clock source.
1311 * @param freq The frequency specified by src.
1312 * @retval true The clock is set successfully.
1313 * @retval false The clock source is invalid to get proper USB HS clock.
1314 */
1315bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1316
1317/*! @brief Disable USB HS PHY PLL clock.
1318 *
1319 * This function disables USB HS PHY PLL clock.
1320 */
1321void CLOCK_DisableUsbhs0PhyPllClock(void);
1322
1323/* @} */
1324
1325/*!
1326 * @name Clock Output Inferfaces
1327 * @{
1328 */
1329
1330/*!
1331 * @brief Set the clock source and the divider of the clock output1.
1332 *
1333 * @param selection The clock source to be output, please refer to @ref clock_output1_selection_t.
1334 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1335 */
1336void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider);
1337
1338/*!
1339 * @brief Set the clock source and the divider of the clock output2.
1340 *
1341 * @param selection The clock source to be output, please refer to @ref clock_output2_selection_t.
1342 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1343 */
1344void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider);
1345
1346/*!
1347 * @brief Get the frequency of clock output1 clock signal.
1348 *
1349 * @return The frequency of clock output1 clock signal.
1350 */
1351uint32_t CLOCK_GetClockOutCLKO1Freq(void);
1352
1353/*!
1354 * @brief Get the frequency of clock output2 clock signal.
1355 *
1356 * @return The frequency of clock output2 clock signal.
1357 */
1358uint32_t CLOCK_GetClockOutClkO2Freq(void);
1359
1360/*! @} */
1361
1362#if defined(__cplusplus)
1363}
1364#endif /* __cplusplus */
1365
1366/*! @} */
1367
1368#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 22:57:35 +0100