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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1011/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1011/project_template/board.c
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1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "board.h"
11#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12#include "fsl_lpi2c.h"
13#endif /* SDK_I2C_BASED_COMPONENT_USED */
14#include "fsl_iomuxc.h"
15
16/*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20/*******************************************************************************
21 * Code
22 ******************************************************************************/
23
24/* Get debug console frequency. */
25uint32_t BOARD_DebugConsoleSrcFreq(void)
26{
27 uint32_t freq;
28
29 /* To make it simple, we assume default PLL and divider settings, and the only variable
30 from application is use PLL3 source or OSC source */
31 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
32 {
33 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
34 }
35 else
36 {
37 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
38 }
39
40 return freq;
41}
42
43/* Initialize debug console. */
44void BOARD_InitDebugConsole(void)
45{
46 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
47
48 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
49}
50
51/* MPU configuration. */
52void BOARD_ConfigMPU(void)
53{
54#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
55 extern uint32_t Image$$RW_m_ncache$$Base[];
56 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
57 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
58 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
59 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
60 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
61 0 :
62 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
63#elif defined(__MCUXPRESSO)
64 extern uint32_t __base_NCACHE_REGION;
65 extern uint32_t __top_NCACHE_REGION;
66 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
67 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
68#elif defined(__ICCARM__) || defined(__GNUC__)
69 extern uint32_t __NCACHE_REGION_START[];
70 extern uint32_t __NCACHE_REGION_SIZE[];
71 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
72 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
73#endif
74 uint32_t i = 0;
75
76 /* Disable I cache and D cache */
77 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
78 {
79 SCB_DisableICache();
80 }
81 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
82 {
83 SCB_DisableDCache();
84 }
85
86 /* Disable MPU */
87 ARM_MPU_Disable();
88
89 /* MPU configure:
90 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
91 * SubRegionDisable, Size)
92 * API in mpu_armv7.h.
93 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
94 * disabled.
95 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
96 * Privileged mode.
97 * Use MACROS defined in mpu_armv7.h:
98 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
99 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
100 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
101 * 0 x 0 0 Strongly Ordered shareable
102 * 0 x 0 1 Device shareable
103 * 0 0 1 0 Normal not shareable Outer and inner write
104 * through no write allocate
105 * 0 0 1 1 Normal not shareable Outer and inner write
106 * back no write allocate
107 * 0 1 1 0 Normal shareable Outer and inner write
108 * through no write allocate
109 * 0 1 1 1 Normal shareable Outer and inner write
110 * back no write allocate
111 * 1 0 0 0 Normal not shareable outer and inner
112 * noncache
113 * 1 1 0 0 Normal shareable outer and inner
114 * noncache
115 * 1 0 1 1 Normal not shareable outer and inner write
116 * back write/read acllocate
117 * 1 1 1 1 Normal shareable outer and inner write
118 * back write/read acllocate
119 * 2 x 0 0 Device not shareable
120 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
121 * policy.
122 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
123 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
124 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
125 * mpu_armv7.h.
126 */
127
128 /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
129 MPU->RBAR = ARM_MPU_RBAR(0, 0x80000000U);
130 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
131
132 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
133 MPU->RBAR = ARM_MPU_RBAR(1, 0x60000000U);
134 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
135
136#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
137 /* Region 2 setting: Memory with Normal type, not shareable, outer/inner write back. */
138 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
139 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
140#endif
141
142 /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
143 MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
144 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
145
146 /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
147 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
148 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);
149
150 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
151 MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
152 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);
153
154 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
155 MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
156 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
157
158 while ((size >> i) > 0x1U)
159 {
160 i++;
161 }
162
163 if (i != 0)
164 {
165 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
166 assert(!(nonCacheStart % size));
167 assert(size == (uint32_t)(1 << i));
168 assert(i >= 5);
169
170 /* Region 7 setting: Memory with Normal type, not shareable, non-cacheable */
171 MPU->RBAR = ARM_MPU_RBAR(7, nonCacheStart);
172 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
173 }
174
175 /* Enable MPU */
176 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
177
178 /* Enable I cache and D cache */
179 SCB_EnableDCache();
180 SCB_EnableICache();
181}
182
183#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
184void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
185{
186 lpi2c_master_config_t lpi2cConfig = {0};
187
188 /*
189 * lpi2cConfig.debugEnable = false;
190 * lpi2cConfig.ignoreAck = false;
191 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
192 * lpi2cConfig.baudRate_Hz = 100000U;
193 * lpi2cConfig.busIdleTimeout_ns = 0;
194 * lpi2cConfig.pinLowTimeout_ns = 0;
195 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
196 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
197 */
198 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
199 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
200}
201
202status_t BOARD_LPI2C_Send(LPI2C_Type *base,
203 uint8_t deviceAddress,
204 uint32_t subAddress,
205 uint8_t subAddressSize,
206 uint8_t *txBuff,
207 uint8_t txBuffSize)
208{
209 lpi2c_master_transfer_t xfer;
210
211 xfer.flags = kLPI2C_TransferDefaultFlag;
212 xfer.slaveAddress = deviceAddress;
213 xfer.direction = kLPI2C_Write;
214 xfer.subaddress = subAddress;
215 xfer.subaddressSize = subAddressSize;
216 xfer.data = txBuff;
217 xfer.dataSize = txBuffSize;
218
219 return LPI2C_MasterTransferBlocking(base, &xfer);
220}
221
222status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
223 uint8_t deviceAddress,
224 uint32_t subAddress,
225 uint8_t subAddressSize,
226 uint8_t *rxBuff,
227 uint8_t rxBuffSize)
228{
229 lpi2c_master_transfer_t xfer;
230
231 xfer.flags = kLPI2C_TransferDefaultFlag;
232 xfer.slaveAddress = deviceAddress;
233 xfer.direction = kLPI2C_Read;
234 xfer.subaddress = subAddress;
235 xfer.subaddressSize = subAddressSize;
236 xfer.data = rxBuff;
237 xfer.dataSize = rxBuffSize;
238
239 return LPI2C_MasterTransferBlocking(base, &xfer);
240}
241
242void BOARD_Accel_I2C_Init(void)
243{
244 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
245}
246
247status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
248{
249 uint8_t data = (uint8_t)txBuff;
250
251 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
252}
253
254status_t BOARD_Accel_I2C_Receive(
255 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
256{
257 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
258}
259
260void BOARD_Codec_I2C_Init(void)
261{
262 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
263}
264
265status_t BOARD_Codec_I2C_Send(
266 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
267{
268 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
269 txBuffSize);
270}
271
272status_t BOARD_Codec_I2C_Receive(
273 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
274{
275 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
276}
277#endif /*SDK_I2C_BASED_COMPONENT_USED */
278
279#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
280/* SystemInitHook */
281void SystemInitHook(void)
282{
283 /* When set this bit, FlexSPI will fetch more data than AHB burst required to meet the alignment requirement. */
284 FLEXSPI->AHBCR |= FLEXSPI_AHBCR_READADDROPT_MASK;
285}
286#endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 08:21:48 +0100