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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1011/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1011/project_template/clock_config.c
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+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1011/project_template/clock_config.c
@@ -0,0 +1,345 @@
1/*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v6.0
26processor: MIMXRT1011xxxxx
27package_id: MIMXRT1011DAE5A
28mcu_data: ksdk2_0
29processor_version: 0.0.1
30board: MIMXRT1010-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: ADC_ALT_CLK.outFreq, value: 40 MHz}
63- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
64- {id: CLK_1M.outFreq, value: 1 MHz}
65- {id: CLK_24M.outFreq, value: 24 MHz}
66- {id: CORE_CLK_ROOT.outFreq, value: 500 MHz}
67- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
68- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
69- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
70- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
71- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
72- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
73- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
74- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
75- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
76- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
77- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
78- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
79- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
80- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
81- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
82- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
83- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
84- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
85- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
86- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
87settings:
88- {id: CCM.ADC_ACLK_PODF.scale, value: '12', locked: true}
89- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
90- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
91- {id: CCM.IPG_PODF.scale, value: '4'}
92- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
93- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
94- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM_ANALOG.ENET_500M_REF_CLK}
95- {id: CCM.SAI1_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
96- {id: CCM.SAI3_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD2_CLK}
97- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
98- {id: CCM_ANALOG.PLL2.denom, value: '1'}
99- {id: CCM_ANALOG.PLL2.div, value: '22'}
100- {id: CCM_ANALOG.PLL2.num, value: '0'}
101- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
102- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
103- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
104- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
105- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
106- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
107- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
108- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
109- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
110- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
111- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
112- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
113- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
114- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
115- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
116- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
117- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
118- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
119- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
120- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
121sources:
122- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
123- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
124 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
125
126/*******************************************************************************
127 * Variables for BOARD_BootClockRUN configuration
128 ******************************************************************************/
129const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
130 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
131 .numerator = 0, /* 30 bit numerator of fractional loop divider */
132 .denominator = 1, /* 30 bit denominator of fractional loop divider */
133 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
134};
135const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
136 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
137 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
138};
139const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = {
140 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
141 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
142};
143/*******************************************************************************
144 * Code for BOARD_BootClockRUN configuration
145 ******************************************************************************/
146void BOARD_BootClockRUN(void)
147{
148 /* Init RTC OSC clock frequency. */
149 CLOCK_SetRtcXtalFreq(32768U);
150 /* Enable 1MHz clock output. */
151 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
152 /* Use free 1MHz clock output. */
153 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
154 /* Set XTAL 24MHz clock frequency. */
155 CLOCK_SetXtalFreq(24000000U);
156 /* Enable XTAL 24MHz clock source. */
157 CLOCK_InitExternalClk(0);
158 /* Enable internal RC. */
159 CLOCK_InitRcOsc24M();
160 /* Switch clock source to external OSC. */
161 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
162 /* Set Oscillator ready counter value. */
163 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
164 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
165 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
166 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
167 /* Setting the VDD_SOC to 1.5V. It is necessary to config CORE to 500Mhz. */
168 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
169 /* Waiting for DCDC_STS_DC_OK bit is asserted */
170 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
171 {
172 }
173 /* Set AHB_PODF. */
174 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
175 /* Disable IPG clock gate. */
176 CLOCK_DisableClock(kCLOCK_Adc1);
177 CLOCK_DisableClock(kCLOCK_Xbar1);
178 /* Set IPG_PODF. */
179 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
180 /* Disable PERCLK clock gate. */
181 CLOCK_DisableClock(kCLOCK_Gpt1);
182 CLOCK_DisableClock(kCLOCK_Gpt1S);
183 CLOCK_DisableClock(kCLOCK_Gpt2);
184 CLOCK_DisableClock(kCLOCK_Gpt2S);
185 CLOCK_DisableClock(kCLOCK_Pit);
186 /* Set PERCLK_PODF. */
187 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
188 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
189 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
190 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
191 * well.*/
192#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
193 /* Disable Flexspi clock gate. */
194 CLOCK_DisableClock(kCLOCK_FlexSpi);
195 /* Set FLEXSPI_PODF. */
196 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
197 /* Set Flexspi clock source. */
198 CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
199 CLOCK_SetMux(kCLOCK_FlexspiSrcMux, 0);
200#endif
201 /* Disable ADC_ACLK_EN clock gate. */
202 CCM->CSCMR2 &= ~CCM_CSCMR2_ADC_ACLK_EN_MASK;
203 /* Set ADC_ACLK_PODF. */
204 CLOCK_SetDiv(kCLOCK_AdcDiv, 11);
205 /* Disable LPSPI clock gate. */
206 CLOCK_DisableClock(kCLOCK_Lpspi1);
207 CLOCK_DisableClock(kCLOCK_Lpspi2);
208 /* Set LPSPI_PODF. */
209 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
210 /* Set Lpspi clock source. */
211 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
212 /* Disable TRACE clock gate. */
213 CLOCK_DisableClock(kCLOCK_Trace);
214 /* Set TRACE_PODF. */
215 CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
216 /* Set Trace clock source. */
217 CLOCK_SetMux(kCLOCK_TraceMux, 2);
218 /* Disable SAI1 clock gate. */
219 CLOCK_DisableClock(kCLOCK_Sai1);
220 /* Set SAI1_CLK_PRED. */
221 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
222 /* Set SAI1_CLK_PODF. */
223 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
224 /* Set Sai1 clock source. */
225 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
226 /* Disable SAI3 clock gate. */
227 CLOCK_DisableClock(kCLOCK_Sai3);
228 /* Set SAI3_CLK_PRED. */
229 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
230 /* Set SAI3_CLK_PODF. */
231 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
232 /* Set Sai3 clock source. */
233 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
234 /* Disable Lpi2c clock gate. */
235 CLOCK_DisableClock(kCLOCK_Lpi2c1);
236 CLOCK_DisableClock(kCLOCK_Lpi2c2);
237 /* Set LPI2C_CLK_PODF. */
238 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
239 /* Set Lpi2c clock source. */
240 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
241 /* Disable UART clock gate. */
242 CLOCK_DisableClock(kCLOCK_Lpuart1);
243 CLOCK_DisableClock(kCLOCK_Lpuart2);
244 CLOCK_DisableClock(kCLOCK_Lpuart3);
245 CLOCK_DisableClock(kCLOCK_Lpuart4);
246 /* Set UART_CLK_PODF. */
247 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
248 /* Set Uart clock source. */
249 CLOCK_SetMux(kCLOCK_UartMux, 0);
250 /* Disable SPDIF clock gate. */
251 CLOCK_DisableClock(kCLOCK_Spdif);
252 /* Set SPDIF0_CLK_PRED. */
253 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
254 /* Set SPDIF0_CLK_PODF. */
255 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
256 /* Set Spdif clock source. */
257 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
258 /* Disable Flexio1 clock gate. */
259 CLOCK_DisableClock(kCLOCK_Flexio1);
260 /* Set FLEXIO1_CLK_PRED. */
261 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
262 /* Set FLEXIO1_CLK_PODF. */
263 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
264 /* Set Flexio1 clock source. */
265 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
266 /* Set Pll3 sw clock source. */
267 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
268 /* Init System PLL. */
269 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
270 /* Init System pfd0. */
271 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
272 /* Init System pfd1. */
273 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
274 /* Init System pfd2. */
275 CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
276 /* Init System pfd3. */
277 CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
278 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
279 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
280 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
281 * well.*/
282#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
283 /* Init Usb1 PLL. */
284 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
285 /* Init Usb1 pfd0. */
286 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
287 /* Init Usb1 pfd1. */
288 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
289 /* Init Usb1 pfd2. */
290 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
291 /* Init Usb1 pfd3. */
292 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
293 /* Disable Usb1 PLL output for USBPHY1. */
294 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
295#endif
296 /* DeInit Audio PLL. */
297 CLOCK_DeinitAudioPll();
298 /* Bypass Audio PLL. */
299 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
300 /* Set divider for Audio PLL. */
301 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
302 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
303 /* Enable Audio PLL output. */
304 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
305 /* Init Enet PLL. */
306 CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
307 /* Set preperiph clock source. */
308 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
309 /* Set periph clock source. */
310 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
311 /* Set periph clock2 clock source. */
312 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
313 /* Set per clock source. */
314 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
315 /* Set clock out1 divider. */
316 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
317 /* Set clock out1 source. */
318 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
319 /* Set clock out2 divider. */
320 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
321 /* Set clock out2 source. */
322 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
323 /* Set clock out1 drives clock out1. */
324 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
325 /* Disable clock out1. */
326 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
327 /* Disable clock out2. */
328 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
329 /* Set SAI1 MCLK1 clock source. */
330 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
331 /* Set SAI1 MCLK2 clock source. */
332 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
333 /* Set SAI1 MCLK3 clock source. */
334 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
335 /* Set SAI3 MCLK3 clock source. */
336 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
337 /* Set MQS configuration. */
338 IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
339 /* Set GPT1 High frequency reference clock source. */
340 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
341 /* Set GPT2 High frequency reference clock source. */
342 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
343 /* Set SystemCoreClock variable. */
344 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
345}
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