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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/MIMXRT1015.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/MIMXRT1015.h
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1/*
2** ###################################################################
3** Processors: MIMXRT1015CAF4A
4** MIMXRT1015DAF5A
5**
6** Compilers: Freescale C/C++ for Embedded ARM
7** GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10** MCUXpresso Compiler
11**
12** Reference manual: IMXRT1015RM Rev.0, 12/2018 | IMXRT1015SRM Rev.3
13** Version: rev. 1.2, 2019-04-29
14** Build: b201019
15**
16** Abstract:
17** CMSIS Peripheral Access Layer for MIMXRT1015
18**
19** Copyright 1997-2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2020 NXP
21** All rights reserved.
22**
23** SPDX-License-Identifier: BSD-3-Clause
24**
25** http: www.nxp.com
26** mail: [email protected]
27**
28** Revisions:
29** - rev. 0.1 (2018-11-05)
30** Initial version.
31** - rev. 1.0 (2019-01-18)
32** Rev.0 Header GA
33** - rev. 1.1 (2019-02-20)
34** Update register SRC_SRSR's bitfield LOCKUP_SYSRESETREQ to LOCKUP.
35** - rev. 1.2 (2019-04-29)
36** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
37**
38** ###################################################################
39*/
40
41/*!
42 * @file MIMXRT1015.h
43 * @version 1.2
44 * @date 2019-04-29
45 * @brief CMSIS Peripheral Access Layer for MIMXRT1015
46 *
47 * CMSIS Peripheral Access Layer for MIMXRT1015
48 */
49
50#ifndef _MIMXRT1015_H_
51#define _MIMXRT1015_H_ /**< Symbol preventing repeated inclusion */
52
53/** Memory map major version (memory maps with equal major version number are
54 * compatible) */
55#define MCU_MEM_MAP_VERSION 0x0100U
56/** Memory map minor version */
57#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
58
59
60/* ----------------------------------------------------------------------------
61 -- Interrupt vector numbers
62 ---------------------------------------------------------------------------- */
63
64/*!
65 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
66 * @{
67 */
68
69/** Interrupt Number Definitions */
70#define NUMBER_OF_INT_VECTORS 150 /**< Number of interrupts in the Vector table */
71
72typedef enum IRQn {
73 /* Auxiliary constants */
74 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
75
76 /* Core interrupts */
77 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
78 HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */
79 MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */
80 BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */
81 UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */
82 SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */
83 DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */
84 PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */
85 SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */
86
87 /* Device specific interrupts */
88 DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */
89 DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */
90 DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */
91 DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */
92 DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */
93 DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */
94 DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */
95 DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */
96 DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */
97 DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */
98 DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */
99 DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */
100 DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */
101 DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */
102 DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */
103 DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */
104 DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */
105 CTI0_ERROR_IRQn = 17, /**< CTI trigger outputs */
106 CTI1_ERROR_IRQn = 18, /**< CTI trigger outputs */
107 CORE_IRQn = 19, /**< CorePlatform exception IRQ */
108 LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */
109 LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */
110 LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */
111 LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */
112 Reserved40_IRQn = 24, /**< Reserved interrupt */
113 Reserved41_IRQn = 25, /**< Reserved interrupt */
114 Reserved42_IRQn = 26, /**< Reserved interrupt */
115 Reserved43_IRQn = 27, /**< Reserved interrupt */
116 LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */
117 LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */
118 Reserved46_IRQn = 30, /**< Reserved interrupt */
119 Reserved47_IRQn = 31, /**< Reserved interrupt */
120 LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */
121 LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */
122 Reserved50_IRQn = 34, /**< Reserved interrupt */
123 Reserved51_IRQn = 35, /**< Reserved interrupt */
124 Reserved52_IRQn = 36, /**< Reserved interrupt */
125 Reserved53_IRQn = 37, /**< Reserved interrupt */
126 FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */
127 KPP_IRQn = 39, /**< Keypad nterrupt */
128 Reserved56_IRQn = 40, /**< Reserved interrupt */
129 GPR_IRQ_IRQn = 41, /**< Used to notify cores on exception condition while boot */
130 Reserved58_IRQn = 42, /**< Reserved interrupt */
131 Reserved59_IRQn = 43, /**< Reserved interrupt */
132 Reserved60_IRQn = 44, /**< Reserved interrupt */
133 WDOG2_IRQn = 45, /**< WDOG2 interrupt */
134 SNVS_HP_WRAPPER_IRQn = 46, /**< SNVS Functional Interrupt */
135 SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SNVS Security Interrupt */
136 SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */
137 CSU_IRQn = 49, /**< CSU interrupt */
138 DCP_IRQn = 50, /**< Combined DCP channel interrupts(except channel 0) and CRC interrupt */
139 DCP_VMI_IRQn = 51, /**< IRQ of DCP channel 0 */
140 Reserved68_IRQn = 52, /**< Reserved interrupt */
141 TRNG_IRQn = 53, /**< TRNG interrupt */
142 Reserved70_IRQn = 54, /**< Reserved interrupt */
143 BEE_IRQn = 55, /**< BEE interrupt */
144 SAI1_IRQn = 56, /**< SAI1 interrupt */
145 SAI2_IRQn = 57, /**< SAI1 interrupt */
146 SAI3_RX_IRQn = 58, /**< SAI3 interrupt */
147 SAI3_TX_IRQn = 59, /**< SAI3 interrupt */
148 SPDIF_IRQn = 60, /**< SPDIF interrupt */
149 PMU_IRQn = 61, /**< PMU interrupt */
150 Reserved78_IRQn = 62, /**< Reserved interrupt */
151 TEMP_LOW_HIGH_IRQn = 63, /**< TEMPMON interrupt */
152 TEMP_PANIC_IRQn = 64, /**< TEMPMON interrupt */
153 USB_PHY_IRQn = 65, /**< USBPHY (OTG1 UTMI), Interrupt */
154 Reserved82_IRQn = 66, /**< Reserved interrupt */
155 ADC1_IRQn = 67, /**< ADC1 interrupt */
156 Reserved84_IRQn = 68, /**< Reserved interrupt */
157 DCDC_IRQn = 69, /**< DCDC interrupt */
158 Reserved86_IRQn = 70, /**< Reserved interrupt */
159 Reserved87_IRQn = 71, /**< Reserved interrupt */
160 GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */
161 GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */
162 GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */
163 GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */
164 GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */
165 GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */
166 GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */
167 GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */
168 GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
169 GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
170 GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
171 GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
172 GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
173 GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
174 Reserved102_IRQn = 86, /**< Reserved interrupt */
175 Reserved103_IRQn = 87, /**< Reserved interrupt */
176 GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
177 GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
178 FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */
179 Reserved107_IRQn = 91, /**< Reserved interrupt */
180 WDOG1_IRQn = 92, /**< WDOG1 interrupt */
181 RTWDOG_IRQn = 93, /**< RTWDOG interrupt */
182 EWM_IRQn = 94, /**< EWM interrupt */
183 CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */
184 CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */
185 GPC_IRQn = 97, /**< GPC interrupt */
186 SRC_IRQn = 98, /**< SRC interrupt */
187 Reserved115_IRQn = 99, /**< Reserved interrupt */
188 GPT1_IRQn = 100, /**< GPT1 interrupt */
189 GPT2_IRQn = 101, /**< GPT2 interrupt */
190 PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
191 PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */
192 PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */
193 PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */
194 PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */
195 Reserved123_IRQn = 107, /**< Reserved interrupt */
196 FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */
197 Reserved125_IRQn = 109, /**< Reserved interrupt */
198 Reserved126_IRQn = 110, /**< Reserved interrupt */
199 Reserved127_IRQn = 111, /**< Reserved interrupt */
200 Reserved128_IRQn = 112, /**< Reserved interrupt */
201 USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */
202 Reserved130_IRQn = 114, /**< Reserved interrupt */
203 Reserved131_IRQn = 115, /**< Reserved interrupt */
204 XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */
205 XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */
206 ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */
207 ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */
208 ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */
209 ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */
210 PIT_IRQn = 122, /**< PIT interrupt */
211 Reserved139_IRQn = 123, /**< Reserved interrupt */
212 Reserved140_IRQn = 124, /**< Reserved interrupt */
213 Reserved141_IRQn = 125, /**< Reserved interrupt */
214 Reserved142_IRQn = 126, /**< Reserved interrupt */
215 Reserved143_IRQn = 127, /**< Reserved interrupt */
216 Reserved144_IRQn = 128, /**< Reserved interrupt */
217 ENC1_IRQn = 129, /**< ENC1 interrupt */
218 Reserved146_IRQn = 130, /**< Reserved interrupt */
219 Reserved147_IRQn = 131, /**< Reserved interrupt */
220 Reserved148_IRQn = 132, /**< Reserved interrupt */
221 TMR1_IRQn = 133 /**< TMR1 interrupt */
222} IRQn_Type;
223
224/*!
225 * @}
226 */ /* end of group Interrupt_vector_numbers */
227
228
229/* ----------------------------------------------------------------------------
230 -- Cortex M7 Core Configuration
231 ---------------------------------------------------------------------------- */
232
233/*!
234 * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
235 * @{
236 */
237
238#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
239#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */
240#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */
241#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */
242#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
243#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
244#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
245
246#include "core_cm7.h" /* Core Peripheral Access Layer */
247#include "system_MIMXRT1015.h" /* Device specific configuration file */
248
249/*!
250 * @}
251 */ /* end of group Cortex_Core_Configuration */
252
253
254/* ----------------------------------------------------------------------------
255 -- Mapping Information
256 ---------------------------------------------------------------------------- */
257
258/*!
259 * @addtogroup Mapping_Information Mapping Information
260 * @{
261 */
262
263/** Mapping Information */
264/*!
265 * @addtogroup edma_request
266 * @{
267 */
268
269/*******************************************************************************
270 * Definitions
271 ******************************************************************************/
272
273/*!
274 * @brief Structure for the DMA hardware request
275 *
276 * Defines the structure for the DMA hardware request collections. The user can configure the
277 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
278 * of the hardware request varies according to the to SoC.
279 */
280typedef enum _dma_request_source
281{
282 kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */
283 kDmaRequestMuxFlexIO1Request4Request5 = 1|0x100U, /**< FlexIO1 Request4 and Request5 */
284 kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */
285 kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */
286 kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */
287 kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */
288 kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */
289 kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */
290 kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */
291 kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */
292 kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */
293 kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */
294 kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */
295 kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */
296 kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */
297 kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FLEXSPI Receive */
298 kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FLEXSPI Transmit */
299 kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR Request 0 */
300 kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR Request 1 */
301 kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */
302 kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */
303 kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */
304 kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */
305 kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */
306 kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */
307 kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */
308 kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */
309 kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< QTIMER1 Capture timer 0 */
310 kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< QTIMER1 Capture timer 1 */
311 kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< QTIMER1 Capture timer 2 */
312 kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< QTIMER1 Capture timer 3 */
313 kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< QTIMER1 cmpld1 in timer 0 or cmpld2 in timer 1 */
314 kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< QTIMER1 cmpld1 in timer 1 or cmpld2 in timer 0 */
315 kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< QTIMER1 cmpld1 in timer 2 or cmpld2 in timer 3 */
316 kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< QTIMER1 cmpld1 in timer 3 or cmpld2 in timer 2 */
317 kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */
318 kDmaRequestMuxFlexIO1Request6Request7 = 65|0x100U, /**< FlexIO1 Request6 and Request7 */
319 kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */
320 kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */
321 kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */
322 kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */
323 kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */
324 kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */
325 kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */
326 kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */
327 kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */
328 kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */
329 kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */
330 kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR Request 2 */
331 kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR Request 3 */
332} dma_request_source_t;
333
334/* @} */
335
336/*!
337 * @addtogroup iomuxc_pads
338 * @{ */
339
340/*******************************************************************************
341 * Definitions
342*******************************************************************************/
343
344/*!
345 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
346 *
347 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
348 */
349typedef enum _iomuxc_sw_mux_ctl_pad
350{
351 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
352 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
353 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
354 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
355 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
356 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
357 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
358 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
359 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
360 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
361 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
362 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
363 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
364 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
365 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
366 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
367 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
368 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
369 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
370 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
371 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
372 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
373 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
374 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
375 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
376 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
377 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
378 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
379 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
380 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
381 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
382 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
383 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
384 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
385 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
386 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
387 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
388 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
389 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
390 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
391 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
392 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
393 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
394 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
395 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
396 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
397 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */
398 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */
399 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */
400 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */
401 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */
402 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */
403 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */
404 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */
405 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */
406 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */
407} iomuxc_sw_mux_ctl_pad_t;
408
409/* @} */
410
411/*!
412 * @addtogroup iomuxc_pads
413 * @{ */
414
415/*******************************************************************************
416 * Definitions
417*******************************************************************************/
418
419/*!
420 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
421 *
422 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
423 */
424typedef enum _iomuxc_sw_pad_ctl_pad
425{
426 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
427 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
428 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
429 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
430 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
431 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
432 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
433 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
434 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
435 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
436 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
437 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
438 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
439 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
440 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
441 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
442 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
443 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
444 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
445 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
446 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
447 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
448 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
449 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
450 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
451 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
452 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
453 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
454 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
455 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
456 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
457 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
458 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
459 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
460 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
461 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
462 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
463 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
464 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
465 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
466 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
467 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
468 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
469 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
470 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
471 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
472 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
473 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
474 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
475 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
476 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
477 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
478 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
479 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
480 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
481 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
482} iomuxc_sw_pad_ctl_pad_t;
483
484/* @} */
485
486/*!
487 * @brief Enumeration for the IOMUXC select input
488 *
489 * Defines the enumeration for the IOMUXC select input collections.
490 */
491typedef enum _iomuxc_select_input
492{
493 kIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */
494 kIOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT = 1U, /**< IOMUXC select input index */
495 kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_0 = 11U, /**< IOMUXC select input index */
496 kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_1 = 12U, /**< IOMUXC select input index */
497 kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_2 = 13U, /**< IOMUXC select input index */
498 kIOMUXC_FLEXPWM1_IPP_IND_PWMA_SELECT_INPUT_3 = 14U, /**< IOMUXC select input index */
499 kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_0 = 15U, /**< IOMUXC select input index */
500 kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_1 = 16U, /**< IOMUXC select input index */
501 kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_2 = 17U, /**< IOMUXC select input index */
502 kIOMUXC_FLEXPWM1_IPP_IND_PWMB_SELECT_INPUT_3 = 18U, /**< IOMUXC select input index */
503 kIOMUXC_FLEXSPI_IPP_IND_IO_FA_BIT0_SELECT_INPUT = 27U, /**< IOMUXC select input index */
504 kIOMUXC_FLEXSPI_IPP_IND_IO_FA_BIT1_SELECT_INPUT = 28U, /**< IOMUXC select input index */
505 kIOMUXC_FLEXSPI_IPP_IND_IO_FA_BIT2_SELECT_INPUT = 29U, /**< IOMUXC select input index */
506 kIOMUXC_FLEXSPI_IPP_IND_IO_FA_BIT3_SELECT_INPUT = 30U, /**< IOMUXC select input index */
507 kIOMUXC_FLEXSPI_IPP_IND_SCK_FA_SELECT_INPUT = 31U, /**< IOMUXC select input index */
508 kIOMUXC_LPI2C1_IPP_IND_LPI2C_SCL_SELECT_INPUT = 32U, /**< IOMUXC select input index */
509 kIOMUXC_LPI2C1_IPP_IND_LPI2C_SDA_SELECT_INPUT = 33U, /**< IOMUXC select input index */
510 kIOMUXC_LPI2C2_IPP_IND_LPI2C_SCL_SELECT_INPUT = 34U, /**< IOMUXC select input index */
511 kIOMUXC_LPI2C2_IPP_IND_LPI2C_SDA_SELECT_INPUT = 35U, /**< IOMUXC select input index */
512 kIOMUXC_LPSPI1_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 40U, /**< IOMUXC select input index */
513 kIOMUXC_LPSPI1_IPP_IND_LPSPI_SCK_SELECT_INPUT = 41U, /**< IOMUXC select input index */
514 kIOMUXC_LPSPI1_IPP_IND_LPSPI_SDI_SELECT_INPUT = 42U, /**< IOMUXC select input index */
515 kIOMUXC_LPSPI1_IPP_IND_LPSPI_SDO_SELECT_INPUT = 43U, /**< IOMUXC select input index */
516 kIOMUXC_LPSPI2_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 44U, /**< IOMUXC select input index */
517 kIOMUXC_LPSPI2_IPP_IND_LPSPI_SCK_SELECT_INPUT = 45U, /**< IOMUXC select input index */
518 kIOMUXC_LPSPI2_IPP_IND_LPSPI_SDI_SELECT_INPUT = 46U, /**< IOMUXC select input index */
519 kIOMUXC_LPSPI2_IPP_IND_LPSPI_SDO_SELECT_INPUT = 47U, /**< IOMUXC select input index */
520 kIOMUXC_LPUART2_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 52U, /**< IOMUXC select input index */
521 kIOMUXC_LPUART2_IPP_IND_LPUART_RXD_SELECT_INPUT = 53U, /**< IOMUXC select input index */
522 kIOMUXC_LPUART2_IPP_IND_LPUART_TXD_SELECT_INPUT = 54U, /**< IOMUXC select input index */
523 kIOMUXC_LPUART3_IPP_IND_LPUART_RXD_SELECT_INPUT = 55U, /**< IOMUXC select input index */
524 kIOMUXC_LPUART3_IPP_IND_LPUART_TXD_SELECT_INPUT = 56U, /**< IOMUXC select input index */
525 kIOMUXC_LPUART4_IPP_IND_LPUART_CTS_B_SELECT_INPUT = 57U, /**< IOMUXC select input index */
526 kIOMUXC_LPUART4_IPP_IND_LPUART_RXD_SELECT_INPUT = 58U, /**< IOMUXC select input index */
527 kIOMUXC_LPUART4_IPP_IND_LPUART_TXD_SELECT_INPUT = 59U, /**< IOMUXC select input index */
528 kIOMUXC_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT = 68U, /**< IOMUXC select input index */
529 kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 69U, /**< IOMUXC select input index */
530 kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 70U, /**< IOMUXC select input index */
531 kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 71U, /**< IOMUXC select input index */
532 kIOMUXC_QTIMER1_TMR3_INPUT_SELECT_INPUT = 72U, /**< IOMUXC select input index */
533 kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 = 77U, /**< IOMUXC select input index */
534 kIOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 78U, /**< IOMUXC select input index */
535 kIOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 79U, /**< IOMUXC select input index */
536 kIOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_1 = 80U, /**< IOMUXC select input index */
537 kIOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_2 = 81U, /**< IOMUXC select input index */
538 kIOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_3 = 82U, /**< IOMUXC select input index */
539 kIOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 83U, /**< IOMUXC select input index */
540 kIOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 84U, /**< IOMUXC select input index */
541 kIOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 85U, /**< IOMUXC select input index */
542 kIOMUXC_SAI2_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 = 86U, /**< IOMUXC select input index */
543 kIOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 87U, /**< IOMUXC select input index */
544 kIOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 88U, /**< IOMUXC select input index */
545 kIOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 89U, /**< IOMUXC select input index */
546 kIOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 90U, /**< IOMUXC select input index */
547 kIOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 91U, /**< IOMUXC select input index */
548 kIOMUXC_SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 = 92U, /**< IOMUXC select input index */
549 kIOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 93U, /**< IOMUXC select input index */
550 kIOMUXC_SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 94U, /**< IOMUXC select input index */
551 kIOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 95U, /**< IOMUXC select input index */
552 kIOMUXC_SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 96U, /**< IOMUXC select input index */
553 kIOMUXC_SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 97U, /**< IOMUXC select input index */
554 kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 99U, /**< IOMUXC select input index */
555 kIOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT = 100U, /**< IOMUXC select input index */
556 kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_14 = 105U, /**< IOMUXC select input index */
557 kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_15 = 106U, /**< IOMUXC select input index */
558 kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_16 = 107U, /**< IOMUXC select input index */
559 kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_17 = 108U, /**< IOMUXC select input index */
560 kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_10 = 109U, /**< IOMUXC select input index */
561 kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_12 = 110U, /**< IOMUXC select input index */
562 kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_13 = 111U, /**< IOMUXC select input index */
563 kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_18 = 112U, /**< IOMUXC select input index */
564 kIOMUXC_XBAR1_XBAR_IN_SELECT_INPUT_19 = 113U, /**< IOMUXC select input index */
565} iomuxc_select_input_t;
566
567typedef enum _xbar_input_signal
568{
569 kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA_IN0 input. */
570 kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA_IN1 input. */
571 kXBARA1_InputRESERVED2 = 2|0x100U, /**< XBARA_IN2 input is reserved. */
572 kXBARA1_InputRESERVED3 = 3|0x100U, /**< XBARA_IN3 input is reserved. */
573 kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA_IN4 input. */
574 kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA_IN5 input. */
575 kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA_IN6 input. */
576 kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA_IN7 input. */
577 kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA_IN8 input. */
578 kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA_IN9 input. */
579 kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA_IN10 input. */
580 kXBARA1_InputRESERVED11 = 11|0x100U, /**< XBARA_IN11 input is reserved. */
581 kXBARA1_InputRESERVED12 = 12|0x100U, /**< XBARA_IN12 input is reserved. */
582 kXBARA1_InputRESERVED13 = 13|0x100U, /**< XBARA_IN13 input is reserved. */
583 kXBARA1_InputRESERVED14 = 14|0x100U, /**< XBARA_IN14 input is reserved. */
584 kXBARA1_InputRESERVED15 = 15|0x100U, /**< XBARA_IN15 input is reserved. */
585 kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA_IN16 input. */
586 kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA_IN17 input. */
587 kXBARA1_InputRESERVED18 = 18|0x100U, /**< XBARA_IN18 input is reserved. */
588 kXBARA1_InputRESERVED19 = 19|0x100U, /**< XBARA_IN19 input is reserved. */
589 kXBARA1_InputRESERVED20 = 20|0x100U, /**< XBARA_IN20 input is reserved. */
590 kXBARA1_InputRESERVED21 = 21|0x100U, /**< XBARA_IN21 input is reserved. */
591 kXBARA1_InputRESERVED22 = 22|0x100U, /**< XBARA_IN22 input is reserved. */
592 kXBARA1_InputRESERVED23 = 23|0x100U, /**< XBARA_IN23 input is reserved. */
593 kXBARA1_InputRESERVED24 = 24|0x100U, /**< XBARA_IN24 input is reserved. */
594 kXBARA1_InputRESERVED25 = 25|0x100U, /**< XBARA_IN25 input is reserved. */
595 kXBARA1_InputRESERVED26 = 26|0x100U, /**< XBARA_IN26 input is reserved. */
596 kXBARA1_InputRESERVED27 = 27|0x100U, /**< XBARA_IN27 input is reserved. */
597 kXBARA1_InputRESERVED28 = 28|0x100U, /**< XBARA_IN28 input is reserved. */
598 kXBARA1_InputRESERVED29 = 29|0x100U, /**< XBARA_IN29 input is reserved. */
599 kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA_IN30 input is reserved. */
600 kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA_IN31 input is reserved. */
601 kXBARA1_InputQtimer1Tmr0 = 32|0x100U, /**< QTIMER1_TMR0 output assigned to XBARA_IN32 input. */
602 kXBARA1_InputQtimer1Tmr1 = 33|0x100U, /**< QTIMER1_TMR1 output assigned to XBARA_IN33 input. */
603 kXBARA1_InputQtimer1Tmr2 = 34|0x100U, /**< QTIMER1_TMR2 output assigned to XBARA_IN34 input. */
604 kXBARA1_InputQtimer1Tmr3 = 35|0x100U, /**< QTIMER1_TMR3 output assigned to XBARA_IN35 input. */
605 kXBARA1_InputRESERVED36 = 36|0x100U, /**< XBARA_IN36 input is reserved. */
606 kXBARA1_InputRESERVED37 = 37|0x100U, /**< XBARA_IN37 input is reserved. */
607 kXBARA1_InputRESERVED38 = 38|0x100U, /**< XBARA_IN38 input is reserved. */
608 kXBARA1_InputRESERVED39 = 39|0x100U, /**< XBARA_IN39 input is reserved. */
609 kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA_IN40 input. */
610 kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA_IN41 input. */
611 kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA_IN42 input. */
612 kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA_IN43 input. */
613 kXBARA1_InputRESERVED44 = 44|0x100U, /**< XBARA_IN44 input is reserved. */
614 kXBARA1_InputRESERVED45 = 45|0x100U, /**< XBARA_IN45 input is reserved. */
615 kXBARA1_InputRESERVED46 = 46|0x100U, /**< XBARA_IN46 input is reserved. */
616 kXBARA1_InputRESERVED47 = 47|0x100U, /**< XBARA_IN47 input is reserved. */
617 kXBARA1_InputRESERVED48 = 48|0x100U, /**< XBARA_IN48 input is reserved. */
618 kXBARA1_InputRESERVED49 = 49|0x100U, /**< XBARA_IN49 input is reserved. */
619 kXBARA1_InputRESERVED50 = 50|0x100U, /**< XBARA_IN50 input is reserved. */
620 kXBARA1_InputRESERVED51 = 51|0x100U, /**< XBARA_IN51 input is reserved. */
621 kXBARA1_InputRESERVED52 = 52|0x100U, /**< XBARA_IN52 input is reserved. */
622 kXBARA1_InputRESERVED53 = 53|0x100U, /**< XBARA_IN53 input is reserved. */
623 kXBARA1_InputRESERVED54 = 54|0x100U, /**< XBARA_IN54 input is reserved. */
624 kXBARA1_InputRESERVED55 = 55|0x100U, /**< XBARA_IN55 input is reserved. */
625 kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA_IN56 input. */
626 kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA_IN57 input. */
627 kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA_IN58 input. */
628 kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA_IN59 input. */
629 kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA_IN60 input. */
630 kXBARA1_InputRESERVED61 = 61|0x100U, /**< XBARA_IN61 input is reserved. */
631 kXBARA1_InputRESERVED62 = 62|0x100U, /**< XBARA_IN62 input is reserved. */
632 kXBARA1_InputRESERVED63 = 63|0x100U, /**< XBARA_IN63 input is reserved. */
633 kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA_IN64 input. */
634 kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA_IN65 input. */
635 kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA_IN66 input. */
636 kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA_IN67 input. */
637 kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA_IN68 input. */
638 kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA_IN69 input. */
639 kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA_IN70 input. */
640 kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA_IN71 input. */
641 kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA_IN72 input. */
642 kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA_IN73 input. */
643 kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA_IN74 input. */
644 kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA_IN75 input. */
645 kXBARA1_InputRESERVED76 = 76|0x100U, /**< XBARA_IN76 input is reserved. */
646 kXBARA1_InputRESERVED77 = 77|0x100U, /**< XBARA_IN77 input is reserved. */
647 kXBARA1_InputRESERVED78 = 78|0x100U, /**< XBARA_IN78 input is reserved. */
648 kXBARA1_InputRESERVED79 = 79|0x100U, /**< XBARA_IN79 input is reserved. */
649 kXBARA1_InputAdcEtc0Coco0 = 80|0x100U, /**< ADC_ETC0_COCO0 output assigned to XBARA_IN80 input. */
650 kXBARA1_InputAdcEtc0Coco1 = 81|0x100U, /**< ADC_ETC0_COCO1 output assigned to XBARA_IN81 input. */
651 kXBARA1_InputAdcEtc0Coco2 = 82|0x100U, /**< ADC_ETC0_COCO2 output assigned to XBARA_IN82 input. */
652 kXBARA1_InputAdcEtc0Coco3 = 83|0x100U, /**< ADC_ETC0_COCO3 output assigned to XBARA_IN83 input. */
653 kXBARA1_InputAdcEtc1Coco0 = 84|0x100U, /**< ADC_ETC1_COCO0 output assigned to XBARA_IN84 input. */
654 kXBARA1_InputAdcEtc1Coco1 = 85|0x100U, /**< ADC_ETC1_COCO1 output assigned to XBARA_IN85 input. */
655 kXBARA1_InputAdcEtc1Coco2 = 86|0x100U, /**< ADC_ETC1_COCO2 output assigned to XBARA_IN86 input. */
656 kXBARA1_InputAdcEtc1Coco3 = 87|0x100U, /**< ADC_ETC1_COCO3 output assigned to XBARA_IN87 input. */
657 kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB_IN0 input. */
658 kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB_IN1 input. */
659 kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB_IN2 input is reserved. */
660 kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB_IN3 input is reserved. */
661 kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB_IN4 input is reserved. */
662 kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB_IN5 input is reserved. */
663 kXBARB2_InputRESERVED6 = 6|0x200U, /**< XBARB_IN6 input is reserved. */
664 kXBARB2_InputRESERVED7 = 7|0x200U, /**< XBARB_IN7 input is reserved. */
665 kXBARB2_InputRESERVED8 = 8|0x200U, /**< XBARB_IN8 input is reserved. */
666 kXBARB2_InputRESERVED9 = 9|0x200U, /**< XBARB_IN9 input is reserved. */
667 kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB_IN10 input is reserved. */
668 kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB_IN11 input is reserved. */
669 kXBARB2_InputQtimer1Tmr0 = 12|0x200U, /**< QTIMER1_TMR0 output assigned to XBARB_IN12 input. */
670 kXBARB2_InputQtimer1Tmr1 = 13|0x200U, /**< QTIMER1_TMR1 output assigned to XBARB_IN13 input. */
671 kXBARB2_InputQtimer1Tmr2 = 14|0x200U, /**< QTIMER1_TMR2 output assigned to XBARB_IN14 input. */
672 kXBARB2_InputQtimer1Tmr3 = 15|0x200U, /**< QTIMER1_TMR3 output assigned to XBARB_IN15 input. */
673 kXBARB2_InputRESERVED16 = 16|0x200U, /**< XBARB_IN16 input is reserved. */
674 kXBARB2_InputRESERVED17 = 17|0x200U, /**< XBARB_IN17 input is reserved. */
675 kXBARB2_InputRESERVED18 = 18|0x200U, /**< XBARB_IN18 input is reserved. */
676 kXBARB2_InputRESERVED19 = 19|0x200U, /**< XBARB_IN19 input is reserved. */
677 kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB_IN20 input. */
678 kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB_IN21 input. */
679 kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB_IN22 input. */
680 kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB_IN23 input. */
681 kXBARB2_InputRESERVED24 = 24|0x200U, /**< XBARB_IN24 input is reserved. */
682 kXBARB2_InputRESERVED25 = 25|0x200U, /**< XBARB_IN25 input is reserved. */
683 kXBARB2_InputRESERVED26 = 26|0x200U, /**< XBARB_IN26 input is reserved. */
684 kXBARB2_InputRESERVED27 = 27|0x200U, /**< XBARB_IN27 input is reserved. */
685 kXBARB2_InputRESERVED28 = 28|0x200U, /**< XBARB_IN28 input is reserved. */
686 kXBARB2_InputRESERVED29 = 29|0x200U, /**< XBARB_IN29 input is reserved. */
687 kXBARB2_InputRESERVED30 = 30|0x200U, /**< XBARB_IN30 input is reserved. */
688 kXBARB2_InputRESERVED31 = 31|0x200U, /**< XBARB_IN31 input is reserved. */
689 kXBARB2_InputRESERVED32 = 32|0x200U, /**< XBARB_IN32 input is reserved. */
690 kXBARB2_InputRESERVED33 = 33|0x200U, /**< XBARB_IN33 input is reserved. */
691 kXBARB2_InputRESERVED34 = 34|0x200U, /**< XBARB_IN34 input is reserved. */
692 kXBARB2_InputRESERVED35 = 35|0x200U, /**< XBARB_IN35 input is reserved. */
693 kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB_IN36 input. */
694 kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB_IN37 input. */
695 kXBARB2_InputAdcEtc0Coco0 = 38|0x200U, /**< ADC_ETC0_COCO0 output assigned to XBARB_IN38 input. */
696 kXBARB2_InputAdcEtc0Coco1 = 39|0x200U, /**< ADC_ETC0_COCO1 output assigned to XBARB_IN39 input. */
697 kXBARB2_InputAdcEtc0Coco2 = 40|0x200U, /**< ADC_ETC0_COCO2 output assigned to XBARB_IN40 input. */
698 kXBARB2_InputAdcEtc0Coco3 = 41|0x200U, /**< ADC_ETC0_COCO3 output assigned to XBARB_IN41 input. */
699 kXBARB2_InputAdcEtc1Coco0 = 42|0x200U, /**< ADC_ETC1_COCO0 output assigned to XBARB_IN42 input. */
700 kXBARB2_InputAdcEtc1Coco1 = 43|0x200U, /**< ADC_ETC1_COCO1 output assigned to XBARB_IN43 input. */
701 kXBARB2_InputAdcEtc1Coco2 = 44|0x200U, /**< ADC_ETC1_COCO2 output assigned to XBARB_IN44 input. */
702 kXBARB2_InputAdcEtc1Coco3 = 45|0x200U, /**< ADC_ETC1_COCO3 output assigned to XBARB_IN45 input. */
703 kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB_IN46 input. */
704 kXBARB2_InputRESERVED47 = 47|0x200U, /**< XBARB_IN47 input is reserved. */
705 kXBARB2_InputRESERVED48 = 48|0x200U, /**< XBARB_IN48 input is reserved. */
706 kXBARB2_InputRESERVED49 = 49|0x200U, /**< XBARB_IN49 input is reserved. */
707 kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB_IN50 input. */
708 kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB_IN51 input. */
709 kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB_IN52 input. */
710 kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB_IN53 input. */
711 kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB_IN54 input. */
712 kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB_IN55 input. */
713 kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB_IN56 input. */
714 kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB_IN57 input. */
715} xbar_input_signal_t;
716
717typedef enum _xbar_output_signal
718{
719 kXBARA1_OutputRESERVED0 = 0|0x100U, /**< XBARA_OUT0 output is reserved. */
720 kXBARA1_OutputRESERVED1 = 1|0x100U, /**< XBARA_OUT1 output is reserved. */
721 kXBARA1_OutputRESERVED2 = 2|0x100U, /**< XBARA_OUT2 output is reserved. */
722 kXBARA1_OutputRESERVED3 = 3|0x100U, /**< XBARA_OUT3 output is reserved. */
723 kXBARA1_OutputRESERVED4 = 4|0x100U, /**< XBARA_OUT4 output is reserved. */
724 kXBARA1_OutputRESERVED5 = 5|0x100U, /**< XBARA_OUT5 output is reserved. */
725 kXBARA1_OutputRESERVED6 = 6|0x100U, /**< XBARA_OUT6 output is reserved. */
726 kXBARA1_OutputRESERVED7 = 7|0x100U, /**< XBARA_OUT7 output is reserved. */
727 kXBARA1_OutputRESERVED8 = 8|0x100U, /**< XBARA_OUT8 output is reserved. */
728 kXBARA1_OutputRESERVED9 = 9|0x100U, /**< XBARA_OUT9 output is reserved. */
729 kXBARA1_OutputRESERVED10 = 10|0x100U, /**< XBARA_OUT10 output is reserved. */
730 kXBARA1_OutputRESERVED11 = 11|0x100U, /**< XBARA_OUT11 output is reserved. */
731 kXBARA1_OutputRESERVED12 = 12|0x100U, /**< XBARA_OUT12 output is reserved. */
732 kXBARA1_OutputRESERVED13 = 13|0x100U, /**< XBARA_OUT13 output is reserved. */
733 kXBARA1_OutputRESERVED14 = 14|0x100U, /**< XBARA_OUT14 output is reserved. */
734 kXBARA1_OutputRESERVED15 = 15|0x100U, /**< XBARA_OUT15 output is reserved. */
735 kXBARA1_OutputRESERVED16 = 16|0x100U, /**< XBARA_OUT16 output is reserved. */
736 kXBARA1_OutputRESERVED17 = 17|0x100U, /**< XBARA_OUT17 output is reserved. */
737 kXBARA1_OutputRESERVED18 = 18|0x100U, /**< XBARA_OUT18 output is reserved. */
738 kXBARA1_OutputRESERVED19 = 19|0x100U, /**< XBARA_OUT19 output is reserved. */
739 kXBARA1_OutputRESERVED20 = 20|0x100U, /**< XBARA_OUT20 output is reserved. */
740 kXBARA1_OutputRESERVED21 = 21|0x100U, /**< XBARA_OUT21 output is reserved. */
741 kXBARA1_OutputRESERVED22 = 22|0x100U, /**< XBARA_OUT22 output is reserved. */
742 kXBARA1_OutputRESERVED23 = 23|0x100U, /**< XBARA_OUT23 output is reserved. */
743 kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA_OUT24 output is reserved. */
744 kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA_OUT25 output is reserved. */
745 kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA_OUT26 output assigned to FLEXPWM1_EXTA0 */
746 kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA_OUT27 output assigned to FLEXPWM1_EXTA1 */
747 kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA_OUT28 output assigned to FLEXPWM1_EXTA2 */
748 kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA_OUT29 output assigned to FLEXPWM1_EXTA3 */
749 kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
750 kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
751 kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
752 kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
753 kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA_OUT34 output assigned to FLEXPWM1_EXT_CLK */
754 kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA_OUT35 output assigned to FLEXPWM1_FAULT0 */
755 kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA_OUT36 output assigned to FLEXPWM1_FAULT1 */
756 kXBARA1_OutputFlexpwm1Fault2 = 37|0x100U, /**< XBARA_OUT37 output assigned to FLEXPWM1_FAULT2 */
757 kXBARA1_OutputFlexpwm1Fault3 = 38|0x100U, /**< XBARA_OUT38 output assigned to FLEXPWM1_FAULT3 */
758 kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
759 kXBARA1_OutputRESERVED40 = 40|0x100U, /**< XBARA_OUT40 output is reserved. */
760 kXBARA1_OutputRESERVED41 = 41|0x100U, /**< XBARA_OUT41 output is reserved. */
761 kXBARA1_OutputRESERVED42 = 42|0x100U, /**< XBARA_OUT42 output is reserved. */
762 kXBARA1_OutputRESERVED43 = 43|0x100U, /**< XBARA_OUT43 output is reserved. */
763 kXBARA1_OutputRESERVED44 = 44|0x100U, /**< XBARA_OUT44 output is reserved. */
764 kXBARA1_OutputRESERVED45 = 45|0x100U, /**< XBARA_OUT45 output is reserved. */
765 kXBARA1_OutputRESERVED46 = 46|0x100U, /**< XBARA_OUT46 output is reserved. */
766 kXBARA1_OutputRESERVED47 = 47|0x100U, /**< XBARA_OUT47 output is reserved. */
767 kXBARA1_OutputRESERVED48 = 48|0x100U, /**< XBARA_OUT48 output is reserved. */
768 kXBARA1_OutputRESERVED49 = 49|0x100U, /**< XBARA_OUT49 output is reserved. */
769 kXBARA1_OutputRESERVED50 = 50|0x100U, /**< XBARA_OUT50 output is reserved. */
770 kXBARA1_OutputRESERVED51 = 51|0x100U, /**< XBARA_OUT51 output is reserved. */
771 kXBARA1_OutputRESERVED52 = 52|0x100U, /**< XBARA_OUT52 output is reserved. */
772 kXBARA1_OutputRESERVED53 = 53|0x100U, /**< XBARA_OUT53 output is reserved. */
773 kXBARA1_OutputRESERVED54 = 54|0x100U, /**< XBARA_OUT54 output is reserved. */
774 kXBARA1_OutputRESERVED55 = 55|0x100U, /**< XBARA_OUT55 output is reserved. */
775 kXBARA1_OutputRESERVED56 = 56|0x100U, /**< XBARA_OUT56 output is reserved. */
776 kXBARA1_OutputRESERVED57 = 57|0x100U, /**< XBARA_OUT57 output is reserved. */
777 kXBARA1_OutputRESERVED58 = 58|0x100U, /**< XBARA_OUT58 output is reserved. */
778 kXBARA1_OutputRESERVED59 = 59|0x100U, /**< XBARA_OUT59 output is reserved. */
779 kXBARA1_OutputRESERVED60 = 60|0x100U, /**< XBARA_OUT60 output is reserved. */
780 kXBARA1_OutputRESERVED61 = 61|0x100U, /**< XBARA_OUT61 output is reserved. */
781 kXBARA1_OutputRESERVED62 = 62|0x100U, /**< XBARA_OUT62 output is reserved. */
782 kXBARA1_OutputRESERVED63 = 63|0x100U, /**< XBARA_OUT63 output is reserved. */
783 kXBARA1_OutputRESERVED64 = 64|0x100U, /**< XBARA_OUT64 output is reserved. */
784 kXBARA1_OutputRESERVED65 = 65|0x100U, /**< XBARA_OUT65 output is reserved. */
785 kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA_OUT66 output assigned to ENC1_PHASE_A_INPUT */
786 kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA_OUT67 output assigned to ENC1_PHASE_B_INPUT */
787 kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA_OUT68 output assigned to ENC1_INDEX */
788 kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA_OUT69 output assigned to ENC1_HOME */
789 kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA_OUT70 output assigned to ENC1_TRIGGER */
790 kXBARA1_OutputRESERVED71 = 71|0x100U, /**< XBARA_OUT71 output is reserved. */
791 kXBARA1_OutputRESERVED72 = 72|0x100U, /**< XBARA_OUT72 output is reserved. */
792 kXBARA1_OutputRESERVED73 = 73|0x100U, /**< XBARA_OUT73 output is reserved. */
793 kXBARA1_OutputRESERVED74 = 74|0x100U, /**< XBARA_OUT74 output is reserved. */
794 kXBARA1_OutputRESERVED75 = 75|0x100U, /**< XBARA_OUT75 output is reserved. */
795 kXBARA1_OutputRESERVED76 = 76|0x100U, /**< XBARA_OUT76 output is reserved. */
796 kXBARA1_OutputRESERVED77 = 77|0x100U, /**< XBARA_OUT77 output is reserved. */
797 kXBARA1_OutputRESERVED78 = 78|0x100U, /**< XBARA_OUT78 output is reserved. */
798 kXBARA1_OutputRESERVED79 = 79|0x100U, /**< XBARA_OUT79 output is reserved. */
799 kXBARA1_OutputRESERVED80 = 80|0x100U, /**< XBARA_OUT80 output is reserved. */
800 kXBARA1_OutputRESERVED81 = 81|0x100U, /**< XBARA_OUT81 output is reserved. */
801 kXBARA1_OutputRESERVED82 = 82|0x100U, /**< XBARA_OUT82 output is reserved. */
802 kXBARA1_OutputRESERVED83 = 83|0x100U, /**< XBARA_OUT83 output is reserved. */
803 kXBARA1_OutputRESERVED84 = 84|0x100U, /**< XBARA_OUT84 output is reserved. */
804 kXBARA1_OutputRESERVED85 = 85|0x100U, /**< XBARA_OUT85 output is reserved. */
805 kXBARA1_OutputQtimer1Tmr0 = 86|0x100U, /**< XBARA_OUT86 output assigned to QTIMER1_TMR0 */
806 kXBARA1_OutputQtimer1Tmr1 = 87|0x100U, /**< XBARA_OUT87 output assigned to QTIMER1_TMR1 */
807 kXBARA1_OutputQtimer1Tmr2 = 88|0x100U, /**< XBARA_OUT88 output assigned to QTIMER1_TMR2 */
808 kXBARA1_OutputQtimer1Tmr3 = 89|0x100U, /**< XBARA_OUT89 output assigned to QTIMER1_TMR3 */
809 kXBARA1_OutputRESERVED90 = 90|0x100U, /**< XBARA_OUT90 output is reserved. */
810 kXBARA1_OutputRESERVED91 = 91|0x100U, /**< XBARA_OUT91 output is reserved. */
811 kXBARA1_OutputRESERVED92 = 92|0x100U, /**< XBARA_OUT92 output is reserved. */
812 kXBARA1_OutputRESERVED93 = 93|0x100U, /**< XBARA_OUT93 output is reserved. */
813 kXBARA1_OutputRESERVED94 = 94|0x100U, /**< XBARA_OUT94 output is reserved. */
814 kXBARA1_OutputRESERVED95 = 95|0x100U, /**< XBARA_OUT95 output is reserved. */
815 kXBARA1_OutputRESERVED96 = 96|0x100U, /**< XBARA_OUT96 output is reserved. */
816 kXBARA1_OutputRESERVED97 = 97|0x100U, /**< XBARA_OUT97 output is reserved. */
817 kXBARA1_OutputRESERVED98 = 98|0x100U, /**< XBARA_OUT98 output is reserved. */
818 kXBARA1_OutputRESERVED99 = 99|0x100U, /**< XBARA_OUT99 output is reserved. */
819 kXBARA1_OutputRESERVED100 = 100|0x100U, /**< XBARA_OUT100 output is reserved. */
820 kXBARA1_OutputRESERVED101 = 101|0x100U, /**< XBARA_OUT101 output is reserved. */
821 kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA_OUT102 output assigned to EWM_EWM_IN */
822 kXBARA1_OutputAdcEtcTrig00 = 103|0x100U, /**< XBARA_OUT103 output assigned to ADC_ETC_TRIG00 */
823 kXBARA1_OutputAdcEtcTrig01 = 104|0x100U, /**< XBARA_OUT104 output assigned to ADC_ETC_TRIG01 */
824 kXBARA1_OutputAdcEtcTrig02 = 105|0x100U, /**< XBARA_OUT105 output assigned to ADC_ETC_TRIG02 */
825 kXBARA1_OutputAdcEtcTrig03 = 106|0x100U, /**< XBARA_OUT106 output assigned to ADC_ETC_TRIG03 */
826 kXBARA1_OutputAdcEtcTrig10 = 107|0x100U, /**< XBARA_OUT107 output assigned to ADC_ETC_TRIG10 */
827 kXBARA1_OutputAdcEtcTrig11 = 108|0x100U, /**< XBARA_OUT108 output assigned to ADC_ETC_TRIG11 */
828 kXBARA1_OutputAdcEtcTrig12 = 109|0x100U, /**< XBARA_OUT109 output assigned to ADC_ETC_TRIG12 */
829 kXBARA1_OutputAdcEtcTrig13 = 110|0x100U, /**< XBARA_OUT110 output assigned to ADC_ETC_TRIG13 */
830 kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA_OUT111 output assigned to LPI2C1_TRG_INPUT */
831 kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA_OUT112 output assigned to LPI2C2_TRG_INPUT */
832 kXBARA1_OutputRESERVED113 = 113|0x100U, /**< XBARA_OUT113 output is reserved. */
833 kXBARA1_OutputRESERVED114 = 114|0x100U, /**< XBARA_OUT114 output is reserved. */
834 kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA_OUT115 output assigned to LPSPI1_TRG_INPUT */
835 kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA_OUT116 output assigned to LPSPI2_TRG_INPUT */
836 kXBARA1_OutputRESERVED117 = 117|0x100U, /**< XBARA_OUT117 output is reserved. */
837 kXBARA1_OutputRESERVED118 = 118|0x100U, /**< XBARA_OUT118 output is reserved. */
838 kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA_OUT119 output assigned to LPUART1_TRG_INPUT */
839 kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA_OUT120 output assigned to LPUART2_TRG_INPUT */
840 kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA_OUT121 output assigned to LPUART3_TRG_INPUT */
841 kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA_OUT122 output assigned to LPUART4_TRG_INPUT */
842 kXBARA1_OutputRESERVED123 = 123|0x100U, /**< XBARA_OUT123 output is reserved. */
843 kXBARA1_OutputRESERVED124 = 124|0x100U, /**< XBARA_OUT124 output is reserved. */
844 kXBARA1_OutputRESERVED125 = 125|0x100U, /**< XBARA_OUT125 output is reserved. */
845 kXBARA1_OutputRESERVED126 = 126|0x100U, /**< XBARA_OUT126 output is reserved. */
846 kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
847 kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
848 kXBARA1_OutputRESERVED129 = 129|0x100U, /**< XBARA_OUT129 output is reserved. */
849 kXBARA1_OutputRESERVED130 = 130|0x100U, /**< XBARA_OUT130 output is reserved. */
850 kXBARA1_OutputRESERVED131 = 131|0x100U, /**< XBARA_OUT131 output is reserved. */
851 kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB_OUT0 output assigned to AOI1_IN00 */
852 kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB_OUT1 output assigned to AOI1_IN01 */
853 kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB_OUT2 output assigned to AOI1_IN02 */
854 kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB_OUT3 output assigned to AOI1_IN03 */
855 kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB_OUT4 output assigned to AOI1_IN04 */
856 kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB_OUT5 output assigned to AOI1_IN05 */
857 kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB_OUT6 output assigned to AOI1_IN06 */
858 kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB_OUT7 output assigned to AOI1_IN07 */
859 kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB_OUT8 output assigned to AOI1_IN08 */
860 kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB_OUT9 output assigned to AOI1_IN09 */
861 kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB_OUT10 output assigned to AOI1_IN10 */
862 kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB_OUT11 output assigned to AOI1_IN11 */
863 kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB_OUT12 output assigned to AOI1_IN12 */
864 kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB_OUT13 output assigned to AOI1_IN13 */
865 kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB_OUT14 output assigned to AOI1_IN14 */
866 kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB_OUT15 output assigned to AOI1_IN15 */
867} xbar_output_signal_t;
868
869
870/*!
871 * @}
872 */ /* end of group Mapping_Information */
873
874
875/* ----------------------------------------------------------------------------
876 -- Device Peripheral Access Layer
877 ---------------------------------------------------------------------------- */
878
879/*!
880 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
881 * @{
882 */
883
884
885/*
886** Start of section using anonymous unions
887*/
888
889#if defined(__ARMCC_VERSION)
890 #if (__ARMCC_VERSION >= 6010050)
891 #pragma clang diagnostic push
892 #else
893 #pragma push
894 #pragma anon_unions
895 #endif
896#elif defined(__CWCC__)
897 #pragma push
898 #pragma cpp_extensions on
899#elif defined(__GNUC__)
900 /* anonymous unions are enabled by default */
901#elif defined(__IAR_SYSTEMS_ICC__)
902 #pragma language=extended
903#else
904 #error Not supported compiler type
905#endif
906
907/* ----------------------------------------------------------------------------
908 -- ADC Peripheral Access Layer
909 ---------------------------------------------------------------------------- */
910
911/*!
912 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
913 * @{
914 */
915
916/** ADC - Register Layout Typedef */
917typedef struct {
918 __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */
919 __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */
920 __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */
921 __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */
922 __IO uint32_t GC; /**< General control register, offset: 0x48 */
923 __IO uint32_t GS; /**< General status register, offset: 0x4C */
924 __IO uint32_t CV; /**< Compare value register, offset: 0x50 */
925 __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */
926 __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */
927} ADC_Type;
928
929/* ----------------------------------------------------------------------------
930 -- ADC Register Masks
931 ---------------------------------------------------------------------------- */
932
933/*!
934 * @addtogroup ADC_Register_Masks ADC Register Masks
935 * @{
936 */
937
938/*! @name HC - Control register for hardware triggers */
939/*! @{ */
940#define ADC_HC_ADCH_MASK (0x1FU)
941#define ADC_HC_ADCH_SHIFT (0U)
942/*! ADCH - Input Channel Select
943 * 0b10000..External channel selection from ADC_ETC
944 * 0b11000..Reserved.
945 * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally
946 * 0b11010..Reserved.
947 * 0b11011..Reserved.
948 * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion.
949 */
950#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
951#define ADC_HC_AIEN_MASK (0x80U)
952#define ADC_HC_AIEN_SHIFT (7U)
953/*! AIEN - Conversion Complete Interrupt Enable/Disable Control
954 * 0b1..Conversion complete interrupt enabled
955 * 0b0..Conversion complete interrupt disabled
956 */
957#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
958/*! @} */
959
960/* The count of ADC_HC */
961#define ADC_HC_COUNT (8U)
962
963/*! @name HS - Status register for HW triggers */
964/*! @{ */
965#define ADC_HS_COCO0_MASK (0x1U)
966#define ADC_HS_COCO0_SHIFT (0U)
967/*! COCO0 - Conversion Complete Flag
968 */
969#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
970/*! @} */
971
972/*! @name R - Data result register for HW triggers */
973/*! @{ */
974#define ADC_R_CDATA_MASK (0xFFFU)
975#define ADC_R_CDATA_SHIFT (0U)
976/*! CDATA - Data (result of an ADC conversion)
977 */
978#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
979/*! @} */
980
981/* The count of ADC_R */
982#define ADC_R_COUNT (8U)
983
984/*! @name CFG - Configuration register */
985/*! @{ */
986#define ADC_CFG_ADICLK_MASK (0x3U)
987#define ADC_CFG_ADICLK_SHIFT (0U)
988/*! ADICLK - Input Clock Select
989 * 0b00..IPG clock
990 * 0b01..IPG clock divided by 2
991 * 0b10..Reserved
992 * 0b11..Asynchronous clock (ADACK)
993 */
994#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
995#define ADC_CFG_MODE_MASK (0xCU)
996#define ADC_CFG_MODE_SHIFT (2U)
997/*! MODE - Conversion Mode Selection
998 * 0b00..8-bit conversion
999 * 0b01..10-bit conversion
1000 * 0b10..12-bit conversion
1001 * 0b11..Reserved
1002 */
1003#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
1004#define ADC_CFG_ADLSMP_MASK (0x10U)
1005#define ADC_CFG_ADLSMP_SHIFT (4U)
1006/*! ADLSMP - Long Sample Time Configuration
1007 * 0b0..Short sample mode.
1008 * 0b1..Long sample mode.
1009 */
1010#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
1011#define ADC_CFG_ADIV_MASK (0x60U)
1012#define ADC_CFG_ADIV_SHIFT (5U)
1013/*! ADIV - Clock Divide Select
1014 * 0b00..Input clock
1015 * 0b01..Input clock / 2
1016 * 0b10..Input clock / 4
1017 * 0b11..Input clock / 8
1018 */
1019#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
1020#define ADC_CFG_ADLPC_MASK (0x80U)
1021#define ADC_CFG_ADLPC_SHIFT (7U)
1022/*! ADLPC - Low-Power Configuration
1023 * 0b0..ADC hard block not in low power mode.
1024 * 0b1..ADC hard block in low power mode.
1025 */
1026#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
1027#define ADC_CFG_ADSTS_MASK (0x300U)
1028#define ADC_CFG_ADSTS_SHIFT (8U)
1029/*! ADSTS
1030 * 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b
1031 * 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b
1032 * 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b
1033 * 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b
1034 */
1035#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
1036#define ADC_CFG_ADHSC_MASK (0x400U)
1037#define ADC_CFG_ADHSC_SHIFT (10U)
1038/*! ADHSC - High Speed Configuration
1039 * 0b0..Normal conversion selected.
1040 * 0b1..High speed conversion selected.
1041 */
1042#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
1043#define ADC_CFG_REFSEL_MASK (0x1800U)
1044#define ADC_CFG_REFSEL_SHIFT (11U)
1045/*! REFSEL - Voltage Reference Selection
1046 * 0b00..Selects VREFH/VREFL as reference voltage.
1047 * 0b01..Reserved
1048 * 0b10..Reserved
1049 * 0b11..Reserved
1050 */
1051#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
1052#define ADC_CFG_ADTRG_MASK (0x2000U)
1053#define ADC_CFG_ADTRG_SHIFT (13U)
1054/*! ADTRG - Conversion Trigger Select
1055 * 0b0..Software trigger selected
1056 * 0b1..Hardware trigger selected
1057 */
1058#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
1059#define ADC_CFG_AVGS_MASK (0xC000U)
1060#define ADC_CFG_AVGS_SHIFT (14U)
1061/*! AVGS - Hardware Average select
1062 * 0b00..4 samples averaged
1063 * 0b01..8 samples averaged
1064 * 0b10..16 samples averaged
1065 * 0b11..32 samples averaged
1066 */
1067#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
1068#define ADC_CFG_OVWREN_MASK (0x10000U)
1069#define ADC_CFG_OVWREN_SHIFT (16U)
1070/*! OVWREN - Data Overwrite Enable
1071 * 0b1..Enable the overwriting.
1072 * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.
1073 */
1074#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
1075/*! @} */
1076
1077/*! @name GC - General control register */
1078/*! @{ */
1079#define ADC_GC_ADACKEN_MASK (0x1U)
1080#define ADC_GC_ADACKEN_SHIFT (0U)
1081/*! ADACKEN - Asynchronous clock output enable
1082 * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.
1083 * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC
1084 */
1085#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
1086#define ADC_GC_DMAEN_MASK (0x2U)
1087#define ADC_GC_DMAEN_SHIFT (1U)
1088/*! DMAEN - DMA Enable
1089 * 0b0..DMA disabled (default)
1090 * 0b1..DMA enabled
1091 */
1092#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
1093#define ADC_GC_ACREN_MASK (0x4U)
1094#define ADC_GC_ACREN_SHIFT (2U)
1095/*! ACREN - Compare Function Range Enable
1096 * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared.
1097 * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.
1098 */
1099#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
1100#define ADC_GC_ACFGT_MASK (0x8U)
1101#define ADC_GC_ACFGT_SHIFT (3U)
1102/*! ACFGT - Compare Function Greater Than Enable
1103 * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive"
1104 * functionality based on the values placed in the ADC_CV register.
1105 * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive"
1106 * functionality based on the values placed in the ADC_CV registers.
1107 */
1108#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
1109#define ADC_GC_ACFE_MASK (0x10U)
1110#define ADC_GC_ACFE_SHIFT (4U)
1111/*! ACFE - Compare Function Enable
1112 * 0b0..Compare function disabled
1113 * 0b1..Compare function enabled
1114 */
1115#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
1116#define ADC_GC_AVGE_MASK (0x20U)
1117#define ADC_GC_AVGE_SHIFT (5U)
1118/*! AVGE - Hardware average enable
1119 * 0b0..Hardware average function disabled
1120 * 0b1..Hardware average function enabled
1121 */
1122#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
1123#define ADC_GC_ADCO_MASK (0x40U)
1124#define ADC_GC_ADCO_SHIFT (6U)
1125/*! ADCO - Continuous Conversion Enable
1126 * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
1127 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
1128 */
1129#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
1130#define ADC_GC_CAL_MASK (0x80U)
1131#define ADC_GC_CAL_SHIFT (7U)
1132/*! CAL - Calibration
1133 */
1134#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
1135/*! @} */
1136
1137/*! @name GS - General status register */
1138/*! @{ */
1139#define ADC_GS_ADACT_MASK (0x1U)
1140#define ADC_GS_ADACT_SHIFT (0U)
1141/*! ADACT - Conversion Active
1142 * 0b0..Conversion not in progress.
1143 * 0b1..Conversion in progress.
1144 */
1145#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
1146#define ADC_GS_CALF_MASK (0x2U)
1147#define ADC_GS_CALF_SHIFT (1U)
1148/*! CALF - Calibration Failed Flag
1149 * 0b0..Calibration completed normally.
1150 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
1151 */
1152#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
1153#define ADC_GS_AWKST_MASK (0x4U)
1154#define ADC_GS_AWKST_SHIFT (2U)
1155/*! AWKST - Asynchronous wakeup interrupt status
1156 * 0b1..Asynchronous wake up interrupt occurred in stop mode.
1157 * 0b0..No asynchronous interrupt.
1158 */
1159#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
1160/*! @} */
1161
1162/*! @name CV - Compare value register */
1163/*! @{ */
1164#define ADC_CV_CV1_MASK (0xFFFU)
1165#define ADC_CV_CV1_SHIFT (0U)
1166/*! CV1 - Compare Value 1
1167 */
1168#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
1169#define ADC_CV_CV2_MASK (0xFFF0000U)
1170#define ADC_CV_CV2_SHIFT (16U)
1171/*! CV2 - Compare Value 2
1172 */
1173#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
1174/*! @} */
1175
1176/*! @name OFS - Offset correction value register */
1177/*! @{ */
1178#define ADC_OFS_OFS_MASK (0xFFFU)
1179#define ADC_OFS_OFS_SHIFT (0U)
1180/*! OFS - Offset value
1181 */
1182#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
1183#define ADC_OFS_SIGN_MASK (0x1000U)
1184#define ADC_OFS_SIGN_SHIFT (12U)
1185/*! SIGN - Sign bit
1186 * 0b0..The offset value is added with the raw result
1187 * 0b1..The offset value is subtracted from the raw converted value
1188 */
1189#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
1190/*! @} */
1191
1192/*! @name CAL - Calibration value register */
1193/*! @{ */
1194#define ADC_CAL_CAL_CODE_MASK (0xFU)
1195#define ADC_CAL_CAL_CODE_SHIFT (0U)
1196/*! CAL_CODE - Calibration Result Value
1197 */
1198#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)
1199/*! @} */
1200
1201
1202/*!
1203 * @}
1204 */ /* end of group ADC_Register_Masks */
1205
1206
1207/* ADC - Peripheral instance base addresses */
1208/** Peripheral ADC1 base address */
1209#define ADC1_BASE (0x400C4000u)
1210/** Peripheral ADC1 base pointer */
1211#define ADC1 ((ADC_Type *)ADC1_BASE)
1212/** Array initializer of ADC peripheral base addresses */
1213#define ADC_BASE_ADDRS { 0u, ADC1_BASE }
1214/** Array initializer of ADC peripheral base pointers */
1215#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1 }
1216/** Interrupt vectors for the ADC peripheral type */
1217#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn }
1218
1219/*!
1220 * @}
1221 */ /* end of group ADC_Peripheral_Access_Layer */
1222
1223
1224/* ----------------------------------------------------------------------------
1225 -- ADC_ETC Peripheral Access Layer
1226 ---------------------------------------------------------------------------- */
1227
1228/*!
1229 * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
1230 * @{
1231 */
1232
1233/** ADC_ETC - Register Layout Typedef */
1234typedef struct {
1235 __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */
1236 __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */
1237 __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */
1238 __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */
1239 struct { /* offset: 0x10, array step: 0x28 */
1240 __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG3 Control Register, array offset: 0x10, array step: 0x28 */
1241 __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG3 Counter Register, array offset: 0x14, array step: 0x28 */
1242 __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */
1243 __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */
1244 __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */
1245 __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */
1246 __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */
1247 __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */
1248 __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */
1249 __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */
1250 } TRIG[4];
1251} ADC_ETC_Type;
1252
1253/* ----------------------------------------------------------------------------
1254 -- ADC_ETC Register Masks
1255 ---------------------------------------------------------------------------- */
1256
1257/*!
1258 * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
1259 * @{
1260 */
1261
1262/*! @name CTRL - ADC_ETC Global Control Register */
1263/*! @{ */
1264#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
1265#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
1266#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
1267#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
1268#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
1269#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
1270#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
1271#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
1272#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
1273#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
1274#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
1275#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
1276#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
1277#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
1278#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
1279#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
1280#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
1281#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
1282#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
1283#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
1284#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
1285#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
1286#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
1287#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
1288#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
1289#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
1290#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
1291/*! @} */
1292
1293/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
1294/*! @{ */
1295#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
1296#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
1297#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
1298#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
1299#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
1300#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
1301#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
1302#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
1303#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
1304#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
1305#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
1306#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
1307#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
1308#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
1309#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
1310#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
1311#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
1312#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
1313#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
1314#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
1315#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
1316#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
1317#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
1318#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
1319#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
1320#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
1321#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
1322#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
1323#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
1324#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
1325#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
1326#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
1327#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
1328#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
1329#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
1330#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
1331#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
1332#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
1333#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
1334#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
1335#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
1336#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
1337#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
1338#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
1339#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
1340#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
1341#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
1342#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
1343/*! @} */
1344
1345/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */
1346/*! @{ */
1347#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
1348#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
1349#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)
1350#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
1351#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
1352#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)
1353#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
1354#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
1355#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)
1356#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
1357#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
1358#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)
1359#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
1360#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
1361#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)
1362#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
1363#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
1364#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)
1365#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
1366#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
1367#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)
1368#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
1369#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
1370#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)
1371#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
1372#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
1373#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)
1374#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
1375#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
1376#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)
1377#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
1378#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
1379#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)
1380#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
1381#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
1382#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)
1383#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
1384#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
1385#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)
1386#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
1387#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
1388#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)
1389#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
1390#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
1391#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)
1392#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
1393#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
1394#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)
1395/*! @} */
1396
1397/*! @name DMA_CTRL - ETC DMA control Register */
1398/*! @{ */
1399#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
1400#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
1401#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
1402#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
1403#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
1404#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
1405#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
1406#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
1407#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
1408#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
1409#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
1410#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
1411#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
1412#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
1413#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
1414#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
1415#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
1416#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
1417#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
1418#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
1419#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
1420#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
1421#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
1422#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
1423#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
1424#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
1425#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
1426#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
1427#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
1428#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
1429#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
1430#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
1431#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
1432#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
1433#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
1434#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
1435#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
1436#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
1437#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
1438#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
1439#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
1440#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
1441#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
1442#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
1443#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
1444#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
1445#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
1446#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
1447/*! @} */
1448
1449/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG3 Control Register */
1450/*! @{ */
1451#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
1452#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
1453#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
1454#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
1455#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
1456#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
1457#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
1458#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
1459#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
1460#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
1461#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
1462#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
1463#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
1464#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
1465#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
1466/*! @} */
1467
1468/* The count of ADC_ETC_TRIGn_CTRL */
1469#define ADC_ETC_TRIGn_CTRL_COUNT (4U)
1470
1471/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG3 Counter Register */
1472/*! @{ */
1473#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
1474#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
1475#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
1476#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
1477#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
1478#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
1479/*! @} */
1480
1481/* The count of ADC_ETC_TRIGn_COUNTER */
1482#define ADC_ETC_TRIGn_COUNTER_COUNT (4U)
1483
1484/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
1485/*! @{ */
1486#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
1487#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
1488#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
1489#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
1490#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
1491#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
1492#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
1493#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
1494#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
1495#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
1496#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
1497#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
1498#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
1499#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
1500#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
1501#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
1502#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
1503#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
1504#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
1505#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
1506#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
1507#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
1508#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
1509#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
1510/*! @} */
1511
1512/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
1513#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (4U)
1514
1515/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
1516/*! @{ */
1517#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
1518#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
1519#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
1520#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
1521#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
1522#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
1523#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
1524#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
1525#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
1526#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
1527#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
1528#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
1529#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
1530#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
1531#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
1532#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
1533#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
1534#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
1535#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
1536#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
1537#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
1538#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
1539#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
1540#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
1541/*! @} */
1542
1543/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
1544#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (4U)
1545
1546/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
1547/*! @{ */
1548#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
1549#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
1550#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
1551#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
1552#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
1553#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
1554#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
1555#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
1556#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
1557#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
1558#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
1559#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
1560#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
1561#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
1562#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
1563#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
1564#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
1565#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
1566#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
1567#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
1568#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
1569#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
1570#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
1571#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
1572/*! @} */
1573
1574/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
1575#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (4U)
1576
1577/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
1578/*! @{ */
1579#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
1580#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
1581#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
1582#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
1583#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
1584#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
1585#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
1586#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
1587#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
1588#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
1589#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
1590#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
1591#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
1592#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
1593#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
1594#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
1595#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
1596#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
1597#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
1598#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
1599#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
1600#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
1601#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
1602#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
1603/*! @} */
1604
1605/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
1606#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (4U)
1607
1608/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
1609/*! @{ */
1610#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
1611#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
1612#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
1613#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
1614#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
1615#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
1616/*! @} */
1617
1618/* The count of ADC_ETC_TRIGn_RESULT_1_0 */
1619#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (4U)
1620
1621/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
1622/*! @{ */
1623#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
1624#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
1625#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
1626#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
1627#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
1628#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
1629/*! @} */
1630
1631/* The count of ADC_ETC_TRIGn_RESULT_3_2 */
1632#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (4U)
1633
1634/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
1635/*! @{ */
1636#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
1637#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
1638#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
1639#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
1640#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
1641#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
1642/*! @} */
1643
1644/* The count of ADC_ETC_TRIGn_RESULT_5_4 */
1645#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (4U)
1646
1647/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
1648/*! @{ */
1649#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
1650#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
1651#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
1652#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
1653#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
1654#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
1655/*! @} */
1656
1657/* The count of ADC_ETC_TRIGn_RESULT_7_6 */
1658#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (4U)
1659
1660
1661/*!
1662 * @}
1663 */ /* end of group ADC_ETC_Register_Masks */
1664
1665
1666/* ADC_ETC - Peripheral instance base addresses */
1667/** Peripheral ADC_ETC base address */
1668#define ADC_ETC_BASE (0x403B0000u)
1669/** Peripheral ADC_ETC base pointer */
1670#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
1671/** Array initializer of ADC_ETC peripheral base addresses */
1672#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
1673/** Array initializer of ADC_ETC peripheral base pointers */
1674#define ADC_ETC_BASE_PTRS { ADC_ETC }
1675/** Interrupt vectors for the ADC_ETC peripheral type */
1676#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
1677#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
1678
1679/*!
1680 * @}
1681 */ /* end of group ADC_ETC_Peripheral_Access_Layer */
1682
1683
1684/* ----------------------------------------------------------------------------
1685 -- AIPSTZ Peripheral Access Layer
1686 ---------------------------------------------------------------------------- */
1687
1688/*!
1689 * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
1690 * @{
1691 */
1692
1693/** AIPSTZ - Register Layout Typedef */
1694typedef struct {
1695 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */
1696 uint8_t RESERVED_0[60];
1697 __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
1698 __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
1699 __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
1700 __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
1701 __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
1702} AIPSTZ_Type;
1703
1704/* ----------------------------------------------------------------------------
1705 -- AIPSTZ Register Masks
1706 ---------------------------------------------------------------------------- */
1707
1708/*!
1709 * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
1710 * @{
1711 */
1712
1713/*! @name MPR - Master Priviledge Registers */
1714/*! @{ */
1715#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
1716#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
1717/*! MPROT5
1718 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1719 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1720 * 0bxx0x..This master is not trusted for write accesses.
1721 * 0bxx1x..This master is trusted for write accesses.
1722 * 0bx0xx..This master is not trusted for read accesses.
1723 * 0bx1xx..This master is trusted for read accesses.
1724 * 0b1xxx..Write accesses from this master are allowed to be buffered
1725 */
1726#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
1727#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
1728#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
1729/*! MPROT3
1730 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1731 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1732 * 0bxx0x..This master is not trusted for write accesses.
1733 * 0bxx1x..This master is trusted for write accesses.
1734 * 0bx0xx..This master is not trusted for read accesses.
1735 * 0bx1xx..This master is trusted for read accesses.
1736 * 0b1xxx..Write accesses from this master are allowed to be buffered
1737 */
1738#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
1739#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
1740#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
1741/*! MPROT2
1742 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1743 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1744 * 0bxx0x..This master is not trusted for write accesses.
1745 * 0bxx1x..This master is trusted for write accesses.
1746 * 0bx0xx..This master is not trusted for read accesses.
1747 * 0bx1xx..This master is trusted for read accesses.
1748 * 0b1xxx..Write accesses from this master are allowed to be buffered
1749 */
1750#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
1751#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
1752#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
1753/*! MPROT1
1754 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1755 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1756 * 0bxx0x..This master is not trusted for write accesses.
1757 * 0bxx1x..This master is trusted for write accesses.
1758 * 0bx0xx..This master is not trusted for read accesses.
1759 * 0bx1xx..This master is trusted for read accesses.
1760 * 0b1xxx..Write accesses from this master are allowed to be buffered
1761 */
1762#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
1763#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
1764#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
1765/*! MPROT0
1766 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1767 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1768 * 0bxx0x..This master is not trusted for write accesses.
1769 * 0bxx1x..This master is trusted for write accesses.
1770 * 0bx0xx..This master is not trusted for read accesses.
1771 * 0bx1xx..This master is trusted for read accesses.
1772 * 0b1xxx..Write accesses from this master are allowed to be buffered
1773 */
1774#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
1775/*! @} */
1776
1777/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
1778/*! @{ */
1779#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
1780#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
1781/*! OPAC7
1782 * 0bxxx0..Accesses from an untrusted master are allowed.
1783 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1784 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1785 * 0bxx0x..This peripheral allows write accesses.
1786 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1787 * error response and no peripheral access is initiated on the IPS bus.
1788 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1789 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1790 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1791 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1792 * on the IPS bus.
1793 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1794 */
1795#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
1796#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
1797#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
1798/*! OPAC6
1799 * 0bxxx0..Accesses from an untrusted master are allowed.
1800 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1801 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1802 * 0bxx0x..This peripheral allows write accesses.
1803 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1804 * error response and no peripheral access is initiated on the IPS bus.
1805 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1806 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1807 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1808 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1809 * on the IPS bus.
1810 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1811 */
1812#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
1813#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
1814#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
1815/*! OPAC5
1816 * 0bxxx0..Accesses from an untrusted master are allowed.
1817 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1818 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1819 * 0bxx0x..This peripheral allows write accesses.
1820 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1821 * error response and no peripheral access is initiated on the IPS bus.
1822 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1823 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1824 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1825 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1826 * on the IPS bus.
1827 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1828 */
1829#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
1830#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
1831#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
1832/*! OPAC4
1833 * 0bxxx0..Accesses from an untrusted master are allowed.
1834 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1835 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1836 * 0bxx0x..This peripheral allows write accesses.
1837 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1838 * error response and no peripheral access is initiated on the IPS bus.
1839 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1840 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1841 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1842 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1843 * on the IPS bus.
1844 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1845 */
1846#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
1847#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
1848#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
1849/*! OPAC3
1850 * 0bxxx0..Accesses from an untrusted master are allowed.
1851 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1852 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1853 * 0bxx0x..This peripheral allows write accesses.
1854 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1855 * error response and no peripheral access is initiated on the IPS bus.
1856 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1857 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1858 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1859 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1860 * on the IPS bus.
1861 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1862 */
1863#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
1864#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
1865#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
1866/*! OPAC2
1867 * 0bxxx0..Accesses from an untrusted master are allowed.
1868 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1869 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1870 * 0bxx0x..This peripheral allows write accesses.
1871 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1872 * error response and no peripheral access is initiated on the IPS bus.
1873 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1874 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1875 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1876 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1877 * on the IPS bus.
1878 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1879 */
1880#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
1881#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
1882#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
1883/*! OPAC1
1884 * 0bxxx0..Accesses from an untrusted master are allowed.
1885 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1886 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1887 * 0bxx0x..This peripheral allows write accesses.
1888 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1889 * error response and no peripheral access is initiated on the IPS bus.
1890 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1891 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1892 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1893 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1894 * on the IPS bus.
1895 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1896 */
1897#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
1898#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
1899#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
1900/*! OPAC0
1901 * 0bxxx0..Accesses from an untrusted master are allowed.
1902 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1903 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1904 * 0bxx0x..This peripheral allows write accesses.
1905 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1906 * error response and no peripheral access is initiated on the IPS bus.
1907 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1908 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1909 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1910 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1911 * on the IPS bus.
1912 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1913 */
1914#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
1915/*! @} */
1916
1917/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
1918/*! @{ */
1919#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
1920#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
1921/*! OPAC15
1922 * 0bxxx0..Accesses from an untrusted master are allowed.
1923 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1924 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1925 * 0bxx0x..This peripheral allows write accesses.
1926 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1927 * error response and no peripheral access is initiated on the IPS bus.
1928 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1929 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1930 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1931 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1932 * on the IPS bus.
1933 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1934 */
1935#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
1936#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
1937#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
1938/*! OPAC14
1939 * 0bxxx0..Accesses from an untrusted master are allowed.
1940 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1941 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1942 * 0bxx0x..This peripheral allows write accesses.
1943 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1944 * error response and no peripheral access is initiated on the IPS bus.
1945 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1946 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1947 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1948 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1949 * on the IPS bus.
1950 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1951 */
1952#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
1953#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
1954#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
1955/*! OPAC13
1956 * 0bxxx0..Accesses from an untrusted master are allowed.
1957 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1958 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1959 * 0bxx0x..This peripheral allows write accesses.
1960 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1961 * error response and no peripheral access is initiated on the IPS bus.
1962 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1963 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1964 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1965 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1966 * on the IPS bus.
1967 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1968 */
1969#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
1970#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
1971#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
1972/*! OPAC12
1973 * 0bxxx0..Accesses from an untrusted master are allowed.
1974 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1975 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1976 * 0bxx0x..This peripheral allows write accesses.
1977 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1978 * error response and no peripheral access is initiated on the IPS bus.
1979 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1980 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1981 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1982 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1983 * on the IPS bus.
1984 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1985 */
1986#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
1987#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
1988#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
1989/*! OPAC11
1990 * 0bxxx0..Accesses from an untrusted master are allowed.
1991 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1992 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1993 * 0bxx0x..This peripheral allows write accesses.
1994 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1995 * error response and no peripheral access is initiated on the IPS bus.
1996 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1997 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1998 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1999 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2000 * on the IPS bus.
2001 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2002 */
2003#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
2004#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
2005#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
2006/*! OPAC10
2007 * 0bxxx0..Accesses from an untrusted master are allowed.
2008 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2009 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2010 * 0bxx0x..This peripheral allows write accesses.
2011 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2012 * error response and no peripheral access is initiated on the IPS bus.
2013 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2014 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2015 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2016 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2017 * on the IPS bus.
2018 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2019 */
2020#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
2021#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
2022#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
2023/*! OPAC9
2024 * 0bxxx0..Accesses from an untrusted master are allowed.
2025 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2026 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2027 * 0bxx0x..This peripheral allows write accesses.
2028 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2029 * error response and no peripheral access is initiated on the IPS bus.
2030 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2031 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2032 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2033 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2034 * on the IPS bus.
2035 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2036 */
2037#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
2038#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
2039#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
2040/*! OPAC8
2041 * 0bxxx0..Accesses from an untrusted master are allowed.
2042 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2043 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2044 * 0bxx0x..This peripheral allows write accesses.
2045 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2046 * error response and no peripheral access is initiated on the IPS bus.
2047 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2048 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2049 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2050 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2051 * on the IPS bus.
2052 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2053 */
2054#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
2055/*! @} */
2056
2057/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
2058/*! @{ */
2059#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
2060#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
2061/*! OPAC23
2062 * 0bxxx0..Accesses from an untrusted master are allowed.
2063 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2064 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2065 * 0bxx0x..This peripheral allows write accesses.
2066 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2067 * error response and no peripheral access is initiated on the IPS bus.
2068 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2069 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2070 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2071 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2072 * on the IPS bus.
2073 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2074 */
2075#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
2076#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
2077#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
2078/*! OPAC22
2079 * 0bxxx0..Accesses from an untrusted master are allowed.
2080 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2081 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2082 * 0bxx0x..This peripheral allows write accesses.
2083 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2084 * error response and no peripheral access is initiated on the IPS bus.
2085 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2086 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2087 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2088 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2089 * on the IPS bus.
2090 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2091 */
2092#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
2093#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
2094#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
2095/*! OPAC21
2096 * 0bxxx0..Accesses from an untrusted master are allowed.
2097 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2098 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2099 * 0bxx0x..This peripheral allows write accesses.
2100 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2101 * error response and no peripheral access is initiated on the IPS bus.
2102 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2103 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2104 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2105 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2106 * on the IPS bus.
2107 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2108 */
2109#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
2110#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
2111#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
2112/*! OPAC20
2113 * 0bxxx0..Accesses from an untrusted master are allowed.
2114 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2115 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2116 * 0bxx0x..This peripheral allows write accesses.
2117 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2118 * error response and no peripheral access is initiated on the IPS bus.
2119 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2120 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2121 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2122 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2123 * on the IPS bus.
2124 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2125 */
2126#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
2127#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
2128#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
2129/*! OPAC19
2130 * 0bxxx0..Accesses from an untrusted master are allowed.
2131 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2132 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2133 * 0bxx0x..This peripheral allows write accesses.
2134 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2135 * error response and no peripheral access is initiated on the IPS bus.
2136 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2137 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2138 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2139 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2140 * on the IPS bus.
2141 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2142 */
2143#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
2144#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
2145#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
2146/*! OPAC18
2147 * 0bxxx0..Accesses from an untrusted master are allowed.
2148 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2149 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2150 * 0bxx0x..This peripheral allows write accesses.
2151 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2152 * error response and no peripheral access is initiated on the IPS bus.
2153 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2154 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2155 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2156 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2157 * on the IPS bus.
2158 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2159 */
2160#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
2161#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
2162#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
2163/*! OPAC17
2164 * 0bxxx0..Accesses from an untrusted master are allowed.
2165 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2166 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2167 * 0bxx0x..This peripheral allows write accesses.
2168 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2169 * error response and no peripheral access is initiated on the IPS bus.
2170 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2171 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2172 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2173 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2174 * on the IPS bus.
2175 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2176 */
2177#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
2178#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
2179#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
2180/*! OPAC16
2181 * 0bxxx0..Accesses from an untrusted master are allowed.
2182 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2183 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2184 * 0bxx0x..This peripheral allows write accesses.
2185 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2186 * error response and no peripheral access is initiated on the IPS bus.
2187 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2188 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2189 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2190 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2191 * on the IPS bus.
2192 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2193 */
2194#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
2195/*! @} */
2196
2197/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
2198/*! @{ */
2199#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
2200#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
2201/*! OPAC31
2202 * 0bxxx0..Accesses from an untrusted master are allowed.
2203 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2204 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2205 * 0bxx0x..This peripheral allows write accesses.
2206 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2207 * error response and no peripheral access is initiated on the IPS bus.
2208 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2209 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2210 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2211 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2212 * on the IPS bus.
2213 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2214 */
2215#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
2216#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
2217#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
2218/*! OPAC30
2219 * 0bxxx0..Accesses from an untrusted master are allowed.
2220 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2221 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2222 * 0bxx0x..This peripheral allows write accesses.
2223 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2224 * error response and no peripheral access is initiated on the IPS bus.
2225 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2226 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2227 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2228 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2229 * on the IPS bus.
2230 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2231 */
2232#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
2233#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
2234#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
2235/*! OPAC29
2236 * 0bxxx0..Accesses from an untrusted master are allowed.
2237 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2238 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2239 * 0bxx0x..This peripheral allows write accesses.
2240 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2241 * error response and no peripheral access is initiated on the IPS bus.
2242 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2243 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2244 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2245 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2246 * on the IPS bus.
2247 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2248 */
2249#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
2250#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
2251#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
2252/*! OPAC28
2253 * 0bxxx0..Accesses from an untrusted master are allowed.
2254 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2255 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2256 * 0bxx0x..This peripheral allows write accesses.
2257 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2258 * error response and no peripheral access is initiated on the IPS bus.
2259 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2260 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2261 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2262 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2263 * on the IPS bus.
2264 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2265 */
2266#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
2267#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
2268#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
2269/*! OPAC27
2270 * 0bxxx0..Accesses from an untrusted master are allowed.
2271 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2272 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2273 * 0bxx0x..This peripheral allows write accesses.
2274 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2275 * error response and no peripheral access is initiated on the IPS bus.
2276 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2277 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2278 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2279 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2280 * on the IPS bus.
2281 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2282 */
2283#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
2284#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
2285#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
2286/*! OPAC26
2287 * 0bxxx0..Accesses from an untrusted master are allowed.
2288 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2289 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2290 * 0bxx0x..This peripheral allows write accesses.
2291 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2292 * error response and no peripheral access is initiated on the IPS bus.
2293 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2294 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2295 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2296 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2297 * on the IPS bus.
2298 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2299 */
2300#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
2301#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
2302#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
2303/*! OPAC25
2304 * 0bxxx0..Accesses from an untrusted master are allowed.
2305 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2306 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2307 * 0bxx0x..This peripheral allows write accesses.
2308 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2309 * error response and no peripheral access is initiated on the IPS bus.
2310 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2311 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2312 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2313 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2314 * on the IPS bus.
2315 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2316 */
2317#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
2318#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
2319#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
2320/*! OPAC24
2321 * 0bxxx0..Accesses from an untrusted master are allowed.
2322 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2323 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2324 * 0bxx0x..This peripheral allows write accesses.
2325 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2326 * error response and no peripheral access is initiated on the IPS bus.
2327 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2328 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2329 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2330 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2331 * on the IPS bus.
2332 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2333 */
2334#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
2335/*! @} */
2336
2337/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
2338/*! @{ */
2339#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
2340#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
2341/*! OPAC33
2342 * 0bxxx0..Accesses from an untrusted master are allowed.
2343 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2344 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2345 * 0bxx0x..This peripheral allows write accesses.
2346 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2347 * error response and no peripheral access is initiated on the IPS bus.
2348 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2349 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2350 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2351 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2352 * on the IPS bus.
2353 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2354 */
2355#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
2356#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
2357#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
2358/*! OPAC32
2359 * 0bxxx0..Accesses from an untrusted master are allowed.
2360 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2361 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2362 * 0bxx0x..This peripheral allows write accesses.
2363 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2364 * error response and no peripheral access is initiated on the IPS bus.
2365 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2366 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2367 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2368 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2369 * on the IPS bus.
2370 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2371 */
2372#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
2373/*! @} */
2374
2375
2376/*!
2377 * @}
2378 */ /* end of group AIPSTZ_Register_Masks */
2379
2380
2381/* AIPSTZ - Peripheral instance base addresses */
2382/** Peripheral AIPSTZ1 base address */
2383#define AIPSTZ1_BASE (0x4007C000u)
2384/** Peripheral AIPSTZ1 base pointer */
2385#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
2386/** Peripheral AIPSTZ2 base address */
2387#define AIPSTZ2_BASE (0x4017C000u)
2388/** Peripheral AIPSTZ2 base pointer */
2389#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
2390/** Peripheral AIPSTZ3 base address */
2391#define AIPSTZ3_BASE (0x4027C000u)
2392/** Peripheral AIPSTZ3 base pointer */
2393#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
2394/** Peripheral AIPSTZ4 base address */
2395#define AIPSTZ4_BASE (0x4037C000u)
2396/** Peripheral AIPSTZ4 base pointer */
2397#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
2398/** Array initializer of AIPSTZ peripheral base addresses */
2399#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
2400/** Array initializer of AIPSTZ peripheral base pointers */
2401#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
2402
2403/*!
2404 * @}
2405 */ /* end of group AIPSTZ_Peripheral_Access_Layer */
2406
2407
2408/* ----------------------------------------------------------------------------
2409 -- AOI Peripheral Access Layer
2410 ---------------------------------------------------------------------------- */
2411
2412/*!
2413 * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
2414 * @{
2415 */
2416
2417/** AOI - Register Layout Typedef */
2418typedef struct {
2419 struct { /* offset: 0x0, array step: 0x4 */
2420 __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
2421 __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
2422 } BFCRT[4];
2423} AOI_Type;
2424
2425/* ----------------------------------------------------------------------------
2426 -- AOI Register Masks
2427 ---------------------------------------------------------------------------- */
2428
2429/*!
2430 * @addtogroup AOI_Register_Masks AOI Register Masks
2431 * @{
2432 */
2433
2434/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
2435/*! @{ */
2436#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
2437#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
2438/*! PT1_DC - Product term 1, D input configuration
2439 * 0b00..Force the D input in this product term to a logical zero
2440 * 0b01..Pass the D input in this product term
2441 * 0b10..Complement the D input in this product term
2442 * 0b11..Force the D input in this product term to a logical one
2443 */
2444#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
2445#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
2446#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
2447/*! PT1_CC - Product term 1, C input configuration
2448 * 0b00..Force the C input in this product term to a logical zero
2449 * 0b01..Pass the C input in this product term
2450 * 0b10..Complement the C input in this product term
2451 * 0b11..Force the C input in this product term to a logical one
2452 */
2453#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
2454#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
2455#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
2456/*! PT1_BC - Product term 1, B input configuration
2457 * 0b00..Force the B input in this product term to a logical zero
2458 * 0b01..Pass the B input in this product term
2459 * 0b10..Complement the B input in this product term
2460 * 0b11..Force the B input in this product term to a logical one
2461 */
2462#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
2463#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
2464#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
2465/*! PT1_AC - Product term 1, A input configuration
2466 * 0b00..Force the A input in this product term to a logical zero
2467 * 0b01..Pass the A input in this product term
2468 * 0b10..Complement the A input in this product term
2469 * 0b11..Force the A input in this product term to a logical one
2470 */
2471#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
2472#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
2473#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
2474/*! PT0_DC - Product term 0, D input configuration
2475 * 0b00..Force the D input in this product term to a logical zero
2476 * 0b01..Pass the D input in this product term
2477 * 0b10..Complement the D input in this product term
2478 * 0b11..Force the D input in this product term to a logical one
2479 */
2480#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
2481#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
2482#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
2483/*! PT0_CC - Product term 0, C input configuration
2484 * 0b00..Force the C input in this product term to a logical zero
2485 * 0b01..Pass the C input in this product term
2486 * 0b10..Complement the C input in this product term
2487 * 0b11..Force the C input in this product term to a logical one
2488 */
2489#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
2490#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
2491#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
2492/*! PT0_BC - Product term 0, B input configuration
2493 * 0b00..Force the B input in this product term to a logical zero
2494 * 0b01..Pass the B input in this product term
2495 * 0b10..Complement the B input in this product term
2496 * 0b11..Force the B input in this product term to a logical one
2497 */
2498#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
2499#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
2500#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
2501/*! PT0_AC - Product term 0, A input configuration
2502 * 0b00..Force the A input in this product term to a logical zero
2503 * 0b01..Pass the A input in this product term
2504 * 0b10..Complement the A input in this product term
2505 * 0b11..Force the A input in this product term to a logical one
2506 */
2507#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
2508/*! @} */
2509
2510/* The count of AOI_BFCRT01 */
2511#define AOI_BFCRT01_COUNT (4U)
2512
2513/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
2514/*! @{ */
2515#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
2516#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
2517/*! PT3_DC - Product term 3, D input configuration
2518 * 0b00..Force the D input in this product term to a logical zero
2519 * 0b01..Pass the D input in this product term
2520 * 0b10..Complement the D input in this product term
2521 * 0b11..Force the D input in this product term to a logical one
2522 */
2523#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
2524#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
2525#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
2526/*! PT3_CC - Product term 3, C input configuration
2527 * 0b00..Force the C input in this product term to a logical zero
2528 * 0b01..Pass the C input in this product term
2529 * 0b10..Complement the C input in this product term
2530 * 0b11..Force the C input in this product term to a logical one
2531 */
2532#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
2533#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
2534#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
2535/*! PT3_BC - Product term 3, B input configuration
2536 * 0b00..Force the B input in this product term to a logical zero
2537 * 0b01..Pass the B input in this product term
2538 * 0b10..Complement the B input in this product term
2539 * 0b11..Force the B input in this product term to a logical one
2540 */
2541#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
2542#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
2543#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
2544/*! PT3_AC - Product term 3, A input configuration
2545 * 0b00..Force the A input in this product term to a logical zero
2546 * 0b01..Pass the A input in this product term
2547 * 0b10..Complement the A input in this product term
2548 * 0b11..Force the A input in this product term to a logical one
2549 */
2550#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
2551#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
2552#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
2553/*! PT2_DC - Product term 2, D input configuration
2554 * 0b00..Force the D input in this product term to a logical zero
2555 * 0b01..Pass the D input in this product term
2556 * 0b10..Complement the D input in this product term
2557 * 0b11..Force the D input in this product term to a logical one
2558 */
2559#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
2560#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
2561#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
2562/*! PT2_CC - Product term 2, C input configuration
2563 * 0b00..Force the C input in this product term to a logical zero
2564 * 0b01..Pass the C input in this product term
2565 * 0b10..Complement the C input in this product term
2566 * 0b11..Force the C input in this product term to a logical one
2567 */
2568#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
2569#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
2570#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
2571/*! PT2_BC - Product term 2, B input configuration
2572 * 0b00..Force the B input in this product term to a logical zero
2573 * 0b01..Pass the B input in this product term
2574 * 0b10..Complement the B input in this product term
2575 * 0b11..Force the B input in this product term to a logical one
2576 */
2577#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
2578#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
2579#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
2580/*! PT2_AC - Product term 2, A input configuration
2581 * 0b00..Force the A input in this product term to a logical zero
2582 * 0b01..Pass the A input in this product term
2583 * 0b10..Complement the A input in this product term
2584 * 0b11..Force the A input in this product term to a logical one
2585 */
2586#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
2587/*! @} */
2588
2589/* The count of AOI_BFCRT23 */
2590#define AOI_BFCRT23_COUNT (4U)
2591
2592
2593/*!
2594 * @}
2595 */ /* end of group AOI_Register_Masks */
2596
2597
2598/* AOI - Peripheral instance base addresses */
2599/** Peripheral AOI base address */
2600#define AOI_BASE (0x403B4000u)
2601/** Peripheral AOI base pointer */
2602#define AOI ((AOI_Type *)AOI_BASE)
2603/** Array initializer of AOI peripheral base addresses */
2604#define AOI_BASE_ADDRS { AOI_BASE }
2605/** Array initializer of AOI peripheral base pointers */
2606#define AOI_BASE_PTRS { AOI }
2607
2608/*!
2609 * @}
2610 */ /* end of group AOI_Peripheral_Access_Layer */
2611
2612
2613/* ----------------------------------------------------------------------------
2614 -- BEE Peripheral Access Layer
2615 ---------------------------------------------------------------------------- */
2616
2617/*!
2618 * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer
2619 * @{
2620 */
2621
2622/** BEE - Register Layout Typedef */
2623typedef struct {
2624 __IO uint32_t CTRL; /**< Control Register, offset: 0x0 */
2625 __IO uint32_t ADDR_OFFSET0; /**< Offset region 0 Register, offset: 0x4 */
2626 __IO uint32_t ADDR_OFFSET1; /**< Offset region 1 Register, offset: 0x8 */
2627 __IO uint32_t AES_KEY0_W0; /**< AES Key 0 Register, offset: 0xC */
2628 __IO uint32_t AES_KEY0_W1; /**< AES Key 1 Register, offset: 0x10 */
2629 __IO uint32_t AES_KEY0_W2; /**< AES Key 2 Register, offset: 0x14 */
2630 __IO uint32_t AES_KEY0_W3; /**< AES Key 3 Register, offset: 0x18 */
2631 __IO uint32_t STATUS; /**< Status Register, offset: 0x1C */
2632 __O uint32_t CTR_NONCE0_W0; /**< NONCE00 Register, offset: 0x20 */
2633 __O uint32_t CTR_NONCE0_W1; /**< NONCE01 Register, offset: 0x24 */
2634 __O uint32_t CTR_NONCE0_W2; /**< NONCE02 Register, offset: 0x28 */
2635 __O uint32_t CTR_NONCE0_W3; /**< NONCE03 Register, offset: 0x2C */
2636 __O uint32_t CTR_NONCE1_W0; /**< NONCE10 Register, offset: 0x30 */
2637 __O uint32_t CTR_NONCE1_W1; /**< NONCE11 Register, offset: 0x34 */
2638 __O uint32_t CTR_NONCE1_W2; /**< NONCE12 Register, offset: 0x38 */
2639 __O uint32_t CTR_NONCE1_W3; /**< NONCE13 Register, offset: 0x3C */
2640 __IO uint32_t REGION1_TOP; /**< Region1 Top Address Register, offset: 0x40 */
2641 __IO uint32_t REGION1_BOT; /**< Region1 Bottom Address Register, offset: 0x44 */
2642} BEE_Type;
2643
2644/* ----------------------------------------------------------------------------
2645 -- BEE Register Masks
2646 ---------------------------------------------------------------------------- */
2647
2648/*!
2649 * @addtogroup BEE_Register_Masks BEE Register Masks
2650 * @{
2651 */
2652
2653/*! @name CTRL - Control Register */
2654/*! @{ */
2655#define BEE_CTRL_BEE_ENABLE_MASK (0x1U)
2656#define BEE_CTRL_BEE_ENABLE_SHIFT (0U)
2657/*! BEE_ENABLE
2658 * 0b0..Disable BEE
2659 * 0b1..Enable BEE
2660 */
2661#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
2662#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
2663#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
2664#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
2665#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
2666#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
2667#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
2668#define BEE_CTRL_KEY_VALID_MASK (0x10U)
2669#define BEE_CTRL_KEY_VALID_SHIFT (4U)
2670#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
2671#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
2672#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
2673/*! KEY_REGION_SEL
2674 * 0b0..Load AES key for region0
2675 * 0b1..Load AES key for region1
2676 */
2677#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
2678#define BEE_CTRL_AC_PROT_EN_MASK (0x40U)
2679#define BEE_CTRL_AC_PROT_EN_SHIFT (6U)
2680#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
2681#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
2682#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
2683/*! LITTLE_ENDIAN
2684 * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8,
2685 * B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to
2686 * Byte0 to Byte15.
2687 * 0b1..The input and output data of AES core is not swapped.
2688 */
2689#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
2690#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
2691#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
2692#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
2693#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
2694#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
2695/*! CTRL_AES_MODE_R0
2696 * 0b0..ECB
2697 * 0b1..CTR
2698 */
2699#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
2700#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
2701#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
2702#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
2703#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
2704#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
2705/*! CTRL_AES_MODE_R1
2706 * 0b0..ECB
2707 * 0b1..CTR
2708 */
2709#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
2710#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
2711#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
2712#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
2713#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
2714#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
2715#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
2716#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
2717#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
2718#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
2719#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
2720#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
2721#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
2722#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
2723#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
2724#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
2725#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
2726#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
2727#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
2728#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
2729#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
2730#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
2731#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
2732#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
2733#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
2734#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
2735#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
2736#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
2737#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
2738#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
2739#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
2740#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
2741#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
2742#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
2743#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
2744#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
2745#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
2746#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
2747#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
2748#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
2749#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
2750#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
2751#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
2752/*! @} */
2753
2754/*! @name ADDR_OFFSET0 - Offset region 0 Register */
2755/*! @{ */
2756#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
2757#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
2758#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
2759#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
2760#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
2761#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
2762/*! @} */
2763
2764/*! @name ADDR_OFFSET1 - Offset region 1 Register */
2765/*! @{ */
2766#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)
2767#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)
2768#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
2769#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)
2770#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
2771#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
2772/*! @} */
2773
2774/*! @name AES_KEY0_W0 - AES Key 0 Register */
2775/*! @{ */
2776#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
2777#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
2778/*! KEY0 - AES 128 key from software
2779 */
2780#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
2781/*! @} */
2782
2783/*! @name AES_KEY0_W1 - AES Key 1 Register */
2784/*! @{ */
2785#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
2786#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
2787/*! KEY1 - AES 128 key from software
2788 */
2789#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
2790/*! @} */
2791
2792/*! @name AES_KEY0_W2 - AES Key 2 Register */
2793/*! @{ */
2794#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
2795#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
2796/*! KEY2 - AES 128 key from software
2797 */
2798#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
2799/*! @} */
2800
2801/*! @name AES_KEY0_W3 - AES Key 3 Register */
2802/*! @{ */
2803#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
2804#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
2805/*! KEY3 - AES 128 key from software
2806 */
2807#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
2808/*! @} */
2809
2810/*! @name STATUS - Status Register */
2811/*! @{ */
2812#define BEE_STATUS_IRQ_VEC_MASK (0xFFU)
2813#define BEE_STATUS_IRQ_VEC_SHIFT (0U)
2814#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
2815#define BEE_STATUS_BEE_IDLE_MASK (0x100U)
2816#define BEE_STATUS_BEE_IDLE_SHIFT (8U)
2817#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
2818/*! @} */
2819
2820/*! @name CTR_NONCE0_W0 - NONCE00 Register */
2821/*! @{ */
2822#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
2823#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
2824#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
2825/*! @} */
2826
2827/*! @name CTR_NONCE0_W1 - NONCE01 Register */
2828/*! @{ */
2829#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
2830#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
2831#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
2832/*! @} */
2833
2834/*! @name CTR_NONCE0_W2 - NONCE02 Register */
2835/*! @{ */
2836#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
2837#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
2838#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
2839/*! @} */
2840
2841/*! @name CTR_NONCE0_W3 - NONCE03 Register */
2842/*! @{ */
2843#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
2844#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
2845#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
2846/*! @} */
2847
2848/*! @name CTR_NONCE1_W0 - NONCE10 Register */
2849/*! @{ */
2850#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
2851#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
2852#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
2853/*! @} */
2854
2855/*! @name CTR_NONCE1_W1 - NONCE11 Register */
2856/*! @{ */
2857#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
2858#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
2859#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
2860/*! @} */
2861
2862/*! @name CTR_NONCE1_W2 - NONCE12 Register */
2863/*! @{ */
2864#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
2865#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
2866#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
2867/*! @} */
2868
2869/*! @name CTR_NONCE1_W3 - NONCE13 Register */
2870/*! @{ */
2871#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
2872#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
2873#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
2874/*! @} */
2875
2876/*! @name REGION1_TOP - Region1 Top Address Register */
2877/*! @{ */
2878#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
2879#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
2880/*! REGION1_TOP - Address upper limit of region1
2881 */
2882#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
2883/*! @} */
2884
2885/*! @name REGION1_BOT - Region1 Bottom Address Register */
2886/*! @{ */
2887#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
2888#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
2889/*! REGION1_BOT - Address lower limit of region1
2890 */
2891#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)
2892/*! @} */
2893
2894
2895/*!
2896 * @}
2897 */ /* end of group BEE_Register_Masks */
2898
2899
2900/* BEE - Peripheral instance base addresses */
2901/** Peripheral BEE base address */
2902#define BEE_BASE (0x403EC000u)
2903/** Peripheral BEE base pointer */
2904#define BEE ((BEE_Type *)BEE_BASE)
2905/** Array initializer of BEE peripheral base addresses */
2906#define BEE_BASE_ADDRS { BEE_BASE }
2907/** Array initializer of BEE peripheral base pointers */
2908#define BEE_BASE_PTRS { BEE }
2909
2910/*!
2911 * @}
2912 */ /* end of group BEE_Peripheral_Access_Layer */
2913
2914
2915/* ----------------------------------------------------------------------------
2916 -- CCM Peripheral Access Layer
2917 ---------------------------------------------------------------------------- */
2918
2919/*!
2920 * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
2921 * @{
2922 */
2923
2924/** CCM - Register Layout Typedef */
2925typedef struct {
2926 __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */
2927 uint8_t RESERVED_0[4];
2928 __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */
2929 __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */
2930 __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */
2931 __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */
2932 __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */
2933 __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */
2934 __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */
2935 __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */
2936 __IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */
2937 __IO uint32_t CS2CDR; /**< CCM Clock Divider Register, offset: 0x2C */
2938 __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */
2939 uint8_t RESERVED_1[4];
2940 __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */
2941 uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */
2942 uint8_t RESERVED_2[8];
2943 __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */
2944 uint8_t RESERVED_3[8];
2945 __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */
2946 __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */
2947 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */
2948 __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */
2949 __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */
2950 __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */
2951 __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */
2952 __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */
2953 __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */
2954 __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */
2955 __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */
2956 __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */
2957 uint8_t RESERVED_4[4];
2958 __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */
2959} CCM_Type;
2960
2961/* ----------------------------------------------------------------------------
2962 -- CCM Register Masks
2963 ---------------------------------------------------------------------------- */
2964
2965/*!
2966 * @addtogroup CCM_Register_Masks CCM Register Masks
2967 * @{
2968 */
2969
2970/*! @name CCR - CCM Control Register */
2971/*! @{ */
2972#define CCM_CCR_OSCNT_MASK (0xFFU)
2973#define CCM_CCR_OSCNT_SHIFT (0U)
2974/*! OSCNT - Oscillator ready counter value. These bits define value of 32KHz counter, that serve as
2975 * counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time.
2976 * Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from
2977 * stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for
2978 * the dpll_ip to use and only then the gate in dpll_ip can be opened.
2979 */
2980#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
2981#define CCM_CCR_COSC_EN_MASK (0x1000U)
2982#define CCM_CCR_COSC_EN_SHIFT (12U)
2983/*! COSC_EN
2984 * 0b0..disable on chip oscillator
2985 * 0b1..enable on chip oscillator
2986 */
2987#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
2988#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
2989#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
2990/*! REG_BYPASS_COUNT
2991 * 0b000000..no delay
2992 * 0b000001..1 CKIL clock period delay
2993 * 0b111111..63 CKIL clock periods delay
2994 */
2995#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
2996#define CCM_CCR_RBC_EN_MASK (0x8000000U)
2997#define CCM_CCR_RBC_EN_SHIFT (27U)
2998/*! RBC_EN
2999 * 0b1..REG_BYPASS_COUNTER enabled.
3000 * 0b0..REG_BYPASS_COUNTER disabled
3001 */
3002#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
3003/*! @} */
3004
3005/*! @name CSR - CCM Status Register */
3006/*! @{ */
3007#define CCM_CSR_REF_EN_B_MASK (0x1U)
3008#define CCM_CSR_REF_EN_B_SHIFT (0U)
3009/*! REF_EN_B
3010 * 0b0..value of CCM_REF_EN_B is '0'
3011 * 0b1..value of CCM_REF_EN_B is '1'
3012 */
3013#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
3014#define CCM_CSR_CAMP2_READY_MASK (0x8U)
3015#define CCM_CSR_CAMP2_READY_SHIFT (3U)
3016/*! CAMP2_READY
3017 * 0b0..CAMP2 is not ready.
3018 * 0b1..CAMP2 is ready.
3019 */
3020#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
3021#define CCM_CSR_COSC_READY_MASK (0x20U)
3022#define CCM_CSR_COSC_READY_SHIFT (5U)
3023/*! COSC_READY
3024 * 0b0..on board oscillator is not ready.
3025 * 0b1..on board oscillator is ready.
3026 */
3027#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
3028/*! @} */
3029
3030/*! @name CCSR - CCM Clock Switcher Register */
3031/*! @{ */
3032#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
3033#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
3034/*! PLL3_SW_CLK_SEL
3035 * 0b0..pll3_main_clk
3036 * 0b1..pll3 bypass clock
3037 */
3038#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
3039/*! @} */
3040
3041/*! @name CACRR - CCM Arm Clock Root Register */
3042/*! @{ */
3043#define CCM_CACRR_ARM_PODF_MASK (0x7U)
3044#define CCM_CACRR_ARM_PODF_SHIFT (0U)
3045/*! ARM_PODF
3046 * 0b000..divide by 1
3047 * 0b001..divide by 2
3048 * 0b010..divide by 3
3049 * 0b011..divide by 4
3050 * 0b100..divide by 5
3051 * 0b101..divide by 6
3052 * 0b110..divide by 7
3053 * 0b111..divide by 8
3054 */
3055#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
3056/*! @} */
3057
3058/*! @name CBCDR - CCM Bus Clock Divider Register */
3059/*! @{ */
3060#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)
3061#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)
3062/*! SEMC_CLK_SEL
3063 * 0b0..Periph_clk output will be used as SEMC clock root
3064 * 0b1..SEMC alternative clock will be used as SEMC clock root
3065 */
3066#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
3067#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)
3068#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)
3069/*! SEMC_ALT_CLK_SEL
3070 * 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock
3071 * 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock
3072 */
3073#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
3074#define CCM_CBCDR_IPG_PODF_MASK (0x300U)
3075#define CCM_CBCDR_IPG_PODF_SHIFT (8U)
3076/*! IPG_PODF
3077 * 0b00..divide by 1
3078 * 0b01..divide by 2
3079 * 0b10..divide by 3
3080 * 0b11..divide by 4
3081 */
3082#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
3083#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
3084#define CCM_CBCDR_AHB_PODF_SHIFT (10U)
3085/*! AHB_PODF
3086 * 0b000..divide by 1
3087 * 0b001..divide by 2
3088 * 0b010..divide by 3
3089 * 0b011..divide by 4
3090 * 0b100..divide by 5
3091 * 0b101..divide by 6
3092 * 0b110..divide by 7
3093 * 0b111..divide by 8
3094 */
3095#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
3096#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U)
3097#define CCM_CBCDR_SEMC_PODF_SHIFT (16U)
3098/*! SEMC_PODF
3099 * 0b000..divide by 1
3100 * 0b001..divide by 2
3101 * 0b010..divide by 3
3102 * 0b011..divide by 4
3103 * 0b100..divide by 5
3104 * 0b101..divide by 6
3105 * 0b110..divide by 7
3106 * 0b111..divide by 8
3107 */
3108#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
3109#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
3110#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
3111/*! PERIPH_CLK_SEL
3112 * 0b0..derive clock from pre_periph_clk_sel
3113 * 0b1..derive clock from periph_clk2_clk_divided
3114 */
3115#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
3116#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)
3117#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)
3118/*! PERIPH_CLK2_PODF
3119 * 0b000..divide by 1
3120 * 0b001..divide by 2
3121 * 0b010..divide by 3
3122 * 0b011..divide by 4
3123 * 0b100..divide by 5
3124 * 0b101..divide by 6
3125 * 0b110..divide by 7
3126 * 0b111..divide by 8
3127 */
3128#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
3129/*! @} */
3130
3131/*! @name CBCMR - CCM Bus Clock Multiplexer Register */
3132/*! @{ */
3133#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
3134#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
3135/*! LPSPI_CLK_SEL
3136 * 0b00..derive clock from PLL3 PFD1 clk
3137 * 0b01..derive clock from PLL3 PFD0
3138 * 0b10..derive clock from PLL2
3139 * 0b11..derive clock from PLL2 PFD2
3140 */
3141#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
3142#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
3143#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
3144/*! PERIPH_CLK2_SEL
3145 * 0b00..derive clock from pll3_sw_clk
3146 * 0b01..derive clock from osc_clk
3147 * 0b10..derive clock from pll2_bypass_clk
3148 * 0b11..reserved
3149 */
3150#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
3151#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
3152#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
3153/*! TRACE_CLK_SEL
3154 * 0b00..derive clock from PLL2
3155 * 0b01..derive clock from PLL2 PFD2
3156 * 0b10..derive clock from PLL2 PFD0
3157 * 0b11..derive clock from PLL2 PFD1
3158 */
3159#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
3160#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
3161#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
3162/*! PRE_PERIPH_CLK_SEL
3163 * 0b00..derive clock from PLL2
3164 * 0b01..derive clock from PLL3 PFD3
3165 * 0b10..derive clock from PLL2 PFD3
3166 * 0b11..derive clock from divided PLL6
3167 */
3168#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
3169#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)
3170#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
3171/*! LPSPI_PODF
3172 * 0b000..divide by 1
3173 * 0b001..divide by 2
3174 * 0b010..divide by 3
3175 * 0b011..divide by 4
3176 * 0b100..divide by 5
3177 * 0b101..divide by 6
3178 * 0b110..divide by 7
3179 * 0b111..divide by 8
3180 */
3181#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
3182/*! @} */
3183
3184/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */
3185/*! @{ */
3186#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
3187#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
3188/*! PERCLK_PODF - Divider for perclk podf.
3189 * 0b000000..Divide by 1
3190 * 0b000001..Divide by 2
3191 * 0b000010..Divide by 3
3192 * 0b000011..Divide by 4
3193 * 0b000100..Divide by 5
3194 * 0b000101..Divide by 6
3195 * 0b000110..Divide by 7
3196 * 0b000111..Divide by 8
3197 * 0b001000..Divide by 9
3198 * 0b001001..Divide by 10
3199 * 0b001010..Divide by 11
3200 * 0b001011..Divide by 12
3201 * 0b001100..Divide by 13
3202 * 0b001101..Divide by 14
3203 * 0b001110..Divide by 15
3204 * 0b001111..Divide by 16
3205 * 0b010000..Divide by 17
3206 * 0b010001..Divide by 18
3207 * 0b010010..Divide by 19
3208 * 0b010011..Divide by 20
3209 * 0b010100..Divide by 21
3210 * 0b010101..Divide by 22
3211 * 0b010110..Divide by 23
3212 * 0b010111..Divide by 24
3213 * 0b011000..Divide by 25
3214 * 0b011001..Divide by 26
3215 * 0b011010..Divide by 27
3216 * 0b011011..Divide by 28
3217 * 0b011100..Divide by 29
3218 * 0b011101..Divide by 30
3219 * 0b011110..Divide by 31
3220 * 0b011111..Divide by 32
3221 * 0b100000..Divide by 33
3222 * 0b100001..Divide by 34
3223 * 0b100010..Divide by 35
3224 * 0b100011..Divide by 36
3225 * 0b100100..Divide by 37
3226 * 0b100101..Divide by 38
3227 * 0b100110..Divide by 39
3228 * 0b100111..Divide by 40
3229 * 0b101000..Divide by 41
3230 * 0b101001..Divide by 42
3231 * 0b101010..Divide by 43
3232 * 0b101011..Divide by 44
3233 * 0b101100..Divide by 45
3234 * 0b101101..Divide by 46
3235 * 0b101110..Divide by 47
3236 * 0b101111..Divide by 48
3237 * 0b110000..Divide by 49
3238 * 0b110001..Divide by 50
3239 * 0b110010..Divide by 51
3240 * 0b110011..Divide by 52
3241 * 0b110100..Divide by 53
3242 * 0b110101..Divide by 54
3243 * 0b110110..Divide by 55
3244 * 0b110111..Divide by 56
3245 * 0b111000..Divide by 57
3246 * 0b111001..Divide by 58
3247 * 0b111010..Divide by 59
3248 * 0b111011..Divide by 60
3249 * 0b111100..Divide by 61
3250 * 0b111101..Divide by 62
3251 * 0b111110..Divide by 63
3252 * 0b111111..Divide by 64
3253 */
3254#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
3255#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
3256#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
3257/*! PERCLK_CLK_SEL
3258 * 0b0..derive clock from ipg clk root
3259 * 0b1..derive clock from osc_clk
3260 */
3261#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
3262#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
3263#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
3264/*! SAI1_CLK_SEL
3265 * 0b00..derive clock from PLL3 PFD2
3266 * 0b01..Reserved
3267 * 0b10..derive clock from PLL4
3268 * 0b11..Reserved
3269 */
3270#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
3271#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)
3272#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)
3273/*! SAI2_CLK_SEL
3274 * 0b00..derive clock from PLL3 PFD2
3275 * 0b01..Reserved
3276 * 0b10..derive clock from PLL4
3277 * 0b11..Reserved
3278 */
3279#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
3280#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
3281#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
3282/*! SAI3_CLK_SEL
3283 * 0b00..derive clock from PLL3 PFD2
3284 * 0b01..Reserved
3285 * 0b10..derive clock from PLL4
3286 * 0b11..Reserved
3287 */
3288#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
3289#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
3290#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
3291/*! FLEXSPI_PODF
3292 * 0b000..divide by 1
3293 * 0b001..divide by 2
3294 * 0b010..divide by 3
3295 * 0b011..divide by 4
3296 * 0b100..divide by 5
3297 * 0b101..divide by 6
3298 * 0b110..divide by 7
3299 * 0b111..divide by 8
3300 */
3301#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
3302#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
3303#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
3304/*! FLEXSPI_CLK_SEL
3305 * 0b00..derive clock from semc_clk_root_pre
3306 * 0b01..derive clock from pll3_sw_clk
3307 * 0b10..derive clock from PLL2 PFD2
3308 * 0b11..derive clock from PLL3 PFD0
3309 */
3310#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
3311/*! @} */
3312
3313/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */
3314/*! @{ */
3315#define CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK (0x180000U)
3316#define CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT (19U)
3317/*! FLEXIO1_CLK_SEL
3318 * 0b00..derive clock from PLL4 divided clock
3319 * 0b01..derive clock from PLL3 PFD2 clock
3320 * 0b10..Reserved
3321 * 0b11..derive clock from pll3_sw_clk
3322 */
3323#define CCM_CSCMR2_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK)
3324/*! @} */
3325
3326/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */
3327/*! @{ */
3328#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
3329#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
3330/*! UART_CLK_PODF - Divider for uart clock podf.
3331 * 0b000000..Divide by 1
3332 * 0b000001..Divide by 2
3333 * 0b000010..Divide by 3
3334 * 0b000011..Divide by 4
3335 * 0b000100..Divide by 5
3336 * 0b000101..Divide by 6
3337 * 0b000110..Divide by 7
3338 * 0b000111..Divide by 8
3339 * 0b001000..Divide by 9
3340 * 0b001001..Divide by 10
3341 * 0b001010..Divide by 11
3342 * 0b001011..Divide by 12
3343 * 0b001100..Divide by 13
3344 * 0b001101..Divide by 14
3345 * 0b001110..Divide by 15
3346 * 0b001111..Divide by 16
3347 * 0b010000..Divide by 17
3348 * 0b010001..Divide by 18
3349 * 0b010010..Divide by 19
3350 * 0b010011..Divide by 20
3351 * 0b010100..Divide by 21
3352 * 0b010101..Divide by 22
3353 * 0b010110..Divide by 23
3354 * 0b010111..Divide by 24
3355 * 0b011000..Divide by 25
3356 * 0b011001..Divide by 26
3357 * 0b011010..Divide by 27
3358 * 0b011011..Divide by 28
3359 * 0b011100..Divide by 29
3360 * 0b011101..Divide by 30
3361 * 0b011110..Divide by 31
3362 * 0b011111..Divide by 32
3363 * 0b100000..Divide by 33
3364 * 0b100001..Divide by 34
3365 * 0b100010..Divide by 35
3366 * 0b100011..Divide by 36
3367 * 0b100100..Divide by 37
3368 * 0b100101..Divide by 38
3369 * 0b100110..Divide by 39
3370 * 0b100111..Divide by 40
3371 * 0b101000..Divide by 41
3372 * 0b101001..Divide by 42
3373 * 0b101010..Divide by 43
3374 * 0b101011..Divide by 44
3375 * 0b101100..Divide by 45
3376 * 0b101101..Divide by 46
3377 * 0b101110..Divide by 47
3378 * 0b101111..Divide by 48
3379 * 0b110000..Divide by 49
3380 * 0b110001..Divide by 50
3381 * 0b110010..Divide by 51
3382 * 0b110011..Divide by 52
3383 * 0b110100..Divide by 53
3384 * 0b110101..Divide by 54
3385 * 0b110110..Divide by 55
3386 * 0b110111..Divide by 56
3387 * 0b111000..Divide by 57
3388 * 0b111001..Divide by 58
3389 * 0b111010..Divide by 59
3390 * 0b111011..Divide by 60
3391 * 0b111100..Divide by 61
3392 * 0b111101..Divide by 62
3393 * 0b111110..Divide by 63
3394 * 0b111111..Divide by 64
3395 */
3396#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
3397#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)
3398#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
3399/*! UART_CLK_SEL
3400 * 0b0..derive clock from pll3_80m
3401 * 0b1..derive clock from osc_clk
3402 */
3403#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
3404#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)
3405#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
3406/*! TRACE_PODF
3407 * 0b00..divide by 1
3408 * 0b01..divide by 2
3409 * 0b10..divide by 3
3410 * 0b11..divide by 4
3411 */
3412#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
3413/*! @} */
3414
3415/*! @name CS1CDR - CCM Clock Divider Register */
3416/*! @{ */
3417#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
3418#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
3419/*! SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower
3420 * than 300Mhz, the predivider can be used to achieve this.
3421 * 0b000000..Divide by 1
3422 * 0b000001..Divide by 2
3423 * 0b000010..Divide by 3
3424 * 0b000011..Divide by 4
3425 * 0b000100..Divide by 5
3426 * 0b000101..Divide by 6
3427 * 0b000110..Divide by 7
3428 * 0b000111..Divide by 8
3429 * 0b001000..Divide by 9
3430 * 0b001001..Divide by 10
3431 * 0b001010..Divide by 11
3432 * 0b001011..Divide by 12
3433 * 0b001100..Divide by 13
3434 * 0b001101..Divide by 14
3435 * 0b001110..Divide by 15
3436 * 0b001111..Divide by 16
3437 * 0b010000..Divide by 17
3438 * 0b010001..Divide by 18
3439 * 0b010010..Divide by 19
3440 * 0b010011..Divide by 20
3441 * 0b010100..Divide by 21
3442 * 0b010101..Divide by 22
3443 * 0b010110..Divide by 23
3444 * 0b010111..Divide by 24
3445 * 0b011000..Divide by 25
3446 * 0b011001..Divide by 26
3447 * 0b011010..Divide by 27
3448 * 0b011011..Divide by 28
3449 * 0b011100..Divide by 29
3450 * 0b011101..Divide by 30
3451 * 0b011110..Divide by 31
3452 * 0b011111..Divide by 32
3453 * 0b100000..Divide by 33
3454 * 0b100001..Divide by 34
3455 * 0b100010..Divide by 35
3456 * 0b100011..Divide by 36
3457 * 0b100100..Divide by 37
3458 * 0b100101..Divide by 38
3459 * 0b100110..Divide by 39
3460 * 0b100111..Divide by 40
3461 * 0b101000..Divide by 41
3462 * 0b101001..Divide by 42
3463 * 0b101010..Divide by 43
3464 * 0b101011..Divide by 44
3465 * 0b101100..Divide by 45
3466 * 0b101101..Divide by 46
3467 * 0b101110..Divide by 47
3468 * 0b101111..Divide by 48
3469 * 0b110000..Divide by 49
3470 * 0b110001..Divide by 50
3471 * 0b110010..Divide by 51
3472 * 0b110011..Divide by 52
3473 * 0b110100..Divide by 53
3474 * 0b110101..Divide by 54
3475 * 0b110110..Divide by 55
3476 * 0b110111..Divide by 56
3477 * 0b111000..Divide by 57
3478 * 0b111001..Divide by 58
3479 * 0b111010..Divide by 59
3480 * 0b111011..Divide by 60
3481 * 0b111100..Divide by 61
3482 * 0b111101..Divide by 62
3483 * 0b111110..Divide by 63
3484 * 0b111111..Divide by 64
3485 */
3486#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
3487#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
3488#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
3489/*! SAI1_CLK_PRED
3490 * 0b000..divide by 1
3491 * 0b001..divide by 2
3492 * 0b010..divide by 3
3493 * 0b011..divide by 4
3494 * 0b100..divide by 5
3495 * 0b101..divide by 6
3496 * 0b110..divide by 7
3497 * 0b111..divide by 8
3498 */
3499#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
3500#define CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK (0xE00U)
3501#define CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT (9U)
3502/*! FLEXIO1_CLK_PRED
3503 * 0b000..divide by 1
3504 * 0b001..divide by 2
3505 * 0b010..divide by 3
3506 * 0b011..divide by 4
3507 * 0b100..divide by 5
3508 * 0b101..divide by 6
3509 * 0b110..divide by 7
3510 * 0b111..divide by 8
3511 */
3512#define CCM_CS1CDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK)
3513#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
3514#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
3515/*! SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower
3516 * than 300Mhz, the predivider can be used to achieve this.
3517 * 0b000000..Divide by 1
3518 * 0b000001..Divide by 2
3519 * 0b000010..Divide by 3
3520 * 0b000011..Divide by 4
3521 * 0b000100..Divide by 5
3522 * 0b000101..Divide by 6
3523 * 0b000110..Divide by 7
3524 * 0b000111..Divide by 8
3525 * 0b001000..Divide by 9
3526 * 0b001001..Divide by 10
3527 * 0b001010..Divide by 11
3528 * 0b001011..Divide by 12
3529 * 0b001100..Divide by 13
3530 * 0b001101..Divide by 14
3531 * 0b001110..Divide by 15
3532 * 0b001111..Divide by 16
3533 * 0b010000..Divide by 17
3534 * 0b010001..Divide by 18
3535 * 0b010010..Divide by 19
3536 * 0b010011..Divide by 20
3537 * 0b010100..Divide by 21
3538 * 0b010101..Divide by 22
3539 * 0b010110..Divide by 23
3540 * 0b010111..Divide by 24
3541 * 0b011000..Divide by 25
3542 * 0b011001..Divide by 26
3543 * 0b011010..Divide by 27
3544 * 0b011011..Divide by 28
3545 * 0b011100..Divide by 29
3546 * 0b011101..Divide by 30
3547 * 0b011110..Divide by 31
3548 * 0b011111..Divide by 32
3549 * 0b100000..Divide by 33
3550 * 0b100001..Divide by 34
3551 * 0b100010..Divide by 35
3552 * 0b100011..Divide by 36
3553 * 0b100100..Divide by 37
3554 * 0b100101..Divide by 38
3555 * 0b100110..Divide by 39
3556 * 0b100111..Divide by 40
3557 * 0b101000..Divide by 41
3558 * 0b101001..Divide by 42
3559 * 0b101010..Divide by 43
3560 * 0b101011..Divide by 44
3561 * 0b101100..Divide by 45
3562 * 0b101101..Divide by 46
3563 * 0b101110..Divide by 47
3564 * 0b101111..Divide by 48
3565 * 0b110000..Divide by 49
3566 * 0b110001..Divide by 50
3567 * 0b110010..Divide by 51
3568 * 0b110011..Divide by 52
3569 * 0b110100..Divide by 53
3570 * 0b110101..Divide by 54
3571 * 0b110110..Divide by 55
3572 * 0b110111..Divide by 56
3573 * 0b111000..Divide by 57
3574 * 0b111001..Divide by 58
3575 * 0b111010..Divide by 59
3576 * 0b111011..Divide by 60
3577 * 0b111100..Divide by 61
3578 * 0b111101..Divide by 62
3579 * 0b111110..Divide by 63
3580 * 0b111111..Divide by 64
3581 */
3582#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
3583#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
3584#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
3585/*! SAI3_CLK_PRED
3586 * 0b000..divide by 1
3587 * 0b001..divide by 2
3588 * 0b010..divide by 3
3589 * 0b011..divide by 4
3590 * 0b100..divide by 5
3591 * 0b101..divide by 6
3592 * 0b110..divide by 7
3593 * 0b111..divide by 8
3594 */
3595#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
3596#define CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK (0xE000000U)
3597#define CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT (25U)
3598/*! FLEXIO1_CLK_PODF - Divider for flexio1 clock. Divider should be updated when output clock is gated.
3599 * 0b000..Divide by 1
3600 * 0b001..Divide by 2
3601 * 0b010..Divide by 3
3602 * 0b011..Divide by 4
3603 * 0b100..Divide by 5
3604 * 0b101..Divide by 6
3605 * 0b110..Divide by 7
3606 * 0b111..Divide by 8
3607 */
3608#define CCM_CS1CDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK)
3609/*! @} */
3610
3611/*! @name CS2CDR - CCM Clock Divider Register */
3612/*! @{ */
3613#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)
3614#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)
3615/*! SAI2_CLK_PODF - Divider for sai2 clock podf. The input clock to this divider should be lower
3616 * than 300Mhz, the predivider can be used to achieve this.
3617 * 0b000000..Divide by 1
3618 * 0b000001..Divide by 2
3619 * 0b000010..Divide by 3
3620 * 0b000011..Divide by 4
3621 * 0b000100..Divide by 5
3622 * 0b000101..Divide by 6
3623 * 0b000110..Divide by 7
3624 * 0b000111..Divide by 8
3625 * 0b001000..Divide by 9
3626 * 0b001001..Divide by 10
3627 * 0b001010..Divide by 11
3628 * 0b001011..Divide by 12
3629 * 0b001100..Divide by 13
3630 * 0b001101..Divide by 14
3631 * 0b001110..Divide by 15
3632 * 0b001111..Divide by 16
3633 * 0b010000..Divide by 17
3634 * 0b010001..Divide by 18
3635 * 0b010010..Divide by 19
3636 * 0b010011..Divide by 20
3637 * 0b010100..Divide by 21
3638 * 0b010101..Divide by 22
3639 * 0b010110..Divide by 23
3640 * 0b010111..Divide by 24
3641 * 0b011000..Divide by 25
3642 * 0b011001..Divide by 26
3643 * 0b011010..Divide by 27
3644 * 0b011011..Divide by 28
3645 * 0b011100..Divide by 29
3646 * 0b011101..Divide by 30
3647 * 0b011110..Divide by 31
3648 * 0b011111..Divide by 32
3649 * 0b100000..Divide by 33
3650 * 0b100001..Divide by 34
3651 * 0b100010..Divide by 35
3652 * 0b100011..Divide by 36
3653 * 0b100100..Divide by 37
3654 * 0b100101..Divide by 38
3655 * 0b100110..Divide by 39
3656 * 0b100111..Divide by 40
3657 * 0b101000..Divide by 41
3658 * 0b101001..Divide by 42
3659 * 0b101010..Divide by 43
3660 * 0b101011..Divide by 44
3661 * 0b101100..Divide by 45
3662 * 0b101101..Divide by 46
3663 * 0b101110..Divide by 47
3664 * 0b101111..Divide by 48
3665 * 0b110000..Divide by 49
3666 * 0b110001..Divide by 50
3667 * 0b110010..Divide by 51
3668 * 0b110011..Divide by 52
3669 * 0b110100..Divide by 53
3670 * 0b110101..Divide by 54
3671 * 0b110110..Divide by 55
3672 * 0b110111..Divide by 56
3673 * 0b111000..Divide by 57
3674 * 0b111001..Divide by 58
3675 * 0b111010..Divide by 59
3676 * 0b111011..Divide by 60
3677 * 0b111100..Divide by 61
3678 * 0b111101..Divide by 62
3679 * 0b111110..Divide by 63
3680 * 0b111111..Divide by 64
3681 */
3682#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
3683#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)
3684#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)
3685/*! SAI2_CLK_PRED
3686 * 0b000..divide by 1
3687 * 0b001..divide by 2
3688 * 0b010..divide by 3
3689 * 0b011..divide by 4
3690 * 0b100..divide by 5
3691 * 0b101..divide by 6
3692 * 0b110..divide by 7
3693 * 0b111..divide by 8
3694 */
3695#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
3696/*! @} */
3697
3698/*! @name CDCDR - CCM D1 Clock Divider Register */
3699/*! @{ */
3700#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
3701#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
3702/*! SPDIF0_CLK_SEL
3703 * 0b00..derive clock from PLL4
3704 * 0b01..derive clock from PLL3 PFD2
3705 * 0b10..Reserved
3706 * 0b11..derive clock from pll3_sw_clk
3707 */
3708#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
3709#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
3710#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
3711/*! SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
3712 * 0b000..Divide by 1
3713 * 0b001..Divide by 2
3714 * 0b010..Divide by 3
3715 * 0b011..Divide by 4
3716 * 0b100..Divide by 5
3717 * 0b101..Divide by 6
3718 * 0b110..Divide by 7
3719 * 0b111..Divide by 8
3720 */
3721#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
3722#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
3723#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
3724/*! SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated.
3725 * 0b000..Divide by 1
3726 * 0b001..Divide by 2
3727 * 0b010..Divide by 3
3728 * 0b011..Divide by 4
3729 * 0b100..Divide by 5
3730 * 0b101..Divide by 6
3731 * 0b110..Divide by 7
3732 * 0b111..Divide by 8
3733 */
3734#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
3735/*! @} */
3736
3737/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */
3738/*! @{ */
3739#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
3740#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
3741/*! LPI2C_CLK_SEL
3742 * 0b0..derive clock from pll3_60m
3743 * 0b1..derive clock from osc_clk
3744 */
3745#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
3746#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
3747#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
3748/*! LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is
3749 * gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used
3750 * to achieve this.
3751 * 0b000000..Divide by 1
3752 * 0b000001..Divide by 2
3753 * 0b000010..Divide by 3
3754 * 0b000011..Divide by 4
3755 * 0b000100..Divide by 5
3756 * 0b000101..Divide by 6
3757 * 0b000110..Divide by 7
3758 * 0b000111..Divide by 8
3759 * 0b001000..Divide by 9
3760 * 0b001001..Divide by 10
3761 * 0b001010..Divide by 11
3762 * 0b001011..Divide by 12
3763 * 0b001100..Divide by 13
3764 * 0b001101..Divide by 14
3765 * 0b001110..Divide by 15
3766 * 0b001111..Divide by 16
3767 * 0b010000..Divide by 17
3768 * 0b010001..Divide by 18
3769 * 0b010010..Divide by 19
3770 * 0b010011..Divide by 20
3771 * 0b010100..Divide by 21
3772 * 0b010101..Divide by 22
3773 * 0b010110..Divide by 23
3774 * 0b010111..Divide by 24
3775 * 0b011000..Divide by 25
3776 * 0b011001..Divide by 26
3777 * 0b011010..Divide by 27
3778 * 0b011011..Divide by 28
3779 * 0b011100..Divide by 29
3780 * 0b011101..Divide by 30
3781 * 0b011110..Divide by 31
3782 * 0b011111..Divide by 32
3783 * 0b100000..Divide by 33
3784 * 0b100001..Divide by 34
3785 * 0b100010..Divide by 35
3786 * 0b100011..Divide by 36
3787 * 0b100100..Divide by 37
3788 * 0b100101..Divide by 38
3789 * 0b100110..Divide by 39
3790 * 0b100111..Divide by 40
3791 * 0b101000..Divide by 41
3792 * 0b101001..Divide by 42
3793 * 0b101010..Divide by 43
3794 * 0b101011..Divide by 44
3795 * 0b101100..Divide by 45
3796 * 0b101101..Divide by 46
3797 * 0b101110..Divide by 47
3798 * 0b101111..Divide by 48
3799 * 0b110000..Divide by 49
3800 * 0b110001..Divide by 50
3801 * 0b110010..Divide by 51
3802 * 0b110011..Divide by 52
3803 * 0b110100..Divide by 53
3804 * 0b110101..Divide by 54
3805 * 0b110110..Divide by 55
3806 * 0b110111..Divide by 56
3807 * 0b111000..Divide by 57
3808 * 0b111001..Divide by 58
3809 * 0b111010..Divide by 59
3810 * 0b111011..Divide by 60
3811 * 0b111100..Divide by 61
3812 * 0b111101..Divide by 62
3813 * 0b111110..Divide by 63
3814 * 0b111111..Divide by 64
3815 */
3816#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
3817/*! @} */
3818
3819/*! @name CDHIPR - CCM Divider Handshake In-Process Register */
3820/*! @{ */
3821#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)
3822#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)
3823/*! SEMC_PODF_BUSY
3824 * 0b0..divider is not busy and its value represents the actual division.
3825 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
3826 * value of the division factor, and after the handshake the written value of the semc_podf will be applied.
3827 */
3828#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
3829#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
3830#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
3831/*! AHB_PODF_BUSY
3832 * 0b0..divider is not busy and its value represents the actual division.
3833 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
3834 * value of the division factor, and after the handshake the written value of the ahb_podf will be applied.
3835 */
3836#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
3837#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)
3838#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)
3839/*! PERIPH2_CLK_SEL_BUSY
3840 * 0b0..mux is not busy and its value represents the actual division.
3841 * 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the
3842 * previous value of select, and after the handshake periph2_clk_sel value will be applied.
3843 */
3844#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
3845#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
3846#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
3847/*! PERIPH_CLK_SEL_BUSY
3848 * 0b0..mux is not busy and its value represents the actual division.
3849 * 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the
3850 * previous value of select, and after the handshake periph_clk_sel value will be applied.
3851 */
3852#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
3853#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)
3854#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)
3855/*! ARM_PODF_BUSY
3856 * 0b0..divider is not busy and its value represents the actual division.
3857 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
3858 * value of the division factor, and after the handshake the written value of the arm_podf will be applied.
3859 */
3860#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
3861/*! @} */
3862
3863/*! @name CLPCR - CCM Low Power Control Register */
3864/*! @{ */
3865#define CCM_CLPCR_LPM_MASK (0x3U)
3866#define CCM_CLPCR_LPM_SHIFT (0U)
3867/*! LPM
3868 * 0b00..Remain in run mode
3869 * 0b01..Transfer to wait mode
3870 * 0b10..Transfer to stop mode
3871 * 0b11..Reserved
3872 */
3873#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
3874#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
3875#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
3876/*! ARM_CLK_DIS_ON_LPM
3877 * 0b0..ARM clock enabled on wait mode.
3878 * 0b1..ARM clock disabled on wait mode. .
3879 */
3880#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
3881#define CCM_CLPCR_SBYOS_MASK (0x40U)
3882#define CCM_CLPCR_SBYOS_SHIFT (6U)
3883/*! SBYOS
3884 * 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain
3885 * asserted - '0' and cosc_pwrdown will remain de asserted - '0')
3886 * 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be
3887 * deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will
3888 * be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will
3889 * continue with the exit from the STOP mode process.
3890 */
3891#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
3892#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
3893#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
3894/*! DIS_REF_OSC
3895 * 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.
3896 * 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'
3897 */
3898#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
3899#define CCM_CLPCR_VSTBY_MASK (0x100U)
3900#define CCM_CLPCR_VSTBY_SHIFT (8U)
3901/*! VSTBY
3902 * 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')
3903 * 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').
3904 */
3905#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
3906#define CCM_CLPCR_STBY_COUNT_MASK (0x600U)
3907#define CCM_CLPCR_STBY_COUNT_SHIFT (9U)
3908/*! STBY_COUNT
3909 * 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles
3910 * 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles
3911 * 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles
3912 * 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles
3913 */
3914#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
3915#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
3916#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
3917/*! COSC_PWRDOWN
3918 * 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.
3919 * 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.
3920 */
3921#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
3922#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)
3923#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)
3924#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
3925#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)
3926#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)
3927#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
3928#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
3929#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
3930/*! MASK_CORE0_WFI
3931 * 0b0..WFI of core0 is not masked
3932 * 0b1..WFI of core0 is masked
3933 */
3934#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
3935#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
3936#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
3937/*! MASK_SCU_IDLE
3938 * 0b1..SCU IDLE is masked
3939 * 0b0..SCU IDLE is not masked
3940 */
3941#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
3942#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
3943#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
3944/*! MASK_L2CC_IDLE
3945 * 0b1..L2CC IDLE is masked
3946 * 0b0..L2CC IDLE is not masked
3947 */
3948#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
3949/*! @} */
3950
3951/*! @name CISR - CCM Interrupt Status Register */
3952/*! @{ */
3953#define CCM_CISR_LRF_PLL_MASK (0x1U)
3954#define CCM_CISR_LRF_PLL_SHIFT (0U)
3955/*! LRF_PLL
3956 * 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs
3957 * 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs
3958 */
3959#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
3960#define CCM_CISR_COSC_READY_MASK (0x40U)
3961#define CCM_CISR_COSC_READY_SHIFT (6U)
3962/*! COSC_READY
3963 * 0b0..interrupt is not generated due to on board oscillator ready
3964 * 0b1..interrupt generated due to on board oscillator ready
3965 */
3966#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
3967#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)
3968#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)
3969/*! SEMC_PODF_LOADED
3970 * 0b0..interrupt is not generated due to frequency change of semc_podf
3971 * 0b1..interrupt generated due to frequency change of semc_podf
3972 */
3973#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
3974#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
3975#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
3976/*! PERIPH2_CLK_SEL_LOADED
3977 * 0b0..interrupt is not generated due to frequency change of periph2_clk_sel
3978 * 0b1..interrupt generated due to frequency change of periph2_clk_sel
3979 */
3980#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
3981#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
3982#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
3983/*! AHB_PODF_LOADED
3984 * 0b0..interrupt is not generated due to frequency change of ahb_podf
3985 * 0b1..interrupt generated due to frequency change of ahb_podf
3986 */
3987#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
3988#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
3989#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
3990/*! PERIPH_CLK_SEL_LOADED
3991 * 0b0..interrupt is not generated due to update of periph_clk_sel.
3992 * 0b1..interrupt generated due to update of periph_clk_sel.
3993 */
3994#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
3995#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)
3996#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)
3997/*! ARM_PODF_LOADED
3998 * 0b0..interrupt is not generated due to frequency change of arm_podf
3999 * 0b1..interrupt generated due to frequency change of arm_podf
4000 */
4001#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
4002/*! @} */
4003
4004/*! @name CIMR - CCM Interrupt Mask Register */
4005/*! @{ */
4006#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
4007#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
4008/*! MASK_LRF_PLL
4009 * 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created
4010 * 0b1..mask interrupt due to lrf of PLLs
4011 */
4012#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
4013#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
4014#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
4015/*! MASK_COSC_READY
4016 * 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created
4017 * 0b1..mask interrupt due to on board oscillator ready
4018 */
4019#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
4020#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)
4021#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)
4022/*! MASK_SEMC_PODF_LOADED
4023 * 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created
4024 * 0b1..mask interrupt due to frequency change of semc_podf
4025 */
4026#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
4027#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
4028#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
4029/*! MASK_PERIPH2_CLK_SEL_LOADED
4030 * 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created
4031 * 0b1..mask interrupt due to update of periph2_clk_sel
4032 */
4033#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
4034#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
4035#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
4036/*! MASK_AHB_PODF_LOADED
4037 * 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created
4038 * 0b1..mask interrupt due to frequency change of ahb_podf
4039 */
4040#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
4041#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
4042#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
4043/*! MASK_PERIPH_CLK_SEL_LOADED
4044 * 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created
4045 * 0b1..mask interrupt due to update of periph_clk_sel
4046 */
4047#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
4048#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)
4049#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)
4050/*! ARM_PODF_LOADED
4051 * 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created
4052 * 0b1..mask interrupt due to frequency change of arm_podf
4053 */
4054#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
4055/*! @} */
4056
4057/*! @name CCOSR - CCM Clock Output Source Register */
4058/*! @{ */
4059#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
4060#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
4061/*! CLKO1_SEL
4062 * 0b0000..pll3_sw_clk (divided by 2)
4063 * 0b0001..PLL2 (divided by 2)
4064 * 0b0010..ENET PLL (divided by 2)
4065 * 0b0011..Reserved
4066 * 0b0101..Reserved
4067 * 0b0110..Reserved
4068 * 0b1010..Reserved
4069 * 0b1011..ahb_clk_root
4070 * 0b1100..ipg_clk_root
4071 * 0b1101..perclk_root
4072 * 0b1110..Reserved
4073 * 0b1111..pll4_main_clk
4074 */
4075#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
4076#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
4077#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
4078/*! CLKO1_DIV
4079 * 0b000..divide by 1
4080 * 0b001..divide by 2
4081 * 0b010..divide by 3
4082 * 0b011..divide by 4
4083 * 0b100..divide by 5
4084 * 0b101..divide by 6
4085 * 0b110..divide by 7
4086 * 0b111..divide by 8
4087 */
4088#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
4089#define CCM_CCOSR_CLKO1_EN_MASK (0x80U)
4090#define CCM_CCOSR_CLKO1_EN_SHIFT (7U)
4091/*! CLKO1_EN
4092 * 0b0..CCM_CLKO1 disabled.
4093 * 0b1..CCM_CLKO1 enabled.
4094 */
4095#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
4096#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
4097#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
4098/*! CLK_OUT_SEL
4099 * 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock
4100 * 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock
4101 */
4102#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
4103#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
4104#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
4105/*! CLKO2_SEL
4106 * 0b00101..Reserved
4107 * 0b00110..lpi2c_clk_root
4108 * 0b01110..osc_clk
4109 * 0b10000..lpspi_clk_root
4110 * 0b10010..sai1_clk_root
4111 * 0b10011..sai2_clk_root
4112 * 0b10100..sai3_clk_root
4113 * 0b10110..trace_clk_root
4114 * 0b11011..flexspi_clk_root
4115 * 0b11100..uart_clk_root
4116 * 0b11101..spdif0_clk_root
4117 * 0b11111..Reserved
4118 */
4119#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
4120#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
4121#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
4122/*! CLKO2_DIV
4123 * 0b000..divide by 1
4124 * 0b001..divide by 2
4125 * 0b010..divide by 3
4126 * 0b011..divide by 4
4127 * 0b100..divide by 5
4128 * 0b101..divide by 6
4129 * 0b110..divide by 7
4130 * 0b111..divide by 8
4131 */
4132#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
4133#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
4134#define CCM_CCOSR_CLKO2_EN_SHIFT (24U)
4135/*! CLKO2_EN
4136 * 0b0..CCM_CLKO2 disabled.
4137 * 0b1..CCM_CLKO2 enabled.
4138 */
4139#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
4140/*! @} */
4141
4142/*! @name CGPR - CCM General Purpose Register */
4143/*! @{ */
4144#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
4145#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
4146/*! PMIC_DELAY_SCALER
4147 * 0b0..clock is not divided
4148 * 0b1..clock is divided /8
4149 */
4150#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
4151#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
4152#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
4153/*! EFUSE_PROG_SUPPLY_GATE
4154 * 0b0..fuse programing supply voltage is gated off to the efuse module
4155 * 0b1..allow fuse programing.
4156 */
4157#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
4158#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
4159#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
4160/*! SYS_MEM_DS_CTRL
4161 * 0b00..Disable memory DS mode always
4162 * 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled
4163 * 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode
4164 */
4165#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
4166#define CCM_CGPR_FPL_MASK (0x10000U)
4167#define CCM_CGPR_FPL_SHIFT (16U)
4168/*! FPL - Fast PLL enable.
4169 * 0b0..Engage PLL enable default way.
4170 * 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.
4171 */
4172#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
4173#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
4174#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
4175/*! INT_MEM_CLK_LPM
4176 * 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode
4177 * 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low
4178 * Power Modes (WAIT and STOP without power gating)
4179 */
4180#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
4181/*! @} */
4182
4183/*! @name CCGR0 - CCM Clock Gating Register 0 */
4184/*! @{ */
4185#define CCM_CCGR0_CG0_MASK (0x3U)
4186#define CCM_CCGR0_CG0_SHIFT (0U)
4187#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
4188#define CCM_CCGR0_CG1_MASK (0xCU)
4189#define CCM_CCGR0_CG1_SHIFT (2U)
4190#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
4191#define CCM_CCGR0_CG2_MASK (0x30U)
4192#define CCM_CCGR0_CG2_SHIFT (4U)
4193#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
4194#define CCM_CCGR0_CG3_MASK (0xC0U)
4195#define CCM_CCGR0_CG3_SHIFT (6U)
4196#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
4197#define CCM_CCGR0_CG4_MASK (0x300U)
4198#define CCM_CCGR0_CG4_SHIFT (8U)
4199#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
4200#define CCM_CCGR0_CG5_MASK (0xC00U)
4201#define CCM_CCGR0_CG5_SHIFT (10U)
4202#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
4203#define CCM_CCGR0_CG6_MASK (0x3000U)
4204#define CCM_CCGR0_CG6_SHIFT (12U)
4205#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
4206#define CCM_CCGR0_CG7_MASK (0xC000U)
4207#define CCM_CCGR0_CG7_SHIFT (14U)
4208#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
4209#define CCM_CCGR0_CG8_MASK (0x30000U)
4210#define CCM_CCGR0_CG8_SHIFT (16U)
4211#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
4212#define CCM_CCGR0_CG9_MASK (0xC0000U)
4213#define CCM_CCGR0_CG9_SHIFT (18U)
4214#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
4215#define CCM_CCGR0_CG10_MASK (0x300000U)
4216#define CCM_CCGR0_CG10_SHIFT (20U)
4217#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
4218#define CCM_CCGR0_CG11_MASK (0xC00000U)
4219#define CCM_CCGR0_CG11_SHIFT (22U)
4220#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
4221#define CCM_CCGR0_CG12_MASK (0x3000000U)
4222#define CCM_CCGR0_CG12_SHIFT (24U)
4223#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
4224#define CCM_CCGR0_CG13_MASK (0xC000000U)
4225#define CCM_CCGR0_CG13_SHIFT (26U)
4226#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
4227#define CCM_CCGR0_CG14_MASK (0x30000000U)
4228#define CCM_CCGR0_CG14_SHIFT (28U)
4229#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
4230#define CCM_CCGR0_CG15_MASK (0xC0000000U)
4231#define CCM_CCGR0_CG15_SHIFT (30U)
4232#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
4233/*! @} */
4234
4235/*! @name CCGR1 - CCM Clock Gating Register 1 */
4236/*! @{ */
4237#define CCM_CCGR1_CG0_MASK (0x3U)
4238#define CCM_CCGR1_CG0_SHIFT (0U)
4239#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
4240#define CCM_CCGR1_CG1_MASK (0xCU)
4241#define CCM_CCGR1_CG1_SHIFT (2U)
4242#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
4243#define CCM_CCGR1_CG2_MASK (0x30U)
4244#define CCM_CCGR1_CG2_SHIFT (4U)
4245#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
4246#define CCM_CCGR1_CG3_MASK (0xC0U)
4247#define CCM_CCGR1_CG3_SHIFT (6U)
4248#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
4249#define CCM_CCGR1_CG4_MASK (0x300U)
4250#define CCM_CCGR1_CG4_SHIFT (8U)
4251#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
4252#define CCM_CCGR1_CG5_MASK (0xC00U)
4253#define CCM_CCGR1_CG5_SHIFT (10U)
4254#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
4255#define CCM_CCGR1_CG6_MASK (0x3000U)
4256#define CCM_CCGR1_CG6_SHIFT (12U)
4257#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
4258#define CCM_CCGR1_CG7_MASK (0xC000U)
4259#define CCM_CCGR1_CG7_SHIFT (14U)
4260#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
4261#define CCM_CCGR1_CG8_MASK (0x30000U)
4262#define CCM_CCGR1_CG8_SHIFT (16U)
4263#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
4264#define CCM_CCGR1_CG9_MASK (0xC0000U)
4265#define CCM_CCGR1_CG9_SHIFT (18U)
4266#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
4267#define CCM_CCGR1_CG10_MASK (0x300000U)
4268#define CCM_CCGR1_CG10_SHIFT (20U)
4269#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
4270#define CCM_CCGR1_CG11_MASK (0xC00000U)
4271#define CCM_CCGR1_CG11_SHIFT (22U)
4272#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
4273#define CCM_CCGR1_CG12_MASK (0x3000000U)
4274#define CCM_CCGR1_CG12_SHIFT (24U)
4275#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
4276#define CCM_CCGR1_CG13_MASK (0xC000000U)
4277#define CCM_CCGR1_CG13_SHIFT (26U)
4278#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
4279#define CCM_CCGR1_CG14_MASK (0x30000000U)
4280#define CCM_CCGR1_CG14_SHIFT (28U)
4281#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
4282#define CCM_CCGR1_CG15_MASK (0xC0000000U)
4283#define CCM_CCGR1_CG15_SHIFT (30U)
4284#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
4285/*! @} */
4286
4287/*! @name CCGR2 - CCM Clock Gating Register 2 */
4288/*! @{ */
4289#define CCM_CCGR2_CG0_MASK (0x3U)
4290#define CCM_CCGR2_CG0_SHIFT (0U)
4291#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
4292#define CCM_CCGR2_CG1_MASK (0xCU)
4293#define CCM_CCGR2_CG1_SHIFT (2U)
4294#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
4295#define CCM_CCGR2_CG2_MASK (0x30U)
4296#define CCM_CCGR2_CG2_SHIFT (4U)
4297#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
4298#define CCM_CCGR2_CG3_MASK (0xC0U)
4299#define CCM_CCGR2_CG3_SHIFT (6U)
4300#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
4301#define CCM_CCGR2_CG4_MASK (0x300U)
4302#define CCM_CCGR2_CG4_SHIFT (8U)
4303#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
4304#define CCM_CCGR2_CG5_MASK (0xC00U)
4305#define CCM_CCGR2_CG5_SHIFT (10U)
4306#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
4307#define CCM_CCGR2_CG6_MASK (0x3000U)
4308#define CCM_CCGR2_CG6_SHIFT (12U)
4309#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
4310#define CCM_CCGR2_CG7_MASK (0xC000U)
4311#define CCM_CCGR2_CG7_SHIFT (14U)
4312#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
4313#define CCM_CCGR2_CG8_MASK (0x30000U)
4314#define CCM_CCGR2_CG8_SHIFT (16U)
4315#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
4316#define CCM_CCGR2_CG9_MASK (0xC0000U)
4317#define CCM_CCGR2_CG9_SHIFT (18U)
4318#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
4319#define CCM_CCGR2_CG10_MASK (0x300000U)
4320#define CCM_CCGR2_CG10_SHIFT (20U)
4321#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
4322#define CCM_CCGR2_CG11_MASK (0xC00000U)
4323#define CCM_CCGR2_CG11_SHIFT (22U)
4324#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
4325#define CCM_CCGR2_CG12_MASK (0x3000000U)
4326#define CCM_CCGR2_CG12_SHIFT (24U)
4327#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
4328#define CCM_CCGR2_CG13_MASK (0xC000000U)
4329#define CCM_CCGR2_CG13_SHIFT (26U)
4330#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
4331#define CCM_CCGR2_CG14_MASK (0x30000000U)
4332#define CCM_CCGR2_CG14_SHIFT (28U)
4333#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
4334#define CCM_CCGR2_CG15_MASK (0xC0000000U)
4335#define CCM_CCGR2_CG15_SHIFT (30U)
4336#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
4337/*! @} */
4338
4339/*! @name CCGR3 - CCM Clock Gating Register 3 */
4340/*! @{ */
4341#define CCM_CCGR3_CG0_MASK (0x3U)
4342#define CCM_CCGR3_CG0_SHIFT (0U)
4343#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
4344#define CCM_CCGR3_CG1_MASK (0xCU)
4345#define CCM_CCGR3_CG1_SHIFT (2U)
4346#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
4347#define CCM_CCGR3_CG2_MASK (0x30U)
4348#define CCM_CCGR3_CG2_SHIFT (4U)
4349#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
4350#define CCM_CCGR3_CG3_MASK (0xC0U)
4351#define CCM_CCGR3_CG3_SHIFT (6U)
4352#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
4353#define CCM_CCGR3_CG4_MASK (0x300U)
4354#define CCM_CCGR3_CG4_SHIFT (8U)
4355#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
4356#define CCM_CCGR3_CG5_MASK (0xC00U)
4357#define CCM_CCGR3_CG5_SHIFT (10U)
4358#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
4359#define CCM_CCGR3_CG6_MASK (0x3000U)
4360#define CCM_CCGR3_CG6_SHIFT (12U)
4361#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
4362#define CCM_CCGR3_CG7_MASK (0xC000U)
4363#define CCM_CCGR3_CG7_SHIFT (14U)
4364#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
4365#define CCM_CCGR3_CG8_MASK (0x30000U)
4366#define CCM_CCGR3_CG8_SHIFT (16U)
4367#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
4368#define CCM_CCGR3_CG9_MASK (0xC0000U)
4369#define CCM_CCGR3_CG9_SHIFT (18U)
4370#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
4371#define CCM_CCGR3_CG10_MASK (0x300000U)
4372#define CCM_CCGR3_CG10_SHIFT (20U)
4373#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
4374#define CCM_CCGR3_CG11_MASK (0xC00000U)
4375#define CCM_CCGR3_CG11_SHIFT (22U)
4376#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
4377#define CCM_CCGR3_CG12_MASK (0x3000000U)
4378#define CCM_CCGR3_CG12_SHIFT (24U)
4379#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
4380#define CCM_CCGR3_CG13_MASK (0xC000000U)
4381#define CCM_CCGR3_CG13_SHIFT (26U)
4382#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
4383#define CCM_CCGR3_CG14_MASK (0x30000000U)
4384#define CCM_CCGR3_CG14_SHIFT (28U)
4385/*! CG14 - The OCRAM clock cannot be turned off when the CM cache is running on this device.
4386 */
4387#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
4388#define CCM_CCGR3_CG15_MASK (0xC0000000U)
4389#define CCM_CCGR3_CG15_SHIFT (30U)
4390#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
4391/*! @} */
4392
4393/*! @name CCGR4 - CCM Clock Gating Register 4 */
4394/*! @{ */
4395#define CCM_CCGR4_CG0_MASK (0x3U)
4396#define CCM_CCGR4_CG0_SHIFT (0U)
4397#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
4398#define CCM_CCGR4_CG1_MASK (0xCU)
4399#define CCM_CCGR4_CG1_SHIFT (2U)
4400#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
4401#define CCM_CCGR4_CG2_MASK (0x30U)
4402#define CCM_CCGR4_CG2_SHIFT (4U)
4403#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
4404#define CCM_CCGR4_CG3_MASK (0xC0U)
4405#define CCM_CCGR4_CG3_SHIFT (6U)
4406#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
4407#define CCM_CCGR4_CG4_MASK (0x300U)
4408#define CCM_CCGR4_CG4_SHIFT (8U)
4409#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
4410#define CCM_CCGR4_CG5_MASK (0xC00U)
4411#define CCM_CCGR4_CG5_SHIFT (10U)
4412#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
4413#define CCM_CCGR4_CG6_MASK (0x3000U)
4414#define CCM_CCGR4_CG6_SHIFT (12U)
4415#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
4416#define CCM_CCGR4_CG7_MASK (0xC000U)
4417#define CCM_CCGR4_CG7_SHIFT (14U)
4418#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
4419#define CCM_CCGR4_CG8_MASK (0x30000U)
4420#define CCM_CCGR4_CG8_SHIFT (16U)
4421#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
4422#define CCM_CCGR4_CG9_MASK (0xC0000U)
4423#define CCM_CCGR4_CG9_SHIFT (18U)
4424#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
4425#define CCM_CCGR4_CG10_MASK (0x300000U)
4426#define CCM_CCGR4_CG10_SHIFT (20U)
4427#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
4428#define CCM_CCGR4_CG11_MASK (0xC00000U)
4429#define CCM_CCGR4_CG11_SHIFT (22U)
4430#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
4431#define CCM_CCGR4_CG12_MASK (0x3000000U)
4432#define CCM_CCGR4_CG12_SHIFT (24U)
4433#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
4434#define CCM_CCGR4_CG13_MASK (0xC000000U)
4435#define CCM_CCGR4_CG13_SHIFT (26U)
4436#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
4437#define CCM_CCGR4_CG14_MASK (0x30000000U)
4438#define CCM_CCGR4_CG14_SHIFT (28U)
4439#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
4440#define CCM_CCGR4_CG15_MASK (0xC0000000U)
4441#define CCM_CCGR4_CG15_SHIFT (30U)
4442#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
4443/*! @} */
4444
4445/*! @name CCGR5 - CCM Clock Gating Register 5 */
4446/*! @{ */
4447#define CCM_CCGR5_CG0_MASK (0x3U)
4448#define CCM_CCGR5_CG0_SHIFT (0U)
4449#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
4450#define CCM_CCGR5_CG1_MASK (0xCU)
4451#define CCM_CCGR5_CG1_SHIFT (2U)
4452#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
4453#define CCM_CCGR5_CG2_MASK (0x30U)
4454#define CCM_CCGR5_CG2_SHIFT (4U)
4455#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
4456#define CCM_CCGR5_CG3_MASK (0xC0U)
4457#define CCM_CCGR5_CG3_SHIFT (6U)
4458#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
4459#define CCM_CCGR5_CG4_MASK (0x300U)
4460#define CCM_CCGR5_CG4_SHIFT (8U)
4461#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
4462#define CCM_CCGR5_CG5_MASK (0xC00U)
4463#define CCM_CCGR5_CG5_SHIFT (10U)
4464#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
4465#define CCM_CCGR5_CG6_MASK (0x3000U)
4466#define CCM_CCGR5_CG6_SHIFT (12U)
4467#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
4468#define CCM_CCGR5_CG7_MASK (0xC000U)
4469#define CCM_CCGR5_CG7_SHIFT (14U)
4470#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
4471#define CCM_CCGR5_CG8_MASK (0x30000U)
4472#define CCM_CCGR5_CG8_SHIFT (16U)
4473#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
4474#define CCM_CCGR5_CG9_MASK (0xC0000U)
4475#define CCM_CCGR5_CG9_SHIFT (18U)
4476#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
4477#define CCM_CCGR5_CG10_MASK (0x300000U)
4478#define CCM_CCGR5_CG10_SHIFT (20U)
4479#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
4480#define CCM_CCGR5_CG11_MASK (0xC00000U)
4481#define CCM_CCGR5_CG11_SHIFT (22U)
4482#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
4483#define CCM_CCGR5_CG12_MASK (0x3000000U)
4484#define CCM_CCGR5_CG12_SHIFT (24U)
4485#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
4486#define CCM_CCGR5_CG13_MASK (0xC000000U)
4487#define CCM_CCGR5_CG13_SHIFT (26U)
4488#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
4489#define CCM_CCGR5_CG14_MASK (0x30000000U)
4490#define CCM_CCGR5_CG14_SHIFT (28U)
4491#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
4492#define CCM_CCGR5_CG15_MASK (0xC0000000U)
4493#define CCM_CCGR5_CG15_SHIFT (30U)
4494#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
4495/*! @} */
4496
4497/*! @name CCGR6 - CCM Clock Gating Register 6 */
4498/*! @{ */
4499#define CCM_CCGR6_CG0_MASK (0x3U)
4500#define CCM_CCGR6_CG0_SHIFT (0U)
4501#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
4502#define CCM_CCGR6_CG1_MASK (0xCU)
4503#define CCM_CCGR6_CG1_SHIFT (2U)
4504#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
4505#define CCM_CCGR6_CG2_MASK (0x30U)
4506#define CCM_CCGR6_CG2_SHIFT (4U)
4507#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
4508#define CCM_CCGR6_CG3_MASK (0xC0U)
4509#define CCM_CCGR6_CG3_SHIFT (6U)
4510#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
4511#define CCM_CCGR6_CG4_MASK (0x300U)
4512#define CCM_CCGR6_CG4_SHIFT (8U)
4513#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
4514#define CCM_CCGR6_CG5_MASK (0xC00U)
4515#define CCM_CCGR6_CG5_SHIFT (10U)
4516#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
4517#define CCM_CCGR6_CG6_MASK (0x3000U)
4518#define CCM_CCGR6_CG6_SHIFT (12U)
4519#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
4520#define CCM_CCGR6_CG7_MASK (0xC000U)
4521#define CCM_CCGR6_CG7_SHIFT (14U)
4522#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
4523#define CCM_CCGR6_CG8_MASK (0x30000U)
4524#define CCM_CCGR6_CG8_SHIFT (16U)
4525#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
4526#define CCM_CCGR6_CG9_MASK (0xC0000U)
4527#define CCM_CCGR6_CG9_SHIFT (18U)
4528#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
4529#define CCM_CCGR6_CG10_MASK (0x300000U)
4530#define CCM_CCGR6_CG10_SHIFT (20U)
4531#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
4532#define CCM_CCGR6_CG11_MASK (0xC00000U)
4533#define CCM_CCGR6_CG11_SHIFT (22U)
4534#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
4535#define CCM_CCGR6_CG12_MASK (0x3000000U)
4536#define CCM_CCGR6_CG12_SHIFT (24U)
4537#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
4538#define CCM_CCGR6_CG13_MASK (0xC000000U)
4539#define CCM_CCGR6_CG13_SHIFT (26U)
4540#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
4541#define CCM_CCGR6_CG14_MASK (0x30000000U)
4542#define CCM_CCGR6_CG14_SHIFT (28U)
4543#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
4544#define CCM_CCGR6_CG15_MASK (0xC0000000U)
4545#define CCM_CCGR6_CG15_SHIFT (30U)
4546#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
4547/*! @} */
4548
4549/*! @name CMEOR - CCM Module Enable Overide Register */
4550/*! @{ */
4551#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
4552#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
4553/*! MOD_EN_OV_GPT
4554 * 0b0..don't override module enable signal
4555 * 0b1..override module enable signal
4556 */
4557#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
4558#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
4559#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
4560/*! MOD_EN_OV_PIT
4561 * 0b0..don't override module enable signal
4562 * 0b1..override module enable signal
4563 */
4564#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
4565#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
4566#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
4567/*! MOD_EN_OV_TRNG
4568 * 0b0..don't override module enable signal
4569 * 0b1..override module enable signal
4570 */
4571#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
4572/*! @} */
4573
4574
4575/*!
4576 * @}
4577 */ /* end of group CCM_Register_Masks */
4578
4579
4580/* CCM - Peripheral instance base addresses */
4581/** Peripheral CCM base address */
4582#define CCM_BASE (0x400FC000u)
4583/** Peripheral CCM base pointer */
4584#define CCM ((CCM_Type *)CCM_BASE)
4585/** Array initializer of CCM peripheral base addresses */
4586#define CCM_BASE_ADDRS { CCM_BASE }
4587/** Array initializer of CCM peripheral base pointers */
4588#define CCM_BASE_PTRS { CCM }
4589/** Interrupt vectors for the CCM peripheral type */
4590#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }
4591
4592/*!
4593 * @}
4594 */ /* end of group CCM_Peripheral_Access_Layer */
4595
4596
4597/* ----------------------------------------------------------------------------
4598 -- CCM_ANALOG Peripheral Access Layer
4599 ---------------------------------------------------------------------------- */
4600
4601/*!
4602 * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
4603 * @{
4604 */
4605
4606/** CCM_ANALOG - Register Layout Typedef */
4607typedef struct {
4608 uint8_t RESERVED_0[16];
4609 __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */
4610 __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */
4611 __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */
4612 __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */
4613 uint8_t RESERVED_1[16];
4614 __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */
4615 __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */
4616 __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */
4617 __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */
4618 __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */
4619 uint8_t RESERVED_2[12];
4620 __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */
4621 uint8_t RESERVED_3[12];
4622 __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */
4623 uint8_t RESERVED_4[12];
4624 __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */
4625 __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */
4626 __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */
4627 __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */
4628 __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */
4629 uint8_t RESERVED_5[12];
4630 __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */
4631 uint8_t RESERVED_6[76];
4632 __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */
4633 __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */
4634 __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */
4635 __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */
4636 __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */
4637 __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */
4638 __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */
4639 __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */
4640 __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */
4641 __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */
4642 __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */
4643 __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */
4644 uint8_t RESERVED_7[64];
4645 __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */
4646 __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */
4647 __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */
4648 __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */
4649 __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */
4650 __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */
4651 __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */
4652 __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */
4653 __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */
4654 __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */
4655 __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */
4656 __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */
4657} CCM_ANALOG_Type;
4658
4659/* ----------------------------------------------------------------------------
4660 -- CCM_ANALOG Register Masks
4661 ---------------------------------------------------------------------------- */
4662
4663/*!
4664 * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
4665 * @{
4666 */
4667
4668/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */
4669/*! @{ */
4670#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)
4671#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)
4672#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
4673#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)
4674#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)
4675/*! EN_USB_CLKS
4676 * 0b0..PLL outputs for USBPHYn off.
4677 * 0b1..PLL outputs for USBPHYn on.
4678 */
4679#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
4680#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)
4681#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)
4682#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
4683#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)
4684#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)
4685#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
4686#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)
4687#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
4688/*! BYPASS_CLK_SRC
4689 * 0b00..Select the 24MHz oscillator as source.
4690 */
4691#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
4692#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)
4693#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)
4694#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
4695#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)
4696#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)
4697#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
4698/*! @} */
4699
4700/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */
4701/*! @{ */
4702#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)
4703#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
4704#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
4705#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
4706#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
4707/*! EN_USB_CLKS
4708 * 0b0..PLL outputs for USBPHYn off.
4709 * 0b1..PLL outputs for USBPHYn on.
4710 */
4711#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
4712#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)
4713#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)
4714#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
4715#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)
4716#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)
4717#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
4718#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
4719#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
4720/*! BYPASS_CLK_SRC
4721 * 0b00..Select the 24MHz oscillator as source.
4722 */
4723#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
4724#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)
4725#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)
4726#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
4727#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)
4728#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)
4729#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
4730/*! @} */
4731
4732/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */
4733/*! @{ */
4734#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)
4735#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
4736#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
4737#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
4738#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
4739/*! EN_USB_CLKS
4740 * 0b0..PLL outputs for USBPHYn off.
4741 * 0b1..PLL outputs for USBPHYn on.
4742 */
4743#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
4744#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)
4745#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)
4746#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
4747#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)
4748#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)
4749#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
4750#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
4751#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
4752/*! BYPASS_CLK_SRC
4753 * 0b00..Select the 24MHz oscillator as source.
4754 */
4755#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
4756#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)
4757#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)
4758#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
4759#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)
4760#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)
4761#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
4762/*! @} */
4763
4764/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */
4765/*! @{ */
4766#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)
4767#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
4768#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
4769#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
4770#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
4771/*! EN_USB_CLKS
4772 * 0b0..PLL outputs for USBPHYn off.
4773 * 0b1..PLL outputs for USBPHYn on.
4774 */
4775#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
4776#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)
4777#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)
4778#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
4779#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)
4780#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)
4781#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
4782#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
4783#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
4784/*! BYPASS_CLK_SRC
4785 * 0b00..Select the 24MHz oscillator as source.
4786 */
4787#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
4788#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)
4789#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)
4790#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
4791#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)
4792#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)
4793#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
4794/*! @} */
4795
4796/*! @name PLL_SYS - Analog System PLL Control Register */
4797/*! @{ */
4798#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)
4799#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)
4800#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
4801#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)
4802#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)
4803#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
4804#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)
4805#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)
4806#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
4807#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)
4808#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)
4809/*! BYPASS_CLK_SRC
4810 * 0b00..Select the 24MHz oscillator as source.
4811 */
4812#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
4813#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)
4814#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)
4815#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
4816#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)
4817#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)
4818#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
4819/*! @} */
4820
4821/*! @name PLL_SYS_SET - Analog System PLL Control Register */
4822/*! @{ */
4823#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)
4824#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)
4825#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
4826#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)
4827#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)
4828#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
4829#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)
4830#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)
4831#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
4832#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
4833#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
4834/*! BYPASS_CLK_SRC
4835 * 0b00..Select the 24MHz oscillator as source.
4836 */
4837#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
4838#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)
4839#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)
4840#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
4841#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)
4842#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)
4843#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
4844/*! @} */
4845
4846/*! @name PLL_SYS_CLR - Analog System PLL Control Register */
4847/*! @{ */
4848#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)
4849#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)
4850#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
4851#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)
4852#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)
4853#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
4854#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)
4855#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)
4856#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
4857#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
4858#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
4859/*! BYPASS_CLK_SRC
4860 * 0b00..Select the 24MHz oscillator as source.
4861 */
4862#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
4863#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)
4864#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)
4865#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
4866#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)
4867#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)
4868#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
4869/*! @} */
4870
4871/*! @name PLL_SYS_TOG - Analog System PLL Control Register */
4872/*! @{ */
4873#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)
4874#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)
4875#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
4876#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)
4877#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)
4878#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
4879#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)
4880#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)
4881#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
4882#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
4883#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
4884/*! BYPASS_CLK_SRC
4885 * 0b00..Select the 24MHz oscillator as source.
4886 */
4887#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
4888#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)
4889#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)
4890#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
4891#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)
4892#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)
4893#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
4894/*! @} */
4895
4896/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */
4897/*! @{ */
4898#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)
4899#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)
4900#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
4901#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)
4902#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)
4903/*! ENABLE - Enable bit
4904 * 0b0..Spread spectrum modulation disabled
4905 * 0b1..Soread spectrum modulation enabled
4906 */
4907#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
4908#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)
4909#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)
4910#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
4911/*! @} */
4912
4913/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */
4914/*! @{ */
4915#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)
4916#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)
4917#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
4918/*! @} */
4919
4920/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */
4921/*! @{ */
4922#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)
4923#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)
4924#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
4925/*! @} */
4926
4927/*! @name PLL_AUDIO - Analog Audio PLL control Register */
4928/*! @{ */
4929#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
4930#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
4931#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
4932#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)
4933#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)
4934#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
4935#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)
4936#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)
4937#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
4938#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
4939#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
4940/*! BYPASS_CLK_SRC
4941 * 0b00..Select the 24MHz oscillator as source.
4942 * 0b10..Reserved1
4943 * 0b11..Reserved2
4944 */
4945#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
4946#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)
4947#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)
4948#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
4949#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
4950#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
4951/*! POST_DIV_SELECT
4952 * 0b00..Divide by 4.
4953 * 0b01..Divide by 2.
4954 * 0b10..Divide by 1.
4955 * 0b11..Reserved
4956 */
4957#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
4958#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)
4959#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)
4960#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
4961/*! @} */
4962
4963/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */
4964/*! @{ */
4965#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
4966#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
4967#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
4968#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)
4969#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
4970#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
4971#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)
4972#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)
4973#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
4974#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
4975#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
4976/*! BYPASS_CLK_SRC
4977 * 0b00..Select the 24MHz oscillator as source.
4978 * 0b10..Reserved1
4979 * 0b11..Reserved2
4980 */
4981#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
4982#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)
4983#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)
4984#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
4985#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
4986#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
4987/*! POST_DIV_SELECT
4988 * 0b00..Divide by 4.
4989 * 0b01..Divide by 2.
4990 * 0b10..Divide by 1.
4991 * 0b11..Reserved
4992 */
4993#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
4994#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)
4995#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)
4996#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)
4997/*! @} */
4998
4999/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */
5000/*! @{ */
5001#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)
5002#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)
5003#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
5004#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)
5005#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)
5006#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)
5007#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)
5008#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)
5009#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
5010#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
5011#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
5012/*! BYPASS_CLK_SRC
5013 * 0b00..Select the 24MHz oscillator as source.
5014 * 0b10..Reserved1
5015 * 0b11..Reserved2
5016 */
5017#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
5018#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)
5019#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)
5020#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)
5021#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
5022#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
5023/*! POST_DIV_SELECT
5024 * 0b00..Divide by 4.
5025 * 0b01..Divide by 2.
5026 * 0b10..Divide by 1.
5027 * 0b11..Reserved
5028 */
5029#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
5030#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)
5031#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)
5032#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)
5033/*! @} */
5034
5035/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */
5036/*! @{ */
5037#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)
5038#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)
5039#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
5040#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)
5041#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)
5042#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)
5043#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)
5044#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)
5045#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
5046#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
5047#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
5048/*! BYPASS_CLK_SRC
5049 * 0b00..Select the 24MHz oscillator as source.
5050 * 0b10..Reserved1
5051 * 0b11..Reserved2
5052 */
5053#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
5054#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)
5055#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)
5056#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)
5057#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
5058#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
5059/*! POST_DIV_SELECT
5060 * 0b00..Divide by 4.
5061 * 0b01..Divide by 2.
5062 * 0b10..Divide by 1.
5063 * 0b11..Reserved
5064 */
5065#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
5066#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)
5067#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)
5068#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)
5069/*! @} */
5070
5071/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */
5072/*! @{ */
5073#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)
5074#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)
5075#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
5076/*! @} */
5077
5078/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */
5079/*! @{ */
5080#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)
5081#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)
5082#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
5083/*! @} */
5084
5085/*! @name PLL_ENET - Analog ENET PLL Control Register */
5086/*! @{ */
5087#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)
5088#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)
5089#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
5090#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)
5091#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
5092/*! BYPASS_CLK_SRC
5093 * 0b00..Select the 24MHz oscillator as source.
5094 * 0b10..Reserved1
5095 * 0b11..Reserved2
5096 */
5097#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
5098#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)
5099#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)
5100#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
5101#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK (0x400000U)
5102#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT (22U)
5103#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK)
5104#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)
5105#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)
5106#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)
5107/*! @} */
5108
5109/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */
5110/*! @{ */
5111#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)
5112#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)
5113#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)
5114#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
5115#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
5116/*! BYPASS_CLK_SRC
5117 * 0b00..Select the 24MHz oscillator as source.
5118 * 0b10..Reserved1
5119 * 0b11..Reserved2
5120 */
5121#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
5122#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)
5123#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)
5124#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)
5125#define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK (0x400000U)
5126#define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT (22U)
5127#define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK)
5128#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)
5129#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)
5130#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)
5131/*! @} */
5132
5133/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */
5134/*! @{ */
5135#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)
5136#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)
5137#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)
5138#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
5139#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
5140/*! BYPASS_CLK_SRC
5141 * 0b00..Select the 24MHz oscillator as source.
5142 * 0b10..Reserved1
5143 * 0b11..Reserved2
5144 */
5145#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
5146#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)
5147#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)
5148#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)
5149#define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK (0x400000U)
5150#define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT (22U)
5151#define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK)
5152#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)
5153#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)
5154#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)
5155/*! @} */
5156
5157/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */
5158/*! @{ */
5159#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)
5160#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)
5161#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)
5162#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
5163#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
5164/*! BYPASS_CLK_SRC
5165 * 0b00..Select the 24MHz oscillator as source.
5166 * 0b10..Reserved1
5167 * 0b11..Reserved2
5168 */
5169#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
5170#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)
5171#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)
5172#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)
5173#define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK (0x400000U)
5174#define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT (22U)
5175#define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK)
5176#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)
5177#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)
5178#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)
5179/*! @} */
5180
5181/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
5182/*! @{ */
5183#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)
5184#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)
5185#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
5186#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)
5187#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)
5188#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)
5189#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)
5190#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)
5191#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)
5192#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)
5193#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)
5194#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
5195#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)
5196#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)
5197#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)
5198#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)
5199#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)
5200#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)
5201#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)
5202#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)
5203#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
5204#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)
5205#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)
5206#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)
5207#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)
5208#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)
5209#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)
5210#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)
5211#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)
5212#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
5213#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)
5214#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)
5215#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)
5216#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)
5217#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)
5218#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)
5219/*! @} */
5220
5221/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
5222/*! @{ */
5223#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)
5224#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)
5225#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
5226#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)
5227#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)
5228#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)
5229#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)
5230#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)
5231#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)
5232#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)
5233#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)
5234#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
5235#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)
5236#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)
5237#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)
5238#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)
5239#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)
5240#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)
5241#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)
5242#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)
5243#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
5244#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)
5245#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)
5246#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)
5247#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)
5248#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)
5249#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)
5250#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)
5251#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)
5252#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
5253#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)
5254#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)
5255#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)
5256#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)
5257#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)
5258#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)
5259/*! @} */
5260
5261/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
5262/*! @{ */
5263#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)
5264#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)
5265#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
5266#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)
5267#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)
5268#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)
5269#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)
5270#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)
5271#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)
5272#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)
5273#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)
5274#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
5275#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)
5276#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)
5277#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)
5278#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)
5279#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)
5280#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)
5281#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)
5282#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)
5283#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
5284#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)
5285#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)
5286#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)
5287#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)
5288#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)
5289#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)
5290#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)
5291#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)
5292#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
5293#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)
5294#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)
5295#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)
5296#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)
5297#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)
5298#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)
5299/*! @} */
5300
5301/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
5302/*! @{ */
5303#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)
5304#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)
5305#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
5306#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)
5307#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)
5308#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)
5309#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)
5310#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)
5311#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)
5312#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)
5313#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)
5314#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
5315#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)
5316#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)
5317#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)
5318#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)
5319#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)
5320#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)
5321#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)
5322#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)
5323#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
5324#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)
5325#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)
5326#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)
5327#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)
5328#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)
5329#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)
5330#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)
5331#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)
5332#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
5333#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)
5334#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)
5335#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)
5336#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)
5337#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)
5338#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)
5339/*! @} */
5340
5341/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
5342/*! @{ */
5343#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)
5344#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)
5345#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
5346#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)
5347#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)
5348#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)
5349#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)
5350#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)
5351#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)
5352#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)
5353#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)
5354#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
5355#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)
5356#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)
5357#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)
5358#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)
5359#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)
5360#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)
5361#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)
5362#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)
5363#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
5364#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)
5365#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)
5366#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)
5367#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)
5368#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)
5369#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)
5370#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)
5371#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)
5372#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
5373#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)
5374#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)
5375#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)
5376#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)
5377#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)
5378#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)
5379/*! @} */
5380
5381/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
5382/*! @{ */
5383#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)
5384#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)
5385#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
5386#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)
5387#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)
5388#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)
5389#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)
5390#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)
5391#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)
5392#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)
5393#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)
5394#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
5395#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)
5396#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)
5397#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)
5398#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)
5399#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)
5400#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)
5401#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)
5402#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)
5403#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
5404#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)
5405#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)
5406#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)
5407#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)
5408#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)
5409#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)
5410#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)
5411#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)
5412#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
5413#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)
5414#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)
5415#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)
5416#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)
5417#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)
5418#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)
5419/*! @} */
5420
5421/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
5422/*! @{ */
5423#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)
5424#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)
5425#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
5426#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)
5427#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)
5428#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)
5429#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)
5430#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)
5431#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)
5432#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)
5433#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)
5434#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
5435#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)
5436#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)
5437#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)
5438#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)
5439#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)
5440#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)
5441#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)
5442#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)
5443#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
5444#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)
5445#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)
5446#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)
5447#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)
5448#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)
5449#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)
5450#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)
5451#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)
5452#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
5453#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)
5454#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)
5455#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)
5456#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)
5457#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)
5458#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)
5459/*! @} */
5460
5461/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
5462/*! @{ */
5463#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)
5464#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)
5465#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
5466#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)
5467#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)
5468#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)
5469#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)
5470#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)
5471#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)
5472#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)
5473#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)
5474#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
5475#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)
5476#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)
5477#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)
5478#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)
5479#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)
5480#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)
5481#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)
5482#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)
5483#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
5484#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)
5485#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)
5486#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)
5487#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)
5488#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)
5489#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)
5490#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)
5491#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)
5492#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
5493#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)
5494#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)
5495#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)
5496#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)
5497#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)
5498#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)
5499/*! @} */
5500
5501/*! @name MISC0 - Miscellaneous Register 0 */
5502/*! @{ */
5503#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)
5504#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)
5505#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
5506#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
5507#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
5508/*! REFTOP_SELFBIASOFF
5509 * 0b0..Uses coarse bias currents for startup
5510 * 0b1..Uses bandgap-based bias currents for best performance.
5511 */
5512#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
5513#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)
5514#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)
5515/*! REFTOP_VBGADJ
5516 * 0b000..Nominal VBG
5517 * 0b001..VBG+0.78%
5518 * 0b010..VBG+1.56%
5519 * 0b011..VBG+2.34%
5520 * 0b100..VBG-0.78%
5521 * 0b101..VBG-1.56%
5522 * 0b110..VBG-2.34%
5523 * 0b111..VBG-3.12%
5524 */
5525#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
5526#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)
5527#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)
5528#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
5529#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
5530#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
5531/*! STOP_MODE_CONFIG
5532 * 0b00..All analog except RTC powered down on stop mode assertion.
5533 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
5534 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
5535 * bandgap together with the rest analog is powered down.
5536 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
5537 */
5538#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
5539#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
5540#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
5541/*! DISCON_HIGH_SNVS
5542 * 0b0..Turn on the switch
5543 * 0b1..Turn off the switch
5544 */
5545#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
5546#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)
5547#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)
5548/*! OSC_I
5549 * 0b00..Nominal
5550 * 0b01..Decrease current by 12.5%
5551 * 0b10..Decrease current by 25.0%
5552 * 0b11..Decrease current by 37.5%
5553 */
5554#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
5555#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)
5556#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)
5557#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)
5558#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
5559#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)
5560#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
5561#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
5562#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)
5563/*! CLKGATE_CTRL
5564 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
5565 * 0b1..Prevent the logic from ever gating off the clock.
5566 */
5567#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
5568#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
5569#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)
5570/*! CLKGATE_DELAY
5571 * 0b000..0.5ms
5572 * 0b001..1.0ms
5573 * 0b010..2.0ms
5574 * 0b011..3.0ms
5575 * 0b100..4.0ms
5576 * 0b101..5.0ms
5577 * 0b110..6.0ms
5578 * 0b111..7.0ms
5579 */
5580#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
5581#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
5582#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
5583/*! RTC_XTAL_SOURCE
5584 * 0b0..Internal ring oscillator
5585 * 0b1..RTC_XTAL
5586 */
5587#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
5588#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
5589#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)
5590#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)
5591/*! @} */
5592
5593/*! @name MISC0_SET - Miscellaneous Register 0 */
5594/*! @{ */
5595#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)
5596#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)
5597#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
5598#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
5599#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
5600/*! REFTOP_SELFBIASOFF
5601 * 0b0..Uses coarse bias currents for startup
5602 * 0b1..Uses bandgap-based bias currents for best performance.
5603 */
5604#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
5605#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
5606#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
5607/*! REFTOP_VBGADJ
5608 * 0b000..Nominal VBG
5609 * 0b001..VBG+0.78%
5610 * 0b010..VBG+1.56%
5611 * 0b011..VBG+2.34%
5612 * 0b100..VBG-0.78%
5613 * 0b101..VBG-1.56%
5614 * 0b110..VBG-2.34%
5615 * 0b111..VBG-3.12%
5616 */
5617#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
5618#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
5619#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
5620#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
5621#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
5622#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
5623/*! STOP_MODE_CONFIG
5624 * 0b00..All analog except RTC powered down on stop mode assertion.
5625 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
5626 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
5627 * bandgap together with the rest analog is powered down.
5628 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
5629 */
5630#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
5631#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
5632#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
5633/*! DISCON_HIGH_SNVS
5634 * 0b0..Turn on the switch
5635 * 0b1..Turn off the switch
5636 */
5637#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
5638#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)
5639#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)
5640/*! OSC_I
5641 * 0b00..Nominal
5642 * 0b01..Decrease current by 12.5%
5643 * 0b10..Decrease current by 25.0%
5644 * 0b11..Decrease current by 37.5%
5645 */
5646#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
5647#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
5648#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)
5649#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)
5650#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
5651#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
5652#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
5653#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
5654#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
5655/*! CLKGATE_CTRL
5656 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
5657 * 0b1..Prevent the logic from ever gating off the clock.
5658 */
5659#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
5660#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
5661#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
5662/*! CLKGATE_DELAY
5663 * 0b000..0.5ms
5664 * 0b001..1.0ms
5665 * 0b010..2.0ms
5666 * 0b011..3.0ms
5667 * 0b100..4.0ms
5668 * 0b101..5.0ms
5669 * 0b110..6.0ms
5670 * 0b111..7.0ms
5671 */
5672#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
5673#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
5674#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
5675/*! RTC_XTAL_SOURCE
5676 * 0b0..Internal ring oscillator
5677 * 0b1..RTC_XTAL
5678 */
5679#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
5680#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
5681#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
5682#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)
5683/*! @} */
5684
5685/*! @name MISC0_CLR - Miscellaneous Register 0 */
5686/*! @{ */
5687#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
5688#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
5689#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
5690#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
5691#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
5692/*! REFTOP_SELFBIASOFF
5693 * 0b0..Uses coarse bias currents for startup
5694 * 0b1..Uses bandgap-based bias currents for best performance.
5695 */
5696#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
5697#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
5698#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
5699/*! REFTOP_VBGADJ
5700 * 0b000..Nominal VBG
5701 * 0b001..VBG+0.78%
5702 * 0b010..VBG+1.56%
5703 * 0b011..VBG+2.34%
5704 * 0b100..VBG-0.78%
5705 * 0b101..VBG-1.56%
5706 * 0b110..VBG-2.34%
5707 * 0b111..VBG-3.12%
5708 */
5709#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
5710#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
5711#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
5712#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
5713#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
5714#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
5715/*! STOP_MODE_CONFIG
5716 * 0b00..All analog except RTC powered down on stop mode assertion.
5717 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
5718 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
5719 * bandgap together with the rest analog is powered down.
5720 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
5721 */
5722#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
5723#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
5724#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
5725/*! DISCON_HIGH_SNVS
5726 * 0b0..Turn on the switch
5727 * 0b1..Turn off the switch
5728 */
5729#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
5730#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)
5731#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)
5732/*! OSC_I
5733 * 0b00..Nominal
5734 * 0b01..Decrease current by 12.5%
5735 * 0b10..Decrease current by 25.0%
5736 * 0b11..Decrease current by 37.5%
5737 */
5738#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
5739#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
5740#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
5741#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)
5742#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
5743#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
5744#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
5745#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
5746#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
5747/*! CLKGATE_CTRL
5748 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
5749 * 0b1..Prevent the logic from ever gating off the clock.
5750 */
5751#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
5752#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
5753#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
5754/*! CLKGATE_DELAY
5755 * 0b000..0.5ms
5756 * 0b001..1.0ms
5757 * 0b010..2.0ms
5758 * 0b011..3.0ms
5759 * 0b100..4.0ms
5760 * 0b101..5.0ms
5761 * 0b110..6.0ms
5762 * 0b111..7.0ms
5763 */
5764#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
5765#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
5766#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
5767/*! RTC_XTAL_SOURCE
5768 * 0b0..Internal ring oscillator
5769 * 0b1..RTC_XTAL
5770 */
5771#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
5772#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
5773#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
5774#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)
5775/*! @} */
5776
5777/*! @name MISC0_TOG - Miscellaneous Register 0 */
5778/*! @{ */
5779#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
5780#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
5781#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
5782#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
5783#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
5784/*! REFTOP_SELFBIASOFF
5785 * 0b0..Uses coarse bias currents for startup
5786 * 0b1..Uses bandgap-based bias currents for best performance.
5787 */
5788#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
5789#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
5790#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
5791/*! REFTOP_VBGADJ
5792 * 0b000..Nominal VBG
5793 * 0b001..VBG+0.78%
5794 * 0b010..VBG+1.56%
5795 * 0b011..VBG+2.34%
5796 * 0b100..VBG-0.78%
5797 * 0b101..VBG-1.56%
5798 * 0b110..VBG-2.34%