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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/board.c295
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/board.h147
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/clock_config.c366
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/clock_config.h108
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/peripherals.c51
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/peripherals.h34
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/pin_mux.c55
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/pin_mux.h65
8 files changed, 1121 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/board.c
new file mode 100644
index 000000000..7e275f748
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/board.c
@@ -0,0 +1,295 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "board.h"
11#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12#include "fsl_lpi2c.h"
13#endif /* SDK_I2C_BASED_COMPONENT_USED */
14#if defined BOARD_USE_CODEC
15#include "fsl_wm8960.h"
16#endif
17#include "fsl_iomuxc.h"
18
19/*******************************************************************************
20 * Variables
21 ******************************************************************************/
22#if defined BOARD_USE_CODEC
23codec_config_t boardCodecConfig = {.I2C_SendFunc = BOARD_Codec_I2C_Send,
24 .I2C_ReceiveFunc = BOARD_Codec_I2C_Receive,
25 .op.Init = WM8960_Init,
26 .op.Deinit = WM8960_Deinit,
27 .op.SetFormat = WM8960_ConfigDataFormat};
28#endif
29
30/*******************************************************************************
31 * Code
32 ******************************************************************************/
33
34/* Get debug console frequency. */
35uint32_t BOARD_DebugConsoleSrcFreq(void)
36{
37 uint32_t freq;
38
39 /* To make it simple, we assume default PLL and divider settings, and the only variable
40 from application is use PLL3 source or OSC source */
41 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
42 {
43 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
44 }
45 else
46 {
47 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
48 }
49
50 return freq;
51}
52
53/* Initialize debug console. */
54void BOARD_InitDebugConsole(void)
55{
56 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
57
58 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
59}
60
61/* MPU configuration. */
62void BOARD_ConfigMPU(void)
63{
64 /* Disable I cache and D cache */
65 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
66 {
67 SCB_DisableICache();
68 }
69 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
70 {
71 SCB_DisableDCache();
72 }
73
74 /* Disable MPU */
75 ARM_MPU_Disable();
76
77 /* MPU configure:
78 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
79 * SubRegionDisable, Size)
80 * API in core_cm7.h.
81 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
82 * disabled.
83 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
84 * Privileged mode.
85 * Use MACROS defined in core_cm7.h:
86 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
87 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
88 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
89 * 0 x 0 0 Strongly Ordered shareable
90 * 0 x 0 1 Device shareable
91 * 0 0 1 0 Normal not shareable Outer and inner write
92 * through no write allocate
93 * 0 0 1 1 Normal not shareable Outer and inner write
94 * back no write allocate
95 * 0 1 1 0 Normal shareable Outer and inner write
96 * through no write allocate
97 * 0 1 1 1 Normal shareable Outer and inner write
98 * back no write allocate
99 * 1 0 0 0 Normal not shareable outer and inner
100 * noncache
101 * 1 1 0 0 Normal shareable outer and inner
102 * noncache
103 * 1 0 1 1 Normal not shareable outer and inner write
104 * back write/read acllocate
105 * 1 1 1 1 Normal shareable outer and inner write
106 * back write/read acllocate
107 * 2 x 0 0 Device not shareable
108 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
109 * policy.
110 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
111 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
112 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
113 * core_cm7.h.
114 */
115
116 /* Region 0 setting: Memory with Device type, not shareable, non-cacheable. */
117 MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
118 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
119
120 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
121 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
122 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
123
124/* Region 2 setting */
125#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
126 /* Setting Memory with Normal type, not shareable, outer/inner write back. */
127 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
128 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_16MB);
129#else
130 /* Setting Memory with Device type, not shareable, non-cacheable. */
131 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
132 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_16MB);
133#endif
134
135 /* Region 3 setting: Memory with Device type, not shareable, non-cacheable. */
136 MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
137 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
138
139 /* Region 4 setting: Memory with Normal type, not shareable, outer/inner write back */
140 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
141 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);
142
143 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
144 MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
145 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32KB);
146
147 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
148 MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
149 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
150
151 /* Enable MPU */
152 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
153
154 /* Enable I cache and D cache */
155 SCB_EnableDCache();
156 SCB_EnableICache();
157}
158
159#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
160void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
161{
162 lpi2c_master_config_t lpi2cConfig = {0};
163
164 /*
165 * lpi2cConfig.debugEnable = false;
166 * lpi2cConfig.ignoreAck = false;
167 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
168 * lpi2cConfig.baudRate_Hz = 100000U;
169 * lpi2cConfig.busIdleTimeout_ns = 0;
170 * lpi2cConfig.pinLowTimeout_ns = 0;
171 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
172 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
173 */
174 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
175 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
176}
177
178status_t BOARD_LPI2C_Send(LPI2C_Type *base,
179 uint8_t deviceAddress,
180 uint32_t subAddress,
181 uint8_t subAddressSize,
182 uint8_t *txBuff,
183 uint8_t txBuffSize)
184{
185 status_t reVal;
186
187 /* Send master blocking data to slave */
188 reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
189 if (kStatus_Success == reVal)
190 {
191 while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
192 {
193 }
194
195 reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
196 if (reVal != kStatus_Success)
197 {
198 return reVal;
199 }
200
201 reVal = LPI2C_MasterSend(base, txBuff, txBuffSize);
202 if (reVal != kStatus_Success)
203 {
204 return reVal;
205 }
206
207 reVal = LPI2C_MasterStop(base);
208 if (reVal != kStatus_Success)
209 {
210 return reVal;
211 }
212 }
213
214 return reVal;
215}
216
217status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
218 uint8_t deviceAddress,
219 uint32_t subAddress,
220 uint8_t subAddressSize,
221 uint8_t *rxBuff,
222 uint8_t rxBuffSize)
223{
224 status_t reVal;
225
226 reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
227 if (kStatus_Success == reVal)
228 {
229 while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
230 {
231 }
232
233 reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
234 if (reVal != kStatus_Success)
235 {
236 return reVal;
237 }
238
239 reVal = LPI2C_MasterRepeatedStart(base, deviceAddress, kLPI2C_Read);
240 if (reVal != kStatus_Success)
241 {
242 return reVal;
243 }
244
245 reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
246 if (reVal != kStatus_Success)
247 {
248 return reVal;
249 }
250
251 reVal = LPI2C_MasterStop(base);
252 if (reVal != kStatus_Success)
253 {
254 return reVal;
255 }
256 }
257 return reVal;
258}
259
260void BOARD_Accel_I2C_Init(void)
261{
262 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
263}
264
265status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
266{
267 uint8_t data = (uint8_t)txBuff;
268
269 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
270}
271
272status_t BOARD_Accel_I2C_Receive(
273 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
274{
275 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
276}
277
278void BOARD_Codec_I2C_Init(void)
279{
280 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
281}
282
283status_t BOARD_Codec_I2C_Send(
284 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
285{
286 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
287 txBuffSize);
288}
289
290status_t BOARD_Codec_I2C_Receive(
291 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
292{
293 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
294}
295#endif /*SDK_I2C_BASED_COMPONENT_USED */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/board.h
new file mode 100644
index 000000000..77cfbec77
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/board.h
@@ -0,0 +1,147 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10
11#include "clock_config.h"
12#include "fsl_common.h"
13#include "fsl_gpio.h"
14
15/*******************************************************************************
16 * Definitions
17 ******************************************************************************/
18/*! @brief The board name */
19#define BOARD_NAME "MIMXRT1015-EVK"
20
21/* The UART to use for debug messages. */
22#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
23#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
24#define BOARD_DEBUG_UART_INSTANCE 1U
25
26#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
27
28#define BOARD_UART_IRQ LPUART1_IRQn
29#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
30
31#ifndef BOARD_DEBUG_UART_BAUDRATE
32#define BOARD_DEBUG_UART_BAUDRATE (115200U)
33#endif /* BOARD_DEBUG_UART_BAUDRATE */
34
35/* @Brief Board accelerator sensor configuration */
36#define BOARD_ACCEL_I2C_BASEADDR LPI2C1
37#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
38#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
39#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
40
41#define BOARD_CODEC_I2C_BASEADDR LPI2C1
42#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
43#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
44#define BOARD_CODEC_I2C_CLOCK_FREQ \
45 ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER + 1U))
46
47/*! @brief The USER_LED used for board */
48#define LOGIC_LED_ON (0U)
49#define LOGIC_LED_OFF (1U)
50#ifndef BOARD_USER_LED_GPIO
51#define BOARD_USER_LED_GPIO GPIO3
52#endif
53#ifndef BOARD_USER_LED_GPIO_PIN
54#define BOARD_USER_LED_GPIO_PIN (21U)
55#endif
56
57#define USER_LED_INIT(output) \
58 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
59 BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
60#define USER_LED_ON() \
61 GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
62#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
63#define USER_LED_TOGGLE() \
64 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
65 0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
66
67/*! @brief Define the port interrupt number for the board switches */
68#ifndef BOARD_USER_BUTTON_GPIO
69#define BOARD_USER_BUTTON_GPIO GPIO2
70#endif
71#ifndef BOARD_USER_BUTTON_GPIO_PIN
72#define BOARD_USER_BUTTON_GPIO_PIN (9U)
73#endif
74#define BOARD_USER_BUTTON_IRQ GPIO2_Combined_0_15_IRQn
75#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO2_Combined_0_15_IRQHandler
76#define BOARD_USER_BUTTON_NAME "SW4"
77
78/*! @brief The flash size */
79#define BOARD_FLASH_SIZE (0x1000000U)
80
81/* USB PHY condfiguration */
82#define BOARD_USB_PHY_D_CAL (0x0CU)
83#define BOARD_USB_PHY_TXCAL45DP (0x06U)
84#define BOARD_USB_PHY_TXCAL45DM (0x06U)
85
86#define BOARD_ARDUINO_INT_IRQ (GPIO1_Combined_16_31_IRQn)
87#define BOARD_ARDUINO_I2C_IRQ (LPI2C1_IRQn)
88#define BOARD_ARDUINO_I2C_INDEX (1)
89
90/*! @brief The WIFI-QCA shield pin. */
91#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO GPIO3 /*!< GPIO device name: GPIO */
92#define BOARD_INITSILEX2401SHIELD_PWRON_PORT 3U /*!< PORT device index: 3 */
93#define BOARD_INITSILEX2401SHIELD_PWRON_GPIO_PIN 2U /*!< PIO3 pin index: 2 */
94#define BOARD_INITSILEX2401SHIELD_PWRON_PIN_NAME GPIO3_34 /*!< Pin name */
95#define BOARD_INITSILEX2401SHIELD_PWRON_LABEL "PWRON" /*!< Label */
96#define BOARD_INITSILEX2401SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
97#define BOARD_INITSILEX2401SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
98
99#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO GPIO2 /*!< GPIO device name: GPIO */
100#define BOARD_INITSILEX2401SHIELD_IRQ_PORT 2U /*!< PORT device index: 2 */
101#define BOARD_INITSILEX2401SHIELD_IRQ_GPIO_PIN 20U /*!< PIO2 pin index: 20 */
102#define BOARD_INITSILEX2401SHIELD_IRQ_PIN_NAME GPIO2_20 /*!< Pin name */
103#define BOARD_INITSILEX2401SHIELD_IRQ_LABEL "IRQ" /*!< Label */
104#define BOARD_INITSILEX2401SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
105#define BOARD_INITSILEX2401SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
106
107#if defined(__cplusplus)
108extern "C" {
109#endif /* __cplusplus */
110
111/*******************************************************************************
112 * API
113 ******************************************************************************/
114uint32_t BOARD_DebugConsoleSrcFreq(void);
115
116void BOARD_InitDebugConsole(void);
117void BOARD_ConfigMPU(void);
118#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
119void BOARD_InitDebugConsole(void);
120void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
121status_t BOARD_LPI2C_Send(LPI2C_Type *base,
122 uint8_t deviceAddress,
123 uint32_t subAddress,
124 uint8_t subaddressSize,
125 uint8_t *txBuff,
126 uint8_t txBuffSize);
127status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
128 uint8_t deviceAddress,
129 uint32_t subAddress,
130 uint8_t subaddressSize,
131 uint8_t *rxBuff,
132 uint8_t rxBuffSize);
133void BOARD_Accel_I2C_Init(void);
134status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
135status_t BOARD_Accel_I2C_Receive(
136 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
137void BOARD_Codec_I2C_Init(void);
138status_t BOARD_Codec_I2C_Send(
139 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
140status_t BOARD_Codec_I2C_Receive(
141 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
142#endif /* SDK_I2C_BASED_COMPONENT_USED */
143#if defined(__cplusplus)
144}
145#endif /* __cplusplus */
146
147#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/clock_config.c
new file mode 100644
index 000000000..aa57a3351
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/clock_config.c
@@ -0,0 +1,366 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v5.0
26processor: MIMXRT1015xxxxx
27package_id: MIMXRT1015DAF5A
28mcu_data: ksdk2_0
29processor_version: 0.0.0
30board: MIMXRT1015-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
63- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
64- {id: CLK_1M.outFreq, value: 1 MHz}
65- {id: CLK_24M.outFreq, value: 24 MHz}
66- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
67- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
68- {id: FLEXSPI_CLK_ROOT.outFreq, value: 125 MHz}
69- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
70- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
71- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
72- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
73- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
74- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
75- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
76- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
77- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
78- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
79- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
80- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
81- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
82- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
83- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
84- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
85- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
86- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
87- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
88- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
89settings:
90- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
91- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
92- {id: CCM.CLKO2_SEL.sel, value: CCM.LPI2C_CLK_ROOT}
93- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
94- {id: CCM.IPG_PODF.scale, value: '4'}
95- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
96- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
97- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
98- {id: CCM.SEMC_PODF.scale, value: '2'}
99- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
100- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
101- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
102- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
103- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
104- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
105- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
106- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
107- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
108- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
109- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
110- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
111- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
112- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
113- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
114- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
115- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
116- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
117- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
118- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
119- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
120- {id: CCM_ANALOG.PLL4.denom, value: '50'}
121- {id: CCM_ANALOG.PLL4.div, value: '47'}
122- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
123- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
124sources:
125- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
126- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
127 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
128
129/*******************************************************************************
130 * Variables for BOARD_BootClockRUN configuration
131 ******************************************************************************/
132const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
133 {
134 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
135 .numerator = 0, /* 30 bit numerator of fractional loop divider */
136 .denominator = 1, /* 30 bit denominator of fractional loop divider */
137 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
138 };
139const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
140 {
141 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
142 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
143 };
144const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
145 {
146 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
147 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
148 };
149/*******************************************************************************
150 * Code for BOARD_BootClockRUN configuration
151 ******************************************************************************/
152void BOARD_BootClockRUN(void)
153{
154 /* Init RTC OSC clock frequency. */
155 CLOCK_SetRtcXtalFreq(32768U);
156 /* Enable 1MHz clock output. */
157 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
158 /* Use free 1MHz clock output. */
159 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
160 /* Set XTAL 24MHz clock frequency. */
161 CLOCK_SetXtalFreq(24000000U);
162 /* Enable XTAL 24MHz clock source. */
163 CLOCK_InitExternalClk(0);
164 /* Enable internal RC. */
165 CLOCK_InitRcOsc24M();
166 /* Switch clock source to external OSC. */
167 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
168 /* Set Oscillator ready counter value. */
169 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
170 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
171 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
172 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
173 /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 500Mhz. */
174 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
175 /* Waiting for DCDC_STS_DC_OK bit is asserted */
176 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
177 {
178 }
179 /* Set AHB_PODF. */
180 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
181 /* Disable IPG clock gate. */
182 CLOCK_DisableClock(kCLOCK_Adc1);
183 CLOCK_DisableClock(kCLOCK_Xbar1);
184 CLOCK_DisableClock(kCLOCK_Xbar2);
185 /* Set IPG_PODF. */
186 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
187 /* Set ARM_PODF. */
188 CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
189 /* Set PERIPH_CLK2_PODF. */
190 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
191 /* Disable PERCLK clock gate. */
192 CLOCK_DisableClock(kCLOCK_Gpt1);
193 CLOCK_DisableClock(kCLOCK_Gpt1S);
194 CLOCK_DisableClock(kCLOCK_Gpt2);
195 CLOCK_DisableClock(kCLOCK_Gpt2S);
196 CLOCK_DisableClock(kCLOCK_Pit);
197 /* Set PERCLK_PODF. */
198 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
199 /* Set SEMC_PODF. */
200 CLOCK_SetDiv(kCLOCK_SemcDiv, 1);
201 /* Set Semc alt clock source. */
202 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
203 /* Set Semc clock source. */
204 CLOCK_SetMux(kCLOCK_SemcMux, 0);
205 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
206 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
207 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
208#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
209 /* Disable Flexspi clock gate. */
210 CLOCK_DisableClock(kCLOCK_FlexSpi);
211 /* Set FLEXSPI_PODF. */
212 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
213 /* Set Flexspi clock source. */
214 CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
215#endif
216 /* Disable LPSPI clock gate. */
217 CLOCK_DisableClock(kCLOCK_Lpspi1);
218 CLOCK_DisableClock(kCLOCK_Lpspi2);
219 /* Set LPSPI_PODF. */
220 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
221 /* Set Lpspi clock source. */
222 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
223 /* Disable TRACE clock gate. */
224 CLOCK_DisableClock(kCLOCK_Trace);
225 /* Set TRACE_PODF. */
226 CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
227 /* Set Trace clock source. */
228 CLOCK_SetMux(kCLOCK_TraceMux, 2);
229 /* Disable SAI1 clock gate. */
230 CLOCK_DisableClock(kCLOCK_Sai1);
231 /* Set SAI1_CLK_PRED. */
232 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
233 /* Set SAI1_CLK_PODF. */
234 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
235 /* Set Sai1 clock source. */
236 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
237 /* Disable SAI2 clock gate. */
238 CLOCK_DisableClock(kCLOCK_Sai2);
239 /* Set SAI2_CLK_PRED. */
240 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
241 /* Set SAI2_CLK_PODF. */
242 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
243 /* Set Sai2 clock source. */
244 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
245 /* Disable SAI3 clock gate. */
246 CLOCK_DisableClock(kCLOCK_Sai3);
247 /* Set SAI3_CLK_PRED. */
248 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
249 /* Set SAI3_CLK_PODF. */
250 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
251 /* Set Sai3 clock source. */
252 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
253 /* Disable Lpi2c clock gate. */
254 CLOCK_DisableClock(kCLOCK_Lpi2c1);
255 CLOCK_DisableClock(kCLOCK_Lpi2c2);
256 /* Set LPI2C_CLK_PODF. */
257 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
258 /* Set Lpi2c clock source. */
259 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
260 /* Disable UART clock gate. */
261 CLOCK_DisableClock(kCLOCK_Lpuart1);
262 CLOCK_DisableClock(kCLOCK_Lpuart2);
263 CLOCK_DisableClock(kCLOCK_Lpuart3);
264 CLOCK_DisableClock(kCLOCK_Lpuart4);
265 /* Set UART_CLK_PODF. */
266 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
267 /* Set Uart clock source. */
268 CLOCK_SetMux(kCLOCK_UartMux, 0);
269 /* Disable SPDIF clock gate. */
270 CLOCK_DisableClock(kCLOCK_Spdif);
271 /* Set SPDIF0_CLK_PRED. */
272 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
273 /* Set SPDIF0_CLK_PODF. */
274 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
275 /* Set Spdif clock source. */
276 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
277 /* Disable Flexio1 clock gate. */
278 CLOCK_DisableClock(kCLOCK_Flexio1);
279 /* Set FLEXIO1_CLK_PRED. */
280 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
281 /* Set FLEXIO1_CLK_PODF. */
282 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
283 /* Set Flexio1 clock source. */
284 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
285 /* Set Pll3 sw clock source. */
286 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
287 /* Init System PLL. */
288 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
289 /* Init System pfd0. */
290 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
291 /* Init System pfd1. */
292 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
293 /* Init System pfd2. */
294 CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
295 /* Init System pfd3. */
296 CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
297 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
298 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
299 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
300#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
301 /* Init Usb1 PLL. */
302 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
303 /* Init Usb1 pfd0. */
304 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
305 /* Init Usb1 pfd1. */
306 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
307 /* Init Usb1 pfd2. */
308 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
309 /* Init Usb1 pfd3. */
310 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
311 /* Disable Usb1 PLL output for USBPHY1. */
312 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
313#endif
314 /* DeInit Audio PLL. */
315 CLOCK_DeinitAudioPll();
316 /* Bypass Audio PLL. */
317 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
318 /* Set divider for Audio PLL. */
319 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
320 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
321 /* Enable Audio PLL output. */
322 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
323 /* Init Enet PLL. */
324 CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
325 /* Set preperiph clock source. */
326 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
327 /* Set periph clock source. */
328 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
329 /* Set periph clock2 clock source. */
330 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
331 /* Set per clock source. */
332 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
333 /* Set clock out1 divider. */
334 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
335 /* Set clock out1 source. */
336 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
337 /* Set clock out2 divider. */
338 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
339 /* Set clock out2 source. */
340 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(6);
341 /* Set clock out1 drives clock out1. */
342 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
343 /* Disable clock out1. */
344 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
345 /* Disable clock out2. */
346 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
347 /* Set SAI1 MCLK1 clock source. */
348 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
349 /* Set SAI1 MCLK2 clock source. */
350 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
351 /* Set SAI1 MCLK3 clock source. */
352 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
353 /* Set SAI2 MCLK3 clock source. */
354 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
355 /* Set SAI3 MCLK3 clock source. */
356 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
357 /* Set MQS configuration. */
358 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
359 /* Set GPT1 High frequency reference clock source. */
360 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
361 /* Set GPT2 High frequency reference clock source. */
362 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
363 /* Set SystemCoreClock variable. */
364 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
365}
366
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/clock_config.h
new file mode 100644
index 000000000..5b2d3d949
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/clock_config.h
@@ -0,0 +1,108 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _CLOCK_CONFIG_H_
9#define _CLOCK_CONFIG_H_
10
11#include "fsl_common.h"
12
13/*******************************************************************************
14 * Definitions
15 ******************************************************************************/
16#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
17
18#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
19/*******************************************************************************
20 ************************ BOARD_InitBootClocks function ************************
21 ******************************************************************************/
22
23#if defined(__cplusplus)
24extern "C" {
25#endif /* __cplusplus*/
26
27/*!
28 * @brief This function executes default configuration of clocks.
29 *
30 */
31void BOARD_InitBootClocks(void);
32
33#if defined(__cplusplus)
34}
35#endif /* __cplusplus*/
36
37/*******************************************************************************
38 ********************** Configuration BOARD_BootClockRUN ***********************
39 ******************************************************************************/
40/*******************************************************************************
41 * Definitions for BOARD_BootClockRUN configuration
42 ******************************************************************************/
43#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
44
45/* Clock outputs (values are in Hz): */
46#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
47#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
48#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
49#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
50#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
51#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
52#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
53#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
54#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 125000000UL
55#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
56#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
57#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
58#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
59#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
60#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
61#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
62#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
63#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
64#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
65#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
66#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
67#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
68#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
69#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
70#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
71#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
72#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
73#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
74#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
75#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
76#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
77#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
78#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
79
80/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
81 */
82extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
83/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
84 */
85extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
86/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
87 */
88extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
89
90/*******************************************************************************
91 * API for BOARD_BootClockRUN configuration
92 ******************************************************************************/
93#if defined(__cplusplus)
94extern "C" {
95#endif /* __cplusplus*/
96
97/*!
98 * @brief This function executes configuration of clocks.
99 *
100 */
101void BOARD_BootClockRUN(void);
102
103#if defined(__cplusplus)
104}
105#endif /* __cplusplus*/
106
107#endif /* _CLOCK_CONFIG_H_ */
108
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/peripherals.c
new file mode 100644
index 000000000..e56d507b6
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/peripherals.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright 2018-2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/* clang-format off */
14/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Peripherals v6.0
17processor: MIMXRT1015xxxxx
18mcu_data: ksdk2_0
19processor_version: 0.0.8
20functionalGroups:
21- name: BOARD_InitPeripherals
22 called_from_default_init: true
23 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
24
25/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
26component:
27- type: 'system'
28- type_id: 'system_54b53072540eeeb8f8e9343e71f28176'
29- global_system_definitions: []
30 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
31/* clang-format on */
32
33/***********************************************************************************************************************
34 * Included files
35 **********************************************************************************************************************/
36#include "peripherals.h"
37
38/***********************************************************************************************************************
39 * Initialization functions
40 **********************************************************************************************************************/
41void BOARD_InitPeripherals(void)
42{
43}
44
45/***********************************************************************************************************************
46 * BOARD_InitBootPeripherals function
47 **********************************************************************************************************************/
48void BOARD_InitBootPeripherals(void)
49{
50 BOARD_InitPeripherals();
51}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/peripherals.h
new file mode 100644
index 000000000..c0972aa95
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/peripherals.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright 2018-2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PERIPHERALS_H_
14#define _PERIPHERALS_H_
15
16#if defined(__cplusplus)
17extern "C" {
18#endif /* __cplusplus */
19
20/***********************************************************************************************************************
21 * Initialization functions
22 **********************************************************************************************************************/
23void BOARD_InitPeripherals(void);
24
25/***********************************************************************************************************************
26 * BOARD_InitBootPeripherals function
27 **********************************************************************************************************************/
28void BOARD_InitBootPeripherals(void);
29
30#if defined(__cplusplus)
31}
32#endif
33
34#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/pin_mux.c
new file mode 100644
index 000000000..6df8dd605
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/pin_mux.c
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2018-2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/*
14 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Pins v6.0
17processor: MIMXRT1015xxxxx
18mcu_data: ksdk2_0
19processor_version: 0.0.8
20 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
21 */
22
23#include "fsl_common.h"
24#include "pin_mux.h"
25
26/* FUNCTION ************************************************************************************************************
27 *
28 * Function Name : BOARD_InitBootPins
29 * Description : Calls initialization functions.
30 *
31 * END ****************************************************************************************************************/
32void BOARD_InitBootPins(void) {
33 BOARD_InitPins();
34}
35
36/*
37 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
38BOARD_InitPins:
39- options: {callFromInitBoot: 'true', enableClock: 'true'}
40- pin_list: []
41 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
42 */
43
44/* FUNCTION ************************************************************************************************************
45 *
46 * Function Name : BOARD_InitPins
47 * Description : Configures pin routing and optionally pin electrical features.
48 *
49 * END ****************************************************************************************************************/
50void BOARD_InitPins(void) {
51}
52
53/***********************************************************************************************************************
54 * EOF
55 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/pin_mux.h
new file mode 100644
index 000000000..05c1577b9
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1015/project_template/pin_mux.h
@@ -0,0 +1,65 @@
1/*
2 * Copyright 2018-2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PIN_MUX_H_
14#define _PIN_MUX_H_
15
16/***********************************************************************************************************************
17 * Definitions
18 **********************************************************************************************************************/
19
20/*! @brief Direction type */
21typedef enum _pin_mux_direction
22{
23 kPIN_MUX_DirectionInput = 0U, /* Input direction */
24 kPIN_MUX_DirectionOutput = 1U, /* Output direction */
25 kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
26} pin_mux_direction_t;
27
28/*!
29 * @addtogroup pin_mux
30 * @{
31 */
32
33/***********************************************************************************************************************
34 * API
35 **********************************************************************************************************************/
36
37#if defined(__cplusplus)
38extern "C" {
39#endif
40
41/*!
42 * @brief Calls initialization functions.
43 *
44 */
45void BOARD_InitBootPins(void);
46
47
48/*!
49 * @brief Configures pin routing and optionally pin electrical features.
50 *
51 */
52void BOARD_InitPins(void);
53
54#if defined(__cplusplus)
55}
56#endif
57
58/*!
59 * @}
60 */
61#endif /* _PIN_MUX_H_ */
62
63/***********************************************************************************************************************
64 * EOF
65 **********************************************************************************************************************/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 01:10:01 +0100