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1/*
2** ###################################################################
3** Processors: MIMXRT1021CAF4A
4** MIMXRT1021CAG4A
5** MIMXRT1021DAF5A
6** MIMXRT1021DAG5A
7**
8** Compilers: Freescale C/C++ for Embedded ARM
9** GNU C Compiler
10** IAR ANSI C/C++ Compiler for ARM
11** Keil ARM C/C++ Compiler
12** MCUXpresso Compiler
13**
14** Reference manual: IMXRT1020RM Rev.1, 12/2018 | IMXRT1020SRM Rev.3
15** Version: rev. 1.1, 2019-04-29
16** Build: b201123
17**
18** Abstract:
19** CMSIS Peripheral Access Layer for MIMXRT1021
20**
21** Copyright 1997-2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2020 NXP
23** All rights reserved.
24**
25** SPDX-License-Identifier: BSD-3-Clause
26**
27** http: www.nxp.com
28** mail: [email protected]
29**
30** Revisions:
31** - rev. 0.1 (2017-11-06)
32** Initial version.
33** - rev. 1.0 (2018-11-27)
34** Update header files to align with IMXRT1020RM Rev.1.
35** - rev. 1.1 (2019-04-29)
36** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
37**
38** ###################################################################
39*/
40
41/*!
42 * @file MIMXRT1021.h
43 * @version 1.1
44 * @date 2019-04-29
45 * @brief CMSIS Peripheral Access Layer for MIMXRT1021
46 *
47 * CMSIS Peripheral Access Layer for MIMXRT1021
48 */
49
50#ifndef _MIMXRT1021_H_
51#define _MIMXRT1021_H_ /**< Symbol preventing repeated inclusion */
52
53/** Memory map major version (memory maps with equal major version number are
54 * compatible) */
55#define MCU_MEM_MAP_VERSION 0x0100U
56/** Memory map minor version */
57#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
58
59
60/* ----------------------------------------------------------------------------
61 -- Interrupt vector numbers
62 ---------------------------------------------------------------------------- */
63
64/*!
65 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
66 * @{
67 */
68
69/** Interrupt Number Definitions */
70#define NUMBER_OF_INT_VECTORS 158 /**< Number of interrupts in the Vector table */
71
72typedef enum IRQn {
73 /* Auxiliary constants */
74 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
75
76 /* Core interrupts */
77 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
78 HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */
79 MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */
80 BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */
81 UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */
82 SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */
83 DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */
84 PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */
85 SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */
86
87 /* Device specific interrupts */
88 DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */
89 DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */
90 DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */
91 DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */
92 DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */
93 DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */
94 DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */
95 DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */
96 DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */
97 DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */
98 DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */
99 DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */
100 DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */
101 DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */
102 DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */
103 DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */
104 DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */
105 CTI0_ERROR_IRQn = 17, /**< CTI trigger outputs */
106 CTI1_ERROR_IRQn = 18, /**< CTI trigger outputs */
107 CORE_IRQn = 19, /**< CorePlatform exception IRQ */
108 LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */
109 LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */
110 LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */
111 LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */
112 LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */
113 LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */
114 LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */
115 LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */
116 LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */
117 LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */
118 LPI2C3_IRQn = 30, /**< LPI2C3 interrupt */
119 LPI2C4_IRQn = 31, /**< LPI2C4 interrupt */
120 LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */
121 LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */
122 LPSPI3_IRQn = 34, /**< LPSPI3 single interrupt vector for all sources */
123 LPSPI4_IRQn = 35, /**< LPSPI4 single interrupt vector for all sources */
124 CAN1_IRQn = 36, /**< CAN1 interrupt */
125 CAN2_IRQn = 37, /**< CAN2 interrupt */
126 FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */
127 KPP_IRQn = 39, /**< Keypad nterrupt */
128 Reserved56_IRQn = 40, /**< Reserved interrupt */
129 GPR_IRQ_IRQn = 41, /**< Used to notify cores on exception condition while boot */
130 Reserved58_IRQn = 42, /**< Reserved interrupt */
131 Reserved59_IRQn = 43, /**< Reserved interrupt */
132 Reserved60_IRQn = 44, /**< Reserved interrupt */
133 WDOG2_IRQn = 45, /**< WDOG2 interrupt */
134 SNVS_HP_WRAPPER_IRQn = 46, /**< SNVS Functional Interrupt */
135 SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SNVS Security Interrupt */
136 SNVS_LP_HP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */
137 CSU_IRQn = 49, /**< CSU interrupt */
138 DCP_IRQn = 50, /**< Combined DCP channel interrupts(except channel 0) and CRC interrupt */
139 DCP_VMI_IRQn = 51, /**< IRQ of DCP channel 0 */
140 Reserved68_IRQn = 52, /**< Reserved interrupt */
141 TRNG_IRQn = 53, /**< TRNG interrupt */
142 Reserved70_IRQn = 54, /**< Reserved interrupt */
143 BEE_IRQn = 55, /**< BEE interrupt */
144 SAI1_IRQn = 56, /**< SAI1 interrupt */
145 SAI2_IRQn = 57, /**< SAI1 interrupt */
146 SAI3_RX_IRQn = 58, /**< SAI3 interrupt */
147 SAI3_TX_IRQn = 59, /**< SAI3 interrupt */
148 SPDIF_IRQn = 60, /**< SPDIF interrupt */
149 PMU_IRQn = 61, /**< PMU interrupt */
150 Reserved78_IRQn = 62, /**< Reserved interrupt */
151 TEMP_LOW_HIGH_IRQn = 63, /**< TEMPMON interrupt */
152 TEMP_PANIC_IRQn = 64, /**< TEMPMON interrupt */
153 USB_PHY_IRQn = 65, /**< USBPHY (OTG1 UTMI), Interrupt */
154 Reserved82_IRQn = 66, /**< Reserved interrupt */
155 ADC1_IRQn = 67, /**< ADC1 interrupt */
156 ADC2_IRQn = 68, /**< ADC2 interrupt */
157 DCDC_IRQn = 69, /**< DCDC interrupt */
158 Reserved86_IRQn = 70, /**< Reserved interrupt */
159 Reserved87_IRQn = 71, /**< Reserved interrupt */
160 GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */
161 GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */
162 GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */
163 GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */
164 GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */
165 GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */
166 GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */
167 GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */
168 GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
169 GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
170 GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
171 GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
172 GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
173 GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
174 Reserved102_IRQn = 86, /**< Reserved interrupt */
175 Reserved103_IRQn = 87, /**< Reserved interrupt */
176 GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
177 GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
178 FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */
179 Reserved107_IRQn = 91, /**< Reserved interrupt */
180 WDOG1_IRQn = 92, /**< WDOG1 interrupt */
181 RTWDOG_IRQn = 93, /**< RTWDOG interrupt */
182 EWM_IRQn = 94, /**< EWM interrupt */
183 CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */
184 CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */
185 GPC_IRQn = 97, /**< GPC interrupt */
186 SRC_IRQn = 98, /**< SRC interrupt */
187 Reserved115_IRQn = 99, /**< Reserved interrupt */
188 GPT1_IRQn = 100, /**< GPT1 interrupt */
189 GPT2_IRQn = 101, /**< GPT2 interrupt */
190 PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
191 PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */
192 PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */
193 PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */
194 PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */
195 Reserved123_IRQn = 107, /**< Reserved interrupt */
196 FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */
197 SEMC_IRQn = 109, /**< Reserved interrupt */
198 USDHC1_IRQn = 110, /**< USDHC1 interrupt */
199 USDHC2_IRQn = 111, /**< USDHC2 interrupt */
200 Reserved128_IRQn = 112, /**< Reserved interrupt */
201 USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */
202 ENET_IRQn = 114, /**< ENET interrupt */
203 ENET_1588_Timer_IRQn = 115, /**< ENET_1588_Timer interrupt */
204 XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */
205 XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */
206 ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */
207 ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */
208 ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */
209 ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */
210 PIT_IRQn = 122, /**< PIT interrupt */
211 ACMP1_IRQn = 123, /**< ACMP interrupt */
212 ACMP2_IRQn = 124, /**< ACMP interrupt */
213 ACMP3_IRQn = 125, /**< ACMP interrupt */
214 ACMP4_IRQn = 126, /**< ACMP interrupt */
215 Reserved143_IRQn = 127, /**< Reserved interrupt */
216 Reserved144_IRQn = 128, /**< Reserved interrupt */
217 ENC1_IRQn = 129, /**< ENC1 interrupt */
218 ENC2_IRQn = 130, /**< ENC2 interrupt */
219 Reserved147_IRQn = 131, /**< Reserved interrupt */
220 Reserved148_IRQn = 132, /**< Reserved interrupt */
221 TMR1_IRQn = 133, /**< TMR1 interrupt */
222 TMR2_IRQn = 134, /**< TMR2 interrupt */
223 Reserved151_IRQn = 135, /**< Reserved interrupt */
224 Reserved152_IRQn = 136, /**< Reserved interrupt */
225 PWM2_0_IRQn = 137, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */
226 PWM2_1_IRQn = 138, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */
227 PWM2_2_IRQn = 139, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */
228 PWM2_3_IRQn = 140, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */
229 PWM2_FAULT_IRQn = 141 /**< PWM2 fault or reload error interrupt */
230} IRQn_Type;
231
232/*!
233 * @}
234 */ /* end of group Interrupt_vector_numbers */
235
236
237/* ----------------------------------------------------------------------------
238 -- Cortex M7 Core Configuration
239 ---------------------------------------------------------------------------- */
240
241/*!
242 * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
243 * @{
244 */
245
246#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
247#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */
248#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */
249#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */
250#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
251#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
252#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
253
254#include "core_cm7.h" /* Core Peripheral Access Layer */
255#include "system_MIMXRT1021.h" /* Device specific configuration file */
256
257/*!
258 * @}
259 */ /* end of group Cortex_Core_Configuration */
260
261
262/* ----------------------------------------------------------------------------
263 -- Mapping Information
264 ---------------------------------------------------------------------------- */
265
266/*!
267 * @addtogroup Mapping_Information Mapping Information
268 * @{
269 */
270
271/** Mapping Information */
272/*!
273 * @addtogroup edma_request
274 * @{
275 */
276
277/*******************************************************************************
278 * Definitions
279 ******************************************************************************/
280
281/*!
282 * @brief Structure for the DMA hardware request
283 *
284 * Defines the structure for the DMA hardware request collections. The user can configure the
285 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
286 * of the hardware request varies according to the to SoC.
287 */
288typedef enum _dma_request_source
289{
290 kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */
291 kDmaRequestMuxFlexIO1Request4Request5 = 1|0x100U, /**< FlexIO1 Request4 and Request5 */
292 kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */
293 kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */
294 kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */
295 kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */
296 kDmaRequestMuxLPUART5Tx = 6|0x100U, /**< LPUART5 Transmit */
297 kDmaRequestMuxLPUART5Rx = 7|0x100U, /**< LPUART5 Receive */
298 kDmaRequestMuxLPUART7Tx = 8|0x100U, /**< LPUART7 Transmit */
299 kDmaRequestMuxLPUART7Rx = 9|0x100U, /**< LPUART7 Receive */
300 kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */
301 kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */
302 kDmaRequestMuxLPSPI3Rx = 15|0x100U, /**< LPSPI3 Receive */
303 kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */
304 kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */
305 kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */
306 kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */
307 kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */
308 kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */
309 kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */
310 kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */
311 kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */
312 kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */
313 kDmaRequestMuxACMP3 = 26|0x100U, /**< ACMP3 */
314 kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */
315 kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */
316 kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */
317 kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR1 Request 1 */
318 kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */
319 kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */
320 kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */
321 kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */
322 kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */
323 kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */
324 kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */
325 kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */
326 kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< TMR1 Capture timer 0 */
327 kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< TMR1 Capture timer 1 */
328 kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< TMR1 Capture timer 2 */
329 kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< TMR1 Capture timer 3 */
330 kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */
331 kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */
332 kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */
333 kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */
334 kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */
335 kDmaRequestMuxFlexIO1Request6Request7 = 65|0x100U, /**< FlexIO1 Request6 and Request7 */
336 kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */
337 kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */
338 kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */
339 kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */
340 kDmaRequestMuxLPUART6Tx = 70|0x100U, /**< LPUART6 Transmit */
341 kDmaRequestMuxLPUART6Rx = 71|0x100U, /**< LPUART6 Receive */
342 kDmaRequestMuxLPUART8Tx = 72|0x100U, /**< LPUART8 Transmit */
343 kDmaRequestMuxLPUART8Rx = 73|0x100U, /**< LPUART8 Receive */
344 kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */
345 kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */
346 kDmaRequestMuxLPSPI4Rx = 79|0x100U, /**< LPSPI4 Receive */
347 kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */
348 kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */
349 kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */
350 kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */
351 kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */
352 kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */
353 kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */
354 kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */
355 kDmaRequestMuxACMP2 = 89|0x100U, /**< ACMP2 */
356 kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */
357 kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< ENET Timer0 */
358 kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< ENET Timer1 */
359 kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */
360 kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */
361 kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */
362 kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */
363 kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */
364 kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */
365 kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, /**< FlexPWM2 Value sub-module0 */
366 kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, /**< FlexPWM2 Value sub-module1 */
367 kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U, /**< FlexPWM2 Value sub-module2 */
368 kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, /**< FlexPWM2 Value sub-module3 */
369 kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< TMR2 Capture timer 0 */
370 kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< TMR2 Capture timer 1 */
371 kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< TMR2 Capture timer 2 */
372 kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< TMR2 Capture timer 3 */
373 kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */
374 kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */
375 kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */
376 kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */
377} dma_request_source_t;
378
379/* @} */
380
381/*!
382 * @addtogroup iomuxc_pads
383 * @{ */
384
385/*******************************************************************************
386 * Definitions
387*******************************************************************************/
388
389/*!
390 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
391 *
392 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
393 */
394typedef enum _iomuxc_sw_mux_ctl_pad
395{
396 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
397 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
398 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
399 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
400 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
401 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
402 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
403 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
404 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
405 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
406 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
407 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
408 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
409 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
410 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
411 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
412 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
413 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
414 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
415 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
416 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
417 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
418 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
419 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
420 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
421 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
422 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
423 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
424 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
425 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
426 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
427 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
428 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
429 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
430 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
431 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
432 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
433 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
434 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
435 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
436 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
437 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
438 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
439 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
440 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
441 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
442 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
443 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
444 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
445 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
446 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
447 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
448 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
449 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
450 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
451 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
452 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
453 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
454 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
455 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
456 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
457 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
458 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
459 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
460 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
461 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
462 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
463 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
464 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
465 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
466 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
467 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
468 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
469 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
470 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
471 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
472 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
473 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
474 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
475 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */
476 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_06 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */
477 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */
478 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */
479 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */
480 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */
481 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */
482 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */
483 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */
484 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */
485 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */
486 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */
487 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */
488 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */
489} iomuxc_sw_mux_ctl_pad_t;
490
491/* @} */
492
493/*!
494 * @addtogroup iomuxc_pads
495 * @{ */
496
497/*******************************************************************************
498 * Definitions
499*******************************************************************************/
500
501/*!
502 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
503 *
504 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
505 */
506typedef enum _iomuxc_sw_pad_ctl_pad
507{
508 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
509 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
510 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
511 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
512 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
513 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
514 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
515 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
516 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
517 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
518 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
519 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
520 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
521 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
522 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
523 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
524 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
525 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
526 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
527 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
528 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
529 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
530 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
531 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
532 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
533 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
534 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
535 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
536 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
537 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
538 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
539 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
540 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
541 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
542 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
543 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
544 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
545 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
546 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
547 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
548 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
549 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
550 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
551 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
552 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
553 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
554 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
555 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
556 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
557 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
558 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
559 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
560 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
561 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
562 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */
563 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */
564 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */
565 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */
566 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */
567 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */
568 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */
569 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */
570 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */
571 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */
572 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
573 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
574 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
575 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
576 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
577 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
578 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */
579 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */
580 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */
581 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */
582 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */
583 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */
584 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */
585 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
586 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
587 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
588 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_06 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
589 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
590 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
591 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
592 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
593 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
594 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
595 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
596 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
597 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */
598 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */
599 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */
600 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */
601} iomuxc_sw_pad_ctl_pad_t;
602
603/* @} */
604
605/*!
606 * @brief Enumeration for the IOMUXC select input
607 *
608 * Defines the enumeration for the IOMUXC select input collections.
609 */
610typedef enum _iomuxc_select_input
611{
612 kIOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */
613 kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 1U, /**< IOMUXC select input index */
614 kIOMUXC_ENET_RMII_SELECT_INPUT = 2U, /**< IOMUXC select input index */
615 kIOMUXC_ENET_MDIO_SELECT_INPUT = 3U, /**< IOMUXC select input index */
616 kIOMUXC_ENET_RX_DATA0_SELECT_INPUT = 4U, /**< IOMUXC select input index */
617 kIOMUXC_ENET_RX_DATA1_SELECT_INPUT = 5U, /**< IOMUXC select input index */
618 kIOMUXC_ENET_RX_EN_SELECT_INPUT = 6U, /**< IOMUXC select input index */
619 kIOMUXC_ENET_RX_ERR_SELECT_INPUT = 7U, /**< IOMUXC select input index */
620 kIOMUXC_ENET_TX_CLK_SELECT_INPUT = 8U, /**< IOMUXC select input index */
621 kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 9U, /**< IOMUXC select input index */
622 kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 10U, /**< IOMUXC select input index */
623 kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 11U, /**< IOMUXC select input index */
624 kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 12U, /**< IOMUXC select input index */
625 kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 13U, /**< IOMUXC select input index */
626 kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 14U, /**< IOMUXC select input index */
627 kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 15U, /**< IOMUXC select input index */
628 kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 16U, /**< IOMUXC select input index */
629 kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 17U, /**< IOMUXC select input index */
630 kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 18U, /**< IOMUXC select input index */
631 kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 19U, /**< IOMUXC select input index */
632 kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 20U, /**< IOMUXC select input index */
633 kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 21U, /**< IOMUXC select input index */
634 kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 22U, /**< IOMUXC select input index */
635 kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 23U, /**< IOMUXC select input index */
636 kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 24U, /**< IOMUXC select input index */
637 kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 25U, /**< IOMUXC select input index */
638 kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 26U, /**< IOMUXC select input index */
639 kIOMUXC_FLEXSPI_A_DATA0_SELECT_INPUT = 27U, /**< IOMUXC select input index */
640 kIOMUXC_FLEXSPI_A_DATA1_SELECT_INPUT = 28U, /**< IOMUXC select input index */
641 kIOMUXC_FLEXSPI_A_DATA2_SELECT_INPUT = 29U, /**< IOMUXC select input index */
642 kIOMUXC_FLEXSPI_A_DATA3_SELECT_INPUT = 30U, /**< IOMUXC select input index */
643 kIOMUXC_FLEXSPI_A_SCLK_SELECT_INPUT = 31U, /**< IOMUXC select input index */
644 kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 32U, /**< IOMUXC select input index */
645 kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 33U, /**< IOMUXC select input index */
646 kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 34U, /**< IOMUXC select input index */
647 kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 35U, /**< IOMUXC select input index */
648 kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 36U, /**< IOMUXC select input index */
649 kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 37U, /**< IOMUXC select input index */
650 kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 38U, /**< IOMUXC select input index */
651 kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 39U, /**< IOMUXC select input index */
652 kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 40U, /**< IOMUXC select input index */
653 kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 41U, /**< IOMUXC select input index */
654 kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 42U, /**< IOMUXC select input index */
655 kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 43U, /**< IOMUXC select input index */
656 kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 44U, /**< IOMUXC select input index */
657 kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 45U, /**< IOMUXC select input index */
658 kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 46U, /**< IOMUXC select input index */
659 kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 47U, /**< IOMUXC select input index */
660 kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 48U, /**< IOMUXC select input index */
661 kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 49U, /**< IOMUXC select input index */
662 kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 50U, /**< IOMUXC select input index */
663 kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 51U, /**< IOMUXC select input index */
664 kIOMUXC_LPUART2_CTS_B_SELECT_INPUT = 52U, /**< IOMUXC select input index */
665 kIOMUXC_LPUART2_RX_SELECT_INPUT = 53U, /**< IOMUXC select input index */
666 kIOMUXC_LPUART2_TX_SELECT_INPUT = 54U, /**< IOMUXC select input index */
667 kIOMUXC_LPUART3_RX_SELECT_INPUT = 55U, /**< IOMUXC select input index */
668 kIOMUXC_LPUART3_TX_SELECT_INPUT = 56U, /**< IOMUXC select input index */
669 kIOMUXC_LPUART4_CTS_B_SELECT_INPUT = 57U, /**< IOMUXC select input index */
670 kIOMUXC_LPUART4_RX_SELECT_INPUT = 58U, /**< IOMUXC select input index */
671 kIOMUXC_LPUART4_TX_SELECT_INPUT = 59U, /**< IOMUXC select input index */
672 kIOMUXC_LPUART5_RX_SELECT_INPUT = 60U, /**< IOMUXC select input index */
673 kIOMUXC_LPUART5_TX_SELECT_INPUT = 61U, /**< IOMUXC select input index */
674 kIOMUXC_LPUART6_RX_SELECT_INPUT = 62U, /**< IOMUXC select input index */
675 kIOMUXC_LPUART6_TX_SELECT_INPUT = 63U, /**< IOMUXC select input index */
676 kIOMUXC_LPUART7_RX_SELECT_INPUT = 64U, /**< IOMUXC select input index */
677 kIOMUXC_LPUART7_TX_SELECT_INPUT = 65U, /**< IOMUXC select input index */
678 kIOMUXC_LPUART8_RX_SELECT_INPUT = 66U, /**< IOMUXC select input index */
679 kIOMUXC_LPUART8_TX_SELECT_INPUT = 67U, /**< IOMUXC select input index */
680 kIOMUXC_NMI_SELECT_INPUT = 68U, /**< IOMUXC select input index */
681 kIOMUXC_QTIMER1_TIMER0_INPUT_SELECT_INPUT = 69U, /**< IOMUXC select input index */
682 kIOMUXC_QTIMER1_TIMER1_INPUT_SELECT_INPUT = 70U, /**< IOMUXC select input index */
683 kIOMUXC_QTIMER1_TIMER2_INPUT_SELECT_INPUT = 71U, /**< IOMUXC select input index */
684 kIOMUXC_QTIMER1_TIMER3_INPUT_SELECT_INPUT = 72U, /**< IOMUXC select input index */
685 kIOMUXC_QTIMER2_TIMER0_INPUT_SELECT_INPUT = 73U, /**< IOMUXC select input index */
686 kIOMUXC_QTIMER2_TIMER1_INPUT_SELECT_INPUT = 74U, /**< IOMUXC select input index */
687 kIOMUXC_QTIMER2_TIMER2_INPUT_SELECT_INPUT = 75U, /**< IOMUXC select input index */
688 kIOMUXC_QTIMER2_TIMER3_INPUT_SELECT_INPUT = 76U, /**< IOMUXC select input index */
689 kIOMUXC_SAI1_MCLK_SELECT_INPUT = 77U, /**< IOMUXC select input index */
690 kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 78U, /**< IOMUXC select input index */
691 kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 79U, /**< IOMUXC select input index */
692 kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 80U, /**< IOMUXC select input index */
693 kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 81U, /**< IOMUXC select input index */
694 kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 82U, /**< IOMUXC select input index */
695 kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 83U, /**< IOMUXC select input index */
696 kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 84U, /**< IOMUXC select input index */
697 kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 85U, /**< IOMUXC select input index */
698 kIOMUXC_SAI2_MCLK_SELECT_INPUT = 86U, /**< IOMUXC select input index */
699 kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 87U, /**< IOMUXC select input index */
700 kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 88U, /**< IOMUXC select input index */
701 kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 89U, /**< IOMUXC select input index */
702 kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 90U, /**< IOMUXC select input index */
703 kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 91U, /**< IOMUXC select input index */
704 kIOMUXC_SAI3_MCLK_SELECT_INPUT = 92U, /**< IOMUXC select input index */
705 kIOMUXC_SAI3_RX_BCLK_SELECT_INPUT = 93U, /**< IOMUXC select input index */
706 kIOMUXC_SAI3_RX_DATA0_SELECT_INPUT = 94U, /**< IOMUXC select input index */
707 kIOMUXC_SAI3_RX_SYNC_SELECT_INPUT = 95U, /**< IOMUXC select input index */
708 kIOMUXC_SAI3_TX_BCLK_SELECT_INPUT = 96U, /**< IOMUXC select input index */
709 kIOMUXC_SAI3_TX_SYNC_SELECT_INPUT = 97U, /**< IOMUXC select input index */
710 kIOMUXC_SEMC_READY_SELECT_INPUT = 98U, /**< IOMUXC select input index */
711 kIOMUXC_SPDIF_IN_SELECT_INPUT = 99U, /**< IOMUXC select input index */
712 kIOMUXC_USB_OTG_OC_SELECT_INPUT = 100U, /**< IOMUXC select input index */
713 kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 101U, /**< IOMUXC select input index */
714 kIOMUXC_USDHC1_WP_SELECT_INPUT = 102U, /**< IOMUXC select input index */
715 kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 103U, /**< IOMUXC select input index */
716 kIOMUXC_USDHC2_WP_SELECT_INPUT = 104U, /**< IOMUXC select input index */
717 kIOMUXC_XBAR1_IN14_SELECT_INPUT = 105U, /**< IOMUXC select input index */
718 kIOMUXC_XBAR1_IN15_SELECT_INPUT = 106U, /**< IOMUXC select input index */
719 kIOMUXC_XBAR1_IN16_SELECT_INPUT = 107U, /**< IOMUXC select input index */
720 kIOMUXC_XBAR1_IN17_SELECT_INPUT = 108U, /**< IOMUXC select input index */
721 kIOMUXC_XBAR1_IN10_SELECT_INPUT = 109U, /**< IOMUXC select input index */
722 kIOMUXC_XBAR1_IN12_SELECT_INPUT = 110U, /**< IOMUXC select input index */
723 kIOMUXC_XBAR1_IN13_SELECT_INPUT = 111U, /**< IOMUXC select input index */
724 kIOMUXC_XBAR1_IN18_SELECT_INPUT = 112U, /**< IOMUXC select input index */
725 kIOMUXC_XBAR1_IN19_SELECT_INPUT = 113U, /**< IOMUXC select input index */
726} iomuxc_select_input_t;
727
728typedef enum _xbar_input_signal
729{
730 kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA_IN0 input. */
731 kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA_IN1 input. */
732 kXBARA1_InputRESERVED2 = 2|0x100U, /**< XBARA_IN2 input is reserved. */
733 kXBARA1_InputRESERVED3 = 3|0x100U, /**< XBARA_IN3 input is reserved. */
734 kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA_IN4 input. */
735 kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA_IN5 input. */
736 kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA_IN6 input. */
737 kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA_IN7 input. */
738 kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA_IN8 input. */
739 kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA_IN9 input. */
740 kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA_IN10 input. */
741 kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA_IN11 input. */
742 kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA_IN12 input. */
743 kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA_IN13 input. */
744 kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA_IN14 input. */
745 kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA_IN15 input. */
746 kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA_IN16 input. */
747 kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA_IN17 input. */
748 kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA_IN18 input. */
749 kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA_IN19 input. */
750 kXBARA1_InputRESERVED20 = 20|0x100U, /**< XBARA_IN20 input is reserved. */
751 kXBARA1_InputRESERVED21 = 21|0x100U, /**< XBARA_IN21 input is reserved. */
752 kXBARA1_InputRESERVED22 = 22|0x100U, /**< XBARA_IN22 input is reserved. */
753 kXBARA1_InputRESERVED23 = 23|0x100U, /**< XBARA_IN23 input is reserved. */
754 kXBARA1_InputRESERVED24 = 24|0x100U, /**< XBARA_IN24 input is reserved. */
755 kXBARA1_InputRESERVED25 = 25|0x100U, /**< XBARA_IN25 input is reserved. */
756 kXBARA1_InputAcmp1Out = 26|0x100U, /**< ACMP1_OUT output assigned to XBARA_IN26 input. */
757 kXBARA1_InputAcmp2Out = 27|0x100U, /**< ACMP2_OUT output assigned to XBARA_IN27 input. */
758 kXBARA1_InputAcmp3Out = 28|0x100U, /**< ACMP3_OUT output assigned to XBARA_IN28 input. */
759 kXBARA1_InputAcmp4Out = 29|0x100U, /**< ACMP4_OUT output assigned to XBARA_IN29 input. */
760 kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA_IN30 input is reserved. */
761 kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA_IN31 input is reserved. */
762 kXBARA1_InputQtimer1Tmr0 = 32|0x100U, /**< QTIMER1_TMR0 output assigned to XBARA_IN32 input. */
763 kXBARA1_InputQtimer1Tmr1 = 33|0x100U, /**< QTIMER1_TMR1 output assigned to XBARA_IN33 input. */
764 kXBARA1_InputQtimer1Tmr2 = 34|0x100U, /**< QTIMER1_TMR2 output assigned to XBARA_IN34 input. */
765 kXBARA1_InputQtimer1Tmr3 = 35|0x100U, /**< QTIMER1_TMR3 output assigned to XBARA_IN35 input. */
766 kXBARA1_InputQtimer2Tmr0 = 36|0x100U, /**< QTIMER2_TMR0 output assigned to XBARA_IN36 input. */
767 kXBARA1_InputQtimer2Tmr1 = 37|0x100U, /**< QTIMER2_TMR1 output assigned to XBARA_IN37 input. */
768 kXBARA1_InputQtimer2Tmr2 = 38|0x100U, /**< QTIMER2_TMR2 output assigned to XBARA_IN38 input. */
769 kXBARA1_InputQtimer2Tmr3 = 39|0x100U, /**< QTIMER2_TMR3 output assigned to XBARA_IN39 input. */
770 kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA_IN40 input. */
771 kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA_IN41 input. */
772 kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA_IN42 input. */
773 kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA_IN43 input. */
774 kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA_IN44 input. */
775 kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA_IN45 input. */
776 kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA_IN46 input. */
777 kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA_IN47 input. */
778 kXBARA1_InputRESERVED48 = 48|0x100U, /**< XBARA_IN48 input is reserved. */
779 kXBARA1_InputRESERVED49 = 49|0x100U, /**< XBARA_IN49 input is reserved. */
780 kXBARA1_InputRESERVED50 = 50|0x100U, /**< XBARA_IN50 input is reserved. */
781 kXBARA1_InputRESERVED51 = 51|0x100U, /**< XBARA_IN51 input is reserved. */
782 kXBARA1_InputRESERVED52 = 52|0x100U, /**< XBARA_IN52 input is reserved. */
783 kXBARA1_InputRESERVED53 = 53|0x100U, /**< XBARA_IN53 input is reserved. */
784 kXBARA1_InputRESERVED54 = 54|0x100U, /**< XBARA_IN54 input is reserved. */
785 kXBARA1_InputRESERVED55 = 55|0x100U, /**< XBARA_IN55 input is reserved. */
786 kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA_IN56 input. */
787 kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA_IN57 input. */
788 kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA_IN58 input. */
789 kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA_IN59 input. */
790 kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA_IN60 input. */
791 kXBARA1_InputEnc2PosMatch = 61|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA_IN61 input. */
792 kXBARA1_InputRESERVED62 = 62|0x100U, /**< XBARA_IN62 input is reserved. */
793 kXBARA1_InputRESERVED63 = 63|0x100U, /**< XBARA_IN63 input is reserved. */
794 kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA_IN64 input. */
795 kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA_IN65 input. */
796 kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA_IN66 input. */
797 kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA_IN67 input. */
798 kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA_IN68 input. */
799 kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA_IN69 input. */
800 kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA_IN70 input. */
801 kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA_IN71 input. */
802 kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA_IN72 input. */
803 kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA_IN73 input. */
804 kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA_IN74 input. */
805 kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA_IN75 input. */
806 kXBARA1_InputRESERVED76 = 76|0x100U, /**< XBARA_IN76 input is reserved. */
807 kXBARA1_InputRESERVED77 = 77|0x100U, /**< XBARA_IN77 input is reserved. */
808 kXBARA1_InputRESERVED78 = 78|0x100U, /**< XBARA_IN78 input is reserved. */
809 kXBARA1_InputRESERVED79 = 79|0x100U, /**< XBARA_IN79 input is reserved. */
810 kXBARA1_InputAdcEtc0Coco0 = 80|0x100U, /**< ADC_ETC0_COCO0 output assigned to XBARA_IN80 input. */
811 kXBARA1_InputAdcEtc0Coco1 = 81|0x100U, /**< ADC_ETC0_COCO1 output assigned to XBARA_IN81 input. */
812 kXBARA1_InputAdcEtc0Coco2 = 82|0x100U, /**< ADC_ETC0_COCO2 output assigned to XBARA_IN82 input. */
813 kXBARA1_InputAdcEtc0Coco3 = 83|0x100U, /**< ADC_ETC0_COCO3 output assigned to XBARA_IN83 input. */
814 kXBARA1_InputAdcEtc1Coco0 = 84|0x100U, /**< ADC_ETC1_COCO0 output assigned to XBARA_IN84 input. */
815 kXBARA1_InputAdcEtc1Coco1 = 85|0x100U, /**< ADC_ETC1_COCO1 output assigned to XBARA_IN85 input. */
816 kXBARA1_InputAdcEtc1Coco2 = 86|0x100U, /**< ADC_ETC1_COCO2 output assigned to XBARA_IN86 input. */
817 kXBARA1_InputAdcEtc1Coco3 = 87|0x100U, /**< ADC_ETC1_COCO3 output assigned to XBARA_IN87 input. */
818 kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB_IN0 input. */
819 kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB_IN1 input. */
820 kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB_IN2 input is reserved. */
821 kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB_IN3 input is reserved. */
822 kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB_IN4 input is reserved. */
823 kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB_IN5 input is reserved. */
824 kXBARB2_InputAcmp1Out = 6|0x200U, /**< ACMP1_OUT output assigned to XBARB_IN6 input. */
825 kXBARB2_InputAcmp2Out = 7|0x200U, /**< ACMP2_OUT output assigned to XBARB_IN7 input. */
826 kXBARB2_InputAcmp3Out = 8|0x200U, /**< ACMP3_OUT output assigned to XBARB_IN8 input. */
827 kXBARB2_InputAcmp4Out = 9|0x200U, /**< ACMP4_OUT output assigned to XBARB_IN9 input. */
828 kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB_IN10 input is reserved. */
829 kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB_IN11 input is reserved. */
830 kXBARB2_InputQtimer1Tmr0 = 12|0x200U, /**< QTIMER1_TMR0 output assigned to XBARB_IN12 input. */
831 kXBARB2_InputQtimer1Tmr1 = 13|0x200U, /**< QTIMER1_TMR1 output assigned to XBARB_IN13 input. */
832 kXBARB2_InputQtimer1Tmr2 = 14|0x200U, /**< QTIMER1_TMR2 output assigned to XBARB_IN14 input. */
833 kXBARB2_InputQtimer1Tmr3 = 15|0x200U, /**< QTIMER1_TMR3 output assigned to XBARB_IN15 input. */
834 kXBARB2_InputQtimer2Tmr0 = 16|0x200U, /**< QTIMER2_TMR0 output assigned to XBARB_IN16 input. */
835 kXBARB2_InputQtimer2Tmr1 = 17|0x200U, /**< QTIMER2_TMR1 output assigned to XBARB_IN17 input. */
836 kXBARB2_InputQtimer2Tmr2 = 18|0x200U, /**< QTIMER2_TMR2 output assigned to XBARB_IN18 input. */
837 kXBARB2_InputQtimer2Tmr3 = 19|0x200U, /**< QTIMER2_TMR3 output assigned to XBARB_IN19 input. */
838 kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB_IN20 input. */
839 kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB_IN21 input. */
840 kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB_IN22 input. */
841 kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB_IN23 input. */
842 kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB_IN24 input. */
843 kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB_IN25 input. */
844 kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB_IN26 input. */
845 kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB_IN27 input. */
846 kXBARB2_InputRESERVED28 = 28|0x200U, /**< XBARB_IN28 input is reserved. */
847 kXBARB2_InputRESERVED29 = 29|0x200U, /**< XBARB_IN29 input is reserved. */
848 kXBARB2_InputRESERVED30 = 30|0x200U, /**< XBARB_IN30 input is reserved. */
849 kXBARB2_InputRESERVED31 = 31|0x200U, /**< XBARB_IN31 input is reserved. */
850 kXBARB2_InputRESERVED32 = 32|0x200U, /**< XBARB_IN32 input is reserved. */
851 kXBARB2_InputRESERVED33 = 33|0x200U, /**< XBARB_IN33 input is reserved. */
852 kXBARB2_InputRESERVED34 = 34|0x200U, /**< XBARB_IN34 input is reserved. */
853 kXBARB2_InputRESERVED35 = 35|0x200U, /**< XBARB_IN35 input is reserved. */
854 kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB_IN36 input. */
855 kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB_IN37 input. */
856 kXBARB2_InputAdcEtc0Coco0 = 38|0x200U, /**< ADC_ETC0_COCO0 output assigned to XBARB_IN38 input. */
857 kXBARB2_InputAdcEtc0Coco1 = 39|0x200U, /**< ADC_ETC0_COCO1 output assigned to XBARB_IN39 input. */
858 kXBARB2_InputAdcEtc0Coco2 = 40|0x200U, /**< ADC_ETC0_COCO2 output assigned to XBARB_IN40 input. */
859 kXBARB2_InputAdcEtc0Coco3 = 41|0x200U, /**< ADC_ETC0_COCO3 output assigned to XBARB_IN41 input. */
860 kXBARB2_InputAdcEtc1Coco0 = 42|0x200U, /**< ADC_ETC1_COCO0 output assigned to XBARB_IN42 input. */
861 kXBARB2_InputAdcEtc1Coco1 = 43|0x200U, /**< ADC_ETC1_COCO1 output assigned to XBARB_IN43 input. */
862 kXBARB2_InputAdcEtc1Coco2 = 44|0x200U, /**< ADC_ETC1_COCO2 output assigned to XBARB_IN44 input. */
863 kXBARB2_InputAdcEtc1Coco3 = 45|0x200U, /**< ADC_ETC1_COCO3 output assigned to XBARB_IN45 input. */
864 kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB_IN46 input. */
865 kXBARB2_InputEnc2PosMatch = 47|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB_IN47 input. */
866 kXBARB2_InputRESERVED48 = 48|0x200U, /**< XBARB_IN48 input is reserved. */
867 kXBARB2_InputRESERVED49 = 49|0x200U, /**< XBARB_IN49 input is reserved. */
868 kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB_IN50 input. */
869 kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB_IN51 input. */
870 kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB_IN52 input. */
871 kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB_IN53 input. */
872 kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB_IN54 input. */
873 kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB_IN55 input. */
874 kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB_IN56 input. */
875 kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB_IN57 input. */
876} xbar_input_signal_t;
877
878typedef enum _xbar_output_signal
879{
880 kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA_OUT0 output assigned to DMA_CH_MUX_REQ30 */
881 kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA_OUT1 output assigned to DMA_CH_MUX_REQ31 */
882 kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA_OUT2 output assigned to DMA_CH_MUX_REQ94 */
883 kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA_OUT3 output assigned to DMA_CH_MUX_REQ95 */
884 kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
885 kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
886 kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
887 kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
888 kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
889 kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
890 kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
891 kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
892 kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
893 kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
894 kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
895 kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
896 kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
897 kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
898 kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
899 kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
900 kXBARA1_OutputAcmp1Sample = 20|0x100U, /**< XBARA_OUT20 output assigned to ACMP1_SAMPLE */
901 kXBARA1_OutputAcmp2Sample = 21|0x100U, /**< XBARA_OUT21 output assigned to ACMP2_SAMPLE */
902 kXBARA1_OutputAcmp3Sample = 22|0x100U, /**< XBARA_OUT22 output assigned to ACMP3_SAMPLE */
903 kXBARA1_OutputAcmp4Sample = 23|0x100U, /**< XBARA_OUT23 output assigned to ACMP4_SAMPLE */
904 kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA_OUT24 output is reserved. */
905 kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA_OUT25 output is reserved. */
906 kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA_OUT26 output assigned to FLEXPWM1_EXTA0 */
907 kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA_OUT27 output assigned to FLEXPWM1_EXTA1 */
908 kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA_OUT28 output assigned to FLEXPWM1_EXTA2 */
909 kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA_OUT29 output assigned to FLEXPWM1_EXTA3 */
910 kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
911 kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
912 kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
913 kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
914 kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA_OUT34 output assigned to FLEXPWM1_EXT_CLK */
915 kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA_OUT35 output assigned to FLEXPWM1_FAULT0 */
916 kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA_OUT36 output assigned to FLEXPWM1_FAULT1 */
917 kXBARA1_OutputFlexpwm12Fault2 = 37|0x100U, /**< XBARA_OUT37 output assigned to FLEXPWM1_2_FAULT2 */
918 kXBARA1_OutputFlexpwm12Fault3 = 38|0x100U, /**< XBARA_OUT38 output assigned to FLEXPWM1_2_FAULT3 */
919 kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
920 kXBARA1_OutputFlexpwm2Exta0 = 40|0x100U, /**< XBARA_OUT40 output assigned to FLEXPWM2_EXTA0 */
921 kXBARA1_OutputFlexpwm2Exta1 = 41|0x100U, /**< XBARA_OUT41 output assigned to FLEXPWM2_EXTA1 */
922 kXBARA1_OutputFlexpwm2Exta2 = 42|0x100U, /**< XBARA_OUT42 output assigned to FLEXPWM2_EXTA2 */
923 kXBARA1_OutputFlexpwm2Exta3 = 43|0x100U, /**< XBARA_OUT43 output assigned to FLEXPWM2_EXTA3 */
924 kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, /**< XBARA_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
925 kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, /**< XBARA_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
926 kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, /**< XBARA_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
927 kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U, /**< XBARA_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
928 kXBARA1_OutputFlexpwm2ExtClk = 48|0x100U, /**< XBARA_OUT48 output assigned to FLEXPWM2_EXT_CLK */
929 kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, /**< XBARA_OUT49 output assigned to FLEXPWM2_FAULT0 */
930 kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, /**< XBARA_OUT50 output assigned to FLEXPWM2_FAULT1 */
931 kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U, /**< XBARA_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
932 kXBARA1_OutputRESERVED52 = 52|0x100U, /**< XBARA_OUT52 output is reserved. */
933 kXBARA1_OutputRESERVED53 = 53|0x100U, /**< XBARA_OUT53 output is reserved. */
934 kXBARA1_OutputRESERVED54 = 54|0x100U, /**< XBARA_OUT54 output is reserved. */
935 kXBARA1_OutputRESERVED55 = 55|0x100U, /**< XBARA_OUT55 output is reserved. */
936 kXBARA1_OutputRESERVED56 = 56|0x100U, /**< XBARA_OUT56 output is reserved. */
937 kXBARA1_OutputRESERVED57 = 57|0x100U, /**< XBARA_OUT57 output is reserved. */
938 kXBARA1_OutputRESERVED58 = 58|0x100U, /**< XBARA_OUT58 output is reserved. */
939 kXBARA1_OutputRESERVED59 = 59|0x100U, /**< XBARA_OUT59 output is reserved. */
940 kXBARA1_OutputRESERVED60 = 60|0x100U, /**< XBARA_OUT60 output is reserved. */
941 kXBARA1_OutputRESERVED61 = 61|0x100U, /**< XBARA_OUT61 output is reserved. */
942 kXBARA1_OutputRESERVED62 = 62|0x100U, /**< XBARA_OUT62 output is reserved. */
943 kXBARA1_OutputRESERVED63 = 63|0x100U, /**< XBARA_OUT63 output is reserved. */
944 kXBARA1_OutputRESERVED64 = 64|0x100U, /**< XBARA_OUT64 output is reserved. */
945 kXBARA1_OutputRESERVED65 = 65|0x100U, /**< XBARA_OUT65 output is reserved. */
946 kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA_OUT66 output assigned to ENC1_PHASE_A_INPUT */
947 kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA_OUT67 output assigned to ENC1_PHASE_B_INPUT */
948 kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA_OUT68 output assigned to ENC1_INDEX */
949 kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA_OUT69 output assigned to ENC1_HOME */
950 kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA_OUT70 output assigned to ENC1_TRIGGER */
951 kXBARA1_OutputEnc2PhaseAInput = 71|0x100U, /**< XBARA_OUT71 output assigned to ENC2_PHASE_A_INPUT */
952 kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, /**< XBARA_OUT72 output assigned to ENC2_PHASE_B_INPUT */
953 kXBARA1_OutputEnc2Index = 73|0x100U, /**< XBARA_OUT73 output assigned to ENC2_INDEX */
954 kXBARA1_OutputEnc2Home = 74|0x100U, /**< XBARA_OUT74 output assigned to ENC2_HOME */
955 kXBARA1_OutputEnc2Trigger = 75|0x100U, /**< XBARA_OUT75 output assigned to ENC2_TRIGGER */
956 kXBARA1_OutputRESERVED76 = 76|0x100U, /**< XBARA_OUT76 output is reserved. */
957 kXBARA1_OutputRESERVED77 = 77|0x100U, /**< XBARA_OUT77 output is reserved. */
958 kXBARA1_OutputRESERVED78 = 78|0x100U, /**< XBARA_OUT78 output is reserved. */
959 kXBARA1_OutputRESERVED79 = 79|0x100U, /**< XBARA_OUT79 output is reserved. */
960 kXBARA1_OutputRESERVED80 = 80|0x100U, /**< XBARA_OUT80 output is reserved. */
961 kXBARA1_OutputRESERVED81 = 81|0x100U, /**< XBARA_OUT81 output is reserved. */
962 kXBARA1_OutputRESERVED82 = 82|0x100U, /**< XBARA_OUT82 output is reserved. */
963 kXBARA1_OutputRESERVED83 = 83|0x100U, /**< XBARA_OUT83 output is reserved. */
964 kXBARA1_OutputRESERVED84 = 84|0x100U, /**< XBARA_OUT84 output is reserved. */
965 kXBARA1_OutputRESERVED85 = 85|0x100U, /**< XBARA_OUT85 output is reserved. */
966 kXBARA1_OutputQtimer1Tmr0 = 86|0x100U, /**< XBARA_OUT86 output assigned to QTIMER1_TMR0 */
967 kXBARA1_OutputQtimer1Tmr1 = 87|0x100U, /**< XBARA_OUT87 output assigned to QTIMER1_TMR1 */
968 kXBARA1_OutputQtimer1Tmr2 = 88|0x100U, /**< XBARA_OUT88 output assigned to QTIMER1_TMR2 */
969 kXBARA1_OutputQtimer1Tmr3 = 89|0x100U, /**< XBARA_OUT89 output assigned to QTIMER1_TMR3 */
970 kXBARA1_OutputQtimer2Tmr0 = 90|0x100U, /**< XBARA_OUT90 output assigned to QTIMER2_TMR0 */
971 kXBARA1_OutputQtimer2Tmr1 = 91|0x100U, /**< XBARA_OUT91 output assigned to QTIMER2_TMR1 */
972 kXBARA1_OutputQtimer2Tmr2 = 92|0x100U, /**< XBARA_OUT92 output assigned to QTIMER2_TMR2 */
973 kXBARA1_OutputQtimer2Tmr3 = 93|0x100U, /**< XBARA_OUT93 output assigned to QTIMER2_TMR3 */
974 kXBARA1_OutputRESERVED94 = 94|0x100U, /**< XBARA_OUT94 output is reserved. */
975 kXBARA1_OutputRESERVED95 = 95|0x100U, /**< XBARA_OUT95 output is reserved. */
976 kXBARA1_OutputRESERVED96 = 96|0x100U, /**< XBARA_OUT96 output is reserved. */
977 kXBARA1_OutputRESERVED97 = 97|0x100U, /**< XBARA_OUT97 output is reserved. */
978 kXBARA1_OutputRESERVED98 = 98|0x100U, /**< XBARA_OUT98 output is reserved. */
979 kXBARA1_OutputRESERVED99 = 99|0x100U, /**< XBARA_OUT99 output is reserved. */
980 kXBARA1_OutputRESERVED100 = 100|0x100U, /**< XBARA_OUT100 output is reserved. */
981 kXBARA1_OutputRESERVED101 = 101|0x100U, /**< XBARA_OUT101 output is reserved. */
982 kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA_OUT102 output assigned to EWM_EWM_IN */
983 kXBARA1_OutputAdcEtcTrig00 = 103|0x100U, /**< XBARA_OUT103 output assigned to ADC_ETC_TRIG00 */
984 kXBARA1_OutputAdcEtcTrig01 = 104|0x100U, /**< XBARA_OUT104 output assigned to ADC_ETC_TRIG01 */
985 kXBARA1_OutputAdcEtcTrig02 = 105|0x100U, /**< XBARA_OUT105 output assigned to ADC_ETC_TRIG02 */
986 kXBARA1_OutputAdcEtcTrig03 = 106|0x100U, /**< XBARA_OUT106 output assigned to ADC_ETC_TRIG03 */
987 kXBARA1_OutputAdcEtcTrig10 = 107|0x100U, /**< XBARA_OUT107 output assigned to ADC_ETC_TRIG10 */
988 kXBARA1_OutputAdcEtcTrig11 = 108|0x100U, /**< XBARA_OUT108 output assigned to ADC_ETC_TRIG11 */
989 kXBARA1_OutputAdcEtcTrig12 = 109|0x100U, /**< XBARA_OUT109 output assigned to ADC_ETC_TRIG12 */
990 kXBARA1_OutputAdcEtcTrig13 = 110|0x100U, /**< XBARA_OUT110 output assigned to ADC_ETC_TRIG13 */
991 kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA_OUT111 output assigned to LPI2C1_TRG_INPUT */
992 kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA_OUT112 output assigned to LPI2C2_TRG_INPUT */
993 kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, /**< XBARA_OUT113 output assigned to LPI2C3_TRG_INPUT */
994 kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, /**< XBARA_OUT114 output assigned to LPI2C4_TRG_INPUT */
995 kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA_OUT115 output assigned to LPSPI1_TRG_INPUT */
996 kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA_OUT116 output assigned to LPSPI2_TRG_INPUT */
997 kXBARA1_OutputLpspi3TrgInput = 117|0x100U, /**< XBARA_OUT117 output assigned to LPSPI3_TRG_INPUT */
998 kXBARA1_OutputLpspi4TrgInput = 118|0x100U, /**< XBARA_OUT118 output assigned to LPSPI4_TRG_INPUT */
999 kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA_OUT119 output assigned to LPUART1_TRG_INPUT */
1000 kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA_OUT120 output assigned to LPUART2_TRG_INPUT */
1001 kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA_OUT121 output assigned to LPUART3_TRG_INPUT */
1002 kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA_OUT122 output assigned to LPUART4_TRG_INPUT */
1003 kXBARA1_OutputLpuart5TrgInput = 123|0x100U, /**< XBARA_OUT123 output assigned to LPUART5_TRG_INPUT */
1004 kXBARA1_OutputLpuart6TrgInput = 124|0x100U, /**< XBARA_OUT124 output assigned to LPUART6_TRG_INPUT */
1005 kXBARA1_OutputLpuart7TrgInput = 125|0x100U, /**< XBARA_OUT125 output assigned to LPUART7_TRG_INPUT */
1006 kXBARA1_OutputLpuart8TrgInput = 126|0x100U, /**< XBARA_OUT126 output assigned to LPUART8_TRG_INPUT */
1007 kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
1008 kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
1009 kXBARA1_OutputRESERVED129 = 129|0x100U, /**< XBARA_OUT129 output is reserved. */
1010 kXBARA1_OutputRESERVED130 = 130|0x100U, /**< XBARA_OUT130 output is reserved. */
1011 kXBARA1_OutputRESERVED131 = 131|0x100U, /**< XBARA_OUT131 output is reserved. */
1012 kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB_OUT0 output assigned to AOI1_IN00 */
1013 kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB_OUT1 output assigned to AOI1_IN01 */
1014 kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB_OUT2 output assigned to AOI1_IN02 */
1015 kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB_OUT3 output assigned to AOI1_IN03 */
1016 kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB_OUT4 output assigned to AOI1_IN04 */
1017 kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB_OUT5 output assigned to AOI1_IN05 */
1018 kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB_OUT6 output assigned to AOI1_IN06 */
1019 kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB_OUT7 output assigned to AOI1_IN07 */
1020 kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB_OUT8 output assigned to AOI1_IN08 */
1021 kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB_OUT9 output assigned to AOI1_IN09 */
1022 kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB_OUT10 output assigned to AOI1_IN10 */
1023 kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB_OUT11 output assigned to AOI1_IN11 */
1024 kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB_OUT12 output assigned to AOI1_IN12 */
1025 kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB_OUT13 output assigned to AOI1_IN13 */
1026 kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB_OUT14 output assigned to AOI1_IN14 */
1027 kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB_OUT15 output assigned to AOI1_IN15 */
1028} xbar_output_signal_t;
1029
1030
1031/*!
1032 * @}
1033 */ /* end of group Mapping_Information */
1034
1035
1036/* ----------------------------------------------------------------------------
1037 -- Device Peripheral Access Layer
1038 ---------------------------------------------------------------------------- */
1039
1040/*!
1041 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
1042 * @{
1043 */
1044
1045
1046/*
1047** Start of section using anonymous unions
1048*/
1049
1050#if defined(__ARMCC_VERSION)
1051 #if (__ARMCC_VERSION >= 6010050)
1052 #pragma clang diagnostic push
1053 #else
1054 #pragma push
1055 #pragma anon_unions
1056 #endif
1057#elif defined(__CWCC__)
1058 #pragma push
1059 #pragma cpp_extensions on
1060#elif defined(__GNUC__)
1061 /* anonymous unions are enabled by default */
1062#elif defined(__IAR_SYSTEMS_ICC__)
1063 #pragma language=extended
1064#else
1065 #error Not supported compiler type
1066#endif
1067
1068/* ----------------------------------------------------------------------------
1069 -- ADC Peripheral Access Layer
1070 ---------------------------------------------------------------------------- */
1071
1072/*!
1073 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
1074 * @{
1075 */
1076
1077/** ADC - Register Layout Typedef */
1078typedef struct {
1079 __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */
1080 __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */
1081 __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */
1082 __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */
1083 __IO uint32_t GC; /**< General control register, offset: 0x48 */
1084 __IO uint32_t GS; /**< General status register, offset: 0x4C */
1085 __IO uint32_t CV; /**< Compare value register, offset: 0x50 */
1086 __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */
1087 __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */
1088} ADC_Type;
1089
1090/* ----------------------------------------------------------------------------
1091 -- ADC Register Masks
1092 ---------------------------------------------------------------------------- */
1093
1094/*!
1095 * @addtogroup ADC_Register_Masks ADC Register Masks
1096 * @{
1097 */
1098
1099/*! @name HC - Control register for hardware triggers */
1100/*! @{ */
1101#define ADC_HC_ADCH_MASK (0x1FU)
1102#define ADC_HC_ADCH_SHIFT (0U)
1103/*! ADCH - Input Channel Select
1104 * 0b10000..External channel selection from ADC_ETC
1105 * 0b11000..Reserved.
1106 * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally
1107 * 0b11010..Reserved.
1108 * 0b11011..Reserved.
1109 * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion.
1110 */
1111#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
1112#define ADC_HC_AIEN_MASK (0x80U)
1113#define ADC_HC_AIEN_SHIFT (7U)
1114/*! AIEN - Conversion Complete Interrupt Enable/Disable Control
1115 * 0b1..Conversion complete interrupt enabled
1116 * 0b0..Conversion complete interrupt disabled
1117 */
1118#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
1119/*! @} */
1120
1121/* The count of ADC_HC */
1122#define ADC_HC_COUNT (8U)
1123
1124/*! @name HS - Status register for HW triggers */
1125/*! @{ */
1126#define ADC_HS_COCO0_MASK (0x1U)
1127#define ADC_HS_COCO0_SHIFT (0U)
1128/*! COCO0 - Conversion Complete Flag
1129 */
1130#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
1131#define ADC_HS_COCO1_MASK (0x2U)
1132#define ADC_HS_COCO1_SHIFT (1U)
1133/*! COCO1 - Conversion Complete Flag
1134 */
1135#define ADC_HS_COCO1(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO1_SHIFT)) & ADC_HS_COCO1_MASK)
1136#define ADC_HS_COCO2_MASK (0x4U)
1137#define ADC_HS_COCO2_SHIFT (2U)
1138#define ADC_HS_COCO2(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO2_SHIFT)) & ADC_HS_COCO2_MASK)
1139#define ADC_HS_COCO3_MASK (0x8U)
1140#define ADC_HS_COCO3_SHIFT (3U)
1141#define ADC_HS_COCO3(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO3_SHIFT)) & ADC_HS_COCO3_MASK)
1142#define ADC_HS_COCO4_MASK (0x10U)
1143#define ADC_HS_COCO4_SHIFT (4U)
1144#define ADC_HS_COCO4(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO4_SHIFT)) & ADC_HS_COCO4_MASK)
1145#define ADC_HS_COCO5_MASK (0x20U)
1146#define ADC_HS_COCO5_SHIFT (5U)
1147#define ADC_HS_COCO5(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO5_SHIFT)) & ADC_HS_COCO5_MASK)
1148#define ADC_HS_COCO6_MASK (0x40U)
1149#define ADC_HS_COCO6_SHIFT (6U)
1150#define ADC_HS_COCO6(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO6_SHIFT)) & ADC_HS_COCO6_MASK)
1151#define ADC_HS_COCO7_MASK (0x80U)
1152#define ADC_HS_COCO7_SHIFT (7U)
1153#define ADC_HS_COCO7(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO7_SHIFT)) & ADC_HS_COCO7_MASK)
1154/*! @} */
1155
1156/*! @name R - Data result register for HW triggers */
1157/*! @{ */
1158#define ADC_R_CDATA_MASK (0xFFFU)
1159#define ADC_R_CDATA_SHIFT (0U)
1160/*! CDATA - Data (result of an ADC conversion)
1161 */
1162#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
1163/*! @} */
1164
1165/* The count of ADC_R */
1166#define ADC_R_COUNT (8U)
1167
1168/*! @name CFG - Configuration register */
1169/*! @{ */
1170#define ADC_CFG_ADICLK_MASK (0x3U)
1171#define ADC_CFG_ADICLK_SHIFT (0U)
1172/*! ADICLK - Input Clock Select
1173 * 0b00..IPG clock
1174 * 0b01..IPG clock divided by 2
1175 * 0b10..Reserved
1176 * 0b11..Asynchronous clock (ADACK)
1177 */
1178#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
1179#define ADC_CFG_MODE_MASK (0xCU)
1180#define ADC_CFG_MODE_SHIFT (2U)
1181/*! MODE - Conversion Mode Selection
1182 * 0b00..8-bit conversion
1183 * 0b01..10-bit conversion
1184 * 0b10..12-bit conversion
1185 * 0b11..Reserved
1186 */
1187#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
1188#define ADC_CFG_ADLSMP_MASK (0x10U)
1189#define ADC_CFG_ADLSMP_SHIFT (4U)
1190/*! ADLSMP - Long Sample Time Configuration
1191 * 0b0..Short sample mode.
1192 * 0b1..Long sample mode.
1193 */
1194#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
1195#define ADC_CFG_ADIV_MASK (0x60U)
1196#define ADC_CFG_ADIV_SHIFT (5U)
1197/*! ADIV - Clock Divide Select
1198 * 0b00..Input clock
1199 * 0b01..Input clock / 2
1200 * 0b10..Input clock / 4
1201 * 0b11..Input clock / 8
1202 */
1203#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
1204#define ADC_CFG_ADLPC_MASK (0x80U)
1205#define ADC_CFG_ADLPC_SHIFT (7U)
1206/*! ADLPC - Low-Power Configuration
1207 * 0b0..ADC hard block not in low power mode.
1208 * 0b1..ADC hard block in low power mode.
1209 */
1210#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
1211#define ADC_CFG_ADSTS_MASK (0x300U)
1212#define ADC_CFG_ADSTS_SHIFT (8U)
1213/*! ADSTS
1214 * 0b00..Sample period (ADC clocks) = 3 if ADLSMP=0b Sample period (ADC clocks) = 13 if ADLSMP=1b
1215 * 0b01..Sample period (ADC clocks) = 5 if ADLSMP=0b Sample period (ADC clocks) = 17 if ADLSMP=1b
1216 * 0b10..Sample period (ADC clocks) = 7 if ADLSMP=0b Sample period (ADC clocks) = 21 if ADLSMP=1b
1217 * 0b11..Sample period (ADC clocks) = 9 if ADLSMP=0b Sample period (ADC clocks) = 25 if ADLSMP=1b
1218 */
1219#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
1220#define ADC_CFG_ADHSC_MASK (0x400U)
1221#define ADC_CFG_ADHSC_SHIFT (10U)
1222/*! ADHSC - High Speed Configuration
1223 * 0b0..Normal conversion selected.
1224 * 0b1..High speed conversion selected.
1225 */
1226#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
1227#define ADC_CFG_REFSEL_MASK (0x1800U)
1228#define ADC_CFG_REFSEL_SHIFT (11U)
1229/*! REFSEL - Voltage Reference Selection
1230 * 0b00..Selects VREFH/VREFL as reference voltage.
1231 * 0b01..Reserved
1232 * 0b10..Reserved
1233 * 0b11..Reserved
1234 */
1235#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
1236#define ADC_CFG_ADTRG_MASK (0x2000U)
1237#define ADC_CFG_ADTRG_SHIFT (13U)
1238/*! ADTRG - Conversion Trigger Select
1239 * 0b0..Software trigger selected
1240 * 0b1..Hardware trigger selected
1241 */
1242#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
1243#define ADC_CFG_AVGS_MASK (0xC000U)
1244#define ADC_CFG_AVGS_SHIFT (14U)
1245/*! AVGS - Hardware Average select
1246 * 0b00..4 samples averaged
1247 * 0b01..8 samples averaged
1248 * 0b10..16 samples averaged
1249 * 0b11..32 samples averaged
1250 */
1251#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
1252#define ADC_CFG_OVWREN_MASK (0x10000U)
1253#define ADC_CFG_OVWREN_SHIFT (16U)
1254/*! OVWREN - Data Overwrite Enable
1255 * 0b1..Enable the overwriting.
1256 * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.
1257 */
1258#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
1259/*! @} */
1260
1261/*! @name GC - General control register */
1262/*! @{ */
1263#define ADC_GC_ADACKEN_MASK (0x1U)
1264#define ADC_GC_ADACKEN_SHIFT (0U)
1265/*! ADACKEN - Asynchronous clock output enable
1266 * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.
1267 * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC
1268 */
1269#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
1270#define ADC_GC_DMAEN_MASK (0x2U)
1271#define ADC_GC_DMAEN_SHIFT (1U)
1272/*! DMAEN - DMA Enable
1273 * 0b0..DMA disabled (default)
1274 * 0b1..DMA enabled
1275 */
1276#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
1277#define ADC_GC_ACREN_MASK (0x4U)
1278#define ADC_GC_ACREN_SHIFT (2U)
1279/*! ACREN - Compare Function Range Enable
1280 * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared.
1281 * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.
1282 */
1283#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
1284#define ADC_GC_ACFGT_MASK (0x8U)
1285#define ADC_GC_ACFGT_SHIFT (3U)
1286/*! ACFGT - Compare Function Greater Than Enable
1287 * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive"
1288 * functionality based on the values placed in the ADC_CV register.
1289 * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive"
1290 * functionality based on the values placed in the ADC_CV registers.
1291 */
1292#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
1293#define ADC_GC_ACFE_MASK (0x10U)
1294#define ADC_GC_ACFE_SHIFT (4U)
1295/*! ACFE - Compare Function Enable
1296 * 0b0..Compare function disabled
1297 * 0b1..Compare function enabled
1298 */
1299#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
1300#define ADC_GC_AVGE_MASK (0x20U)
1301#define ADC_GC_AVGE_SHIFT (5U)
1302/*! AVGE - Hardware average enable
1303 * 0b0..Hardware average function disabled
1304 * 0b1..Hardware average function enabled
1305 */
1306#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
1307#define ADC_GC_ADCO_MASK (0x40U)
1308#define ADC_GC_ADCO_SHIFT (6U)
1309/*! ADCO - Continuous Conversion Enable
1310 * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
1311 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
1312 */
1313#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
1314#define ADC_GC_CAL_MASK (0x80U)
1315#define ADC_GC_CAL_SHIFT (7U)
1316/*! CAL - Calibration
1317 */
1318#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
1319/*! @} */
1320
1321/*! @name GS - General status register */
1322/*! @{ */
1323#define ADC_GS_ADACT_MASK (0x1U)
1324#define ADC_GS_ADACT_SHIFT (0U)
1325/*! ADACT - Conversion Active
1326 * 0b0..Conversion not in progress.
1327 * 0b1..Conversion in progress.
1328 */
1329#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
1330#define ADC_GS_CALF_MASK (0x2U)
1331#define ADC_GS_CALF_SHIFT (1U)
1332/*! CALF - Calibration Failed Flag
1333 * 0b0..Calibration completed normally.
1334 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
1335 */
1336#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
1337#define ADC_GS_AWKST_MASK (0x4U)
1338#define ADC_GS_AWKST_SHIFT (2U)
1339/*! AWKST - Asynchronous wakeup interrupt status
1340 * 0b1..Asynchronous wake up interrupt occurred in stop mode.
1341 * 0b0..No asynchronous interrupt.
1342 */
1343#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
1344/*! @} */
1345
1346/*! @name CV - Compare value register */
1347/*! @{ */
1348#define ADC_CV_CV1_MASK (0xFFFU)
1349#define ADC_CV_CV1_SHIFT (0U)
1350/*! CV1 - Compare Value 1
1351 */
1352#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
1353#define ADC_CV_CV2_MASK (0xFFF0000U)
1354#define ADC_CV_CV2_SHIFT (16U)
1355/*! CV2 - Compare Value 2
1356 */
1357#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
1358/*! @} */
1359
1360/*! @name OFS - Offset correction value register */
1361/*! @{ */
1362#define ADC_OFS_OFS_MASK (0xFFFU)
1363#define ADC_OFS_OFS_SHIFT (0U)
1364/*! OFS - Offset value
1365 */
1366#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
1367#define ADC_OFS_SIGN_MASK (0x1000U)
1368#define ADC_OFS_SIGN_SHIFT (12U)
1369/*! SIGN - Sign bit
1370 * 0b0..The offset value is added with the raw result
1371 * 0b1..The offset value is subtracted from the raw converted value
1372 */
1373#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
1374/*! @} */
1375
1376/*! @name CAL - Calibration value register */
1377/*! @{ */
1378#define ADC_CAL_CAL_CODE_MASK (0xFU)
1379#define ADC_CAL_CAL_CODE_SHIFT (0U)
1380/*! CAL_CODE - Calibration Result Value
1381 */
1382#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)
1383/*! @} */
1384
1385
1386/*!
1387 * @}
1388 */ /* end of group ADC_Register_Masks */
1389
1390
1391/* ADC - Peripheral instance base addresses */
1392/** Peripheral ADC1 base address */
1393#define ADC1_BASE (0x400C4000u)
1394/** Peripheral ADC1 base pointer */
1395#define ADC1 ((ADC_Type *)ADC1_BASE)
1396/** Peripheral ADC2 base address */
1397#define ADC2_BASE (0x400C8000u)
1398/** Peripheral ADC2 base pointer */
1399#define ADC2 ((ADC_Type *)ADC2_BASE)
1400/** Array initializer of ADC peripheral base addresses */
1401#define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE }
1402/** Array initializer of ADC peripheral base pointers */
1403#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 }
1404/** Interrupt vectors for the ADC peripheral type */
1405#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
1406
1407/*!
1408 * @}
1409 */ /* end of group ADC_Peripheral_Access_Layer */
1410
1411
1412/* ----------------------------------------------------------------------------
1413 -- ADC_ETC Peripheral Access Layer
1414 ---------------------------------------------------------------------------- */
1415
1416/*!
1417 * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
1418 * @{
1419 */
1420
1421/** ADC_ETC - Register Layout Typedef */
1422typedef struct {
1423 __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */
1424 __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */
1425 __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */
1426 __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */
1427 struct { /* offset: 0x10, array step: 0x28 */
1428 __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG Control Register, array offset: 0x10, array step: 0x28 */
1429 __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28 */
1430 __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */
1431 __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */
1432 __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */
1433 __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */
1434 __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */
1435 __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */
1436 __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */
1437 __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */
1438 } TRIG[8];
1439} ADC_ETC_Type;
1440
1441/* ----------------------------------------------------------------------------
1442 -- ADC_ETC Register Masks
1443 ---------------------------------------------------------------------------- */
1444
1445/*!
1446 * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
1447 * @{
1448 */
1449
1450/*! @name CTRL - ADC_ETC Global Control Register */
1451/*! @{ */
1452#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
1453#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
1454#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
1455#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
1456#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
1457#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
1458#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
1459#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
1460#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
1461#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
1462#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
1463#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
1464#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
1465#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
1466#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
1467#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
1468#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
1469#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
1470#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
1471#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
1472#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
1473#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
1474#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
1475#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
1476#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
1477#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
1478#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
1479/*! @} */
1480
1481/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
1482/*! @{ */
1483#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
1484#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
1485#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
1486#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
1487#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
1488#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
1489#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
1490#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
1491#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
1492#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
1493#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
1494#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
1495#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
1496#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
1497#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
1498#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
1499#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
1500#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
1501#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
1502#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
1503#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
1504#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
1505#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
1506#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
1507#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
1508#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
1509#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
1510#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
1511#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
1512#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
1513#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
1514#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
1515#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
1516#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
1517#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
1518#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
1519#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
1520#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
1521#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
1522#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
1523#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
1524#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
1525#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
1526#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
1527#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
1528#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
1529#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
1530#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
1531/*! @} */
1532
1533/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */
1534/*! @{ */
1535#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
1536#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
1537#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)
1538#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
1539#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
1540#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)
1541#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
1542#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
1543#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)
1544#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
1545#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
1546#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)
1547#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
1548#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
1549#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)
1550#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
1551#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
1552#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)
1553#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
1554#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
1555#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)
1556#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
1557#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
1558#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)
1559#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
1560#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
1561#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)
1562#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
1563#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
1564#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)
1565#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
1566#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
1567#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)
1568#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
1569#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
1570#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)
1571#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
1572#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
1573#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)
1574#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
1575#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
1576#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)
1577#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
1578#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
1579#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)
1580#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
1581#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
1582#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)
1583/*! @} */
1584
1585/*! @name DMA_CTRL - ETC DMA control Register */
1586/*! @{ */
1587#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
1588#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
1589#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
1590#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
1591#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
1592#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
1593#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
1594#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
1595#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
1596#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
1597#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
1598#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
1599#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
1600#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
1601#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
1602#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
1603#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
1604#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
1605#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
1606#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
1607#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
1608#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
1609#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
1610#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
1611#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
1612#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
1613#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
1614#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
1615#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
1616#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
1617#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
1618#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
1619#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
1620#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
1621#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
1622#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
1623#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
1624#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
1625#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
1626#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
1627#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
1628#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
1629#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
1630#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
1631#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
1632#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
1633#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
1634#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
1635/*! @} */
1636
1637/*! @name TRIGn_CTRL - ETC_TRIG Control Register */
1638/*! @{ */
1639#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
1640#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
1641#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
1642#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
1643#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
1644#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
1645#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
1646#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
1647#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
1648#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
1649#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
1650#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
1651#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
1652#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
1653#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
1654/*! @} */
1655
1656/* The count of ADC_ETC_TRIGn_CTRL */
1657#define ADC_ETC_TRIGn_CTRL_COUNT (8U)
1658
1659/*! @name TRIGn_COUNTER - ETC_TRIG Counter Register */
1660/*! @{ */
1661#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
1662#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
1663#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
1664#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
1665#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
1666#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
1667/*! @} */
1668
1669/* The count of ADC_ETC_TRIGn_COUNTER */
1670#define ADC_ETC_TRIGn_COUNTER_COUNT (8U)
1671
1672/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
1673/*! @{ */
1674#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
1675#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
1676#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
1677#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
1678#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
1679#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
1680#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
1681#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
1682#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
1683#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
1684#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
1685#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
1686#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
1687#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
1688#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
1689#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
1690#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
1691#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
1692#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
1693#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
1694#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
1695#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
1696#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
1697#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
1698/*! @} */
1699
1700/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
1701#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
1702
1703/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
1704/*! @{ */
1705#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
1706#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
1707#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
1708#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
1709#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
1710#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
1711#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
1712#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
1713#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
1714#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
1715#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
1716#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
1717#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
1718#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
1719#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
1720#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
1721#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
1722#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
1723#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
1724#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
1725#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
1726#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
1727#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
1728#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
1729/*! @} */
1730
1731/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
1732#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
1733
1734/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
1735/*! @{ */
1736#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
1737#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
1738#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
1739#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
1740#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
1741#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
1742#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
1743#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
1744#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
1745#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
1746#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
1747#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
1748#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
1749#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
1750#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
1751#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
1752#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
1753#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
1754#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
1755#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
1756#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
1757#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
1758#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
1759#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
1760/*! @} */
1761
1762/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
1763#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
1764
1765/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
1766/*! @{ */
1767#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
1768#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
1769#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
1770#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
1771#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
1772#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
1773#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
1774#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
1775#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
1776#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
1777#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
1778#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
1779#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
1780#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
1781#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
1782#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
1783#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
1784#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
1785#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
1786#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
1787#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
1788#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
1789#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
1790#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
1791/*! @} */
1792
1793/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
1794#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
1795
1796/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
1797/*! @{ */
1798#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
1799#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
1800#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
1801#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
1802#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
1803#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
1804/*! @} */
1805
1806/* The count of ADC_ETC_TRIGn_RESULT_1_0 */
1807#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
1808
1809/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
1810/*! @{ */
1811#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
1812#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
1813#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
1814#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
1815#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
1816#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
1817/*! @} */
1818
1819/* The count of ADC_ETC_TRIGn_RESULT_3_2 */
1820#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
1821
1822/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
1823/*! @{ */
1824#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
1825#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
1826#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
1827#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
1828#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
1829#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
1830/*! @} */
1831
1832/* The count of ADC_ETC_TRIGn_RESULT_5_4 */
1833#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
1834
1835/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
1836/*! @{ */
1837#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
1838#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
1839#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
1840#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
1841#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
1842#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
1843/*! @} */
1844
1845/* The count of ADC_ETC_TRIGn_RESULT_7_6 */
1846#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
1847
1848
1849/*!
1850 * @}
1851 */ /* end of group ADC_ETC_Register_Masks */
1852
1853
1854/* ADC_ETC - Peripheral instance base addresses */
1855/** Peripheral ADC_ETC base address */
1856#define ADC_ETC_BASE (0x403B0000u)
1857/** Peripheral ADC_ETC base pointer */
1858#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
1859/** Array initializer of ADC_ETC peripheral base addresses */
1860#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
1861/** Array initializer of ADC_ETC peripheral base pointers */
1862#define ADC_ETC_BASE_PTRS { ADC_ETC }
1863/** Interrupt vectors for the ADC_ETC peripheral type */
1864#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
1865#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
1866
1867/*!
1868 * @}
1869 */ /* end of group ADC_ETC_Peripheral_Access_Layer */
1870
1871
1872/* ----------------------------------------------------------------------------
1873 -- AIPSTZ Peripheral Access Layer
1874 ---------------------------------------------------------------------------- */
1875
1876/*!
1877 * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
1878 * @{
1879 */
1880
1881/** AIPSTZ - Register Layout Typedef */
1882typedef struct {
1883 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */
1884 uint8_t RESERVED_0[60];
1885 __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
1886 __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
1887 __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
1888 __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
1889 __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
1890} AIPSTZ_Type;
1891
1892/* ----------------------------------------------------------------------------
1893 -- AIPSTZ Register Masks
1894 ---------------------------------------------------------------------------- */
1895
1896/*!
1897 * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
1898 * @{
1899 */
1900
1901/*! @name MPR - Master Priviledge Registers */
1902/*! @{ */
1903#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
1904#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
1905/*! MPROT3
1906 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1907 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1908 * 0bxx0x..This master is not trusted for write accesses.
1909 * 0bxx1x..This master is trusted for write accesses.
1910 * 0bx0xx..This master is not trusted for read accesses.
1911 * 0bx1xx..This master is trusted for read accesses.
1912 * 0b1xxx..Write accesses from this master are allowed to be buffered
1913 */
1914#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
1915#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
1916#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
1917/*! MPROT2
1918 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1919 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1920 * 0bxx0x..This master is not trusted for write accesses.
1921 * 0bxx1x..This master is trusted for write accesses.
1922 * 0bx0xx..This master is not trusted for read accesses.
1923 * 0bx1xx..This master is trusted for read accesses.
1924 * 0b1xxx..Write accesses from this master are allowed to be buffered
1925 */
1926#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
1927#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
1928#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
1929/*! MPROT1
1930 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1931 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1932 * 0bxx0x..This master is not trusted for write accesses.
1933 * 0bxx1x..This master is trusted for write accesses.
1934 * 0bx0xx..This master is not trusted for read accesses.
1935 * 0bx1xx..This master is trusted for read accesses.
1936 * 0b1xxx..Write accesses from this master are allowed to be buffered
1937 */
1938#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
1939#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
1940#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
1941/*! MPROT0
1942 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
1943 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
1944 * 0bxx0x..This master is not trusted for write accesses.
1945 * 0bxx1x..This master is trusted for write accesses.
1946 * 0bx0xx..This master is not trusted for read accesses.
1947 * 0bx1xx..This master is trusted for read accesses.
1948 * 0b1xxx..Write accesses from this master are allowed to be buffered
1949 */
1950#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
1951/*! @} */
1952
1953/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
1954/*! @{ */
1955#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
1956#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
1957/*! OPAC7
1958 * 0bxxx0..Accesses from an untrusted master are allowed.
1959 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1960 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1961 * 0bxx0x..This peripheral allows write accesses.
1962 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1963 * error response and no peripheral access is initiated on the IPS bus.
1964 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1965 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1966 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1967 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1968 * on the IPS bus.
1969 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1970 */
1971#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
1972#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
1973#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
1974/*! OPAC6
1975 * 0bxxx0..Accesses from an untrusted master are allowed.
1976 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1977 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1978 * 0bxx0x..This peripheral allows write accesses.
1979 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1980 * error response and no peripheral access is initiated on the IPS bus.
1981 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1982 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
1983 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
1984 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
1985 * on the IPS bus.
1986 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
1987 */
1988#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
1989#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
1990#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
1991/*! OPAC5
1992 * 0bxxx0..Accesses from an untrusted master are allowed.
1993 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
1994 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
1995 * 0bxx0x..This peripheral allows write accesses.
1996 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
1997 * error response and no peripheral access is initiated on the IPS bus.
1998 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
1999 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2000 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2001 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2002 * on the IPS bus.
2003 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2004 */
2005#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
2006#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
2007#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
2008/*! OPAC4
2009 * 0bxxx0..Accesses from an untrusted master are allowed.
2010 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2011 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2012 * 0bxx0x..This peripheral allows write accesses.
2013 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2014 * error response and no peripheral access is initiated on the IPS bus.
2015 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2016 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2017 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2018 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2019 * on the IPS bus.
2020 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2021 */
2022#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
2023#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
2024#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
2025/*! OPAC3
2026 * 0bxxx0..Accesses from an untrusted master are allowed.
2027 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2028 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2029 * 0bxx0x..This peripheral allows write accesses.
2030 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2031 * error response and no peripheral access is initiated on the IPS bus.
2032 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2033 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2034 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2035 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2036 * on the IPS bus.
2037 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2038 */
2039#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
2040#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
2041#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
2042/*! OPAC2
2043 * 0bxxx0..Accesses from an untrusted master are allowed.
2044 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2045 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2046 * 0bxx0x..This peripheral allows write accesses.
2047 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2048 * error response and no peripheral access is initiated on the IPS bus.
2049 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2050 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2051 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2052 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2053 * on the IPS bus.
2054 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2055 */
2056#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
2057#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
2058#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
2059/*! OPAC1
2060 * 0bxxx0..Accesses from an untrusted master are allowed.
2061 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2062 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2063 * 0bxx0x..This peripheral allows write accesses.
2064 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2065 * error response and no peripheral access is initiated on the IPS bus.
2066 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2067 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2068 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2069 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2070 * on the IPS bus.
2071 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2072 */
2073#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
2074#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
2075#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
2076/*! OPAC0
2077 * 0bxxx0..Accesses from an untrusted master are allowed.
2078 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2079 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2080 * 0bxx0x..This peripheral allows write accesses.
2081 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2082 * error response and no peripheral access is initiated on the IPS bus.
2083 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2084 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2085 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2086 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2087 * on the IPS bus.
2088 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2089 */
2090#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
2091/*! @} */
2092
2093/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
2094/*! @{ */
2095#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
2096#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
2097/*! OPAC15
2098 * 0bxxx0..Accesses from an untrusted master are allowed.
2099 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2100 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2101 * 0bxx0x..This peripheral allows write accesses.
2102 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2103 * error response and no peripheral access is initiated on the IPS bus.
2104 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2105 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2106 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2107 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2108 * on the IPS bus.
2109 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2110 */
2111#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
2112#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
2113#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
2114/*! OPAC14
2115 * 0bxxx0..Accesses from an untrusted master are allowed.
2116 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2117 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2118 * 0bxx0x..This peripheral allows write accesses.
2119 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2120 * error response and no peripheral access is initiated on the IPS bus.
2121 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2122 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2123 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2124 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2125 * on the IPS bus.
2126 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2127 */
2128#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
2129#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
2130#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
2131/*! OPAC13
2132 * 0bxxx0..Accesses from an untrusted master are allowed.
2133 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2134 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2135 * 0bxx0x..This peripheral allows write accesses.
2136 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2137 * error response and no peripheral access is initiated on the IPS bus.
2138 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2139 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2140 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2141 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2142 * on the IPS bus.
2143 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2144 */
2145#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
2146#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
2147#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
2148/*! OPAC12
2149 * 0bxxx0..Accesses from an untrusted master are allowed.
2150 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2151 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2152 * 0bxx0x..This peripheral allows write accesses.
2153 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2154 * error response and no peripheral access is initiated on the IPS bus.
2155 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2156 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2157 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2158 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2159 * on the IPS bus.
2160 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2161 */
2162#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
2163#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
2164#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
2165/*! OPAC11
2166 * 0bxxx0..Accesses from an untrusted master are allowed.
2167 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2168 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2169 * 0bxx0x..This peripheral allows write accesses.
2170 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2171 * error response and no peripheral access is initiated on the IPS bus.
2172 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2173 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2174 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2175 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2176 * on the IPS bus.
2177 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2178 */
2179#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
2180#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
2181#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
2182/*! OPAC10
2183 * 0bxxx0..Accesses from an untrusted master are allowed.
2184 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2185 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2186 * 0bxx0x..This peripheral allows write accesses.
2187 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2188 * error response and no peripheral access is initiated on the IPS bus.
2189 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2190 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2191 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2192 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2193 * on the IPS bus.
2194 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2195 */
2196#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
2197#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
2198#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
2199/*! OPAC9
2200 * 0bxxx0..Accesses from an untrusted master are allowed.
2201 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2202 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2203 * 0bxx0x..This peripheral allows write accesses.
2204 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2205 * error response and no peripheral access is initiated on the IPS bus.
2206 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2207 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2208 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2209 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2210 * on the IPS bus.
2211 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2212 */
2213#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
2214#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
2215#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
2216/*! OPAC8
2217 * 0bxxx0..Accesses from an untrusted master are allowed.
2218 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2219 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2220 * 0bxx0x..This peripheral allows write accesses.
2221 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2222 * error response and no peripheral access is initiated on the IPS bus.
2223 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2224 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2225 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2226 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2227 * on the IPS bus.
2228 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2229 */
2230#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
2231/*! @} */
2232
2233/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
2234/*! @{ */
2235#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
2236#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
2237/*! OPAC23
2238 * 0bxxx0..Accesses from an untrusted master are allowed.
2239 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2240 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2241 * 0bxx0x..This peripheral allows write accesses.
2242 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2243 * error response and no peripheral access is initiated on the IPS bus.
2244 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2245 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2246 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2247 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2248 * on the IPS bus.
2249 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2250 */
2251#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
2252#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
2253#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
2254/*! OPAC22
2255 * 0bxxx0..Accesses from an untrusted master are allowed.
2256 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2257 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2258 * 0bxx0x..This peripheral allows write accesses.
2259 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2260 * error response and no peripheral access is initiated on the IPS bus.
2261 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2262 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2263 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2264 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2265 * on the IPS bus.
2266 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2267 */
2268#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
2269#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
2270#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
2271/*! OPAC21
2272 * 0bxxx0..Accesses from an untrusted master are allowed.
2273 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2274 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2275 * 0bxx0x..This peripheral allows write accesses.
2276 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2277 * error response and no peripheral access is initiated on the IPS bus.
2278 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2279 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2280 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2281 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2282 * on the IPS bus.
2283 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2284 */
2285#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
2286#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
2287#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
2288/*! OPAC20
2289 * 0bxxx0..Accesses from an untrusted master are allowed.
2290 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2291 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2292 * 0bxx0x..This peripheral allows write accesses.
2293 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2294 * error response and no peripheral access is initiated on the IPS bus.
2295 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2296 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2297 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2298 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2299 * on the IPS bus.
2300 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2301 */
2302#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
2303#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
2304#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
2305/*! OPAC19
2306 * 0bxxx0..Accesses from an untrusted master are allowed.
2307 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2308 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2309 * 0bxx0x..This peripheral allows write accesses.
2310 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2311 * error response and no peripheral access is initiated on the IPS bus.
2312 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2313 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2314 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2315 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2316 * on the IPS bus.
2317 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2318 */
2319#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
2320#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
2321#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
2322/*! OPAC18
2323 * 0bxxx0..Accesses from an untrusted master are allowed.
2324 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2325 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2326 * 0bxx0x..This peripheral allows write accesses.
2327 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2328 * error response and no peripheral access is initiated on the IPS bus.
2329 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2330 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2331 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2332 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2333 * on the IPS bus.
2334 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2335 */
2336#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
2337#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
2338#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
2339/*! OPAC17
2340 * 0bxxx0..Accesses from an untrusted master are allowed.
2341 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2342 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2343 * 0bxx0x..This peripheral allows write accesses.
2344 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2345 * error response and no peripheral access is initiated on the IPS bus.
2346 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2347 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2348 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2349 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2350 * on the IPS bus.
2351 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2352 */
2353#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
2354#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
2355#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
2356/*! OPAC16
2357 * 0bxxx0..Accesses from an untrusted master are allowed.
2358 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2359 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2360 * 0bxx0x..This peripheral allows write accesses.
2361 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2362 * error response and no peripheral access is initiated on the IPS bus.
2363 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2364 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2365 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2366 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2367 * on the IPS bus.
2368 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2369 */
2370#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
2371/*! @} */
2372
2373/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
2374/*! @{ */
2375#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
2376#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
2377/*! OPAC31
2378 * 0bxxx0..Accesses from an untrusted master are allowed.
2379 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2380 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2381 * 0bxx0x..This peripheral allows write accesses.
2382 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2383 * error response and no peripheral access is initiated on the IPS bus.
2384 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2385 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2386 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2387 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2388 * on the IPS bus.
2389 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2390 */
2391#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
2392#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
2393#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
2394/*! OPAC30
2395 * 0bxxx0..Accesses from an untrusted master are allowed.
2396 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2397 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2398 * 0bxx0x..This peripheral allows write accesses.
2399 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2400 * error response and no peripheral access is initiated on the IPS bus.
2401 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2402 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2403 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2404 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2405 * on the IPS bus.
2406 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2407 */
2408#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
2409#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
2410#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
2411/*! OPAC29
2412 * 0bxxx0..Accesses from an untrusted master are allowed.
2413 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2414 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2415 * 0bxx0x..This peripheral allows write accesses.
2416 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2417 * error response and no peripheral access is initiated on the IPS bus.
2418 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2419 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2420 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2421 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2422 * on the IPS bus.
2423 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2424 */
2425#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
2426#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
2427#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
2428/*! OPAC28
2429 * 0bxxx0..Accesses from an untrusted master are allowed.
2430 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2431 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2432 * 0bxx0x..This peripheral allows write accesses.
2433 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2434 * error response and no peripheral access is initiated on the IPS bus.
2435 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2436 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2437 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2438 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2439 * on the IPS bus.
2440 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2441 */
2442#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
2443#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
2444#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
2445/*! OPAC27
2446 * 0bxxx0..Accesses from an untrusted master are allowed.
2447 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2448 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2449 * 0bxx0x..This peripheral allows write accesses.
2450 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2451 * error response and no peripheral access is initiated on the IPS bus.
2452 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2453 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2454 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2455 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2456 * on the IPS bus.
2457 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2458 */
2459#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
2460#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
2461#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
2462/*! OPAC26
2463 * 0bxxx0..Accesses from an untrusted master are allowed.
2464 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2465 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2466 * 0bxx0x..This peripheral allows write accesses.
2467 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2468 * error response and no peripheral access is initiated on the IPS bus.
2469 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2470 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2471 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2472 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2473 * on the IPS bus.
2474 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2475 */
2476#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
2477#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
2478#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
2479/*! OPAC25
2480 * 0bxxx0..Accesses from an untrusted master are allowed.
2481 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2482 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2483 * 0bxx0x..This peripheral allows write accesses.
2484 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2485 * error response and no peripheral access is initiated on the IPS bus.
2486 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2487 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2488 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2489 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2490 * on the IPS bus.
2491 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2492 */
2493#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
2494#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
2495#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
2496/*! OPAC24
2497 * 0bxxx0..Accesses from an untrusted master are allowed.
2498 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2499 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2500 * 0bxx0x..This peripheral allows write accesses.
2501 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2502 * error response and no peripheral access is initiated on the IPS bus.
2503 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2504 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2505 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2506 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2507 * on the IPS bus.
2508 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2509 */
2510#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
2511/*! @} */
2512
2513/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
2514/*! @{ */
2515#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
2516#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
2517/*! OPAC33
2518 * 0bxxx0..Accesses from an untrusted master are allowed.
2519 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2520 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2521 * 0bxx0x..This peripheral allows write accesses.
2522 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2523 * error response and no peripheral access is initiated on the IPS bus.
2524 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2525 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2526 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2527 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2528 * on the IPS bus.
2529 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2530 */
2531#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
2532#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
2533#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
2534/*! OPAC32
2535 * 0bxxx0..Accesses from an untrusted master are allowed.
2536 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2537 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2538 * 0bxx0x..This peripheral allows write accesses.
2539 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2540 * error response and no peripheral access is initiated on the IPS bus.
2541 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2542 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2543 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2544 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2545 * on the IPS bus.
2546 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2547 */
2548#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
2549/*! @} */
2550
2551
2552/*!
2553 * @}
2554 */ /* end of group AIPSTZ_Register_Masks */
2555
2556
2557/* AIPSTZ - Peripheral instance base addresses */
2558/** Peripheral AIPSTZ1 base address */
2559#define AIPSTZ1_BASE (0x4007C000u)
2560/** Peripheral AIPSTZ1 base pointer */
2561#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
2562/** Peripheral AIPSTZ2 base address */
2563#define AIPSTZ2_BASE (0x4017C000u)
2564/** Peripheral AIPSTZ2 base pointer */
2565#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
2566/** Peripheral AIPSTZ3 base address */
2567#define AIPSTZ3_BASE (0x4027C000u)
2568/** Peripheral AIPSTZ3 base pointer */
2569#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
2570/** Peripheral AIPSTZ4 base address */
2571#define AIPSTZ4_BASE (0x4037C000u)
2572/** Peripheral AIPSTZ4 base pointer */
2573#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
2574/** Array initializer of AIPSTZ peripheral base addresses */
2575#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
2576/** Array initializer of AIPSTZ peripheral base pointers */
2577#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
2578
2579/*!
2580 * @}
2581 */ /* end of group AIPSTZ_Peripheral_Access_Layer */
2582
2583
2584/* ----------------------------------------------------------------------------
2585 -- AOI Peripheral Access Layer
2586 ---------------------------------------------------------------------------- */
2587
2588/*!
2589 * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
2590 * @{
2591 */
2592
2593/** AOI - Register Layout Typedef */
2594typedef struct {
2595 struct { /* offset: 0x0, array step: 0x4 */
2596 __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
2597 __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
2598 } BFCRT[4];
2599} AOI_Type;
2600
2601/* ----------------------------------------------------------------------------
2602 -- AOI Register Masks
2603 ---------------------------------------------------------------------------- */
2604
2605/*!
2606 * @addtogroup AOI_Register_Masks AOI Register Masks
2607 * @{
2608 */
2609
2610/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
2611/*! @{ */
2612#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
2613#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
2614/*! PT1_DC - Product term 1, D input configuration
2615 * 0b00..Force the D input in this product term to a logical zero
2616 * 0b01..Pass the D input in this product term
2617 * 0b10..Complement the D input in this product term
2618 * 0b11..Force the D input in this product term to a logical one
2619 */
2620#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
2621#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
2622#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
2623/*! PT1_CC - Product term 1, C input configuration
2624 * 0b00..Force the C input in this product term to a logical zero
2625 * 0b01..Pass the C input in this product term
2626 * 0b10..Complement the C input in this product term
2627 * 0b11..Force the C input in this product term to a logical one
2628 */
2629#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
2630#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
2631#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
2632/*! PT1_BC - Product term 1, B input configuration
2633 * 0b00..Force the B input in this product term to a logical zero
2634 * 0b01..Pass the B input in this product term
2635 * 0b10..Complement the B input in this product term
2636 * 0b11..Force the B input in this product term to a logical one
2637 */
2638#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
2639#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
2640#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
2641/*! PT1_AC - Product term 1, A input configuration
2642 * 0b00..Force the A input in this product term to a logical zero
2643 * 0b01..Pass the A input in this product term
2644 * 0b10..Complement the A input in this product term
2645 * 0b11..Force the A input in this product term to a logical one
2646 */
2647#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
2648#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
2649#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
2650/*! PT0_DC - Product term 0, D input configuration
2651 * 0b00..Force the D input in this product term to a logical zero
2652 * 0b01..Pass the D input in this product term
2653 * 0b10..Complement the D input in this product term
2654 * 0b11..Force the D input in this product term to a logical one
2655 */
2656#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
2657#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
2658#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
2659/*! PT0_CC - Product term 0, C input configuration
2660 * 0b00..Force the C input in this product term to a logical zero
2661 * 0b01..Pass the C input in this product term
2662 * 0b10..Complement the C input in this product term
2663 * 0b11..Force the C input in this product term to a logical one
2664 */
2665#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
2666#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
2667#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
2668/*! PT0_BC - Product term 0, B input configuration
2669 * 0b00..Force the B input in this product term to a logical zero
2670 * 0b01..Pass the B input in this product term
2671 * 0b10..Complement the B input in this product term
2672 * 0b11..Force the B input in this product term to a logical one
2673 */
2674#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
2675#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
2676#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
2677/*! PT0_AC - Product term 0, A input configuration
2678 * 0b00..Force the A input in this product term to a logical zero
2679 * 0b01..Pass the A input in this product term
2680 * 0b10..Complement the A input in this product term
2681 * 0b11..Force the A input in this product term to a logical one
2682 */
2683#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
2684/*! @} */
2685
2686/* The count of AOI_BFCRT01 */
2687#define AOI_BFCRT01_COUNT (4U)
2688
2689/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
2690/*! @{ */
2691#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
2692#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
2693/*! PT3_DC - Product term 3, D input configuration
2694 * 0b00..Force the D input in this product term to a logical zero
2695 * 0b01..Pass the D input in this product term
2696 * 0b10..Complement the D input in this product term
2697 * 0b11..Force the D input in this product term to a logical one
2698 */
2699#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
2700#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
2701#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
2702/*! PT3_CC - Product term 3, C input configuration
2703 * 0b00..Force the C input in this product term to a logical zero
2704 * 0b01..Pass the C input in this product term
2705 * 0b10..Complement the C input in this product term
2706 * 0b11..Force the C input in this product term to a logical one
2707 */
2708#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
2709#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
2710#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
2711/*! PT3_BC - Product term 3, B input configuration
2712 * 0b00..Force the B input in this product term to a logical zero
2713 * 0b01..Pass the B input in this product term
2714 * 0b10..Complement the B input in this product term
2715 * 0b11..Force the B input in this product term to a logical one
2716 */
2717#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
2718#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
2719#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
2720/*! PT3_AC - Product term 3, A input configuration
2721 * 0b00..Force the A input in this product term to a logical zero
2722 * 0b01..Pass the A input in this product term
2723 * 0b10..Complement the A input in this product term
2724 * 0b11..Force the A input in this product term to a logical one
2725 */
2726#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
2727#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
2728#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
2729/*! PT2_DC - Product term 2, D input configuration
2730 * 0b00..Force the D input in this product term to a logical zero
2731 * 0b01..Pass the D input in this product term
2732 * 0b10..Complement the D input in this product term
2733 * 0b11..Force the D input in this product term to a logical one
2734 */
2735#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
2736#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
2737#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
2738/*! PT2_CC - Product term 2, C input configuration
2739 * 0b00..Force the C input in this product term to a logical zero
2740 * 0b01..Pass the C input in this product term
2741 * 0b10..Complement the C input in this product term
2742 * 0b11..Force the C input in this product term to a logical one
2743 */
2744#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
2745#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
2746#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
2747/*! PT2_BC - Product term 2, B input configuration
2748 * 0b00..Force the B input in this product term to a logical zero
2749 * 0b01..Pass the B input in this product term
2750 * 0b10..Complement the B input in this product term
2751 * 0b11..Force the B input in this product term to a logical one
2752 */
2753#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
2754#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
2755#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
2756/*! PT2_AC - Product term 2, A input configuration
2757 * 0b00..Force the A input in this product term to a logical zero
2758 * 0b01..Pass the A input in this product term
2759 * 0b10..Complement the A input in this product term
2760 * 0b11..Force the A input in this product term to a logical one
2761 */
2762#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
2763/*! @} */
2764
2765/* The count of AOI_BFCRT23 */
2766#define AOI_BFCRT23_COUNT (4U)
2767
2768
2769/*!
2770 * @}
2771 */ /* end of group AOI_Register_Masks */
2772
2773
2774/* AOI - Peripheral instance base addresses */
2775/** Peripheral AOI base address */
2776#define AOI_BASE (0x403B4000u)
2777/** Peripheral AOI base pointer */
2778#define AOI ((AOI_Type *)AOI_BASE)
2779/** Array initializer of AOI peripheral base addresses */
2780#define AOI_BASE_ADDRS { AOI_BASE }
2781/** Array initializer of AOI peripheral base pointers */
2782#define AOI_BASE_PTRS { AOI }
2783
2784/*!
2785 * @}
2786 */ /* end of group AOI_Peripheral_Access_Layer */
2787
2788
2789/* ----------------------------------------------------------------------------
2790 -- BEE Peripheral Access Layer
2791 ---------------------------------------------------------------------------- */
2792
2793/*!
2794 * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer
2795 * @{
2796 */
2797
2798/** BEE - Register Layout Typedef */
2799typedef struct {
2800 __IO uint32_t CTRL; /**< Control Register, offset: 0x0 */
2801 __IO uint32_t ADDR_OFFSET0; /**< Offset region 0 Register, offset: 0x4 */
2802 __IO uint32_t ADDR_OFFSET1; /**< Offset region 1 Register, offset: 0x8 */
2803 __O uint32_t AES_KEY0_W0; /**< AES Key 0 Register, offset: 0xC */
2804 __O uint32_t AES_KEY0_W1; /**< AES Key 1 Register, offset: 0x10 */
2805 __O uint32_t AES_KEY0_W2; /**< AES Key 2 Register, offset: 0x14 */
2806 __O uint32_t AES_KEY0_W3; /**< AES Key 3 Register, offset: 0x18 */
2807 __IO uint32_t STATUS; /**< Status Register, offset: 0x1C */
2808 __O uint32_t CTR_NONCE0_W0; /**< NONCE00 Register, offset: 0x20 */
2809 __O uint32_t CTR_NONCE0_W1; /**< NONCE01 Register, offset: 0x24 */
2810 __O uint32_t CTR_NONCE0_W2; /**< NONCE02 Register, offset: 0x28 */
2811 __O uint32_t CTR_NONCE0_W3; /**< NONCE03 Register, offset: 0x2C */
2812 __O uint32_t CTR_NONCE1_W0; /**< NONCE10 Register, offset: 0x30 */
2813 __O uint32_t CTR_NONCE1_W1; /**< NONCE11 Register, offset: 0x34 */
2814 __O uint32_t CTR_NONCE1_W2; /**< NONCE12 Register, offset: 0x38 */
2815 __O uint32_t CTR_NONCE1_W3; /**< NONCE13 Register, offset: 0x3C */
2816 __IO uint32_t REGION1_TOP; /**< Region1 Top Address Register, offset: 0x40 */
2817 __IO uint32_t REGION1_BOT; /**< Region1 Bottom Address Register, offset: 0x44 */
2818} BEE_Type;
2819
2820/* ----------------------------------------------------------------------------
2821 -- BEE Register Masks
2822 ---------------------------------------------------------------------------- */
2823
2824/*!
2825 * @addtogroup BEE_Register_Masks BEE Register Masks
2826 * @{
2827 */
2828
2829/*! @name CTRL - Control Register */
2830/*! @{ */
2831#define BEE_CTRL_BEE_ENABLE_MASK (0x1U)
2832#define BEE_CTRL_BEE_ENABLE_SHIFT (0U)
2833/*! BEE_ENABLE
2834 * 0b0..Disable BEE
2835 * 0b1..Enable BEE
2836 */
2837#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
2838#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
2839#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
2840#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
2841#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
2842#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
2843#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
2844#define BEE_CTRL_KEY_VALID_MASK (0x10U)
2845#define BEE_CTRL_KEY_VALID_SHIFT (4U)
2846#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
2847#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
2848#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
2849/*! KEY_REGION_SEL
2850 * 0b0..Load AES key for region0
2851 * 0b1..Load AES key for region1
2852 */
2853#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
2854#define BEE_CTRL_AC_PROT_EN_MASK (0x40U)
2855#define BEE_CTRL_AC_PROT_EN_SHIFT (6U)
2856#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
2857#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
2858#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
2859/*! LITTLE_ENDIAN
2860 * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8,
2861 * B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to
2862 * Byte0 to Byte15.
2863 * 0b1..The input and output data of AES core is not swapped.
2864 */
2865#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
2866#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
2867#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
2868#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
2869#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
2870#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
2871/*! CTRL_AES_MODE_R0
2872 * 0b0..ECB
2873 * 0b1..CTR
2874 */
2875#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
2876#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
2877#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
2878#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
2879#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
2880#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
2881/*! CTRL_AES_MODE_R1
2882 * 0b0..ECB
2883 * 0b1..CTR
2884 */
2885#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
2886#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
2887#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
2888#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
2889#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
2890#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
2891#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
2892#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
2893#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
2894#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
2895#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
2896#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
2897#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
2898#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
2899#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
2900#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
2901#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
2902#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
2903#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
2904#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
2905#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
2906#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
2907#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
2908#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
2909#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
2910#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
2911#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
2912#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
2913#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
2914#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
2915#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
2916#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
2917#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
2918#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
2919#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
2920#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
2921#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
2922#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
2923#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
2924#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
2925#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
2926#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
2927#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
2928/*! @} */
2929
2930/*! @name ADDR_OFFSET0 - Offset region 0 Register */
2931/*! @{ */
2932#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
2933#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
2934#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
2935#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
2936#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
2937#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
2938/*! @} */
2939
2940/*! @name ADDR_OFFSET1 - Offset region 1 Register */
2941/*! @{ */
2942#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)
2943#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)
2944#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
2945#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)
2946#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
2947#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
2948/*! @} */
2949
2950/*! @name AES_KEY0_W0 - AES Key 0 Register */
2951/*! @{ */
2952#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
2953#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
2954/*! KEY0 - AES 128 key from software
2955 */
2956#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
2957/*! @} */
2958
2959/*! @name AES_KEY0_W1 - AES Key 1 Register */
2960/*! @{ */
2961#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
2962#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
2963/*! KEY1 - AES 128 key from software
2964 */
2965#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
2966/*! @} */
2967
2968/*! @name AES_KEY0_W2 - AES Key 2 Register */
2969/*! @{ */
2970#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
2971#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
2972/*! KEY2 - AES 128 key from software
2973 */
2974#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
2975/*! @} */
2976
2977/*! @name AES_KEY0_W3 - AES Key 3 Register */
2978/*! @{ */
2979#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
2980#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
2981/*! KEY3 - AES 128 key from software
2982 */
2983#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
2984/*! @} */
2985
2986/*! @name STATUS - Status Register */
2987/*! @{ */
2988#define BEE_STATUS_IRQ_VEC_MASK (0xFFU)
2989#define BEE_STATUS_IRQ_VEC_SHIFT (0U)
2990#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
2991#define BEE_STATUS_BEE_IDLE_MASK (0x100U)
2992#define BEE_STATUS_BEE_IDLE_SHIFT (8U)
2993#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
2994/*! @} */
2995
2996/*! @name CTR_NONCE0_W0 - NONCE00 Register */
2997/*! @{ */
2998#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
2999#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
3000#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
3001/*! @} */
3002
3003/*! @name CTR_NONCE0_W1 - NONCE01 Register */
3004/*! @{ */
3005#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
3006#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
3007#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
3008/*! @} */
3009
3010/*! @name CTR_NONCE0_W2 - NONCE02 Register */
3011/*! @{ */
3012#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
3013#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
3014#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
3015/*! @} */
3016
3017/*! @name CTR_NONCE0_W3 - NONCE03 Register */
3018/*! @{ */
3019#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
3020#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
3021#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
3022/*! @} */
3023
3024/*! @name CTR_NONCE1_W0 - NONCE10 Register */
3025/*! @{ */
3026#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
3027#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
3028#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
3029/*! @} */
3030
3031/*! @name CTR_NONCE1_W1 - NONCE11 Register */
3032/*! @{ */
3033#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
3034#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
3035#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
3036/*! @} */
3037
3038/*! @name CTR_NONCE1_W2 - NONCE12 Register */
3039/*! @{ */
3040#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
3041#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
3042#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
3043/*! @} */
3044
3045/*! @name CTR_NONCE1_W3 - NONCE13 Register */
3046/*! @{ */
3047#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
3048#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
3049#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
3050/*! @} */
3051
3052/*! @name REGION1_TOP - Region1 Top Address Register */
3053/*! @{ */
3054#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
3055#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
3056/*! REGION1_TOP - Address upper limit of region1
3057 */
3058#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
3059/*! @} */
3060
3061/*! @name REGION1_BOT - Region1 Bottom Address Register */
3062/*! @{ */
3063#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
3064#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
3065/*! REGION1_BOT - Address lower limit of region1
3066 */
3067#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)
3068/*! @} */
3069
3070
3071/*!
3072 * @}
3073 */ /* end of group BEE_Register_Masks */
3074
3075
3076/* BEE - Peripheral instance base addresses */
3077/** Peripheral BEE base address */
3078#define BEE_BASE (0x403EC000u)
3079/** Peripheral BEE base pointer */
3080#define BEE ((BEE_Type *)BEE_BASE)
3081/** Array initializer of BEE peripheral base addresses */
3082#define BEE_BASE_ADDRS { BEE_BASE }
3083/** Array initializer of BEE peripheral base pointers */
3084#define BEE_BASE_PTRS { BEE }
3085
3086/*!
3087 * @}
3088 */ /* end of group BEE_Peripheral_Access_Layer */
3089
3090
3091/* ----------------------------------------------------------------------------
3092 -- CAN Peripheral Access Layer
3093 ---------------------------------------------------------------------------- */
3094
3095/*!
3096 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
3097 * @{
3098 */
3099
3100/** CAN - Register Layout Typedef */
3101typedef struct {
3102 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
3103 __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */
3104 __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */
3105 uint8_t RESERVED_0[4];
3106 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
3107 __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */
3108 __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */
3109 __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */
3110 __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */
3111 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */
3112 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */
3113 __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */
3114 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */
3115 __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */
3116 __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */
3117 uint8_t RESERVED_1[8];
3118 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
3119 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */
3120 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
3121 uint8_t RESERVED_2[8];
3122 __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */
3123 __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */
3124 uint8_t RESERVED_3[32];
3125 struct { /* offset: 0x80, array step: 0x10 */
3126 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
3127 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
3128 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
3129 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
3130 } MB[64];
3131 uint8_t RESERVED_4[1024];
3132 __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
3133 uint8_t RESERVED_5[96];
3134 __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */
3135} CAN_Type;
3136
3137/* ----------------------------------------------------------------------------
3138 -- CAN Register Masks
3139 ---------------------------------------------------------------------------- */
3140
3141/*!
3142 * @addtogroup CAN_Register_Masks CAN Register Masks
3143 * @{
3144 */
3145
3146/*! @name MCR - Module Configuration Register */
3147/*! @{ */
3148#define CAN_MCR_MAXMB_MASK (0x7FU)
3149#define CAN_MCR_MAXMB_SHIFT (0U)
3150#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
3151#define CAN_MCR_IDAM_MASK (0x300U)
3152#define CAN_MCR_IDAM_SHIFT (8U)
3153/*! IDAM
3154 * 0b00..Format A One full ID (standard or extended) per ID filter Table element.
3155 * 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element.
3156 * 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element.
3157 * 0b11..Format D All frames rejected.
3158 */
3159#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
3160#define CAN_MCR_AEN_MASK (0x1000U)
3161#define CAN_MCR_AEN_SHIFT (12U)
3162/*! AEN
3163 * 0b1..Abort enabled
3164 * 0b0..Abort disabled
3165 */
3166#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
3167#define CAN_MCR_LPRIOEN_MASK (0x2000U)
3168#define CAN_MCR_LPRIOEN_SHIFT (13U)
3169/*! LPRIOEN
3170 * 0b1..Local Priority enabled
3171 * 0b0..Local Priority disabled
3172 */
3173#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
3174#define CAN_MCR_IRMQ_MASK (0x10000U)
3175#define CAN_MCR_IRMQ_SHIFT (16U)
3176/*! IRMQ
3177 * 0b1..Individual Rx masking and queue feature are enabled.
3178 * 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY.
3179 */
3180#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
3181#define CAN_MCR_SRXDIS_MASK (0x20000U)
3182#define CAN_MCR_SRXDIS_SHIFT (17U)
3183/*! SRXDIS
3184 * 0b1..Self reception disabled
3185 * 0b0..Self reception enabled
3186 */
3187#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
3188#define CAN_MCR_WAKSRC_MASK (0x80000U)
3189#define CAN_MCR_WAKSRC_SHIFT (19U)
3190/*! WAKSRC
3191 * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus
3192 * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus.
3193 */
3194#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
3195#define CAN_MCR_LPMACK_MASK (0x100000U)
3196#define CAN_MCR_LPMACK_SHIFT (20U)
3197/*! LPMACK
3198 * 0b1..FLEXCAN is either in Disable Mode, or Stop mode
3199 * 0b0..FLEXCAN not in any of the low power modes
3200 */
3201#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
3202#define CAN_MCR_WRNEN_MASK (0x200000U)
3203#define CAN_MCR_WRNEN_SHIFT (21U)
3204/*! WRNEN
3205 * 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96.
3206 * 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.
3207 */
3208#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
3209#define CAN_MCR_SLFWAK_MASK (0x400000U)
3210#define CAN_MCR_SLFWAK_SHIFT (22U)
3211/*! SLFWAK
3212 * 0b1..FLEXCAN Self Wake Up feature is enabled
3213 * 0b0..FLEXCAN Self Wake Up feature is disabled
3214 */
3215#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
3216#define CAN_MCR_SUPV_MASK (0x800000U)
3217#define CAN_MCR_SUPV_SHIFT (23U)
3218/*! SUPV
3219 * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access
3220 * behaves as though the access was done to an unimplemented register location
3221 * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses
3222 */
3223#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
3224#define CAN_MCR_FRZACK_MASK (0x1000000U)
3225#define CAN_MCR_FRZACK_SHIFT (24U)
3226/*! FRZACK
3227 * 0b1..FLEXCAN in Freeze Mode, prescaler stopped
3228 * 0b0..FLEXCAN not in Freeze Mode, prescaler running
3229 */
3230#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
3231#define CAN_MCR_SOFTRST_MASK (0x2000000U)
3232#define CAN_MCR_SOFTRST_SHIFT (25U)
3233/*! SOFTRST
3234 * 0b1..Reset the registers
3235 * 0b0..No reset request
3236 */
3237#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
3238#define CAN_MCR_WAKMSK_MASK (0x4000000U)
3239#define CAN_MCR_WAKMSK_SHIFT (26U)
3240/*! WAKMSK
3241 * 0b1..Wake Up Interrupt is enabled
3242 * 0b0..Wake Up Interrupt is disabled
3243 */
3244#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
3245#define CAN_MCR_NOTRDY_MASK (0x8000000U)
3246#define CAN_MCR_NOTRDY_SHIFT (27U)
3247/*! NOTRDY
3248 * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode
3249 * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode
3250 */
3251#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
3252#define CAN_MCR_HALT_MASK (0x10000000U)
3253#define CAN_MCR_HALT_SHIFT (28U)
3254/*! HALT
3255 * 0b1..Enters Freeze Mode if the FRZ bit is asserted.
3256 * 0b0..No Freeze Mode request.
3257 */
3258#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
3259#define CAN_MCR_RFEN_MASK (0x20000000U)
3260#define CAN_MCR_RFEN_SHIFT (29U)
3261/*! RFEN
3262 * 0b1..FIFO enabled
3263 * 0b0..FIFO not enabled
3264 */
3265#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
3266#define CAN_MCR_FRZ_MASK (0x40000000U)
3267#define CAN_MCR_FRZ_SHIFT (30U)
3268/*! FRZ
3269 * 0b1..Enabled to enter Freeze Mode
3270 * 0b0..Not enabled to enter Freeze Mode
3271 */
3272#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
3273#define CAN_MCR_MDIS_MASK (0x80000000U)
3274#define CAN_MCR_MDIS_SHIFT (31U)
3275/*! MDIS
3276 * 0b1..Disable the FLEXCAN module
3277 * 0b0..Enable the FLEXCAN module
3278 */
3279#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
3280/*! @} */
3281
3282/*! @name CTRL1 - Control 1 Register */
3283/*! @{ */
3284#define CAN_CTRL1_PROPSEG_MASK (0x7U)
3285#define CAN_CTRL1_PROPSEG_SHIFT (0U)
3286#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
3287#define CAN_CTRL1_LOM_MASK (0x8U)
3288#define CAN_CTRL1_LOM_SHIFT (3U)
3289/*! LOM
3290 * 0b1..FLEXCAN module operates in Listen Only Mode
3291 * 0b0..Listen Only Mode is deactivated
3292 */
3293#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
3294#define CAN_CTRL1_LBUF_MASK (0x10U)
3295#define CAN_CTRL1_LBUF_SHIFT (4U)
3296/*! LBUF
3297 * 0b1..Lowest number buffer is transmitted first
3298 * 0b0..Buffer with highest priority is transmitted first
3299 */
3300#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
3301#define CAN_CTRL1_TSYN_MASK (0x20U)
3302#define CAN_CTRL1_TSYN_SHIFT (5U)
3303/*! TSYN
3304 * 0b1..Timer Sync feature enabled
3305 * 0b0..Timer Sync feature disabled
3306 */
3307#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
3308#define CAN_CTRL1_BOFFREC_MASK (0x40U)
3309#define CAN_CTRL1_BOFFREC_SHIFT (6U)
3310/*! BOFFREC
3311 * 0b1..Automatic recovering from Bus Off state disabled
3312 * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
3313 */
3314#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
3315#define CAN_CTRL1_SMP_MASK (0x80U)
3316#define CAN_CTRL1_SMP_SHIFT (7U)
3317/*! SMP
3318 * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2
3319 * preceding samples, a majority rule is used
3320 * 0b0..Just one sample is used to determine the bit value
3321 */
3322#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
3323#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
3324#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
3325/*! RWRNMSK
3326 * 0b1..Rx Warning Interrupt enabled
3327 * 0b0..Rx Warning Interrupt disabled
3328 */
3329#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
3330#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
3331#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
3332/*! TWRNMSK
3333 * 0b1..Tx Warning Interrupt enabled
3334 * 0b0..Tx Warning Interrupt disabled
3335 */
3336#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
3337#define CAN_CTRL1_LPB_MASK (0x1000U)
3338#define CAN_CTRL1_LPB_SHIFT (12U)
3339/*! LPB
3340 * 0b1..Loop Back enabled
3341 * 0b0..Loop Back disabled
3342 */
3343#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
3344#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
3345#define CAN_CTRL1_ERRMSK_SHIFT (14U)
3346/*! ERRMSK
3347 * 0b1..Error interrupt enabled
3348 * 0b0..Error interrupt disabled
3349 */
3350#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
3351#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
3352#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
3353/*! BOFFMSK
3354 * 0b1..Bus Off interrupt enabled
3355 * 0b0..Bus Off interrupt disabled
3356 */
3357#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
3358#define CAN_CTRL1_PSEG2_MASK (0x70000U)
3359#define CAN_CTRL1_PSEG2_SHIFT (16U)
3360#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
3361#define CAN_CTRL1_PSEG1_MASK (0x380000U)
3362#define CAN_CTRL1_PSEG1_SHIFT (19U)
3363#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
3364#define CAN_CTRL1_RJW_MASK (0xC00000U)
3365#define CAN_CTRL1_RJW_SHIFT (22U)
3366#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
3367#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
3368#define CAN_CTRL1_PRESDIV_SHIFT (24U)
3369#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
3370/*! @} */
3371
3372/*! @name TIMER - Free Running Timer Register */
3373/*! @{ */
3374#define CAN_TIMER_TIMER_MASK (0xFFFFU)
3375#define CAN_TIMER_TIMER_SHIFT (0U)
3376#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
3377/*! @} */
3378
3379/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
3380/*! @{ */
3381#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
3382#define CAN_RXMGMASK_MG_SHIFT (0U)
3383/*! MG
3384 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received
3385 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
3386 */
3387#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
3388/*! @} */
3389
3390/*! @name RX14MASK - Rx Buffer 14 Mask Register */
3391/*! @{ */
3392#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
3393#define CAN_RX14MASK_RX14M_SHIFT (0U)
3394/*! RX14M
3395 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
3396 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
3397 */
3398#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
3399/*! @} */
3400
3401/*! @name RX15MASK - Rx Buffer 15 Mask Register */
3402/*! @{ */
3403#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
3404#define CAN_RX15MASK_RX15M_SHIFT (0U)
3405/*! RX15M
3406 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
3407 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
3408 */
3409#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
3410/*! @} */
3411
3412/*! @name ECR - Error Counter Register */
3413/*! @{ */
3414#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)
3415#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)
3416#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
3417#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)
3418#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)
3419#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
3420/*! @} */
3421
3422/*! @name ESR1 - Error and Status 1 Register */
3423/*! @{ */
3424#define CAN_ESR1_WAKINT_MASK (0x1U)
3425#define CAN_ESR1_WAKINT_SHIFT (0U)
3426/*! WAKINT
3427 * 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode
3428 * 0b0..No such occurrence
3429 */
3430#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
3431#define CAN_ESR1_ERRINT_MASK (0x2U)
3432#define CAN_ESR1_ERRINT_SHIFT (1U)
3433/*! ERRINT
3434 * 0b1..Indicates setting of any Error Bit in the Error and Status Register
3435 * 0b0..No such occurrence
3436 */
3437#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
3438#define CAN_ESR1_BOFFINT_MASK (0x4U)
3439#define CAN_ESR1_BOFFINT_SHIFT (2U)
3440/*! BOFFINT
3441 * 0b1..FLEXCAN module entered 'Bus Off' state
3442 * 0b0..No such occurrence
3443 */
3444#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
3445#define CAN_ESR1_RX_MASK (0x8U)
3446#define CAN_ESR1_RX_SHIFT (3U)
3447/*! RX
3448 * 0b1..FLEXCAN is transmitting a message
3449 * 0b0..FLEXCAN is receiving a message
3450 */
3451#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
3452#define CAN_ESR1_FLTCONF_MASK (0x30U)
3453#define CAN_ESR1_FLTCONF_SHIFT (4U)
3454/*! FLTCONF
3455 * 0b00..Error Active
3456 * 0b01..Error Passive
3457 * 0b1x..Bus off
3458 */
3459#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
3460#define CAN_ESR1_TX_MASK (0x40U)
3461#define CAN_ESR1_TX_SHIFT (6U)
3462/*! TX
3463 * 0b1..FLEXCAN is transmitting a message
3464 * 0b0..FLEXCAN is receiving a message
3465 */
3466#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
3467#define CAN_ESR1_IDLE_MASK (0x80U)
3468#define CAN_ESR1_IDLE_SHIFT (7U)
3469/*! IDLE
3470 * 0b1..CAN bus is now IDLE
3471 * 0b0..No such occurrence
3472 */
3473#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
3474#define CAN_ESR1_RXWRN_MASK (0x100U)
3475#define CAN_ESR1_RXWRN_SHIFT (8U)
3476/*! RXWRN
3477 * 0b1..Rx_Err_Counter >= 96
3478 * 0b0..No such occurrence
3479 */
3480#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
3481#define CAN_ESR1_TXWRN_MASK (0x200U)
3482#define CAN_ESR1_TXWRN_SHIFT (9U)
3483/*! TXWRN
3484 * 0b1..TX_Err_Counter >= 96
3485 * 0b0..No such occurrence
3486 */
3487#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
3488#define CAN_ESR1_STFERR_MASK (0x400U)
3489#define CAN_ESR1_STFERR_SHIFT (10U)
3490/*! STFERR
3491 * 0b1..A Stuffing Error occurred since last read of this register.
3492 * 0b0..No such occurrence.
3493 */
3494#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
3495#define CAN_ESR1_FRMERR_MASK (0x800U)
3496#define CAN_ESR1_FRMERR_SHIFT (11U)
3497/*! FRMERR
3498 * 0b1..A Form Error occurred since last read of this register
3499 * 0b0..No such occurrence
3500 */
3501#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
3502#define CAN_ESR1_CRCERR_MASK (0x1000U)
3503#define CAN_ESR1_CRCERR_SHIFT (12U)
3504/*! CRCERR
3505 * 0b1..A CRC error occurred since last read of this register.
3506 * 0b0..No such occurrence
3507 */
3508#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
3509#define CAN_ESR1_ACKERR_MASK (0x2000U)
3510#define CAN_ESR1_ACKERR_SHIFT (13U)
3511/*! ACKERR
3512 * 0b1..An ACK error occurred since last read of this register
3513 * 0b0..No such occurrence
3514 */
3515#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
3516#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
3517#define CAN_ESR1_BIT0ERR_SHIFT (14U)
3518/*! BIT0ERR
3519 * 0b1..At least one bit sent as dominant is received as recessive
3520 * 0b0..No such occurrence
3521 */
3522#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
3523#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
3524#define CAN_ESR1_BIT1ERR_SHIFT (15U)
3525/*! BIT1ERR
3526 * 0b1..At least one bit sent as recessive is received as dominant
3527 * 0b0..No such occurrence
3528 */
3529#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
3530#define CAN_ESR1_RWRNINT_MASK (0x10000U)
3531#define CAN_ESR1_RWRNINT_SHIFT (16U)
3532/*! RWRNINT
3533 * 0b1..The Rx error counter transition from < 96 to >= 96
3534 * 0b0..No such occurrence
3535 */
3536#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
3537#define CAN_ESR1_TWRNINT_MASK (0x20000U)
3538#define CAN_ESR1_TWRNINT_SHIFT (17U)
3539/*! TWRNINT
3540 * 0b1..The Tx error counter transition from < 96 to >= 96
3541 * 0b0..No such occurrence
3542 */
3543#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
3544#define CAN_ESR1_SYNCH_MASK (0x40000U)
3545#define CAN_ESR1_SYNCH_SHIFT (18U)
3546/*! SYNCH
3547 * 0b1..FlexCAN is synchronized to the CAN bus
3548 * 0b0..FlexCAN is not synchronized to the CAN bus
3549 */
3550#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
3551/*! @} */
3552
3553/*! @name IMASK2 - Interrupt Masks 2 Register */
3554/*! @{ */
3555#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)
3556#define CAN_IMASK2_BUFHM_SHIFT (0U)
3557/*! BUFHM
3558 * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
3559 * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
3560 */
3561#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
3562/*! @} */
3563
3564/*! @name IMASK1 - Interrupt Masks 1 Register */
3565/*! @{ */
3566#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
3567#define CAN_IMASK1_BUFLM_SHIFT (0U)
3568/*! BUFLM
3569 * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
3570 * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
3571 */
3572#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
3573/*! @} */
3574
3575/*! @name IFLAG2 - Interrupt Flags 2 Register */
3576/*! @{ */
3577#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)
3578#define CAN_IFLAG2_BUFHI_SHIFT (0U)
3579/*! BUFHI
3580 * 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception
3581 * 0b00000000000000000000000000000000..No such occurrence
3582 */
3583#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
3584/*! @} */
3585
3586/*! @name IFLAG1 - Interrupt Flags 1 Register */
3587/*! @{ */
3588#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)
3589#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U)
3590/*! BUF4TO0I
3591 * 0b00001..Corresponding MB completed transmission/reception
3592 * 0b00000..No such occurrence
3593 */
3594#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
3595#define CAN_IFLAG1_BUF5I_MASK (0x20U)
3596#define CAN_IFLAG1_BUF5I_SHIFT (5U)
3597/*! BUF5I
3598 * 0b1..MB5 completed transmission/reception or frames available in the FIFO
3599 * 0b0..No such occurrence
3600 */
3601#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
3602#define CAN_IFLAG1_BUF6I_MASK (0x40U)
3603#define CAN_IFLAG1_BUF6I_SHIFT (6U)
3604/*! BUF6I
3605 * 0b1..MB6 completed transmission/reception or FIFO almost full
3606 * 0b0..No such occurrence
3607 */
3608#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
3609#define CAN_IFLAG1_BUF7I_MASK (0x80U)
3610#define CAN_IFLAG1_BUF7I_SHIFT (7U)
3611/*! BUF7I
3612 * 0b1..MB7 completed transmission/reception or FIFO overflow
3613 * 0b0..No such occurrence
3614 */
3615#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
3616#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
3617#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
3618/*! BUF31TO8I
3619 * 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception
3620 * 0b000000000000000000000000..No such occurrence
3621 */
3622#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
3623/*! @} */
3624
3625/*! @name CTRL2 - Control 2 Register */
3626/*! @{ */
3627#define CAN_CTRL2_EACEN_MASK (0x10000U)
3628#define CAN_CTRL2_EACEN_SHIFT (16U)
3629/*! EACEN
3630 * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within
3631 * the incoming frame. Mask bits do apply.
3632 * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
3633 */
3634#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
3635#define CAN_CTRL2_RRS_MASK (0x20000U)
3636#define CAN_CTRL2_RRS_SHIFT (17U)
3637/*! RRS
3638 * 0b1..Remote Request Frame is stored
3639 * 0b0..Remote Response Frame is generated
3640 */
3641#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
3642#define CAN_CTRL2_MRP_MASK (0x40000U)
3643#define CAN_CTRL2_MRP_SHIFT (18U)
3644/*! MRP
3645 * 0b1..Matching starts from Mailboxes and continues on Rx FIFO
3646 * 0b0..Matching starts from Rx FIFO and continues on Mailboxes
3647 */
3648#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
3649#define CAN_CTRL2_TASD_MASK (0xF80000U)
3650#define CAN_CTRL2_TASD_SHIFT (19U)
3651#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
3652#define CAN_CTRL2_RFFN_MASK (0xF000000U)
3653#define CAN_CTRL2_RFFN_SHIFT (24U)
3654#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
3655#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
3656#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
3657/*! WRMFRZ
3658 * 0b1..Enable unrestricted write access to FlexCAN memory
3659 * 0b0..Keep the write access restricted in some regions of FlexCAN memory
3660 */
3661#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
3662/*! @} */
3663
3664/*! @name ESR2 - Error and Status 2 Register */
3665/*! @{ */
3666#define CAN_ESR2_IMB_MASK (0x2000U)
3667#define CAN_ESR2_IMB_SHIFT (13U)
3668/*! IMB
3669 * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.
3670 * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
3671 */
3672#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
3673#define CAN_ESR2_VPS_MASK (0x4000U)
3674#define CAN_ESR2_VPS_SHIFT (14U)
3675/*! VPS
3676 * 0b1..Contents of IMB and LPTM are valid
3677 * 0b0..Contents of IMB and LPTM are invalid
3678 */
3679#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
3680#define CAN_ESR2_LPTM_MASK (0x7F0000U)
3681#define CAN_ESR2_LPTM_SHIFT (16U)
3682#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
3683/*! @} */
3684
3685/*! @name CRCR - CRC Register */
3686/*! @{ */
3687#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
3688#define CAN_CRCR_TXCRC_SHIFT (0U)
3689#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
3690#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
3691#define CAN_CRCR_MBCRC_SHIFT (16U)
3692#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
3693/*! @} */
3694
3695/*! @name RXFGMASK - Rx FIFO Global Mask Register */
3696/*! @{ */
3697#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
3698#define CAN_RXFGMASK_FGM_SHIFT (0U)
3699/*! FGM
3700 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
3701 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care"
3702 */
3703#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
3704/*! @} */
3705
3706/*! @name RXFIR - Rx FIFO Information Register */
3707/*! @{ */
3708#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
3709#define CAN_RXFIR_IDHIT_SHIFT (0U)
3710#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
3711/*! @} */
3712
3713/*! @name DBG1 - Debug 1 register */
3714/*! @{ */
3715#define CAN_DBG1_CFSM_MASK (0x3FU)
3716#define CAN_DBG1_CFSM_SHIFT (0U)
3717/*! CFSM - CAN Finite State Machine
3718 */
3719#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
3720#define CAN_DBG1_CBN_MASK (0x1F000000U)
3721#define CAN_DBG1_CBN_SHIFT (24U)
3722/*! CBN - CAN Bit Number
3723 */
3724#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
3725/*! @} */
3726
3727/*! @name DBG2 - Debug 2 register */
3728/*! @{ */
3729#define CAN_DBG2_RMP_MASK (0x7FU)
3730#define CAN_DBG2_RMP_SHIFT (0U)
3731/*! RMP - Rx Matching Pointer
3732 */
3733#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
3734#define CAN_DBG2_MPP_MASK (0x80U)
3735#define CAN_DBG2_MPP_SHIFT (7U)
3736/*! MPP - Matching Process in Progress
3737 * 0b0..No matching process ongoing.
3738 * 0b1..Matching process is in progress.
3739 */
3740#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
3741#define CAN_DBG2_TAP_MASK (0x7F00U)
3742#define CAN_DBG2_TAP_SHIFT (8U)
3743/*! TAP - Tx Arbitration Pointer
3744 */
3745#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
3746#define CAN_DBG2_APP_MASK (0x8000U)
3747#define CAN_DBG2_APP_SHIFT (15U)
3748/*! APP - Arbitration Process in Progress
3749 * 0b0..No matching process ongoing.
3750 * 0b1..Matching process is in progress.
3751 */
3752#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
3753/*! @} */
3754
3755/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
3756/*! @{ */
3757#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
3758#define CAN_CS_TIME_STAMP_SHIFT (0U)
3759/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
3760 * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
3761 * appears on the CAN bus.
3762 */
3763#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
3764#define CAN_CS_DLC_MASK (0xF0000U)
3765#define CAN_CS_DLC_SHIFT (16U)
3766/*! DLC - Length of the data to be stored/transmitted.
3767 */
3768#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
3769#define CAN_CS_RTR_MASK (0x100000U)
3770#define CAN_CS_RTR_SHIFT (20U)
3771/*! RTR - Remote Transmission Request. One/zero for remote/data frame.
3772 */
3773#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
3774#define CAN_CS_IDE_MASK (0x200000U)
3775#define CAN_CS_IDE_SHIFT (21U)
3776/*! IDE - ID Extended. One/zero for extended/standard format frame.
3777 */
3778#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
3779#define CAN_CS_SRR_MASK (0x400000U)
3780#define CAN_CS_SRR_SHIFT (22U)
3781/*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
3782 */
3783#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
3784#define CAN_CS_CODE_MASK (0xF000000U)
3785#define CAN_CS_CODE_SHIFT (24U)
3786/*! CODE - Reserved
3787 */
3788#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
3789/*! @} */
3790
3791/* The count of CAN_CS */
3792#define CAN_CS_COUNT (64U)
3793
3794/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
3795/*! @{ */
3796#define CAN_ID_EXT_MASK (0x3FFFFU)
3797#define CAN_ID_EXT_SHIFT (0U)
3798/*! EXT - Contains extended (LOW word) identifier of message buffer.
3799 */
3800#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
3801#define CAN_ID_STD_MASK (0x1FFC0000U)
3802#define CAN_ID_STD_SHIFT (18U)
3803/*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
3804 */
3805#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
3806#define CAN_ID_PRIO_MASK (0xE0000000U)
3807#define CAN_ID_PRIO_SHIFT (29U)
3808/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
3809 * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
3810 * ID to define the transmission priority.
3811 */
3812#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
3813/*! @} */
3814
3815/* The count of CAN_ID */
3816#define CAN_ID_COUNT (64U)
3817
3818/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
3819/*! @{ */
3820#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
3821#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
3822/*! DATA_BYTE_3 - Data byte 3 of Rx/Tx frame.
3823 */
3824#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
3825#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
3826#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
3827/*! DATA_BYTE_2 - Data byte 2 of Rx/Tx frame.
3828 */
3829#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
3830#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
3831#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
3832/*! DATA_BYTE_1 - Data byte 1 of Rx/Tx frame.
3833 */
3834#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
3835#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
3836#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
3837/*! DATA_BYTE_0 - Data byte 0 of Rx/Tx frame.
3838 */
3839#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
3840/*! @} */
3841
3842/* The count of CAN_WORD0 */
3843#define CAN_WORD0_COUNT (64U)
3844
3845/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
3846/*! @{ */
3847#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
3848#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
3849/*! DATA_BYTE_7 - Data byte 7 of Rx/Tx frame.
3850 */
3851#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
3852#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
3853#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
3854/*! DATA_BYTE_6 - Data byte 6 of Rx/Tx frame.
3855 */
3856#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
3857#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
3858#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
3859/*! DATA_BYTE_5 - Data byte 5 of Rx/Tx frame.
3860 */
3861#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
3862#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
3863#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
3864/*! DATA_BYTE_4 - Data byte 4 of Rx/Tx frame.
3865 */
3866#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
3867/*! @} */
3868
3869/* The count of CAN_WORD1 */
3870#define CAN_WORD1_COUNT (64U)
3871
3872/*! @name RXIMR - Rx Individual Mask Registers */
3873/*! @{ */
3874#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
3875#define CAN_RXIMR_MI_SHIFT (0U)
3876/*! MI
3877 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
3878 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
3879 */
3880#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
3881/*! @} */
3882
3883/* The count of CAN_RXIMR */
3884#define CAN_RXIMR_COUNT (64U)
3885
3886/*! @name GFWR - Glitch Filter Width Registers */
3887/*! @{ */
3888#define CAN_GFWR_GFWR_MASK (0xFFU)
3889#define CAN_GFWR_GFWR_SHIFT (0U)
3890#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)
3891/*! @} */
3892
3893
3894/*!
3895 * @}
3896 */ /* end of group CAN_Register_Masks */
3897
3898
3899/* CAN - Peripheral instance base addresses */
3900/** Peripheral CAN1 base address */
3901#define CAN1_BASE (0x401D0000u)
3902/** Peripheral CAN1 base pointer */
3903#define CAN1 ((CAN_Type *)CAN1_BASE)
3904/** Peripheral CAN2 base address */
3905#define CAN2_BASE (0x401D4000u)
3906/** Peripheral CAN2 base pointer */
3907#define CAN2 ((CAN_Type *)CAN2_BASE)
3908/** Array initializer of CAN peripheral base addresses */
3909#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE }
3910/** Array initializer of CAN peripheral base pointers */
3911#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 }
3912/** Interrupt vectors for the CAN peripheral type */
3913#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
3914#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
3915#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
3916#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
3917#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
3918#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
3919/* Backward compatibility */
3920#define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK
3921#define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT
3922#define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x)
3923#define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK
3924#define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT
3925#define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x)
3926
3927
3928/*!
3929 * @}
3930 */ /* end of group CAN_Peripheral_Access_Layer */
3931
3932
3933/* ----------------------------------------------------------------------------
3934 -- CCM Peripheral Access Layer
3935 ---------------------------------------------------------------------------- */
3936
3937/*!
3938 * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
3939 * @{
3940 */
3941
3942/** CCM - Register Layout Typedef */
3943typedef struct {
3944 __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */
3945 uint8_t RESERVED_0[4];
3946 __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */
3947 __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */
3948 __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */
3949 __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */
3950 __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */
3951 __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */
3952 __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */
3953 __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */
3954 __IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */
3955 __IO uint32_t CS2CDR; /**< CCM Clock Divider Register, offset: 0x2C */
3956 __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */
3957 uint8_t RESERVED_1[4];
3958 __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */
3959 uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */
3960 uint8_t RESERVED_2[8];
3961 __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */
3962 uint8_t RESERVED_3[8];
3963 __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */
3964 __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */
3965 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */
3966 __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */
3967 __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */
3968 __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */
3969 __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */
3970 __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */
3971 __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */
3972 __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */
3973 __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */
3974 __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */
3975 uint8_t RESERVED_4[4];
3976 __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */
3977} CCM_Type;
3978
3979/* ----------------------------------------------------------------------------
3980 -- CCM Register Masks
3981 ---------------------------------------------------------------------------- */
3982
3983/*!
3984 * @addtogroup CCM_Register_Masks CCM Register Masks
3985 * @{
3986 */
3987
3988/*! @name CCR - CCM Control Register */
3989/*! @{ */
3990#define CCM_CCR_OSCNT_MASK (0xFFU)
3991#define CCM_CCR_OSCNT_SHIFT (0U)
3992/*! OSCNT - Oscillator ready counter value. These bits define value of 32KHz counter, that serve as
3993 * counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time.
3994 * Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from
3995 * stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for
3996 * the dpll_ip to use and only then the gate in dpll_ip can be opened.
3997 */
3998#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
3999#define CCM_CCR_COSC_EN_MASK (0x1000U)
4000#define CCM_CCR_COSC_EN_SHIFT (12U)
4001/*! COSC_EN
4002 * 0b0..disable on chip oscillator
4003 * 0b1..enable on chip oscillator
4004 */
4005#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
4006#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
4007#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
4008/*! REG_BYPASS_COUNT
4009 * 0b000000..no delay
4010 * 0b000001..1 CKIL clock period delay
4011 * 0b111111..63 CKIL clock periods delay
4012 */
4013#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
4014#define CCM_CCR_RBC_EN_MASK (0x8000000U)
4015#define CCM_CCR_RBC_EN_SHIFT (27U)
4016/*! RBC_EN
4017 * 0b1..REG_BYPASS_COUNTER enabled.
4018 * 0b0..REG_BYPASS_COUNTER disabled
4019 */
4020#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
4021/*! @} */
4022
4023/*! @name CSR - CCM Status Register */
4024/*! @{ */
4025#define CCM_CSR_REF_EN_B_MASK (0x1U)
4026#define CCM_CSR_REF_EN_B_SHIFT (0U)
4027/*! REF_EN_B
4028 * 0b0..value of CCM_REF_EN_B is '0'
4029 * 0b1..value of CCM_REF_EN_B is '1'
4030 */
4031#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
4032#define CCM_CSR_CAMP2_READY_MASK (0x8U)
4033#define CCM_CSR_CAMP2_READY_SHIFT (3U)
4034/*! CAMP2_READY
4035 * 0b0..CAMP2 is not ready.
4036 * 0b1..CAMP2 is ready.
4037 */
4038#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
4039#define CCM_CSR_COSC_READY_MASK (0x20U)
4040#define CCM_CSR_COSC_READY_SHIFT (5U)
4041/*! COSC_READY
4042 * 0b0..on board oscillator is not ready.
4043 * 0b1..on board oscillator is ready.
4044 */
4045#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
4046/*! @} */
4047
4048/*! @name CCSR - CCM Clock Switcher Register */
4049/*! @{ */
4050#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
4051#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
4052/*! PLL3_SW_CLK_SEL
4053 * 0b0..pll3_main_clk
4054 * 0b1..pll3 bypass clock
4055 */
4056#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
4057/*! @} */
4058
4059/*! @name CACRR - CCM Arm Clock Root Register */
4060/*! @{ */
4061#define CCM_CACRR_ARM_PODF_MASK (0x7U)
4062#define CCM_CACRR_ARM_PODF_SHIFT (0U)
4063/*! ARM_PODF
4064 * 0b000..divide by 1
4065 * 0b001..divide by 2
4066 * 0b010..divide by 3
4067 * 0b011..divide by 4
4068 * 0b100..divide by 5
4069 * 0b101..divide by 6
4070 * 0b110..divide by 7
4071 * 0b111..divide by 8
4072 */
4073#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
4074/*! @} */
4075
4076/*! @name CBCDR - CCM Bus Clock Divider Register */
4077/*! @{ */
4078#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)
4079#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)
4080/*! SEMC_CLK_SEL
4081 * 0b0..Periph_clk output will be used as SEMC clock root
4082 * 0b1..SEMC alternative clock will be used as SEMC clock root
4083 */
4084#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
4085#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)
4086#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)
4087/*! SEMC_ALT_CLK_SEL
4088 * 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock
4089 * 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock
4090 */
4091#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
4092#define CCM_CBCDR_IPG_PODF_MASK (0x300U)
4093#define CCM_CBCDR_IPG_PODF_SHIFT (8U)
4094/*! IPG_PODF
4095 * 0b00..divide by 1
4096 * 0b01..divide by 2
4097 * 0b10..divide by 3
4098 * 0b11..divide by 4
4099 */
4100#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
4101#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
4102#define CCM_CBCDR_AHB_PODF_SHIFT (10U)
4103/*! AHB_PODF
4104 * 0b000..divide by 1
4105 * 0b001..divide by 2
4106 * 0b010..divide by 3
4107 * 0b011..divide by 4
4108 * 0b100..divide by 5
4109 * 0b101..divide by 6
4110 * 0b110..divide by 7
4111 * 0b111..divide by 8
4112 */
4113#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
4114#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U)
4115#define CCM_CBCDR_SEMC_PODF_SHIFT (16U)
4116/*! SEMC_PODF
4117 * 0b000..divide by 1
4118 * 0b001..divide by 2
4119 * 0b010..divide by 3
4120 * 0b011..divide by 4
4121 * 0b100..divide by 5
4122 * 0b101..divide by 6
4123 * 0b110..divide by 7
4124 * 0b111..divide by 8
4125 */
4126#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
4127#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
4128#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
4129/*! PERIPH_CLK_SEL
4130 * 0b0..derive clock from pre_periph_clk_sel
4131 * 0b1..derive clock from periph_clk2_clk_divided
4132 */
4133#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
4134#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)
4135#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)
4136/*! PERIPH_CLK2_PODF
4137 * 0b000..divide by 1
4138 * 0b001..divide by 2
4139 * 0b010..divide by 3
4140 * 0b011..divide by 4
4141 * 0b100..divide by 5
4142 * 0b101..divide by 6
4143 * 0b110..divide by 7
4144 * 0b111..divide by 8
4145 */
4146#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
4147/*! @} */
4148
4149/*! @name CBCMR - CCM Bus Clock Multiplexer Register */
4150/*! @{ */
4151#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
4152#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
4153/*! LPSPI_CLK_SEL
4154 * 0b00..derive clock from PLL3 PFD1 clk
4155 * 0b01..derive clock from PLL3 PFD0
4156 * 0b10..derive clock from PLL2
4157 * 0b11..derive clock from PLL2 PFD2
4158 */
4159#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
4160#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
4161#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
4162/*! PERIPH_CLK2_SEL
4163 * 0b00..derive clock from pll3_sw_clk
4164 * 0b01..derive clock from osc_clk
4165 * 0b10..derive clock from pll2_bypass_clk
4166 * 0b11..reserved
4167 */
4168#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
4169#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
4170#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
4171/*! TRACE_CLK_SEL
4172 * 0b00..derive clock from PLL2
4173 * 0b01..derive clock from PLL2 PFD2
4174 * 0b10..derive clock from PLL2 PFD0
4175 * 0b11..derive clock from PLL2 PFD1
4176 */
4177#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
4178#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
4179#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
4180/*! PRE_PERIPH_CLK_SEL
4181 * 0b00..derive clock from PLL2
4182 * 0b01..derive clock from PLL3 PFD3
4183 * 0b10..derive clock from PLL2 PFD3
4184 * 0b11..derive clock from divided PLL6
4185 */
4186#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
4187#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)
4188#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
4189/*! LPSPI_PODF
4190 * 0b000..divide by 1
4191 * 0b001..divide by 2
4192 * 0b010..divide by 3
4193 * 0b011..divide by 4
4194 * 0b100..divide by 5
4195 * 0b101..divide by 6
4196 * 0b110..divide by 7
4197 * 0b111..divide by 8
4198 */
4199#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
4200/*! @} */
4201
4202/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */
4203/*! @{ */
4204#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
4205#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
4206/*! PERCLK_PODF - Divider for perclk podf.
4207 * 0b000000..Divide by 1
4208 * 0b000001..Divide by 2
4209 * 0b000010..Divide by 3
4210 * 0b000011..Divide by 4
4211 * 0b000100..Divide by 5
4212 * 0b000101..Divide by 6
4213 * 0b000110..Divide by 7
4214 * 0b000111..Divide by 8
4215 * 0b001000..Divide by 9
4216 * 0b001001..Divide by 10
4217 * 0b001010..Divide by 11
4218 * 0b001011..Divide by 12
4219 * 0b001100..Divide by 13
4220 * 0b001101..Divide by 14
4221 * 0b001110..Divide by 15
4222 * 0b001111..Divide by 16
4223 * 0b010000..Divide by 17
4224 * 0b010001..Divide by 18
4225 * 0b010010..Divide by 19
4226 * 0b010011..Divide by 20
4227 * 0b010100..Divide by 21
4228 * 0b010101..Divide by 22
4229 * 0b010110..Divide by 23
4230 * 0b010111..Divide by 24
4231 * 0b011000..Divide by 25
4232 * 0b011001..Divide by 26
4233 * 0b011010..Divide by 27
4234 * 0b011011..Divide by 28
4235 * 0b011100..Divide by 29
4236 * 0b011101..Divide by 30
4237 * 0b011110..Divide by 31
4238 * 0b011111..Divide by 32
4239 * 0b100000..Divide by 33
4240 * 0b100001..Divide by 34
4241 * 0b100010..Divide by 35
4242 * 0b100011..Divide by 36
4243 * 0b100100..Divide by 37
4244 * 0b100101..Divide by 38
4245 * 0b100110..Divide by 39
4246 * 0b100111..Divide by 40
4247 * 0b101000..Divide by 41
4248 * 0b101001..Divide by 42
4249 * 0b101010..Divide by 43
4250 * 0b101011..Divide by 44
4251 * 0b101100..Divide by 45
4252 * 0b101101..Divide by 46
4253 * 0b101110..Divide by 47
4254 * 0b101111..Divide by 48
4255 * 0b110000..Divide by 49
4256 * 0b110001..Divide by 50
4257 * 0b110010..Divide by 51
4258 * 0b110011..Divide by 52
4259 * 0b110100..Divide by 53
4260 * 0b110101..Divide by 54
4261 * 0b110110..Divide by 55
4262 * 0b110111..Divide by 56
4263 * 0b111000..Divide by 57
4264 * 0b111001..Divide by 58
4265 * 0b111010..Divide by 59
4266 * 0b111011..Divide by 60
4267 * 0b111100..Divide by 61
4268 * 0b111101..Divide by 62
4269 * 0b111110..Divide by 63
4270 * 0b111111..Divide by 64
4271 */
4272#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
4273#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
4274#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
4275/*! PERCLK_CLK_SEL
4276 * 0b0..derive clock from ipg clk root
4277 * 0b1..derive clock from osc_clk
4278 */
4279#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
4280#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
4281#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
4282/*! SAI1_CLK_SEL
4283 * 0b00..derive clock from PLL3 PFD2
4284 * 0b01..Reserved
4285 * 0b10..derive clock from PLL4
4286 * 0b11..Reserved
4287 */
4288#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
4289#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)
4290#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)
4291/*! SAI2_CLK_SEL
4292 * 0b00..derive clock from PLL3 PFD2
4293 * 0b01..Reserved
4294 * 0b10..derive clock from PLL4
4295 * 0b11..Reserved
4296 */
4297#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
4298#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
4299#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
4300/*! SAI3_CLK_SEL
4301 * 0b00..derive clock from PLL3 PFD2
4302 * 0b01..Reserved
4303 * 0b10..derive clock from PLL4
4304 * 0b11..Reserved
4305 */
4306#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
4307#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)
4308#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)
4309/*! USDHC1_CLK_SEL
4310 * 0b0..derive clock from PLL2 PFD2
4311 * 0b1..derive clock from PLL2 PFD0
4312 */
4313#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
4314#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)
4315#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)
4316/*! USDHC2_CLK_SEL
4317 * 0b0..derive clock from PLL2 PFD2
4318 * 0b1..derive clock from PLL2 PFD0
4319 */
4320#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
4321#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
4322#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
4323/*! FLEXSPI_PODF
4324 * 0b000..divide by 1
4325 * 0b001..divide by 2
4326 * 0b010..divide by 3
4327 * 0b011..divide by 4
4328 * 0b100..divide by 5
4329 * 0b101..divide by 6
4330 * 0b110..divide by 7
4331 * 0b111..divide by 8
4332 */
4333#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
4334#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
4335#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
4336/*! FLEXSPI_CLK_SEL
4337 * 0b00..derive clock from semc_clk_root_pre
4338 * 0b01..derive clock from pll3_sw_clk
4339 * 0b10..derive clock from PLL2 PFD2
4340 * 0b11..derive clock from PLL3 PFD0
4341 */
4342#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
4343/*! @} */
4344
4345/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */
4346/*! @{ */
4347#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)
4348#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)
4349/*! CAN_CLK_PODF - Divider for CAN clock podf.
4350 * 0b000000..Divide by 1
4351 * 0b000001..Divide by 2
4352 * 0b000010..Divide by 3
4353 * 0b000011..Divide by 4
4354 * 0b000100..Divide by 5
4355 * 0b000101..Divide by 6
4356 * 0b000110..Divide by 7
4357 * 0b000111..Divide by 8
4358 * 0b001000..Divide by 9
4359 * 0b001001..Divide by 10
4360 * 0b001010..Divide by 11
4361 * 0b001011..Divide by 12
4362 * 0b001100..Divide by 13
4363 * 0b001101..Divide by 14
4364 * 0b001110..Divide by 15
4365 * 0b001111..Divide by 16
4366 * 0b010000..Divide by 17
4367 * 0b010001..Divide by 18
4368 * 0b010010..Divide by 19
4369 * 0b010011..Divide by 20
4370 * 0b010100..Divide by 21
4371 * 0b010101..Divide by 22
4372 * 0b010110..Divide by 23
4373 * 0b010111..Divide by 24
4374 * 0b011000..Divide by 25
4375 * 0b011001..Divide by 26
4376 * 0b011010..Divide by 27
4377 * 0b011011..Divide by 28
4378 * 0b011100..Divide by 29
4379 * 0b011101..Divide by 30
4380 * 0b011110..Divide by 31
4381 * 0b011111..Divide by 32
4382 * 0b100000..Divide by 33
4383 * 0b100001..Divide by 34
4384 * 0b100010..Divide by 35
4385 * 0b100011..Divide by 36
4386 * 0b100100..Divide by 37
4387 * 0b100101..Divide by 38
4388 * 0b100110..Divide by 39
4389 * 0b100111..Divide by 40
4390 * 0b101000..Divide by 41
4391 * 0b101001..Divide by 42
4392 * 0b101010..Divide by 43
4393 * 0b101011..Divide by 44
4394 * 0b101100..Divide by 45
4395 * 0b101101..Divide by 46
4396 * 0b101110..Divide by 47
4397 * 0b101111..Divide by 48
4398 * 0b110000..Divide by 49
4399 * 0b110001..Divide by 50
4400 * 0b110010..Divide by 51
4401 * 0b110011..Divide by 52
4402 * 0b110100..Divide by 53
4403 * 0b110101..Divide by 54
4404 * 0b110110..Divide by 55
4405 * 0b110111..Divide by 56
4406 * 0b111000..Divide by 57
4407 * 0b111001..Divide by 58
4408 * 0b111010..Divide by 59
4409 * 0b111011..Divide by 60
4410 * 0b111100..Divide by 61
4411 * 0b111101..Divide by 62
4412 * 0b111110..Divide by 63
4413 * 0b111111..Divide by 64
4414 */
4415#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
4416#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)
4417#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)
4418/*! CAN_CLK_SEL
4419 * 0b00..derive clock from pll3_sw_clk divided clock (60M)
4420 * 0b01..derive clock from osc_clk (24M)
4421 * 0b10..derive clock from pll3_sw_clk divided clock (80M)
4422 */
4423#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
4424#define CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK (0x180000U)
4425#define CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT (19U)
4426/*! FLEXIO1_CLK_SEL
4427 * 0b00..derive clock from PLL4 divided clock
4428 * 0b01..derive clock from PLL3 PFD2 clock
4429 * 0b10..Reserved
4430 * 0b11..derive clock from pll3_sw_clk
4431 */
4432#define CCM_CSCMR2_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO1_CLK_SEL_MASK)
4433/*! @} */
4434
4435/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */
4436/*! @{ */
4437#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
4438#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
4439/*! UART_CLK_PODF - Divider for uart clock podf.
4440 * 0b000000..Divide by 1
4441 * 0b000001..Divide by 2
4442 * 0b000010..Divide by 3
4443 * 0b000011..Divide by 4
4444 * 0b000100..Divide by 5
4445 * 0b000101..Divide by 6
4446 * 0b000110..Divide by 7
4447 * 0b000111..Divide by 8
4448 * 0b001000..Divide by 9
4449 * 0b001001..Divide by 10
4450 * 0b001010..Divide by 11
4451 * 0b001011..Divide by 12
4452 * 0b001100..Divide by 13
4453 * 0b001101..Divide by 14
4454 * 0b001110..Divide by 15
4455 * 0b001111..Divide by 16
4456 * 0b010000..Divide by 17
4457 * 0b010001..Divide by 18
4458 * 0b010010..Divide by 19
4459 * 0b010011..Divide by 20
4460 * 0b010100..Divide by 21
4461 * 0b010101..Divide by 22
4462 * 0b010110..Divide by 23
4463 * 0b010111..Divide by 24
4464 * 0b011000..Divide by 25
4465 * 0b011001..Divide by 26
4466 * 0b011010..Divide by 27
4467 * 0b011011..Divide by 28
4468 * 0b011100..Divide by 29
4469 * 0b011101..Divide by 30
4470 * 0b011110..Divide by 31
4471 * 0b011111..Divide by 32
4472 * 0b100000..Divide by 33
4473 * 0b100001..Divide by 34
4474 * 0b100010..Divide by 35
4475 * 0b100011..Divide by 36
4476 * 0b100100..Divide by 37
4477 * 0b100101..Divide by 38
4478 * 0b100110..Divide by 39
4479 * 0b100111..Divide by 40
4480 * 0b101000..Divide by 41
4481 * 0b101001..Divide by 42
4482 * 0b101010..Divide by 43
4483 * 0b101011..Divide by 44
4484 * 0b101100..Divide by 45
4485 * 0b101101..Divide by 46
4486 * 0b101110..Divide by 47
4487 * 0b101111..Divide by 48
4488 * 0b110000..Divide by 49
4489 * 0b110001..Divide by 50
4490 * 0b110010..Divide by 51
4491 * 0b110011..Divide by 52
4492 * 0b110100..Divide by 53
4493 * 0b110101..Divide by 54
4494 * 0b110110..Divide by 55
4495 * 0b110111..Divide by 56
4496 * 0b111000..Divide by 57
4497 * 0b111001..Divide by 58
4498 * 0b111010..Divide by 59
4499 * 0b111011..Divide by 60
4500 * 0b111100..Divide by 61
4501 * 0b111101..Divide by 62
4502 * 0b111110..Divide by 63
4503 * 0b111111..Divide by 64
4504 */
4505#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
4506#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)
4507#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
4508/*! UART_CLK_SEL
4509 * 0b0..derive clock from pll3_80m
4510 * 0b1..derive clock from osc_clk
4511 */
4512#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
4513#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)
4514#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)
4515/*! USDHC1_PODF
4516 * 0b000..divide by 1
4517 * 0b001..divide by 2
4518 * 0b010..divide by 3
4519 * 0b011..divide by 4
4520 * 0b100..divide by 5
4521 * 0b101..divide by 6
4522 * 0b110..divide by 7
4523 * 0b111..divide by 8
4524 */
4525#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
4526#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)
4527#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)
4528/*! USDHC2_PODF
4529 * 0b000..divide by 1
4530 * 0b001..divide by 2
4531 * 0b010..divide by 3
4532 * 0b011..divide by 4
4533 * 0b100..divide by 5
4534 * 0b101..divide by 6
4535 * 0b110..divide by 7
4536 * 0b111..divide by 8
4537 */
4538#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
4539#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)
4540#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
4541/*! TRACE_PODF
4542 * 0b00..divide by 1
4543 * 0b01..divide by 2
4544 * 0b10..divide by 3
4545 * 0b11..divide by 4
4546 */
4547#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
4548/*! @} */
4549
4550/*! @name CS1CDR - CCM Clock Divider Register */
4551/*! @{ */
4552#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
4553#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
4554/*! SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower
4555 * than 300Mhz, the predivider can be used to achieve this.
4556 * 0b000000..Divide by 1
4557 * 0b000001..Divide by 2
4558 * 0b000010..Divide by 3
4559 * 0b000011..Divide by 4
4560 * 0b000100..Divide by 5
4561 * 0b000101..Divide by 6
4562 * 0b000110..Divide by 7
4563 * 0b000111..Divide by 8
4564 * 0b001000..Divide by 9
4565 * 0b001001..Divide by 10
4566 * 0b001010..Divide by 11
4567 * 0b001011..Divide by 12
4568 * 0b001100..Divide by 13
4569 * 0b001101..Divide by 14
4570 * 0b001110..Divide by 15
4571 * 0b001111..Divide by 16
4572 * 0b010000..Divide by 17
4573 * 0b010001..Divide by 18
4574 * 0b010010..Divide by 19
4575 * 0b010011..Divide by 20
4576 * 0b010100..Divide by 21
4577 * 0b010101..Divide by 22
4578 * 0b010110..Divide by 23
4579 * 0b010111..Divide by 24
4580 * 0b011000..Divide by 25
4581 * 0b011001..Divide by 26
4582 * 0b011010..Divide by 27
4583 * 0b011011..Divide by 28
4584 * 0b011100..Divide by 29
4585 * 0b011101..Divide by 30
4586 * 0b011110..Divide by 31
4587 * 0b011111..Divide by 32
4588 * 0b100000..Divide by 33
4589 * 0b100001..Divide by 34
4590 * 0b100010..Divide by 35
4591 * 0b100011..Divide by 36
4592 * 0b100100..Divide by 37
4593 * 0b100101..Divide by 38
4594 * 0b100110..Divide by 39
4595 * 0b100111..Divide by 40
4596 * 0b101000..Divide by 41
4597 * 0b101001..Divide by 42
4598 * 0b101010..Divide by 43
4599 * 0b101011..Divide by 44
4600 * 0b101100..Divide by 45
4601 * 0b101101..Divide by 46
4602 * 0b101110..Divide by 47
4603 * 0b101111..Divide by 48
4604 * 0b110000..Divide by 49
4605 * 0b110001..Divide by 50
4606 * 0b110010..Divide by 51
4607 * 0b110011..Divide by 52
4608 * 0b110100..Divide by 53
4609 * 0b110101..Divide by 54
4610 * 0b110110..Divide by 55
4611 * 0b110111..Divide by 56
4612 * 0b111000..Divide by 57
4613 * 0b111001..Divide by 58
4614 * 0b111010..Divide by 59
4615 * 0b111011..Divide by 60
4616 * 0b111100..Divide by 61
4617 * 0b111101..Divide by 62
4618 * 0b111110..Divide by 63
4619 * 0b111111..Divide by 64
4620 */
4621#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
4622#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
4623#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
4624/*! SAI1_CLK_PRED
4625 * 0b000..divide by 1
4626 * 0b001..divide by 2
4627 * 0b010..divide by 3
4628 * 0b011..divide by 4
4629 * 0b100..divide by 5
4630 * 0b101..divide by 6
4631 * 0b110..divide by 7
4632 * 0b111..divide by 8
4633 */
4634#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
4635#define CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK (0xE00U)
4636#define CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT (9U)
4637/*! FLEXIO1_CLK_PRED
4638 * 0b000..divide by 1
4639 * 0b001..divide by 2
4640 * 0b010..divide by 3
4641 * 0b011..divide by 4
4642 * 0b100..divide by 5
4643 * 0b101..divide by 6
4644 * 0b110..divide by 7
4645 * 0b111..divide by 8
4646 */
4647#define CCM_CS1CDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PRED_MASK)
4648#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
4649#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
4650/*! SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower
4651 * than 300Mhz, the predivider can be used to achieve this.
4652 * 0b000000..Divide by 1
4653 * 0b000001..Divide by 2
4654 * 0b000010..Divide by 3
4655 * 0b000011..Divide by 4
4656 * 0b000100..Divide by 5
4657 * 0b000101..Divide by 6
4658 * 0b000110..Divide by 7
4659 * 0b000111..Divide by 8
4660 * 0b001000..Divide by 9
4661 * 0b001001..Divide by 10
4662 * 0b001010..Divide by 11
4663 * 0b001011..Divide by 12
4664 * 0b001100..Divide by 13
4665 * 0b001101..Divide by 14
4666 * 0b001110..Divide by 15
4667 * 0b001111..Divide by 16
4668 * 0b010000..Divide by 17
4669 * 0b010001..Divide by 18
4670 * 0b010010..Divide by 19
4671 * 0b010011..Divide by 20
4672 * 0b010100..Divide by 21
4673 * 0b010101..Divide by 22
4674 * 0b010110..Divide by 23
4675 * 0b010111..Divide by 24
4676 * 0b011000..Divide by 25
4677 * 0b011001..Divide by 26
4678 * 0b011010..Divide by 27
4679 * 0b011011..Divide by 28
4680 * 0b011100..Divide by 29
4681 * 0b011101..Divide by 30
4682 * 0b011110..Divide by 31
4683 * 0b011111..Divide by 32
4684 * 0b100000..Divide by 33
4685 * 0b100001..Divide by 34
4686 * 0b100010..Divide by 35
4687 * 0b100011..Divide by 36
4688 * 0b100100..Divide by 37
4689 * 0b100101..Divide by 38
4690 * 0b100110..Divide by 39
4691 * 0b100111..Divide by 40
4692 * 0b101000..Divide by 41
4693 * 0b101001..Divide by 42
4694 * 0b101010..Divide by 43
4695 * 0b101011..Divide by 44
4696 * 0b101100..Divide by 45
4697 * 0b101101..Divide by 46
4698 * 0b101110..Divide by 47
4699 * 0b101111..Divide by 48
4700 * 0b110000..Divide by 49
4701 * 0b110001..Divide by 50
4702 * 0b110010..Divide by 51
4703 * 0b110011..Divide by 52
4704 * 0b110100..Divide by 53
4705 * 0b110101..Divide by 54
4706 * 0b110110..Divide by 55
4707 * 0b110111..Divide by 56
4708 * 0b111000..Divide by 57
4709 * 0b111001..Divide by 58
4710 * 0b111010..Divide by 59
4711 * 0b111011..Divide by 60
4712 * 0b111100..Divide by 61
4713 * 0b111101..Divide by 62
4714 * 0b111110..Divide by 63
4715 * 0b111111..Divide by 64
4716 */
4717#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
4718#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
4719#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
4720/*! SAI3_CLK_PRED
4721 * 0b000..divide by 1
4722 * 0b001..divide by 2
4723 * 0b010..divide by 3
4724 * 0b011..divide by 4
4725 * 0b100..divide by 5
4726 * 0b101..divide by 6
4727 * 0b110..divide by 7
4728 * 0b111..divide by 8
4729 */
4730#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
4731#define CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK (0xE000000U)
4732#define CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT (25U)
4733/*! FLEXIO1_CLK_PODF - Divider for flexio1 clock. Divider should be updated when output clock is gated.
4734 * 0b000..Divide by 1
4735 * 0b001..Divide by 2
4736 * 0b010..Divide by 3
4737 * 0b011..Divide by 4
4738 * 0b100..Divide by 5
4739 * 0b101..Divide by 6
4740 * 0b110..Divide by 7
4741 * 0b111..Divide by 8
4742 */
4743#define CCM_CS1CDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO1_CLK_PODF_MASK)
4744/*! @} */
4745
4746/*! @name CS2CDR - CCM Clock Divider Register */
4747/*! @{ */
4748#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)
4749#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)
4750/*! SAI2_CLK_PODF - Divider for sai2 clock podf. The input clock to this divider should be lower
4751 * than 300Mhz, the predivider can be used to achieve this.
4752 * 0b000000..Divide by 1
4753 * 0b000001..Divide by 2
4754 * 0b000010..Divide by 3
4755 * 0b000011..Divide by 4
4756 * 0b000100..Divide by 5
4757 * 0b000101..Divide by 6
4758 * 0b000110..Divide by 7
4759 * 0b000111..Divide by 8
4760 * 0b001000..Divide by 9
4761 * 0b001001..Divide by 10
4762 * 0b001010..Divide by 11
4763 * 0b001011..Divide by 12
4764 * 0b001100..Divide by 13
4765 * 0b001101..Divide by 14
4766 * 0b001110..Divide by 15
4767 * 0b001111..Divide by 16
4768 * 0b010000..Divide by 17
4769 * 0b010001..Divide by 18
4770 * 0b010010..Divide by 19
4771 * 0b010011..Divide by 20
4772 * 0b010100..Divide by 21
4773 * 0b010101..Divide by 22
4774 * 0b010110..Divide by 23
4775 * 0b010111..Divide by 24
4776 * 0b011000..Divide by 25
4777 * 0b011001..Divide by 26
4778 * 0b011010..Divide by 27
4779 * 0b011011..Divide by 28
4780 * 0b011100..Divide by 29
4781 * 0b011101..Divide by 30
4782 * 0b011110..Divide by 31
4783 * 0b011111..Divide by 32
4784 * 0b100000..Divide by 33
4785 * 0b100001..Divide by 34
4786 * 0b100010..Divide by 35
4787 * 0b100011..Divide by 36
4788 * 0b100100..Divide by 37
4789 * 0b100101..Divide by 38
4790 * 0b100110..Divide by 39
4791 * 0b100111..Divide by 40
4792 * 0b101000..Divide by 41
4793 * 0b101001..Divide by 42
4794 * 0b101010..Divide by 43
4795 * 0b101011..Divide by 44
4796 * 0b101100..Divide by 45
4797 * 0b101101..Divide by 46
4798 * 0b101110..Divide by 47
4799 * 0b101111..Divide by 48
4800 * 0b110000..Divide by 49
4801 * 0b110001..Divide by 50
4802 * 0b110010..Divide by 51
4803 * 0b110011..Divide by 52
4804 * 0b110100..Divide by 53
4805 * 0b110101..Divide by 54
4806 * 0b110110..Divide by 55
4807 * 0b110111..Divide by 56
4808 * 0b111000..Divide by 57
4809 * 0b111001..Divide by 58
4810 * 0b111010..Divide by 59
4811 * 0b111011..Divide by 60
4812 * 0b111100..Divide by 61
4813 * 0b111101..Divide by 62
4814 * 0b111110..Divide by 63
4815 * 0b111111..Divide by 64
4816 */
4817#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
4818#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)
4819#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)
4820/*! SAI2_CLK_PRED
4821 * 0b000..divide by 1
4822 * 0b001..divide by 2
4823 * 0b010..divide by 3
4824 * 0b011..divide by 4
4825 * 0b100..divide by 5
4826 * 0b101..divide by 6
4827 * 0b110..divide by 7
4828 * 0b111..divide by 8
4829 */
4830#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
4831/*! @} */
4832
4833/*! @name CDCDR - CCM D1 Clock Divider Register */
4834/*! @{ */
4835#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
4836#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
4837/*! SPDIF0_CLK_SEL
4838 * 0b00..derive clock from PLL4
4839 * 0b01..derive clock from PLL3 PFD2
4840 * 0b10..Reserved
4841 * 0b11..derive clock from pll3_sw_clk
4842 */
4843#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
4844#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
4845#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
4846/*! SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
4847 * 0b000..Divide by 1
4848 * 0b001..Divide by 2
4849 * 0b010..Divide by 3
4850 * 0b011..Divide by 4
4851 * 0b100..Divide by 5
4852 * 0b101..Divide by 6
4853 * 0b110..Divide by 7
4854 * 0b111..Divide by 8
4855 */
4856#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
4857#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
4858#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
4859/*! SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated.
4860 * 0b000..Divide by 1
4861 * 0b001..Divide by 2
4862 * 0b010..Divide by 3
4863 * 0b011..Divide by 4
4864 * 0b100..Divide by 5
4865 * 0b101..Divide by 6
4866 * 0b110..Divide by 7
4867 * 0b111..Divide by 8
4868 */
4869#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
4870/*! @} */
4871
4872/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */
4873/*! @{ */
4874#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
4875#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
4876/*! LPI2C_CLK_SEL
4877 * 0b0..derive clock from pll3_60m
4878 * 0b1..derive clock from osc_clk
4879 */
4880#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
4881#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
4882#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
4883/*! LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is
4884 * gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used
4885 * to achieve this.
4886 * 0b000000..Divide by 1
4887 * 0b000001..Divide by 2
4888 * 0b000010..Divide by 3
4889 * 0b000011..Divide by 4
4890 * 0b000100..Divide by 5
4891 * 0b000101..Divide by 6
4892 * 0b000110..Divide by 7
4893 * 0b000111..Divide by 8
4894 * 0b001000..Divide by 9
4895 * 0b001001..Divide by 10
4896 * 0b001010..Divide by 11
4897 * 0b001011..Divide by 12
4898 * 0b001100..Divide by 13
4899 * 0b001101..Divide by 14
4900 * 0b001110..Divide by 15
4901 * 0b001111..Divide by 16
4902 * 0b010000..Divide by 17
4903 * 0b010001..Divide by 18
4904 * 0b010010..Divide by 19
4905 * 0b010011..Divide by 20
4906 * 0b010100..Divide by 21
4907 * 0b010101..Divide by 22
4908 * 0b010110..Divide by 23
4909 * 0b010111..Divide by 24
4910 * 0b011000..Divide by 25
4911 * 0b011001..Divide by 26
4912 * 0b011010..Divide by 27
4913 * 0b011011..Divide by 28
4914 * 0b011100..Divide by 29
4915 * 0b011101..Divide by 30
4916 * 0b011110..Divide by 31
4917 * 0b011111..Divide by 32
4918 * 0b100000..Divide by 33
4919 * 0b100001..Divide by 34
4920 * 0b100010..Divide by 35
4921 * 0b100011..Divide by 36
4922 * 0b100100..Divide by 37
4923 * 0b100101..Divide by 38
4924 * 0b100110..Divide by 39
4925 * 0b100111..Divide by 40
4926 * 0b101000..Divide by 41
4927 * 0b101001..Divide by 42
4928 * 0b101010..Divide by 43
4929 * 0b101011..Divide by 44
4930 * 0b101100..Divide by 45
4931 * 0b101101..Divide by 46
4932 * 0b101110..Divide by 47
4933 * 0b101111..Divide by 48
4934 * 0b110000..Divide by 49
4935 * 0b110001..Divide by 50
4936 * 0b110010..Divide by 51
4937 * 0b110011..Divide by 52
4938 * 0b110100..Divide by 53
4939 * 0b110101..Divide by 54
4940 * 0b110110..Divide by 55
4941 * 0b110111..Divide by 56
4942 * 0b111000..Divide by 57
4943 * 0b111001..Divide by 58
4944 * 0b111010..Divide by 59
4945 * 0b111011..Divide by 60
4946 * 0b111100..Divide by 61
4947 * 0b111101..Divide by 62
4948 * 0b111110..Divide by 63
4949 * 0b111111..Divide by 64
4950 */
4951#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
4952/*! @} */
4953
4954/*! @name CDHIPR - CCM Divider Handshake In-Process Register */
4955/*! @{ */
4956#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)
4957#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)
4958/*! SEMC_PODF_BUSY
4959 * 0b0..divider is not busy and its value represents the actual division.
4960 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
4961 * value of the division factor, and after the handshake the written value of the semc_podf will be applied.
4962 */
4963#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
4964#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
4965#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
4966/*! AHB_PODF_BUSY
4967 * 0b0..divider is not busy and its value represents the actual division.
4968 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
4969 * value of the division factor, and after the handshake the written value of the ahb_podf will be applied.
4970 */
4971#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
4972#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)
4973#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)
4974/*! PERIPH2_CLK_SEL_BUSY
4975 * 0b0..mux is not busy and its value represents the actual division.
4976 * 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the
4977 * previous value of select, and after the handshake periph2_clk_sel value will be applied.
4978 */
4979#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
4980#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
4981#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
4982/*! PERIPH_CLK_SEL_BUSY
4983 * 0b0..mux is not busy and its value represents the actual division.
4984 * 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the
4985 * previous value of select, and after the handshake periph_clk_sel value will be applied.
4986 */
4987#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
4988#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)
4989#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)
4990/*! ARM_PODF_BUSY
4991 * 0b0..divider is not busy and its value represents the actual division.
4992 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
4993 * value of the division factor, and after the handshake the written value of the arm_podf will be applied.
4994 */
4995#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
4996/*! @} */
4997
4998/*! @name CLPCR - CCM Low Power Control Register */
4999/*! @{ */
5000#define CCM_CLPCR_LPM_MASK (0x3U)
5001#define CCM_CLPCR_LPM_SHIFT (0U)
5002/*! LPM
5003 * 0b00..Remain in run mode
5004 * 0b01..Transfer to wait mode
5005 * 0b10..Transfer to stop mode
5006 * 0b11..Reserved
5007 */
5008#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
5009#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
5010#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
5011/*! ARM_CLK_DIS_ON_LPM
5012 * 0b0..Arm clock enabled on wait mode.
5013 * 0b1..Arm clock disabled on wait mode. .
5014 */
5015#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
5016#define CCM_CLPCR_SBYOS_MASK (0x40U)
5017#define CCM_CLPCR_SBYOS_SHIFT (6U)
5018/*! SBYOS
5019 * 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain
5020 * asserted - '0' and cosc_pwrdown will remain de asserted - '0')
5021 * 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be
5022 * deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will
5023 * be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will
5024 * continue with the exit from the STOP mode process.
5025 */
5026#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
5027#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
5028#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
5029/*! DIS_REF_OSC
5030 * 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.
5031 * 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'
5032 */
5033#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
5034#define CCM_CLPCR_VSTBY_MASK (0x100U)
5035#define CCM_CLPCR_VSTBY_SHIFT (8U)
5036/*! VSTBY
5037 * 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')
5038 * 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').
5039 */
5040#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
5041#define CCM_CLPCR_STBY_COUNT_MASK (0x600U)
5042#define CCM_CLPCR_STBY_COUNT_SHIFT (9U)
5043/*! STBY_COUNT
5044 * 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles
5045 * 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles
5046 * 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles
5047 * 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles
5048 */
5049#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
5050#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
5051#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
5052/*! COSC_PWRDOWN
5053 * 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.
5054 * 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.
5055 */
5056#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
5057#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)
5058#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)
5059#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
5060#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)
5061#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)
5062#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
5063#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
5064#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
5065/*! MASK_CORE0_WFI
5066 * 0b0..WFI of core0 is not masked
5067 * 0b1..WFI of core0 is masked
5068 */
5069#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
5070#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
5071#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
5072/*! MASK_SCU_IDLE
5073 * 0b1..SCU IDLE is masked
5074 * 0b0..SCU IDLE is not masked
5075 */
5076#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
5077#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
5078#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
5079/*! MASK_L2CC_IDLE
5080 * 0b1..L2CC IDLE is masked
5081 * 0b0..L2CC IDLE is not masked
5082 */
5083#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
5084/*! @} */
5085
5086/*! @name CISR - CCM Interrupt Status Register */
5087/*! @{ */
5088#define CCM_CISR_LRF_PLL_MASK (0x1U)
5089#define CCM_CISR_LRF_PLL_SHIFT (0U)
5090/*! LRF_PLL
5091 * 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs
5092 * 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs
5093 */
5094#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
5095#define CCM_CISR_COSC_READY_MASK (0x40U)
5096#define CCM_CISR_COSC_READY_SHIFT (6U)
5097/*! COSC_READY
5098 * 0b0..interrupt is not generated due to on board oscillator ready
5099 * 0b1..interrupt generated due to on board oscillator ready
5100 */
5101#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
5102#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)
5103#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)
5104/*! SEMC_PODF_LOADED
5105 * 0b0..interrupt is not generated due to frequency change of semc_podf
5106 * 0b1..interrupt generated due to frequency change of semc_podf
5107 */
5108#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
5109#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
5110#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
5111/*! PERIPH2_CLK_SEL_LOADED
5112 * 0b0..interrupt is not generated due to frequency change of periph2_clk_sel
5113 * 0b1..interrupt generated due to frequency change of periph2_clk_sel
5114 */
5115#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
5116#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
5117#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
5118/*! AHB_PODF_LOADED
5119 * 0b0..interrupt is not generated due to frequency change of ahb_podf
5120 * 0b1..interrupt generated due to frequency change of ahb_podf
5121 */
5122#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
5123#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
5124#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
5125/*! PERIPH_CLK_SEL_LOADED
5126 * 0b0..interrupt is not generated due to update of periph_clk_sel.
5127 * 0b1..interrupt generated due to update of periph_clk_sel.
5128 */
5129#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
5130#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)
5131#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)
5132/*! ARM_PODF_LOADED
5133 * 0b0..interrupt is not generated due to frequency change of arm_podf
5134 * 0b1..interrupt generated due to frequency change of arm_podf
5135 */
5136#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
5137/*! @} */
5138
5139/*! @name CIMR - CCM Interrupt Mask Register */
5140/*! @{ */
5141#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
5142#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
5143/*! MASK_LRF_PLL
5144 * 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created
5145 * 0b1..mask interrupt due to lrf of PLLs
5146 */
5147#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
5148#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
5149#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
5150/*! MASK_COSC_READY
5151 * 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created
5152 * 0b1..mask interrupt due to on board oscillator ready
5153 */
5154#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
5155#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)
5156#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)
5157/*! MASK_SEMC_PODF_LOADED
5158 * 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created
5159 * 0b1..mask interrupt due to frequency change of semc_podf
5160 */
5161#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
5162#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
5163#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
5164/*! MASK_PERIPH2_CLK_SEL_LOADED
5165 * 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created
5166 * 0b1..mask interrupt due to update of periph2_clk_sel
5167 */
5168#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
5169#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
5170#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
5171/*! MASK_AHB_PODF_LOADED
5172 * 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created
5173 * 0b1..mask interrupt due to frequency change of ahb_podf
5174 */
5175#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
5176#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
5177#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
5178/*! MASK_PERIPH_CLK_SEL_LOADED
5179 * 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created
5180 * 0b1..mask interrupt due to update of periph_clk_sel
5181 */
5182#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
5183#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)
5184#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)
5185/*! ARM_PODF_LOADED
5186 * 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created
5187 * 0b1..mask interrupt due to frequency change of arm_podf
5188 */
5189#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
5190/*! @} */
5191
5192/*! @name CCOSR - CCM Clock Output Source Register */
5193/*! @{ */
5194#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
5195#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
5196/*! CLKO1_SEL
5197 * 0b0000..pll3_sw_clk (divided by 2)
5198 * 0b0001..PLL2 (divided by 2)
5199 * 0b0010..ENET PLL (divided by 2)
5200 * 0b0011..Reserved
5201 * 0b0101..semc_clk_root
5202 * 0b0110..Reserved
5203 * 0b1010..Reserved
5204 * 0b1011..ahb_clk_root
5205 * 0b1100..ipg_clk_root
5206 * 0b1101..perclk_root
5207 * 0b1110..Reserved
5208 * 0b1111..pll4_main_clk
5209 */
5210#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
5211#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
5212#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
5213/*! CLKO1_DIV
5214 * 0b000..divide by 1
5215 * 0b001..divide by 2
5216 * 0b010..divide by 3
5217 * 0b011..divide by 4
5218 * 0b100..divide by 5
5219 * 0b101..divide by 6
5220 * 0b110..divide by 7
5221 * 0b111..divide by 8
5222 */
5223#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
5224#define CCM_CCOSR_CLKO1_EN_MASK (0x80U)
5225#define CCM_CCOSR_CLKO1_EN_SHIFT (7U)
5226/*! CLKO1_EN
5227 * 0b0..CCM_CLKO1 disabled.
5228 * 0b1..CCM_CLKO1 enabled.
5229 */
5230#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
5231#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
5232#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
5233/*! CLK_OUT_SEL
5234 * 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock
5235 * 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock
5236 */
5237#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
5238#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
5239#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
5240/*! CLKO2_SEL
5241 * 0b00011..usdhc1_clk_root
5242 * 0b00101..Reserved
5243 * 0b00110..lpi2c_clk_root
5244 * 0b01110..osc_clk
5245 * 0b10000..lpspi_clk_root
5246 * 0b10001..usdhc2_clk_root
5247 * 0b10010..sai1_clk_root
5248 * 0b10011..sai2_clk_root
5249 * 0b10100..sai3_clk_root
5250 * 0b10110..trace_clk_root
5251 * 0b10111..can_clk_root
5252 * 0b11011..flexspi_clk_root
5253 * 0b11100..uart_clk_root
5254 * 0b11101..spdif0_clk_root
5255 * 0b11111..Reserved
5256 */
5257#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
5258#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
5259#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
5260/*! CLKO2_DIV
5261 * 0b000..divide by 1
5262 * 0b001..divide by 2
5263 * 0b010..divide by 3
5264 * 0b011..divide by 4
5265 * 0b100..divide by 5
5266 * 0b101..divide by 6
5267 * 0b110..divide by 7
5268 * 0b111..divide by 8
5269 */
5270#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
5271#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
5272#define CCM_CCOSR_CLKO2_EN_SHIFT (24U)
5273/*! CLKO2_EN
5274 * 0b0..CCM_CLKO2 disabled.
5275 * 0b1..CCM_CLKO2 enabled.
5276 */
5277#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
5278/*! @} */
5279
5280/*! @name CGPR - CCM General Purpose Register */
5281/*! @{ */
5282#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
5283#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
5284/*! PMIC_DELAY_SCALER
5285 * 0b0..clock is not divided
5286 * 0b1..clock is divided /8
5287 */
5288#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
5289#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
5290#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
5291/*! EFUSE_PROG_SUPPLY_GATE
5292 * 0b0..fuse programing supply voltage is gated off to the efuse module
5293 * 0b1..allow fuse programing.
5294 */
5295#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
5296#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
5297#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
5298/*! SYS_MEM_DS_CTRL
5299 * 0b00..Disable memory DS mode always
5300 * 0b01..Enable memory (outside Arm platform) DS mode when system STOP and PLL are disabled
5301 * 0b1x..enable memory (outside Arm platform) DS mode when system is in STOP mode
5302 */
5303#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
5304#define CCM_CGPR_FPL_MASK (0x10000U)
5305#define CCM_CGPR_FPL_SHIFT (16U)
5306/*! FPL - Fast PLL enable.
5307 * 0b0..Engage PLL enable default way.
5308 * 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.
5309 */
5310#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
5311#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
5312#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
5313/*! INT_MEM_CLK_LPM
5314 * 0b0..Disable the clock to the Arm platform memories when entering Low Power Mode
5315 * 0b1..Keep the clocks to the Arm platform memories enabled only if an interrupt is pending when entering Low
5316 * Power Modes (WAIT and STOP without power gating)
5317 */
5318#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
5319/*! @} */
5320
5321/*! @name CCGR0 - CCM Clock Gating Register 0 */
5322/*! @{ */
5323#define CCM_CCGR0_CG0_MASK (0x3U)
5324#define CCM_CCGR0_CG0_SHIFT (0U)
5325#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
5326#define CCM_CCGR0_CG1_MASK (0xCU)
5327#define CCM_CCGR0_CG1_SHIFT (2U)
5328#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
5329#define CCM_CCGR0_CG2_MASK (0x30U)
5330#define CCM_CCGR0_CG2_SHIFT (4U)
5331#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
5332#define CCM_CCGR0_CG3_MASK (0xC0U)
5333#define CCM_CCGR0_CG3_SHIFT (6U)
5334#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
5335#define CCM_CCGR0_CG4_MASK (0x300U)
5336#define CCM_CCGR0_CG4_SHIFT (8U)
5337#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
5338#define CCM_CCGR0_CG5_MASK (0xC00U)
5339#define CCM_CCGR0_CG5_SHIFT (10U)
5340#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
5341#define CCM_CCGR0_CG6_MASK (0x3000U)
5342#define CCM_CCGR0_CG6_SHIFT (12U)
5343#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
5344#define CCM_CCGR0_CG7_MASK (0xC000U)
5345#define CCM_CCGR0_CG7_SHIFT (14U)
5346#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
5347#define CCM_CCGR0_CG8_MASK (0x30000U)
5348#define CCM_CCGR0_CG8_SHIFT (16U)
5349#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
5350#define CCM_CCGR0_CG9_MASK (0xC0000U)
5351#define CCM_CCGR0_CG9_SHIFT (18U)
5352#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
5353#define CCM_CCGR0_CG10_MASK (0x300000U)
5354#define CCM_CCGR0_CG10_SHIFT (20U)
5355#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
5356#define CCM_CCGR0_CG11_MASK (0xC00000U)
5357#define CCM_CCGR0_CG11_SHIFT (22U)
5358#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
5359#define CCM_CCGR0_CG12_MASK (0x3000000U)
5360#define CCM_CCGR0_CG12_SHIFT (24U)
5361#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
5362#define CCM_CCGR0_CG13_MASK (0xC000000U)
5363#define CCM_CCGR0_CG13_SHIFT (26U)
5364#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
5365#define CCM_CCGR0_CG14_MASK (0x30000000U)
5366#define CCM_CCGR0_CG14_SHIFT (28U)
5367#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
5368#define CCM_CCGR0_CG15_MASK (0xC0000000U)
5369#define CCM_CCGR0_CG15_SHIFT (30U)
5370#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
5371/*! @} */
5372
5373/*! @name CCGR1 - CCM Clock Gating Register 1 */
5374/*! @{ */
5375#define CCM_CCGR1_CG0_MASK (0x3U)
5376#define CCM_CCGR1_CG0_SHIFT (0U)
5377#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
5378#define CCM_CCGR1_CG1_MASK (0xCU)
5379#define CCM_CCGR1_CG1_SHIFT (2U)
5380#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
5381#define CCM_CCGR1_CG2_MASK (0x30U)
5382#define CCM_CCGR1_CG2_SHIFT (4U)
5383#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
5384#define CCM_CCGR1_CG3_MASK (0xC0U)
5385#define CCM_CCGR1_CG3_SHIFT (6U)
5386#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
5387#define CCM_CCGR1_CG4_MASK (0x300U)
5388#define CCM_CCGR1_CG4_SHIFT (8U)
5389#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
5390#define CCM_CCGR1_CG5_MASK (0xC00U)
5391#define CCM_CCGR1_CG5_SHIFT (10U)
5392#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
5393#define CCM_CCGR1_CG6_MASK (0x3000U)
5394#define CCM_CCGR1_CG6_SHIFT (12U)
5395#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
5396#define CCM_CCGR1_CG7_MASK (0xC000U)
5397#define CCM_CCGR1_CG7_SHIFT (14U)
5398#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
5399#define CCM_CCGR1_CG8_MASK (0x30000U)
5400#define CCM_CCGR1_CG8_SHIFT (16U)
5401#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
5402#define CCM_CCGR1_CG9_MASK (0xC0000U)
5403#define CCM_CCGR1_CG9_SHIFT (18U)
5404#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
5405#define CCM_CCGR1_CG10_MASK (0x300000U)
5406#define CCM_CCGR1_CG10_SHIFT (20U)
5407#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
5408#define CCM_CCGR1_CG11_MASK (0xC00000U)
5409#define CCM_CCGR1_CG11_SHIFT (22U)
5410#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
5411#define CCM_CCGR1_CG12_MASK (0x3000000U)
5412#define CCM_CCGR1_CG12_SHIFT (24U)
5413#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
5414#define CCM_CCGR1_CG13_MASK (0xC000000U)
5415#define CCM_CCGR1_CG13_SHIFT (26U)
5416#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
5417#define CCM_CCGR1_CG14_MASK (0x30000000U)
5418#define CCM_CCGR1_CG14_SHIFT (28U)
5419#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
5420#define CCM_CCGR1_CG15_MASK (0xC0000000U)
5421#define CCM_CCGR1_CG15_SHIFT (30U)
5422#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
5423/*! @} */
5424
5425/*! @name CCGR2 - CCM Clock Gating Register 2 */
5426/*! @{ */
5427#define CCM_CCGR2_CG0_MASK (0x3U)
5428#define CCM_CCGR2_CG0_SHIFT (0U)
5429#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
5430#define CCM_CCGR2_CG1_MASK (0xCU)
5431#define CCM_CCGR2_CG1_SHIFT (2U)
5432#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
5433#define CCM_CCGR2_CG2_MASK (0x30U)
5434#define CCM_CCGR2_CG2_SHIFT (4U)
5435#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
5436#define CCM_CCGR2_CG3_MASK (0xC0U)
5437#define CCM_CCGR2_CG3_SHIFT (6U)
5438#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
5439#define CCM_CCGR2_CG4_MASK (0x300U)
5440#define CCM_CCGR2_CG4_SHIFT (8U)
5441#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
5442#define CCM_CCGR2_CG5_MASK (0xC00U)
5443#define CCM_CCGR2_CG5_SHIFT (10U)
5444#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
5445#define CCM_CCGR2_CG6_MASK (0x3000U)
5446#define CCM_CCGR2_CG6_SHIFT (12U)
5447#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
5448#define CCM_CCGR2_CG7_MASK (0xC000U)
5449#define CCM_CCGR2_CG7_SHIFT (14U)
5450#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
5451#define CCM_CCGR2_CG8_MASK (0x30000U)
5452#define CCM_CCGR2_CG8_SHIFT (16U)
5453#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
5454#define CCM_CCGR2_CG9_MASK (0xC0000U)
5455#define CCM_CCGR2_CG9_SHIFT (18U)
5456#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
5457#define CCM_CCGR2_CG10_MASK (0x300000U)
5458#define CCM_CCGR2_CG10_SHIFT (20U)
5459#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
5460#define CCM_CCGR2_CG11_MASK (0xC00000U)
5461#define CCM_CCGR2_CG11_SHIFT (22U)
5462#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
5463#define CCM_CCGR2_CG12_MASK (0x3000000U)
5464#define CCM_CCGR2_CG12_SHIFT (24U)
5465#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
5466#define CCM_CCGR2_CG13_MASK (0xC000000U)
5467#define CCM_CCGR2_CG13_SHIFT (26U)
5468#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
5469#define CCM_CCGR2_CG14_MASK (0x30000000U)
5470#define CCM_CCGR2_CG14_SHIFT (28U)
5471#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
5472#define CCM_CCGR2_CG15_MASK (0xC0000000U)
5473#define CCM_CCGR2_CG15_SHIFT (30U)
5474#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
5475/*! @} */
5476
5477/*! @name CCGR3 - CCM Clock Gating Register 3 */
5478/*! @{ */
5479#define CCM_CCGR3_CG0_MASK (0x3U)
5480#define CCM_CCGR3_CG0_SHIFT (0U)
5481#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
5482#define CCM_CCGR3_CG1_MASK (0xCU)
5483#define CCM_CCGR3_CG1_SHIFT (2U)
5484#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
5485#define CCM_CCGR3_CG2_MASK (0x30U)
5486#define CCM_CCGR3_CG2_SHIFT (4U)
5487#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
5488#define CCM_CCGR3_CG3_MASK (0xC0U)
5489#define CCM_CCGR3_CG3_SHIFT (6U)
5490#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
5491#define CCM_CCGR3_CG4_MASK (0x300U)
5492#define CCM_CCGR3_CG4_SHIFT (8U)
5493#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
5494#define CCM_CCGR3_CG5_MASK (0xC00U)
5495#define CCM_CCGR3_CG5_SHIFT (10U)
5496#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
5497#define CCM_CCGR3_CG6_MASK (0x3000U)
5498#define CCM_CCGR3_CG6_SHIFT (12U)
5499#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
5500#define CCM_CCGR3_CG7_MASK (0xC000U)
5501#define CCM_CCGR3_CG7_SHIFT (14U)
5502#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
5503#define CCM_CCGR3_CG8_MASK (0x30000U)
5504#define CCM_CCGR3_CG8_SHIFT (16U)
5505#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
5506#define CCM_CCGR3_CG9_MASK (0xC0000U)
5507#define CCM_CCGR3_CG9_SHIFT (18U)
5508#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
5509#define CCM_CCGR3_CG10_MASK (0x300000U)
5510#define CCM_CCGR3_CG10_SHIFT (20U)
5511#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
5512#define CCM_CCGR3_CG11_MASK (0xC00000U)
5513#define CCM_CCGR3_CG11_SHIFT (22U)
5514#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
5515#define CCM_CCGR3_CG12_MASK (0x3000000U)
5516#define CCM_CCGR3_CG12_SHIFT (24U)
5517#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
5518#define CCM_CCGR3_CG13_MASK (0xC000000U)
5519#define CCM_CCGR3_CG13_SHIFT (26U)
5520#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
5521#define CCM_CCGR3_CG14_MASK (0x30000000U)
5522#define CCM_CCGR3_CG14_SHIFT (28U)
5523/*! CG14 - The OCRAM clock cannot be turned off when the CM cache is running on this device.
5524 */
5525#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
5526#define CCM_CCGR3_CG15_MASK (0xC0000000U)
5527#define CCM_CCGR3_CG15_SHIFT (30U)
5528#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
5529/*! @} */
5530
5531/*! @name CCGR4 - CCM Clock Gating Register 4 */
5532/*! @{ */
5533#define CCM_CCGR4_CG0_MASK (0x3U)
5534#define CCM_CCGR4_CG0_SHIFT (0U)
5535#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
5536#define CCM_CCGR4_CG1_MASK (0xCU)
5537#define CCM_CCGR4_CG1_SHIFT (2U)
5538#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
5539#define CCM_CCGR4_CG2_MASK (0x30U)
5540#define CCM_CCGR4_CG2_SHIFT (4U)
5541#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
5542#define CCM_CCGR4_CG3_MASK (0xC0U)
5543#define CCM_CCGR4_CG3_SHIFT (6U)
5544#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
5545#define CCM_CCGR4_CG4_MASK (0x300U)
5546#define CCM_CCGR4_CG4_SHIFT (8U)
5547#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
5548#define CCM_CCGR4_CG5_MASK (0xC00U)
5549#define CCM_CCGR4_CG5_SHIFT (10U)
5550#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
5551#define CCM_CCGR4_CG6_MASK (0x3000U)
5552#define CCM_CCGR4_CG6_SHIFT (12U)
5553#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
5554#define CCM_CCGR4_CG7_MASK (0xC000U)
5555#define CCM_CCGR4_CG7_SHIFT (14U)
5556#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
5557#define CCM_CCGR4_CG8_MASK (0x30000U)
5558#define CCM_CCGR4_CG8_SHIFT (16U)
5559#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
5560#define CCM_CCGR4_CG9_MASK (0xC0000U)
5561#define CCM_CCGR4_CG9_SHIFT (18U)
5562#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
5563#define CCM_CCGR4_CG10_MASK (0x300000U)
5564#define CCM_CCGR4_CG10_SHIFT (20U)
5565#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
5566#define CCM_CCGR4_CG11_MASK (0xC00000U)
5567#define CCM_CCGR4_CG11_SHIFT (22U)
5568#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
5569#define CCM_CCGR4_CG12_MASK (0x3000000U)
5570#define CCM_CCGR4_CG12_SHIFT (24U)
5571#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
5572#define CCM_CCGR4_CG13_MASK (0xC000000U)
5573#define CCM_CCGR4_CG13_SHIFT (26U)
5574#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
5575#define CCM_CCGR4_CG14_MASK (0x30000000U)
5576#define CCM_CCGR4_CG14_SHIFT (28U)
5577#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
5578#define CCM_CCGR4_CG15_MASK (0xC0000000U)
5579#define CCM_CCGR4_CG15_SHIFT (30U)
5580#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
5581/*! @} */
5582
5583/*! @name CCGR5 - CCM Clock Gating Register 5 */
5584/*! @{ */
5585#define CCM_CCGR5_CG0_MASK (0x3U)
5586#define CCM_CCGR5_CG0_SHIFT (0U)
5587#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
5588#define CCM_CCGR5_CG1_MASK (0xCU)
5589#define CCM_CCGR5_CG1_SHIFT (2U)
5590#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
5591#define CCM_CCGR5_CG2_MASK (0x30U)
5592#define CCM_CCGR5_CG2_SHIFT (4U)
5593#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
5594#define CCM_CCGR5_CG3_MASK (0xC0U)
5595#define CCM_CCGR5_CG3_SHIFT (6U)
5596#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
5597#define CCM_CCGR5_CG4_MASK (0x300U)
5598#define CCM_CCGR5_CG4_SHIFT (8U)
5599#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
5600#define CCM_CCGR5_CG5_MASK (0xC00U)
5601#define CCM_CCGR5_CG5_SHIFT (10U)
5602#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
5603#define CCM_CCGR5_CG6_MASK (0x3000U)
5604#define CCM_CCGR5_CG6_SHIFT (12U)
5605#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
5606#define CCM_CCGR5_CG7_MASK (0xC000U)
5607#define CCM_CCGR5_CG7_SHIFT (14U)
5608#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
5609#define CCM_CCGR5_CG8_MASK (0x30000U)
5610#define CCM_CCGR5_CG8_SHIFT (16U)
5611#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
5612#define CCM_CCGR5_CG9_MASK (0xC0000U)
5613#define CCM_CCGR5_CG9_SHIFT (18U)
5614#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
5615#define CCM_CCGR5_CG10_MASK (0x300000U)
5616#define CCM_CCGR5_CG10_SHIFT (20U)
5617#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
5618#define CCM_CCGR5_CG11_MASK (0xC00000U)
5619#define CCM_CCGR5_CG11_SHIFT (22U)
5620#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
5621#define CCM_CCGR5_CG12_MASK (0x3000000U)
5622#define CCM_CCGR5_CG12_SHIFT (24U)
5623#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
5624#define CCM_CCGR5_CG13_MASK (0xC000000U)
5625#define CCM_CCGR5_CG13_SHIFT (26U)
5626#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
5627#define CCM_CCGR5_CG14_MASK (0x30000000U)
5628#define CCM_CCGR5_CG14_SHIFT (28U)
5629#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
5630#define CCM_CCGR5_CG15_MASK (0xC0000000U)
5631#define CCM_CCGR5_CG15_SHIFT (30U)
5632#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
5633/*! @} */
5634
5635/*! @name CCGR6 - CCM Clock Gating Register 6 */
5636/*! @{ */
5637#define CCM_CCGR6_CG0_MASK (0x3U)
5638#define CCM_CCGR6_CG0_SHIFT (0U)
5639#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
5640#define CCM_CCGR6_CG1_MASK (0xCU)
5641#define CCM_CCGR6_CG1_SHIFT (2U)
5642#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
5643#define CCM_CCGR6_CG2_MASK (0x30U)
5644#define CCM_CCGR6_CG2_SHIFT (4U)
5645#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
5646#define CCM_CCGR6_CG3_MASK (0xC0U)
5647#define CCM_CCGR6_CG3_SHIFT (6U)
5648#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
5649#define CCM_CCGR6_CG4_MASK (0x300U)
5650#define CCM_CCGR6_CG4_SHIFT (8U)
5651#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
5652#define CCM_CCGR6_CG5_MASK (0xC00U)
5653#define CCM_CCGR6_CG5_SHIFT (10U)
5654#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
5655#define CCM_CCGR6_CG6_MASK (0x3000U)
5656#define CCM_CCGR6_CG6_SHIFT (12U)
5657#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
5658#define CCM_CCGR6_CG7_MASK (0xC000U)
5659#define CCM_CCGR6_CG7_SHIFT (14U)
5660#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
5661#define CCM_CCGR6_CG8_MASK (0x30000U)
5662#define CCM_CCGR6_CG8_SHIFT (16U)
5663#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
5664#define CCM_CCGR6_CG9_MASK (0xC0000U)
5665#define CCM_CCGR6_CG9_SHIFT (18U)
5666#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
5667#define CCM_CCGR6_CG10_MASK (0x300000U)
5668#define CCM_CCGR6_CG10_SHIFT (20U)
5669#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
5670#define CCM_CCGR6_CG11_MASK (0xC00000U)
5671#define CCM_CCGR6_CG11_SHIFT (22U)
5672#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
5673#define CCM_CCGR6_CG12_MASK (0x3000000U)
5674#define CCM_CCGR6_CG12_SHIFT (24U)
5675#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
5676#define CCM_CCGR6_CG13_MASK (0xC000000U)
5677#define CCM_CCGR6_CG13_SHIFT (26U)
5678#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
5679#define CCM_CCGR6_CG14_MASK (0x30000000U)
5680#define CCM_CCGR6_CG14_SHIFT (28U)
5681#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
5682#define CCM_CCGR6_CG15_MASK (0xC0000000U)
5683#define CCM_CCGR6_CG15_SHIFT (30U)
5684#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
5685/*! @} */
5686
5687/*! @name CMEOR - CCM Module Enable Overide Register */
5688/*! @{ */
5689#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
5690#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
5691/*! MOD_EN_OV_GPT
5692 * 0b0..don't override module enable signal
5693 * 0b1..override module enable signal
5694 */
5695#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
5696#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
5697#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
5698/*! MOD_EN_OV_PIT
5699 * 0b0..don't override module enable signal
5700 * 0b1..override module enable signal
5701 */
5702#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
5703#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)
5704#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)
5705/*! MOD_EN_USDHC
5706 * 0b0..don't override module enable signal
5707 * 0b1..override module enable signal
5708 */
5709#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
5710#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
5711#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
5712/*! MOD_EN_OV_TRNG
5713 * 0b0..don't override module enable signal
5714 * 0b1..override module enable signal
5715 */
5716#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
5717#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)
5718#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)
5719/*! MOD_EN_OV_CAN2_CPI
5720 * 0b0..don't override module enable signal
5721 * 0b1..override module enable signal
5722 */
5723#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
5724#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)
5725#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)
5726/*! MOD_EN_OV_CAN1_CPI
5727 * 0b0..don't overide module enable signal
5728 * 0b1..overide module enable signal
5729 */
5730#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)
5731/*! @} */
5732
5733
5734/*!
5735 * @}
5736 */ /* end of group CCM_Register_Masks */
5737
5738
5739/* CCM - Peripheral instance base addresses */
5740/** Peripheral CCM base address */
5741#define CCM_BASE (0x400FC000u)
5742/** Peripheral CCM base pointer */
5743#define CCM ((CCM_Type *)CCM_BASE)
5744/** Array initializer of CCM peripheral base addresses */
5745#define CCM_BASE_ADDRS { CCM_BASE }
5746/** Array initializer of CCM peripheral base pointers */
5747#define CCM_BASE_PTRS { CCM }
5748/** Interrupt vectors for the CCM peripheral type */
5749#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }
5750
5751/*!
5752 * @}
5753 */ /* end of group CCM_Peripheral_Access_Layer */
5754
5755
5756/* ----------------------------------------------------------------------------
5757 -- CCM_ANALOG Peripheral Access Layer
5758 ---------------------------------------------------------------------------- */
5759
5760/*!
5761 * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
5762 * @{
5763 */
5764
5765/** CCM_ANALOG - Register Layout Typedef */
5766typedef struct {
5767 uint8_t RESERVED_0[16];
5768 __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */
5769 __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */
5770 __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */
5771 __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */
5772 uint8_t RESERVED_1[16];
5773 __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */
5774 __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */
5775 __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */
5776 __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */
5777 __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */
5778 uint8_t RESERVED_2[12];
5779 __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */
5780 uint8_t RESERVED_3[12];
5781 __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */
5782 uint8_t RESERVED_4[12];
5783 __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */
5784 __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */
5785 __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */
5786 __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */
5787 __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */
5788 uint8_t RESERVED_5[12];
5789 __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */
5790 uint8_t RESERVED_6[76];
5791 __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */
5792 __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */
5793 __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */
5794 __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */
5795 __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */
5796 __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */
5797 __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */
5798 __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */
5799 __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */
5800 __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */
5801 __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */
5802 __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */
5803 uint8_t RESERVED_7[64];
5804 __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */
5805 __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */
5806 __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */
5807 __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */
5808 __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */
5809 __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */
5810 __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */
5811 __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */
5812 __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */
5813 __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */
5814 __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */
5815 __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */
5816} CCM_ANALOG_Type;
5817
5818/* ----------------------------------------------------------------------------
5819 -- CCM_ANALOG Register Masks
5820 ---------------------------------------------------------------------------- */
5821
5822/*!
5823 * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
5824 * @{
5825 */
5826
5827/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */
5828/*! @{ */
5829#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)
5830#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)
5831#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
5832#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)
5833#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)
5834/*! EN_USB_CLKS
5835 * 0b0..PLL outputs for USBPHYn off.
5836 * 0b1..PLL outputs for USBPHYn on.
5837 */
5838#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
5839#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)
5840#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)
5841#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
5842#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)
5843#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)
5844#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
5845#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)
5846#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
5847/*! BYPASS_CLK_SRC
5848 * 0b00..Select the 24MHz oscillator as source.
5849 */
5850#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
5851#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)
5852#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)
5853#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
5854#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)
5855#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)
5856#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
5857/*! @} */
5858
5859/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */
5860/*! @{ */
5861#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)
5862#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
5863#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
5864#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
5865#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
5866/*! EN_USB_CLKS
5867 * 0b0..PLL outputs for USBPHYn off.
5868 * 0b1..PLL outputs for USBPHYn on.
5869 */
5870#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
5871#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)
5872#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)
5873#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
5874#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)
5875#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)
5876#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
5877#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
5878#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
5879/*! BYPASS_CLK_SRC
5880 * 0b00..Select the 24MHz oscillator as source.
5881 */
5882#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
5883#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)
5884#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)
5885#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
5886#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)
5887#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)
5888#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
5889/*! @} */
5890
5891/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */
5892/*! @{ */
5893#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)
5894#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
5895#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
5896#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
5897#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
5898/*! EN_USB_CLKS
5899 * 0b0..PLL outputs for USBPHYn off.
5900 * 0b1..PLL outputs for USBPHYn on.
5901 */
5902#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
5903#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)
5904#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)
5905#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
5906#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)
5907#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)
5908#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
5909#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
5910#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
5911/*! BYPASS_CLK_SRC
5912 * 0b00..Select the 24MHz oscillator as source.
5913 */
5914#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
5915#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)
5916#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)
5917#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
5918#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)
5919#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)
5920#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
5921/*! @} */
5922
5923/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */
5924/*! @{ */
5925#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)
5926#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
5927#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
5928#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
5929#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
5930/*! EN_USB_CLKS
5931 * 0b0..PLL outputs for USBPHYn off.
5932 * 0b1..PLL outputs for USBPHYn on.
5933 */
5934#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
5935#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)
5936#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)
5937#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
5938#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)
5939#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)
5940#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
5941#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
5942#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
5943/*! BYPASS_CLK_SRC
5944 * 0b00..Select the 24MHz oscillator as source.
5945 */
5946#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
5947#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)
5948#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)
5949#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
5950#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)
5951#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)
5952#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
5953/*! @} */
5954
5955/*! @name PLL_SYS - Analog System PLL Control Register */
5956/*! @{ */
5957#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)
5958#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)
5959#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
5960#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)
5961#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)
5962#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
5963#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)
5964#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)
5965#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
5966#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)
5967#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)
5968/*! BYPASS_CLK_SRC
5969 * 0b00..Select the 24MHz oscillator as source.
5970 */
5971#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
5972#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)
5973#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)
5974#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
5975#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)
5976#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)
5977#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
5978/*! @} */
5979
5980/*! @name PLL_SYS_SET - Analog System PLL Control Register */
5981/*! @{ */
5982#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)
5983#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)
5984#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
5985#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)
5986#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)
5987#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
5988#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)
5989#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)
5990#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
5991#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
5992#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
5993/*! BYPASS_CLK_SRC
5994 * 0b00..Select the 24MHz oscillator as source.
5995 */
5996#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
5997#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)
5998#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)
5999#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
6000#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)
6001#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)
6002#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
6003/*! @} */
6004
6005/*! @name PLL_SYS_CLR - Analog System PLL Control Register */
6006/*! @{ */
6007#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)
6008#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)
6009#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
6010#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)
6011#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)
6012#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
6013#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)
6014#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)
6015#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
6016#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
6017#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
6018/*! BYPASS_CLK_SRC
6019 * 0b00..Select the 24MHz oscillator as source.
6020 */
6021#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
6022#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)
6023#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)
6024#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
6025#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)
6026#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)
6027#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
6028/*! @} */
6029
6030/*! @name PLL_SYS_TOG - Analog System PLL Control Register */
6031/*! @{ */
6032#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)
6033#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)
6034#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
6035#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)
6036#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)
6037#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
6038#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)
6039#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)
6040#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
6041#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
6042#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
6043/*! BYPASS_CLK_SRC
6044 * 0b00..Select the 24MHz oscillator as source.
6045 */
6046#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
6047#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)
6048#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)
6049#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
6050#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)
6051#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)
6052#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
6053/*! @} */
6054
6055/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */
6056/*! @{ */
6057#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)
6058#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)
6059#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
6060#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)
6061#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)
6062/*! ENABLE - Enable bit
6063 * 0b0..Spread spectrum modulation disabled
6064 * 0b1..Soread spectrum modulation enabled
6065 */
6066#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
6067#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)
6068#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)
6069#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
6070/*! @} */
6071
6072/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */
6073/*! @{ */
6074#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)
6075#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)
6076#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
6077/*! @} */
6078
6079/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */
6080/*! @{ */
6081#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)
6082#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)
6083#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
6084/*! @} */
6085
6086/*! @name PLL_AUDIO - Analog Audio PLL control Register */
6087/*! @{ */
6088#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
6089#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
6090#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
6091#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)
6092#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)
6093#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
6094#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)
6095#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)
6096#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
6097#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
6098#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
6099/*! BYPASS_CLK_SRC
6100 * 0b00..Select the 24MHz oscillator as source.
6101 * 0b10..Reserved1
6102 * 0b11..Reserved2
6103 */
6104#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
6105#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)
6106#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)
6107#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
6108#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
6109#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
6110/*! POST_DIV_SELECT
6111 * 0b00..Divide by 4.
6112 * 0b01..Divide by 2.
6113 * 0b10..Divide by 1.
6114 * 0b11..Reserved
6115 */
6116#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
6117#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)
6118#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)
6119#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
6120/*! @} */
6121
6122/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */
6123/*! @{ */
6124#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
6125#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
6126#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
6127#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)
6128#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
6129#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
6130#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)
6131#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)
6132#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
6133#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
6134#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
6135/*! BYPASS_CLK_SRC
6136 * 0b00..Select the 24MHz oscillator as source.
6137 * 0b10..Reserved1
6138 * 0b11..Reserved2
6139 */
6140#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
6141#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)
6142#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)
6143#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
6144#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
6145#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
6146/*! POST_DIV_SELECT
6147 * 0b00..Divide by 4.
6148 * 0b01..Divide by 2.
6149 * 0b10..Divide by 1.
6150 * 0b11..Reserved
6151 */
6152#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
6153#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)
6154#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)
6155#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)
6156/*! @} */
6157
6158/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */
6159/*! @{ */
6160#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)
6161#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)
6162#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
6163#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)
6164#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)
6165#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)
6166#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)
6167#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)
6168#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
6169#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
6170#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
6171/*! BYPASS_CLK_SRC
6172 * 0b00..Select the 24MHz oscillator as source.
6173 * 0b10..Reserved1
6174 * 0b11..Reserved2
6175 */
6176#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
6177#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)
6178#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)
6179#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)
6180#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
6181#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
6182/*! POST_DIV_SELECT
6183 * 0b00..Divide by 4.
6184 * 0b01..Divide by 2.
6185 * 0b10..Divide by 1.
6186 * 0b11..Reserved
6187 */
6188#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
6189#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)
6190#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)
6191#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)
6192/*! @} */
6193
6194/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */
6195/*! @{ */
6196#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)
6197#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)
6198#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
6199#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)
6200#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)
6201#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)
6202#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)
6203#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)
6204#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
6205#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
6206#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
6207/*! BYPASS_CLK_SRC
6208 * 0b00..Select the 24MHz oscillator as source.
6209 * 0b10..Reserved1
6210 * 0b11..Reserved2
6211 */
6212#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
6213#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)
6214#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)
6215#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)
6216#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
6217#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
6218/*! POST_DIV_SELECT
6219 * 0b00..Divide by 4.
6220 * 0b01..Divide by 2.
6221 * 0b10..Divide by 1.
6222 * 0b11..Reserved
6223 */
6224#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
6225#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)
6226#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)
6227#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)
6228/*! @} */
6229
6230/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */
6231/*! @{ */
6232#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)
6233#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)
6234#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
6235/*! @} */
6236
6237/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */
6238/*! @{ */
6239#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)
6240#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)
6241#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
6242/*! @} */
6243
6244/*! @name PLL_ENET - Analog ENET PLL Control Register */
6245/*! @{ */
6246#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U)
6247#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U)
6248#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)
6249#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)
6250#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)
6251#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
6252#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U)
6253#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U)
6254#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)
6255#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)
6256#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
6257/*! BYPASS_CLK_SRC
6258 * 0b00..Select the 24MHz oscillator as source.
6259 * 0b10..Reserved1
6260 * 0b11..Reserved2
6261 */
6262#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
6263#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)
6264#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)
6265#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
6266#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)
6267#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)
6268#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)
6269#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK (0x400000U)
6270#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT (22U)
6271#define CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_500M_REF_EN_MASK)
6272#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)
6273#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)
6274#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)
6275/*! @} */
6276
6277/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */
6278/*! @{ */
6279#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U)
6280#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U)
6281#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK)
6282#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)
6283#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)
6284#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)
6285#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U)
6286#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U)
6287#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)
6288#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
6289#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
6290/*! BYPASS_CLK_SRC
6291 * 0b00..Select the 24MHz oscillator as source.
6292 * 0b10..Reserved1
6293 * 0b11..Reserved2
6294 */
6295#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
6296#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)
6297#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)
6298#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)
6299#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)
6300#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)
6301#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)
6302#define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK (0x400000U)
6303#define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT (22U)
6304#define CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_500M_REF_EN_MASK)
6305#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)
6306#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)
6307#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)
6308/*! @} */
6309
6310/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */
6311/*! @{ */
6312#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U)
6313#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U)
6314#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK)
6315#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)
6316#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)
6317#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)
6318#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U)
6319#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U)
6320#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)
6321#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
6322#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
6323/*! BYPASS_CLK_SRC
6324 * 0b00..Select the 24MHz oscillator as source.
6325 * 0b10..Reserved1
6326 * 0b11..Reserved2
6327 */
6328#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
6329#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)
6330#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)
6331#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)
6332#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)
6333#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)
6334#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)
6335#define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK (0x400000U)
6336#define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT (22U)
6337#define CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_500M_REF_EN_MASK)
6338#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)
6339#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)
6340#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)
6341/*! @} */
6342
6343/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */
6344/*! @{ */
6345#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U)
6346#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U)
6347#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK)
6348#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)
6349#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)
6350#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)
6351#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U)
6352#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U)
6353#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)
6354#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
6355#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
6356/*! BYPASS_CLK_SRC
6357 * 0b00..Select the 24MHz oscillator as source.
6358 * 0b10..Reserved1
6359 * 0b11..Reserved2
6360 */
6361#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
6362#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)
6363#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)
6364#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)
6365#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)
6366#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)
6367#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)
6368#define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK (0x400000U)
6369#define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT (22U)
6370#define CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_500M_REF_EN_MASK)
6371#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)
6372#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)
6373#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)
6374/*! @} */
6375
6376/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
6377/*! @{ */
6378#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)
6379#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)
6380#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
6381#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)
6382#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)
6383#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)
6384#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)
6385#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)
6386#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)
6387#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)
6388#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)
6389#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
6390#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)
6391#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)
6392#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)
6393#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)
6394#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)
6395#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)
6396#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)
6397#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)
6398#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
6399#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)
6400#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)
6401#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)
6402#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)
6403#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)
6404#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)
6405#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)
6406#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)
6407#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
6408#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)
6409#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)
6410#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)
6411#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)
6412#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)
6413#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)
6414/*! @} */
6415
6416/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
6417/*! @{ */
6418#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)
6419#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)
6420#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
6421#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)
6422#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)
6423#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)
6424#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)
6425#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)
6426#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)
6427#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)
6428#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)
6429#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
6430#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)
6431#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)
6432#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)
6433#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)
6434#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)
6435#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)
6436#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)
6437#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)
6438#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
6439#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)
6440#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)
6441#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)
6442#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)
6443#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)
6444#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)
6445#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)
6446#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)
6447#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
6448#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)
6449#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)
6450#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)
6451#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)
6452#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)
6453#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)
6454/*! @} */
6455
6456/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
6457/*! @{ */
6458#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)
6459#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)
6460#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
6461#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)
6462#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)
6463#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)
6464#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)
6465#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)
6466#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)
6467#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)
6468#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)
6469#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
6470#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)
6471#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)
6472#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)
6473#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)
6474#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)
6475#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)
6476#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)
6477#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)
6478#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
6479#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)
6480#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)
6481#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)
6482#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)
6483#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)
6484#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)
6485#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)
6486#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)
6487#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
6488#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)
6489#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)
6490#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)
6491#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)
6492#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)
6493#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)
6494/*! @} */
6495
6496/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
6497/*! @{ */
6498#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)
6499#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)
6500#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
6501#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)
6502#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)
6503#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)
6504#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)
6505#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)
6506#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)
6507#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)
6508#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)
6509#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
6510#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)
6511#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)
6512#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)
6513#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)
6514#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)
6515#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)
6516#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)
6517#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)
6518#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
6519#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)
6520#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)
6521#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)
6522#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)
6523#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)
6524#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)
6525#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)
6526#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)
6527#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
6528#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)
6529#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)
6530#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)
6531#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)
6532#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)
6533#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)
6534/*! @} */
6535
6536/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
6537/*! @{ */
6538#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)
6539#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)
6540#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
6541#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)
6542#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)
6543#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)
6544#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)
6545#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)
6546#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)
6547#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)
6548#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)
6549#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
6550#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)
6551#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)
6552#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)
6553#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)
6554#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)
6555#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)
6556#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)
6557#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)
6558#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
6559#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)
6560#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)
6561#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)
6562#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)
6563#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)
6564#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)
6565#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)
6566#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)
6567#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
6568#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)
6569#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)
6570#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)
6571#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)
6572#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)
6573#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)
6574/*! @} */
6575
6576/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
6577/*! @{ */
6578#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)
6579#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)
6580#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
6581#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)
6582#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)
6583#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)
6584#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)
6585#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)
6586#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)
6587#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)
6588#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)
6589#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
6590#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)
6591#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)
6592#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)
6593#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)
6594#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)
6595#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)
6596#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)
6597#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)
6598#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
6599#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)
6600#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)
6601#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)
6602#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)
6603#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)
6604#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)
6605#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)
6606#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)
6607#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
6608#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)
6609#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)
6610#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)
6611#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)
6612#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)
6613#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)
6614/*! @} */
6615
6616/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
6617/*! @{ */
6618#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)
6619#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)
6620#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
6621#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)
6622#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)
6623#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)
6624#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)
6625#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)
6626#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)
6627#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)
6628#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)
6629#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
6630#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)
6631#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)
6632#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)
6633#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)
6634#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)
6635#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)
6636#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)
6637#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)
6638#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
6639#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)
6640#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)
6641#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)
6642#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)
6643#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)
6644#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)
6645#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)
6646#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)
6647#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
6648#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)
6649#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)
6650#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)
6651#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)
6652#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)
6653#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)
6654/*! @} */
6655
6656/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
6657/*! @{ */
6658#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)
6659#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)
6660#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
6661#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)
6662#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)
6663#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)
6664#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)
6665#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)
6666#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)
6667#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)
6668#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)
6669#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
6670#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)
6671#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)
6672#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)
6673#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)
6674#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)
6675#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)
6676#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)
6677#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)
6678#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
6679#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)
6680#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)
6681#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)
6682#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)
6683#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)
6684#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)
6685#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)
6686#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)
6687#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
6688#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)
6689#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)
6690#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)
6691#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)
6692#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)
6693#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)
6694/*! @} */
6695
6696/*! @name MISC0 - Miscellaneous Register 0 */
6697/*! @{ */
6698#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)
6699#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)
6700#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
6701#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
6702#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
6703/*! REFTOP_SELFBIASOFF
6704 * 0b0..Uses coarse bias currents for startup
6705 * 0b1..Uses bandgap-based bias currents for best performance.
6706 */
6707#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
6708#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)
6709#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)
6710/*! REFTOP_VBGADJ
6711 * 0b000..Nominal VBG
6712 * 0b001..VBG+0.78%
6713 * 0b010..VBG+1.56%
6714 * 0b011..VBG+2.34%
6715 * 0b100..VBG-0.78%
6716 * 0b101..VBG-1.56%
6717 * 0b110..VBG-2.34%
6718 * 0b111..VBG-3.12%
6719 */
6720#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
6721#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)
6722#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)
6723#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
6724#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
6725#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
6726/*! STOP_MODE_CONFIG
6727 * 0b00..All analog except RTC powered down on stop mode assertion.
6728 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
6729 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
6730 * bandgap together with the rest analog is powered down.
6731 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
6732 */
6733#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
6734#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
6735#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
6736/*! DISCON_HIGH_SNVS
6737 * 0b0..Turn on the switch
6738 * 0b1..Turn off the switch
6739 */
6740#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
6741#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)
6742#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)
6743/*! OSC_I
6744 * 0b00..Nominal
6745 * 0b01..Decrease current by 12.5%
6746 * 0b10..Decrease current by 25.0%
6747 * 0b11..Decrease current by 37.5%
6748 */
6749#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
6750#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)
6751#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)
6752#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)
6753#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
6754#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)
6755#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
6756#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
6757#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)
6758/*! CLKGATE_CTRL
6759 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
6760 * 0b1..Prevent the logic from ever gating off the clock.
6761 */
6762#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
6763#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
6764#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)
6765/*! CLKGATE_DELAY
6766 * 0b000..0.5ms
6767 * 0b001..1.0ms
6768 * 0b010..2.0ms
6769 * 0b011..3.0ms
6770 * 0b100..4.0ms
6771 * 0b101..5.0ms
6772 * 0b110..6.0ms
6773 * 0b111..7.0ms
6774 */
6775#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
6776#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
6777#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
6778/*! RTC_XTAL_SOURCE
6779 * 0b0..Internal ring oscillator
6780 * 0b1..RTC_XTAL
6781 */
6782#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
6783#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
6784#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)
6785#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)
6786/*! @} */
6787
6788/*! @name MISC0_SET - Miscellaneous Register 0 */
6789/*! @{ */
6790#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)
6791#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)
6792#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
6793#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
6794#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
6795/*! REFTOP_SELFBIASOFF
6796 * 0b0..Uses coarse bias currents for startup
6797 * 0b1..Uses bandgap-based bias currents for best performance.
6798 */
6799#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
6800#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
6801#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
6802/*! REFTOP_VBGADJ
6803 * 0b000..Nominal VBG
6804 * 0b001..VBG+0.78%
6805 * 0b010..VBG+1.56%
6806 * 0b011..VBG+2.34%
6807 * 0b100..VBG-0.78%
6808 * 0b101..VBG-1.56%
6809 * 0b110..VBG-2.34%
6810 * 0b111..VBG-3.12%
6811 */
6812#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
6813#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
6814#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
6815#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
6816#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
6817#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
6818/*! STOP_MODE_CONFIG
6819 * 0b00..All analog except RTC powered down on stop mode assertion.
6820 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
6821 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
6822 * bandgap together with the rest analog is powered down.
6823 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
6824 */
6825#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
6826#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
6827#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
6828/*! DISCON_HIGH_SNVS
6829 * 0b0..Turn on the switch
6830 * 0b1..Turn off the switch
6831 */
6832#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
6833#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)
6834#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)
6835/*! OSC_I
6836 * 0b00..Nominal
6837 * 0b01..Decrease current by 12.5%
6838 * 0b10..Decrease current by 25.0%
6839 * 0b11..Decrease current by 37.5%
6840 */
6841#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
6842#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
6843#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)
6844#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)
6845#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
6846#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
6847#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
6848#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
6849#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
6850/*! CLKGATE_CTRL
6851 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
6852 * 0b1..Prevent the logic from ever gating off the clock.
6853 */
6854#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
6855#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
6856#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
6857/*! CLKGATE_DELAY
6858 * 0b000..0.5ms
6859 * 0b001..1.0ms
6860 * 0b010..2.0ms
6861 * 0b011..3.0ms
6862 * 0b100..4.0ms
6863 * 0b101..5.0ms
6864 * 0b110..6.0ms
6865 * 0b111..7.0ms
6866 */
6867#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
6868#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
6869#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
6870/*! RTC_XTAL_SOURCE
6871 * 0b0..Internal ring oscillator
6872 * 0b1..RTC_XTAL
6873 */
6874#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
6875#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
6876#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
6877#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)
6878/*! @} */
6879
6880/*! @name MISC0_CLR - Miscellaneous Register 0 */
6881/*! @{ */
6882#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
6883#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
6884#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
6885#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
6886#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
6887/*! REFTOP_SELFBIASOFF
6888 * 0b0..Uses coarse bias currents for startup
6889 * 0b1..Uses bandgap-based bias currents for best performance.
6890 */
6891#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
6892#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
6893#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
6894/*! REFTOP_VBGADJ
6895 * 0b000..Nominal VBG
6896 * 0b001..VBG+0.78%
6897 * 0b010..VBG+1.56%
6898 * 0b011..VBG+2.34%
6899 * 0b100..VBG-0.78%
6900 * 0b101..VBG-1.56%
6901 * 0b110..VBG-2.34%
6902 * 0b111..VBG-3.12%
6903 */
6904#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
6905#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
6906#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
6907#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
6908#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
6909#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
6910/*! STOP_MODE_CONFIG
6911 * 0b00..All analog except RTC powered down on stop mode assertion.
6912 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
6913 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
6914 * bandgap together with the rest analog is powered down.
6915 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
6916 */
6917#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
6918#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
6919#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
6920/*! DISCON_HIGH_SNVS
6921 * 0b0..Turn on the switch
6922 * 0b1..Turn off the switch
6923 */
6924#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
6925#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)
6926#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)
6927/*! OSC_I
6928 * 0b00..Nominal
6929 * 0b01..Decrease current by 12.5%
6930 * 0b10..Decrease current by 25.0%
6931 * 0b11..Decrease current by 37.5%
6932 */
6933#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
6934#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
6935#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
6936#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)
6937#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
6938#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
6939#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
6940#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
6941#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
6942/*! CLKGATE_CTRL
6943 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
6944 * 0b1..Prevent the logic from ever gating off the clock.
6945 */
6946#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
6947#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
6948#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
6949/*! CLKGATE_DELAY
6950 * 0b000..0.5ms
6951 * 0b001..1.0ms
6952 * 0b010..2.0ms
6953 * 0b011..3.0ms
6954 * 0b100..4.0ms
6955 * 0b101..5.0ms
6956 * 0b110..6.0ms
6957 * 0b111..7.0ms
6958 */
6959#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
6960#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
6961#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
6962/*! RTC_XTAL_SOURCE
6963 * 0b0..Internal ring oscillator
6964 * 0b1..RTC_XTAL
6965 */
6966#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
6967#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
6968#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
6969#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)
6970/*! @} */
6971
6972/*! @name MISC0_TOG - Miscellaneous Register 0 */
6973/*! @{ */
6974#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
6975#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
6976#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
6977#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
6978#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
6979/*! REFTOP_SELFBIASOFF
6980 * 0b0..Uses coarse bias currents for startup
6981 * 0b1..Uses bandgap-based bias currents for best performance.
6982 */
6983#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
6984#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
6985#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
6986/*! REFTOP_VBGADJ
6987 * 0b000..Nominal VBG
6988 * 0b001..VBG+0.78%
6989 * 0b010..VBG+1.56%
6990 * 0b011..VBG+2.34%
6991 * 0b100..VBG-0.78%
6992 * 0b101..VBG-1.56%
6993 * 0b110..VBG-2.34%
6994 * 0b111..VBG-3.12%
6995 */
6996#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
6997#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
6998#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
6999#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)
7000#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
7001#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
7002/*! STOP_MODE_CONFIG
7003 * 0b00..All analog except RTC powered down on stop mode assertion.
7004 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
7005 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
7006 * bandgap together with the rest analog is powered down.
7007 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
7008 */
7009#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
7010#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
7011#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
7012/*! DISCON_HIGH_SNVS
7013 * 0b0..Turn on the switch
7014 * 0b1..Turn off the switch
7015 */
7016#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
7017#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)
7018#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)
7019/*! OSC_I
7020 * 0b00..Nominal
7021 * 0b01..Decrease current by 12.5%
7022 * 0b10..Decrease current by 25.0%
7023 * 0b11..Decrease current by 37.5%
7024 */
7025#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
7026#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
7027#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
7028#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)
7029#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
7030#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
7031#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)
7032#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
7033#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
7034/*! CLKGATE_CTRL
7035 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
7036 * 0b1..Prevent the logic from ever gating off the clock.
7037 */
7038#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)
7039#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
7040#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
7041/*! CLKGATE_DELAY
7042 * 0b000..0.5ms
7043 * 0b001..1.0ms
7044 * 0b010..2.0ms
7045 * 0b011..3.0ms
7046 * 0b100..4.0ms
7047 * 0b101..5.0ms
7048 * 0b110..6.0ms
7049 * 0b111..7.0ms
7050 */
7051#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
7052#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
7053#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
7054/*! RTC_XTAL_SOURCE
7055 * 0b0..Internal ring oscillator
7056 * 0b1..RTC_XTAL
7057 */
7058#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
7059#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
7060#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
7061#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)
7062/*! @} */
7063
7064/*! @name MISC1 - Miscellaneous Register 1 */
7065/*! @{ */
7066#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
7067#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
7068#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)
7069#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
7070#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
7071#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)
7072#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
7073#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
7074#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)
7075#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
7076#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)
7077#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)
7078#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
7079#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
7080#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)
7081#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
7082#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)
7083#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)
7084#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
7085#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)
7086#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)
7087/*! @} */
7088
7089/*! @name MISC1_SET - Miscellaneous Register 1 */
7090/*! @{ */
7091#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
7092#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
7093#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
7094#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
7095#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
7096#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
7097#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
7098#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
7099#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)
7100#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
7101#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
7102#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)
7103#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
7104#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
7105#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)
7106#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
7107#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
7108#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)
7109#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
7110#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
7111#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)
7112/*! @} */
7113
7114/*! @name MISC1_CLR - Miscellaneous Register 1 */
7115/*! @{ */
7116#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
7117#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
7118#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
7119#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
7120#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
7121#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
7122#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
7123#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
7124#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)
7125#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
7126#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
7127#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)
7128#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
7129#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
7130#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)
7131#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
7132#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
7133#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)
7134#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
7135#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
7136#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)
7137/*! @} */
7138
7139/*! @name MISC1_TOG - Miscellaneous Register 1 */
7140/*! @{ */
7141#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
7142#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
7143#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
7144#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
7145#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
7146#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
7147#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
7148#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
7149#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)
7150#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
7151#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
7152#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)
7153#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
7154#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
7155#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)
7156#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
7157#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
7158#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)
7159#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
7160#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
7161#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)
7162/*! @} */
7163
7164/*! @name MISC2 - Miscellaneous Register 2 */
7165/*! @{ */
7166#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)
7167#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)
7168/*! REG0_BO_OFFSET
7169 * 0b100..Brownout offset = 0.100V
7170 * 0b111..Brownout offset = 0.175V
7171 */
7172#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
7173#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)
7174#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)
7175/*! REG0_BO_STATUS
7176 * 0b1..Brownout, supply is below target minus brownout offset.
7177 */
7178#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)
7179#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)
7180#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)
7181#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)
7182#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)
7183#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)
7184#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)
7185#define CCM_ANALOG_MISC2_PLL3_DISABLE_MASK (0x80U)
7186#define CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT (7U)
7187/*! PLL3_DISABLE
7188 * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
7189 * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
7190 */
7191#define CCM_ANALOG_MISC2_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK)
7192#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)
7193#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)
7194/*! REG1_BO_OFFSET
7195 * 0b100..Brownout offset = 0.100V
7196 * 0b111..Brownout offset = 0.175V
7197 */
7198#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
7199#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)
7200#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)
7201/*! REG1_BO_STATUS
7202 * 0b1..Brownout, supply is below target minus brownout offset.
7203 */
7204#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)
7205#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
7206#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)
7207#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)
7208#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)
7209#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)
7210#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)
7211#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
7212#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
7213/*! AUDIO_DIV_LSB
7214 * 0b0..divide by 1 (Default)
7215 * 0b1..divide by 2
7216 */
7217#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)
7218#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
7219#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)
7220/*! REG2_BO_OFFSET
7221 * 0b100..Brownout offset = 0.100V
7222 * 0b111..Brownout offset = 0.175V
7223 */
7224#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
7225#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)
7226#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)
7227#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)
7228#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
7229#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)
7230#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)
7231#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)
7232#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)
7233#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)
7234#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
7235#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
7236/*! AUDIO_DIV_MSB
7237 * 0b0..divide by 1 (Default)
7238 * 0b1..divide by 2
7239 */
7240#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)
7241#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
7242#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)
7243/*! REG0_STEP_TIME
7244 * 0b00..64
7245 * 0b01..128
7246 * 0b10..256
7247 * 0b11..512
7248 */
7249#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
7250#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
7251#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)
7252/*! REG1_STEP_TIME
7253 * 0b00..64
7254 * 0b01..128
7255 * 0b10..256
7256 * 0b11..512
7257 */
7258#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
7259#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
7260#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)
7261/*! REG2_STEP_TIME
7262 * 0b00..64
7263 * 0b01..128
7264 * 0b10..256
7265 * 0b11..512
7266 */
7267#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
7268/*! @} */
7269
7270/*! @name MISC2_SET - Miscellaneous Register 2 */
7271/*! @{ */
7272#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
7273#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
7274/*! REG0_BO_OFFSET
7275 * 0b100..Brownout offset = 0.100V
7276 * 0b111..Brownout offset = 0.175V
7277 */
7278#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
7279#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
7280#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
7281/*! REG0_BO_STATUS
7282 * 0b1..Brownout, supply is below target minus brownout offset.
7283 */
7284#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)
7285#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
7286#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
7287#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)
7288#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)
7289#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)
7290#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)
7291#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK (0x80U)
7292#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT (7U)
7293/*! PLL3_DISABLE
7294 * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
7295 * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
7296 */
7297#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK)
7298#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
7299#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
7300/*! REG1_BO_OFFSET
7301 * 0b100..Brownout offset = 0.100V
7302 * 0b111..Brownout offset = 0.175V
7303 */
7304#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
7305#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
7306#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
7307/*! REG1_BO_STATUS
7308 * 0b1..Brownout, supply is below target minus brownout offset.
7309 */
7310#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)
7311#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
7312#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
7313#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)
7314#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)
7315#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)
7316#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)
7317#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
7318#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
7319/*! AUDIO_DIV_LSB
7320 * 0b0..divide by 1 (Default)
7321 * 0b1..divide by 2
7322 */
7323#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)
7324#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
7325#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
7326/*! REG2_BO_OFFSET
7327 * 0b100..Brownout offset = 0.100V
7328 * 0b111..Brownout offset = 0.175V
7329 */
7330#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
7331#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
7332#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
7333#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)
7334#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
7335#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
7336#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)
7337#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)
7338#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)
7339#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)
7340#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
7341#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
7342/*! AUDIO_DIV_MSB
7343 * 0b0..divide by 1 (Default)
7344 * 0b1..divide by 2
7345 */
7346#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)
7347#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
7348#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
7349/*! REG0_STEP_TIME
7350 * 0b00..64
7351 * 0b01..128
7352 * 0b10..256
7353 * 0b11..512
7354 */
7355#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
7356#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
7357#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
7358/*! REG1_STEP_TIME
7359 * 0b00..64
7360 * 0b01..128
7361 * 0b10..256
7362 * 0b11..512
7363 */
7364#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
7365#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
7366#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
7367/*! REG2_STEP_TIME
7368 * 0b00..64
7369 * 0b01..128
7370 * 0b10..256
7371 * 0b11..512
7372 */
7373#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
7374/*! @} */
7375
7376/*! @name MISC2_CLR - Miscellaneous Register 2 */
7377/*! @{ */
7378#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
7379#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
7380/*! REG0_BO_OFFSET
7381 * 0b100..Brownout offset = 0.100V
7382 * 0b111..Brownout offset = 0.175V
7383 */
7384#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
7385#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
7386#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
7387/*! REG0_BO_STATUS
7388 * 0b1..Brownout, supply is below target minus brownout offset.
7389 */
7390#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)
7391#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
7392#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
7393#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)
7394#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)
7395#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)
7396#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)
7397#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK (0x80U)
7398#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT (7U)
7399/*! PLL3_DISABLE
7400 * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
7401 * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
7402 */
7403#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK)
7404#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
7405#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
7406/*! REG1_BO_OFFSET
7407 * 0b100..Brownout offset = 0.100V
7408 * 0b111..Brownout offset = 0.175V
7409 */
7410#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
7411#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
7412#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
7413/*! REG1_BO_STATUS
7414 * 0b1..Brownout, supply is below target minus brownout offset.
7415 */
7416#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)
7417#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
7418#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
7419#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)
7420#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)
7421#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)
7422#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)
7423#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
7424#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
7425/*! AUDIO_DIV_LSB
7426 * 0b0..divide by 1 (Default)
7427 * 0b1..divide by 2
7428 */
7429#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)
7430#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
7431#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
7432/*! REG2_BO_OFFSET
7433 * 0b100..Brownout offset = 0.100V
7434 * 0b111..Brownout offset = 0.175V
7435 */
7436#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
7437#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
7438#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
7439#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)
7440#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
7441#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
7442#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)
7443#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)
7444#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)
7445#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)
7446#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
7447#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
7448/*! AUDIO_DIV_MSB
7449 * 0b0..divide by 1 (Default)
7450 * 0b1..divide by 2
7451 */
7452#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)
7453#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
7454#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
7455/*! REG0_STEP_TIME
7456 * 0b00..64
7457 * 0b01..128
7458 * 0b10..256
7459 * 0b11..512
7460 */
7461#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
7462#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
7463#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
7464/*! REG1_STEP_TIME
7465 * 0b00..64
7466 * 0b01..128
7467 * 0b10..256
7468 * 0b11..512
7469 */
7470#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
7471#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
7472#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
7473/*! REG2_STEP_TIME
7474 * 0b00..64
7475 * 0b01..128
7476 * 0b10..256
7477 * 0b11..512
7478 */
7479#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
7480/*! @} */
7481
7482/*! @name MISC2_TOG - Miscellaneous Register 2 */
7483/*! @{ */
7484#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
7485#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
7486/*! REG0_BO_OFFSET
7487 * 0b100..Brownout offset = 0.100V
7488 * 0b111..Brownout offset = 0.175V
7489 */
7490#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
7491#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
7492#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
7493/*! REG0_BO_STATUS
7494 * 0b1..Brownout, supply is below target minus brownout offset.
7495 */
7496#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)
7497#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
7498#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
7499#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)
7500#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)
7501#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)
7502#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)
7503#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK (0x80U)
7504#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT (7U)
7505/*! PLL3_DISABLE
7506 * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
7507 * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
7508 */
7509#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK)
7510#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
7511#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
7512/*! REG1_BO_OFFSET
7513 * 0b100..Brownout offset = 0.100V
7514 * 0b111..Brownout offset = 0.175V
7515 */
7516#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
7517#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
7518#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
7519/*! REG1_BO_STATUS
7520 * 0b1..Brownout, supply is below target minus brownout offset.
7521 */
7522#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)
7523#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
7524#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
7525#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)
7526#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)
7527#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)
7528#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)
7529#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
7530#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
7531/*! AUDIO_DIV_LSB
7532 * 0b0..divide by 1 (Default)
7533 * 0b1..divide by 2
7534 */
7535#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)
7536#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
7537#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
7538/*! REG2_BO_OFFSET
7539 * 0b100..Brownout offset = 0.100V
7540 * 0b111..Brownout offset = 0.175V
7541 */
7542#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
7543#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
7544#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
7545#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)
7546#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
7547#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
7548#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)
7549#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)
7550#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)
7551#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)
7552#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
7553#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
7554/*! AUDIO_DIV_MSB
7555 * 0b0..divide by 1 (Default)
7556 * 0b1..divide by 2
7557 */
7558#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)
7559#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
7560#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
7561/*! REG0_STEP_TIME
7562 * 0b00..64
7563 * 0b01..128
7564 * 0b10..256
7565 * 0b11..512
7566 */
7567#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
7568#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
7569#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
7570/*! REG1_STEP_TIME
7571 * 0b00..64
7572 * 0b01..128
7573 * 0b10..256
7574 * 0b11..512
7575 */
7576#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
7577#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
7578#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
7579/*! REG2_STEP_TIME
7580 * 0b00..64
7581 * 0b01..128
7582 * 0b10..256
7583 * 0b11..512
7584 */
7585#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)
7586/*! @} */
7587
7588
7589/*!
7590 * @}
7591 */ /* end of group CCM_ANALOG_Register_Masks */
7592
7593
7594/* CCM_ANALOG - Peripheral instance base addresses */
7595/** Peripheral CCM_ANALOG base address */
7596#define CCM_ANALOG_BASE (0x400D8000u)
7597/** Peripheral CCM_ANALOG base pointer */
7598#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
7599/** Array initializer of CCM_ANALOG peripheral base addresses */
7600#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
7601/** Array initializer of CCM_ANALOG peripheral base pointers */
7602#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
7603
7604/*!
7605 * @}
7606 */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
7607
7608
7609/* ----------------------------------------------------------------------------
7610 -- CM7_MCM Peripheral Access Layer
7611 ---------------------------------------------------------------------------- */
7612
7613/*!
7614 * @addtogroup CM7_MCM_Peripheral_Access_Layer CM7_MCM Peripheral Access Layer
7615 * @{
7616 */
7617
7618/** CM7_MCM - Register Layout Typedef */
7619typedef struct {
7620 uint8_t RESERVED_0[16];
7621 __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
7622} CM7_MCM_Type;
7623
7624/* ----------------------------------------------------------------------------
7625 -- CM7_MCM Register Masks
7626 ---------------------------------------------------------------------------- */
7627
7628/*!
7629 * @addtogroup CM7_MCM_Register_Masks CM7_MCM Register Masks
7630 * @{
7631 */
7632
7633/*! @name ISCR - Interrupt Status and Control Register */
7634/*! @{ */
7635#define CM7_MCM_ISCR_WABS_MASK (0x20U)
7636#define CM7_MCM_ISCR_WABS_SHIFT (5U)
7637/*! WABS - Write Abort on Slave
7638 * 0b0..No abort
7639 * 0b1..Abort
7640 */
7641#define CM7_MCM_ISCR_WABS(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABS_SHIFT)) & CM7_MCM_ISCR_WABS_MASK)
7642#define CM7_MCM_ISCR_WABSO_MASK (0x40U)
7643#define CM7_MCM_ISCR_WABSO_SHIFT (6U)
7644/*! WABSO - Write Abort on Slave Overrun
7645 * 0b0..No write abort overrun
7646 * 0b1..Write abort overrun occurred
7647 */
7648#define CM7_MCM_ISCR_WABSO(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABSO_SHIFT)) & CM7_MCM_ISCR_WABSO_MASK)
7649#define CM7_MCM_ISCR_FIOC_MASK (0x100U)
7650#define CM7_MCM_ISCR_FIOC_SHIFT (8U)
7651/*! FIOC - FPU Invalid Operation interrupt Status
7652 * 0b0..No interrupt
7653 * 0b1..Interrupt occured
7654 */
7655#define CM7_MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOC_SHIFT)) & CM7_MCM_ISCR_FIOC_MASK)
7656#define CM7_MCM_ISCR_FDZC_MASK (0x200U)
7657#define CM7_MCM_ISCR_FDZC_SHIFT (9U)
7658/*! FDZC - FPU Divide-by-Zero Interrupt Status
7659 * 0b0..No interrupt
7660 * 0b1..Interrupt occured
7661 */
7662#define CM7_MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZC_SHIFT)) & CM7_MCM_ISCR_FDZC_MASK)
7663#define CM7_MCM_ISCR_FOFC_MASK (0x400U)
7664#define CM7_MCM_ISCR_FOFC_SHIFT (10U)
7665/*! FOFC - FPU Overflow interrupt status
7666 * 0b0..No interrupt
7667 * 0b1..Interrupt occured
7668 */
7669#define CM7_MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFC_SHIFT)) & CM7_MCM_ISCR_FOFC_MASK)
7670#define CM7_MCM_ISCR_FUFC_MASK (0x800U)
7671#define CM7_MCM_ISCR_FUFC_SHIFT (11U)
7672/*! FUFC - FPU Underflow Interrupt Status
7673 * 0b0..No interrupt
7674 * 0b1..Interrupt occured
7675 */
7676#define CM7_MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFC_SHIFT)) & CM7_MCM_ISCR_FUFC_MASK)
7677#define CM7_MCM_ISCR_FIXC_MASK (0x1000U)
7678#define CM7_MCM_ISCR_FIXC_SHIFT (12U)
7679/*! FIXC - FPU Inexact Interrupt Status
7680 * 0b0..No interrupt
7681 * 0b1..Interrupt occured
7682 */
7683#define CM7_MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXC_SHIFT)) & CM7_MCM_ISCR_FIXC_MASK)
7684#define CM7_MCM_ISCR_FIDC_MASK (0x8000U)
7685#define CM7_MCM_ISCR_FIDC_SHIFT (15U)
7686/*! FIDC - FPU Input Denormal Interrupt Status
7687 * 0b0..No interrupt
7688 * 0b1..Interrupt occured
7689 */
7690#define CM7_MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDC_SHIFT)) & CM7_MCM_ISCR_FIDC_MASK)
7691#define CM7_MCM_ISCR_WABE_MASK (0x200000U)
7692#define CM7_MCM_ISCR_WABE_SHIFT (21U)
7693/*! WABE - TCM Write Abort Interrupt enable
7694 * 0b0..Disable interrupt
7695 * 0b1..Enable interrupt
7696 */
7697#define CM7_MCM_ISCR_WABE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABE_SHIFT)) & CM7_MCM_ISCR_WABE_MASK)
7698#define CM7_MCM_ISCR_FIOCE_MASK (0x1000000U)
7699#define CM7_MCM_ISCR_FIOCE_SHIFT (24U)
7700/*! FIOCE - FPU Invalid Operation Interrupt Enable
7701 * 0b0..Disable interrupt
7702 * 0b1..Enable interrupt
7703 */
7704#define CM7_MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOCE_SHIFT)) & CM7_MCM_ISCR_FIOCE_MASK)
7705#define CM7_MCM_ISCR_FDZCE_MASK (0x2000000U)
7706#define CM7_MCM_ISCR_FDZCE_SHIFT (25U)
7707/*! FDZCE - FPU Divide-by-Zero Interrupt Enable
7708 * 0b0..Disable interrupt
7709 * 0b1..Enable interrupt
7710 */
7711#define CM7_MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZCE_SHIFT)) & CM7_MCM_ISCR_FDZCE_MASK)
7712#define CM7_MCM_ISCR_FOFCE_MASK (0x4000000U)
7713#define CM7_MCM_ISCR_FOFCE_SHIFT (26U)
7714/*! FOFCE - FPU Overflow Interrupt Enable
7715 * 0b0..Disable interrupt
7716 * 0b1..Enable interrupt
7717 */
7718#define CM7_MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFCE_SHIFT)) & CM7_MCM_ISCR_FOFCE_MASK)
7719#define CM7_MCM_ISCR_FUFCE_MASK (0x8000000U)
7720#define CM7_MCM_ISCR_FUFCE_SHIFT (27U)
7721/*! FUFCE - FPU Underflow Interrupt Enable
7722 * 0b0..Disable interrupt
7723 * 0b1..Enable interrupt
7724 */
7725#define CM7_MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFCE_SHIFT)) & CM7_MCM_ISCR_FUFCE_MASK)
7726#define CM7_MCM_ISCR_FIXCE_MASK (0x10000000U)
7727#define CM7_MCM_ISCR_FIXCE_SHIFT (28U)
7728/*! FIXCE - FPU Inexact Interrupt Enable
7729 * 0b0..Disable interrupt
7730 * 0b1..Enable interrupt
7731 */
7732#define CM7_MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXCE_SHIFT)) & CM7_MCM_ISCR_FIXCE_MASK)
7733#define CM7_MCM_ISCR_FIDCE_MASK (0x80000000U)
7734#define CM7_MCM_ISCR_FIDCE_SHIFT (31U)
7735/*! FIDCE - FPU Input Denormal Interrupt Enable
7736 * 0b0..Disable interrupt
7737 * 0b1..Enable interrupt
7738 */
7739#define CM7_MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDCE_SHIFT)) & CM7_MCM_ISCR_FIDCE_MASK)
7740/*! @} */
7741
7742
7743/*!
7744 * @}
7745 */ /* end of group CM7_MCM_Register_Masks */
7746
7747
7748/* CM7_MCM - Peripheral instance base addresses */
7749/** Peripheral CM7_MCM base address */
7750#define CM7_MCM_BASE (0xE0080000u)
7751/** Peripheral CM7_MCM base pointer */
7752#define CM7_MCM ((CM7_MCM_Type *)CM7_MCM_BASE)
7753/** Array initializer of CM7_MCM peripheral base addresses */
7754#define CM7_MCM_BASE_ADDRS { CM7_MCM_BASE }
7755/** Array initializer of CM7_MCM peripheral base pointers */
7756#define CM7_MCM_BASE_PTRS { CM7_MCM }
7757
7758/*!
7759 * @}
7760 */ /* end of group CM7_MCM_Peripheral_Access_Layer */
7761
7762
7763/* ----------------------------------------------------------------------------
7764 -- CMP Peripheral Access Layer
7765 ---------------------------------------------------------------------------- */
7766
7767/*!
7768 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
7769 * @{
7770 */
7771
7772/** CMP - Register Layout Typedef */
7773typedef struct {
7774 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
7775 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
7776 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
7777 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
7778 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
7779 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
7780} CMP_Type;
7781
7782/* ----------------------------------------------------------------------------
7783 -- CMP Register Masks
7784 ---------------------------------------------------------------------------- */
7785
7786/*!
7787 * @addtogroup CMP_Register_Masks CMP Register Masks
7788 * @{
7789 */
7790
7791/*! @name CR0 - CMP Control Register 0 */
7792/*! @{ */
7793#define CMP_CR0_HYSTCTR_MASK (0x3U)
7794#define CMP_CR0_HYSTCTR_SHIFT (0U)
7795/*! HYSTCTR - Comparator hard block hysteresis control
7796 * 0b00..Level 0
7797 * 0b01..Level 1
7798 * 0b10..Level 2
7799 * 0b11..Level 3
7800 */
7801#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
7802#define CMP_CR0_FILTER_CNT_MASK (0x70U)
7803#define CMP_CR0_FILTER_CNT_SHIFT (4U)
7804/*! FILTER_CNT - Filter Sample Count
7805 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
7806 * 0b001..One sample must agree. The comparator output is simply sampled.
7807 * 0b010..2 consecutive samples must agree.
7808 * 0b011..3 consecutive samples must agree.
7809 * 0b100..4 consecutive samples must agree.
7810 * 0b101..5 consecutive samples must agree.
7811 * 0b110..6 consecutive samples must agree.
7812 * 0b111..7 consecutive samples must agree.
7813 */
7814#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
7815/*! @} */
7816
7817/*! @name CR1 - CMP Control Register 1 */
7818/*! @{ */
7819#define CMP_CR1_EN_MASK (0x1U)
7820#define CMP_CR1_EN_SHIFT (0U)
7821/*! EN - Comparator Module Enable
7822 * 0b0..Analog Comparator is disabled.
7823 * 0b1..Analog Comparator is enabled.
7824 */
7825#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
7826#define CMP_CR1_OPE_MASK (0x2U)
7827#define CMP_CR1_OPE_SHIFT (1U)
7828/*! OPE - Comparator Output Pin Enable
7829 * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
7830 * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the
7831 * associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this
7832 * bit has no effect.
7833 */
7834#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
7835#define CMP_CR1_COS_MASK (0x4U)
7836#define CMP_CR1_COS_SHIFT (2U)
7837/*! COS - Comparator Output Select
7838 * 0b0..Set the filtered comparator output (CMPO) to equal COUT.
7839 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
7840 */
7841#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
7842#define CMP_CR1_INV_MASK (0x8U)
7843#define CMP_CR1_INV_SHIFT (3U)
7844/*! INV - Comparator INVERT
7845 * 0b0..Does not invert the comparator output.
7846 * 0b1..Inverts the comparator output.
7847 */
7848#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
7849#define CMP_CR1_PMODE_MASK (0x10U)
7850#define CMP_CR1_PMODE_SHIFT (4U)
7851/*! PMODE - Power Mode Select
7852 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
7853 * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
7854 */
7855#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
7856#define CMP_CR1_WE_MASK (0x40U)
7857#define CMP_CR1_WE_SHIFT (6U)
7858/*! WE - Windowing Enable
7859 * 0b0..Windowing mode is not selected.
7860 * 0b1..Windowing mode is selected.
7861 */
7862#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
7863#define CMP_CR1_SE_MASK (0x80U)
7864#define CMP_CR1_SE_SHIFT (7U)
7865/*! SE - Sample Enable
7866 * 0b0..Sampling mode is not selected.
7867 * 0b1..Sampling mode is selected.
7868 */
7869#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
7870/*! @} */
7871
7872/*! @name FPR - CMP Filter Period Register */
7873/*! @{ */
7874#define CMP_FPR_FILT_PER_MASK (0xFFU)
7875#define CMP_FPR_FILT_PER_SHIFT (0U)
7876/*! FILT_PER - Filter Sample Period
7877 */
7878#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
7879/*! @} */
7880
7881/*! @name SCR - CMP Status and Control Register */
7882/*! @{ */
7883#define CMP_SCR_COUT_MASK (0x1U)
7884#define CMP_SCR_COUT_SHIFT (0U)
7885/*! COUT - Analog Comparator Output
7886 */
7887#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
7888#define CMP_SCR_CFF_MASK (0x2U)
7889#define CMP_SCR_CFF_SHIFT (1U)
7890/*! CFF - Analog Comparator Flag Falling
7891 * 0b0..Falling-edge on COUT has not been detected.
7892 * 0b1..Falling-edge on COUT has occurred.
7893 */
7894#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
7895#define CMP_SCR_CFR_MASK (0x4U)
7896#define CMP_SCR_CFR_SHIFT (2U)
7897/*! CFR - Analog Comparator Flag Rising
7898 * 0b0..Rising-edge on COUT has not been detected.
7899 * 0b1..Rising-edge on COUT has occurred.
7900 */
7901#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
7902#define CMP_SCR_IEF_MASK (0x8U)
7903#define CMP_SCR_IEF_SHIFT (3U)
7904/*! IEF - Comparator Interrupt Enable Falling
7905 * 0b0..Interrupt is disabled.
7906 * 0b1..Interrupt is enabled.
7907 */
7908#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
7909#define CMP_SCR_IER_MASK (0x10U)
7910#define CMP_SCR_IER_SHIFT (4U)
7911/*! IER - Comparator Interrupt Enable Rising
7912 * 0b0..Interrupt is disabled.
7913 * 0b1..Interrupt is enabled.
7914 */
7915#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
7916#define CMP_SCR_DMAEN_MASK (0x40U)
7917#define CMP_SCR_DMAEN_SHIFT (6U)
7918/*! DMAEN - DMA Enable Control
7919 * 0b0..DMA is disabled.
7920 * 0b1..DMA is enabled.
7921 */
7922#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
7923/*! @} */
7924
7925/*! @name DACCR - DAC Control Register */
7926/*! @{ */
7927#define CMP_DACCR_VOSEL_MASK (0x3FU)
7928#define CMP_DACCR_VOSEL_SHIFT (0U)
7929/*! VOSEL - DAC Output Voltage Select
7930 */
7931#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
7932#define CMP_DACCR_VRSEL_MASK (0x40U)
7933#define CMP_DACCR_VRSEL_SHIFT (6U)
7934/*! VRSEL - Supply Voltage Reference Source Select
7935 * 0b0..Vin1 is selected as resistor ladder network supply reference.
7936 * 0b1..Vin2 is selected as resistor ladder network supply reference.
7937 */
7938#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
7939#define CMP_DACCR_DACEN_MASK (0x80U)
7940#define CMP_DACCR_DACEN_SHIFT (7U)
7941/*! DACEN - DAC Enable
7942 * 0b0..DAC is disabled.
7943 * 0b1..DAC is enabled.
7944 */
7945#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
7946/*! @} */
7947
7948/*! @name MUXCR - MUX Control Register */
7949/*! @{ */
7950#define CMP_MUXCR_MSEL_MASK (0x7U)
7951#define CMP_MUXCR_MSEL_SHIFT (0U)
7952/*! MSEL - Minus Input Mux Control
7953 * 0b000..IN0
7954 * 0b001..IN1
7955 * 0b010..IN2
7956 * 0b011..IN3
7957 * 0b100..IN4
7958 * 0b101..IN5
7959 * 0b110..IN6
7960 * 0b111..IN7
7961 */
7962#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
7963#define CMP_MUXCR_PSEL_MASK (0x38U)
7964#define CMP_MUXCR_PSEL_SHIFT (3U)
7965/*! PSEL - Plus Input Mux Control
7966 * 0b000..IN0
7967 * 0b001..IN1
7968 * 0b010..IN2
7969 * 0b011..IN3
7970 * 0b100..IN4
7971 * 0b101..IN5
7972 * 0b110..IN6
7973 * 0b111..IN7
7974 */
7975#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
7976/*! @} */
7977
7978
7979/*!
7980 * @}
7981 */ /* end of group CMP_Register_Masks */
7982
7983
7984/* CMP - Peripheral instance base addresses */
7985/** Peripheral CMP1 base address */
7986#define CMP1_BASE (0x40094000u)
7987/** Peripheral CMP1 base pointer */
7988#define CMP1 ((CMP_Type *)CMP1_BASE)
7989/** Peripheral CMP2 base address */
7990#define CMP2_BASE (0x40094008u)
7991/** Peripheral CMP2 base pointer */
7992#define CMP2 ((CMP_Type *)CMP2_BASE)
7993/** Peripheral CMP3 base address */
7994#define CMP3_BASE (0x40094010u)
7995/** Peripheral CMP3 base pointer */
7996#define CMP3 ((CMP_Type *)CMP3_BASE)
7997/** Peripheral CMP4 base address */
7998#define CMP4_BASE (0x40094018u)
7999/** Peripheral CMP4 base pointer */
8000#define CMP4 ((CMP_Type *)CMP4_BASE)
8001/** Array initializer of CMP peripheral base addresses */
8002#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
8003/** Array initializer of CMP peripheral base pointers */
8004#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
8005/** Interrupt vectors for the CMP peripheral type */
8006#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
8007
8008/*!
8009 * @}
8010 */ /* end of group CMP_Peripheral_Access_Layer */
8011
8012
8013/* ----------------------------------------------------------------------------
8014 -- CSU Peripheral Access Layer
8015 ---------------------------------------------------------------------------- */
8016
8017/*!
8018 * @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer
8019 * @{
8020 */
8021
8022/** CSU - Register Layout Typedef */
8023typedef struct {
8024 __IO uint32_t CSL[32]; /**< Config security level register, array offset: 0x0, array step: 0x4 */
8025 uint8_t RESERVED_0[384];
8026 __IO uint32_t HP0; /**< HP0 register, offset: 0x200 */
8027 uint8_t RESERVED_1[20];
8028 __IO uint32_t SA; /**< Secure access register, offset: 0x218 */
8029 uint8_t RESERVED_2[316];
8030 __IO uint32_t HPCONTROL0; /**< HPCONTROL0 register, offset: 0x358 */
8031} CSU_Type;
8032
8033/* ----------------------------------------------------------------------------
8034 -- CSU Register Masks
8035 ---------------------------------------------------------------------------- */
8036
8037/*!
8038 * @addtogroup CSU_Register_Masks CSU Register Masks
8039 * @{
8040 */
8041
8042/*! @name CSL - Config security level register *