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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/board.c309
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/board.h221
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/clock_config.c420
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/clock_config.h114
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/peripherals.c51
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/peripherals.h34
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/pin_mux.c55
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/pin_mux.h65
8 files changed, 1269 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/board.c
new file mode 100644
index 000000000..f180ffce1
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/board.c
@@ -0,0 +1,309 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "board.h"
11#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12#include "fsl_lpi2c.h"
13#endif /* SDK_I2C_BASED_COMPONENT_USED */
14#if defined BOARD_USE_CODEC
15#include "fsl_wm8960.h"
16#endif
17#include "fsl_iomuxc.h"
18
19/*******************************************************************************
20 * Variables
21 ******************************************************************************/
22#if defined BOARD_USE_CODEC
23codec_config_t boardCodecConfig = {.I2C_SendFunc = BOARD_Codec_I2C_Send,
24 .I2C_ReceiveFunc = BOARD_Codec_I2C_Receive,
25 .op.Init = WM8960_Init,
26 .op.Deinit = WM8960_Deinit,
27 .op.SetFormat = WM8960_ConfigDataFormat};
28#endif
29
30/*******************************************************************************
31 * Code
32 ******************************************************************************/
33
34/* Get debug console frequency. */
35uint32_t BOARD_DebugConsoleSrcFreq(void)
36{
37 uint32_t freq;
38
39 /* To make it simple, we assume default PLL and divider settings, and the only variable
40 from application is use PLL3 source or OSC source */
41 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
42 {
43 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
44 }
45 else
46 {
47 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
48 }
49
50 return freq;
51}
52
53/* Initialize debug console. */
54void BOARD_InitDebugConsole(void)
55{
56 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
57
58 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
59}
60
61void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength)
62{
63 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_02_USDHC1_CMD,
64 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
65 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
66 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
67 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
68 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_03_USDHC1_CLK,
69 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
70 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(0) |
71 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
72 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_04_USDHC1_DATA0,
73 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
74 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
75 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
76 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
77 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_05_USDHC1_DATA1,
78 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
79 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
80 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
81 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
82 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_00_USDHC1_DATA2,
83 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
84 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
85 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
86 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
87 IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B0_01_USDHC1_DATA3,
88 IOMUXC_SW_PAD_CTL_PAD_SPEED(speed) | IOMUXC_SW_PAD_CTL_PAD_SRE_MASK |
89 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK | IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
90 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK | IOMUXC_SW_PAD_CTL_PAD_PUS(1) |
91 IOMUXC_SW_PAD_CTL_PAD_DSE(strength));
92}
93
94void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength)
95{
96}
97
98/* MPU configuration. */
99void BOARD_ConfigMPU(void)
100{
101 /* Disable I cache and D cache */
102 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
103 {
104 SCB_DisableICache();
105 }
106 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
107 {
108 SCB_DisableDCache();
109 }
110
111 /* Disable MPU */
112 ARM_MPU_Disable();
113
114 /* Region 0 setting */
115 MPU->RBAR = ARM_MPU_RBAR(0, 0xC0000000U);
116 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
117
118 /* Region 1 setting */
119 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
120 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
121
122/* Region 2 setting */
123#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
124 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
125 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_8MB);
126#else
127 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
128 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_8MB);
129#endif
130
131 /* Region 3 setting */
132 MPU->RBAR = ARM_MPU_RBAR(3, 0x00000000U);
133 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
134
135 /* Region 4 setting */
136 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
137 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
138
139 /* Region 5 setting */
140 MPU->RBAR = ARM_MPU_RBAR(5, 0x20000000U);
141 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
142
143 /* Region 6 setting */
144 MPU->RBAR = ARM_MPU_RBAR(6, 0x20200000U);
145 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
146
147/* The define sets the cacheable memory to shareable,
148 * this suggestion is referred from chapter 2.2.1 Memory regions,
149 * types and attributes in Cortex-M7 Devices, Generic User Guide */
150#if defined(SDRAM_IS_SHAREABLE)
151 /* Region 7 setting, set whole SDRAM can be accessed by cache */
152 MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
153 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 1, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
154#else
155 /* Region 7 setting, set whole SDRAM can be accessed by cache */
156 MPU->RBAR = ARM_MPU_RBAR(7, 0x80000000U);
157 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
158#endif
159
160 /* Region 8 setting, set last 2MB of SDRAM can't be accessed by cache, glocal variables which are not expected to be
161 * accessed by cache can be put here */
162 MPU->RBAR = ARM_MPU_RBAR(8, 0x81E00000U);
163 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_2MB);
164
165 /* Enable MPU */
166 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
167
168 /* Enable I cache and D cache */
169 SCB_EnableDCache();
170 SCB_EnableICache();
171}
172
173#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
174void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
175{
176 lpi2c_master_config_t lpi2cConfig = {0};
177
178 /*
179 * lpi2cConfig.debugEnable = false;
180 * lpi2cConfig.ignoreAck = false;
181 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
182 * lpi2cConfig.baudRate_Hz = 100000U;
183 * lpi2cConfig.busIdleTimeout_ns = 0;
184 * lpi2cConfig.pinLowTimeout_ns = 0;
185 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
186 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
187 */
188 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
189 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
190}
191
192status_t BOARD_LPI2C_Send(LPI2C_Type *base,
193 uint8_t deviceAddress,
194 uint32_t subAddress,
195 uint8_t subAddressSize,
196 uint8_t *txBuff,
197 uint8_t txBuffSize)
198{
199 status_t reVal;
200
201 /* Send master blocking data to slave */
202 reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
203 if (kStatus_Success == reVal)
204 {
205 while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
206 {
207 }
208
209 reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
210 if (reVal != kStatus_Success)
211 {
212 return reVal;
213 }
214
215 reVal = LPI2C_MasterSend(base, txBuff, txBuffSize);
216 if (reVal != kStatus_Success)
217 {
218 return reVal;
219 }
220
221 reVal = LPI2C_MasterStop(base);
222 if (reVal != kStatus_Success)
223 {
224 return reVal;
225 }
226 }
227
228 return reVal;
229}
230
231status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
232 uint8_t deviceAddress,
233 uint32_t subAddress,
234 uint8_t subAddressSize,
235 uint8_t *rxBuff,
236 uint8_t rxBuffSize)
237{
238 status_t reVal;
239
240 reVal = LPI2C_MasterStart(base, deviceAddress, kLPI2C_Write);
241 if (kStatus_Success == reVal)
242 {
243 while (LPI2C_MasterGetStatusFlags(base) & kLPI2C_MasterNackDetectFlag)
244 {
245 }
246
247 reVal = LPI2C_MasterSend(base, &subAddress, subAddressSize);
248 if (reVal != kStatus_Success)
249 {
250 return reVal;
251 }
252
253 reVal = LPI2C_MasterRepeatedStart(base, deviceAddress, kLPI2C_Read);
254 if (reVal != kStatus_Success)
255 {
256 return reVal;
257 }
258
259 reVal = LPI2C_MasterReceive(base, rxBuff, rxBuffSize);
260 if (reVal != kStatus_Success)
261 {
262 return reVal;
263 }
264
265 reVal = LPI2C_MasterStop(base);
266 if (reVal != kStatus_Success)
267 {
268 return reVal;
269 }
270 }
271 return reVal;
272}
273
274void BOARD_Accel_I2C_Init(void)
275{
276 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
277}
278
279status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
280{
281 uint8_t data = (uint8_t)txBuff;
282
283 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
284}
285
286status_t BOARD_Accel_I2C_Receive(
287 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
288{
289 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
290}
291
292void BOARD_Codec_I2C_Init(void)
293{
294 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
295}
296
297status_t BOARD_Codec_I2C_Send(
298 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
299{
300 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
301 txBuffSize);
302}
303
304status_t BOARD_Codec_I2C_Receive(
305 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
306{
307 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
308}
309#endif /* SDK_I2C_BASED_COMPONENT_USED */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/board.h
new file mode 100644
index 000000000..3c0097879
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/board.h
@@ -0,0 +1,221 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10
11#include "clock_config.h"
12#include "fsl_common.h"
13#include "fsl_gpio.h"
14
15/*******************************************************************************
16 * Definitions
17 ******************************************************************************/
18/*! @brief The board name */
19#define BOARD_NAME "MIMXRT1020-EVK"
20
21/* The UART to use for debug messages. */
22#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
23#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
24#define BOARD_DEBUG_UART_INSTANCE 1U
25
26#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
27
28#define BOARD_UART_IRQ LPUART1_IRQn
29#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
30
31#ifndef BOARD_DEBUG_UART_BAUDRATE
32#define BOARD_DEBUG_UART_BAUDRATE (115200U)
33#endif /* BOARD_DEBUG_UART_BAUDRATE */
34
35/* @Brief Board accelerator sensor configuration */
36#define BOARD_ACCEL_I2C_BASEADDR LPI2C4
37#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
38#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
39#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
40
41#define BOARD_CODEC_I2C_BASEADDR LPI2C1
42#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
43#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
44#define BOARD_CODEC_I2C_CLOCK_FREQ \
45 ((CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8) / (BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER + 1U))
46
47/*! @brief The USER_LED used for board */
48#define LOGIC_LED_ON (0U)
49#define LOGIC_LED_OFF (1U)
50#ifndef BOARD_USER_LED_GPIO
51#define BOARD_USER_LED_GPIO GPIO1
52#endif
53#ifndef BOARD_USER_LED_GPIO_PIN
54#define BOARD_USER_LED_GPIO_PIN (5U)
55#endif
56
57#define USER_LED_INIT(output) \
58 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
59 BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
60#define USER_LED_ON() \
61 GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
62#define USER_LED_OFF() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
63#define USER_LED_TOGGLE() \
64 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
65 0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
66
67/*! @brief Define the port interrupt number for the board switches */
68#ifndef BOARD_USER_BUTTON_GPIO
69#define BOARD_USER_BUTTON_GPIO GPIO5
70#endif
71#ifndef BOARD_USER_BUTTON_GPIO_PIN
72#define BOARD_USER_BUTTON_GPIO_PIN (0U)
73#endif
74#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
75#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
76#define BOARD_USER_BUTTON_NAME "SW4"
77
78/*! @brief The hyper flash size */
79#define BOARD_FLASH_SIZE (0x800000U)
80
81/*! @brief The ENET PHY address. */
82#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
83
84/* USB PHY condfiguration */
85#define BOARD_USB_PHY_D_CAL (0x0CU)
86#define BOARD_USB_PHY_TXCAL45DP (0x06U)
87#define BOARD_USB_PHY_TXCAL45DM (0x06U)
88
89#define BOARD_ARDUINO_INT_IRQ (GPIO1_Combined_16_31_IRQn)
90#define BOARD_ARDUINO_I2C_IRQ (LPI2C4_IRQn)
91#define BOARD_ARDUINO_I2C_INDEX (4)
92#define BOARD_USDHC1_BASEADDR USDHC1
93#define BOARD_USDHC2_BASEADDR USDHC2
94#define BOARD_USDHC_CD_GPIO_BASE GPIO3
95#define BOARD_USDHC_CD_GPIO_PIN 19
96#define BOARD_USDHC_CD_PORT_IRQ GPIO3_Combined_16_31_IRQn
97#define BOARD_USDHC_CD_PORT_IRQ_HANDLER GPIO3_Combined_16_31_IRQHandler
98
99#define BOARD_USDHC_CD_STATUS() (GPIO_PinRead(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN))
100
101#define BOARD_USDHC_CD_INTERRUPT_STATUS() (GPIO_PortGetInterruptFlags(BOARD_USDHC_CD_GPIO_BASE))
102#define BOARD_USDHC_CD_CLEAR_INTERRUPT(flag) (GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, flag))
103
104#define BOARD_USDHC_CD_GPIO_INIT() \
105 { \
106 gpio_pin_config_t sw_config = { \
107 kGPIO_DigitalInput, 0, kGPIO_IntFallingEdge, \
108 }; \
109 GPIO_PinInit(BOARD_USDHC_CD_GPIO_BASE, BOARD_USDHC_CD_GPIO_PIN, &sw_config); \
110 GPIO_PortEnableInterrupts(BOARD_USDHC_CD_GPIO_BASE, 1U << BOARD_USDHC_CD_GPIO_PIN); \
111 GPIO_PortClearInterruptFlags(BOARD_USDHC_CD_GPIO_BASE, ~0); \
112 }
113
114#define BOARD_HAS_SDCARD (1U)
115#define BOARD_SD_POWER_RESET_GPIO (GPIO3)
116#define BOARD_SD_POWER_RESET_GPIO_PIN (24U)
117
118#define BOARD_USDHC_CARD_INSERT_CD_LEVEL (0U)
119
120#define BOARD_USDHC_MMCCARD_POWER_CONTROL(state)
121
122#define BOARD_USDHC_MMCCARD_POWER_CONTROL_INIT() \
123 { \
124 gpio_pin_config_t sw_config = { \
125 kGPIO_DigitalOutput, 0, kGPIO_NoIntmode, \
126 }; \
127 GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
128 GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, true); \
129 }
130
131#define BOARD_USDHC_SDCARD_POWER_CONTROL_INIT() \
132 { \
133 gpio_pin_config_t sw_config = { \
134 kGPIO_DigitalOutput, 0, kGPIO_NoIntmode, \
135 }; \
136 GPIO_PinInit(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, &sw_config); \
137 }
138
139#define BOARD_USDHC_SDCARD_POWER_CONTROL(state) \
140 (GPIO_PinWrite(BOARD_SD_POWER_RESET_GPIO, BOARD_SD_POWER_RESET_GPIO_PIN, state))
141
142#define BOARD_USDHC1_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U))
143#define BOARD_USDHC2_CLK_FREQ (CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U))
144
145#define BOARD_SD_HOST_BASEADDR BOARD_USDHC1_BASEADDR
146#define BOARD_SD_HOST_CLK_FREQ BOARD_USDHC1_CLK_FREQ
147#define BOARD_SD_HOST_IRQ USDHC1_IRQn
148
149#define BOARD_MMC_HOST_BASEADDR BOARD_USDHC2_BASEADDR
150#define BOARD_MMC_HOST_CLK_FREQ BOARD_USDHC2_CLK_FREQ
151#define BOARD_MMC_HOST_IRQ USDHC2_IRQn
152#define BOARD_MMC_VCCQ_SUPPLY kMMC_VoltageWindow170to195
153#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
154/* we are using the BB SD socket to DEMO the MMC example,but the
155* SD socket provide 4bit bus only, so we define this macro to avoid
156* 8bit data bus test
157*/
158#define BOARD_MMC_SUPPORT_8BIT_BUS (1U)
159
160#define BOARD_SD_HOST_SUPPORT_SDR104_FREQ (100000000U)
161#define BOARD_SD_HOST_SUPPORT_HS200_FREQ (180000000U)
162/*! @brief The WIFI-QCA shield pin. */
163#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
164#define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
165#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 23U /*!< PIO4 pin index: 23 */
166#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_23 /*!< Pin name */
167#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
168#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
169#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
170
171#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
172#define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
173#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 22U /*!< PIO1 pin index: 22 */
174#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_22 /*!< Pin name */
175#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
176#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
177#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
178
179#if defined(__cplusplus)
180extern "C" {
181#endif /* __cplusplus */
182
183/*******************************************************************************
184 * API
185 ******************************************************************************/
186uint32_t BOARD_DebugConsoleSrcFreq(void);
187
188void BOARD_InitDebugConsole(void);
189void BOARD_ConfigMPU(void);
190#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
191void BOARD_InitDebugConsole(void);
192void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
193status_t BOARD_LPI2C_Send(LPI2C_Type *base,
194 uint8_t deviceAddress,
195 uint32_t subAddress,
196 uint8_t subaddressSize,
197 uint8_t *txBuff,
198 uint8_t txBuffSize);
199status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
200 uint8_t deviceAddress,
201 uint32_t subAddress,
202 uint8_t subaddressSize,
203 uint8_t *rxBuff,
204 uint8_t rxBuffSize);
205void BOARD_Accel_I2C_Init(void);
206status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
207status_t BOARD_Accel_I2C_Receive(
208 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
209void BOARD_Codec_I2C_Init(void);
210status_t BOARD_Codec_I2C_Send(
211 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
212status_t BOARD_Codec_I2C_Receive(
213 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
214#endif /* SDK_I2C_BASED_COMPONENT_USED */
215void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
216void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
217#if defined(__cplusplus)
218}
219#endif /* __cplusplus */
220
221#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/clock_config.c
new file mode 100644
index 000000000..e6357dc33
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/clock_config.c
@@ -0,0 +1,420 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v5.0
26processor: MIMXRT1021xxxxx
27package_id: MIMXRT1021DAG5A
28mcu_data: ksdk2_0
29processor_version: 0.0.0
30board: MIMXRT1020-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
63- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
64- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
65- {id: CLK_1M.outFreq, value: 1 MHz}
66- {id: CLK_24M.outFreq, value: 24 MHz}
67- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
68- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
69- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
70- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
71- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
72- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
73- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
74- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
75- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
76- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
77- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
78- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
79- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
80- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
81- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
82- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
83- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
84- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
85- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
86- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
87- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
88- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
89- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
90- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
91- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
92- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
93settings:
94- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
95- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
96- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
97- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
98- {id: CCM.IPG_PODF.scale, value: '4'}
99- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
100- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
101- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
102- {id: CCM.SEMC_PODF.scale, value: '8'}
103- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
104- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
105- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
106- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
107- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
108- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
109- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
110- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
111- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
112- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
113- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
114- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
115- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
116- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
117- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
118- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
119- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
120- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
121- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
122- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
123- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
124- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
125- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
126- {id: CCM_ANALOG.PLL4.denom, value: '50'}
127- {id: CCM_ANALOG.PLL4.div, value: '47'}
128- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
129- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
130- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
131- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
132sources:
133- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
134- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
135 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
136
137/*******************************************************************************
138 * Variables for BOARD_BootClockRUN configuration
139 ******************************************************************************/
140const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
141 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
142 .numerator = 0, /* 30 bit numerator of fractional loop divider */
143 .denominator = 1, /* 30 bit denominator of fractional loop divider */
144 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
145};
146const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
147 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
148 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
149};
150const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = {
151 .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
152 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
153 .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
154 .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
155 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
156};
157/*******************************************************************************
158 * Code for BOARD_BootClockRUN configuration
159 ******************************************************************************/
160void BOARD_BootClockRUN(void)
161{
162 /* Init RTC OSC clock frequency. */
163 CLOCK_SetRtcXtalFreq(32768U);
164 /* Enable 1MHz clock output. */
165 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
166 /* Use free 1MHz clock output. */
167 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
168 /* Set XTAL 24MHz clock frequency. */
169 CLOCK_SetXtalFreq(24000000U);
170 /* Enable XTAL 24MHz clock source. */
171 CLOCK_InitExternalClk(0);
172 /* Enable internal RC. */
173 CLOCK_InitRcOsc24M();
174 /* Switch clock source to external OSC. */
175 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
176 /* Set Oscillator ready counter value. */
177 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
178 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
179 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
180 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
181 /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 500Mhz. */
182 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
183 /* Waiting for DCDC_STS_DC_OK bit is asserted */
184 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
185 {
186 }
187 /* Set AHB_PODF. */
188 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
189 /* Disable IPG clock gate. */
190 CLOCK_DisableClock(kCLOCK_Adc1);
191 CLOCK_DisableClock(kCLOCK_Adc2);
192 CLOCK_DisableClock(kCLOCK_Xbar1);
193 CLOCK_DisableClock(kCLOCK_Xbar2);
194 /* Set IPG_PODF. */
195 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
196 /* Set ARM_PODF. */
197 CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
198 /* Set PERIPH_CLK2_PODF. */
199 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
200 /* Disable PERCLK clock gate. */
201 CLOCK_DisableClock(kCLOCK_Gpt1);
202 CLOCK_DisableClock(kCLOCK_Gpt1S);
203 CLOCK_DisableClock(kCLOCK_Gpt2);
204 CLOCK_DisableClock(kCLOCK_Gpt2S);
205 CLOCK_DisableClock(kCLOCK_Pit);
206 /* Set PERCLK_PODF. */
207 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
208 /* Disable USDHC1 clock gate. */
209 CLOCK_DisableClock(kCLOCK_Usdhc1);
210 /* Set USDHC1_PODF. */
211 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
212 /* Set Usdhc1 clock source. */
213 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
214 /* Disable USDHC2 clock gate. */
215 CLOCK_DisableClock(kCLOCK_Usdhc2);
216 /* Set USDHC2_PODF. */
217 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
218 /* Set Usdhc2 clock source. */
219 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
220 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
221 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
222 * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
223 * well.*/
224#ifndef SKIP_SYSCLK_INIT
225 /* Disable Semc clock gate. */
226 CLOCK_DisableClock(kCLOCK_Semc);
227 /* Set SEMC_PODF. */
228 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
229 /* Set Semc alt clock source. */
230 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
231 /* Set Semc clock source. */
232 CLOCK_SetMux(kCLOCK_SemcMux, 0);
233#endif
234 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
235 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
236 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
237 * well.*/
238#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
239 /* Disable Flexspi clock gate. */
240 CLOCK_DisableClock(kCLOCK_FlexSpi);
241 /* Set FLEXSPI_PODF. */
242 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
243 /* Set Flexspi clock source. */
244 CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
245#endif
246 /* Disable LPSPI clock gate. */
247 CLOCK_DisableClock(kCLOCK_Lpspi1);
248 CLOCK_DisableClock(kCLOCK_Lpspi2);
249 CLOCK_DisableClock(kCLOCK_Lpspi3);
250 CLOCK_DisableClock(kCLOCK_Lpspi4);
251 /* Set LPSPI_PODF. */
252 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
253 /* Set Lpspi clock source. */
254 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
255 /* Disable TRACE clock gate. */
256 CLOCK_DisableClock(kCLOCK_Trace);
257 /* Set TRACE_PODF. */
258 CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
259 /* Set Trace clock source. */
260 CLOCK_SetMux(kCLOCK_TraceMux, 2);
261 /* Disable SAI1 clock gate. */
262 CLOCK_DisableClock(kCLOCK_Sai1);
263 /* Set SAI1_CLK_PRED. */
264 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
265 /* Set SAI1_CLK_PODF. */
266 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
267 /* Set Sai1 clock source. */
268 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
269 /* Disable SAI2 clock gate. */
270 CLOCK_DisableClock(kCLOCK_Sai2);
271 /* Set SAI2_CLK_PRED. */
272 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
273 /* Set SAI2_CLK_PODF. */
274 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
275 /* Set Sai2 clock source. */
276 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
277 /* Disable SAI3 clock gate. */
278 CLOCK_DisableClock(kCLOCK_Sai3);
279 /* Set SAI3_CLK_PRED. */
280 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
281 /* Set SAI3_CLK_PODF. */
282 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
283 /* Set Sai3 clock source. */
284 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
285 /* Disable Lpi2c clock gate. */
286 CLOCK_DisableClock(kCLOCK_Lpi2c1);
287 CLOCK_DisableClock(kCLOCK_Lpi2c2);
288 CLOCK_DisableClock(kCLOCK_Lpi2c3);
289 /* Set LPI2C_CLK_PODF. */
290 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
291 /* Set Lpi2c clock source. */
292 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
293 /* Disable CAN clock gate. */
294 CLOCK_DisableClock(kCLOCK_Can1);
295 CLOCK_DisableClock(kCLOCK_Can2);
296 CLOCK_DisableClock(kCLOCK_Can1S);
297 CLOCK_DisableClock(kCLOCK_Can2S);
298 /* Set CAN_CLK_PODF. */
299 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
300 /* Set Can clock source. */
301 CLOCK_SetMux(kCLOCK_CanMux, 2);
302 /* Disable UART clock gate. */
303 CLOCK_DisableClock(kCLOCK_Lpuart1);
304 CLOCK_DisableClock(kCLOCK_Lpuart2);
305 CLOCK_DisableClock(kCLOCK_Lpuart3);
306 CLOCK_DisableClock(kCLOCK_Lpuart4);
307 CLOCK_DisableClock(kCLOCK_Lpuart5);
308 CLOCK_DisableClock(kCLOCK_Lpuart6);
309 CLOCK_DisableClock(kCLOCK_Lpuart7);
310 CLOCK_DisableClock(kCLOCK_Lpuart8);
311 /* Set UART_CLK_PODF. */
312 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
313 /* Set Uart clock source. */
314 CLOCK_SetMux(kCLOCK_UartMux, 0);
315 /* Disable SPDIF clock gate. */
316 CLOCK_DisableClock(kCLOCK_Spdif);
317 /* Set SPDIF0_CLK_PRED. */
318 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
319 /* Set SPDIF0_CLK_PODF. */
320 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
321 /* Set Spdif clock source. */
322 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
323 /* Disable Flexio1 clock gate. */
324 CLOCK_DisableClock(kCLOCK_Flexio1);
325 /* Set FLEXIO1_CLK_PRED. */
326 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
327 /* Set FLEXIO1_CLK_PODF. */
328 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
329 /* Set Flexio1 clock source. */
330 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
331 /* Set Pll3 sw clock source. */
332 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
333 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
334 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
335 * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
336 * well.*/
337#ifndef SKIP_SYSCLK_INIT
338 /* Init System PLL. */
339 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
340 /* Init System pfd0. */
341 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
342 /* Init System pfd1. */
343 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
344 /* Init System pfd2. */
345 CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
346 /* Init System pfd3. */
347 CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
348#endif
349 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
350 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
351 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
352 * well.*/
353#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
354 /* Init Usb1 PLL. */
355 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
356 /* Init Usb1 pfd0. */
357 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
358 /* Init Usb1 pfd1. */
359 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
360 /* Init Usb1 pfd2. */
361 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
362 /* Init Usb1 pfd3. */
363 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
364 /* Disable Usb1 PLL output for USBPHY1. */
365 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
366#endif
367 /* DeInit Audio PLL. */
368 CLOCK_DeinitAudioPll();
369 /* Bypass Audio PLL. */
370 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
371 /* Set divider for Audio PLL. */
372 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
373 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
374 /* Enable Audio PLL output. */
375 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
376 /* Init Enet PLL. */
377 CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
378 /* Set preperiph clock source. */
379 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
380 /* Set periph clock source. */
381 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
382 /* Set periph clock2 clock source. */
383 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
384 /* Set per clock source. */
385 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
386 /* Set clock out1 divider. */
387 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
388 /* Set clock out1 source. */
389 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
390 /* Set clock out2 divider. */
391 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
392 /* Set clock out2 source. */
393 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
394 /* Set clock out1 drives clock out1. */
395 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
396 /* Disable clock out1. */
397 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
398 /* Disable clock out2. */
399 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
400 /* Set SAI1 MCLK1 clock source. */
401 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
402 /* Set SAI1 MCLK2 clock source. */
403 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
404 /* Set SAI1 MCLK3 clock source. */
405 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
406 /* Set SAI2 MCLK3 clock source. */
407 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
408 /* Set SAI3 MCLK3 clock source. */
409 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
410 /* Set MQS configuration. */
411 IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
412 /* Set ENET Tx clock source. */
413 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
414 /* Set GPT1 High frequency reference clock source. */
415 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
416 /* Set GPT2 High frequency reference clock source. */
417 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
418 /* Set SystemCoreClock variable. */
419 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
420}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/clock_config.h
new file mode 100644
index 000000000..21d4e630a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/clock_config.h
@@ -0,0 +1,114 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _CLOCK_CONFIG_H_
9#define _CLOCK_CONFIG_H_
10
11#include "fsl_common.h"
12
13/*******************************************************************************
14 * Definitions
15 ******************************************************************************/
16#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
17
18#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
19/*******************************************************************************
20 ************************ BOARD_InitBootClocks function ************************
21 ******************************************************************************/
22
23#if defined(__cplusplus)
24extern "C" {
25#endif /* __cplusplus*/
26
27/*!
28 * @brief This function executes default configuration of clocks.
29 *
30 */
31void BOARD_InitBootClocks(void);
32
33#if defined(__cplusplus)
34}
35#endif /* __cplusplus*/
36
37/*******************************************************************************
38 ********************** Configuration BOARD_BootClockRUN ***********************
39 ******************************************************************************/
40/*******************************************************************************
41 * Definitions for BOARD_BootClockRUN configuration
42 ******************************************************************************/
43#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
44
45/* Clock outputs (values are in Hz): */
46#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
47#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
48#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
49#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
50#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
51#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
52#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
53#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 0UL
54#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL
55#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL
56#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
57#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
58#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
59#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
60#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
61#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
62#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
63#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
64#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
65#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
66#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
67#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
68#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
69#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
70#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
71#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
72#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
73#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
74#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
75#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
76#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
77#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
78#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL
79#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
80#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
81#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
82#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
83#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
84#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL
85#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL
86
87/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
88 */
89extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
90/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
91 */
92extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
93/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
94 */
95extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
96
97/*******************************************************************************
98 * API for BOARD_BootClockRUN configuration
99 ******************************************************************************/
100#if defined(__cplusplus)
101extern "C" {
102#endif /* __cplusplus*/
103
104/*!
105 * @brief This function executes configuration of clocks.
106 *
107 */
108void BOARD_BootClockRUN(void);
109
110#if defined(__cplusplus)
111}
112#endif /* __cplusplus*/
113
114#endif /* _CLOCK_CONFIG_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/peripherals.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/peripherals.c
new file mode 100644
index 000000000..f27502d0e
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/peripherals.c
@@ -0,0 +1,51 @@
1/*
2 * Copyright 2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/* clang-format off */
14/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Peripherals v6.0
17processor: MIMXRT1021xxxxx
18mcu_data: ksdk2_0
19processor_version: 0.0.22
20functionalGroups:
21- name: BOARD_InitPeripherals
22 called_from_default_init: true
23 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
24
25/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
26component:
27- type: 'system'
28- type_id: 'system_54b53072540eeeb8f8e9343e71f28176'
29- global_system_definitions: []
30 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
31/* clang-format on */
32
33/***********************************************************************************************************************
34 * Included files
35 **********************************************************************************************************************/
36#include "peripherals.h"
37
38/***********************************************************************************************************************
39 * Initialization functions
40 **********************************************************************************************************************/
41void BOARD_InitPeripherals(void)
42{
43}
44
45/***********************************************************************************************************************
46 * BOARD_InitBootPeripherals function
47 **********************************************************************************************************************/
48void BOARD_InitBootPeripherals(void)
49{
50 BOARD_InitPeripherals();
51}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/peripherals.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/peripherals.h
new file mode 100644
index 000000000..150360637
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/peripherals.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright 2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PERIPHERALS_H_
14#define _PERIPHERALS_H_
15
16#if defined(__cplusplus)
17extern "C" {
18#endif /* __cplusplus */
19
20/***********************************************************************************************************************
21 * Initialization functions
22 **********************************************************************************************************************/
23void BOARD_InitPeripherals(void);
24
25/***********************************************************************************************************************
26 * BOARD_InitBootPeripherals function
27 **********************************************************************************************************************/
28void BOARD_InitBootPeripherals(void);
29
30#if defined(__cplusplus)
31}
32#endif
33
34#endif /* _PERIPHERALS_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/pin_mux.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/pin_mux.c
new file mode 100644
index 000000000..df1754358
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/pin_mux.c
@@ -0,0 +1,55 @@
1/*
2 * Copyright 2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13/*
14 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
15!!GlobalInfo
16product: Pins v6.0
17processor: MIMXRT1021xxxxx
18mcu_data: ksdk2_0
19processor_version: 0.0.22
20 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
21 */
22
23#include "fsl_common.h"
24#include "pin_mux.h"
25
26/* FUNCTION ************************************************************************************************************
27 *
28 * Function Name : BOARD_InitBootPins
29 * Description : Calls initialization functions.
30 *
31 * END ****************************************************************************************************************/
32void BOARD_InitBootPins(void) {
33 BOARD_InitPins();
34}
35
36/*
37 * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
38BOARD_InitPins:
39- options: {callFromInitBoot: 'true', enableClock: 'true'}
40- pin_list: []
41 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
42 */
43
44/* FUNCTION ************************************************************************************************************
45 *
46 * Function Name : BOARD_InitPins
47 * Description : Configures pin routing and optionally pin electrical features.
48 *
49 * END ****************************************************************************************************************/
50void BOARD_InitPins(void) {
51}
52
53/***********************************************************************************************************************
54 * EOF
55 **********************************************************************************************************************/
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/pin_mux.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/pin_mux.h
new file mode 100644
index 000000000..3ce8fab85
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1021/project_template/pin_mux.h
@@ -0,0 +1,65 @@
1/*
2 * Copyright 2019 NXP.
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef _PIN_MUX_H_
14#define _PIN_MUX_H_
15
16/***********************************************************************************************************************
17 * Definitions
18 **********************************************************************************************************************/
19
20/*! @brief Direction type */
21typedef enum _pin_mux_direction
22{
23 kPIN_MUX_DirectionInput = 0U, /* Input direction */
24 kPIN_MUX_DirectionOutput = 1U, /* Output direction */
25 kPIN_MUX_DirectionInputOrOutput = 2U /* Input or output direction */
26} pin_mux_direction_t;
27
28/*!
29 * @addtogroup pin_mux
30 * @{
31 */
32
33/***********************************************************************************************************************
34 * API
35 **********************************************************************************************************************/
36
37#if defined(__cplusplus)
38extern "C" {
39#endif
40
41/*!
42 * @brief Calls initialization functions.
43 *
44 */
45void BOARD_InitBootPins(void);
46
47
48/*!
49 * @brief Configures pin routing and optionally pin electrical features.
50 *
51 */
52void BOARD_InitPins(void);
53
54#if defined(__cplusplus)
55}
56#endif
57
58/*!
59 * @}
60 */
61#endif /* _PIN_MUX_H_ */
62
63/***********************************************************************************************************************
64 * EOF
65 **********************************************************************************************************************/
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 21:12:04 +0100