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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1052/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1052/drivers/fsl_clock.h
new file mode 100644
index 000000000..cedb9c4a0
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1052/drivers/fsl_clock.h
@@ -0,0 +1,1738 @@
1/*
2 * Copyright 2017 - 2020, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
13/*! @addtogroup clock */
14/*! @{ */
15
16/*! @file */
17
18/*******************************************************************************
19 * Configurations
20 ******************************************************************************/
21
22/*! @brief Configure whether driver controls clock
23 *
24 * When set to 0, peripheral drivers will enable clock in initialize function
25 * and disable clock in de-initialize function. When set to 1, peripheral
26 * driver will not control the clock, application could control the clock out of
27 * the driver.
28 *
29 * @note All drivers share this feature switcher. If it is set to 1, application
30 * should handle clock enable and disable for all drivers.
31 */
32#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34#endif
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*! @name Driver version */
41/*@{*/
42/*! @brief CLOCK driver version 2.4.0. */
43#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
44
45/* Definition for delay API in clock driver, users can redefine it to the real application. */
46#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
47#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
48#endif
49
50/* analog pll definition */
51#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
52#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
53#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
54
55/*@}*/
56
57/*!
58 * @brief CCM registers offset.
59 */
60#define CCSR_OFFSET 0x0C
61#define CBCDR_OFFSET 0x14
62#define CBCMR_OFFSET 0x18
63#define CSCMR1_OFFSET 0x1C
64#define CSCMR2_OFFSET 0x20
65#define CSCDR1_OFFSET 0x24
66#define CDCDR_OFFSET 0x30
67#define CSCDR2_OFFSET 0x38
68#define CSCDR3_OFFSET 0x3C
69#define CACRR_OFFSET 0x10
70#define CS1CDR_OFFSET 0x28
71#define CS2CDR_OFFSET 0x2C
72
73/*!
74 * @brief CCM Analog registers offset.
75 */
76#define PLL_ARM_OFFSET 0x00
77#define PLL_SYS_OFFSET 0x30
78#define PLL_USB1_OFFSET 0x10
79#define PLL_AUDIO_OFFSET 0x70
80#define PLL_VIDEO_OFFSET 0xA0
81#define PLL_ENET_OFFSET 0xE0
82#define PLL_USB2_OFFSET 0x20
83
84#define CCM_TUPLE(reg, shift, mask, busyShift) \
85 (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
86#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU))))
87#define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
88#define CCM_TUPLE_MASK(tuple) \
89 ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
90#define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
91
92#define CCM_NO_BUSY_WAIT (0x20U)
93
94/*!
95 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
96 */
97#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
98#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)
99#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
100 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
101#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
102
103/* Definition for ERRATA 50235 check */
104#if (defined(FSL_FEATURE_CCM_HAS_ERRATA_50235) && FSL_FEATURE_CCM_HAS_ERRATA_50235)
105#define CAN_CLOCK_CHECK_NO_AFFECTS \
106 ((CCM_CSCMR2_CAN_CLK_SEL(2U) != (CCM->CSCMR2 & CCM_CSCMR2_CAN_CLK_SEL_MASK)) || \
107 (CCM_CCGR5_CG12(0) != (CCM->CCGR5 & CCM_CCGR5_CG12_MASK)))
108#endif /* FSL_FEATURE_CCM_HAS_ERRATA_50235 */
109
110/*!
111 * @brief clock1PN frequency.
112 */
113#define CLKPN_FREQ 0U
114
115/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
116 *
117 * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
118 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
119 * if XTAL is 24MHz,
120 * @code
121 * CLOCK_InitExternalClk(false);
122 * CLOCK_SetXtalFreq(240000000);
123 * @endcode
124 */
125extern volatile uint32_t g_xtalFreq;
126
127/*! @brief External RTC XTAL (32K OSC) clock frequency.
128 *
129 * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
130 * function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
131 */
132extern volatile uint32_t g_rtcXtalFreq;
133
134/* For compatible with other platforms */
135#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
136#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
137
138/*! @brief Clock ip name array for ADC. */
139#define ADC_CLOCKS \
140 { \
141 kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
142 }
143
144/*! @brief Clock ip name array for AOI. */
145#define AOI_CLOCKS \
146 { \
147 kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
148 }
149
150/*! @brief Clock ip name array for BEE. */
151#define BEE_CLOCKS \
152 { \
153 kCLOCK_Bee \
154 }
155
156/*! @brief Clock ip name array for CMP. */
157#define CMP_CLOCKS \
158 { \
159 kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
160 }
161
162/*! @brief Clock ip name array for CSI. */
163#define CSI_CLOCKS \
164 { \
165 kCLOCK_Csi \
166 }
167
168/*! @brief Clock ip name array for DCDC. */
169#define DCDC_CLOCKS \
170 { \
171 kCLOCK_Dcdc \
172 }
173
174/*! @brief Clock ip name array for DCP. */
175#define DCP_CLOCKS \
176 { \
177 kCLOCK_Dcp \
178 }
179
180/*! @brief Clock ip name array for DMAMUX_CLOCKS. */
181#define DMAMUX_CLOCKS \
182 { \
183 kCLOCK_Dma \
184 }
185
186/*! @brief Clock ip name array for DMA. */
187#define EDMA_CLOCKS \
188 { \
189 kCLOCK_Dma \
190 }
191
192/*! @brief Clock ip name array for ENC. */
193#define ENC_CLOCKS \
194 { \
195 kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
196 }
197
198/*! @brief Clock ip name array for ENET. */
199#define ENET_CLOCKS \
200 { \
201 kCLOCK_Enet \
202 }
203
204/*! @brief Clock ip name array for EWM. */
205#define EWM_CLOCKS \
206 { \
207 kCLOCK_Ewm0 \
208 }
209
210/*! @brief Clock ip name array for FLEXCAN. */
211#define FLEXCAN_CLOCKS \
212 { \
213 kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2 \
214 }
215
216/*! @brief Clock ip name array for FLEXCAN Peripheral clock. */
217#define FLEXCAN_PERIPH_CLOCKS \
218 { \
219 kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S \
220 }
221
222/*! @brief Clock ip name array for FLEXIO. */
223#define FLEXIO_CLOCKS \
224 { \
225 kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2 \
226 }
227
228/*! @brief Clock ip name array for FLEXRAM. */
229#define FLEXRAM_CLOCKS \
230 { \
231 kCLOCK_FlexRam \
232 }
233
234/*! @brief Clock ip name array for FLEXSPI. */
235#define FLEXSPI_CLOCKS \
236 { \
237 kCLOCK_FlexSpi \
238 }
239
240/*! @brief Clock ip name array for FLEXSPI EXSC. */
241#define FLEXSPI_EXSC_CLOCKS \
242 { \
243 kCLOCK_FlexSpiExsc \
244 }
245
246/*! @brief Clock ip name array for GPIO. */
247#define GPIO_CLOCKS \
248 { \
249 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
250 }
251
252/*! @brief Clock ip name array for GPT. */
253#define GPT_CLOCKS \
254 { \
255 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
256 }
257
258/*! @brief Clock ip name array for KPP. */
259#define KPP_CLOCKS \
260 { \
261 kCLOCK_Kpp \
262 }
263
264/*! @brief Clock ip name array for LCDIF. */
265#define LCDIF_CLOCKS \
266 { \
267 kCLOCK_Lcd \
268 }
269
270/*! @brief Clock ip name array for LCDIF PIXEL. */
271#define LCDIF_PERIPH_CLOCKS \
272 { \
273 kCLOCK_LcdPixel \
274 }
275
276/*! @brief Clock ip name array for LPI2C. */
277#define LPI2C_CLOCKS \
278 { \
279 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \
280 }
281
282/*! @brief Clock ip name array for LPSPI. */
283#define LPSPI_CLOCKS \
284 { \
285 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \
286 }
287
288/*! @brief Clock ip name array for LPUART. */
289#define LPUART_CLOCKS \
290 { \
291 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
292 kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \
293 }
294
295/*! @brief Clock ip name array for MQS. */
296#define MQS_CLOCKS \
297 { \
298 kCLOCK_Mqs \
299 }
300
301/*! @brief Clock ip name array for OCRAM EXSC. */
302#define OCRAM_EXSC_CLOCKS \
303 { \
304 kCLOCK_OcramExsc \
305 }
306
307/*! @brief Clock ip name array for PIT. */
308#define PIT_CLOCKS \
309 { \
310 kCLOCK_Pit \
311 }
312
313/*! @brief Clock ip name array for PWM. */
314#define PWM_CLOCKS \
315 { \
316 {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
317 {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \
318 {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \
319 {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \
320 { \
321 kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \
322 } \
323 }
324
325/*! @brief Clock ip name array for PXP. */
326#define PXP_CLOCKS \
327 { \
328 kCLOCK_Pxp \
329 }
330
331/*! @brief Clock ip name array for RTWDOG. */
332#define RTWDOG_CLOCKS \
333 { \
334 kCLOCK_Wdog3 \
335 }
336
337/*! @brief Clock ip name array for SAI. */
338#define SAI_CLOCKS \
339 { \
340 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
341 }
342
343/*! @brief Clock ip name array for SEMC. */
344#define SEMC_CLOCKS \
345 { \
346 kCLOCK_Semc \
347 }
348
349/*! @brief Clock ip name array for SEMC EXSC. */
350#define SEMC_EXSC_CLOCKS \
351 { \
352 kCLOCK_SemcExsc \
353 }
354
355/*! @brief Clock ip name array for QTIMER. */
356#define TMR_CLOCKS \
357 { \
358 kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
359 }
360
361/*! @brief Clock ip name array for TRNG. */
362#define TRNG_CLOCKS \
363 { \
364 kCLOCK_Trng \
365 }
366
367/*! @brief Clock ip name array for TSC. */
368#define TSC_CLOCKS \
369 { \
370 kCLOCK_Tsc \
371 }
372
373/*! @brief Clock ip name array for WDOG. */
374#define WDOG_CLOCKS \
375 { \
376 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
377 }
378
379/*! @brief Clock ip name array for USDHC. */
380#define USDHC_CLOCKS \
381 { \
382 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
383 }
384
385/*! @brief Clock ip name array for SPDIF. */
386#define SPDIF_CLOCKS \
387 { \
388 kCLOCK_Spdif \
389 }
390
391/*! @brief Clock ip name array for XBARA. */
392#define XBARA_CLOCKS \
393 { \
394 kCLOCK_Xbar1 \
395 }
396
397/*! @brief Clock ip name array for XBARB. */
398#define XBARB_CLOCKS \
399 { \
400 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
401 }
402
403#define CLOCK_SOURCE_NONE (0xFFU)
404
405#define CLOCK_ROOT_SOUCE \
406 { \
407 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
408 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC1 Clock Root. */ \
409 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
410 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC2 Clock Root. */ \
411 {kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk, \
412 kCLOCK_Usb1PllPfd0Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXSPI Clock Root. */ \
413 {kCLOCK_OscClk, kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1Sw120MClk, \
414 kCLOCK_Usb1PllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* CSI Clock Root. */ \
415 {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \
416 kCLOCK_SysPllPfd2Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPSPI Clock Root. */ \
417 {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \
418 kCLOCK_SysPllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* TRACE Clock Root */ \
419 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
420 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI1 Clock Root */ \
421 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
422 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI2 Clock Root */ \
423 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
424 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI3 Clock Root */ \
425 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
426 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPI2C Clock Root */ \
427 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_Usb1Sw80MClk, \
428 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* CAN Clock Root. */ \
429 {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
430 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* UART Clock Root */ \
431 {kCLOCK_SysPllClk, kCLOCK_Usb1PllPfd3Clk, kCLOCK_VideoPllClk, \
432 kCLOCK_SysPllPfd0Clk, kCLOCK_SysPllPfd1Clk, kCLOCK_Usb1PllPfd1Clk}, /* LCDIF Clock Root */ \
433 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
434 kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* SPDIF0 Clock Root */ \
435 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
436 kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO1 Clock Root */ \
437 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
438 kCLOCK_Usb1PllClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO2 Clock ROOT */ \
439 }
440
441#define CLOCK_ROOT_MUX_TUPLE \
442 { \
443 kCLOCK_Usdhc1Mux, kCLOCK_Usdhc2Mux, kCLOCK_FlexspiMux, kCLOCK_CsiMux, kCLOCK_LpspiMux, kCLOCK_TraceMux, \
444 kCLOCK_Sai1Mux, kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, kCLOCK_CanMux, kCLOCK_UartMux, \
445 kCLOCK_LcdifPreMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, kCLOCK_Flexio2Mux, \
446 }
447
448#define CLOCK_ROOT_NONE_PRE_DIV 0UL
449
450#define CLOCK_ROOT_DIV_TUPLE \
451 { \
452 {kCLOCK_NonePreDiv, kCLOCK_Usdhc1Div}, {kCLOCK_NonePreDiv, kCLOCK_Usdhc2Div}, \
453 {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_CsiDiv}, \
454 {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, \
455 {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div}, \
456 {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, \
457 {kCLOCK_NonePreDiv, kCLOCK_CanDiv}, {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, \
458 {kCLOCK_LcdifPreDiv, kCLOCK_LcdifDiv}, {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, \
459 {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, {kCLOCK_Flexio2PreDiv, kCLOCK_Flexio2Div}, \
460 }
461
462/*! @brief Clock name used to get clock frequency. */
463typedef enum _clock_name
464{
465 kCLOCK_CpuClk = 0x0U, /*!< CPU clock */
466 kCLOCK_AhbClk = 0x1U, /*!< AHB clock */
467 kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */
468 kCLOCK_IpgClk = 0x3U, /*!< IPG clock */
469 kCLOCK_PerClk = 0x4U, /*!< PER clock */
470
471 kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
472 kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */
473
474 kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */
475
476 kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */
477 kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */
478 kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */
479 kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */
480 kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */
481 kCLOCK_Usb1SwClk = 0x17U, /*!< USB1PLLSWCLK */
482 kCLOCK_Usb1Sw120MClk = 0x18U, /*!< USB1PLLSw120MCLK */
483 kCLOCK_Usb1Sw60MClk = 0x19U, /*!< USB1PLLSw60MCLK */
484 kCLOCK_Usb1Sw80MClk = 0x1AU, /*!< USB1PLLSw80MCLK */
485
486 kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */
487
488 kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */
489 kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */
490 kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */
491 kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */
492 kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */
493
494 kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */
495 kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */
496
497 kCLOCK_AudioPllClk = 0x15U, /*!< Audio PLLCLK. */
498 kCLOCK_VideoPllClk = 0x16U, /*!< Video PLLCLK. */
499 kCLOCK_NoneName = CLOCK_SOURCE_NONE, /*!< None Clock Name. */
500} clock_name_t;
501
502#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */
503#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */
504
505/*!
506 * @brief CCM CCGR gate control for each module independently.
507 */
508typedef enum _clock_ip_name
509{
510 kCLOCK_IpInvalid = -1,
511
512 /* CCM CCGR0 */
513 kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */
514 kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */
515 kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */
516 kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */
517 kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */
518 kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */
519 kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */
520 kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */
521 kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */
522 kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */
523 kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */
524 kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */
525 kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */
526 kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */
527 kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */
528 kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */
529
530 /* CCM CCGR1 */
531 kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */
532 kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */
533 kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */
534 kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */
535 kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */
536 kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */
537 kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */
538 kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */
539 kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */
540 kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */
541 kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */
542 kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */
543 kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */
544 kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */
545 kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */
546 kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */
547
548 /* CCM CCGR2 */
549 kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */
550 kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */
551 kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */
552 kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */
553 kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */
554 kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */
555 kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */
556 kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */
557 kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */
558 kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */
559 kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */
560 kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */
561 kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */
562 kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */
563 kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */
564 kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */
565
566 /* CCM CCGR3 */
567 kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */
568 kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */
569 kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */
570 kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */
571 kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */
572 kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */
573 kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */
574 kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */
575 kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */
576 kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */
577 kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */
578 kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */
579 kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */
580 kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */
581 kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */
582 kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */
583
584 /* CCM CCGR4 */
585 kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */
586 kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */
587 kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */
588 kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */
589 kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */
590 kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */
591 kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */
592 kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */
593 kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */
594 kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */
595 kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */
596 kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */
597 kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */
598 kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */
599 kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */
600
601 /* CCM CCGR5 */
602 kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */
603 kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */
604 kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */
605 kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */
606 kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */
607 kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */
608 kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */
609 kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */
610 kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */
611 kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */
612 kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */
613 kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */
614 kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */
615 kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */
616 kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */
617 kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */
618
619 /* CCM CCGR6 */
620 kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */
621 kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */
622 kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */
623 kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */
624 kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */
625 kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */
626 kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */
627 kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */
628 kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */
629 kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */
630 kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */
631 kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */
632 kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */
633 kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */
634 kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */
635 kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */
636
637} clock_ip_name_t;
638
639/*! @brief OSC 24M sorce select */
640typedef enum _clock_osc
641{
642 kCLOCK_RcOsc = 0U, /*!< On chip OSC. */
643 kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
644} clock_osc_t;
645
646/*! @brief Clock gate value */
647typedef enum _clock_gate_value
648{
649 kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */
650 kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */
651 kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */
652} clock_gate_value_t;
653
654/*! @brief System clock mode */
655typedef enum _clock_mode_t
656{
657 kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */
658 kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
659 kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
660} clock_mode_t;
661
662/*!
663 * @brief MUX control names for clock mux setting.
664 *
665 * These constants define the mux control names for clock mux setting.\n
666 * - 0:7: REG offset to CCM_BASE in bytes.
667 * - 8:15: Root clock setting bit field shift.
668 * - 16:31: Root clock setting bit field width.
669 */
670typedef enum _clock_mux
671{
672 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
673 CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
674 CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
675 CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */
676
677 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
678 CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
679 CCM_CBCDR_PERIPH_CLK_SEL_MASK,
680 CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */
681 kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
682 CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
683 CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
684 CCM_NO_BUSY_WAIT), /*!< semc mux name */
685 kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
686 CCM_CBCDR_SEMC_CLK_SEL_SHIFT,
687 CCM_CBCDR_SEMC_CLK_SEL_MASK,
688 CCM_NO_BUSY_WAIT), /*!< semc mux name */
689
690 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
691 CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
692 CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
693 CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */
694 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
695 CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
696 CCM_CBCMR_TRACE_CLK_SEL_MASK,
697 CCM_NO_BUSY_WAIT), /*!< trace mux name */
698 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
699 CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
700 CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
701 CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
702 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
703 CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
704 CCM_CBCMR_LPSPI_CLK_SEL_MASK,
705 CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
706
707 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
708 CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
709 CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
710 CCM_NO_BUSY_WAIT), /*!< flexspi mux name */
711 kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET,
712 CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT,
713 CCM_CSCMR1_USDHC2_CLK_SEL_MASK,
714 CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */
715 kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET,
716 CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT,
717 CCM_CSCMR1_USDHC1_CLK_SEL_MASK,
718 CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */
719 kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET,
720 CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
721 CCM_CSCMR1_SAI3_CLK_SEL_MASK,
722 CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
723 kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET,
724 CCM_CSCMR1_SAI2_CLK_SEL_SHIFT,
725 CCM_CSCMR1_SAI2_CLK_SEL_MASK,
726 CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
727 kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET,
728 CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
729 CCM_CSCMR1_SAI1_CLK_SEL_MASK,
730 CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
731 kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
732 CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
733 CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
734 CCM_NO_BUSY_WAIT), /*!< perclk mux name */
735
736 kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2_OFFSET,
737 CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT,
738 CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK,
739 CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */
740 kCLOCK_CanMux = CCM_TUPLE(CSCMR2_OFFSET,
741 CCM_CSCMR2_CAN_CLK_SEL_SHIFT,
742 CCM_CSCMR2_CAN_CLK_SEL_MASK,
743 CCM_NO_BUSY_WAIT), /*!< can mux name */
744
745 kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
746 CCM_CSCDR1_UART_CLK_SEL_SHIFT,
747 CCM_CSCDR1_UART_CLK_SEL_MASK,
748 CCM_NO_BUSY_WAIT), /*!< uart mux name */
749
750 kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET,
751 CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
752 CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
753 CCM_NO_BUSY_WAIT), /*!< spdif mux name */
754 kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET,
755 CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT,
756 CCM_CDCDR_FLEXIO1_CLK_SEL_MASK,
757 CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */
758
759 kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET,
760 CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
761 CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
762 CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
763 kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET,
764 CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT,
765 CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK,
766 CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */
767
768 kCLOCK_CsiMux = CCM_TUPLE(CSCDR3_OFFSET,
769 CCM_CSCDR3_CSI_CLK_SEL_SHIFT,
770 CCM_CSCDR3_CSI_CLK_SEL_MASK,
771 CCM_NO_BUSY_WAIT), /*!< csi mux name */
772} clock_mux_t;
773
774/*!
775 * @brief DIV control names for clock div setting.
776 *
777 * These constants define div control names for clock div setting.\n
778 * - 0:7: REG offset to CCM_BASE in bytes.
779 * - 8:15: Root clock setting bit field shift.
780 * - 16:31: Root clock setting bit field width.
781 */
782typedef enum _clock_div
783{
784 kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET,
785 CCM_CACRR_ARM_PODF_SHIFT,
786 CCM_CACRR_ARM_PODF_MASK,
787 CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
788
789 kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
790 CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
791 CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
792 CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */
793 kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
794 CCM_CBCDR_SEMC_PODF_SHIFT,
795 CCM_CBCDR_SEMC_PODF_MASK,
796 CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */
797 kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET,
798 CCM_CBCDR_AHB_PODF_SHIFT,
799 CCM_CBCDR_AHB_PODF_MASK,
800 CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
801 kCLOCK_IpgDiv = CCM_TUPLE(
802 CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
803
804 kCLOCK_LpspiDiv = CCM_TUPLE(
805 CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
806 kCLOCK_LcdifDiv = CCM_TUPLE(
807 CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */
808
809 kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
810 CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
811 CCM_CSCMR1_FLEXSPI_PODF_MASK,
812 CCM_NO_BUSY_WAIT), /*!< flexspi div name */
813 kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET,
814 CCM_CSCMR1_PERCLK_PODF_SHIFT,
815 CCM_CSCMR1_PERCLK_PODF_MASK,
816 CCM_NO_BUSY_WAIT), /*!< perclk div name */
817
818 kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET,
819 CCM_CSCMR2_CAN_CLK_PODF_SHIFT,
820 CCM_CSCMR2_CAN_CLK_PODF_MASK,
821 CCM_NO_BUSY_WAIT), /*!< can div name */
822
823 kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET,
824 CCM_CSCDR1_TRACE_PODF_SHIFT,
825 CCM_CSCDR1_TRACE_PODF_MASK,
826 CCM_NO_BUSY_WAIT), /*!< trace div name */
827 kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET,
828 CCM_CSCDR1_USDHC2_PODF_SHIFT,
829 CCM_CSCDR1_USDHC2_PODF_MASK,
830 CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */
831 kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET,
832 CCM_CSCDR1_USDHC1_PODF_SHIFT,
833 CCM_CSCDR1_USDHC1_PODF_MASK,
834 CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */
835 kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET,
836 CCM_CSCDR1_UART_CLK_PODF_SHIFT,
837 CCM_CSCDR1_UART_CLK_PODF_MASK,
838 CCM_NO_BUSY_WAIT), /*!< uart div name */
839
840 kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET,
841 CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT,
842 CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK,
843 CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */
844 kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
845 CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
846 CCM_CS1CDR_SAI3_CLK_PRED_MASK,
847 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
848 kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET,
849 CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
850 CCM_CS1CDR_SAI3_CLK_PODF_MASK,
851 CCM_NO_BUSY_WAIT), /*!< sai3 div name */
852 kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
853 CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT,
854 CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK,
855 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
856 kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
857 CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
858 CCM_CS1CDR_SAI1_CLK_PRED_MASK,
859 CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */
860 kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET,
861 CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
862 CCM_CS1CDR_SAI1_CLK_PODF_MASK,
863 CCM_NO_BUSY_WAIT), /*!< sai1 div name */
864
865 kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
866 CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
867 CCM_CS2CDR_SAI2_CLK_PRED_MASK,
868 CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */
869 kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET,
870 CCM_CS2CDR_SAI2_CLK_PODF_SHIFT,
871 CCM_CS2CDR_SAI2_CLK_PODF_MASK,
872 CCM_NO_BUSY_WAIT), /*!< sai2 div name */
873
874 kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
875 CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
876 CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
877 CCM_NO_BUSY_WAIT), /*!< spdif pre div name */
878 kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
879 CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
880 CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
881 CCM_NO_BUSY_WAIT), /*!< spdif div name */
882 kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR_OFFSET,
883 CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT,
884 CCM_CDCDR_FLEXIO1_CLK_PRED_MASK,
885 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
886 kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET,
887 CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT,
888 CCM_CDCDR_FLEXIO1_CLK_PODF_MASK,
889 CCM_NO_BUSY_WAIT), /*!< flexio1 div name */
890
891 kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
892 CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
893 CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
894 CCM_NO_BUSY_WAIT), /*!< lpi2c div name */
895 kCLOCK_LcdifPreDiv = CCM_TUPLE(CSCDR2_OFFSET,
896 CCM_CSCDR2_LCDIF_PRED_SHIFT,
897 CCM_CSCDR2_LCDIF_PRED_MASK,
898 CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */
899
900 kCLOCK_CsiDiv = CCM_TUPLE(
901 CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */
902
903 kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV, /*!< None Pre div. */
904} clock_div_t;
905
906/*! @brief USB clock source definition. */
907typedef enum _clock_usb_src
908{
909 kCLOCK_Usb480M = 0, /*!< Use 480M. */
910 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
911 care the clock source. */
912} clock_usb_src_t;
913
914/*! @brief Source of the USB HS PHY. */
915typedef enum _clock_usb_phy_src
916{
917 kCLOCK_Usbphy480M = 0, /*!< Use 480M. */
918} clock_usb_phy_src_t;
919
920/*!@brief PLL clock source, bypass cloco source also */
921enum _clock_pll_clk_src
922{
923 kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
924 kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
925};
926
927/*! @brief PLL configuration for ARM */
928typedef struct _clock_arm_pll_config
929{
930 uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */
931 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
932} clock_arm_pll_config_t;
933
934/*! @brief PLL configuration for USB */
935typedef struct _clock_usb_pll_config
936{
937 uint8_t loopDivider; /*!< PLL loop divider.
938 0 - Fout=Fref*20;
939 1 - Fout=Fref*22 */
940 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
941
942} clock_usb_pll_config_t;
943
944/*! @brief PLL configuration for System */
945typedef struct _clock_sys_pll_config
946{
947 uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M).
948 0 - Fout=Fref*20;
949 1 - Fout=Fref*22 */
950 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
951 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
952 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
953 uint16_t ss_stop; /*!< Stop value to get frequency change. */
954 uint8_t ss_enable; /*!< Enable spread spectrum modulation */
955 uint16_t ss_step; /*!< Step value to get frequency change step. */
956
957} clock_sys_pll_config_t;
958
959/*! @brief PLL configuration for AUDIO and VIDEO */
960typedef struct _clock_audio_pll_config
961{
962 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
963 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
964 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
965 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
966 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
967} clock_audio_pll_config_t;
968
969/*! @brief PLL configuration for AUDIO and VIDEO */
970typedef struct _clock_video_pll_config
971{
972 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
973 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
974 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
975 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
976 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
977
978} clock_video_pll_config_t;
979
980/*! @brief PLL configuration for ENET */
981typedef struct _clock_enet_pll_config
982{
983 bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
984
985 bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
986 uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock.
987 b00 25MHz
988 b01 50MHz
989 b10 100MHz (not 50% duty cycle)
990 b11 125MHz */
991 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
992
993} clock_enet_pll_config_t;
994
995/*! @brief PLL name */
996typedef enum _clock_pll
997{
998 kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */
999 kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
1000 kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
1001 kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
1002 kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */
1003
1004 kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */
1005
1006 kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet1 */
1007
1008 kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */
1009
1010} clock_pll_t;
1011
1012/*! @brief PLL PFD name */
1013typedef enum _clock_pfd
1014{
1015 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
1016 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
1017 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
1018 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
1019} clock_pfd_t;
1020
1021/*!
1022 * @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
1023 */
1024typedef enum _clock_output1_selection
1025{
1026 kCLOCK_OutputPllUsb1 = 0U, /*!< Selects USB1 PLL clock(Divided by 2) output. */
1027 kCLOCK_OutputPllSys = 1U, /*!< Selects SYS PLL clock(Divided by 2) output. */
1028 kCLOCK_OutputPllVideo = 3U, /*!< Selects Video PLL clock(Divided by 2) output. */
1029 kCLOCK_OutputSemcClk = 5U, /*!< Selects semc clock root output. */
1030 kCLOCK_OutputLcdifPixClk = 0xAU, /*!< Selects Lcdif pix clock root output. */
1031 kCLOCK_OutputAhbClk = 0xBU, /*!< Selects AHB clock root output. */
1032 kCLOCK_OutputIpgClk = 0xCU, /*!< Selects IPG clock root output. */
1033 kCLOCK_OutputPerClk = 0xDU, /*!< Selects PERCLK clock root output. */
1034 kCLOCK_OutputCkilSyncClk = 0xEU, /*!< Selects Ckil clock root output. */
1035 kCLOCK_OutputPll4MainClk = 0xFU, /*!< Selects PLL4 main clock output. */
1036 kCLOCK_DisableClockOutput1 = 0x10U, /*!< Disables CLKO1. */
1037} clock_output1_selection_t;
1038
1039/*!
1040 * @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
1041 *
1042 */
1043typedef enum _clock_output2_selection
1044{
1045 kCLOCK_OutputUsdhc1Clk = 3U, /*!< Selects USDHC1 clock root output. */
1046 kCLOCK_OutputLpi2cClk = 6U, /*!< Selects LPI2C clock root output. */
1047 kCLOCK_OutputCsiClk = 0xBU, /*!< Selects CSI clock root output. */
1048 kCLOCK_OutputOscClk = 0xEU, /*!< Selects OSC output. */
1049 kCLOCK_OutputUsdhc2Clk = 0x11U, /*!< Selects USDHC2 clock root output. */
1050 kCLOCK_OutputSai1Clk = 0x12U, /*!< Selects SAI1 clock root output. */
1051 kCLOCK_OutputSai2Clk = 0x13U, /*!< Selects SAI2 clock root output. */
1052 kCLOCK_OutputSai3Clk = 0x14U, /*!< Selects SAI3 clock root output. */
1053 kCLOCK_OutputCanClk = 0x17U, /*!< Selects CAN clock root output. */
1054 kCLOCK_OutputFlexspiClk = 0x1BU, /*!< Selects FLEXSPI clock root output. */
1055 kCLOCK_OutputUartClk = 0x1CU, /*!< Selects UART clock root output. */
1056 kCLOCK_OutputSpdif0Clk = 0x1DU, /*!< Selects SPDIF0 clock root output. */
1057 kCLOCK_DisableClockOutput2 = 0x1FU, /*!< Disables CLKO2. */
1058} clock_output2_selection_t;
1059
1060/*!
1061 * @brief The enumerator of clock output's divider.
1062 */
1063typedef enum _clock_output_divider
1064{
1065 kCLOCK_DivideBy1 = 0U, /*!< Output clock divided by 1. */
1066 kCLOCK_DivideBy2, /*!< Output clock divided by 2. */
1067 kCLOCK_DivideBy3, /*!< Output clock divided by 3. */
1068 kCLOCK_DivideBy4, /*!< Output clock divided by 4. */
1069 kCLOCK_DivideBy5, /*!< Output clock divided by 5. */
1070 kCLOCK_DivideBy6, /*!< Output clock divided by 6. */
1071 kCLOCK_DivideBy7, /*!< Output clock divided by 7. */
1072 kCLOCK_DivideBy8, /*!< Output clock divided by 8. */
1073} clock_output_divider_t;
1074
1075/*!
1076 * @brief The enumerator of clock root.
1077 */
1078typedef enum _clock_root
1079{
1080 kCLOCK_Usdhc1ClkRoot = 0U, /*!< USDHC1 clock root. */
1081 kCLOCK_Usdhc2ClkRoot, /*!< USDHC2 clock root. */
1082 kCLOCK_FlexspiClkRoot, /*!< FLEXSPI clock root. */
1083 kCLOCK_CsiClkRoot, /*!< CSI clock root. */
1084 kCLOCK_LpspiClkRoot, /*!< LPSPI clock root. */
1085 kCLOCK_TraceClkRoot, /*!< Trace clock root. */
1086 kCLOCK_Sai1ClkRoot, /*!< SAI1 clock root. */
1087 kCLOCK_Sai2ClkRoot, /*!< SAI2 clock root. */
1088 kCLOCK_Sai3ClkRoot, /*!< SAI3 clock root. */
1089 kCLOCK_Lpi2cClkRoot, /*!< LPI2C clock root. */
1090 kCLOCK_CanClkRoot, /*!< CAN clock root. */
1091 kCLOCK_UartClkRoot, /*!< UART clock root. */
1092 kCLOCK_LcdifClkRoot, /*!< LCD clock root. */
1093 kCLOCK_SpdifClkRoot, /*!< SPDIF clock root. */
1094 kCLOCK_Flexio1ClkRoot, /*!< FLEXIO1 clock root. */
1095 kCLOCK_Flexio2ClkRoot, /*!< FLEXIO2 clock root. */
1096} clock_root_t;
1097
1098/*******************************************************************************
1099 * API
1100 ******************************************************************************/
1101
1102#if defined(__cplusplus)
1103extern "C" {
1104#endif /* __cplusplus */
1105
1106/*!
1107 * @brief Set CCM MUX node to certain value.
1108 *
1109 * @param mux Which mux node to set, see \ref clock_mux_t.
1110 * @param value Clock mux value to set, different mux has different value range.
1111 */
1112static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
1113{
1114 uint32_t busyShift;
1115
1116 busyShift = (uint32_t)CCM_TUPLE_BUSY_SHIFT(mux);
1117 CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
1118 (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
1119
1120 assert(busyShift <= CCM_NO_BUSY_WAIT);
1121
1122 /* Clock switch need Handshake? */
1123 if (CCM_NO_BUSY_WAIT != busyShift)
1124 {
1125 /* Wait until CCM internal handshake finish. */
1126 while ((CCM->CDHIPR & ((1UL << busyShift))) != 0UL)
1127 {
1128 }
1129 }
1130}
1131
1132/*!
1133 * @brief Get CCM MUX value.
1134 *
1135 * @param mux Which mux node to get, see \ref clock_mux_t.
1136 * @return Clock mux value.
1137 */
1138static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
1139{
1140 return (((uint32_t)(CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux))) >> CCM_TUPLE_SHIFT(mux));
1141}
1142
1143/*!
1144 * @brief Set CCM DIV node to certain value.
1145 *
1146 * @param divider Which div node to set, see \ref clock_div_t.
1147 * @param value Clock div value to set, different divider has different value range.
1148 */
1149static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
1150{
1151 uint32_t busyShift;
1152
1153 busyShift = CCM_TUPLE_BUSY_SHIFT(divider);
1154 CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
1155 (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
1156
1157 assert(busyShift <= CCM_NO_BUSY_WAIT);
1158
1159 /* Clock switch need Handshake? */
1160 if (CCM_NO_BUSY_WAIT != busyShift)
1161 {
1162 /* Wait until CCM internal handshake finish. */
1163 while ((CCM->CDHIPR & ((uint32_t)(1UL << busyShift))) != 0UL)
1164 {
1165 }
1166 }
1167}
1168
1169/*!
1170 * @brief Get CCM DIV node value.
1171 *
1172 * @param divider Which div node to get, see \ref clock_div_t.
1173 */
1174static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
1175{
1176 return ((uint32_t)(CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
1177}
1178
1179/*!
1180 * @brief Control the clock gate for specific IP.
1181 *
1182 * @param name Which clock to enable, see \ref clock_ip_name_t.
1183 * @param value Clock gate value to set, see \ref clock_gate_value_t.
1184 */
1185static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
1186{
1187 uint32_t index = ((uint32_t)name) >> 8U;
1188 uint32_t shift = ((uint32_t)name) & 0x1FU;
1189 volatile uint32_t *reg;
1190
1191 assert(index <= 6UL);
1192
1193 reg = (volatile uint32_t *)(&(((volatile uint32_t *)&CCM->CCGR0)[index]));
1194 *reg = ((*reg) & ~((uint32_t)(3UL << shift))) | (((uint32_t)value) << shift);
1195}
1196
1197/*!
1198 * @brief Enable the clock for specific IP.
1199 *
1200 * @param name Which clock to enable, see \ref clock_ip_name_t.
1201 */
1202static inline void CLOCK_EnableClock(clock_ip_name_t name)
1203{
1204 CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
1205}
1206
1207/*!
1208 * @brief Disable the clock for specific IP.
1209 *
1210 * @param name Which clock to disable, see \ref clock_ip_name_t.
1211 */
1212static inline void CLOCK_DisableClock(clock_ip_name_t name)
1213{
1214 CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
1215}
1216
1217/*!
1218 * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal.
1219 *
1220 * @param mode Which mode to enter, see \ref clock_mode_t.
1221 */
1222static inline void CLOCK_SetMode(clock_mode_t mode)
1223{
1224 CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode);
1225}
1226
1227/*!
1228 * @brief Gets the OSC clock frequency.
1229 *
1230 * This function will return the external XTAL OSC frequency if it is selected as the source of OSC,
1231 * otherwise internal 24MHz RC OSC frequency will be returned.
1232 *
1233 * @return Clock frequency; If the clock is invalid, returns 0.
1234 */
1235static inline uint32_t CLOCK_GetOscFreq(void)
1236{
1237 return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
1238}
1239
1240/*!
1241 * @brief Gets the AHB clock frequency.
1242 *
1243 * @return The AHB clock frequency value in hertz.
1244 */
1245uint32_t CLOCK_GetAhbFreq(void);
1246
1247/*!
1248 * @brief Gets the SEMC clock frequency.
1249 *
1250 * @return The SEMC clock frequency value in hertz.
1251 */
1252uint32_t CLOCK_GetSemcFreq(void);
1253
1254/*!
1255 * @brief Gets the IPG clock frequency.
1256 *
1257 * @return The IPG clock frequency value in hertz.
1258 */
1259uint32_t CLOCK_GetIpgFreq(void);
1260
1261/*!
1262 * @brief Gets the PER clock frequency.
1263 *
1264 * @return The PER clock frequency value in hertz.
1265 */
1266uint32_t CLOCK_GetPerClkFreq(void);
1267
1268/*!
1269 * @brief Gets the clock frequency for a specific clock name.
1270 *
1271 * This function checks the current clock configurations and then calculates
1272 * the clock frequency for a specific clock name defined in clock_name_t.
1273 *
1274 * @param name Clock names defined in clock_name_t
1275 * @return Clock frequency value in hertz
1276 */
1277uint32_t CLOCK_GetFreq(clock_name_t name);
1278
1279/*!
1280 * @brief Get the CCM CPU/core/system frequency.
1281 *
1282 * @return Clock frequency; If the clock is invalid, returns 0.
1283 */
1284static inline uint32_t CLOCK_GetCpuClkFreq(void)
1285{
1286 return CLOCK_GetFreq(kCLOCK_CpuClk);
1287}
1288
1289/*!
1290 * @brief Gets the frequency of selected clock root.
1291 *
1292 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1293 * @return The frequency of selected clock root.
1294 */
1295uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1296
1297/*!
1298 * @name OSC operations
1299 * @{
1300 */
1301
1302/*!
1303 * @brief Initialize the external 24MHz clock.
1304 *
1305 * This function supports two modes:
1306 * 1. Use external crystal oscillator.
1307 * 2. Bypass the external crystal oscillator, using input source clock directly.
1308 *
1309 * After this function, please call CLOCK_SetXtal0Freq to inform clock driver
1310 * the external clock frequency.
1311 *
1312 * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
1313 * @note This device does not support bypass external crystal oscillator, so
1314 * the input parameter should always be false.
1315 */
1316void CLOCK_InitExternalClk(bool bypassXtalOsc);
1317
1318/*!
1319 * @brief Deinitialize the external 24MHz clock.
1320 *
1321 * This function disables the external 24MHz clock.
1322 *
1323 * After this function, please call CLOCK_SetXtal0Freq to set external clock
1324 * frequency to 0.
1325 */
1326void CLOCK_DeinitExternalClk(void);
1327
1328/*!
1329 * @brief Switch the OSC.
1330 *
1331 * This function switches the OSC source for SoC.
1332 *
1333 * @param osc OSC source to switch to.
1334 */
1335void CLOCK_SwitchOsc(clock_osc_t osc);
1336
1337/*!
1338 * @brief Gets the RTC clock frequency.
1339 *
1340 * @return Clock frequency; If the clock is invalid, returns 0.
1341 */
1342static inline uint32_t CLOCK_GetRtcFreq(void)
1343{
1344 return 32768U;
1345}
1346
1347/*!
1348 * @brief Set the XTAL (24M OSC) frequency based on board setting.
1349 *
1350 * @param freq The XTAL input clock frequency in Hz.
1351 */
1352static inline void CLOCK_SetXtalFreq(uint32_t freq)
1353{
1354 g_xtalFreq = freq;
1355}
1356
1357/*!
1358 * @brief Set the RTC XTAL (32K OSC) frequency based on board setting.
1359 *
1360 * @param freq The RTC XTAL input clock frequency in Hz.
1361 */
1362static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
1363{
1364 g_rtcXtalFreq = freq;
1365}
1366
1367/*!
1368 * @brief Initialize the RC oscillator 24MHz clock.
1369 */
1370void CLOCK_InitRcOsc24M(void);
1371
1372/*!
1373 * @brief Power down the RCOSC 24M clock.
1374 */
1375void CLOCK_DeinitRcOsc24M(void);
1376/* @} */
1377
1378/*! @brief Enable USB HS clock.
1379 *
1380 * This function only enables the access to USB HS prepheral, upper layer
1381 * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1382 * clock to use USB HS.
1383 *
1384 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1385 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1386 * @retval true The clock is set successfully.
1387 * @retval false The clock source is invalid to get proper USB HS clock.
1388 */
1389bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
1390
1391/*! @brief Enable USB HS clock.
1392 *
1393 * This function only enables the access to USB HS prepheral, upper layer
1394 * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1395 * clock to use USB HS.
1396 *
1397 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1398 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1399 * @retval true The clock is set successfully.
1400 * @retval false The clock source is invalid to get proper USB HS clock.
1401 */
1402bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq);
1403
1404/* @} */
1405
1406/*!
1407 * @name PLL/PFD operations
1408 * @{
1409 */
1410/*!
1411 * @brief PLL bypass setting
1412 *
1413 * @param base CCM_ANALOG base pointer.
1414 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1415 * @param bypass Bypass the PLL.
1416 * - true: Bypass the PLL.
1417 * - false:Not bypass the PLL.
1418 */
1419static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
1420{
1421 if (bypass)
1422 {
1423 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1424 }
1425 else
1426 {
1427 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1428 }
1429}
1430
1431/*!
1432 * @brief Check if PLL is bypassed
1433 *
1434 * @param base CCM_ANALOG base pointer.
1435 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1436 * @return PLL bypass status.
1437 * - true: The PLL is bypassed.
1438 * - false: The PLL is not bypassed.
1439 */
1440static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
1441{
1442 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
1443}
1444
1445/*!
1446 * @brief Check if PLL is enabled
1447 *
1448 * @param base CCM_ANALOG base pointer.
1449 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1450 * @return PLL bypass status.
1451 * - true: The PLL is enabled.
1452 * - false: The PLL is not enabled.
1453 */
1454static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
1455{
1456 return ((CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll))) != 0U);
1457}
1458
1459/*!
1460 * @brief PLL bypass clock source setting.
1461 * Note: change the bypass clock source also change the pll reference clock source.
1462 *
1463 * @param base CCM_ANALOG base pointer.
1464 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1465 * @param src Bypass clock source, reference _clock_pll_bypass_clk_src.
1466 */
1467static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
1468{
1469 CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src;
1470}
1471
1472/*!
1473 * @brief Get PLL bypass clock value, it is PLL reference clock actually.
1474 * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0
1475 * will be returned.
1476 * @param base CCM_ANALOG base pointer.
1477 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1478 * @retval bypass reference clock frequency value.
1479 */
1480static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
1481{
1482 return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >>
1483 CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
1484 CLOCK_GetOscFreq() :
1485 CLKPN_FREQ;
1486}
1487
1488/*!
1489 * @brief Initialize the ARM PLL.
1490 *
1491 * This function initialize the ARM PLL with specific settings
1492 *
1493 * @param config configuration to set to PLL.
1494 */
1495void CLOCK_InitArmPll(const clock_arm_pll_config_t *config);
1496
1497/*!
1498 * @brief De-initialize the ARM PLL.
1499 */
1500void CLOCK_DeinitArmPll(void);
1501
1502/*!
1503 * @brief Initialize the System PLL.
1504 *
1505 * This function initializes the System PLL with specific settings
1506 *
1507 * @param config Configuration to set to PLL.
1508 */
1509void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1510
1511/*!
1512 * @brief De-initialize the System PLL.
1513 */
1514void CLOCK_DeinitSysPll(void);
1515
1516/*!
1517 * @brief Initialize the USB1 PLL.
1518 *
1519 * This function initializes the USB1 PLL with specific settings
1520 *
1521 * @param config Configuration to set to PLL.
1522 */
1523void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config);
1524
1525/*!
1526 * @brief Deinitialize the USB1 PLL.
1527 */
1528void CLOCK_DeinitUsb1Pll(void);
1529
1530/*!
1531 * @brief Initialize the USB2 PLL.
1532 *
1533 * This function initializes the USB2 PLL with specific settings
1534 *
1535 * @param config Configuration to set to PLL.
1536 */
1537void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config);
1538
1539/*!
1540 * @brief Deinitialize the USB2 PLL.
1541 */
1542void CLOCK_DeinitUsb2Pll(void);
1543
1544/*!
1545 * @brief Initializes the Audio PLL.
1546 *
1547 * This function initializes the Audio PLL with specific settings
1548 *
1549 * @param config Configuration to set to PLL.
1550 */
1551void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1552
1553/*!
1554 * @brief De-initialize the Audio PLL.
1555 */
1556void CLOCK_DeinitAudioPll(void);
1557
1558/*!
1559 * @brief Initialize the video PLL.
1560 *
1561 * This function configures the Video PLL with specific settings
1562 *
1563 * @param config configuration to set to PLL.
1564 */
1565void CLOCK_InitVideoPll(const clock_video_pll_config_t *config);
1566
1567/*!
1568 * @brief De-initialize the Video PLL.
1569 */
1570void CLOCK_DeinitVideoPll(void);
1571/*!
1572 * @brief Initialize the ENET PLL.
1573 *
1574 * This function initializes the ENET PLL with specific settings.
1575 *
1576 * @param config Configuration to set to PLL.
1577 */
1578void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config);
1579
1580/*!
1581 * @brief Deinitialize the ENET PLL.
1582 *
1583 * This function disables the ENET PLL.
1584 */
1585void CLOCK_DeinitEnetPll(void);
1586
1587/*!
1588 * @brief Get current PLL output frequency.
1589 *
1590 * This function get current output frequency of specific PLL
1591 *
1592 * @param pll pll name to get frequency.
1593 * @return The PLL output frequency in hertz.
1594 */
1595uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
1596
1597/*!
1598 * @brief Initialize the System PLL PFD.
1599 *
1600 * This function initializes the System PLL PFD. During new value setting,
1601 * the clock output is disabled to prevent glitch.
1602 *
1603 * @param pfd Which PFD clock to enable.
1604 * @param pfdFrac The PFD FRAC value.
1605 * @note It is recommended that PFD settings are kept between 12-35.
1606 */
1607void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
1608
1609/*!
1610 * @brief De-initialize the System PLL PFD.
1611 *
1612 * This function disables the System PLL PFD.
1613 *
1614 * @param pfd Which PFD clock to disable.
1615 */
1616void CLOCK_DeinitSysPfd(clock_pfd_t pfd);
1617
1618/*!
1619 * @brief Initialize the USB1 PLL PFD.
1620 *
1621 * This function initializes the USB1 PLL PFD. During new value setting,
1622 * the clock output is disabled to prevent glitch.
1623 *
1624 * @param pfd Which PFD clock to enable.
1625 * @param pfdFrac The PFD FRAC value.
1626 * @note It is recommended that PFD settings are kept between 12-35.
1627 */
1628void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
1629
1630/*!
1631 * @brief De-initialize the USB1 PLL PFD.
1632 *
1633 * This function disables the USB1 PLL PFD.
1634 *
1635 * @param pfd Which PFD clock to disable.
1636 */
1637void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd);
1638
1639/*!
1640 * @brief Get current System PLL PFD output frequency.
1641 *
1642 * This function get current output frequency of specific System PLL PFD
1643 *
1644 * @param pfd pfd name to get frequency.
1645 * @return The PFD output frequency in hertz.
1646 */
1647uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
1648
1649/*!
1650 * @brief Get current USB1 PLL PFD output frequency.
1651 *
1652 * This function get current output frequency of specific USB1 PLL PFD
1653 *
1654 * @param pfd pfd name to get frequency.
1655 * @return The PFD output frequency in hertz.
1656 */
1657uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
1658
1659/*! @brief Enable USB HS PHY PLL clock.
1660 *
1661 * This function enables the internal 480MHz USB PHY PLL clock.
1662 *
1663 * @param src USB HS PHY PLL clock source.
1664 * @param freq The frequency specified by src.
1665 * @retval true The clock is set successfully.
1666 * @retval false The clock source is invalid to get proper USB HS clock.
1667 */
1668bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1669
1670/*! @brief Disable USB HS PHY PLL clock.
1671 *
1672 * This function disables USB HS PHY PLL clock.
1673 */
1674void CLOCK_DisableUsbhs0PhyPllClock(void);
1675
1676/*! @brief Enable USB HS PHY PLL clock.
1677 *
1678 * This function enables the internal 480MHz USB PHY PLL clock.
1679 *
1680 * @param src USB HS PHY PLL clock source.
1681 * @param freq The frequency specified by src.
1682 * @retval true The clock is set successfully.
1683 * @retval false The clock source is invalid to get proper USB HS clock.
1684 */
1685bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1686
1687/*! @brief Disable USB HS PHY PLL clock.
1688 *
1689 * This function disables USB HS PHY PLL clock.
1690 */
1691void CLOCK_DisableUsbhs1PhyPllClock(void);
1692
1693/* @} */
1694
1695/*!
1696 * @name Clock Output Inferfaces
1697 * @{
1698 */
1699
1700/*!
1701 * @brief Set the clock source and the divider of the clock output1.
1702 *
1703 * @param selection The clock source to be output, please refer to @ref clock_output1_selection_t.
1704 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1705 */
1706void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider);
1707
1708/*!
1709 * @brief Set the clock source and the divider of the clock output2.
1710 *
1711 * @param selection The clock source to be output, please refer to @ref clock_output2_selection_t.
1712 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1713 */
1714void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider);
1715
1716/*!
1717 * @brief Get the frequency of clock output1 clock signal.
1718 *
1719 * @return The frequency of clock output1 clock signal.
1720 */
1721uint32_t CLOCK_GetClockOutCLKO1Freq(void);
1722
1723/*!
1724 * @brief Get the frequency of clock output2 clock signal.
1725 *
1726 * @return The frequency of clock output2 clock signal.
1727 */
1728uint32_t CLOCK_GetClockOutClkO2Freq(void);
1729
1730/*! @} */
1731
1732#if defined(__cplusplus)
1733}
1734#endif /* __cplusplus */
1735
1736/*! @} */
1737
1738#endif /* _FSL_CLOCK_H_ */
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