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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1052/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1052/project_template/clock_config.c
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+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1052/project_template/clock_config.c
@@ -0,0 +1,471 @@
1/*
2 * Copyright 2017-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v5.0
26processor: MIMXRT1052xxxxB
27package_id: MIMXRT1052DVL6B
28mcu_data: ksdk2_0
29processor_version: 0.0.0
30board: IMXRT1050-EVKB
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
63- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
64- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
65- {id: CLK_1M.outFreq, value: 1 MHz}
66- {id: CLK_24M.outFreq, value: 24 MHz}
67- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
68- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
69- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
70- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
71- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
72- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
73- {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
74- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
75- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
76- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
77- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
78- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
79- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
80- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
81- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
82- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
83- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
84- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
85- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
86- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
87- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
88- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
89- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
90- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
91- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
92- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
93- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
94- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
95- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
96- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
97- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
98- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
99- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
100settings:
101- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
102- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
103- {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
104- {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
105- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
106- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
107- {id: CCM.SEMC_PODF.scale, value: '8'}
108- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
109- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
110- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
111- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
112- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
113- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
114- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
115- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
116- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
117- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
118- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
119- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
120- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
121- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
122- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
123- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
124- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
125- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
126- {id: CCM_ANALOG.PLL4.denom, value: '50'}
127- {id: CCM_ANALOG.PLL4.div, value: '47'}
128- {id: CCM_ANALOG.PLL5.denom, value: '1'}
129- {id: CCM_ANALOG.PLL5.div, value: '40'}
130- {id: CCM_ANALOG.PLL5.num, value: '0'}
131- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
132- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
133sources:
134- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
135- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
136 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
137
138/*******************************************************************************
139 * Variables for BOARD_BootClockRUN configuration
140 ******************************************************************************/
141const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
142 .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
143 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
144};
145const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
146 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
147 .numerator = 0, /* 30 bit numerator of fractional loop divider */
148 .denominator = 1, /* 30 bit denominator of fractional loop divider */
149 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
150};
151const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
152 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
153 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
154};
155/*******************************************************************************
156 * Code for BOARD_BootClockRUN configuration
157 ******************************************************************************/
158void BOARD_BootClockRUN(void)
159{
160 /* Init RTC OSC clock frequency. */
161 CLOCK_SetRtcXtalFreq(32768U);
162 /* Enable 1MHz clock output. */
163 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
164 /* Use free 1MHz clock output. */
165 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
166 /* Set XTAL 24MHz clock frequency. */
167 CLOCK_SetXtalFreq(24000000U);
168 /* Enable XTAL 24MHz clock source. */
169 CLOCK_InitExternalClk(0);
170 /* Enable internal RC. */
171 CLOCK_InitRcOsc24M();
172 /* Switch clock source to external OSC. */
173 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
174 /* Set Oscillator ready counter value. */
175 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
176 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
177 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
178 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
179 /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
180 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
181 /* Waiting for DCDC_STS_DC_OK bit is asserted */
182 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
183 {
184 }
185 /* Set AHB_PODF. */
186 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
187 /* Disable IPG clock gate. */
188 CLOCK_DisableClock(kCLOCK_Adc1);
189 CLOCK_DisableClock(kCLOCK_Adc2);
190 CLOCK_DisableClock(kCLOCK_Xbar1);
191 CLOCK_DisableClock(kCLOCK_Xbar2);
192 CLOCK_DisableClock(kCLOCK_Xbar3);
193 /* Set IPG_PODF. */
194 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
195 /* Set ARM_PODF. */
196 CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
197 /* Set PERIPH_CLK2_PODF. */
198 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
199 /* Disable PERCLK clock gate. */
200 CLOCK_DisableClock(kCLOCK_Gpt1);
201 CLOCK_DisableClock(kCLOCK_Gpt1S);
202 CLOCK_DisableClock(kCLOCK_Gpt2);
203 CLOCK_DisableClock(kCLOCK_Gpt2S);
204 CLOCK_DisableClock(kCLOCK_Pit);
205 /* Set PERCLK_PODF. */
206 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
207 /* Disable USDHC1 clock gate. */
208 CLOCK_DisableClock(kCLOCK_Usdhc1);
209 /* Set USDHC1_PODF. */
210 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
211 /* Set Usdhc1 clock source. */
212 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
213 /* Disable USDHC2 clock gate. */
214 CLOCK_DisableClock(kCLOCK_Usdhc2);
215 /* Set USDHC2_PODF. */
216 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
217 /* Set Usdhc2 clock source. */
218 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
219/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
220 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
221 * unchanged.
222 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
223#ifndef SKIP_SYSCLK_INIT
224 /* Disable Semc clock gate. */
225 CLOCK_DisableClock(kCLOCK_Semc);
226 /* Set SEMC_PODF. */
227 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
228 /* Set Semc alt clock source. */
229 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
230 /* Set Semc clock source. */
231 CLOCK_SetMux(kCLOCK_SemcMux, 0);
232#endif
233/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
234 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
235 * unchanged.
236 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
237#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
238 /* Disable Flexspi clock gate. */
239 CLOCK_DisableClock(kCLOCK_FlexSpi);
240 /* Set FLEXSPI_PODF. */
241 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 2);
242 /* Set Flexspi clock source. */
243 CLOCK_SetMux(kCLOCK_FlexspiMux, 1);
244#endif
245 /* Disable CSI clock gate. */
246 CLOCK_DisableClock(kCLOCK_Csi);
247 /* Set CSI_PODF. */
248 CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
249 /* Set Csi clock source. */
250 CLOCK_SetMux(kCLOCK_CsiMux, 0);
251 /* Disable LPSPI clock gate. */
252 CLOCK_DisableClock(kCLOCK_Lpspi1);
253 CLOCK_DisableClock(kCLOCK_Lpspi2);
254 CLOCK_DisableClock(kCLOCK_Lpspi3);
255 CLOCK_DisableClock(kCLOCK_Lpspi4);
256 /* Set LPSPI_PODF. */
257 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
258 /* Set Lpspi clock source. */
259 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
260 /* Disable TRACE clock gate. */
261 CLOCK_DisableClock(kCLOCK_Trace);
262 /* Set TRACE_PODF. */
263 CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
264 /* Set Trace clock source. */
265 CLOCK_SetMux(kCLOCK_TraceMux, 2);
266 /* Disable SAI1 clock gate. */
267 CLOCK_DisableClock(kCLOCK_Sai1);
268 /* Set SAI1_CLK_PRED. */
269 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
270 /* Set SAI1_CLK_PODF. */
271 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
272 /* Set Sai1 clock source. */
273 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
274 /* Disable SAI2 clock gate. */
275 CLOCK_DisableClock(kCLOCK_Sai2);
276 /* Set SAI2_CLK_PRED. */
277 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
278 /* Set SAI2_CLK_PODF. */
279 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
280 /* Set Sai2 clock source. */
281 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
282 /* Disable SAI3 clock gate. */
283 CLOCK_DisableClock(kCLOCK_Sai3);
284 /* Set SAI3_CLK_PRED. */
285 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
286 /* Set SAI3_CLK_PODF. */
287 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
288 /* Set Sai3 clock source. */
289 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
290 /* Disable Lpi2c clock gate. */
291 CLOCK_DisableClock(kCLOCK_Lpi2c1);
292 CLOCK_DisableClock(kCLOCK_Lpi2c2);
293 CLOCK_DisableClock(kCLOCK_Lpi2c3);
294 /* Set LPI2C_CLK_PODF. */
295 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
296 /* Set Lpi2c clock source. */
297 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
298 /* Disable CAN clock gate. */
299 CLOCK_DisableClock(kCLOCK_Can1);
300 CLOCK_DisableClock(kCLOCK_Can2);
301 CLOCK_DisableClock(kCLOCK_Can1S);
302 CLOCK_DisableClock(kCLOCK_Can2S);
303 /* Set CAN_CLK_PODF. */
304 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
305 /* Set Can clock source. */
306 CLOCK_SetMux(kCLOCK_CanMux, 2);
307 /* Disable UART clock gate. */
308 CLOCK_DisableClock(kCLOCK_Lpuart1);
309 CLOCK_DisableClock(kCLOCK_Lpuart2);
310 CLOCK_DisableClock(kCLOCK_Lpuart3);
311 CLOCK_DisableClock(kCLOCK_Lpuart4);
312 CLOCK_DisableClock(kCLOCK_Lpuart5);
313 CLOCK_DisableClock(kCLOCK_Lpuart6);
314 CLOCK_DisableClock(kCLOCK_Lpuart7);
315 CLOCK_DisableClock(kCLOCK_Lpuart8);
316 /* Set UART_CLK_PODF. */
317 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
318 /* Set Uart clock source. */
319 CLOCK_SetMux(kCLOCK_UartMux, 0);
320 /* Disable LCDIF clock gate. */
321 CLOCK_DisableClock(kCLOCK_LcdPixel);
322 /* Set LCDIF_PRED. */
323 CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
324 /* Set LCDIF_CLK_PODF. */
325 CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
326 /* Set Lcdif pre clock source. */
327 CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
328 /* Disable SPDIF clock gate. */
329 CLOCK_DisableClock(kCLOCK_Spdif);
330 /* Set SPDIF0_CLK_PRED. */
331 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
332 /* Set SPDIF0_CLK_PODF. */
333 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
334 /* Set Spdif clock source. */
335 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
336 /* Disable Flexio1 clock gate. */
337 CLOCK_DisableClock(kCLOCK_Flexio1);
338 /* Set FLEXIO1_CLK_PRED. */
339 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
340 /* Set FLEXIO1_CLK_PODF. */
341 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
342 /* Set Flexio1 clock source. */
343 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
344 /* Disable Flexio2 clock gate. */
345 CLOCK_DisableClock(kCLOCK_Flexio2);
346 /* Set FLEXIO2_CLK_PRED. */
347 CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
348 /* Set FLEXIO2_CLK_PODF. */
349 CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
350 /* Set Flexio2 clock source. */
351 CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
352 /* Set Pll3 sw clock source. */
353 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
354 /* Init ARM PLL. */
355 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
356 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
357 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
358 * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
359 * well.*/
360#ifndef SKIP_SYSCLK_INIT
361 /* Init System PLL. */
362 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
363 /* Init System pfd0. */
364 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
365 /* Init System pfd1. */
366 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
367 /* Init System pfd2. */
368 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
369 /* Init System pfd3. */
370 CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
371 /* Disable pfd offset. */
372 CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
373#endif
374 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
375 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
376 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
377 * well.*/
378#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
379 /* Init Usb1 PLL. */
380 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
381 /* Init Usb1 pfd0. */
382 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
383 /* Init Usb1 pfd1. */
384 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
385 /* Init Usb1 pfd2. */
386 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
387 /* Init Usb1 pfd3. */
388 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
389 /* Disable Usb1 PLL output for USBPHY1. */
390 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
391#endif
392 /* DeInit Audio PLL. */
393 CLOCK_DeinitAudioPll();
394 /* Bypass Audio PLL. */
395 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
396 /* Set divider for Audio PLL. */
397 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
398 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
399 /* Enable Audio PLL output. */
400 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
401 /* DeInit Video PLL. */
402 CLOCK_DeinitVideoPll();
403 /* Bypass Video PLL. */
404 CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
405 /* Set divider for Video PLL. */
406 CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
407 /* Enable Video PLL output. */
408 CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
409 /* DeInit Enet PLL. */
410 CLOCK_DeinitEnetPll();
411 /* Bypass Enet PLL. */
412 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
413 /* Set Enet output divider. */
414 CCM_ANALOG->PLL_ENET =
415 (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
416 /* Enable Enet output. */
417 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
418 /* Enable Enet25M output. */
419 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
420 /* DeInit Usb2 PLL. */
421 CLOCK_DeinitUsb2Pll();
422 /* Bypass Usb2 PLL. */
423 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
424 /* Enable Usb2 PLL output. */
425 CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
426 /* Set preperiph clock source. */
427 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
428 /* Set periph clock source. */
429 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
430 /* Set periph clock2 clock source. */
431 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
432 /* Set per clock source. */
433 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
434 /* Set lvds1 clock source. */
435 CCM_ANALOG->MISC1 =
436 (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
437 /* Set clock out1 divider. */
438 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
439 /* Set clock out1 source. */
440 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
441 /* Set clock out2 divider. */
442 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
443 /* Set clock out2 source. */
444 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
445 /* Set clock out1 drives clock out1. */
446 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
447 /* Disable clock out1. */
448 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
449 /* Disable clock out2. */
450 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
451 /* Set SAI1 MCLK1 clock source. */
452 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
453 /* Set SAI1 MCLK2 clock source. */
454 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
455 /* Set SAI1 MCLK3 clock source. */
456 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
457 /* Set SAI2 MCLK3 clock source. */
458 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
459 /* Set SAI3 MCLK3 clock source. */
460 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
461 /* Set MQS configuration. */
462 IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
463 /* Set ENET Tx clock source. */
464 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
465 /* Set GPT1 High frequency reference clock source. */
466 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
467 /* Set GPT2 High frequency reference clock source. */
468 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
469 /* Set SystemCoreClock variable. */
470 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
471}
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 20:22:50 +0100