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1/*
2** ###################################################################
3** Processors: MIMXRT1062CVJ5A
4** MIMXRT1062CVL5A
5** MIMXRT1062DVJ6A
6** MIMXRT1062DVL6A
7**
8** Compilers: Freescale C/C++ for Embedded ARM
9** GNU C Compiler
10** IAR ANSI C/C++ Compiler for ARM
11** Keil ARM C/C++ Compiler
12** MCUXpresso Compiler
13**
14** Reference manual: IMXRT1060RM Rev.1, 12/2018 | IMXRT1060SRM Rev.3
15** Version: rev. 1.2, 2019-04-29
16** Build: b201019
17**
18** Abstract:
19** CMSIS Peripheral Access Layer for MIMXRT1062
20**
21** Copyright 1997-2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2020 NXP
23** All rights reserved.
24**
25** SPDX-License-Identifier: BSD-3-Clause
26**
27** http: www.nxp.com
28** mail: [email protected]
29**
30** Revisions:
31** - rev. 0.1 (2017-01-10)
32** Initial version.
33** - rev. 1.0 (2018-11-16)
34** Update header files to align with IMXRT1060RM Rev.0.
35** - rev. 1.1 (2018-11-27)
36** Update header files to align with IMXRT1060RM Rev.1.
37** - rev. 1.2 (2019-04-29)
38** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
39**
40** ###################################################################
41*/
42
43/*!
44 * @file MIMXRT1062.h
45 * @version 1.2
46 * @date 2019-04-29
47 * @brief CMSIS Peripheral Access Layer for MIMXRT1062
48 *
49 * CMSIS Peripheral Access Layer for MIMXRT1062
50 */
51
52#ifndef _MIMXRT1062_H_
53#define _MIMXRT1062_H_ /**< Symbol preventing repeated inclusion */
54
55/** Memory map major version (memory maps with equal major version number are
56 * compatible) */
57#define MCU_MEM_MAP_VERSION 0x0100U
58/** Memory map minor version */
59#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
60
61
62/* ----------------------------------------------------------------------------
63 -- Interrupt vector numbers
64 ---------------------------------------------------------------------------- */
65
66/*!
67 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
68 * @{
69 */
70
71/** Interrupt Number Definitions */
72#define NUMBER_OF_INT_VECTORS 174 /**< Number of interrupts in the Vector table */
73
74typedef enum IRQn {
75 /* Auxiliary constants */
76 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
77
78 /* Core interrupts */
79 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
80 HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */
81 MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */
82 BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */
83 UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */
84 SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */
85 DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */
86 PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */
87 SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */
88
89 /* Device specific interrupts */
90 DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */
91 DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */
92 DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */
93 DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */
94 DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */
95 DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */
96 DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */
97 DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */
98 DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */
99 DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */
100 DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */
101 DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */
102 DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */
103 DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */
104 DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */
105 DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */
106 DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */
107 CTI0_ERROR_IRQn = 17, /**< CTI0_Error */
108 CTI1_ERROR_IRQn = 18, /**< CTI1_Error */
109 CORE_IRQn = 19, /**< CorePlatform exception IRQ */
110 LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */
111 LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */
112 LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */
113 LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */
114 LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */
115 LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */
116 LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */
117 LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */
118 LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */
119 LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */
120 LPI2C3_IRQn = 30, /**< LPI2C3 interrupt */
121 LPI2C4_IRQn = 31, /**< LPI2C4 interrupt */
122 LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */
123 LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */
124 LPSPI3_IRQn = 34, /**< LPSPI3 single interrupt vector for all sources */
125 LPSPI4_IRQn = 35, /**< LPSPI4 single interrupt vector for all sources */
126 CAN1_IRQn = 36, /**< CAN1 interrupt */
127 CAN2_IRQn = 37, /**< CAN2 interrupt */
128 FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */
129 KPP_IRQn = 39, /**< Keypad nterrupt */
130 TSC_DIG_IRQn = 40, /**< TSC interrupt */
131 GPR_IRQ_IRQn = 41, /**< GPR interrupt */
132 LCDIF_IRQn = 42, /**< LCDIF interrupt */
133 CSI_IRQn = 43, /**< CSI interrupt */
134 PXP_IRQn = 44, /**< PXP interrupt */
135 WDOG2_IRQn = 45, /**< WDOG2 interrupt */
136 SNVS_HP_WRAPPER_IRQn = 46, /**< SRTC Consolidated Interrupt. Non TZ */
137 SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SRTC Security Interrupt. TZ */
138 SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */
139 CSU_IRQn = 49, /**< CSU interrupt */
140 DCP_IRQn = 50, /**< DCP_IRQ interrupt */
141 DCP_VMI_IRQn = 51, /**< DCP_VMI_IRQ interrupt */
142 Reserved68_IRQn = 52, /**< Reserved interrupt */
143 TRNG_IRQn = 53, /**< TRNG interrupt */
144 SJC_IRQn = 54, /**< SJC interrupt */
145 BEE_IRQn = 55, /**< BEE interrupt */
146 SAI1_IRQn = 56, /**< SAI1 interrupt */
147 SAI2_IRQn = 57, /**< SAI1 interrupt */
148 SAI3_RX_IRQn = 58, /**< SAI3 interrupt */
149 SAI3_TX_IRQn = 59, /**< SAI3 interrupt */
150 SPDIF_IRQn = 60, /**< SPDIF interrupt */
151 PMU_EVENT_IRQn = 61, /**< Brown-out event interrupt */
152 Reserved78_IRQn = 62, /**< Reserved interrupt */
153 TEMP_LOW_HIGH_IRQn = 63, /**< TempSensor low/high interrupt */
154 TEMP_PANIC_IRQn = 64, /**< TempSensor panic interrupt */
155 USB_PHY1_IRQn = 65, /**< USBPHY (UTMI0), Interrupt */
156 USB_PHY2_IRQn = 66, /**< USBPHY (UTMI1), Interrupt */
157 ADC1_IRQn = 67, /**< ADC1 interrupt */
158 ADC2_IRQn = 68, /**< ADC2 interrupt */
159 DCDC_IRQn = 69, /**< DCDC interrupt */
160 Reserved86_IRQn = 70, /**< Reserved interrupt */
161 Reserved87_IRQn = 71, /**< Reserved interrupt */
162 GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */
163 GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */
164 GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */
165 GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */
166 GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */
167 GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */
168 GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */
169 GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */
170 GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
171 GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
172 GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
173 GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
174 GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
175 GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
176 GPIO4_Combined_0_15_IRQn = 86, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
177 GPIO4_Combined_16_31_IRQn = 87, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
178 GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
179 GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
180 FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */
181 FLEXIO2_IRQn = 91, /**< FLEXIO2 interrupt */
182 WDOG1_IRQn = 92, /**< WDOG1 interrupt */
183 RTWDOG_IRQn = 93, /**< RTWDOG interrupt */
184 EWM_IRQn = 94, /**< EWM interrupt */
185 CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */
186 CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */
187 GPC_IRQn = 97, /**< GPC interrupt */
188 SRC_IRQn = 98, /**< SRC interrupt */
189 Reserved115_IRQn = 99, /**< Reserved interrupt */
190 GPT1_IRQn = 100, /**< GPT1 interrupt */
191 GPT2_IRQn = 101, /**< GPT2 interrupt */
192 PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
193 PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */
194 PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */
195 PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */
196 PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */
197 FLEXSPI2_IRQn = 107, /**< FlexSPI2 interrupt */
198 FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */
199 SEMC_IRQn = 109, /**< Reserved interrupt */
200 USDHC1_IRQn = 110, /**< USDHC1 interrupt */
201 USDHC2_IRQn = 111, /**< USDHC2 interrupt */
202 USB_OTG2_IRQn = 112, /**< USBO2 USB OTG2 */
203 USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */
204 ENET_IRQn = 114, /**< ENET interrupt */
205 ENET_1588_Timer_IRQn = 115, /**< ENET_1588_Timer interrupt */
206 XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */
207 XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */
208 ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */
209 ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */
210 ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */
211 ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */
212 PIT_IRQn = 122, /**< PIT interrupt */
213 ACMP1_IRQn = 123, /**< ACMP interrupt */
214 ACMP2_IRQn = 124, /**< ACMP interrupt */
215 ACMP3_IRQn = 125, /**< ACMP interrupt */
216 ACMP4_IRQn = 126, /**< ACMP interrupt */
217 Reserved143_IRQn = 127, /**< Reserved interrupt */
218 Reserved144_IRQn = 128, /**< Reserved interrupt */
219 ENC1_IRQn = 129, /**< ENC1 interrupt */
220 ENC2_IRQn = 130, /**< ENC2 interrupt */
221 ENC3_IRQn = 131, /**< ENC3 interrupt */
222 ENC4_IRQn = 132, /**< ENC4 interrupt */
223 TMR1_IRQn = 133, /**< TMR1 interrupt */
224 TMR2_IRQn = 134, /**< TMR2 interrupt */
225 TMR3_IRQn = 135, /**< TMR3 interrupt */
226 TMR4_IRQn = 136, /**< TMR4 interrupt */
227 PWM2_0_IRQn = 137, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */
228 PWM2_1_IRQn = 138, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */
229 PWM2_2_IRQn = 139, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */
230 PWM2_3_IRQn = 140, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */
231 PWM2_FAULT_IRQn = 141, /**< PWM2 fault or reload error interrupt */
232 PWM3_0_IRQn = 142, /**< PWM3 capture 0, compare 0, or reload 0 interrupt */
233 PWM3_1_IRQn = 143, /**< PWM3 capture 1, compare 1, or reload 0 interrupt */
234 PWM3_2_IRQn = 144, /**< PWM3 capture 2, compare 2, or reload 0 interrupt */
235 PWM3_3_IRQn = 145, /**< PWM3 capture 3, compare 3, or reload 0 interrupt */
236 PWM3_FAULT_IRQn = 146, /**< PWM3 fault or reload error interrupt */
237 PWM4_0_IRQn = 147, /**< PWM4 capture 0, compare 0, or reload 0 interrupt */
238 PWM4_1_IRQn = 148, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */
239 PWM4_2_IRQn = 149, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */
240 PWM4_3_IRQn = 150, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */
241 PWM4_FAULT_IRQn = 151, /**< PWM4 fault or reload error interrupt */
242 ENET2_IRQn = 152, /**< ENET2 interrupt */
243 ENET2_1588_Timer_IRQn = 153, /**< ENET2_1588_Timer interrupt */
244 CAN3_IRQn = 154, /**< CAN3 interrupt */
245 Reserved171_IRQn = 155, /**< Reserved interrupt */
246 FLEXIO3_IRQn = 156, /**< FLEXIO3 interrupt */
247 GPIO6_7_8_9_IRQn = 157 /**< GPIO6, GPIO7, GPIO8, GPIO9 interrupt */
248} IRQn_Type;
249
250/*!
251 * @}
252 */ /* end of group Interrupt_vector_numbers */
253
254
255/* ----------------------------------------------------------------------------
256 -- Cortex M7 Core Configuration
257 ---------------------------------------------------------------------------- */
258
259/*!
260 * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
261 * @{
262 */
263
264#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
265#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */
266#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */
267#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */
268#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
269#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
270#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
271
272#include "core_cm7.h" /* Core Peripheral Access Layer */
273#include "system_MIMXRT1062.h" /* Device specific configuration file */
274
275/*!
276 * @}
277 */ /* end of group Cortex_Core_Configuration */
278
279
280/* ----------------------------------------------------------------------------
281 -- Mapping Information
282 ---------------------------------------------------------------------------- */
283
284/*!
285 * @addtogroup Mapping_Information Mapping Information
286 * @{
287 */
288
289/** Mapping Information */
290/*!
291 * @addtogroup edma_request
292 * @{
293 */
294
295/*******************************************************************************
296 * Definitions
297 ******************************************************************************/
298
299/*!
300 * @brief Structure for the DMA hardware request
301 *
302 * Defines the structure for the DMA hardware request collections. The user can configure the
303 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
304 * of the hardware request varies according to the to SoC.
305 */
306typedef enum _dma_request_source
307{
308 kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */
309 kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */
310 kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */
311 kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */
312 kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */
313 kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */
314 kDmaRequestMuxLPUART5Tx = 6|0x100U, /**< LPUART5 Transmit */
315 kDmaRequestMuxLPUART5Rx = 7|0x100U, /**< LPUART5 Receive */
316 kDmaRequestMuxLPUART7Tx = 8|0x100U, /**< LPUART7 Transmit */
317 kDmaRequestMuxLPUART7Rx = 9|0x100U, /**< LPUART7 Receive */
318 kDmaRequestMuxCAN3 = 11|0x100U, /**< CAN3 */
319 kDmaRequestMuxCSI = 12|0x100U, /**< CSI */
320 kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */
321 kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */
322 kDmaRequestMuxLPSPI3Rx = 15|0x100U, /**< LPSPI3 Receive */
323 kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */
324 kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */
325 kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */
326 kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */
327 kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */
328 kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */
329 kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */
330 kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */
331 kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */
332 kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */
333 kDmaRequestMuxACMP3 = 26|0x100U, /**< ACMP3 */
334 kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */
335 kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */
336 kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */
337 kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR1 Request 1 */
338 kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */
339 kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */
340 kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */
341 kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */
342 kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */
343 kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */
344 kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */
345 kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */
346 kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, /**< FlexPWM3 Capture sub-module0 */
347 kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U, /**< FlexPWM3 Capture sub-module1 */
348 kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, /**< FlexPWM3 Capture sub-module2 */
349 kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, /**< FlexPWM3 Capture sub-module3 */
350 kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U, /**< FlexPWM3 Value sub-module0 */
351 kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U, /**< FlexPWM3 Value sub-module1 */
352 kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, /**< FlexPWM3 Value sub-module2 */
353 kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, /**< FlexPWM3 Value sub-module3 */
354 kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< TMR1 Capture timer 0 */
355 kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< TMR1 Capture timer 1 */
356 kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< TMR1 Capture timer 2 */
357 kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< TMR1 Capture timer 3 */
358 kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */
359 kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */
360 kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */
361 kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */
362 kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< TMR3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
363 kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U, /**< TMR3 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */
364 kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, /**< TMR3 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */
365 kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< TMR3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */
366 kDmaRequestMuxFlexSPI2Rx = 60|0x100U, /**< FlexSPI2 Receive */
367 kDmaRequestMuxFlexSPI2Tx = 61|0x100U, /**< FlexSPI2 Transmit */
368 kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */
369 kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */
370 kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */
371 kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */
372 kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */
373 kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */
374 kDmaRequestMuxLPUART6Tx = 70|0x100U, /**< LPUART6 Transmit */
375 kDmaRequestMuxLPUART6Rx = 71|0x100U, /**< LPUART6 Receive */
376 kDmaRequestMuxLPUART8Tx = 72|0x100U, /**< LPUART8 Transmit */
377 kDmaRequestMuxLPUART8Rx = 73|0x100U, /**< LPUART8 Receive */
378 kDmaRequestMuxPxp = 75|0x100U, /**< PXP */
379 kDmaRequestMuxLCDIF = 76|0x100U, /**< LCDIF */
380 kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */
381 kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */
382 kDmaRequestMuxLPSPI4Rx = 79|0x100U, /**< LPSPI4 Receive */
383 kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */
384 kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */
385 kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */
386 kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */
387 kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */
388 kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */
389 kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */
390 kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */
391 kDmaRequestMuxACMP2 = 89|0x100U, /**< ACMP2 */
392 kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */
393 kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< ENET Timer0 */
394 kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< ENET Timer1 */
395 kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */
396 kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */
397 kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */
398 kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */
399 kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */
400 kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */
401 kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, /**< FlexPWM2 Value sub-module0 */
402 kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, /**< FlexPWM2 Value sub-module1 */
403 kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U, /**< FlexPWM2 Value sub-module2 */
404 kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, /**< FlexPWM2 Value sub-module3 */
405 kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, /**< FlexPWM4 Capture sub-module0 */
406 kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, /**< FlexPWM4 Capture sub-module1 */
407 kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U, /**< FlexPWM4 Capture sub-module2 */
408 kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, /**< FlexPWM4 Capture sub-module3 */
409 kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U, /**< FlexPWM4 Value sub-module0 */
410 kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, /**< FlexPWM4 Value sub-module1 */
411 kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U, /**< FlexPWM4 Value sub-module2 */
412 kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, /**< FlexPWM4 Value sub-module3 */
413 kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< TMR2 Capture timer 0 */
414 kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< TMR2 Capture timer 1 */
415 kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< TMR2 Capture timer 2 */
416 kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< TMR2 Capture timer 3 */
417 kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */
418 kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */
419 kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */
420 kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */
421 kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< TMR4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
422 kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, /**< TMR4 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */
423 kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U, /**< TMR4 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */
424 kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, /**< TMR4 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */
425 kDmaRequestMuxEnet2Timer0 = 124|0x100U, /**< ENET2 Timer0 */
426 kDmaRequestMuxEnet2Timer1 = 125|0x100U, /**< ENET2 Timer1 */
427} dma_request_source_t;
428
429/* @} */
430
431/*!
432 * @addtogroup iomuxc_pads
433 * @{ */
434
435/*******************************************************************************
436 * Definitions
437*******************************************************************************/
438
439/*!
440 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
441 *
442 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
443 */
444typedef enum _iomuxc_sw_mux_ctl_pad
445{
446 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
447 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
448 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
449 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
450 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
451 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
452 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
453 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
454 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
455 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
456 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
457 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
458 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
459 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
460 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
461 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
462 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
463 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
464 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
465 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
466 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
467 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
468 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
469 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
470 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
471 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
472 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
473 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
474 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
475 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
476 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
477 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
478 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
479 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
480 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
481 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
482 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
483 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
484 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
485 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
486 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
487 kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
488 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
489 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
490 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
491 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
492 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
493 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
494 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
495 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
496 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
497 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
498 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
499 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
500 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
501 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
502 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
503 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
504 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
505 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
506 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
507 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
508 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
509 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
510 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
511 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
512 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
513 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
514 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
515 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
516 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
517 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
518 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
519 kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
520 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
521 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
522 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
523 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
524 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
525 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */
526 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */
527 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */
528 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */
529 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */
530 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */
531 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */
532 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */
533 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */
534 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */
535 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */
536 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */
537 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */
538 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */
539 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */
540 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */
541 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */
542 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */
543 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */
544 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */
545 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */
546 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
547 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
548 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
549 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
550 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
551 kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
552 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
553 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
554 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
555 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
556 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
557 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
558 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
559 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
560 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
561 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
562 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */
563 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
564 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
565 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
566 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
567 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
568 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
569 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
570} iomuxc_sw_mux_ctl_pad_t;
571
572/* @} */
573
574/*!
575 * @addtogroup iomuxc_pads
576 * @{ */
577
578/*******************************************************************************
579 * Definitions
580*******************************************************************************/
581
582/*!
583 * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD_1
584 *
585 * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD_1 collections.
586 */
587typedef enum _iomuxc_sw_mux_ctl_pad_1
588{
589 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
590 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
591 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
592 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
593 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
594 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
595 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
596 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
597 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
598 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
599 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
600 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
601 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
602 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B0_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
603 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_00 = 14U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
604 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_01 = 15U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
605 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_02 = 16U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
606 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_03 = 17U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
607 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_04 = 18U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
608 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_05 = 19U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
609 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_06 = 20U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
610 kIOMUXC_SW_MUX_CTL_PAD_GPIO_SPI_B1_07 = 21U, /**< IOMUXC SW_MUX_CTL_PAD_1 index */
611} iomuxc_sw_mux_ctl_pad_1_t;
612
613/* @} */
614
615/*!
616 * @addtogroup iomuxc_pads
617 * @{ */
618
619/*******************************************************************************
620 * Definitions
621*******************************************************************************/
622
623/*!
624 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
625 *
626 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
627 */
628typedef enum _iomuxc_sw_pad_ctl_pad
629{
630 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
631 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
632 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
633 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
634 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
635 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
636 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
637 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
638 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
639 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
640 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
641 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
642 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
643 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
644 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
645 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
646 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
647 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
648 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
649 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
650 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
651 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
652 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
653 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
654 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
655 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
656 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
657 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
658 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
659 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
660 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
661 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
662 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
663 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
664 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
665 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
666 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
667 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
668 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
669 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
670 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
671 kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
672 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
673 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
674 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
675 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
676 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
677 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
678 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
679 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
680 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
681 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
682 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
683 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
684 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */
685 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */
686 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */
687 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */
688 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */
689 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */
690 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */
691 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */
692 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */
693 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */
694 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
695 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
696 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
697 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
698 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
699 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
700 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */
701 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */
702 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */
703 kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */
704 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */
705 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */
706 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */
707 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
708 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
709 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
710 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
711 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
712 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
713 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
714 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
715 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
716 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
717 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
718 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
719 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */
720 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */
721 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */
722 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */
723 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */
724 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */
725 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */
726 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */
727 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */
728 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */
729 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */
730 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */
731 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */
732 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */
733 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */
734 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */
735 kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */
736 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */
737 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */
738 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */
739 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */
740 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */
741 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */
742 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */
743 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */
744 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */
745 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */
746 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */
747 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
748 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
749 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
750 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
751 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
752 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
753 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
754} iomuxc_sw_pad_ctl_pad_t;
755
756/* @} */
757
758/*!
759 * @addtogroup iomuxc_pads
760 * @{ */
761
762/*******************************************************************************
763 * Definitions
764*******************************************************************************/
765
766/*!
767 * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD_1
768 *
769 * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD_1 collections.
770 */
771typedef enum _iomuxc_sw_pad_ctl_pad_1
772{
773 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
774 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
775 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
776 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
777 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
778 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
779 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
780 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
781 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
782 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
783 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
784 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
785 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
786 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B0_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
787 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_00 = 14U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
788 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_01 = 15U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
789 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_02 = 16U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
790 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_03 = 17U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
791 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_04 = 18U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
792 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_05 = 19U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
793 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_06 = 20U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
794 kIOMUXC_SW_PAD_CTL_PAD_GPIO_SPI_B1_07 = 21U, /**< IOMUXC SW_PAD_CTL_PAD_1 index */
795} iomuxc_sw_pad_ctl_pad_1_t;
796
797/* @} */
798
799/*!
800 * @brief Enumeration for the IOMUXC select input
801 *
802 * Defines the enumeration for the IOMUXC select input collections.
803 */
804typedef enum _iomuxc_select_input
805{
806 kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */
807 kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */
808 kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */
809 kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */
810 kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */
811 kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U, /**< IOMUXC select input index */
812 kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U, /**< IOMUXC select input index */
813 kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U, /**< IOMUXC select input index */
814 kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U, /**< IOMUXC select input index */
815 kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U, /**< IOMUXC select input index */
816 kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U, /**< IOMUXC select input index */
817 kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U, /**< IOMUXC select input index */
818 kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U, /**< IOMUXC select input index */
819 kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U, /**< IOMUXC select input index */
820 kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U, /**< IOMUXC select input index */
821 kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U, /**< IOMUXC select input index */
822 kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U, /**< IOMUXC select input index */
823 kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U, /**< IOMUXC select input index */
824 kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U, /**< IOMUXC select input index */
825 kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */
826 kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U, /**< IOMUXC select input index */
827 kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */
828 kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U, /**< IOMUXC select input index */
829 kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U, /**< IOMUXC select input index */
830 kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U, /**< IOMUXC select input index */
831 kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U, /**< IOMUXC select input index */
832 kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U, /**< IOMUXC select input index */
833 kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U, /**< IOMUXC select input index */
834 kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U, /**< IOMUXC select input index */
835 kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U, /**< IOMUXC select input index */
836 kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U, /**< IOMUXC select input index */
837 kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U, /**< IOMUXC select input index */
838 kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U, /**< IOMUXC select input index */
839 kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U, /**< IOMUXC select input index */
840 kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U, /**< IOMUXC select input index */
841 kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U, /**< IOMUXC select input index */
842 kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U, /**< IOMUXC select input index */
843 kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U, /**< IOMUXC select input index */
844 kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U, /**< IOMUXC select input index */
845 kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U, /**< IOMUXC select input index */
846 kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U, /**< IOMUXC select input index */
847 kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U, /**< IOMUXC select input index */
848 kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U, /**< IOMUXC select input index */
849 kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U, /**< IOMUXC select input index */
850 kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U, /**< IOMUXC select input index */
851 kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U, /**< IOMUXC select input index */
852 kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U, /**< IOMUXC select input index */
853 kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U, /**< IOMUXC select input index */
854 kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U, /**< IOMUXC select input index */
855 kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U, /**< IOMUXC select input index */
856 kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U, /**< IOMUXC select input index */
857 kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U, /**< IOMUXC select input index */
858 kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U, /**< IOMUXC select input index */
859 kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U, /**< IOMUXC select input index */
860 kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U, /**< IOMUXC select input index */
861 kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U, /**< IOMUXC select input index */
862 kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U, /**< IOMUXC select input index */
863 kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U, /**< IOMUXC select input index */
864 kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U, /**< IOMUXC select input index */
865 kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U, /**< IOMUXC select input index */
866 kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U, /**< IOMUXC select input index */
867 kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U, /**< IOMUXC select input index */
868 kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U, /**< IOMUXC select input index */
869 kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U, /**< IOMUXC select input index */
870 kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U, /**< IOMUXC select input index */
871 kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U, /**< IOMUXC select input index */
872 kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U, /**< IOMUXC select input index */
873 kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U, /**< IOMUXC select input index */
874 kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U, /**< IOMUXC select input index */
875 kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U, /**< IOMUXC select input index */
876 kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U, /**< IOMUXC select input index */
877 kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U, /**< IOMUXC select input index */
878 kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U, /**< IOMUXC select input index */
879 kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U, /**< IOMUXC select input index */
880 kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U, /**< IOMUXC select input index */
881 kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U, /**< IOMUXC select input index */
882 kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U, /**< IOMUXC select input index */
883 kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U, /**< IOMUXC select input index */
884 kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U, /**< IOMUXC select input index */
885 kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U, /**< IOMUXC select input index */
886 kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U, /**< IOMUXC select input index */
887 kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U, /**< IOMUXC select input index */
888 kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U, /**< IOMUXC select input index */
889 kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U, /**< IOMUXC select input index */
890 kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U, /**< IOMUXC select input index */
891 kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U, /**< IOMUXC select input index */
892 kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U, /**< IOMUXC select input index */
893 kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U, /**< IOMUXC select input index */
894 kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U, /**< IOMUXC select input index */
895 kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U, /**< IOMUXC select input index */
896 kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U, /**< IOMUXC select input index */
897 kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U, /**< IOMUXC select input index */
898 kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U, /**< IOMUXC select input index */
899 kIOMUXC_NMI_SELECT_INPUT = 93U, /**< IOMUXC select input index */
900 kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U, /**< IOMUXC select input index */
901 kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U, /**< IOMUXC select input index */
902 kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U, /**< IOMUXC select input index */
903 kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U, /**< IOMUXC select input index */
904 kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U, /**< IOMUXC select input index */
905 kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U, /**< IOMUXC select input index */
906 kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U, /**< IOMUXC select input index */
907 kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U, /**< IOMUXC select input index */
908 kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U, /**< IOMUXC select input index */
909 kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U, /**< IOMUXC select input index */
910 kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U, /**< IOMUXC select input index */
911 kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U, /**< IOMUXC select input index */
912 kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U, /**< IOMUXC select input index */
913 kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U, /**< IOMUXC select input index */
914 kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U, /**< IOMUXC select input index */
915 kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U, /**< IOMUXC select input index */
916 kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U, /**< IOMUXC select input index */
917 kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U, /**< IOMUXC select input index */
918 kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U, /**< IOMUXC select input index */
919 kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */
920 kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U, /**< IOMUXC select input index */
921 kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U, /**< IOMUXC select input index */
922 kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U, /**< IOMUXC select input index */
923 kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U, /**< IOMUXC select input index */
924 kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U, /**< IOMUXC select input index */
925 kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U, /**< IOMUXC select input index */
926 kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U, /**< IOMUXC select input index */
927 kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */
928 kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U, /**< IOMUXC select input index */
929 kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U, /**< IOMUXC select input index */
930 kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U, /**< IOMUXC select input index */
931 kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U, /**< IOMUXC select input index */
932 kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U, /**< IOMUXC select input index */
933 kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U, /**< IOMUXC select input index */
934 kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U, /**< IOMUXC select input index */
935 kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U, /**< IOMUXC select input index */
936 kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U, /**< IOMUXC select input index */
937 kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U, /**< IOMUXC select input index */
938 kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U, /**< IOMUXC select input index */
939 kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U, /**< IOMUXC select input index */
940 kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U, /**< IOMUXC select input index */
941 kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U, /**< IOMUXC select input index */
942 kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U, /**< IOMUXC select input index */
943 kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U, /**< IOMUXC select input index */
944 kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U, /**< IOMUXC select input index */
945 kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U, /**< IOMUXC select input index */
946 kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U, /**< IOMUXC select input index */
947 kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U, /**< IOMUXC select input index */
948 kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U, /**< IOMUXC select input index */
949 kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U, /**< IOMUXC select input index */
950 kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U, /**< IOMUXC select input index */
951 kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U, /**< IOMUXC select input index */
952 kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U, /**< IOMUXC select input index */
953 kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U, /**< IOMUXC select input index */
954 kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U, /**< IOMUXC select input index */
955 kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U, /**< IOMUXC select input index */
956 kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U, /**< IOMUXC select input index */
957 kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U, /**< IOMUXC select input index */
958 kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U, /**< IOMUXC select input index */
959 kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */
960} iomuxc_select_input_t;
961
962/*!
963 * @brief Enumeration for the IOMUXC select input
964 *
965 * Defines the enumeration for the IOMUXC select input collections.
966 */
967typedef enum _iomuxc_select_input_1
968{
969 kIOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT = 0U, /**< IOMUXC select input index */
970 kIOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT = 1U, /**< IOMUXC select input index */
971 kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_0 = 2U, /**< IOMUXC select input index */
972 kIOMUXC_ENET2_IPP_IND_MAC0_RXDATA_SELECT_INPUT_1 = 3U, /**< IOMUXC select input index */
973 kIOMUXC_ENET2_IPP_IND_MAC0_RXEN_SELECT_INPUT = 4U, /**< IOMUXC select input index */
974 kIOMUXC_ENET2_IPP_IND_MAC0_RXERR_SELECT_INPUT = 5U, /**< IOMUXC select input index */
975 kIOMUXC_ENET2_IPP_IND_MAC0_TIMER_SELECT_INPUT_0 = 6U, /**< IOMUXC select input index */
976 kIOMUXC_ENET2_IPP_IND_MAC0_TXCLK_SELECT_INPUT = 7U, /**< IOMUXC select input index */
977 kIOMUXC_FLEXSPI2_IPP_IND_DQS_FA_SELECT_INPUT = 8U, /**< IOMUXC select input index */
978 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT0_SELECT_INPUT = 9U, /**< IOMUXC select input index */
979 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT1_SELECT_INPUT = 10U, /**< IOMUXC select input index */
980 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT2_SELECT_INPUT = 11U, /**< IOMUXC select input index */
981 kIOMUXC_FLEXSPI2_IPP_IND_IO_FA_BIT3_SELECT_INPUT = 12U, /**< IOMUXC select input index */
982 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT0_SELECT_INPUT = 13U, /**< IOMUXC select input index */
983 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT1_SELECT_INPUT = 14U, /**< IOMUXC select input index */
984 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT2_SELECT_INPUT = 15U, /**< IOMUXC select input index */
985 kIOMUXC_FLEXSPI2_IPP_IND_IO_FB_BIT3_SELECT_INPUT = 16U, /**< IOMUXC select input index */
986 kIOMUXC_FLEXSPI2_IPP_IND_SCK_FA_SELECT_INPUT = 17U, /**< IOMUXC select input index */
987 kIOMUXC_FLEXSPI2_IPP_IND_SCK_FB_SELECT_INPUT = 18U, /**< IOMUXC select input index */
988 kIOMUXC_GPT1_IPP_IND_CAPIN1_SELECT_INPUT = 19U, /**< IOMUXC select input index */
989 kIOMUXC_GPT1_IPP_IND_CAPIN2_SELECT_INPUT = 20U, /**< IOMUXC select input index */
990 kIOMUXC_GPT1_IPP_IND_CLKIN_SELECT_INPUT = 21U, /**< IOMUXC select input index */
991 kIOMUXC_GPT2_IPP_IND_CAPIN1_SELECT_INPUT = 22U, /**< IOMUXC select input index */
992 kIOMUXC_GPT2_IPP_IND_CAPIN2_SELECT_INPUT = 23U, /**< IOMUXC select input index */
993 kIOMUXC_GPT2_IPP_IND_CLKIN_SELECT_INPUT = 24U, /**< IOMUXC select input index */
994 kIOMUXC_SAI3_IPG_CLK_SAI_MCLK_SELECT_INPUT_2 = 25U, /**< IOMUXC select input index */
995 kIOMUXC_SAI3_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 26U, /**< IOMUXC select input index */
996 kIOMUXC_SAI3_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 27U, /**< IOMUXC select input index */
997 kIOMUXC_SAI3_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 28U, /**< IOMUXC select input index */
998 kIOMUXC_SAI3_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 29U, /**< IOMUXC select input index */
999 kIOMUXC_SAI3_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 30U, /**< IOMUXC select input index */
1000 kIOMUXC_SEMC_I_IPP_IND_DQS4_SELECT_INPUT = 31U, /**< IOMUXC select input index */
1001 kIOMUXC_CANFD_IPP_IND_CANRX_SELECT_INPUT = 32U, /**< IOMUXC select input index */
1002} iomuxc_select_input_1_t;
1003
1004typedef enum _xbar_input_signal
1005{
1006 kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */
1007 kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */
1008 kXBARA1_InputIomuxXbarIn02 = 2|0x100U, /**< IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
1009 kXBARA1_InputIomuxXbarIn03 = 3|0x100U, /**< IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
1010 kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
1011 kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
1012 kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
1013 kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
1014 kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
1015 kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
1016 kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
1017 kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
1018 kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
1019 kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
1020 kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
1021 kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
1022 kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
1023 kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
1024 kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
1025 kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
1026 kXBARA1_InputIomuxXbarIn20 = 20|0x100U, /**< IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
1027 kXBARA1_InputIomuxXbarIn21 = 21|0x100U, /**< IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
1028 kXBARA1_InputIomuxXbarIn22 = 22|0x100U, /**< IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
1029 kXBARA1_InputIomuxXbarIn23 = 23|0x100U, /**< IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
1030 kXBARA1_InputIomuxXbarIn24 = 24|0x100U, /**< IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
1031 kXBARA1_InputIomuxXbarIn25 = 25|0x100U, /**< IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
1032 kXBARA1_InputAcmp1Out = 26|0x100U, /**< ACMP1_OUT output assigned to XBARA1_IN26 input. */
1033 kXBARA1_InputAcmp2Out = 27|0x100U, /**< ACMP2_OUT output assigned to XBARA1_IN27 input. */
1034 kXBARA1_InputAcmp3Out = 28|0x100U, /**< ACMP3_OUT output assigned to XBARA1_IN28 input. */
1035 kXBARA1_InputAcmp4Out = 29|0x100U, /**< ACMP4_OUT output assigned to XBARA1_IN29 input. */
1036 kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA1_IN30 input is reserved. */
1037 kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA1_IN31 input is reserved. */
1038 kXBARA1_InputQtimer3Tmr0Output = 32|0x100U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
1039 kXBARA1_InputQtimer3Tmr1Output = 33|0x100U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
1040 kXBARA1_InputQtimer3Tmr2Output = 34|0x100U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
1041 kXBARA1_InputQtimer3Tmr3Output = 35|0x100U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
1042 kXBARA1_InputQtimer4Tmr0Output = 36|0x100U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
1043 kXBARA1_InputQtimer4Tmr1Output = 37|0x100U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
1044 kXBARA1_InputQtimer4Tmr2Output = 38|0x100U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
1045 kXBARA1_InputQtimer4Tmr3Output = 39|0x100U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
1046 kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
1047 kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
1048 kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
1049 kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
1050 kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
1051 kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
1052 kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
1053 kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
1054 kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
1055 kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
1056 kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
1057 kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
1058 kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
1059 kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
1060 kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
1061 kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
1062 kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
1063 kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
1064 kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
1065 kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
1066 kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
1067 kXBARA1_InputEnc2PosMatch = 61|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
1068 kXBARA1_InputEnc3PosMatch = 62|0x100U, /**< ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
1069 kXBARA1_InputEnc4PosMatch = 63|0x100U, /**< ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
1070 kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA1_IN64 input. */
1071 kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA1_IN65 input. */
1072 kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA1_IN66 input. */
1073 kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA1_IN67 input. */
1074 kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA1_IN68 input. */
1075 kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA1_IN69 input. */
1076 kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA1_IN70 input. */
1077 kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA1_IN71 input. */
1078 kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA1_IN72 input. */
1079 kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA1_IN73 input. */
1080 kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA1_IN74 input. */
1081 kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA1_IN75 input. */
1082 kXBARA1_InputAoi2Out0 = 76|0x100U, /**< AOI2_OUT0 output assigned to XBARA1_IN76 input. */
1083 kXBARA1_InputAoi2Out1 = 77|0x100U, /**< AOI2_OUT1 output assigned to XBARA1_IN77 input. */
1084 kXBARA1_InputAoi2Out2 = 78|0x100U, /**< AOI2_OUT2 output assigned to XBARA1_IN78 input. */
1085 kXBARA1_InputAoi2Out3 = 79|0x100U, /**< AOI2_OUT3 output assigned to XBARA1_IN79 input. */
1086 kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
1087 kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
1088 kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
1089 kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
1090 kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
1091 kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
1092 kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
1093 kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
1094 kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */
1095 kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */
1096 kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB2_IN2 input is reserved. */
1097 kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB2_IN3 input is reserved. */
1098 kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB2_IN4 input is reserved. */
1099 kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB2_IN5 input is reserved. */
1100 kXBARB2_InputAcmp1Out = 6|0x200U, /**< ACMP1_OUT output assigned to XBARB2_IN6 input. */
1101 kXBARB2_InputAcmp2Out = 7|0x200U, /**< ACMP2_OUT output assigned to XBARB2_IN7 input. */
1102 kXBARB2_InputAcmp3Out = 8|0x200U, /**< ACMP3_OUT output assigned to XBARB2_IN8 input. */
1103 kXBARB2_InputAcmp4Out = 9|0x200U, /**< ACMP4_OUT output assigned to XBARB2_IN9 input. */
1104 kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB2_IN10 input is reserved. */
1105 kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB2_IN11 input is reserved. */
1106 kXBARB2_InputQtimer3Tmr0Output = 12|0x200U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
1107 kXBARB2_InputQtimer3Tmr1Output = 13|0x200U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
1108 kXBARB2_InputQtimer3Tmr2Output = 14|0x200U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
1109 kXBARB2_InputQtimer3Tmr3Output = 15|0x200U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
1110 kXBARB2_InputQtimer4Tmr0Output = 16|0x200U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
1111 kXBARB2_InputQtimer4Tmr1Output = 17|0x200U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
1112 kXBARB2_InputQtimer4Tmr2Output = 18|0x200U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
1113 kXBARB2_InputQtimer4Tmr3Output = 19|0x200U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
1114 kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
1115 kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
1116 kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
1117 kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
1118 kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
1119 kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
1120 kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
1121 kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
1122 kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
1123 kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
1124 kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
1125 kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
1126 kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
1127 kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
1128 kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
1129 kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
1130 kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
1131 kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
1132 kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
1133 kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
1134 kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
1135 kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
1136 kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
1137 kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
1138 kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
1139 kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
1140 kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
1141 kXBARB2_InputEnc2PosMatch = 47|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
1142 kXBARB2_InputEnc3PosMatch = 48|0x200U, /**< ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
1143 kXBARB2_InputEnc4PosMatch = 49|0x200U, /**< ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
1144 kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB2_IN50 input. */
1145 kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB2_IN51 input. */
1146 kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB2_IN52 input. */
1147 kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB2_IN53 input. */
1148 kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB2_IN54 input. */
1149 kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB2_IN55 input. */
1150 kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB2_IN56 input. */
1151 kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB2_IN57 input. */
1152 kXBARB3_InputLogicLow = 0|0x300U, /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */
1153 kXBARB3_InputLogicHigh = 1|0x300U, /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */
1154 kXBARB3_InputRESERVED2 = 2|0x300U, /**< XBARB3_IN2 input is reserved. */
1155 kXBARB3_InputRESERVED3 = 3|0x300U, /**< XBARB3_IN3 input is reserved. */
1156 kXBARB3_InputRESERVED4 = 4|0x300U, /**< XBARB3_IN4 input is reserved. */
1157 kXBARB3_InputRESERVED5 = 5|0x300U, /**< XBARB3_IN5 input is reserved. */
1158 kXBARB3_InputAcmp1Out = 6|0x300U, /**< ACMP1_OUT output assigned to XBARB3_IN6 input. */
1159 kXBARB3_InputAcmp2Out = 7|0x300U, /**< ACMP2_OUT output assigned to XBARB3_IN7 input. */
1160 kXBARB3_InputAcmp3Out = 8|0x300U, /**< ACMP3_OUT output assigned to XBARB3_IN8 input. */
1161 kXBARB3_InputAcmp4Out = 9|0x300U, /**< ACMP4_OUT output assigned to XBARB3_IN9 input. */
1162 kXBARB3_InputRESERVED10 = 10|0x300U, /**< XBARB3_IN10 input is reserved. */
1163 kXBARB3_InputRESERVED11 = 11|0x300U, /**< XBARB3_IN11 input is reserved. */
1164 kXBARB3_InputQtimer3Tmr0Output = 12|0x300U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
1165 kXBARB3_InputQtimer3Tmr1Output = 13|0x300U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
1166 kXBARB3_InputQtimer3Tmr2Output = 14|0x300U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
1167 kXBARB3_InputQtimer3Tmr3Output = 15|0x300U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
1168 kXBARB3_InputQtimer4Tmr0Output = 16|0x300U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
1169 kXBARB3_InputQtimer4Tmr1Output = 17|0x300U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
1170 kXBARB3_InputQtimer4Tmr2Output = 18|0x300U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
1171 kXBARB3_InputQtimer4Tmr3Output = 19|0x300U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
1172 kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
1173 kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
1174 kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
1175 kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
1176 kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
1177 kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
1178 kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
1179 kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
1180 kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
1181 kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
1182 kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
1183 kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
1184 kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
1185 kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
1186 kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
1187 kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
1188 kXBARB3_InputPitTrigger0 = 36|0x300U, /**< PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
1189 kXBARB3_InputPitTrigger1 = 37|0x300U, /**< PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
1190 kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
1191 kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
1192 kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
1193 kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
1194 kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
1195 kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
1196 kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
1197 kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
1198 kXBARB3_InputEnc1PosMatch = 46|0x300U, /**< ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
1199 kXBARB3_InputEnc2PosMatch = 47|0x300U, /**< ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
1200 kXBARB3_InputEnc3PosMatch = 48|0x300U, /**< ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
1201 kXBARB3_InputEnc4PosMatch = 49|0x300U, /**< ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
1202 kXBARB3_InputDmaDone0 = 50|0x300U, /**< DMA_DONE0 output assigned to XBARB3_IN50 input. */
1203 kXBARB3_InputDmaDone1 = 51|0x300U, /**< DMA_DONE1 output assigned to XBARB3_IN51 input. */
1204 kXBARB3_InputDmaDone2 = 52|0x300U, /**< DMA_DONE2 output assigned to XBARB3_IN52 input. */
1205 kXBARB3_InputDmaDone3 = 53|0x300U, /**< DMA_DONE3 output assigned to XBARB3_IN53 input. */
1206 kXBARB3_InputDmaDone4 = 54|0x300U, /**< DMA_DONE4 output assigned to XBARB3_IN54 input. */
1207 kXBARB3_InputDmaDone5 = 55|0x300U, /**< DMA_DONE5 output assigned to XBARB3_IN55 input. */
1208 kXBARB3_InputDmaDone6 = 56|0x300U, /**< DMA_DONE6 output assigned to XBARB3_IN56 input. */
1209 kXBARB3_InputDmaDone7 = 57|0x300U, /**< DMA_DONE7 output assigned to XBARB3_IN57 input. */
1210} xbar_input_signal_t;
1211
1212typedef enum _xbar_output_signal
1213{
1214 kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
1215 kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
1216 kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
1217 kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
1218 kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
1219 kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
1220 kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
1221 kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
1222 kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
1223 kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
1224 kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
1225 kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
1226 kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
1227 kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
1228 kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
1229 kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
1230 kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
1231 kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
1232 kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
1233 kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
1234 kXBARA1_OutputAcmp1Sample = 20|0x100U, /**< XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
1235 kXBARA1_OutputAcmp2Sample = 21|0x100U, /**< XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
1236 kXBARA1_OutputAcmp3Sample = 22|0x100U, /**< XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
1237 kXBARA1_OutputAcmp4Sample = 23|0x100U, /**< XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
1238 kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA1_OUT24 output is reserved. */
1239 kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA1_OUT25 output is reserved. */
1240 kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
1241 kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
1242 kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
1243 kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
1244 kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
1245 kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
1246 kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
1247 kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
1248 kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
1249 kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
1250 kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
1251 kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U, /**< XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
1252 kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U, /**< XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
1253 kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
1254 kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U, /**< XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
1255 kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U, /**< XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
1256 kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U, /**< XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
1257 kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U, /**< XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
1258 kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, /**< XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
1259 kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, /**< XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
1260 kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, /**< XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
1261 kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U, /**< XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
1262 kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U, /**< XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
1263 kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, /**< XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
1264 kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, /**< XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
1265 kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U, /**< XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
1266 kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U, /**< XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
1267 kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
1268 kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
1269 kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
1270 kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
1271 kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U, /**< XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
1272 kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U, /**< XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
1273 kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U, /**< XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
1274 kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U, /**< XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
1275 kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U, /**< XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
1276 kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U, /**< XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
1277 kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U, /**< XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
1278 kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U, /**< XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
1279 kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U, /**< XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
1280 kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT */
1281 kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT */
1282 kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA1_OUT68 output assigned to ENC1_INDEX */
1283 kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA1_OUT69 output assigned to ENC1_HOME */
1284 kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA1_OUT70 output assigned to ENC1_TRIGGER */
1285 kXBARA1_OutputEnc2PhaseAInput = 71|0x100U, /**< XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT */
1286 kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, /**< XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT */
1287 kXBARA1_OutputEnc2Index = 73|0x100U, /**< XBARA1_OUT73 output assigned to ENC2_INDEX */
1288 kXBARA1_OutputEnc2Home = 74|0x100U, /**< XBARA1_OUT74 output assigned to ENC2_HOME */
1289 kXBARA1_OutputEnc2Trigger = 75|0x100U, /**< XBARA1_OUT75 output assigned to ENC2_TRIGGER */
1290 kXBARA1_OutputEnc3PhaseAInput = 76|0x100U, /**< XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT */
1291 kXBARA1_OutputEnc3PhaseBInput = 77|0x100U, /**< XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT */
1292 kXBARA1_OutputEnc3Index = 78|0x100U, /**< XBARA1_OUT78 output assigned to ENC3_INDEX */
1293 kXBARA1_OutputEnc3Home = 79|0x100U, /**< XBARA1_OUT79 output assigned to ENC3_HOME */
1294 kXBARA1_OutputEnc3Trigger = 80|0x100U, /**< XBARA1_OUT80 output assigned to ENC3_TRIGGER */
1295 kXBARA1_OutputEnc4PhaseAInput = 81|0x100U, /**< XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT */
1296 kXBARA1_OutputEnc4PhaseBInput = 82|0x100U, /**< XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT */
1297 kXBARA1_OutputEnc4Index = 83|0x100U, /**< XBARA1_OUT83 output assigned to ENC4_INDEX */
1298 kXBARA1_OutputEnc4Home = 84|0x100U, /**< XBARA1_OUT84 output assigned to ENC4_HOME */
1299 kXBARA1_OutputEnc4Trigger = 85|0x100U, /**< XBARA1_OUT85 output assigned to ENC4_TRIGGER */
1300 kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U, /**< XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT */
1301 kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U, /**< XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT */
1302 kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U, /**< XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT */
1303 kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U, /**< XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT */
1304 kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U, /**< XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT */
1305 kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U, /**< XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT */
1306 kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U, /**< XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT */
1307 kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U, /**< XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT */
1308 kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U, /**< XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT */
1309 kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U, /**< XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT */
1310 kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U, /**< XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT */
1311 kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U, /**< XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT */
1312 kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U, /**< XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT */
1313 kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U, /**< XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT */
1314 kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U, /**< XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT */
1315 kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U, /**< XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT */
1316 kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA1_OUT102 output assigned to EWM_EWM_IN */
1317 kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U, /**< XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
1318 kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U, /**< XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
1319 kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U, /**< XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
1320 kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U, /**< XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
1321 kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U, /**< XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
1322 kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U, /**< XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
1323 kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U, /**< XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
1324 kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U, /**< XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
1325 kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT */
1326 kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT */
1327 kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, /**< XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT */
1328 kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, /**< XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT */
1329 kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT */
1330 kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT */
1331 kXBARA1_OutputLpspi3TrgInput = 117|0x100U, /**< XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT */
1332 kXBARA1_OutputLpspi4TrgInput = 118|0x100U, /**< XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT */
1333 kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT */
1334 kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT */
1335 kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT */
1336 kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT */
1337 kXBARA1_OutputLpuart5TrgInput = 123|0x100U, /**< XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT */
1338 kXBARA1_OutputLpuart6TrgInput = 124|0x100U, /**< XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT */
1339 kXBARA1_OutputLpuart7TrgInput = 125|0x100U, /**< XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT */
1340 kXBARA1_OutputLpuart8TrgInput = 126|0x100U, /**< XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT */
1341 kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
1342 kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
1343 kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U, /**< XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
1344 kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U, /**< XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
1345 kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB2_OUT0 output assigned to AOI1_IN00 */
1346 kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB2_OUT1 output assigned to AOI1_IN01 */
1347 kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB2_OUT2 output assigned to AOI1_IN02 */
1348 kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB2_OUT3 output assigned to AOI1_IN03 */
1349 kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB2_OUT4 output assigned to AOI1_IN04 */
1350 kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB2_OUT5 output assigned to AOI1_IN05 */
1351 kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB2_OUT6 output assigned to AOI1_IN06 */
1352 kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB2_OUT7 output assigned to AOI1_IN07 */
1353 kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB2_OUT8 output assigned to AOI1_IN08 */
1354 kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB2_OUT9 output assigned to AOI1_IN09 */
1355 kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB2_OUT10 output assigned to AOI1_IN10 */
1356 kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB2_OUT11 output assigned to AOI1_IN11 */
1357 kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB2_OUT12 output assigned to AOI1_IN12 */
1358 kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB2_OUT13 output assigned to AOI1_IN13 */
1359 kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB2_OUT14 output assigned to AOI1_IN14 */
1360 kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB2_OUT15 output assigned to AOI1_IN15 */
1361 kXBARB3_OutputAoi2In00 = 0|0x300U, /**< XBARB3_OUT0 output assigned to AOI2_IN00 */
1362 kXBARB3_OutputAoi2In01 = 1|0x300U, /**< XBARB3_OUT1 output assigned to AOI2_IN01 */
1363 kXBARB3_OutputAoi2In02 = 2|0x300U, /**< XBARB3_OUT2 output assigned to AOI2_IN02 */
1364 kXBARB3_OutputAoi2In03 = 3|0x300U, /**< XBARB3_OUT3 output assigned to AOI2_IN03 */
1365 kXBARB3_OutputAoi2In04 = 4|0x300U, /**< XBARB3_OUT4 output assigned to AOI2_IN04 */
1366 kXBARB3_OutputAoi2In05 = 5|0x300U, /**< XBARB3_OUT5 output assigned to AOI2_IN05 */
1367 kXBARB3_OutputAoi2In06 = 6|0x300U, /**< XBARB3_OUT6 output assigned to AOI2_IN06 */
1368 kXBARB3_OutputAoi2In07 = 7|0x300U, /**< XBARB3_OUT7 output assigned to AOI2_IN07 */
1369 kXBARB3_OutputAoi2In08 = 8|0x300U, /**< XBARB3_OUT8 output assigned to AOI2_IN08 */
1370 kXBARB3_OutputAoi2In09 = 9|0x300U, /**< XBARB3_OUT9 output assigned to AOI2_IN09 */
1371 kXBARB3_OutputAoi2In10 = 10|0x300U, /**< XBARB3_OUT10 output assigned to AOI2_IN10 */
1372 kXBARB3_OutputAoi2In11 = 11|0x300U, /**< XBARB3_OUT11 output assigned to AOI2_IN11 */
1373 kXBARB3_OutputAoi2In12 = 12|0x300U, /**< XBARB3_OUT12 output assigned to AOI2_IN12 */
1374 kXBARB3_OutputAoi2In13 = 13|0x300U, /**< XBARB3_OUT13 output assigned to AOI2_IN13 */
1375 kXBARB3_OutputAoi2In14 = 14|0x300U, /**< XBARB3_OUT14 output assigned to AOI2_IN14 */
1376 kXBARB3_OutputAoi2In15 = 15|0x300U, /**< XBARB3_OUT15 output assigned to AOI2_IN15 */
1377} xbar_output_signal_t;
1378
1379
1380/*!
1381 * @}
1382 */ /* end of group Mapping_Information */
1383
1384
1385/* ----------------------------------------------------------------------------
1386 -- Device Peripheral Access Layer
1387 ---------------------------------------------------------------------------- */
1388
1389/*!
1390 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
1391 * @{
1392 */
1393
1394
1395/*
1396** Start of section using anonymous unions
1397*/
1398
1399#if defined(__ARMCC_VERSION)
1400 #if (__ARMCC_VERSION >= 6010050)
1401 #pragma clang diagnostic push
1402 #else
1403 #pragma push
1404 #pragma anon_unions
1405 #endif
1406#elif defined(__CWCC__)
1407 #pragma push
1408 #pragma cpp_extensions on
1409#elif defined(__GNUC__)
1410 /* anonymous unions are enabled by default */
1411#elif defined(__IAR_SYSTEMS_ICC__)
1412 #pragma language=extended
1413#else
1414 #error Not supported compiler type
1415#endif
1416
1417/* ----------------------------------------------------------------------------
1418 -- ADC Peripheral Access Layer
1419 ---------------------------------------------------------------------------- */
1420
1421/*!
1422 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
1423 * @{
1424 */
1425
1426/** ADC - Register Layout Typedef */
1427typedef struct {
1428 __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */
1429 __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */
1430 __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */
1431 __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */
1432 __IO uint32_t GC; /**< General control register, offset: 0x48 */
1433 __IO uint32_t GS; /**< General status register, offset: 0x4C */
1434 __IO uint32_t CV; /**< Compare value register, offset: 0x50 */
1435 __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */
1436 __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */
1437} ADC_Type;
1438
1439/* ----------------------------------------------------------------------------
1440 -- ADC Register Masks
1441 ---------------------------------------------------------------------------- */
1442
1443/*!
1444 * @addtogroup ADC_Register_Masks ADC Register Masks
1445 * @{
1446 */
1447
1448/*! @name HC - Control register for hardware triggers */
1449/*! @{ */
1450#define ADC_HC_ADCH_MASK (0x1FU)
1451#define ADC_HC_ADCH_SHIFT (0U)
1452/*! ADCH - Input Channel Select
1453 * 0b10000..External channel selection from ADC_ETC
1454 * 0b11000..Reserved.
1455 * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally
1456 * 0b11010..Reserved.
1457 * 0b11011..Reserved.
1458 * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion.
1459 */
1460#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
1461#define ADC_HC_AIEN_MASK (0x80U)
1462#define ADC_HC_AIEN_SHIFT (7U)
1463/*! AIEN - Conversion Complete Interrupt Enable/Disable Control
1464 * 0b1..Conversion complete interrupt enabled
1465 * 0b0..Conversion complete interrupt disabled
1466 */
1467#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
1468/*! @} */
1469
1470/* The count of ADC_HC */
1471#define ADC_HC_COUNT (8U)
1472
1473/*! @name HS - Status register for HW triggers */
1474/*! @{ */
1475#define ADC_HS_COCO0_MASK (0x1U)
1476#define ADC_HS_COCO0_SHIFT (0U)
1477/*! COCO0 - Conversion Complete Flag
1478 */
1479#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
1480/*! @} */
1481
1482/*! @name R - Data result register for HW triggers */
1483/*! @{ */
1484#define ADC_R_CDATA_MASK (0xFFFU)
1485#define ADC_R_CDATA_SHIFT (0U)
1486/*! CDATA - Data (result of an ADC conversion)
1487 */
1488#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
1489/*! @} */
1490
1491/* The count of ADC_R */
1492#define ADC_R_COUNT (8U)
1493
1494/*! @name CFG - Configuration register */
1495/*! @{ */
1496#define ADC_CFG_ADICLK_MASK (0x3U)
1497#define ADC_CFG_ADICLK_SHIFT (0U)
1498/*! ADICLK - Input Clock Select
1499 * 0b00..IPG clock
1500 * 0b01..IPG clock divided by 2
1501 * 0b10..Reserved
1502 * 0b11..Asynchronous clock (ADACK)
1503 */
1504#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
1505#define ADC_CFG_MODE_MASK (0xCU)
1506#define ADC_CFG_MODE_SHIFT (2U)
1507/*! MODE - Conversion Mode Selection
1508 * 0b00..8-bit conversion
1509 * 0b01..10-bit conversion
1510 * 0b10..12-bit conversion
1511 * 0b11..Reserved
1512 */
1513#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
1514#define ADC_CFG_ADLSMP_MASK (0x10U)
1515#define ADC_CFG_ADLSMP_SHIFT (4U)
1516/*! ADLSMP - Long Sample Time Configuration
1517 * 0b0..Short sample mode.
1518 * 0b1..Long sample mode.
1519 */
1520#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
1521#define ADC_CFG_ADIV_MASK (0x60U)
1522#define ADC_CFG_ADIV_SHIFT (5U)
1523/*! ADIV - Clock Divide Select
1524 * 0b00..Input clock
1525 * 0b01..Input clock / 2
1526 * 0b10..Input clock / 4
1527 * 0b11..Input clock / 8
1528 */
1529#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
1530#define ADC_CFG_ADLPC_MASK (0x80U)
1531#define ADC_CFG_ADLPC_SHIFT (7U)
1532/*! ADLPC - Low-Power Configuration
1533 * 0b0..ADC hard block not in low power mode.
1534 * 0b1..ADC hard block in low power mode.
1535 */
1536#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
1537#define ADC_CFG_ADSTS_MASK (0x300U)
1538#define ADC_CFG_ADSTS_SHIFT (8U)
1539/*! ADSTS
1540 * 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b
1541 * 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b
1542 * 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b
1543 * 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b
1544 */
1545#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
1546#define ADC_CFG_ADHSC_MASK (0x400U)
1547#define ADC_CFG_ADHSC_SHIFT (10U)
1548/*! ADHSC - High Speed Configuration
1549 * 0b0..Normal conversion selected.
1550 * 0b1..High speed conversion selected.
1551 */
1552#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
1553#define ADC_CFG_REFSEL_MASK (0x1800U)
1554#define ADC_CFG_REFSEL_SHIFT (11U)
1555/*! REFSEL - Voltage Reference Selection
1556 * 0b00..Selects VREFH/VREFL as reference voltage.
1557 * 0b01..Reserved
1558 * 0b10..Reserved
1559 * 0b11..Reserved
1560 */
1561#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
1562#define ADC_CFG_ADTRG_MASK (0x2000U)
1563#define ADC_CFG_ADTRG_SHIFT (13U)
1564/*! ADTRG - Conversion Trigger Select
1565 * 0b0..Software trigger selected
1566 * 0b1..Hardware trigger selected
1567 */
1568#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
1569#define ADC_CFG_AVGS_MASK (0xC000U)
1570#define ADC_CFG_AVGS_SHIFT (14U)
1571/*! AVGS - Hardware Average select
1572 * 0b00..4 samples averaged
1573 * 0b01..8 samples averaged
1574 * 0b10..16 samples averaged
1575 * 0b11..32 samples averaged
1576 */
1577#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
1578#define ADC_CFG_OVWREN_MASK (0x10000U)
1579#define ADC_CFG_OVWREN_SHIFT (16U)
1580/*! OVWREN - Data Overwrite Enable
1581 * 0b1..Enable the overwriting.
1582 * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.
1583 */
1584#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
1585/*! @} */
1586
1587/*! @name GC - General control register */
1588/*! @{ */
1589#define ADC_GC_ADACKEN_MASK (0x1U)
1590#define ADC_GC_ADACKEN_SHIFT (0U)
1591/*! ADACKEN - Asynchronous clock output enable
1592 * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.
1593 * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC
1594 */
1595#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
1596#define ADC_GC_DMAEN_MASK (0x2U)
1597#define ADC_GC_DMAEN_SHIFT (1U)
1598/*! DMAEN - DMA Enable
1599 * 0b0..DMA disabled (default)
1600 * 0b1..DMA enabled
1601 */
1602#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
1603#define ADC_GC_ACREN_MASK (0x4U)
1604#define ADC_GC_ACREN_SHIFT (2U)
1605/*! ACREN - Compare Function Range Enable
1606 * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared.
1607 * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.
1608 */
1609#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
1610#define ADC_GC_ACFGT_MASK (0x8U)
1611#define ADC_GC_ACFGT_SHIFT (3U)
1612/*! ACFGT - Compare Function Greater Than Enable
1613 * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive"
1614 * functionality based on the values placed in the ADC_CV register.
1615 * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive"
1616 * functionality based on the values placed in the ADC_CV registers.
1617 */
1618#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
1619#define ADC_GC_ACFE_MASK (0x10U)
1620#define ADC_GC_ACFE_SHIFT (4U)
1621/*! ACFE - Compare Function Enable
1622 * 0b0..Compare function disabled
1623 * 0b1..Compare function enabled
1624 */
1625#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
1626#define ADC_GC_AVGE_MASK (0x20U)
1627#define ADC_GC_AVGE_SHIFT (5U)
1628/*! AVGE - Hardware average enable
1629 * 0b0..Hardware average function disabled
1630 * 0b1..Hardware average function enabled
1631 */
1632#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
1633#define ADC_GC_ADCO_MASK (0x40U)
1634#define ADC_GC_ADCO_SHIFT (6U)
1635/*! ADCO - Continuous Conversion Enable
1636 * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
1637 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
1638 */
1639#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
1640#define ADC_GC_CAL_MASK (0x80U)
1641#define ADC_GC_CAL_SHIFT (7U)
1642/*! CAL - Calibration
1643 */
1644#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
1645/*! @} */
1646
1647/*! @name GS - General status register */
1648/*! @{ */
1649#define ADC_GS_ADACT_MASK (0x1U)
1650#define ADC_GS_ADACT_SHIFT (0U)
1651/*! ADACT - Conversion Active
1652 * 0b0..Conversion not in progress.
1653 * 0b1..Conversion in progress.
1654 */
1655#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
1656#define ADC_GS_CALF_MASK (0x2U)
1657#define ADC_GS_CALF_SHIFT (1U)
1658/*! CALF - Calibration Failed Flag
1659 * 0b0..Calibration completed normally.
1660 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
1661 */
1662#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
1663#define ADC_GS_AWKST_MASK (0x4U)
1664#define ADC_GS_AWKST_SHIFT (2U)
1665/*! AWKST - Asynchronous wakeup interrupt status
1666 * 0b1..Asynchronous wake up interrupt occurred in stop mode.
1667 * 0b0..No asynchronous interrupt.
1668 */
1669#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
1670/*! @} */
1671
1672/*! @name CV - Compare value register */
1673/*! @{ */
1674#define ADC_CV_CV1_MASK (0xFFFU)
1675#define ADC_CV_CV1_SHIFT (0U)
1676/*! CV1 - Compare Value 1
1677 */
1678#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
1679#define ADC_CV_CV2_MASK (0xFFF0000U)
1680#define ADC_CV_CV2_SHIFT (16U)
1681/*! CV2 - Compare Value 2
1682 */
1683#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
1684/*! @} */
1685
1686/*! @name OFS - Offset correction value register */
1687/*! @{ */
1688#define ADC_OFS_OFS_MASK (0xFFFU)
1689#define ADC_OFS_OFS_SHIFT (0U)
1690/*! OFS - Offset value
1691 */
1692#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
1693#define ADC_OFS_SIGN_MASK (0x1000U)
1694#define ADC_OFS_SIGN_SHIFT (12U)
1695/*! SIGN - Sign bit
1696 * 0b0..The offset value is added with the raw result
1697 * 0b1..The offset value is subtracted from the raw converted value
1698 */
1699#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
1700/*! @} */
1701
1702/*! @name CAL - Calibration value register */
1703/*! @{ */
1704#define ADC_CAL_CAL_CODE_MASK (0xFU)
1705#define ADC_CAL_CAL_CODE_SHIFT (0U)
1706/*! CAL_CODE - Calibration Result Value
1707 */
1708#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)
1709/*! @} */
1710
1711
1712/*!
1713 * @}
1714 */ /* end of group ADC_Register_Masks */
1715
1716
1717/* ADC - Peripheral instance base addresses */
1718/** Peripheral ADC1 base address */
1719#define ADC1_BASE (0x400C4000u)
1720/** Peripheral ADC1 base pointer */
1721#define ADC1 ((ADC_Type *)ADC1_BASE)
1722/** Peripheral ADC2 base address */
1723#define ADC2_BASE (0x400C8000u)
1724/** Peripheral ADC2 base pointer */
1725#define ADC2 ((ADC_Type *)ADC2_BASE)
1726/** Array initializer of ADC peripheral base addresses */
1727#define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE }
1728/** Array initializer of ADC peripheral base pointers */
1729#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 }
1730/** Interrupt vectors for the ADC peripheral type */
1731#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
1732
1733/*!
1734 * @}
1735 */ /* end of group ADC_Peripheral_Access_Layer */
1736
1737
1738/* ----------------------------------------------------------------------------
1739 -- ADC_ETC Peripheral Access Layer
1740 ---------------------------------------------------------------------------- */
1741
1742/*!
1743 * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
1744 * @{
1745 */
1746
1747/** ADC_ETC - Register Layout Typedef */
1748typedef struct {
1749 __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */
1750 __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */
1751 __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */
1752 __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */
1753 struct { /* offset: 0x10, array step: 0x28 */
1754 __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */
1755 __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */
1756 __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */
1757 __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */
1758 __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */
1759 __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */
1760 __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */
1761 __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */
1762 __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */
1763 __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */
1764 } TRIG[8];
1765} ADC_ETC_Type;
1766
1767/* ----------------------------------------------------------------------------
1768 -- ADC_ETC Register Masks
1769 ---------------------------------------------------------------------------- */
1770
1771/*!
1772 * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
1773 * @{
1774 */
1775
1776/*! @name CTRL - ADC_ETC Global Control Register */
1777/*! @{ */
1778#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
1779#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
1780#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
1781#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
1782#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
1783#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
1784#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
1785#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
1786#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
1787#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
1788#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
1789#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
1790#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
1791#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
1792#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
1793#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
1794#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
1795#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
1796#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
1797#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
1798#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
1799#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
1800#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
1801#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
1802#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
1803#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
1804#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
1805/*! @} */
1806
1807/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
1808/*! @{ */
1809#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
1810#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
1811#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
1812#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
1813#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
1814#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
1815#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
1816#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
1817#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
1818#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
1819#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
1820#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
1821#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
1822#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
1823#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
1824#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
1825#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
1826#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
1827#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
1828#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
1829#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
1830#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
1831#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
1832#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
1833#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
1834#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
1835#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
1836#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
1837#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
1838#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
1839#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
1840#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
1841#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
1842#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
1843#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
1844#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
1845#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
1846#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
1847#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
1848#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
1849#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
1850#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
1851#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
1852#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
1853#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
1854#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
1855#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
1856#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
1857/*! @} */
1858
1859/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */
1860/*! @{ */
1861#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
1862#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
1863#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)
1864#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
1865#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
1866#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)
1867#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
1868#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
1869#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)
1870#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
1871#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
1872#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)
1873#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
1874#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
1875#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)
1876#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
1877#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
1878#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)
1879#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
1880#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
1881#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)
1882#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
1883#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
1884#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)
1885#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
1886#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
1887#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)
1888#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
1889#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
1890#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)
1891#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
1892#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
1893#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)
1894#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
1895#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
1896#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)
1897#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
1898#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
1899#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)
1900#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
1901#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
1902#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)
1903#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
1904#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
1905#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)
1906#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
1907#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
1908#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)
1909/*! @} */
1910
1911/*! @name DMA_CTRL - ETC DMA control Register */
1912/*! @{ */
1913#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
1914#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
1915#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
1916#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
1917#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
1918#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
1919#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
1920#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
1921#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
1922#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
1923#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
1924#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
1925#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
1926#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
1927#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
1928#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
1929#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
1930#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
1931#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
1932#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
1933#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
1934#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
1935#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
1936#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
1937#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
1938#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
1939#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
1940#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
1941#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
1942#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
1943#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
1944#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
1945#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
1946#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
1947#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
1948#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
1949#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
1950#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
1951#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
1952#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
1953#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
1954#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
1955#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
1956#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
1957#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
1958#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
1959#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
1960#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
1961/*! @} */
1962
1963/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */
1964/*! @{ */
1965#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
1966#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
1967#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
1968#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
1969#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
1970#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
1971#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
1972#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
1973#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
1974#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
1975#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
1976#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
1977#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
1978#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
1979#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
1980/*! @} */
1981
1982/* The count of ADC_ETC_TRIGn_CTRL */
1983#define ADC_ETC_TRIGn_CTRL_COUNT (8U)
1984
1985/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */
1986/*! @{ */
1987#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
1988#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
1989#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
1990#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
1991#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
1992#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
1993/*! @} */
1994
1995/* The count of ADC_ETC_TRIGn_COUNTER */
1996#define ADC_ETC_TRIGn_COUNTER_COUNT (8U)
1997
1998/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
1999/*! @{ */
2000#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
2001#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
2002#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
2003#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
2004#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
2005#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
2006#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
2007#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
2008#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
2009#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
2010#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
2011#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
2012#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
2013#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
2014#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
2015#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
2016#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
2017#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
2018#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
2019#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
2020#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
2021#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
2022#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
2023#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
2024/*! @} */
2025
2026/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
2027#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
2028
2029/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
2030/*! @{ */
2031#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
2032#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
2033#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
2034#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
2035#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
2036#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
2037#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
2038#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
2039#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
2040#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
2041#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
2042#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
2043#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
2044#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
2045#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
2046#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
2047#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
2048#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
2049#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
2050#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
2051#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
2052#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
2053#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
2054#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
2055/*! @} */
2056
2057/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
2058#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
2059
2060/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
2061/*! @{ */
2062#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
2063#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
2064#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
2065#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
2066#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
2067#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
2068#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
2069#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
2070#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
2071#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
2072#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
2073#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
2074#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
2075#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
2076#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
2077#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
2078#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
2079#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
2080#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
2081#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
2082#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
2083#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
2084#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
2085#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
2086/*! @} */
2087
2088/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
2089#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
2090
2091/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
2092/*! @{ */
2093#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
2094#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
2095#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
2096#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
2097#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
2098#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
2099#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
2100#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
2101#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
2102#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
2103#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
2104#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
2105#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
2106#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
2107#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
2108#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
2109#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
2110#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
2111#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
2112#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
2113#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
2114#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
2115#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
2116#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
2117/*! @} */
2118
2119/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
2120#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
2121
2122/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
2123/*! @{ */
2124#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
2125#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
2126#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
2127#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
2128#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
2129#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
2130/*! @} */
2131
2132/* The count of ADC_ETC_TRIGn_RESULT_1_0 */
2133#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
2134
2135/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
2136/*! @{ */
2137#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
2138#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
2139#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
2140#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
2141#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
2142#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
2143/*! @} */
2144
2145/* The count of ADC_ETC_TRIGn_RESULT_3_2 */
2146#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
2147
2148/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
2149/*! @{ */
2150#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
2151#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
2152#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
2153#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
2154#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
2155#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
2156/*! @} */
2157
2158/* The count of ADC_ETC_TRIGn_RESULT_5_4 */
2159#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
2160
2161/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
2162/*! @{ */
2163#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
2164#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
2165#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
2166#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
2167#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
2168#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
2169/*! @} */
2170
2171/* The count of ADC_ETC_TRIGn_RESULT_7_6 */
2172#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
2173
2174
2175/*!
2176 * @}
2177 */ /* end of group ADC_ETC_Register_Masks */
2178
2179
2180/* ADC_ETC - Peripheral instance base addresses */
2181/** Peripheral ADC_ETC base address */
2182#define ADC_ETC_BASE (0x403B0000u)
2183/** Peripheral ADC_ETC base pointer */
2184#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
2185/** Array initializer of ADC_ETC peripheral base addresses */
2186#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
2187/** Array initializer of ADC_ETC peripheral base pointers */
2188#define ADC_ETC_BASE_PTRS { ADC_ETC }
2189/** Interrupt vectors for the ADC_ETC peripheral type */
2190#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
2191#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
2192
2193/*!
2194 * @}
2195 */ /* end of group ADC_ETC_Peripheral_Access_Layer */
2196
2197
2198/* ----------------------------------------------------------------------------
2199 -- AIPSTZ Peripheral Access Layer
2200 ---------------------------------------------------------------------------- */
2201
2202/*!
2203 * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
2204 * @{
2205 */
2206
2207/** AIPSTZ - Register Layout Typedef */
2208typedef struct {
2209 __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */
2210 uint8_t RESERVED_0[60];
2211 __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
2212 __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
2213 __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
2214 __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
2215 __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
2216} AIPSTZ_Type;
2217
2218/* ----------------------------------------------------------------------------
2219 -- AIPSTZ Register Masks
2220 ---------------------------------------------------------------------------- */
2221
2222/*!
2223 * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
2224 * @{
2225 */
2226
2227/*! @name MPR - Master Priviledge Registers */
2228/*! @{ */
2229#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
2230#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
2231/*! MPROT5
2232 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2233 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2234 * 0bxx0x..This master is not trusted for write accesses.
2235 * 0bxx1x..This master is trusted for write accesses.
2236 * 0bx0xx..This master is not trusted for read accesses.
2237 * 0bx1xx..This master is trusted for read accesses.
2238 * 0b1xxx..Write accesses from this master are allowed to be buffered
2239 */
2240#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
2241#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
2242#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
2243/*! MPROT3
2244 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2245 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2246 * 0bxx0x..This master is not trusted for write accesses.
2247 * 0bxx1x..This master is trusted for write accesses.
2248 * 0bx0xx..This master is not trusted for read accesses.
2249 * 0bx1xx..This master is trusted for read accesses.
2250 * 0b1xxx..Write accesses from this master are allowed to be buffered
2251 */
2252#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
2253#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
2254#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
2255/*! MPROT2
2256 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2257 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2258 * 0bxx0x..This master is not trusted for write accesses.
2259 * 0bxx1x..This master is trusted for write accesses.
2260 * 0bx0xx..This master is not trusted for read accesses.
2261 * 0bx1xx..This master is trusted for read accesses.
2262 * 0b1xxx..Write accesses from this master are allowed to be buffered
2263 */
2264#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
2265#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
2266#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
2267/*! MPROT1
2268 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2269 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2270 * 0bxx0x..This master is not trusted for write accesses.
2271 * 0bxx1x..This master is trusted for write accesses.
2272 * 0bx0xx..This master is not trusted for read accesses.
2273 * 0bx1xx..This master is trusted for read accesses.
2274 * 0b1xxx..Write accesses from this master are allowed to be buffered
2275 */
2276#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
2277#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
2278#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
2279/*! MPROT0
2280 * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
2281 * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
2282 * 0bxx0x..This master is not trusted for write accesses.
2283 * 0bxx1x..This master is trusted for write accesses.
2284 * 0bx0xx..This master is not trusted for read accesses.
2285 * 0bx1xx..This master is trusted for read accesses.
2286 * 0b1xxx..Write accesses from this master are allowed to be buffered
2287 */
2288#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
2289/*! @} */
2290
2291/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
2292/*! @{ */
2293#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
2294#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
2295/*! OPAC7
2296 * 0bxxx0..Accesses from an untrusted master are allowed.
2297 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2298 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2299 * 0bxx0x..This peripheral allows write accesses.
2300 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2301 * error response and no peripheral access is initiated on the IPS bus.
2302 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2303 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2304 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2305 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2306 * on the IPS bus.
2307 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2308 */
2309#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
2310#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
2311#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
2312/*! OPAC6
2313 * 0bxxx0..Accesses from an untrusted master are allowed.
2314 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2315 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2316 * 0bxx0x..This peripheral allows write accesses.
2317 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2318 * error response and no peripheral access is initiated on the IPS bus.
2319 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2320 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2321 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2322 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2323 * on the IPS bus.
2324 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2325 */
2326#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
2327#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
2328#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
2329/*! OPAC5
2330 * 0bxxx0..Accesses from an untrusted master are allowed.
2331 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2332 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2333 * 0bxx0x..This peripheral allows write accesses.
2334 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2335 * error response and no peripheral access is initiated on the IPS bus.
2336 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2337 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2338 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2339 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2340 * on the IPS bus.
2341 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2342 */
2343#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
2344#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
2345#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
2346/*! OPAC4
2347 * 0bxxx0..Accesses from an untrusted master are allowed.
2348 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2349 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2350 * 0bxx0x..This peripheral allows write accesses.
2351 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2352 * error response and no peripheral access is initiated on the IPS bus.
2353 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2354 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2355 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2356 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2357 * on the IPS bus.
2358 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2359 */
2360#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
2361#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
2362#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
2363/*! OPAC3
2364 * 0bxxx0..Accesses from an untrusted master are allowed.
2365 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2366 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2367 * 0bxx0x..This peripheral allows write accesses.
2368 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2369 * error response and no peripheral access is initiated on the IPS bus.
2370 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2371 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2372 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2373 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2374 * on the IPS bus.
2375 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2376 */
2377#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
2378#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
2379#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
2380/*! OPAC2
2381 * 0bxxx0..Accesses from an untrusted master are allowed.
2382 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2383 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2384 * 0bxx0x..This peripheral allows write accesses.
2385 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2386 * error response and no peripheral access is initiated on the IPS bus.
2387 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2388 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2389 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2390 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2391 * on the IPS bus.
2392 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2393 */
2394#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
2395#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
2396#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
2397/*! OPAC1
2398 * 0bxxx0..Accesses from an untrusted master are allowed.
2399 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2400 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2401 * 0bxx0x..This peripheral allows write accesses.
2402 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2403 * error response and no peripheral access is initiated on the IPS bus.
2404 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2405 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2406 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2407 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2408 * on the IPS bus.
2409 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2410 */
2411#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
2412#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
2413#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
2414/*! OPAC0
2415 * 0bxxx0..Accesses from an untrusted master are allowed.
2416 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2417 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2418 * 0bxx0x..This peripheral allows write accesses.
2419 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2420 * error response and no peripheral access is initiated on the IPS bus.
2421 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2422 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2423 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2424 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2425 * on the IPS bus.
2426 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2427 */
2428#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
2429/*! @} */
2430
2431/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
2432/*! @{ */
2433#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
2434#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
2435/*! OPAC15
2436 * 0bxxx0..Accesses from an untrusted master are allowed.
2437 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2438 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2439 * 0bxx0x..This peripheral allows write accesses.
2440 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2441 * error response and no peripheral access is initiated on the IPS bus.
2442 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2443 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2444 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2445 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2446 * on the IPS bus.
2447 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2448 */
2449#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
2450#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
2451#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
2452/*! OPAC14
2453 * 0bxxx0..Accesses from an untrusted master are allowed.
2454 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2455 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2456 * 0bxx0x..This peripheral allows write accesses.
2457 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2458 * error response and no peripheral access is initiated on the IPS bus.
2459 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2460 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2461 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2462 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2463 * on the IPS bus.
2464 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2465 */
2466#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
2467#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
2468#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
2469/*! OPAC13
2470 * 0bxxx0..Accesses from an untrusted master are allowed.
2471 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2472 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2473 * 0bxx0x..This peripheral allows write accesses.
2474 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2475 * error response and no peripheral access is initiated on the IPS bus.
2476 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2477 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2478 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2479 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2480 * on the IPS bus.
2481 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2482 */
2483#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
2484#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
2485#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
2486/*! OPAC12
2487 * 0bxxx0..Accesses from an untrusted master are allowed.
2488 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2489 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2490 * 0bxx0x..This peripheral allows write accesses.
2491 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2492 * error response and no peripheral access is initiated on the IPS bus.
2493 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2494 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2495 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2496 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2497 * on the IPS bus.
2498 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2499 */
2500#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
2501#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
2502#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
2503/*! OPAC11
2504 * 0bxxx0..Accesses from an untrusted master are allowed.
2505 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2506 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2507 * 0bxx0x..This peripheral allows write accesses.
2508 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2509 * error response and no peripheral access is initiated on the IPS bus.
2510 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2511 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2512 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2513 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2514 * on the IPS bus.
2515 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2516 */
2517#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
2518#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
2519#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
2520/*! OPAC10
2521 * 0bxxx0..Accesses from an untrusted master are allowed.
2522 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2523 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2524 * 0bxx0x..This peripheral allows write accesses.
2525 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2526 * error response and no peripheral access is initiated on the IPS bus.
2527 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2528 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2529 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2530 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2531 * on the IPS bus.
2532 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2533 */
2534#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
2535#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
2536#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
2537/*! OPAC9
2538 * 0bxxx0..Accesses from an untrusted master are allowed.
2539 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2540 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2541 * 0bxx0x..This peripheral allows write accesses.
2542 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2543 * error response and no peripheral access is initiated on the IPS bus.
2544 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2545 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2546 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2547 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2548 * on the IPS bus.
2549 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2550 */
2551#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
2552#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
2553#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
2554/*! OPAC8
2555 * 0bxxx0..Accesses from an untrusted master are allowed.
2556 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2557 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2558 * 0bxx0x..This peripheral allows write accesses.
2559 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2560 * error response and no peripheral access is initiated on the IPS bus.
2561 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2562 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2563 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2564 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2565 * on the IPS bus.
2566 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2567 */
2568#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
2569/*! @} */
2570
2571/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
2572/*! @{ */
2573#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
2574#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
2575/*! OPAC23
2576 * 0bxxx0..Accesses from an untrusted master are allowed.
2577 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2578 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2579 * 0bxx0x..This peripheral allows write accesses.
2580 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2581 * error response and no peripheral access is initiated on the IPS bus.
2582 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2583 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2584 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2585 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2586 * on the IPS bus.
2587 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2588 */
2589#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
2590#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
2591#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
2592/*! OPAC22
2593 * 0bxxx0..Accesses from an untrusted master are allowed.
2594 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2595 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2596 * 0bxx0x..This peripheral allows write accesses.
2597 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2598 * error response and no peripheral access is initiated on the IPS bus.
2599 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2600 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2601 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2602 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2603 * on the IPS bus.
2604 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2605 */
2606#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
2607#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
2608#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
2609/*! OPAC21
2610 * 0bxxx0..Accesses from an untrusted master are allowed.
2611 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2612 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2613 * 0bxx0x..This peripheral allows write accesses.
2614 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2615 * error response and no peripheral access is initiated on the IPS bus.
2616 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2617 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2618 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2619 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2620 * on the IPS bus.
2621 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2622 */
2623#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
2624#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
2625#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
2626/*! OPAC20
2627 * 0bxxx0..Accesses from an untrusted master are allowed.
2628 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2629 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2630 * 0bxx0x..This peripheral allows write accesses.
2631 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2632 * error response and no peripheral access is initiated on the IPS bus.
2633 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2634 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2635 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2636 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2637 * on the IPS bus.
2638 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2639 */
2640#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
2641#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
2642#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
2643/*! OPAC19
2644 * 0bxxx0..Accesses from an untrusted master are allowed.
2645 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2646 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2647 * 0bxx0x..This peripheral allows write accesses.
2648 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2649 * error response and no peripheral access is initiated on the IPS bus.
2650 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2651 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2652 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2653 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2654 * on the IPS bus.
2655 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2656 */
2657#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
2658#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
2659#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
2660/*! OPAC18
2661 * 0bxxx0..Accesses from an untrusted master are allowed.
2662 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2663 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2664 * 0bxx0x..This peripheral allows write accesses.
2665 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2666 * error response and no peripheral access is initiated on the IPS bus.
2667 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2668 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2669 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2670 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2671 * on the IPS bus.
2672 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2673 */
2674#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
2675#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
2676#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
2677/*! OPAC17
2678 * 0bxxx0..Accesses from an untrusted master are allowed.
2679 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2680 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2681 * 0bxx0x..This peripheral allows write accesses.
2682 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2683 * error response and no peripheral access is initiated on the IPS bus.
2684 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2685 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2686 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2687 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2688 * on the IPS bus.
2689 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2690 */
2691#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
2692#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
2693#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
2694/*! OPAC16
2695 * 0bxxx0..Accesses from an untrusted master are allowed.
2696 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2697 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2698 * 0bxx0x..This peripheral allows write accesses.
2699 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2700 * error response and no peripheral access is initiated on the IPS bus.
2701 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2702 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2703 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2704 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2705 * on the IPS bus.
2706 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2707 */
2708#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
2709/*! @} */
2710
2711/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
2712/*! @{ */
2713#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
2714#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
2715/*! OPAC31
2716 * 0bxxx0..Accesses from an untrusted master are allowed.
2717 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2718 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2719 * 0bxx0x..This peripheral allows write accesses.
2720 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2721 * error response and no peripheral access is initiated on the IPS bus.
2722 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2723 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2724 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2725 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2726 * on the IPS bus.
2727 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2728 */
2729#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
2730#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
2731#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
2732/*! OPAC30
2733 * 0bxxx0..Accesses from an untrusted master are allowed.
2734 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2735 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2736 * 0bxx0x..This peripheral allows write accesses.
2737 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2738 * error response and no peripheral access is initiated on the IPS bus.
2739 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2740 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2741 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2742 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2743 * on the IPS bus.
2744 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2745 */
2746#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
2747#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
2748#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
2749/*! OPAC29
2750 * 0bxxx0..Accesses from an untrusted master are allowed.
2751 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2752 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2753 * 0bxx0x..This peripheral allows write accesses.
2754 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2755 * error response and no peripheral access is initiated on the IPS bus.
2756 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2757 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2758 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2759 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2760 * on the IPS bus.
2761 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2762 */
2763#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
2764#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
2765#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
2766/*! OPAC28
2767 * 0bxxx0..Accesses from an untrusted master are allowed.
2768 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2769 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2770 * 0bxx0x..This peripheral allows write accesses.
2771 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2772 * error response and no peripheral access is initiated on the IPS bus.
2773 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2774 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2775 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2776 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2777 * on the IPS bus.
2778 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2779 */
2780#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
2781#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
2782#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
2783/*! OPAC27
2784 * 0bxxx0..Accesses from an untrusted master are allowed.
2785 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2786 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2787 * 0bxx0x..This peripheral allows write accesses.
2788 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2789 * error response and no peripheral access is initiated on the IPS bus.
2790 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2791 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2792 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2793 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2794 * on the IPS bus.
2795 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2796 */
2797#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
2798#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
2799#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
2800/*! OPAC26
2801 * 0bxxx0..Accesses from an untrusted master are allowed.
2802 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2803 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2804 * 0bxx0x..This peripheral allows write accesses.
2805 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2806 * error response and no peripheral access is initiated on the IPS bus.
2807 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2808 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2809 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2810 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2811 * on the IPS bus.
2812 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2813 */
2814#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
2815#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
2816#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
2817/*! OPAC25
2818 * 0bxxx0..Accesses from an untrusted master are allowed.
2819 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2820 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2821 * 0bxx0x..This peripheral allows write accesses.
2822 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2823 * error response and no peripheral access is initiated on the IPS bus.
2824 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2825 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2826 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2827 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2828 * on the IPS bus.
2829 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2830 */
2831#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
2832#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
2833#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
2834/*! OPAC24
2835 * 0bxxx0..Accesses from an untrusted master are allowed.
2836 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2837 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2838 * 0bxx0x..This peripheral allows write accesses.
2839 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2840 * error response and no peripheral access is initiated on the IPS bus.
2841 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2842 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2843 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2844 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2845 * on the IPS bus.
2846 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2847 */
2848#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
2849/*! @} */
2850
2851/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
2852/*! @{ */
2853#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
2854#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
2855/*! OPAC33
2856 * 0bxxx0..Accesses from an untrusted master are allowed.
2857 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2858 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2859 * 0bxx0x..This peripheral allows write accesses.
2860 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2861 * error response and no peripheral access is initiated on the IPS bus.
2862 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2863 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2864 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2865 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2866 * on the IPS bus.
2867 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2868 */
2869#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
2870#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
2871#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
2872/*! OPAC32
2873 * 0bxxx0..Accesses from an untrusted master are allowed.
2874 * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
2875 * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
2876 * 0bxx0x..This peripheral allows write accesses.
2877 * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
2878 * error response and no peripheral access is initiated on the IPS bus.
2879 * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
2880 * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
2881 * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
2882 * be set. If not, the access is terminated with an error response and no peripheral access is initiated
2883 * on the IPS bus.
2884 * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
2885 */
2886#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
2887/*! @} */
2888
2889
2890/*!
2891 * @}
2892 */ /* end of group AIPSTZ_Register_Masks */
2893
2894
2895/* AIPSTZ - Peripheral instance base addresses */
2896/** Peripheral AIPSTZ1 base address */
2897#define AIPSTZ1_BASE (0x4007C000u)
2898/** Peripheral AIPSTZ1 base pointer */
2899#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
2900/** Peripheral AIPSTZ2 base address */
2901#define AIPSTZ2_BASE (0x4017C000u)
2902/** Peripheral AIPSTZ2 base pointer */
2903#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
2904/** Peripheral AIPSTZ3 base address */
2905#define AIPSTZ3_BASE (0x4027C000u)
2906/** Peripheral AIPSTZ3 base pointer */
2907#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
2908/** Peripheral AIPSTZ4 base address */
2909#define AIPSTZ4_BASE (0x4037C000u)
2910/** Peripheral AIPSTZ4 base pointer */
2911#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
2912/** Array initializer of AIPSTZ peripheral base addresses */
2913#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
2914/** Array initializer of AIPSTZ peripheral base pointers */
2915#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
2916
2917/*!
2918 * @}
2919 */ /* end of group AIPSTZ_Peripheral_Access_Layer */
2920
2921
2922/* ----------------------------------------------------------------------------
2923 -- AOI Peripheral Access Layer
2924 ---------------------------------------------------------------------------- */
2925
2926/*!
2927 * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
2928 * @{
2929 */
2930
2931/** AOI - Register Layout Typedef */
2932typedef struct {
2933 struct { /* offset: 0x0, array step: 0x4 */
2934 __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
2935 __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
2936 } BFCRT[4];
2937} AOI_Type;
2938
2939/* ----------------------------------------------------------------------------
2940 -- AOI Register Masks
2941 ---------------------------------------------------------------------------- */
2942
2943/*!
2944 * @addtogroup AOI_Register_Masks AOI Register Masks
2945 * @{
2946 */
2947
2948/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
2949/*! @{ */
2950#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
2951#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
2952/*! PT1_DC - Product term 1, D input configuration
2953 * 0b00..Force the D input in this product term to a logical zero
2954 * 0b01..Pass the D input in this product term
2955 * 0b10..Complement the D input in this product term
2956 * 0b11..Force the D input in this product term to a logical one
2957 */
2958#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
2959#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
2960#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
2961/*! PT1_CC - Product term 1, C input configuration
2962 * 0b00..Force the C input in this product term to a logical zero
2963 * 0b01..Pass the C input in this product term
2964 * 0b10..Complement the C input in this product term
2965 * 0b11..Force the C input in this product term to a logical one
2966 */
2967#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
2968#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
2969#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
2970/*! PT1_BC - Product term 1, B input configuration
2971 * 0b00..Force the B input in this product term to a logical zero
2972 * 0b01..Pass the B input in this product term
2973 * 0b10..Complement the B input in this product term
2974 * 0b11..Force the B input in this product term to a logical one
2975 */
2976#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
2977#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
2978#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
2979/*! PT1_AC - Product term 1, A input configuration
2980 * 0b00..Force the A input in this product term to a logical zero
2981 * 0b01..Pass the A input in this product term
2982 * 0b10..Complement the A input in this product term
2983 * 0b11..Force the A input in this product term to a logical one
2984 */
2985#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
2986#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
2987#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
2988/*! PT0_DC - Product term 0, D input configuration
2989 * 0b00..Force the D input in this product term to a logical zero
2990 * 0b01..Pass the D input in this product term
2991 * 0b10..Complement the D input in this product term
2992 * 0b11..Force the D input in this product term to a logical one
2993 */
2994#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
2995#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
2996#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
2997/*! PT0_CC - Product term 0, C input configuration
2998 * 0b00..Force the C input in this product term to a logical zero
2999 * 0b01..Pass the C input in this product term
3000 * 0b10..Complement the C input in this product term
3001 * 0b11..Force the C input in this product term to a logical one
3002 */
3003#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
3004#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
3005#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
3006/*! PT0_BC - Product term 0, B input configuration
3007 * 0b00..Force the B input in this product term to a logical zero
3008 * 0b01..Pass the B input in this product term
3009 * 0b10..Complement the B input in this product term
3010 * 0b11..Force the B input in this product term to a logical one
3011 */
3012#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
3013#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
3014#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
3015/*! PT0_AC - Product term 0, A input configuration
3016 * 0b00..Force the A input in this product term to a logical zero
3017 * 0b01..Pass the A input in this product term
3018 * 0b10..Complement the A input in this product term
3019 * 0b11..Force the A input in this product term to a logical one
3020 */
3021#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
3022/*! @} */
3023
3024/* The count of AOI_BFCRT01 */
3025#define AOI_BFCRT01_COUNT (4U)
3026
3027/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
3028/*! @{ */
3029#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
3030#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
3031/*! PT3_DC - Product term 3, D input configuration
3032 * 0b00..Force the D input in this product term to a logical zero
3033 * 0b01..Pass the D input in this product term
3034 * 0b10..Complement the D input in this product term
3035 * 0b11..Force the D input in this product term to a logical one
3036 */
3037#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
3038#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
3039#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
3040/*! PT3_CC - Product term 3, C input configuration
3041 * 0b00..Force the C input in this product term to a logical zero
3042 * 0b01..Pass the C input in this product term
3043 * 0b10..Complement the C input in this product term
3044 * 0b11..Force the C input in this product term to a logical one
3045 */
3046#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
3047#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
3048#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
3049/*! PT3_BC - Product term 3, B input configuration
3050 * 0b00..Force the B input in this product term to a logical zero
3051 * 0b01..Pass the B input in this product term
3052 * 0b10..Complement the B input in this product term
3053 * 0b11..Force the B input in this product term to a logical one
3054 */
3055#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
3056#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
3057#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
3058/*! PT3_AC - Product term 3, A input configuration
3059 * 0b00..Force the A input in this product term to a logical zero
3060 * 0b01..Pass the A input in this product term
3061 * 0b10..Complement the A input in this product term
3062 * 0b11..Force the A input in this product term to a logical one
3063 */
3064#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
3065#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
3066#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
3067/*! PT2_DC - Product term 2, D input configuration
3068 * 0b00..Force the D input in this product term to a logical zero
3069 * 0b01..Pass the D input in this product term
3070 * 0b10..Complement the D input in this product term
3071 * 0b11..Force the D input in this product term to a logical one
3072 */
3073#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
3074#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
3075#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
3076/*! PT2_CC - Product term 2, C input configuration
3077 * 0b00..Force the C input in this product term to a logical zero
3078 * 0b01..Pass the C input in this product term
3079 * 0b10..Complement the C input in this product term
3080 * 0b11..Force the C input in this product term to a logical one
3081 */
3082#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
3083#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
3084#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
3085/*! PT2_BC - Product term 2, B input configuration
3086 * 0b00..Force the B input in this product term to a logical zero
3087 * 0b01..Pass the B input in this product term
3088 * 0b10..Complement the B input in this product term
3089 * 0b11..Force the B input in this product term to a logical one
3090 */
3091#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
3092#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
3093#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
3094/*! PT2_AC - Product term 2, A input configuration
3095 * 0b00..Force the A input in this product term to a logical zero
3096 * 0b01..Pass the A input in this product term
3097 * 0b10..Complement the A input in this product term
3098 * 0b11..Force the A input in this product term to a logical one
3099 */
3100#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
3101/*! @} */
3102
3103/* The count of AOI_BFCRT23 */
3104#define AOI_BFCRT23_COUNT (4U)
3105
3106
3107/*!
3108 * @}
3109 */ /* end of group AOI_Register_Masks */
3110
3111
3112/* AOI - Peripheral instance base addresses */
3113/** Peripheral AOI1 base address */
3114#define AOI1_BASE (0x403B4000u)
3115/** Peripheral AOI1 base pointer */
3116#define AOI1 ((AOI_Type *)AOI1_BASE)
3117/** Peripheral AOI2 base address */
3118#define AOI2_BASE (0x403B8000u)
3119/** Peripheral AOI2 base pointer */
3120#define AOI2 ((AOI_Type *)AOI2_BASE)
3121/** Array initializer of AOI peripheral base addresses */
3122#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }
3123/** Array initializer of AOI peripheral base pointers */
3124#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }
3125
3126/*!
3127 * @}
3128 */ /* end of group AOI_Peripheral_Access_Layer */
3129
3130
3131/* ----------------------------------------------------------------------------
3132 -- BEE Peripheral Access Layer
3133 ---------------------------------------------------------------------------- */
3134
3135/*!
3136 * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer
3137 * @{
3138 */
3139
3140/** BEE - Register Layout Typedef */
3141typedef struct {
3142 __IO uint32_t CTRL; /**< Control Register, offset: 0x0 */
3143 __IO uint32_t ADDR_OFFSET0; /**< Offset region 0 Register, offset: 0x4 */
3144 __IO uint32_t ADDR_OFFSET1; /**< Offset region 1 Register, offset: 0x8 */
3145 __IO uint32_t AES_KEY0_W0; /**< AES Key 0 Register, offset: 0xC */
3146 __IO uint32_t AES_KEY0_W1; /**< AES Key 1 Register, offset: 0x10 */
3147 __IO uint32_t AES_KEY0_W2; /**< AES Key 2 Register, offset: 0x14 */
3148 __IO uint32_t AES_KEY0_W3; /**< AES Key 3 Register, offset: 0x18 */
3149 __IO uint32_t STATUS; /**< Status Register, offset: 0x1C */
3150 __O uint32_t CTR_NONCE0_W0; /**< NONCE00 Register, offset: 0x20 */
3151 __O uint32_t CTR_NONCE0_W1; /**< NONCE01 Register, offset: 0x24 */
3152 __O uint32_t CTR_NONCE0_W2; /**< NONCE02 Register, offset: 0x28 */
3153 __O uint32_t CTR_NONCE0_W3; /**< NONCE03 Register, offset: 0x2C */
3154 __O uint32_t CTR_NONCE1_W0; /**< NONCE10 Register, offset: 0x30 */
3155 __O uint32_t CTR_NONCE1_W1; /**< NONCE11 Register, offset: 0x34 */
3156 __O uint32_t CTR_NONCE1_W2; /**< NONCE12 Register, offset: 0x38 */
3157 __O uint32_t CTR_NONCE1_W3; /**< NONCE13 Register, offset: 0x3C */
3158 __IO uint32_t REGION1_TOP; /**< Region1 Top Address Register, offset: 0x40 */
3159 __IO uint32_t REGION1_BOT; /**< Region1 Bottom Address Register, offset: 0x44 */
3160} BEE_Type;
3161
3162/* ----------------------------------------------------------------------------
3163 -- BEE Register Masks
3164 ---------------------------------------------------------------------------- */
3165
3166/*!
3167 * @addtogroup BEE_Register_Masks BEE Register Masks
3168 * @{
3169 */
3170
3171/*! @name CTRL - Control Register */
3172/*! @{ */
3173#define BEE_CTRL_BEE_ENABLE_MASK (0x1U)
3174#define BEE_CTRL_BEE_ENABLE_SHIFT (0U)
3175/*! BEE_ENABLE
3176 * 0b0..Disable BEE
3177 * 0b1..Enable BEE
3178 */
3179#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
3180#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
3181#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
3182#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
3183#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
3184#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
3185#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
3186#define BEE_CTRL_KEY_VALID_MASK (0x10U)
3187#define BEE_CTRL_KEY_VALID_SHIFT (4U)
3188#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
3189#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
3190#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
3191/*! KEY_REGION_SEL
3192 * 0b0..Load AES key for region0
3193 * 0b1..Load AES key for region1
3194 */
3195#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
3196#define BEE_CTRL_AC_PROT_EN_MASK (0x40U)
3197#define BEE_CTRL_AC_PROT_EN_SHIFT (6U)
3198#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
3199#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
3200#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
3201/*! LITTLE_ENDIAN
3202 * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8,
3203 * B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to
3204 * Byte0 to Byte15.
3205 * 0b1..The input and output data of AES core is not swapped.
3206 */
3207#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
3208#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
3209#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
3210#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
3211#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
3212#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
3213/*! CTRL_AES_MODE_R0
3214 * 0b0..ECB
3215 * 0b1..CTR
3216 */
3217#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
3218#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
3219#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
3220#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
3221#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
3222#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
3223/*! CTRL_AES_MODE_R1
3224 * 0b0..ECB
3225 * 0b1..CTR
3226 */
3227#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
3228#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
3229#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
3230#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
3231#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
3232#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
3233#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
3234#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
3235#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
3236#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
3237#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
3238#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
3239#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
3240#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
3241#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
3242#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
3243#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
3244#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
3245#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
3246#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
3247#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
3248#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
3249#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
3250#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
3251#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
3252#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
3253#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
3254#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
3255#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
3256#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
3257#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
3258#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
3259#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
3260#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
3261#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
3262#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
3263#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
3264#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
3265#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
3266#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
3267#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
3268#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
3269#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
3270/*! @} */
3271
3272/*! @name ADDR_OFFSET0 - Offset region 0 Register */
3273/*! @{ */
3274#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
3275#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
3276#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
3277#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
3278#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
3279#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
3280/*! @} */
3281
3282/*! @name ADDR_OFFSET1 - Offset region 1 Register */
3283/*! @{ */
3284#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)
3285#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)
3286#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
3287#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)
3288#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
3289#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
3290/*! @} */
3291
3292/*! @name AES_KEY0_W0 - AES Key 0 Register */
3293/*! @{ */
3294#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
3295#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
3296/*! KEY0 - AES 128 key from software
3297 */
3298#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
3299/*! @} */
3300
3301/*! @name AES_KEY0_W1 - AES Key 1 Register */
3302/*! @{ */
3303#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
3304#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
3305/*! KEY1 - AES 128 key from software
3306 */
3307#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
3308/*! @} */
3309
3310/*! @name AES_KEY0_W2 - AES Key 2 Register */
3311/*! @{ */
3312#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
3313#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
3314/*! KEY2 - AES 128 key from software
3315 */
3316#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
3317/*! @} */
3318
3319/*! @name AES_KEY0_W3 - AES Key 3 Register */
3320/*! @{ */
3321#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
3322#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
3323/*! KEY3 - AES 128 key from software
3324 */
3325#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
3326/*! @} */
3327
3328/*! @name STATUS - Status Register */
3329/*! @{ */
3330#define BEE_STATUS_IRQ_VEC_MASK (0xFFU)
3331#define BEE_STATUS_IRQ_VEC_SHIFT (0U)
3332#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
3333#define BEE_STATUS_BEE_IDLE_MASK (0x100U)
3334#define BEE_STATUS_BEE_IDLE_SHIFT (8U)
3335#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
3336/*! @} */
3337
3338/*! @name CTR_NONCE0_W0 - NONCE00 Register */
3339/*! @{ */
3340#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
3341#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
3342#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
3343/*! @} */
3344
3345/*! @name CTR_NONCE0_W1 - NONCE01 Register */
3346/*! @{ */
3347#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
3348#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
3349#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
3350/*! @} */
3351
3352/*! @name CTR_NONCE0_W2 - NONCE02 Register */
3353/*! @{ */
3354#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
3355#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
3356#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
3357/*! @} */
3358
3359/*! @name CTR_NONCE0_W3 - NONCE03 Register */
3360/*! @{ */
3361#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
3362#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
3363#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
3364/*! @} */
3365
3366/*! @name CTR_NONCE1_W0 - NONCE10 Register */
3367/*! @{ */
3368#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
3369#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
3370#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
3371/*! @} */
3372
3373/*! @name CTR_NONCE1_W1 - NONCE11 Register */
3374/*! @{ */
3375#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
3376#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
3377#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
3378/*! @} */
3379
3380/*! @name CTR_NONCE1_W2 - NONCE12 Register */
3381/*! @{ */
3382#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
3383#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
3384#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
3385/*! @} */
3386
3387/*! @name CTR_NONCE1_W3 - NONCE13 Register */
3388/*! @{ */
3389#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
3390#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
3391#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
3392/*! @} */
3393
3394/*! @name REGION1_TOP - Region1 Top Address Register */
3395/*! @{ */
3396#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
3397#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
3398/*! REGION1_TOP - Address upper limit of region1
3399 */
3400#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
3401/*! @} */
3402
3403/*! @name REGION1_BOT - Region1 Bottom Address Register */
3404/*! @{ */
3405#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
3406#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
3407/*! REGION1_BOT - Address lower limit of region1
3408 */
3409#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)
3410/*! @} */
3411
3412
3413/*!
3414 * @}
3415 */ /* end of group BEE_Register_Masks */
3416
3417
3418/* BEE - Peripheral instance base addresses */
3419/** Peripheral BEE base address */
3420#define BEE_BASE (0x403EC000u)
3421/** Peripheral BEE base pointer */
3422#define BEE ((BEE_Type *)BEE_BASE)
3423/** Array initializer of BEE peripheral base addresses */
3424#define BEE_BASE_ADDRS { BEE_BASE }
3425/** Array initializer of BEE peripheral base pointers */
3426#define BEE_BASE_PTRS { BEE }
3427
3428/*!
3429 * @}
3430 */ /* end of group BEE_Peripheral_Access_Layer */
3431
3432
3433/* ----------------------------------------------------------------------------
3434 -- CAN Peripheral Access Layer
3435 ---------------------------------------------------------------------------- */
3436
3437/*!
3438 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
3439 * @{
3440 */
3441
3442/** CAN - Register Layout Typedef */
3443typedef struct {
3444 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
3445 __IO uint32_t CTRL1; /**< Control 1 Register..Control 1 register, offset: 0x4 */
3446 __IO uint32_t TIMER; /**< Free Running Timer Register..Free Running Timer, offset: 0x8 */
3447 uint8_t RESERVED_0[4];
3448 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
3449 __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register..Rx 14 Mask register, offset: 0x14 */
3450 __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register..Rx 15 Mask register, offset: 0x18 */
3451 __IO uint32_t ECR; /**< Error Counter Register..Error Counter, offset: 0x1C */
3452 __IO uint32_t ESR1; /**< Error and Status 1 Register..Error and Status 1 register, offset: 0x20 */
3453 __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register..Interrupt Masks 2 register, offset: 0x24 */
3454 __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register..Interrupt Masks 1 register, offset: 0x28 */
3455 __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register..Interrupt Flags 2 register, offset: 0x2C */
3456 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register..Interrupt Flags 1 register, offset: 0x30 */
3457 __IO uint32_t CTRL2; /**< Control 2 Register..Control 2 register, offset: 0x34 */
3458 __I uint32_t ESR2; /**< Error and Status 2 Register..Error and Status 2 register, offset: 0x38 */
3459 uint8_t RESERVED_1[8];
3460 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
3461 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register..Legacy Rx FIFO Global Mask register, offset: 0x48 */
3462 __I uint32_t RXFIR; /**< Rx FIFO Information Register..Legacy Rx FIFO Information Register, offset: 0x4C */
3463 __IO uint32_t CBT; /**< CAN Bit Timing Register, offset: 0x50 */
3464 uint8_t RESERVED_2[4];
3465 __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */
3466 __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */
3467 uint8_t RESERVED_3[32];
3468 union { /* offset: 0x80 */
3469 struct { /* offset: 0x80, array step: 0x10 */
3470 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
3471 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
3472 __IO uint32_t WORD[2]; /**< Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */
3473 } MB_8B[64];
3474 struct { /* offset: 0x80, array step: 0x18 */
3475 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 41 CS Register, array offset: 0x80, array step: 0x18 */
3476 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 41 ID Register, array offset: 0x84, array step: 0x18 */
3477 __IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 41 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */
3478 } MB_16B[42];
3479 struct { /* offset: 0x80, array step: 0x28 */
3480 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 23 CS Register, array offset: 0x80, array step: 0x28 */
3481 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 23 ID Register, array offset: 0x84, array step: 0x28 */
3482 __IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 23 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */
3483 } MB_32B[24];
3484 struct { /* offset: 0x80, array step: 0x48 */
3485 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 13 CS Register, array offset: 0x80, array step: 0x48 */
3486 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 13 ID Register, array offset: 0x84, array step: 0x48 */
3487 __IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */
3488 } MB_64B[14];
3489 struct { /* offset: 0x80, array step: 0x10 */
3490 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
3491 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
3492 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
3493 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
3494 } MB[64];
3495 };
3496 uint8_t RESERVED_4[1024];
3497 __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
3498 uint8_t RESERVED_5[96];
3499 __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */
3500 uint8_t RESERVED_6[524];
3501 __IO uint32_t EPRS; /**< Enhanced CAN Bit Timing Prescalers, offset: 0xBF0 */
3502 __IO uint32_t ENCBT; /**< Enhanced Nominal CAN Bit Timing, offset: 0xBF4 */
3503 __IO uint32_t EDCBT; /**< Enhanced Data Phase CAN bit Timing, offset: 0xBF8 */
3504 __IO uint32_t ETDC; /**< Enhanced Transceiver Delay Compensation, offset: 0xBFC */
3505 __IO uint32_t FDCTRL; /**< CAN FD Control Register, offset: 0xC00 */
3506 __IO uint32_t FDCBT; /**< CAN FD Bit Timing Register, offset: 0xC04 */
3507 __I uint32_t FDCRC; /**< CAN FD CRC Register, offset: 0xC08 */
3508 __IO uint32_t ERFCR; /**< Enhanced Rx FIFO Control Register, offset: 0xC0C */
3509 __IO uint32_t ERFIER; /**< Enhanced Rx FIFO Interrupt Enable register, offset: 0xC10 */
3510 __IO uint32_t ERFSR; /**< Enhanced Rx FIFO Status Register, offset: 0xC14 */
3511 uint8_t RESERVED_7[24];
3512 __I uint32_t HR_TIME_STAMP[64]; /**< High Resolution Time Stamp, array offset: 0xC30, array step: 0x4 */
3513 uint8_t RESERVED_8[8912];
3514 __IO uint32_t ERFFEL[128]; /**< Enhanced Rx FIFO Filter Element, array offset: 0x3000, array step: 0x4 */
3515} CAN_Type;
3516
3517/* ----------------------------------------------------------------------------
3518 -- CAN Register Masks
3519 ---------------------------------------------------------------------------- */
3520
3521/*!
3522 * @addtogroup CAN_Register_Masks CAN Register Masks
3523 * @{
3524 */
3525
3526/*! @name MCR - Module Configuration Register */
3527/*! @{ */
3528#define CAN_MCR_MAXMB_MASK (0x7FU)
3529#define CAN_MCR_MAXMB_SHIFT (0U)
3530/*! MAXMB - Number Of The Last Message Buffer
3531 */
3532#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
3533#define CAN_MCR_IDAM_MASK (0x300U)
3534#define CAN_MCR_IDAM_SHIFT (8U)
3535/*! IDAM - ID Acceptance Mode
3536 * 0b00..Format A One full ID (standard or extended) per ID filter Table element.
3537 * 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element.
3538 * 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element.
3539 * 0b11..Format D All frames rejected.
3540 */
3541#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
3542#define CAN_MCR_FDEN_MASK (0x800U)
3543#define CAN_MCR_FDEN_SHIFT (11U)
3544/*! FDEN - CAN FD operation enable
3545 * 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
3546 * 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
3547 */
3548#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
3549#define CAN_MCR_AEN_MASK (0x1000U)
3550#define CAN_MCR_AEN_SHIFT (12U)
3551/*! AEN - Abort Enable
3552 * 0b1..Abort enabled
3553 * 0b0..Abort disabled
3554 */
3555#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
3556#define CAN_MCR_LPRIOEN_MASK (0x2000U)
3557#define CAN_MCR_LPRIOEN_SHIFT (13U)
3558/*! LPRIOEN - Local Priority Enable
3559 * 0b1..Local Priority enabled
3560 * 0b0..Local Priority disabled
3561 */
3562#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
3563#define CAN_MCR_DMA_MASK (0x8000U)
3564#define CAN_MCR_DMA_SHIFT (15U)
3565/*! DMA - DMA Enable
3566 * 0b0..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO are disabled.
3567 * 0b1..DMA feature for Legacy RX FIFO or Enhanced Rx FIFO are enabled.
3568 */
3569#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
3570#define CAN_MCR_IRMQ_MASK (0x10000U)
3571#define CAN_MCR_IRMQ_SHIFT (16U)
3572/*! IRMQ - Individual Rx Masking And Queue Enable
3573 * 0b1..Individual Rx masking and queue feature are enabled.
3574 * 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY.
3575 */
3576#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
3577#define CAN_MCR_SRXDIS_MASK (0x20000U)
3578#define CAN_MCR_SRXDIS_SHIFT (17U)
3579/*! SRXDIS - Self Reception Disable
3580 * 0b1..Self reception disabled
3581 * 0b0..Self reception enabled
3582 */
3583#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
3584#define CAN_MCR_DOZE_MASK (0x40000U)
3585#define CAN_MCR_DOZE_SHIFT (18U)
3586/*! DOZE - Doze Mode Enable
3587 * 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
3588 * 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
3589 */
3590#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
3591#define CAN_MCR_WAKSRC_MASK (0x80000U)
3592#define CAN_MCR_WAKSRC_SHIFT (19U)
3593/*! WAKSRC - Wake Up Source
3594 * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus
3595 * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus.
3596 */
3597#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
3598#define CAN_MCR_LPMACK_MASK (0x100000U)
3599#define CAN_MCR_LPMACK_SHIFT (20U)
3600/*! LPMACK - Low-Power Mode Acknowledge
3601 * 0b1..FLEXCAN is either in Disable Mode, or Stop mode
3602 * 0b0..FLEXCAN not in any of the low power modes
3603 */
3604#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
3605#define CAN_MCR_WRNEN_MASK (0x200000U)
3606#define CAN_MCR_WRNEN_SHIFT (21U)
3607/*! WRNEN - Warning Interrupt Enable
3608 * 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96.
3609 * 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.
3610 */
3611#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
3612#define CAN_MCR_SLFWAK_MASK (0x400000U)
3613#define CAN_MCR_SLFWAK_SHIFT (22U)
3614/*! SLFWAK - Self Wake Up
3615 * 0b1..FLEXCAN Self Wake Up feature is enabled
3616 * 0b0..FLEXCAN Self Wake Up feature is disabled
3617 */
3618#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
3619#define CAN_MCR_SUPV_MASK (0x800000U)
3620#define CAN_MCR_SUPV_SHIFT (23U)
3621/*! SUPV - Supervisor Mode
3622 * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access
3623 * behaves as though the access was done to an unimplemented register location
3624 * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses
3625 */
3626#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
3627#define CAN_MCR_FRZACK_MASK (0x1000000U)
3628#define CAN_MCR_FRZACK_SHIFT (24U)
3629/*! FRZACK - Freeze Mode Acknowledge
3630 * 0b1..FLEXCAN in Freeze Mode, prescaler stopped
3631 * 0b0..FLEXCAN not in Freeze Mode, prescaler running
3632 */
3633#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
3634#define CAN_MCR_SOFTRST_MASK (0x2000000U)
3635#define CAN_MCR_SOFTRST_SHIFT (25U)
3636/*! SOFTRST - Soft Reset
3637 * 0b1..Reset the registers
3638 * 0b0..No reset request
3639 */
3640#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
3641#define CAN_MCR_WAKMSK_MASK (0x4000000U)
3642#define CAN_MCR_WAKMSK_SHIFT (26U)
3643/*! WAKMSK - Wake Up Interrupt Mask
3644 * 0b1..Wake Up Interrupt is enabled
3645 * 0b0..Wake Up Interrupt is disabled
3646 */
3647#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
3648#define CAN_MCR_NOTRDY_MASK (0x8000000U)
3649#define CAN_MCR_NOTRDY_SHIFT (27U)
3650/*! NOTRDY - FlexCAN Not Ready
3651 * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode
3652 * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode
3653 */
3654#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
3655#define CAN_MCR_HALT_MASK (0x10000000U)
3656#define CAN_MCR_HALT_SHIFT (28U)
3657/*! HALT - Halt FlexCAN
3658 * 0b1..Enters Freeze Mode if the FRZ bit is asserted.
3659 * 0b0..No Freeze Mode request.
3660 */
3661#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
3662#define CAN_MCR_RFEN_MASK (0x20000000U)
3663#define CAN_MCR_RFEN_SHIFT (29U)
3664/*! RFEN - Legacy Rx FIFO Enable
3665 * 0b1..FIFO enabled
3666 * 0b0..FIFO not enabled
3667 */
3668#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
3669#define CAN_MCR_FRZ_MASK (0x40000000U)
3670#define CAN_MCR_FRZ_SHIFT (30U)
3671/*! FRZ - Freeze Enable
3672 * 0b1..Enabled to enter Freeze Mode
3673 * 0b0..Not enabled to enter Freeze Mode
3674 */
3675#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
3676#define CAN_MCR_MDIS_MASK (0x80000000U)
3677#define CAN_MCR_MDIS_SHIFT (31U)
3678/*! MDIS - Module Disable
3679 * 0b1..Disable the FLEXCAN module
3680 * 0b0..Enable the FLEXCAN module
3681 */
3682#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
3683/*! @} */
3684
3685/*! @name CTRL1 - Control 1 Register..Control 1 register */
3686/*! @{ */
3687#define CAN_CTRL1_PROPSEG_MASK (0x7U)
3688#define CAN_CTRL1_PROPSEG_SHIFT (0U)
3689/*! PROPSEG - Propagation Segment
3690 */
3691#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
3692#define CAN_CTRL1_LOM_MASK (0x8U)
3693#define CAN_CTRL1_LOM_SHIFT (3U)
3694/*! LOM - Listen-Only Mode
3695 * 0b1..FLEXCAN module operates in Listen Only Mode
3696 * 0b0..Listen Only Mode is deactivated
3697 */
3698#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
3699#define CAN_CTRL1_LBUF_MASK (0x10U)
3700#define CAN_CTRL1_LBUF_SHIFT (4U)
3701/*! LBUF - Lowest Buffer Transmitted First
3702 * 0b1..Lowest number buffer is transmitted first
3703 * 0b0..Buffer with highest priority is transmitted first
3704 */
3705#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
3706#define CAN_CTRL1_TSYN_MASK (0x20U)
3707#define CAN_CTRL1_TSYN_SHIFT (5U)
3708/*! TSYN - Timer Sync
3709 * 0b1..Timer Sync feature enabled
3710 * 0b0..Timer Sync feature disabled
3711 */
3712#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
3713#define CAN_CTRL1_BOFFREC_MASK (0x40U)
3714#define CAN_CTRL1_BOFFREC_SHIFT (6U)
3715/*! BOFFREC - Bus Off Recovery
3716 * 0b1..Automatic recovering from Bus Off state disabled
3717 * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
3718 */
3719#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
3720#define CAN_CTRL1_SMP_MASK (0x80U)
3721#define CAN_CTRL1_SMP_SHIFT (7U)
3722/*! SMP - CAN Bit Sampling
3723 * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2
3724 * preceding samples, a majority rule is used
3725 * 0b0..Just one sample is used to determine the bit value
3726 */
3727#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
3728#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
3729#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
3730/*! RWRNMSK - Rx Warning Interrupt Mask
3731 * 0b1..Rx Warning Interrupt enabled
3732 * 0b0..Rx Warning Interrupt disabled
3733 */
3734#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
3735#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
3736#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
3737/*! TWRNMSK - Tx Warning Interrupt Mask
3738 * 0b1..Tx Warning Interrupt enabled
3739 * 0b0..Tx Warning Interrupt disabled
3740 */
3741#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
3742#define CAN_CTRL1_LPB_MASK (0x1000U)
3743#define CAN_CTRL1_LPB_SHIFT (12U)
3744/*! LPB - Loop Back Mode
3745 * 0b1..Loop Back enabled
3746 * 0b0..Loop Back disabled
3747 */
3748#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
3749#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
3750#define CAN_CTRL1_CLKSRC_SHIFT (13U)
3751/*! CLKSRC - CAN Engine Clock Source
3752 * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
3753 * 0b1..The CAN engine clock source is the peripheral clock.
3754 */
3755#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
3756#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
3757#define CAN_CTRL1_ERRMSK_SHIFT (14U)
3758/*! ERRMSK - Error Interrupt Mask
3759 * 0b1..Error interrupt enabled
3760 * 0b0..Error interrupt disabled
3761 */
3762#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
3763#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
3764#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
3765/*! BOFFMSK - Bus Off Interrupt Mask
3766 * 0b1..Bus Off interrupt enabled
3767 * 0b0..Bus Off interrupt disabled
3768 */
3769#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
3770#define CAN_CTRL1_PSEG2_MASK (0x70000U)
3771#define CAN_CTRL1_PSEG2_SHIFT (16U)
3772/*! PSEG2 - Phase Segment 2
3773 */
3774#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
3775#define CAN_CTRL1_PSEG1_MASK (0x380000U)
3776#define CAN_CTRL1_PSEG1_SHIFT (19U)
3777/*! PSEG1 - Phase Segment 1
3778 */
3779#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
3780#define CAN_CTRL1_RJW_MASK (0xC00000U)
3781#define CAN_CTRL1_RJW_SHIFT (22U)
3782/*! RJW - Resync Jump Width
3783 */
3784#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
3785#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
3786#define CAN_CTRL1_PRESDIV_SHIFT (24U)
3787/*! PRESDIV - Prescaler Division Factor
3788 */
3789#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
3790/*! @} */
3791
3792/*! @name TIMER - Free Running Timer Register..Free Running Timer */
3793/*! @{ */
3794#define CAN_TIMER_TIMER_MASK (0xFFFFU)
3795#define CAN_TIMER_TIMER_SHIFT (0U)
3796/*! TIMER - Timer Value
3797 */
3798#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
3799/*! @} */
3800
3801/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
3802/*! @{ */
3803#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
3804#define CAN_RXMGMASK_MG_SHIFT (0U)
3805/*! MG - Rx Mailboxes Global Mask Bits
3806 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received
3807 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
3808 */
3809#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
3810/*! @} */
3811
3812/*! @name RX14MASK - Rx Buffer 14 Mask Register..Rx 14 Mask register */
3813/*! @{ */
3814#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
3815#define CAN_RX14MASK_RX14M_SHIFT (0U)
3816/*! RX14M - Rx Buffer 14 Mask Bits
3817 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
3818 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
3819 */
3820#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
3821/*! @} */
3822
3823/*! @name RX15MASK - Rx Buffer 15 Mask Register..Rx 15 Mask register */
3824/*! @{ */
3825#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
3826#define CAN_RX15MASK_RX15M_SHIFT (0U)
3827/*! RX15M - Rx Buffer 15 Mask Bits
3828 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
3829 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
3830 */
3831#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
3832/*! @} */
3833
3834/*! @name ECR - Error Counter Register..Error Counter */
3835/*! @{ */
3836#define CAN_ECR_TXERRCNT_MASK (0xFFU)
3837#define CAN_ECR_TXERRCNT_SHIFT (0U)
3838/*! TXERRCNT - Transmit Error Counter
3839 */
3840#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
3841#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)
3842#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)
3843#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
3844#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
3845#define CAN_ECR_RXERRCNT_SHIFT (8U)
3846/*! RXERRCNT - Receive Error Counter
3847 */
3848#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
3849#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)
3850#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)
3851#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
3852#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)
3853#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U)
3854/*! TXERRCNT_FAST - Transmit Error Counter for fast bits
3855 */
3856#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
3857#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)
3858#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U)
3859/*! RXERRCNT_FAST - Receive Error Counter for fast bits
3860 */
3861#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
3862/*! @} */
3863
3864/*! @name ESR1 - Error and Status 1 Register..Error and Status 1 register */
3865/*! @{ */
3866#define CAN_ESR1_WAKINT_MASK (0x1U)
3867#define CAN_ESR1_WAKINT_SHIFT (0U)
3868/*! WAKINT - Wake-Up Interrupt
3869 * 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode
3870 * 0b0..No such occurrence
3871 */
3872#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
3873#define CAN_ESR1_ERRINT_MASK (0x2U)
3874#define CAN_ESR1_ERRINT_SHIFT (1U)
3875/*! ERRINT - Error Interrupt
3876 * 0b1..Indicates setting of any Error Bit in the Error and Status Register
3877 * 0b0..No such occurrence
3878 */
3879#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
3880#define CAN_ESR1_BOFFINT_MASK (0x4U)
3881#define CAN_ESR1_BOFFINT_SHIFT (2U)
3882/*! BOFFINT - Bus Off Interrupt
3883 * 0b1..FLEXCAN module entered 'Bus Off' state
3884 * 0b0..No such occurrence
3885 */
3886#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
3887#define CAN_ESR1_RX_MASK (0x8U)
3888#define CAN_ESR1_RX_SHIFT (3U)
3889/*! RX - FlexCAN In Reception
3890 * 0b1..FLEXCAN is transmitting a message
3891 * 0b0..FLEXCAN is receiving a message
3892 */
3893#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
3894#define CAN_ESR1_FLTCONF_MASK (0x30U)
3895#define CAN_ESR1_FLTCONF_SHIFT (4U)
3896/*! FLTCONF - Fault Confinement State
3897 * 0b00..Error Active
3898 * 0b01..Error Passive
3899 * 0b1x..Bus off
3900 */
3901#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
3902#define CAN_ESR1_TX_MASK (0x40U)
3903#define CAN_ESR1_TX_SHIFT (6U)
3904/*! TX - FlexCAN In Transmission
3905 * 0b1..FLEXCAN is transmitting a message
3906 * 0b0..FLEXCAN is receiving a message
3907 */
3908#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
3909#define CAN_ESR1_IDLE_MASK (0x80U)
3910#define CAN_ESR1_IDLE_SHIFT (7U)
3911/*! IDLE - IDLE
3912 * 0b1..CAN bus is now IDLE
3913 * 0b0..No such occurrence
3914 */
3915#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
3916#define CAN_ESR1_RXWRN_MASK (0x100U)
3917#define CAN_ESR1_RXWRN_SHIFT (8U)
3918/*! RXWRN - Rx Error Warning
3919 * 0b1..Rx_Err_Counter >= 96
3920 * 0b0..No such occurrence
3921 */
3922#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
3923#define CAN_ESR1_TXWRN_MASK (0x200U)
3924#define CAN_ESR1_TXWRN_SHIFT (9U)
3925/*! TXWRN - TX Error Warning
3926 * 0b1..TX_Err_Counter >= 96
3927 * 0b0..No such occurrence
3928 */
3929#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
3930#define CAN_ESR1_STFERR_MASK (0x400U)
3931#define CAN_ESR1_STFERR_SHIFT (10U)
3932/*! STFERR - Stuffing Error
3933 * 0b1..A Stuffing Error occurred since last read of this register.
3934 * 0b0..No such occurrence.
3935 */
3936#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
3937#define CAN_ESR1_FRMERR_MASK (0x800U)
3938#define CAN_ESR1_FRMERR_SHIFT (11U)
3939/*! FRMERR - Form Error
3940 * 0b1..A Form Error occurred since last read of this register
3941 * 0b0..No such occurrence
3942 */
3943#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
3944#define CAN_ESR1_CRCERR_MASK (0x1000U)
3945#define CAN_ESR1_CRCERR_SHIFT (12U)
3946/*! CRCERR - Cyclic Redundancy Check Error
3947 * 0b1..A CRC error occurred since last read of this register.
3948 * 0b0..No such occurrence
3949 */
3950#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
3951#define CAN_ESR1_ACKERR_MASK (0x2000U)
3952#define CAN_ESR1_ACKERR_SHIFT (13U)
3953/*! ACKERR - Acknowledge Error
3954 * 0b1..An ACK error occurred since last read of this register
3955 * 0b0..No such occurrence
3956 */
3957#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
3958#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
3959#define CAN_ESR1_BIT0ERR_SHIFT (14U)
3960/*! BIT0ERR - Bit0 Error
3961 * 0b1..At least one bit sent as dominant is received as recessive
3962 * 0b0..No such occurrence
3963 */
3964#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
3965#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
3966#define CAN_ESR1_BIT1ERR_SHIFT (15U)
3967/*! BIT1ERR - Bit1 Error
3968 * 0b1..At least one bit sent as recessive is received as dominant
3969 * 0b0..No such occurrence
3970 */
3971#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
3972#define CAN_ESR1_RWRNINT_MASK (0x10000U)
3973#define CAN_ESR1_RWRNINT_SHIFT (16U)
3974/*! RWRNINT - Rx Warning Interrupt Flag
3975 * 0b1..The Rx error counter transition from < 96 to >= 96
3976 * 0b0..No such occurrence
3977 */
3978#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
3979#define CAN_ESR1_TWRNINT_MASK (0x20000U)
3980#define CAN_ESR1_TWRNINT_SHIFT (17U)
3981/*! TWRNINT - Tx Warning Interrupt Flag
3982 * 0b1..The Tx error counter transition from < 96 to >= 96
3983 * 0b0..No such occurrence
3984 */
3985#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
3986#define CAN_ESR1_SYNCH_MASK (0x40000U)
3987#define CAN_ESR1_SYNCH_SHIFT (18U)
3988/*! SYNCH - CAN Synchronization Status
3989 * 0b1..FlexCAN is synchronized to the CAN bus
3990 * 0b0..FlexCAN is not synchronized to the CAN bus
3991 */
3992#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
3993#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U)
3994#define CAN_ESR1_BOFFDONEINT_SHIFT (19U)
3995/*! BOFFDONEINT - Bus Off Done Interrupt
3996 * 0b0..No such occurrence.
3997 * 0b1..FlexCAN module has completed Bus Off process.
3998 */
3999#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
4000#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U)
4001#define CAN_ESR1_ERRINT_FAST_SHIFT (20U)
4002/*! ERRINT_FAST - Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set
4003 * 0b0..No such occurrence.
4004 * 0b1..Indicates setting of any Error Bit detected in the Data Phase of CAN FD frames with the BRS bit set.
4005 */
4006#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
4007#define CAN_ESR1_ERROVR_MASK (0x200000U)
4008#define CAN_ESR1_ERROVR_SHIFT (21U)
4009/*! ERROVR - Error Overrun bit
4010 * 0b0..Overrun has not occurred.
4011 * 0b1..Overrun has occurred.
4012 */
4013#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
4014#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U)
4015#define CAN_ESR1_STFERR_FAST_SHIFT (26U)
4016/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
4017 * 0b0..No such occurrence.
4018 * 0b1..A Stuffing Error occurred since last read of this register.
4019 */
4020#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
4021#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U)
4022#define CAN_ESR1_FRMERR_FAST_SHIFT (27U)
4023/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
4024 * 0b0..No such occurrence.
4025 * 0b1..A Form Error occurred since last read of this register.
4026 */
4027#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
4028#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U)
4029#define CAN_ESR1_CRCERR_FAST_SHIFT (28U)
4030/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
4031 * 0b0..No such occurrence.
4032 * 0b1..A CRC error occurred since last read of this register.
4033 */
4034#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
4035#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U)
4036#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U)
4037/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
4038 * 0b0..No such occurrence.
4039 * 0b1..At least one bit sent as dominant is received as recessive.
4040 */
4041#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
4042#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U)
4043#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U)
4044/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
4045 * 0b0..No such occurrence.
4046 * 0b1..At least one bit sent as recessive is received as dominant.
4047 */
4048#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
4049/*! @} */
4050
4051/*! @name IMASK2 - Interrupt Masks 2 Register..Interrupt Masks 2 register */
4052/*! @{ */
4053#define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU)
4054#define CAN_IMASK2_BUF63TO32M_SHIFT (0U)
4055/*! BUF63TO32M - Buffer MB i Mask
4056 */
4057#define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
4058#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)
4059#define CAN_IMASK2_BUFHM_SHIFT (0U)
4060/*! BUFHM
4061 * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
4062 * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
4063 */
4064#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
4065/*! @} */
4066
4067/*! @name IMASK1 - Interrupt Masks 1 Register..Interrupt Masks 1 register */
4068/*! @{ */
4069#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)
4070#define CAN_IMASK1_BUF31TO0M_SHIFT (0U)
4071/*! BUF31TO0M - Buffer MB i Mask
4072 */
4073#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
4074#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
4075#define CAN_IMASK1_BUFLM_SHIFT (0U)
4076/*! BUFLM
4077 * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
4078 * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
4079 */
4080#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
4081/*! @} */
4082
4083/*! @name IFLAG2 - Interrupt Flags 2 Register..Interrupt Flags 2 register */
4084/*! @{ */
4085#define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU)
4086#define CAN_IFLAG2_BUF63TO32I_SHIFT (0U)
4087/*! BUF63TO32I - Buffer MB i Interrupt
4088 */
4089#define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
4090#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)
4091#define CAN_IFLAG2_BUFHI_SHIFT (0U)
4092/*! BUFHI
4093 * 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception
4094 * 0b00000000000000000000000000000000..No such occurrence
4095 */
4096#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
4097/*! @} */
4098
4099/*! @name IFLAG1 - Interrupt Flags 1 Register..Interrupt Flags 1 register */
4100/*! @{ */
4101#define CAN_IFLAG1_BUF0I_MASK (0x1U)
4102#define CAN_IFLAG1_BUF0I_SHIFT (0U)
4103/*! BUF0I - Buffer MB0 Interrupt Or Clear Legacy FIFO bit
4104 * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when CAN_MCR[RFEN]=0.
4105 * 0b1..The corresponding buffer has successfully completed transmission or reception when CAN_MCR[RFEN]=0.
4106 */
4107#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
4108#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)
4109#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U)
4110/*! BUF4TO0I
4111 * 0b00001..Corresponding MB completed transmission/reception
4112 * 0b00000..No such occurrence
4113 */
4114#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
4115#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
4116#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
4117/*! BUF4TO1I - Buffer MB i Interrupt Or "reserved"
4118 */
4119#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
4120#define CAN_IFLAG1_BUF5I_MASK (0x20U)
4121#define CAN_IFLAG1_BUF5I_SHIFT (5U)
4122/*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Legacy Rx FIFO"
4123 * 0b1..MB5 completed transmission/reception or frames available in the FIFO
4124 * 0b0..No such occurrence
4125 */
4126#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4127#define CAN_IFLAG1_BUF6I_MASK (0x40U)
4128#define CAN_IFLAG1_BUF6I_SHIFT (6U)
4129/*! BUF6I - Buffer MB6 Interrupt Or "Legacy Rx FIFO Warning"
4130 * 0b1..MB6 completed transmission/reception or FIFO almost full
4131 * 0b0..No such occurrence
4132 */
4133#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4134#define CAN_IFLAG1_BUF7I_MASK (0x80U)
4135#define CAN_IFLAG1_BUF7I_SHIFT (7U)
4136/*! BUF7I - Buffer MB7 Interrupt Or "Legacy Rx FIFO Overflow"
4137 * 0b1..MB7 completed transmission/reception or FIFO overflow
4138 * 0b0..No such occurrence
4139 */
4140#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4141#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
4142#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
4143/*! BUF31TO8I - Buffer MBi Interrupt
4144 * 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception
4145 * 0b000000000000000000000000..No such occurrence
4146 */
4147#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
4148/*! @} */
4149
4150/*! @name CTRL2 - Control 2 Register..Control 2 register */
4151/*! @{ */
4152#define CAN_CTRL2_TSTAMPCAP_MASK (0xC0U)
4153#define CAN_CTRL2_TSTAMPCAP_SHIFT (6U)
4154/*! TSTAMPCAP - Time Stamp Capture Point
4155 * 0b00..The high resolution time stamp capture is disabled
4156 * 0b01..The high resolution time stamp is captured in the end of the CAN frame
4157 * 0b10..The high resolution time stamp is captured in the start of the CAN frame
4158 * 0b11..The high resolution time stamp is captured in the start of frame for classical CAN frames and in res bit for CAN FD frames
4159 */
4160#define CAN_CTRL2_TSTAMPCAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TSTAMPCAP_SHIFT)) & CAN_CTRL2_TSTAMPCAP_MASK)
4161#define CAN_CTRL2_MBTSBASE_MASK (0x300U)
4162#define CAN_CTRL2_MBTSBASE_SHIFT (8U)
4163/*! MBTSBASE - Message Buffer Time Stamp Base
4164 * 0b00..Message Buffer Time Stamp base is CAN_TIMER
4165 * 0b01..Message Buffer Time Stamp base is lower 16-bits of high resolution timer
4166 * 0b10..Message Buffer Time Stamp base is upper 16-bits of high resolution timerT
4167 * 0b11..Reserved.
4168 */
4169#define CAN_CTRL2_MBTSBASE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MBTSBASE_SHIFT)) & CAN_CTRL2_MBTSBASE_MASK)
4170#define CAN_CTRL2_EDFLTDIS_MASK (0x800U)
4171#define CAN_CTRL2_EDFLTDIS_SHIFT (11U)
4172/*! EDFLTDIS - Edge Filter Disable
4173 * 0b0..Edge Filter is enabled
4174 * 0b1..Edge Filter is disabled
4175 */
4176#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
4177#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U)
4178#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U)
4179/*! ISOCANFDEN - ISO CAN FD Enable
4180 * 0b0..FlexCAN operates using the non-ISO CAN FD protocol.
4181 * 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
4182 */
4183#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
4184#define CAN_CTRL2_BTE_MASK (0x2000U)
4185#define CAN_CTRL2_BTE_SHIFT (13U)
4186/*! BTE - Bit Timing Expansion enable
4187 * 0b0..CAN Bit timing expansion is disabled.
4188 * 0b1..CAN bit timing expansion is enabled.
4189 */
4190#define CAN_CTRL2_BTE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BTE_SHIFT)) & CAN_CTRL2_BTE_MASK)
4191#define CAN_CTRL2_PREXCEN_MASK (0x4000U)
4192#define CAN_CTRL2_PREXCEN_SHIFT (14U)
4193/*! PREXCEN - Protocol Exception Enable
4194 * 0b0..Protocol Exception is disabled.
4195 * 0b1..Protocol Exception is enabled.
4196 */
4197#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
4198#define CAN_CTRL2_TIMER_SRC_MASK (0x8000U)
4199#define CAN_CTRL2_TIMER_SRC_SHIFT (15U)
4200/*! TIMER_SRC - Timer Source
4201 * 0b0..The Free Running Timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus.
4202 * 0b1..The Free Running Timer is clocked by an external time tick. The period can be either adjusted to be equal
4203 * to the baud rate on the CAN bus, or a different value as required. See the device specific section for
4204 * details about the external time tick.
4205 */
4206#define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)
4207#define CAN_CTRL2_EACEN_MASK (0x10000U)
4208#define CAN_CTRL2_EACEN_SHIFT (16U)
4209/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
4210 * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within
4211 * the incoming frame. Mask bits do apply.
4212 * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
4213 */
4214#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
4215#define CAN_CTRL2_RRS_MASK (0x20000U)
4216#define CAN_CTRL2_RRS_SHIFT (17U)
4217/*! RRS - Remote Request Storing
4218 * 0b1..Remote Request Frame is stored
4219 * 0b0..Remote Response Frame is generated
4220 */
4221#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
4222#define CAN_CTRL2_MRP_MASK (0x40000U)
4223#define CAN_CTRL2_MRP_SHIFT (18U)
4224/*! MRP - Mailboxes Reception Priority
4225 * 0b1..Matching starts from Mailboxes and continues on Rx FIFO
4226 * 0b0..Matching starts from Rx FIFO and continues on Mailboxes
4227 */
4228#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
4229#define CAN_CTRL2_TASD_MASK (0xF80000U)
4230#define CAN_CTRL2_TASD_SHIFT (19U)
4231/*! TASD - Tx Arbitration Start Delay
4232 */
4233#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
4234#define CAN_CTRL2_RFFN_MASK (0xF000000U)
4235#define CAN_CTRL2_RFFN_SHIFT (24U)
4236/*! RFFN - Number Of Legacy Rx FIFO Filters
4237 */
4238#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
4239#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
4240#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
4241/*! WRMFRZ
4242 * 0b1..Enable unrestricted write access to FlexCAN memory
4243 * 0b0..Keep the write access restricted in some regions of FlexCAN memory
4244 */
4245#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
4246#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)
4247#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)
4248/*! BOFFDONEMSK - Bus Off Done Interrupt Mask
4249 * 0b0..Bus Off Done interrupt disabled.
4250 * 0b1..Bus Off Done interrupt enabled.
4251 */
4252#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
4253#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U)
4254#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U)
4255/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames
4256 * 0b0..ERRINT_FAST Error interrupt disabled.
4257 * 0b1..ERRINT_FAST Error interrupt enabled.
4258 */
4259#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
4260/*! @} */
4261
4262/*! @name ESR2 - Error and Status 2 Register..Error and Status 2 register */
4263/*! @{ */
4264#define CAN_ESR2_IMB_MASK (0x2000U)
4265#define CAN_ESR2_IMB_SHIFT (13U)
4266/*! IMB - Inactive Mailbox
4267 * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.
4268 * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
4269 */
4270#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
4271#define CAN_ESR2_VPS_MASK (0x4000U)
4272#define CAN_ESR2_VPS_SHIFT (14U)
4273/*! VPS - Valid Priority Status
4274 * 0b1..Contents of IMB and LPTM are valid
4275 * 0b0..Contents of IMB and LPTM are invalid
4276 */
4277#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
4278#define CAN_ESR2_LPTM_MASK (0x7F0000U)
4279#define CAN_ESR2_LPTM_SHIFT (16U)
4280/*! LPTM - Lowest Priority Tx Mailbox
4281 */
4282#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
4283/*! @} */
4284
4285/*! @name CRCR - CRC Register */
4286/*! @{ */
4287#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
4288#define CAN_CRCR_TXCRC_SHIFT (0U)
4289/*! TXCRC - Transmitted CRC value
4290 */
4291#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
4292#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
4293#define CAN_CRCR_MBCRC_SHIFT (16U)
4294/*! MBCRC - CRC Mailbox
4295 */
4296#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
4297/*! @} */
4298
4299/*! @name RXFGMASK - Rx FIFO Global Mask Register..Legacy Rx FIFO Global Mask register */
4300/*! @{ */
4301#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
4302#define CAN_RXFGMASK_FGM_SHIFT (0U)
4303/*! FGM - Legacy Rx FIFO Global Mask Bits
4304 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
4305 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care"
4306 */
4307#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
4308/*! @} */
4309
4310/*! @name RXFIR - Rx FIFO Information Register..Legacy Rx FIFO Information Register */
4311/*! @{ */
4312#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
4313#define CAN_RXFIR_IDHIT_SHIFT (0U)
4314/*! IDHIT - Identifier Acceptance Filter Hit Indicator
4315 */
4316#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
4317/*! @} */
4318
4319/*! @name CBT - CAN Bit Timing Register */
4320/*! @{ */
4321#define CAN_CBT_EPSEG2_MASK (0x1FU)
4322#define CAN_CBT_EPSEG2_SHIFT (0U)
4323/*! EPSEG2 - Extended Phase Segment 2
4324 */
4325#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
4326#define CAN_CBT_EPSEG1_MASK (0x3E0U)
4327#define CAN_CBT_EPSEG1_SHIFT (5U)
4328/*! EPSEG1 - Extended Phase Segment 1
4329 */
4330#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
4331#define CAN_CBT_EPROPSEG_MASK (0xFC00U)
4332#define CAN_CBT_EPROPSEG_SHIFT (10U)
4333/*! EPROPSEG - Extended Propagation Segment
4334 */
4335#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
4336#define CAN_CBT_ERJW_MASK (0x1F0000U)
4337#define CAN_CBT_ERJW_SHIFT (16U)
4338/*! ERJW - Extended Resync Jump Width
4339 */
4340#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
4341#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U)
4342#define CAN_CBT_EPRESDIV_SHIFT (21U)
4343/*! EPRESDIV - Extended Prescaler Division Factor
4344 */
4345#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
4346#define CAN_CBT_BTF_MASK (0x80000000U)
4347#define CAN_CBT_BTF_SHIFT (31U)
4348/*! BTF - Bit Timing Format Enable
4349 * 0b0..Extended bit time definitions disabled.
4350 * 0b1..Extended bit time definitions enabled.
4351 */
4352#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
4353/*! @} */
4354
4355/*! @name DBG1 - Debug 1 register */
4356/*! @{ */
4357#define CAN_DBG1_CFSM_MASK (0x3FU)
4358#define CAN_DBG1_CFSM_SHIFT (0U)
4359/*! CFSM - CAN Finite State Machine
4360 */
4361#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
4362#define CAN_DBG1_CBN_MASK (0x1F000000U)
4363#define CAN_DBG1_CBN_SHIFT (24U)
4364/*! CBN - CAN Bit Number
4365 */
4366#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
4367/*! @} */
4368
4369/*! @name DBG2 - Debug 2 register */
4370/*! @{ */
4371#define CAN_DBG2_RMP_MASK (0x7FU)
4372#define CAN_DBG2_RMP_SHIFT (0U)
4373/*! RMP - Rx Matching Pointer
4374 */
4375#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
4376#define CAN_DBG2_MPP_MASK (0x80U)
4377#define CAN_DBG2_MPP_SHIFT (7U)
4378/*! MPP - Matching Process in Progress
4379 * 0b0..No matching process ongoing.
4380 * 0b1..Matching process is in progress.
4381 */
4382#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
4383#define CAN_DBG2_TAP_MASK (0x7F00U)
4384#define CAN_DBG2_TAP_SHIFT (8U)
4385/*! TAP - Tx Arbitration Pointer
4386 */
4387#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
4388#define CAN_DBG2_APP_MASK (0x8000U)
4389#define CAN_DBG2_APP_SHIFT (15U)
4390/*! APP - Arbitration Process in Progress
4391 * 0b0..No matching process ongoing.
4392 * 0b1..Matching process is in progress.
4393 */
4394#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
4395/*! @} */
4396
4397/* The count of CAN_CS */
4398#define CAN_CS_COUNT_MB8B (64U)
4399
4400/* The count of CAN_ID */
4401#define CAN_ID_COUNT_MB8B (64U)
4402
4403/* The count of CAN_WORD */
4404#define CAN_WORD_COUNT_MB8B (64U)
4405
4406/* The count of CAN_WORD */
4407#define CAN_WORD_COUNT_MB8B2 (2U)
4408
4409/* The count of CAN_CS */
4410#define CAN_CS_COUNT_MB16B (42U)
4411
4412/* The count of CAN_ID */
4413#define CAN_ID_COUNT_MB16B (42U)
4414
4415/* The count of CAN_WORD */
4416#define CAN_WORD_COUNT_MB16B (42U)
4417
4418/* The count of CAN_WORD */
4419#define CAN_WORD_COUNT_MB16B2 (4U)
4420
4421/* The count of CAN_CS */
4422#define CAN_CS_COUNT_MB32B (24U)
4423
4424/* The count of CAN_ID */
4425#define CAN_ID_COUNT_MB32B (24U)
4426
4427/* The count of CAN_WORD */
4428#define CAN_WORD_COUNT_MB32B (24U)
4429
4430/* The count of CAN_WORD */
4431#define CAN_WORD_COUNT_MB32B2 (8U)
4432
4433/*! @name CS - Message Buffer 0 CS Register..Message Buffer 13 CS Register */
4434/*! @{ */
4435#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
4436#define CAN_CS_TIME_STAMP_SHIFT (0U)
4437/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
4438 * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
4439 * appears on the CAN bus.
4440 */
4441#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
4442#define CAN_CS_DLC_MASK (0xF0000U)
4443#define CAN_CS_DLC_SHIFT (16U)
4444/*! DLC - Length of the data to be stored/transmitted.
4445 */
4446#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
4447#define CAN_CS_RTR_MASK (0x100000U)
4448#define CAN_CS_RTR_SHIFT (20U)
4449/*! RTR - Remote Transmission Request. One/zero for remote/data frame.
4450 */
4451#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
4452#define CAN_CS_IDE_MASK (0x200000U)
4453#define CAN_CS_IDE_SHIFT (21U)
4454/*! IDE - ID Extended. One/zero for extended/standard format frame.
4455 */
4456#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
4457#define CAN_CS_SRR_MASK (0x400000U)
4458#define CAN_CS_SRR_SHIFT (22U)
4459/*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
4460 */
4461#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
4462#define CAN_CS_CODE_MASK (0xF000000U)
4463#define CAN_CS_CODE_SHIFT (24U)
4464/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
4465 * the FlexCAN module itself, as part of the message buffer matching and arbitration process.
4466 */
4467#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
4468#define CAN_CS_ESI_MASK (0x20000000U)
4469#define CAN_CS_ESI_SHIFT (29U)
4470/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
4471 */
4472#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
4473#define CAN_CS_BRS_MASK (0x40000000U)
4474#define CAN_CS_BRS_SHIFT (30U)
4475/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
4476 */
4477#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
4478#define CAN_CS_EDL_MASK (0x80000000U)
4479#define CAN_CS_EDL_SHIFT (31U)
4480/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
4481 * The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
4482 */
4483#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
4484/*! @} */
4485
4486/* The count of CAN_CS */
4487#define CAN_CS_COUNT_MB64B (14U)
4488
4489/*! @name ID - Message Buffer 0 ID Register..Message Buffer 13 ID Register */
4490/*! @{ */
4491#define CAN_ID_EXT_MASK (0x3FFFFU)
4492#define CAN_ID_EXT_SHIFT (0U)
4493/*! EXT - Contains extended (LOW word) identifier of message buffer.
4494 */
4495#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
4496#define CAN_ID_STD_MASK (0x1FFC0000U)
4497#define CAN_ID_STD_SHIFT (18U)
4498/*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
4499 */
4500#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
4501#define CAN_ID_PRIO_MASK (0xE0000000U)
4502#define CAN_ID_PRIO_SHIFT (29U)
4503/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
4504 * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
4505 * ID to define the transmission priority.
4506 */
4507#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
4508/*! @} */
4509
4510/* The count of CAN_ID */
4511#define CAN_ID_COUNT_MB64B (14U)
4512
4513/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 13 WORD_64B Register */
4514/*! @{ */
4515#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU)
4516#define CAN_WORD_DATA_BYTE_3_SHIFT (0U)
4517/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
4518 */
4519#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
4520#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU)
4521#define CAN_WORD_DATA_BYTE_7_SHIFT (0U)
4522/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
4523 */
4524#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
4525#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU)
4526#define CAN_WORD_DATA_BYTE_11_SHIFT (0U)
4527/*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame.
4528 */
4529#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
4530#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU)
4531#define CAN_WORD_DATA_BYTE_15_SHIFT (0U)
4532/*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame.
4533 */
4534#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
4535#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU)
4536#define CAN_WORD_DATA_BYTE_19_SHIFT (0U)
4537/*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame.
4538 */
4539#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
4540#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU)
4541#define CAN_WORD_DATA_BYTE_23_SHIFT (0U)
4542/*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame.
4543 */
4544#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
4545#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU)
4546#define CAN_WORD_DATA_BYTE_27_SHIFT (0U)
4547/*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame.
4548 */
4549#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
4550#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU)
4551#define CAN_WORD_DATA_BYTE_31_SHIFT (0U)
4552/*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame.
4553 */
4554#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
4555#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU)
4556#define CAN_WORD_DATA_BYTE_35_SHIFT (0U)
4557/*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame.
4558 */
4559#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
4560#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU)
4561#define CAN_WORD_DATA_BYTE_39_SHIFT (0U)
4562/*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame.
4563 */
4564#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
4565#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU)
4566#define CAN_WORD_DATA_BYTE_43_SHIFT (0U)
4567/*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame.
4568 */
4569#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
4570#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU)
4571#define CAN_WORD_DATA_BYTE_47_SHIFT (0U)
4572/*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame.
4573 */
4574#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
4575#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU)
4576#define CAN_WORD_DATA_BYTE_51_SHIFT (0U)
4577/*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame.
4578 */
4579#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
4580#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU)
4581#define CAN_WORD_DATA_BYTE_55_SHIFT (0U)
4582/*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame.
4583 */
4584#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
4585#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU)
4586#define CAN_WORD_DATA_BYTE_59_SHIFT (0U)
4587/*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame.
4588 */
4589#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
4590#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU)
4591#define CAN_WORD_DATA_BYTE_63_SHIFT (0U)
4592/*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame.
4593 */
4594#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
4595#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U)
4596#define CAN_WORD_DATA_BYTE_2_SHIFT (8U)
4597/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
4598 */
4599#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
4600#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U)
4601#define CAN_WORD_DATA_BYTE_6_SHIFT (8U)
4602/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
4603 */
4604#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
4605#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U)
4606#define CAN_WORD_DATA_BYTE_10_SHIFT (8U)
4607/*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame.
4608 */
4609#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
4610#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U)
4611#define CAN_WORD_DATA_BYTE_14_SHIFT (8U)
4612/*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame.
4613 */
4614#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
4615#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U)
4616#define CAN_WORD_DATA_BYTE_18_SHIFT (8U)
4617/*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame.
4618 */
4619#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
4620#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U)
4621#define CAN_WORD_DATA_BYTE_22_SHIFT (8U)
4622/*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame.
4623 */
4624#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
4625#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U)
4626#define CAN_WORD_DATA_BYTE_26_SHIFT (8U)
4627/*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame.
4628 */
4629#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
4630#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U)
4631#define CAN_WORD_DATA_BYTE_30_SHIFT (8U)
4632/*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame.
4633 */
4634#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
4635#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U)
4636#define CAN_WORD_DATA_BYTE_34_SHIFT (8U)
4637/*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame.
4638 */
4639#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
4640#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U)
4641#define CAN_WORD_DATA_BYTE_38_SHIFT (8U)
4642/*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame.
4643 */
4644#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
4645#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U)
4646#define CAN_WORD_DATA_BYTE_42_SHIFT (8U)
4647/*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame.
4648 */
4649#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
4650#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U)
4651#define CAN_WORD_DATA_BYTE_46_SHIFT (8U)
4652/*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame.
4653 */
4654#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
4655#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U)
4656#define CAN_WORD_DATA_BYTE_50_SHIFT (8U)
4657/*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame.
4658 */
4659#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
4660#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U)
4661#define CAN_WORD_DATA_BYTE_54_SHIFT (8U)
4662/*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame.
4663 */
4664#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
4665#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U)
4666#define CAN_WORD_DATA_BYTE_58_SHIFT (8U)
4667/*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame.
4668 */
4669#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
4670#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U)
4671#define CAN_WORD_DATA_BYTE_62_SHIFT (8U)
4672/*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame.
4673 */
4674#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
4675#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U)
4676#define CAN_WORD_DATA_BYTE_1_SHIFT (16U)
4677/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
4678 */
4679#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
4680#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U)
4681#define CAN_WORD_DATA_BYTE_5_SHIFT (16U)
4682/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
4683 */
4684#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
4685#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U)
4686#define CAN_WORD_DATA_BYTE_9_SHIFT (16U)
4687/*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame.
4688 */
4689#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
4690#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U)
4691#define CAN_WORD_DATA_BYTE_13_SHIFT (16U)
4692/*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame.
4693 */
4694#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
4695#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U)
4696#define CAN_WORD_DATA_BYTE_17_SHIFT (16U)
4697/*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame.
4698 */
4699#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
4700#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U)
4701#define CAN_WORD_DATA_BYTE_21_SHIFT (16U)
4702/*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame.
4703 */
4704#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
4705#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U)
4706#define CAN_WORD_DATA_BYTE_25_SHIFT (16U)
4707/*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame.
4708 */
4709#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
4710#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U)
4711#define CAN_WORD_DATA_BYTE_29_SHIFT (16U)
4712/*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame.
4713 */
4714#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
4715#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U)
4716#define CAN_WORD_DATA_BYTE_33_SHIFT (16U)
4717/*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame.
4718 */
4719#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
4720#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U)
4721#define CAN_WORD_DATA_BYTE_37_SHIFT (16U)
4722/*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame.
4723 */
4724#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
4725#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U)
4726#define CAN_WORD_DATA_BYTE_41_SHIFT (16U)
4727/*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame.
4728 */
4729#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
4730#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U)
4731#define CAN_WORD_DATA_BYTE_45_SHIFT (16U)
4732/*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame.
4733 */
4734#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
4735#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U)
4736#define CAN_WORD_DATA_BYTE_49_SHIFT (16U)
4737/*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame.
4738 */
4739#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
4740#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U)
4741#define CAN_WORD_DATA_BYTE_53_SHIFT (16U)
4742/*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame.
4743 */
4744#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
4745#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U)
4746#define CAN_WORD_DATA_BYTE_57_SHIFT (16U)
4747/*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame.
4748 */
4749#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
4750#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U)
4751#define CAN_WORD_DATA_BYTE_61_SHIFT (16U)
4752/*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame.
4753 */
4754#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
4755#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U)
4756#define CAN_WORD_DATA_BYTE_0_SHIFT (24U)
4757/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
4758 */
4759#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
4760#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U)
4761#define CAN_WORD_DATA_BYTE_4_SHIFT (24U)
4762/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
4763 */
4764#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
4765#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U)
4766#define CAN_WORD_DATA_BYTE_8_SHIFT (24U)
4767/*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame.
4768 */
4769#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
4770#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U)
4771#define CAN_WORD_DATA_BYTE_12_SHIFT (24U)
4772/*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame.
4773 */
4774#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
4775#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U)
4776#define CAN_WORD_DATA_BYTE_16_SHIFT (24U)
4777/*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame.
4778 */
4779#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
4780#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U)
4781#define CAN_WORD_DATA_BYTE_20_SHIFT (24U)
4782/*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame.
4783 */
4784#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
4785#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U)
4786#define CAN_WORD_DATA_BYTE_24_SHIFT (24U)
4787/*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame.
4788 */
4789#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
4790#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U)
4791#define CAN_WORD_DATA_BYTE_28_SHIFT (24U)
4792/*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame.
4793 */
4794#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
4795#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U)
4796#define CAN_WORD_DATA_BYTE_32_SHIFT (24U)
4797/*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame.
4798 */
4799#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
4800#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U)
4801#define CAN_WORD_DATA_BYTE_36_SHIFT (24U)
4802/*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame.
4803 */
4804#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
4805#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U)
4806#define CAN_WORD_DATA_BYTE_40_SHIFT (24U)
4807/*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame.
4808 */
4809#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
4810#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U)
4811#define CAN_WORD_DATA_BYTE_44_SHIFT (24U)
4812/*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame.
4813 */
4814#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
4815#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U)
4816#define CAN_WORD_DATA_BYTE_48_SHIFT (24U)
4817/*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame.
4818 */
4819#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
4820#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U)
4821#define CAN_WORD_DATA_BYTE_52_SHIFT (24U)
4822/*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame.
4823 */
4824#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
4825#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U)
4826#define CAN_WORD_DATA_BYTE_56_SHIFT (24U)
4827/*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame.
4828 */
4829#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
4830#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U)
4831#define CAN_WORD_DATA_BYTE_60_SHIFT (24U)
4832/*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame.
4833 */
4834#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
4835/*! @} */
4836
4837/* The count of CAN_WORD */
4838#define CAN_WORD_COUNT_MB64B (14U)
4839
4840/* The count of CAN_WORD */
4841#define CAN_WORD_COUNT_MB64B2 (16U)
4842
4843/* The count of CAN_CS */
4844#define CAN_CS_COUNT (64U)
4845
4846/* The count of CAN_ID */
4847#define CAN_ID_COUNT (64U)
4848
4849/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
4850/*! @{ */
4851#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
4852#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
4853/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
4854 */
4855#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
4856#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
4857#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
4858/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
4859 */
4860#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
4861#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
4862#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
4863/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
4864 */
4865#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
4866#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
4867#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
4868/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
4869 */
4870#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
4871/*! @} */
4872
4873/* The count of CAN_WORD0 */
4874#define CAN_WORD0_COUNT (64U)
4875
4876/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
4877/*! @{ */
4878#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
4879#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
4880/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
4881 */
4882#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
4883#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
4884#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
4885/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
4886 */
4887#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
4888#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
4889#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
4890/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
4891 */
4892#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
4893#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
4894#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
4895/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
4896 */
4897#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
4898/*! @} */
4899
4900/* The count of CAN_WORD1 */
4901#define CAN_WORD1_COUNT (64U)
4902
4903/*! @name RXIMR - Rx Individual Mask Registers */
4904/*! @{ */
4905#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
4906#define CAN_RXIMR_MI_SHIFT (0U)
4907/*! MI - Individual Mask Bits
4908 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
4909 * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
4910 */
4911#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
4912/*! @} */
4913
4914/* The count of CAN_RXIMR */
4915#define CAN_RXIMR_COUNT (64U)
4916
4917/*! @name GFWR - Glitch Filter Width Registers */
4918/*! @{ */
4919#define CAN_GFWR_GFWR_MASK (0xFFU)
4920#define CAN_GFWR_GFWR_SHIFT (0U)
4921#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)
4922/*! @} */
4923
4924/*! @name EPRS - Enhanced CAN Bit Timing Prescalers */
4925/*! @{ */
4926#define CAN_EPRS_ENPRESDIV_MASK (0x3FFU)
4927#define CAN_EPRS_ENPRESDIV_SHIFT (0U)
4928/*! ENPRESDIV - Extended Nominal Prescaler Division Factor
4929 */
4930#define CAN_EPRS_ENPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_ENPRESDIV_SHIFT)) & CAN_EPRS_ENPRESDIV_MASK)
4931#define CAN_EPRS_EDPRESDIV_MASK (0x3FF0000U)
4932#define CAN_EPRS_EDPRESDIV_SHIFT (16U)
4933/*! EDPRESDIV - Extended Data Phase Prescaler Division Factor
4934 */
4935#define CAN_EPRS_EDPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_EPRS_EDPRESDIV_SHIFT)) & CAN_EPRS_EDPRESDIV_MASK)
4936/*! @} */
4937
4938/*! @name ENCBT - Enhanced Nominal CAN Bit Timing */
4939/*! @{ */
4940#define CAN_ENCBT_NTSEG1_MASK (0xFFU)
4941#define CAN_ENCBT_NTSEG1_SHIFT (0U)
4942/*! NTSEG1 - Nominal Time Segment 1
4943 */
4944#define CAN_ENCBT_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG1_SHIFT)) & CAN_ENCBT_NTSEG1_MASK)
4945#define CAN_ENCBT_NTSEG2_MASK (0x7F000U)
4946#define CAN_ENCBT_NTSEG2_SHIFT (12U)
4947/*! NTSEG2 - Nominal Time Segment 2
4948 */
4949#define CAN_ENCBT_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NTSEG2_SHIFT)) & CAN_ENCBT_NTSEG2_MASK)
4950#define CAN_ENCBT_NRJW_MASK (0x1FC00000U)
4951#define CAN_ENCBT_NRJW_SHIFT (22U)
4952/*! NRJW - Nominal Resynchronization Jump Width
4953 */
4954#define CAN_ENCBT_NRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ENCBT_NRJW_SHIFT)) & CAN_ENCBT_NRJW_MASK)
4955/*! @} */
4956
4957/*! @name EDCBT - Enhanced Data Phase CAN bit Timing */
4958/*! @{ */
4959#define CAN_EDCBT_DTSEG1_MASK (0x1FU)
4960#define CAN_EDCBT_DTSEG1_SHIFT (0U)
4961/*! DTSEG1 - Data Phase Segment 1
4962 */
4963#define CAN_EDCBT_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG1_SHIFT)) & CAN_EDCBT_DTSEG1_MASK)
4964#define CAN_EDCBT_DTSEG2_MASK (0xF000U)
4965#define CAN_EDCBT_DTSEG2_SHIFT (12U)
4966/*! DTSEG2 - Data Phase Time Segment 2
4967 */
4968#define CAN_EDCBT_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DTSEG2_SHIFT)) & CAN_EDCBT_DTSEG2_MASK)
4969#define CAN_EDCBT_DRJW_MASK (0x3C00000U)
4970#define CAN_EDCBT_DRJW_SHIFT (22U)
4971/*! DRJW - Data Phase Resynchronization Jump Width
4972 */
4973#define CAN_EDCBT_DRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_EDCBT_DRJW_SHIFT)) & CAN_EDCBT_DRJW_MASK)
4974/*! @} */
4975
4976/*! @name ETDC - Enhanced Transceiver Delay Compensation */
4977/*! @{ */
4978#define CAN_ETDC_ETDCVAL_MASK (0xFFU)
4979#define CAN_ETDC_ETDCVAL_SHIFT (0U)
4980/*! ETDCVAL - Enhanced Transceiver Delay Compensation Value
4981 */
4982#define CAN_ETDC_ETDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCVAL_SHIFT)) & CAN_ETDC_ETDCVAL_MASK)
4983#define CAN_ETDC_ETDCOFF_MASK (0x7F0000U)
4984#define CAN_ETDC_ETDCOFF_SHIFT (16U)
4985/*! ETDCOFF - Enhanced Transceiver Delay Compensation Offset
4986 */
4987#define CAN_ETDC_ETDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_ETDCOFF_SHIFT)) & CAN_ETDC_ETDCOFF_MASK)
4988#define CAN_ETDC_TDMDIS_MASK (0x80000000U)
4989#define CAN_ETDC_TDMDIS_SHIFT (31U)
4990/*! TDMDIS - Transceiver Delay Measurement Disable
4991 * 0b0..TDC measurement is enabled
4992 * 0b1..TDC measurement is disabled
4993 */
4994#define CAN_ETDC_TDMDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETDC_TDMDIS_SHIFT)) & CAN_ETDC_TDMDIS_MASK)
4995/*! @} */
4996
4997/*! @name FDCTRL - CAN FD Control Register */
4998/*! @{ */
4999#define CAN_FDCTRL_TDCVAL_MASK (0x3FU)
5000#define CAN_FDCTRL_TDCVAL_SHIFT (0U)
5001/*! TDCVAL - Transceiver Delay Compensation Value
5002 */
5003#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
5004#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U)
5005#define CAN_FDCTRL_TDCOFF_SHIFT (8U)
5006/*! TDCOFF - Transceiver Delay Compensation Offset
5007 */
5008#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
5009#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U)
5010#define CAN_FDCTRL_TDCFAIL_SHIFT (14U)
5011/*! TDCFAIL - Transceiver Delay Compensation Fail
5012 * 0b0..Measured loop delay is in range.
5013 * 0b1..Measured loop delay is out of range.
5014 */
5015#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
5016#define CAN_FDCTRL_TDCEN_MASK (0x8000U)
5017#define CAN_FDCTRL_TDCEN_SHIFT (15U)
5018/*! TDCEN - Transceiver Delay Compensation Enable
5019 * 0b0..TDC is disabled
5020 * 0b1..TDC is enabled
5021 */
5022#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
5023#define CAN_FDCTRL_MBDSR0_MASK (0x30000U)
5024#define CAN_FDCTRL_MBDSR0_SHIFT (16U)
5025/*! MBDSR0 - Message Buffer Data Size for Region 0
5026 * 0b00..Selects 8 bytes per Message Buffer.
5027 * 0b01..Selects 16 bytes per Message Buffer.
5028 * 0b10..Selects 32 bytes per Message Buffer.
5029 * 0b11..Selects 64 bytes per Message Buffer.
5030 */
5031#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
5032#define CAN_FDCTRL_MBDSR1_MASK (0x180000U)
5033#define CAN_FDCTRL_MBDSR1_SHIFT (19U)
5034/*! MBDSR1 - Message Buffer Data Size for Region 1
5035 * 0b00..Selects 8 bytes per Message Buffer.
5036 * 0b01..Selects 16 bytes per Message Buffer.
5037 * 0b10..Selects 32 bytes per Message Buffer.
5038 * 0b11..Selects 64 bytes per Message Buffer.
5039 */
5040#define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
5041#define CAN_FDCTRL_FDRATE_MASK (0x80000000U)
5042#define CAN_FDCTRL_FDRATE_SHIFT (31U)
5043/*! FDRATE - Bit Rate Switch Enable
5044 * 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
5045 * 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
5046 */
5047#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
5048/*! @} */
5049
5050/*! @name FDCBT - CAN FD Bit Timing Register */
5051/*! @{ */
5052#define CAN_FDCBT_FPSEG2_MASK (0x7U)
5053#define CAN_FDCBT_FPSEG2_SHIFT (0U)
5054/*! FPSEG2 - Fast Phase Segment 2
5055 */
5056#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
5057#define CAN_FDCBT_FPSEG1_MASK (0xE0U)
5058#define CAN_FDCBT_FPSEG1_SHIFT (5U)
5059/*! FPSEG1 - Fast Phase Segment 1
5060 */
5061#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
5062#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U)
5063#define CAN_FDCBT_FPROPSEG_SHIFT (10U)
5064/*! FPROPSEG - Fast Propagation Segment
5065 */
5066#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
5067#define CAN_FDCBT_FRJW_MASK (0x70000U)
5068#define CAN_FDCBT_FRJW_SHIFT (16U)
5069/*! FRJW - Fast Resync Jump Width
5070 */
5071#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
5072#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U)
5073#define CAN_FDCBT_FPRESDIV_SHIFT (20U)
5074/*! FPRESDIV - Fast Prescaler Division Factor
5075 */
5076#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
5077/*! @} */
5078
5079/*! @name FDCRC - CAN FD CRC Register */
5080/*! @{ */
5081#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU)
5082#define CAN_FDCRC_FD_TXCRC_SHIFT (0U)
5083/*! FD_TXCRC - Extended Transmitted CRC value
5084 */
5085#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
5086#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U)
5087#define CAN_FDCRC_FD_MBCRC_SHIFT (24U)
5088/*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC
5089 */
5090#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
5091/*! @} */
5092
5093/*! @name ERFCR - Enhanced Rx FIFO Control Register */
5094/*! @{ */
5095#define CAN_ERFCR_ERFWM_MASK (0x1FU)
5096#define CAN_ERFCR_ERFWM_SHIFT (0U)
5097/*! ERFWM - Enhanced Rx FIFO Watermark
5098 */
5099#define CAN_ERFCR_ERFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFWM_SHIFT)) & CAN_ERFCR_ERFWM_MASK)
5100#define CAN_ERFCR_NFE_MASK (0x3F00U)
5101#define CAN_ERFCR_NFE_SHIFT (8U)
5102/*! NFE - Number of Enhanced Rx FIFO Filter Elements
5103 */
5104#define CAN_ERFCR_NFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NFE_SHIFT)) & CAN_ERFCR_NFE_MASK)
5105#define CAN_ERFCR_NEXIF_MASK (0x7F0000U)
5106#define CAN_ERFCR_NEXIF_SHIFT (16U)
5107/*! NEXIF - Number of Extended ID Filter Elements
5108 */
5109#define CAN_ERFCR_NEXIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_NEXIF_SHIFT)) & CAN_ERFCR_NEXIF_MASK)
5110#define CAN_ERFCR_DMALW_MASK (0x7C000000U)
5111#define CAN_ERFCR_DMALW_SHIFT (26U)
5112/*! DMALW - DMA Last Word
5113 */
5114#define CAN_ERFCR_DMALW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_DMALW_SHIFT)) & CAN_ERFCR_DMALW_MASK)
5115#define CAN_ERFCR_ERFEN_MASK (0x80000000U)
5116#define CAN_ERFCR_ERFEN_SHIFT (31U)
5117/*! ERFEN - Enhanced Rx FIFO enable
5118 * 0b0..Enhanced Rx FIFO is disabled
5119 * 0b1..Enhanced Rx FIFO is enabled
5120 */
5121#define CAN_ERFCR_ERFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFCR_ERFEN_SHIFT)) & CAN_ERFCR_ERFEN_MASK)
5122/*! @} */
5123
5124/*! @name ERFIER - Enhanced Rx FIFO Interrupt Enable register */
5125/*! @{ */
5126#define CAN_ERFIER_ERFDAIE_MASK (0x10000000U)
5127#define CAN_ERFIER_ERFDAIE_SHIFT (28U)
5128/*! ERFDAIE - Enhanced Rx FIFO Data Available Interrupt Enable
5129 * 0b0..Enhanced Rx FIFO Data Available Interrupt is disabled
5130 * 0b1..Enhanced Rx FIFO Data Available Interrupt is enabled
5131 */
5132#define CAN_ERFIER_ERFDAIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFDAIE_SHIFT)) & CAN_ERFIER_ERFDAIE_MASK)
5133#define CAN_ERFIER_ERFWMIIE_MASK (0x20000000U)
5134#define CAN_ERFIER_ERFWMIIE_SHIFT (29U)
5135/*! ERFWMIIE - Enhanced Rx FIFO Watermark Indication Interrupt Enable
5136 * 0b0..Enhanced Rx FIFO Watermark Interrupt is disabled
5137 * 0b1..Enhanced Rx FIFO Watermark Interrupt is enabled
5138 */
5139#define CAN_ERFIER_ERFWMIIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFWMIIE_SHIFT)) & CAN_ERFIER_ERFWMIIE_MASK)
5140#define CAN_ERFIER_ERFOVFIE_MASK (0x40000000U)
5141#define CAN_ERFIER_ERFOVFIE_SHIFT (30U)
5142/*! ERFOVFIE - Enhanced Rx FIFO Overflow Interrupt Enable
5143 * 0b0..Enhanced Rx FIFO Overflow is disabled
5144 * 0b1..Enhanced Rx FIFO Overflow is enabled
5145 */
5146#define CAN_ERFIER_ERFOVFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFOVFIE_SHIFT)) & CAN_ERFIER_ERFOVFIE_MASK)
5147#define CAN_ERFIER_ERFUFWIE_MASK (0x80000000U)
5148#define CAN_ERFIER_ERFUFWIE_SHIFT (31U)
5149/*! ERFUFWIE - Enhanced Rx FIFO Underflow Interrupt Enable
5150 * 0b0..Enhanced Rx FIFO Underflow interrupt is disabled
5151 * 0b1..Enhanced Rx FIFO Underflow interrupt is enabled
5152 */
5153#define CAN_ERFIER_ERFUFWIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFIER_ERFUFWIE_SHIFT)) & CAN_ERFIER_ERFUFWIE_MASK)
5154/*! @} */
5155
5156/*! @name ERFSR - Enhanced Rx FIFO Status Register */
5157/*! @{ */
5158#define CAN_ERFSR_ERFEL_MASK (0x3FU)
5159#define CAN_ERFSR_ERFEL_SHIFT (0U)
5160/*! ERFEL - Enhanced Rx FIFO Elements
5161 */
5162#define CAN_ERFSR_ERFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFEL_SHIFT)) & CAN_ERFSR_ERFEL_MASK)
5163#define CAN_ERFSR_ERFF_MASK (0x10000U)
5164#define CAN_ERFSR_ERFF_SHIFT (16U)
5165/*! ERFF - Enhanced Rx FIFO full
5166 * 0b0..Enhanced Rx FIFO is not full
5167 * 0b1..Enhanced Rx FIFO is full
5168 */
5169#define CAN_ERFSR_ERFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFF_SHIFT)) & CAN_ERFSR_ERFF_MASK)
5170#define CAN_ERFSR_ERFE_MASK (0x20000U)
5171#define CAN_ERFSR_ERFE_SHIFT (17U)
5172/*! ERFE - Enhanced Rx FIFO empty
5173 * 0b0..Enhanced Rx FIFO is not empty
5174 * 0b1..Enhanced Rx FIFO is empty
5175 */
5176#define CAN_ERFSR_ERFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFE_SHIFT)) & CAN_ERFSR_ERFE_MASK)
5177#define CAN_ERFSR_ERFCLR_MASK (0x8000000U)
5178#define CAN_ERFSR_ERFCLR_SHIFT (27U)
5179/*! ERFCLR - Enhanced Rx FIFO Clear
5180 * 0b0..No effect
5181 * 0b1..Clear Enhanced Rx FIFO content
5182 */
5183#define CAN_ERFSR_ERFCLR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFCLR_SHIFT)) & CAN_ERFSR_ERFCLR_MASK)
5184#define CAN_ERFSR_ERFDA_MASK (0x10000000U)
5185#define CAN_ERFSR_ERFDA_SHIFT (28U)
5186/*! ERFDA - Enhanced Rx FIFO Data Available
5187 * 0b0..No such occurrence
5188 * 0b1..There is at least one message stored in Enhanced Rx FIFO
5189 */
5190#define CAN_ERFSR_ERFDA(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFDA_SHIFT)) & CAN_ERFSR_ERFDA_MASK)
5191#define CAN_ERFSR_ERFWMI_MASK (0x20000000U)
5192#define CAN_ERFSR_ERFWMI_SHIFT (29U)
5193/*! ERFWMI - Enhanced Rx FIFO Watermark Indication
5194 * 0b0..No such occurrence
5195 * 0b1..The number of messages in FIFO is greater than the watermark
5196 */
5197#define CAN_ERFSR_ERFWMI(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFWMI_SHIFT)) & CAN_ERFSR_ERFWMI_MASK)
5198#define CAN_ERFSR_ERFOVF_MASK (0x40000000U)
5199#define CAN_ERFSR_ERFOVF_SHIFT (30U)
5200/*! ERFOVF - Enhanced Rx FIFO Overflow
5201 * 0b0..No such occurrence
5202 * 0b1..Enhanced Rx FIFO overflow
5203 */
5204#define CAN_ERFSR_ERFOVF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFOVF_SHIFT)) & CAN_ERFSR_ERFOVF_MASK)
5205#define CAN_ERFSR_ERFUFW_MASK (0x80000000U)
5206#define CAN_ERFSR_ERFUFW_SHIFT (31U)
5207/*! ERFUFW - Enhanced Rx FIFO Underflow
5208 * 0b0..No such occurrence
5209 * 0b1..Enhanced Rx FIFO underflow
5210 */
5211#define CAN_ERFSR_ERFUFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFSR_ERFUFW_SHIFT)) & CAN_ERFSR_ERFUFW_MASK)
5212/*! @} */
5213
5214/*! @name HR_TIME_STAMP - High Resolution Time Stamp */
5215/*! @{ */
5216#define CAN_HR_TIME_STAMP_TS_MASK (0xFFFFFFFFU)
5217#define CAN_HR_TIME_STAMP_TS_SHIFT (0U)
5218/*! TS - High Resolution Time Stamp
5219 */
5220#define CAN_HR_TIME_STAMP_TS(x) (((uint32_t)(((uint32_t)(x)) << CAN_HR_TIME_STAMP_TS_SHIFT)) & CAN_HR_TIME_STAMP_TS_MASK)
5221/*! @} */
5222
5223/* The count of CAN_HR_TIME_STAMP */
5224#define CAN_HR_TIME_STAMP_COUNT (64U)
5225
5226/*! @name ERFFEL - Enhanced Rx FIFO Filter Element */
5227/*! @{ */
5228#define CAN_ERFFEL_FEL_MASK (0xFFFFFFFFU)
5229#define CAN_ERFFEL_FEL_SHIFT (0U)
5230/*! FEL - Filter Element Bits
5231 */
5232#define CAN_ERFFEL_FEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERFFEL_FEL_SHIFT)) & CAN_ERFFEL_FEL_MASK)
5233/*! @} */
5234
5235/* The count of CAN_ERFFEL */
5236#define CAN_ERFFEL_COUNT (128U)
5237
5238
5239/*!
5240 * @}
5241 */ /* end of group CAN_Register_Masks */
5242
5243
5244/* CAN - Peripheral instance base addresses */
5245/** Peripheral CAN1 base address */
5246#define CAN1_BASE (0x401D0000u)
5247/** Peripheral CAN1 base pointer */
5248#define CAN1 ((CAN_Type *)CAN1_BASE)
5249/** Peripheral CAN2 base address */
5250#define CAN2_BASE (0x401D4000u)
5251/** Peripheral CAN2 base pointer */
5252#define CAN2 ((CAN_Type *)CAN2_BASE)
5253/** Peripheral CAN3 base address */
5254#define CAN3_BASE (0x401D8000u)
5255/** Peripheral CAN3 base pointer */
5256#define CAN3 ((CAN_Type *)CAN3_BASE)
5257/** Array initializer of CAN peripheral base addresses */
5258#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }
5259/** Array initializer of CAN peripheral base pointers */
5260#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2, CAN3 }
5261/** Interrupt vectors for the CAN peripheral type */
5262#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
5263#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
5264#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
5265#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
5266#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
5267#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
5268
5269/*!
5270 * @}
5271 */ /* end of group CAN_Peripheral_Access_Layer */
5272
5273
5274/* ----------------------------------------------------------------------------
5275 -- CCM Peripheral Access Layer
5276 ---------------------------------------------------------------------------- */
5277
5278/*!
5279 * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
5280 * @{
5281 */
5282
5283/** CCM - Register Layout Typedef */
5284typedef struct {
5285 __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */
5286 uint8_t RESERVED_0[4];
5287 __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */
5288 __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */
5289 __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */
5290 __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */
5291 __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */
5292 __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */
5293 __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */
5294 __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */
5295 __IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */
5296 __IO uint32_t CS2CDR; /**< CCM Clock Divider Register, offset: 0x2C */
5297 __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */
5298 uint8_t RESERVED_1[4];
5299 __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */
5300 __IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */
5301 uint8_t RESERVED_2[8];
5302 __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */
5303 uint8_t RESERVED_3[8];
5304 __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */
5305 __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */
5306 __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */
5307 __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */
5308 __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */
5309 __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */
5310 __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */
5311 __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */
5312 __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */
5313 __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */
5314 __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */
5315 __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */
5316 __IO uint32_t CCGR7; /**< CCM Clock Gating Register 7, offset: 0x84 */
5317 __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */
5318} CCM_Type;
5319
5320/* ----------------------------------------------------------------------------
5321 -- CCM Register Masks
5322 ---------------------------------------------------------------------------- */
5323
5324/*!
5325 * @addtogroup CCM_Register_Masks CCM Register Masks
5326 * @{
5327 */
5328
5329/*! @name CCR - CCM Control Register */
5330/*! @{ */
5331#define CCM_CCR_OSCNT_MASK (0xFFU)
5332#define CCM_CCR_OSCNT_SHIFT (0U)
5333/*! OSCNT - Oscillator ready counter value. These bits define value of 32KHz counter, that serve as
5334 * counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time.
5335 * Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from
5336 * stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for
5337 * the dpll_ip to use and only then the gate in dpll_ip can be opened.
5338 */
5339#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
5340#define CCM_CCR_COSC_EN_MASK (0x1000U)
5341#define CCM_CCR_COSC_EN_SHIFT (12U)
5342/*! COSC_EN
5343 * 0b0..disable on chip oscillator
5344 * 0b1..enable on chip oscillator
5345 */
5346#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
5347#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
5348#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
5349/*! REG_BYPASS_COUNT
5350 * 0b000000..no delay
5351 * 0b000001..1 CKIL clock period delay
5352 * 0b111111..63 CKIL clock periods delay
5353 */
5354#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
5355#define CCM_CCR_RBC_EN_MASK (0x8000000U)
5356#define CCM_CCR_RBC_EN_SHIFT (27U)
5357/*! RBC_EN
5358 * 0b1..REG_BYPASS_COUNTER enabled.
5359 * 0b0..REG_BYPASS_COUNTER disabled
5360 */
5361#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
5362/*! @} */
5363
5364/*! @name CSR - CCM Status Register */
5365/*! @{ */
5366#define CCM_CSR_REF_EN_B_MASK (0x1U)
5367#define CCM_CSR_REF_EN_B_SHIFT (0U)
5368/*! REF_EN_B
5369 * 0b0..value of CCM_REF_EN_B is '0'
5370 * 0b1..value of CCM_REF_EN_B is '1'
5371 */
5372#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
5373#define CCM_CSR_CAMP2_READY_MASK (0x8U)
5374#define CCM_CSR_CAMP2_READY_SHIFT (3U)
5375/*! CAMP2_READY
5376 * 0b0..CAMP2 is not ready.
5377 * 0b1..CAMP2 is ready.
5378 */
5379#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
5380#define CCM_CSR_COSC_READY_MASK (0x20U)
5381#define CCM_CSR_COSC_READY_SHIFT (5U)
5382/*! COSC_READY
5383 * 0b0..on board oscillator is not ready.
5384 * 0b1..on board oscillator is ready.
5385 */
5386#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
5387/*! @} */
5388
5389/*! @name CCSR - CCM Clock Switcher Register */
5390/*! @{ */
5391#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
5392#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
5393/*! PLL3_SW_CLK_SEL
5394 * 0b0..pll3_main_clk
5395 * 0b1..pll3 bypass clock
5396 */
5397#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
5398/*! @} */
5399
5400/*! @name CACRR - CCM Arm Clock Root Register */
5401/*! @{ */
5402#define CCM_CACRR_ARM_PODF_MASK (0x7U)
5403#define CCM_CACRR_ARM_PODF_SHIFT (0U)
5404/*! ARM_PODF
5405 * 0b000..divide by 1
5406 * 0b001..divide by 2
5407 * 0b010..divide by 3
5408 * 0b011..divide by 4
5409 * 0b100..divide by 5
5410 * 0b101..divide by 6
5411 * 0b110..divide by 7
5412 * 0b111..divide by 8
5413 */
5414#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
5415/*! @} */
5416
5417/*! @name CBCDR - CCM Bus Clock Divider Register */
5418/*! @{ */
5419#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)
5420#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)
5421/*! SEMC_CLK_SEL
5422 * 0b0..Periph_clk output will be used as SEMC clock root
5423 * 0b1..SEMC alternative clock will be used as SEMC clock root
5424 */
5425#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
5426#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)
5427#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)
5428/*! SEMC_ALT_CLK_SEL
5429 * 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock
5430 * 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock
5431 */
5432#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
5433#define CCM_CBCDR_IPG_PODF_MASK (0x300U)
5434#define CCM_CBCDR_IPG_PODF_SHIFT (8U)
5435/*! IPG_PODF
5436 * 0b00..divide by 1
5437 * 0b01..divide by 2
5438 * 0b10..divide by 3
5439 * 0b11..divide by 4
5440 */
5441#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
5442#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
5443#define CCM_CBCDR_AHB_PODF_SHIFT (10U)
5444/*! AHB_PODF
5445 * 0b000..divide by 1
5446 * 0b001..divide by 2
5447 * 0b010..divide by 3
5448 * 0b011..divide by 4
5449 * 0b100..divide by 5
5450 * 0b101..divide by 6
5451 * 0b110..divide by 7
5452 * 0b111..divide by 8
5453 */
5454#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
5455#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U)
5456#define CCM_CBCDR_SEMC_PODF_SHIFT (16U)
5457/*! SEMC_PODF
5458 * 0b000..divide by 1
5459 * 0b001..divide by 2
5460 * 0b010..divide by 3
5461 * 0b011..divide by 4
5462 * 0b100..divide by 5
5463 * 0b101..divide by 6
5464 * 0b110..divide by 7
5465 * 0b111..divide by 8
5466 */
5467#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
5468#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
5469#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
5470/*! PERIPH_CLK_SEL
5471 * 0b0..derive clock from pre_periph_clk_sel
5472 * 0b1..derive clock from periph_clk2_clk_divided
5473 */
5474#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
5475#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)
5476#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)
5477/*! PERIPH_CLK2_PODF
5478 * 0b000..divide by 1
5479 * 0b001..divide by 2
5480 * 0b010..divide by 3
5481 * 0b011..divide by 4
5482 * 0b100..divide by 5
5483 * 0b101..divide by 6
5484 * 0b110..divide by 7
5485 * 0b111..divide by 8
5486 */
5487#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
5488/*! @} */
5489
5490/*! @name CBCMR - CCM Bus Clock Multiplexer Register */
5491/*! @{ */
5492#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
5493#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
5494/*! LPSPI_CLK_SEL
5495 * 0b00..derive clock from PLL3 PFD1 clk
5496 * 0b01..derive clock from PLL3 PFD0
5497 * 0b10..derive clock from PLL2
5498 * 0b11..derive clock from PLL2 PFD2
5499 */
5500#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
5501#define CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK (0x300U)
5502#define CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT (8U)
5503/*! FLEXSPI2_CLK_SEL
5504 * 0b00..derive clock from PLL2 PFD2
5505 * 0b01..derive clock from PLL3 PFD0
5506 * 0b10..derive clock from PLL3 PFD1
5507 * 0b11..derive clock from PLL2 (pll2_main_clk)
5508 */
5509#define CCM_CBCMR_FLEXSPI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT)) & CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK)
5510#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
5511#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
5512/*! PERIPH_CLK2_SEL
5513 * 0b00..derive clock from pll3_sw_clk
5514 * 0b01..derive clock from osc_clk (pll1_ref_clk)
5515 * 0b10..derive clock from pll2_bypass_clk
5516 * 0b11..reserved
5517 */
5518#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
5519#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
5520#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
5521/*! TRACE_CLK_SEL
5522 * 0b00..derive clock from PLL2
5523 * 0b01..derive clock from PLL2 PFD2
5524 * 0b10..derive clock from PLL2 PFD0
5525 * 0b11..derive clock from PLL2 PFD1
5526 */
5527#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
5528#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
5529#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
5530/*! PRE_PERIPH_CLK_SEL
5531 * 0b00..derive clock from PLL2
5532 * 0b01..derive clock from PLL2 PFD2
5533 * 0b10..derive clock from PLL2 PFD0
5534 * 0b11..derive clock from divided PLL1
5535 */
5536#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
5537#define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)
5538#define CCM_CBCMR_LCDIF_PODF_SHIFT (23U)
5539/*! LCDIF_PODF
5540 * 0b000..divide by 1
5541 * 0b001..divide by 2
5542 * 0b010..divide by 3
5543 * 0b011..divide by 4
5544 * 0b100..divide by 5
5545 * 0b101..divide by 6
5546 * 0b110..divide by 7
5547 * 0b111..divide by 8
5548 */
5549#define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)
5550#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)
5551#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
5552/*! LPSPI_PODF
5553 * 0b000..divide by 1
5554 * 0b001..divide by 2
5555 * 0b010..divide by 3
5556 * 0b011..divide by 4
5557 * 0b100..divide by 5
5558 * 0b101..divide by 6
5559 * 0b110..divide by 7
5560 * 0b111..divide by 8
5561 */
5562#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
5563#define CCM_CBCMR_FLEXSPI2_PODF_MASK (0xE0000000U)
5564#define CCM_CBCMR_FLEXSPI2_PODF_SHIFT (29U)
5565/*! FLEXSPI2_PODF
5566 * 0b000..divide by 1
5567 * 0b001..divide by 2
5568 * 0b010..divide by 3
5569 * 0b011..divide by 4
5570 * 0b100..divide by 5
5571 * 0b101..divide by 6
5572 * 0b110..divide by 7
5573 * 0b111..divide by 8
5574 */
5575#define CCM_CBCMR_FLEXSPI2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_FLEXSPI2_PODF_SHIFT)) & CCM_CBCMR_FLEXSPI2_PODF_MASK)
5576/*! @} */
5577
5578/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */
5579/*! @{ */
5580#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
5581#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
5582/*! PERCLK_PODF - Divider for perclk podf.
5583 * 0b000000..Divide by 1
5584 * 0b000001..Divide by 2
5585 * 0b000010..Divide by 3
5586 * 0b000011..Divide by 4
5587 * 0b000100..Divide by 5
5588 * 0b000101..Divide by 6
5589 * 0b000110..Divide by 7
5590 * 0b000111..Divide by 8
5591 * 0b001000..Divide by 9
5592 * 0b001001..Divide by 10
5593 * 0b001010..Divide by 11
5594 * 0b001011..Divide by 12
5595 * 0b001100..Divide by 13
5596 * 0b001101..Divide by 14
5597 * 0b001110..Divide by 15
5598 * 0b001111..Divide by 16
5599 * 0b010000..Divide by 17
5600 * 0b010001..Divide by 18
5601 * 0b010010..Divide by 19
5602 * 0b010011..Divide by 20
5603 * 0b010100..Divide by 21
5604 * 0b010101..Divide by 22
5605 * 0b010110..Divide by 23
5606 * 0b010111..Divide by 24
5607 * 0b011000..Divide by 25
5608 * 0b011001..Divide by 26
5609 * 0b011010..Divide by 27
5610 * 0b011011..Divide by 28
5611 * 0b011100..Divide by 29
5612 * 0b011101..Divide by 30
5613 * 0b011110..Divide by 31
5614 * 0b011111..Divide by 32
5615 * 0b100000..Divide by 33
5616 * 0b100001..Divide by 34
5617 * 0b100010..Divide by 35
5618 * 0b100011..Divide by 36
5619 * 0b100100..Divide by 37
5620 * 0b100101..Divide by 38
5621 * 0b100110..Divide by 39
5622 * 0b100111..Divide by 40
5623 * 0b101000..Divide by 41
5624 * 0b101001..Divide by 42
5625 * 0b101010..Divide by 43
5626 * 0b101011..Divide by 44
5627 * 0b101100..Divide by 45
5628 * 0b101101..Divide by 46
5629 * 0b101110..Divide by 47
5630 * 0b101111..Divide by 48
5631 * 0b110000..Divide by 49
5632 * 0b110001..Divide by 50
5633 * 0b110010..Divide by 51
5634 * 0b110011..Divide by 52
5635 * 0b110100..Divide by 53
5636 * 0b110101..Divide by 54
5637 * 0b110110..Divide by 55
5638 * 0b110111..Divide by 56
5639 * 0b111000..Divide by 57
5640 * 0b111001..Divide by 58
5641 * 0b111010..Divide by 59
5642 * 0b111011..Divide by 60
5643 * 0b111100..Divide by 61
5644 * 0b111101..Divide by 62
5645 * 0b111110..Divide by 63
5646 * 0b111111..Divide by 64
5647 */
5648#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
5649#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
5650#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
5651/*! PERCLK_CLK_SEL
5652 * 0b0..derive clock from ipg clk root
5653 * 0b1..derive clock from osc_clk
5654 */
5655#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
5656#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
5657#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
5658/*! SAI1_CLK_SEL
5659 * 0b00..derive clock from PLL3 PFD2
5660 * 0b01..derive clock from PLL5
5661 * 0b10..derive clock from PLL4
5662 * 0b11..Reserved
5663 */
5664#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
5665#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)
5666#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)
5667/*! SAI2_CLK_SEL
5668 * 0b00..derive clock from PLL3 PFD2
5669 * 0b01..derive clock from PLL5
5670 * 0b10..derive clock from PLL4
5671 * 0b11..Reserved
5672 */
5673#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
5674#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
5675#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
5676/*! SAI3_CLK_SEL
5677 * 0b00..derive clock from PLL3 PFD2
5678 * 0b01..derive clock from PLL5
5679 * 0b10..derive clock from PLL4
5680 * 0b11..Reserved
5681 */
5682#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
5683#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)
5684#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)
5685/*! USDHC1_CLK_SEL
5686 * 0b0..derive clock from PLL2 PFD2
5687 * 0b1..derive clock from PLL2 PFD0
5688 */
5689#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
5690#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)
5691#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)
5692/*! USDHC2_CLK_SEL
5693 * 0b0..derive clock from PLL2 PFD2
5694 * 0b1..derive clock from PLL2 PFD0
5695 */
5696#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
5697#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
5698#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
5699/*! FLEXSPI_PODF
5700 * 0b000..divide by 1
5701 * 0b001..divide by 2
5702 * 0b010..divide by 3
5703 * 0b011..divide by 4
5704 * 0b100..divide by 5
5705 * 0b101..divide by 6
5706 * 0b110..divide by 7
5707 * 0b111..divide by 8
5708 */
5709#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
5710#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
5711#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
5712/*! FLEXSPI_CLK_SEL
5713 * 0b00..derive clock from semc_clk_root_pre
5714 * 0b01..derive clock from pll3_sw_clk
5715 * 0b10..derive clock from PLL2 PFD2
5716 * 0b11..derive clock from PLL3 PFD0
5717 */
5718#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
5719/*! @} */
5720
5721/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */
5722/*! @{ */
5723#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)
5724#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)
5725/*! CAN_CLK_PODF - Divider for CAN/CANFD clock podf.
5726 * 0b000000..Divide by 1
5727 * 0b000001..Divide by 2
5728 * 0b000010..Divide by 3
5729 * 0b000011..Divide by 4
5730 * 0b000100..Divide by 5
5731 * 0b000101..Divide by 6
5732 * 0b000110..Divide by 7
5733 * 0b000111..Divide by 8
5734 * 0b001000..Divide by 9
5735 * 0b001001..Divide by 10
5736 * 0b001010..Divide by 11
5737 * 0b001011..Divide by 12
5738 * 0b001100..Divide by 13
5739 * 0b001101..Divide by 14
5740 * 0b001110..Divide by 15
5741 * 0b001111..Divide by 16
5742 * 0b010000..Divide by 17
5743 * 0b010001..Divide by 18
5744 * 0b010010..Divide by 19
5745 * 0b010011..Divide by 20
5746 * 0b010100..Divide by 21
5747 * 0b010101..Divide by 22
5748 * 0b010110..Divide by 23
5749 * 0b010111..Divide by 24
5750 * 0b011000..Divide by 25
5751 * 0b011001..Divide by 26
5752 * 0b011010..Divide by 27
5753 * 0b011011..Divide by 28
5754 * 0b011100..Divide by 29
5755 * 0b011101..Divide by 30
5756 * 0b011110..Divide by 31
5757 * 0b011111..Divide by 32
5758 * 0b100000..Divide by 33
5759 * 0b100001..Divide by 34
5760 * 0b100010..Divide by 35
5761 * 0b100011..Divide by 36
5762 * 0b100100..Divide by 37
5763 * 0b100101..Divide by 38
5764 * 0b100110..Divide by 39
5765 * 0b100111..Divide by 40
5766 * 0b101000..Divide by 41
5767 * 0b101001..Divide by 42
5768 * 0b101010..Divide by 43
5769 * 0b101011..Divide by 44
5770 * 0b101100..Divide by 45
5771 * 0b101101..Divide by 46
5772 * 0b101110..Divide by 47
5773 * 0b101111..Divide by 48
5774 * 0b110000..Divide by 49
5775 * 0b110001..Divide by 50
5776 * 0b110010..Divide by 51
5777 * 0b110011..Divide by 52
5778 * 0b110100..Divide by 53
5779 * 0b110101..Divide by 54
5780 * 0b110110..Divide by 55
5781 * 0b110111..Divide by 56
5782 * 0b111000..Divide by 57
5783 * 0b111001..Divide by 58
5784 * 0b111010..Divide by 59
5785 * 0b111011..Divide by 60
5786 * 0b111100..Divide by 61
5787 * 0b111101..Divide by 62
5788 * 0b111110..Divide by 63
5789 * 0b111111..Divide by 64
5790 */
5791#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
5792#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)
5793#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)
5794/*! CAN_CLK_SEL
5795 * 0b00..derive clock from pll3_sw_clk divided clock (60M)
5796 * 0b01..derive clock from osc_clk (24M)
5797 * 0b10..derive clock from pll3_sw_clk divided clock (80M)
5798 * 0b11..Disable FlexCAN clock
5799 */
5800#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
5801#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)
5802#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)
5803/*! FLEXIO2_CLK_SEL
5804 * 0b00..derive clock from PLL4 divided clock
5805 * 0b01..derive clock from PLL3 PFD2 clock
5806 * 0b10..derive clock from PLL5 clock
5807 * 0b11..derive clock from pll3_sw_clk
5808 */
5809#define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)
5810/*! @} */
5811
5812/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */
5813/*! @{ */
5814#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
5815#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
5816/*! UART_CLK_PODF - Divider for uart clock podf.
5817 * 0b000000..Divide by 1
5818 * 0b000001..Divide by 2
5819 * 0b000010..Divide by 3
5820 * 0b000011..Divide by 4
5821 * 0b000100..Divide by 5
5822 * 0b000101..Divide by 6
5823 * 0b000110..Divide by 7
5824 * 0b000111..Divide by 8
5825 * 0b001000..Divide by 9
5826 * 0b001001..Divide by 10
5827 * 0b001010..Divide by 11
5828 * 0b001011..Divide by 12
5829 * 0b001100..Divide by 13
5830 * 0b001101..Divide by 14
5831 * 0b001110..Divide by 15
5832 * 0b001111..Divide by 16
5833 * 0b010000..Divide by 17
5834 * 0b010001..Divide by 18
5835 * 0b010010..Divide by 19
5836 * 0b010011..Divide by 20
5837 * 0b010100..Divide by 21
5838 * 0b010101..Divide by 22
5839 * 0b010110..Divide by 23
5840 * 0b010111..Divide by 24
5841 * 0b011000..Divide by 25
5842 * 0b011001..Divide by 26
5843 * 0b011010..Divide by 27
5844 * 0b011011..Divide by 28
5845 * 0b011100..Divide by 29
5846 * 0b011101..Divide by 30
5847 * 0b011110..Divide by 31
5848 * 0b011111..Divide by 32
5849 * 0b100000..Divide by 33
5850 * 0b100001..Divide by 34
5851 * 0b100010..Divide by 35
5852 * 0b100011..Divide by 36
5853 * 0b100100..Divide by 37
5854 * 0b100101..Divide by 38
5855 * 0b100110..Divide by 39
5856 * 0b100111..Divide by 40
5857 * 0b101000..Divide by 41
5858 * 0b101001..Divide by 42
5859 * 0b101010..Divide by 43
5860 * 0b101011..Divide by 44
5861 * 0b101100..Divide by 45
5862 * 0b101101..Divide by 46
5863 * 0b101110..Divide by 47
5864 * 0b101111..Divide by 48
5865 * 0b110000..Divide by 49
5866 * 0b110001..Divide by 50
5867 * 0b110010..Divide by 51
5868 * 0b110011..Divide by 52
5869 * 0b110100..Divide by 53
5870 * 0b110101..Divide by 54
5871 * 0b110110..Divide by 55
5872 * 0b110111..Divide by 56
5873 * 0b111000..Divide by 57
5874 * 0b111001..Divide by 58
5875 * 0b111010..Divide by 59
5876 * 0b111011..Divide by 60
5877 * 0b111100..Divide by 61
5878 * 0b111101..Divide by 62
5879 * 0b111110..Divide by 63
5880 * 0b111111..Divide by 64
5881 */
5882#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
5883#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)
5884#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
5885/*! UART_CLK_SEL
5886 * 0b0..derive clock from pll3_80m
5887 * 0b1..derive clock from osc_clk
5888 */
5889#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
5890#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)
5891#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)
5892/*! USDHC1_PODF
5893 * 0b000..divide by 1
5894 * 0b001..divide by 2
5895 * 0b010..divide by 3
5896 * 0b011..divide by 4
5897 * 0b100..divide by 5
5898 * 0b101..divide by 6
5899 * 0b110..divide by 7
5900 * 0b111..divide by 8
5901 */
5902#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
5903#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)
5904#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)
5905/*! USDHC2_PODF
5906 * 0b000..divide by 1
5907 * 0b001..divide by 2
5908 * 0b010..divide by 3
5909 * 0b011..divide by 4
5910 * 0b100..divide by 5
5911 * 0b101..divide by 6
5912 * 0b110..divide by 7
5913 * 0b111..divide by 8
5914 */
5915#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
5916#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)
5917#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
5918/*! TRACE_PODF
5919 * 0b00..divide by 1
5920 * 0b01..divide by 2
5921 * 0b10..divide by 3
5922 * 0b11..divide by 4
5923 */
5924#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
5925/*! @} */
5926
5927/*! @name CS1CDR - CCM Clock Divider Register */
5928/*! @{ */
5929#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
5930#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
5931/*! SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower
5932 * than 300Mhz, the predivider can be used to achieve this.
5933 * 0b000000..Divide by 1
5934 * 0b000001..Divide by 2
5935 * 0b000010..Divide by 3
5936 * 0b000011..Divide by 4
5937 * 0b000100..Divide by 5
5938 * 0b000101..Divide by 6
5939 * 0b000110..Divide by 7
5940 * 0b000111..Divide by 8
5941 * 0b001000..Divide by 9
5942 * 0b001001..Divide by 10
5943 * 0b001010..Divide by 11
5944 * 0b001011..Divide by 12
5945 * 0b001100..Divide by 13
5946 * 0b001101..Divide by 14
5947 * 0b001110..Divide by 15
5948 * 0b001111..Divide by 16
5949 * 0b010000..Divide by 17
5950 * 0b010001..Divide by 18
5951 * 0b010010..Divide by 19
5952 * 0b010011..Divide by 20
5953 * 0b010100..Divide by 21
5954 * 0b010101..Divide by 22
5955 * 0b010110..Divide by 23
5956 * 0b010111..Divide by 24
5957 * 0b011000..Divide by 25
5958 * 0b011001..Divide by 26
5959 * 0b011010..Divide by 27
5960 * 0b011011..Divide by 28
5961 * 0b011100..Divide by 29
5962 * 0b011101..Divide by 30
5963 * 0b011110..Divide by 31
5964 * 0b011111..Divide by 32
5965 * 0b100000..Divide by 33
5966 * 0b100001..Divide by 34
5967 * 0b100010..Divide by 35
5968 * 0b100011..Divide by 36
5969 * 0b100100..Divide by 37
5970 * 0b100101..Divide by 38
5971 * 0b100110..Divide by 39
5972 * 0b100111..Divide by 40
5973 * 0b101000..Divide by 41
5974 * 0b101001..Divide by 42
5975 * 0b101010..Divide by 43
5976 * 0b101011..Divide by 44
5977 * 0b101100..Divide by 45
5978 * 0b101101..Divide by 46
5979 * 0b101110..Divide by 47
5980 * 0b101111..Divide by 48
5981 * 0b110000..Divide by 49
5982 * 0b110001..Divide by 50
5983 * 0b110010..Divide by 51
5984 * 0b110011..Divide by 52
5985 * 0b110100..Divide by 53
5986 * 0b110101..Divide by 54
5987 * 0b110110..Divide by 55
5988 * 0b110111..Divide by 56
5989 * 0b111000..Divide by 57
5990 * 0b111001..Divide by 58
5991 * 0b111010..Divide by 59
5992 * 0b111011..Divide by 60
5993 * 0b111100..Divide by 61
5994 * 0b111101..Divide by 62
5995 * 0b111110..Divide by 63
5996 * 0b111111..Divide by 64
5997 */
5998#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
5999#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
6000#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
6001/*! SAI1_CLK_PRED
6002 * 0b000..divide by 1
6003 * 0b001..divide by 2
6004 * 0b010..divide by 3
6005 * 0b011..divide by 4
6006 * 0b100..divide by 5
6007 * 0b101..divide by 6
6008 * 0b110..divide by 7
6009 * 0b111..divide by 8
6010 */
6011#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
6012#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)
6013#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)
6014/*! FLEXIO2_CLK_PRED
6015 * 0b000..divide by 1
6016 * 0b001..divide by 2
6017 * 0b010..divide by 3
6018 * 0b011..divide by 4
6019 * 0b100..divide by 5
6020 * 0b101..divide by 6
6021 * 0b110..divide by 7
6022 * 0b111..divide by 8
6023 */
6024#define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)
6025#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
6026#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
6027/*! SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower
6028 * than 300Mhz, the predivider can be used to achieve this.
6029 * 0b000000..Divide by 1
6030 * 0b000001..Divide by 2
6031 * 0b000010..Divide by 3
6032 * 0b000011..Divide by 4
6033 * 0b000100..Divide by 5
6034 * 0b000101..Divide by 6
6035 * 0b000110..Divide by 7
6036 * 0b000111..Divide by 8
6037 * 0b001000..Divide by 9
6038 * 0b001001..Divide by 10
6039 * 0b001010..Divide by 11
6040 * 0b001011..Divide by 12
6041 * 0b001100..Divide by 13
6042 * 0b001101..Divide by 14
6043 * 0b001110..Divide by 15
6044 * 0b001111..Divide by 16
6045 * 0b010000..Divide by 17
6046 * 0b010001..Divide by 18
6047 * 0b010010..Divide by 19
6048 * 0b010011..Divide by 20
6049 * 0b010100..Divide by 21
6050 * 0b010101..Divide by 22
6051 * 0b010110..Divide by 23
6052 * 0b010111..Divide by 24
6053 * 0b011000..Divide by 25
6054 * 0b011001..Divide by 26
6055 * 0b011010..Divide by 27
6056 * 0b011011..Divide by 28
6057 * 0b011100..Divide by 29
6058 * 0b011101..Divide by 30
6059 * 0b011110..Divide by 31
6060 * 0b011111..Divide by 32
6061 * 0b100000..Divide by 33
6062 * 0b100001..Divide by 34
6063 * 0b100010..Divide by 35
6064 * 0b100011..Divide by 36
6065 * 0b100100..Divide by 37
6066 * 0b100101..Divide by 38
6067 * 0b100110..Divide by 39
6068 * 0b100111..Divide by 40
6069 * 0b101000..Divide by 41
6070 * 0b101001..Divide by 42
6071 * 0b101010..Divide by 43
6072 * 0b101011..Divide by 44
6073 * 0b101100..Divide by 45
6074 * 0b101101..Divide by 46
6075 * 0b101110..Divide by 47
6076 * 0b101111..Divide by 48
6077 * 0b110000..Divide by 49
6078 * 0b110001..Divide by 50
6079 * 0b110010..Divide by 51
6080 * 0b110011..Divide by 52
6081 * 0b110100..Divide by 53
6082 * 0b110101..Divide by 54
6083 * 0b110110..Divide by 55
6084 * 0b110111..Divide by 56
6085 * 0b111000..Divide by 57
6086 * 0b111001..Divide by 58
6087 * 0b111010..Divide by 59
6088 * 0b111011..Divide by 60
6089 * 0b111100..Divide by 61
6090 * 0b111101..Divide by 62
6091 * 0b111110..Divide by 63
6092 * 0b111111..Divide by 64
6093 */
6094#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
6095#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
6096#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
6097/*! SAI3_CLK_PRED
6098 * 0b000..divide by 1
6099 * 0b001..divide by 2
6100 * 0b010..divide by 3
6101 * 0b011..divide by 4
6102 * 0b100..divide by 5
6103 * 0b101..divide by 6
6104 * 0b110..divide by 7
6105 * 0b111..divide by 8
6106 */
6107#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
6108#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)
6109#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)
6110/*! FLEXIO2_CLK_PODF - Divider for flexio2/flexio3 clock. Divider should be updated when output clock is gated.
6111 * 0b000..Divide by 1
6112 * 0b001..Divide by 2
6113 * 0b010..Divide by 3
6114 * 0b011..Divide by 4
6115 * 0b100..Divide by 5
6116 * 0b101..Divide by 6
6117 * 0b110..Divide by 7
6118 * 0b111..Divide by 8
6119 */
6120#define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)
6121/*! @} */
6122
6123/*! @name CS2CDR - CCM Clock Divider Register */
6124/*! @{ */
6125#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)
6126#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)
6127/*! SAI2_CLK_PODF - Divider for sai2 clock podf. The input clock to this divider should be lower
6128 * than 300Mhz, the predivider can be used to achieve this.
6129 * 0b000000..Divide by 1
6130 * 0b000001..Divide by 2
6131 * 0b000010..Divide by 3
6132 * 0b000011..Divide by 4
6133 * 0b000100..Divide by 5
6134 * 0b000101..Divide by 6
6135 * 0b000110..Divide by 7
6136 * 0b000111..Divide by 8
6137 * 0b001000..Divide by 9
6138 * 0b001001..Divide by 10
6139 * 0b001010..Divide by 11
6140 * 0b001011..Divide by 12
6141 * 0b001100..Divide by 13
6142 * 0b001101..Divide by 14
6143 * 0b001110..Divide by 15
6144 * 0b001111..Divide by 16
6145 * 0b010000..Divide by 17
6146 * 0b010001..Divide by 18
6147 * 0b010010..Divide by 19
6148 * 0b010011..Divide by 20
6149 * 0b010100..Divide by 21
6150 * 0b010101..Divide by 22
6151 * 0b010110..Divide by 23
6152 * 0b010111..Divide by 24
6153 * 0b011000..Divide by 25
6154 * 0b011001..Divide by 26
6155 * 0b011010..Divide by 27
6156 * 0b011011..Divide by 28
6157 * 0b011100..Divide by 29
6158 * 0b011101..Divide by 30
6159 * 0b011110..Divide by 31
6160 * 0b011111..Divide by 32
6161 * 0b100000..Divide by 33
6162 * 0b100001..Divide by 34
6163 * 0b100010..Divide by 35
6164 * 0b100011..Divide by 36
6165 * 0b100100..Divide by 37
6166 * 0b100101..Divide by 38
6167 * 0b100110..Divide by 39
6168 * 0b100111..Divide by 40
6169 * 0b101000..Divide by 41
6170 * 0b101001..Divide by 42
6171 * 0b101010..Divide by 43
6172 * 0b101011..Divide by 44
6173 * 0b101100..Divide by 45
6174 * 0b101101..Divide by 46
6175 * 0b101110..Divide by 47
6176 * 0b101111..Divide by 48
6177 * 0b110000..Divide by 49
6178 * 0b110001..Divide by 50
6179 * 0b110010..Divide by 51
6180 * 0b110011..Divide by 52
6181 * 0b110100..Divide by 53
6182 * 0b110101..Divide by 54
6183 * 0b110110..Divide by 55
6184 * 0b110111..Divide by 56
6185 * 0b111000..Divide by 57
6186 * 0b111001..Divide by 58
6187 * 0b111010..Divide by 59
6188 * 0b111011..Divide by 60
6189 * 0b111100..Divide by 61
6190 * 0b111101..Divide by 62
6191 * 0b111110..Divide by 63
6192 * 0b111111..Divide by 64
6193 */
6194#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
6195#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)
6196#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)
6197/*! SAI2_CLK_PRED
6198 * 0b000..divide by 1
6199 * 0b001..divide by 2
6200 * 0b010..divide by 3
6201 * 0b011..divide by 4
6202 * 0b100..divide by 5
6203 * 0b101..divide by 6
6204 * 0b110..divide by 7
6205 * 0b111..divide by 8
6206 */
6207#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
6208/*! @} */
6209
6210/*! @name CDCDR - CCM D1 Clock Divider Register */
6211/*! @{ */
6212#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)
6213#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)
6214/*! FLEXIO1_CLK_SEL
6215 * 0b00..derive clock from PLL4
6216 * 0b01..derive clock from PLL3 PFD2
6217 * 0b10..derive clock from PLL5
6218 * 0b11..derive clock from pll3_sw_clk
6219 */
6220#define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)
6221#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)
6222#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)
6223/*! FLEXIO1_CLK_PODF - Divider for flexio1 clock podf. Divider should be updated when output clock is gated.
6224 * 0b000..Divide by 1
6225 * 0b001..Divide by 2
6226 * 0b010..Divide by 3
6227 * 0b011..Divide by 4
6228 * 0b100..Divide by 5
6229 * 0b101..Divide by 6
6230 * 0b110..Divide by 7
6231 * 0b111..Divide by 8
6232 */
6233#define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)
6234#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)
6235#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)
6236/*! FLEXIO1_CLK_PRED - Divider for flexio1 clock pred. Divider should be updated when output clock is gated.
6237 * 0b000..Divide by 1
6238 * 0b001..Divide by 2
6239 * 0b010..Divide by 3
6240 * 0b011..Divide by 4
6241 * 0b100..Divide by 5
6242 * 0b101..Divide by 6
6243 * 0b110..Divide by 7
6244 * 0b111..Divide by 8
6245 */
6246#define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)
6247#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
6248#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
6249/*! SPDIF0_CLK_SEL
6250 * 0b00..derive clock from PLL4
6251 * 0b01..derive clock from PLL3 PFD2
6252 * 0b10..derive clock from PLL5
6253 * 0b11..derive clock from pll3_sw_clk
6254 */
6255#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
6256#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
6257#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
6258/*! SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
6259 * 0b000..Divide by 1
6260 * 0b001..Divide by 2
6261 * 0b010..Divide by 3
6262 * 0b011..Divide by 4
6263 * 0b100..Divide by 5
6264 * 0b101..Divide by 6
6265 * 0b110..Divide by 7
6266 * 0b111..Divide by 8
6267 */
6268#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
6269#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
6270#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
6271/*! SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated.
6272 * 0b000..Divide by 1
6273 * 0b001..Divide by 2
6274 * 0b010..Divide by 3
6275 * 0b011..Divide by 4
6276 * 0b100..Divide by 5
6277 * 0b101..Divide by 6
6278 * 0b110..Divide by 7
6279 * 0b111..Divide by 8
6280 */
6281#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
6282/*! @} */
6283
6284/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */
6285/*! @{ */
6286#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)
6287#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)
6288/*! LCDIF_PRED
6289 * 0b000..divide by 1
6290 * 0b001..divide by 2
6291 * 0b010..divide by 3
6292 * 0b011..divide by 4
6293 * 0b100..divide by 5
6294 * 0b101..divide by 6
6295 * 0b110..divide by 7
6296 * 0b111..divide by 8
6297 */
6298#define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)
6299#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)
6300#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)
6301/*! LCDIF_PRE_CLK_SEL
6302 * 0b000..derive clock from PLL2
6303 * 0b001..derive clock from PLL3 PFD3
6304 * 0b010..derive clock from PLL5
6305 * 0b011..derive clock from PLL2 PFD0
6306 * 0b100..derive clock from PLL2 PFD1
6307 * 0b101..derive clock from PLL3 PFD1
6308 */
6309#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)
6310#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
6311#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
6312/*! LPI2C_CLK_SEL
6313 * 0b0..derive clock from pll3_60m
6314 * 0b1..derive clock from osc_clk
6315 */
6316#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
6317#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
6318#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
6319/*! LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is
6320 * gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used
6321 * to achieve this.
6322 * 0b000000..Divide by 1
6323 * 0b000001..Divide by 2
6324 * 0b000010..Divide by 3
6325 * 0b000011..Divide by 4
6326 * 0b000100..Divide by 5
6327 * 0b000101..Divide by 6
6328 * 0b000110..Divide by 7
6329 * 0b000111..Divide by 8
6330 * 0b001000..Divide by 9
6331 * 0b001001..Divide by 10
6332 * 0b001010..Divide by 11
6333 * 0b001011..Divide by 12
6334 * 0b001100..Divide by 13
6335 * 0b001101..Divide by 14
6336 * 0b001110..Divide by 15
6337 * 0b001111..Divide by 16
6338 * 0b010000..Divide by 17
6339 * 0b010001..Divide by 18
6340 * 0b010010..Divide by 19
6341 * 0b010011..Divide by 20
6342 * 0b010100..Divide by 21
6343 * 0b010101..Divide by 22
6344 * 0b010110..Divide by 23
6345 * 0b010111..Divide by 24
6346 * 0b011000..Divide by 25
6347 * 0b011001..Divide by 26
6348 * 0b011010..Divide by 27
6349 * 0b011011..Divide by 28
6350 * 0b011100..Divide by 29
6351 * 0b011101..Divide by 30
6352 * 0b011110..Divide by 31
6353 * 0b011111..Divide by 32
6354 * 0b100000..Divide by 33
6355 * 0b100001..Divide by 34
6356 * 0b100010..Divide by 35
6357 * 0b100011..Divide by 36
6358 * 0b100100..Divide by 37
6359 * 0b100101..Divide by 38
6360 * 0b100110..Divide by 39
6361 * 0b100111..Divide by 40
6362 * 0b101000..Divide by 41
6363 * 0b101001..Divide by 42
6364 * 0b101010..Divide by 43
6365 * 0b101011..Divide by 44
6366 * 0b101100..Divide by 45
6367 * 0b101101..Divide by 46
6368 * 0b101110..Divide by 47
6369 * 0b101111..Divide by 48
6370 * 0b110000..Divide by 49
6371 * 0b110001..Divide by 50
6372 * 0b110010..Divide by 51
6373 * 0b110011..Divide by 52
6374 * 0b110100..Divide by 53
6375 * 0b110101..Divide by 54
6376 * 0b110110..Divide by 55
6377 * 0b110111..Divide by 56
6378 * 0b111000..Divide by 57
6379 * 0b111001..Divide by 58
6380 * 0b111010..Divide by 59
6381 * 0b111011..Divide by 60
6382 * 0b111100..Divide by 61
6383 * 0b111101..Divide by 62
6384 * 0b111110..Divide by 63
6385 * 0b111111..Divide by 64
6386 */
6387#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
6388/*! @} */
6389
6390/*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */
6391/*! @{ */
6392#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)
6393#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)
6394/*! CSI_CLK_SEL
6395 * 0b00..derive clock from osc_clk (24M)
6396 * 0b01..derive clock from PLL2 PFD2
6397 * 0b10..derive clock from pll3_120M
6398 * 0b11..derive clock from PLL3 PFD1
6399 */
6400#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)
6401#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U)
6402#define CCM_CSCDR3_CSI_PODF_SHIFT (11U)
6403/*! CSI_PODF
6404 * 0b000..divide by 1
6405 * 0b001..divide by 2
6406 * 0b010..divide by 3
6407 * 0b011..divide by 4
6408 * 0b100..divide by 5
6409 * 0b101..divide by 6
6410 * 0b110..divide by 7
6411 * 0b111..divide by 8
6412 */
6413#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)
6414/*! @} */
6415
6416/*! @name CDHIPR - CCM Divider Handshake In-Process Register */
6417/*! @{ */
6418#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)
6419#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)
6420/*! SEMC_PODF_BUSY
6421 * 0b0..divider is not busy and its value represents the actual division.
6422 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
6423 * value of the division factor, and after the handshake the written value of the semc_podf will be applied.
6424 */
6425#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
6426#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
6427#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
6428/*! AHB_PODF_BUSY
6429 * 0b0..divider is not busy and its value represents the actual division.
6430 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
6431 * value of the division factor, and after the handshake the written value of the ahb_podf will be applied.
6432 */
6433#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
6434#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)
6435#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)
6436/*! PERIPH2_CLK_SEL_BUSY
6437 * 0b0..mux is not busy and its value represents the actual division.
6438 * 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the
6439 * previous value of select, and after the handshake periph2_clk_sel value will be applied.
6440 */
6441#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
6442#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
6443#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
6444/*! PERIPH_CLK_SEL_BUSY
6445 * 0b0..mux is not busy and its value represents the actual division.
6446 * 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the
6447 * previous value of select, and after the handshake periph_clk_sel value will be applied.
6448 */
6449#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
6450#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)
6451#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)
6452/*! ARM_PODF_BUSY
6453 * 0b0..divider is not busy and its value represents the actual division.
6454 * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
6455 * value of the division factor, and after the handshake the written value of the arm_podf will be applied.
6456 */
6457#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
6458/*! @} */
6459
6460/*! @name CLPCR - CCM Low Power Control Register */
6461/*! @{ */
6462#define CCM_CLPCR_LPM_MASK (0x3U)
6463#define CCM_CLPCR_LPM_SHIFT (0U)
6464/*! LPM
6465 * 0b00..Remain in run mode
6466 * 0b01..Transfer to wait mode
6467 * 0b10..Transfer to stop mode
6468 * 0b11..Reserved
6469 */
6470#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
6471#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
6472#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
6473/*! ARM_CLK_DIS_ON_LPM
6474 * 0b0..ARM clock enabled on wait mode.
6475 * 0b1..ARM clock disabled on wait mode. .
6476 */
6477#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
6478#define CCM_CLPCR_SBYOS_MASK (0x40U)
6479#define CCM_CLPCR_SBYOS_SHIFT (6U)
6480/*! SBYOS
6481 * 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain
6482 * asserted - '0' and cosc_pwrdown will remain de asserted - '0')
6483 * 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be
6484 * deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will
6485 * be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will
6486 * continue with the exit from the STOP mode process.
6487 */
6488#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
6489#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
6490#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
6491/*! DIS_REF_OSC
6492 * 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.
6493 * 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'
6494 */
6495#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
6496#define CCM_CLPCR_VSTBY_MASK (0x100U)
6497#define CCM_CLPCR_VSTBY_SHIFT (8U)
6498/*! VSTBY
6499 * 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')
6500 * 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').
6501 */
6502#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
6503#define CCM_CLPCR_STBY_COUNT_MASK (0x600U)
6504#define CCM_CLPCR_STBY_COUNT_SHIFT (9U)
6505/*! STBY_COUNT
6506 * 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles
6507 * 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles
6508 * 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles
6509 * 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles
6510 */
6511#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
6512#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
6513#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
6514/*! COSC_PWRDOWN
6515 * 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.
6516 * 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.
6517 */
6518#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
6519#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)
6520#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)
6521#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
6522#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)
6523#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)
6524#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
6525#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
6526#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
6527/*! MASK_CORE0_WFI
6528 * 0b0..WFI of core0 is not masked
6529 * 0b1..WFI of core0 is masked
6530 */
6531#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
6532#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
6533#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
6534/*! MASK_SCU_IDLE
6535 * 0b1..SCU IDLE is masked
6536 * 0b0..SCU IDLE is not masked
6537 */
6538#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
6539#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
6540#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
6541/*! MASK_L2CC_IDLE
6542 * 0b1..L2CC IDLE is masked
6543 * 0b0..L2CC IDLE is not masked
6544 */
6545#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
6546/*! @} */
6547
6548/*! @name CISR - CCM Interrupt Status Register */
6549/*! @{ */
6550#define CCM_CISR_LRF_PLL_MASK (0x1U)
6551#define CCM_CISR_LRF_PLL_SHIFT (0U)
6552/*! LRF_PLL
6553 * 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs
6554 * 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs
6555 */
6556#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
6557#define CCM_CISR_COSC_READY_MASK (0x40U)
6558#define CCM_CISR_COSC_READY_SHIFT (6U)
6559/*! COSC_READY
6560 * 0b0..interrupt is not generated due to on board oscillator ready
6561 * 0b1..interrupt generated due to on board oscillator ready
6562 */
6563#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
6564#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)
6565#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)
6566/*! SEMC_PODF_LOADED
6567 * 0b0..interrupt is not generated due to frequency change of semc_podf
6568 * 0b1..interrupt generated due to frequency change of semc_podf
6569 */
6570#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
6571#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
6572#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
6573/*! PERIPH2_CLK_SEL_LOADED
6574 * 0b0..interrupt is not generated due to frequency change of periph2_clk_sel
6575 * 0b1..interrupt generated due to frequency change of periph2_clk_sel
6576 */
6577#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
6578#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
6579#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
6580/*! AHB_PODF_LOADED
6581 * 0b0..interrupt is not generated due to frequency change of ahb_podf
6582 * 0b1..interrupt generated due to frequency change of ahb_podf
6583 */
6584#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
6585#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
6586#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
6587/*! PERIPH_CLK_SEL_LOADED
6588 * 0b0..interrupt is not generated due to update of periph_clk_sel.
6589 * 0b1..interrupt generated due to update of periph_clk_sel.
6590 */
6591#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
6592#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)
6593#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)
6594/*! ARM_PODF_LOADED
6595 * 0b0..interrupt is not generated due to frequency change of arm_podf
6596 * 0b1..interrupt generated due to frequency change of arm_podf
6597 */
6598#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
6599/*! @} */
6600
6601/*! @name CIMR - CCM Interrupt Mask Register */
6602/*! @{ */
6603#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
6604#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
6605/*! MASK_LRF_PLL
6606 * 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created
6607 * 0b1..mask interrupt due to lrf of PLLs
6608 */
6609#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
6610#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
6611#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
6612/*! MASK_COSC_READY
6613 * 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created
6614 * 0b1..mask interrupt due to on board oscillator ready
6615 */
6616#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
6617#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)
6618#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)
6619/*! MASK_SEMC_PODF_LOADED
6620 * 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created
6621 * 0b1..mask interrupt due to frequency change of semc_podf
6622 */
6623#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
6624#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
6625#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
6626/*! MASK_PERIPH2_CLK_SEL_LOADED
6627 * 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created
6628 * 0b1..mask interrupt due to update of periph2_clk_sel
6629 */
6630#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
6631#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
6632#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
6633/*! MASK_AHB_PODF_LOADED
6634 * 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created
6635 * 0b1..mask interrupt due to frequency change of ahb_podf
6636 */
6637#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
6638#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
6639#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
6640/*! MASK_PERIPH_CLK_SEL_LOADED
6641 * 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created
6642 * 0b1..mask interrupt due to update of periph_clk_sel
6643 */
6644#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
6645#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)
6646#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)
6647/*! ARM_PODF_LOADED
6648 * 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created
6649 * 0b1..mask interrupt due to frequency change of arm_podf
6650 */
6651#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
6652/*! @} */
6653
6654/*! @name CCOSR - CCM Clock Output Source Register */
6655/*! @{ */
6656#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
6657#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
6658/*! CLKO1_SEL
6659 * 0b0000..USB1 PLL clock (divided by 2)
6660 * 0b0001..SYS PLL clock (divided by 2)
6661 * 0b0011..VIDEO PLL clock (divided by 2)
6662 * 0b0101..semc_clk_root
6663 * 0b0110..Reserved
6664 * 0b1010..lcdif_pix_clk_root
6665 * 0b1011..ahb_clk_root
6666 * 0b1100..ipg_clk_root
6667 * 0b1101..perclk_root
6668 * 0b1110..ckil_sync_clk_root
6669 * 0b1111..pll4_main_clk
6670 */
6671#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
6672#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
6673#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
6674/*! CLKO1_DIV
6675 * 0b000..divide by 1
6676 * 0b001..divide by 2
6677 * 0b010..divide by 3
6678 * 0b011..divide by 4
6679 * 0b100..divide by 5
6680 * 0b101..divide by 6
6681 * 0b110..divide by 7
6682 * 0b111..divide by 8
6683 */
6684#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
6685#define CCM_CCOSR_CLKO1_EN_MASK (0x80U)
6686#define CCM_CCOSR_CLKO1_EN_SHIFT (7U)
6687/*! CLKO1_EN
6688 * 0b0..CCM_CLKO1 disabled.
6689 * 0b1..CCM_CLKO1 enabled.
6690 */
6691#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
6692#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
6693#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
6694/*! CLK_OUT_SEL
6695 * 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock
6696 * 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock
6697 */
6698#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
6699#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
6700#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
6701/*! CLKO2_SEL
6702 * 0b00011..usdhc1_clk_root
6703 * 0b00110..lpi2c_clk_root
6704 * 0b01011..csi_clk_root
6705 * 0b01110..osc_clk
6706 * 0b10001..usdhc2_clk_root
6707 * 0b10010..sai1_clk_root
6708 * 0b10011..sai2_clk_root
6709 * 0b10100..sai3_clk_root (shared with ADC1 and ADC2 alt_clk root)
6710 * 0b10111..can_clk_root (FlexCAN, shared with CANFD)
6711 * 0b11011..flexspi_clk_root
6712 * 0b11100..uart_clk_root
6713 * 0b11101..spdif0_clk_root
6714 * 0b11111..Reserved
6715 */
6716#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
6717#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
6718#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
6719/*! CLKO2_DIV
6720 * 0b000..divide by 1
6721 * 0b001..divide by 2
6722 * 0b010..divide by 3
6723 * 0b011..divide by 4
6724 * 0b100..divide by 5
6725 * 0b101..divide by 6
6726 * 0b110..divide by 7
6727 * 0b111..divide by 8
6728 */
6729#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
6730#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
6731#define CCM_CCOSR_CLKO2_EN_SHIFT (24U)
6732/*! CLKO2_EN
6733 * 0b0..CCM_CLKO2 disabled.
6734 * 0b1..CCM_CLKO2 enabled.
6735 */
6736#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
6737/*! @} */
6738
6739/*! @name CGPR - CCM General Purpose Register */
6740/*! @{ */
6741#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
6742#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
6743/*! PMIC_DELAY_SCALER
6744 * 0b0..clock is not divided
6745 * 0b1..clock is divided /8
6746 */
6747#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
6748#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
6749#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
6750/*! EFUSE_PROG_SUPPLY_GATE
6751 * 0b0..fuse programing supply voltage is gated off to the efuse module
6752 * 0b1..allow fuse programing.
6753 */
6754#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
6755#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
6756#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
6757/*! SYS_MEM_DS_CTRL
6758 * 0b00..Disable memory DS mode always
6759 * 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled
6760 * 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode
6761 */
6762#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
6763#define CCM_CGPR_FPL_MASK (0x10000U)
6764#define CCM_CGPR_FPL_SHIFT (16U)
6765/*! FPL - Fast PLL enable.
6766 * 0b0..Engage PLL enable default way.
6767 * 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.
6768 */
6769#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
6770#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
6771#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
6772/*! INT_MEM_CLK_LPM
6773 * 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode
6774 * 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low
6775 * Power Modes (WAIT and STOP without power gating)
6776 */
6777#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
6778/*! @} */
6779
6780/*! @name CCGR0 - CCM Clock Gating Register 0 */
6781/*! @{ */
6782#define CCM_CCGR0_CG0_MASK (0x3U)
6783#define CCM_CCGR0_CG0_SHIFT (0U)
6784#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
6785#define CCM_CCGR0_CG1_MASK (0xCU)
6786#define CCM_CCGR0_CG1_SHIFT (2U)
6787#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
6788#define CCM_CCGR0_CG2_MASK (0x30U)
6789#define CCM_CCGR0_CG2_SHIFT (4U)
6790#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
6791#define CCM_CCGR0_CG3_MASK (0xC0U)
6792#define CCM_CCGR0_CG3_SHIFT (6U)
6793#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
6794#define CCM_CCGR0_CG4_MASK (0x300U)
6795#define CCM_CCGR0_CG4_SHIFT (8U)
6796#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
6797#define CCM_CCGR0_CG5_MASK (0xC00U)
6798#define CCM_CCGR0_CG5_SHIFT (10U)
6799#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
6800#define CCM_CCGR0_CG6_MASK (0x3000U)
6801#define CCM_CCGR0_CG6_SHIFT (12U)
6802#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
6803#define CCM_CCGR0_CG7_MASK (0xC000U)
6804#define CCM_CCGR0_CG7_SHIFT (14U)
6805#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
6806#define CCM_CCGR0_CG8_MASK (0x30000U)
6807#define CCM_CCGR0_CG8_SHIFT (16U)
6808#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
6809#define CCM_CCGR0_CG9_MASK (0xC0000U)
6810#define CCM_CCGR0_CG9_SHIFT (18U)
6811#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
6812#define CCM_CCGR0_CG10_MASK (0x300000U)
6813#define CCM_CCGR0_CG10_SHIFT (20U)
6814#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
6815#define CCM_CCGR0_CG11_MASK (0xC00000U)
6816#define CCM_CCGR0_CG11_SHIFT (22U)
6817#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
6818#define CCM_CCGR0_CG12_MASK (0x3000000U)
6819#define CCM_CCGR0_CG12_SHIFT (24U)
6820#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
6821#define CCM_CCGR0_CG13_MASK (0xC000000U)
6822#define CCM_CCGR0_CG13_SHIFT (26U)
6823#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
6824#define CCM_CCGR0_CG14_MASK (0x30000000U)
6825#define CCM_CCGR0_CG14_SHIFT (28U)
6826#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
6827#define CCM_CCGR0_CG15_MASK (0xC0000000U)
6828#define CCM_CCGR0_CG15_SHIFT (30U)
6829#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
6830/*! @} */
6831
6832/*! @name CCGR1 - CCM Clock Gating Register 1 */
6833/*! @{ */
6834#define CCM_CCGR1_CG0_MASK (0x3U)
6835#define CCM_CCGR1_CG0_SHIFT (0U)
6836#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
6837#define CCM_CCGR1_CG1_MASK (0xCU)
6838#define CCM_CCGR1_CG1_SHIFT (2U)
6839#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
6840#define CCM_CCGR1_CG2_MASK (0x30U)
6841#define CCM_CCGR1_CG2_SHIFT (4U)
6842#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
6843#define CCM_CCGR1_CG3_MASK (0xC0U)
6844#define CCM_CCGR1_CG3_SHIFT (6U)
6845#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
6846#define CCM_CCGR1_CG4_MASK (0x300U)
6847#define CCM_CCGR1_CG4_SHIFT (8U)
6848#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
6849#define CCM_CCGR1_CG5_MASK (0xC00U)
6850#define CCM_CCGR1_CG5_SHIFT (10U)
6851#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
6852#define CCM_CCGR1_CG6_MASK (0x3000U)
6853#define CCM_CCGR1_CG6_SHIFT (12U)
6854#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
6855#define CCM_CCGR1_CG7_MASK (0xC000U)
6856#define CCM_CCGR1_CG7_SHIFT (14U)
6857#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
6858#define CCM_CCGR1_CG8_MASK (0x30000U)
6859#define CCM_CCGR1_CG8_SHIFT (16U)
6860#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
6861#define CCM_CCGR1_CG9_MASK (0xC0000U)
6862#define CCM_CCGR1_CG9_SHIFT (18U)
6863#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
6864#define CCM_CCGR1_CG10_MASK (0x300000U)
6865#define CCM_CCGR1_CG10_SHIFT (20U)
6866#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
6867#define CCM_CCGR1_CG11_MASK (0xC00000U)
6868#define CCM_CCGR1_CG11_SHIFT (22U)
6869#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
6870#define CCM_CCGR1_CG12_MASK (0x3000000U)
6871#define CCM_CCGR1_CG12_SHIFT (24U)
6872#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
6873#define CCM_CCGR1_CG13_MASK (0xC000000U)
6874#define CCM_CCGR1_CG13_SHIFT (26U)
6875#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
6876#define CCM_CCGR1_CG14_MASK (0x30000000U)
6877#define CCM_CCGR1_CG14_SHIFT (28U)
6878#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
6879#define CCM_CCGR1_CG15_MASK (0xC0000000U)
6880#define CCM_CCGR1_CG15_SHIFT (30U)
6881#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
6882/*! @} */
6883
6884/*! @name CCGR2 - CCM Clock Gating Register 2 */
6885/*! @{ */
6886#define CCM_CCGR2_CG0_MASK (0x3U)
6887#define CCM_CCGR2_CG0_SHIFT (0U)
6888#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
6889#define CCM_CCGR2_CG1_MASK (0xCU)
6890#define CCM_CCGR2_CG1_SHIFT (2U)
6891#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
6892#define CCM_CCGR2_CG2_MASK (0x30U)
6893#define CCM_CCGR2_CG2_SHIFT (4U)
6894#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
6895#define CCM_CCGR2_CG3_MASK (0xC0U)
6896#define CCM_CCGR2_CG3_SHIFT (6U)
6897#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
6898#define CCM_CCGR2_CG4_MASK (0x300U)
6899#define CCM_CCGR2_CG4_SHIFT (8U)
6900#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
6901#define CCM_CCGR2_CG5_MASK (0xC00U)
6902#define CCM_CCGR2_CG5_SHIFT (10U)
6903#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
6904#define CCM_CCGR2_CG6_MASK (0x3000U)
6905#define CCM_CCGR2_CG6_SHIFT (12U)
6906#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
6907#define CCM_CCGR2_CG7_MASK (0xC000U)
6908#define CCM_CCGR2_CG7_SHIFT (14U)
6909#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
6910#define CCM_CCGR2_CG8_MASK (0x30000U)
6911#define CCM_CCGR2_CG8_SHIFT (16U)
6912#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
6913#define CCM_CCGR2_CG9_MASK (0xC0000U)
6914#define CCM_CCGR2_CG9_SHIFT (18U)
6915#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
6916#define CCM_CCGR2_CG10_MASK (0x300000U)
6917#define CCM_CCGR2_CG10_SHIFT (20U)
6918#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
6919#define CCM_CCGR2_CG11_MASK (0xC00000U)
6920#define CCM_CCGR2_CG11_SHIFT (22U)
6921#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
6922#define CCM_CCGR2_CG12_MASK (0x3000000U)
6923#define CCM_CCGR2_CG12_SHIFT (24U)
6924#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
6925#define CCM_CCGR2_CG13_MASK (0xC000000U)
6926#define CCM_CCGR2_CG13_SHIFT (26U)
6927#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
6928#define CCM_CCGR2_CG14_MASK (0x30000000U)
6929#define CCM_CCGR2_CG14_SHIFT (28U)
6930#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
6931#define CCM_CCGR2_CG15_MASK (0xC0000000U)
6932#define CCM_CCGR2_CG15_SHIFT (30U)
6933#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
6934/*! @} */
6935
6936/*! @name CCGR3 - CCM Clock Gating Register 3 */
6937/*! @{ */
6938#define CCM_CCGR3_CG0_MASK (0x3U)
6939#define CCM_CCGR3_CG0_SHIFT (0U)
6940#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
6941#define CCM_CCGR3_CG1_MASK (0xCU)
6942#define CCM_CCGR3_CG1_SHIFT (2U)
6943#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
6944#define CCM_CCGR3_CG2_MASK (0x30U)
6945#define CCM_CCGR3_CG2_SHIFT (4U)
6946#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
6947#define CCM_CCGR3_CG3_MASK (0xC0U)
6948#define CCM_CCGR3_CG3_SHIFT (6U)
6949#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
6950#define CCM_CCGR3_CG4_MASK (0x300U)
6951#define CCM_CCGR3_CG4_SHIFT (8U)
6952#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
6953#define CCM_CCGR3_CG5_MASK (0xC00U)
6954#define CCM_CCGR3_CG5_SHIFT (10U)
6955#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
6956#define CCM_CCGR3_CG6_MASK (0x3000U)
6957#define CCM_CCGR3_CG6_SHIFT (12U)
6958#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
6959#define CCM_CCGR3_CG7_MASK (0xC000U)
6960#define CCM_CCGR3_CG7_SHIFT (14U)
6961#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
6962#define CCM_CCGR3_CG8_MASK (0x30000U)
6963#define CCM_CCGR3_CG8_SHIFT (16U)
6964#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
6965#define CCM_CCGR3_CG9_MASK (0xC0000U)
6966#define CCM_CCGR3_CG9_SHIFT (18U)
6967#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
6968#define CCM_CCGR3_CG10_MASK (0x300000U)
6969#define CCM_CCGR3_CG10_SHIFT (20U)
6970#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
6971#define CCM_CCGR3_CG11_MASK (0xC00000U)
6972#define CCM_CCGR3_CG11_SHIFT (22U)
6973#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
6974#define CCM_CCGR3_CG12_MASK (0x3000000U)
6975#define CCM_CCGR3_CG12_SHIFT (24U)
6976#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
6977#define CCM_CCGR3_CG13_MASK (0xC000000U)
6978#define CCM_CCGR3_CG13_SHIFT (26U)
6979#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
6980#define CCM_CCGR3_CG14_MASK (0x30000000U)
6981#define CCM_CCGR3_CG14_SHIFT (28U)
6982/*! CG14 - The OCRAM clock cannot be turned off when the CM cache is running on this device.
6983 */
6984#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
6985#define CCM_CCGR3_CG15_MASK (0xC0000000U)
6986#define CCM_CCGR3_CG15_SHIFT (30U)
6987#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
6988/*! @} */
6989
6990/*! @name CCGR4 - CCM Clock Gating Register 4 */
6991/*! @{ */
6992#define CCM_CCGR4_CG0_MASK (0x3U)
6993#define CCM_CCGR4_CG0_SHIFT (0U)
6994#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
6995#define CCM_CCGR4_CG1_MASK (0xCU)
6996#define CCM_CCGR4_CG1_SHIFT (2U)
6997#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
6998#define CCM_CCGR4_CG2_MASK (0x30U)
6999#define CCM_CCGR4_CG2_SHIFT (4U)
7000#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
7001#define CCM_CCGR4_CG3_MASK (0xC0U)
7002#define CCM_CCGR4_CG3_SHIFT (6U)
7003#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
7004#define CCM_CCGR4_CG4_MASK (0x300U)
7005#define CCM_CCGR4_CG4_SHIFT (8U)
7006#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
7007#define CCM_CCGR4_CG5_MASK (0xC00U)
7008#define CCM_CCGR4_CG5_SHIFT (10U)
7009#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
7010#define CCM_CCGR4_CG6_MASK (0x3000U)
7011#define CCM_CCGR4_CG6_SHIFT (12U)
7012#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
7013#define CCM_CCGR4_CG7_MASK (0xC000U)
7014#define CCM_CCGR4_CG7_SHIFT (14U)
7015#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
7016#define CCM_CCGR4_CG8_MASK (0x30000U)
7017#define CCM_CCGR4_CG8_SHIFT (16U)
7018#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
7019#define CCM_CCGR4_CG9_MASK (0xC0000U)
7020#define CCM_CCGR4_CG9_SHIFT (18U)
7021#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
7022#define CCM_CCGR4_CG10_MASK (0x300000U)
7023#define CCM_CCGR4_CG10_SHIFT (20U)
7024#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
7025#define CCM_CCGR4_CG11_MASK (0xC00000U)
7026#define CCM_CCGR4_CG11_SHIFT (22U)
7027#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
7028#define CCM_CCGR4_CG12_MASK (0x3000000U)
7029#define CCM_CCGR4_CG12_SHIFT (24U)
7030#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
7031#define CCM_CCGR4_CG13_MASK (0xC000000U)
7032#define CCM_CCGR4_CG13_SHIFT (26U)
7033#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
7034#define CCM_CCGR4_CG14_MASK (0x30000000U)
7035#define CCM_CCGR4_CG14_SHIFT (28U)
7036#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
7037#define CCM_CCGR4_CG15_MASK (0xC0000000U)
7038#define CCM_CCGR4_CG15_SHIFT (30U)
7039#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
7040/*! @} */
7041
7042/*! @name CCGR5 - CCM Clock Gating Register 5 */
7043/*! @{ */
7044#define CCM_CCGR5_CG0_MASK (0x3U)
7045#define CCM_CCGR5_CG0_SHIFT (0U)
7046#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
7047#define CCM_CCGR5_CG1_MASK (0xCU)
7048#define CCM_CCGR5_CG1_SHIFT (2U)
7049#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
7050#define CCM_CCGR5_CG2_MASK (0x30U)
7051#define CCM_CCGR5_CG2_SHIFT (4U)
7052#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
7053#define CCM_CCGR5_CG3_MASK (0xC0U)
7054#define CCM_CCGR5_CG3_SHIFT (6U)
7055#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
7056#define CCM_CCGR5_CG4_MASK (0x300U)
7057#define CCM_CCGR5_CG4_SHIFT (8U)
7058#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
7059#define CCM_CCGR5_CG5_MASK (0xC00U)
7060#define CCM_CCGR5_CG5_SHIFT (10U)
7061#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
7062#define CCM_CCGR5_CG6_MASK (0x3000U)
7063#define CCM_CCGR5_CG6_SHIFT (12U)
7064#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
7065#define CCM_CCGR5_CG7_MASK (0xC000U)
7066#define CCM_CCGR5_CG7_SHIFT (14U)
7067#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
7068#define CCM_CCGR5_CG8_MASK (0x30000U)
7069#define CCM_CCGR5_CG8_SHIFT (16U)
7070#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
7071#define CCM_CCGR5_CG9_MASK (0xC0000U)
7072#define CCM_CCGR5_CG9_SHIFT (18U)
7073#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
7074#define CCM_CCGR5_CG10_MASK (0x300000U)
7075#define CCM_CCGR5_CG10_SHIFT (20U)
7076#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
7077#define CCM_CCGR5_CG11_MASK (0xC00000U)
7078#define CCM_CCGR5_CG11_SHIFT (22U)
7079#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
7080#define CCM_CCGR5_CG12_MASK (0x3000000U)
7081#define CCM_CCGR5_CG12_SHIFT (24U)
7082#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
7083#define CCM_CCGR5_CG13_MASK (0xC000000U)
7084#define CCM_CCGR5_CG13_SHIFT (26U)
7085#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
7086#define CCM_CCGR5_CG14_MASK (0x30000000U)
7087#define CCM_CCGR5_CG14_SHIFT (28U)
7088#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
7089#define CCM_CCGR5_CG15_MASK (0xC0000000U)
7090#define CCM_CCGR5_CG15_SHIFT (30U)
7091#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
7092/*! @} */
7093
7094/*! @name CCGR6 - CCM Clock Gating Register 6 */
7095/*! @{ */
7096#define CCM_CCGR6_CG0_MASK (0x3U)
7097#define CCM_CCGR6_CG0_SHIFT (0U)
7098#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
7099#define CCM_CCGR6_CG1_MASK (0xCU)
7100#define CCM_CCGR6_CG1_SHIFT (2U)
7101#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
7102#define CCM_CCGR6_CG2_MASK (0x30U)
7103#define CCM_CCGR6_CG2_SHIFT (4U)
7104#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
7105#define CCM_CCGR6_CG3_MASK (0xC0U)
7106#define CCM_CCGR6_CG3_SHIFT (6U)
7107#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
7108#define CCM_CCGR6_CG4_MASK (0x300U)
7109#define CCM_CCGR6_CG4_SHIFT (8U)
7110#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
7111#define CCM_CCGR6_CG5_MASK (0xC00U)
7112#define CCM_CCGR6_CG5_SHIFT (10U)
7113#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
7114#define CCM_CCGR6_CG6_MASK (0x3000U)
7115#define CCM_CCGR6_CG6_SHIFT (12U)
7116#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
7117#define CCM_CCGR6_CG7_MASK (0xC000U)
7118#define CCM_CCGR6_CG7_SHIFT (14U)
7119#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
7120#define CCM_CCGR6_CG8_MASK (0x30000U)
7121#define CCM_CCGR6_CG8_SHIFT (16U)
7122#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
7123#define CCM_CCGR6_CG9_MASK (0xC0000U)
7124#define CCM_CCGR6_CG9_SHIFT (18U)
7125#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
7126#define CCM_CCGR6_CG10_MASK (0x300000U)
7127#define CCM_CCGR6_CG10_SHIFT (20U)
7128#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
7129#define CCM_CCGR6_CG11_MASK (0xC00000U)
7130#define CCM_CCGR6_CG11_SHIFT (22U)
7131#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
7132#define CCM_CCGR6_CG12_MASK (0x3000000U)
7133#define CCM_CCGR6_CG12_SHIFT (24U)
7134#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
7135#define CCM_CCGR6_CG13_MASK (0xC000000U)
7136#define CCM_CCGR6_CG13_SHIFT (26U)
7137#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
7138#define CCM_CCGR6_CG14_MASK (0x30000000U)
7139#define CCM_CCGR6_CG14_SHIFT (28U)
7140#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
7141#define CCM_CCGR6_CG15_MASK (0xC0000000U)
7142#define CCM_CCGR6_CG15_SHIFT (30U)
7143#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
7144/*! @} */
7145
7146/*! @name CCGR7 - CCM Clock Gating Register 7 */
7147/*! @{ */
7148#define CCM_CCGR7_CG0_MASK (0x3U)
7149#define CCM_CCGR7_CG0_SHIFT (0U)
7150#define CCM_CCGR7_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG0_SHIFT)) & CCM_CCGR7_CG0_MASK)
7151#define CCM_CCGR7_CG1_MASK (0xCU)
7152#define CCM_CCGR7_CG1_SHIFT (2U)
7153#define CCM_CCGR7_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG1_SHIFT)) & CCM_CCGR7_CG1_MASK)
7154#define CCM_CCGR7_CG2_MASK (0x30U)
7155#define CCM_CCGR7_CG2_SHIFT (4U)
7156#define CCM_CCGR7_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG2_SHIFT)) & CCM_CCGR7_CG2_MASK)
7157#define CCM_CCGR7_CG3_MASK (0xC0U)
7158#define CCM_CCGR7_CG3_SHIFT (6U)
7159#define CCM_CCGR7_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG3_SHIFT)) & CCM_CCGR7_CG3_MASK)
7160#define CCM_CCGR7_CG4_MASK (0x300U)
7161#define CCM_CCGR7_CG4_SHIFT (8U)
7162#define CCM_CCGR7_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG4_SHIFT)) & CCM_CCGR7_CG4_MASK)
7163#define CCM_CCGR7_CG5_MASK (0xC00U)
7164#define CCM_CCGR7_CG5_SHIFT (10U)
7165#define CCM_CCGR7_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG5_SHIFT)) & CCM_CCGR7_CG5_MASK)
7166#define CCM_CCGR7_CG6_MASK (0x3000U)
7167#define CCM_CCGR7_CG6_SHIFT (12U)
7168#define CCM_CCGR7_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR7_CG6_SHIFT)) & CCM_CCGR7_CG6_MASK)
7169/*! @} */
7170
7171/*! @name CMEOR - CCM Module Enable Overide Register */
7172/*! @{ */
7173#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
7174#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
7175/*! MOD_EN_OV_GPT
7176 * 0b0..don't override module enable signal
7177 * 0b1..override module enable signal
7178 */
7179#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
7180#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
7181#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
7182/*! MOD_EN_OV_PIT
7183 * 0b0..don't override module enable signal
7184 * 0b1..override module enable signal
7185 */
7186#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
7187#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)
7188#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)
7189/*! MOD_EN_USDHC
7190 * 0b0..don't override module enable signal
7191 * 0b1..override module enable signal
7192 */
7193#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
7194#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
7195#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
7196/*! MOD_EN_OV_TRNG
7197 * 0b0..don't override module enable signal
7198 * 0b1..override module enable signal
7199 */
7200#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
7201#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK (0x400U)
7202#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT (10U)
7203/*! MOD_EN_OV_CANFD_CPI
7204 * 0b0..don't override module enable signal
7205 * 0b1..override module enable signal
7206 */
7207#define CCM_CMEOR_MOD_EN_OV_CANFD_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CANFD_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CANFD_CPI_MASK)
7208#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)
7209#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)
7210/*! MOD_EN_OV_CAN2_CPI
7211 * 0b0..don't override module enable signal
7212 * 0b1..override module enable signal
7213 */
7214#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
7215#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)
7216#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)
7217/*! MOD_EN_OV_CAN1_CPI
7218 * 0b0..don't overide module enable signal
7219 * 0b1..overide module enable signal
7220 */
7221#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)
7222/*! @} */
7223
7224
7225/*!
7226 * @}
7227 */ /* end of group CCM_Register_Masks */
7228
7229
7230/* CCM - Peripheral instance base addresses */
7231/** Peripheral CCM base address */
7232#define CCM_BASE (0x400FC000u)
7233/** Peripheral CCM base pointer */
7234#define CCM ((CCM_Type *)CCM_BASE)
7235/** Array initializer of CCM peripheral base addresses */
7236#define CCM_BASE_ADDRS { CCM_BASE }
7237/** Array initializer of CCM peripheral base pointers */
7238#define CCM_BASE_PTRS { CCM }
7239/** Interrupt vectors for the CCM peripheral type */
7240#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }
7241
7242/*!
7243 * @}
7244 */ /* end of group CCM_Peripheral_Access_Layer */
7245
7246
7247/* ----------------------------------------------------------------------------
7248 -- CCM_ANALOG Peripheral Access Layer
7249 ---------------------------------------------------------------------------- */
7250
7251/*!
7252 * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
7253 * @{
7254 */
7255
7256/** CCM_ANALOG - Register Layout Typedef */
7257typedef struct {
7258 __IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */
7259 __IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */
7260 __IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */
7261 __IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */
7262 __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */
7263 __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */
7264 __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */
7265 __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */
7266 __IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */
7267 __IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */
7268 __IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */
7269 __IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */
7270 __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */
7271 __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */
7272 __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */
7273 __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */
7274 __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */
7275 uint8_t RESERVED_0[12];
7276 __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */
7277 uint8_t RESERVED_1[12];
7278 __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */
7279 uint8_t RESERVED_2[12];
7280 __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */
7281 __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */
7282 __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */
7283 __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */
7284 __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */
7285 uint8_t RESERVED_3[12];
7286 __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */
7287 uint8_t RESERVED_4[12];
7288 __IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */
7289 __IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */
7290 __IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */
7291 __IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */
7292 __IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */
7293 uint8_t RESERVED_5[12];
7294 __IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */
7295 uint8_t RESERVED_6[28];
7296 __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */
7297 __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */
7298 __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */
7299 __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */
7300 __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */
7301 __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */
7302 __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */
7303 __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */
7304 __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */
7305 __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */
7306 __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */
7307 __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */
7308 uint8_t RESERVED_7[64];
7309 __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */
7310 __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */
7311 __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */
7312 __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */
7313 __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */
7314 __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */
7315 __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */
7316 __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */
7317 __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */
7318 __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */
7319 __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */
7320 __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */
7321} CCM_ANALOG_Type;
7322
7323/* ----------------------------------------------------------------------------
7324 -- CCM_ANALOG Register Masks
7325 ---------------------------------------------------------------------------- */
7326
7327/*!
7328 * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
7329 * @{
7330 */
7331
7332/*! @name PLL_ARM - Analog ARM PLL control Register */
7333/*! @{ */
7334#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU)
7335#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U)
7336#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)
7337#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U)
7338#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U)
7339#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
7340#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U)
7341#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U)
7342#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)
7343#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U)
7344#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U)
7345/*! BYPASS_CLK_SRC
7346 * 0b00..Select the 24MHz oscillator as source.
7347 * 0b01..Select the CLK1_N / CLK1_P as source.
7348 * 0b10..Reserved1
7349 * 0b11..Reserved2
7350 */
7351#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)
7352#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U)
7353#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U)
7354#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
7355#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U)
7356#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U)
7357#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK)
7358#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U)
7359#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U)
7360#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK)
7361/*! @} */
7362
7363/*! @name PLL_ARM_SET - Analog ARM PLL control Register */
7364/*! @{ */
7365#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU)
7366#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U)
7367#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)
7368#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U)
7369#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U)
7370#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK)
7371#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U)
7372#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U)
7373#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)
7374#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7375#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)
7376/*! BYPASS_CLK_SRC
7377 * 0b00..Select the 24MHz oscillator as source.
7378 * 0b01..Select the CLK1_N / CLK1_P as source.
7379 * 0b10..Reserved1
7380 * 0b11..Reserved2
7381 */
7382#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)
7383#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U)
7384#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U)
7385#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK)
7386#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U)
7387#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U)
7388#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK)
7389#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U)
7390#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U)
7391#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK)
7392/*! @} */
7393
7394/*! @name PLL_ARM_CLR - Analog ARM PLL control Register */
7395/*! @{ */
7396#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU)
7397#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U)
7398#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)
7399#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U)
7400#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U)
7401#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK)
7402#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U)
7403#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U)
7404#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)
7405#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7406#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7407/*! BYPASS_CLK_SRC
7408 * 0b00..Select the 24MHz oscillator as source.
7409 * 0b01..Select the CLK1_N / CLK1_P as source.
7410 * 0b10..Reserved1
7411 * 0b11..Reserved2
7412 */
7413#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)
7414#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U)
7415#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U)
7416#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK)
7417#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U)
7418#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U)
7419#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK)
7420#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U)
7421#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U)
7422#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK)
7423/*! @} */
7424
7425/*! @name PLL_ARM_TOG - Analog ARM PLL control Register */
7426/*! @{ */
7427#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU)
7428#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U)
7429#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)
7430#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U)
7431#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U)
7432#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK)
7433#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U)
7434#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U)
7435#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)
7436#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7437#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7438/*! BYPASS_CLK_SRC
7439 * 0b00..Select the 24MHz oscillator as source.
7440 * 0b01..Select the CLK1_N / CLK1_P as source.
7441 * 0b10..Reserved1
7442 * 0b11..Reserved2
7443 */
7444#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)
7445#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U)
7446#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U)
7447#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK)
7448#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U)
7449#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U)
7450#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK)
7451#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U)
7452#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U)
7453#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK)
7454/*! @} */
7455
7456/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */
7457/*! @{ */
7458#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)
7459#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)
7460#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
7461#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)
7462#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)
7463/*! EN_USB_CLKS
7464 * 0b0..PLL outputs for USBPHYn off.
7465 * 0b1..PLL outputs for USBPHYn on.
7466 */
7467#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
7468#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)
7469#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)
7470#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
7471#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)
7472#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)
7473#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
7474#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)
7475#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
7476/*! BYPASS_CLK_SRC
7477 * 0b00..Select the 24MHz oscillator as source.
7478 * 0b01..Select the CLK1_N / CLK1_P as source.
7479 */
7480#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
7481#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)
7482#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)
7483#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
7484#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)
7485#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)
7486#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
7487/*! @} */
7488
7489/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */
7490/*! @{ */
7491#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)
7492#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
7493#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
7494#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
7495#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
7496/*! EN_USB_CLKS
7497 * 0b0..PLL outputs for USBPHYn off.
7498 * 0b1..PLL outputs for USBPHYn on.
7499 */
7500#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
7501#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)
7502#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)
7503#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
7504#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)
7505#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)
7506#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
7507#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7508#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
7509/*! BYPASS_CLK_SRC
7510 * 0b00..Select the 24MHz oscillator as source.
7511 * 0b01..Select the CLK1_N / CLK1_P as source.
7512 */
7513#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
7514#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)
7515#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)
7516#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
7517#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)
7518#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)
7519#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
7520/*! @} */
7521
7522/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */
7523/*! @{ */
7524#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)
7525#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
7526#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
7527#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
7528#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
7529/*! EN_USB_CLKS
7530 * 0b0..PLL outputs for USBPHYn off.
7531 * 0b1..PLL outputs for USBPHYn on.
7532 */
7533#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
7534#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)
7535#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)
7536#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
7537#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)
7538#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)
7539#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
7540#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7541#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7542/*! BYPASS_CLK_SRC
7543 * 0b00..Select the 24MHz oscillator as source.
7544 * 0b01..Select the CLK1_N / CLK1_P as source.
7545 */
7546#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
7547#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)
7548#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)
7549#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
7550#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)
7551#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)
7552#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
7553/*! @} */
7554
7555/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */
7556/*! @{ */
7557#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)
7558#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
7559#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
7560#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
7561#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
7562/*! EN_USB_CLKS
7563 * 0b0..PLL outputs for USBPHYn off.
7564 * 0b1..PLL outputs for USBPHYn on.
7565 */
7566#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
7567#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)
7568#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)
7569#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
7570#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)
7571#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)
7572#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
7573#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7574#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7575/*! BYPASS_CLK_SRC
7576 * 0b00..Select the 24MHz oscillator as source.
7577 * 0b01..Select the CLK1_N / CLK1_P as source.
7578 */
7579#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
7580#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)
7581#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)
7582#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
7583#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)
7584#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)
7585#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
7586/*! @} */
7587
7588/*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */
7589/*! @{ */
7590#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U)
7591#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U)
7592#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)
7593#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U)
7594#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U)
7595#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK)
7596#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U)
7597#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U)
7598#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK)
7599#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U)
7600#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U)
7601#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)
7602#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U)
7603#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)
7604/*! BYPASS_CLK_SRC
7605 * 0b00..Select the 24MHz oscillator as source.
7606 * 0b01..Select the CLK1_N / CLK1_P as source.
7607 * 0b10..Reserved1
7608 * 0b11..Reserved2
7609 */
7610#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)
7611#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U)
7612#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U)
7613#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK)
7614#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U)
7615#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U)
7616#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK)
7617/*! @} */
7618
7619/*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */
7620/*! @{ */
7621#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U)
7622#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U)
7623#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)
7624#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U)
7625#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U)
7626#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK)
7627#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U)
7628#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U)
7629#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK)
7630#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U)
7631#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U)
7632#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)
7633#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7634#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)
7635/*! BYPASS_CLK_SRC
7636 * 0b00..Select the 24MHz oscillator as source.
7637 * 0b01..Select the CLK1_N / CLK1_P as source.
7638 * 0b10..Reserved1
7639 * 0b11..Reserved2
7640 */
7641#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)
7642#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U)
7643#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U)
7644#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK)
7645#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U)
7646#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U)
7647#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK)
7648/*! @} */
7649
7650/*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */
7651/*! @{ */
7652#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U)
7653#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U)
7654#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)
7655#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U)
7656#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U)
7657#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK)
7658#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U)
7659#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U)
7660#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK)
7661#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U)
7662#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U)
7663#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)
7664#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7665#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7666/*! BYPASS_CLK_SRC
7667 * 0b00..Select the 24MHz oscillator as source.
7668 * 0b01..Select the CLK1_N / CLK1_P as source.
7669 * 0b10..Reserved1
7670 * 0b11..Reserved2
7671 */
7672#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)
7673#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U)
7674#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U)
7675#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK)
7676#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U)
7677#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U)
7678#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK)
7679/*! @} */
7680
7681/*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */
7682/*! @{ */
7683#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U)
7684#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U)
7685#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)
7686#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U)
7687#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U)
7688#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK)
7689#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U)
7690#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U)
7691#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK)
7692#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U)
7693#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U)
7694#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)
7695#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7696#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7697/*! BYPASS_CLK_SRC
7698 * 0b00..Select the 24MHz oscillator as source.
7699 * 0b01..Select the CLK1_N / CLK1_P as source.
7700 * 0b10..Reserved1
7701 * 0b11..Reserved2
7702 */
7703#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)
7704#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U)
7705#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U)
7706#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK)
7707#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U)
7708#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U)
7709#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK)
7710/*! @} */
7711
7712/*! @name PLL_SYS - Analog System PLL Control Register */
7713/*! @{ */
7714#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)
7715#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)
7716#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
7717#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)
7718#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)
7719#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
7720#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)
7721#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)
7722#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
7723#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)
7724#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)
7725/*! BYPASS_CLK_SRC
7726 * 0b00..Select the 24MHz oscillator as source.
7727 * 0b01..Select the CLK1_N / CLK1_P as source.
7728 */
7729#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
7730#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)
7731#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)
7732#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
7733#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)
7734#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)
7735#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
7736/*! @} */
7737
7738/*! @name PLL_SYS_SET - Analog System PLL Control Register */
7739/*! @{ */
7740#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)
7741#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)
7742#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
7743#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)
7744#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)
7745#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
7746#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)
7747#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)
7748#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
7749#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7750#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
7751/*! BYPASS_CLK_SRC
7752 * 0b00..Select the 24MHz oscillator as source.
7753 * 0b01..Select the CLK1_N / CLK1_P as source.
7754 */
7755#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
7756#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)
7757#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)
7758#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
7759#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)
7760#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)
7761#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
7762/*! @} */
7763
7764/*! @name PLL_SYS_CLR - Analog System PLL Control Register */
7765/*! @{ */
7766#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)
7767#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)
7768#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
7769#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)
7770#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)
7771#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
7772#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)
7773#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)
7774#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
7775#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7776#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7777/*! BYPASS_CLK_SRC
7778 * 0b00..Select the 24MHz oscillator as source.
7779 * 0b01..Select the CLK1_N / CLK1_P as source.
7780 */
7781#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
7782#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)
7783#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)
7784#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
7785#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)
7786#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)
7787#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
7788/*! @} */
7789
7790/*! @name PLL_SYS_TOG - Analog System PLL Control Register */
7791/*! @{ */
7792#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)
7793#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)
7794#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
7795#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)
7796#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)
7797#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
7798#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)
7799#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)
7800#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
7801#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7802#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7803/*! BYPASS_CLK_SRC
7804 * 0b00..Select the 24MHz oscillator as source.
7805 * 0b01..Select the CLK1_N / CLK1_P as source.
7806 */
7807#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
7808#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)
7809#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)
7810#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
7811#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)
7812#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)
7813#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
7814/*! @} */
7815
7816/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */
7817/*! @{ */
7818#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)
7819#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)
7820#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
7821#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)
7822#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)
7823/*! ENABLE - Enable bit
7824 * 0b0..Spread spectrum modulation disabled
7825 * 0b1..Soread spectrum modulation enabled
7826 */
7827#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
7828#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)
7829#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)
7830#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
7831/*! @} */
7832
7833/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */
7834/*! @{ */
7835#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)
7836#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)
7837#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
7838/*! @} */
7839
7840/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */
7841/*! @{ */
7842#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)
7843#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)
7844#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
7845/*! @} */
7846
7847/*! @name PLL_AUDIO - Analog Audio PLL control Register */
7848/*! @{ */
7849#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
7850#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
7851#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
7852#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)
7853#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)
7854#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
7855#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)
7856#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)
7857#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
7858#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
7859#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
7860/*! BYPASS_CLK_SRC
7861 * 0b00..Select the 24MHz oscillator as source.
7862 * 0b01..Select the CLK1_N / CLK1_P as source.
7863 * 0b10..Reserved1
7864 * 0b11..Reserved2
7865 */
7866#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
7867#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)
7868#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)
7869#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
7870#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
7871#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
7872/*! POST_DIV_SELECT
7873 * 0b00..Divide by 4.
7874 * 0b01..Divide by 2.
7875 * 0b10..Divide by 1.
7876 * 0b11..Reserved
7877 */
7878#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
7879#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)
7880#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)
7881#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
7882/*! @} */
7883
7884/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */
7885/*! @{ */
7886#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
7887#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
7888#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
7889#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)
7890#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
7891#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
7892#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)
7893#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)
7894#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
7895#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
7896#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
7897/*! BYPASS_CLK_SRC
7898 * 0b00..Select the 24MHz oscillator as source.
7899 * 0b01..Select the CLK1_N / CLK1_P as source.
7900 * 0b10..Reserved1
7901 * 0b11..Reserved2
7902 */
7903#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
7904#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)
7905#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)
7906#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
7907#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
7908#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
7909/*! POST_DIV_SELECT
7910 * 0b00..Divide by 4.
7911 * 0b01..Divide by 2.
7912 * 0b10..Divide by 1.
7913 * 0b11..Reserved
7914 */
7915#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
7916#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)
7917#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)
7918#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)
7919/*! @} */
7920
7921/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */
7922/*! @{ */
7923#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)
7924#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)
7925#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
7926#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)
7927#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)
7928#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)
7929#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)
7930#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)
7931#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
7932#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
7933#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
7934/*! BYPASS_CLK_SRC
7935 * 0b00..Select the 24MHz oscillator as source.
7936 * 0b01..Select the CLK1_N / CLK1_P as source.
7937 * 0b10..Reserved1
7938 * 0b11..Reserved2
7939 */
7940#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
7941#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)
7942#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)
7943#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)
7944#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
7945#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
7946/*! POST_DIV_SELECT
7947 * 0b00..Divide by 4.
7948 * 0b01..Divide by 2.
7949 * 0b10..Divide by 1.
7950 * 0b11..Reserved
7951 */
7952#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
7953#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)
7954#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)
7955#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)
7956/*! @} */
7957
7958/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */
7959/*! @{ */
7960#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)
7961#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)
7962#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
7963#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)
7964#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)
7965#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)
7966#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)
7967#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)
7968#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
7969#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
7970#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
7971/*! BYPASS_CLK_SRC
7972 * 0b00..Select the 24MHz oscillator as source.
7973 * 0b01..Select the CLK1_N / CLK1_P as source.
7974 * 0b10..Reserved1
7975 * 0b11..Reserved2
7976 */
7977#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
7978#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)
7979#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)
7980#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)
7981#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
7982#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
7983/*! POST_DIV_SELECT
7984 * 0b00..Divide by 4.
7985 * 0b01..Divide by 2.
7986 * 0b10..Divide by 1.
7987 * 0b11..Reserved
7988 */
7989#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
7990#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)
7991#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)
7992#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)
7993/*! @} */
7994
7995/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */
7996/*! @{ */
7997#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)
7998#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)
7999#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
8000/*! @} */
8001
8002/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */
8003/*! @{ */
8004#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)
8005#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)
8006#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
8007/*! @} */
8008
8009/*! @name PLL_VIDEO - Analog Video PLL control Register */
8010/*! @{ */
8011#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU)
8012#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U)
8013#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
8014#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U)
8015#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U)
8016#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK)
8017#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U)
8018#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U)
8019#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)
8020#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)
8021#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)
8022/*! BYPASS_CLK_SRC
8023 * 0b00..Select the 24MHz oscillator as source.
8024 * 0b01..Select the CLK1_N / CLK1_P as source.
8025 * 0b10..Reserved1
8026 * 0b11..Reserved2
8027 */
8028#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
8029#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U)
8030#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U)
8031#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK)
8032#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)
8033#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)
8034/*! POST_DIV_SELECT
8035 * 0b00..Divide by 4.
8036 * 0b01..Divide by 2.
8037 * 0b10..Divide by 1.
8038 * 0b11..Reserved
8039 */
8040#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)
8041#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U)
8042#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U)
8043#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK)
8044/*! @} */
8045
8046/*! @name PLL_VIDEO_SET - Analog Video PLL control Register */
8047/*! @{ */
8048#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU)
8049#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U)
8050#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
8051#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U)
8052#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U)
8053#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK)
8054#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U)
8055#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U)
8056#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)
8057#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
8058#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)
8059/*! BYPASS_CLK_SRC
8060 * 0b00..Select the 24MHz oscillator as source.
8061 * 0b01..Select the CLK1_N / CLK1_P as source.
8062 * 0b10..Reserved1
8063 * 0b11..Reserved2
8064 */
8065#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
8066#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U)
8067#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U)
8068#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK)
8069#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)
8070#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)
8071/*! POST_DIV_SELECT
8072 * 0b00..Divide by 4.
8073 * 0b01..Divide by 2.
8074 * 0b10..Divide by 1.
8075 * 0b11..Reserved
8076 */
8077#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)
8078#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U)
8079#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U)
8080#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK)
8081/*! @} */
8082
8083/*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */
8084/*! @{ */
8085#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU)
8086#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U)
8087#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
8088#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U)
8089#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U)
8090#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK)
8091#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U)
8092#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U)
8093#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)
8094#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
8095#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
8096/*! BYPASS_CLK_SRC
8097 * 0b00..Select the 24MHz oscillator as source.
8098 * 0b01..Select the CLK1_N / CLK1_P as source.
8099 * 0b10..Reserved1
8100 * 0b11..Reserved2
8101 */
8102#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
8103#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U)
8104#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U)
8105#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK)
8106#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)
8107#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)
8108/*! POST_DIV_SELECT
8109 * 0b00..Divide by 4.
8110 * 0b01..Divide by 2.
8111 * 0b10..Divide by 1.
8112 * 0b11..Reserved
8113 */
8114#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)
8115#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U)
8116#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U)
8117#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK)
8118/*! @} */
8119
8120/*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */
8121/*! @{ */
8122#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU)
8123#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U)
8124#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
8125#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U)
8126#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U)
8127#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK)
8128#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U)
8129#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U)
8130#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)
8131#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
8132#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
8133/*! BYPASS_CLK_SRC
8134 * 0b00..Select the 24MHz oscillator as source.
8135 * 0b01..Select the CLK1_N / CLK1_P as source.
8136 * 0b10..Reserved1
8137 * 0b11..Reserved2
8138 */
8139#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
8140#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U)
8141#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U)
8142#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK)
8143#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)
8144#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)
8145/*! POST_DIV_SELECT
8146 * 0b00..Divide by 4.
8147 * 0b01..Divide by 2.
8148 * 0b10..Divide by 1.
8149 * 0b11..Reserved
8150 */
8151#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)
8152#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U)
8153#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U)
8154#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK)
8155/*! @} */
8156
8157/*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */
8158/*! @{ */
8159#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU)
8160#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U)
8161#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
8162/*! @} */
8163
8164/*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */
8165/*! @{ */
8166#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU)
8167#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U)
8168#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
8169/*! @} */
8170
8171/*! @name PLL_ENET - Analog ENET PLL Control Register */
8172/*! @{ */
8173#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U)
8174#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U)
8175#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)
8176#define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK (0xCU)
8177#define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_SHIFT (2U)
8178/*! ENET2_DIV_SELECT
8179 * 0b00..25MHz
8180 * 0b01..50MHz
8181 * 0b10..100MHz (not 50% duty cycle)
8182 * 0b11..125MHz
8183 */
8184#define CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)
8185#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)
8186#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)
8187#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
8188#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U)
8189#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U)
8190#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)
8191#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)
8192#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
8193/*! BYPASS_CLK_SRC
8194 * 0b00..Select the 24MHz oscillator as source.
8195 * 0b01..Select the CLK1_N / CLK1_P as source.
8196 * 0b10..Reserved1
8197 * 0b11..Reserved2
8198 */
8199#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
8200#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)
8201#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)
8202#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
8203#define CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK (0x100000U)
8204#define CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT (20U)
8205#define CCM_ANALOG_PLL_ENET_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK)
8206#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)
8207#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)
8208#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)
8209#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)
8210#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)
8211#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)
8212/*! @} */
8213
8214/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */
8215/*! @{ */
8216#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U)
8217#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U)
8218#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK)
8219#define CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_MASK (0xCU)
8220#define CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_SHIFT (2U)
8221/*! ENET2_DIV_SELECT
8222 * 0b00..25MHz
8223 * 0b01..50MHz
8224 * 0b10..100MHz (not 50% duty cycle)
8225 * 0b11..125MHz
8226 */
8227#define CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_DIV_SELECT_MASK)
8228#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)
8229#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)
8230#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)
8231#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U)
8232#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U)
8233#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)
8234#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
8235#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
8236/*! BYPASS_CLK_SRC
8237 * 0b00..Select the 24MHz oscillator as source.
8238 * 0b01..Select the CLK1_N / CLK1_P as source.
8239 * 0b10..Reserved1
8240 * 0b11..Reserved2
8241 */
8242#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
8243#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)
8244#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)
8245#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)
8246#define CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_MASK (0x100000U)
8247#define CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_SHIFT (20U)
8248#define CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET2_REF_EN_MASK)
8249#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)
8250#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)
8251#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)
8252#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)
8253#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)
8254#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)
8255/*! @} */
8256
8257/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */
8258/*! @{ */
8259#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U)
8260#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U)
8261#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK)
8262#define CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_MASK (0xCU)
8263#define CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_SHIFT (2U)
8264/*! ENET2_DIV_SELECT
8265 * 0b00..25MHz
8266 * 0b01..50MHz
8267 * 0b10..100MHz (not 50% duty cycle)
8268 * 0b11..125MHz
8269 */
8270#define CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_DIV_SELECT_MASK)
8271#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)
8272#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)
8273#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)
8274#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U)
8275#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U)
8276#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)
8277#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
8278#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
8279/*! BYPASS_CLK_SRC
8280 * 0b00..Select the 24MHz oscillator as source.
8281 * 0b01..Select the CLK1_N / CLK1_P as source.
8282 * 0b10..Reserved1
8283 * 0b11..Reserved2
8284 */
8285#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
8286#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)
8287#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)
8288#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)
8289#define CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_MASK (0x100000U)
8290#define CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_SHIFT (20U)
8291#define CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET2_REF_EN_MASK)
8292#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)
8293#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)
8294#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)
8295#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)
8296#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)
8297#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)
8298/*! @} */
8299
8300/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */
8301/*! @{ */
8302#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U)
8303#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U)
8304#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK)
8305#define CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_MASK (0xCU)
8306#define CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_SHIFT (2U)
8307/*! ENET2_DIV_SELECT
8308 * 0b00..25MHz
8309 * 0b01..50MHz
8310 * 0b10..100MHz (not 50% duty cycle)
8311 * 0b11..125MHz
8312 */
8313#define CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_DIV_SELECT_MASK)
8314#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)
8315#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)
8316#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)
8317#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U)
8318#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U)
8319#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)
8320#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
8321#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
8322/*! BYPASS_CLK_SRC
8323 * 0b00..Select the 24MHz oscillator as source.
8324 * 0b01..Select the CLK1_N / CLK1_P as source.
8325 * 0b10..Reserved1
8326 * 0b11..Reserved2
8327 */
8328#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
8329#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)
8330#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)
8331#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)
8332#define CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_MASK (0x100000U)
8333#define CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_SHIFT (20U)
8334#define CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET2_REF_EN_MASK)
8335#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)
8336#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)
8337#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)
8338#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)
8339#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)
8340#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)
8341/*! @} */
8342
8343/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
8344/*! @{ */
8345#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)
8346#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)
8347#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
8348#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)
8349#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)
8350#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)
8351#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)
8352#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)
8353#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)
8354#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)
8355#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)
8356#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
8357#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)
8358#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)
8359#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)
8360#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)
8361#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)
8362#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)
8363#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)
8364#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)
8365#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
8366#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)
8367#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)
8368#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)
8369#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)
8370#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)
8371#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)
8372#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)
8373#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)
8374#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
8375#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)
8376#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)
8377#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)
8378#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)
8379#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)
8380#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)
8381/*! @} */
8382
8383/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
8384/*! @{ */
8385#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)
8386#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)
8387#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
8388#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)
8389#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)
8390#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)
8391#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)
8392#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)
8393#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)
8394#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)
8395#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)
8396#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
8397#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)
8398#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)
8399#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)
8400#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)
8401#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)
8402#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)
8403#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)
8404#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)
8405#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
8406#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)
8407#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)
8408#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)
8409#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)
8410#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)
8411#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)
8412#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)
8413#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)
8414#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
8415#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)
8416#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)
8417#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)
8418#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)
8419#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)
8420#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)
8421/*! @} */
8422
8423/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
8424/*! @{ */
8425#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)
8426#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)
8427#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
8428#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)
8429#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)
8430#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)
8431#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)
8432#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)
8433#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)
8434#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)
8435#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)
8436#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
8437#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)
8438#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)
8439#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)
8440#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)
8441#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)
8442#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)
8443#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)
8444#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)
8445#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
8446#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)
8447#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)
8448#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)
8449#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)
8450#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)
8451#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)
8452#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)
8453#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)
8454#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
8455#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)
8456#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)
8457#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)
8458#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)
8459#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)
8460#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)
8461/*! @} */
8462
8463/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
8464/*! @{ */
8465#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)
8466#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)
8467#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
8468#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)
8469#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)
8470#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)
8471#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)
8472#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)
8473#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)
8474#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)
8475#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)
8476#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
8477#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)
8478#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)
8479#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)
8480#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)
8481#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)
8482#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)
8483#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)
8484#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)
8485#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
8486#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)
8487#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)
8488#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)
8489#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)
8490#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)
8491#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)
8492#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)
8493#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)
8494#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
8495#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)
8496#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)
8497#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)
8498#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)
8499#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)
8500#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)
8501/*! @} */
8502
8503/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
8504/*! @{ */
8505#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)
8506#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)
8507#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
8508#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)
8509#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)
8510#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)
8511#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)
8512#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)
8513#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)
8514#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)
8515#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)
8516#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
8517#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)
8518#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)
8519#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)
8520#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)
8521#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)
8522#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)
8523#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)
8524#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)
8525#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
8526#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)
8527#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)
8528#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)
8529#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)
8530#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)
8531#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)
8532#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)
8533#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)
8534#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
8535#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)
8536#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)
8537#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)
8538#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)
8539#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)
8540#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)
8541/*! @} */
8542
8543/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
8544/*! @{ */
8545#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)
8546#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)
8547#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
8548#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)
8549#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)
8550#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)
8551#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)
8552#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)
8553#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)
8554#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)
8555#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)
8556#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
8557#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)
8558#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)
8559#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)
8560#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)
8561#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)
8562#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)
8563#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)
8564#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)
8565#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
8566#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)
8567#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)
8568#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)
8569#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)
8570#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)
8571#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)
8572#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)
8573#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)
8574#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
8575#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)
8576#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)
8577#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)
8578#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)
8579#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)
8580#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)
8581/*! @} */
8582
8583/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
8584/*! @{ */
8585#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)
8586#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)
8587#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
8588#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)
8589#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)
8590#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)
8591#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)
8592#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)
8593#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)
8594#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)
8595#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)
8596#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
8597#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)
8598#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)
8599#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)
8600#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)
8601#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)
8602#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)
8603#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)
8604#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)
8605#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
8606#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)
8607#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)
8608#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)
8609#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)
8610#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)
8611#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)
8612#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)
8613#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)
8614#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
8615#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)
8616#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)
8617#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)
8618#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)
8619#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)
8620#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)
8621/*! @} */
8622
8623/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
8624/*! @{ */
8625#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)
8626#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)
8627#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
8628#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)
8629#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)
8630#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)
8631#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)
8632#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)
8633#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)
8634#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)
8635#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)
8636#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
8637#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)
8638#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)
8639#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)
8640#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)
8641#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)
8642#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)
8643#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)
8644#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)
8645#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
8646#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)
8647#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)
8648#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)
8649#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)
8650#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)
8651#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)
8652#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)
8653#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)
8654#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
8655#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)
8656#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)
8657#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)
8658#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)
8659#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)
8660#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)
8661/*! @} */
8662
8663/*! @name MISC0 - Miscellaneous Register 0 */
8664/*! @{ */
8665#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)
8666#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)
8667#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
8668#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
8669#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
8670/*! REFTOP_SELFBIASOFF
8671 * 0b0..Uses coarse bias currents for startup
8672 * 0b1..Uses bandgap-based bias currents for best performance.
8673 */
8674#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
8675#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)
8676#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)
8677/*! REFTOP_VBGADJ
8678 * 0b000..Nominal VBG
8679 * 0b001..VBG+0.78%
8680 * 0b010..VBG+1.56%
8681 * 0b011..VBG+2.34%
8682 * 0b100..VBG-0.78%
8683 * 0b101..VBG-1.56%
8684 * 0b110..VBG-2.34%
8685 * 0b111..VBG-3.12%
8686 */
8687#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
8688#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)
8689#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)
8690#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
8691#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
8692#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
8693/*! STOP_MODE_CONFIG
8694 * 0b00..All analog except RTC powered down on stop mode assertion.
8695 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
8696 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
8697 * bandgap together with the rest analog is powered down.
8698 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
8699 */
8700#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
8701#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
8702#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
8703/*! DISCON_HIGH_SNVS
8704 * 0b0..Turn on the switch
8705 * 0b1..Turn off the switch
8706 */
8707#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
8708#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)
8709#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)
8710/*! OSC_I
8711 * 0b00..Nominal
8712 * 0b01..Decrease current by 12.5%
8713 * 0b10..Decrease current by 25.0%
8714 * 0b11..Decrease current by 37.5%
8715 */
8716#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
8717#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)
8718#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)
8719#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)
8720#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
8721#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)
8722#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
8723#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
8724#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)
8725/*! CLKGATE_CTRL
8726 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
8727 * 0b1..Prevent the logic from ever gating off the clock.
8728 */
8729#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
8730#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
8731#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)
8732/*! CLKGATE_DELAY
8733 * 0b000..0.5ms
8734 * 0b001..1.0ms
8735 * 0b010..2.0ms
8736 * 0b011..3.0ms
8737 * 0b100..4.0ms
8738 * 0b101..5.0ms
8739 * 0b110..6.0ms
8740 * 0b111..7.0ms
8741 */
8742#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
8743#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
8744#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
8745/*! RTC_XTAL_SOURCE
8746 * 0b0..Internal ring oscillator
8747 * 0b1..RTC_XTAL
8748 */
8749#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
8750#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
8751#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)
8752#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)
8753/*! @} */
8754
8755/*! @name MISC0_SET - Miscellaneous Register 0 */
8756/*! @{ */
8757#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)
8758#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)
8759#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
8760#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
8761#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
8762/*! REFTOP_SELFBIASOFF
8763 * 0b0..Uses coarse bias currents for startup
8764 * 0b1..Uses bandgap-based bias currents for best performance.
8765 */
8766#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
8767#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
8768#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
8769/*! REFTOP_VBGADJ
8770 * 0b000..Nominal VBG
8771 * 0b001..VBG+0.78%
8772 * 0b010..VBG+1.56%
8773 * 0b011..VBG+2.34%
8774 * 0b100..VBG-0.78%
8775 * 0b101..VBG-1.56%
8776 * 0b110..VBG-2.34%
8777 * 0b111..VBG-3.12%
8778 */
8779#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
8780#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
8781#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
8782#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
8783#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
8784#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
8785/*! STOP_MODE_CONFIG
8786 * 0b00..All analog except RTC powered down on stop mode assertion.
8787 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
8788 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
8789 * bandgap together with the rest analog is powered down.
8790 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
8791 */
8792#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
8793#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
8794#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
8795/*! DISCON_HIGH_SNVS
8796 * 0b0..Turn on the switch
8797 * 0b1..Turn off the switch
8798 */
8799#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
8800#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)
8801#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)
8802/*! OSC_I
8803 * 0b00..Nominal
8804 * 0b01..Decrease current by 12.5%
8805 * 0b10..Decrease current by 25.0%
8806 * 0b11..Decrease current by 37.5%
8807 */
8808#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
8809#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
8810#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)
8811#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)
8812#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
8813#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
8814#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
8815#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
8816#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
8817/*! CLKGATE_CTRL
8818 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
8819 * 0b1..Prevent the logic from ever gating off the clock.
8820 */
8821#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
8822#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
8823#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
8824/*! CLKGATE_DELAY
8825 * 0b000..0.5ms
8826 * 0b001..1.0ms
8827 * 0b010..2.0ms
8828 * 0b011..3.0ms
8829 * 0b100..4.0ms
8830 * 0b101..5.0ms
8831 * 0b110..6.0ms
8832 * 0b111..7.0ms
8833 */
8834#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
8835#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
8836#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
8837/*! RTC_XTAL_SOURCE
8838 * 0b0..Internal ring oscillator
8839 * 0b1..RTC_XTAL
8840 */
8841#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
8842#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
8843#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
8844#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)
8845/*! @} */
8846
8847/*! @name MISC0_CLR - Miscellaneous Register 0 */
8848/*! @{ */
8849#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
8850#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
8851#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
8852#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
8853#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
8854/*! REFTOP_SELFBIASOFF
8855 * 0b0..Uses coarse bias currents for startup
8856 * 0b1..Uses bandgap-based bias currents for best performance.
8857 */
8858#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
8859#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
8860#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
8861/*! REFTOP_VBGADJ
8862 * 0b000..Nominal VBG
8863 * 0b001..VBG+0.78%
8864 * 0b010..VBG+1.56%
8865 * 0b011..VBG+2.34%
8866 * 0b100..VBG-0.78%
8867 * 0b101..VBG-1.56%
8868 * 0b110..VBG-2.34%
8869 * 0b111..VBG-3.12%
8870 */
8871#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
8872#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
8873#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
8874#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
8875#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
8876#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
8877/*! STOP_MODE_CONFIG
8878 * 0b00..All analog except RTC powered down on stop mode assertion.
8879 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
8880 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
8881 * bandgap together with the rest analog is powered down.
8882 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
8883 */
8884#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
8885#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
8886#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
8887/*! DISCON_HIGH_SNVS
8888 * 0b0..Turn on the switch
8889 * 0b1..Turn off the switch
8890 */
8891#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
8892#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)
8893#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)
8894/*! OSC_I
8895 * 0b00..Nominal
8896 * 0b01..Decrease current by 12.5%
8897 * 0b10..Decrease current by 25.0%
8898 * 0b11..Decrease current by 37.5%
8899 */
8900#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
8901#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
8902#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
8903#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)
8904#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
8905#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
8906#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
8907#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
8908#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
8909/*! CLKGATE_CTRL
8910 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
8911 * 0b1..Prevent the logic from ever gating off the clock.
8912 */
8913#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
8914#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
8915#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
8916/*! CLKGATE_DELAY
8917 * 0b000..0.5ms
8918 * 0b001..1.0ms
8919 * 0b010..2.0ms
8920 * 0b011..3.0ms
8921 * 0b100..4.0ms
8922 * 0b101..5.0ms
8923 * 0b110..6.0ms
8924 * 0b111..7.0ms
8925 */
8926#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
8927#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
8928#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
8929/*! RTC_XTAL_SOURCE
8930 * 0b0..Internal ring oscillator
8931 * 0b1..RTC_XTAL
8932 */
8933#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
8934#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
8935#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
8936#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)
8937/*! @} */
8938
8939/*! @name MISC0_TOG - Miscellaneous Register 0 */
8940/*! @{ */
8941#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
8942#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
8943#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
8944#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
8945#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
8946/*! REFTOP_SELFBIASOFF
8947 * 0b0..Uses coarse bias currents for startup
8948 * 0b1..Uses bandgap-based bias currents for best performance.
8949 */
8950#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
8951#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
8952#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
8953/*! REFTOP_VBGADJ
8954 * 0b000..Nominal VBG
8955 * 0b001..VBG+0.78%
8956 * 0b010..VBG+1.56%
8957 * 0b011..VBG+2.34%
8958 * 0b100..VBG-0.78%
8959 * 0b101..VBG-1.56%
8960 * 0b110..VBG-2.34%
8961 * 0b111..VBG-3.12%
8962 */
8963#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
8964#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
8965#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
8966#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)
8967#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
8968#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
8969/*! STOP_MODE_CONFIG
8970 * 0b00..All analog except RTC powered down on stop mode assertion.
8971 * 0b01..Beside RTC, analog bandgap, 1p1 and 2p5 regulators are also on.
8972 * 0b10..Beside RTC, 1p1 and 2p5 regulators are also on, low-power bandgap is selected so that the normal analog
8973 * bandgap together with the rest analog is powered down.
8974 * 0b11..Beside RTC, low-power bandgap is selected and the rest analog is powered down.
8975 */
8976#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
8977#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
8978#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
8979/*! DISCON_HIGH_SNVS
8980 * 0b0..Turn on the switch
8981 * 0b1..Turn off the switch
8982 */
8983#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
8984#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)
8985#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)
8986/*! OSC_I
8987 * 0b00..Nominal
8988 * 0b01..Decrease current by 12.5%
8989 * 0b10..Decrease current by 25.0%
8990 * 0b11..Decrease current by 37.5%
8991 */
8992#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
8993#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
8994#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
8995#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)
8996#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
8997#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
8998#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)
8999#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
9000#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
9001/*! CLKGATE_CTRL
9002 * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
9003 * 0b1..Prevent the logic from ever gating off the clock.
9004 */
9005#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)
9006#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
9007#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
9008/*! CLKGATE_DELAY
9009 * 0b000..0.5ms
9010 * 0b001..1.0ms
9011 * 0b010..2.0ms
9012 * 0b011..3.0ms
9013 * 0b100..4.0ms
9014 * 0b101..5.0ms
9015 * 0b110..6.0ms
9016 * 0b111..7.0ms
9017 */
9018#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
9019#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
9020#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
9021/*! RTC_XTAL_SOURCE
9022 * 0b0..Internal ring oscillator
9023 * 0b1..RTC_XTAL
9024 */
9025#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
9026#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
9027#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
9028#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)
9029/*! @} */
9030
9031/*! @name MISC1 - Miscellaneous Register 1 */
9032/*! @{ */
9033#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
9034#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
9035/*! LVDS1_CLK_SEL
9036 * 0b00000..Arm PLL
9037 * 0b00001..System PLL
9038 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
9039 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
9040 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
9041 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
9042 * 0b00110..Audio PLL
9043 * 0b00111..Video PLL
9044 * 0b01001..ethernet ref clock (ENET_PLL)
9045 * 0b01100..USB1 PLL clock
9046 * 0b01101..USB2 PLL clock
9047 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
9048 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
9049 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
9050 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
9051 * 0b10010..xtal (24M)
9052 */
9053#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)
9054#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
9055#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
9056#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)
9057#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
9058#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
9059#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)
9060#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9061#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
9062#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)
9063#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9064#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
9065#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)
9066#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
9067#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
9068#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)
9069#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
9070#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)
9071#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)
9072#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
9073#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
9074#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)
9075#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
9076#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)
9077#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)
9078#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
9079#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)
9080#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)
9081/*! @} */
9082
9083/*! @name MISC1_SET - Miscellaneous Register 1 */
9084/*! @{ */
9085#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
9086#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
9087/*! LVDS1_CLK_SEL
9088 * 0b00000..Arm PLL
9089 * 0b00001..System PLL
9090 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
9091 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
9092 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
9093 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
9094 * 0b00110..Audio PLL
9095 * 0b00111..Video PLL
9096 * 0b01001..ethernet ref clock (ENET_PLL)
9097 * 0b01100..USB1 PLL clock
9098 * 0b01101..USB2 PLL clock
9099 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
9100 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
9101 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
9102 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
9103 * 0b10010..xtal (24M)
9104 */
9105#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)
9106#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
9107#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
9108#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)
9109#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
9110#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
9111#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)
9112#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9113#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
9114#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
9115#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9116#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
9117#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
9118#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
9119#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
9120#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)
9121#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
9122#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
9123#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)
9124#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
9125#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
9126#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)
9127#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
9128#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
9129#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)
9130#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
9131#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
9132#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)
9133/*! @} */
9134
9135/*! @name MISC1_CLR - Miscellaneous Register 1 */
9136/*! @{ */
9137#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
9138#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
9139/*! LVDS1_CLK_SEL
9140 * 0b00000..Arm PLL
9141 * 0b00001..System PLL
9142 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
9143 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
9144 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
9145 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
9146 * 0b00110..Audio PLL
9147 * 0b00111..Video PLL
9148 * 0b01001..ethernet ref clock (ENET_PLL)
9149 * 0b01100..USB1 PLL clock
9150 * 0b01101..USB2 PLL clock
9151 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
9152 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
9153 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
9154 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
9155 * 0b10010..xtal (24M)
9156 */
9157#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)
9158#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
9159#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
9160#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)
9161#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
9162#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
9163#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)
9164#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9165#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
9166#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
9167#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9168#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
9169#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
9170#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
9171#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
9172#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)
9173#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
9174#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
9175#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)
9176#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
9177#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
9178#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)
9179#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
9180#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
9181#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)
9182#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
9183#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
9184#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)
9185/*! @} */
9186
9187/*! @name MISC1_TOG - Miscellaneous Register 1 */
9188/*! @{ */
9189#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
9190#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
9191/*! LVDS1_CLK_SEL
9192 * 0b00000..Arm PLL
9193 * 0b00001..System PLL
9194 * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
9195 * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
9196 * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
9197 * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
9198 * 0b00110..Audio PLL
9199 * 0b00111..Video PLL
9200 * 0b01001..ethernet ref clock (ENET_PLL)
9201 * 0b01100..USB1 PLL clock
9202 * 0b01101..USB2 PLL clock
9203 * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
9204 * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
9205 * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
9206 * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
9207 * 0b10010..xtal (24M)
9208 */
9209#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)
9210#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
9211#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
9212#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)
9213#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
9214#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
9215#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)
9216#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
9217#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
9218#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
9219#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
9220#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
9221#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
9222#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
9223#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
9224#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)
9225#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
9226#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
9227#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)
9228#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
9229#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
9230#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)
9231#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
9232#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
9233#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)
9234#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
9235#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
9236#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)
9237/*! @} */
9238
9239/*! @name MISC2 - Miscellaneous Register 2 */
9240/*! @{ */
9241#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)
9242#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)
9243/*! REG0_BO_OFFSET
9244 * 0b100..Brownout offset = 0.100V
9245 * 0b111..Brownout offset = 0.175V
9246 */
9247#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
9248#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)
9249#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)
9250/*! REG0_BO_STATUS
9251 * 0b1..Brownout, supply is below target minus brownout offset.
9252 */
9253#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)
9254#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)
9255#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)
9256#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)
9257#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)
9258#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)
9259#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)
9260#define CCM_ANALOG_MISC2_PLL3_DISABLE_MASK (0x80U)
9261#define CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT (7U)
9262/*! PLL3_DISABLE
9263 * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
9264 * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
9265 */
9266#define CCM_ANALOG_MISC2_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_PLL3_DISABLE_MASK)
9267#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)
9268#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)
9269/*! REG1_BO_OFFSET
9270 * 0b100..Brownout offset = 0.100V
9271 * 0b111..Brownout offset = 0.175V
9272 */
9273#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
9274#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)
9275#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)
9276/*! REG1_BO_STATUS
9277 * 0b1..Brownout, supply is below target minus brownout offset.
9278 */
9279#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)
9280#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
9281#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)
9282#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)
9283#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)
9284#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)
9285#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)
9286#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
9287#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
9288/*! AUDIO_DIV_LSB
9289 * 0b0..divide by 1 (Default)
9290 * 0b1..divide by 2
9291 */
9292#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)
9293#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
9294#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)
9295/*! REG2_BO_OFFSET
9296 * 0b100..Brownout offset = 0.100V
9297 * 0b111..Brownout offset = 0.175V
9298 */
9299#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
9300#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)
9301#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)
9302#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)
9303#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
9304#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)
9305#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)
9306#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)
9307#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)
9308#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)
9309#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
9310#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
9311/*! AUDIO_DIV_MSB
9312 * 0b0..divide by 1 (Default)
9313 * 0b1..divide by 2
9314 */
9315#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)
9316#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
9317#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)
9318/*! REG0_STEP_TIME
9319 * 0b00..64
9320 * 0b01..128
9321 * 0b10..256
9322 * 0b11..512
9323 */
9324#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
9325#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
9326#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)
9327/*! REG1_STEP_TIME
9328 * 0b00..64
9329 * 0b01..128
9330 * 0b10..256
9331 * 0b11..512
9332 */
9333#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
9334#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
9335#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)
9336/*! REG2_STEP_TIME
9337 * 0b00..64
9338 * 0b01..128
9339 * 0b10..256
9340 * 0b11..512
9341 */
9342#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
9343#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)
9344#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)
9345/*! VIDEO_DIV
9346 * 0b00..divide by 1 (Default)
9347 * 0b01..divide by 2
9348 * 0b10..divide by 1
9349 * 0b11..divide by 4
9350 */
9351#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)
9352/*! @} */
9353
9354/*! @name MISC2_SET - Miscellaneous Register 2 */
9355/*! @{ */
9356#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
9357#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
9358/*! REG0_BO_OFFSET
9359 * 0b100..Brownout offset = 0.100V
9360 * 0b111..Brownout offset = 0.175V
9361 */
9362#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
9363#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
9364#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
9365/*! REG0_BO_STATUS
9366 * 0b1..Brownout, supply is below target minus brownout offset.
9367 */
9368#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)
9369#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
9370#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
9371#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)
9372#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)
9373#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)
9374#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)
9375#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK (0x80U)
9376#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT (7U)
9377/*! PLL3_DISABLE
9378 * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
9379 * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
9380 */
9381#define CCM_ANALOG_MISC2_SET_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_DISABLE_MASK)
9382#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
9383#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
9384/*! REG1_BO_OFFSET
9385 * 0b100..Brownout offset = 0.100V
9386 * 0b111..Brownout offset = 0.175V
9387 */
9388#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
9389#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
9390#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
9391/*! REG1_BO_STATUS
9392 * 0b1..Brownout, supply is below target minus brownout offset.
9393 */
9394#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)
9395#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
9396#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
9397#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)
9398#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)
9399#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)
9400#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)
9401#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
9402#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
9403/*! AUDIO_DIV_LSB
9404 * 0b0..divide by 1 (Default)
9405 * 0b1..divide by 2
9406 */
9407#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)
9408#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
9409#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
9410/*! REG2_BO_OFFSET
9411 * 0b100..Brownout offset = 0.100V
9412 * 0b111..Brownout offset = 0.175V
9413 */
9414#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
9415#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
9416#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
9417#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)
9418#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
9419#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
9420#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)
9421#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)
9422#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)
9423#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)
9424#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
9425#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
9426/*! AUDIO_DIV_MSB
9427 * 0b0..divide by 1 (Default)
9428 * 0b1..divide by 2
9429 */
9430#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)
9431#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
9432#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
9433/*! REG0_STEP_TIME
9434 * 0b00..64
9435 * 0b01..128
9436 * 0b10..256
9437 * 0b11..512
9438 */
9439#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
9440#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
9441#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
9442/*! REG1_STEP_TIME
9443 * 0b00..64
9444 * 0b01..128
9445 * 0b10..256
9446 * 0b11..512
9447 */
9448#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
9449#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
9450#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
9451/*! REG2_STEP_TIME
9452 * 0b00..64
9453 * 0b01..128
9454 * 0b10..256
9455 * 0b11..512
9456 */
9457#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
9458#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
9459#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U)
9460/*! VIDEO_DIV
9461 * 0b00..divide by 1 (Default)
9462 * 0b01..divide by 2
9463 * 0b10..divide by 1
9464 * 0b11..divide by 4
9465 */
9466#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)
9467/*! @} */
9468
9469/*! @name MISC2_CLR - Miscellaneous Register 2 */
9470/*! @{ */
9471#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
9472#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
9473/*! REG0_BO_OFFSET
9474 * 0b100..Brownout offset = 0.100V
9475 * 0b111..Brownout offset = 0.175V
9476 */
9477#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
9478#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
9479#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
9480/*! REG0_BO_STATUS
9481 * 0b1..Brownout, supply is below target minus brownout offset.
9482 */
9483#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)
9484#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
9485#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
9486#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)
9487#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)
9488#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)
9489#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)
9490#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK (0x80U)
9491#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT (7U)
9492/*! PLL3_DISABLE
9493 * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
9494 * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
9495 */
9496#define CCM_ANALOG_MISC2_CLR_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_DISABLE_MASK)
9497#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
9498#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
9499/*! REG1_BO_OFFSET
9500 * 0b100..Brownout offset = 0.100V
9501 * 0b111..Brownout offset = 0.175V
9502 */
9503#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
9504#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
9505#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
9506/*! REG1_BO_STATUS
9507 * 0b1..Brownout, supply is below target minus brownout offset.
9508 */
9509#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)
9510#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
9511#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
9512#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)
9513#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)
9514#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)
9515#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)
9516#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
9517#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
9518/*! AUDIO_DIV_LSB
9519 * 0b0..divide by 1 (Default)
9520 * 0b1..divide by 2
9521 */
9522#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)
9523#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
9524#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
9525/*! REG2_BO_OFFSET
9526 * 0b100..Brownout offset = 0.100V
9527 * 0b111..Brownout offset = 0.175V
9528 */
9529#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
9530#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
9531#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
9532#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)
9533#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
9534#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
9535#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)
9536#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)
9537#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)
9538#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)
9539#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
9540#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
9541/*! AUDIO_DIV_MSB
9542 * 0b0..divide by 1 (Default)
9543 * 0b1..divide by 2
9544 */
9545#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)
9546#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
9547#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
9548/*! REG0_STEP_TIME
9549 * 0b00..64
9550 * 0b01..128
9551 * 0b10..256
9552 * 0b11..512
9553 */
9554#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
9555#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
9556#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
9557/*! REG1_STEP_TIME
9558 * 0b00..64
9559 * 0b01..128
9560 * 0b10..256
9561 * 0b11..512
9562 */
9563#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
9564#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
9565#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
9566/*! REG2_STEP_TIME
9567 * 0b00..64
9568 * 0b01..128
9569 * 0b10..256
9570 * 0b11..512
9571 */
9572#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
9573#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
9574#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
9575/*! VIDEO_DIV
9576 * 0b00..divide by 1 (Default)
9577 * 0b01..divide by 2
9578 * 0b10..divide by 1
9579 * 0b11..divide by 4
9580 */
9581#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)
9582/*! @} */
9583
9584/*! @name MISC2_TOG - Miscellaneous Register 2 */
9585/*! @{ */
9586#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
9587#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
9588/*! REG0_BO_OFFSET
9589 * 0b100..Brownout offset = 0.100V
9590 * 0b111..Brownout offset = 0.175V
9591 */
9592#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
9593#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
9594#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
9595/*! REG0_BO_STATUS
9596 * 0b1..Brownout, supply is below target minus brownout offset.
9597 */
9598#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)
9599#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
9600#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
9601#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)
9602#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)
9603#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)
9604#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)
9605#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK (0x80U)
9606#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT (7U)
9607/*! PLL3_DISABLE
9608 * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
9609 * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
9610 */
9611#define CCM_ANALOG_MISC2_TOG_PLL3_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_DISABLE_MASK)
9612#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
9613#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
9614/*! REG1_BO_OFFSET
9615 * 0b100..Brownout offset = 0.100V
9616 * 0b111..Brownout offset = 0.175V
9617 */
9618#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
9619#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
9620#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
9621/*! REG1_BO_STATUS
9622 * 0b1..Brownout, supply is below target minus brownout offset.
9623 */
9624#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)
9625#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
9626#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
9627#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)
9628#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)
9629#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)
9630#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)
9631#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
9632#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
9633/*! AUDIO_DIV_LSB
9634 * 0b0..divide by 1 (Default)
9635 * 0b1..divide by 2
9636 */
9637#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)
9638#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
9639#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
9640/*! REG2_BO_OFFSET
9641 * 0b100..Brownout offset = 0.100V
9642 * 0b111..Brownout offset = 0.175V
9643 */
9644#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
9645#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
9646#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
9647#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)
9648#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
9649#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
9650#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)
9651#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)
9652#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)
9653#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)
9654#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
9655#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
9656/*! AUDIO_DIV_MSB
9657 * 0b0..divide by 1 (Default)
9658 * 0b1..divide by 2
9659 */
9660#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)
9661#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
9662#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
9663/*! REG0_STEP_TIME
9664 * 0b00..64
9665 * 0b01..128
9666 * 0b10..256
9667 * 0b11..512
9668 */
9669#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
9670#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
9671#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
9672/*! REG1_STEP_TIME
9673 * 0b00..64
9674 * 0b01..128
9675 * 0b10..256
9676 * 0b11..512
9677 */
9678#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
9679#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
9680#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
9681/*! REG2_STEP_TIME
9682 * 0b00..64
9683 * 0b01..128
9684 * 0b10..256
9685 * 0b11..512
9686 */
9687#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)
9688#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
9689#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
9690/*! VIDEO_DIV
9691 * 0b00..divide by 1 (Default)
9692 * 0b01..divide by 2
9693 * 0b10..divide by 1
9694 * 0b11..divide by 4
9695 */
9696#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)
9697/*! @} */
9698
9699
9700/*!
9701 * @}
9702 */ /* end of group CCM_ANALOG_Register_Masks */
9703
9704
9705/* CCM_ANALOG - Peripheral instance base addresses */
9706/** Peripheral CCM_ANALOG base address */
9707#define CCM_ANALOG_BASE (0x400D8000u)
9708/** Peripheral CCM_ANALOG base pointer */
9709#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
9710/** Array initializer of CCM_ANALOG peripheral base addresses */
9711#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
9712/** Array initializer of CCM_ANALOG peripheral base pointers */
9713#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
9714
9715/*!
9716 * @}
9717 */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
9718
9719
9720/* ----------------------------------------------------------------------------
9721 -- CM7_MCM Peripheral Access Layer
9722 ---------------------------------------------------------------------------- */
9723
9724/*!
9725 * @addtogroup CM7_MCM_Peripheral_Access_Layer CM7_MCM Peripheral Access Layer
9726 * @{
9727 */
9728
9729/** CM7_MCM - Register Layout Typedef */
9730typedef struct {
9731 uint8_t RESERVED_0[16];
9732 __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
9733} CM7_MCM_Type;
9734
9735/* ----------------------------------------------------------------------------
9736 -- CM7_MCM Register Masks
9737 ---------------------------------------------------------------------------- */
9738
9739/*!
9740 * @addtogroup CM7_MCM_Register_Masks CM7_MCM Register Masks
9741 * @{
9742 */
9743
9744/*! @name ISCR - Interrupt Status and Control Register */
9745/*! @{ */
9746#define CM7_MCM_ISCR_WABS_MASK (0x20U)
9747#define CM7_MCM_ISCR_WABS_SHIFT (5U)
9748/*! WABS - Write Abort on Slave
9749 * 0b0..No abort
9750 * 0b1..Abort
9751 */
9752#define CM7_MCM_ISCR_WABS(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABS_SHIFT)) & CM7_MCM_ISCR_WABS_MASK)
9753#define CM7_MCM_ISCR_WABSO_MASK (0x40U)
9754#define CM7_MCM_ISCR_WABSO_SHIFT (6U)
9755/*! WABSO - Write Abort on Slave Overrun
9756 * 0b0..No write abort overrun
9757 * 0b1..Write abort overrun occurred
9758 */
9759#define CM7_MCM_ISCR_WABSO(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABSO_SHIFT)) & CM7_MCM_ISCR_WABSO_MASK)
9760#define CM7_MCM_ISCR_FIOC_MASK (0x100U)
9761#define CM7_MCM_ISCR_FIOC_SHIFT (8U)
9762/*! FIOC - FPU Invalid Operation interrupt Status
9763 * 0b0..No interrupt
9764 * 0b1..Interrupt occured
9765 */
9766#define CM7_MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOC_SHIFT)) & CM7_MCM_ISCR_FIOC_MASK)
9767#define CM7_MCM_ISCR_FDZC_MASK (0x200U)
9768#define CM7_MCM_ISCR_FDZC_SHIFT (9U)
9769/*! FDZC - FPU Divide-by-Zero Interrupt Status
9770 * 0b0..No interrupt
9771 * 0b1..Interrupt occured
9772 */
9773#define CM7_MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZC_SHIFT)) & CM7_MCM_ISCR_FDZC_MASK)
9774#define CM7_MCM_ISCR_FOFC_MASK (0x400U)
9775#define CM7_MCM_ISCR_FOFC_SHIFT (10U)
9776/*! FOFC - FPU Overflow interrupt status
9777 * 0b0..No interrupt
9778 * 0b1..Interrupt occured
9779 */
9780#define CM7_MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFC_SHIFT)) & CM7_MCM_ISCR_FOFC_MASK)
9781#define CM7_MCM_ISCR_FUFC_MASK (0x800U)
9782#define CM7_MCM_ISCR_FUFC_SHIFT (11U)
9783/*! FUFC - FPU Underflow Interrupt Status
9784 * 0b0..No interrupt
9785 * 0b1..Interrupt occured
9786 */
9787#define CM7_MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFC_SHIFT)) & CM7_MCM_ISCR_FUFC_MASK)
9788#define CM7_MCM_ISCR_FIXC_MASK (0x1000U)
9789#define CM7_MCM_ISCR_FIXC_SHIFT (12U)
9790/*! FIXC - FPU Inexact Interrupt Status
9791 * 0b0..No interrupt
9792 * 0b1..Interrupt occured
9793 */
9794#define CM7_MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXC_SHIFT)) & CM7_MCM_ISCR_FIXC_MASK)
9795#define CM7_MCM_ISCR_FIDC_MASK (0x8000U)
9796#define CM7_MCM_ISCR_FIDC_SHIFT (15U)
9797/*! FIDC - FPU Input Denormal Interrupt Status
9798 * 0b0..No interrupt
9799 * 0b1..Interrupt occured
9800 */
9801#define CM7_MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDC_SHIFT)) & CM7_MCM_ISCR_FIDC_MASK)
9802#define CM7_MCM_ISCR_WABE_MASK (0x200000U)
9803#define CM7_MCM_ISCR_WABE_SHIFT (21U)
9804/*! WABE - TCM Write Abort Interrupt enable
9805 * 0b0..Disable interrupt
9806 * 0b1..Enable interrupt
9807 */
9808#define CM7_MCM_ISCR_WABE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_WABE_SHIFT)) & CM7_MCM_ISCR_WABE_MASK)
9809#define CM7_MCM_ISCR_FIOCE_MASK (0x1000000U)
9810#define CM7_MCM_ISCR_FIOCE_SHIFT (24U)
9811/*! FIOCE - FPU Invalid Operation Interrupt Enable
9812 * 0b0..Disable interrupt
9813 * 0b1..Enable interrupt
9814 */
9815#define CM7_MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIOCE_SHIFT)) & CM7_MCM_ISCR_FIOCE_MASK)
9816#define CM7_MCM_ISCR_FDZCE_MASK (0x2000000U)
9817#define CM7_MCM_ISCR_FDZCE_SHIFT (25U)
9818/*! FDZCE - FPU Divide-by-Zero Interrupt Enable
9819 * 0b0..Disable interrupt
9820 * 0b1..Enable interrupt
9821 */
9822#define CM7_MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FDZCE_SHIFT)) & CM7_MCM_ISCR_FDZCE_MASK)
9823#define CM7_MCM_ISCR_FOFCE_MASK (0x4000000U)
9824#define CM7_MCM_ISCR_FOFCE_SHIFT (26U)
9825/*! FOFCE - FPU Overflow Interrupt Enable
9826 * 0b0..Disable interrupt
9827 * 0b1..Enable interrupt
9828 */
9829#define CM7_MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FOFCE_SHIFT)) & CM7_MCM_ISCR_FOFCE_MASK)
9830#define CM7_MCM_ISCR_FUFCE_MASK (0x8000000U)
9831#define CM7_MCM_ISCR_FUFCE_SHIFT (27U)
9832/*! FUFCE - FPU Underflow Interrupt Enable
9833 * 0b0..Disable interrupt
9834 * 0b1..Enable interrupt
9835 */
9836#define CM7_MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FUFCE_SHIFT)) & CM7_MCM_ISCR_FUFCE_MASK)
9837#define CM7_MCM_ISCR_FIXCE_MASK (0x10000000U)
9838#define CM7_MCM_ISCR_FIXCE_SHIFT (28U)
9839/*! FIXCE - FPU Inexact Interrupt Enable
9840 * 0b0..Disable interrupt
9841 * 0b1..Enable interrupt
9842 */
9843#define CM7_MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIXCE_SHIFT)) & CM7_MCM_ISCR_FIXCE_MASK)
9844#define CM7_MCM_ISCR_FIDCE_MASK (0x80000000U)
9845#define CM7_MCM_ISCR_FIDCE_SHIFT (31U)
9846/*! FIDCE - FPU Input Denormal Interrupt Enable
9847 * 0b0..Disable interrupt
9848 * 0b1..Enable interrupt
9849 */
9850#define CM7_MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << CM7_MCM_ISCR_FIDCE_SHIFT)) & CM7_MCM_ISCR_FIDCE_MASK)
9851/*! @} */
9852
9853
9854/*!
9855 * @}
9856 */ /* end of group CM7_MCM_Register_Masks */
9857
9858
9859/* CM7_MCM - Peripheral instance base addresses */
9860/** Peripheral CM7_MCM base address */
9861#define CM7_MCM_BASE (0xE0080000u)
9862/** Peripheral CM7_MCM base pointer */
9863#define CM7_MCM ((CM7_MCM_Type *)CM7_MCM_BASE)
9864/** Array initializer of CM7_MCM peripheral base addresses */
9865#define CM7_MCM_BASE_ADDRS { CM7_MCM_BASE }
9866/** Array initializer of CM7_MCM peripheral base pointers */
9867#define CM7_MCM_BASE_PTRS { CM7_MCM }
9868
9869/*!
9870 * @}
9871 */ /* end of group CM7_MCM_Peripheral_Access_Layer */
9872
9873
9874/* ----------------------------------------------------------------------------
9875 -- CMP Peripheral Access Layer
9876 ---------------------------------------------------------------------------- */
9877
9878/*!
9879 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
9880 * @{
9881 */
9882
9883/** CMP - Register Layout Typedef */
9884typedef struct {
9885 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
9886 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
9887 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
9888 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
9889 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
9890 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
9891} CMP_Type;
9892
9893/* ----------------------------------------------------------------------------
9894 -- CMP Register Masks
9895 ---------------------------------------------------------------------------- */
9896
9897/*!
9898 * @addtogroup CMP_Register_Masks CMP Register Masks
9899 * @{
9900 */
9901
9902/*! @name CR0 - CMP Control Register 0 */
9903/*! @{ */
9904#define CMP_CR0_HYSTCTR_MASK (0x3U)
9905#define CMP_CR0_HYSTCTR_SHIFT (0U)
9906/*! HYSTCTR - Comparator hard block hysteresis control
9907 * 0b00..Level 0
9908 * 0b01..Level 1
9909 * 0b10..Level 2
9910 * 0b11..Level 3
9911 */
9912#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
9913#define CMP_CR0_FILTER_CNT_MASK (0x70U)
9914#define CMP_CR0_FILTER_CNT_SHIFT (4U)
9915/*! FILTER_CNT - Filter Sample Count
9916 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
9917 * 0b001..One sample must agree. The comparator output is simply sampled.
9918 * 0b010..2 consecutive samples must agree.
9919 * 0b011..3 consecutive samples must agree.
9920 * 0b100..4 consecutive samples must agree.
9921 * 0b101..5 consecutive samples must agree.
9922 * 0b110..6 consecutive samples must agree.
9923 * 0b111..7 consecutive samples must agree.
9924 */
9925#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
9926/*! @} */
9927
9928/*! @name CR1 - CMP Control Register 1 */
9929/*! @{ */
9930#define CMP_CR1_EN_MASK (0x1U)
9931#define CMP_CR1_EN_SHIFT (0U)
9932/*! EN - Comparator Module Enable
9933 * 0b0..Analog Comparator is disabled.
9934 * 0b1..Analog Comparator is enabled.
9935 */
9936#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
9937#define CMP_CR1_OPE_MASK (0x2U)
9938#define CMP_CR1_OPE_SHIFT (1U)
9939/*! OPE - Comparator Output Pin Enable
9940 * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
9941 * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the
9942 * associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this
9943 * bit has no effect.
9944 */
9945#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
9946#define CMP_CR1_COS_MASK (0x4U)
9947#define CMP_CR1_COS_SHIFT (2U)
9948/*! COS - Comparator Output Select
9949 * 0b0..Set the filtered comparator output (CMPO) to equal COUT.
9950 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
9951 */
9952#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
9953#define CMP_CR1_INV_MASK (0x8U)
9954#define CMP_CR1_INV_SHIFT (3U)
9955/*! INV - Comparator INVERT
9956 * 0b0..Does not invert the comparator output.
9957 * 0b1..Inverts the comparator output.
9958 */
9959#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
9960#define CMP_CR1_PMODE_MASK (0x10U)
9961#define CMP_CR1_PMODE_SHIFT (4U)
9962/*! PMODE - Power Mode Select
9963 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
9964 * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
9965 */
9966#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
9967#define CMP_CR1_WE_MASK (0x40U)
9968#define CMP_CR1_WE_SHIFT (6U)
9969/*! WE - Windowing Enable
9970 * 0b0..Windowing mode is not selected.
9971 * 0b1..Windowing mode is selected.
9972 */
9973#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
9974#define CMP_CR1_SE_MASK (0x80U)
9975#define CMP_CR1_SE_SHIFT (7U)
9976/*! SE - Sample Enable
9977 * 0b0..Sampling mode is not selected.
9978 * 0b1..Sampling mode is selected.
9979 */
9980#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
9981/*! @} */
9982
9983/*! @name FPR - CMP Filter Period Register */
9984/*! @{ */
9985#define CMP_FPR_FILT_PER_MASK (0xFFU)
9986#define CMP_FPR_FILT_PER_SHIFT (0U)
9987/*! FILT_PER - Filter Sample Period
9988 */
9989#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
9990/*! @} */
9991
9992/*! @name SCR - CMP Status and Control Register */
9993/*! @{ */
9994#define CMP_SCR_COUT_MASK (0x1U)
9995#define CMP_SCR_COUT_SHIFT (0U)
9996/*! COUT - Analog Comparator Output
9997 */
9998#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
9999#define CMP_SCR_CFF_MASK (0x2U)
10000#define CMP_SCR_CFF_SHIFT (1U)
10001/*! CFF - Analog Comparator Flag Falling
10002 * 0b0..Falling-edge on COUT has not been detected.
10003 * 0b1..Falling-edge on COUT has occurred.
10004 */
10005#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
10006#define CMP_SCR_CFR_MASK (0x4U)
10007#define CMP_SCR_CFR_SHIFT (2U)
10008/*! CFR - Analog Comparator Flag Rising
10009 * 0b0..Rising-edge on COUT has not been detected.
10010 * 0b1..Rising-edge on COUT has occurred.
10011 */
10012#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
10013#define CMP_SCR_IEF_MASK (0x8U)
10014#define CMP_SCR_IEF_SHIFT (3U)
10015/*! IEF - Comparator Interrupt Enable Falling
10016 * 0b0..Interrupt is disabled.
10017 * 0b1..Interrupt is enabled.
10018 */
10019#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
10020#define CMP_SCR_IER_MASK (0x10U)
10021#define CMP_SCR_IER_SHIFT (4U)
10022/*! IER - Comparator Interrupt Enable Rising
10023 * 0b0..Interrupt is disabled.
10024 * 0b1..Interrupt is enabled.
10025 */
10026#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
10027#define CMP_SCR_DMAEN_MASK (0x40U)
10028#define CMP_SCR_DMAEN_SHIFT (6U)
10029/*! DMAEN - DMA Enable Control
10030 * 0b0..DMA is disabled.
10031 * 0b1..DMA is enabled.
10032 */
10033#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
10034/*! @} */
10035
10036/*! @name DACCR - DAC Control Register */
10037/*! @{ */
10038#define CMP_DACCR_VOSEL_MASK (0x3FU)
10039#define CMP_DACCR_VOSEL_SHIFT (0U)
10040/*! VOSEL - DAC Output Voltage Select
10041 */
10042#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
10043#define CMP_DACCR_VRSEL_MASK (0x40U)
10044#define CMP_DACCR_VRSEL_SHIFT (6U)
10045/*! VRSEL - Supply Voltage Reference Source Select
10046 * 0b0..Vin1 is selected as resistor ladder network supply reference.
10047 * 0b1..Vin2 is selected as resistor ladder network supply reference.
10048 */
10049#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
10050#define CMP_DACCR_DACEN_MASK (0x80U)
10051#define CMP_DACCR_DACEN_SHIFT (7U)
10052/*! DACEN - DAC Enable
10053 * 0b0..DAC is disabled.
10054 * 0b1..DAC is enabled.
10055 */
10056#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
10057/*! @} */
10058
10059/*! @name MUXCR - MUX Control Register */
10060/*! @{ */
10061#define CMP_MUXCR_MSEL_MASK (0x7U)
10062#define CMP_MUXCR_MSEL_SHIFT (0U)
10063/*! MSEL - Minus Input Mux Control
10064 * 0b000..IN0
10065 * 0b001..IN1
10066 * 0b010..IN2
10067 * 0b011..IN3
10068 * 0b100..IN4
10069 * 0b101..IN5
10070 * 0b110..IN6
10071 * 0b111..IN7
10072 */
10073#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
10074#define CMP_MUXCR_PSEL_MASK (0x38U)
10075#define CMP_MUXCR_PSEL_SHIFT (3U)
10076/*! PSEL - Plus Input Mux Control
10077 * 0b000..IN0
10078 * 0b001..IN1
10079 * 0b010..IN2
10080 * 0b011..IN3
10081 * 0b100..IN4
10082 * 0b101..IN5
10083 * 0b110..IN6
10084 * 0b111..IN7
10085 */
10086#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
10087/*! @} */
10088
10089
10090/*!
10091 * @}
10092 */ /* end of group CMP_Register_Masks */
10093
10094
10095/* CMP - Peripheral instance base addresses */
10096/** Peripheral CMP1 base address */
10097#define CMP1_BASE (0x40094000u)
10098/** Peripheral CMP1 base pointer */
10099#define CMP1 ((CMP_Type *)CMP1_BASE)
10100/** Peripheral CMP2 base address */
10101#define CMP2_BASE (0x40094008u)
10102/** Peripheral CMP2 base pointer */
10103#define CMP2 ((CMP_Type *)CMP2_BASE)
10104/** Peripheral CMP3 base address */
10105#define CMP3_BASE (0x40094010u)
10106/** Peripheral CMP3 base pointer */
10107#define CMP3 ((CMP_Type *)CMP3_BASE)
10108/** Peripheral CMP4 base address */
10109#define CMP4_BASE (0x40094018u)
10110/** Peripheral CMP4 base pointer */
10111#define CMP4 ((CMP_Type *)CMP4_BASE)
10112/** Array initializer of CMP peripheral base addresses */
10113#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
10114/** Array initializer of CMP peripheral base pointers */
10115#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
10116/** Interrupt vectors for the CMP peripheral type */
10117#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
10118
10119/*!
10120 * @}
10121 */ /* end of group CMP_Peripheral_Access_Layer */
10122
10123
10124/* ----------------------------------------------------------------------------
10125 -- CSI Peripheral Access Layer
10126 ---------------------------------------------------------------------------- */
10127
10128/*!
10129 * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer
10130 * @{
10131 */
10132
10133/** CSI - Register Layout Typedef */
10134typedef struct {
10135 __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */
10136 __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */
10137 __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */
10138 __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */
10139 __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */
10140 __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */
10141 __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */
10142 uint8_t RESERVED_0[4];
10143 __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */
10144 __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */
10145 __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */
10146 __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */
10147 __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */
10148 __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */
10149 uint8_t RESERVED_1[16];
10150 __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */
10151 __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */
10152} CSI_Type;
10153
10154/* ----------------------------------------------------------------------------
10155 -- CSI Register Masks
10156 ---------------------------------------------------------------------------- */
10157
10158/*!
10159 * @addtogroup CSI_Register_Masks CSI Register Masks
10160 * @{
10161 */
10162
10163/*! @name CSICR1 - CSI Control Register 1 */
10164/*! @{ */
10165#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U)
10166#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U)
10167/*! PIXEL_BIT
10168 * 0b0..8-bit data for each pixel
10169 * 0b1..10-bit data for each pixel
10170 */
10171#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)
10172#define CSI_CSICR1_REDGE_MASK (0x2U)
10173#define CSI_CSICR1_REDGE_SHIFT (1U)
10174/*! REDGE
10175 * 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK
10176 * 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
10177 */
10178#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)
10179#define CSI_CSICR1_INV_PCLK_MASK (0x4U)
10180#define CSI_CSICR1_INV_PCLK_SHIFT (2U)
10181/*! INV_PCLK
10182 * 0b0..CSI_PIXCLK is directly applied to internal circuitry
10183 * 0b1..CSI_PIXCLK is inverted before applied to internal circuitry
10184 */
10185#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)
10186#define CSI_CSICR1_INV_DATA_MASK (0x8U)
10187#define CSI_CSICR1_INV_DATA_SHIFT (3U)
10188/*! INV_DATA
10189 * 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry
10190 * 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
10191 */
10192#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)
10193#define CSI_CSICR1_GCLK_MODE_MASK (0x10U)
10194#define CSI_CSICR1_GCLK_MODE_SHIFT (4U)
10195/*! GCLK_MODE
10196 * 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
10197 * 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
10198 */
10199#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)
10200#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U)
10201#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U)
10202#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK)
10203#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U)
10204#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U)
10205#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)
10206#define CSI_CSICR1_PACK_DIR_MASK (0x80U)
10207#define CSI_CSICR1_PACK_DIR_SHIFT (7U)
10208/*! PACK_DIR
10209 * 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For
10210 * stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
10211 * 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For
10212 * stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
10213 */
10214#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)
10215#define CSI_CSICR1_FCC_MASK (0x100U)
10216#define CSI_CSICR1_FCC_SHIFT (8U)
10217/*! FCC
10218 * 0b0..Asynchronous FIFO clear is selected.
10219 * 0b1..Synchronous FIFO clear is selected.
10220 */
10221#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)
10222#define CSI_CSICR1_CCIR_EN_MASK (0x400U)
10223#define CSI_CSICR1_CCIR_EN_SHIFT (10U)
10224/*! CCIR_EN
10225 * 0b0..Traditional interface is selected. Timing interface logic is used to latch data.
10226 * 0b1..CCIR656 interface is selected.
10227 */
10228#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)
10229#define CSI_CSICR1_HSYNC_POL_MASK (0x800U)
10230#define CSI_CSICR1_HSYNC_POL_SHIFT (11U)
10231/*! HSYNC_POL
10232 * 0b0..HSYNC is active low
10233 * 0b1..HSYNC is active high
10234 */
10235#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)
10236#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U)
10237#define CSI_CSICR1_SOF_INTEN_SHIFT (16U)
10238/*! SOF_INTEN
10239 * 0b0..SOF interrupt disable
10240 * 0b1..SOF interrupt enable
10241 */
10242#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)
10243#define CSI_CSICR1_SOF_POL_MASK (0x20000U)
10244#define CSI_CSICR1_SOF_POL_SHIFT (17U)
10245/*! SOF_POL
10246 * 0b0..SOF interrupt is generated on SOF falling edge
10247 * 0b1..SOF interrupt is generated on SOF rising edge
10248 */
10249#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)
10250#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U)
10251#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U)
10252/*! RXFF_INTEN
10253 * 0b0..RxFIFO full interrupt disable
10254 * 0b1..RxFIFO full interrupt enable
10255 */
10256#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)
10257#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)
10258#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U)
10259/*! FB1_DMA_DONE_INTEN
10260 * 0b0..Frame Buffer1 DMA Transfer Done interrupt disable
10261 * 0b1..Frame Buffer1 DMA Transfer Done interrupt enable
10262 */
10263#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)
10264#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)
10265#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U)
10266/*! FB2_DMA_DONE_INTEN
10267 * 0b0..Frame Buffer2 DMA Transfer Done interrupt disable
10268 * 0b1..Frame Buffer2 DMA Transfer Done interrupt enable
10269 */
10270#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)
10271#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U)
10272#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U)
10273/*! STATFF_INTEN
10274 * 0b0..STATFIFO full interrupt disable
10275 * 0b1..STATFIFO full interrupt enable
10276 */
10277#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)
10278#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)
10279#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U)
10280/*! SFF_DMA_DONE_INTEN
10281 * 0b0..STATFIFO DMA Transfer Done interrupt disable
10282 * 0b1..STATFIFO DMA Transfer Done interrupt enable
10283 */
10284#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)
10285#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U)
10286#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U)
10287/*! RF_OR_INTEN
10288 * 0b0..RxFIFO overrun interrupt is disabled
10289 * 0b1..RxFIFO overrun interrupt is enabled
10290 */
10291#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)
10292#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U)
10293#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U)
10294/*! SF_OR_INTEN
10295 * 0b0..STATFIFO overrun interrupt is disabled
10296 * 0b1..STATFIFO overrun interrupt is enabled
10297 */
10298#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK)
10299#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U)
10300#define CSI_CSICR1_COF_INT_EN_SHIFT (26U)
10301/*! COF_INT_EN
10302 * 0b0..COF interrupt is disabled
10303 * 0b1..COF interrupt is enabled
10304 */
10305#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK)
10306#define CSI_CSICR1_CCIR_MODE_MASK (0x8000000U)
10307#define CSI_CSICR1_CCIR_MODE_SHIFT (27U)
10308/*! CCIR_MODE
10309 * 0b0..Progressive mode is selected
10310 * 0b1..Interlace mode is selected
10311 */
10312#define CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK)
10313#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U)
10314#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U)
10315/*! PrP_IF_EN
10316 * 0b0..CSI to PrP bus is disabled
10317 * 0b1..CSI to PrP bus is enabled
10318 */
10319#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK)
10320#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U)
10321#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U)
10322/*! EOF_INT_EN
10323 * 0b0..EOF interrupt is disabled.
10324 * 0b1..EOF interrupt is generated when RX count value is reached.
10325 */
10326#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK)
10327#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U)
10328#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U)
10329/*! EXT_VSYNC
10330 * 0b0..Internal VSYNC mode
10331 * 0b1..External VSYNC mode
10332 */
10333#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK)
10334#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U)
10335#define CSI_CSICR1_SWAP16_EN_SHIFT (31U)
10336/*! SWAP16_EN
10337 * 0b0..Disable swapping
10338 * 0b1..Enable swapping
10339 */
10340#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK)
10341/*! @} */
10342
10343/*! @name CSICR2 - CSI Control Register 2 */
10344/*! @{ */
10345#define CSI_CSICR2_HSC_MASK (0xFFU)
10346#define CSI_CSICR2_HSC_SHIFT (0U)
10347#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK)
10348#define CSI_CSICR2_VSC_MASK (0xFF00U)
10349#define CSI_CSICR2_VSC_SHIFT (8U)
10350#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK)
10351#define CSI_CSICR2_LVRM_MASK (0x70000U)
10352#define CSI_CSICR2_LVRM_SHIFT (16U)
10353/*! LVRM
10354 * 0b000..512 x 384
10355 * 0b001..448 x 336
10356 * 0b010..384 x 288
10357 * 0b011..384 x 256
10358 * 0b100..320 x 240
10359 * 0b101..288 x 216
10360 * 0b110..400 x 300
10361 */
10362#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK)
10363#define CSI_CSICR2_BTS_MASK (0x180000U)
10364#define CSI_CSICR2_BTS_SHIFT (19U)
10365/*! BTS
10366 * 0b00..GR
10367 * 0b01..RG
10368 * 0b10..BG
10369 * 0b11..GB
10370 */
10371#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK)
10372#define CSI_CSICR2_SCE_MASK (0x800000U)
10373#define CSI_CSICR2_SCE_SHIFT (23U)
10374/*! SCE
10375 * 0b0..Skip count disable
10376 * 0b1..Skip count enable
10377 */
10378#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK)
10379#define CSI_CSICR2_AFS_MASK (0x3000000U)
10380#define CSI_CSICR2_AFS_SHIFT (24U)
10381/*! AFS
10382 * 0b00..Abs Diff on consecutive green pixels
10383 * 0b01..Abs Diff on every third green pixels
10384 * 0b1x..Abs Diff on every four green pixels
10385 */
10386#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK)
10387#define CSI_CSICR2_DRM_MASK (0x4000000U)
10388#define CSI_CSICR2_DRM_SHIFT (26U)
10389/*! DRM
10390 * 0b0..Stats grid of 8 x 6
10391 * 0b1..Stats grid of 8 x 12
10392 */
10393#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK)
10394#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U)
10395#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U)
10396/*! DMA_BURST_TYPE_SFF
10397 * 0bx0..INCR8
10398 * 0b01..INCR4
10399 * 0b11..INCR16
10400 */
10401#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)
10402#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U)
10403#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U)
10404/*! DMA_BURST_TYPE_RFF
10405 * 0bx0..INCR8
10406 * 0b01..INCR4
10407 * 0b11..INCR16
10408 */
10409#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)
10410/*! @} */
10411
10412/*! @name CSICR3 - CSI Control Register 3 */
10413/*! @{ */
10414#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U)
10415#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U)
10416/*! ECC_AUTO_EN
10417 * 0b0..Auto Error correction is disabled.
10418 * 0b1..Auto Error correction is enabled.
10419 */
10420#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK)
10421#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U)
10422#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U)
10423/*! ECC_INT_EN
10424 * 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
10425 * 0b1..Interrupt is generated when error is detected.
10426 */
10427#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK)
10428#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U)
10429#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U)
10430/*! ZERO_PACK_EN
10431 * 0b0..Zero packing disabled
10432 * 0b1..Zero packing enabled
10433 */
10434#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK)
10435#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U)
10436#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U)
10437/*! TWO_8BIT_SENSOR
10438 * 0b0..Only one sensor is connected.
10439 * 0b1..Two 8-bit sensors are connected or one 16-bit sensor is connected.
10440 */
10441#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK)
10442#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U)
10443#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U)
10444/*! RxFF_LEVEL
10445 * 0b000..4 Double words
10446 * 0b001..8 Double words
10447 * 0b010..16 Double words
10448 * 0b011..24 Double words
10449 * 0b100..32 Double words
10450 * 0b101..48 Double words
10451 * 0b110..64 Double words
10452 * 0b111..96 Double words
10453 */
10454#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK)
10455#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U)
10456#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U)
10457/*! HRESP_ERR_EN
10458 * 0b0..Disable hresponse error interrupt
10459 * 0b1..Enable hresponse error interrupt
10460 */
10461#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK)
10462#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U)
10463#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U)
10464/*! STATFF_LEVEL
10465 * 0b000..4 Double words
10466 * 0b001..8 Double words
10467 * 0b010..12 Double words
10468 * 0b011..16 Double words
10469 * 0b100..24 Double words
10470 * 0b101..32 Double words
10471 * 0b110..48 Double words
10472 * 0b111..64 Double words
10473 */
10474#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK)
10475#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U)
10476#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U)
10477/*! DMA_REQ_EN_SFF
10478 * 0b0..Disable the dma request
10479 * 0b1..Enable the dma request
10480 */
10481#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK)
10482#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U)
10483#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U)
10484/*! DMA_REQ_EN_RFF
10485 * 0b0..Disable the dma request
10486 * 0b1..Enable the dma request
10487 */
10488#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK)
10489#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U)
10490#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U)
10491/*! DMA_REFLASH_SFF
10492 * 0b0..No reflashing
10493 * 0b1..Reflash the embedded DMA controller
10494 */
10495#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK)
10496#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U)
10497#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U)
10498/*! DMA_REFLASH_RFF
10499 * 0b0..No reflashing
10500 * 0b1..Reflash the embedded DMA controller
10501 */
10502#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK)
10503#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U)
10504#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U)
10505/*! FRMCNT_RST
10506 * 0b0..Do not reset
10507 * 0b1..Reset frame counter immediately
10508 */
10509#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK)
10510#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U)
10511#define CSI_CSICR3_FRMCNT_SHIFT (16U)
10512#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK)
10513/*! @} */
10514
10515/*! @name CSISTATFIFO - CSI Statistic FIFO Register */
10516/*! @{ */
10517#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU)
10518#define CSI_CSISTATFIFO_STAT_SHIFT (0U)
10519#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK)
10520/*! @} */
10521
10522/*! @name CSIRFIFO - CSI RX FIFO Register */
10523/*! @{ */
10524#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU)
10525#define CSI_CSIRFIFO_IMAGE_SHIFT (0U)
10526#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK)
10527/*! @} */
10528
10529/*! @name CSIRXCNT - CSI RX Count Register */
10530/*! @{ */
10531#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU)
10532#define CSI_CSIRXCNT_RXCNT_SHIFT (0U)
10533#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK)
10534/*! @} */
10535
10536/*! @name CSISR - CSI Status Register */
10537/*! @{ */
10538#define CSI_CSISR_DRDY_MASK (0x1U)
10539#define CSI_CSISR_DRDY_SHIFT (0U)
10540/*! DRDY
10541 * 0b0..No data (word) is ready
10542 * 0b1..At least 1 datum (word) is ready in RXFIFO.
10543 */
10544#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK)
10545#define CSI_CSISR_ECC_INT_MASK (0x2U)
10546#define CSI_CSISR_ECC_INT_SHIFT (1U)
10547/*! ECC_INT
10548 * 0b0..No error detected
10549 * 0b1..Error is detected in CCIR coding
10550 */
10551#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK)
10552#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U)
10553#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U)
10554/*! HRESP_ERR_INT
10555 * 0b0..No hresponse error.
10556 * 0b1..Hresponse error is detected.
10557 */
10558#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK)
10559#define CSI_CSISR_COF_INT_MASK (0x2000U)
10560#define CSI_CSISR_COF_INT_SHIFT (13U)
10561/*! COF_INT
10562 * 0b0..Video field has no change.
10563 * 0b1..Change of video field is detected.
10564 */
10565#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK)
10566#define CSI_CSISR_F1_INT_MASK (0x4000U)
10567#define CSI_CSISR_F1_INT_SHIFT (14U)
10568/*! F1_INT
10569 * 0b0..Field 1 of video is not detected.
10570 * 0b1..Field 1 of video is about to start.
10571 */
10572#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK)
10573#define CSI_CSISR_F2_INT_MASK (0x8000U)
10574#define CSI_CSISR_F2_INT_SHIFT (15U)
10575/*! F2_INT
10576 * 0b0..Field 2 of video is not detected
10577 * 0b1..Field 2 of video is about to start
10578 */
10579#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK)
10580#define CSI_CSISR_SOF_INT_MASK (0x10000U)
10581#define CSI_CSISR_SOF_INT_SHIFT (16U)
10582/*! SOF_INT
10583 * 0b0..SOF is not detected.
10584 * 0b1..SOF is detected.
10585 */
10586#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK)
10587#define CSI_CSISR_EOF_INT_MASK (0x20000U)
10588#define CSI_CSISR_EOF_INT_SHIFT (17U)
10589/*! EOF_INT
10590 * 0b0..EOF is not detected.
10591 * 0b1..EOF is detected.
10592 */
10593#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)
10594#define CSI_CSISR_RxFF_INT_MASK (0x40000U)
10595#define CSI_CSISR_RxFF_INT_SHIFT (18U)
10596/*! RxFF_INT
10597 * 0b0..RxFIFO is not full.
10598 * 0b1..RxFIFO is full.
10599 */
10600#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)
10601#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U)
10602#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U)
10603/*! DMA_TSF_DONE_FB1
10604 * 0b0..DMA transfer is not completed.
10605 * 0b1..DMA transfer is completed.
10606 */
10607#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
10608#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U)
10609#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U)
10610/*! DMA_TSF_DONE_FB2
10611 * 0b0..DMA transfer is not completed.
10612 * 0b1..DMA transfer is completed.
10613 */
10614#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)
10615#define CSI_CSISR_STATFF_INT_MASK (0x200000U)
10616#define CSI_CSISR_STATFF_INT_SHIFT (21U)
10617/*! STATFF_INT
10618 * 0b0..STATFIFO is not full.
10619 * 0b1..STATFIFO is full.
10620 */
10621#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)
10622#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U)
10623#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U)
10624/*! DMA_TSF_DONE_SFF
10625 * 0b0..DMA transfer is not completed.
10626 * 0b1..DMA transfer is completed.
10627 */
10628#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)
10629#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U)
10630#define CSI_CSISR_RF_OR_INT_SHIFT (24U)
10631/*! RF_OR_INT
10632 * 0b0..RXFIFO has not overflowed.
10633 * 0b1..RXFIFO has overflowed.
10634 */
10635#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)
10636#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U)
10637#define CSI_CSISR_SF_OR_INT_SHIFT (25U)
10638/*! SF_OR_INT
10639 * 0b0..STATFIFO has not overflowed.
10640 * 0b1..STATFIFO has overflowed.
10641 */
10642#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)
10643#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U)
10644#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U)
10645#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK)
10646#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U)
10647#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U)
10648#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK)
10649#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)
10650#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)
10651#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK)
10652/*! @} */
10653
10654/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */
10655/*! @{ */
10656#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
10657#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
10658#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
10659/*! @} */
10660
10661/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */
10662/*! @{ */
10663#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
10664#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
10665#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
10666/*! @} */
10667
10668/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */
10669/*! @{ */
10670#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)
10671#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)
10672#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)
10673/*! @} */
10674
10675/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */
10676/*! @{ */
10677#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)
10678#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)
10679#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)
10680/*! @} */
10681
10682/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */
10683/*! @{ */
10684#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)
10685#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U)
10686#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)
10687#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)
10688#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)
10689#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)
10690/*! @} */
10691
10692/*! @name CSIIMAG_PARA - CSI Image Parameter Register */
10693/*! @{ */
10694#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)
10695#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)
10696#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)
10697#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)
10698#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U)
10699#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)
10700/*! @} */
10701
10702/*! @name CSICR18 - CSI Control Register 18 */
10703/*! @{ */
10704#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U)
10705#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U)
10706/*! DEINTERLACE_EN
10707 * 0b0..Deinterlace disabled
10708 * 0b1..Deinterlace enabled
10709 */
10710#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)
10711#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U)
10712#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U)
10713#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK)
10714#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U)
10715#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U)
10716#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)
10717#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U)
10718#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U)
10719/*! BASEADDR_SWITCH_SEL
10720 * 0b0..Switching base address at the edge of the vsync
10721 * 0b1..Switching base address at the edge of the first data of each frame
10722 */
10723#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)
10724#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U)
10725#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U)
10726/*! FIELD0_DONE_IE
10727 * 0b0..Interrupt disabled
10728 * 0b1..Interrupt enabled
10729 */
10730#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)
10731#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U)
10732#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U)
10733/*! DMA_FIELD1_DONE_IE
10734 * 0b0..Interrupt disabled
10735 * 0b1..Interrupt enabled
10736 */
10737#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)
10738#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U)
10739#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U)
10740/*! LAST_DMA_REQ_SEL
10741 * 0b0..fifo_full_level
10742 * 0b1..hburst_length
10743 */
10744#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)
10745#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
10746#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
10747#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)
10748#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U)
10749#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U)
10750/*! RGB888A_FORMAT_SEL
10751 * 0b0..{8'h0, data[23:0]}
10752 * 0b1..{data[23:0], 8'h0}
10753 */
10754#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)
10755#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U)
10756#define CSI_CSICR18_AHB_HPROT_SHIFT (12U)
10757#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)
10758#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U)
10759#define CSI_CSICR18_MASK_OPTION_SHIFT (18U)
10760/*! MASK_OPTION
10761 * 0b00..Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1.
10762 * 0b01..Writing to memory when CSI_ENABLE is 1.
10763 * 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1.
10764 * 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
10765 */
10766#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)
10767#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U)
10768#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U)
10769#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK)
10770/*! @} */
10771
10772/*! @name CSICR19 - CSI Control Register 19 */
10773/*! @{ */
10774#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
10775#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
10776#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
10777/*! @} */
10778
10779
10780/*!
10781 * @}
10782 */ /* end of group CSI_Register_Masks */
10783
10784
10785/* CSI - Peripheral instance base addresses */
10786/** Peripheral CSI base address */
10787#define CSI_BASE (0x402BC000u)
10788/** Peripheral CSI base pointer */
10789#define CSI ((CSI_Type *)CSI_BASE)
10790/** Array initializer of CSI peripheral base addresses */
10791#define CSI_BASE_ADDRS { CSI_BASE }
10792/** Array initializer of CSI peripheral base pointers */
10793#define CSI_BASE_PTRS { CSI }
10794/** Interrupt vectors for the CSI peripheral type */
10795#define CSI_IRQS { CSI_IRQn }
10796
10797/*!
10798 * @}
10799 */ /* end of group CSI_Peripheral_Access_Layer */
10800
10801
10802/* ----------------------------------------------------------------------------
10803 -- CSU Peripheral Access Layer
10804 ---------------------------------------------------------------------------- */
10805
10806/*!
10807 * @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer
10808 * @{
10809 */
10810
10811/** CSU - Register Layout Typedef */
10812typedef struct {
10813 __IO uint32_t CSL[32]; /**< Config security level register, array offset: 0x0, array step: 0x4 */
10814 uint8_t RESERVED_0[384];
10815 __IO uint32_t HP0; /**< HP0 register, offset: 0x200 */
10816 uint8_t RESERVED_1[20];
10817 __IO uint32_t SA; /**< Secure access register, offset: 0x218 */
10818 uint8_t RESERVED_2[316];
10819 __IO uint32_t HPCONTROL0; /**< HPCONTROL0 register, offset: 0x358 */
10820} CSU_Type;
10821
10822/* ----------------------------------------------------------------------------
10823 -- CSU Register Masks
10824 ---------------------------------------------------------------------------- */
10825
10826/*!
10827 * @addtogroup CSU_Register_Masks CSU Register Masks
10828 * @{
10829 */
10830
10831/*! @name CSL - Config security level register */
10832/*! @{ */
10833#define CSU_CSL_SUR_S2_MASK (0x1U)
10834#define CSU_CSL_SUR_S2_SHIFT (0U)
10835/*! SUR_S2
10836 * 0b0..The secure user read access is disabled for the second slave.
10837 * 0b1..The secure user read access is enabled for the second slave.
10838 */
10839#define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
10840#define CSU_CSL_SSR_S2_MASK (0x2U)
10841#define CSU_CSL_SSR_S2_SHIFT (1U)
10842/*! SSR_S2
10843 * 0b0..The secure supervisor read access is disabled for the second slave.
10844 * 0b1..The secure supervisor read access is enabled for the second slave.
10845 */
10846#define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
10847#define CSU_CSL_NUR_S2_MASK (0x4U)
10848#define CSU_CSL_NUR_S2_SHIFT (2U)
10849/*! NUR_S2
10850 * 0b0..The non-secure user read access is disabled for the second slave.
10851 * 0b1..The non-secure user read access is enabled for the second slave.
10852 */
10853#define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
10854#define CSU_CSL_NSR_S2_MASK (0x8U)
10855#define CSU_CSL_NSR_S2_SHIFT (3U)
10856/*! NSR_S2
10857 * 0b0..The non-secure supervisor read access is disabled for the second slave.
10858 * 0b1..The non-secure supervisor read access is enabled for the second slave.
10859 */
10860#define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
10861#define CSU_CSL_SUW_S2_MASK (0x10U)
10862#define CSU_CSL_SUW_S2_SHIFT (4U)
10863/*! SUW_S2
10864 * 0b0..The secure user write access is disabled for the second slave.
10865 * 0b1..The secure user write access is enabled for the second slave.
10866 */
10867#define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
10868#define CSU_CSL_SSW_S2_MASK (0x20U)
10869#define CSU_CSL_SSW_S2_SHIFT (5U)
10870/*! SSW_S2
10871 * 0b0..The secure supervisor write access is disabled for the second slave.
10872 * 0b1..The secure supervisor write access is enabled for the second slave.
10873 */
10874#define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
10875#define CSU_CSL_NUW_S2_MASK (0x40U)
10876#define CSU_CSL_NUW_S2_SHIFT (6U)
10877/*! NUW_S2
10878 * 0b0..The non-secure user write access is disabled for the second slave.
10879 * 0b1..The non-secure user write access is enabled for the second slave.
10880 */
10881#define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
10882#define CSU_CSL_NSW_S2_MASK (0x80U)
10883#define CSU_CSL_NSW_S2_SHIFT (7U)
10884/*! NSW_S2
10885 * 0b0..The non-secure supervisor write access is disabled for the second slave.
10886 * 0b1..The non-secure supervisor write access is enabled for the second slave.
10887 */
10888#define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
10889#define CSU_CSL_LOCK_S2_MASK (0x100U)
10890#define CSU_CSL_LOCK_S2_SHIFT (8U)
10891/*! LOCK_S2
10892 * 0b0..Not locked. Bits 7-0 can be written by the software.
10893 * 0b1..Bits 7-0 are locked and cannot be written by the software
10894 */
10895#define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
10896#define CSU_CSL_SUR_S1_MASK (0x10000U)
10897#define CSU_CSL_SUR_S1_SHIFT (16U)
10898/*! SUR_S1
10899 * 0b0..The secure user read access is disabled for the first slave.
10900 * 0b1..The secure user read access is enabled for the first slave.
10901 */
10902#define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
10903#define CSU_CSL_SSR_S1_MASK (0x20000U)
10904#define CSU_CSL_SSR_S1_SHIFT (17U)
10905/*! SSR_S1
10906 * 0b0..The secure supervisor read access is disabled for the first slave.
10907 * 0b1..The secure supervisor read access is enabled for the first slave.
10908 */
10909#define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
10910#define CSU_CSL_NUR_S1_MASK (0x40000U)
10911#define CSU_CSL_NUR_S1_SHIFT (18U)
10912/*! NUR_S1
10913 * 0b0..The non-secure user read access is disabled for the first slave.
10914 * 0b1..The non-secure user read access is enabled for the first slave.
10915 */
10916#define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
10917#define CSU_CSL_NSR_S1_MASK (0x80000U)
10918#define CSU_CSL_NSR_S1_SHIFT (19U)
10919/*! NSR_S1
10920 * 0b0..The non-secure supervisor read access is disabled for the first slave.
10921 * 0b1..The non-secure supervisor read access is enabled for the first slave.
10922 */
10923#define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
10924#define CSU_CSL_SUW_S1_MASK (0x100000U)
10925#define CSU_CSL_SUW_S1_SHIFT (20U)
10926/*! SUW_S1
10927 * 0b0..The secure user write access is disabled for the first slave.
10928 * 0b1..The secure user write access is enabled for the first slave.
10929 */
10930#define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
10931#define CSU_CSL_SSW_S1_MASK (0x200000U)
10932#define CSU_CSL_SSW_S1_SHIFT (21U)
10933/*! SSW_S1
10934 * 0b0..The secure supervisor write access is disabled for the first slave.
10935 * 0b1..The secure supervisor write access is enabled for the first slave.
10936 */
10937#define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
10938#define CSU_CSL_NUW_S1_MASK (0x400000U)
10939#define CSU_CSL_NUW_S1_SHIFT (22U)
10940/*! NUW_S1
10941 * 0b0..The non-secure user write access is disabled for the first slave.
10942 * 0b1..The non-secure user write access is enabled for the first slave.
10943 */
10944#define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
10945#define CSU_CSL_NSW_S1_MASK (0x800000U)
10946#define CSU_CSL_NSW_S1_SHIFT (23U)
10947/*! NSW_S1
10948 * 0b0..The non-secure supervisor write access is disabled for the first slave.
10949 * 0b1..The non-secure supervisor write access is enabled for the first slave
10950 */
10951#define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
10952#define CSU_CSL_LOCK_S1_MASK (0x1000000U)
10953#define CSU_CSL_LOCK_S1_SHIFT (24U)
10954/*! LOCK_S1
10955 * 0b0..Not locked. The bits 16-23 can be written by the software.
10956 * 0b1..The bits 16-23 are locked and can't be written by the software.
10957 */
10958#define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
10959/*! @} */
10960
10961/* The count of CSU_CSL */
10962#define CSU_CSL_COUNT (32U)
10963
10964/*! @name HP0 - HP0 register */
10965/*! @{ */
10966#define CSU_HP0_HP_DMA_MASK (0x4U)
10967#define CSU_HP0_HP_DMA_SHIFT (2U)
10968/*! HP_DMA
10969 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
10970 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
10971 */
10972#define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
10973#define CSU_HP0_L_DMA_MASK (0x8U)
10974#define CSU_HP0_L_DMA_SHIFT (3U)
10975/*! L_DMA
10976 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
10977 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
10978 */
10979#define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
10980#define CSU_HP0_HP_LCDIF_MASK (0x10U)
10981#define CSU_HP0_HP_LCDIF_SHIFT (4U)
10982/*! HP_LCDIF
10983 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
10984 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
10985 */
10986#define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
10987#define CSU_HP0_L_LCDIF_MASK (0x20U)
10988#define CSU_HP0_L_LCDIF_SHIFT (5U)
10989/*! L_LCDIF
10990 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
10991 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
10992 */
10993#define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
10994#define CSU_HP0_HP_CSI_MASK (0x40U)
10995#define CSU_HP0_HP_CSI_SHIFT (6U)
10996/*! HP_CSI
10997 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
10998 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
10999 */
11000#define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
11001#define CSU_HP0_L_CSI_MASK (0x80U)
11002#define CSU_HP0_L_CSI_SHIFT (7U)
11003/*! L_CSI
11004 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11005 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11006 */
11007#define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
11008#define CSU_HP0_HP_PXP_MASK (0x100U)
11009#define CSU_HP0_HP_PXP_SHIFT (8U)
11010/*! HP_PXP
11011 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11012 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11013 */
11014#define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
11015#define CSU_HP0_L_PXP_MASK (0x200U)
11016#define CSU_HP0_L_PXP_SHIFT (9U)
11017/*! L_PXP
11018 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11019 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11020 */
11021#define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
11022#define CSU_HP0_HP_DCP_MASK (0x400U)
11023#define CSU_HP0_HP_DCP_SHIFT (10U)
11024/*! HP_DCP
11025 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11026 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11027 */
11028#define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
11029#define CSU_HP0_L_DCP_MASK (0x800U)
11030#define CSU_HP0_L_DCP_SHIFT (11U)
11031/*! L_DCP
11032 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11033 * 0b1..Lock-the adjacent (next lower) bit cannot be written by the software.
11034 */
11035#define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
11036#define CSU_HP0_HP_ENET_MASK (0x4000U)
11037#define CSU_HP0_HP_ENET_SHIFT (14U)
11038/*! HP_ENET
11039 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11040 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11041 */
11042#define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
11043#define CSU_HP0_L_ENET_MASK (0x8000U)
11044#define CSU_HP0_L_ENET_SHIFT (15U)
11045/*! L_ENET
11046 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11047 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11048 */
11049#define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
11050#define CSU_HP0_HP_USDHC1_MASK (0x10000U)
11051#define CSU_HP0_HP_USDHC1_SHIFT (16U)
11052/*! HP_USDHC1
11053 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11054 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11055 */
11056#define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
11057#define CSU_HP0_L_USDHC1_MASK (0x20000U)
11058#define CSU_HP0_L_USDHC1_SHIFT (17U)
11059/*! L_USDHC1
11060 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11061 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11062 */
11063#define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
11064#define CSU_HP0_HP_USDHC2_MASK (0x40000U)
11065#define CSU_HP0_HP_USDHC2_SHIFT (18U)
11066/*! HP_USDHC2
11067 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11068 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11069 */
11070#define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
11071#define CSU_HP0_L_USDHC2_MASK (0x80000U)
11072#define CSU_HP0_L_USDHC2_SHIFT (19U)
11073/*! L_USDHC2
11074 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11075 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11076 */
11077#define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
11078#define CSU_HP0_HP_TPSMP_MASK (0x100000U)
11079#define CSU_HP0_HP_TPSMP_SHIFT (20U)
11080/*! HP_TPSMP
11081 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11082 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11083 */
11084#define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
11085#define CSU_HP0_L_TPSMP_MASK (0x200000U)
11086#define CSU_HP0_L_TPSMP_SHIFT (21U)
11087/*! L_TPSMP
11088 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11089 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11090 */
11091#define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
11092#define CSU_HP0_HP_USB_MASK (0x400000U)
11093#define CSU_HP0_HP_USB_SHIFT (22U)
11094/*! HP_USB
11095 * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
11096 * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
11097 */
11098#define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
11099#define CSU_HP0_L_USB_MASK (0x800000U)
11100#define CSU_HP0_L_USB_SHIFT (23U)
11101/*! L_USB
11102 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11103 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11104 */
11105#define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
11106/*! @} */
11107
11108/*! @name SA - Secure access register */
11109/*! @{ */
11110#define CSU_SA_NSA_DMA_MASK (0x4U)
11111#define CSU_SA_NSA_DMA_SHIFT (2U)
11112/*! NSA_DMA - Non-secure access policy indicator bit
11113 * 0b0..Secure access for the corresponding type-1 master
11114 * 0b1..Non-secure access for the corresponding type-1 master
11115 */
11116#define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
11117#define CSU_SA_L_DMA_MASK (0x8U)
11118#define CSU_SA_L_DMA_SHIFT (3U)
11119/*! L_DMA
11120 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11121 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11122 */
11123#define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
11124#define CSU_SA_NSA_LCDIF_MASK (0x10U)
11125#define CSU_SA_NSA_LCDIF_SHIFT (4U)
11126/*! NSA_LCDIF - Non-secure access policy indicator bit
11127 * 0b0..Secure access for the corresponding type-1 master
11128 * 0b1..Non-secure access for the corresponding type-1 master
11129 */
11130#define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
11131#define CSU_SA_L_LCDIF_MASK (0x20U)
11132#define CSU_SA_L_LCDIF_SHIFT (5U)
11133/*! L_LCDIF
11134 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11135 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11136 */
11137#define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
11138#define CSU_SA_NSA_CSI_MASK (0x40U)
11139#define CSU_SA_NSA_CSI_SHIFT (6U)
11140/*! NSA_CSI - Non-secure access policy indicator bit
11141 * 0b0..Secure access for the corresponding type-1 master
11142 * 0b1..Non-secure access for the corresponding type-1 master
11143 */
11144#define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
11145#define CSU_SA_L_CSI_MASK (0x80U)
11146#define CSU_SA_L_CSI_SHIFT (7U)
11147/*! L_CSI
11148 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11149 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11150 */
11151#define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
11152#define CSU_SA_NSA_PXP_MASK (0x100U)
11153#define CSU_SA_NSA_PXP_SHIFT (8U)
11154/*! NSA_PXP - Non-Secure Access Policy indicator bit
11155 * 0b0..Secure access for the corresponding type-1 master
11156 * 0b1..Non-secure access for the corresponding type-1 master
11157 */
11158#define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
11159#define CSU_SA_L_PXP_MASK (0x200U)
11160#define CSU_SA_L_PXP_SHIFT (9U)
11161/*! L_PXP
11162 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11163 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11164 */
11165#define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
11166#define CSU_SA_NSA_DCP_MASK (0x400U)
11167#define CSU_SA_NSA_DCP_SHIFT (10U)
11168/*! NSA_DCP - Non-secure access policy indicator bit
11169 * 0b0..Secure access for the corresponding type-1 master
11170 * 0b1..Non-secure access for the corresponding type-1 master
11171 */
11172#define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
11173#define CSU_SA_L_DCP_MASK (0x800U)
11174#define CSU_SA_L_DCP_SHIFT (11U)
11175/*! L_DCP
11176 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11177 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11178 */
11179#define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
11180#define CSU_SA_NSA_ENET_MASK (0x4000U)
11181#define CSU_SA_NSA_ENET_SHIFT (14U)
11182/*! NSA_ENET - Non-secure access policy indicator bit
11183 * 0b0..Secure access for the corresponding type-1 master
11184 * 0b1..Non-secure access for the corresponding type-1 master
11185 */
11186#define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
11187#define CSU_SA_L_ENET_MASK (0x8000U)
11188#define CSU_SA_L_ENET_SHIFT (15U)
11189/*! L_ENET
11190 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11191 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11192 */
11193#define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
11194#define CSU_SA_NSA_USDHC1_MASK (0x10000U)
11195#define CSU_SA_NSA_USDHC1_SHIFT (16U)
11196/*! NSA_USDHC1 - Non-secure access policy indicator bit
11197 * 0b0..Secure access for the corresponding type-1 master
11198 * 0b1..Non-secure access for the corresponding type-1 master
11199 */
11200#define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
11201#define CSU_SA_L_USDHC1_MASK (0x20000U)
11202#define CSU_SA_L_USDHC1_SHIFT (17U)
11203/*! L_USDHC1
11204 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11205 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11206 */
11207#define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
11208#define CSU_SA_NSA_USDHC2_MASK (0x40000U)
11209#define CSU_SA_NSA_USDHC2_SHIFT (18U)
11210/*! NSA_USDHC2 - Non-secure access policy indicator bit
11211 * 0b0..Secure access for the corresponding type-1 master
11212 * 0b1..Non-secure access for the corresponding type-1 master
11213 */
11214#define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
11215#define CSU_SA_L_USDHC2_MASK (0x80000U)
11216#define CSU_SA_L_USDHC2_SHIFT (19U)
11217/*! L_USDHC2
11218 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11219 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11220 */
11221#define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
11222#define CSU_SA_NSA_TPSMP_MASK (0x100000U)
11223#define CSU_SA_NSA_TPSMP_SHIFT (20U)
11224/*! NSA_TPSMP - Non-secure access policy indicator bit
11225 * 0b0..Secure access for the corresponding type-1 master
11226 * 0b1..Non-secure access for the corresponding type-1 master
11227 */
11228#define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
11229#define CSU_SA_L_TPSMP_MASK (0x200000U)
11230#define CSU_SA_L_TPSMP_SHIFT (21U)
11231/*! L_TPSMP
11232 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11233 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11234 */
11235#define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
11236#define CSU_SA_NSA_USB_MASK (0x400000U)
11237#define CSU_SA_NSA_USB_SHIFT (22U)
11238/*! NSA_USB - Non-secure access policy indicator bit
11239 * 0b0..Secure access for the corresponding type-1 master
11240 * 0b1..Non-secure access for the corresponding type-1 master
11241 */
11242#define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
11243#define CSU_SA_L_USB_MASK (0x800000U)
11244#define CSU_SA_L_USB_SHIFT (23U)
11245/*! L_USB
11246 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11247 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11248 */
11249#define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
11250/*! @} */
11251
11252/*! @name HPCONTROL0 - HPCONTROL0 register */
11253/*! @{ */
11254#define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)
11255#define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)
11256/*! HPC_DMA
11257 * 0b0..User mode for the corresponding master
11258 * 0b1..Supervisor mode for the corresponding master
11259 */
11260#define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
11261#define CSU_HPCONTROL0_L_DMA_MASK (0x8U)
11262#define CSU_HPCONTROL0_L_DMA_SHIFT (3U)
11263/*! L_DMA
11264 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11265 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11266 */
11267#define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
11268#define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)
11269#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)
11270/*! HPC_LCDIF
11271 * 0b0..User mode for the corresponding master
11272 * 0b1..Supervisor mode for the corresponding master
11273 */
11274#define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
11275#define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)
11276#define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)
11277/*! L_LCDIF
11278 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11279 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11280 */
11281#define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
11282#define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)
11283#define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)
11284/*! HPC_CSI
11285 * 0b0..User mode for the corresponding master
11286 * 0b1..Supervisor mode for the corresponding master
11287 */
11288#define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
11289#define CSU_HPCONTROL0_L_CSI_MASK (0x80U)
11290#define CSU_HPCONTROL0_L_CSI_SHIFT (7U)
11291/*! L_CSI
11292 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11293 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11294 */
11295#define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
11296#define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)
11297#define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)
11298/*! HPC_PXP
11299 * 0b0..User mode for the corresponding master
11300 * 0b1..Supervisor mode for the corresponding master
11301 */
11302#define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
11303#define CSU_HPCONTROL0_L_PXP_MASK (0x200U)
11304#define CSU_HPCONTROL0_L_PXP_SHIFT (9U)
11305/*! L_PXP
11306 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11307 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11308 */
11309#define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
11310#define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)
11311#define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)
11312/*! HPC_DCP
11313 * 0b0..User mode for the corresponding master
11314 * 0b1..Supervisor mode for the corresponding master
11315 */
11316#define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
11317#define CSU_HPCONTROL0_L_DCP_MASK (0x800U)
11318#define CSU_HPCONTROL0_L_DCP_SHIFT (11U)
11319/*! L_DCP
11320 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11321 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11322 */
11323#define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
11324#define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)
11325#define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)
11326/*! HPC_ENET
11327 * 0b0..User mode for the corresponding master
11328 * 0b1..Supervisor mode for the corresponding master
11329 */
11330#define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
11331#define CSU_HPCONTROL0_L_ENET_MASK (0x8000U)
11332#define CSU_HPCONTROL0_L_ENET_SHIFT (15U)
11333/*! L_ENET
11334 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11335 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11336 */
11337#define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
11338#define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)
11339#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)
11340/*! HPC_USDHC1
11341 * 0b0..User mode for the corresponding master
11342 * 0b1..Supervisor mode for the corresponding master
11343 */
11344#define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
11345#define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)
11346#define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)
11347/*! L_USDHC1
11348 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11349 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11350 */
11351#define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
11352#define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)
11353#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)
11354/*! HPC_USDHC2
11355 * 0b0..User mode for the corresponding master
11356 * 0b1..Supervisor mode for the corresponding master
11357 */
11358#define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
11359#define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)
11360#define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)
11361/*! L_USDHC2
11362 * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
11363 * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
11364 */
11365#define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
11366#define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)
11367#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)
11368/*! HPC_TPSMP
11369 * 0b0..User mode for the corresponding master
11370 * 0b1..Supervisor mode for the corresponding master
11371 */
11372#define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
11373#define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)
11374#define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)
11375/*! L_TPSMP