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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1062/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1062/drivers/fsl_clock.h
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index 000000000..04682a007
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+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1062/drivers/fsl_clock.h
@@ -0,0 +1,1764 @@
1/*
2 * Copyright 2018 - 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_CLOCK_H_
9#define _FSL_CLOCK_H_
10
11#include "fsl_common.h"
12
13/*! @addtogroup clock */
14/*! @{ */
15
16/*! @file */
17
18/*******************************************************************************
19 * Configurations
20 ******************************************************************************/
21
22/*! @brief Configure whether driver controls clock
23 *
24 * When set to 0, peripheral drivers will enable clock in initialize function
25 * and disable clock in de-initialize function. When set to 1, peripheral
26 * driver will not control the clock, application could control the clock out of
27 * the driver.
28 *
29 * @note All drivers share this feature switcher. If it is set to 1, application
30 * should handle clock enable and disable for all drivers.
31 */
32#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
33#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
34#endif
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*! @name Driver version */
41/*@{*/
42/*! @brief CLOCK driver version 2.4.0. */
43#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 4, 0))
44
45/* Definition for delay API in clock driver, users can redefine it to the real application. */
46#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
47#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
48#endif
49
50/* analog pll definition */
51#define CCM_ANALOG_PLL_BYPASS_SHIFT (16U)
52#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK (0xC000U)
53#define CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT (14U)
54
55/*@}*/
56
57/*!
58 * @brief CCM registers offset.
59 */
60#define CCSR_OFFSET 0x0C
61#define CBCDR_OFFSET 0x14
62#define CBCMR_OFFSET 0x18
63#define CSCMR1_OFFSET 0x1C
64#define CSCMR2_OFFSET 0x20
65#define CSCDR1_OFFSET 0x24
66#define CDCDR_OFFSET 0x30
67#define CSCDR2_OFFSET 0x38
68#define CSCDR3_OFFSET 0x3C
69#define CACRR_OFFSET 0x10
70#define CS1CDR_OFFSET 0x28
71#define CS2CDR_OFFSET 0x2C
72
73/*!
74 * @brief CCM Analog registers offset.
75 */
76#define PLL_ARM_OFFSET 0x00
77#define PLL_SYS_OFFSET 0x30
78#define PLL_USB1_OFFSET 0x10
79#define PLL_AUDIO_OFFSET 0x70
80#define PLL_VIDEO_OFFSET 0xA0
81#define PLL_ENET_OFFSET 0xE0
82#define PLL_USB2_OFFSET 0x20
83
84#define CCM_TUPLE(reg, shift, mask, busyShift) \
85 (int)(((reg)&0xFFU) | ((shift) << 8U) | ((((mask) >> (shift)) & 0x1FFFU) << 13U) | ((busyShift) << 26U))
86#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFU))))
87#define CCM_TUPLE_SHIFT(tuple) ((((uint32_t)tuple) >> 8U) & 0x1FU)
88#define CCM_TUPLE_MASK(tuple) \
89 ((uint32_t)((((uint32_t)(tuple) >> 13U) & 0x1FFFU) << (((((uint32_t)tuple) >> 8U) & 0x1FU))))
90#define CCM_TUPLE_BUSY_SHIFT(tuple) ((((uint32_t)tuple) >> 26U) & 0x3FU)
91
92#define CCM_NO_BUSY_WAIT (0x20U)
93
94/*!
95 * @brief CCM ANALOG tuple macros to map corresponding registers and bit fields.
96 */
97#define CCM_ANALOG_TUPLE(reg, shift) ((((reg)&0xFFFU) << 16U) | (shift))
98#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((uint32_t)tuple) & 0x1FU)
99#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) \
100 (*((volatile uint32_t *)((uint32_t)(base) + (((uint32_t)(tuple) >> 16U) & 0xFFFU) + (off))))
101#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0U)
102
103/* Definition for ERRATA 50235 check */
104#if (defined(FSL_FEATURE_CCM_HAS_ERRATA_50235) && FSL_FEATURE_CCM_HAS_ERRATA_50235)
105#define CAN_CLOCK_CHECK_NO_AFFECTS \
106 ((CCM_CSCMR2_CAN_CLK_SEL(2U) != (CCM->CSCMR2 & CCM_CSCMR2_CAN_CLK_SEL_MASK)) || \
107 (CCM_CCGR5_CG12(0) != (CCM->CCGR5 & CCM_CCGR5_CG12_MASK)))
108#endif /* FSL_FEATURE_CCM_HAS_ERRATA_50235 */
109
110/*!
111 * @brief clock1PN frequency.
112 */
113#define CLKPN_FREQ 0U
114
115/*! @brief External XTAL (24M OSC/SYSOSC) clock frequency.
116 *
117 * The XTAL (24M OSC/SYSOSC) clock frequency in Hz, when the clock is setup, use the
118 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
119 * if XTAL is 24MHz,
120 * @code
121 * CLOCK_InitExternalClk(false);
122 * CLOCK_SetXtalFreq(240000000);
123 * @endcode
124 */
125extern volatile uint32_t g_xtalFreq;
126
127/*! @brief External RTC XTAL (32K OSC) clock frequency.
128 *
129 * The RTC XTAL (32K OSC) clock frequency in Hz, when the clock is setup, use the
130 * function CLOCK_SetRtcXtalFreq to set the value in to clock driver.
131 */
132extern volatile uint32_t g_rtcXtalFreq;
133
134/* For compatible with other platforms */
135#define CLOCK_SetXtal0Freq CLOCK_SetXtalFreq
136#define CLOCK_SetXtal32Freq CLOCK_SetRtcXtalFreq
137
138/*! @brief Clock ip name array for ADC. */
139#define ADC_CLOCKS \
140 { \
141 kCLOCK_IpInvalid, kCLOCK_Adc1, kCLOCK_Adc2 \
142 }
143
144/*! @brief Clock ip name array for AOI. */
145#define AOI_CLOCKS \
146 { \
147 kCLOCK_IpInvalid, kCLOCK_Aoi1, kCLOCK_Aoi2 \
148 }
149
150/*! @brief Clock ip name array for BEE. */
151#define BEE_CLOCKS \
152 { \
153 kCLOCK_Bee \
154 }
155
156/*! @brief Clock ip name array for CMP. */
157#define CMP_CLOCKS \
158 { \
159 kCLOCK_IpInvalid, kCLOCK_Acmp1, kCLOCK_Acmp2, kCLOCK_Acmp3, kCLOCK_Acmp4 \
160 }
161
162/*! @brief Clock ip name array for CSI. */
163#define CSI_CLOCKS \
164 { \
165 kCLOCK_Csi \
166 }
167
168/*! @brief Clock ip name array for DCDC. */
169#define DCDC_CLOCKS \
170 { \
171 kCLOCK_Dcdc \
172 }
173
174/*! @brief Clock ip name array for DCP. */
175#define DCP_CLOCKS \
176 { \
177 kCLOCK_Dcp \
178 }
179
180/*! @brief Clock ip name array for DMAMUX_CLOCKS. */
181#define DMAMUX_CLOCKS \
182 { \
183 kCLOCK_Dma \
184 }
185
186/*! @brief Clock ip name array for DMA. */
187#define EDMA_CLOCKS \
188 { \
189 kCLOCK_Dma \
190 }
191
192/*! @brief Clock ip name array for ENC. */
193#define ENC_CLOCKS \
194 { \
195 kCLOCK_IpInvalid, kCLOCK_Enc1, kCLOCK_Enc2, kCLOCK_Enc3, kCLOCK_Enc4 \
196 }
197
198/*! @brief Clock ip name array for ENET. */
199#define ENET_CLOCKS \
200 { \
201 kCLOCK_Enet, kCLOCK_IpInvalid, kCLOCK_Enet2 \
202 }
203
204/*! @brief Clock ip name array for EWM. */
205#define EWM_CLOCKS \
206 { \
207 kCLOCK_Ewm0 \
208 }
209
210/*! @brief Clock ip name array for FLEXCAN. */
211#define FLEXCAN_CLOCKS \
212 { \
213 kCLOCK_IpInvalid, kCLOCK_Can1, kCLOCK_Can2, kCLOCK_Can3 \
214 }
215
216/*! @brief Clock ip name array for FLEXCAN Peripheral clock. */
217#define FLEXCAN_PERIPH_CLOCKS \
218 { \
219 kCLOCK_IpInvalid, kCLOCK_Can1S, kCLOCK_Can2S, kCLOCK_Can3S \
220 }
221
222/*! @brief Clock ip name array for FLEXIO. */
223#define FLEXIO_CLOCKS \
224 { \
225 kCLOCK_IpInvalid, kCLOCK_Flexio1, kCLOCK_Flexio2, kCLOCK_Flexio3 \
226 }
227
228/*! @brief Clock ip name array for FLEXRAM. */
229#define FLEXRAM_CLOCKS \
230 { \
231 kCLOCK_FlexRam \
232 }
233
234/*! @brief Clock ip name array for FLEXSPI. */
235#define FLEXSPI_CLOCKS \
236 { \
237 kCLOCK_FlexSpi, kCLOCK_IpInvalid, kCLOCK_FlexSpi2 \
238 }
239
240/*! @brief Clock ip name array for FLEXSPI EXSC. */
241#define FLEXSPI_EXSC_CLOCKS \
242 { \
243 kCLOCK_FlexSpiExsc \
244 }
245
246/*! @brief Clock ip name array for GPIO. */
247#define GPIO_CLOCKS \
248 { \
249 kCLOCK_IpInvalid, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
250 }
251
252/*! @brief Clock ip name array for GPT. */
253#define GPT_CLOCKS \
254 { \
255 kCLOCK_IpInvalid, kCLOCK_Gpt1, kCLOCK_Gpt2 \
256 }
257
258/*! @brief Clock ip name array for KPP. */
259#define KPP_CLOCKS \
260 { \
261 kCLOCK_Kpp \
262 }
263
264/*! @brief Clock ip name array for LCDIF. */
265#define LCDIF_CLOCKS \
266 { \
267 kCLOCK_Lcd \
268 }
269
270/*! @brief Clock ip name array for LCDIF PIXEL. */
271#define LCDIF_PERIPH_CLOCKS \
272 { \
273 kCLOCK_LcdPixel \
274 }
275
276/*! @brief Clock ip name array for LPI2C. */
277#define LPI2C_CLOCKS \
278 { \
279 kCLOCK_IpInvalid, kCLOCK_Lpi2c1, kCLOCK_Lpi2c2, kCLOCK_Lpi2c3, kCLOCK_Lpi2c4 \
280 }
281
282/*! @brief Clock ip name array for LPSPI. */
283#define LPSPI_CLOCKS \
284 { \
285 kCLOCK_IpInvalid, kCLOCK_Lpspi1, kCLOCK_Lpspi2, kCLOCK_Lpspi3, kCLOCK_Lpspi4 \
286 }
287
288/*! @brief Clock ip name array for LPUART. */
289#define LPUART_CLOCKS \
290 { \
291 kCLOCK_IpInvalid, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4, kCLOCK_Lpuart5, \
292 kCLOCK_Lpuart6, kCLOCK_Lpuart7, kCLOCK_Lpuart8 \
293 }
294
295/*! @brief Clock ip name array for MQS. */
296#define MQS_CLOCKS \
297 { \
298 kCLOCK_Mqs \
299 }
300
301/*! @brief Clock ip name array for OCRAM EXSC. */
302#define OCRAM_EXSC_CLOCKS \
303 { \
304 kCLOCK_OcramExsc \
305 }
306
307/*! @brief Clock ip name array for PIT. */
308#define PIT_CLOCKS \
309 { \
310 kCLOCK_Pit \
311 }
312
313/*! @brief Clock ip name array for PWM. */
314#define PWM_CLOCKS \
315 { \
316 {kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_IpInvalid}, \
317 {kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1, kCLOCK_Pwm1}, \
318 {kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2, kCLOCK_Pwm2}, \
319 {kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3, kCLOCK_Pwm3}, \
320 { \
321 kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4, kCLOCK_Pwm4 \
322 } \
323 }
324
325/*! @brief Clock ip name array for PXP. */
326#define PXP_CLOCKS \
327 { \
328 kCLOCK_Pxp \
329 }
330
331/*! @brief Clock ip name array for RTWDOG. */
332#define RTWDOG_CLOCKS \
333 { \
334 kCLOCK_Wdog3 \
335 }
336
337/*! @brief Clock ip name array for SAI. */
338#define SAI_CLOCKS \
339 { \
340 kCLOCK_IpInvalid, kCLOCK_Sai1, kCLOCK_Sai2, kCLOCK_Sai3 \
341 }
342
343/*! @brief Clock ip name array for SEMC. */
344#define SEMC_CLOCKS \
345 { \
346 kCLOCK_Semc \
347 }
348
349/*! @brief Clock ip name array for SEMC EXSC. */
350#define SEMC_EXSC_CLOCKS \
351 { \
352 kCLOCK_SemcExsc \
353 }
354
355/*! @brief Clock ip name array for QTIMER. */
356#define TMR_CLOCKS \
357 { \
358 kCLOCK_IpInvalid, kCLOCK_Timer1, kCLOCK_Timer2, kCLOCK_Timer3, kCLOCK_Timer4 \
359 }
360
361/*! @brief Clock ip name array for TRNG. */
362#define TRNG_CLOCKS \
363 { \
364 kCLOCK_Trng \
365 }
366
367/*! @brief Clock ip name array for TSC. */
368#define TSC_CLOCKS \
369 { \
370 kCLOCK_Tsc \
371 }
372
373/*! @brief Clock ip name array for WDOG. */
374#define WDOG_CLOCKS \
375 { \
376 kCLOCK_IpInvalid, kCLOCK_Wdog1, kCLOCK_Wdog2 \
377 }
378
379/*! @brief Clock ip name array for USDHC. */
380#define USDHC_CLOCKS \
381 { \
382 kCLOCK_IpInvalid, kCLOCK_Usdhc1, kCLOCK_Usdhc2 \
383 }
384
385/*! @brief Clock ip name array for SPDIF. */
386#define SPDIF_CLOCKS \
387 { \
388 kCLOCK_Spdif \
389 }
390
391/*! @brief Clock ip name array for XBARA. */
392#define XBARA_CLOCKS \
393 { \
394 kCLOCK_Xbar1 \
395 }
396
397/*! @brief Clock ip name array for XBARB. */
398#define XBARB_CLOCKS \
399 { \
400 kCLOCK_IpInvalid, kCLOCK_IpInvalid, kCLOCK_Xbar2, kCLOCK_Xbar3 \
401 }
402
403#define CLOCK_SOURCE_NONE (0xFFU)
404
405#define CLOCK_ROOT_SOUCE \
406 { \
407 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
408 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC1 Clock Root. */ \
409 {kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, kCLOCK_NoneName, \
410 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* USDHC2 Clock Root. */ \
411 {kCLOCK_SemcClk, kCLOCK_Usb1SwClk, kCLOCK_SysPllPfd2Clk, \
412 kCLOCK_Usb1PllPfd0Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXSPI Clock Root. */ \
413 {kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_Usb1PllPfd1Clk, \
414 kCLOCK_SysPllClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXSPI2 Clock Root. */ \
415 {kCLOCK_OscClk, kCLOCK_SysPllPfd2Clk, kCLOCK_Usb1Sw120MClk, \
416 kCLOCK_Usb1PllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* CSI Clock Root. */ \
417 {kCLOCK_Usb1PllPfd1Clk, kCLOCK_Usb1PllPfd0Clk, kCLOCK_SysPllClk, \
418 kCLOCK_SysPllPfd2Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPSPI Clock Root. */ \
419 {kCLOCK_SysPllClk, kCLOCK_SysPllPfd2Clk, kCLOCK_SysPllPfd0Clk, \
420 kCLOCK_SysPllPfd1Clk, kCLOCK_NoneName, kCLOCK_NoneName}, /* TRACE Clock Root */ \
421 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
422 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI1 Clock Root */ \
423 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
424 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI2 Clock Root */ \
425 {kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, kCLOCK_AudioPllClk, \
426 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* SAI3 Clock Root */ \
427 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
428 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* LPI2C Clock Root */ \
429 {kCLOCK_Usb1Sw60MClk, kCLOCK_OscClk, kCLOCK_Usb1Sw80MClk, \
430 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* CAN Clock Root. */ \
431 {kCLOCK_Usb1Sw80MClk, kCLOCK_OscClk, kCLOCK_NoneName, \
432 kCLOCK_NoneName, kCLOCK_NoneName, kCLOCK_NoneName}, /* UART Clock Root */ \
433 {kCLOCK_SysPllClk, kCLOCK_Usb1PllPfd3Clk, kCLOCK_VideoPllClk, \
434 kCLOCK_SysPllPfd0Clk, kCLOCK_SysPllPfd1Clk, kCLOCK_Usb1PllPfd1Clk}, /* LCDIF Clock Root */ \
435 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
436 kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* SPDIF0 Clock Root */ \
437 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
438 kCLOCK_Usb1SwClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO1 Clock Root */ \
439 {kCLOCK_AudioPllClk, kCLOCK_Usb1PllPfd2Clk, kCLOCK_VideoPllClk, \
440 kCLOCK_Usb1PllClk, kCLOCK_NoneName, kCLOCK_NoneName}, /* FLEXIO2 Clock ROOT */ \
441 }
442
443#define CLOCK_ROOT_MUX_TUPLE \
444 { \
445 kCLOCK_Usdhc1Mux, kCLOCK_Usdhc2Mux, kCLOCK_FlexspiMux, kCLOCK_Flexspi2Mux, kCLOCK_CsiMux, kCLOCK_LpspiMux, \
446 kCLOCK_TraceMux, kCLOCK_Sai1Mux, kCLOCK_Sai2Mux, kCLOCK_Sai3Mux, kCLOCK_Lpi2cMux, kCLOCK_CanMux, \
447 kCLOCK_UartMux, kCLOCK_LcdifPreMux, kCLOCK_SpdifMux, kCLOCK_Flexio1Mux, kCLOCK_Flexio2Mux, \
448 }
449
450#define CLOCK_ROOT_NONE_PRE_DIV 0UL
451
452#define CLOCK_ROOT_DIV_TUPLE \
453 { \
454 {kCLOCK_NonePreDiv, kCLOCK_Usdhc1Div}, {kCLOCK_NonePreDiv, kCLOCK_Usdhc2Div}, \
455 {kCLOCK_NonePreDiv, kCLOCK_FlexspiDiv}, {kCLOCK_NonePreDiv, kCLOCK_Flexspi2Div}, \
456 {kCLOCK_NonePreDiv, kCLOCK_CsiDiv}, {kCLOCK_NonePreDiv, kCLOCK_LpspiDiv}, \
457 {kCLOCK_NonePreDiv, kCLOCK_TraceDiv}, {kCLOCK_Sai1PreDiv, kCLOCK_Sai1Div}, \
458 {kCLOCK_Sai2PreDiv, kCLOCK_Sai2Div}, {kCLOCK_Sai3PreDiv, kCLOCK_Sai3Div}, \
459 {kCLOCK_NonePreDiv, kCLOCK_Lpi2cDiv}, {kCLOCK_NonePreDiv, kCLOCK_CanDiv}, \
460 {kCLOCK_NonePreDiv, kCLOCK_UartDiv}, {kCLOCK_LcdifPreDiv, kCLOCK_LcdifDiv}, \
461 {kCLOCK_Spdif0PreDiv, kCLOCK_Spdif0Div}, {kCLOCK_Flexio1PreDiv, kCLOCK_Flexio1Div}, \
462 {kCLOCK_Flexio2PreDiv, kCLOCK_Flexio2Div}, \
463 }
464
465/*! @brief Clock name used to get clock frequency. */
466typedef enum _clock_name
467{
468 kCLOCK_CpuClk = 0x0U, /*!< CPU clock */
469 kCLOCK_AhbClk = 0x1U, /*!< AHB clock */
470 kCLOCK_SemcClk = 0x2U, /*!< SEMC clock */
471 kCLOCK_IpgClk = 0x3U, /*!< IPG clock */
472 kCLOCK_PerClk = 0x4U, /*!< PER clock */
473
474 kCLOCK_OscClk = 0x5U, /*!< OSC clock selected by PMU_LOWPWR_CTRL[OSC_SEL]. */
475 kCLOCK_RtcClk = 0x6U, /*!< RTC clock. (RTCCLK) */
476
477 kCLOCK_ArmPllClk = 0x7U, /*!< ARMPLLCLK. */
478
479 kCLOCK_Usb1PllClk = 0x8U, /*!< USB1PLLCLK. */
480 kCLOCK_Usb1PllPfd0Clk = 0x9U, /*!< USB1PLLPDF0CLK. */
481 kCLOCK_Usb1PllPfd1Clk = 0xAU, /*!< USB1PLLPFD1CLK. */
482 kCLOCK_Usb1PllPfd2Clk = 0xBU, /*!< USB1PLLPFD2CLK. */
483 kCLOCK_Usb1PllPfd3Clk = 0xCU, /*!< USB1PLLPFD3CLK. */
484 kCLOCK_Usb1SwClk = 0x18U,
485 kCLOCK_Usb1Sw120MClk = 0x19U,
486 kCLOCK_Usb1Sw60MClk = 0x1AU,
487 kCLOCK_Usb1Sw80MClk = 0x1BU,
488
489 kCLOCK_Usb2PllClk = 0xDU, /*!< USB2PLLCLK. */
490
491 kCLOCK_SysPllClk = 0xEU, /*!< SYSPLLCLK. */
492 kCLOCK_SysPllPfd0Clk = 0xFU, /*!< SYSPLLPDF0CLK. */
493 kCLOCK_SysPllPfd1Clk = 0x10U, /*!< SYSPLLPFD1CLK. */
494 kCLOCK_SysPllPfd2Clk = 0x11U, /*!< SYSPLLPFD2CLK. */
495 kCLOCK_SysPllPfd3Clk = 0x12U, /*!< SYSPLLPFD3CLK. */
496
497 kCLOCK_EnetPll0Clk = 0x13U, /*!< Enet PLLCLK ref_enetpll0. */
498 kCLOCK_EnetPll1Clk = 0x14U, /*!< Enet PLLCLK ref_enetpll1. */
499 kCLOCK_EnetPll2Clk = 0x15U, /*!< Enet PLLCLK ref_enetpll2. */
500
501 kCLOCK_AudioPllClk = 0x16U, /*!< Audio PLLCLK. */
502 kCLOCK_VideoPllClk = 0x17U, /*!< Video PLLCLK. */
503
504 kCLOCK_NoneName = CLOCK_SOURCE_NONE,
505} clock_name_t;
506
507#define kCLOCK_CoreSysClk kCLOCK_CpuClk /*!< For compatible with other platforms without CCM. */
508#define CLOCK_GetCoreSysClkFreq CLOCK_GetCpuClkFreq /*!< For compatible with other platforms without CCM. */
509
510/*!
511 * @brief CCM CCGR gate control for each module independently.
512 */
513typedef enum _clock_ip_name
514{
515 kCLOCK_IpInvalid = -1,
516
517 /* CCM CCGR0 */
518 kCLOCK_Aips_tz1 = (0U << 8U) | CCM_CCGR0_CG0_SHIFT, /*!< CCGR0, CG0 */
519 kCLOCK_Aips_tz2 = (0U << 8U) | CCM_CCGR0_CG1_SHIFT, /*!< CCGR0, CG1 */
520 kCLOCK_Mqs = (0U << 8U) | CCM_CCGR0_CG2_SHIFT, /*!< CCGR0, CG2 */
521 kCLOCK_FlexSpiExsc = (0U << 8U) | CCM_CCGR0_CG3_SHIFT, /*!< CCGR0, CG3 */
522 kCLOCK_Sim_M_Main = (0U << 8U) | CCM_CCGR0_CG4_SHIFT, /*!< CCGR0, CG4 */
523 kCLOCK_Dcp = (0U << 8U) | CCM_CCGR0_CG5_SHIFT, /*!< CCGR0, CG5 */
524 kCLOCK_Lpuart3 = (0U << 8U) | CCM_CCGR0_CG6_SHIFT, /*!< CCGR0, CG6 */
525 kCLOCK_Can1 = (0U << 8U) | CCM_CCGR0_CG7_SHIFT, /*!< CCGR0, CG7 */
526 kCLOCK_Can1S = (0U << 8U) | CCM_CCGR0_CG8_SHIFT, /*!< CCGR0, CG8 */
527 kCLOCK_Can2 = (0U << 8U) | CCM_CCGR0_CG9_SHIFT, /*!< CCGR0, CG9 */
528 kCLOCK_Can2S = (0U << 8U) | CCM_CCGR0_CG10_SHIFT, /*!< CCGR0, CG10 */
529 kCLOCK_Trace = (0U << 8U) | CCM_CCGR0_CG11_SHIFT, /*!< CCGR0, CG11 */
530 kCLOCK_Gpt2 = (0U << 8U) | CCM_CCGR0_CG12_SHIFT, /*!< CCGR0, CG12 */
531 kCLOCK_Gpt2S = (0U << 8U) | CCM_CCGR0_CG13_SHIFT, /*!< CCGR0, CG13 */
532 kCLOCK_Lpuart2 = (0U << 8U) | CCM_CCGR0_CG14_SHIFT, /*!< CCGR0, CG14 */
533 kCLOCK_Gpio2 = (0U << 8U) | CCM_CCGR0_CG15_SHIFT, /*!< CCGR0, CG15 */
534
535 /* CCM CCGR1 */
536 kCLOCK_Lpspi1 = (1U << 8U) | CCM_CCGR1_CG0_SHIFT, /*!< CCGR1, CG0 */
537 kCLOCK_Lpspi2 = (1U << 8U) | CCM_CCGR1_CG1_SHIFT, /*!< CCGR1, CG1 */
538 kCLOCK_Lpspi3 = (1U << 8U) | CCM_CCGR1_CG2_SHIFT, /*!< CCGR1, CG2 */
539 kCLOCK_Lpspi4 = (1U << 8U) | CCM_CCGR1_CG3_SHIFT, /*!< CCGR1, CG3 */
540 kCLOCK_Adc2 = (1U << 8U) | CCM_CCGR1_CG4_SHIFT, /*!< CCGR1, CG4 */
541 kCLOCK_Enet = (1U << 8U) | CCM_CCGR1_CG5_SHIFT, /*!< CCGR1, CG5 */
542 kCLOCK_Pit = (1U << 8U) | CCM_CCGR1_CG6_SHIFT, /*!< CCGR1, CG6 */
543 kCLOCK_Aoi2 = (1U << 8U) | CCM_CCGR1_CG7_SHIFT, /*!< CCGR1, CG7 */
544 kCLOCK_Adc1 = (1U << 8U) | CCM_CCGR1_CG8_SHIFT, /*!< CCGR1, CG8 */
545 kCLOCK_SemcExsc = (1U << 8U) | CCM_CCGR1_CG9_SHIFT, /*!< CCGR1, CG9 */
546 kCLOCK_Gpt1 = (1U << 8U) | CCM_CCGR1_CG10_SHIFT, /*!< CCGR1, CG10 */
547 kCLOCK_Gpt1S = (1U << 8U) | CCM_CCGR1_CG11_SHIFT, /*!< CCGR1, CG11 */
548 kCLOCK_Lpuart4 = (1U << 8U) | CCM_CCGR1_CG12_SHIFT, /*!< CCGR1, CG12 */
549 kCLOCK_Gpio1 = (1U << 8U) | CCM_CCGR1_CG13_SHIFT, /*!< CCGR1, CG13 */
550 kCLOCK_Csu = (1U << 8U) | CCM_CCGR1_CG14_SHIFT, /*!< CCGR1, CG14 */
551 kCLOCK_Gpio5 = (1U << 8U) | CCM_CCGR1_CG15_SHIFT, /*!< CCGR1, CG15 */
552
553 /* CCM CCGR2 */
554 kCLOCK_OcramExsc = (2U << 8U) | CCM_CCGR2_CG0_SHIFT, /*!< CCGR2, CG0 */
555 kCLOCK_Csi = (2U << 8U) | CCM_CCGR2_CG1_SHIFT, /*!< CCGR2, CG1 */
556 kCLOCK_IomuxcSnvs = (2U << 8U) | CCM_CCGR2_CG2_SHIFT, /*!< CCGR2, CG2 */
557 kCLOCK_Lpi2c1 = (2U << 8U) | CCM_CCGR2_CG3_SHIFT, /*!< CCGR2, CG3 */
558 kCLOCK_Lpi2c2 = (2U << 8U) | CCM_CCGR2_CG4_SHIFT, /*!< CCGR2, CG4 */
559 kCLOCK_Lpi2c3 = (2U << 8U) | CCM_CCGR2_CG5_SHIFT, /*!< CCGR2, CG5 */
560 kCLOCK_Ocotp = (2U << 8U) | CCM_CCGR2_CG6_SHIFT, /*!< CCGR2, CG6 */
561 kCLOCK_Xbar3 = (2U << 8U) | CCM_CCGR2_CG7_SHIFT, /*!< CCGR2, CG7 */
562 kCLOCK_Ipmux1 = (2U << 8U) | CCM_CCGR2_CG8_SHIFT, /*!< CCGR2, CG8 */
563 kCLOCK_Ipmux2 = (2U << 8U) | CCM_CCGR2_CG9_SHIFT, /*!< CCGR2, CG9 */
564 kCLOCK_Ipmux3 = (2U << 8U) | CCM_CCGR2_CG10_SHIFT, /*!< CCGR2, CG10 */
565 kCLOCK_Xbar1 = (2U << 8U) | CCM_CCGR2_CG11_SHIFT, /*!< CCGR2, CG11 */
566 kCLOCK_Xbar2 = (2U << 8U) | CCM_CCGR2_CG12_SHIFT, /*!< CCGR2, CG12 */
567 kCLOCK_Gpio3 = (2U << 8U) | CCM_CCGR2_CG13_SHIFT, /*!< CCGR2, CG13 */
568 kCLOCK_Lcd = (2U << 8U) | CCM_CCGR2_CG14_SHIFT, /*!< CCGR2, CG14 */
569 kCLOCK_Pxp = (2U << 8U) | CCM_CCGR2_CG15_SHIFT, /*!< CCGR2, CG15 */
570
571 /* CCM CCGR3 */
572 kCLOCK_Flexio2 = (3U << 8U) | CCM_CCGR3_CG0_SHIFT, /*!< CCGR3, CG0 */
573 kCLOCK_Lpuart5 = (3U << 8U) | CCM_CCGR3_CG1_SHIFT, /*!< CCGR3, CG1 */
574 kCLOCK_Semc = (3U << 8U) | CCM_CCGR3_CG2_SHIFT, /*!< CCGR3, CG2 */
575 kCLOCK_Lpuart6 = (3U << 8U) | CCM_CCGR3_CG3_SHIFT, /*!< CCGR3, CG3 */
576 kCLOCK_Aoi1 = (3U << 8U) | CCM_CCGR3_CG4_SHIFT, /*!< CCGR3, CG4 */
577 kCLOCK_LcdPixel = (3U << 8U) | CCM_CCGR3_CG5_SHIFT, /*!< CCGR3, CG5 */
578 kCLOCK_Gpio4 = (3U << 8U) | CCM_CCGR3_CG6_SHIFT, /*!< CCGR3, CG6 */
579 kCLOCK_Ewm0 = (3U << 8U) | CCM_CCGR3_CG7_SHIFT, /*!< CCGR3, CG7 */
580 kCLOCK_Wdog1 = (3U << 8U) | CCM_CCGR3_CG8_SHIFT, /*!< CCGR3, CG8 */
581 kCLOCK_FlexRam = (3U << 8U) | CCM_CCGR3_CG9_SHIFT, /*!< CCGR3, CG9 */
582 kCLOCK_Acmp1 = (3U << 8U) | CCM_CCGR3_CG10_SHIFT, /*!< CCGR3, CG10 */
583 kCLOCK_Acmp2 = (3U << 8U) | CCM_CCGR3_CG11_SHIFT, /*!< CCGR3, CG11 */
584 kCLOCK_Acmp3 = (3U << 8U) | CCM_CCGR3_CG12_SHIFT, /*!< CCGR3, CG12 */
585 kCLOCK_Acmp4 = (3U << 8U) | CCM_CCGR3_CG13_SHIFT, /*!< CCGR3, CG13 */
586 kCLOCK_Ocram = (3U << 8U) | CCM_CCGR3_CG14_SHIFT, /*!< CCGR3, CG14 */
587 kCLOCK_IomuxcSnvsGpr = (3U << 8U) | CCM_CCGR3_CG15_SHIFT, /*!< CCGR3, CG15 */
588
589 /* CCM CCGR4 */
590 kCLOCK_Iomuxc = (4U << 8U) | CCM_CCGR4_CG1_SHIFT, /*!< CCGR4, CG1 */
591 kCLOCK_IomuxcGpr = (4U << 8U) | CCM_CCGR4_CG2_SHIFT, /*!< CCGR4, CG2 */
592 kCLOCK_Bee = (4U << 8U) | CCM_CCGR4_CG3_SHIFT, /*!< CCGR4, CG3 */
593 kCLOCK_SimM7 = (4U << 8U) | CCM_CCGR4_CG4_SHIFT, /*!< CCGR4, CG4 */
594 kCLOCK_Tsc = (4U << 8U) | CCM_CCGR4_CG5_SHIFT, /*!< CCGR4, CG5 */
595 kCLOCK_SimM = (4U << 8U) | CCM_CCGR4_CG6_SHIFT, /*!< CCGR4, CG6 */
596 kCLOCK_SimEms = (4U << 8U) | CCM_CCGR4_CG7_SHIFT, /*!< CCGR4, CG7 */
597 kCLOCK_Pwm1 = (4U << 8U) | CCM_CCGR4_CG8_SHIFT, /*!< CCGR4, CG8 */
598 kCLOCK_Pwm2 = (4U << 8U) | CCM_CCGR4_CG9_SHIFT, /*!< CCGR4, CG9 */
599 kCLOCK_Pwm3 = (4U << 8U) | CCM_CCGR4_CG10_SHIFT, /*!< CCGR4, CG10 */
600 kCLOCK_Pwm4 = (4U << 8U) | CCM_CCGR4_CG11_SHIFT, /*!< CCGR4, CG11 */
601 kCLOCK_Enc1 = (4U << 8U) | CCM_CCGR4_CG12_SHIFT, /*!< CCGR4, CG12 */
602 kCLOCK_Enc2 = (4U << 8U) | CCM_CCGR4_CG13_SHIFT, /*!< CCGR4, CG13 */
603 kCLOCK_Enc3 = (4U << 8U) | CCM_CCGR4_CG14_SHIFT, /*!< CCGR4, CG14 */
604 kCLOCK_Enc4 = (4U << 8U) | CCM_CCGR4_CG15_SHIFT, /*!< CCGR4, CG15 */
605
606 /* CCM CCGR5 */
607 kCLOCK_Rom = (5U << 8U) | CCM_CCGR5_CG0_SHIFT, /*!< CCGR5, CG0 */
608 kCLOCK_Flexio1 = (5U << 8U) | CCM_CCGR5_CG1_SHIFT, /*!< CCGR5, CG1 */
609 kCLOCK_Wdog3 = (5U << 8U) | CCM_CCGR5_CG2_SHIFT, /*!< CCGR5, CG2 */
610 kCLOCK_Dma = (5U << 8U) | CCM_CCGR5_CG3_SHIFT, /*!< CCGR5, CG3 */
611 kCLOCK_Kpp = (5U << 8U) | CCM_CCGR5_CG4_SHIFT, /*!< CCGR5, CG4 */
612 kCLOCK_Wdog2 = (5U << 8U) | CCM_CCGR5_CG5_SHIFT, /*!< CCGR5, CG5 */
613 kCLOCK_Aips_tz4 = (5U << 8U) | CCM_CCGR5_CG6_SHIFT, /*!< CCGR5, CG6 */
614 kCLOCK_Spdif = (5U << 8U) | CCM_CCGR5_CG7_SHIFT, /*!< CCGR5, CG7 */
615 kCLOCK_SimMain = (5U << 8U) | CCM_CCGR5_CG8_SHIFT, /*!< CCGR5, CG8 */
616 kCLOCK_Sai1 = (5U << 8U) | CCM_CCGR5_CG9_SHIFT, /*!< CCGR5, CG9 */
617 kCLOCK_Sai2 = (5U << 8U) | CCM_CCGR5_CG10_SHIFT, /*!< CCGR5, CG10 */
618 kCLOCK_Sai3 = (5U << 8U) | CCM_CCGR5_CG11_SHIFT, /*!< CCGR5, CG11 */
619 kCLOCK_Lpuart1 = (5U << 8U) | CCM_CCGR5_CG12_SHIFT, /*!< CCGR5, CG12 */
620 kCLOCK_Lpuart7 = (5U << 8U) | CCM_CCGR5_CG13_SHIFT, /*!< CCGR5, CG13 */
621 kCLOCK_SnvsHp = (5U << 8U) | CCM_CCGR5_CG14_SHIFT, /*!< CCGR5, CG14 */
622 kCLOCK_SnvsLp = (5U << 8U) | CCM_CCGR5_CG15_SHIFT, /*!< CCGR5, CG15 */
623
624 /* CCM CCGR6 */
625 kCLOCK_UsbOh3 = (6U << 8U) | CCM_CCGR6_CG0_SHIFT, /*!< CCGR6, CG0 */
626 kCLOCK_Usdhc1 = (6U << 8U) | CCM_CCGR6_CG1_SHIFT, /*!< CCGR6, CG1 */
627 kCLOCK_Usdhc2 = (6U << 8U) | CCM_CCGR6_CG2_SHIFT, /*!< CCGR6, CG2 */
628 kCLOCK_Dcdc = (6U << 8U) | CCM_CCGR6_CG3_SHIFT, /*!< CCGR6, CG3 */
629 kCLOCK_Ipmux4 = (6U << 8U) | CCM_CCGR6_CG4_SHIFT, /*!< CCGR6, CG4 */
630 kCLOCK_FlexSpi = (6U << 8U) | CCM_CCGR6_CG5_SHIFT, /*!< CCGR6, CG5 */
631 kCLOCK_Trng = (6U << 8U) | CCM_CCGR6_CG6_SHIFT, /*!< CCGR6, CG6 */
632 kCLOCK_Lpuart8 = (6U << 8U) | CCM_CCGR6_CG7_SHIFT, /*!< CCGR6, CG7 */
633 kCLOCK_Timer4 = (6U << 8U) | CCM_CCGR6_CG8_SHIFT, /*!< CCGR6, CG8 */
634 kCLOCK_Aips_tz3 = (6U << 8U) | CCM_CCGR6_CG9_SHIFT, /*!< CCGR6, CG9 */
635 kCLOCK_SimPer = (6U << 8U) | CCM_CCGR6_CG10_SHIFT, /*!< CCGR6, CG10 */
636 kCLOCK_Anadig = (6U << 8U) | CCM_CCGR6_CG11_SHIFT, /*!< CCGR6, CG11 */
637 kCLOCK_Lpi2c4 = (6U << 8U) | CCM_CCGR6_CG12_SHIFT, /*!< CCGR6, CG12 */
638 kCLOCK_Timer1 = (6U << 8U) | CCM_CCGR6_CG13_SHIFT, /*!< CCGR6, CG13 */
639 kCLOCK_Timer2 = (6U << 8U) | CCM_CCGR6_CG14_SHIFT, /*!< CCGR6, CG14 */
640 kCLOCK_Timer3 = (6U << 8U) | CCM_CCGR6_CG15_SHIFT, /*!< CCGR6, CG15 */
641
642 /* CCM CCGR7 */
643 kCLOCK_Enet2 = (7U << 8U) | CCM_CCGR7_CG0_SHIFT, /*!< CCGR7, CG0 */
644 kCLOCK_FlexSpi2 = (7U << 8U) | CCM_CCGR7_CG1_SHIFT, /*!< CCGR7, CG1 */
645 kCLOCK_Axbs_l = (7U << 8U) | CCM_CCGR7_CG2_SHIFT, /*!< CCGR7, CG2 */
646 kCLOCK_Can3 = (7U << 8U) | CCM_CCGR7_CG3_SHIFT, /*!< CCGR7, CG3 */
647 kCLOCK_Can3S = (7U << 8U) | CCM_CCGR7_CG4_SHIFT, /*!< CCGR7, CG4 */
648 kCLOCK_Aips_lite = (7U << 8U) | CCM_CCGR7_CG5_SHIFT, /*!< CCGR7, CG5 */
649 kCLOCK_Flexio3 = (7U << 8U) | CCM_CCGR7_CG6_SHIFT, /*!< CCGR7, CG6 */
650
651} clock_ip_name_t;
652
653/*! @brief OSC 24M sorce select */
654typedef enum _clock_osc
655{
656 kCLOCK_RcOsc = 0U, /*!< On chip OSC. */
657 kCLOCK_XtalOsc = 1U, /*!< 24M Xtal OSC */
658} clock_osc_t;
659
660/*! @brief Clock gate value */
661typedef enum _clock_gate_value
662{
663 kCLOCK_ClockNotNeeded = 0U, /*!< Clock is off during all modes. */
664 kCLOCK_ClockNeededRun = 1U, /*!< Clock is on in run mode, but off in WAIT and STOP modes */
665 kCLOCK_ClockNeededRunWait = 3U, /*!< Clock is on during all modes, except STOP mode */
666} clock_gate_value_t;
667
668/*! @brief System clock mode */
669typedef enum _clock_mode_t
670{
671 kCLOCK_ModeRun = 0U, /*!< Remain in run mode. */
672 kCLOCK_ModeWait = 1U, /*!< Transfer to wait mode. */
673 kCLOCK_ModeStop = 2U, /*!< Transfer to stop mode. */
674} clock_mode_t;
675
676/*!
677 * @brief MUX control names for clock mux setting.
678 *
679 * These constants define the mux control names for clock mux setting.\n
680 * - 0:7: REG offset to CCM_BASE in bytes.
681 * - 8:15: Root clock setting bit field shift.
682 * - 16:31: Root clock setting bit field width.
683 */
684typedef enum _clock_mux
685{
686 kCLOCK_Pll3SwMux = CCM_TUPLE(CCSR_OFFSET,
687 CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT,
688 CCM_CCSR_PLL3_SW_CLK_SEL_MASK,
689 CCM_NO_BUSY_WAIT), /*!< pll3_sw_clk mux name */
690
691 kCLOCK_PeriphMux = CCM_TUPLE(CBCDR_OFFSET,
692 CCM_CBCDR_PERIPH_CLK_SEL_SHIFT,
693 CCM_CBCDR_PERIPH_CLK_SEL_MASK,
694 CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT), /*!< periph mux name */
695 kCLOCK_SemcAltMux = CCM_TUPLE(CBCDR_OFFSET,
696 CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT,
697 CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK,
698 CCM_NO_BUSY_WAIT), /*!< semc mux name */
699 kCLOCK_SemcMux = CCM_TUPLE(CBCDR_OFFSET,
700 CCM_CBCDR_SEMC_CLK_SEL_SHIFT,
701 CCM_CBCDR_SEMC_CLK_SEL_MASK,
702 CCM_NO_BUSY_WAIT), /*!< semc mux name */
703
704 kCLOCK_PrePeriphMux = CCM_TUPLE(CBCMR_OFFSET,
705 CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT,
706 CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK,
707 CCM_NO_BUSY_WAIT), /*!< pre-periph mux name */
708 kCLOCK_TraceMux = CCM_TUPLE(CBCMR_OFFSET,
709 CCM_CBCMR_TRACE_CLK_SEL_SHIFT,
710 CCM_CBCMR_TRACE_CLK_SEL_MASK,
711 CCM_NO_BUSY_WAIT), /*!< trace mux name */
712 kCLOCK_PeriphClk2Mux = CCM_TUPLE(CBCMR_OFFSET,
713 CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT,
714 CCM_CBCMR_PERIPH_CLK2_SEL_MASK,
715 CCM_NO_BUSY_WAIT), /*!< periph clock2 mux name */
716 kCLOCK_Flexspi2Mux = CCM_TUPLE(CBCMR_OFFSET,
717 CCM_CBCMR_FLEXSPI2_CLK_SEL_SHIFT,
718 CCM_CBCMR_FLEXSPI2_CLK_SEL_MASK,
719 CCM_NO_BUSY_WAIT), /*!< flexspi2 mux name */
720 kCLOCK_LpspiMux = CCM_TUPLE(CBCMR_OFFSET,
721 CCM_CBCMR_LPSPI_CLK_SEL_SHIFT,
722 CCM_CBCMR_LPSPI_CLK_SEL_MASK,
723 CCM_NO_BUSY_WAIT), /*!< lpspi mux name */
724
725 kCLOCK_FlexspiMux = CCM_TUPLE(CSCMR1_OFFSET,
726 CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT,
727 CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK,
728 CCM_NO_BUSY_WAIT), /*!< flexspi mux name */
729 kCLOCK_Usdhc2Mux = CCM_TUPLE(CSCMR1_OFFSET,
730 CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT,
731 CCM_CSCMR1_USDHC2_CLK_SEL_MASK,
732 CCM_NO_BUSY_WAIT), /*!< usdhc2 mux name */
733 kCLOCK_Usdhc1Mux = CCM_TUPLE(CSCMR1_OFFSET,
734 CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT,
735 CCM_CSCMR1_USDHC1_CLK_SEL_MASK,
736 CCM_NO_BUSY_WAIT), /*!< usdhc1 mux name */
737 kCLOCK_Sai3Mux = CCM_TUPLE(CSCMR1_OFFSET,
738 CCM_CSCMR1_SAI3_CLK_SEL_SHIFT,
739 CCM_CSCMR1_SAI3_CLK_SEL_MASK,
740 CCM_NO_BUSY_WAIT), /*!< sai3 mux name */
741 kCLOCK_Sai2Mux = CCM_TUPLE(CSCMR1_OFFSET,
742 CCM_CSCMR1_SAI2_CLK_SEL_SHIFT,
743 CCM_CSCMR1_SAI2_CLK_SEL_MASK,
744 CCM_NO_BUSY_WAIT), /*!< sai2 mux name */
745 kCLOCK_Sai1Mux = CCM_TUPLE(CSCMR1_OFFSET,
746 CCM_CSCMR1_SAI1_CLK_SEL_SHIFT,
747 CCM_CSCMR1_SAI1_CLK_SEL_MASK,
748 CCM_NO_BUSY_WAIT), /*!< sai1 mux name */
749 kCLOCK_PerclkMux = CCM_TUPLE(CSCMR1_OFFSET,
750 CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT,
751 CCM_CSCMR1_PERCLK_CLK_SEL_MASK,
752 CCM_NO_BUSY_WAIT), /*!< perclk mux name */
753
754 kCLOCK_Flexio2Mux = CCM_TUPLE(CSCMR2_OFFSET,
755 CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT,
756 CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK,
757 CCM_NO_BUSY_WAIT), /*!< flexio2 mux name */
758 kCLOCK_CanMux = CCM_TUPLE(CSCMR2_OFFSET,
759 CCM_CSCMR2_CAN_CLK_SEL_SHIFT,
760 CCM_CSCMR2_CAN_CLK_SEL_MASK,
761 CCM_NO_BUSY_WAIT), /*!< can mux name */
762
763 kCLOCK_UartMux = CCM_TUPLE(CSCDR1_OFFSET,
764 CCM_CSCDR1_UART_CLK_SEL_SHIFT,
765 CCM_CSCDR1_UART_CLK_SEL_MASK,
766 CCM_NO_BUSY_WAIT), /*!< uart mux name */
767
768 kCLOCK_SpdifMux = CCM_TUPLE(CDCDR_OFFSET,
769 CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT,
770 CCM_CDCDR_SPDIF0_CLK_SEL_MASK,
771 CCM_NO_BUSY_WAIT), /*!< spdif mux name */
772 kCLOCK_Flexio1Mux = CCM_TUPLE(CDCDR_OFFSET,
773 CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT,
774 CCM_CDCDR_FLEXIO1_CLK_SEL_MASK,
775 CCM_NO_BUSY_WAIT), /*!< flexio1 mux name */
776
777 kCLOCK_Lpi2cMux = CCM_TUPLE(CSCDR2_OFFSET,
778 CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT,
779 CCM_CSCDR2_LPI2C_CLK_SEL_MASK,
780 CCM_NO_BUSY_WAIT), /*!< lpi2c mux name */
781 kCLOCK_LcdifPreMux = CCM_TUPLE(CSCDR2_OFFSET,
782 CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT,
783 CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK,
784 CCM_NO_BUSY_WAIT), /*!< lcdif pre mux name */
785
786 kCLOCK_CsiMux = CCM_TUPLE(CSCDR3_OFFSET,
787 CCM_CSCDR3_CSI_CLK_SEL_SHIFT,
788 CCM_CSCDR3_CSI_CLK_SEL_MASK,
789 CCM_NO_BUSY_WAIT), /*!< csi mux name */
790} clock_mux_t;
791
792/*!
793 * @brief DIV control names for clock div setting.
794 *
795 * These constants define div control names for clock div setting.\n
796 * - 0:7: REG offset to CCM_BASE in bytes.
797 * - 8:15: Root clock setting bit field shift.
798 * - 16:31: Root clock setting bit field width.
799 */
800typedef enum _clock_div
801{
802 kCLOCK_ArmDiv = CCM_TUPLE(CACRR_OFFSET,
803 CCM_CACRR_ARM_PODF_SHIFT,
804 CCM_CACRR_ARM_PODF_MASK,
805 CCM_CDHIPR_ARM_PODF_BUSY_SHIFT), /*!< core div name */
806
807 kCLOCK_PeriphClk2Div = CCM_TUPLE(CBCDR_OFFSET,
808 CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT,
809 CCM_CBCDR_PERIPH_CLK2_PODF_MASK,
810 CCM_NO_BUSY_WAIT), /*!< periph clock2 div name */
811 kCLOCK_SemcDiv = CCM_TUPLE(CBCDR_OFFSET,
812 CCM_CBCDR_SEMC_PODF_SHIFT,
813 CCM_CBCDR_SEMC_PODF_MASK,
814 CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT), /*!< semc div name */
815 kCLOCK_AhbDiv = CCM_TUPLE(CBCDR_OFFSET,
816 CCM_CBCDR_AHB_PODF_SHIFT,
817 CCM_CBCDR_AHB_PODF_MASK,
818 CCM_CDHIPR_AHB_PODF_BUSY_SHIFT), /*!< ahb div name */
819 kCLOCK_IpgDiv = CCM_TUPLE(
820 CBCDR_OFFSET, CCM_CBCDR_IPG_PODF_SHIFT, CCM_CBCDR_IPG_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< ipg div name */
821
822 kCLOCK_Flexspi2Div = CCM_TUPLE(CBCMR_OFFSET,
823 CCM_CBCMR_FLEXSPI2_PODF_SHIFT,
824 CCM_CBCMR_FLEXSPI2_PODF_MASK,
825 CCM_NO_BUSY_WAIT), /*!< flexspi2 div name */
826 kCLOCK_LpspiDiv = CCM_TUPLE(
827 CBCMR_OFFSET, CCM_CBCMR_LPSPI_PODF_SHIFT, CCM_CBCMR_LPSPI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lpspi div name */
828 kCLOCK_LcdifDiv = CCM_TUPLE(
829 CBCMR_OFFSET, CCM_CBCMR_LCDIF_PODF_SHIFT, CCM_CBCMR_LCDIF_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< lcdif div name */
830
831 kCLOCK_FlexspiDiv = CCM_TUPLE(CSCMR1_OFFSET,
832 CCM_CSCMR1_FLEXSPI_PODF_SHIFT,
833 CCM_CSCMR1_FLEXSPI_PODF_MASK,
834 CCM_NO_BUSY_WAIT), /*!< flexspi div name */
835 kCLOCK_PerclkDiv = CCM_TUPLE(CSCMR1_OFFSET,
836 CCM_CSCMR1_PERCLK_PODF_SHIFT,
837 CCM_CSCMR1_PERCLK_PODF_MASK,
838 CCM_NO_BUSY_WAIT), /*!< perclk div name */
839
840 kCLOCK_CanDiv = CCM_TUPLE(CSCMR2_OFFSET,
841 CCM_CSCMR2_CAN_CLK_PODF_SHIFT,
842 CCM_CSCMR2_CAN_CLK_PODF_MASK,
843 CCM_NO_BUSY_WAIT), /*!< can div name */
844
845 kCLOCK_TraceDiv = CCM_TUPLE(CSCDR1_OFFSET,
846 CCM_CSCDR1_TRACE_PODF_SHIFT,
847 CCM_CSCDR1_TRACE_PODF_MASK,
848 CCM_NO_BUSY_WAIT), /*!< trace div name */
849 kCLOCK_Usdhc2Div = CCM_TUPLE(CSCDR1_OFFSET,
850 CCM_CSCDR1_USDHC2_PODF_SHIFT,
851 CCM_CSCDR1_USDHC2_PODF_MASK,
852 CCM_NO_BUSY_WAIT), /*!< usdhc2 div name */
853 kCLOCK_Usdhc1Div = CCM_TUPLE(CSCDR1_OFFSET,
854 CCM_CSCDR1_USDHC1_PODF_SHIFT,
855 CCM_CSCDR1_USDHC1_PODF_MASK,
856 CCM_NO_BUSY_WAIT), /*!< usdhc1 div name */
857 kCLOCK_UartDiv = CCM_TUPLE(CSCDR1_OFFSET,
858 CCM_CSCDR1_UART_CLK_PODF_SHIFT,
859 CCM_CSCDR1_UART_CLK_PODF_MASK,
860 CCM_NO_BUSY_WAIT), /*!< uart div name */
861
862 kCLOCK_Flexio2Div = CCM_TUPLE(CS1CDR_OFFSET,
863 CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT,
864 CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK,
865 CCM_NO_BUSY_WAIT), /*!< flexio2 pre div name */
866 kCLOCK_Sai3PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
867 CCM_CS1CDR_SAI3_CLK_PRED_SHIFT,
868 CCM_CS1CDR_SAI3_CLK_PRED_MASK,
869 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
870 kCLOCK_Sai3Div = CCM_TUPLE(CS1CDR_OFFSET,
871 CCM_CS1CDR_SAI3_CLK_PODF_SHIFT,
872 CCM_CS1CDR_SAI3_CLK_PODF_MASK,
873 CCM_NO_BUSY_WAIT), /*!< sai3 div name */
874 kCLOCK_Flexio2PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
875 CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT,
876 CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK,
877 CCM_NO_BUSY_WAIT), /*!< sai3 pre div name */
878 kCLOCK_Sai1PreDiv = CCM_TUPLE(CS1CDR_OFFSET,
879 CCM_CS1CDR_SAI1_CLK_PRED_SHIFT,
880 CCM_CS1CDR_SAI1_CLK_PRED_MASK,
881 CCM_NO_BUSY_WAIT), /*!< sai1 pre div name */
882 kCLOCK_Sai1Div = CCM_TUPLE(CS1CDR_OFFSET,
883 CCM_CS1CDR_SAI1_CLK_PODF_SHIFT,
884 CCM_CS1CDR_SAI1_CLK_PODF_MASK,
885 CCM_NO_BUSY_WAIT), /*!< sai1 div name */
886
887 kCLOCK_Sai2PreDiv = CCM_TUPLE(CS2CDR_OFFSET,
888 CCM_CS2CDR_SAI2_CLK_PRED_SHIFT,
889 CCM_CS2CDR_SAI2_CLK_PRED_MASK,
890 CCM_NO_BUSY_WAIT), /*!< sai2 pre div name */
891 kCLOCK_Sai2Div = CCM_TUPLE(CS2CDR_OFFSET,
892 CCM_CS2CDR_SAI2_CLK_PODF_SHIFT,
893 CCM_CS2CDR_SAI2_CLK_PODF_MASK,
894 CCM_NO_BUSY_WAIT), /*!< sai2 div name */
895
896 kCLOCK_Spdif0PreDiv = CCM_TUPLE(CDCDR_OFFSET,
897 CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT,
898 CCM_CDCDR_SPDIF0_CLK_PRED_MASK,
899 CCM_NO_BUSY_WAIT), /*!< spdif pre div name */
900 kCLOCK_Spdif0Div = CCM_TUPLE(CDCDR_OFFSET,
901 CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT,
902 CCM_CDCDR_SPDIF0_CLK_PODF_MASK,
903 CCM_NO_BUSY_WAIT), /*!< spdif div name */
904 kCLOCK_Flexio1PreDiv = CCM_TUPLE(CDCDR_OFFSET,
905 CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT,
906 CCM_CDCDR_FLEXIO1_CLK_PRED_MASK,
907 CCM_NO_BUSY_WAIT), /*!< flexio1 pre div name */
908 kCLOCK_Flexio1Div = CCM_TUPLE(CDCDR_OFFSET,
909 CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT,
910 CCM_CDCDR_FLEXIO1_CLK_PODF_MASK,
911 CCM_NO_BUSY_WAIT), /*!< flexio1 div name */
912
913 kCLOCK_Lpi2cDiv = CCM_TUPLE(CSCDR2_OFFSET,
914 CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT,
915 CCM_CSCDR2_LPI2C_CLK_PODF_MASK,
916 CCM_NO_BUSY_WAIT), /*!< lpi2c div name */
917 kCLOCK_LcdifPreDiv = CCM_TUPLE(CSCDR2_OFFSET,
918 CCM_CSCDR2_LCDIF_PRED_SHIFT,
919 CCM_CSCDR2_LCDIF_PRED_MASK,
920 CCM_NO_BUSY_WAIT), /*!< lcdif pre div name */
921
922 kCLOCK_CsiDiv = CCM_TUPLE(
923 CSCDR3_OFFSET, CCM_CSCDR3_CSI_PODF_SHIFT, CCM_CSCDR3_CSI_PODF_MASK, CCM_NO_BUSY_WAIT), /*!< csi div name */
924
925 kCLOCK_NonePreDiv = CLOCK_ROOT_NONE_PRE_DIV,
926} clock_div_t;
927
928/*! @brief USB clock source definition. */
929typedef enum _clock_usb_src
930{
931 kCLOCK_Usb480M = 0, /*!< Use 480M. */
932 kCLOCK_UsbSrcUnused = (int)0xFFFFFFFFU, /*!< Used when the function does not
933 care the clock source. */
934} clock_usb_src_t;
935
936/*! @brief Source of the USB HS PHY. */
937typedef enum _clock_usb_phy_src
938{
939 kCLOCK_Usbphy480M = 0, /*!< Use 480M. */
940} clock_usb_phy_src_t;
941
942/*!@brief PLL clock source, bypass cloco source also */
943enum _clock_pll_clk_src
944{
945 kCLOCK_PllClkSrc24M = 0U, /*!< Pll clock source 24M */
946 kCLOCK_PllSrcClkPN = 1U, /*!< Pll clock source CLK1_P and CLK1_N */
947};
948
949/*! @brief PLL configuration for ARM */
950typedef struct _clock_arm_pll_config
951{
952 uint32_t loopDivider; /*!< PLL loop divider. Valid range for divider value: 54-108. Fout=Fin*loopDivider/2. */
953 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
954} clock_arm_pll_config_t;
955
956/*! @brief PLL configuration for USB */
957typedef struct _clock_usb_pll_config
958{
959 uint8_t loopDivider; /*!< PLL loop divider.
960 0 - Fout=Fref*20;
961 1 - Fout=Fref*22 */
962 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
963
964} clock_usb_pll_config_t;
965
966/*! @brief PLL configuration for System */
967typedef struct _clock_sys_pll_config
968{
969 uint8_t loopDivider; /*!< PLL loop divider. Intended to be 1 (528M).
970 0 - Fout=Fref*20;
971 1 - Fout=Fref*22 */
972 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
973 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
974 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
975 uint16_t ss_stop; /*!< Stop value to get frequency change. */
976 uint8_t ss_enable; /*!< Enable spread spectrum modulation */
977 uint16_t ss_step; /*!< Step value to get frequency change step. */
978} clock_sys_pll_config_t;
979
980/*! @brief PLL configuration for AUDIO and VIDEO */
981typedef struct _clock_audio_pll_config
982{
983 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
984 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
985 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
986 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
987 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
988} clock_audio_pll_config_t;
989
990/*! @brief PLL configuration for AUDIO and VIDEO */
991typedef struct _clock_video_pll_config
992{
993 uint8_t loopDivider; /*!< PLL loop divider. Valid range for DIV_SELECT divider value: 27~54. */
994 uint8_t postDivider; /*!< Divider after the PLL, should only be 1, 2, 4, 8, 16. */
995 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider.*/
996 uint32_t denominator; /*!< 30 bit denominator of fractional loop divider */
997 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
998
999} clock_video_pll_config_t;
1000
1001/*! @brief PLL configuration for ENET */
1002typedef struct _clock_enet_pll_config
1003{
1004 bool enableClkOutput; /*!< Power on and enable PLL clock output for ENET0 (ref_enetpll0). */
1005 bool enableClkOutput25M; /*!< Power on and enable PLL clock output for ENET2 (ref_enetpll2). */
1006 uint8_t loopDivider; /*!< Controls the frequency of the ENET0 reference clock.
1007 b00 25MHz
1008 b01 50MHz
1009 b10 100MHz (not 50% duty cycle)
1010 b11 125MHz */
1011 uint8_t src; /*!< Pll clock source, reference _clock_pll_clk_src */
1012 bool enableClkOutput1; /*!< Power on and enable PLL clock output for ENET1 (ref_enetpll1). */
1013 uint8_t loopDivider1; /*!< Controls the frequency of the ENET1 reference clock.
1014 b00 25MHz
1015 b01 50MHz
1016 b10 100MHz (not 50% duty cycle)
1017 b11 125MHz */
1018} clock_enet_pll_config_t;
1019
1020/*! @brief PLL name */
1021typedef enum _clock_pll
1022{
1023 kCLOCK_PllArm = CCM_ANALOG_TUPLE(PLL_ARM_OFFSET, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< PLL ARM */
1024 kCLOCK_PllSys = CCM_ANALOG_TUPLE(PLL_SYS_OFFSET, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< PLL SYS */
1025 kCLOCK_PllUsb1 = CCM_ANALOG_TUPLE(PLL_USB1_OFFSET, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< PLL USB1 */
1026 kCLOCK_PllAudio = CCM_ANALOG_TUPLE(PLL_AUDIO_OFFSET, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< PLL Audio */
1027 kCLOCK_PllVideo = CCM_ANALOG_TUPLE(PLL_VIDEO_OFFSET, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< PLL Video */
1028
1029 kCLOCK_PllEnet = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENABLE_SHIFT), /*!< PLL Enet0 */
1030 kCLOCK_PllEnet2 = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET2_REF_EN_SHIFT), /*!< PLL Enet1 */
1031 kCLOCK_PllEnet25M = CCM_ANALOG_TUPLE(PLL_ENET_OFFSET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< PLL Enet2 */
1032
1033 kCLOCK_PllUsb2 = CCM_ANALOG_TUPLE(PLL_USB2_OFFSET, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< PLL USB2 */
1034
1035} clock_pll_t;
1036
1037/*! @brief PLL PFD name */
1038typedef enum _clock_pfd
1039{
1040 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
1041 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
1042 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
1043 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
1044} clock_pfd_t;
1045
1046/*!
1047 * @brief The enumerater of clock output1's clock source, such as USB1 PLL, SYS PLL and so on.
1048 */
1049typedef enum _clock_output1_selection
1050{
1051 kCLOCK_OutputPllUsb1 = 0U, /*!< Selects USB1 PLL clock(Divided by 2) output. */
1052 kCLOCK_OutputPllSys = 1U, /*!< Selects SYS PLL clock(Divided by 2) output. */
1053 kCLOCK_OutputPllVideo = 3U, /*!< Selects Video PLL clock(Divided by 2) output. */
1054 kCLOCK_OutputSemcClk = 5U, /*!< Selects semc clock root output. */
1055 kCLOCK_OutputLcdifPixClk = 0xAU, /*!< Selects Lcdif pix clock root output. */
1056 kCLOCK_OutputAhbClk = 0xBU, /*!< Selects AHB clock root output. */
1057 kCLOCK_OutputIpgClk = 0xCU, /*!< Selects IPG clock root output. */
1058 kCLOCK_OutputPerClk = 0xDU, /*!< Selects PERCLK clock root output. */
1059 kCLOCK_OutputCkilSyncClk = 0xEU, /*!< Selects Ckil clock root output. */
1060 kCLOCK_OutputPll4MainClk = 0xFU, /*!< Selects PLL4 main clock output. */
1061 kCLOCK_DisableClockOutput1 = 0x10U, /*!< Disables CLKO1. */
1062} clock_output1_selection_t;
1063
1064/*!
1065 * @brief The enumerater of clock output2's clock source, such as USDHC1 clock root, LPI2C clock root and so on.
1066 *
1067 */
1068typedef enum _clock_output2_selection
1069{
1070 kCLOCK_OutputUsdhc1Clk = 3U, /*!< Selects USDHC1 clock root output. */
1071 kCLOCK_OutputLpi2cClk = 6U, /*!< Selects LPI2C clock root output. */
1072 kCLOCK_OutputCsiClk = 0xBU, /*!< Selects CSI clock root output. */
1073 kCLOCK_OutputOscClk = 0xEU, /*!< Selects OSC output. */
1074 kCLOCK_OutputUsdhc2Clk = 0x11U, /*!< Selects USDHC2 clock root output. */
1075 kCLOCK_OutputSai1Clk = 0x12U, /*!< Selects SAI1 clock root output. */
1076 kCLOCK_OutputSai2Clk = 0x13U, /*!< Selects SAI2 clock root output. */
1077 kCLOCK_OutputSai3Clk = 0x14U, /*!< Selects SAI3 clock root output. */
1078 kCLOCK_OutputCanClk = 0x17U, /*!< Selects CAN clock root output. */
1079 kCLOCK_OutputFlexspiClk = 0x1BU, /*!< Selects FLEXSPI clock root output. */
1080 kCLOCK_OutputUartClk = 0x1CU, /*!< Selects UART clock root output. */
1081 kCLOCK_OutputSpdif0Clk = 0x1DU, /*!< Selects SPDIF0 clock root output. */
1082 kCLOCK_DisableClockOutput2 = 0x1FU, /*!< Disables CLKO2. */
1083} clock_output2_selection_t;
1084
1085/*!
1086 * @brief The enumerator of clock output's divider.
1087 */
1088typedef enum _clock_output_divider
1089{
1090 kCLOCK_DivideBy1 = 0U, /*!< Output clock divided by 1. */
1091 kCLOCK_DivideBy2, /*!< Output clock divided by 2. */
1092 kCLOCK_DivideBy3, /*!< Output clock divided by 3. */
1093 kCLOCK_DivideBy4, /*!< Output clock divided by 4. */
1094 kCLOCK_DivideBy5, /*!< Output clock divided by 5. */
1095 kCLOCK_DivideBy6, /*!< Output clock divided by 6. */
1096 kCLOCK_DivideBy7, /*!< Output clock divided by 7. */
1097 kCLOCK_DivideBy8, /*!< Output clock divided by 8. */
1098} clock_output_divider_t;
1099
1100/*!
1101 * @brief The enumerator of clock root.
1102 */
1103typedef enum _clock_root
1104{
1105 kCLOCK_Usdhc1ClkRoot = 0U, /*!< USDHC1 clock root. */
1106 kCLOCK_Usdhc2ClkRoot, /*!< USDHC2 clock root. */
1107 kCLOCK_FlexspiClkRoot, /*!< FLEXSPI clock root. */
1108 kCLOCK_Flexspi2ClkRoot, /*!< FLEXSPI2 clock root. */
1109 kCLOCK_CsiClkRoot, /*!< CSI clock root. */
1110 kCLOCK_LpspiClkRoot, /*!< LPSPI clock root. */
1111 kCLOCK_TraceClkRoot, /*!< Trace clock root. */
1112 kCLOCK_Sai1ClkRoot, /*!< SAI1 clock root. */
1113 kCLOCK_Sai2ClkRoot, /*!< SAI2 clock root. */
1114 kCLOCK_Sai3ClkRoot, /*!< SAI3 clock root. */
1115 kCLOCK_Lpi2cClkRoot, /*!< LPI2C clock root. */
1116 kCLOCK_CanClkRoot, /*!< CAN clock root. */
1117 kCLOCK_UartClkRoot, /*!< UART clock root. */
1118 kCLOCK_LcdifClkRoot, /*!< LCD clock root. */
1119 kCLOCK_SpdifClkRoot, /*!< SPDIF clock root. */
1120 kCLOCK_Flexio1ClkRoot, /*!< FLEXIO1 clock root. */
1121 kCLOCK_Flexio2ClkRoot, /*!< FLEXIO2 clock root. */
1122} clock_root_t;
1123
1124/*******************************************************************************
1125 * API
1126 ******************************************************************************/
1127
1128#if defined(__cplusplus)
1129extern "C" {
1130#endif /* __cplusplus */
1131
1132/*!
1133 * @brief Set CCM MUX node to certain value.
1134 *
1135 * @param mux Which mux node to set, see \ref clock_mux_t.
1136 * @param value Clock mux value to set, different mux has different value range.
1137 */
1138static inline void CLOCK_SetMux(clock_mux_t mux, uint32_t value)
1139{
1140 uint32_t busyShift;
1141
1142 busyShift = (uint32_t)CCM_TUPLE_BUSY_SHIFT(mux);
1143 CCM_TUPLE_REG(CCM, mux) = (CCM_TUPLE_REG(CCM, mux) & (~CCM_TUPLE_MASK(mux))) |
1144 (((uint32_t)((value) << CCM_TUPLE_SHIFT(mux))) & CCM_TUPLE_MASK(mux));
1145
1146 assert(busyShift <= CCM_NO_BUSY_WAIT);
1147
1148 /* Clock switch need Handshake? */
1149 if (CCM_NO_BUSY_WAIT != busyShift)
1150 {
1151 /* Wait until CCM internal handshake finish. */
1152 while ((CCM->CDHIPR & ((1UL << busyShift))) != 0UL)
1153 {
1154 }
1155 }
1156}
1157
1158/*!
1159 * @brief Get CCM MUX value.
1160 *
1161 * @param mux Which mux node to get, see \ref clock_mux_t.
1162 * @return Clock mux value.
1163 */
1164static inline uint32_t CLOCK_GetMux(clock_mux_t mux)
1165{
1166 return (((uint32_t)(CCM_TUPLE_REG(CCM, mux) & CCM_TUPLE_MASK(mux))) >> CCM_TUPLE_SHIFT(mux));
1167}
1168
1169/*!
1170 * @brief Set CCM DIV node to certain value.
1171 *
1172 * @param divider Which div node to set, see \ref clock_div_t.
1173 * @param value Clock div value to set, different divider has different value range.
1174 */
1175static inline void CLOCK_SetDiv(clock_div_t divider, uint32_t value)
1176{
1177 uint32_t busyShift;
1178
1179 busyShift = CCM_TUPLE_BUSY_SHIFT(divider);
1180 CCM_TUPLE_REG(CCM, divider) = (CCM_TUPLE_REG(CCM, divider) & (~CCM_TUPLE_MASK(divider))) |
1181 (((uint32_t)((value) << CCM_TUPLE_SHIFT(divider))) & CCM_TUPLE_MASK(divider));
1182
1183 assert(busyShift <= CCM_NO_BUSY_WAIT);
1184
1185 /* Clock switch need Handshake? */
1186 if (CCM_NO_BUSY_WAIT != busyShift)
1187 {
1188 /* Wait until CCM internal handshake finish. */
1189 while ((CCM->CDHIPR & ((uint32_t)(1UL << busyShift))) != 0UL)
1190 {
1191 }
1192 }
1193}
1194
1195/*!
1196 * @brief Get CCM DIV node value.
1197 *
1198 * @param divider Which div node to get, see \ref clock_div_t.
1199 */
1200static inline uint32_t CLOCK_GetDiv(clock_div_t divider)
1201{
1202 return ((uint32_t)(CCM_TUPLE_REG(CCM, divider) & CCM_TUPLE_MASK(divider)) >> CCM_TUPLE_SHIFT(divider));
1203}
1204
1205/*!
1206 * @brief Control the clock gate for specific IP.
1207 *
1208 * @param name Which clock to enable, see \ref clock_ip_name_t.
1209 * @param value Clock gate value to set, see \ref clock_gate_value_t.
1210 */
1211static inline void CLOCK_ControlGate(clock_ip_name_t name, clock_gate_value_t value)
1212{
1213 uint32_t index = ((uint32_t)name) >> 8U;
1214 uint32_t shift = ((uint32_t)name) & 0x1FU;
1215 volatile uint32_t *reg;
1216
1217 assert(index <= 7UL);
1218
1219 reg = (volatile uint32_t *)(&(((volatile uint32_t *)&CCM->CCGR0)[index]));
1220 *reg = ((*reg) & ~((uint32_t)(3UL << shift))) | (((uint32_t)value) << shift);
1221}
1222
1223/*!
1224 * @brief Enable the clock for specific IP.
1225 *
1226 * @param name Which clock to enable, see \ref clock_ip_name_t.
1227 */
1228static inline void CLOCK_EnableClock(clock_ip_name_t name)
1229{
1230 CLOCK_ControlGate(name, kCLOCK_ClockNeededRunWait);
1231}
1232
1233/*!
1234 * @brief Disable the clock for specific IP.
1235 *
1236 * @param name Which clock to disable, see \ref clock_ip_name_t.
1237 */
1238static inline void CLOCK_DisableClock(clock_ip_name_t name)
1239{
1240 CLOCK_ControlGate(name, kCLOCK_ClockNotNeeded);
1241}
1242
1243/*!
1244 * @brief Setting the low power mode that system will enter on next assertion of dsm_request signal.
1245 *
1246 * @param mode Which mode to enter, see \ref clock_mode_t.
1247 */
1248static inline void CLOCK_SetMode(clock_mode_t mode)
1249{
1250 CCM->CLPCR = (CCM->CLPCR & ~CCM_CLPCR_LPM_MASK) | CCM_CLPCR_LPM((uint32_t)mode);
1251}
1252
1253/*!
1254 * @brief Gets the OSC clock frequency.
1255 *
1256 * This function will return the external XTAL OSC frequency if it is selected as the source of OSC,
1257 * otherwise internal 24MHz RC OSC frequency will be returned.
1258 *
1259 * @return Clock frequency; If the clock is invalid, returns 0.
1260 */
1261static inline uint32_t CLOCK_GetOscFreq(void)
1262{
1263 return ((XTALOSC24M->LOWPWR_CTRL & XTALOSC24M_LOWPWR_CTRL_OSC_SEL_MASK) != 0UL) ? 24000000UL : g_xtalFreq;
1264}
1265
1266/*!
1267 * @brief Gets the AHB clock frequency.
1268 *
1269 * @return The AHB clock frequency value in hertz.
1270 */
1271uint32_t CLOCK_GetAhbFreq(void);
1272
1273/*!
1274 * @brief Gets the SEMC clock frequency.
1275 *
1276 * @return The SEMC clock frequency value in hertz.
1277 */
1278uint32_t CLOCK_GetSemcFreq(void);
1279
1280/*!
1281 * @brief Gets the IPG clock frequency.
1282 *
1283 * @return The IPG clock frequency value in hertz.
1284 */
1285uint32_t CLOCK_GetIpgFreq(void);
1286
1287/*!
1288 * @brief Gets the PER clock frequency.
1289 *
1290 * @return The PER clock frequency value in hertz.
1291 */
1292uint32_t CLOCK_GetPerClkFreq(void);
1293
1294/*!
1295 * @brief Gets the clock frequency for a specific clock name.
1296 *
1297 * This function checks the current clock configurations and then calculates
1298 * the clock frequency for a specific clock name defined in clock_name_t.
1299 *
1300 * @param name Clock names defined in clock_name_t
1301 * @return Clock frequency value in hertz
1302 */
1303uint32_t CLOCK_GetFreq(clock_name_t name);
1304
1305/*!
1306 * @brief Get the CCM CPU/core/system frequency.
1307 *
1308 * @return Clock frequency; If the clock is invalid, returns 0.
1309 */
1310static inline uint32_t CLOCK_GetCpuClkFreq(void)
1311{
1312 return CLOCK_GetFreq(kCLOCK_CpuClk);
1313}
1314
1315/*!
1316 * @brief Gets the frequency of selected clock root.
1317 *
1318 * @param clockRoot The clock root used to get the frequency, please refer to @ref clock_root_t.
1319 * @return The frequency of selected clock root.
1320 */
1321uint32_t CLOCK_GetClockRootFreq(clock_root_t clockRoot);
1322
1323/*!
1324 * @name OSC operations
1325 * @{
1326 */
1327
1328/*!
1329 * @brief Initialize the external 24MHz clock.
1330 *
1331 * This function supports two modes:
1332 * 1. Use external crystal oscillator.
1333 * 2. Bypass the external crystal oscillator, using input source clock directly.
1334 *
1335 * After this function, please call CLOCK_SetXtal0Freq to inform clock driver
1336 * the external clock frequency.
1337 *
1338 * @param bypassXtalOsc Pass in true to bypass the external crystal oscillator.
1339 * @note This device does not support bypass external crystal oscillator, so
1340 * the input parameter should always be false.
1341 */
1342void CLOCK_InitExternalClk(bool bypassXtalOsc);
1343
1344/*!
1345 * @brief Deinitialize the external 24MHz clock.
1346 *
1347 * This function disables the external 24MHz clock.
1348 *
1349 * After this function, please call CLOCK_SetXtal0Freq to set external clock
1350 * frequency to 0.
1351 */
1352void CLOCK_DeinitExternalClk(void);
1353
1354/*!
1355 * @brief Switch the OSC.
1356 *
1357 * This function switches the OSC source for SoC.
1358 *
1359 * @param osc OSC source to switch to.
1360 */
1361void CLOCK_SwitchOsc(clock_osc_t osc);
1362
1363/*!
1364 * @brief Gets the RTC clock frequency.
1365 *
1366 * @return Clock frequency; If the clock is invalid, returns 0.
1367 */
1368static inline uint32_t CLOCK_GetRtcFreq(void)
1369{
1370 return 32768U;
1371}
1372
1373/*!
1374 * @brief Set the XTAL (24M OSC) frequency based on board setting.
1375 *
1376 * @param freq The XTAL input clock frequency in Hz.
1377 */
1378static inline void CLOCK_SetXtalFreq(uint32_t freq)
1379{
1380 g_xtalFreq = freq;
1381}
1382
1383/*!
1384 * @brief Set the RTC XTAL (32K OSC) frequency based on board setting.
1385 *
1386 * @param freq The RTC XTAL input clock frequency in Hz.
1387 */
1388static inline void CLOCK_SetRtcXtalFreq(uint32_t freq)
1389{
1390 g_rtcXtalFreq = freq;
1391}
1392
1393/*!
1394 * @brief Initialize the RC oscillator 24MHz clock.
1395 */
1396void CLOCK_InitRcOsc24M(void);
1397
1398/*!
1399 * @brief Power down the RCOSC 24M clock.
1400 */
1401void CLOCK_DeinitRcOsc24M(void);
1402/* @} */
1403
1404/*! @brief Enable USB HS clock.
1405 *
1406 * This function only enables the access to USB HS prepheral, upper layer
1407 * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1408 * clock to use USB HS.
1409 *
1410 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1411 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1412 * @retval true The clock is set successfully.
1413 * @retval false The clock source is invalid to get proper USB HS clock.
1414 */
1415bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
1416
1417/*! @brief Enable USB HS clock.
1418 *
1419 * This function only enables the access to USB HS prepheral, upper layer
1420 * should first call the CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
1421 * clock to use USB HS.
1422 *
1423 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
1424 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
1425 * @retval true The clock is set successfully.
1426 * @retval false The clock source is invalid to get proper USB HS clock.
1427 */
1428bool CLOCK_EnableUsbhs1Clock(clock_usb_src_t src, uint32_t freq);
1429
1430/* @} */
1431
1432/*!
1433 * @name PLL/PFD operations
1434 * @{
1435 */
1436/*!
1437 * @brief PLL bypass setting
1438 *
1439 * @param base CCM_ANALOG base pointer.
1440 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1441 * @param bypass Bypass the PLL.
1442 * - true: Bypass the PLL.
1443 * - false:Not bypass the PLL.
1444 */
1445static inline void CLOCK_SetPllBypass(CCM_ANALOG_Type *base, clock_pll_t pll, bool bypass)
1446{
1447 if (bypass)
1448 {
1449 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 4U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1450 }
1451 else
1452 {
1453 CCM_ANALOG_TUPLE_REG_OFF(base, pll, 8U) = 1UL << CCM_ANALOG_PLL_BYPASS_SHIFT;
1454 }
1455}
1456
1457/*!
1458 * @brief Check if PLL is bypassed
1459 *
1460 * @param base CCM_ANALOG base pointer.
1461 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1462 * @return PLL bypass status.
1463 * - true: The PLL is bypassed.
1464 * - false: The PLL is not bypassed.
1465 */
1466static inline bool CLOCK_IsPllBypassed(CCM_ANALOG_Type *base, clock_pll_t pll)
1467{
1468 return (bool)(CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_PLL_BYPASS_SHIFT));
1469}
1470
1471/*!
1472 * @brief Check if PLL is enabled
1473 *
1474 * @param base CCM_ANALOG base pointer.
1475 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1476 * @return PLL bypass status.
1477 * - true: The PLL is enabled.
1478 * - false: The PLL is not enabled.
1479 */
1480static inline bool CLOCK_IsPllEnabled(CCM_ANALOG_Type *base, clock_pll_t pll)
1481{
1482 return ((CCM_ANALOG_TUPLE_REG(base, pll) & (1UL << CCM_ANALOG_TUPLE_SHIFT(pll))) != 0U);
1483}
1484
1485/*!
1486 * @brief PLL bypass clock source setting.
1487 * Note: change the bypass clock source also change the pll reference clock source.
1488 *
1489 * @param base CCM_ANALOG base pointer.
1490 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1491 * @param src Bypass clock source, reference _clock_pll_bypass_clk_src.
1492 */
1493static inline void CLOCK_SetPllBypassRefClkSrc(CCM_ANALOG_Type *base, clock_pll_t pll, uint32_t src)
1494{
1495 CCM_ANALOG_TUPLE_REG(base, pll) |= (CCM_ANALOG_TUPLE_REG(base, pll) & (~CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK)) | src;
1496}
1497
1498/*!
1499 * @brief Get PLL bypass clock value, it is PLL reference clock actually.
1500 * If CLOCK1_P,CLOCK1_N is choose as the pll bypass clock source, please implement the CLKPN_FREQ define, otherwise 0
1501 * will be returned.
1502 * @param base CCM_ANALOG base pointer.
1503 * @param pll PLL control name (see @ref ccm_analog_pll_control_t enumeration)
1504 * @retval bypass reference clock frequency value.
1505 */
1506static inline uint32_t CLOCK_GetPllBypassRefClk(CCM_ANALOG_Type *base, clock_pll_t pll)
1507{
1508 return (((CCM_ANALOG_TUPLE_REG(base, pll) & CCM_ANALOG_PLL_BYPASS_CLK_SRC_MASK) >>
1509 CCM_ANALOG_PLL_BYPASS_CLK_SRC_SHIFT) == (uint32_t)kCLOCK_PllClkSrc24M) ?
1510 CLOCK_GetOscFreq() :
1511 CLKPN_FREQ;
1512}
1513
1514/*!
1515 * @brief Initialize the ARM PLL.
1516 *
1517 * This function initialize the ARM PLL with specific settings
1518 *
1519 * @param config configuration to set to PLL.
1520 */
1521void CLOCK_InitArmPll(const clock_arm_pll_config_t *config);
1522
1523/*!
1524 * @brief De-initialize the ARM PLL.
1525 */
1526void CLOCK_DeinitArmPll(void);
1527
1528/*!
1529 * @brief Initialize the System PLL.
1530 *
1531 * This function initializes the System PLL with specific settings
1532 *
1533 * @param config Configuration to set to PLL.
1534 */
1535void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1536
1537/*!
1538 * @brief De-initialize the System PLL.
1539 */
1540void CLOCK_DeinitSysPll(void);
1541
1542/*!
1543 * @brief Initialize the USB1 PLL.
1544 *
1545 * This function initializes the USB1 PLL with specific settings
1546 *
1547 * @param config Configuration to set to PLL.
1548 */
1549void CLOCK_InitUsb1Pll(const clock_usb_pll_config_t *config);
1550
1551/*!
1552 * @brief Deinitialize the USB1 PLL.
1553 */
1554void CLOCK_DeinitUsb1Pll(void);
1555
1556/*!
1557 * @brief Initialize the USB2 PLL.
1558 *
1559 * This function initializes the USB2 PLL with specific settings
1560 *
1561 * @param config Configuration to set to PLL.
1562 */
1563void CLOCK_InitUsb2Pll(const clock_usb_pll_config_t *config);
1564
1565/*!
1566 * @brief Deinitialize the USB2 PLL.
1567 */
1568void CLOCK_DeinitUsb2Pll(void);
1569
1570/*!
1571 * @brief Initializes the Audio PLL.
1572 *
1573 * This function initializes the Audio PLL with specific settings
1574 *
1575 * @param config Configuration to set to PLL.
1576 */
1577void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1578
1579/*!
1580 * @brief De-initialize the Audio PLL.
1581 */
1582void CLOCK_DeinitAudioPll(void);
1583
1584/*!
1585 * @brief Initialize the video PLL.
1586 *
1587 * This function configures the Video PLL with specific settings
1588 *
1589 * @param config configuration to set to PLL.
1590 */
1591void CLOCK_InitVideoPll(const clock_video_pll_config_t *config);
1592
1593/*!
1594 * @brief De-initialize the Video PLL.
1595 */
1596void CLOCK_DeinitVideoPll(void);
1597/*!
1598 * @brief Initialize the ENET PLL.
1599 *
1600 * This function initializes the ENET PLL with specific settings.
1601 *
1602 * @param config Configuration to set to PLL.
1603 */
1604void CLOCK_InitEnetPll(const clock_enet_pll_config_t *config);
1605
1606/*!
1607 * @brief Deinitialize the ENET PLL.
1608 *
1609 * This function disables the ENET PLL.
1610 */
1611void CLOCK_DeinitEnetPll(void);
1612
1613/*!
1614 * @brief Get current PLL output frequency.
1615 *
1616 * This function get current output frequency of specific PLL
1617 *
1618 * @param pll pll name to get frequency.
1619 * @return The PLL output frequency in hertz.
1620 */
1621uint32_t CLOCK_GetPllFreq(clock_pll_t pll);
1622
1623/*!
1624 * @brief Initialize the System PLL PFD.
1625 *
1626 * This function initializes the System PLL PFD. During new value setting,
1627 * the clock output is disabled to prevent glitch.
1628 *
1629 * @param pfd Which PFD clock to enable.
1630 * @param pfdFrac The PFD FRAC value.
1631 * @note It is recommended that PFD settings are kept between 12-35.
1632 */
1633void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t pfdFrac);
1634
1635/*!
1636 * @brief De-initialize the System PLL PFD.
1637 *
1638 * This function disables the System PLL PFD.
1639 *
1640 * @param pfd Which PFD clock to disable.
1641 */
1642void CLOCK_DeinitSysPfd(clock_pfd_t pfd);
1643
1644/*!
1645 * @brief Initialize the USB1 PLL PFD.
1646 *
1647 * This function initializes the USB1 PLL PFD. During new value setting,
1648 * the clock output is disabled to prevent glitch.
1649 *
1650 * @param pfd Which PFD clock to enable.
1651 * @param pfdFrac The PFD FRAC value.
1652 * @note It is recommended that PFD settings are kept between 12-35.
1653 */
1654void CLOCK_InitUsb1Pfd(clock_pfd_t pfd, uint8_t pfdFrac);
1655
1656/*!
1657 * @brief De-initialize the USB1 PLL PFD.
1658 *
1659 * This function disables the USB1 PLL PFD.
1660 *
1661 * @param pfd Which PFD clock to disable.
1662 */
1663void CLOCK_DeinitUsb1Pfd(clock_pfd_t pfd);
1664
1665/*!
1666 * @brief Get current System PLL PFD output frequency.
1667 *
1668 * This function get current output frequency of specific System PLL PFD
1669 *
1670 * @param pfd pfd name to get frequency.
1671 * @return The PFD output frequency in hertz.
1672 */
1673uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
1674
1675/*!
1676 * @brief Get current USB1 PLL PFD output frequency.
1677 *
1678 * This function get current output frequency of specific USB1 PLL PFD
1679 *
1680 * @param pfd pfd name to get frequency.
1681 * @return The PFD output frequency in hertz.
1682 */
1683uint32_t CLOCK_GetUsb1PfdFreq(clock_pfd_t pfd);
1684
1685/*! @brief Enable USB HS PHY PLL clock.
1686 *
1687 * This function enables the internal 480MHz USB PHY PLL clock.
1688 *
1689 * @param src USB HS PHY PLL clock source.
1690 * @param freq The frequency specified by src.
1691 * @retval true The clock is set successfully.
1692 * @retval false The clock source is invalid to get proper USB HS clock.
1693 */
1694bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1695
1696/*! @brief Disable USB HS PHY PLL clock.
1697 *
1698 * This function disables USB HS PHY PLL clock.
1699 */
1700void CLOCK_DisableUsbhs0PhyPllClock(void);
1701
1702/*! @brief Enable USB HS PHY PLL clock.
1703 *
1704 * This function enables the internal 480MHz USB PHY PLL clock.
1705 *
1706 * @param src USB HS PHY PLL clock source.
1707 * @param freq The frequency specified by src.
1708 * @retval true The clock is set successfully.
1709 * @retval false The clock source is invalid to get proper USB HS clock.
1710 */
1711bool CLOCK_EnableUsbhs1PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
1712
1713/*! @brief Disable USB HS PHY PLL clock.
1714 *
1715 * This function disables USB HS PHY PLL clock.
1716 */
1717void CLOCK_DisableUsbhs1PhyPllClock(void);
1718
1719/* @} */
1720
1721/*!
1722 * @name Clock Output Inferfaces
1723 * @{
1724 */
1725
1726/*!
1727 * @brief Set the clock source and the divider of the clock output1.
1728 *
1729 * @param selection The clock source to be output, please refer to @ref clock_output1_selection_t.
1730 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1731 */
1732void CLOCK_SetClockOutput1(clock_output1_selection_t selection, clock_output_divider_t divider);
1733
1734/*!
1735 * @brief Set the clock source and the divider of the clock output2.
1736 *
1737 * @param selection The clock source to be output, please refer to @ref clock_output2_selection_t.
1738 * @param divider The divider of the output clock signal, please refer to @ref clock_output_divider_t.
1739 */
1740void CLOCK_SetClockOutput2(clock_output2_selection_t selection, clock_output_divider_t divider);
1741
1742/*!
1743 * @brief Get the frequency of clock output1 clock signal.
1744 *
1745 * @return The frequency of clock output1 clock signal.
1746 */
1747uint32_t CLOCK_GetClockOutCLKO1Freq(void);
1748
1749/*!
1750 * @brief Get the frequency of clock output2 clock signal.
1751 *
1752 * @return The frequency of clock output2 clock signal.
1753 */
1754uint32_t CLOCK_GetClockOutClkO2Freq(void);
1755
1756/*! @} */
1757
1758#if defined(__cplusplus)
1759}
1760#endif /* __cplusplus */
1761
1762/*! @} */
1763
1764#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 21:12:19 +0100