diff options
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1062/drivers/fsl_iomuxc.h')
| -rw-r--r-- | lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1062/drivers/fsl_iomuxc.h | 1419 |
1 files changed, 1419 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1062/drivers/fsl_iomuxc.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1062/drivers/fsl_iomuxc.h new file mode 100644 index 000000000..40910c268 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1062/drivers/fsl_iomuxc.h | |||
| @@ -0,0 +1,1419 @@ | |||
| 1 | /* | ||
| 2 | * Copyright 2016 Freescale Semiconductor, Inc. | ||
| 3 | * Copyright 2016-2020 NXP | ||
| 4 | * All rights reserved. | ||
| 5 | * | ||
| 6 | * SPDX-License-Identifier: BSD-3-Clause | ||
| 7 | */ | ||
| 8 | |||
| 9 | #ifndef _FSL_IOMUXC_H_ | ||
| 10 | #define _FSL_IOMUXC_H_ | ||
| 11 | |||
| 12 | #include "fsl_common.h" | ||
| 13 | |||
| 14 | /*! | ||
| 15 | * @addtogroup iomuxc_driver | ||
| 16 | * @{ | ||
| 17 | */ | ||
| 18 | |||
| 19 | /*! @file */ | ||
| 20 | |||
| 21 | /******************************************************************************* | ||
| 22 | * Definitions | ||
| 23 | ******************************************************************************/ | ||
| 24 | /* Component ID definition, used by tools. */ | ||
| 25 | #ifndef FSL_COMPONENT_ID | ||
| 26 | #define FSL_COMPONENT_ID "platform.drivers.iomuxc" | ||
| 27 | #endif | ||
| 28 | |||
| 29 | /*! @name Driver version */ | ||
| 30 | /*@{*/ | ||
| 31 | /*! @brief IOMUXC driver version 2.0.3. */ | ||
| 32 | #define FSL_IOMUXC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) | ||
| 33 | /*@}*/ | ||
| 34 | |||
| 35 | /*! | ||
| 36 | * @name Pin function ID | ||
| 37 | * The pin function ID is a tuple of \<muxRegister muxMode inputRegister inputDaisy configRegister\> | ||
| 38 | * | ||
| 39 | * @{ | ||
| 40 | */ | ||
| 41 | #define IOMUXC_SNVS_WAKEUP_GPIO5_IO00 0x400A8000U, 0x5U, 0, 0, 0x400A8018U | ||
| 42 | #define IOMUXC_SNVS_WAKEUP_NMI_GLUE_NMI 0x400A8000U, 0x7U, 0x401F8568U, 0x1U, 0x400A8018U | ||
| 43 | |||
| 44 | #define IOMUXC_SNVS_PMIC_ON_REQ_SNVS_LP_PMIC_ON_REQ 0x400A8004U, 0x0U, 0, 0, 0x400A801CU | ||
| 45 | #define IOMUXC_SNVS_PMIC_ON_REQ_GPIO5_IO01 0x400A8004U, 0x5U, 0, 0, 0x400A801CU | ||
| 46 | |||
| 47 | #define IOMUXC_SNVS_PMIC_STBY_REQ_CCM_PMIC_VSTBY_REQ 0x400A8008U, 0x0U, 0, 0, 0x400A8020U | ||
| 48 | #define IOMUXC_SNVS_PMIC_STBY_REQ_GPIO5_IO02 0x400A8008U, 0x5U, 0, 0, 0x400A8020U | ||
| 49 | |||
| 50 | #define IOMUXC_SNVS_TEST_MODE 0, 0, 0, 0, 0x400A800CU | ||
| 51 | |||
| 52 | #define IOMUXC_SNVS_POR_B 0, 0, 0, 0, 0x400A8010U | ||
| 53 | |||
| 54 | #define IOMUXC_SNVS_ONOFF 0, 0, 0, 0, 0x400A8014U | ||
| 55 | |||
| 56 | #define IOMUXC_GPIO_EMC_00_SEMC_DATA00 0x401F8014U, 0x0U, 0, 0, 0x401F8204U | ||
| 57 | #define IOMUXC_GPIO_EMC_00_FLEXPWM4_PWMA00 0x401F8014U, 0x1U, 0x401F8494U, 0x0U, 0x401F8204U | ||
| 58 | #define IOMUXC_GPIO_EMC_00_LPSPI2_SCK 0x401F8014U, 0x2U, 0x401F8500U, 0x1U, 0x401F8204U | ||
| 59 | #define IOMUXC_GPIO_EMC_00_XBAR1_XBAR_IN02 0x401F8014U, 0x3U, 0x401F860CU, 0x0U, 0x401F8204U | ||
| 60 | #define IOMUXC_GPIO_EMC_00_FLEXIO1_FLEXIO00 0x401F8014U, 0x4U, 0, 0, 0x401F8204U | ||
| 61 | #define IOMUXC_GPIO_EMC_00_GPIO4_IO00 0x401F8014U, 0x5U, 0, 0, 0x401F8204U | ||
| 62 | |||
| 63 | #define IOMUXC_GPIO_EMC_01_SEMC_DATA01 0x401F8018U, 0x0U, 0, 0, 0x401F8208U | ||
| 64 | #define IOMUXC_GPIO_EMC_01_FLEXPWM4_PWMB00 0x401F8018U, 0x1U, 0, 0, 0x401F8208U | ||
| 65 | #define IOMUXC_GPIO_EMC_01_LPSPI2_PCS0 0x401F8018U, 0x2U, 0x401F84FCU, 0x1U, 0x401F8208U | ||
| 66 | #define IOMUXC_GPIO_EMC_01_XBAR1_IN03 0x401F8018U, 0x3U, 0x401F8610U, 0x0U, 0x401F8208U | ||
| 67 | #define IOMUXC_GPIO_EMC_01_FLEXIO1_FLEXIO01 0x401F8018U, 0x4U, 0, 0, 0x401F8208U | ||
| 68 | #define IOMUXC_GPIO_EMC_01_GPIO4_IO01 0x401F8018U, 0x5U, 0, 0, 0x401F8208U | ||
| 69 | |||
| 70 | #define IOMUXC_GPIO_EMC_02_SEMC_DATA02 0x401F801CU, 0x0U, 0, 0, 0x401F820CU | ||
| 71 | #define IOMUXC_GPIO_EMC_02_FLEXPWM4_PWMA01 0x401F801CU, 0x1U, 0x401F8498U, 0x0U, 0x401F820CU | ||
| 72 | #define IOMUXC_GPIO_EMC_02_LPSPI2_SDO 0x401F801CU, 0x2U, 0x401F8508U, 0x1U, 0x401F820CU | ||
| 73 | #define IOMUXC_GPIO_EMC_02_XBAR1_INOUT04 0x401F801CU, 0x3U, 0x401F8614U, 0x0U, 0x401F820CU | ||
| 74 | #define IOMUXC_GPIO_EMC_02_FLEXIO1_FLEXIO02 0x401F801CU, 0x4U, 0, 0, 0x401F820CU | ||
| 75 | #define IOMUXC_GPIO_EMC_02_GPIO4_IO02 0x401F801CU, 0x5U, 0, 0, 0x401F820CU | ||
| 76 | |||
| 77 | #define IOMUXC_GPIO_EMC_03_SEMC_DATA03 0x401F8020U, 0x0U, 0, 0, 0x401F8210U | ||
| 78 | #define IOMUXC_GPIO_EMC_03_FLEXPWM4_PWMB01 0x401F8020U, 0x1U, 0, 0, 0x401F8210U | ||
| 79 | #define IOMUXC_GPIO_EMC_03_LPSPI2_SDI 0x401F8020U, 0x2U, 0x401F8504U, 0x1U, 0x401F8210U | ||
| 80 | #define IOMUXC_GPIO_EMC_03_XBAR1_INOUT05 0x401F8020U, 0x3U, 0x401F8618U, 0x0U, 0x401F8210U | ||
| 81 | #define IOMUXC_GPIO_EMC_03_FLEXIO1_FLEXIO03 0x401F8020U, 0x4U, 0, 0, 0x401F8210U | ||
| 82 | #define IOMUXC_GPIO_EMC_03_GPIO4_IO03 0x401F8020U, 0x5U, 0, 0, 0x401F8210U | ||
| 83 | |||
| 84 | #define IOMUXC_GPIO_EMC_04_SEMC_DATA04 0x401F8024U, 0x0U, 0, 0, 0x401F8214U | ||
| 85 | #define IOMUXC_GPIO_EMC_04_FLEXPWM4_PWMA02 0x401F8024U, 0x1U, 0x401F849CU, 0x0U, 0x401F8214U | ||
| 86 | #define IOMUXC_GPIO_EMC_04_SAI2_TX_DATA 0x401F8024U, 0x2U, 0, 0, 0x401F8214U | ||
| 87 | #define IOMUXC_GPIO_EMC_04_XBAR1_INOUT06 0x401F8024U, 0x3U, 0x401F861CU, 0x0U, 0x401F8214U | ||
| 88 | #define IOMUXC_GPIO_EMC_04_FLEXIO1_FLEXIO04 0x401F8024U, 0x4U, 0, 0, 0x401F8214U | ||
| 89 | #define IOMUXC_GPIO_EMC_04_GPIO4_IO04 0x401F8024U, 0x5U, 0, 0, 0x401F8214U | ||
| 90 | |||
| 91 | #define IOMUXC_GPIO_EMC_05_SEMC_DATA05 0x401F8028U, 0x0U, 0, 0, 0x401F8218U | ||
| 92 | #define IOMUXC_GPIO_EMC_05_FLEXPWM4_PWMB02 0x401F8028U, 0x1U, 0, 0, 0x401F8218U | ||
| 93 | #define IOMUXC_GPIO_EMC_05_SAI2_TX_SYNC 0x401F8028U, 0x2U, 0x401F85C4U, 0x0U, 0x401F8218U | ||
| 94 | #define IOMUXC_GPIO_EMC_05_XBAR1_INOUT07 0x401F8028U, 0x3U, 0x401F8620U, 0x0U, 0x401F8218U | ||
| 95 | #define IOMUXC_GPIO_EMC_05_FLEXIO1_FLEXIO05 0x401F8028U, 0x4U, 0, 0, 0x401F8218U | ||
| 96 | #define IOMUXC_GPIO_EMC_05_GPIO4_IO05 0x401F8028U, 0x5U, 0, 0, 0x401F8218U | ||
| 97 | |||
| 98 | #define IOMUXC_GPIO_EMC_06_SEMC_DATA06 0x401F802CU, 0x0U, 0, 0, 0x401F821CU | ||
| 99 | #define IOMUXC_GPIO_EMC_06_FLEXPWM2_PWMA00 0x401F802CU, 0x1U, 0x401F8478U, 0x0U, 0x401F821CU | ||
| 100 | #define IOMUXC_GPIO_EMC_06_SAI2_TX_BCLK 0x401F802CU, 0x2U, 0x401F85C0U, 0x0U, 0x401F821CU | ||
| 101 | #define IOMUXC_GPIO_EMC_06_XBAR1_INOUT08 0x401F802CU, 0x3U, 0x401F8624U, 0x0U, 0x401F821CU | ||
| 102 | #define IOMUXC_GPIO_EMC_06_FLEXIO1_FLEXIO06 0x401F802CU, 0x4U, 0, 0, 0x401F821CU | ||
| 103 | #define IOMUXC_GPIO_EMC_06_GPIO4_IO06 0x401F802CU, 0x5U, 0, 0, 0x401F821CU | ||
| 104 | |||
| 105 | #define IOMUXC_GPIO_EMC_07_SEMC_DATA07 0x401F8030U, 0x0U, 0, 0, 0x401F8220U | ||
| 106 | #define IOMUXC_GPIO_EMC_07_FLEXPWM2_PWMB00 0x401F8030U, 0x1U, 0x401F8488U, 0x0U, 0x401F8220U | ||
| 107 | #define IOMUXC_GPIO_EMC_07_SAI2_MCLK 0x401F8030U, 0x2U, 0x401F85B0U, 0x0U, 0x401F8220U | ||
| 108 | #define IOMUXC_GPIO_EMC_07_XBAR1_INOUT09 0x401F8030U, 0x3U, 0x401F8628U, 0x0U, 0x401F8220U | ||
| 109 | #define IOMUXC_GPIO_EMC_07_FLEXIO1_FLEXIO07 0x401F8030U, 0x4U, 0, 0, 0x401F8220U | ||
| 110 | #define IOMUXC_GPIO_EMC_07_GPIO4_IO07 0x401F8030U, 0x5U, 0, 0, 0x401F8220U | ||
| 111 | |||
| 112 | #define IOMUXC_GPIO_EMC_08_SEMC_DM00 0x401F8034U, 0x0U, 0, 0, 0x401F8224U | ||
| 113 | #define IOMUXC_GPIO_EMC_08_FLEXPWM2_PWMA01 0x401F8034U, 0x1U, 0x401F847CU, 0x0U, 0x401F8224U | ||
| 114 | #define IOMUXC_GPIO_EMC_08_SAI2_RX_DATA 0x401F8034U, 0x2U, 0x401F85B8U, 0x0U, 0x401F8224U | ||
| 115 | #define IOMUXC_GPIO_EMC_08_XBAR1_INOUT17 0x401F8034U, 0x3U, 0x401F862CU, 0x0U, 0x401F8224U | ||
| 116 | #define IOMUXC_GPIO_EMC_08_FLEXIO1_FLEXIO08 0x401F8034U, 0x4U, 0, 0, 0x401F8224U | ||
| 117 | #define IOMUXC_GPIO_EMC_08_GPIO4_IO08 0x401F8034U, 0x5U, 0, 0, 0x401F8224U | ||
| 118 | |||
| 119 | #define IOMUXC_GPIO_EMC_09_SEMC_ADDR00 0x401F8038U, 0x0U, 0, 0, 0x401F8228U | ||
| 120 | #define IOMUXC_GPIO_EMC_09_FLEXPWM2_PWMB01 0x401F8038U, 0x1U, 0x401F848CU, 0x0U, 0x401F8228U | ||
| 121 | #define IOMUXC_GPIO_EMC_09_SAI2_RX_SYNC 0x401F8038U, 0x2U, 0x401F85BCU, 0x0U, 0x401F8228U | ||
| 122 | #define IOMUXC_GPIO_EMC_09_FLEXCAN2_TX 0x401F8038U, 0x3U, 0, 0, 0x401F8228U | ||
| 123 | #define IOMUXC_GPIO_EMC_09_FLEXIO1_FLEXIO09 0x401F8038U, 0x4U, 0, 0, 0x401F8228U | ||
| 124 | #define IOMUXC_GPIO_EMC_09_GPIO4_IO09 0x401F8038U, 0x5U, 0, 0, 0x401F8228U | ||
| 125 | #define IOMUXC_GPIO_EMC_09_FLEXSPI2_B_SS1_B 0x401F8038U, 0x8U, 0, 0, 0x401F8228U | ||
| 126 | |||
| 127 | #define IOMUXC_GPIO_EMC_10_SEMC_ADDR01 0x401F803CU, 0x0U, 0, 0, 0x401F822CU | ||
| 128 | #define IOMUXC_GPIO_EMC_10_FLEXPWM2_PWMA02 0x401F803CU, 0x1U, 0x401F8480U, 0x0U, 0x401F822CU | ||
| 129 | #define IOMUXC_GPIO_EMC_10_SAI2_RX_BCLK 0x401F803CU, 0x2U, 0x401F85B4U, 0x0U, 0x401F822CU | ||
| 130 | #define IOMUXC_GPIO_EMC_10_FLEXCAN2_RX 0x401F803CU, 0x3U, 0x401F8450U, 0x0U, 0x401F822CU | ||
| 131 | #define IOMUXC_GPIO_EMC_10_FLEXIO1_FLEXIO10 0x401F803CU, 0x4U, 0, 0, 0x401F822CU | ||
| 132 | #define IOMUXC_GPIO_EMC_10_GPIO4_IO10 0x401F803CU, 0x5U, 0, 0, 0x401F822CU | ||
| 133 | #define IOMUXC_GPIO_EMC_10_FLEXSPI2_B_SS0_B 0x401F803CU, 0x8U, 0, 0, 0x401F822CU | ||
| 134 | |||
| 135 | #define IOMUXC_GPIO_EMC_11_SEMC_ADDR02 0x401F8040U, 0x0U, 0, 0, 0x401F8230U | ||
| 136 | #define IOMUXC_GPIO_EMC_11_FLEXPWM2_PWMB02 0x401F8040U, 0x1U, 0x401F8490U, 0x0U, 0x401F8230U | ||
| 137 | #define IOMUXC_GPIO_EMC_11_LPI2C4_SDA 0x401F8040U, 0x2U, 0x401F84E8U, 0x0U, 0x401F8230U | ||
| 138 | #define IOMUXC_GPIO_EMC_11_USDHC2_RESET_B 0x401F8040U, 0x3U, 0, 0, 0x401F8230U | ||
| 139 | #define IOMUXC_GPIO_EMC_11_FLEXIO1_FLEXIO11 0x401F8040U, 0x4U, 0, 0, 0x401F8230U | ||
| 140 | #define IOMUXC_GPIO_EMC_11_GPIO4_IO11 0x401F8040U, 0x5U, 0, 0, 0x401F8230U | ||
| 141 | #define IOMUXC_GPIO_EMC_11_FLEXSPI2_B_DQS 0x401F8040U, 0x8U, 0, 0, 0x401F8230U | ||
| 142 | |||
| 143 | #define IOMUXC_GPIO_EMC_12_SEMC_ADDR03 0x401F8044U, 0x0U, 0, 0, 0x401F8234U | ||
| 144 | #define IOMUXC_GPIO_EMC_12_XBAR1_IN24 0x401F8044U, 0x1U, 0x401F8640U, 0x0U, 0x401F8234U | ||
| 145 | #define IOMUXC_GPIO_EMC_12_LPI2C4_SCL 0x401F8044U, 0x2U, 0x401F84E4U, 0x0U, 0x401F8234U | ||
| 146 | #define IOMUXC_GPIO_EMC_12_USDHC1_WP 0x401F8044U, 0x3U, 0x401F85D8U, 0x0U, 0x401F8234U | ||
| 147 | #define IOMUXC_GPIO_EMC_12_FLEXPWM1_PWMA03 0x401F8044U, 0x4U, 0x401F8454U, 0x1U, 0x401F8234U | ||
| 148 | #define IOMUXC_GPIO_EMC_12_GPIO4_IO12 0x401F8044U, 0x5U, 0, 0, 0x401F8234U | ||
| 149 | #define IOMUXC_GPIO_EMC_12_FLEXSPI2_B_SCLK 0x401F8044U, 0x8U, 0x401F8754U, 0x0U, 0x401F8234U | ||
| 150 | |||
| 151 | #define IOMUXC_GPIO_EMC_13_SEMC_ADDR04 0x401F8048U, 0x0U, 0, 0, 0x401F8238U | ||
| 152 | #define IOMUXC_GPIO_EMC_13_XBAR1_IN25 0x401F8048U, 0x1U, 0x401F8650U, 0x1U, 0x401F8238U | ||
| 153 | #define IOMUXC_GPIO_EMC_13_LPUART3_TX 0x401F8048U, 0x2U, 0x401F853CU, 0x1U, 0x401F8238U | ||
| 154 | #define IOMUXC_GPIO_EMC_13_MQS_RIGHT 0x401F8048U, 0x3U, 0, 0, 0x401F8238U | ||
| 155 | #define IOMUXC_GPIO_EMC_13_FLEXPWM1_PWMB03 0x401F8048U, 0x4U, 0x401F8464U, 0x1U, 0x401F8238U | ||
| 156 | #define IOMUXC_GPIO_EMC_13_GPIO4_IO13 0x401F8048U, 0x5U, 0, 0, 0x401F8238U | ||
| 157 | #define IOMUXC_GPIO_EMC_13_FLEXSPI2_B_DATA00 0x401F8048U, 0x8U, 0x401F8740U, 0x0U, 0x401F8238U | ||
| 158 | |||
| 159 | #define IOMUXC_GPIO_EMC_14_SEMC_ADDR05 0x401F804CU, 0x0U, 0, 0, 0x401F823CU | ||
| 160 | #define IOMUXC_GPIO_EMC_14_XBAR1_INOUT19 0x401F804CU, 0x1U, 0x401F8654U, 0x0U, 0x401F823CU | ||
| 161 | #define IOMUXC_GPIO_EMC_14_LPUART3_RX 0x401F804CU, 0x2U, 0x401F8538U, 0x1U, 0x401F823CU | ||
| 162 | #define IOMUXC_GPIO_EMC_14_MQS_LEFT 0x401F804CU, 0x3U, 0, 0, 0x401F823CU | ||
| 163 | #define IOMUXC_GPIO_EMC_14_LPSPI2_PCS1 0x401F804CU, 0x4U, 0, 0, 0x401F823CU | ||
| 164 | #define IOMUXC_GPIO_EMC_14_GPIO4_IO14 0x401F804CU, 0x5U, 0, 0, 0x401F823CU | ||
| 165 | #define IOMUXC_GPIO_EMC_14_FLEXSPI2_B_DATA01 0x401F804CU, 0x8U, 0x401F8744U, 0x0U, 0x401F823CU | ||
| 166 | |||
| 167 | #define IOMUXC_GPIO_EMC_15_SEMC_ADDR06 0x401F8050U, 0x0U, 0, 0, 0x401F8240U | ||
| 168 | #define IOMUXC_GPIO_EMC_15_XBAR1_IN20 0x401F8050U, 0x1U, 0x401F8634U, 0x0U, 0x401F8240U | ||
| 169 | #define IOMUXC_GPIO_EMC_15_LPUART3_CTS_B 0x401F8050U, 0x2U, 0x401F8534U, 0x0U, 0x401F8240U | ||
| 170 | #define IOMUXC_GPIO_EMC_15_SPDIF_OUT 0x401F8050U, 0x3U, 0, 0, 0x401F8240U | ||
| 171 | #define IOMUXC_GPIO_EMC_15_QTIMER3_TIMER0 0x401F8050U, 0x4U, 0x401F857CU, 0x0U, 0x401F8240U | ||
| 172 | #define IOMUXC_GPIO_EMC_15_GPIO4_IO15 0x401F8050U, 0x5U, 0, 0, 0x401F8240U | ||
| 173 | #define IOMUXC_GPIO_EMC_15_FLEXSPI2_B_DATA02 0x401F8050U, 0x8U, 0x401F8748U, 0x0U, 0x401F8240U | ||
| 174 | |||
| 175 | #define IOMUXC_GPIO_EMC_16_SEMC_ADDR07 0x401F8054U, 0x0U, 0, 0, 0x401F8244U | ||
| 176 | #define IOMUXC_GPIO_EMC_16_XBAR1_IN21 0x401F8054U, 0x1U, 0x401F8658U, 0x0U, 0x401F8244U | ||
| 177 | #define IOMUXC_GPIO_EMC_16_LPUART3_RTS_B 0x401F8054U, 0x2U, 0, 0, 0x401F8244U | ||
| 178 | #define IOMUXC_GPIO_EMC_16_SPDIF_IN 0x401F8054U, 0x3U, 0x401F85C8U, 0x1U, 0x401F8244U | ||
| 179 | #define IOMUXC_GPIO_EMC_16_QTIMER3_TIMER1 0x401F8054U, 0x4U, 0x401F8580U, 0x1U, 0x401F8244U | ||
| 180 | #define IOMUXC_GPIO_EMC_16_GPIO4_IO16 0x401F8054U, 0x5U, 0, 0, 0x401F8244U | ||
| 181 | #define IOMUXC_GPIO_EMC_16_FLEXSPI2_B_DATA03 0x401F8054U, 0x8U, 0x401F874CU, 0x0U, 0x401F8244U | ||
| 182 | |||
| 183 | #define IOMUXC_GPIO_EMC_17_SEMC_ADDR08 0x401F8058U, 0x0U, 0, 0, 0x401F8248U | ||
| 184 | #define IOMUXC_GPIO_EMC_17_FLEXPWM4_PWMA03 0x401F8058U, 0x1U, 0x401F84A0U, 0x0U, 0x401F8248U | ||
| 185 | #define IOMUXC_GPIO_EMC_17_LPUART4_CTS_B 0x401F8058U, 0x2U, 0, 0, 0x401F8248U | ||
| 186 | #define IOMUXC_GPIO_EMC_17_FLEXCAN1_TX 0x401F8058U, 0x3U, 0, 0, 0x401F8248U | ||
| 187 | #define IOMUXC_GPIO_EMC_17_QTIMER3_TIMER2 0x401F8058U, 0x4U, 0x401F8584U, 0x0U, 0x401F8248U | ||
| 188 | #define IOMUXC_GPIO_EMC_17_GPIO4_IO17 0x401F8058U, 0x5U, 0, 0, 0x401F8248U | ||
| 189 | |||
| 190 | #define IOMUXC_GPIO_EMC_18_SEMC_ADDR09 0x401F805CU, 0x0U, 0, 0, 0x401F824CU | ||
| 191 | #define IOMUXC_GPIO_EMC_18_FLEXPWM4_PWMB03 0x401F805CU, 0x1U, 0, 0, 0x401F824CU | ||
| 192 | #define IOMUXC_GPIO_EMC_18_LPUART4_RTS_B 0x401F805CU, 0x2U, 0, 0, 0x401F824CU | ||
| 193 | #define IOMUXC_GPIO_EMC_18_FLEXCAN1_RX 0x401F805CU, 0x3U, 0x401F844CU, 0x1U, 0x401F824CU | ||
| 194 | #define IOMUXC_GPIO_EMC_18_QTIMER3_TIMER3 0x401F805CU, 0x4U, 0x401F8588U, 0x0U, 0x401F824CU | ||
| 195 | #define IOMUXC_GPIO_EMC_18_GPIO4_IO18 0x401F805CU, 0x5U, 0, 0, 0x401F824CU | ||
| 196 | #define IOMUXC_GPIO_EMC_18_SNVS_VIO_5_CTL 0x401F805CU, 0x6U, 0, 0, 0x401F824CU | ||
| 197 | |||
| 198 | #define IOMUXC_GPIO_EMC_19_SEMC_ADDR11 0x401F8060U, 0x0U, 0, 0, 0x401F8250U | ||
| 199 | #define IOMUXC_GPIO_EMC_19_FLEXPWM2_PWMA03 0x401F8060U, 0x1U, 0x401F8474U, 0x1U, 0x401F8250U | ||
| 200 | #define IOMUXC_GPIO_EMC_19_LPUART4_TX 0x401F8060U, 0x2U, 0x401F8544U, 0x1U, 0x401F8250U | ||
| 201 | #define IOMUXC_GPIO_EMC_19_ENET_RDATA01 0x401F8060U, 0x3U, 0x401F8438U, 0x0U, 0x401F8250U | ||
| 202 | #define IOMUXC_GPIO_EMC_19_QTIMER2_TIMER0 0x401F8060U, 0x4U, 0x401F856CU, 0x0U, 0x401F8250U | ||
| 203 | #define IOMUXC_GPIO_EMC_19_GPIO4_IO19 0x401F8060U, 0x5U, 0, 0, 0x401F8250U | ||
| 204 | #define IOMUXC_GPIO_EMC_19_SNVS_VIO_5 0x401F8060U, 0x6U, 0, 0, 0x401F8250U | ||
| 205 | |||
| 206 | #define IOMUXC_GPIO_EMC_20_SEMC_ADDR12 0x401F8064U, 0x0U, 0, 0, 0x401F8254U | ||
| 207 | #define IOMUXC_GPIO_EMC_20_FLEXPWM2_PWMB03 0x401F8064U, 0x1U, 0x401F8484U, 0x1U, 0x401F8254U | ||
| 208 | #define IOMUXC_GPIO_EMC_20_LPUART4_RX 0x401F8064U, 0x2U, 0x401F8540U, 0x1U, 0x401F8254U | ||
| 209 | #define IOMUXC_GPIO_EMC_20_ENET_RDATA00 0x401F8064U, 0x3U, 0x401F8434U, 0x0U, 0x401F8254U | ||
| 210 | #define IOMUXC_GPIO_EMC_20_QTIMER2_TIMER1 0x401F8064U, 0x4U, 0x401F8570U, 0x0U, 0x401F8254U | ||
| 211 | #define IOMUXC_GPIO_EMC_20_GPIO4_IO20 0x401F8064U, 0x5U, 0, 0, 0x401F8254U | ||
| 212 | |||
| 213 | #define IOMUXC_GPIO_EMC_21_SEMC_BA0 0x401F8068U, 0x0U, 0, 0, 0x401F8258U | ||
| 214 | #define IOMUXC_GPIO_EMC_21_FLEXPWM3_PWMA03 0x401F8068U, 0x1U, 0, 0, 0x401F8258U | ||
| 215 | #define IOMUXC_GPIO_EMC_21_LPI2C3_SDA 0x401F8068U, 0x2U, 0x401F84E0U, 0x0U, 0x401F8258U | ||
| 216 | #define IOMUXC_GPIO_EMC_21_ENET_TDATA01 0x401F8068U, 0x3U, 0, 0, 0x401F8258U | ||
| 217 | #define IOMUXC_GPIO_EMC_21_QTIMER2_TIMER2 0x401F8068U, 0x4U, 0x401F8574U, 0x0U, 0x401F8258U | ||
| 218 | #define IOMUXC_GPIO_EMC_21_GPIO4_IO21 0x401F8068U, 0x5U, 0, 0, 0x401F8258U | ||
| 219 | |||
| 220 | #define IOMUXC_GPIO_EMC_22_SEMC_BA1 0x401F806CU, 0x0U, 0, 0, 0x401F825CU | ||
| 221 | #define IOMUXC_GPIO_EMC_22_FLEXPWM3_PWMB03 0x401F806CU, 0x1U, 0, 0, 0x401F825CU | ||
| 222 | #define IOMUXC_GPIO_EMC_22_LPI2C3_SCL 0x401F806CU, 0x2U, 0x401F84DCU, 0x0U, 0x401F825CU | ||
| 223 | #define IOMUXC_GPIO_EMC_22_ENET_TDATA00 0x401F806CU, 0x3U, 0, 0, 0x401F825CU | ||
| 224 | #define IOMUXC_GPIO_EMC_22_QTIMER2_TIMER3 0x401F806CU, 0x4U, 0x401F8578U, 0x0U, 0x401F825CU | ||
| 225 | #define IOMUXC_GPIO_EMC_22_GPIO4_IO22 0x401F806CU, 0x5U, 0, 0, 0x401F825CU | ||
| 226 | #define IOMUXC_GPIO_EMC_22_FLEXSPI2_A_SS1_B 0x401F806CU, 0x8U, 0, 0, 0x401F825CU | ||
| 227 | |||
| 228 | #define IOMUXC_GPIO_EMC_23_SEMC_ADDR10 0x401F8070U, 0x0U, 0, 0, 0x401F8260U | ||
| 229 | #define IOMUXC_GPIO_EMC_23_FLEXPWM1_PWMA00 0x401F8070U, 0x1U, 0x401F8458U, 0x0U, 0x401F8260U | ||
| 230 | #define IOMUXC_GPIO_EMC_23_LPUART5_TX 0x401F8070U, 0x2U, 0x401F854CU, 0x0U, 0x401F8260U | ||
| 231 | #define IOMUXC_GPIO_EMC_23_ENET_RX_EN 0x401F8070U, 0x3U, 0x401F843CU, 0x0U, 0x401F8260U | ||
| 232 | #define IOMUXC_GPIO_EMC_23_GPT1_CAPTURE2 0x401F8070U, 0x4U, 0x401F875CU, 0x0U, 0x401F8260U | ||
| 233 | #define IOMUXC_GPIO_EMC_23_GPIO4_IO23 0x401F8070U, 0x5U, 0, 0, 0x401F8260U | ||
| 234 | #define IOMUXC_GPIO_EMC_23_FLEXSPI2_A_DQS 0x401F8070U, 0x8U, 0x401F872CU, 0x1U, 0x401F8260U | ||
| 235 | |||
| 236 | #define IOMUXC_GPIO_EMC_24_SEMC_CAS 0x401F8074U, 0x0U, 0, 0, 0x401F8264U | ||
| 237 | #define IOMUXC_GPIO_EMC_24_FLEXPWM1_PWMB00 0x401F8074U, 0x1U, 0x401F8468U, 0x0U, 0x401F8264U | ||
| 238 | #define IOMUXC_GPIO_EMC_24_LPUART5_RX 0x401F8074U, 0x2U, 0x401F8548U, 0x0U, 0x401F8264U | ||
| 239 | #define IOMUXC_GPIO_EMC_24_ENET_TX_EN 0x401F8074U, 0x3U, 0, 0, 0x401F8264U | ||
| 240 | #define IOMUXC_GPIO_EMC_24_GPT1_CAPTURE1 0x401F8074U, 0x4U, 0x401F8758U, 0x0U, 0x401F8264U | ||
| 241 | #define IOMUXC_GPIO_EMC_24_GPIO4_IO24 0x401F8074U, 0x5U, 0, 0, 0x401F8264U | ||
| 242 | #define IOMUXC_GPIO_EMC_24_FLEXSPI2_A_SS0_B 0x401F8074U, 0x8U, 0, 0, 0x401F8264U | ||
| 243 | |||
| 244 | #define IOMUXC_GPIO_EMC_25_SEMC_RAS 0x401F8078U, 0x0U, 0, 0, 0x401F8268U | ||
| 245 | #define IOMUXC_GPIO_EMC_25_FLEXPWM1_PWMA01 0x401F8078U, 0x1U, 0x401F845CU, 0x0U, 0x401F8268U | ||
| 246 | #define IOMUXC_GPIO_EMC_25_LPUART6_TX 0x401F8078U, 0x2U, 0x401F8554U, 0x0U, 0x401F8268U | ||
| 247 | #define IOMUXC_GPIO_EMC_25_ENET_TX_CLK 0x401F8078U, 0x3U, 0x401F8448U, 0x0U, 0x401F8268U | ||
| 248 | #define IOMUXC_GPIO_EMC_25_ENET_REF_CLK 0x401F8078U, 0x4U, 0x401F842CU, 0x0U, 0x401F8268U | ||
| 249 | #define IOMUXC_GPIO_EMC_25_GPIO4_IO25 0x401F8078U, 0x5U, 0, 0, 0x401F8268U | ||
| 250 | #define IOMUXC_GPIO_EMC_25_FLEXSPI2_A_SCLK 0x401F8078U, 0x8U, 0x401F8750U, 0x1U, 0x401F8268U | ||
| 251 | |||
| 252 | #define IOMUXC_GPIO_EMC_26_SEMC_CLK 0x401F807CU, 0x0U, 0, 0, 0x401F826CU | ||
| 253 | #define IOMUXC_GPIO_EMC_26_FLEXPWM1_PWMB01 0x401F807CU, 0x1U, 0x401F846CU, 0x0U, 0x401F826CU | ||
| 254 | #define IOMUXC_GPIO_EMC_26_LPUART6_RX 0x401F807CU, 0x2U, 0x401F8550U, 0x0U, 0x401F826CU | ||
| 255 | #define IOMUXC_GPIO_EMC_26_ENET_RX_ER 0x401F807CU, 0x3U, 0x401F8440U, 0x0U, 0x401F826CU | ||
| 256 | #define IOMUXC_GPIO_EMC_26_FLEXIO1_FLEXIO12 0x401F807CU, 0x4U, 0, 0, 0x401F826CU | ||
| 257 | #define IOMUXC_GPIO_EMC_26_GPIO4_IO26 0x401F807CU, 0x5U, 0, 0, 0x401F826CU | ||
| 258 | #define IOMUXC_GPIO_EMC_26_FLEXSPI2_A_DATA00 0x401F807CU, 0x8U, 0x401F8730U, 0x1U, 0x401F826CU | ||
| 259 | |||
| 260 | #define IOMUXC_GPIO_EMC_27_SEMC_CKE 0x401F8080U, 0x0U, 0, 0, 0x401F8270U | ||
| 261 | #define IOMUXC_GPIO_EMC_27_FLEXPWM1_PWMA02 0x401F8080U, 0x1U, 0x401F8460U, 0x0U, 0x401F8270U | ||
| 262 | #define IOMUXC_GPIO_EMC_27_LPUART5_RTS_B 0x401F8080U, 0x2U, 0, 0, 0x401F8270U | ||
| 263 | #define IOMUXC_GPIO_EMC_27_LPSPI1_SCK 0x401F8080U, 0x3U, 0x401F84F0U, 0x0U, 0x401F8270U | ||
| 264 | #define IOMUXC_GPIO_EMC_27_FLEXIO1_FLEXIO13 0x401F8080U, 0x4U, 0, 0, 0x401F8270U | ||
| 265 | #define IOMUXC_GPIO_EMC_27_GPIO4_IO27 0x401F8080U, 0x5U, 0, 0, 0x401F8270U | ||
| 266 | #define IOMUXC_GPIO_EMC_27_FLEXSPI2_A_DATA01 0x401F8080U, 0x8U, 0x401F8734U, 0x1U, 0x401F8270U | ||
| 267 | |||
| 268 | #define IOMUXC_GPIO_EMC_28_SEMC_WE 0x401F8084U, 0x0U, 0, 0, 0x401F8274U | ||
| 269 | #define IOMUXC_GPIO_EMC_28_FLEXPWM1_PWMB02 0x401F8084U, 0x1U, 0x401F8470U, 0x0U, 0x401F8274U | ||
| 270 | #define IOMUXC_GPIO_EMC_28_LPUART5_CTS_B 0x401F8084U, 0x2U, 0, 0, 0x401F8274U | ||
| 271 | #define IOMUXC_GPIO_EMC_28_LPSPI1_SDO 0x401F8084U, 0x3U, 0x401F84F8U, 0x0U, 0x401F8274U | ||
| 272 | #define IOMUXC_GPIO_EMC_28_FLEXIO1_FLEXIO14 0x401F8084U, 0x4U, 0, 0, 0x401F8274U | ||
| 273 | #define IOMUXC_GPIO_EMC_28_GPIO4_IO28 0x401F8084U, 0x5U, 0, 0, 0x401F8274U | ||
| 274 | #define IOMUXC_GPIO_EMC_28_FLEXSPI2_A_DATA02 0x401F8084U, 0x8U, 0x401F8738U, 0x1U, 0x401F8274U | ||
| 275 | |||
| 276 | #define IOMUXC_GPIO_EMC_29_SEMC_CS0 0x401F8088U, 0x0U, 0, 0, 0x401F8278U | ||
| 277 | #define IOMUXC_GPIO_EMC_29_FLEXPWM3_PWMA00 0x401F8088U, 0x1U, 0, 0, 0x401F8278U | ||
| 278 | #define IOMUXC_GPIO_EMC_29_LPUART6_RTS_B 0x401F8088U, 0x2U, 0, 0, 0x401F8278U | ||
| 279 | #define IOMUXC_GPIO_EMC_29_LPSPI1_SDI 0x401F8088U, 0x3U, 0x401F84F4U, 0x0U, 0x401F8278U | ||
| 280 | #define IOMUXC_GPIO_EMC_29_FLEXIO1_FLEXIO15 0x401F8088U, 0x4U, 0, 0, 0x401F8278U | ||
| 281 | #define IOMUXC_GPIO_EMC_29_GPIO4_IO29 0x401F8088U, 0x5U, 0, 0, 0x401F8278U | ||
| 282 | #define IOMUXC_GPIO_EMC_29_FLEXSPI2_A_DATA03 0x401F8088U, 0x8U, 0x401F873CU, 0x1U, 0x401F8278U | ||
| 283 | |||
| 284 | #define IOMUXC_GPIO_EMC_30_SEMC_DATA08 0x401F808CU, 0x0U, 0, 0, 0x401F827CU | ||
| 285 | #define IOMUXC_GPIO_EMC_30_FLEXPWM3_PWMB00 0x401F808CU, 0x1U, 0, 0, 0x401F827CU | ||
| 286 | #define IOMUXC_GPIO_EMC_30_LPUART6_CTS_B 0x401F808CU, 0x2U, 0, 0, 0x401F827CU | ||
| 287 | #define IOMUXC_GPIO_EMC_30_LPSPI1_PCS0 0x401F808CU, 0x3U, 0x401F84ECU, 0x1U, 0x401F827CU | ||
| 288 | #define IOMUXC_GPIO_EMC_30_CSI_DATA23 0x401F808CU, 0x4U, 0, 0, 0x401F827CU | ||
| 289 | #define IOMUXC_GPIO_EMC_30_GPIO4_IO30 0x401F808CU, 0x5U, 0, 0, 0x401F827CU | ||
| 290 | #define IOMUXC_GPIO_EMC_30_ENET2_TDATA00 0x401F808CU, 0x8U, 0, 0, 0x401F827CU | ||
| 291 | |||
| 292 | #define IOMUXC_GPIO_EMC_31_SEMC_DATA09 0x401F8090U, 0x0U, 0, 0, 0x401F8280U | ||
| 293 | #define IOMUXC_GPIO_EMC_31_FLEXPWM3_PWMA01 0x401F8090U, 0x1U, 0, 0, 0x401F8280U | ||
| 294 | #define IOMUXC_GPIO_EMC_31_LPUART7_TX 0x401F8090U, 0x2U, 0x401F855CU, 0x1U, 0x401F8280U | ||
| 295 | #define IOMUXC_GPIO_EMC_31_LPSPI1_PCS1 0x401F8090U, 0x3U, 0, 0, 0x401F8280U | ||
| 296 | #define IOMUXC_GPIO_EMC_31_CSI_DATA22 0x401F8090U, 0x4U, 0, 0, 0x401F8280U | ||
| 297 | #define IOMUXC_GPIO_EMC_31_GPIO4_IO31 0x401F8090U, 0x5U, 0, 0, 0x401F8280U | ||
| 298 | #define IOMUXC_GPIO_EMC_31_ENET2_TDATA01 0x401F8090U, 0x8U, 0, 0, 0x401F8280U | ||
| 299 | |||
| 300 | #define IOMUXC_GPIO_EMC_32_SEMC_DATA10 0x401F8094U, 0x0U, 0, 0, 0x401F8284U | ||
| 301 | #define IOMUXC_GPIO_EMC_32_FLEXPWM3_PWMB01 0x401F8094U, 0x1U, 0, 0, 0x401F8284U | ||
| 302 | #define IOMUXC_GPIO_EMC_32_LPUART7_RX 0x401F8094U, 0x2U, 0x401F8558U, 0x1U, 0x401F8284U | ||
| 303 | #define IOMUXC_GPIO_EMC_32_CCM_PMIC_RDY 0x401F8094U, 0x3U, 0x401F83FCU, 0x4U, 0x401F8284U | ||
| 304 | #define IOMUXC_GPIO_EMC_32_CSI_DATA21 0x401F8094U, 0x4U, 0, 0, 0x401F8284U | ||
| 305 | #define IOMUXC_GPIO_EMC_32_GPIO3_IO18 0x401F8094U, 0x5U, 0, 0, 0x401F8284U | ||
| 306 | #define IOMUXC_GPIO_EMC_32_ENET2_TX_EN 0x401F8094U, 0x8U, 0, 0, 0x401F8284U | ||
| 307 | |||
| 308 | #define IOMUXC_GPIO_EMC_33_SEMC_DATA11 0x401F8098U, 0x0U, 0, 0, 0x401F8288U | ||
| 309 | #define IOMUXC_GPIO_EMC_33_FLEXPWM3_PWMA02 0x401F8098U, 0x1U, 0, 0, 0x401F8288U | ||
| 310 | #define IOMUXC_GPIO_EMC_33_USDHC1_RESET_B 0x401F8098U, 0x2U, 0, 0, 0x401F8288U | ||
| 311 | #define IOMUXC_GPIO_EMC_33_SAI3_RX_DATA 0x401F8098U, 0x3U, 0x401F8778U, 0x0U, 0x401F8288U | ||
| 312 | #define IOMUXC_GPIO_EMC_33_CSI_DATA20 0x401F8098U, 0x4U, 0, 0, 0x401F8288U | ||
| 313 | #define IOMUXC_GPIO_EMC_33_GPIO3_IO19 0x401F8098U, 0x5U, 0, 0, 0x401F8288U | ||
| 314 | #define IOMUXC_GPIO_EMC_33_ENET2_TX_CLK 0x401F8098U, 0x8U, 0x401F8728U, 0x0U, 0x401F8288U | ||
| 315 | #define IOMUXC_GPIO_EMC_33_ENET2_REF_CLK2 0x401F8098U, 0x9U, 0x401F870CU, 0x0U, 0x401F8288U | ||
| 316 | |||
| 317 | #define IOMUXC_GPIO_EMC_34_SEMC_DATA12 0x401F809CU, 0x0U, 0, 0, 0x401F828CU | ||
| 318 | #define IOMUXC_GPIO_EMC_34_FLEXPWM3_PWMB02 0x401F809CU, 0x1U, 0, 0, 0x401F828CU | ||
| 319 | #define IOMUXC_GPIO_EMC_34_USDHC1_VSELECT 0x401F809CU, 0x2U, 0, 0, 0x401F828CU | ||
| 320 | #define IOMUXC_GPIO_EMC_34_SAI3_RX_SYNC 0x401F809CU, 0x3U, 0x401F877CU, 0x0U, 0x401F828CU | ||
| 321 | #define IOMUXC_GPIO_EMC_34_CSI_DATA19 0x401F809CU, 0x4U, 0, 0, 0x401F828CU | ||
| 322 | #define IOMUXC_GPIO_EMC_34_GPIO3_IO20 0x401F809CU, 0x5U, 0, 0, 0x401F828CU | ||
| 323 | #define IOMUXC_GPIO_EMC_34_ENET2_RX_ER 0x401F809CU, 0x8U, 0x401F8720U, 0x0U, 0x401F828CU | ||
| 324 | |||
| 325 | #define IOMUXC_GPIO_EMC_35_SEMC_DATA13 0x401F80A0U, 0x0U, 0, 0, 0x401F8290U | ||
| 326 | #define IOMUXC_GPIO_EMC_35_XBAR1_INOUT18 0x401F80A0U, 0x1U, 0x401F8630U, 0x0U, 0x401F8290U | ||
| 327 | #define IOMUXC_GPIO_EMC_35_GPT1_COMPARE1 0x401F80A0U, 0x2U, 0, 0, 0x401F8290U | ||
| 328 | #define IOMUXC_GPIO_EMC_35_SAI3_RX_BCLK 0x401F80A0U, 0x3U, 0x401F8774U, 0x0U, 0x401F8290U | ||
| 329 | #define IOMUXC_GPIO_EMC_35_CSI_DATA18 0x401F80A0U, 0x4U, 0, 0, 0x401F8290U | ||
| 330 | #define IOMUXC_GPIO_EMC_35_GPIO3_IO21 0x401F80A0U, 0x5U, 0, 0, 0x401F8290U | ||
| 331 | #define IOMUXC_GPIO_EMC_35_USDHC1_CD_B 0x401F80A0U, 0x6U, 0x401F85D4U, 0x0U, 0x401F8290U | ||
| 332 | #define IOMUXC_GPIO_EMC_35_ENET2_RDATA00 0x401F80A0U, 0x8U, 0x401F8714U, 0x0U, 0x401F8290U | ||
| 333 | |||
| 334 | #define IOMUXC_GPIO_EMC_36_SEMC_DATA14 0x401F80A4U, 0x0U, 0, 0, 0x401F8294U | ||
| 335 | #define IOMUXC_GPIO_EMC_36_XBAR1_IN22 0x401F80A4U, 0x1U, 0x401F8638U, 0x0U, 0x401F8294U | ||
| 336 | #define IOMUXC_GPIO_EMC_36_GPT1_COMPARE2 0x401F80A4U, 0x2U, 0, 0, 0x401F8294U | ||
| 337 | #define IOMUXC_GPIO_EMC_36_SAI3_TX_DATA 0x401F80A4U, 0x3U, 0, 0, 0x401F8294U | ||
| 338 | #define IOMUXC_GPIO_EMC_36_CSI_DATA17 0x401F80A4U, 0x4U, 0, 0, 0x401F8294U | ||
| 339 | #define IOMUXC_GPIO_EMC_36_GPIO3_IO22 0x401F80A4U, 0x5U, 0, 0, 0x401F8294U | ||
| 340 | #define IOMUXC_GPIO_EMC_36_USDHC1_WP 0x401F80A4U, 0x6U, 0x401F85D8U, 0x1U, 0x401F8294U | ||
| 341 | #define IOMUXC_GPIO_EMC_36_ENET2_RDATA01 0x401F80A4U, 0x8U, 0x401F8718U, 0x0U, 0x401F8294U | ||
| 342 | #define IOMUXC_GPIO_EMC_36_FLEXCAN3_TX 0x401F80A4U, 0x9U, 0, 0, 0x401F8294U | ||
| 343 | |||
| 344 | #define IOMUXC_GPIO_EMC_37_SEMC_DATA15 0x401F80A8U, 0x0U, 0, 0, 0x401F8298U | ||
| 345 | #define IOMUXC_GPIO_EMC_37_XBAR1_IN23 0x401F80A8U, 0x1U, 0x401F863CU, 0x0U, 0x401F8298U | ||
| 346 | #define IOMUXC_GPIO_EMC_37_GPT1_COMPARE3 0x401F80A8U, 0x2U, 0, 0, 0x401F8298U | ||
| 347 | #define IOMUXC_GPIO_EMC_37_SAI3_MCLK 0x401F80A8U, 0x3U, 0x401F8770U, 0x0U, 0x401F8298U | ||
| 348 | #define IOMUXC_GPIO_EMC_37_CSI_DATA16 0x401F80A8U, 0x4U, 0, 0, 0x401F8298U | ||
| 349 | #define IOMUXC_GPIO_EMC_37_GPIO3_IO23 0x401F80A8U, 0x5U, 0, 0, 0x401F8298U | ||
| 350 | #define IOMUXC_GPIO_EMC_37_USDHC2_WP 0x401F80A8U, 0x6U, 0x401F8608U, 0x0U, 0x401F8298U | ||
| 351 | #define IOMUXC_GPIO_EMC_37_ENET2_RX_EN 0x401F80A8U, 0x8U, 0x401F871CU, 0x0U, 0x401F8298U | ||
| 352 | #define IOMUXC_GPIO_EMC_37_FLEXCAN3_RX 0x401F80A8U, 0x9U, 0x401F878CU, 0x0U, 0x401F8298U | ||
| 353 | |||
| 354 | #define IOMUXC_GPIO_EMC_38_SEMC_DM01 0x401F80ACU, 0x0U, 0, 0, 0x401F829CU | ||
| 355 | #define IOMUXC_GPIO_EMC_38_FLEXPWM1_PWMA03 0x401F80ACU, 0x1U, 0x401F8454U, 0x2U, 0x401F829CU | ||
| 356 | #define IOMUXC_GPIO_EMC_38_LPUART8_TX 0x401F80ACU, 0x2U, 0x401F8564U, 0x2U, 0x401F829CU | ||
| 357 | #define IOMUXC_GPIO_EMC_38_SAI3_TX_BCLK 0x401F80ACU, 0x3U, 0x401F8780U, 0x0U, 0x401F829CU | ||
| 358 | #define IOMUXC_GPIO_EMC_38_CSI_FIELD 0x401F80ACU, 0x4U, 0, 0, 0x401F829CU | ||
| 359 | #define IOMUXC_GPIO_EMC_38_GPIO3_IO24 0x401F80ACU, 0x5U, 0, 0, 0x401F829CU | ||
| 360 | #define IOMUXC_GPIO_EMC_38_USDHC2_VSELECT 0x401F80ACU, 0x6U, 0, 0, 0x401F829CU | ||
| 361 | #define IOMUXC_GPIO_EMC_38_ENET2_MDC 0x401F80ACU, 0x8U, 0, 0, 0x401F829CU | ||
| 362 | |||
| 363 | #define IOMUXC_GPIO_EMC_39_SEMC_DQS 0x401F80B0U, 0x0U, 0, 0, 0x401F82A0U | ||
| 364 | #define IOMUXC_GPIO_EMC_39_FLEXPWM1_PWMB03 0x401F80B0U, 0x1U, 0x401F8464U, 0x2U, 0x401F82A0U | ||
| 365 | #define IOMUXC_GPIO_EMC_39_LPUART8_RX 0x401F80B0U, 0x2U, 0x401F8560U, 0x2U, 0x401F82A0U | ||
| 366 | #define IOMUXC_GPIO_EMC_39_SAI3_TX_SYNC 0x401F80B0U, 0x3U, 0x401F8784U, 0x0U, 0x401F82A0U | ||
| 367 | #define IOMUXC_GPIO_EMC_39_WDOG1_WDOG_B 0x401F80B0U, 0x4U, 0, 0, 0x401F82A0U | ||
| 368 | #define IOMUXC_GPIO_EMC_39_GPIO3_IO25 0x401F80B0U, 0x5U, 0, 0, 0x401F82A0U | ||
| 369 | #define IOMUXC_GPIO_EMC_39_USDHC2_CD_B 0x401F80B0U, 0x6U, 0x401F85E0U, 0x1U, 0x401F82A0U | ||
| 370 | #define IOMUXC_GPIO_EMC_39_ENET2_MDIO 0x401F80B0U, 0x8U, 0x401F8710U, 0x0U, 0x401F82A0U | ||
| 371 | #define IOMUXC_GPIO_EMC_39_SEMC_DQS4 0x401F80B0U, 0x9U, 0x401F8788U, 0x1U, 0x401F82A0U | ||
| 372 | |||
| 373 | #define IOMUXC_GPIO_EMC_40_SEMC_RDY 0x401F80B4U, 0x0U, 0, 0, 0x401F82A4U | ||
| 374 | #define IOMUXC_GPIO_EMC_40_GPT2_CAPTURE2 0x401F80B4U, 0x1U, 0x401F8768U, 0x0U, 0x401F82A4U | ||
| 375 | #define IOMUXC_GPIO_EMC_40_LPSPI1_PCS2 0x401F80B4U, 0x2U, 0, 0, 0x401F82A4U | ||
| 376 | #define IOMUXC_GPIO_EMC_40_USB_OTG2_OC 0x401F80B4U, 0x3U, 0x401F85CCU, 0x1U, 0x401F82A4U | ||
| 377 | #define IOMUXC_GPIO_EMC_40_ENET_MDC 0x401F80B4U, 0x4U, 0, 0, 0x401F82A4U | ||
| 378 | #define IOMUXC_GPIO_EMC_40_GPIO3_IO26 0x401F80B4U, 0x5U, 0, 0, 0x401F82A4U | ||
| 379 | #define IOMUXC_GPIO_EMC_40_USDHC2_RESET_B 0x401F80B4U, 0x6U, 0, 0, 0x401F82A4U | ||
| 380 | #define IOMUXC_GPIO_EMC_40_SEMC_CLK5 0x401F80B4U, 0x9U, 0, 0, 0x401F82A4U | ||
| 381 | |||
| 382 | #define IOMUXC_GPIO_EMC_41_SEMC_CSX00 0x401F80B8U, 0x0U, 0, 0, 0x401F82A8U | ||
| 383 | #define IOMUXC_GPIO_EMC_41_GPT2_CAPTURE1 0x401F80B8U, 0x1U, 0x401F8764U, 0x0U, 0x401F82A8U | ||
| 384 | #define IOMUXC_GPIO_EMC_41_LPSPI1_PCS3 0x401F80B8U, 0x2U, 0, 0, 0x401F82A8U | ||
| 385 | #define IOMUXC_GPIO_EMC_41_USB_OTG2_PWR 0x401F80B8U, 0x3U, 0, 0, 0x401F82A8U | ||
| 386 | #define IOMUXC_GPIO_EMC_41_ENET_MDIO 0x401F80B8U, 0x4U, 0x401F8430U, 0x1U, 0x401F82A8U | ||
| 387 | #define IOMUXC_GPIO_EMC_41_GPIO3_IO27 0x401F80B8U, 0x5U, 0, 0, 0x401F82A8U | ||
| 388 | #define IOMUXC_GPIO_EMC_41_USDHC1_VSELECT 0x401F80B8U, 0x6U, 0, 0, 0x401F82A8U | ||
| 389 | |||
| 390 | #define IOMUXC_GPIO_AD_B0_00_FLEXPWM2_PWMA03 0x401F80BCU, 0x0U, 0x401F8474U, 0x2U, 0x401F82ACU | ||
| 391 | #define IOMUXC_GPIO_AD_B0_00_XBAR1_INOUT14 0x401F80BCU, 0x1U, 0x401F8644U, 0x0U, 0x401F82ACU | ||
| 392 | #define IOMUXC_GPIO_AD_B0_00_REF_CLK_32K 0x401F80BCU, 0x2U, 0, 0, 0x401F82ACU | ||
| 393 | #define IOMUXC_GPIO_AD_B0_00_USB_OTG2_ID 0x401F80BCU, 0x3U, 0x401F83F8U, 0x0U, 0x401F82ACU | ||
| 394 | #define IOMUXC_GPIO_AD_B0_00_LPI2C1_SCLS 0x401F80BCU, 0x4U, 0, 0, 0x401F82ACU | ||
| 395 | #define IOMUXC_GPIO_AD_B0_00_GPIO1_IO00 0x401F80BCU, 0x5U, 0, 0, 0x401F82ACU | ||
| 396 | #define IOMUXC_GPIO_AD_B0_00_USDHC1_RESET_B 0x401F80BCU, 0x6U, 0, 0, 0x401F82ACU | ||
| 397 | #define IOMUXC_GPIO_AD_B0_00_LPSPI3_SCK 0x401F80BCU, 0x7U, 0x401F8510U, 0x0U, 0x401F82ACU | ||
| 398 | |||
| 399 | #define IOMUXC_GPIO_AD_B0_01_FLEXPWM2_PWMB03 0x401F80C0U, 0x0U, 0x401F8484U, 0x2U, 0x401F82B0U | ||
| 400 | #define IOMUXC_GPIO_AD_B0_01_XBAR1_INOUT15 0x401F80C0U, 0x1U, 0x401F8648U, 0x0U, 0x401F82B0U | ||
| 401 | #define IOMUXC_GPIO_AD_B0_01_REF_CLK_24M 0x401F80C0U, 0x2U, 0, 0, 0x401F82B0U | ||
| 402 | #define IOMUXC_GPIO_AD_B0_01_USB_OTG1_ID 0x401F80C0U, 0x3U, 0x401F83F4U, 0x0U, 0x401F82B0U | ||
| 403 | #define IOMUXC_GPIO_AD_B0_01_LPI2C1_SDAS 0x401F80C0U, 0x4U, 0, 0, 0x401F82B0U | ||
| 404 | #define IOMUXC_GPIO_AD_B0_01_GPIO1_IO01 0x401F80C0U, 0x5U, 0, 0, 0x401F82B0U | ||
| 405 | #define IOMUXC_GPIO_AD_B0_01_EWM_OUT_B 0x401F80C0U, 0x6U, 0, 0, 0x401F82B0U | ||
| 406 | #define IOMUXC_GPIO_AD_B0_01_LPSPI3_SDO 0x401F80C0U, 0x7U, 0x401F8518U, 0x0U, 0x401F82B0U | ||
| 407 | |||
| 408 | #define IOMUXC_GPIO_AD_B0_02_FLEXCAN2_TX 0x401F80C4U, 0x0U, 0, 0, 0x401F82B4U | ||
| 409 | #define IOMUXC_GPIO_AD_B0_02_XBAR1_INOUT16 0x401F80C4U, 0x1U, 0x401F864CU, 0x0U, 0x401F82B4U | ||
| 410 | #define IOMUXC_GPIO_AD_B0_02_LPUART6_TX 0x401F80C4U, 0x2U, 0x401F8554U, 0x1U, 0x401F82B4U | ||
| 411 | #define IOMUXC_GPIO_AD_B0_02_USB_OTG1_PWR 0x401F80C4U, 0x3U, 0, 0, 0x401F82B4U | ||
| 412 | #define IOMUXC_GPIO_AD_B0_02_FLEXPWM1_PWMX00 0x401F80C4U, 0x4U, 0, 0, 0x401F82B4U | ||
| 413 | #define IOMUXC_GPIO_AD_B0_02_GPIO1_IO02 0x401F80C4U, 0x5U, 0, 0, 0x401F82B4U | ||
| 414 | #define IOMUXC_GPIO_AD_B0_02_LPI2C1_HREQ 0x401F80C4U, 0x6U, 0, 0, 0x401F82B4U | ||
| 415 | #define IOMUXC_GPIO_AD_B0_02_LPSPI3_SDI 0x401F80C4U, 0x7U, 0x401F8514U, 0x0U, 0x401F82B4U | ||
| 416 | |||
| 417 | #define IOMUXC_GPIO_AD_B0_03_FLEXCAN2_RX 0x401F80C8U, 0x0U, 0x401F8450U, 0x1U, 0x401F82B8U | ||
| 418 | #define IOMUXC_GPIO_AD_B0_03_XBAR1_INOUT17 0x401F80C8U, 0x1U, 0x401F862CU, 0x1U, 0x401F82B8U | ||
| 419 | #define IOMUXC_GPIO_AD_B0_03_LPUART6_RX 0x401F80C8U, 0x2U, 0x401F8550U, 0x1U, 0x401F82B8U | ||
| 420 | #define IOMUXC_GPIO_AD_B0_03_USB_OTG1_OC 0x401F80C8U, 0x3U, 0x401F85D0U, 0x0U, 0x401F82B8U | ||
| 421 | #define IOMUXC_GPIO_AD_B0_03_FLEXPWM1_PWMX01 0x401F80C8U, 0x4U, 0, 0, 0x401F82B8U | ||
| 422 | #define IOMUXC_GPIO_AD_B0_03_GPIO1_IO03 0x401F80C8U, 0x5U, 0, 0, 0x401F82B8U | ||
| 423 | #define IOMUXC_GPIO_AD_B0_03_REF_CLK_24M 0x401F80C8U, 0x6U, 0, 0, 0x401F82B8U | ||
| 424 | #define IOMUXC_GPIO_AD_B0_03_LPSPI3_PCS0 0x401F80C8U, 0x7U, 0x401F850CU, 0x0U, 0x401F82B8U | ||
| 425 | |||
| 426 | #define IOMUXC_GPIO_AD_B0_04_SRC_BOOT_MODE00 0x401F80CCU, 0x0U, 0, 0, 0x401F82BCU | ||
| 427 | #define IOMUXC_GPIO_AD_B0_04_MQS_RIGHT 0x401F80CCU, 0x1U, 0, 0, 0x401F82BCU | ||
| 428 | #define IOMUXC_GPIO_AD_B0_04_ENET_TX_DATA03 0x401F80CCU, 0x2U, 0, 0, 0x401F82BCU | ||
| 429 | #define IOMUXC_GPIO_AD_B0_04_SAI2_TX_SYNC 0x401F80CCU, 0x3U, 0x401F85C4U, 0x1U, 0x401F82BCU | ||
| 430 | #define IOMUXC_GPIO_AD_B0_04_CSI_DATA09 0x401F80CCU, 0x4U, 0x401F841CU, 0x1U, 0x401F82BCU | ||
| 431 | #define IOMUXC_GPIO_AD_B0_04_GPIO1_IO04 0x401F80CCU, 0x5U, 0, 0, 0x401F82BCU | ||
| 432 | #define IOMUXC_GPIO_AD_B0_04_PIT_TRIGGER00 0x401F80CCU, 0x6U, 0, 0, 0x401F82BCU | ||
| 433 | #define IOMUXC_GPIO_AD_B0_04_LPSPI3_PCS1 0x401F80CCU, 0x7U, 0, 0, 0x401F82BCU | ||
| 434 | |||
| 435 | #define IOMUXC_GPIO_AD_B0_05_SRC_BOOT_MODE01 0x401F80D0U, 0x0U, 0, 0, 0x401F82C0U | ||
| 436 | #define IOMUXC_GPIO_AD_B0_05_MQS_LEFT 0x401F80D0U, 0x1U, 0, 0, 0x401F82C0U | ||
| 437 | #define IOMUXC_GPIO_AD_B0_05_ENET_TX_DATA02 0x401F80D0U, 0x2U, 0, 0, 0x401F82C0U | ||
| 438 | #define IOMUXC_GPIO_AD_B0_05_SAI2_TX_BCLK 0x401F80D0U, 0x3U, 0x401F85C0U, 0x1U, 0x401F82C0U | ||
| 439 | #define IOMUXC_GPIO_AD_B0_05_CSI_DATA08 0x401F80D0U, 0x4U, 0x401F8418U, 0x1U, 0x401F82C0U | ||
| 440 | #define IOMUXC_GPIO_AD_B0_05_GPIO1_IO05 0x401F80D0U, 0x5U, 0, 0, 0x401F82C0U | ||
| 441 | #define IOMUXC_GPIO_AD_B0_05_XBAR1_INOUT17 0x401F80D0U, 0x6U, 0x401F862CU, 0x2U, 0x401F82C0U | ||
| 442 | #define IOMUXC_GPIO_AD_B0_05_LPSPI3_PCS2 0x401F80D0U, 0x7U, 0, 0, 0x401F82C0U | ||
| 443 | |||
| 444 | #define IOMUXC_GPIO_AD_B0_06_JTAG_TMS 0x401F80D4U, 0x0U, 0, 0, 0x401F82C4U | ||
| 445 | #define IOMUXC_GPIO_AD_B0_06_GPT2_COMPARE1 0x401F80D4U, 0x1U, 0, 0, 0x401F82C4U | ||
| 446 | #define IOMUXC_GPIO_AD_B0_06_ENET_RX_CLK 0x401F80D4U, 0x2U, 0, 0, 0x401F82C4U | ||
| 447 | #define IOMUXC_GPIO_AD_B0_06_SAI2_RX_BCLK 0x401F80D4U, 0x3U, 0x401F85B4U, 0x1U, 0x401F82C4U | ||
| 448 | #define IOMUXC_GPIO_AD_B0_06_CSI_DATA07 0x401F80D4U, 0x4U, 0x401F8414U, 0x1U, 0x401F82C4U | ||
| 449 | #define IOMUXC_GPIO_AD_B0_06_GPIO1_IO06 0x401F80D4U, 0x5U, 0, 0, 0x401F82C4U | ||
| 450 | #define IOMUXC_GPIO_AD_B0_06_XBAR1_INOUT18 0x401F80D4U, 0x6U, 0x401F8630U, 0x1U, 0x401F82C4U | ||
| 451 | #define IOMUXC_GPIO_AD_B0_06_LPSPI3_PCS3 0x401F80D4U, 0x7U, 0, 0, 0x401F82C4U | ||
| 452 | |||
| 453 | #define IOMUXC_GPIO_AD_B0_07_JTAG_TCK 0x401F80D8U, 0x0U, 0, 0, 0x401F82C8U | ||
| 454 | #define IOMUXC_GPIO_AD_B0_07_GPT2_COMPARE2 0x401F80D8U, 0x1U, 0, 0, 0x401F82C8U | ||
| 455 | #define IOMUXC_GPIO_AD_B0_07_ENET_TX_ER 0x401F80D8U, 0x2U, 0, 0, 0x401F82C8U | ||
| 456 | #define IOMUXC_GPIO_AD_B0_07_SAI2_RX_SYNC 0x401F80D8U, 0x3U, 0x401F85BCU, 0x1U, 0x401F82C8U | ||
| 457 | #define IOMUXC_GPIO_AD_B0_07_CSI_DATA06 0x401F80D8U, 0x4U, 0x401F8410U, 0x1U, 0x401F82C8U | ||
| 458 | #define IOMUXC_GPIO_AD_B0_07_GPIO1_IO07 0x401F80D8U, 0x5U, 0, 0, 0x401F82C8U | ||
| 459 | #define IOMUXC_GPIO_AD_B0_07_XBAR1_INOUT19 0x401F80D8U, 0x6U, 0x401F8654U, 0x1U, 0x401F82C8U | ||
| 460 | #define IOMUXC_GPIO_AD_B0_07_ENET_1588_EVENT3_OUT 0x401F80D8U, 0x7U, 0, 0, 0x401F82C8U | ||
| 461 | |||
| 462 | #define IOMUXC_GPIO_AD_B0_08_JTAG_MOD 0x401F80DCU, 0x0U, 0, 0, 0x401F82CCU | ||
| 463 | #define IOMUXC_GPIO_AD_B0_08_GPT2_COMPARE3 0x401F80DCU, 0x1U, 0, 0, 0x401F82CCU | ||
| 464 | #define IOMUXC_GPIO_AD_B0_08_ENET_RX_DATA03 0x401F80DCU, 0x2U, 0, 0, 0x401F82CCU | ||
| 465 | #define IOMUXC_GPIO_AD_B0_08_SAI2_RX_DATA 0x401F80DCU, 0x3U, 0x401F85B8U, 0x1U, 0x401F82CCU | ||
| 466 | #define IOMUXC_GPIO_AD_B0_08_CSI_DATA05 0x401F80DCU, 0x4U, 0x401F840CU, 0x1U, 0x401F82CCU | ||
| 467 | #define IOMUXC_GPIO_AD_B0_08_GPIO1_IO08 0x401F80DCU, 0x5U, 0, 0, 0x401F82CCU | ||
| 468 | #define IOMUXC_GPIO_AD_B0_08_XBAR1_IN20 0x401F80DCU, 0x6U, 0x401F8634U, 0x1U, 0x401F82CCU | ||
| 469 | #define IOMUXC_GPIO_AD_B0_08_ENET_1588_EVENT3_IN 0x401F80DCU, 0x7U, 0, 0, 0x401F82CCU | ||
| 470 | |||
| 471 | #define IOMUXC_GPIO_AD_B0_09_JTAG_TDI 0x401F80E0U, 0x0U, 0, 0, 0x401F82D0U | ||
| 472 | #define IOMUXC_GPIO_AD_B0_09_FLEXPWM2_PWMA03 0x401F80E0U, 0x1U, 0x401F8474U, 0x3U, 0x401F82D0U | ||
| 473 | #define IOMUXC_GPIO_AD_B0_09_ENET_RX_DATA02 0x401F80E0U, 0x2U, 0, 0, 0x401F82D0U | ||
| 474 | #define IOMUXC_GPIO_AD_B0_09_SAI2_TX_DATA 0x401F80E0U, 0x3U, 0, 0, 0x401F82D0U | ||
| 475 | #define IOMUXC_GPIO_AD_B0_09_CSI_DATA04 0x401F80E0U, 0x4U, 0x401F8408U, 0x1U, 0x401F82D0U | ||
| 476 | #define IOMUXC_GPIO_AD_B0_09_GPIO1_IO09 0x401F80E0U, 0x5U, 0, 0, 0x401F82D0U | ||
| 477 | #define IOMUXC_GPIO_AD_B0_09_XBAR1_IN21 0x401F80E0U, 0x6U, 0x401F8658U, 0x1U, 0x401F82D0U | ||
| 478 | #define IOMUXC_GPIO_AD_B0_09_GPT2_CLK 0x401F80E0U, 0x7U, 0x401F876CU, 0x0U, 0x401F82D0U | ||
| 479 | #define IOMUXC_GPIO_AD_B0_09_SEMC_DQS4 0x401F80E0U, 0x9U, 0x401F8788U, 0x2U, 0x401F82D0U | ||
| 480 | |||
| 481 | #define IOMUXC_GPIO_AD_B0_10_JTAG_TDO 0x401F80E4U, 0x0U, 0, 0, 0x401F82D4U | ||
| 482 | #define IOMUXC_GPIO_AD_B0_10_FLEXPWM1_PWMA03 0x401F80E4U, 0x1U, 0x401F8454U, 0x3U, 0x401F82D4U | ||
| 483 | #define IOMUXC_GPIO_AD_B0_10_ENET_CRS 0x401F80E4U, 0x2U, 0, 0, 0x401F82D4U | ||
| 484 | #define IOMUXC_GPIO_AD_B0_10_SAI2_MCLK 0x401F80E4U, 0x3U, 0x401F85B0U, 0x1U, 0x401F82D4U | ||
| 485 | #define IOMUXC_GPIO_AD_B0_10_CSI_DATA03 0x401F80E4U, 0x4U, 0x401F8404U, 0x1U, 0x401F82D4U | ||
| 486 | #define IOMUXC_GPIO_AD_B0_10_GPIO1_IO10 0x401F80E4U, 0x5U, 0, 0, 0x401F82D4U | ||
| 487 | #define IOMUXC_GPIO_AD_B0_10_XBAR1_IN22 0x401F80E4U, 0x6U, 0x401F8638U, 0x1U, 0x401F82D4U | ||
| 488 | #define IOMUXC_GPIO_AD_B0_10_ENET_1588_EVENT0_OUT 0x401F80E4U, 0x7U, 0, 0, 0x401F82D4U | ||
| 489 | #define IOMUXC_GPIO_AD_B0_10_FLEXCAN3_TX 0x401F80E4U, 0x8U, 0, 0, 0x401F82D4U | ||
| 490 | #define IOMUXC_GPIO_AD_B0_10_ARM_TRACE_SWO 0x401F80E4U, 0x9U, 0, 0, 0x401F82D4U | ||
| 491 | |||
| 492 | #define IOMUXC_GPIO_AD_B0_11_JTAG_TRSTB 0x401F80E8U, 0x0U, 0, 0, 0x401F82D8U | ||
| 493 | #define IOMUXC_GPIO_AD_B0_11_FLEXPWM1_PWMB03 0x401F80E8U, 0x1U, 0x401F8464U, 0x3U, 0x401F82D8U | ||
| 494 | #define IOMUXC_GPIO_AD_B0_11_ENET_COL 0x401F80E8U, 0x2U, 0, 0, 0x401F82D8U | ||
| 495 | #define IOMUXC_GPIO_AD_B0_11_WDOG1_WDOG_B 0x401F80E8U, 0x3U, 0, 0, 0x401F82D8U | ||
| 496 | #define IOMUXC_GPIO_AD_B0_11_CSI_DATA02 0x401F80E8U, 0x4U, 0x401F8400U, 0x1U, 0x401F82D8U | ||
| 497 | #define IOMUXC_GPIO_AD_B0_11_GPIO1_IO11 0x401F80E8U, 0x5U, 0, 0, 0x401F82D8U | ||
| 498 | #define IOMUXC_GPIO_AD_B0_11_XBAR1_IN23 0x401F80E8U, 0x6U, 0x401F863CU, 0x1U, 0x401F82D8U | ||
| 499 | #define IOMUXC_GPIO_AD_B0_11_ENET_1588_EVENT0_IN 0x401F80E8U, 0x7U, 0x401F8444U, 0x1U, 0x401F82D8U | ||
| 500 | #define IOMUXC_GPIO_AD_B0_11_FLEXCAN3_RX 0x401F80E8U, 0x8U, 0x401F878CU, 0x2U, 0x401F82D8U | ||
| 501 | #define IOMUXC_GPIO_AD_B0_11_SEMC_CLK6 0x401F80E8U, 0x9U, 0, 0, 0x401F82D8U | ||
| 502 | |||
| 503 | #define IOMUXC_GPIO_AD_B0_12_LPI2C4_SCL 0x401F80ECU, 0x0U, 0x401F84E4U, 0x1U, 0x401F82DCU | ||
| 504 | #define IOMUXC_GPIO_AD_B0_12_CCM_PMIC_READY 0x401F80ECU, 0x1U, 0x401F83FCU, 0x1U, 0x401F82DCU | ||
| 505 | #define IOMUXC_GPIO_AD_B0_12_LPUART1_TX 0x401F80ECU, 0x2U, 0, 0, 0x401F82DCU | ||
| 506 | #define IOMUXC_GPIO_AD_B0_12_WDOG2_WDOG_B 0x401F80ECU, 0x3U, 0, 0, 0x401F82DCU | ||
| 507 | #define IOMUXC_GPIO_AD_B0_12_FLEXPWM1_PWMX02 0x401F80ECU, 0x4U, 0, 0, 0x401F82DCU | ||
| 508 | #define IOMUXC_GPIO_AD_B0_12_GPIO1_IO12 0x401F80ECU, 0x5U, 0, 0, 0x401F82DCU | ||
| 509 | #define IOMUXC_GPIO_AD_B0_12_ENET_1588_EVENT1_OUT 0x401F80ECU, 0x6U, 0, 0, 0x401F82DCU | ||
| 510 | #define IOMUXC_GPIO_AD_B0_12_NMI_GLUE_NMI 0x401F80ECU, 0x7U, 0x401F8568U, 0x0U, 0x401F82DCU | ||
| 511 | |||
| 512 | #define IOMUXC_GPIO_AD_B0_13_LPI2C4_SDA 0x401F80F0U, 0x0U, 0x401F84E8U, 0x1U, 0x401F82E0U | ||
| 513 | #define IOMUXC_GPIO_AD_B0_13_GPT1_CLK 0x401F80F0U, 0x1U, 0x401F8760U, 0x0U, 0x401F82E0U | ||
| 514 | #define IOMUXC_GPIO_AD_B0_13_LPUART1_RX 0x401F80F0U, 0x2U, 0, 0, 0x401F82E0U | ||
| 515 | #define IOMUXC_GPIO_AD_B0_13_EWM_OUT_B 0x401F80F0U, 0x3U, 0, 0, 0x401F82E0U | ||
| 516 | #define IOMUXC_GPIO_AD_B0_13_FLEXPWM1_PWMX03 0x401F80F0U, 0x4U, 0, 0, 0x401F82E0U | ||
| 517 | #define IOMUXC_GPIO_AD_B0_13_GPIO1_IO13 0x401F80F0U, 0x5U, 0, 0, 0x401F82E0U | ||
| 518 | #define IOMUXC_GPIO_AD_B0_13_ENET_1588_EVENT1_IN 0x401F80F0U, 0x6U, 0, 0, 0x401F82E0U | ||
| 519 | #define IOMUXC_GPIO_AD_B0_13_REF_CLK_24M 0x401F80F0U, 0x7U, 0, 0, 0x401F82E0U | ||
| 520 | |||
| 521 | #define IOMUXC_GPIO_AD_B0_14_USB_OTG2_OC 0x401F80F4U, 0x0U, 0x401F85CCU, 0x0U, 0x401F82E4U | ||
| 522 | #define IOMUXC_GPIO_AD_B0_14_XBAR1_IN24 0x401F80F4U, 0x1U, 0x401F8640U, 0x1U, 0x401F82E4U | ||
| 523 | #define IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B 0x401F80F4U, 0x2U, 0, 0, 0x401F82E4U | ||
| 524 | #define IOMUXC_GPIO_AD_B0_14_ENET_1588_EVENT0_OUT 0x401F80F4U, 0x3U, 0, 0, 0x401F82E4U | ||
| 525 | #define IOMUXC_GPIO_AD_B0_14_CSI_VSYNC 0x401F80F4U, 0x4U, 0x401F8428U, 0x0U, 0x401F82E4U | ||
| 526 | #define IOMUXC_GPIO_AD_B0_14_GPIO1_IO14 0x401F80F4U, 0x5U, 0, 0, 0x401F82E4U | ||
| 527 | #define IOMUXC_GPIO_AD_B0_14_FLEXCAN2_TX 0x401F80F4U, 0x6U, 0, 0, 0x401F82E4U | ||
| 528 | #define IOMUXC_GPIO_AD_B0_14_FLEXCAN3_TX 0x401F80F4U, 0x8U, 0, 0, 0x401F82E4U | ||
| 529 | |||
| 530 | #define IOMUXC_GPIO_AD_B0_15_USB_OTG2_PWR 0x401F80F8U, 0x0U, 0, 0, 0x401F82E8U | ||
| 531 | #define IOMUXC_GPIO_AD_B0_15_XBAR1_IN25 0x401F80F8U, 0x1U, 0x401F8650U, 0x0U, 0x401F82E8U | ||
| 532 | #define IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B 0x401F80F8U, 0x2U, 0, 0, 0x401F82E8U | ||
| 533 | #define IOMUXC_GPIO_AD_B0_15_ENET_1588_EVENT0_IN 0x401F80F8U, 0x3U, 0x401F8444U, 0x0U, 0x401F82E8U | ||
| 534 | #define IOMUXC_GPIO_AD_B0_15_CSI_HSYNC 0x401F80F8U, 0x4U, 0x401F8420U, 0x0U, 0x401F82E8U | ||
| 535 | #define IOMUXC_GPIO_AD_B0_15_GPIO1_IO15 0x401F80F8U, 0x5U, 0, 0, 0x401F82E8U | ||
| 536 | #define IOMUXC_GPIO_AD_B0_15_FLEXCAN2_RX 0x401F80F8U, 0x6U, 0x401F8450U, 0x2U, 0x401F82E8U | ||
| 537 | #define IOMUXC_GPIO_AD_B0_15_WDOG1_WDOG_RST_B_DEB 0x401F80F8U, 0x7U, 0, 0, 0x401F82E8U | ||
| 538 | #define IOMUXC_GPIO_AD_B0_15_FLEXCAN3_RX 0x401F80F8U, 0x8U, 0x401F878CU, 0x1U, 0x401F82E8U | ||
| 539 | |||
| 540 | #define IOMUXC_GPIO_AD_B1_00_USB_OTG2_ID 0x401F80FCU, 0x0U, 0x401F83F8U, 0x1U, 0x401F82ECU | ||
| 541 | #define IOMUXC_GPIO_AD_B1_00_QTIMER3_TIMER0 0x401F80FCU, 0x1U, 0x401F857CU, 0x1U, 0x401F82ECU | ||
| 542 | #define IOMUXC_GPIO_AD_B1_00_LPUART2_CTS_B 0x401F80FCU, 0x2U, 0, 0, 0x401F82ECU | ||
| 543 | #define IOMUXC_GPIO_AD_B1_00_LPI2C1_SCL 0x401F80FCU, 0x3U, 0x401F84CCU, 0x1U, 0x401F82ECU | ||
| 544 | #define IOMUXC_GPIO_AD_B1_00_WDOG1_B 0x401F80FCU, 0x4U, 0, 0, 0x401F82ECU | ||
| 545 | #define IOMUXC_GPIO_AD_B1_00_GPIO1_IO16 0x401F80FCU, 0x5U, 0, 0, 0x401F82ECU | ||
| 546 | #define IOMUXC_GPIO_AD_B1_00_USDHC1_WP 0x401F80FCU, 0x6U, 0x401F85D8U, 0x2U, 0x401F82ECU | ||
| 547 | #define IOMUXC_GPIO_AD_B1_00_KPP_ROW07 0x401F80FCU, 0x7U, 0, 0, 0x401F82ECU | ||
| 548 | #define IOMUXC_GPIO_AD_B1_00_ENET2_1588_EVENT0_OUT 0x401F80FCU, 0x8U, 0, 0, 0x401F82ECU | ||
| 549 | #define IOMUXC_GPIO_AD_B1_00_FLEXIO3_FLEXIO00 0x401F80FCU, 0x9U, 0, 0, 0x401F82ECU | ||
| 550 | |||
| 551 | #define IOMUXC_GPIO_AD_B1_01_USB_OTG1_PWR 0x401F8100U, 0x0U, 0, 0, 0x401F82F0U | ||
| 552 | #define IOMUXC_GPIO_AD_B1_01_QTIMER3_TIMER1 0x401F8100U, 0x1U, 0x401F8580U, 0x0U, 0x401F82F0U | ||
| 553 | #define IOMUXC_GPIO_AD_B1_01_LPUART2_RTS_B 0x401F8100U, 0x2U, 0, 0, 0x401F82F0U | ||
| 554 | #define IOMUXC_GPIO_AD_B1_01_LPI2C1_SDA 0x401F8100U, 0x3U, 0x401F84D0U, 0x1U, 0x401F82F0U | ||
| 555 | #define IOMUXC_GPIO_AD_B1_01_CCM_PMIC_READY 0x401F8100U, 0x4U, 0x401F83FCU, 0x2U, 0x401F82F0U | ||
| 556 | #define IOMUXC_GPIO_AD_B1_01_GPIO1_IO17 0x401F8100U, 0x5U, 0, 0, 0x401F82F0U | ||
| 557 | #define IOMUXC_GPIO_AD_B1_01_USDHC1_VSELECT 0x401F8100U, 0x6U, 0, 0, 0x401F82F0U | ||
| 558 | #define IOMUXC_GPIO_AD_B1_01_KPP_COL07 0x401F8100U, 0x7U, 0, 0, 0x401F82F0U | ||
| 559 | #define IOMUXC_GPIO_AD_B1_01_ENET2_1588_EVENT0_IN 0x401F8100U, 0x8U, 0x401F8724U, 0x0U, 0x401F82F0U | ||
| 560 | #define IOMUXC_GPIO_AD_B1_01_FLEXIO3_FLEXIO01 0x401F8100U, 0x9U, 0, 0, 0x401F82F0U | ||
| 561 | |||
| 562 | #define IOMUXC_GPIO_AD_B1_02_USB_OTG1_ID 0x401F8104U, 0x0U, 0x401F83F4U, 0x1U, 0x401F82F4U | ||
| 563 | #define IOMUXC_GPIO_AD_B1_02_QTIMER3_TIMER2 0x401F8104U, 0x1U, 0x401F8584U, 0x1U, 0x401F82F4U | ||
| 564 | #define IOMUXC_GPIO_AD_B1_02_LPUART2_TX 0x401F8104U, 0x2U, 0x401F8530U, 0x1U, 0x401F82F4U | ||
| 565 | #define IOMUXC_GPIO_AD_B1_02_SPDIF_OUT 0x401F8104U, 0x3U, 0, 0, 0x401F82F4U | ||
| 566 | #define IOMUXC_GPIO_AD_B1_02_ENET_1588_EVENT2_OUT 0x401F8104U, 0x4U, 0, 0, 0x401F82F4U | ||
| 567 | #define IOMUXC_GPIO_AD_B1_02_GPIO1_IO18 0x401F8104U, 0x5U, 0, 0, 0x401F82F4U | ||
| 568 | #define IOMUXC_GPIO_AD_B1_02_USDHC1_CD_B 0x401F8104U, 0x6U, 0x401F85D4U, 0x1U, 0x401F82F4U | ||
| 569 | #define IOMUXC_GPIO_AD_B1_02_KPP_ROW06 0x401F8104U, 0x7U, 0, 0, 0x401F82F4U | ||
| 570 | #define IOMUXC_GPIO_AD_B1_02_GPT2_CLK 0x401F8104U, 0x8U, 0x401F876CU, 0x1U, 0x401F82F4U | ||
| 571 | #define IOMUXC_GPIO_AD_B1_02_FLEXIO3_FLEXIO02 0x401F8104U, 0x9U, 0, 0, 0x401F82F4U | ||
| 572 | |||
| 573 | #define IOMUXC_GPIO_AD_B1_03_USB_OTG1_OC 0x401F8108U, 0x0U, 0x401F85D0U, 0x1U, 0x401F82F8U | ||
| 574 | #define IOMUXC_GPIO_AD_B1_03_QTIMER3_TIMER3 0x401F8108U, 0x1U, 0x401F8588U, 0x1U, 0x401F82F8U | ||
| 575 | #define IOMUXC_GPIO_AD_B1_03_LPUART2_RX 0x401F8108U, 0x2U, 0x401F852CU, 0x1U, 0x401F82F8U | ||
| 576 | #define IOMUXC_GPIO_AD_B1_03_SPDIF_IN 0x401F8108U, 0x3U, 0x401F85C8U, 0x0U, 0x401F82F8U | ||
| 577 | #define IOMUXC_GPIO_AD_B1_03_ENET_1588_EVENT2_IN 0x401F8108U, 0x4U, 0, 0, 0x401F82F8U | ||
| 578 | #define IOMUXC_GPIO_AD_B1_03_GPIO1_IO19 0x401F8108U, 0x5U, 0, 0, 0x401F82F8U | ||
| 579 | #define IOMUXC_GPIO_AD_B1_03_USDHC2_CD_B 0x401F8108U, 0x6U, 0x401F85E0U, 0x0U, 0x401F82F8U | ||
| 580 | #define IOMUXC_GPIO_AD_B1_03_KPP_COL06 0x401F8108U, 0x7U, 0, 0, 0x401F82F8U | ||
| 581 | #define IOMUXC_GPIO_AD_B1_03_GPT2_CAPTURE1 0x401F8108U, 0x8U, 0x401F8764U, 0x1U, 0x401F82F8U | ||
| 582 | #define IOMUXC_GPIO_AD_B1_03_FLEXIO3_FLEXIO03 0x401F8108U, 0x9U, 0, 0, 0x401F82F8U | ||
| 583 | |||
| 584 | #define IOMUXC_GPIO_AD_B1_04_FLEXSPIB_DATA03 0x401F810CU, 0x0U, 0x401F84C4U, 0x1U, 0x401F82FCU | ||
| 585 | #define IOMUXC_GPIO_AD_B1_04_ENET_MDC 0x401F810CU, 0x1U, 0, 0, 0x401F82FCU | ||
| 586 | #define IOMUXC_GPIO_AD_B1_04_LPUART3_CTS_B 0x401F810CU, 0x2U, 0x401F8534U, 0x1U, 0x401F82FCU | ||
| 587 | #define IOMUXC_GPIO_AD_B1_04_SPDIF_SR_CLK 0x401F810CU, 0x3U, 0, 0, 0x401F82FCU | ||
| 588 | #define IOMUXC_GPIO_AD_B1_04_CSI_PIXCLK 0x401F810CU, 0x4U, 0x401F8424U, 0x0U, 0x401F82FCU | ||
| 589 | #define IOMUXC_GPIO_AD_B1_04_GPIO1_IO20 0x401F810CU, 0x5U, 0, 0, 0x401F82FCU | ||
| 590 | #define IOMUXC_GPIO_AD_B1_04_USDHC2_DATA0 0x401F810CU, 0x6U, 0x401F85E8U, 0x1U, 0x401F82FCU | ||
| 591 | #define IOMUXC_GPIO_AD_B1_04_KPP_ROW05 0x401F810CU, 0x7U, 0, 0, 0x401F82FCU | ||
| 592 | #define IOMUXC_GPIO_AD_B1_04_GPT2_CAPTURE2 0x401F810CU, 0x8U, 0x401F8768U, 0x1U, 0x401F82FCU | ||
| 593 | #define IOMUXC_GPIO_AD_B1_04_FLEXIO3_FLEXIO04 0x401F810CU, 0x9U, 0, 0, 0x401F82FCU | ||
| 594 | |||
| 595 | #define IOMUXC_GPIO_AD_B1_05_FLEXSPIB_DATA02 0x401F8110U, 0x0U, 0x401F84C0U, 0x1U, 0x401F8300U | ||
| 596 | #define IOMUXC_GPIO_AD_B1_05_ENET_MDIO 0x401F8110U, 0x1U, 0x401F8430U, 0x0U, 0x401F8300U | ||
| 597 | #define IOMUXC_GPIO_AD_B1_05_LPUART3_RTS_B 0x401F8110U, 0x2U, 0, 0, 0x401F8300U | ||
| 598 | #define IOMUXC_GPIO_AD_B1_05_SPDIF_OUT 0x401F8110U, 0x3U, 0, 0, 0x401F8300U | ||
| 599 | #define IOMUXC_GPIO_AD_B1_05_CSI_MCLK 0x401F8110U, 0x4U, 0, 0, 0x401F8300U | ||
| 600 | #define IOMUXC_GPIO_AD_B1_05_GPIO1_IO21 0x401F8110U, 0x5U, 0, 0, 0x401F8300U | ||
| 601 | #define IOMUXC_GPIO_AD_B1_05_USDHC2_DATA1 0x401F8110U, 0x6U, 0x401F85ECU, 0x1U, 0x401F8300U | ||
| 602 | #define IOMUXC_GPIO_AD_B1_05_KPP_COL05 0x401F8110U, 0x7U, 0, 0, 0x401F8300U | ||
| 603 | #define IOMUXC_GPIO_AD_B1_05_GPT2_COMPARE1 0x401F8110U, 0x8U, 0, 0, 0x401F8300U | ||
| 604 | #define IOMUXC_GPIO_AD_B1_05_FLEXIO3_FLEXIO05 0x401F8110U, 0x9U, 0, 0, 0x401F8300U | ||
| 605 | |||
| 606 | #define IOMUXC_GPIO_AD_B1_06_FLEXSPIB_DATA01 0x401F8114U, 0x0U, 0x401F84BCU, 0x1U, 0x401F8304U | ||
| 607 | #define IOMUXC_GPIO_AD_B1_06_LPI2C3_SDA 0x401F8114U, 0x1U, 0x401F84E0U, 0x2U, 0x401F8304U | ||
| 608 | #define IOMUXC_GPIO_AD_B1_06_LPUART3_TX 0x401F8114U, 0x2U, 0x401F853CU, 0x0U, 0x401F8304U | ||
| 609 | #define IOMUXC_GPIO_AD_B1_06_SPDIF_LOCK 0x401F8114U, 0x3U, 0, 0, 0x401F8304U | ||
| 610 | #define IOMUXC_GPIO_AD_B1_06_CSI_VSYNC 0x401F8114U, 0x4U, 0x401F8428U, 0x1U, 0x401F8304U | ||
| 611 | #define IOMUXC_GPIO_AD_B1_06_GPIO1_IO22 0x401F8114U, 0x5U, 0, 0, 0x401F8304U | ||
| 612 | #define IOMUXC_GPIO_AD_B1_06_USDHC2_DATA2 0x401F8114U, 0x6U, 0x401F85F0U, 0x1U, 0x401F8304U | ||
| 613 | #define IOMUXC_GPIO_AD_B1_06_KPP_ROW04 0x401F8114U, 0x7U, 0, 0, 0x401F8304U | ||
| 614 | #define IOMUXC_GPIO_AD_B1_06_GPT2_COMPARE2 0x401F8114U, 0x8U, 0, 0, 0x401F8304U | ||
| 615 | #define IOMUXC_GPIO_AD_B1_06_FLEXIO3_FLEXIO06 0x401F8114U, 0x9U, 0, 0, 0x401F8304U | ||
| 616 | |||
| 617 | #define IOMUXC_GPIO_AD_B1_07_FLEXSPIB_DATA00 0x401F8118U, 0x0U, 0x401F84B8U, 0x1U, 0x401F8308U | ||
| 618 | #define IOMUXC_GPIO_AD_B1_07_LPI2C3_SCL 0x401F8118U, 0x1U, 0x401F84DCU, 0x2U, 0x401F8308U | ||
| 619 | #define IOMUXC_GPIO_AD_B1_07_LPUART3_RX 0x401F8118U, 0x2U, 0x401F8538U, 0x0U, 0x401F8308U | ||
| 620 | #define IOMUXC_GPIO_AD_B1_07_SPDIF_EXT_CLK 0x401F8118U, 0x3U, 0, 0, 0x401F8308U | ||
| 621 | #define IOMUXC_GPIO_AD_B1_07_CSI_HSYNC 0x401F8118U, 0x4U, 0x401F8420U, 0x1U, 0x401F8308U | ||
| 622 | #define IOMUXC_GPIO_AD_B1_07_GPIO1_IO23 0x401F8118U, 0x5U, 0, 0, 0x401F8308U | ||
| 623 | #define IOMUXC_GPIO_AD_B1_07_USDHC2_DATA3 0x401F8118U, 0x6U, 0x401F85F4U, 0x1U, 0x401F8308U | ||
| 624 | #define IOMUXC_GPIO_AD_B1_07_KPP_COL04 0x401F8118U, 0x7U, 0, 0, 0x401F8308U | ||
| 625 | #define IOMUXC_GPIO_AD_B1_07_GPT2_COMPARE3 0x401F8118U, 0x8U, 0, 0, 0x401F8308U | ||
| 626 | #define IOMUXC_GPIO_AD_B1_07_FLEXIO3_FLEXIO07 0x401F8118U, 0x9U, 0, 0, 0x401F8308U | ||
| 627 | |||
| 628 | #define IOMUXC_GPIO_AD_B1_08_FLEXSPIA_SS1_B 0x401F811CU, 0x0U, 0, 0, 0x401F830CU | ||
| 629 | #define IOMUXC_GPIO_AD_B1_08_FLEXPWM4_PWMA00 0x401F811CU, 0x1U, 0x401F8494U, 0x1U, 0x401F830CU | ||
| 630 | #define IOMUXC_GPIO_AD_B1_08_FLEXCAN1_TX 0x401F811CU, 0x2U, 0, 0, 0x401F830CU | ||
| 631 | #define IOMUXC_GPIO_AD_B1_08_CCM_PMIC_READY 0x401F811CU, 0x3U, 0x401F83FCU, 0x3U, 0x401F830CU | ||
| 632 | #define IOMUXC_GPIO_AD_B1_08_CSI_DATA09 0x401F811CU, 0x4U, 0x401F841CU, 0x0U, 0x401F830CU | ||
| 633 | #define IOMUXC_GPIO_AD_B1_08_GPIO1_IO24 0x401F811CU, 0x5U, 0, 0, 0x401F830CU | ||
| 634 | #define IOMUXC_GPIO_AD_B1_08_USDHC2_CMD 0x401F811CU, 0x6U, 0x401F85E4U, 0x1U, 0x401F830CU | ||
| 635 | #define IOMUXC_GPIO_AD_B1_08_KPP_ROW03 0x401F811CU, 0x7U, 0, 0, 0x401F830CU | ||
| 636 | #define IOMUXC_GPIO_AD_B1_08_FLEXIO3_FLEXIO08 0x401F811CU, 0x9U, 0, 0, 0x401F830CU | ||
| 637 | |||
| 638 | #define IOMUXC_GPIO_AD_B1_09_FLEXSPIA_DQS 0x401F8120U, 0x0U, 0x401F84A4U, 0x1U, 0x401F8310U | ||
| 639 | #define IOMUXC_GPIO_AD_B1_09_FLEXPWM4_PWMA01 0x401F8120U, 0x1U, 0x401F8498U, 0x1U, 0x401F8310U | ||
| 640 | #define IOMUXC_GPIO_AD_B1_09_FLEXCAN1_RX 0x401F8120U, 0x2U, 0x401F844CU, 0x2U, 0x401F8310U | ||
| 641 | #define IOMUXC_GPIO_AD_B1_09_SAI1_MCLK 0x401F8120U, 0x3U, 0x401F858CU, 0x1U, 0x401F8310U | ||
| 642 | #define IOMUXC_GPIO_AD_B1_09_CSI_DATA08 0x401F8120U, 0x4U, 0x401F8418U, 0x0U, 0x401F8310U | ||
| 643 | #define IOMUXC_GPIO_AD_B1_09_GPIO1_IO25 0x401F8120U, 0x5U, 0, 0, 0x401F8310U | ||
| 644 | #define IOMUXC_GPIO_AD_B1_09_USDHC2_CLK 0x401F8120U, 0x6U, 0x401F85DCU, 0x1U, 0x401F8310U | ||
| 645 | #define IOMUXC_GPIO_AD_B1_09_KPP_COL03 0x401F8120U, 0x7U, 0, 0, 0x401F8310U | ||
| 646 | #define IOMUXC_GPIO_AD_B1_09_FLEXIO3_FLEXIO09 0x401F8120U, 0x9U, 0, 0, 0x401F8310U | ||
| 647 | |||
| 648 | #define IOMUXC_GPIO_AD_B1_10_FLEXSPIA_DATA03 0x401F8124U, 0x0U, 0x401F84B4U, 0x1U, 0x401F8314U | ||
| 649 | #define IOMUXC_GPIO_AD_B1_10_WDOG1_B 0x401F8124U, 0x1U, 0, 0, 0x401F8314U | ||
| 650 | #define IOMUXC_GPIO_AD_B1_10_LPUART8_TX 0x401F8124U, 0x2U, 0x401F8564U, 0x1U, 0x401F8314U | ||
| 651 | #define IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC 0x401F8124U, 0x3U, 0x401F85A4U, 0x1U, 0x401F8314U | ||
| 652 | #define IOMUXC_GPIO_AD_B1_10_CSI_DATA07 0x401F8124U, 0x4U, 0x401F8414U, 0x0U, 0x401F8314U | ||
| 653 | #define IOMUXC_GPIO_AD_B1_10_GPIO1_IO26 0x401F8124U, 0x5U, 0, 0, 0x401F8314U | ||
| 654 | #define IOMUXC_GPIO_AD_B1_10_USDHC2_WP 0x401F8124U, 0x6U, 0x401F8608U, 0x1U, 0x401F8314U | ||
| 655 | #define IOMUXC_GPIO_AD_B1_10_KPP_ROW02 0x401F8124U, 0x7U, 0, 0, 0x401F8314U | ||
| 656 | #define IOMUXC_GPIO_AD_B1_10_ENET2_1588_EVENT1_OUT 0x401F8124U, 0x8U, 0, 0, 0x401F8314U | ||
| 657 | #define IOMUXC_GPIO_AD_B1_10_FLEXIO3_FLEXIO10 0x401F8124U, 0x9U, 0, 0, 0x401F8314U | ||
| 658 | |||
| 659 | #define IOMUXC_GPIO_AD_B1_11_FLEXSPIA_DATA02 0x401F8128U, 0x0U, 0x401F84B0U, 0x1U, 0x401F8318U | ||
| 660 | #define IOMUXC_GPIO_AD_B1_11_EWM_OUT_B 0x401F8128U, 0x1U, 0, 0, 0x401F8318U | ||
| 661 | #define IOMUXC_GPIO_AD_B1_11_LPUART8_RX 0x401F8128U, 0x2U, 0x401F8560U, 0x1U, 0x401F8318U | ||
| 662 | #define IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK 0x401F8128U, 0x3U, 0x401F8590U, 0x1U, 0x401F8318U | ||
| 663 | #define IOMUXC_GPIO_AD_B1_11_CSI_DATA06 0x401F8128U, 0x4U, 0x401F8410U, 0x0U, 0x401F8318U | ||
| 664 | #define IOMUXC_GPIO_AD_B1_11_GPIO1_IO27 0x401F8128U, 0x5U, 0, 0, 0x401F8318U | ||
| 665 | #define IOMUXC_GPIO_AD_B1_11_USDHC2_RESET_B 0x401F8128U, 0x6U, 0, 0, 0x401F8318U | ||
| 666 | #define IOMUXC_GPIO_AD_B1_11_KPP_COL02 0x401F8128U, 0x7U, 0, 0, 0x401F8318U | ||
| 667 | #define IOMUXC_GPIO_AD_B1_11_ENET2_1588_EVENT1_IN 0x401F8128U, 0x8U, 0, 0, 0x401F8318U | ||
| 668 | #define IOMUXC_GPIO_AD_B1_11_FLEXIO3_FLEXIO11 0x401F8128U, 0x9U, 0, 0, 0x401F8318U | ||
| 669 | |||
| 670 | #define IOMUXC_GPIO_AD_B1_12_FLEXSPIA_DATA01 0x401F812CU, 0x0U, 0x401F84ACU, 0x1U, 0x401F831CU | ||
| 671 | #define IOMUXC_GPIO_AD_B1_12_ACMP_OUT00 0x401F812CU, 0x1U, 0, 0, 0x401F831CU | ||
| 672 | #define IOMUXC_GPIO_AD_B1_12_LPSPI3_PCS0 0x401F812CU, 0x2U, 0x401F850CU, 0x1U, 0x401F831CU | ||
| 673 | #define IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00 0x401F812CU, 0x3U, 0x401F8594U, 0x1U, 0x401F831CU | ||
| 674 | #define IOMUXC_GPIO_AD_B1_12_CSI_DATA05 0x401F812CU, 0x4U, 0x401F840CU, 0x0U, 0x401F831CU | ||
| 675 | #define IOMUXC_GPIO_AD_B1_12_GPIO1_IO28 0x401F812CU, 0x5U, 0, 0, 0x401F831CU | ||
| 676 | #define IOMUXC_GPIO_AD_B1_12_USDHC2_DATA4 0x401F812CU, 0x6U, 0x401F85F8U, 0x1U, 0x401F831CU | ||
| 677 | #define IOMUXC_GPIO_AD_B1_12_KPP_ROW01 0x401F812CU, 0x7U, 0, 0, 0x401F831CU | ||
| 678 | #define IOMUXC_GPIO_AD_B1_12_ENET2_1588_EVENT2_OUT 0x401F812CU, 0x8U, 0, 0, 0x401F831CU | ||
| 679 | #define IOMUXC_GPIO_AD_B1_12_FLEXIO3_FLEXIO12 0x401F812CU, 0x9U, 0, 0, 0x401F831CU | ||
| 680 | |||
| 681 | #define IOMUXC_GPIO_AD_B1_13_FLEXSPIA_DATA00 0x401F8130U, 0x0U, 0x401F84A8U, 0x1U, 0x401F8320U | ||
| 682 | #define IOMUXC_GPIO_AD_B1_13_ACMP_OUT01 0x401F8130U, 0x1U, 0, 0, 0x401F8320U | ||
| 683 | #define IOMUXC_GPIO_AD_B1_13_LPSPI3_SDI 0x401F8130U, 0x2U, 0x401F8514U, 0x1U, 0x401F8320U | ||
| 684 | #define IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00 0x401F8130U, 0x3U, 0, 0, 0x401F8320U | ||
| 685 | #define IOMUXC_GPIO_AD_B1_13_CSI_DATA04 0x401F8130U, 0x4U, 0x401F8408U, 0x0U, 0x401F8320U | ||
| 686 | #define IOMUXC_GPIO_AD_B1_13_GPIO1_IO29 0x401F8130U, 0x5U, 0, 0, 0x401F8320U | ||
| 687 | #define IOMUXC_GPIO_AD_B1_13_USDHC2_DATA5 0x401F8130U, 0x6U, 0x401F85FCU, 0x1U, 0x401F8320U | ||
| 688 | #define IOMUXC_GPIO_AD_B1_13_KPP_COL01 0x401F8130U, 0x7U, 0, 0, 0x401F8320U | ||
| 689 | #define IOMUXC_GPIO_AD_B1_13_ENET2_1588_EVENT2_IN 0x401F8130U, 0x8U, 0, 0, 0x401F8320U | ||
| 690 | #define IOMUXC_GPIO_AD_B1_13_FLEXIO3_FLEXIO13 0x401F8130U, 0x9U, 0, 0, 0x401F8320U | ||
| 691 | |||
| 692 | #define IOMUXC_GPIO_AD_B1_14_FLEXSPIA_SCLK 0x401F8134U, 0x0U, 0x401F84C8U, 0x1U, 0x401F8324U | ||
| 693 | #define IOMUXC_GPIO_AD_B1_14_ACMP_OUT02 0x401F8134U, 0x1U, 0, 0, 0x401F8324U | ||
| 694 | #define IOMUXC_GPIO_AD_B1_14_LPSPI3_SDO 0x401F8134U, 0x2U, 0x401F8518U, 0x1U, 0x401F8324U | ||
| 695 | #define IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK 0x401F8134U, 0x3U, 0x401F85A8U, 0x1U, 0x401F8324U | ||
| 696 | #define IOMUXC_GPIO_AD_B1_14_CSI_DATA03 0x401F8134U, 0x4U, 0x401F8404U, 0x0U, 0x401F8324U | ||
| 697 | #define IOMUXC_GPIO_AD_B1_14_GPIO1_IO30 0x401F8134U, 0x5U, 0, 0, 0x401F8324U | ||
| 698 | #define IOMUXC_GPIO_AD_B1_14_USDHC2_DATA6 0x401F8134U, 0x6U, 0x401F8600U, 0x1U, 0x401F8324U | ||
| 699 | #define IOMUXC_GPIO_AD_B1_14_KPP_ROW00 0x401F8134U, 0x7U, 0, 0, 0x401F8324U | ||
| 700 | #define IOMUXC_GPIO_AD_B1_14_ENET2_1588_EVENT3_OUT 0x401F8134U, 0x8U, 0, 0, 0x401F8324U | ||
| 701 | #define IOMUXC_GPIO_AD_B1_14_FLEXIO3_FLEXIO14 0x401F8134U, 0x9U, 0, 0, 0x401F8324U | ||
| 702 | |||
| 703 | #define IOMUXC_GPIO_AD_B1_15_FLEXSPIA_SS0_B 0x401F8138U, 0x0U, 0, 0, 0x401F8328U | ||
| 704 | #define IOMUXC_GPIO_AD_B1_15_ACMP_OUT03 0x401F8138U, 0x1U, 0, 0, 0x401F8328U | ||
| 705 | #define IOMUXC_GPIO_AD_B1_15_LPSPI3_SCK 0x401F8138U, 0x2U, 0x401F8510U, 0x1U, 0x401F8328U | ||
| 706 | #define IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC 0x401F8138U, 0x3U, 0x401F85ACU, 0x1U, 0x401F8328U | ||
| 707 | #define IOMUXC_GPIO_AD_B1_15_CSI_DATA02 0x401F8138U, 0x4U, 0x401F8400U, 0x0U, 0x401F8328U | ||
| 708 | #define IOMUXC_GPIO_AD_B1_15_GPIO1_IO31 0x401F8138U, 0x5U, 0, 0, 0x401F8328U | ||
| 709 | #define IOMUXC_GPIO_AD_B1_15_USDHC2_DATA7 0x401F8138U, 0x6U, 0x401F8604U, 0x1U, 0x401F8328U | ||
| 710 | #define IOMUXC_GPIO_AD_B1_15_KPP_COL00 0x401F8138U, 0x7U, 0, 0, 0x401F8328U | ||
| 711 | #define IOMUXC_GPIO_AD_B1_15_ENET2_1588_EVENT3_IN 0x401F8138U, 0x8U, 0, 0, 0x401F8328U | ||
| 712 | #define IOMUXC_GPIO_AD_B1_15_FLEXIO3_FLEXIO15 0x401F8138U, 0x9U, 0, 0, 0x401F8328U | ||
| 713 | |||
| 714 | #define IOMUXC_GPIO_B0_00_LCD_CLK 0x401F813CU, 0x0U, 0, 0, 0x401F832CU | ||
| 715 | #define IOMUXC_GPIO_B0_00_QTIMER1_TIMER0 0x401F813CU, 0x1U, 0, 0, 0x401F832CU | ||
| 716 | #define IOMUXC_GPIO_B0_00_MQS_RIGHT 0x401F813CU, 0x2U, 0, 0, 0x401F832CU | ||
| 717 | #define IOMUXC_GPIO_B0_00_LPSPI4_PCS0 0x401F813CU, 0x3U, 0x401F851CU, 0x0U, 0x401F832CU | ||
| 718 | #define IOMUXC_GPIO_B0_00_FLEXIO2_FLEXIO00 0x401F813CU, 0x4U, 0, 0, 0x401F832CU | ||
| 719 | #define IOMUXC_GPIO_B0_00_GPIO2_IO00 0x401F813CU, 0x5U, 0, 0, 0x401F832CU | ||
| 720 | #define IOMUXC_GPIO_B0_00_SEMC_CSX01 0x401F813CU, 0x6U, 0, 0, 0x401F832CU | ||
| 721 | #define IOMUXC_GPIO_B0_00_ENET2_MDC 0x401F813CU, 0x8U, 0, 0, 0x401F832CU | ||
| 722 | |||
| 723 | #define IOMUXC_GPIO_B0_01_LCD_ENABLE 0x401F8140U, 0x0U, 0, 0, 0x401F8330U | ||
| 724 | #define IOMUXC_GPIO_B0_01_QTIMER1_TIMER1 0x401F8140U, 0x1U, 0, 0, 0x401F8330U | ||
| 725 | #define IOMUXC_GPIO_B0_01_MQS_LEFT 0x401F8140U, 0x2U, 0, 0, 0x401F8330U | ||
| 726 | #define IOMUXC_GPIO_B0_01_LPSPI4_SDI 0x401F8140U, 0x3U, 0x401F8524U, 0x0U, 0x401F8330U | ||
| 727 | #define IOMUXC_GPIO_B0_01_FLEXIO2_FLEXIO01 0x401F8140U, 0x4U, 0, 0, 0x401F8330U | ||
| 728 | #define IOMUXC_GPIO_B0_01_GPIO2_IO01 0x401F8140U, 0x5U, 0, 0, 0x401F8330U | ||
| 729 | #define IOMUXC_GPIO_B0_01_SEMC_CSX02 0x401F8140U, 0x6U, 0, 0, 0x401F8330U | ||
| 730 | #define IOMUXC_GPIO_B0_01_ENET2_MDIO 0x401F8140U, 0x8U, 0x401F8710U, 0x1U, 0x401F8330U | ||
| 731 | |||
| 732 | #define IOMUXC_GPIO_B0_02_LCD_HSYNC 0x401F8144U, 0x0U, 0, 0, 0x401F8334U | ||
| 733 | #define IOMUXC_GPIO_B0_02_QTIMER1_TIMER2 0x401F8144U, 0x1U, 0, 0, 0x401F8334U | ||
| 734 | #define IOMUXC_GPIO_B0_02_FLEXCAN1_TX 0x401F8144U, 0x2U, 0, 0, 0x401F8334U | ||
| 735 | #define IOMUXC_GPIO_B0_02_LPSPI4_SDO 0x401F8144U, 0x3U, 0x401F8528U, 0x0U, 0x401F8334U | ||
| 736 | #define IOMUXC_GPIO_B0_02_FLEXIO2_FLEXIO02 0x401F8144U, 0x4U, 0, 0, 0x401F8334U | ||
| 737 | #define IOMUXC_GPIO_B0_02_GPIO2_IO02 0x401F8144U, 0x5U, 0, 0, 0x401F8334U | ||
| 738 | #define IOMUXC_GPIO_B0_02_SEMC_CSX03 0x401F8144U, 0x6U, 0, 0, 0x401F8334U | ||
| 739 | #define IOMUXC_GPIO_B0_02_ENET2_1588_EVENT0_OUT 0x401F8144U, 0x8U, 0, 0, 0x401F8334U | ||
| 740 | |||
| 741 | #define IOMUXC_GPIO_B0_03_LCD_VSYNC 0x401F8148U, 0x0U, 0, 0, 0x401F8338U | ||
| 742 | #define IOMUXC_GPIO_B0_03_QTIMER2_TIMER0 0x401F8148U, 0x1U, 0x401F856CU, 0x1U, 0x401F8338U | ||
| 743 | #define IOMUXC_GPIO_B0_03_FLEXCAN1_RX 0x401F8148U, 0x2U, 0x401F844CU, 0x3U, 0x401F8338U | ||
| 744 | #define IOMUXC_GPIO_B0_03_LPSPI4_SCK 0x401F8148U, 0x3U, 0x401F8520U, 0x0U, 0x401F8338U | ||
| 745 | #define IOMUXC_GPIO_B0_03_FLEXIO2_FLEXIO03 0x401F8148U, 0x4U, 0, 0, 0x401F8338U | ||
| 746 | #define IOMUXC_GPIO_B0_03_GPIO2_IO03 0x401F8148U, 0x5U, 0, 0, 0x401F8338U | ||
| 747 | #define IOMUXC_GPIO_B0_03_WDOG2_RESET_B_DEB 0x401F8148U, 0x6U, 0, 0, 0x401F8338U | ||
| 748 | #define IOMUXC_GPIO_B0_03_ENET2_1588_EVENT0_IN 0x401F8148U, 0x8U, 0x401F8724U, 0x1U, 0x401F8338U | ||
| 749 | |||
| 750 | #define IOMUXC_GPIO_B0_04_LCD_DATA00 0x401F814CU, 0x0U, 0, 0, 0x401F833CU | ||
| 751 | #define IOMUXC_GPIO_B0_04_QTIMER2_TIMER1 0x401F814CU, 0x1U, 0x401F8570U, 0x1U, 0x401F833CU | ||
| 752 | #define IOMUXC_GPIO_B0_04_LPI2C2_SCL 0x401F814CU, 0x2U, 0x401F84D4U, 0x1U, 0x401F833CU | ||
| 753 | #define IOMUXC_GPIO_B0_04_ARM_TRACE0 0x401F814CU, 0x3U, 0, 0, 0x401F833CU | ||
| 754 | #define IOMUXC_GPIO_B0_04_FLEXIO2_FLEXIO04 0x401F814CU, 0x4U, 0, 0, 0x401F833CU | ||
| 755 | #define IOMUXC_GPIO_B0_04_GPIO2_IO04 0x401F814CU, 0x5U, 0, 0, 0x401F833CU | ||
| 756 | #define IOMUXC_GPIO_B0_04_SRC_BOOT_CFG00 0x401F814CU, 0x6U, 0, 0, 0x401F833CU | ||
| 757 | #define IOMUXC_GPIO_B0_04_ENET2_TDATA03 0x401F814CU, 0x8U, 0, 0, 0x401F833CU | ||
| 758 | |||
| 759 | #define IOMUXC_GPIO_B0_05_LCD_DATA01 0x401F8150U, 0x0U, 0, 0, 0x401F8340U | ||
| 760 | #define IOMUXC_GPIO_B0_05_QTIMER2_TIMER2 0x401F8150U, 0x1U, 0x401F8574U, 0x1U, 0x401F8340U | ||
| 761 | #define IOMUXC_GPIO_B0_05_LPI2C2_SDA 0x401F8150U, 0x2U, 0x401F84D8U, 0x1U, 0x401F8340U | ||
| 762 | #define IOMUXC_GPIO_B0_05_ARM_TRACE1 0x401F8150U, 0x3U, 0, 0, 0x401F8340U | ||
| 763 | #define IOMUXC_GPIO_B0_05_FLEXIO2_FLEXIO05 0x401F8150U, 0x4U, 0, 0, 0x401F8340U | ||
| 764 | #define IOMUXC_GPIO_B0_05_GPIO2_IO05 0x401F8150U, 0x5U, 0, 0, 0x401F8340U | ||
| 765 | #define IOMUXC_GPIO_B0_05_SRC_BOOT_CFG01 0x401F8150U, 0x6U, 0, 0, 0x401F8340U | ||
| 766 | #define IOMUXC_GPIO_B0_05_ENET2_TDATA02 0x401F8150U, 0x8U, 0, 0, 0x401F8340U | ||
| 767 | |||
| 768 | #define IOMUXC_GPIO_B0_06_LCD_DATA02 0x401F8154U, 0x0U, 0, 0, 0x401F8344U | ||
| 769 | #define IOMUXC_GPIO_B0_06_QTIMER3_TIMER0 0x401F8154U, 0x1U, 0x401F857CU, 0x2U, 0x401F8344U | ||
| 770 | #define IOMUXC_GPIO_B0_06_FLEXPWM2_PWMA00 0x401F8154U, 0x2U, 0x401F8478U, 0x1U, 0x401F8344U | ||
| 771 | #define IOMUXC_GPIO_B0_06_ARM_TRACE2 0x401F8154U, 0x3U, 0, 0, 0x401F8344U | ||
| 772 | #define IOMUXC_GPIO_B0_06_FLEXIO2_FLEXIO06 0x401F8154U, 0x4U, 0, 0, 0x401F8344U | ||
| 773 | #define IOMUXC_GPIO_B0_06_GPIO2_IO06 0x401F8154U, 0x5U, 0, 0, 0x401F8344U | ||
| 774 | #define IOMUXC_GPIO_B0_06_SRC_BOOT_CFG02 0x401F8154U, 0x6U, 0, 0, 0x401F8344U | ||
| 775 | #define IOMUXC_GPIO_B0_06_ENET2_RX_CLK 0x401F8154U, 0x8U, 0, 0, 0x401F8344U | ||
| 776 | |||
| 777 | #define IOMUXC_GPIO_B0_07_LCD_DATA03 0x401F8158U, 0x0U, 0, 0, 0x401F8348U | ||
| 778 | #define IOMUXC_GPIO_B0_07_QTIMER3_TIMER1 0x401F8158U, 0x1U, 0x401F8580U, 0x2U, 0x401F8348U | ||
| 779 | #define IOMUXC_GPIO_B0_07_FLEXPWM2_PWMB00 0x401F8158U, 0x2U, 0x401F8488U, 0x1U, 0x401F8348U | ||
| 780 | #define IOMUXC_GPIO_B0_07_ARM_TRACE3 0x401F8158U, 0x3U, 0, 0, 0x401F8348U | ||
| 781 | #define IOMUXC_GPIO_B0_07_FLEXIO2_FLEXIO07 0x401F8158U, 0x4U, 0, 0, 0x401F8348U | ||
| 782 | #define IOMUXC_GPIO_B0_07_GPIO2_IO07 0x401F8158U, 0x5U, 0, 0, 0x401F8348U | ||
| 783 | #define IOMUXC_GPIO_B0_07_SRC_BOOT_CFG03 0x401F8158U, 0x6U, 0, 0, 0x401F8348U | ||
| 784 | #define IOMUXC_GPIO_B0_07_ENET2_TX_ER 0x401F8158U, 0x8U, 0, 0, 0x401F8348U | ||
| 785 | |||
| 786 | #define IOMUXC_GPIO_B0_08_LCD_DATA04 0x401F815CU, 0x0U, 0, 0, 0x401F834CU | ||
| 787 | #define IOMUXC_GPIO_B0_08_QTIMER3_TIMER2 0x401F815CU, 0x1U, 0x401F8584U, 0x2U, 0x401F834CU | ||
| 788 | #define IOMUXC_GPIO_B0_08_FLEXPWM2_PWMA01 0x401F815CU, 0x2U, 0x401F847CU, 0x1U, 0x401F834CU | ||
| 789 | #define IOMUXC_GPIO_B0_08_LPUART3_TX 0x401F815CU, 0x3U, 0x401F853CU, 0x2U, 0x401F834CU | ||
| 790 | #define IOMUXC_GPIO_B0_08_FLEXIO2_FLEXIO08 0x401F815CU, 0x4U, 0, 0, 0x401F834CU | ||
| 791 | #define IOMUXC_GPIO_B0_08_GPIO2_IO08 0x401F815CU, 0x5U, 0, 0, 0x401F834CU | ||
| 792 | #define IOMUXC_GPIO_B0_08_SRC_BOOT_CFG04 0x401F815CU, 0x6U, 0, 0, 0x401F834CU | ||
| 793 | #define IOMUXC_GPIO_B0_08_ENET2_RDATA03 0x401F815CU, 0x8U, 0, 0, 0x401F834CU | ||
| 794 | |||
| 795 | #define IOMUXC_GPIO_B0_09_LCD_DATA05 0x401F8160U, 0x0U, 0, 0, 0x401F8350U | ||
| 796 | #define IOMUXC_GPIO_B0_09_QTIMER4_TIMER0 0x401F8160U, 0x1U, 0, 0, 0x401F8350U | ||
| 797 | #define IOMUXC_GPIO_B0_09_FLEXPWM2_PWMB01 0x401F8160U, 0x2U, 0x401F848CU, 0x1U, 0x401F8350U | ||
| 798 | #define IOMUXC_GPIO_B0_09_LPUART3_RX 0x401F8160U, 0x3U, 0x401F8538U, 0x2U, 0x401F8350U | ||
| 799 | #define IOMUXC_GPIO_B0_09_FLEXIO2_FLEXIO09 0x401F8160U, 0x4U, 0, 0, 0x401F8350U | ||
| 800 | #define IOMUXC_GPIO_B0_09_GPIO2_IO09 0x401F8160U, 0x5U, 0, 0, 0x401F8350U | ||
| 801 | #define IOMUXC_GPIO_B0_09_SRC_BOOT_CFG05 0x401F8160U, 0x6U, 0, 0, 0x401F8350U | ||
| 802 | #define IOMUXC_GPIO_B0_09_ENET2_RDATA02 0x401F8160U, 0x8U, 0, 0, 0x401F8350U | ||
| 803 | |||
| 804 | #define IOMUXC_GPIO_B0_10_LCD_DATA06 0x401F8164U, 0x0U, 0, 0, 0x401F8354U | ||
| 805 | #define IOMUXC_GPIO_B0_10_QTIMER4_TIMER1 0x401F8164U, 0x1U, 0, 0, 0x401F8354U | ||
| 806 | #define IOMUXC_GPIO_B0_10_FLEXPWM2_PWMA02 0x401F8164U, 0x2U, 0x401F8480U, 0x1U, 0x401F8354U | ||
| 807 | #define IOMUXC_GPIO_B0_10_SAI1_TX_DATA03 0x401F8164U, 0x3U, 0x401F8598U, 0x1U, 0x401F8354U | ||
| 808 | #define IOMUXC_GPIO_B0_10_FLEXIO2_FLEXIO10 0x401F8164U, 0x4U, 0, 0, 0x401F8354U | ||
| 809 | #define IOMUXC_GPIO_B0_10_GPIO2_IO10 0x401F8164U, 0x5U, 0, 0, 0x401F8354U | ||
| 810 | #define IOMUXC_GPIO_B0_10_SRC_BOOT_CFG06 0x401F8164U, 0x6U, 0, 0, 0x401F8354U | ||
| 811 | #define IOMUXC_GPIO_B0_10_ENET2_CRS 0x401F8164U, 0x8U, 0, 0, 0x401F8354U | ||
| 812 | |||
| 813 | #define IOMUXC_GPIO_B0_11_LCD_DATA07 0x401F8168U, 0x0U, 0, 0, 0x401F8358U | ||
| 814 | #define IOMUXC_GPIO_B0_11_QTIMER4_TIMER2 0x401F8168U, 0x1U, 0, 0, 0x401F8358U | ||
| 815 | #define IOMUXC_GPIO_B0_11_FLEXPWM2_PWMB02 0x401F8168U, 0x2U, 0x401F8490U, 0x1U, 0x401F8358U | ||
| 816 | #define IOMUXC_GPIO_B0_11_SAI1_TX_DATA02 0x401F8168U, 0x3U, 0x401F859CU, 0x1U, 0x401F8358U | ||
| 817 | #define IOMUXC_GPIO_B0_11_FLEXIO2_FLEXIO11 0x401F8168U, 0x4U, 0, 0, 0x401F8358U | ||
| 818 | #define IOMUXC_GPIO_B0_11_GPIO2_IO11 0x401F8168U, 0x5U, 0, 0, 0x401F8358U | ||
| 819 | #define IOMUXC_GPIO_B0_11_SRC_BOOT_CFG07 0x401F8168U, 0x6U, 0, 0, 0x401F8358U | ||
| 820 | #define IOMUXC_GPIO_B0_11_ENET2_COL 0x401F8168U, 0x8U, 0, 0, 0x401F8358U | ||
| 821 | |||
| 822 | #define IOMUXC_GPIO_B0_12_LCD_DATA08 0x401F816CU, 0x0U, 0, 0, 0x401F835CU | ||
| 823 | #define IOMUXC_GPIO_B0_12_XBAR1_INOUT10 0x401F816CU, 0x1U, 0, 0, 0x401F835CU | ||
| 824 | #define IOMUXC_GPIO_B0_12_ARM_TRACE_CLK 0x401F816CU, 0x2U, 0, 0, 0x401F835CU | ||
| 825 | #define IOMUXC_GPIO_B0_12_SAI1_TX_DATA01 0x401F816CU, 0x3U, 0x401F85A0U, 0x1U, 0x401F835CU | ||
| 826 | #define IOMUXC_GPIO_B0_12_FLEXIO2_FLEXIO12 0x401F816CU, 0x4U, 0, 0, 0x401F835CU | ||
| 827 | #define IOMUXC_GPIO_B0_12_GPIO2_IO12 0x401F816CU, 0x5U, 0, 0, 0x401F835CU | ||
| 828 | #define IOMUXC_GPIO_B0_12_SRC_BOOT_CFG08 0x401F816CU, 0x6U, 0, 0, 0x401F835CU | ||
| 829 | #define IOMUXC_GPIO_B0_12_ENET2_TDATA00 0x401F816CU, 0x8U, 0, 0, 0x401F835CU | ||
| 830 | |||
| 831 | #define IOMUXC_GPIO_B0_13_LCD_DATA09 0x401F8170U, 0x0U, 0, 0, 0x401F8360U | ||
| 832 | #define IOMUXC_GPIO_B0_13_XBAR1_INOUT11 0x401F8170U, 0x1U, 0, 0, 0x401F8360U | ||
| 833 | #define IOMUXC_GPIO_B0_13_ARM_TRACE_SWO 0x401F8170U, 0x2U, 0, 0, 0x401F8360U | ||
| 834 | #define IOMUXC_GPIO_B0_13_SAI1_MCLK 0x401F8170U, 0x3U, 0x401F858CU, 0x2U, 0x401F8360U | ||
| 835 | #define IOMUXC_GPIO_B0_13_FLEXIO2_FLEXIO13 0x401F8170U, 0x4U, 0, 0, 0x401F8360U | ||
| 836 | #define IOMUXC_GPIO_B0_13_GPIO2_IO13 0x401F8170U, 0x5U, 0, 0, 0x401F8360U | ||
| 837 | #define IOMUXC_GPIO_B0_13_SRC_BOOT_CFG09 0x401F8170U, 0x6U, 0, 0, 0x401F8360U | ||
| 838 | #define IOMUXC_GPIO_B0_13_ENET2_TDATA01 0x401F8170U, 0x8U, 0, 0, 0x401F8360U | ||
| 839 | |||
| 840 | #define IOMUXC_GPIO_B0_14_LCD_DATA10 0x401F8174U, 0x0U, 0, 0, 0x401F8364U | ||
| 841 | #define IOMUXC_GPIO_B0_14_XBAR1_INOUT12 0x401F8174U, 0x1U, 0, 0, 0x401F8364U | ||
| 842 | #define IOMUXC_GPIO_B0_14_ARM_TXEV 0x401F8174U, 0x2U, 0, 0, 0x401F8364U | ||
| 843 | #define IOMUXC_GPIO_B0_14_SAI1_RX_SYNC 0x401F8174U, 0x3U, 0x401F85A4U, 0x2U, 0x401F8364U | ||
| 844 | #define IOMUXC_GPIO_B0_14_FLEXIO2_FLEXIO14 0x401F8174U, 0x4U, 0, 0, 0x401F8364U | ||
| 845 | #define IOMUXC_GPIO_B0_14_GPIO2_IO14 0x401F8174U, 0x5U, 0, 0, 0x401F8364U | ||
| 846 | #define IOMUXC_GPIO_B0_14_SRC_BOOT_CFG10 0x401F8174U, 0x6U, 0, 0, 0x401F8364U | ||
| 847 | #define IOMUXC_GPIO_B0_14_ENET2_TX_EN 0x401F8174U, 0x8U, 0, 0, 0x401F8364U | ||
| 848 | |||
| 849 | #define IOMUXC_GPIO_B0_15_LCD_DATA11 0x401F8178U, 0x0U, 0, 0, 0x401F8368U | ||
| 850 | #define IOMUXC_GPIO_B0_15_XBAR1_INOUT13 0x401F8178U, 0x1U, 0, 0, 0x401F8368U | ||
| 851 | #define IOMUXC_GPIO_B0_15_ARM_RXEV 0x401F8178U, 0x2U, 0, 0, 0x401F8368U | ||
| 852 | #define IOMUXC_GPIO_B0_15_SAI1_RX_BCLK 0x401F8178U, 0x3U, 0x401F8590U, 0x2U, 0x401F8368U | ||
| 853 | #define IOMUXC_GPIO_B0_15_FLEXIO2_FLEXIO15 0x401F8178U, 0x4U, 0, 0, 0x401F8368U | ||
| 854 | #define IOMUXC_GPIO_B0_15_GPIO2_IO15 0x401F8178U, 0x5U, 0, 0, 0x401F8368U | ||
| 855 | #define IOMUXC_GPIO_B0_15_SRC_BOOT_CFG11 0x401F8178U, 0x6U, 0, 0, 0x401F8368U | ||
| 856 | #define IOMUXC_GPIO_B0_15_ENET2_TX_CLK 0x401F8178U, 0x8U, 0x401F8728U, 0x2U, 0x401F8368U | ||
| 857 | #define IOMUXC_GPIO_B0_15_ENET2_REF_CLK2 0x401F8178U, 0x9U, 0x401F870CU, 0x2U, 0x401F8368U | ||
| 858 | |||
| 859 | #define IOMUXC_GPIO_B1_00_LCD_DATA12 0x401F817CU, 0x0U, 0, 0, 0x401F836CU | ||
| 860 | #define IOMUXC_GPIO_B1_00_XBAR1_INOUT14 0x401F817CU, 0x1U, 0x401F8644U, 0x1U, 0x401F836CU | ||
| 861 | #define IOMUXC_GPIO_B1_00_LPUART4_TX 0x401F817CU, 0x2U, 0x401F8544U, 0x2U, 0x401F836CU | ||
| 862 | #define IOMUXC_GPIO_B1_00_SAI1_RX_DATA00 0x401F817CU, 0x3U, 0x401F8594U, 0x2U, 0x401F836CU | ||
| 863 | #define IOMUXC_GPIO_B1_00_FLEXIO2_FLEXIO16 0x401F817CU, 0x4U, 0, 0, 0x401F836CU | ||
| 864 | #define IOMUXC_GPIO_B1_00_GPIO2_IO16 0x401F817CU, 0x5U, 0, 0, 0x401F836CU | ||
| 865 | #define IOMUXC_GPIO_B1_00_FLEXPWM1_PWMA03 0x401F817CU, 0x6U, 0x401F8454U, 0x4U, 0x401F836CU | ||
| 866 | #define IOMUXC_GPIO_B1_00_ENET2_RX_ER 0x401F817CU, 0x8U, 0x401F8720U, 0x2U, 0x401F836CU | ||
| 867 | #define IOMUXC_GPIO_B1_00_FLEXIO3_FLEXIO16 0x401F817CU, 0x9U, 0, 0, 0x401F836CU | ||
| 868 | |||
| 869 | #define IOMUXC_GPIO_B1_01_LCD_DATA13 0x401F8180U, 0x0U, 0, 0, 0x401F8370U | ||
| 870 | #define IOMUXC_GPIO_B1_01_XBAR1_INOUT15 0x401F8180U, 0x1U, 0x401F8648U, 0x1U, 0x401F8370U | ||
| 871 | #define IOMUXC_GPIO_B1_01_LPUART4_RX 0x401F8180U, 0x2U, 0x401F8540U, 0x2U, 0x401F8370U | ||
| 872 | #define IOMUXC_GPIO_B1_01_SAI1_TX_DATA00 0x401F8180U, 0x3U, 0, 0, 0x401F8370U | ||
| 873 | #define IOMUXC_GPIO_B1_01_FLEXIO2_FLEXIO17 0x401F8180U, 0x4U, 0, 0, 0x401F8370U | ||
| 874 | #define IOMUXC_GPIO_B1_01_GPIO2_IO17 0x401F8180U, 0x5U, 0, 0, 0x401F8370U | ||
| 875 | #define IOMUXC_GPIO_B1_01_FLEXPWM1_PWMB03 0x401F8180U, 0x6U, 0x401F8464U, 0x4U, 0x401F8370U | ||
| 876 | #define IOMUXC_GPIO_B1_01_ENET2_RDATA00 0x401F8180U, 0x8U, 0x401F8714U, 0x2U, 0x401F8370U | ||
| 877 | #define IOMUXC_GPIO_B1_01_FLEXIO3_FLEXIO17 0x401F8180U, 0x9U, 0, 0, 0x401F8370U | ||
| 878 | |||
| 879 | #define IOMUXC_GPIO_B1_02_LCD_DATA14 0x401F8184U, 0x0U, 0, 0, 0x401F8374U | ||
| 880 | #define IOMUXC_GPIO_B1_02_XBAR1_INOUT16 0x401F8184U, 0x1U, 0x401F864CU, 0x1U, 0x401F8374U | ||
| 881 | #define IOMUXC_GPIO_B1_02_LPSPI4_PCS2 0x401F8184U, 0x2U, 0, 0, 0x401F8374U | ||
| 882 | #define IOMUXC_GPIO_B1_02_SAI1_TX_BCLK 0x401F8184U, 0x3U, 0x401F85A8U, 0x2U, 0x401F8374U | ||
| 883 | #define IOMUXC_GPIO_B1_02_FLEXIO2_FLEXIO18 0x401F8184U, 0x4U, 0, 0, 0x401F8374U | ||
| 884 | #define IOMUXC_GPIO_B1_02_GPIO2_IO18 0x401F8184U, 0x5U, 0, 0, 0x401F8374U | ||
| 885 | #define IOMUXC_GPIO_B1_02_FLEXPWM2_PWMA03 0x401F8184U, 0x6U, 0x401F8474U, 0x4U, 0x401F8374U | ||
| 886 | #define IOMUXC_GPIO_B1_02_ENET2_RDATA01 0x401F8184U, 0x8U, 0x401F8718U, 0x2U, 0x401F8374U | ||
| 887 | #define IOMUXC_GPIO_B1_02_FLEXIO3_FLEXIO18 0x401F8184U, 0x9U, 0, 0, 0x401F8374U | ||
| 888 | |||
| 889 | #define IOMUXC_GPIO_B1_03_LCD_DATA15 0x401F8188U, 0x0U, 0, 0, 0x401F8378U | ||
| 890 | #define IOMUXC_GPIO_B1_03_XBAR1_INOUT17 0x401F8188U, 0x1U, 0x401F862CU, 0x3U, 0x401F8378U | ||
| 891 | #define IOMUXC_GPIO_B1_03_LPSPI4_PCS1 0x401F8188U, 0x2U, 0, 0, 0x401F8378U | ||
| 892 | #define IOMUXC_GPIO_B1_03_SAI1_TX_SYNC 0x401F8188U, 0x3U, 0x401F85ACU, 0x2U, 0x401F8378U | ||
| 893 | #define IOMUXC_GPIO_B1_03_FLEXIO2_FLEXIO19 0x401F8188U, 0x4U, 0, 0, 0x401F8378U | ||
| 894 | #define IOMUXC_GPIO_B1_03_GPIO2_IO19 0x401F8188U, 0x5U, 0, 0, 0x401F8378U | ||
| 895 | #define IOMUXC_GPIO_B1_03_FLEXPWM2_PWMB03 0x401F8188U, 0x6U, 0x401F8484U, 0x3U, 0x401F8378U | ||
| 896 | #define IOMUXC_GPIO_B1_03_ENET2_RX_EN 0x401F8188U, 0x8U, 0x401F871CU, 0x2U, 0x401F8378U | ||
| 897 | #define IOMUXC_GPIO_B1_03_FLEXIO3_FLEXIO19 0x401F8188U, 0x9U, 0, 0, 0x401F8378U | ||
| 898 | |||
| 899 | #define IOMUXC_GPIO_B1_04_LCD_DATA16 0x401F818CU, 0x0U, 0, 0, 0x401F837CU | ||
| 900 | #define IOMUXC_GPIO_B1_04_LPSPI4_PCS0 0x401F818CU, 0x1U, 0x401F851CU, 0x1U, 0x401F837CU | ||
| 901 | #define IOMUXC_GPIO_B1_04_CSI_DATA15 0x401F818CU, 0x2U, 0, 0, 0x401F837CU | ||
| 902 | #define IOMUXC_GPIO_B1_04_ENET_RX_DATA00 0x401F818CU, 0x3U, 0x401F8434U, 0x1U, 0x401F837CU | ||
| 903 | #define IOMUXC_GPIO_B1_04_FLEXIO2_FLEXIO20 0x401F818CU, 0x4U, 0, 0, 0x401F837CU | ||
| 904 | #define IOMUXC_GPIO_B1_04_GPIO2_IO20 0x401F818CU, 0x5U, 0, 0, 0x401F837CU | ||
| 905 | #define IOMUXC_GPIO_B1_04_GPT1_CLK 0x401F818CU, 0x8U, 0x401F8760U, 0x1U, 0x401F837CU | ||
| 906 | #define IOMUXC_GPIO_B1_04_FLEXIO3_FLEXIO20 0x401F818CU, 0x9U, 0, 0, 0x401F837CU | ||
| 907 | |||
| 908 | #define IOMUXC_GPIO_B1_05_LCD_DATA17 0x401F8190U, 0x0U, 0, 0, 0x401F8380U | ||
| 909 | #define IOMUXC_GPIO_B1_05_LPSPI4_SDI 0x401F8190U, 0x1U, 0x401F8524U, 0x1U, 0x401F8380U | ||
| 910 | #define IOMUXC_GPIO_B1_05_CSI_DATA14 0x401F8190U, 0x2U, 0, 0, 0x401F8380U | ||
| 911 | #define IOMUXC_GPIO_B1_05_ENET_RX_DATA01 0x401F8190U, 0x3U, 0x401F8438U, 0x1U, 0x401F8380U | ||
| 912 | #define IOMUXC_GPIO_B1_05_FLEXIO2_FLEXIO21 0x401F8190U, 0x4U, 0, 0, 0x401F8380U | ||
| 913 | #define IOMUXC_GPIO_B1_05_GPIO2_IO21 0x401F8190U, 0x5U, 0, 0, 0x401F8380U | ||
| 914 | #define IOMUXC_GPIO_B1_05_GPT1_CAPTURE1 0x401F8190U, 0x8U, 0x401F8758U, 0x1U, 0x401F8380U | ||
| 915 | #define IOMUXC_GPIO_B1_05_FLEXIO3_FLEXIO21 0x401F8190U, 0x9U, 0, 0, 0x401F8380U | ||
| 916 | |||
| 917 | #define IOMUXC_GPIO_B1_06_LCD_DATA18 0x401F8194U, 0x0U, 0, 0, 0x401F8384U | ||
| 918 | #define IOMUXC_GPIO_B1_06_LPSPI4_SDO 0x401F8194U, 0x1U, 0x401F8528U, 0x1U, 0x401F8384U | ||
| 919 | #define IOMUXC_GPIO_B1_06_CSI_DATA13 0x401F8194U, 0x2U, 0, 0, 0x401F8384U | ||
| 920 | #define IOMUXC_GPIO_B1_06_ENET_RX_EN 0x401F8194U, 0x3U, 0x401F843CU, 0x1U, 0x401F8384U | ||
| 921 | #define IOMUXC_GPIO_B1_06_FLEXIO2_FLEXIO22 0x401F8194U, 0x4U, 0, 0, 0x401F8384U | ||
| 922 | #define IOMUXC_GPIO_B1_06_GPIO2_IO22 0x401F8194U, 0x5U, 0, 0, 0x401F8384U | ||
| 923 | #define IOMUXC_GPIO_B1_06_GPT1_CAPTURE2 0x401F8194U, 0x8U, 0x401F875CU, 0x1U, 0x401F8384U | ||
| 924 | #define IOMUXC_GPIO_B1_06_FLEXIO3_FLEXIO22 0x401F8194U, 0x9U, 0, 0, 0x401F8384U | ||
| 925 | |||
| 926 | #define IOMUXC_GPIO_B1_07_LCD_DATA19 0x401F8198U, 0x0U, 0, 0, 0x401F8388U | ||
| 927 | #define IOMUXC_GPIO_B1_07_LPSPI4_SCK 0x401F8198U, 0x1U, 0x401F8520U, 0x1U, 0x401F8388U | ||
| 928 | #define IOMUXC_GPIO_B1_07_CSI_DATA12 0x401F8198U, 0x2U, 0, 0, 0x401F8388U | ||
| 929 | #define IOMUXC_GPIO_B1_07_ENET_TX_DATA00 0x401F8198U, 0x3U, 0, 0, 0x401F8388U | ||
| 930 | #define IOMUXC_GPIO_B1_07_FLEXIO2_FLEXIO23 0x401F8198U, 0x4U, 0, 0, 0x401F8388U | ||
| 931 | #define IOMUXC_GPIO_B1_07_GPIO2_IO23 0x401F8198U, 0x5U, 0, 0, 0x401F8388U | ||
| 932 | #define IOMUXC_GPIO_B1_07_GPT1_COMPARE1 0x401F8198U, 0x8U, 0, 0, 0x401F8388U | ||
| 933 | #define IOMUXC_GPIO_B1_07_FLEXIO3_FLEXIO23 0x401F8198U, 0x9U, 0, 0, 0x401F8388U | ||
| 934 | |||
| 935 | #define IOMUXC_GPIO_B1_08_LCD_DATA20 0x401F819CU, 0x0U, 0, 0, 0x401F838CU | ||
| 936 | #define IOMUXC_GPIO_B1_08_QTIMER1_TIMER3 0x401F819CU, 0x1U, 0, 0, 0x401F838CU | ||
| 937 | #define IOMUXC_GPIO_B1_08_CSI_DATA11 0x401F819CU, 0x2U, 0, 0, 0x401F838CU | ||
| 938 | #define IOMUXC_GPIO_B1_08_ENET_TX_DATA01 0x401F819CU, 0x3U, 0, 0, 0x401F838CU | ||
| 939 | #define IOMUXC_GPIO_B1_08_FLEXIO2_FLEXIO24 0x401F819CU, 0x4U, 0, 0, 0x401F838CU | ||
| 940 | #define IOMUXC_GPIO_B1_08_GPIO2_IO24 0x401F819CU, 0x5U, 0, 0, 0x401F838CU | ||
| 941 | #define IOMUXC_GPIO_B1_08_FLEXCAN2_TX 0x401F819CU, 0x6U, 0, 0, 0x401F838CU | ||
| 942 | #define IOMUXC_GPIO_B1_08_GPT1_COMPARE2 0x401F819CU, 0x8U, 0, 0, 0x401F838CU | ||
| 943 | #define IOMUXC_GPIO_B1_08_FLEXIO3_FLEXIO24 0x401F819CU, 0x9U, 0, 0, 0x401F838CU | ||
| 944 | |||
| 945 | #define IOMUXC_GPIO_B1_09_LCD_DATA21 0x401F81A0U, 0x0U, 0, 0, 0x401F8390U | ||
| 946 | #define IOMUXC_GPIO_B1_09_QTIMER2_TIMER3 0x401F81A0U, 0x1U, 0x401F8578U, 0x1U, 0x401F8390U | ||
| 947 | #define IOMUXC_GPIO_B1_09_CSI_DATA10 0x401F81A0U, 0x2U, 0, 0, 0x401F8390U | ||
| 948 | #define IOMUXC_GPIO_B1_09_ENET_TX_EN 0x401F81A0U, 0x3U, 0, 0, 0x401F8390U | ||
| 949 | #define IOMUXC_GPIO_B1_09_FLEXIO2_FLEXIO25 0x401F81A0U, 0x4U, 0, 0, 0x401F8390U | ||
| 950 | #define IOMUXC_GPIO_B1_09_GPIO2_IO25 0x401F81A0U, 0x5U, 0, 0, 0x401F8390U | ||
| 951 | #define IOMUXC_GPIO_B1_09_FLEXCAN2_RX 0x401F81A0U, 0x6U, 0x401F8450U, 0x3U, 0x401F8390U | ||
| 952 | #define IOMUXC_GPIO_B1_09_GPT1_COMPARE3 0x401F81A0U, 0x8U, 0, 0, 0x401F8390U | ||
| 953 | #define IOMUXC_GPIO_B1_09_FLEXIO3_FLEXIO25 0x401F81A0U, 0x9U, 0, 0, 0x401F8390U | ||
| 954 | |||
| 955 | #define IOMUXC_GPIO_B1_10_LCD_DATA22 0x401F81A4U, 0x0U, 0, 0, 0x401F8394U | ||
| 956 | #define IOMUXC_GPIO_B1_10_QTIMER3_TIMER3 0x401F81A4U, 0x1U, 0x401F8588U, 0x2U, 0x401F8394U | ||
| 957 | #define IOMUXC_GPIO_B1_10_CSI_DATA00 0x401F81A4U, 0x2U, 0, 0, 0x401F8394U | ||
| 958 | #define IOMUXC_GPIO_B1_10_ENET_TX_CLK 0x401F81A4U, 0x3U, 0x401F8448U, 0x1U, 0x401F8394U | ||
| 959 | #define IOMUXC_GPIO_B1_10_FLEXIO2_FLEXIO26 0x401F81A4U, 0x4U, 0, 0, 0x401F8394U | ||
| 960 | #define IOMUXC_GPIO_B1_10_GPIO2_IO26 0x401F81A4U, 0x5U, 0, 0, 0x401F8394U | ||
| 961 | #define IOMUXC_GPIO_B1_10_ENET_REF_CLK 0x401F81A4U, 0x6U, 0x401F842CU, 0x1U, 0x401F8394U | ||
| 962 | #define IOMUXC_GPIO_B1_10_FLEXIO3_FLEXIO26 0x401F81A4U, 0x9U, 0, 0, 0x401F8394U | ||
| 963 | |||
| 964 | #define IOMUXC_GPIO_B1_11_LCD_DATA23 0x401F81A8U, 0x0U, 0, 0, 0x401F8398U | ||
| 965 | #define IOMUXC_GPIO_B1_11_QTIMER4_TIMER3 0x401F81A8U, 0x1U, 0, 0, 0x401F8398U | ||
| 966 | #define IOMUXC_GPIO_B1_11_CSI_DATA01 0x401F81A8U, 0x2U, 0, 0, 0x401F8398U | ||
| 967 | #define IOMUXC_GPIO_B1_11_ENET_RX_ER 0x401F81A8U, 0x3U, 0x401F8440U, 0x1U, 0x401F8398U | ||
| 968 | #define IOMUXC_GPIO_B1_11_FLEXIO2_FLEXIO27 0x401F81A8U, 0x4U, 0, 0, 0x401F8398U | ||
| 969 | #define IOMUXC_GPIO_B1_11_GPIO2_IO27 0x401F81A8U, 0x5U, 0, 0, 0x401F8398U | ||
| 970 | #define IOMUXC_GPIO_B1_11_LPSPI4_PCS3 0x401F81A8U, 0x6U, 0, 0, 0x401F8398U | ||
| 971 | #define IOMUXC_GPIO_B1_11_FLEXIO3_FLEXIO27 0x401F81A8U, 0x9U, 0, 0, 0x401F8398U | ||
| 972 | |||
| 973 | #define IOMUXC_GPIO_B1_12_LPUART5_TX 0x401F81ACU, 0x1U, 0x401F854CU, 0x1U, 0x401F839CU | ||
| 974 | #define IOMUXC_GPIO_B1_12_CSI_PIXCLK 0x401F81ACU, 0x2U, 0x401F8424U, 0x1U, 0x401F839CU | ||
| 975 | #define IOMUXC_GPIO_B1_12_ENET_1588_EVENT0_IN 0x401F81ACU, 0x3U, 0x401F8444U, 0x2U, 0x401F839CU | ||
| 976 | #define IOMUXC_GPIO_B1_12_FLEXIO2_FLEXIO28 0x401F81ACU, 0x4U, 0, 0, 0x401F839CU | ||
| 977 | #define IOMUXC_GPIO_B1_12_GPIO2_IO28 0x401F81ACU, 0x5U, 0, 0, 0x401F839CU | ||
| 978 | #define IOMUXC_GPIO_B1_12_USDHC1_CD_B 0x401F81ACU, 0x6U, 0x401F85D4U, 0x2U, 0x401F839CU | ||
| 979 | #define IOMUXC_GPIO_B1_12_FLEXIO3_FLEXIO28 0x401F81ACU, 0x9U, 0, 0, 0x401F839CU | ||
| 980 | |||
| 981 | #define IOMUXC_GPIO_B1_13_WDOG1_B 0x401F81B0U, 0x0U, 0, 0, 0x401F83A0U | ||
| 982 | #define IOMUXC_GPIO_B1_13_LPUART5_RX 0x401F81B0U, 0x1U, 0x401F8548U, 0x1U, 0x401F83A0U | ||
| 983 | #define IOMUXC_GPIO_B1_13_CSI_VSYNC 0x401F81B0U, 0x2U, 0x401F8428U, 0x2U, 0x401F83A0U | ||
| 984 | #define IOMUXC_GPIO_B1_13_ENET_1588_EVENT0_OUT 0x401F81B0U, 0x3U, 0, 0, 0x401F83A0U | ||
| 985 | #define IOMUXC_GPIO_B1_13_FLEXIO2_FLEXIO29 0x401F81B0U, 0x4U, 0, 0, 0x401F83A0U | ||
| 986 | #define IOMUXC_GPIO_B1_13_GPIO2_IO29 0x401F81B0U, 0x5U, 0, 0, 0x401F83A0U | ||
| 987 | #define IOMUXC_GPIO_B1_13_USDHC1_WP 0x401F81B0U, 0x6U, 0x401F85D8U, 0x3U, 0x401F83A0U | ||
| 988 | #define IOMUXC_GPIO_B1_13_SEMC_DQS4 0x401F81B0U, 0x8U, 0x401F8788U, 0x3U, 0x401F83A0U | ||
| 989 | #define IOMUXC_GPIO_B1_13_FLEXIO3_FLEXIO29 0x401F81B0U, 0x9U, 0, 0, 0x401F83A0U | ||
| 990 | |||
| 991 | #define IOMUXC_GPIO_B1_14_ENET_MDC 0x401F81B4U, 0x0U, 0, 0, 0x401F83A4U | ||
| 992 | #define IOMUXC_GPIO_B1_14_FLEXPWM4_PWMA02 0x401F81B4U, 0x1U, 0x401F849CU, 0x1U, 0x401F83A4U | ||
| 993 | #define IOMUXC_GPIO_B1_14_CSI_HSYNC 0x401F81B4U, 0x2U, 0x401F8420U, 0x2U, 0x401F83A4U | ||
| 994 | #define IOMUXC_GPIO_B1_14_XBAR1_IN02 0x401F81B4U, 0x3U, 0x401F860CU, 0x1U, 0x401F83A4U | ||
| 995 | #define IOMUXC_GPIO_B1_14_FLEXIO2_FLEXIO30 0x401F81B4U, 0x4U, 0, 0, 0x401F83A4U | ||
| 996 | #define IOMUXC_GPIO_B1_14_GPIO2_IO30 0x401F81B4U, 0x5U, 0, 0, 0x401F83A4U | ||
| 997 | #define IOMUXC_GPIO_B1_14_USDHC1_VSELECT 0x401F81B4U, 0x6U, 0, 0, 0x401F83A4U | ||
| 998 | #define IOMUXC_GPIO_B1_14_ENET2_TDATA00 0x401F81B4U, 0x8U, 0, 0, 0x401F83A4U | ||
| 999 | #define IOMUXC_GPIO_B1_14_FLEXIO3_FLEXIO30 0x401F81B4U, 0x9U, 0, 0, 0x401F83A4U | ||
| 1000 | |||
| 1001 | #define IOMUXC_GPIO_B1_15_ENET_MDIO 0x401F81B8U, 0x0U, 0x401F8430U, 0x2U, 0x401F83A8U | ||
| 1002 | #define IOMUXC_GPIO_B1_15_FLEXPWM4_PWMA03 0x401F81B8U, 0x1U, 0x401F84A0U, 0x1U, 0x401F83A8U | ||
| 1003 | #define IOMUXC_GPIO_B1_15_CSI_MCLK 0x401F81B8U, 0x2U, 0, 0, 0x401F83A8U | ||
| 1004 | #define IOMUXC_GPIO_B1_15_XBAR1_IN03 0x401F81B8U, 0x3U, 0x401F8610U, 0x1U, 0x401F83A8U | ||
| 1005 | #define IOMUXC_GPIO_B1_15_FLEXIO2_FLEXIO31 0x401F81B8U, 0x4U, 0, 0, 0x401F83A8U | ||
| 1006 | #define IOMUXC_GPIO_B1_15_GPIO2_IO31 0x401F81B8U, 0x5U, 0, 0, 0x401F83A8U | ||
| 1007 | #define IOMUXC_GPIO_B1_15_USDHC1_RESET_B 0x401F81B8U, 0x6U, 0, 0, 0x401F83A8U | ||
| 1008 | #define IOMUXC_GPIO_B1_15_ENET2_TDATA01 0x401F81B8U, 0x8U, 0, 0, 0x401F83A8U | ||
| 1009 | #define IOMUXC_GPIO_B1_15_FLEXIO3_FLEXIO31 0x401F81B8U, 0x9U, 0, 0, 0x401F83A8U | ||
| 1010 | |||
| 1011 | #define IOMUXC_GPIO_SD_B0_00_USDHC1_CMD 0x401F81BCU, 0x0U, 0, 0, 0x401F83ACU | ||
| 1012 | #define IOMUXC_GPIO_SD_B0_00_FLEXPWM1_PWMA00 0x401F81BCU, 0x1U, 0x401F8458U, 0x1U, 0x401F83ACU | ||
| 1013 | #define IOMUXC_GPIO_SD_B0_00_LPI2C3_SCL 0x401F81BCU, 0x2U, 0x401F84DCU, 0x1U, 0x401F83ACU | ||
| 1014 | #define IOMUXC_GPIO_SD_B0_00_XBAR1_INOUT04 0x401F81BCU, 0x3U, 0x401F8614U, 0x1U, 0x401F83ACU | ||
| 1015 | #define IOMUXC_GPIO_SD_B0_00_LPSPI1_SCK 0x401F81BCU, 0x4U, 0x401F84F0U, 0x1U, 0x401F83ACU | ||
| 1016 | #define IOMUXC_GPIO_SD_B0_00_GPIO3_IO12 0x401F81BCU, 0x5U, 0, 0, 0x401F83ACU | ||
| 1017 | #define IOMUXC_GPIO_SD_B0_00_FLEXSPIA_SS1_B 0x401F81BCU, 0x6U, 0, 0, 0x401F83ACU | ||
| 1018 | #define IOMUXC_GPIO_SD_B0_00_ENET2_TX_EN 0x401F81BCU, 0x8U, 0, 0, 0x401F83ACU | ||
| 1019 | #define IOMUXC_GPIO_SD_B0_00_SEMC_DQS4 0x401F81BCU, 0x9U, 0x401F8788U, 0x0U, 0x401F83ACU | ||
| 1020 | |||
| 1021 | #define IOMUXC_GPIO_SD_B0_01_USDHC1_CLK 0x401F81C0U, 0x0U, 0, 0, 0x401F83B0U | ||
| 1022 | #define IOMUXC_GPIO_SD_B0_01_FLEXPWM1_PWMB00 0x401F81C0U, 0x1U, 0x401F8468U, 0x1U, 0x401F83B0U | ||
| 1023 | #define IOMUXC_GPIO_SD_B0_01_LPI2C3_SDA 0x401F81C0U, 0x2U, 0x401F84E0U, 0x1U, 0x401F83B0U | ||
| 1024 | #define IOMUXC_GPIO_SD_B0_01_XBAR1_INOUT05 0x401F81C0U, 0x3U, 0x401F8618U, 0x1U, 0x401F83B0U | ||
| 1025 | #define IOMUXC_GPIO_SD_B0_01_LPSPI1_PCS0 0x401F81C0U, 0x4U, 0x401F84ECU, 0x0U, 0x401F83B0U | ||
| 1026 | #define IOMUXC_GPIO_SD_B0_01_GPIO3_IO13 0x401F81C0U, 0x5U, 0, 0, 0x401F83B0U | ||
| 1027 | #define IOMUXC_GPIO_SD_B0_01_FLEXSPIB_SS1_B 0x401F81C0U, 0x6U, 0, 0, 0x401F83B0U | ||
| 1028 | #define IOMUXC_GPIO_SD_B0_01_ENET2_TX_CLK 0x401F81C0U, 0x8U, 0x401F8728U, 0x1U, 0x401F83B0U | ||
| 1029 | #define IOMUXC_GPIO_SD_B0_01_ENET2_REF_CLK2 0x401F81C0U, 0x9U, 0x401F870CU, 0x1U, 0x401F83B0U | ||
| 1030 | |||
| 1031 | #define IOMUXC_GPIO_SD_B0_02_USDHC1_DATA0 0x401F81C4U, 0x0U, 0, 0, 0x401F83B4U | ||
| 1032 | #define IOMUXC_GPIO_SD_B0_02_FLEXPWM1_PWMA01 0x401F81C4U, 0x1U, 0x401F845CU, 0x1U, 0x401F83B4U | ||
| 1033 | #define IOMUXC_GPIO_SD_B0_02_LPUART8_CTS_B 0x401F81C4U, 0x2U, 0, 0, 0x401F83B4U | ||
| 1034 | #define IOMUXC_GPIO_SD_B0_02_XBAR1_INOUT06 0x401F81C4U, 0x3U, 0x401F861CU, 0x1U, 0x401F83B4U | ||
| 1035 | #define IOMUXC_GPIO_SD_B0_02_LPSPI1_SDO 0x401F81C4U, 0x4U, 0x401F84F8U, 0x1U, 0x401F83B4U | ||
| 1036 | #define IOMUXC_GPIO_SD_B0_02_GPIO3_IO14 0x401F81C4U, 0x5U, 0, 0, 0x401F83B4U | ||
| 1037 | #define IOMUXC_GPIO_SD_B0_02_ENET2_RX_ER 0x401F81C4U, 0x8U, 0x401F8720U, 0x1U, 0x401F83B4U | ||
| 1038 | #define IOMUXC_GPIO_SD_B0_02_SEMC_CLK5 0x401F81C4U, 0x9U, 0, 0, 0x401F83B4U | ||
| 1039 | |||
| 1040 | #define IOMUXC_GPIO_SD_B0_03_USDHC1_DATA1 0x401F81C8U, 0x0U, 0, 0, 0x401F83B8U | ||
| 1041 | #define IOMUXC_GPIO_SD_B0_03_FLEXPWM1_PWMB01 0x401F81C8U, 0x1U, 0x401F846CU, 0x1U, 0x401F83B8U | ||
| 1042 | #define IOMUXC_GPIO_SD_B0_03_LPUART8_RTS_B 0x401F81C8U, 0x2U, 0, 0, 0x401F83B8U | ||
| 1043 | #define IOMUXC_GPIO_SD_B0_03_XBAR1_INOUT07 0x401F81C8U, 0x3U, 0x401F8620U, 0x1U, 0x401F83B8U | ||
| 1044 | #define IOMUXC_GPIO_SD_B0_03_LPSPI1_SDI 0x401F81C8U, 0x4U, 0x401F84F4U, 0x1U, 0x401F83B8U | ||
| 1045 | #define IOMUXC_GPIO_SD_B0_03_GPIO3_IO15 0x401F81C8U, 0x5U, 0, 0, 0x401F83B8U | ||
| 1046 | #define IOMUXC_GPIO_SD_B0_03_ENET2_RDATA00 0x401F81C8U, 0x8U, 0x401F8714U, 0x1U, 0x401F83B8U | ||
| 1047 | #define IOMUXC_GPIO_SD_B0_03_SEMC_CLK6 0x401F81C8U, 0x9U, 0, 0, 0x401F83B8U | ||
| 1048 | |||
| 1049 | #define IOMUXC_GPIO_SD_B0_04_USDHC1_DATA2 0x401F81CCU, 0x0U, 0, 0, 0x401F83BCU | ||
| 1050 | #define IOMUXC_GPIO_SD_B0_04_FLEXPWM1_PWMA02 0x401F81CCU, 0x1U, 0x401F8460U, 0x1U, 0x401F83BCU | ||
| 1051 | #define IOMUXC_GPIO_SD_B0_04_LPUART8_TX 0x401F81CCU, 0x2U, 0x401F8564U, 0x0U, 0x401F83BCU | ||
| 1052 | #define IOMUXC_GPIO_SD_B0_04_XBAR1_INOUT08 0x401F81CCU, 0x3U, 0x401F8624U, 0x1U, 0x401F83BCU | ||
| 1053 | #define IOMUXC_GPIO_SD_B0_04_FLEXSPIB_SS0_B 0x401F81CCU, 0x4U, 0, 0, 0x401F83BCU | ||
| 1054 | #define IOMUXC_GPIO_SD_B0_04_GPIO3_IO16 0x401F81CCU, 0x5U, 0, 0, 0x401F83BCU | ||
| 1055 | #define IOMUXC_GPIO_SD_B0_04_CCM_CLKO1 0x401F81CCU, 0x6U, 0, 0, 0x401F83BCU | ||
| 1056 | #define IOMUXC_GPIO_SD_B0_04_ENET2_RDATA01 0x401F81CCU, 0x8U, 0x401F8718U, 0x1U, 0x401F83BCU | ||
| 1057 | |||
| 1058 | #define IOMUXC_GPIO_SD_B0_05_USDHC1_DATA3 0x401F81D0U, 0x0U, 0, 0, 0x401F83C0U | ||
| 1059 | #define IOMUXC_GPIO_SD_B0_05_FLEXPWM1_PWMB02 0x401F81D0U, 0x1U, 0x401F8470U, 0x1U, 0x401F83C0U | ||
| 1060 | #define IOMUXC_GPIO_SD_B0_05_LPUART8_RX 0x401F81D0U, 0x2U, 0x401F8560U, 0x0U, 0x401F83C0U | ||
| 1061 | #define IOMUXC_GPIO_SD_B0_05_XBAR1_INOUT09 0x401F81D0U, 0x3U, 0x401F8628U, 0x1U, 0x401F83C0U | ||
| 1062 | #define IOMUXC_GPIO_SD_B0_05_FLEXSPIB_DQS 0x401F81D0U, 0x4U, 0, 0, 0x401F83C0U | ||
| 1063 | #define IOMUXC_GPIO_SD_B0_05_GPIO3_IO17 0x401F81D0U, 0x5U, 0, 0, 0x401F83C0U | ||
| 1064 | #define IOMUXC_GPIO_SD_B0_05_CCM_CLKO2 0x401F81D0U, 0x6U, 0, 0, 0x401F83C0U | ||
| 1065 | #define IOMUXC_GPIO_SD_B0_05_ENET2_RX_EN 0x401F81D0U, 0x8U, 0x401F871CU, 0x1U, 0x401F83C0U | ||
| 1066 | |||
| 1067 | #define IOMUXC_GPIO_SD_B1_00_USDHC2_DATA3 0x401F81D4U, 0x0U, 0x401F85F4U, 0x0U, 0x401F83C4U | ||
| 1068 | #define IOMUXC_GPIO_SD_B1_00_FLEXSPIB_DATA03 0x401F81D4U, 0x1U, 0x401F84C4U, 0x0U, 0x401F83C4U | ||
| 1069 | #define IOMUXC_GPIO_SD_B1_00_FLEXPWM1_PWMA03 0x401F81D4U, 0x2U, 0x401F8454U, 0x0U, 0x401F83C4U | ||
| 1070 | #define IOMUXC_GPIO_SD_B1_00_SAI1_TX_DATA03 0x401F81D4U, 0x3U, 0x401F8598U, 0x0U, 0x401F83C4U | ||
| 1071 | #define IOMUXC_GPIO_SD_B1_00_LPUART4_TX 0x401F81D4U, 0x4U, 0x401F8544U, 0x0U, 0x401F83C4U | ||
| 1072 | #define IOMUXC_GPIO_SD_B1_00_GPIO3_IO00 0x401F81D4U, 0x5U, 0, 0, 0x401F83C4U | ||
| 1073 | #define IOMUXC_GPIO_SD_B1_00_SAI3_RX_DATA 0x401F81D4U, 0x8U, 0x401F8778U, 0x1U, 0x401F83C4U | ||
| 1074 | |||
| 1075 | #define IOMUXC_GPIO_SD_B1_01_USDHC2_DATA2 0x401F81D8U, 0x0U, 0x401F85F0U, 0x0U, 0x401F83C8U | ||
| 1076 | #define IOMUXC_GPIO_SD_B1_01_FLEXSPIB_DATA02 0x401F81D8U, 0x1U, 0x401F84C0U, 0x0U, 0x401F83C8U | ||
| 1077 | #define IOMUXC_GPIO_SD_B1_01_FLEXPWM1_PWMB03 0x401F81D8U, 0x2U, 0x401F8464U, 0x0U, 0x401F83C8U | ||
| 1078 | #define IOMUXC_GPIO_SD_B1_01_SAI1_TX_DATA02 0x401F81D8U, 0x3U, 0x401F859CU, 0x0U, 0x401F83C8U | ||
| 1079 | #define IOMUXC_GPIO_SD_B1_01_LPUART4_RX 0x401F81D8U, 0x4U, 0x401F8540U, 0x0U, 0x401F83C8U | ||
| 1080 | #define IOMUXC_GPIO_SD_B1_01_GPIO3_IO01 0x401F81D8U, 0x5U, 0, 0, 0x401F83C8U | ||
| 1081 | #define IOMUXC_GPIO_SD_B1_01_SAI3_TX_DATA 0x401F81D8U, 0x8U, 0, 0, 0x401F83C8U | ||
| 1082 | |||
| 1083 | #define IOMUXC_GPIO_SD_B1_02_USDHC2_DATA1 0x401F81DCU, 0x0U, 0x401F85ECU, 0x0U, 0x401F83CCU | ||
| 1084 | #define IOMUXC_GPIO_SD_B1_02_FLEXSPIB_DATA01 0x401F81DCU, 0x1U, 0x401F84BCU, 0x0U, 0x401F83CCU | ||
| 1085 | #define IOMUXC_GPIO_SD_B1_02_FLEXPWM2_PWMA03 0x401F81DCU, 0x2U, 0x401F8474U, 0x0U, 0x401F83CCU | ||
| 1086 | #define IOMUXC_GPIO_SD_B1_02_SAI1_TX_DATA01 0x401F81DCU, 0x3U, 0x401F85A0U, 0x0U, 0x401F83CCU | ||
| 1087 | #define IOMUXC_GPIO_SD_B1_02_FLEXCAN1_TX 0x401F81DCU, 0x4U, 0, 0, 0x401F83CCU | ||
| 1088 | #define IOMUXC_GPIO_SD_B1_02_GPIO3_IO02 0x401F81DCU, 0x5U, 0, 0, 0x401F83CCU | ||
| 1089 | #define IOMUXC_GPIO_SD_B1_02_CCM_WAIT 0x401F81DCU, 0x6U, 0, 0, 0x401F83CCU | ||
| 1090 | #define IOMUXC_GPIO_SD_B1_02_SAI3_TX_SYNC 0x401F81DCU, 0x8U, 0x401F8784U, 0x1U, 0x401F83CCU | ||
| 1091 | |||
| 1092 | #define IOMUXC_GPIO_SD_B1_03_USDHC2_DATA0 0x401F81E0U, 0x0U, 0x401F85E8U, 0x0U, 0x401F83D0U | ||
| 1093 | #define IOMUXC_GPIO_SD_B1_03_FLEXSPIB_DATA00 0x401F81E0U, 0x1U, 0x401F84B8U, 0x0U, 0x401F83D0U | ||
| 1094 | #define IOMUXC_GPIO_SD_B1_03_FLEXPWM2_PWMB03 0x401F81E0U, 0x2U, 0x401F8484U, 0x0U, 0x401F83D0U | ||
| 1095 | #define IOMUXC_GPIO_SD_B1_03_SAI1_MCLK 0x401F81E0U, 0x3U, 0x401F858CU, 0x0U, 0x401F83D0U | ||
| 1096 | #define IOMUXC_GPIO_SD_B1_03_FLEXCAN1_RX 0x401F81E0U, 0x4U, 0x401F844CU, 0x0U, 0x401F83D0U | ||
| 1097 | #define IOMUXC_GPIO_SD_B1_03_GPIO3_IO03 0x401F81E0U, 0x5U, 0, 0, 0x401F83D0U | ||
| 1098 | #define IOMUXC_GPIO_SD_B1_03_CCM_PMIC_READY 0x401F81E0U, 0x6U, 0x401F83FCU, 0x0U, 0x401F83D0U | ||
| 1099 | #define IOMUXC_GPIO_SD_B1_03_SAI3_TX_BCLK 0x401F81E0U, 0x8U, 0x401F8780U, 0x1U, 0x401F83D0U | ||
| 1100 | |||
| 1101 | #define IOMUXC_GPIO_SD_B1_04_USDHC2_CLK 0x401F81E4U, 0x0U, 0x401F85DCU, 0x0U, 0x401F83D4U | ||
| 1102 | #define IOMUXC_GPIO_SD_B1_04_FLEXSPIB_SCLK 0x401F81E4U, 0x1U, 0, 0, 0x401F83D4U | ||
| 1103 | #define IOMUXC_GPIO_SD_B1_04_LPI2C1_SCL 0x401F81E4U, 0x2U, 0x401F84CCU, 0x0U, 0x401F83D4U | ||
| 1104 | #define IOMUXC_GPIO_SD_B1_04_SAI1_RX_SYNC 0x401F81E4U, 0x3U, 0x401F85A4U, 0x0U, 0x401F83D4U | ||
| 1105 | #define IOMUXC_GPIO_SD_B1_04_FLEXSPIA_SS1_B 0x401F81E4U, 0x4U, 0, 0, 0x401F83D4U | ||
| 1106 | #define IOMUXC_GPIO_SD_B1_04_GPIO3_IO04 0x401F81E4U, 0x5U, 0, 0, 0x401F83D4U | ||
| 1107 | #define IOMUXC_GPIO_SD_B1_04_CCM_STOP 0x401F81E4U, 0x6U, 0, 0, 0x401F83D4U | ||
| 1108 | #define IOMUXC_GPIO_SD_B1_04_SAI3_MCLK 0x401F81E4U, 0x8U, 0x401F8770U, 0x1U, 0x401F83D4U | ||
| 1109 | |||
| 1110 | #define IOMUXC_GPIO_SD_B1_05_USDHC2_CMD 0x401F81E8U, 0x0U, 0x401F85E4U, 0x0U, 0x401F83D8U | ||
| 1111 | #define IOMUXC_GPIO_SD_B1_05_FLEXSPIA_DQS 0x401F81E8U, 0x1U, 0x401F84A4U, 0x0U, 0x401F83D8U | ||
| 1112 | #define IOMUXC_GPIO_SD_B1_05_LPI2C1_SDA 0x401F81E8U, 0x2U, 0x401F84D0U, 0x0U, 0x401F83D8U | ||
| 1113 | #define IOMUXC_GPIO_SD_B1_05_SAI1_RX_BCLK 0x401F81E8U, 0x3U, 0x401F8590U, 0x0U, 0x401F83D8U | ||
| 1114 | #define IOMUXC_GPIO_SD_B1_05_FLEXSPIB_SS0_B 0x401F81E8U, 0x4U, 0, 0, 0x401F83D8U | ||
| 1115 | #define IOMUXC_GPIO_SD_B1_05_GPIO3_IO05 0x401F81E8U, 0x5U, 0, 0, 0x401F83D8U | ||
| 1116 | #define IOMUXC_GPIO_SD_B1_05_SAI3_RX_SYNC 0x401F81E8U, 0x8U, 0x401F877CU, 0x1U, 0x401F83D8U | ||
| 1117 | |||
| 1118 | #define IOMUXC_GPIO_SD_B1_06_USDHC2_RESET_B 0x401F81ECU, 0x0U, 0, 0, 0x401F83DCU | ||
| 1119 | #define IOMUXC_GPIO_SD_B1_06_FLEXSPIA_SS0_B 0x401F81ECU, 0x1U, 0, 0, 0x401F83DCU | ||
| 1120 | #define IOMUXC_GPIO_SD_B1_06_LPUART7_CTS_B 0x401F81ECU, 0x2U, 0, 0, 0x401F83DCU | ||
| 1121 | #define IOMUXC_GPIO_SD_B1_06_SAI1_RX_DATA00 0x401F81ECU, 0x3U, 0x401F8594U, 0x0U, 0x401F83DCU | ||
| 1122 | #define IOMUXC_GPIO_SD_B1_06_LPSPI2_PCS0 0x401F81ECU, 0x4U, 0x401F84FCU, 0x0U, 0x401F83DCU | ||
| 1123 | #define IOMUXC_GPIO_SD_B1_06_GPIO3_IO06 0x401F81ECU, 0x5U, 0, 0, 0x401F83DCU | ||
| 1124 | #define IOMUXC_GPIO_SD_B1_06_SAI3_RX_BCLK 0x401F81ECU, 0x8U, 0x401F8774U, 0x1U, 0x401F83DCU | ||
| 1125 | |||
| 1126 | #define IOMUXC_GPIO_SD_B1_07_SEMC_CSX01 0x401F81F0U, 0x0U, 0, 0, 0x401F83E0U | ||
| 1127 | #define IOMUXC_GPIO_SD_B1_07_FLEXSPIA_SCLK 0x401F81F0U, 0x1U, 0x401F84C8U, 0x0U, 0x401F83E0U | ||
| 1128 | #define IOMUXC_GPIO_SD_B1_07_LPUART7_RTS_B 0x401F81F0U, 0x2U, 0, 0, 0x401F83E0U | ||
| 1129 | #define IOMUXC_GPIO_SD_B1_07_SAI1_TX_DATA00 0x401F81F0U, 0x3U, 0, 0, 0x401F83E0U | ||
| 1130 | #define IOMUXC_GPIO_SD_B1_07_LPSPI2_SCK 0x401F81F0U, 0x4U, 0x401F8500U, 0x0U, 0x401F83E0U | ||
| 1131 | #define IOMUXC_GPIO_SD_B1_07_GPIO3_IO07 0x401F81F0U, 0x5U, 0, 0, 0x401F83E0U | ||
| 1132 | |||
| 1133 | #define IOMUXC_GPIO_SD_B1_08_USDHC2_DATA4 0x401F81F4U, 0x0U, 0x401F85F8U, 0x0U, 0x401F83E4U | ||
| 1134 | #define IOMUXC_GPIO_SD_B1_08_FLEXSPIA_DATA00 0x401F81F4U, 0x1U, 0x401F84A8U, 0x0U, 0x401F83E4U | ||
| 1135 | #define IOMUXC_GPIO_SD_B1_08_LPUART7_TX 0x401F81F4U, 0x2U, 0x401F855CU, 0x0U, 0x401F83E4U | ||
| 1136 | #define IOMUXC_GPIO_SD_B1_08_SAI1_TX_BCLK 0x401F81F4U, 0x3U, 0x401F85A8U, 0x0U, 0x401F83E4U | ||
| 1137 | #define IOMUXC_GPIO_SD_B1_08_LPSPI2_SD0 0x401F81F4U, 0x4U, 0x401F8508U, 0x0U, 0x401F83E4U | ||
| 1138 | #define IOMUXC_GPIO_SD_B1_08_GPIO3_IO08 0x401F81F4U, 0x5U, 0, 0, 0x401F83E4U | ||
| 1139 | #define IOMUXC_GPIO_SD_B1_08_SEMC_CSX02 0x401F81F4U, 0x6U, 0, 0, 0x401F83E4U | ||
| 1140 | |||
| 1141 | #define IOMUXC_GPIO_SD_B1_09_USDHC2_DATA5 0x401F81F8U, 0x0U, 0x401F85FCU, 0x0U, 0x401F83E8U | ||
| 1142 | #define IOMUXC_GPIO_SD_B1_09_FLEXSPIA_DATA01 0x401F81F8U, 0x1U, 0x401F84ACU, 0x0U, 0x401F83E8U | ||
| 1143 | #define IOMUXC_GPIO_SD_B1_09_LPUART7_RX 0x401F81F8U, 0x2U, 0x401F8558U, 0x0U, 0x401F83E8U | ||
| 1144 | #define IOMUXC_GPIO_SD_B1_09_SAI1_TX_SYNC 0x401F81F8U, 0x3U, 0x401F85ACU, 0x0U, 0x401F83E8U | ||
| 1145 | #define IOMUXC_GPIO_SD_B1_09_LPSPI2_SDI 0x401F81F8U, 0x4U, 0x401F8504U, 0x0U, 0x401F83E8U | ||
| 1146 | #define IOMUXC_GPIO_SD_B1_09_GPIO3_IO09 0x401F81F8U, 0x5U, 0, 0, 0x401F83E8U | ||
| 1147 | |||
| 1148 | #define IOMUXC_GPIO_SD_B1_10_USDHC2_DATA6 0x401F81FCU, 0x0U, 0x401F8600U, 0x0U, 0x401F83ECU | ||
| 1149 | #define IOMUXC_GPIO_SD_B1_10_FLEXSPIA_DATA02 0x401F81FCU, 0x1U, 0x401F84B0U, 0x0U, 0x401F83ECU | ||
| 1150 | #define IOMUXC_GPIO_SD_B1_10_LPUART2_RX 0x401F81FCU, 0x2U, 0x401F852CU, 0x0U, 0x401F83ECU | ||
| 1151 | #define IOMUXC_GPIO_SD_B1_10_LPI2C2_SDA 0x401F81FCU, 0x3U, 0x401F84D8U, 0x0U, 0x401F83ECU | ||
| 1152 | #define IOMUXC_GPIO_SD_B1_10_LPSPI2_PCS2 0x401F81FCU, 0x4U, 0, 0, 0x401F83ECU | ||
| 1153 | #define IOMUXC_GPIO_SD_B1_10_GPIO3_IO10 0x401F81FCU, 0x5U, 0, 0, 0x401F83ECU | ||
| 1154 | |||
| 1155 | #define IOMUXC_GPIO_SD_B1_11_USDHC2_DATA7 0x401F8200U, 0x0U, 0x401F8604U, 0x0U, 0x401F83F0U | ||
| 1156 | #define IOMUXC_GPIO_SD_B1_11_FLEXSPIA_DATA03 0x401F8200U, 0x1U, 0x401F84B4U, 0x0U, 0x401F83F0U | ||
| 1157 | #define IOMUXC_GPIO_SD_B1_11_LPUART2_TX 0x401F8200U, 0x2U, 0x401F8530U, 0x0U, 0x401F83F0U | ||
| 1158 | #define IOMUXC_GPIO_SD_B1_11_LPI2C2_SCL 0x401F8200U, 0x3U, 0x401F84D4U, 0x0U, 0x401F83F0U | ||
| 1159 | #define IOMUXC_GPIO_SD_B1_11_LPSPI2_PCS3 0x401F8200U, 0x4U, 0, 0, 0x401F83F0U | ||
| 1160 | #define IOMUXC_GPIO_SD_B1_11_GPIO3_IO11 0x401F8200U, 0x5U, 0, 0, 0x401F83F0U | ||
| 1161 | |||
| 1162 | #define IOMUXC_GPIO_SPI_B0_00 0x401F865CU, 0, 0, 0, 0x401F86B4U | ||
| 1163 | |||
| 1164 | #define IOMUXC_GPIO_SPI_B0_01_FLEXSPI2_B_SCLK 0x401F8660U, 0x0U, 0x401F8754U, 0x1U, 0x401F86B8U | ||
| 1165 | |||
| 1166 | #define IOMUXC_GPIO_SPI_B0_02_FLEXSPI2_A_DATA00 0x401F8664U, 0x0U, 0x401F8730U, 0x2U, 0x401F86BCU | ||
| 1167 | |||
| 1168 | #define IOMUXC_GPIO_SPI_B0_03_FLEXSPI2_B_DATA02 0x401F8668U, 0x0U, 0x401F8748U, 0x1U, 0x401F86C0U | ||
| 1169 | |||
| 1170 | #define IOMUXC_GPIO_SPI_B0_04_FLEXSPI2_B_DATA03 0x401F866CU, 0x0U, 0x401F874CU, 0x1U, 0x401F86C4U | ||
| 1171 | |||
| 1172 | #define IOMUXC_GPIO_SPI_B0_05_FLEXSPI2_A_SS0_B 0x401F8670U, 0x0U, 0, 0, 0x401F86C8U | ||
| 1173 | |||
| 1174 | #define IOMUXC_GPIO_SPI_B0_06_FLEXSPI2_A_DATA02 0x401F8674U, 0x0U, 0x401F8738U, 0x2U, 0x401F86CCU | ||
| 1175 | |||
| 1176 | #define IOMUXC_GPIO_SPI_B0_07_FLEXSPI2_B_DATA01 0x401F8678U, 0x0U, 0x401F8744U, 0x1U, 0x401F86D0U | ||
| 1177 | |||
| 1178 | #define IOMUXC_GPIO_SPI_B0_08_FLEXSPI2_A_SCLK 0x401F867CU, 0x0U, 0x401F8750U, 0x2U, 0x401F86D4U | ||
| 1179 | |||
| 1180 | #define IOMUXC_GPIO_SPI_B0_09_FLEXSPI2_A_DQS 0x401F8680U, 0x0U, 0x401F872CU, 0x2U, 0x401F86D8U | ||
| 1181 | |||
| 1182 | #define IOMUXC_GPIO_SPI_B0_10_FLEXSPI2_A_DATA03 0x401F8684U, 0x0U, 0x401F873CU, 0x2U, 0x401F86DCU | ||
| 1183 | |||
| 1184 | #define IOMUXC_GPIO_SPI_B0_11_FLEXSPI2_B_DATA00 0x401F8688U, 0x0U, 0x401F8740U, 0x1U, 0x401F86E0U | ||
| 1185 | |||
| 1186 | #define IOMUXC_GPIO_SPI_B0_12_FLEXSPI2_A_DATA01 0x401F868CU, 0x0U, 0x401F8734U, 0x2U, 0x401F86E4U | ||
| 1187 | |||
| 1188 | #define IOMUXC_GPIO_SPI_B0_13 0x401F8690U, 0, 0, 0, 0x401F86E8U | ||
| 1189 | |||
| 1190 | #define IOMUXC_GPIO_SPI_B1_00_FLEXSPI2_A_DQS 0x401F8694U, 0x0U, 0x401F872CU, 0x0U, 0x401F86ECU | ||
| 1191 | |||
| 1192 | #define IOMUXC_GPIO_SPI_B1_01_FLEXSPI2_A_DATA03 0x401F8698U, 0x0U, 0x401F873CU, 0x0U, 0x401F86F0U | ||
| 1193 | |||
| 1194 | #define IOMUXC_GPIO_SPI_B1_02_FLEXSPI2_A_DATA02 0x401F869CU, 0x0U, 0x401F8738U, 0x0U, 0x401F86F4U | ||
| 1195 | |||
| 1196 | #define IOMUXC_GPIO_SPI_B1_03_FLEXSPI2_A_DATA01 0x401F86A0U, 0x0U, 0x401F8734U, 0x0U, 0x401F86F8U | ||
| 1197 | |||
| 1198 | #define IOMUXC_GPIO_SPI_B1_04_FLEXSPI2_A_DATA00 0x401F86A4U, 0x0U, 0x401F8730U, 0x0U, 0x401F86FCU | ||
| 1199 | |||
| 1200 | #define IOMUXC_GPIO_SPI_B1_05_FLEXSPI2_A_SCLK 0x401F86A8U, 0x0U, 0x401F8750U, 0x0U, 0x401F8700U | ||
| 1201 | |||
| 1202 | #define IOMUXC_GPIO_SPI_B1_06_FLEXSPI2_A_SS0_B 0x401F86ACU, 0x0U, 0, 0, 0x401F8704U | ||
| 1203 | |||
| 1204 | #define IOMUXC_GPIO_SPI_B1_07 0x401F86B0U, 0, 0, 0, 0x401F8708U | ||
| 1205 | |||
| 1206 | /*@}*/ | ||
| 1207 | |||
| 1208 | #define IOMUXC_GPR_SAIMCLK_LOWBITMASK (0x7U) | ||
| 1209 | #define IOMUXC_GPR_SAIMCLK_HIGHBITMASK (0x3U) | ||
| 1210 | |||
| 1211 | typedef enum _iomuxc_gpr_mode | ||
| 1212 | { | ||
| 1213 | kIOMUXC_GPR_GlobalInterruptRequest = IOMUXC_GPR_GPR1_GINT_MASK, | ||
| 1214 | kIOMUXC_GPR_ENET1RefClkMode = IOMUXC_GPR_GPR1_ENET1_CLK_SEL_MASK, | ||
| 1215 | kIOMUXC_GPR_ENET2RefClkMode = IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, | ||
| 1216 | kIOMUXC_GPR_USBExposureMode = IOMUXC_GPR_GPR1_USB_EXP_MODE_MASK, | ||
| 1217 | kIOMUXC_GPR_ENET1TxClkOutputDir = IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK, | ||
| 1218 | kIOMUXC_GPR_ENET2TxClkOutputDir = IOMUXC_GPR_GPR1_ENET2_TX_CLK_DIR_MASK, | ||
| 1219 | kIOMUXC_GPR_SAI1MClkOutputDir = IOMUXC_GPR_GPR1_SAI1_MCLK_DIR_MASK, | ||
| 1220 | kIOMUXC_GPR_SAI2MClkOutputDir = IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK, | ||
| 1221 | kIOMUXC_GPR_SAI3MClkOutputDir = IOMUXC_GPR_GPR1_SAI3_MCLK_DIR_MASK, | ||
| 1222 | kIOMUXC_GPR_ExcMonitorSlavErrResponse = IOMUXC_GPR_GPR1_EXC_MON_MASK, | ||
| 1223 | kIOMUXC_GPR_ENETIpgClkOn = IOMUXC_GPR_GPR1_ENET_IPG_CLK_S_EN_MASK, | ||
| 1224 | kIOMUXC_GPR_AHBClockEnable = (int)IOMUXC_GPR_GPR1_CM7_FORCE_HCLK_EN_MASK, | ||
| 1225 | } iomuxc_gpr_mode_t; | ||
| 1226 | |||
| 1227 | typedef enum _iomuxc_gpr_saimclk | ||
| 1228 | { | ||
| 1229 | kIOMUXC_GPR_SAI1MClk1Sel = IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_SHIFT, | ||
| 1230 | kIOMUXC_GPR_SAI1MClk2Sel = IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_SHIFT, | ||
| 1231 | kIOMUXC_GPR_SAI1MClk3Sel = IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_SHIFT, | ||
| 1232 | kIOMUXC_GPR_SAI2MClk3Sel = IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT, | ||
| 1233 | kIOMUXC_GPR_SAI3MClk3Sel = IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_SHIFT, | ||
| 1234 | } iomuxc_gpr_saimclk_t; | ||
| 1235 | |||
| 1236 | typedef enum _iomuxc_mqs_pwm_oversample_rate | ||
| 1237 | { | ||
| 1238 | kIOMUXC_MqsPwmOverSampleRate32 = 0, /* MQS PWM over sampling rate 32. */ | ||
| 1239 | kIOMUXC_MqsPwmOverSampleRate64 = 1 /* MQS PWM over sampling rate 64. */ | ||
| 1240 | } iomuxc_mqs_pwm_oversample_rate_t; | ||
| 1241 | |||
| 1242 | #if defined(__cplusplus) | ||
| 1243 | extern "C" { | ||
| 1244 | #endif /*_cplusplus */ | ||
| 1245 | |||
| 1246 | /*! @name Configuration */ | ||
| 1247 | /*@{*/ | ||
| 1248 | |||
| 1249 | /*! | ||
| 1250 | * @brief Sets the IOMUXC pin mux mode. | ||
| 1251 | * @note The first five parameters can be filled with the pin function ID macros. | ||
| 1252 | * | ||
| 1253 | * This is an example to set the PTA6 as the lpuart0_tx: | ||
| 1254 | * @code | ||
| 1255 | * IOMUXC_SetPinMux(IOMUXC_PTA6_LPUART0_TX, 0); | ||
| 1256 | * @endcode | ||
| 1257 | * | ||
| 1258 | * This is an example to set the PTA0 as GPIOA0: | ||
| 1259 | * @code | ||
| 1260 | * IOMUXC_SetPinMux(IOMUXC_PTA0_GPIOA0, 0); | ||
| 1261 | * @endcode | ||
| 1262 | * | ||
| 1263 | * @param muxRegister The pin mux register. | ||
| 1264 | * @param muxMode The pin mux mode. | ||
| 1265 | * @param inputRegister The select input register. | ||
| 1266 | * @param inputDaisy The input daisy. | ||
| 1267 | * @param configRegister The config register. | ||
| 1268 | * @param inputOnfield Software input on field. | ||
| 1269 | */ | ||
| 1270 | static inline void IOMUXC_SetPinMux(uint32_t muxRegister, | ||
| 1271 | uint32_t muxMode, | ||
| 1272 | uint32_t inputRegister, | ||
| 1273 | uint32_t inputDaisy, | ||
| 1274 | uint32_t configRegister, | ||
| 1275 | uint32_t inputOnfield) | ||
| 1276 | { | ||
| 1277 | *((volatile uint32_t *)muxRegister) = | ||
| 1278 | IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(muxMode) | IOMUXC_SW_MUX_CTL_PAD_SION(inputOnfield); | ||
| 1279 | |||
| 1280 | if (inputRegister != 0UL) | ||
| 1281 | { | ||
| 1282 | *((volatile uint32_t *)inputRegister) = inputDaisy; | ||
| 1283 | } | ||
| 1284 | } | ||
| 1285 | |||
| 1286 | /*! | ||
| 1287 | * @brief Sets the IOMUXC pin configuration. | ||
| 1288 | * @note The previous five parameters can be filled with the pin function ID macros. | ||
| 1289 | * | ||
| 1290 | * This is an example to set pin configuration for IOMUXC_PTA3_LPI2C0_SCLS: | ||
| 1291 | * @code | ||
| 1292 | * IOMUXC_SetPinConfig(IOMUXC_PTA3_LPI2C0_SCLS,IOMUXC_SW_PAD_CTL_PAD_PUS_MASK|IOMUXC_SW_PAD_CTL_PAD_PUS(2U)) | ||
| 1293 | * @endcode | ||
| 1294 | * | ||
| 1295 | * @param muxRegister The pin mux register. | ||
| 1296 | * @param muxMode The pin mux mode. | ||
| 1297 | * @param inputRegister The select input register. | ||
| 1298 | * @param inputDaisy The input daisy. | ||
| 1299 | * @param configRegister The config register. | ||
| 1300 | * @param configValue The pin config value. | ||
| 1301 | */ | ||
| 1302 | static inline void IOMUXC_SetPinConfig(uint32_t muxRegister, | ||
| 1303 | uint32_t muxMode, | ||
| 1304 | uint32_t inputRegister, | ||
| 1305 | uint32_t inputDaisy, | ||
| 1306 | uint32_t configRegister, | ||
| 1307 | uint32_t configValue) | ||
| 1308 | { | ||
| 1309 | if (configRegister != 0UL) | ||
| 1310 | { | ||
| 1311 | *((volatile uint32_t *)configRegister) = configValue; | ||
| 1312 | } | ||
| 1313 | } | ||
| 1314 | |||
| 1315 | /*! | ||
| 1316 | * @brief Sets IOMUXC general configuration for some mode. | ||
| 1317 | * | ||
| 1318 | * @param base The IOMUXC GPR base address. | ||
| 1319 | * @param mode The mode for setting. the mode is the logical OR of "iomuxc_gpr_mode" | ||
| 1320 | * @param enable True enable false disable. | ||
| 1321 | */ | ||
| 1322 | static inline void IOMUXC_EnableMode(IOMUXC_GPR_Type *base, uint32_t mode, bool enable) | ||
| 1323 | { | ||
| 1324 | mode &= ~(IOMUXC_GPR_GPR1_SAI1_MCLK1_SEL_MASK | IOMUXC_GPR_GPR1_SAI1_MCLK2_SEL_MASK | | ||
| 1325 | IOMUXC_GPR_GPR1_SAI1_MCLK3_SEL_MASK | IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK | | ||
| 1326 | IOMUXC_GPR_GPR1_SAI3_MCLK3_SEL_MASK); | ||
| 1327 | |||
| 1328 | if (enable) | ||
| 1329 | { | ||
| 1330 | base->GPR1 |= mode; | ||
| 1331 | } | ||
| 1332 | else | ||
| 1333 | { | ||
| 1334 | base->GPR1 &= ~mode; | ||
| 1335 | } | ||
| 1336 | } | ||
| 1337 | |||
| 1338 | /*! | ||
| 1339 | * @brief Sets IOMUXC general configuration for SAI MCLK selection. | ||
| 1340 | * | ||
| 1341 | * @param base The IOMUXC GPR base address. | ||
| 1342 | * @param mclk The SAI MCLK. | ||
| 1343 | * @param clkSrc The clock source. Take refer to register setting details for the clock source in RM. | ||
| 1344 | */ | ||
| 1345 | static inline void IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR_Type *base, iomuxc_gpr_saimclk_t mclk, uint8_t clkSrc) | ||
| 1346 | { | ||
| 1347 | uint32_t gpr; | ||
| 1348 | |||
| 1349 | if (mclk > kIOMUXC_GPR_SAI1MClk2Sel) | ||
| 1350 | { | ||
| 1351 | gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_HIGHBITMASK << (uint32_t)mclk); | ||
| 1352 | base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_HIGHBITMASK) << (uint32_t)mclk) | gpr; | ||
| 1353 | } | ||
| 1354 | else | ||
| 1355 | { | ||
| 1356 | gpr = base->GPR1 & ~((uint32_t)IOMUXC_GPR_SAIMCLK_LOWBITMASK << (uint32_t)mclk); | ||
| 1357 | base->GPR1 = (((uint32_t)clkSrc & IOMUXC_GPR_SAIMCLK_LOWBITMASK) << (uint32_t)mclk) | gpr; | ||
| 1358 | } | ||
| 1359 | } | ||
| 1360 | |||
| 1361 | /*! | ||
| 1362 | * @brief Enters or exit MQS software reset. | ||
| 1363 | * | ||
| 1364 | * @param base The IOMUXC GPR base address. | ||
| 1365 | * @param enable Enter or exit MQS software reset. | ||
| 1366 | */ | ||
| 1367 | static inline void IOMUXC_MQSEnterSoftwareReset(IOMUXC_GPR_Type *base, bool enable) | ||
| 1368 | { | ||
| 1369 | if (enable) | ||
| 1370 | { | ||
| 1371 | base->GPR2 |= IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; | ||
| 1372 | } | ||
| 1373 | else | ||
| 1374 | { | ||
| 1375 | base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_SW_RST_MASK; | ||
| 1376 | } | ||
| 1377 | } | ||
| 1378 | |||
| 1379 | /*! | ||
| 1380 | * @brief Enables or disables MQS. | ||
| 1381 | * | ||
| 1382 | * @param base The IOMUXC GPR base address. | ||
| 1383 | * @param enable Enable or disable the MQS. | ||
| 1384 | */ | ||
| 1385 | static inline void IOMUXC_MQSEnable(IOMUXC_GPR_Type *base, bool enable) | ||
| 1386 | { | ||
| 1387 | if (enable) | ||
| 1388 | { | ||
| 1389 | base->GPR2 |= IOMUXC_GPR_GPR2_MQS_EN_MASK; | ||
| 1390 | } | ||
| 1391 | else | ||
| 1392 | { | ||
| 1393 | base->GPR2 &= ~IOMUXC_GPR_GPR2_MQS_EN_MASK; | ||
| 1394 | } | ||
| 1395 | } | ||
| 1396 | |||
| 1397 | /*! | ||
| 1398 | * @brief Configure MQS PWM oversampling rate compared with mclk and divider ratio control for mclk from hmclk. | ||
| 1399 | * | ||
| 1400 | * @param base The IOMUXC GPR base address. | ||
| 1401 | * @param rate The MQS PWM oversampling rate, refer to "iomuxc_mqs_pwm_oversample_rate_t". | ||
| 1402 | * @param divider The divider ratio control for mclk from hmclk. mclk freq = 1 /(divider + 1) * hmclk freq. | ||
| 1403 | */ | ||
| 1404 | |||
| 1405 | static inline void IOMUXC_MQSConfig(IOMUXC_GPR_Type *base, iomuxc_mqs_pwm_oversample_rate_t rate, uint8_t divider) | ||
| 1406 | { | ||
| 1407 | uint32_t gpr = base->GPR2 & ~(IOMUXC_GPR_GPR2_MQS_OVERSAMPLE_MASK | IOMUXC_GPR_GPR2_MQS_CLK_DIV_MASK); | ||
| 1408 | base->GPR2 = gpr | IOMUXC_GPR_GPR2_MQS_OVERSAMPLE(rate) | IOMUXC_GPR_GPR2_MQS_CLK_DIV(divider); | ||
| 1409 | } | ||
| 1410 | |||
| 1411 | /*@}*/ | ||
| 1412 | |||
| 1413 | #if defined(__cplusplus) | ||
| 1414 | } | ||
| 1415 | #endif /*_cplusplus */ | ||
| 1416 | |||
| 1417 | /*! @}*/ | ||
| 1418 | |||
| 1419 | #endif /* _FSL_IOMUXC_H_ */ | ||