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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1062/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT1062/project_template/clock_config.c
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@@ -0,0 +1,493 @@
1/*
2 * Copyright 2018-2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v5.0
26processor: MIMXRT1062xxxxA
27package_id: MIMXRT1062DVL6A
28mcu_data: ksdk2_0
29processor_version: 0.0.0
30board: MIMXRT1060-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
63- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
64- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
65- {id: CLK_1M.outFreq, value: 1 MHz}
66- {id: CLK_24M.outFreq, value: 24 MHz}
67- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
68- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
69- {id: ENET2_125M_CLK.outFreq, value: 1.2 MHz}
70- {id: ENET2_TX_CLK.outFreq, value: 1.2 MHz}
71- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
72- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
73- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
74- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
75- {id: FLEXSPI2_CLK_ROOT.outFreq, value: 1440/11 MHz}
76- {id: FLEXSPI_CLK_ROOT.outFreq, value: 1440/11 MHz}
77- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
78- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
79- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
80- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5/7 MHz}
81- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
82- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
83- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
84- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
85- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
86- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
87- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
88- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
89- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
90- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
91- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
92- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
93- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
94- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
95- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
96- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
97- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
98- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
99- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
100- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
101- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
102- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
103settings:
104- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
105- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
106- {id: CCM.FLEXSPI2_PODF.scale, value: '2', locked: true}
107- {id: CCM.FLEXSPI2_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
108- {id: CCM.FLEXSPI_PODF.scale, value: '2', locked: true}
109- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
110- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
111- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
112- {id: CCM.SEMC_PODF.scale, value: '8'}
113- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
114- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
115- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
116- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
117- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
118- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
119- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
120- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
121- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
122- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
123- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
124- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
125- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
126- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '33', locked: true}
127- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
128- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
129- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
130- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
131- {id: CCM_ANALOG.PLL4.denom, value: '50'}
132- {id: CCM_ANALOG.PLL4.div, value: '47'}
133- {id: CCM_ANALOG.PLL5.denom, value: '1'}
134- {id: CCM_ANALOG.PLL5.div, value: '40'}
135- {id: CCM_ANALOG.PLL5.num, value: '0'}
136- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
137- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
138sources:
139- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
140- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
141 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
142
143/*******************************************************************************
144 * Variables for BOARD_BootClockRUN configuration
145 ******************************************************************************/
146const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
147 .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
148 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
149};
150const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
151 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
152 .numerator = 0, /* 30 bit numerator of fractional loop divider */
153 .denominator = 1, /* 30 bit denominator of fractional loop divider */
154 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
155};
156const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
157 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
158 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
159};
160/*******************************************************************************
161 * Code for BOARD_BootClockRUN configuration
162 ******************************************************************************/
163void BOARD_BootClockRUN(void)
164{
165 /* Init RTC OSC clock frequency. */
166 CLOCK_SetRtcXtalFreq(32768U);
167 /* Enable 1MHz clock output. */
168 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
169 /* Use free 1MHz clock output. */
170 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
171 /* Set XTAL 24MHz clock frequency. */
172 CLOCK_SetXtalFreq(24000000U);
173 /* Enable XTAL 24MHz clock source. */
174 CLOCK_InitExternalClk(0);
175 /* Enable internal RC. */
176 CLOCK_InitRcOsc24M();
177 /* Switch clock source to external OSC. */
178 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
179 /* Set Oscillator ready counter value. */
180 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
181 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
182 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
183 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
184 /* Setting the VDD_SOC to 1.275V. It is necessary to config AHB to 600Mhz. */
185 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x13);
186 /* Waiting for DCDC_STS_DC_OK bit is asserted */
187 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
188 {
189 }
190 /* Set AHB_PODF. */
191 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
192 /* Disable IPG clock gate. */
193 CLOCK_DisableClock(kCLOCK_Adc1);
194 CLOCK_DisableClock(kCLOCK_Adc2);
195 CLOCK_DisableClock(kCLOCK_Xbar1);
196 CLOCK_DisableClock(kCLOCK_Xbar2);
197 CLOCK_DisableClock(kCLOCK_Xbar3);
198 /* Set IPG_PODF. */
199 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
200 /* Set ARM_PODF. */
201 CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
202 /* Set PERIPH_CLK2_PODF. */
203 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
204 /* Disable PERCLK clock gate. */
205 CLOCK_DisableClock(kCLOCK_Gpt1);
206 CLOCK_DisableClock(kCLOCK_Gpt1S);
207 CLOCK_DisableClock(kCLOCK_Gpt2);
208 CLOCK_DisableClock(kCLOCK_Gpt2S);
209 CLOCK_DisableClock(kCLOCK_Pit);
210 /* Set PERCLK_PODF. */
211 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
212 /* Disable USDHC1 clock gate. */
213 CLOCK_DisableClock(kCLOCK_Usdhc1);
214 /* Set USDHC1_PODF. */
215 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
216 /* Set Usdhc1 clock source. */
217 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
218 /* Disable USDHC2 clock gate. */
219 CLOCK_DisableClock(kCLOCK_Usdhc2);
220 /* Set USDHC2_PODF. */
221 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
222 /* Set Usdhc2 clock source. */
223 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
224 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
225 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
226 * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
227 * well.*/
228#ifndef SKIP_SYSCLK_INIT
229 /* Disable Semc clock gate. */
230 CLOCK_DisableClock(kCLOCK_Semc);
231 /* Set SEMC_PODF. */
232 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
233 /* Set Semc alt clock source. */
234 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
235 /* Set Semc clock source. */
236 CLOCK_SetMux(kCLOCK_SemcMux, 0);
237#endif
238 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
239 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
240 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
241 * well.*/
242#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
243 /* Disable Flexspi clock gate. */
244 CLOCK_DisableClock(kCLOCK_FlexSpi);
245 /* Set FLEXSPI_PODF. */
246 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
247 /* Set Flexspi clock source. */
248 CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
249#endif
250 /* Disable Flexspi2 clock gate. */
251 CLOCK_DisableClock(kCLOCK_FlexSpi2);
252 /* Set FLEXSPI2_PODF. */
253 CLOCK_SetDiv(kCLOCK_Flexspi2Div, 1);
254 /* Set Flexspi2 clock source. */
255 CLOCK_SetMux(kCLOCK_Flexspi2Mux, 1);
256 /* Disable CSI clock gate. */
257 CLOCK_DisableClock(kCLOCK_Csi);
258 /* Set CSI_PODF. */
259 CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
260 /* Set Csi clock source. */
261 CLOCK_SetMux(kCLOCK_CsiMux, 0);
262 /* Disable LPSPI clock gate. */
263 CLOCK_DisableClock(kCLOCK_Lpspi1);
264 CLOCK_DisableClock(kCLOCK_Lpspi2);
265 CLOCK_DisableClock(kCLOCK_Lpspi3);
266 CLOCK_DisableClock(kCLOCK_Lpspi4);
267 /* Set LPSPI_PODF. */
268 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
269 /* Set Lpspi clock source. */
270 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
271 /* Disable TRACE clock gate. */
272 CLOCK_DisableClock(kCLOCK_Trace);
273 /* Set TRACE_PODF. */
274 CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
275 /* Set Trace clock source. */
276 CLOCK_SetMux(kCLOCK_TraceMux, 2);
277 /* Disable SAI1 clock gate. */
278 CLOCK_DisableClock(kCLOCK_Sai1);
279 /* Set SAI1_CLK_PRED. */
280 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
281 /* Set SAI1_CLK_PODF. */
282 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
283 /* Set Sai1 clock source. */
284 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
285 /* Disable SAI2 clock gate. */
286 CLOCK_DisableClock(kCLOCK_Sai2);
287 /* Set SAI2_CLK_PRED. */
288 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
289 /* Set SAI2_CLK_PODF. */
290 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
291 /* Set Sai2 clock source. */
292 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
293 /* Disable SAI3 clock gate. */
294 CLOCK_DisableClock(kCLOCK_Sai3);
295 /* Set SAI3_CLK_PRED. */
296 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
297 /* Set SAI3_CLK_PODF. */
298 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
299 /* Set Sai3 clock source. */
300 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
301 /* Disable Lpi2c clock gate. */
302 CLOCK_DisableClock(kCLOCK_Lpi2c1);
303 CLOCK_DisableClock(kCLOCK_Lpi2c2);
304 CLOCK_DisableClock(kCLOCK_Lpi2c3);
305 /* Set LPI2C_CLK_PODF. */
306 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
307 /* Set Lpi2c clock source. */
308 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
309 /* Disable CAN clock gate. */
310 CLOCK_DisableClock(kCLOCK_Can1);
311 CLOCK_DisableClock(kCLOCK_Can2);
312 CLOCK_DisableClock(kCLOCK_Can3);
313 CLOCK_DisableClock(kCLOCK_Can1S);
314 CLOCK_DisableClock(kCLOCK_Can2S);
315 CLOCK_DisableClock(kCLOCK_Can3S);
316 /* Set CAN_CLK_PODF. */
317 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
318 /* Set Can clock source. */
319 CLOCK_SetMux(kCLOCK_CanMux, 2);
320 /* Disable UART clock gate. */
321 CLOCK_DisableClock(kCLOCK_Lpuart1);
322 CLOCK_DisableClock(kCLOCK_Lpuart2);
323 CLOCK_DisableClock(kCLOCK_Lpuart3);
324 CLOCK_DisableClock(kCLOCK_Lpuart4);
325 CLOCK_DisableClock(kCLOCK_Lpuart5);
326 CLOCK_DisableClock(kCLOCK_Lpuart6);
327 CLOCK_DisableClock(kCLOCK_Lpuart7);
328 CLOCK_DisableClock(kCLOCK_Lpuart8);
329 /* Set UART_CLK_PODF. */
330 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
331 /* Set Uart clock source. */
332 CLOCK_SetMux(kCLOCK_UartMux, 0);
333 /* Disable LCDIF clock gate. */
334 CLOCK_DisableClock(kCLOCK_LcdPixel);
335 /* Set LCDIF_PRED. */
336 CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
337 /* Set LCDIF_CLK_PODF. */
338 CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
339 /* Set Lcdif pre clock source. */
340 CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
341 /* Disable SPDIF clock gate. */
342 CLOCK_DisableClock(kCLOCK_Spdif);
343 /* Set SPDIF0_CLK_PRED. */
344 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
345 /* Set SPDIF0_CLK_PODF. */
346 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
347 /* Set Spdif clock source. */
348 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
349 /* Disable Flexio1 clock gate. */
350 CLOCK_DisableClock(kCLOCK_Flexio1);
351 /* Set FLEXIO1_CLK_PRED. */
352 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
353 /* Set FLEXIO1_CLK_PODF. */
354 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
355 /* Set Flexio1 clock source. */
356 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
357 /* Disable Flexio2 clock gate. */
358 CLOCK_DisableClock(kCLOCK_Flexio2);
359 /* Set FLEXIO2_CLK_PRED. */
360 CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
361 /* Set FLEXIO2_CLK_PODF. */
362 CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
363 /* Set Flexio2 clock source. */
364 CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
365 /* Set Pll3 sw clock source. */
366 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
367 /* Init ARM PLL. */
368 CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
369 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
370 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
371 * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
372 * well.*/
373#ifndef SKIP_SYSCLK_INIT
374 /* Init System PLL. */
375 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
376 /* Init System pfd0. */
377 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
378 /* Init System pfd1. */
379 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
380 /* Init System pfd2. */
381 CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
382 /* Init System pfd3. */
383 CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
384#endif
385 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
386 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
387 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
388 * well.*/
389#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
390 /* Init Usb1 PLL. */
391 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
392 /* Init Usb1 pfd0. */
393 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 33);
394 /* Init Usb1 pfd1. */
395 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
396 /* Init Usb1 pfd2. */
397 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
398 /* Init Usb1 pfd3. */
399 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 19);
400 /* Disable Usb1 PLL output for USBPHY1. */
401 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
402#endif
403 /* DeInit Audio PLL. */
404 CLOCK_DeinitAudioPll();
405 /* Bypass Audio PLL. */
406 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
407 /* Set divider for Audio PLL. */
408 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
409 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
410 /* Enable Audio PLL output. */
411 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
412 /* DeInit Video PLL. */
413 CLOCK_DeinitVideoPll();
414 /* Bypass Video PLL. */
415 CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
416 /* Set divider for Video PLL. */
417 CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
418 /* Enable Video PLL output. */
419 CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
420 /* DeInit Enet PLL. */
421 CLOCK_DeinitEnetPll();
422 /* Bypass Enet PLL. */
423 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
424 /* Set Enet output divider. */
425 CCM_ANALOG->PLL_ENET =
426 (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
427 /* Enable Enet output. */
428 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
429 /* Set Enet2 output divider. */
430 CCM_ANALOG->PLL_ENET =
431 (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_ENET2_DIV_SELECT(0);
432 /* Enable Enet2 output. */
433 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET2_REF_EN_MASK;
434 /* Enable Enet25M output. */
435 CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
436 /* DeInit Usb2 PLL. */
437 CLOCK_DeinitUsb2Pll();
438 /* Bypass Usb2 PLL. */
439 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllUsb2, 1);
440 /* Enable Usb2 PLL output. */
441 CCM_ANALOG->PLL_USB2 |= CCM_ANALOG_PLL_USB2_ENABLE_MASK;
442 /* Set preperiph clock source. */
443 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
444 /* Set periph clock source. */
445 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
446 /* Set periph clock2 clock source. */
447 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
448 /* Set per clock source. */
449 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
450 /* Set lvds1 clock source. */
451 CCM_ANALOG->MISC1 =
452 (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
453 /* Set clock out1 divider. */
454 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
455 /* Set clock out1 source. */
456 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
457 /* Set clock out2 divider. */
458 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
459 /* Set clock out2 source. */
460 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(18);
461 /* Set clock out1 drives clock out1. */
462 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
463 /* Disable clock out1. */
464 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
465 /* Disable clock out2. */
466 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
467 /* Set SAI1 MCLK1 clock source. */
468 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
469 /* Set SAI1 MCLK2 clock source. */
470 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
471 /* Set SAI1 MCLK3 clock source. */
472 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
473 /* Set SAI2 MCLK3 clock source. */
474 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
475 /* Set SAI3 MCLK3 clock source. */
476 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
477 /* Set MQS configuration. */
478 IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
479 /* Set ENET1 Tx clock source. */
480 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
481 /* Set ENET2 Tx clock source. */
482#if defined(FSL_IOMUXC_DRIVER_VERSION) && (FSL_IOMUXC_DRIVER_VERSION != (MAKE_VERSION(2, 0, 0)))
483 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2RefClkMode, false);
484#else
485 IOMUXC_EnableMode(IOMUXC_GPR, IOMUXC_GPR_GPR1_ENET2_CLK_SEL_MASK, false);
486#endif
487 /* Set GPT1 High frequency reference clock source. */
488 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
489 /* Set GPT2 High frequency reference clock source. */
490 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
491 /* Set SystemCoreClock variable. */
492 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
493}
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 20:24:09 +0100