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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT633S/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT633S/drivers/fsl_clock.h
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index 000000000..c2003d90c
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT633S/drivers/fsl_clock.h
@@ -0,0 +1,1203 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020 , NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_CLOCK_H_
10#define _FSL_CLOCK_H_
11
12#include "fsl_device_registers.h"
13#include <stdint.h>
14#include <stdbool.h>
15#include <assert.h>
16#include "fsl_reset.h"
17#include "fsl_common.h"
18
19/*! @addtogroup clock */
20/*! @{ */
21
22/*! @file */
23
24/*******************************************************************************
25 * Definitions
26 *****************************************************************************/
27
28/*! @name Driver version */
29/*@{*/
30/*! @brief CLOCK driver version 2.7.0. */
31#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 7, 0))
32/*@}*/
33
34/* Definition for delay API in clock driver, users can redefine it to the real application. */
35#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
36#ifdef __XCC__
37#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
38#else
39#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (300000000UL)
40#endif
41#endif
42
43/*! @brief External XTAL (SYSOSC) clock frequency.
44 *
45 * The XTAL (SYSOSC) clock frequency in Hz, when the clock is setup, use the
46 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
47 * if XTAL is 16MHz,
48 * @code
49 * CLOCK_SetXtalFreq(160000000);
50 * @endcode
51 */
52extern volatile uint32_t g_xtalFreq;
53/*! @brief External CLK_IN pin clock frequency (clkin) clock frequency.
54 *
55 * The CLK_IN pin (clkin) clock frequency in Hz, when the clock is setup, use the
56 * function CLOCK_SetClkinFreq to set the value in to clock driver. For example,
57 * if CLK_IN is 16MHz,
58 * @code
59 * CLOCK_SetClkinFreq(160000000);
60 * @endcode
61 */
62extern volatile uint32_t g_clkinFreq;
63/*! @brief External XTAL (SYSOSC) clock frequency.
64 *
65 * The MCLK in (mclk_in) PIN clock frequency in Hz, when the clock is setup, use the
66 * function CLOCK_SetMclkInFreq to set the value in to clock driver. For example,
67 * if mclk_In is 16MHz,
68 * @code
69 * CLOCK_SetMclkInFreq(160000000);
70 * @endcode
71 */
72extern volatile uint32_t g_mclkFreq;
73
74/*! @brief Clock ip name array for ACMP. */
75#define CMP_CLOCKS \
76 { \
77 kCLOCK_Acmp0 \
78 }
79/*! @brief Clock ip name array for FLEXCOMM. */
80#define FLEXCOMM_CLOCKS \
81 { \
82 kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3, kCLOCK_Flexcomm4, kCLOCK_Flexcomm5, \
83 kCLOCK_Flexcomm6, kCLOCK_Flexcomm7, kCLOCK_Flexcomm14, kCLOCK_Flexcomm15 \
84 }
85/*! @brief Clock ip name array for LPUART. */
86#define USART_CLOCKS \
87 { \
88 kCLOCK_Usart0, kCLOCK_Usart1, kCLOCK_Usart2, kCLOCK_Usart3, kCLOCK_Usart4, kCLOCK_Usart5, kCLOCK_Usart6, \
89 kCLOCK_Usart7 \
90 }
91
92/*! @brief Clock ip name array for I2C. */
93#define I2C_CLOCKS \
94 { \
95 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, kCLOCK_I2c5, kCLOCK_I2c6, kCLOCK_I2c7, \
96 kCLOCK_I2c15 \
97 }
98/*! @brief Clock ip name array for I3C. */
99#define I3C_CLOCKS \
100 { \
101 kCLOCK_I3c0 \
102 }
103/*! @brief Clock ip name array for SPI. */
104#define SPI_CLOCKS \
105 { \
106 kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2, kCLOCK_Spi3, kCLOCK_Spi4, kCLOCK_Spi5, kCLOCK_Spi6, kCLOCK_Spi7, \
107 kCLOCK_Spi14 \
108 }
109/*! @brief Clock ip name array for FLEXI2S. */
110#define FLEXI2S_CLOCKS \
111 { \
112 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
113 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
114 }
115/*! @brief Clock ip name array for UTICK. */
116#define UTICK_CLOCKS \
117 { \
118 kCLOCK_Utick0 \
119 }
120/*! @brief Clock ip name array for DMIC. */
121#define DMIC_CLOCKS \
122 { \
123 kCLOCK_Dmic0 \
124 }
125/*! @brief Clock ip name array for CT32B. */
126#define CTIMER_CLOCKS \
127 { \
128 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
129 }
130
131/*! @brief Clock ip name array for GPIO. */
132#define GPIO_CLOCKS \
133 { \
134 kCLOCK_HsGpio0, kCLOCK_HsGpio1, kCLOCK_HsGpio2, kCLOCK_HsGpio3, kCLOCK_HsGpio4, kCLOCK_HsGpio5, \
135 kCLOCK_HsGpio6, kCLOCK_HsGpio7 \
136 }
137/*! @brief Clock ip name array for ADC. */
138#define LPADC_CLOCKS \
139 { \
140 kCLOCK_Adc0 \
141 }
142/*! @brief Clock ip name array for MRT. */
143#define MRT_CLOCKS \
144 { \
145 kCLOCK_Mrt0 \
146 }
147/*! @brief Clock ip name array for SCT. */
148#define SCT_CLOCKS \
149 { \
150 kCLOCK_Sct \
151 }
152/*! @brief Clock ip name array for RTC. */
153#define RTC_CLOCKS \
154 { \
155 kCLOCK_Rtc \
156 }
157/*! @brief Clock ip name array for WWDT. */
158#define WWDT_CLOCKS \
159 { \
160 kCLOCK_Wwdt0, kCLOCK_Wwdt1 \
161 }
162/*! @brief Clock ip name array for CRC. */
163#define CRC_CLOCKS \
164 { \
165 kCLOCK_Crc \
166 }
167/*! @brief Clock ip name array for USBD. */
168#define USBD_CLOCKS \
169 { \
170 kCLOCK_UsbhsDevice \
171 }
172/*! @brief Clock ip name array for DMA. */
173#define DMA_CLOCKS \
174 { \
175 kCLOCK_Dmac0, kCLOCK_Dmac1 \
176 }
177/*! @brief Clock ip name array for PINT. */
178#define PINT_CLOCKS \
179 { \
180 kCLOCK_Pint \
181 }
182/*! @brief Clock ip name array for FLEXSPI */
183#define FLEXSPI_CLOCKS \
184 { \
185 kCLOCK_Flexspi \
186 }
187/*! @brief Clock ip name array for Cache64 */
188#define CACHE64_CLOCKS \
189 { \
190 kCLOCK_Flexspi \
191 }
192/*! @brief Clock ip name array for MUA */
193#define MU_CLOCKS \
194 { \
195 kCLOCK_Mu \
196 }
197/*! @brief Clock ip name array for SEMA */
198#define SEMA42_CLOCKS \
199 { \
200 kCLOCK_Sema \
201 }
202/*! @brief Clock ip name array for RNG */
203#define TRNG_CLOCKS \
204 { \
205 kCLOCK_Rng \
206 }
207/*! @brief Clock ip name array for uSDHC */
208#define USDHC_CLOCKS \
209 { \
210 kCLOCK_Sdio0, kCLOCK_Sdio1 \
211 }
212/*! @brief Clock ip name array for OSTimer */
213#define OSTIMER_CLOCKS \
214 { \
215 kCLOCK_OsEventTimer \
216 }
217
218/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
219/*------------------------------------------------------------------------------
220 clock_ip_name_t definition:
221------------------------------------------------------------------------------*/
222
223#define CLK_GATE_REG_OFFSET_SHIFT 8U
224#define CLK_GATE_REG_OFFSET_MASK 0xFF00U
225#define CLK_GATE_BIT_SHIFT_SHIFT 0U
226#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
227
228#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
229 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
230 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
231
232#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
233#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
234
235#define CLK_CTL0_PSCCTL0 0
236#define CLK_CTL0_PSCCTL1 1
237#define CLK_CTL0_PSCCTL2 2
238#define CLK_CTL1_PSCCTL0 3
239#define CLK_CTL1_PSCCTL1 4
240#define CLK_CTL1_PSCCTL2 5
241
242/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
243typedef enum _clock_ip_name
244{
245 kCLOCK_IpInvalid = 0U,
246 kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2),
247 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8),
248 kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9),
249 kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10),
250 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11),
251 kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12),
252 kCLOCK_Flexspi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16),
253 kCLOCK_OtpCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 17),
254 kCLOCK_UsbhsPhy = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20),
255 kCLOCK_UsbhsDevice = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 21),
256 kCLOCK_UsbhsHost = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 22),
257 kCLOCK_UsbhsSram = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 23),
258 kCLOCK_Sct = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 24),
259
260 kCLOCK_Sdio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 2),
261 kCLOCK_Sdio1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 3),
262 kCLOCK_Acmp0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 15),
263 kCLOCK_Adc0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 16),
264 kCLOCK_ShsGpio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 24),
265
266 kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0),
267 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1),
268
269 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
270 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
271 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
272 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
273 kCLOCK_Flexcomm4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
274 kCLOCK_Flexcomm5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
275 kCLOCK_Flexcomm6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
276 kCLOCK_Flexcomm7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
277 kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22),
278 kCLOCK_Flexcomm15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23),
279 kCLOCK_Usart0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
280 kCLOCK_Usart1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
281 kCLOCK_Usart2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
282 kCLOCK_Usart3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
283 kCLOCK_Usart4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
284 kCLOCK_Usart5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
285 kCLOCK_Usart6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
286 kCLOCK_Usart7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
287 kCLOCK_I2s0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
288 kCLOCK_I2s1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
289 kCLOCK_I2s2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
290 kCLOCK_I2s3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
291 kCLOCK_I2s4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
292 kCLOCK_I2s5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
293 kCLOCK_I2s6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
294 kCLOCK_I2s7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
295 kCLOCK_I2c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
296 kCLOCK_I2c1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
297 kCLOCK_I2c2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
298 kCLOCK_I2c3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
299 kCLOCK_I2c4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
300 kCLOCK_I2c5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
301 kCLOCK_I2c6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
302 kCLOCK_I2c7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
303 kCLOCK_I2c15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23),
304 kCLOCK_Spi0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
305 kCLOCK_Spi1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
306 kCLOCK_Spi2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
307 kCLOCK_Spi3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
308 kCLOCK_Spi4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
309 kCLOCK_Spi5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
310 kCLOCK_Spi6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
311 kCLOCK_Spi7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
312 kCLOCK_Spi14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22),
313 kCLOCK_Dmic0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 24),
314 kCLOCK_OsEventTimer = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 27),
315
316 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0),
317 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1),
318 kCLOCK_HsGpio2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 2),
319 kCLOCK_HsGpio3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 3),
320 kCLOCK_HsGpio4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4),
321 kCLOCK_HsGpio5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5),
322 kCLOCK_HsGpio6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6),
323 kCLOCK_HsGpio7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7),
324 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16),
325 kCLOCK_Dmac0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 23),
326 kCLOCK_Dmac1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 24),
327 kCLOCK_Mu = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 28),
328 kCLOCK_Sema = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 29),
329 kCLOCK_Freqme = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 31),
330
331 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0),
332 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1),
333 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2),
334 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3),
335 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4),
336 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7),
337 kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8),
338 kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 10),
339 kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 16),
340 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 30),
341 kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 31)
342} clock_ip_name_t;
343
344/*! @brief Clock name used to get clock frequency. */
345typedef enum _clock_name
346{
347 kCLOCK_CoreSysClk, /*!< Core clock (aka HCLK) */
348 kCLOCK_BusClk, /*!< Bus clock (AHB/APB clock, aka HCLK) */
349 kCLOCK_MclkClk, /*!< MCLK, to MCLK pin */
350 kCLOCK_ClockOutClk, /*!< CLOCKOUT */
351 kCLOCK_AdcClk, /*!< ADC */
352 kCLOCK_FlexspiClk, /*!< FLEXSPI */
353 kCLOCK_SctClk, /*!< SCT */
354 kCLOCK_Wdt0Clk, /*!< Watchdog0 */
355 kCLOCK_Wdt1Clk, /*!< Watchdog1 */
356 kCLOCK_SystickClk, /*!< Systick */
357 kCLOCK_Sdio0Clk, /*!< SDIO0 */
358 kCLOCK_Sdio1Clk, /*!< SDIO1 */
359 kCLOCK_I3cClk, /*!< I3C */
360 kCLOCK_UsbClk, /*!< USB */
361 kCLOCK_DmicClk, /*!< Digital Mic clock */
362 kCLOCK_DspCpuClk, /*!< DSP clock */
363 kCLOCK_AcmpClk, /*!< Acmp clock */
364 kCLOCK_Flexcomm0Clk, /*!< Flexcomm0Clock */
365 kCLOCK_Flexcomm1Clk, /*!< Flexcomm1Clock */
366 kCLOCK_Flexcomm2Clk, /*!< Flexcomm2Clock */
367 kCLOCK_Flexcomm3Clk, /*!< Flexcomm3Clock */
368 kCLOCK_Flexcomm4Clk, /*!< Flexcomm4Clock */
369 kCLOCK_Flexcomm5Clk, /*!< Flexcomm5Clock */
370 kCLOCK_Flexcomm6Clk, /*!< Flexcomm6Clock */
371 kCLOCK_Flexcomm7Clk, /*!< Flexcomm7Clock */
372 kCLOCK_Flexcomm14Clk, /*!< Flexcomm14Clock */
373 kCLOCK_Flexcomm15Clk, /*!< Flexcomm15Clock */
374} clock_name_t;
375
376/**
377 * PLL PFD clock name
378 */
379typedef enum _clock_pfd
380{
381 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
382 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
383 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
384 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
385} clock_pfd_t;
386
387/*! @brief Clock Mux Switches
388 * The encoding is as follows each connection identified is 32bits wide
389 * starting from LSB upwards
390 *
391 * [12 bits for reg offset, 0 means end of descriptor, 4 bits for choice] [bit 31 define CLKCTL0 or CLKCTL1]*
392 *
393 */
394/* CLKCTL0 SEL */
395#define SYSPLL0CLKSEL_OFFSET 0x200
396#define MAINCLKSELA_OFFSET 0x430
397#define MAINCLKSELB_OFFSET 0x434
398#define FLEXSPIFCLKSEL_OFFSET 0x620
399#define SCTFCLKSEL_OFFSET 0x640
400#define USBHSFCLKSEL_OFFSET 0x660
401#define SDIO0FCLKSEL_OFFSET 0x680
402#define SDIO1FCLKSEL_OFFSET 0x690
403#define ADC0FCLKSEL0_OFFSET 0x6D0
404#define ADC0FCLKSEL1_OFFSET 0x6D4
405#define UTICKFCLKSEL_OFFSET 0x700
406#define WDT0FCLKSEL_OFFSET 0x720
407#define WAKECLK32KHZSEL_OFFSET 0x730
408#define SYSTICKFCLKSEL_OFFSET 0x760
409/* CLKCTL1 SEL */
410#define AUDIOPLL0CLKSEL_OFFSET 0x200
411#define DSPCPUCLKSELA_OFFSET 0x430
412#define DSPCPUCLKSELB_OFFSET 0x434
413#define OSEVENTFCLKSEL_OFFSET 0x480
414#define FC0FCLKSEL_OFFSET 0x508
415#define FC1FCLKSEL_OFFSET 0x528
416#define FC2FCLKSEL_OFFSET 0x548
417#define FC3FCLKSEL_OFFSET 0x568
418#define FC4FCLKSEL_OFFSET 0x588
419#define FC5FCLKSEL_OFFSET 0x5A8
420#define FC6FCLKSEL_OFFSET 0x5C8
421#define FC7FCLKSEL_OFFSET 0x5E8
422#define FC14FCLKSEL_OFFSET 0x6C8
423#define FC15FCLKSEL_OFFSET 0x6E8
424#define DMIC0FCLKSEL_OFFSET 0x700
425#define CT32BIT0FCLKSEL_OFFSET 0x720
426#define CT32BIT1FCLKSEL_OFFSET 0x724
427#define CT32BIT2FCLKSEL_OFFSET 0x728
428#define CT32BIT3FCLKSEL_OFFSET 0x72C
429#define CT32BIT4FCLKSEL_OFFSET 0x730
430#define AUDIOMCLKSEL_OFFSET 0x740
431#define CLKOUTSEL0_OFFSET 0x760
432#define CLKOUTSEL1_OFFSET 0x764
433#define I3C0FCLKSEL_OFFSET 0x780
434#define I3C0FCLKSTCSEL_OFFSET 0x784
435#define WDT1FCLKSEL_OFFSET 0x7A0
436#define ACMP0FCLKSEL_OFFSET 0x7C0
437/* CLKCTL0 DIV */
438#define MAINPLLCLKDIV_OFFSET 0x240
439#define DSPPLLCLKDIV_OFFSET 0x244
440#define AUX0PLLCLKDIV_OFFSET 0x248
441#define AUX1PLLCLKDIV_OFFSET 0x24C
442#define SYSCPUAHBCLKDIV_OFFSET 0x400
443#define PFC0CLKDIV_OFFSET 0x500
444#define PFC1CLKDIV_OFFSET 0x504
445#define FLEXSPIFCLKDIV_OFFSET 0x624
446#define SCTFCLKDIV_OFFSET 0x644
447#define USBHSFCLKDIV_OFFSET 0x664
448#define SDIO0FCLKDIV_OFFSET 0x684
449#define SDIO1FCLKDIV_OFFSET 0x694
450#define ADC0FCLKDIV_OFFSET 0x6D8
451#define WAKECLK32KHZDIV_OFFSET 0x734
452#define SYSTICKFCLKDIV_OFFSET 0x764
453
454/* CLKCTL1 DIV */
455#define AUDIOPLLCLKDIV_OFFSET 0x240
456#define DSPCPUCLKDIV_OFFSET 0x400
457#define DSPMAINRAMCLKDIV_OFFSET 0x404
458#define FRGPLLCLKDIV_OFFSET 0x6FC
459#define DMIC0FCLKDIV_OFFSET 0x704
460#define AUDIOMCLKDIV_OFFSET 0x744
461#define CLKOUTDIV_OFFSET 0x768
462#define I3C0FCLKSTCDIV_OFFSET 0x788
463#define I3C0FCLKSDIV_OFFSET 0x78C
464#define I3C0FCLKDIV_OFFSET 0x790
465#define ACMP0FCLKDIV_OFFSET 0x7C4
466
467#define CLKCTL0_TUPLE_MUXA(reg, choice) (((reg)&0xFFFU) | ((choice) << 12U))
468#define CLKCTL0_TUPLE_MUXB(reg, choice) ((((reg)&0xFFFU) << 16) | ((choice) << 28U))
469#define CLKCTL1_TUPLE_MUXA(reg, choice) (0x80000000U | (((reg)&0xFFFU) | ((choice) << 12U)))
470#define CLKCTL1_TUPLE_MUXB(reg, choice) (0x80000000U | ((((reg)&0xFFFU) << 16) | ((choice) << 28U)))
471#define CLKCTL_TUPLE_REG(base, tuple) ((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFFU)))
472#define CLKCTL_TUPLE_SEL(tuple) (((uint32_t)(tuple) >> 12U) & 0x7U)
473
474typedef enum _clock_attach_id
475{
476 kSFRO_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 0),
477 kXTALIN_CLK_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 1),
478 kFFRO_DIV2_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 2),
479 kNONE_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 7),
480
481 kSFRO_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 0),
482 kXTALIN_CLK_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 1),
483 kFFRO_DIV2_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 2),
484 kNONE_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 7),
485
486 kFFRO_DIV4_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 0) | CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0),
487 kXTALIN_CLK_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 1) | CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0),
488 kLPOSC_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 2) | CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0),
489 kFFRO_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 3) | CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0),
490 kSFRO_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 1),
491 kMAIN_PLL_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 2),
492 kOSC32K_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 3),
493
494 kFFRO_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 0) | CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0),
495 kXTALIN_CLK_to_DSP_MAIN_CLK =
496 CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 1) | CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0),
497 kLPOSC_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 2) | CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0),
498 kSFRO_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 3) | CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0),
499 kMAIN_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 1),
500 kDSP_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 2),
501 kOSC32K_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 3),
502
503 kSFRO_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 0) | CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0),
504 kXTALIN_CLK_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 1) | CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0),
505 kLPOSC_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 2) | CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0),
506 kFFRO_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 3) | CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0),
507 kMAIN_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 1),
508 kAUX0_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 3),
509 kAUX1_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 5),
510
511 kSFRO_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 0) | CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0),
512 kXTALIN_CLK_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 1) | CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0),
513 kLPOSC_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 2) | CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0),
514 kFFRO_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 3) | CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0),
515 kMAIN_CLK_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 4) | CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0),
516 kDSP_MAIN_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 6) | CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0),
517 kMAIN_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 1),
518 kAUX0_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 2),
519 kDSP_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 3),
520 kAUX1_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 4),
521 kAUDIO_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 5),
522 kOSC32K_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 6),
523 kNONE_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 7),
524
525 kMAIN_CLK_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 0),
526 kFFRO_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 1),
527 kNONE_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 7),
528
529 kI3C_CLK_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 0),
530 kLPOSC_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 1),
531 kNONE_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 7),
532
533 kLPOSC_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 0),
534 kOSC32K_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 1),
535 kHCLK_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 2),
536 kNONE_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 7),
537
538 kMAIN_CLK_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 0),
539 kMAIN_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 1),
540 kAUX0_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 2),
541 kFFRO_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 3),
542 kAUX1_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 4),
543 kNONE_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 7),
544
545 kMAIN_CLK_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 0),
546 kMAIN_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 1),
547 kAUX0_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 2),
548 kFFRO_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 3),
549 kAUX1_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 4),
550 kAUDIO_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 5),
551 kNONE_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 7),
552
553 kLPOSC_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 0),
554 kNONE_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 7),
555
556 kLPOSC_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 0),
557 kNONE_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 7),
558
559 kLPOSC_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 0),
560 kNONE_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 7),
561
562 kOSC32K_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 0),
563 kLPOSC_DIV32_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 1),
564 kNONE_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 7),
565
566 kMAIN_CLK_DIV_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 0),
567 kLPOSC_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 1),
568 kOSC32K_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 2),
569 kSFRO_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 3),
570 kNONE_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 7),
571
572 kMAIN_CLK_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 0),
573 kMAIN_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 1),
574 kAUX0_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 2),
575 kFFRO_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 3),
576 kAUX1_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 4),
577 kNONE_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 7),
578
579 kMAIN_CLK_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 0),
580 kMAIN_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 1),
581 kAUX0_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 2),
582 kFFRO_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 3),
583 kAUX1_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 4),
584 kNONE_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 7),
585
586 kXTALIN_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 0),
587 kMAIN_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 1),
588 kNONE_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 7),
589
590 kFFRO_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 0),
591 kAUDIO_PLL_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 1),
592 kNONE_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 7),
593
594 kSFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 0),
595 kFFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 1),
596 kAUDIO_PLL_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 2),
597 kMASTER_CLK_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 3),
598 kLPOSC_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 4),
599 k32K_WAKE_CLK_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 5),
600 kNONE_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 7),
601
602 kMAIN_CLK_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 0),
603 kSFRO_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 1),
604 kFFRO_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 2),
605 kAUX0_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 3),
606 kAUX1_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 4),
607 kNONE_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 7),
608
609 kSFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 0),
610 kFFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 1),
611 kAUDIO_PLL_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 2),
612 kMASTER_CLK_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 3),
613 kFRG_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 4),
614 kNONE_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 7),
615
616 kSFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 0),
617 kFFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 1),
618 kAUDIO_PLL_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 2),
619 kMASTER_CLK_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 3),
620 kFRG_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 4),
621 kNONE_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 7),
622
623 kSFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 0),
624 kFFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 1),
625 kAUDIO_PLL_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 2),
626 kMASTER_CLK_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 3),
627 kFRG_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 4),
628 kNONE_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 7),
629
630 kSFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 0),
631 kFFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 1),
632 kAUDIO_PLL_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 2),
633 kMASTER_CLK_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 3),
634 kFRG_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 4),
635 kNONE_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 7),
636
637 kSFRO_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 0),
638 kFFRO_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 1),
639 kAUDIO_PLL_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 2),
640 kMASTER_CLK_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 3),
641 kFRG_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 4),
642 kNONE_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 7),
643
644 kSFRO_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 0),
645 kFFRO_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 1),
646 kAUDIO_PLL_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 2),
647 kMASTER_CLK_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 3),
648 kFRG_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 4),
649 kNONE_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 7),
650
651 kSFRO_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 0),
652 kFFRO_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 1),
653 kAUDIO_PLL_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 2),
654 kMASTER_CLK_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 3),
655 kFRG_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 4),
656 kNONE_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 7),
657
658 kSFRO_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 0),
659 kFFRO_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 1),
660 kAUDIO_PLL_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 2),
661 kMASTER_CLK_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 3),
662 kFRG_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 4),
663 kNONE_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 7),
664
665 kSFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 0),
666 kFFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 1),
667 kAUDIO_PLL_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 2),
668 kMASTER_CLK_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 3),
669 kFRG_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 4),
670 kNONE_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 7),
671
672 kSFRO_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 0),
673 kFFRO_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 1),
674 kAUDIO_PLL_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 2),
675 kMASTER_CLK_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 3),
676 kFRG_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 4),
677 kNONE_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 7),
678
679 kMAIN_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 0),
680 kSFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 1),
681 kFFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 2),
682 kAUDIO_PLL_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 3),
683 kMASTER_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 4),
684 kLPOSC_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 5),
685 kNONE_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 7),
686
687 kMAIN_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 0),
688 kSFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 1),
689 kFFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 2),
690 kAUDIO_PLL_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 3),
691 kMASTER_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 4),
692 kLPOSC_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 5),
693 kNONE_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 7),
694
695 kMAIN_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 0),
696 kSFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 1),
697 kFFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 2),
698 kAUDIO_PLL_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 3),
699 kMASTER_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 4),
700 kLPOSC_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 5),
701 kNONE_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 7),
702
703 kMAIN_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 0),
704 kSFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 1),
705 kFFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 2),
706 kAUDIO_PLL_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 3),
707 kMASTER_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 4),
708 kLPOSC_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 5),
709 kNONE_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 7),
710
711 kMAIN_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 0),
712 kSFRO_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 1),
713 kFFRO_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 2),
714 kAUDIO_PLL_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 3),
715 kMASTER_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 4),
716 kLPOSC_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 5),
717 kNONE_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 7),
718
719} clock_attach_id_t;
720
721/* Clock dividers */
722typedef enum _clock_div_name
723{
724 kCLOCK_DivSysCpuAhbClk = CLKCTL0_TUPLE_MUXA(SYSCPUAHBCLKDIV_OFFSET, 0),
725 kCLOCK_DivMainPllClk = CLKCTL0_TUPLE_MUXA(MAINPLLCLKDIV_OFFSET, 0),
726 kCLOCK_DivDspPllClk = CLKCTL0_TUPLE_MUXA(DSPPLLCLKDIV_OFFSET, 0),
727 kCLOCK_DivAux0PllClk = CLKCTL0_TUPLE_MUXA(AUX0PLLCLKDIV_OFFSET, 0),
728 kCLOCK_DivAux1PllClk = CLKCTL0_TUPLE_MUXA(AUX1PLLCLKDIV_OFFSET, 0),
729 kCLOCK_DivPfc0Clk = CLKCTL0_TUPLE_MUXA(PFC0CLKDIV_OFFSET, 0),
730 kCLOCK_DivPfc1Clk = CLKCTL0_TUPLE_MUXA(PFC1CLKDIV_OFFSET, 0),
731 kCLOCK_DivAdcClk = CLKCTL0_TUPLE_MUXA(ADC0FCLKDIV_OFFSET, 0),
732 kCLOCK_DivFlexspiClk = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKDIV_OFFSET, 0),
733 kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0),
734 kCLOCK_DivSdio0Clk = CLKCTL0_TUPLE_MUXA(SDIO0FCLKDIV_OFFSET, 0),
735 kCLOCK_DivSdio1Clk = CLKCTL0_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0),
736 kCLOCK_DivSystickClk = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKDIV_OFFSET, 0),
737 kCLOCK_DivUsbHsFclk = CLKCTL0_TUPLE_MUXA(USBHSFCLKDIV_OFFSET, 0),
738 kCLOCK_DivAudioPllClk = CLKCTL1_TUPLE_MUXA(AUDIOPLLCLKDIV_OFFSET, 0),
739 kCLOCK_DivAcmpClk = CLKCTL1_TUPLE_MUXA(ACMP0FCLKDIV_OFFSET, 0),
740 kCLOCK_DivClockOut = CLKCTL1_TUPLE_MUXA(CLKOUTDIV_OFFSET, 0),
741 kCLOCK_DivDmicClk = CLKCTL1_TUPLE_MUXA(DMIC0FCLKDIV_OFFSET, 0),
742 kCLOCK_DivDspCpuClk = CLKCTL1_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0),
743 kCLOCK_DivDspRamClk = CLKCTL1_TUPLE_MUXA(DSPMAINRAMCLKDIV_OFFSET, 0),
744 kCLOCK_DivMclkClk = CLKCTL1_TUPLE_MUXA(AUDIOMCLKDIV_OFFSET, 0),
745 kCLOCK_DivPllFrgClk = CLKCTL1_TUPLE_MUXA(FRGPLLCLKDIV_OFFSET, 0),
746 kCLOCK_DivI3cClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKDIV_OFFSET, 0),
747 kCLOCK_DivI3cTcClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCDIV_OFFSET, 0),
748 kCLOCK_DivI3cSlowClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKSDIV_OFFSET, 0),
749} clock_div_name_t;
750
751/*! @brief FFRO frequence configuration */
752typedef enum _clock_ffro_freq
753{
754 kCLOCK_Ffro48M, /*!< 48MHz FFRO clock. */
755 kCLOCK_Ffro60M, /*!< 60MHz FFRO clock. */
756} clock_ffro_freq_t;
757/*! @brief SysPLL Reference Input Clock Source */
758typedef enum _sys_pll_src
759{
760 kCLOCK_SysPllSFroClk = 0, /*!< 16MHz FRO clock */
761 kCLOCK_SysPllXtalIn = 1, /*!< OSC clock */
762 kCLOCK_SysPllFFroDiv2 = 2, /*!< FRO48/60 div2 clock */
763 kCLOCK_SysPllNone = 7 /*!< Gated to reduce power */
764} sys_pll_src_t;
765
766/*! @brief SysPLL Multiplication Factor */
767typedef enum _sys_pll_mult
768{
769 kCLOCK_SysPllMult16 = 0, /*!< Divide by 16 */
770 kCLOCK_SysPllMult17, /*!< Divide by 17 */
771 kCLOCK_SysPllMult18, /*!< Divide by 18 */
772 kCLOCK_SysPllMult19, /*!< Divide by 19 */
773 kCLOCK_SysPllMult20, /*!< Divide by 20 */
774 kCLOCK_SysPllMult21, /*!< Divide by 21 */
775 kCLOCK_SysPllMult22, /*!< Divide by 22 */
776} sys_pll_mult_t;
777
778/*! @brief PLL configuration for SYSPLL */
779typedef struct _clock_sys_pll_config
780{
781 sys_pll_src_t sys_pll_src; /*!< Reference Input Clock Source */
782 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider. */
783 uint32_t denominator; /*!< 30 bit numerator of fractional loop divider. */
784 sys_pll_mult_t sys_pll_mult; /*!< Multiplication Factor */
785} clock_sys_pll_config_t;
786
787/*! @brief AudioPll Reference Input Clock Source */
788typedef enum _audio_pll_src
789{
790 kCLOCK_AudioPllSFroClk = 0, /*!< 16MHz FRO clock */
791 kCLOCK_AudioPllXtalIn = 1, /*!< OSC clock */
792 kCLOCK_AudioPllFFroDiv2 = 2, /*!< FRO48/60 div2 clock */
793 kCLOCK_AudioPllNone = 7 /*!< Gated to reduce power */
794} audio_pll_src_t;
795
796/*! @brief AudioPll Multiplication Factor */
797typedef enum _audio_pll_mult
798{
799 kCLOCK_AudioPllMult16 = 0, /*!< Divide by 16 */
800 kCLOCK_AudioPllMult17, /*!< Divide by 17 */
801 kCLOCK_AudioPllMult18, /*!< Divide by 18 */
802 kCLOCK_AudioPllMult19, /*!< Divide by 19 */
803 kCLOCK_AudioPllMult20, /*!< Divide by 20 */
804 kCLOCK_AudioPllMult21, /*!< Divide by 21 */
805 kCLOCK_AudioPllMult22, /*!< Divide by 22 */
806} audio_pll_mult_t;
807
808/*! @brief PLL configuration for SYSPLL */
809typedef struct _clock_audio_pll_config
810{
811 audio_pll_src_t audio_pll_src; /*!< Reference Input Clock Source */
812 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider. */
813 uint32_t denominator; /*!< 30 bit numerator of fractional loop divider. */
814 audio_pll_mult_t audio_pll_mult; /*!< Multiplication Factor */
815} clock_audio_pll_config_t;
816/*! @brief PLL configuration for FRG */
817typedef struct _clock_frg_clk_config
818{
819 uint8_t num; /*!< FRG clock */
820 enum
821 {
822 kCLOCK_FrgMainClk = 0, /*!< Main System clock */
823 kCLOCK_FrgPllDiv, /*!< Main pll clock divider*/
824 kCLOCK_FrgSFro, /*!< 16MHz FRO */
825 kCLOCK_FrgFFro, /*!< FRO48/60 */
826 } sfg_clock_src;
827 uint8_t divider; /*!< Denominator of the fractional divider. */
828 uint8_t mult; /*!< Numerator of the fractional divider. */
829} clock_frg_clk_config_t;
830
831/*******************************************************************************
832 * API
833 ******************************************************************************/
834
835#if defined(__cplusplus)
836extern "C" {
837#endif /* __cplusplus */
838
839static inline void CLOCK_EnableClock(clock_ip_name_t clk)
840{
841 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
842
843 switch (index)
844 {
845 case CLK_CTL0_PSCCTL0:
846 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
847 break;
848 case CLK_CTL0_PSCCTL1:
849 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
850 break;
851 case CLK_CTL0_PSCCTL2:
852 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
853 break;
854 case CLK_CTL1_PSCCTL0:
855 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
856 break;
857 case CLK_CTL1_PSCCTL1:
858 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
859 break;
860 case CLK_CTL1_PSCCTL2:
861 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
862 break;
863 default:
864 assert(false);
865 break;
866 }
867}
868
869static inline void CLOCK_DisableClock(clock_ip_name_t clk)
870{
871 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
872 switch (index)
873 {
874 case CLK_CTL0_PSCCTL0:
875 CLKCTL0->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
876 break;
877 case CLK_CTL0_PSCCTL1:
878 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
879 break;
880 case CLK_CTL0_PSCCTL2:
881 CLKCTL0->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
882 break;
883 case CLK_CTL1_PSCCTL0:
884 CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
885 break;
886 case CLK_CTL1_PSCCTL1:
887 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
888 break;
889 case CLK_CTL1_PSCCTL2:
890 CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
891 break;
892 default:
893 assert(false);
894 break;
895 }
896}
897/**
898 * @brief Configure the clock selection muxes.
899 * @param connection : Clock to be configured.
900 * @return Nothing
901 */
902void CLOCK_AttachClk(clock_attach_id_t connection);
903/**
904 * @brief Setup peripheral clock dividers.
905 * @param div_name : Clock divider name
906 * @param divider : Value to be divided.
907 * @return Nothing
908 */
909void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divider);
910/*! @brief Return Frequency of selected clock
911 * @return Frequency of selected clock
912 */
913uint32_t CLOCK_GetFreq(clock_name_t clockName);
914
915/*! @brief Return Input frequency for the Fractional baud rate generator
916 * @return Input Frequency for FRG
917 */
918uint32_t CLOCK_GetFRGClock(uint32_t id);
919
920/*! @brief Set output of the Fractional baud rate generator
921 * @param config : Configuration to set to FRGn clock.
922 */
923void CLOCK_SetFRGClock(const clock_frg_clk_config_t *config);
924
925/*! @brief Return Frequency of FRO 16MHz
926 * @return Frequency of FRO 12MHz
927 */
928static inline uint32_t CLOCK_GetSFroFreq(void)
929{
930 return CLK_FRO_16MHZ;
931}
932/*! @brief Return Frequency of SYSPLL
933 * @return Frequency of SYSPLL
934 */
935uint32_t CLOCK_GetSysPllFreq(void);
936/*! @brief Get current output frequency of specific System PLL PFD.
937 * @param pfd : pfd name to get frequency.
938 * @return Frequency of SYSPLL PFD.
939 */
940uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
941/*! @brief Return Frequency of AUDIO PLL
942 * @return Frequency of AUDIO PLL
943 */
944uint32_t CLOCK_GetAudioPllFreq(void);
945/*! @brief Get current output frequency of specific Audio PLL PFD.
946 * @param pfd : pfd name to get frequency.
947 * @return Frequency of AUDIO PLL PFD.
948 */
949uint32_t CLOCK_GetAudioPfdFreq(clock_pfd_t pfd);
950/*! @brief Return Frequency of High-Freq output of FRO
951 * @return Frequency of High-Freq output of FRO
952 */
953uint32_t CLOCK_GetFFroFreq(void);
954/*! @brief Return Frequency of main clk
955 * @return Frequency of main clk
956 */
957uint32_t CLOCK_GetMainClkFreq(void);
958/*! @brief Return Frequency of DSP main clk
959 * @return Frequency of DSP main clk
960 */
961uint32_t CLOCK_GetDspMainClkFreq(void);
962/*! @brief Return Frequency of ACMP clk
963 * @return Frequency of ACMP clk
964 */
965uint32_t CLOCK_GetAcmpClkFreq(void);
966/*! @brief Return Frequency of DMIC clk
967 * @return Frequency of DMIC clk
968 */
969uint32_t CLOCK_GetDmicClkFreq(void);
970/*! @brief Return Frequency of USB clk
971 * @return Frequency of USB clk
972 */
973uint32_t CLOCK_GetUsbClkFreq(void);
974/*! @brief Return Frequency of SDIO clk
975 * @param id : SDIO index to get frequency.
976 * @return Frequency of SDIO clk
977 */
978uint32_t CLOCK_GetSdioClkFreq(uint32_t id);
979/*! @brief Return Frequency of I3C clk
980 * @return Frequency of I3C clk
981 */
982uint32_t CLOCK_GetI3cClkFreq(void);
983/*! @brief Return Frequency of systick clk
984 * @return Frequency of systick clk
985 */
986uint32_t CLOCK_GetSystickClkFreq(void);
987/*! @brief Return Frequency of WDT clk
988 * @param id : WDT index to get frequency.
989 * @return Frequency of WDT clk
990 */
991uint32_t CLOCK_GetWdtClkFreq(uint32_t id);
992/*! @brief Return Frequency of mclk
993 * @return Frequency of mclk clk
994 */
995uint32_t CLOCK_GetMclkClkFreq(void);
996/*! @brief Return Frequency of sct
997 * @return Frequency of sct clk
998 */
999uint32_t CLOCK_GetSctClkFreq(void);
1000/*! @brief Enable/Disable sys osc clock from external crystal clock.
1001 * @param enable : true to enable system osc clock, false to bypass system osc.
1002 * @param enableLowPower : true to enable low power mode, false to enable high gain mode.
1003 * @param delay_us : Delay time after OSC power up.
1004 */
1005void CLOCK_EnableSysOscClk(bool enable, bool enableLowPower, uint32_t delay_us);
1006/*! @brief Return Frequency of sys osc Clock
1007 * @return Frequency of sys osc Clock. Or CLK_IN pin frequency.
1008 */
1009static inline uint32_t CLOCK_GetXtalInClkFreq(void)
1010{
1011 return (CLKCTL0->SYSOSCBYPASS == 0U) ? g_xtalFreq : ((CLKCTL0->SYSOSCBYPASS == 1U) ? g_clkinFreq : 0U);
1012}
1013
1014/*! @brief Return Frequency of MCLK Input Clock
1015 * @return Frequency of MCLK input Clock.
1016 */
1017static inline uint32_t CLOCK_GetMclkInClkFreq(void)
1018{
1019 return g_mclkFreq;
1020}
1021
1022/*! @brief Return Frequency of Lower power osc
1023 * @return Frequency of LPOSC
1024 */
1025static inline uint32_t CLOCK_GetLpOscFreq(void)
1026{
1027 return CLK_LPOSC_1MHZ;
1028}
1029/*! @brief Return Frequency of 32kHz osc
1030 * @return Frequency of 32kHz osc
1031 */
1032static inline uint32_t CLOCK_GetOsc32KFreq(void)
1033{
1034 return ((CLKCTL0->OSC32KHZCTL0 & CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK) != 0UL) ? CLK_RTC_32K_CLK : 0U;
1035}
1036/*! @brief Enables and disables 32kHz osc
1037 * @param enable : true to enable 32k osc clock, false to disable clock
1038 */
1039static inline void CLOCK_EnableOsc32K(bool enable)
1040{
1041 if (enable)
1042 {
1043 CLKCTL0->OSC32KHZCTL0 |= CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK;
1044 }
1045 else
1046 {
1047 CLKCTL0->OSC32KHZCTL0 &= ~CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK;
1048 }
1049}
1050
1051/*! @brief Return Frequency of 32khz wake clk
1052 * @return Frequency of 32kHz wake clk
1053 */
1054static inline uint32_t CLOCK_GetWakeClk32KFreq(void)
1055{
1056 return ((CLKCTL0->WAKECLK32KHZSEL & CLKCTL0_WAKECLK32KHZSEL_SEL_MASK) != 0UL) ?
1057 CLOCK_GetLpOscFreq() / ((CLKCTL0->WAKECLK32KHZDIV & 0xffU) + 1U) :
1058 CLOCK_GetOsc32KFreq();
1059}
1060/*!
1061 * @brief Set the XTALIN (system OSC) frequency based on board setting.
1062 *
1063 * @param freq : The XTAL input clock frequency in Hz.
1064 */
1065static inline void CLOCK_SetXtalFreq(uint32_t freq)
1066{
1067 g_xtalFreq = freq;
1068}
1069/*!
1070 * @brief Set the CLKIN (CLKIN pin) frequency based on board setting.
1071 *
1072 * @param freq : The CLK_IN pin input clock frequency in Hz.
1073 */
1074static inline void CLOCK_SetClkinFreq(uint32_t freq)
1075{
1076 g_clkinFreq = freq;
1077}
1078/*!
1079 * @brief Set the MCLK in (mclk_in) clock frequency based on board setting.
1080 *
1081 * @param freq : The MCLK input clock frequency in Hz.
1082 */
1083static inline void CLOCK_SetMclkFreq(uint32_t freq)
1084{
1085 g_mclkFreq = freq;
1086}
1087
1088/*! @brief Return Frequency of Flexcomm functional Clock
1089 * @param id : flexcomm index to get frequency.
1090 * @return Frequency of Flexcomm functional Clock
1091 */
1092uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
1093/*! @brief Return Frequency of Ctimer Clock
1094 * @param id : ctimer index to get frequency.
1095 * @return Frequency of Ctimer Clock
1096 */
1097uint32_t CLOCK_GetCtimerClkFreq(uint32_t id);
1098/*! @brief Return Frequency of ClockOut
1099 * @return Frequency of ClockOut
1100 */
1101uint32_t CLOCK_GetClockOutClkFreq(void);
1102/*! @brief Return Frequency of Adc Clock
1103 * @return Frequency of Adc Clock.
1104 */
1105uint32_t CLOCK_GetAdcClkFreq(void);
1106/*! @brief Return Frequency of Flexspi Clock
1107 * @return Frequency of Flexspi.
1108 */
1109uint32_t CLOCK_GetFlexspiClkFreq(void);
1110#ifndef __XCC__
1111/**
1112 * brief Enable FFRO 48M/60M clock.
1113 * param ffroFreq : target fro frequency.
1114 * return Nothing
1115 */
1116void CLOCK_EnableFfroClk(clock_ffro_freq_t ffroFreq);
1117/**
1118 * brief Enable SFRO clock.
1119 * param Nothing
1120 * return Nothing
1121 */
1122void CLOCK_EnableSfroClk(void);
1123/*! @brief Initialize the System PLL.
1124 * @param config : Configuration to set to PLL.
1125 */
1126#endif /* __XCC__ */
1127
1128void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1129/*! brief Deinit the System PLL.
1130 * param none.
1131 */
1132static inline void CLOCK_DeinitSysPll(void)
1133{
1134 /* Set System PLL Reset & HOLDRINGOFF_ENA */
1135 CLKCTL0->SYSPLL0CTL0 |= CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL0_SYSPLL0CTL0_RESET_MASK;
1136 /* Power down System PLL*/
1137 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK;
1138}
1139/*! @brief Initialize the System PLL PFD.
1140 * @param pfd : Which PFD clock to enable.
1141 * @param divider : The PFD divider value.
1142 * @note It is recommended that PFD settings are kept between 12-35.
1143 */
1144void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t divider);
1145/*! brief Disable the audio PLL PFD.
1146 * param pfd : Which PFD clock to disable.
1147 */
1148static inline void CLOCK_DeinitSysPfd(clock_pfd_t pfd)
1149{
1150 CLKCTL0->SYSPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd));
1151}
1152/*! @brief Initialize the audio PLL.
1153 * @param config : Configuration to set to PLL.
1154 */
1155void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1156/*! brief Deinit the Audio PLL.
1157 * param none.
1158 */
1159static inline void CLOCK_DeinitAudioPll(void)
1160{
1161 /* Set Audio PLL Reset & HOLDRINGOFF_ENA */
1162 CLKCTL1->AUDIOPLL0CTL0 |= CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL1_AUDIOPLL0CTL0_RESET_MASK;
1163 /* Power down Audio PLL */
1164 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK;
1165}
1166/*! @brief Initialize the audio PLL PFD.
1167 * @param pfd : Which PFD clock to enable.
1168 * @param divider : The PFD divider value.
1169 * @note It is recommended that PFD settings are kept between 12-35.
1170 */
1171void CLOCK_InitAudioPfd(clock_pfd_t pfd, uint8_t divider);
1172/*! brief Disable the audio PLL PFD.
1173 * param pfd : Which PFD clock to disable.
1174 */
1175static inline void CLOCK_DeinitAudioPfd(uint32_t pfd)
1176{
1177 CLKCTL1->AUDIOPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd));
1178}
1179/*! @brief Enable USB HS device PLL clock.
1180 *
1181 * This function enables USB HS device PLL clock.
1182 */
1183void CLOCK_EnableUsbhsDeviceClock(void);
1184/*! @brief Enable USB HS host PLL clock.
1185 *
1186 * This function enables USB HS host PLL clock.
1187 */
1188void CLOCK_EnableUsbhsHostClock(void);
1189/*! brief Enable USB hs0PhyPll clock.
1190 *
1191 * param src USB HS clock source.
1192 * param freq The frequency specified by src.
1193 * retval true The clock is set successfully.
1194 * retval false The clock source is invalid to get proper USB HS clock.
1195 */
1196bool CLOCK_EnableUsbHs0PhyPllClock(clock_attach_id_t src, uint32_t freq);
1197#if defined(__cplusplus)
1198}
1199#endif /* __cplusplus */
1200
1201/*! @} */
1202
1203#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 20:18:35 +0100