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Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT633S/drivers/fsl_inputmux_connections.h')
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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT633S/drivers/fsl_inputmux_connections.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT633S/drivers/fsl_inputmux_connections.h
new file mode 100644
index 000000000..8578ed239
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT633S/drivers/fsl_inputmux_connections.h
@@ -0,0 +1,540 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2019, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_INPUTMUX_CONNECTIONS_
10#define _FSL_INPUTMUX_CONNECTIONS_
11
12/*******************************************************************************
13 * Definitions
14 ******************************************************************************/
15/* Component ID definition, used by tools. */
16#ifndef FSL_COMPONENT_ID
17#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections"
18#endif
19
20/*!
21 * @addtogroup inputmux_driver
22 * @{
23 */
24
25/*! @brief Periphinmux IDs */
26#define SCT0_PMUX_ID 0x00U
27#define SHSGPIO_PMUX_ID 0x80U
28#define PINTSEL_PMUX_ID 0x100U
29#define DSP_INT_PMUX_ID 0x140U
30#define DMA0_ITRIG_PMUX_ID 0x200U
31#define DMA0_OTRIG_PMUX_ID 0x300U
32#define DMA1_ITRIG_PMUX_ID 0x400U
33#define DMA1_OTRIG_PMUX_ID 0x500U
34#define CT32BIT0_CAP_PMUX_ID 0x600U
35#define CT32BIT1_CAP_PMUX_ID 0x610U
36#define CT32BIT2_CAP_PMUX_ID 0x620U
37#define CT32BIT3_CAP_PMUX_ID 0x630U
38#define CT32BIT4_CAP_PMUX_ID 0x640U
39#define FREQMEAS_PMUX_ID 0x700U
40#define DMA0_REQ_ENA0_ID 0x740U
41#define DMA1_REQ_ENA0_ID 0x760U
42#define DMA0_ITRIG_EN0_ID 0x780U
43#define DMA1_ITRIG_EN0_ID 0x7A0U
44#define ENA_SHIFT 8U
45#define PMUX_SHIFT 20U
46
47/*! @brief INPUTMUX connections type */
48typedef enum _inputmux_connection_t
49{
50 /*!< SCT INMUX. */
51 kINPUTMUX_Sct0PinInp0ToSct0 = 0U + (SCT0_PMUX_ID << PMUX_SHIFT),
52 kINPUTMUX_Sct0PinInp1ToSct0 = 1U + (SCT0_PMUX_ID << PMUX_SHIFT),
53 kINPUTMUX_Sct0PinInp2ToSct0 = 2U + (SCT0_PMUX_ID << PMUX_SHIFT),
54 kINPUTMUX_Sct0PinInp3ToSct0 = 3U + (SCT0_PMUX_ID << PMUX_SHIFT),
55 kINPUTMUX_Sct0PinInp4ToSct0 = 4U + (SCT0_PMUX_ID << PMUX_SHIFT),
56 kINPUTMUX_Sct0PinInp5ToSct0 = 5U + (SCT0_PMUX_ID << PMUX_SHIFT),
57 kINPUTMUX_Sct0PinInp6ToSct0 = 6U + (SCT0_PMUX_ID << PMUX_SHIFT),
58 kINPUTMUX_Sct0PinInp7ToSct0 = 7U + (SCT0_PMUX_ID << PMUX_SHIFT),
59 kINPUTMUX_Ctimer0Mat0ToSct0 = 8U + (SCT0_PMUX_ID << PMUX_SHIFT),
60 kINPUTMUX_Ctimer1Mat0ToSct0 = 9U + (SCT0_PMUX_ID << PMUX_SHIFT),
61 kINPUTMUX_Ctimer2Mat0ToSct0 = 10U + (SCT0_PMUX_ID << PMUX_SHIFT),
62 kINPUTMUX_Ctimer3Mat0ToSct0 = 11U + (SCT0_PMUX_ID << PMUX_SHIFT),
63 kINPUTMUX_Ctimer4Mat0ToSct0 = 12U + (SCT0_PMUX_ID << PMUX_SHIFT),
64 kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_PMUX_ID << PMUX_SHIFT),
65 kINPUTMUX_GpioIntBmatchToSct0 = 14U + (SCT0_PMUX_ID << PMUX_SHIFT),
66 kINPUTMUX_Usb1FrameToggleToSct0 = 15U + (SCT0_PMUX_ID << PMUX_SHIFT),
67 kINPUTMUX_Cmp0OutToSct0 = 16U + (SCT0_PMUX_ID << PMUX_SHIFT),
68 kINPUTMUX_SharedI2s0SclkToSct0 = 17U + (SCT0_PMUX_ID << PMUX_SHIFT),
69 kINPUTMUX_SharedI2s1SclkToSct0 = 18U + (SCT0_PMUX_ID << PMUX_SHIFT),
70 kINPUTMUX_SharedI2s0WsToSct0 = 19U + (SCT0_PMUX_ID << PMUX_SHIFT),
71 kINPUTMUX_SharedI2s1WsToSct0 = 20U + (SCT0_PMUX_ID << PMUX_SHIFT),
72 kINPUTMUX_MclkToSct0 = 21U + (SCT0_PMUX_ID << PMUX_SHIFT),
73 kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_PMUX_ID << PMUX_SHIFT),
74 kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_PMUX_ID << PMUX_SHIFT),
75
76 /*!< Pin Interrupt. */
77 kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
78 kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
79 kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
80 kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
81 kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
82 kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
83 kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
84 kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
85 kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
86 kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
87 kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
88 kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
89 kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
90 kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
91 kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
92 kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
93 kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
94 kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
95 kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
96 kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
97 kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
98 kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
99 kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
100 kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
101 kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
102 kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
103 kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
104 kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
105 kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
106 kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
107 kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
108 kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
109 kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
110 kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
111 kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
112 kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
113 kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
114 kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
115 kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
116 kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
117 kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
118 kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
119 kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
120 kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
121 kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
122 kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
123 kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
124 kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
125 kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
126 kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
127 kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
128 kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
129 kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
130 kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
131 kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
132 kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
133 kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
134 kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
135 kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
136 kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
137 kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
138 kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
139 kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
140 kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
141
142 /*!< DSP Interrupt. */
143 kINPUTMUX_Flexcomm0ToDspInterrupt = 0U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
144 kINPUTMUX_Flexcomm1ToDspInterrupt = 1U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
145 kINPUTMUX_Flexcomm2ToDspInterrupt = 2U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
146 kINPUTMUX_Flexcomm3ToDspInterrupt = 3U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
147 kINPUTMUX_Flexcomm4ToDspInterrupt = 4U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
148 kINPUTMUX_Flexcomm5ToDspInterrupt = 5U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
149 kINPUTMUX_Flexcomm6ToDspInterrupt = 6U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
150 kINPUTMUX_Flexcomm7ToDspInterrupt = 7U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
151 kINPUTMUX_GpioInt0ToDspInterrupt = 8U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
152 kINPUTMUX_GpioInt1ToDspInterrupt = 9U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
153 kINPUTMUX_GpioInt2ToDspInterrupt = 10U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
154 kINPUTMUX_GpioInt3ToDspInterrupt = 11U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
155 kINPUTMUX_GpioInt4ToDspInterrupt = 12U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
156 kINPUTMUX_GpioInt5ToDspInterrupt = 13U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
157 kINPUTMUX_GpioInt6ToDspInterrupt = 14U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
158 kINPUTMUX_GpioInt7ToDspInterrupt = 15U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
159 kINPUTMUX_NsHsGpioInt0ToDspInterrupt = 16U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
160 kINPUTMUX_NsHsGpioInt1ToDspInterrupt = 17U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
161 kINPUTMUX_Wdt1ToDspInterrupt = 18U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
162 kINPUTMUX_Dmac0ToDspInterrupt = 19U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
163 kINPUTMUX_Dmac1ToDspInterrupt = 20U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
164 kINPUTMUX_MuBToDspInterrupt = 21U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
165 kINPUTMUX_Utick0ToDspInterrupt = 22U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
166 kINPUTMUX_Mrt0ToDspInterrupt = 23U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
167 kINPUTMUX_OsEventTimerToDspInterrupt = 24U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
168 kINPUTMUX_Ctimer0ToDspInterrupt = 25U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
169 kINPUTMUX_Ctimer1ToDspInterrupt = 26U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
170 kINPUTMUX_Ctimer2ToDspInterrupt = 27U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
171 kINPUTMUX_Ctimer3ToDspInterrupt = 28U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
172 kINPUTMUX_Ctimer4ToDspInterrupt = 29U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
173 kINPUTMUX_RtcToDspInterrupt = 30U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
174 kINPUTMUX_I3c0ToDspInterrupt = 31U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
175 kINPUTMUX_Dmic0ToDspInterrupt = 32U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
176 kINPUTMUX_Hwvad0ToDspInterrupt = 33U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
177 kINPUTMUX_FlexspiToDspInterrupt = 34U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
178
179 /*!< Frequency measure. */
180 kINPUTMUX_XtalinToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
181 kINPUTMUX_SfroToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
182 kINPUTMUX_FfroToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
183 kINPUTMUX_LposcToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
184 kINPUTMUX_Rtc32KhzOscToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
185 kINPUTMUX_MainSysClkToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
186 kINPUTMUX_FreqmeGpioClkToFreqmeas = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
187
188 /*!< CTmier0 capture input mux. */
189 kINPUTMUX_CtInp0ToTimer0CaptureChannels = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
190 kINPUTMUX_CtInp1ToTimer0CaptureChannels = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
191 kINPUTMUX_CtInp2ToTimer0CaptureChannels = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
192 kINPUTMUX_CtInp3ToTimer0CaptureChannels = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
193 kINPUTMUX_CtInp4ToTimer0CaptureChannels = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
194 kINPUTMUX_CtInp5ToTimer0CaptureChannels = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
195 kINPUTMUX_CtInp6ToTimer0CaptureChannels = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
196 kINPUTMUX_CtInp7ToTimer0CaptureChannels = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
197 kINPUTMUX_CtInp8ToTimer0CaptureChannels = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
198 kINPUTMUX_CtInp9ToTimer0CaptureChannels = 9U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
199 kINPUTMUX_CtInp10ToTimer0CaptureChannels = 10U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
200 kINPUTMUX_CtInp11ToTimer0CaptureChannels = 11U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
201 kINPUTMUX_CtInp12ToTimer0CaptureChannels = 12U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
202 kINPUTMUX_CtInp13ToTimer0CaptureChannels = 13U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
203 kINPUTMUX_CtInp14ToTimer0CaptureChannels = 14U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
204 kINPUTMUX_CtInp15ToTimer0CaptureChannels = 15U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
205 kINPUTMUX_SharedI2s0WsToTimer0CaptureChannels = 16U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
206 kINPUTMUX_SharedI2s1WsToTimer0CaptureChannels = 17U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
207 kINPUTMUX_Usb1FrameToggleToTimer0CaptureChannels = 18U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
208
209 /*!< CTmier1 capture input mux. */
210 kINPUTMUX_CtInp0ToTimer1CaptureChannels = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
211 kINPUTMUX_CtInp1ToTimer1CaptureChannels = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
212 kINPUTMUX_CtInp2ToTimer1CaptureChannels = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
213 kINPUTMUX_CtInp3ToTimer1CaptureChannels = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
214 kINPUTMUX_CtInp4ToTimer1CaptureChannels = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
215 kINPUTMUX_CtInp5ToTimer1CaptureChannels = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
216 kINPUTMUX_CtInp6ToTimer1CaptureChannels = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
217 kINPUTMUX_CtInp7ToTimer1CaptureChannels = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
218 kINPUTMUX_CtInp8ToTimer1CaptureChannels = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
219 kINPUTMUX_CtInp9ToTimer1CaptureChannels = 9U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
220 kINPUTMUX_CtInp10ToTimer1CaptureChannels = 10U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
221 kINPUTMUX_CtInp11ToTimer1CaptureChannels = 11U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
222 kINPUTMUX_CtInp12ToTimer1CaptureChannels = 12U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
223 kINPUTMUX_CtInp13ToTimer1CaptureChannels = 13U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
224 kINPUTMUX_CtInp14ToTimer1CaptureChannels = 14U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
225 kINPUTMUX_CtInp15ToTimer1CaptureChannels = 15U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
226 kINPUTMUX_SharedI2s0WsToTimer1CaptureChannels = 16U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
227 kINPUTMUX_SharedI2s1WsToTimer1CaptureChannels = 17U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
228 kINPUTMUX_Usb1FrameToggleToTimer1CaptureChannels = 18U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
229
230 /*!< CTmier2 capture input mux. */
231 kINPUTMUX_CtInp0ToTimer2CaptureChannels = 0U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
232 kINPUTMUX_CtInp1ToTimer2CaptureChannels = 1U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
233 kINPUTMUX_CtInp2ToTimer2CaptureChannels = 2U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
234 kINPUTMUX_CtInp3ToTimer2CaptureChannels = 3U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
235 kINPUTMUX_CtInp4ToTimer2CaptureChannels = 4U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
236 kINPUTMUX_CtInp5ToTimer2CaptureChannels = 5U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
237 kINPUTMUX_CtInp6ToTimer2CaptureChannels = 6U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
238 kINPUTMUX_CtInp7ToTimer2CaptureChannels = 7U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
239 kINPUTMUX_CtInp8ToTimer2CaptureChannels = 8U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
240 kINPUTMUX_CtInp9ToTimer2CaptureChannels = 9U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
241 kINPUTMUX_CtInp10ToTimer2CaptureChannels = 10U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
242 kINPUTMUX_CtInp11ToTimer2CaptureChannels = 11U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
243 kINPUTMUX_CtInp12ToTimer2CaptureChannels = 12U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
244 kINPUTMUX_CtInp13ToTimer2CaptureChannels = 13U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
245 kINPUTMUX_CtInp14ToTimer2CaptureChannels = 14U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
246 kINPUTMUX_CtInp15ToTimer2CaptureChannels = 15U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
247 kINPUTMUX_SharedI2s0WsToTimer2CaptureChannels = 16U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
248 kINPUTMUX_SharedI2s1WsToTimer2CaptureChannels = 17U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
249 kINPUTMUX_Usb1FrameToggleToTimer2CaptureChannels = 18U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
250
251 /*!< CTmier3 capture input mux. */
252 kINPUTMUX_CtInp0ToTimer3CaptureChannels = 0U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
253 kINPUTMUX_CtInp1ToTimer3CaptureChannels = 1U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
254 kINPUTMUX_CtInp2ToTimer3CaptureChannels = 2U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
255 kINPUTMUX_CtInp3ToTimer3CaptureChannels = 3U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
256 kINPUTMUX_CtInp4ToTimer3CaptureChannels = 4U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
257 kINPUTMUX_CtInp5ToTimer3CaptureChannels = 5U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
258 kINPUTMUX_CtInp6ToTimer3CaptureChannels = 6U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
259 kINPUTMUX_CtInp7ToTimer3CaptureChannels = 7U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
260 kINPUTMUX_CtInp8ToTimer3CaptureChannels = 8U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
261 kINPUTMUX_CtInp9ToTimer3CaptureChannels = 9U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
262 kINPUTMUX_CtInp10ToTimer3CaptureChannels = 10U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
263 kINPUTMUX_CtInp11ToTimer3CaptureChannels = 11U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
264 kINPUTMUX_CtInp12ToTimer3CaptureChannels = 12U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
265 kINPUTMUX_CtInp13ToTimer3CaptureChannels = 13U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
266 kINPUTMUX_CtInp14ToTimer3CaptureChannels = 14U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
267 kINPUTMUX_CtInp15ToTimer3CaptureChannels = 15U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
268 kINPUTMUX_SharedI2s0WsToTimer3CaptureChannels = 16U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
269 kINPUTMUX_SharedI2s1WsToTimer3CaptureChannels = 17U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
270 kINPUTMUX_Usb1FrameToggleToTimer3CaptureChannels = 18U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
271
272 /*!< CTmier4 capture input mux. */
273 kINPUTMUX_CtInp0ToTimer4CaptureChannels = 0U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
274 kINPUTMUX_CtInp1ToTimer4CaptureChannels = 1U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
275 kINPUTMUX_CtInp2ToTimer4CaptureChannels = 2U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
276 kINPUTMUX_CtInp3ToTimer4CaptureChannels = 3U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
277 kINPUTMUX_CtInp4ToTimer4CaptureChannels = 4U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
278 kINPUTMUX_CtInp5ToTimer4CaptureChannels = 5U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
279 kINPUTMUX_CtInp6ToTimer4CaptureChannels = 6U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
280 kINPUTMUX_CtInp7ToTimer4CaptureChannels = 7U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
281 kINPUTMUX_CtInp8ToTimer4CaptureChannels = 8U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
282 kINPUTMUX_CtInp9ToTimer4CaptureChannels = 9U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
283 kINPUTMUX_CtInp10ToTimer4CaptureChannels = 10U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
284 kINPUTMUX_CtInp11ToTimer4CaptureChannels = 11U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
285 kINPUTMUX_CtInp12ToTimer4CaptureChannels = 12U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
286 kINPUTMUX_CtInp13ToTimer4CaptureChannels = 13U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
287 kINPUTMUX_CtInp14ToTimer4CaptureChannels = 14U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
288 kINPUTMUX_CtInp15ToTimer4CaptureChannels = 15U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
289 kINPUTMUX_SharedI2s0WsToTimer4CaptureChannels = 16U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
290 kINPUTMUX_SharedI2s1WsToTimer4CaptureChannels = 17U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
291 kINPUTMUX_Usb1FrameToggleToTimer4CaptureChannels = 18U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
292
293 /*!< DMA0 ITRIG. */
294 kINPUTMUX_NsGpioPint0Int0ToDma0 = 0U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
295 kINPUTMUX_NsGpioPint0Int1ToDma0 = 1U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
296 kINPUTMUX_NsGpioPint0Int2ToDma0 = 2U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
297 kINPUTMUX_NsGpioPint0Int3ToDma0 = 3U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
298 kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
299 kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
300 kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
301 kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
302 kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
303 kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
304 kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
305 kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
306 kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
307 kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
308 kINPUTMUX_Dma0TrigOutAToDma0 = 14U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
309 kINPUTMUX_Dma0TrigOutBToDma0 = 15U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
310 kINPUTMUX_Dma0TrigOutCToDma0 = 16U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
311 kINPUTMUX_Dma0TrigOutDToDma0 = 17U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
312 kINPUTMUX_Sct0Dmac0ToDma0 = 18U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
313 kINPUTMUX_Sct0Dmac1ToDma0 = 19U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
314 kINPUTMUX_HashCryptOutToDma0 = 20U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
315 kINPUTMUX_AcmpToDma0 = 21U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
316 kINPUTMUX_AdcToDma0 = 24U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
317 kINPUTMUX_FlexspiRxToDma0 = 28U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
318 kINPUTMUX_FlexspiTxToDma0 = 29U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
319
320 /*!< DMA1 ITRIG. */
321 kINPUTMUX_NsGpioPint0Int0ToDma1 = 0U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
322 kINPUTMUX_NsGpioPint0Int1ToDma1 = 1U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
323 kINPUTMUX_NsGpioPint0Int2ToDma1 = 2U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
324 kINPUTMUX_NsGpioPint0Int3ToDma1 = 3U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
325 kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
326 kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
327 kINPUTMUX_Ctimer1M0ToDma1 = 6U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
328 kINPUTMUX_Ctimer1M1ToDma1 = 7U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
329 kINPUTMUX_Ctimer2M0ToDma1 = 8U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
330 kINPUTMUX_Ctimer2M1ToDma1 = 9U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
331 kINPUTMUX_Ctimer3M0ToDma1 = 10U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
332 kINPUTMUX_Ctimer3M1ToDma1 = 11U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
333 kINPUTMUX_Ctimer4M0ToDma1 = 12U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
334 kINPUTMUX_Ctimer4M1ToDma1 = 13U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
335 kINPUTMUX_Dma1TrigOutAToDma1 = 14U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
336 kINPUTMUX_Dma1TrigOutBToDma1 = 15U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
337 kINPUTMUX_Dma1TrigOutCToDma1 = 16U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
338 kINPUTMUX_Dma1TrigOutDToDma1 = 17U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
339 kINPUTMUX_Sct0Dmac0ToDma1 = 18U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
340 kINPUTMUX_Sct0Dmac1ToDma1 = 19U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
341 kINPUTMUX_HashCryptOutToDma1 = 20U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
342 kINPUTMUX_AcmpToDma1 = 21U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
343 kINPUTMUX_AdcToDma1 = 24U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
344 kINPUTMUX_FlexspiRxToDma1 = 28U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
345 kINPUTMUX_FlexspiTxToDma1 = 29U + (DMA1_ITRIG_PMUX_ID << PMUX_SHIFT),
346
347 /*!< DMA0 OTRIG. */
348 kINPUTMUX_Dma0OtrigChannel0ToTriginChannels = 0U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
349 kINPUTMUX_Dma0OtrigChannel1ToTriginChannels = 1U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
350 kINPUTMUX_Dma0OtrigChannel2ToTriginChannels = 2U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
351 kINPUTMUX_Dma0OtrigChannel3ToTriginChannels = 3U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
352 kINPUTMUX_Dma0OtrigChannel4ToTriginChannels = 4U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
353 kINPUTMUX_Dma0OtrigChannel5ToTriginChannels = 5U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
354 kINPUTMUX_Dma0OtrigChannel6ToTriginChannels = 6U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
355 kINPUTMUX_Dma0OtrigChannel7ToTriginChannels = 7U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
356 kINPUTMUX_Dma0OtrigChannel8ToTriginChannels = 8U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
357 kINPUTMUX_Dma0OtrigChannel9ToTriginChannels = 9U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
358 kINPUTMUX_Dma0OtrigChannel10ToTriginChannels = 10U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
359 kINPUTMUX_Dma0OtrigChannel11ToTriginChannels = 11U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
360 kINPUTMUX_Dma0OtrigChannel12ToTriginChannels = 12U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
361 kINPUTMUX_Dma0OtrigChannel13ToTriginChannels = 13U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
362 kINPUTMUX_Dma0OtrigChannel14ToTriginChannels = 14U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
363 kINPUTMUX_Dma0OtrigChannel15ToTriginChannels = 15U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
364 kINPUTMUX_Dma0OtrigChannel16ToTriginChannels = 16U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
365 kINPUTMUX_Dma0OtrigChannel17ToTriginChannels = 17U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
366 kINPUTMUX_Dma0OtrigChannel18ToTriginChannels = 18U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
367 kINPUTMUX_Dma0OtrigChannel19ToTriginChannels = 19U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
368 kINPUTMUX_Dma0OtrigChannel20ToTriginChannels = 20U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
369 kINPUTMUX_Dma0OtrigChannel21ToTriginChannels = 21U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
370 kINPUTMUX_Dma0OtrigChannel22ToTriginChannels = 22U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
371 kINPUTMUX_Dma0OtrigChannel23ToTriginChannels = 23U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
372 kINPUTMUX_Dma0OtrigChannel24ToTriginChannels = 24U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
373 kINPUTMUX_Dma0OtrigChannel25ToTriginChannels = 25U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
374 kINPUTMUX_Dma0OtrigChannel26ToTriginChannels = 26U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
375 kINPUTMUX_Dma0OtrigChannel27ToTriginChannels = 27U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
376 kINPUTMUX_Dma0OtrigChannel28ToTriginChannels = 28U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
377 kINPUTMUX_Dma0OtrigChannel29ToTriginChannels = 29U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
378 kINPUTMUX_Dma0OtrigChannel30ToTriginChannels = 30U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
379 kINPUTMUX_Dma0OtrigChannel31ToTriginChannels = 31U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
380 kINPUTMUX_Dma0OtrigChannel32ToTriginChannels = 32U + (DMA0_OTRIG_PMUX_ID << PMUX_SHIFT),
381
382 /*!< DMA1 OTRIG. */
383 kINPUTMUX_Dma1OtrigChannel0ToTriginChannels = 0U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
384 kINPUTMUX_Dma1OtrigChannel1ToTriginChannels = 1U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
385 kINPUTMUX_Dma1OtrigChannel2ToTriginChannels = 2U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
386 kINPUTMUX_Dma1OtrigChannel3ToTriginChannels = 3U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
387 kINPUTMUX_Dma1OtrigChannel4ToTriginChannels = 4U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
388 kINPUTMUX_Dma1OtrigChannel5ToTriginChannels = 5U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
389 kINPUTMUX_Dma1OtrigChannel6ToTriginChannels = 6U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
390 kINPUTMUX_Dma1OtrigChannel7ToTriginChannels = 7U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
391 kINPUTMUX_Dma1OtrigChannel8ToTriginChannels = 8U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
392 kINPUTMUX_Dma1OtrigChannel9ToTriginChannels = 9U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
393 kINPUTMUX_Dma1OtrigChannel10ToTriginChannels = 10U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
394 kINPUTMUX_Dma1OtrigChannel11ToTriginChannels = 11U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
395 kINPUTMUX_Dma1OtrigChannel12ToTriginChannels = 12U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
396 kINPUTMUX_Dma1OtrigChannel13ToTriginChannels = 13U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
397 kINPUTMUX_Dma1OtrigChannel14ToTriginChannels = 14U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
398 kINPUTMUX_Dma1OtrigChannel15ToTriginChannels = 15U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
399 kINPUTMUX_Dma1OtrigChannel16ToTriginChannels = 16U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
400 kINPUTMUX_Dma1OtrigChannel17ToTriginChannels = 17U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
401 kINPUTMUX_Dma1OtrigChannel18ToTriginChannels = 18U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
402 kINPUTMUX_Dma1OtrigChannel19ToTriginChannels = 19U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
403 kINPUTMUX_Dma1OtrigChannel20ToTriginChannels = 20U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
404 kINPUTMUX_Dma1OtrigChannel21ToTriginChannels = 21U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
405 kINPUTMUX_Dma1OtrigChannel22ToTriginChannels = 22U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
406 kINPUTMUX_Dma1OtrigChannel23ToTriginChannels = 23U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
407 kINPUTMUX_Dma1OtrigChannel24ToTriginChannels = 24U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
408 kINPUTMUX_Dma1OtrigChannel25ToTriginChannels = 25U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
409 kINPUTMUX_Dma1OtrigChannel26ToTriginChannels = 26U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
410 kINPUTMUX_Dma1OtrigChannel27ToTriginChannels = 27U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
411 kINPUTMUX_Dma1OtrigChannel28ToTriginChannels = 28U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
412 kINPUTMUX_Dma1OtrigChannel29ToTriginChannels = 29U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
413 kINPUTMUX_Dma1OtrigChannel30ToTriginChannels = 30U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
414 kINPUTMUX_Dma1OtrigChannel31ToTriginChannels = 31U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
415 kINPUTMUX_Dma1OtrigChannel32ToTriginChannels = 32U + (DMA1_OTRIG_PMUX_ID << PMUX_SHIFT),
416} inputmux_connection_t;
417/*! @brief INPUTMUX signal enable/disable type */
418typedef enum _inputmux_signal_t
419{
420 /*!< DMA0 input trigger source enable. */
421 kINPUTMUX_Dmac0InputTriggerPint0Ena = 0U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
422 kINPUTMUX_Dmac0InputTriggerPint1Ena = 1U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
423 kINPUTMUX_Dmac0InputTriggerPint2Ena = 2U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
424 kINPUTMUX_Dmac0InputTriggerPint3Ena = 3U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
425 kINPUTMUX_Dmac0InputTriggerCtimer0M0Ena = 4U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
426 kINPUTMUX_Dmac0InputTriggerCtimer0M1Ena = 5U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
427 kINPUTMUX_Dmac0InputTriggerCtimer1M0Ena = 6U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
428 kINPUTMUX_Dmac0InputTriggerCtimer1M1Ena = 7U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
429 kINPUTMUX_Dmac0InputTriggerCtimer2M0Ena = 8U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
430 kINPUTMUX_Dmac0InputTriggerCtimer2M1Ena = 9U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
431 kINPUTMUX_Dmac0InputTriggerCtimer3M0Ena = 10U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
432 kINPUTMUX_Dmac0InputTriggerCtimer3M1Ena = 11U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
433 kINPUTMUX_Dmac0InputTriggerCtimer4M0Ena = 12U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
434 kINPUTMUX_Dmac0InputTriggerCtimer4M1Ena = 13U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
435 kINPUTMUX_Dmac0InputTriggerDma0OutAEna = 14U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
436 kINPUTMUX_Dmac0InputTriggerDma0OutBEna = 15U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
437 kINPUTMUX_Dmac0InputTriggerDma0OutCEna = 16U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
438 kINPUTMUX_Dmac0InputTriggerDma0OutDEna = 17U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
439 kINPUTMUX_Dmac0InputTriggerSctDmac0Ena = 18U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
440 kINPUTMUX_Dmac0InputTriggerSctDmac1Ena = 19U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
441 kINPUTMUX_Dmac0InputTriggerHashOutEna = 20U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
442 kINPUTMUX_Dmac0InputTriggerAcmpEna = 21U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
443 kINPUTMUX_Dmac0InputTriggerAdcEna = 24U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
444 kINPUTMUX_Dmac0InputTriggerFlexspiRxEna = 28U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
445 kINPUTMUX_Dmac0InputTriggerFlexspiTxEna = 29U + (DMA0_ITRIG_EN0_ID << ENA_SHIFT),
446
447 /*!< DMA1 input trigger source enable. */
448 kINPUTMUX_Dmac1InputTriggerPint0Ena = 0U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
449 kINPUTMUX_Dmac1InputTriggerPint1Ena = 1U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
450 kINPUTMUX_Dmac1InputTriggerPint2Ena = 2U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
451 kINPUTMUX_Dmac1InputTriggerPint3Ena = 3U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
452 kINPUTMUX_Dmac1InputTriggerCtimer0M0Ena = 4U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
453 kINPUTMUX_Dmac1InputTriggerCtimer0M1Ena = 5U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
454 kINPUTMUX_Dmac1InputTriggerCtimer1M0Ena = 6U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
455 kINPUTMUX_Dmac1InputTriggerCtimer1M1Ena = 7U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
456 kINPUTMUX_Dmac1InputTriggerCtimer2M0Ena = 8U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
457 kINPUTMUX_Dmac1InputTriggerCtimer2M1Ena = 9U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
458 kINPUTMUX_Dmac1InputTriggerCtimer3M0Ena = 10U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
459 kINPUTMUX_Dmac1InputTriggerCtimer3M1Ena = 11U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
460 kINPUTMUX_Dmac1InputTriggerCtimer4M0Ena = 12U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
461 kINPUTMUX_Dmac1InputTriggerCtimer4M1Ena = 13U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
462 kINPUTMUX_Dmac1InputTriggerDma1OutAEna = 14U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
463 kINPUTMUX_Dmac1InputTriggerDma1OutBEna = 15U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
464 kINPUTMUX_Dmac1InputTriggerDma1OutCEna = 16U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
465 kINPUTMUX_Dmac1InputTriggerDma1OutDEna = 17U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
466 kINPUTMUX_Dmac1InputTriggerSctDmac0Ena = 18U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
467 kINPUTMUX_Dmac1InputTriggerSctDmac1Ena = 19U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
468 kINPUTMUX_Dmac1InputTriggerHashOutEna = 20U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
469 kINPUTMUX_Dmac1InputTriggerAcmpEna = 21U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
470 kINPUTMUX_Dmac1InputTriggerAdcEna = 24U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
471 kINPUTMUX_Dmac1InputTriggerFlexspiRxEna = 28U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
472 kINPUTMUX_Dmac1InputTriggerFlexspiTxEna = 29U + (DMA1_ITRIG_EN0_ID << ENA_SHIFT),
473
474 /*!< DMA0 REQ signal. */
475 kINPUTMUX_Flexcomm0RxToDmac0Ch0RequestEna = 0U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
476 kINPUTMUX_Flexcomm0TxToDmac0Ch1RequestEna = 1U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
477 kINPUTMUX_Flexcomm1RxToDmac0Ch2RequestEna = 2U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
478 kINPUTMUX_Flexcomm1TxToDmac0Ch3RequestEna = 3U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
479 kINPUTMUX_Flexcomm2RxToDmac0Ch4RequestEna = 4U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
480 kINPUTMUX_Flexcomm2TxToDmac0Ch5RequestEna = 5U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
481 kINPUTMUX_Flexcomm3RxToDmac0Ch6RequestEna = 6U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
482 kINPUTMUX_Flexcomm3TxToDmac0Ch7RequestEna = 7U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
483 kINPUTMUX_Flexcomm4RxToDmac0Ch8RequestEna = 8U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
484 kINPUTMUX_Flexcomm4TxToDmac0Ch9RequestEna = 9U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
485 kINPUTMUX_Flexcomm5RxToDmac0Ch10RequestEna = 10U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
486 kINPUTMUX_Flexcomm5TxToDmac0Ch11RequestEna = 11U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
487 kINPUTMUX_Flexcomm6RxToDmac0Ch12RequestEna = 12U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
488 kINPUTMUX_Flexcomm6TxToDmac0Ch13RequestEna = 13U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
489 kINPUTMUX_Flexcomm7RxToDmac0Ch14RequestEna = 14U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
490 kINPUTMUX_Flexcomm7TxToDmac0Ch15RequestEna = 15U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
491 kINPUTMUX_Dmic0Ch0ToDmac0Ch16RequestEna = 16U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
492 kINPUTMUX_Dmic0Ch1ToDmac0Ch17RequestEna = 17U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
493 kINPUTMUX_Dmic0Ch2ToDmac0Ch18RequestEna = 18U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
494 kINPUTMUX_Dmic0Ch3ToDmac0Ch19RequestEna = 19U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
495 kINPUTMUX_Dmic0Ch4ToDmac0Ch20RequestEna = 20U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
496 kINPUTMUX_Dmic0Ch5ToDmac0Ch21RequestEna = 21U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
497 kINPUTMUX_Dmic0Ch6ToDmac0Ch22RequestEna = 22U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
498 kINPUTMUX_Dmic0Ch7ToDmac0Ch23RequestEna = 23U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
499 kINPUTMUX_I3c0RxToDmac0Ch24RequestEna = 24U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
500 kINPUTMUX_I3c0TxToDmac0Ch25RequestEna = 25U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
501 kINPUTMUX_Flexcomm14RxToDmac0Ch26RequestEna = 26U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
502 kINPUTMUX_Flexcomm14TxToDmac0Ch27RequestEna = 27U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
503 kINPUTMUX_HashCryptToDmac0Ch30RequestEna = 30U + (DMA0_REQ_ENA0_ID << ENA_SHIFT),
504
505 /*!< DMA1 REQ signal. */
506 kINPUTMUX_Flexcomm0RxToDmac1Ch0RequestEna = 0U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
507 kINPUTMUX_Flexcomm0TxToDmac1Ch1RequestEna = 1U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
508 kINPUTMUX_Flexcomm1RxToDmac1Ch2RequestEna = 2U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
509 kINPUTMUX_Flexcomm1TxToDmac1Ch3RequestEna = 3U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
510 kINPUTMUX_Flexcomm2RxToDmac1Ch4RequestEna = 4U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
511 kINPUTMUX_Flexcomm2TxToDmac1Ch5RequestEna = 5U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
512 kINPUTMUX_Flexcomm3RxToDmac1Ch6RequestEna = 6U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
513 kINPUTMUX_Flexcomm3TxToDmac1Ch7RequestEna = 7U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
514 kINPUTMUX_Flexcomm4RxToDmac1Ch8RequestEna = 8U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
515 kINPUTMUX_Flexcomm4TxToDmac1Ch9RequestEna = 9U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
516 kINPUTMUX_Flexcomm5RxToDmac1Ch10RequestEna = 10U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
517 kINPUTMUX_Flexcomm5TxToDmac1Ch11RequestEna = 11U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
518 kINPUTMUX_Flexcomm6RxToDmac1Ch12RequestEna = 12U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
519 kINPUTMUX_Flexcomm6TxToDmac1Ch13RequestEna = 13U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
520 kINPUTMUX_Flexcomm7RxToDmac1Ch14RequestEna = 14U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
521 kINPUTMUX_Flexcomm7TxToDmac1Ch15RequestEna = 15U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
522 kINPUTMUX_Dmic0Ch0ToDmac1Ch16RequestEna = 16U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
523 kINPUTMUX_Dmic0Ch1ToDmac1Ch17RequestEna = 17U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
524 kINPUTMUX_Dmic0Ch2ToDmac1Ch18RequestEna = 18U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
525 kINPUTMUX_Dmic0Ch3ToDmac1Ch19RequestEna = 19U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
526 kINPUTMUX_Dmic0Ch4ToDmac1Ch20RequestEna = 20U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
527 kINPUTMUX_Dmic0Ch5ToDmac1Ch21RequestEna = 21U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
528 kINPUTMUX_Dmic0Ch6ToDmac1Ch22RequestEna = 22U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
529 kINPUTMUX_Dmic0Ch7ToDmac1Ch23RequestEna = 23U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
530 kINPUTMUX_I3c0RxToDmac1Ch24RequestEna = 24U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
531 kINPUTMUX_I3c0TxToDmac1Ch25RequestEna = 25U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
532 kINPUTMUX_Flexcomm14RxToDmac1Ch26RequestEna = 26U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
533 kINPUTMUX_Flexcomm14TxToDmac1Ch27RequestEna = 27U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
534 kINPUTMUX_HashCryptToDmac1Ch30RequestEna = 30U + (DMA1_REQ_ENA0_ID << ENA_SHIFT),
535
536} inputmux_signal_t;
537
538/*@}*/
539
540#endif /* _FSL_INPUTMUX_CONNECTIONS_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 05:24:38 +0100