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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT633S/drivers/fsl_power.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT633S/drivers/fsl_power.h
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@@ -0,0 +1,579 @@
1/*
2 * Copyright 2018, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#ifndef _FSL_POWER_H_
8#define _FSL_POWER_H_
9
10#include "fsl_common.h"
11
12/*!
13 * @addtogroup power
14 * @{
15 */
16/*******************************************************************************
17 * Definitions
18 ******************************************************************************/
19
20/*! @name Driver version */
21/*@{*/
22/*! @brief power driver version 2.3.0. */
23#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 3, 0))
24/*@}*/
25
26#define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot))
27#define SYSCTL0_PDRCFGSET_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_SET)) + ((x) << 2U))))
28#define SYSCTL0_PDRCFGCLR_REG(x) (*((volatile uint32_t *)((uint32_t)(&(SYSCTL0->PDRUNCFG0_CLR)) + ((x) << 2U))))
29#define PDRCFG0 0x0U
30#define PDRCFG1 0x1U
31#define PDRCFG2 0x2U
32#define PDRCFG3 0x3U
33
34/*! PMIC is used but vddcore supply is always above LVD threshold. */
35#define PMIC_VDDCORE_RECOVERY_TIME_IGNORE (0xFFFFFFFFU)
36
37/*! Invalid voltage level. */
38#define POWER_INVALID_VOLT_LEVEL (0xFFFFFFFFU)
39/**
40 * @brief PMC event flags.
41 *
42 * @note These enums are meant to be OR'd together to form a bit mask.
43 */
44enum _pmc_interrupt
45{
46 kPMC_INT_LVDCORE = PMC_CTRL_LVDCOREIE_MASK, /*!< Vddcore Low-Voltage Detector Interrupt Enable. */
47 kPMC_INT_HVDCORE = PMC_CTRL_HVDCOREIE_MASK, /*!< Vddcore High-Voltage Detector Interrupt Enable. */
48 kPMC_INT_HVD1V8 = PMC_CTRL_HVD1V8IE_MASK, /*!< Vdd1v8 High-Voltage Detector Interrupt Enable. */
49 kPMC_INT_AUTOWK = PMC_CTRL_AUTOWKEN_MASK, /*!< PMC automatic wakeup enable and interrupt enable. */
50 kPMC_INT_INTRPAD =
51 PMC_CTRL_INTRPADEN_MASK /*!< Interrupt pad deep powerdown and deep sleep wake up & interrupt enable. */
52};
53
54/**
55 * @brief PMC event flags.
56 *
57 * @note These enums are meant to be OR'd together to form a bit mask.
58 */
59enum _pmc_event_flags
60{
61 kPMC_FLAGS_PORCORE = PMC_FLAGS_PORCOREF_MASK, /*!< POR triggered by the vddcore POR monitor (0 = no, 1 = yes). */
62 kPMC_FLAGS_POR1V8 =
63 PMC_FLAGS_POR1V8F_MASK, /*!< vdd1v8 power on event detected since last cleared(0 = no, 1 = yes). */
64 kPMC_FLAGS_PORAO18 =
65 PMC_FLAGS_PORAO18F_MASK, /*!< vdd_ao18 power on event detected since last cleared (0 = no, 1 = yes). */
66 kPMC_FLAGS_LVDCORE =
67 PMC_FLAGS_LVDCOREF_MASK, /*!< LVD tripped since last time this bit was cleared (0 = no, 1 = yes). */
68 kPMC_FLAGS_HVDCORE =
69 PMC_FLAGS_HVDCOREF_MASK, /*!< HVD tripped since last time this bit was cleared (0 = no, 1 = yes). */
70 kPMC_FLAGS_HVD1V8 =
71 PMC_FLAGS_HVD1V8F_MASK, /*!< vdd1v8 HVD tripped since last time this bit was cleared (0 = no, 1 = yes). */
72 kPMC_FLAGS_RTC =
73 PMC_FLAGS_RTCF_MASK, /*!< RTC wakeup detected since last time flag was cleared (0 = no, 1 = yes). */
74 kPMC_FLAGS_AUTOWK =
75 PMC_FLAGS_AUTOWKF_MASK, /*!< PMC Auto wakeup caused a deep sleep wakeup and interrupt (0 = no, 1 = yes). */
76 kPMC_FLAGS_INTNPADF = PMC_FLAGS_INTNPADF_MASK, /*!< Pad interrupt caused a wakeup or interrupt event since the last
77 time this flag was cleared (0 = no, 1 = yes). */
78 kPMC_FLAGS_RESETNPAD = PMC_FLAGS_RESETNPADF_MASK, /*!< Reset pad wakeup caused a wakeup or reset event since the
79 last time this bit was cleared. (0 = no, 1 = yes). */
80 kPMC_FLAGS_DEEPPD = PMC_FLAGS_DEEPPDF_MASK /*!< Deep powerdown was entered since the last time this flag was cleared
81 (0 = no, 1 = yes). */
82};
83
84typedef enum pd_bits
85{
86 kPDRUNCFG_PMC_MODE0 = MAKE_PD_BITS(PDRCFG0, 1U),
87 kPDRUNCFG_PMC_MODE1 = MAKE_PD_BITS(PDRCFG0, 2U),
88 kPDRUNCFG_LP_VDD_COREREG = MAKE_PD_BITS(PDRCFG0, 4U),
89 kPDRUNCFG_LP_PMCREF = MAKE_PD_BITS(PDRCFG0, 6U),
90 kPDRUNCFG_PD_HVD1V8 = MAKE_PD_BITS(PDRCFG0, 7U),
91 kPDRUNCFG_LP_PORCORE = MAKE_PD_BITS(PDRCFG0, 8U),
92 kPDRUNCFG_LP_LVDCORE = MAKE_PD_BITS(PDRCFG0, 9U),
93 kPDRUNCFG_PD_HVDCORE = MAKE_PD_BITS(PDRCFG0, 10U),
94 kPDRUNCFG_PD_SYSXTAL = MAKE_PD_BITS(PDRCFG0, 13U),
95 kPDRUNCFG_PD_LPOSC = MAKE_PD_BITS(PDRCFG0, 14U),
96 kPDRUNCFG_PD_SFRO = MAKE_PD_BITS(PDRCFG0, 15U),
97 kPDRUNCFG_PD_FFRO = MAKE_PD_BITS(PDRCFG0, 16U),
98 kPDRUNCFG_PD_SYSPLL_LDO = MAKE_PD_BITS(PDRCFG0, 17U),
99 kPDRUNCFG_PD_SYSPLL_ANA = MAKE_PD_BITS(PDRCFG0, 18U),
100 kPDRUNCFG_PD_AUDPLL_LDO = MAKE_PD_BITS(PDRCFG0, 19U),
101 kPDRUNCFG_PD_AUDPLL_ANA = MAKE_PD_BITS(PDRCFG0, 20U),
102 kPDRUNCFG_PD_ADC = MAKE_PD_BITS(PDRCFG0, 21U),
103 kPDRUNCFG_LP_ADC = MAKE_PD_BITS(PDRCFG0, 22U),
104 kPDRUNCFG_PD_ADC_TEMPSNS = MAKE_PD_BITS(PDRCFG0, 23U),
105 kPDRUNCFG_PD_ACMP = MAKE_PD_BITS(PDRCFG0, 25U),
106 kPDRUNCFG_LP_HSPAD_VDET = MAKE_PD_BITS(PDRCFG0, 28U),
107 kPDRUNCFG_PD_HSPAD_REF = MAKE_PD_BITS(PDRCFG0, 29U),
108
109 kPDRUNCFG_APD_PQ_SRAM = MAKE_PD_BITS(PDRCFG1, 0U),
110 kPDRUNCFG_PPD_PQ_SRAM = MAKE_PD_BITS(PDRCFG1, 1U),
111 kPDRUNCFG_APD_FLEXSPI_SRAM = MAKE_PD_BITS(PDRCFG1, 2U),
112 kPDRUNCFG_PPD_FLEXSPI_SRAM = MAKE_PD_BITS(PDRCFG1, 3U),
113 kPDRUNCFG_APD_USBHS_SRAM = MAKE_PD_BITS(PDRCFG1, 4U),
114 kPDRUNCFG_PPD_USBHS_SRAM = MAKE_PD_BITS(PDRCFG1, 5U),
115 kPDRUNCFG_APD_USDHC0_SRAM = MAKE_PD_BITS(PDRCFG1, 6U),
116 kPDRUNCFG_PPD_USDHC0_SRAM = MAKE_PD_BITS(PDRCFG1, 7U),
117 kPDRUNCFG_APD_USDHC1_SRAM = MAKE_PD_BITS(PDRCFG1, 8U),
118 kPDRUNCFG_PPD_USDHC1_SRAM = MAKE_PD_BITS(PDRCFG1, 9U),
119 kPDRUNCFG_APD_CASPER_SRAM = MAKE_PD_BITS(PDRCFG1, 10U),
120 kPDRUNCFG_PPD_CASPER_SRAM = MAKE_PD_BITS(PDRCFG1, 11U),
121 kPDRUNCFG_APD_DSP_CACHE_REGF = MAKE_PD_BITS(PDRCFG1, 24U),
122 kPDRUNCFG_PPD_DSP_CACHE_REGF = MAKE_PD_BITS(PDRCFG1, 25U),
123 kPDRUNCFG_APD_DSP_TCM_REGF = MAKE_PD_BITS(PDRCFG1, 26U),
124 kPDRUNCFG_PPD_DSP_TCM_REGF = MAKE_PD_BITS(PDRCFG1, 27U),
125 kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG1, 28U),
126 kPDRUNCFG_SRAM_SLEEP = MAKE_PD_BITS(PDRCFG1, 31U),
127
128 kPDRUNCFG_APD_SRAM_IF0 = MAKE_PD_BITS(PDRCFG2, 0U),
129 kPDRUNCFG_APD_SRAM_IF1 = MAKE_PD_BITS(PDRCFG2, 1U),
130 kPDRUNCFG_APD_SRAM_IF2 = MAKE_PD_BITS(PDRCFG2, 2U),
131 kPDRUNCFG_APD_SRAM_IF3 = MAKE_PD_BITS(PDRCFG2, 3U),
132 kPDRUNCFG_APD_SRAM_IF4 = MAKE_PD_BITS(PDRCFG2, 4U),
133 kPDRUNCFG_APD_SRAM_IF5 = MAKE_PD_BITS(PDRCFG2, 5U),
134 kPDRUNCFG_APD_SRAM_IF6 = MAKE_PD_BITS(PDRCFG2, 6U),
135 kPDRUNCFG_APD_SRAM_IF7 = MAKE_PD_BITS(PDRCFG2, 7U),
136 kPDRUNCFG_APD_SRAM_IF8 = MAKE_PD_BITS(PDRCFG2, 8U),
137 kPDRUNCFG_APD_SRAM_IF9 = MAKE_PD_BITS(PDRCFG2, 9U),
138 kPDRUNCFG_APD_SRAM_IF10 = MAKE_PD_BITS(PDRCFG2, 10U),
139 kPDRUNCFG_APD_SRAM_IF11 = MAKE_PD_BITS(PDRCFG2, 11U),
140 kPDRUNCFG_APD_SRAM_IF12 = MAKE_PD_BITS(PDRCFG2, 12U),
141 kPDRUNCFG_APD_SRAM_IF13 = MAKE_PD_BITS(PDRCFG2, 13U),
142 kPDRUNCFG_APD_SRAM_IF14 = MAKE_PD_BITS(PDRCFG2, 14U),
143 kPDRUNCFG_APD_SRAM_IF15 = MAKE_PD_BITS(PDRCFG2, 15U),
144 kPDRUNCFG_APD_SRAM_IF16 = MAKE_PD_BITS(PDRCFG2, 16U),
145 kPDRUNCFG_APD_SRAM_IF17 = MAKE_PD_BITS(PDRCFG2, 17U),
146 kPDRUNCFG_APD_SRAM_IF18 = MAKE_PD_BITS(PDRCFG2, 18U),
147 kPDRUNCFG_APD_SRAM_IF19 = MAKE_PD_BITS(PDRCFG2, 19U),
148 kPDRUNCFG_APD_SRAM_IF20 = MAKE_PD_BITS(PDRCFG2, 20U),
149 kPDRUNCFG_APD_SRAM_IF21 = MAKE_PD_BITS(PDRCFG2, 21U),
150 kPDRUNCFG_APD_SRAM_IF22 = MAKE_PD_BITS(PDRCFG2, 22U),
151 kPDRUNCFG_APD_SRAM_IF23 = MAKE_PD_BITS(PDRCFG2, 23U),
152 kPDRUNCFG_APD_SRAM_IF24 = MAKE_PD_BITS(PDRCFG2, 24U),
153 kPDRUNCFG_APD_SRAM_IF25 = MAKE_PD_BITS(PDRCFG2, 25U),
154 kPDRUNCFG_APD_SRAM_IF26 = MAKE_PD_BITS(PDRCFG2, 26U),
155 kPDRUNCFG_APD_SRAM_IF27 = MAKE_PD_BITS(PDRCFG2, 27U),
156 kPDRUNCFG_APD_SRAM_IF28 = MAKE_PD_BITS(PDRCFG2, 28U),
157 kPDRUNCFG_APD_SRAM_IF29 = MAKE_PD_BITS(PDRCFG2, 29U),
158
159 kPDRUNCFG_PPD_SRAM_IF0 = MAKE_PD_BITS(PDRCFG3, 0U),
160 kPDRUNCFG_PPD_SRAM_IF1 = MAKE_PD_BITS(PDRCFG3, 1U),
161 kPDRUNCFG_PPD_SRAM_IF2 = MAKE_PD_BITS(PDRCFG3, 2U),
162 kPDRUNCFG_PPD_SRAM_IF3 = MAKE_PD_BITS(PDRCFG3, 3U),
163 kPDRUNCFG_PPD_SRAM_IF4 = MAKE_PD_BITS(PDRCFG3, 4U),
164 kPDRUNCFG_PPD_SRAM_IF5 = MAKE_PD_BITS(PDRCFG3, 5U),
165 kPDRUNCFG_PPD_SRAM_IF6 = MAKE_PD_BITS(PDRCFG3, 6U),
166 kPDRUNCFG_PPD_SRAM_IF7 = MAKE_PD_BITS(PDRCFG3, 7U),
167 kPDRUNCFG_PPD_SRAM_IF8 = MAKE_PD_BITS(PDRCFG3, 8U),
168 kPDRUNCFG_PPD_SRAM_IF9 = MAKE_PD_BITS(PDRCFG3, 9U),
169 kPDRUNCFG_PPD_SRAM_IF10 = MAKE_PD_BITS(PDRCFG3, 10U),
170 kPDRUNCFG_PPD_SRAM_IF11 = MAKE_PD_BITS(PDRCFG3, 11U),
171 kPDRUNCFG_PPD_SRAM_IF12 = MAKE_PD_BITS(PDRCFG3, 12U),
172 kPDRUNCFG_PPD_SRAM_IF13 = MAKE_PD_BITS(PDRCFG3, 13U),
173 kPDRUNCFG_PPD_SRAM_IF14 = MAKE_PD_BITS(PDRCFG3, 14U),
174 kPDRUNCFG_PPD_SRAM_IF15 = MAKE_PD_BITS(PDRCFG3, 15U),
175 kPDRUNCFG_PPD_SRAM_IF16 = MAKE_PD_BITS(PDRCFG3, 16U),
176 kPDRUNCFG_PPD_SRAM_IF17 = MAKE_PD_BITS(PDRCFG3, 17U),
177 kPDRUNCFG_PPD_SRAM_IF18 = MAKE_PD_BITS(PDRCFG3, 18U),
178 kPDRUNCFG_PPD_SRAM_IF19 = MAKE_PD_BITS(PDRCFG3, 19U),
179 kPDRUNCFG_PPD_SRAM_IF20 = MAKE_PD_BITS(PDRCFG3, 20U),
180 kPDRUNCFG_PPD_SRAM_IF21 = MAKE_PD_BITS(PDRCFG3, 21U),
181 kPDRUNCFG_PPD_SRAM_IF22 = MAKE_PD_BITS(PDRCFG3, 22U),
182 kPDRUNCFG_PPD_SRAM_IF23 = MAKE_PD_BITS(PDRCFG3, 23U),
183 kPDRUNCFG_PPD_SRAM_IF24 = MAKE_PD_BITS(PDRCFG3, 24U),
184 kPDRUNCFG_PPD_SRAM_IF25 = MAKE_PD_BITS(PDRCFG3, 25U),
185 kPDRUNCFG_PPD_SRAM_IF26 = MAKE_PD_BITS(PDRCFG3, 26U),
186 kPDRUNCFG_PPD_SRAM_IF27 = MAKE_PD_BITS(PDRCFG3, 27U),
187 kPDRUNCFG_PPD_SRAM_IF28 = MAKE_PD_BITS(PDRCFG3, 28U),
188 kPDRUNCFG_PPD_SRAM_IF29 = MAKE_PD_BITS(PDRCFG3, 29U),
189 /*
190 This enum member has no practical meaning,it is used to avoid MISRA issue,
191 user should not trying to use it.
192 */
193 kPDRUNCFG_ForceUnsigned = (int)0x80000000U,
194} pd_bit_t;
195
196/*! @brief Power mode configuration API parameter */
197typedef enum _power_mode_config
198{
199 kPmu_Sleep = 0U,
200 kPmu_Deep_Sleep = 1U,
201 kPmu_Deep_PowerDown = 2U,
202 kPmu_Full_Deep_PowerDown = 3U,
203} power_mode_cfg_t;
204
205/*! @brief Body Bias mode definition */
206typedef enum _body_bias_mode
207{
208 kPmu_Fbb = 0x01U, /* Forward Body Bias Mode. */
209 kPmu_Rbb = 0x02U, /* Reverse Body Bias Mode. */
210 kPmu_Nbb = 0x03U, /* Normal Body Bias Mode. */
211} body_bias_mode_t;
212
213/*! @brief PMIC mode pin configuration API parameter */
214#define SYSCTL0_TUPLE_REG(reg) (*((volatile uint32_t *)(((uint32_t)(SYSCTL0)) + (((uint32_t)(reg)) & 0xFFFU))))
215typedef enum _pmic_mode_reg
216{
217 kCfg_Run = 0x610,
218 kCfg_Sleep = 0x600,
219} pmic_mode_reg_t;
220
221/*!
222 * @brief pad voltage range value.
223 */
224typedef enum _power_pad_vrange_val
225{
226 kPadVol_171_360 = 0U, /*!< Voltage from 1.71V to 3.60V. */
227 kPadVol_171_198 = 1U, /*!< Voltage from 1.71V to 1.98V. */
228 kPadVol_300_360 = 2U, /*!< Voltage from 3.00V to 3.60V. */
229} power_pad_vrange_val_t;
230
231/*!
232 * @brief pad voltage range configuration.
233 */
234typedef struct _power_pad_vrange
235{
236 uint32_t Vdde0Range : 2; /*!< VDDE0 voltage range for VDDIO_0. @ref power_pad_vrange_val_t */
237 uint32_t Vdde1Range : 2; /*!< VDDE1 voltage range for VDDIO_1. @ref power_pad_vrange_val_t */
238 uint32_t Vdde2Range : 2; /*!< VDDE2 voltage range for VDDIO_2. @ref power_pad_vrange_val_t */
239 uint32_t : 26; /*!< Reserved. */
240} power_pad_vrange_t;
241
242/*!
243 * @brief LVD falling trip voltage value.
244 */
245typedef enum _power_lvd_falling_trip_vol_val
246{
247 kLvdFallingTripVol_720 = 0U, /*!< Voltage 720mV. */
248 kLvdFallingTripVol_735 = 1U, /*!< Voltage 735mV. */
249 kLvdFallingTripVol_750 = 2U, /*!< Voltage 750mV. */
250 kLvdFallingTripVol_765 = 3U, /*!< Voltage 765mV. */
251 kLvdFallingTripVol_780 = 4U, /*!< Voltage 780mV. */
252 kLvdFallingTripVol_795 = 5U, /*!< Voltage 795mV. */
253 kLvdFallingTripVol_810 = 6U, /*!< Voltage 810mV. */
254 kLvdFallingTripVol_825 = 7U, /*!< Voltage 825mV. */
255 kLvdFallingTripVol_840 = 8U, /*!< Voltage 840mV. */
256 kLvdFallingTripVol_855 = 9U, /*!< Voltage 855mV. */
257 kLvdFallingTripVol_870 = 10U, /*!< Voltage 870mV. */
258 kLvdFallingTripVol_885 = 11U, /*!< Voltage 885mV. */
259 kLvdFallingTripVol_900 = 12U, /*!< Voltage 900mV. */
260 kLvdFallingTripVol_915 = 13U, /*!< Voltage 915mV. */
261 kLvdFallingTripVol_930 = 14U, /*!< Voltage 930mV. */
262 kLvdFallingTripVol_945 = 15U, /*!< Voltage 945mV. */
263} power_lvd_falling_trip_vol_val_t;
264
265/*!
266 * @brief Part temperature range.
267 */
268typedef enum _power_part_temp_range
269{
270 kPartTemp_0C_P85C = 0U, /*!< Part temp range 0C - 85C. */
271 kPartTemp_N20C_P85C = 1U, /*!< Part temp range -20C - 85C. */
272} power_part_temp_range_t;
273
274/*!
275 * @brief Voltage operation range.
276 */
277typedef enum _power_volt_op_range
278{
279 kVoltOpLowRange = 0U, /*!< Voltage operation range is (0.7V, 0.8V, 0.9V).
280 Maximum supported CM33 frequency is 220MHz for 0C-85C part and 215MHz for -20C-85C part.
281 Maximum supported DSP frequency is 375MHz for 0C-85C part and 355MHz for -20C-85C part. */
282 kVoltOpFullRange = 1U, /*!< Voltage operation range is (0.7V, 0.8V, 0.9V, 1.0V, 1.13V). This range can support full
283 CM33/DSP speed clarified in Data Sheet. */
284} power_volt_op_range_t;
285
286/*! Frequency levels defined in power library. */
287extern const uint32_t powerLowCm33FreqLevel[2][3];
288extern const uint32_t powerLowDspFreqLevel[2][3];
289extern const uint32_t powerFullCm33FreqLevel[2][5];
290extern const uint32_t powerFullDspFreqLevel[2][5];
291
292/*******************************************************************************
293 * API
294 ******************************************************************************/
295
296#ifdef __cplusplus
297extern "C" {
298#endif
299
300/*!
301 * @brief API to enable PDRUNCFG bit in the Sysctl0. Note that enabling the bit powers down the peripheral
302 *
303 * @param en peripheral for which to enable the PDRUNCFG bit
304 */
305static inline void POWER_EnablePD(pd_bit_t en)
306{
307 /* PDRUNCFGSET */
308 SYSCTL0_PDRCFGSET_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU));
309}
310
311/*!
312 * @brief API to disable PDRUNCFG bit in the Sysctl0. Note that disabling the bit powers up the peripheral
313 *
314 * @param en peripheral for which to disable the PDRUNCFG bit
315 */
316static inline void POWER_DisablePD(pd_bit_t en)
317{
318 /* PDRUNCFGCLR */
319 SYSCTL0_PDRCFGCLR_REG(((uint32_t)en) >> 8UL) = (1UL << (((uint32_t)en) & 0xFFU));
320}
321
322/*!
323 * @brief API to enable deep sleep bit in the ARM Core.
324 */
325static inline void POWER_EnableDeepSleep(void)
326{
327 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
328}
329
330/*!
331 * @brief API to disable deep sleep bit in the ARM Core.
332 */
333static inline void POWER_DisableDeepSleep(void)
334{
335 SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
336}
337
338/**
339 * @brief API to update XTAL oscillator settling time .
340 * @param osc_delay : OSC stabilization time in unit of microsecond
341 */
342void POWER_UpdateOscSettlingTime(uint32_t osc_delay);
343
344/**
345 * @brief API to update on-board PMIC vddcore recovery time.
346 *
347 * NOTE: If LDO is used instead of PMIC, don't call it. Otherwise it must be called to allow power library to well
348 * handle the deep sleep process.
349 *
350 * @param pmic_delay : PMIC stabilization time in unit of microsecond, or PMIC_VDDCORE_RECOVERY_TIME_IGNORE if not
351 * care.
352 */
353void POWER_UpdatePmicRecoveryTime(uint32_t pmic_delay);
354
355/*!
356 * @brief API to apply updated PMC PDRUNCFG bits in the Sysctl0.
357 */
358void POWER_ApplyPD(void);
359
360/**
361 * @brief Clears the PMC event flags state.
362 * @param statusMask : A bitmask of event flags that are to be cleared.
363 */
364void POWER_ClearEventFlags(uint32_t statusMask);
365
366/**
367 * @brief Get the PMC event flags state.
368 * @return PMC FLAGS register value
369 */
370uint32_t POWER_GetEventFlags(void);
371
372/**
373 * @brief Enable the PMC interrupt requests.
374 * @param interruptMask : A bitmask of of interrupts to enable.
375 */
376void POWER_EnableInterrupts(uint32_t interruptMask);
377
378/**
379 * @brief Disable the PMC interrupt requests.
380 * @param interruptMask : A bitmask of of interrupts to disable.
381 */
382void POWER_DisableInterrupts(uint32_t interruptMask);
383
384/**
385 * @brief Set the PMC analog buffer for references or ATX2.
386 * @param enable : Set to true to enable analog buffer for references or ATX2, false to disable.
387 */
388void POWER_SetAnalogBuffer(bool enable);
389
390/**
391 * @brief Get PMIC_MODE pins configure value.
392 * @param reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
393 * @return PMIC_MODE pins value in PDSLEEPCFG0
394 */
395static inline uint32_t POWER_GetPmicMode(pmic_mode_reg_t reg)
396{
397 uint32_t mode = (uint32_t)reg;
398
399 return ((SYSCTL0_TUPLE_REG(mode) & (SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_MASK | SYSCTL0_PDSLEEPCFG0_PMIC_MODE1_MASK)) >>
400 SYSCTL0_PDSLEEPCFG0_PMIC_MODE0_SHIFT);
401}
402
403/**
404 * @brief Get RBB/FBB bit value.
405 * @param reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
406 * @return Current body bias mode
407 */
408static inline body_bias_mode_t POWER_GetBodyBiasMode(pmic_mode_reg_t reg)
409{
410 uint32_t mode = (uint32_t)reg;
411 uint32_t bbMode = (SYSCTL0_TUPLE_REG(mode) & (SYSCTL0_PDSLEEPCFG0_RBB_PD_MASK | SYSCTL0_PDSLEEPCFG0_FBB_PD_MASK)) >>
412 SYSCTL0_PDSLEEPCFG0_RBB_PD_SHIFT;
413
414 return (body_bias_mode_t)bbMode;
415}
416
417/*!
418 * @brief Configure pad voltage level. Wide voltage range cost more power due to enabled voltage detector.
419 *
420 * NOTE: BE CAUTIOUS TO CALL THIS API. IF THE PAD SUPPLY IS BEYOND THE SET RANGE, SILICON MIGHT BE DAMAGED.
421 *
422 * @param config pad voltage range configuration.
423 */
424void POWER_SetPadVolRange(const power_pad_vrange_t *config);
425
426/**
427 * @brief PMC Enter Rbb mode function call
428 */
429#if defined(DOXYGEN_OUTPUT) && DOXYGEN_OUTPUT
430void POWER_EnterRbb(void);
431#else
432AT_QUICKACCESS_SECTION_CODE(void POWER_EnterRbb(void));
433#endif
434
435/**
436 * @brief PMC Enter Fbb mode function call
437 */
438#if defined(DOXYGEN_OUTPUT) && DOXYGEN_OUTPUT
439void POWER_EnterFbb(void);
440#else
441AT_QUICKACCESS_SECTION_CODE(void POWER_EnterFbb(void));
442#endif
443
444/**
445 * @brief PMC exit Rbb & Fbb mode function call
446 */
447#if defined(DOXYGEN_OUTPUT) && DOXYGEN_OUTPUT
448void POWER_EnterNbb(void);
449#else
450AT_QUICKACCESS_SECTION_CODE(void POWER_EnterNbb(void));
451#endif
452
453/**
454 * @brief PMC Set Ldo volatage for particular frequency.
455 * NOTE: The API is only valid when MAINPLLCLKDIV[7:0] and DSPPLLCLKDIV[7:0] are 0.
456 * If LVD falling trip voltage is higher than the required core voltage for particular frequency,
457 * LVD voltage will be decreased to safe level to avoid unexpected LVD reset or interrupt event.
458 * @param tempRange : part temperature range
459 * @param voltOpRange : voltage operation range.
460 * @param cm33Freq : CM33 CPU clock frequency value
461 * @param dspFreq : DSP CPU clock frequency value
462 * @return true for success and false for CPU frequency out of specified voltOpRange.
463 */
464bool POWER_SetLdoVoltageForFreq(power_part_temp_range_t tempRange,
465 power_volt_op_range_t voltOpRange,
466 uint32_t cm33Freq,
467 uint32_t dspFreq);
468
469/*!
470 * @brief Set vddcore low voltage detection falling trip voltage.
471 * @param volt target LVD voltage to set.
472 */
473void POWER_SetLvdFallingTripVoltage(power_lvd_falling_trip_vol_val_t volt);
474
475/**
476 * @brief Get current vddcore low voltage detection falling trip voltage.
477 * @return Current LVD voltage.
478 */
479power_lvd_falling_trip_vol_val_t POWER_GetLvdFallingTripVoltage(void);
480
481/**
482 * @brief Disable low voltage detection, no reset or interrupt is triggered when vddcore voltage drops below
483 * threshold.
484 * NOTE: This API is for internal use only. Application should not touch it.
485 */
486void POWER_DisableLVD(void);
487
488/**
489 * @brief Restore low voltage detection setting.
490 * NOTE: This API is for internal use only. Application should not touch it.
491 */
492void POWER_RestoreLVD(void);
493
494/**
495 * @brief Set PMIC_MODE pins configure value.
496 * @param mode : PMIC MODE pin value
497 * @param reg : PDSLEEPCFG0 or PDRUNCFG0 register offset
498 * @return PMIC_MODE pins value in PDSLEEPCFG0
499 */
500void POWER_SetPmicMode(uint32_t mode, pmic_mode_reg_t reg);
501
502/**
503 * @brief Configures and enters in SLEEP low power mode
504 */
505void POWER_EnterSleep(void);
506
507/**
508 * @brief PMC Deep Sleep function call
509 * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during Deep Sleep mode
510 * selected.
511 */
512#if defined(DOXYGEN_OUTPUT) && DOXYGEN_OUTPUT
513void POWER_EnterDeepSleep(const uint32_t exclude_from_pd[4]);
514#else
515AT_QUICKACCESS_SECTION_CODE(void POWER_EnterDeepSleep(const uint32_t exclude_from_pd[4]));
516#endif
517
518/**
519 * @brief PMC Deep Power Down function call
520 * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during Deep Power Down
521 * mode selected.
522 */
523void POWER_EnterDeepPowerDown(const uint32_t exclude_from_pd[4]);
524
525/**
526 * @brief PMC Full Deep Power Down function call
527 * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during Full Deep Power
528 * Down mode selected.
529 */
530void POWER_EnterFullDeepPowerDown(const uint32_t exclude_from_pd[4]);
531
532/*!
533 * @brief Power Library API to enter different power mode.
534 *
535 * @param mode Power mode to enter.
536 * @param exclude_from_pd Bit mask of the PDRUNCFG0 ~ PDRUNCFG3 that needs to be powered on during power mode selected.
537 */
538void POWER_EnterPowerMode(power_mode_cfg_t mode, const uint32_t exclude_from_pd[4]);
539
540/*!
541 * @brief Enable specific interrupt for wake-up from deep-sleep mode.
542 * Enable the interrupt for wake-up from deep sleep mode.
543 * Some interrupts are typically used in sleep mode only and will not occur during
544 * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
545 * those clocks (significantly increasing power consumption in the reduced power mode),
546 * making these wake-ups possible.
547 * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
548 * @param interrupt The IRQ number.
549 */
550void EnableDeepSleepIRQ(IRQn_Type interrupt);
551
552/*!
553 * @brief Disable specific interrupt for wake-up from deep-sleep mode.
554 * Disable the interrupt for wake-up from deep sleep mode.
555 * Some interrupts are typically used in sleep mode only and will not occur during
556 * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
557 * those clocks (significantly increasing power consumption in the reduced power mode),
558 * making these wake-ups possible.
559 * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
560 * @param interrupt The IRQ number.
561 */
562void DisableDeepSleepIRQ(IRQn_Type interrupt);
563
564/*!
565 * @brief Power Library API to return the library version.
566 *
567 * @return version number of the power library
568 */
569uint32_t POWER_GetLibVersion(void);
570
571#ifdef __cplusplus
572}
573#endif
574
575/**
576 * @}
577 */
578
579#endif /* _FSL_POWER_H_ */
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