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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT633S/drivers/fsl_reset.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT633S/drivers/fsl_reset.h
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index 000000000..f4bc14268
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+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT633S/drivers/fsl_reset.h
@@ -0,0 +1,232 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2018, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_RESET_H_
10#define _FSL_RESET_H_
11
12#include <assert.h>
13#include <stdbool.h>
14#include <stdint.h>
15#include <string.h>
16#include "fsl_device_registers.h"
17
18/*!
19 * @addtogroup reset
20 * @{
21 */
22
23/*******************************************************************************
24 * Definitions
25 ******************************************************************************/
26
27/*! @name Driver version */
28/*@{*/
29/*! @brief reset driver version 2.1.1. */
30#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
31/*@}*/
32
33/*!
34 * @brief Reset control registers index
35 */
36#define RST_CTL0_PSCCTL0 0
37#define RST_CTL0_PSCCTL1 1
38#define RST_CTL0_PSCCTL2 2
39#define RST_CTL1_PSCCTL0 3
40#define RST_CTL1_PSCCTL1 4
41#define RST_CTL1_PSCCTL2 5
42/*!
43 * @brief Enumeration for peripheral reset control bits
44 *
45 * Defines the enumeration for peripheral reset control bits in RSTCLTx registers
46 */
47typedef enum _RSTCTL_RSTn
48{
49 kDSP_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 1U, /**< DSP reset control */
50 kPOWERQUAD_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 8U, /**< POWERQUAD reset control */
51 kCASPER_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 9U, /**< CASPER reset control */
52 kHASHCRYPT_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 10U, /**< HASHCRYPT reset control */
53 kPUF_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 11U, /**< Physical unclonable function reset control */
54 kRNG_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 12U, /**< Random number generator (RNG) reset control */
55 kFLEXSPI_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 16U, /**< FLEXSPI reset control */
56 kUSBHS_PHY_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 20U, /**< High speed USB PHY reset control */
57 kUSBHS_DEVICE_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 21U, /**< High speed USB Device reset control */
58 kUSBHS_HOST_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 22U, /**< High speed USB Host reset control */
59 kUSBHS_SRAM_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 23U, /**< High speed USB SRAM reset control */
60 kSCT_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL0 << 8) | 24U, /**< Standard ctimers reset control */
61
62 kSDIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 2U, /**< SDIO0 reset control */
63 kSDIO1_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 3U, /**< SDIO1 reset control */
64 kACMP0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 15U, /**< Grouped interrupt (PINT) reset control. */
65 kADC0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 16U, /**< ADC0 reset control */
66 kSHSGPIO0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL1 << 8) | 24U, /**< Security HSGPIO 0 reset control */
67
68 kUTICK0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 0U, /**< Micro-tick timer reset control */
69 kWWDT0_RST_SHIFT_RSTn = (RST_CTL0_PSCCTL2 << 8) | 1U, /**< Windowed Watchdog timer 0 reset control */
70
71 kFC0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 8U, /**< Flexcomm Interface 0 reset control */
72 kFC1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 9U, /**< Flexcomm Interface 1 reset control */
73 kFC2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 10U, /**< Flexcomm Interface 2 reset control */
74 kFC3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 11U, /**< Flexcomm Interface 3 reset control */
75 kFC4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 12U, /**< Flexcomm Interface 4 reset control */
76 kFC5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 13U, /**< Flexcomm Interface 5 reset control */
77 kFC6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 14U, /**< Flexcomm Interface 6 reset control */
78 kFC7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 15U, /**< Flexcomm Interface 7 reset control */
79 kFC14_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 22U, /**< Flexcomm Interface 14 reset control */
80 kFC15_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 23U, /**< Flexcomm Interface 15 reset control */
81 kDMIC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 24U, /**< Digital microphone interface reset control */
82 kOSEVENT_TIMER_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL0 << 8) | 27U, /**< Osevent Timer reset control */
83
84 kHSGPIO0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 0U, /**< HSGPIO 0 reset control */
85 kHSGPIO1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 1U, /**< HSGPIO 1 reset control */
86 kHSGPIO2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 2U, /**< HSGPIO 2 reset control */
87 kHSGPIO3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 3U, /**< HSGPIO 3 reset control */
88 kHSGPIO4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 4U, /**< HSGPIO 4 reset control */
89 kHSGPIO5_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 5U, /**< HSGPIO 5 reset control */
90 kHSGPIO6_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 6U, /**< HSGPIO 6 reset control */
91 kHSGPIO7_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 7U, /**< HSGPIO 7 reset control */
92 kCRC_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 16U, /**< CRC reset control */
93 kDMAC0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 23U, /**< DMA Controller 0 reset control */
94 kDMAC1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 24U, /**< DMA Controller 1 reset control */
95 kMU_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 28U, /**< Message Unit reset control */
96 kSEMA_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 29U, /**< Semaphore reset control */
97 kFREQME_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL1 << 8) | 31U, /**< Frequency Measure reset control */
98
99 kCT32B0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 0U, /**< CT32B0 reset control */
100 kCT32B1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 1U, /**< CT32B1 reset control */
101 kCT32B2_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 2U, /**< CT32B3 reset control */
102 kCT32B3_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 3U, /**< CT32B4 reset control */
103 kCT32B4_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 4U, /**< CT32B4 reset control */
104 kMRT0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 8U, /**< Multi-rate timer (MRT) reset control */
105 kWWDT1_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 10U, /**< Windowed Watchdog timer 1 reset control */
106 kI3C0_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 16U, /**< I3C reset control */
107 kPINT_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 30U, /**< GPIO Pin interrupt reset control */
108 kINPUTMUX_RST_SHIFT_RSTn = (RST_CTL1_PSCCTL2 << 8) | 31U, /**< Peripheral input muxes reset control */
109} RSTCTL_RSTn_t;
110
111/** Array initializers with peripheral reset bits **/
112#define ADC_RSTS \
113 { \
114 kADC0_RST_SHIFT_RSTn \
115 } /* Reset bits for ADC peripheral */
116#define CRC_RSTS \
117 { \
118 kCRC_RST_SHIFT_RSTn \
119 } /* Reset bits for CRC peripheral */
120#define DMA_RSTS_N \
121 { \
122 kDMAC0_RST_SHIFT_RSTn, kDMAC1_RST_SHIFT_RSTn \
123 } /* Reset bits for DMA peripheral */
124#define DMIC_RSTS \
125 { \
126 kDMIC_RST_SHIFT_RSTn \
127 } /* Reset bits for ADC peripheral */
128#define FLEXCOMM_RSTS \
129 { \
130 kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
131 kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC14_RST_SHIFT_RSTn, kFC15_RST_SHIFT_RSTn \
132 } /* Reset bits for FLEXCOMM peripheral */
133#define GPIO_RSTS_N \
134 { \
135 kHSGPIO0_RST_SHIFT_RSTn, kHSGPIO1_RST_SHIFT_RSTn, kHSGPIO2_RST_SHIFT_RSTn, kHSGPIO3_RST_SHIFT_RSTn, \
136 kHSGPIO4_RST_SHIFT_RSTn, kHSGPIO5_RST_SHIFT_RSTn, kHSGPIO6_RST_SHIFT_RSTn, kHSGPIO7_RST_SHIFT_RSTn \
137 } /* Reset bits for GPIO peripheral */
138#define I3C_RSTS \
139 { \
140 kI3C0_RST_SHIFT_RSTn \
141 } /* Reset bits for I3C peripheral */
142#define INPUTMUX_RSTS \
143 { \
144 kINPUTMUX_RST_SHIFT_RSTn \
145 } /* Reset bits for INPUTMUX peripheral */
146#define MRT_RSTS \
147 { \
148 kMRT0_RST_SHIFT_RSTn \
149 } /* Reset bits for MRT peripheral */
150#define PINT_RSTS \
151 { \
152 kGPIOINTCTL_RST_SHIFT_RSTn \
153 } /* Reset bits for PINT peripheral */
154#define SCT_RSTS \
155 { \
156 kSCT_RST_SHIFT_RSTn \
157 } /* Reset bits for SCT peripheral */
158#define CTIMER_RSTS \
159 { \
160 kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
161 kCT32B4_RST_SHIFT_RSTn \
162 } /* Reset bits for TIMER peripheral */
163#define USB_RSTS \
164 { \
165 kUSB_RST_SHIFT_RSTn \
166 } /* Reset bits for USB peripheral */
167#define USDHC_RSTS \
168 { \
169 kSDIO0_RST_SHIFT_RSTn, kSDIO1_RST_SHIFT_RSTn \
170 } /* Reset bits for SDIO peripheral */
171#define UTICK_RSTS \
172 { \
173 kUTICK0_RST_SHIFT_RSTn \
174 } /* Reset bits for UTICK peripheral */
175#define WWDT_RSTS \
176 { \
177 kWWDT0_RST_SHIFT_RSTn, kWWDT1_RST_SHIFT_RSTn \
178 } /* Reset bits for WWDT peripheral */
179#define OSTIMER_RSTS \
180 { \
181 kOSEVENT_TIMER_RST_SHIFT_RSTn \
182 } /* Reset bits for OSTIMER peripheral */
183
184/*!
185 * @brief IP reset handle
186 */
187typedef RSTCTL_RSTn_t reset_ip_name_t;
188
189/*******************************************************************************
190 * API
191 ******************************************************************************/
192#if defined(__cplusplus)
193extern "C" {
194#endif
195
196/*!
197 * @brief Assert reset to peripheral.
198 *
199 * Asserts reset signal to specified peripheral module.
200 *
201 * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
202 * and reset bit position in the reset register.
203 */
204void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
205
206/*!
207 * @brief Clear reset to peripheral.
208 *
209 * Clears reset signal to specified peripheral module, allows it to operate.
210 *
211 * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
212 * and reset bit position in the reset register.
213 */
214void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
215
216/*!
217 * @brief Reset peripheral module.
218 *
219 * Reset peripheral module.
220 *
221 * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
222 * and reset bit position in the reset register.
223 */
224void RESET_PeripheralReset(reset_ip_name_t peripheral);
225
226#if defined(__cplusplus)
227}
228#endif
229
230/*! @} */
231
232#endif /* _FSL_RESET_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 05:24:22 +0100