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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_clock.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_inputmux_connections.cmake15
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_power.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_reset.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_clock.c1552
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_clock.h1203
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_dsp.c107
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_dsp.h96
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_iap.c222
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_iap.h726
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_inputmux_connections.h540
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_power.c1087
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_power.h579
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_reset.c164
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_reset.h232
15 files changed, 6571 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_clock.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_clock.cmake
new file mode 100644
index 000000000..154d6a23a
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_clock.cmake
@@ -0,0 +1,16 @@
1if(NOT DRIVER_CLOCK_INCLUDED)
2
3 set(DRIVER_CLOCK_INCLUDED true CACHE BOOL "driver_clock component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 ${CMAKE_CURRENT_LIST_DIR}/fsl_clock.c
7 )
8
9 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
10 ${CMAKE_CURRENT_LIST_DIR}/.
11 )
12
13
14 include(driver_common)
15
16endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_inputmux_connections.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_inputmux_connections.cmake
new file mode 100644
index 000000000..2ac921c5d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_inputmux_connections.cmake
@@ -0,0 +1,15 @@
1if(NOT DRIVER_INPUTMUX_CONNECTIONS_INCLUDED)
2
3 set(DRIVER_INPUTMUX_CONNECTIONS_INCLUDED true CACHE BOOL "driver_inputmux_connections component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 )
7
8 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
9 ${CMAKE_CURRENT_LIST_DIR}/.
10 )
11
12
13 include(driver_common)
14
15endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_power.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_power.cmake
new file mode 100644
index 000000000..267f34840
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_power.cmake
@@ -0,0 +1,16 @@
1if(NOT DRIVER_POWER_INCLUDED)
2
3 set(DRIVER_POWER_INCLUDED true CACHE BOOL "driver_power component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 ${CMAKE_CURRENT_LIST_DIR}/fsl_power.c
7 )
8
9 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
10 ${CMAKE_CURRENT_LIST_DIR}/.
11 )
12
13
14 include(driver_common)
15
16endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_reset.cmake b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_reset.cmake
new file mode 100644
index 000000000..a0a7acf16
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/driver_reset.cmake
@@ -0,0 +1,16 @@
1if(NOT DRIVER_RESET_INCLUDED)
2
3 set(DRIVER_RESET_INCLUDED true CACHE BOOL "driver_reset component is included.")
4
5 target_sources(${MCUX_SDK_PROJECT_NAME} PRIVATE
6 ${CMAKE_CURRENT_LIST_DIR}/fsl_reset.c
7 )
8
9 target_include_directories(${MCUX_SDK_PROJECT_NAME} PRIVATE
10 ${CMAKE_CURRENT_LIST_DIR}/.
11 )
12
13
14 include(driver_common)
15
16endif() \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_clock.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_clock.c
new file mode 100644
index 000000000..c9ebd7374
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_clock.c
@@ -0,0 +1,1552 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#include "fsl_clock.h"
10#include "fsl_common.h"
11/*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14/* Component ID definition, used by tools. */
15#ifndef FSL_COMPONENT_ID
16#define FSL_COMPONENT_ID "platform.drivers.clock"
17#endif
18
19#define OTP_INIT_API ((void (*)(uint32_t src_clk_freq))FSL_ROM_OTP_INIT_ADDR)
20#define OTP_DEINIT_API ((void (*)(void))FSL_ROM_OTP_DEINIT_ADDR)
21#define OTP_FUSE_READ_API ((void (*)(uint32_t addr, uint32_t * data)) FSL_ROM_OTP_FUSE_READ_ADDR)
22/* OTP fuse index. */
23#define FFRO_STABLE_TIME 12
24#define SFRO_STABLE_TIME 13
25#define FIRC_48MHZ_TRIM_TEMPCO 48
26#define FIRC_48MHZ_TRIM_COARSE 49
27#define FIRC_48MHZ_TRIM_FINE 50
28#define FIRC_60MHZ_TRIM_TEMPCO 51
29#define FIRC_60MHZ_TRIM_COARSE 52
30#define FIRC_60MHZ_TRIM_FINE 53
31/*******************************************************************************
32 * Variables
33 ******************************************************************************/
34
35/* External XTAL (OSC) clock frequency. */
36volatile uint32_t g_xtalFreq = 0U;
37/* External CLK_IN pin clock frequency. */
38volatile uint32_t g_clkinFreq = 0U;
39/* External MCLK in (mclk_in) clock frequency. If not used,
40 set this to 0. Otherwise, set it to the exact rate in Hz this pin is
41 being driven at.*/
42volatile uint32_t g_mclkFreq = 0U;
43
44/*******************************************************************************
45 * Code
46 ******************************************************************************/
47/* Clock Selection for IP */
48/**
49 * brief Configure the clock selection muxes.
50 * param connection : Clock to be configured.
51 * return Nothing
52 */
53void CLOCK_AttachClk(clock_attach_id_t connection)
54{
55 bool final_descriptor = false;
56 uint32_t i;
57 volatile uint32_t *pClkSel;
58
59 for (i = 0U; (i < 2U) && (!final_descriptor); i++)
60 {
61 connection =
62 (clock_attach_id_t)(uint32_t)(((uint32_t)connection) >> (i * 16U)); /*!< pick up next descriptor */
63
64 if (((((uint32_t)connection) & 0x80000000U) | ((((uint32_t)connection) & 0x8000U))) != 0UL)
65 {
66 pClkSel = CLKCTL_TUPLE_REG(CLKCTL1, connection);
67 }
68 else
69 {
70 pClkSel = CLKCTL_TUPLE_REG(CLKCTL0, connection);
71 }
72
73 if ((((uint32_t)connection) & 0xfffU) != 0UL)
74 {
75 *pClkSel = CLKCTL_TUPLE_SEL(connection);
76 }
77 else
78 {
79 final_descriptor = true;
80 }
81 }
82}
83/* Set IP Clock divider */
84/**
85 * brief Setup peripheral clock dividers.
86 * param div_name : Clock divider name
87 * param divider : Value to be divided.
88 * return Nothing
89 */
90void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divider)
91{
92 volatile uint32_t *pClkDiv;
93
94 if ((((uint32_t)div_name) & 0x80000000U) != 0UL)
95 {
96 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL1, div_name);
97 }
98 else
99 {
100 pClkDiv = CLKCTL_TUPLE_REG(CLKCTL0, div_name);
101 }
102 /* Reset the divider counter */
103 *pClkDiv |= 1UL << 29U;
104
105 if (divider == 0U) /*!< halt */
106 {
107 *pClkDiv |= 1UL << 30U;
108 }
109 else
110 {
111 *pClkDiv = divider - 1U;
112
113 while (((*pClkDiv) & 0x80000000U) != 0UL)
114 {
115 }
116 }
117}
118/*! @brief Return Frequency of High-Freq output of FRO
119 * @return Frequency of High-Freq output of FRO
120 */
121uint32_t CLOCK_GetFFroFreq(void)
122{
123 uint32_t freq = 0U;
124 /* FFROCTL0 should not be touched by application */
125 switch ((CLKCTL0->FFROCTL0) & CLKCTL0_FFROCTL0_TRIM_RANGE_MASK)
126 {
127 case CLKCTL0_FFROCTL0_TRIM_RANGE(0):
128 freq = CLK_FRO_48MHZ;
129 break;
130 case CLKCTL0_FFROCTL0_TRIM_RANGE(3):
131 freq = CLK_FRO_60MHZ;
132 break;
133 default:
134 freq = 0U;
135 break;
136 }
137 return freq;
138}
139/* Get SYSTEM PLL Clk */
140/*! brief Return Frequency of SYSPLL
141 * return Frequency of SYSPLL
142 */
143uint32_t CLOCK_GetSysPllFreq(void)
144{
145 uint32_t freq = 0U;
146 uint64_t freqTmp;
147
148 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK)
149 {
150 case CLKCTL0_SYSPLL0CLKSEL_SEL(0):
151 freq = CLOCK_GetSFroFreq();
152 break;
153 case CLKCTL0_SYSPLL0CLKSEL_SEL(1):
154 freq = CLOCK_GetXtalInClkFreq();
155 break;
156 case CLKCTL0_SYSPLL0CLKSEL_SEL(2):
157 freq = CLOCK_GetFFroFreq() / 2U;
158 break;
159 default:
160 /* Added comments to prevent the violation of MISRA C-2012 rule. */
161 break;
162 }
163
164 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U)
165 {
166 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
167 freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM));
168 freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT;
169 freq += (uint32_t)freqTmp;
170 }
171 return freq;
172}
173/* Get SYSTEM PLL PFDn Clk */
174/*! brief Get current output frequency of specific System PLL PFD.
175 * param pfd : pfd name to get frequency.
176 * return Frequency of SYSPLL PFD.
177 */
178uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd)
179{
180 uint32_t freq = CLOCK_GetSysPllFreq();
181
182 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U)
183 {
184 switch (pfd)
185 {
186 case kCLOCK_Pfd0:
187 freq =
188 (uint32_t)((uint64_t)freq * 18ULL /
189 ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT));
190 break;
191
192 case kCLOCK_Pfd1:
193 freq =
194 (uint32_t)((uint64_t)freq * 18ULL /
195 ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD1_MASK) >> CLKCTL0_SYSPLL0PFD_PFD1_SHIFT));
196 break;
197
198 case kCLOCK_Pfd2:
199 freq =
200 (uint32_t)((uint64_t)freq * 18ULL /
201 ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD2_MASK) >> CLKCTL0_SYSPLL0PFD_PFD2_SHIFT));
202 break;
203
204 case kCLOCK_Pfd3:
205 freq =
206 (uint32_t)((uint64_t)freq * 18ULL /
207 ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD3_MASK) >> CLKCTL0_SYSPLL0PFD_PFD3_SHIFT));
208 break;
209
210 default:
211 freq = 0U;
212 break;
213 }
214 }
215
216 return freq;
217}
218static uint32_t CLOCK_GetMainPllClkFreq(void)
219{
220 return CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U);
221}
222static uint32_t CLOCK_GetDspPllClkFreq(void)
223{
224 return CLOCK_GetSysPfdFreq(kCLOCK_Pfd1) / ((CLKCTL0->DSPPLLCLKDIV & CLKCTL0_DSPPLLCLKDIV_DIV_MASK) + 1U);
225}
226static uint32_t CLOCK_GetAux0PllClkFreq(void)
227{
228 return CLOCK_GetSysPfdFreq(kCLOCK_Pfd2) / ((CLKCTL0->AUX0PLLCLKDIV & CLKCTL0_AUX0PLLCLKDIV_DIV_MASK) + 1U);
229}
230static uint32_t CLOCK_GetAux1PllClkFreq(void)
231{
232 return CLOCK_GetSysPfdFreq(kCLOCK_Pfd3) / ((CLKCTL0->AUX1PLLCLKDIV & CLKCTL0_AUX1PLLCLKDIV_DIV_MASK) + 1U);
233}
234/* Get AUDIO PLL Clk */
235/*! brief Return Frequency of AUDIO PLL
236 * return Frequency of AUDIO PLL
237 */
238uint32_t CLOCK_GetAudioPllFreq(void)
239{
240 uint32_t freq = 0U;
241 uint64_t freqTmp;
242
243 switch ((CLKCTL1->AUDIOPLL0CLKSEL) & CLKCTL1_AUDIOPLL0CLKSEL_SEL_MASK)
244 {
245 case CLKCTL1_AUDIOPLL0CLKSEL_SEL(0):
246 freq = CLOCK_GetSFroFreq();
247 break;
248 case CLKCTL1_AUDIOPLL0CLKSEL_SEL(1):
249 freq = CLOCK_GetXtalInClkFreq();
250 break;
251 case CLKCTL1_AUDIOPLL0CLKSEL_SEL(2):
252 freq = CLOCK_GetFFroFreq() / 2U;
253 break;
254 default:
255 freq = 0U;
256 break;
257 }
258
259 if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0UL)
260 {
261 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
262 freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL1->AUDIOPLL0NUM))) / ((uint64_t)(CLKCTL1->AUDIOPLL0DENOM));
263 freq *= ((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) >> CLKCTL1_AUDIOPLL0CTL0_MULT_SHIFT;
264 freq += (uint32_t)freqTmp;
265 }
266 return freq;
267}
268/* Get AUDIO PLL PFDn Clk */
269/*! brief Get current output frequency of specific Audio PLL PFD.
270 * param pfd : pfd name to get frequency.
271 * return Frequency of AUDIO PLL PFD.
272 */
273uint32_t CLOCK_GetAudioPfdFreq(clock_pfd_t pfd)
274{
275 uint32_t freq = CLOCK_GetAudioPllFreq();
276
277 if (((CLKCTL1->AUDIOPLL0CTL0) & CLKCTL1_AUDIOPLL0CTL0_BYPASS_MASK) == 0UL)
278 {
279 switch (pfd)
280 {
281 case kCLOCK_Pfd0:
282 freq = (uint32_t)(
283 (uint64_t)freq * 18ULL /
284 ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD0_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD0_SHIFT));
285 break;
286
287 case kCLOCK_Pfd1:
288 freq = (uint32_t)(
289 (uint64_t)freq * 18ULL /
290 ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD1_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD1_SHIFT));
291 break;
292
293 case kCLOCK_Pfd2:
294 freq = (uint32_t)(
295 (uint64_t)freq * 18ULL /
296 ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD2_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD2_SHIFT));
297 break;
298
299 case kCLOCK_Pfd3:
300 freq = (uint32_t)(
301 (uint64_t)freq * 18ULL /
302 ((CLKCTL1->AUDIOPLL0PFD & CLKCTL1_AUDIOPLL0PFD_PFD3_MASK) >> CLKCTL1_AUDIOPLL0PFD_PFD3_SHIFT));
303 break;
304
305 default:
306 freq = 0U;
307 break;
308 }
309 }
310
311 return freq;
312}
313static uint32_t CLOCK_GetAudioPllClkFreq(void)
314{
315 return CLOCK_GetAudioPfdFreq(kCLOCK_Pfd0) / ((CLKCTL1->AUDIOPLLCLKDIV & CLKCTL1_AUDIOPLLCLKDIV_DIV_MASK) + 1U);
316}
317/* Get MAIN Clk */
318/*! brief Return Frequency of main clk
319 * return Frequency of main clk
320 */
321uint32_t CLOCK_GetMainClkFreq(void)
322{
323 uint32_t freq = 0U;
324
325 switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK)
326 {
327 case CLKCTL0_MAINCLKSELB_SEL(0):
328 switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK)
329 {
330 case CLKCTL0_MAINCLKSELA_SEL(0):
331 freq = CLOCK_GetFFroFreq() / 4U;
332 break;
333 case CLKCTL0_MAINCLKSELA_SEL(1):
334 freq = CLOCK_GetXtalInClkFreq();
335 break;
336 case CLKCTL0_MAINCLKSELA_SEL(2):
337 freq = CLOCK_GetLpOscFreq();
338 break;
339 case CLKCTL0_MAINCLKSELA_SEL(3):
340 freq = CLOCK_GetFFroFreq();
341 break;
342 default:
343 freq = 0U;
344 break;
345 }
346 break;
347
348 case CLKCTL0_MAINCLKSELB_SEL(1):
349 freq = CLOCK_GetSFroFreq();
350 break;
351
352 case CLKCTL0_MAINCLKSELB_SEL(2):
353 freq = CLOCK_GetMainPllClkFreq();
354 break;
355
356 case CLKCTL0_MAINCLKSELB_SEL(3):
357 freq = CLOCK_GetOsc32KFreq();
358 break;
359
360 default:
361 freq = 0U;
362 break;
363 }
364
365 return freq;
366}
367/* Get DSP MAIN Clk */
368/*! brief Return Frequency of DSP main clk
369 * return Frequency of DSP main clk
370 */
371uint32_t CLOCK_GetDspMainClkFreq(void)
372{
373 uint32_t freq = 0U;
374
375 switch ((CLKCTL1->DSPCPUCLKSELB) & CLKCTL1_DSPCPUCLKSELB_SEL_MASK)
376 {
377 case CLKCTL1_DSPCPUCLKSELB_SEL(0):
378 switch ((CLKCTL1->DSPCPUCLKSELA) & CLKCTL1_DSPCPUCLKSELA_SEL_MASK)
379 {
380 case CLKCTL1_DSPCPUCLKSELA_SEL(0):
381 freq = CLOCK_GetFFroFreq();
382 break;
383 case CLKCTL1_DSPCPUCLKSELA_SEL(1):
384 freq = CLOCK_GetXtalInClkFreq();
385 break;
386 case CLKCTL1_DSPCPUCLKSELA_SEL(2):
387 freq = CLOCK_GetLpOscFreq();
388 break;
389 case CLKCTL1_DSPCPUCLKSELA_SEL(3):
390 freq = CLOCK_GetSFroFreq();
391 break;
392 default:
393 freq = 0U;
394 break;
395 }
396 break;
397
398 case CLKCTL1_DSPCPUCLKSELB_SEL(1):
399 freq = CLOCK_GetMainPllClkFreq();
400 break;
401
402 case CLKCTL1_DSPCPUCLKSELB_SEL(2):
403 freq = CLOCK_GetDspPllClkFreq();
404 break;
405
406 case CLKCTL1_DSPCPUCLKSELB_SEL(3):
407 freq = CLOCK_GetOsc32KFreq();
408 break;
409
410 default:
411 freq = 0U;
412 break;
413 }
414
415 return freq;
416}
417/* Get ADC Clk */
418/*! brief Return Frequency of Adc Clock
419 * return Frequency of Adc Clock.
420 */
421uint32_t CLOCK_GetAdcClkFreq(void)
422{
423 uint32_t freq = 0U;
424
425 switch ((CLKCTL0->ADC0FCLKSEL1) & CLKCTL0_ADC0FCLKSEL1_SEL_MASK)
426 {
427 case CLKCTL0_ADC0FCLKSEL1_SEL(0):
428 switch ((CLKCTL0->ADC0FCLKSEL0) & CLKCTL0_ADC0FCLKSEL0_SEL_MASK)
429 {
430 case CLKCTL0_ADC0FCLKSEL0_SEL(0):
431 freq = CLOCK_GetSFroFreq();
432 break;
433 case CLKCTL0_ADC0FCLKSEL0_SEL(1):
434 freq = CLOCK_GetXtalInClkFreq();
435 break;
436 case CLKCTL0_ADC0FCLKSEL0_SEL(2):
437 freq = CLOCK_GetLpOscFreq();
438 break;
439 case CLKCTL0_ADC0FCLKSEL0_SEL(3):
440 freq = CLOCK_GetFFroFreq();
441 break;
442 default:
443 freq = 0U;
444 break;
445 }
446 break;
447
448 case CLKCTL0_ADC0FCLKSEL1_SEL(1):
449 freq = CLOCK_GetMainPllClkFreq();
450 break;
451
452 case CLKCTL0_ADC0FCLKSEL1_SEL(3):
453 freq = CLOCK_GetAux0PllClkFreq();
454 break;
455
456 case CLKCTL0_ADC0FCLKSEL1_SEL(5):
457 freq = CLOCK_GetAux1PllClkFreq();
458 break;
459
460 default:
461 freq = 0U;
462 break;
463 }
464
465 return freq / ((CLKCTL0->ADC0FCLKDIV & CLKCTL0_ADC0FCLKDIV_DIV_MASK) + 1U);
466}
467/* Get CLOCK OUT Clk */
468/*! brief Return Frequency of ClockOut
469 * return Frequency of ClockOut
470 */
471uint32_t CLOCK_GetClockOutClkFreq(void)
472{
473 uint32_t freq = 0U;
474
475 switch ((CLKCTL1->CLKOUTSEL1) & CLKCTL1_CLKOUTSEL1_SEL_MASK)
476 {
477 case CLKCTL1_CLKOUTSEL1_SEL(0):
478 switch ((CLKCTL1->CLKOUTSEL0) & CLKCTL1_CLKOUTSEL0_SEL_MASK)
479 {
480 case CLKCTL1_CLKOUTSEL0_SEL(0):
481 freq = CLOCK_GetSFroFreq();
482 break;
483 case CLKCTL1_CLKOUTSEL0_SEL(1):
484 freq = CLOCK_GetXtalInClkFreq();
485 break;
486 case CLKCTL1_CLKOUTSEL0_SEL(2):
487 freq = CLOCK_GetLpOscFreq();
488 break;
489 case CLKCTL1_CLKOUTSEL0_SEL(3):
490 freq = CLOCK_GetFFroFreq();
491 break;
492 case CLKCTL1_CLKOUTSEL0_SEL(4):
493 freq = CLOCK_GetMainClkFreq();
494 break;
495 case CLKCTL1_CLKOUTSEL0_SEL(6):
496 freq = CLOCK_GetDspMainClkFreq();
497 break;
498 default:
499 freq = 0U;
500 break;
501 }
502 break;
503
504 case CLKCTL1_CLKOUTSEL1_SEL(1):
505 freq = CLOCK_GetMainPllClkFreq();
506 break;
507
508 case CLKCTL1_CLKOUTSEL1_SEL(2):
509 freq = CLOCK_GetAux0PllClkFreq();
510 break;
511
512 case CLKCTL1_CLKOUTSEL1_SEL(3):
513 freq = CLOCK_GetDspPllClkFreq();
514 break;
515
516 case CLKCTL1_CLKOUTSEL1_SEL(4):
517 freq = CLOCK_GetAux1PllClkFreq();
518 break;
519
520 case CLKCTL1_CLKOUTSEL1_SEL(5):
521 freq = CLOCK_GetAudioPllClkFreq();
522 break;
523
524 case CLKCTL1_CLKOUTSEL1_SEL(6):
525 freq = CLOCK_GetOsc32KFreq();
526 break;
527
528 default:
529 freq = 0U;
530 break;
531 }
532
533 return freq / ((CLKCTL1->CLKOUTDIV & CLKCTL1_CLKOUTDIV_DIV_MASK) + 1U);
534}
535/* Get FRG Clk */
536/*! brief Return Input frequency for the Fractional baud rate generator
537 * return Input Frequency for FRG
538 */
539uint32_t CLOCK_GetFRGClock(uint32_t id)
540{
541 uint32_t freq = 0U;
542 uint32_t frgPllDiv = 1U;
543 uint32_t clkSel = 0U;
544 uint32_t frgDiv = 0U;
545 uint32_t frgMul = 0U;
546
547 if (id <= 7UL)
548 {
549 clkSel = CLKCTL1->FLEXCOMM[id].FRGCLKSEL & CLKCTL1_FRGCLKSEL_SEL_MASK;
550 frgMul = ((CLKCTL1->FLEXCOMM[id].FRGCTL) & CLKCTL1_FRGCTL_MULT_MASK) >> CLKCTL1_FRGCTL_MULT_SHIFT;
551 frgDiv = ((CLKCTL1->FLEXCOMM[id].FRGCTL) & CLKCTL1_FRGCTL_DIV_MASK) >> CLKCTL1_FRGCTL_DIV_SHIFT;
552 }
553 else if (id == 14UL)
554 {
555 clkSel = CLKCTL1->FRG14CLKSEL & CLKCTL1_FRG14CLKSEL_SEL_MASK;
556 frgMul = ((CLKCTL1->FRG14CTL) & CLKCTL1_FRGCTL_MULT_MASK) >> CLKCTL1_FRGCTL_MULT_SHIFT;
557 frgDiv = ((CLKCTL1->FRG14CTL) & CLKCTL1_FRGCTL_DIV_MASK) >> CLKCTL1_FRGCTL_DIV_SHIFT;
558 }
559 else if (id == 15UL)
560 {
561 clkSel = CLKCTL1->FRG15CLKSEL & CLKCTL1_FRG14CLKSEL_SEL_MASK;
562 frgMul = ((CLKCTL1->FRG15CTL) & CLKCTL1_FRGCTL_MULT_MASK) >> CLKCTL1_FRGCTL_MULT_SHIFT;
563 frgDiv = ((CLKCTL1->FRG15CTL) & CLKCTL1_FRGCTL_DIV_MASK) >> CLKCTL1_FRGCTL_DIV_SHIFT;
564 }
565 else
566 {
567 assert(false);
568 }
569
570 switch (clkSel)
571 {
572 case CLKCTL1_FRGCLKSEL_SEL(0):
573 freq = CLOCK_GetMainClkFreq();
574 break;
575
576 case CLKCTL1_FRGCLKSEL_SEL(1):
577 frgPllDiv = (CLKCTL1->FRGPLLCLKDIV & CLKCTL1_FRGPLLCLKDIV_DIV_MASK) + 1U;
578 freq = CLOCK_GetMainPllClkFreq() / frgPllDiv;
579 break;
580
581 case CLKCTL1_FRGCLKSEL_SEL(2):
582 freq = CLOCK_GetSFroFreq();
583 break;
584
585 case CLKCTL1_FRGCLKSEL_SEL(3):
586 freq = CLOCK_GetFFroFreq();
587 break;
588
589 default:
590 freq = 0U;
591 break;
592 }
593
594 return (uint32_t)(((uint64_t)freq * ((uint64_t)frgDiv + 1ULL)) / (frgMul + frgDiv + 1UL));
595}
596/* Get FLEXCOMM Clk */
597/*! brief Return Frequency of Flexcomm functional Clock
598 * param id : flexcomm index to get frequency.
599 * return Frequency of Flexcomm functional Clock
600 */
601uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id)
602{
603 uint32_t freq = 0U;
604 uint32_t clkSel = 0U;
605
606 if (id <= 7UL)
607 {
608 clkSel = CLKCTL1->FLEXCOMM[id].FCFCLKSEL;
609 }
610 else if (id == 14UL)
611 {
612 clkSel = CLKCTL1->FC14FCLKSEL;
613 }
614 else if (id == 15UL)
615 {
616 clkSel = CLKCTL1->FC15FCLKSEL;
617 }
618 else
619 {
620 assert(false);
621 }
622
623 switch (clkSel)
624 {
625 case CLKCTL1_FCFCLKSEL_SEL(0):
626 freq = CLOCK_GetSFroFreq();
627 break;
628
629 case CLKCTL1_FCFCLKSEL_SEL(1):
630 freq = CLOCK_GetFFroFreq();
631 break;
632
633 case CLKCTL1_FCFCLKSEL_SEL(2):
634 freq = CLOCK_GetAudioPllClkFreq();
635 break;
636
637 case CLKCTL1_FCFCLKSEL_SEL(3):
638 freq = CLOCK_GetMclkInClkFreq();
639 break;
640
641 case CLKCTL1_FCFCLKSEL_SEL(4):
642 freq = CLOCK_GetFRGClock(id);
643 break;
644
645 default:
646 freq = 0U;
647 break;
648 }
649
650 return freq;
651}
652/* Get CTIMER Clk */
653/*! brief Return Frequency of Ctimer Clock
654 * param id : ctimer index to get frequency.
655 * return Frequency of Ctimer Clock
656 */
657uint32_t CLOCK_GetCtimerClkFreq(uint32_t id)
658{
659 uint32_t freq = 0U;
660
661 switch ((CLKCTL1->CT32BITFCLKSEL[id]) & CLKCTL1_CT32BITFCLKSEL_SEL_MASK)
662 {
663 case CLKCTL1_CT32BITFCLKSEL_SEL(0):
664 freq = CLOCK_GetMainClkFreq();
665 break;
666
667 case CLKCTL1_CT32BITFCLKSEL_SEL(1):
668 freq = CLOCK_GetSFroFreq();
669 break;
670
671 case CLKCTL1_CT32BITFCLKSEL_SEL(2):
672 freq = CLOCK_GetFFroFreq();
673 break;
674
675 case CLKCTL1_CT32BITFCLKSEL_SEL(3):
676 freq = CLOCK_GetAudioPllClkFreq();
677 break;
678
679 case CLKCTL1_CT32BITFCLKSEL_SEL(4):
680 freq = CLOCK_GetMclkInClkFreq();
681 break;
682
683 case CLKCTL1_CT32BITFCLKSEL_SEL(5):
684 freq = CLOCK_GetLpOscFreq();
685 break;
686
687 default:
688 freq = 0U;
689 break;
690 }
691
692 return freq;
693}
694/* Get FLEXSPI Clk */
695/*! brief Return Frequency of FLEXSPI Clock
696 * return Frequency of FLEXSPI.
697 */
698uint32_t CLOCK_GetFlexspiClkFreq(void)
699{
700 uint32_t freq = 0U;
701
702 switch ((CLKCTL0->FLEXSPIFCLKSEL) & CLKCTL0_FLEXSPIFCLKSEL_SEL_MASK)
703 {
704 case CLKCTL0_FLEXSPIFCLKSEL_SEL(0):
705 freq = CLOCK_GetMainClkFreq();
706 break;
707
708 case CLKCTL0_FLEXSPIFCLKSEL_SEL(1):
709 freq = CLOCK_GetMainPllClkFreq();
710 break;
711
712 case CLKCTL0_FLEXSPIFCLKSEL_SEL(2):
713 freq = CLOCK_GetAux0PllClkFreq();
714 break;
715
716 case CLKCTL0_FLEXSPIFCLKSEL_SEL(3):
717 freq = CLOCK_GetFFroFreq();
718 break;
719
720 case CLKCTL0_FLEXSPIFCLKSEL_SEL(4):
721 freq = CLOCK_GetAux1PllClkFreq();
722 break;
723
724 default:
725 freq = 0U;
726 break;
727 }
728
729 return freq / ((CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) + 1U);
730}
731
732/* Get SCT Clk */
733/*! brief Return Frequency of sct
734 * return Frequency of sct clk
735 */
736uint32_t CLOCK_GetSctClkFreq(void)
737{
738 uint32_t freq = 0U;
739
740 switch ((CLKCTL0->SCTFCLKSEL) & CLKCTL0_SCTFCLKSEL_SEL_MASK)
741 {
742 case CLKCTL0_SCTFCLKSEL_SEL(0):
743 freq = CLOCK_GetMainClkFreq();
744 break;
745
746 case CLKCTL0_SCTFCLKSEL_SEL(1):
747 freq = CLOCK_GetMainPllClkFreq();
748 break;
749
750 case CLKCTL0_SCTFCLKSEL_SEL(2):
751 freq = CLOCK_GetAux0PllClkFreq();
752 break;
753
754 case CLKCTL0_SCTFCLKSEL_SEL(3):
755 freq = CLOCK_GetFFroFreq();
756 break;
757
758 case CLKCTL0_SCTFCLKSEL_SEL(4):
759 freq = CLOCK_GetAux1PllClkFreq();
760 break;
761
762 case CLKCTL0_SCTFCLKSEL_SEL(5):
763 freq = CLOCK_GetAudioPllClkFreq();
764 break;
765
766 default:
767 freq = 0U;
768 break;
769 }
770
771 return freq / ((CLKCTL0->SCTFCLKDIV & CLKCTL0_SCTFCLKDIV_DIV_MASK) + 1U);
772}
773
774/*! brief Return Frequency of mclk Out
775 * return Frequency of mclk Out clk
776 */
777uint32_t CLOCK_GetMclkClkFreq(void)
778{
779 uint32_t freq = 0U;
780
781 if (CLKCTL1->AUDIOMCLKSEL == 0U)
782 {
783 freq = CLOCK_GetFFroFreq();
784 }
785 else if (CLKCTL1->AUDIOMCLKSEL == 1U)
786 {
787 freq = CLOCK_GetAudioPllClkFreq();
788 }
789 else
790 {
791 /* Added comments to prevent the violation of MISRA C-2012 rule 15.7. */
792 }
793
794 return freq / ((CLKCTL1->AUDIOMCLKDIV & CLKCTL1_AUDIOMCLKDIV_DIV_MASK) + 1U);
795}
796
797/*! @brief Return Frequency of WDT clk
798 * @param id : WDT index to get frequency.
799 * @return Frequency of WDT clk
800 */
801uint32_t CLOCK_GetWdtClkFreq(uint32_t id)
802{
803 uint32_t freq = 0U;
804
805 assert(id <= 1UL);
806
807 if (id == 0UL)
808 {
809 if ((CLKCTL0->WDT0FCLKSEL & CLKCTL0_WDT0FCLKSEL_SEL_MASK) == CLKCTL0_WDT0FCLKSEL_SEL(0))
810 {
811 freq = CLOCK_GetLpOscFreq();
812 }
813 else
814 {
815 freq = CLOCK_GetMainClkFreq();
816 }
817 }
818 else
819 {
820 if ((CLKCTL1->WDT1FCLKSEL & CLKCTL1_WDT1FCLKSEL_SEL_MASK) == CLKCTL1_WDT1FCLKSEL_SEL(0))
821 {
822 freq = CLOCK_GetLpOscFreq();
823 }
824 else
825 {
826 freq = CLOCK_GetMainClkFreq();
827 }
828 }
829
830 return freq;
831}
832
833/*! brief Return Frequency of systick clk
834 * return Frequency of systick clk
835 */
836uint32_t CLOCK_GetSystickClkFreq(void)
837{
838 uint32_t freq = 0U;
839
840 switch (CLKCTL0->SYSTICKFCLKSEL)
841 {
842 case CLKCTL0_SYSTICKFCLKSEL_SEL(0):
843 freq = CLOCK_GetMainClkFreq() / ((CLKCTL0->SYSTICKFCLKDIV & CLKCTL0_SYSTICKFCLKDIV_DIV_MASK) + 1U);
844 break;
845
846 case CLKCTL0_SYSTICKFCLKSEL_SEL(1):
847 freq = CLOCK_GetLpOscFreq();
848 break;
849
850 case CLKCTL0_SYSTICKFCLKSEL_SEL(2):
851 freq = CLOCK_GetOsc32KFreq();
852 break;
853
854 case CLKCTL0_SYSTICKFCLKSEL_SEL(3):
855 freq = CLOCK_GetSFroFreq();
856 break;
857
858 default:
859 freq = 0U;
860 break;
861 }
862
863 return freq;
864}
865
866/*! brief Return Frequency of SDIO clk
867 * param id : SDIO index to get frequency.
868 * return Frequency of SDIO clk
869 */
870uint32_t CLOCK_GetSdioClkFreq(uint32_t id)
871{
872 uint32_t freq = 0U;
873 volatile uint32_t *pClkSel;
874 volatile uint32_t *pClkDiv;
875
876 assert(id <= 1U);
877
878 if (id == 0UL)
879 {
880 pClkSel = &CLKCTL0->SDIO0FCLKSEL;
881 pClkDiv = &CLKCTL0->SDIO0FCLKDIV;
882 }
883 else
884 {
885 pClkSel = &CLKCTL0->SDIO1FCLKSEL;
886 pClkDiv = &CLKCTL0->SDIO1FCLKDIV;
887 }
888
889 switch ((*pClkSel) & CLKCTL0_SDIO0FCLKSEL_SEL_MASK)
890 {
891 case CLKCTL0_SDIO0FCLKSEL_SEL(0):
892 freq = CLOCK_GetMainClkFreq();
893 break;
894
895 case CLKCTL0_SDIO0FCLKSEL_SEL(1):
896 freq = CLOCK_GetMainPllClkFreq();
897 break;
898
899 case CLKCTL0_SDIO0FCLKSEL_SEL(2):
900 freq = CLOCK_GetAux0PllClkFreq();
901 break;
902
903 case CLKCTL0_SDIO0FCLKSEL_SEL(3):
904 freq = CLOCK_GetFFroFreq();
905 break;
906
907 case CLKCTL0_SDIO0FCLKSEL_SEL(4):
908 freq = CLOCK_GetAux1PllClkFreq();
909 break;
910
911 default:
912 freq = 0U;
913 break;
914 }
915
916 return freq / (((*pClkDiv) & CLKCTL0_SDIO0FCLKDIV_DIV_MASK) + 1U);
917}
918
919/*! @brief Return Frequency of I3C clk
920 * @return Frequency of I3C clk
921 */
922uint32_t CLOCK_GetI3cClkFreq(void)
923{
924 uint32_t freq = 0U;
925
926 switch ((CLKCTL1->I3C0FCLKSEL) & CLKCTL1_I3C0FCLKSEL_SEL_MASK)
927 {
928 case CLKCTL1_I3C0FCLKSEL_SEL(0):
929 freq = CLOCK_GetMainClkFreq();
930 break;
931
932 case CLKCTL1_I3C0FCLKSEL_SEL(1):
933 freq = CLOCK_GetFFroFreq();
934 break;
935
936 default:
937 freq = 0U;
938 break;
939 }
940
941 return freq / ((CLKCTL1->I3C0FCLKDIV & CLKCTL1_I3C0FCLKDIV_DIV_MASK) + 1U);
942}
943
944/*! brief Return Frequency of USB clk
945 * return Frequency of USB clk
946 */
947uint32_t CLOCK_GetUsbClkFreq(void)
948{
949 uint32_t freq = 0U;
950
951 if (CLKCTL0->USBHSFCLKSEL == 0U)
952 {
953 freq = CLOCK_GetXtalInClkFreq();
954 }
955 else if (CLKCTL0->USBHSFCLKSEL == 1U)
956 {
957 freq = CLOCK_GetMainClkFreq();
958 }
959 else
960 {
961 /* Add comments to prevent the violation of MISRA C-2012 rule 15.7 */
962 }
963
964 return freq / ((CLKCTL0->USBHSFCLKDIV & 0xffU) + 1U);
965}
966
967/*! brief Return Frequency of DMIC clk
968 * return Frequency of DMIC clk
969 */
970uint32_t CLOCK_GetDmicClkFreq(void)
971{
972 uint32_t freq = 0U;
973
974 switch ((CLKCTL1->DMIC0FCLKSEL) & CLKCTL1_DMIC0FCLKSEL_SEL_MASK)
975 {
976 case CLKCTL1_DMIC0FCLKSEL_SEL(0):
977 freq = CLOCK_GetSFroFreq();
978 break;
979
980 case CLKCTL1_DMIC0FCLKSEL_SEL(1):
981 freq = CLOCK_GetFFroFreq();
982 break;
983
984 case CLKCTL1_DMIC0FCLKSEL_SEL(2):
985 freq = CLOCK_GetAudioPllClkFreq();
986 break;
987
988 case CLKCTL1_DMIC0FCLKSEL_SEL(3):
989 freq = CLOCK_GetMclkInClkFreq();
990 break;
991
992 case CLKCTL1_DMIC0FCLKSEL_SEL(4):
993 freq = CLOCK_GetLpOscFreq();
994 break;
995
996 case CLKCTL1_DMIC0FCLKSEL_SEL(5):
997 freq = CLOCK_GetWakeClk32KFreq();
998 break;
999
1000 default:
1001 freq = 0U;
1002 break;
1003 }
1004
1005 return freq / ((CLKCTL1->DMIC0FCLKDIV & 0xffU) + 1U);
1006}
1007
1008/*! brief Return Frequency of ACMP clk
1009 * return Frequency of ACMP clk
1010 */
1011uint32_t CLOCK_GetAcmpClkFreq(void)
1012{
1013 uint32_t freq = 0U;
1014
1015 switch ((CLKCTL1->ACMP0FCLKSEL) & CLKCTL1_ACMP0FCLKSEL_SEL_MASK)
1016 {
1017 case CLKCTL1_ACMP0FCLKSEL_SEL(0):
1018 freq = CLOCK_GetMainClkFreq();
1019 break;
1020
1021 case CLKCTL1_ACMP0FCLKSEL_SEL(1):
1022 freq = CLOCK_GetSFroFreq();
1023 break;
1024
1025 case CLKCTL1_ACMP0FCLKSEL_SEL(2):
1026 freq = CLOCK_GetFFroFreq();
1027 break;
1028
1029 case CLKCTL1_ACMP0FCLKSEL_SEL(3):
1030 freq = CLOCK_GetAux0PllClkFreq();
1031 break;
1032
1033 case CLKCTL1_ACMP0FCLKSEL_SEL(4):
1034 freq = CLOCK_GetAux1PllClkFreq();
1035 break;
1036
1037 default:
1038 freq = 0U;
1039 break;
1040 }
1041
1042 return freq / ((CLKCTL1->ACMP0FCLKDIV & CLKCTL1_ACMP0FCLKDIV_DIV_MASK) + 1U);
1043}
1044
1045/* Get IP Clk */
1046/*! brief Return Frequency of selected clock
1047 * return Frequency of selected clock
1048 */
1049uint32_t CLOCK_GetFreq(clock_name_t clockName)
1050{
1051 uint32_t freq = 0U;
1052
1053 switch (clockName)
1054 {
1055 case kCLOCK_CoreSysClk:
1056 case kCLOCK_BusClk:
1057 freq = CLOCK_GetMainClkFreq() / ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK) + 1U);
1058 break;
1059 case kCLOCK_MclkClk:
1060 freq = CLOCK_GetMclkClkFreq();
1061 break;
1062 case kCLOCK_ClockOutClk:
1063 freq = CLOCK_GetClockOutClkFreq();
1064 break;
1065 case kCLOCK_AdcClk:
1066 freq = CLOCK_GetAdcClkFreq();
1067 break;
1068 case kCLOCK_FlexspiClk:
1069 freq = CLOCK_GetFlexspiClkFreq();
1070 break;
1071 case kCLOCK_SctClk:
1072 freq = CLOCK_GetSctClkFreq();
1073 break;
1074 case kCLOCK_Wdt0Clk:
1075 freq = CLOCK_GetWdtClkFreq(0U);
1076 break;
1077 case kCLOCK_Wdt1Clk:
1078 freq = CLOCK_GetWdtClkFreq(1U);
1079 break;
1080 case kCLOCK_SystickClk:
1081 freq = CLOCK_GetSystickClkFreq();
1082 break;
1083 case kCLOCK_Sdio0Clk:
1084 freq = CLOCK_GetSdioClkFreq(0U);
1085 break;
1086 case kCLOCK_Sdio1Clk:
1087 freq = CLOCK_GetSdioClkFreq(1U);
1088 break;
1089 case kCLOCK_I3cClk:
1090 freq = CLOCK_GetI3cClkFreq();
1091 break;
1092 case kCLOCK_UsbClk:
1093 freq = CLOCK_GetUsbClkFreq();
1094 break;
1095 case kCLOCK_DmicClk:
1096 freq = CLOCK_GetDmicClkFreq();
1097 break;
1098 case kCLOCK_DspCpuClk:
1099 freq = CLOCK_GetDspMainClkFreq() / ((CLKCTL1->DSPCPUCLKDIV & CLKCTL1_DSPCPUCLKDIV_DIV_MASK) + 1U);
1100 break;
1101 case kCLOCK_AcmpClk:
1102 freq = CLOCK_GetAcmpClkFreq();
1103 break;
1104 case kCLOCK_Flexcomm0Clk:
1105 freq = CLOCK_GetFlexCommClkFreq(0U);
1106 break;
1107 case kCLOCK_Flexcomm1Clk:
1108 freq = CLOCK_GetFlexCommClkFreq(1U);
1109 break;
1110 case kCLOCK_Flexcomm2Clk:
1111 freq = CLOCK_GetFlexCommClkFreq(2U);
1112 break;
1113 case kCLOCK_Flexcomm3Clk:
1114 freq = CLOCK_GetFlexCommClkFreq(3U);
1115 break;
1116 case kCLOCK_Flexcomm4Clk:
1117 freq = CLOCK_GetFlexCommClkFreq(4U);
1118 break;
1119 case kCLOCK_Flexcomm5Clk:
1120 freq = CLOCK_GetFlexCommClkFreq(5U);
1121 break;
1122 case kCLOCK_Flexcomm6Clk:
1123 freq = CLOCK_GetFlexCommClkFreq(6U);
1124 break;
1125 case kCLOCK_Flexcomm7Clk:
1126 freq = CLOCK_GetFlexCommClkFreq(7U);
1127 break;
1128 case kCLOCK_Flexcomm14Clk:
1129 freq = CLOCK_GetFlexCommClkFreq(14U);
1130 break;
1131 case kCLOCK_Flexcomm15Clk:
1132 freq = CLOCK_GetFlexCommClkFreq(15U);
1133 break;
1134 default:
1135 freq = 0U;
1136 break;
1137 }
1138
1139 return freq;
1140}
1141
1142/* Set FRG Clk */
1143/*! brief Set output of the Fractional baud rate generator
1144 * param config : Configuration to set to FRGn clock.
1145 */
1146void CLOCK_SetFRGClock(const clock_frg_clk_config_t *config)
1147{
1148 uint32_t i = config->num;
1149
1150 assert(i <= 15U);
1151 assert(config->divider == 255U); /* Always set to 0xFF to use with the fractional baudrate generator.*/
1152
1153 if (i <= 7UL)
1154 {
1155 CLKCTL1->FLEXCOMM[i].FRGCLKSEL = (uint32_t)config->sfg_clock_src;
1156 CLKCTL1->FLEXCOMM[i].FRGCTL = (CLKCTL1_FRGCTL_MULT(config->mult) | CLKCTL1_FRGCTL_DIV(config->divider));
1157 }
1158 else if (i == 14UL)
1159 {
1160 CLKCTL1->FRG14CLKSEL = (uint32_t)config->sfg_clock_src;
1161 CLKCTL1->FRG14CTL = (CLKCTL1_FRGCTL_MULT(config->mult) | CLKCTL1_FRGCTL_DIV(config->divider));
1162 }
1163 else if (i == 15UL)
1164 {
1165 CLKCTL1->FRG15CLKSEL = (uint32_t)config->sfg_clock_src;
1166 CLKCTL1->FRG15CTL = (CLKCTL1_FRGCTL_MULT(config->mult) | CLKCTL1_FRGCTL_DIV(config->divider));
1167 }
1168 else
1169 {
1170 assert(false);
1171 }
1172}
1173
1174#ifndef __XCC__
1175/**
1176 * brief Enable FFRO 48M/60M clock.
1177 * Note Need to make sure FFRO and ROM has power(PDRUNCFG0[16] and PDRUNCFG1[28] = 0U) before calling this API
1178 *
1179 * param ffroFreq : target fro frequency.
1180 * return Nothing
1181 */
1182void CLOCK_EnableFfroClk(clock_ffro_freq_t ffroFreq)
1183{
1184 uint32_t tempco = 0U;
1185 uint32_t coarse = 0U;
1186 uint32_t fine = 0U;
1187 uint32_t ffro_delay = 0U;
1188
1189 assert(((SYSCTL0->PDRUNCFG0 & SYSCTL0_PDRUNCFG0_FFRO_PD_MASK) == 0UL) &&
1190 ((SYSCTL0->PDRUNCFG1 & SYSCTL0_PDRUNCFG1_ROM_PD_MASK) == 0UL));
1191
1192 /* FFROCTL0, FFROCTL1 and the otp trim value should not be touched by application */
1193 CLKCTL0->FFROCTL1 |= CLKCTL0_FFROCTL1_UPDATE_MASK;
1194 OTP_INIT_API(CLOCK_GetMainClkFreq() / ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK) + 1U));
1195 if (ffroFreq == kCLOCK_Ffro48M)
1196 {
1197 /* Read 48M FFRO clock Trim settings from fuse. */
1198 OTP_FUSE_READ_API(FIRC_48MHZ_TRIM_TEMPCO, &tempco);
1199 OTP_FUSE_READ_API(FIRC_48MHZ_TRIM_COARSE, &coarse);
1200 OTP_FUSE_READ_API(FIRC_48MHZ_TRIM_FINE, &fine);
1201 }
1202 else
1203 {
1204 /* Read 60M FFRO clock Trim settings from fuse. */
1205 OTP_FUSE_READ_API(FIRC_60MHZ_TRIM_TEMPCO, &tempco);
1206 OTP_FUSE_READ_API(FIRC_60MHZ_TRIM_COARSE, &coarse);
1207 OTP_FUSE_READ_API(FIRC_60MHZ_TRIM_FINE, &fine);
1208 }
1209 /* Read FFRO stable time from fuse. */
1210 OTP_FUSE_READ_API(FFRO_STABLE_TIME, &ffro_delay);
1211 OTP_DEINIT_API();
1212 CLKCTL0->FFROCTL0 = CLKCTL0_FFROCTL0_TRIM_TEMPCO(tempco) | CLKCTL0_FFROCTL0_TRIM_COARSE(coarse) |
1213 CLKCTL0_FFROCTL0_TRIM_FINE(fine) |
1214 CLKCTL0_FFROCTL0_TRIM_RANGE((ffroFreq == kCLOCK_Ffro48M) ? 0 : 3);
1215 CLKCTL0->FFROCTL1 &= ~CLKCTL0_FFROCTL1_UPDATE_MASK;
1216 /* No FFRO enable/disable control in CLKCTL. Just wait FFRO stable in case FFRO just get powered on. */
1217 SDK_DelayAtLeastUs(ffro_delay, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
1218}
1219/**
1220 * brief Enable SFRO clock.
1221 * Note Need to make sure SFRO and ROM has power(PDRUNCFG0[15] and PDRUNCFG1[28] = 0U) before calling this API
1222 *
1223 * param Nothing
1224 * return Nothing
1225 */
1226
1227void CLOCK_EnableSfroClk(void)
1228{
1229 uint32_t sfro_delay = 0U;
1230
1231 assert(((SYSCTL0->PDRUNCFG0 & SYSCTL0_PDRUNCFG0_SFRO_PD_MASK) == 0UL) &&
1232 ((SYSCTL0->PDRUNCFG1 & SYSCTL0_PDRUNCFG1_ROM_PD_MASK) == 0UL));
1233 /* The otp trim value should not be touched by application */
1234 OTP_INIT_API(CLOCK_GetMainClkFreq() / ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK) + 1U));
1235 /* Read SFRO stable time from fuse. */
1236 OTP_FUSE_READ_API(SFRO_STABLE_TIME, &sfro_delay);
1237 OTP_DEINIT_API();
1238 /* No SFRO enable/disable control in CLKCTL. Just wait SFRO stable in case SFRO just get powered on. */
1239 SDK_DelayAtLeastUs(sfro_delay, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
1240}
1241#endif /* __XCC__ */
1242
1243/* Initialize the SYSTEM PLL Clk */
1244/*! brief Initialize the System PLL.
1245 * param config : Configuration to set to PLL.
1246 */
1247void CLOCK_InitSysPll(const clock_sys_pll_config_t *config)
1248{
1249 /* Power down SYSPLL before change fractional settings */
1250 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK;
1251
1252 CLKCTL0->SYSPLL0CLKSEL = (uint32_t)config->sys_pll_src;
1253 CLKCTL0->SYSPLL0NUM = config->numerator;
1254 CLKCTL0->SYSPLL0DENOM = config->denominator;
1255 switch (config->sys_pll_mult)
1256 {
1257 case kCLOCK_SysPllMult16:
1258 CLKCTL0->SYSPLL0CTL0 =
1259 (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(16);
1260 break;
1261 case kCLOCK_SysPllMult17:
1262 CLKCTL0->SYSPLL0CTL0 =
1263 (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(17);
1264 break;
1265 case kCLOCK_SysPllMult18:
1266 CLKCTL0->SYSPLL0CTL0 =
1267 (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(18);
1268 break;
1269 case kCLOCK_SysPllMult19:
1270 CLKCTL0->SYSPLL0CTL0 =
1271 (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(19);
1272 break;
1273 case kCLOCK_SysPllMult20:
1274 CLKCTL0->SYSPLL0CTL0 =
1275 (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(20);
1276 break;
1277 case kCLOCK_SysPllMult21:
1278 CLKCTL0->SYSPLL0CTL0 =
1279 (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(21);
1280 break;
1281 case kCLOCK_SysPllMult22:
1282 CLKCTL0->SYSPLL0CTL0 =
1283 (CLKCTL0->SYSPLL0CTL0 & ~CLKCTL0_SYSPLL0CTL0_MULT_MASK) | CLKCTL0_SYSPLL0CTL0_MULT(22);
1284 break;
1285 default:
1286 /* Added comments to prevent the violation of MISRA rule. */
1287 break;
1288 }
1289 /* Clear System PLL reset*/
1290 CLKCTL0->SYSPLL0CTL0 &= ~CLKCTL0_SYSPLL0CTL0_RESET_MASK;
1291 /* Power up SYSPLL*/
1292 SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK;
1293 SDK_DelayAtLeastUs((CLKCTL0->SYSPLL0LOCKTIMEDIV2 & CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 2UL,
1294 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
1295 /* Set System PLL HOLDRINGOFF_ENA */
1296 CLKCTL0->SYSPLL0CTL0 |= CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK;
1297 SDK_DelayAtLeastUs((CLKCTL0->SYSPLL0LOCKTIMEDIV2 & CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 6UL,
1298 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
1299 /* Clear System PLL HOLDRINGOFF_ENA*/
1300 CLKCTL0->SYSPLL0CTL0 &= ~CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK;
1301 SDK_DelayAtLeastUs((CLKCTL0->SYSPLL0LOCKTIMEDIV2 & CLKCTL0_SYSPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 3UL,
1302 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
1303}
1304/* Initialize the System PLL PFD */
1305/*! brief Initialize the System PLL PFD.
1306 * param pfd : Which PFD clock to enable.
1307 * param divider : The PFD divider value.
1308 * note It is recommended that PFD settings are kept between 12-35.
1309 */
1310void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t divider)
1311{
1312 uint32_t pfdIndex = (uint32_t)pfd;
1313 uint32_t syspfd;
1314
1315 syspfd = CLKCTL0->SYSPLL0PFD &
1316 ~(((uint32_t)CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK | (uint32_t)CLKCTL0_SYSPLL0PFD_PFD0_MASK)
1317 << (8UL * pfdIndex));
1318
1319 /* Disable the clock output first. */
1320 CLKCTL0->SYSPLL0PFD = syspfd | ((uint32_t)CLKCTL0_SYSPLL0PFD_PFD0_CLKGATE_MASK << (8UL * pfdIndex));
1321
1322 /* Set the new value and enable output. */
1323 CLKCTL0->SYSPLL0PFD = syspfd | (CLKCTL0_SYSPLL0PFD_PFD0(divider) << (8UL * pfdIndex));
1324 /* Wait for output becomes stable. */
1325 while ((CLKCTL0->SYSPLL0PFD & ((uint32_t)CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY_MASK << (8UL * pfdIndex))) == 0UL)
1326 {
1327 }
1328 /* Clear ready status flag. */
1329 CLKCTL0->SYSPLL0PFD |= ((uint32_t)CLKCTL0_SYSPLL0PFD_PFD0_CLKRDY_MASK << (8UL * pfdIndex));
1330}
1331/* Initialize the Audio PLL Clk */
1332/*! brief Initialize the audio PLL.
1333 * param config : Configuration to set to PLL.
1334 */
1335void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config)
1336{
1337 /* Power down Audio PLL before change fractional settings */
1338 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK;
1339
1340 CLKCTL1->AUDIOPLL0CLKSEL = (uint32_t)(config->audio_pll_src);
1341 CLKCTL1->AUDIOPLL0NUM = config->numerator;
1342 CLKCTL1->AUDIOPLL0DENOM = config->denominator;
1343 switch (config->audio_pll_mult)
1344 {
1345 case kCLOCK_AudioPllMult16:
1346 CLKCTL1->AUDIOPLL0CTL0 =
1347 (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(16);
1348 break;
1349 case kCLOCK_AudioPllMult17:
1350 CLKCTL1->AUDIOPLL0CTL0 =
1351 (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(17);
1352 break;
1353 case kCLOCK_AudioPllMult18:
1354 CLKCTL1->AUDIOPLL0CTL0 =
1355 (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(18);
1356 break;
1357 case kCLOCK_AudioPllMult19:
1358 CLKCTL1->AUDIOPLL0CTL0 =
1359 (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(19);
1360 break;
1361 case kCLOCK_AudioPllMult20:
1362 CLKCTL1->AUDIOPLL0CTL0 =
1363 (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(20);
1364 break;
1365 case kCLOCK_AudioPllMult21:
1366 CLKCTL1->AUDIOPLL0CTL0 =
1367 (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(21);
1368 break;
1369 case kCLOCK_AudioPllMult22:
1370 CLKCTL1->AUDIOPLL0CTL0 =
1371 (CLKCTL1->AUDIOPLL0CTL0 & ~CLKCTL1_AUDIOPLL0CTL0_MULT_MASK) | CLKCTL1_AUDIOPLL0CTL0_MULT(22);
1372 break;
1373 default:
1374 /* Added comments to prevent the violation of MISRA C-2012 rule */
1375 break;
1376 }
1377
1378 /* Clear Audio PLL reset*/
1379 CLKCTL1->AUDIOPLL0CTL0 &= ~CLKCTL1_AUDIOPLL0CTL0_RESET_MASK;
1380 /* Power up Audio PLL*/
1381 SYSCTL0->PDRUNCFG0_CLR = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK;
1382 SDK_DelayAtLeastUs((CLKCTL1->AUDIOPLL0LOCKTIMEDIV2 & CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 2UL,
1383 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
1384 /* Set Audio PLL HOLDRINGOFF_ENA */
1385 CLKCTL1->AUDIOPLL0CTL0 |= CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK;
1386 SDK_DelayAtLeastUs((CLKCTL1->AUDIOPLL0LOCKTIMEDIV2 & CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 6UL,
1387 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
1388 /* Clear Audio PLL HOLDRINGOFF_ENA*/
1389 CLKCTL1->AUDIOPLL0CTL0 &= ~CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK;
1390 SDK_DelayAtLeastUs((CLKCTL1->AUDIOPLL0LOCKTIMEDIV2 & CLKCTL1_AUDIOPLL0LOCKTIMEDIV2_LOCKTIMEDIV2_MASK) / 3UL,
1391 SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
1392}
1393/* Initialize the Audio PLL PFD */
1394/*! brief Initialize the audio PLL PFD.
1395 * param pfd : Which PFD clock to enable.
1396 * param divider : The PFD divider value.
1397 * note It is recommended that PFD settings are kept between 12-35.
1398 */
1399void CLOCK_InitAudioPfd(clock_pfd_t pfd, uint8_t divider)
1400{
1401 uint32_t pfdIndex = (uint32_t)pfd;
1402 uint32_t syspfd;
1403
1404 syspfd = CLKCTL1->AUDIOPLL0PFD &
1405 ~(((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK | (uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_MASK)
1406 << (8UL * pfdIndex));
1407
1408 /* Disable the clock output first. */
1409 CLKCTL1->AUDIOPLL0PFD = syspfd | ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * pfdIndex));
1410
1411 /* Set the new value and enable output. */
1412 CLKCTL1->AUDIOPLL0PFD = syspfd | (CLKCTL1_AUDIOPLL0PFD_PFD0(divider) << (8UL * pfdIndex));
1413 /* Wait for output becomes stable. */
1414 while ((CLKCTL1->AUDIOPLL0PFD & ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY_MASK << (8UL * pfdIndex))) == 0UL)
1415 {
1416 }
1417 /* Clear ready status flag. */
1418 CLKCTL1->AUDIOPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKRDY_MASK << (8UL * pfdIndex));
1419}
1420/*! @brief Enable/Disable sys osc clock from external crystal clock.
1421 * @param enable : true to enable system osc clock, false to bypass system osc.
1422 * @param enableLowPower : true to enable low power mode, false to enable high gain mode.
1423 * @param delay_us : Delay time after OSC power up.
1424 */
1425void CLOCK_EnableSysOscClk(bool enable, bool enableLowPower, uint32_t delay_us)
1426{
1427 uint32_t ctrl = enableLowPower ? CLKCTL0_SYSOSCCTL0_LP_ENABLE_MASK : 0U;
1428
1429 if (enable)
1430 {
1431 CLKCTL0->SYSOSCCTL0 = ctrl;
1432 CLKCTL0->SYSOSCBYPASS = 0;
1433 SDK_DelayAtLeastUs(delay_us, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
1434 }
1435 else
1436 {
1437 CLKCTL0->SYSOSCCTL0 = ctrl | CLKCTL0_SYSOSCCTL0_BYPASS_ENABLE_MASK;
1438 }
1439}
1440/*! @brief Enable USB HS device clock.
1441 *
1442 * This function enables USB HS device clock.
1443 */
1444void CLOCK_EnableUsbhsDeviceClock(void)
1445{
1446 CLOCK_EnableClock(kCLOCK_UsbhsPhy);
1447 /* Enable usbhs device and ram clock */
1448 CLOCK_EnableClock(kCLOCK_UsbhsDevice);
1449 CLOCK_EnableClock(kCLOCK_UsbhsSram);
1450}
1451
1452/*! @brief Enable USB HS host clock.
1453 *
1454 * This function enables USB HS host clock.
1455 */
1456void CLOCK_EnableUsbhsHostClock(void)
1457{
1458 CLOCK_EnableClock(kCLOCK_UsbhsPhy);
1459 /* Enable usbhs host and ram clock */
1460 CLOCK_EnableClock(kCLOCK_UsbhsHost);
1461 CLOCK_EnableClock(kCLOCK_UsbhsSram);
1462}
1463
1464/*! brief Enable USB hs0PhyPll clock.
1465 *
1466 * param src USB HS clock source.
1467 * param freq The frequency specified by src.
1468 * retval true The clock is set successfully.
1469 * retval false The clock source is invalid to get proper USB HS clock.
1470 */
1471bool CLOCK_EnableUsbHs0PhyPllClock(clock_attach_id_t src, uint32_t freq)
1472{
1473 uint32_t phyPllDiv = 0U;
1474 uint32_t multiplier = 0U;
1475 bool retVal = true;
1476
1477 USBPHY->CTRL_CLR = USBPHY_CTRL_SFTRST_MASK;
1478
1479 uint32_t delay = 100000;
1480 while ((delay--) != 0UL)
1481 {
1482 __NOP();
1483 }
1484
1485 multiplier = 480000000UL / freq;
1486
1487 switch (multiplier)
1488 {
1489 case 13:
1490 {
1491 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(0U);
1492 break;
1493 }
1494 case 15:
1495 {
1496 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(1U);
1497 break;
1498 }
1499 case 16:
1500 {
1501 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(2U);
1502 break;
1503 }
1504 case 20:
1505 {
1506 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(3U);
1507 break;
1508 }
1509 case 22:
1510 {
1511 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(4U);
1512 break;
1513 }
1514 case 25:
1515 {
1516 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(5U);
1517 break;
1518 }
1519 case 30:
1520 {
1521 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(6U);
1522 break;
1523 }
1524 case 240:
1525 {
1526 phyPllDiv = USBPHY_PLL_SIC_PLL_DIV_SEL(7U);
1527 break;
1528 }
1529 default:
1530 {
1531 retVal = false;
1532 break;
1533 }
1534 }
1535
1536 if (retVal)
1537 {
1538 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_POWER(1) | USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK);
1539 USBPHY->PLL_SIC = (USBPHY->PLL_SIC & ~(USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)) | phyPllDiv;
1540 USBPHY->PLL_SIC_CLR = USBPHY_PLL_SIC_PLL_BYPASS_MASK;
1541 USBPHY->PLL_SIC_SET = (USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK);
1542
1543 USBPHY->CTRL_CLR = USBPHY_CTRL_CLR_CLKGATE_MASK;
1544 USBPHY->PWD_SET = 0x0;
1545
1546 while (0UL == (USBPHY->PLL_SIC & USBPHY_PLL_SIC_PLL_LOCK_MASK))
1547 {
1548 }
1549 }
1550
1551 return retVal;
1552}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_clock.h
new file mode 100644
index 000000000..c2003d90c
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_clock.h
@@ -0,0 +1,1203 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020 , NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_CLOCK_H_
10#define _FSL_CLOCK_H_
11
12#include "fsl_device_registers.h"
13#include <stdint.h>
14#include <stdbool.h>
15#include <assert.h>
16#include "fsl_reset.h"
17#include "fsl_common.h"
18
19/*! @addtogroup clock */
20/*! @{ */
21
22/*! @file */
23
24/*******************************************************************************
25 * Definitions
26 *****************************************************************************/
27
28/*! @name Driver version */
29/*@{*/
30/*! @brief CLOCK driver version 2.7.0. */
31#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 7, 0))
32/*@}*/
33
34/* Definition for delay API in clock driver, users can redefine it to the real application. */
35#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
36#ifdef __XCC__
37#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (600000000UL)
38#else
39#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (300000000UL)
40#endif
41#endif
42
43/*! @brief External XTAL (SYSOSC) clock frequency.
44 *
45 * The XTAL (SYSOSC) clock frequency in Hz, when the clock is setup, use the
46 * function CLOCK_SetXtalFreq to set the value in to clock driver. For example,
47 * if XTAL is 16MHz,
48 * @code
49 * CLOCK_SetXtalFreq(160000000);
50 * @endcode
51 */
52extern volatile uint32_t g_xtalFreq;
53/*! @brief External CLK_IN pin clock frequency (clkin) clock frequency.
54 *
55 * The CLK_IN pin (clkin) clock frequency in Hz, when the clock is setup, use the
56 * function CLOCK_SetClkinFreq to set the value in to clock driver. For example,
57 * if CLK_IN is 16MHz,
58 * @code
59 * CLOCK_SetClkinFreq(160000000);
60 * @endcode
61 */
62extern volatile uint32_t g_clkinFreq;
63/*! @brief External XTAL (SYSOSC) clock frequency.
64 *
65 * The MCLK in (mclk_in) PIN clock frequency in Hz, when the clock is setup, use the
66 * function CLOCK_SetMclkInFreq to set the value in to clock driver. For example,
67 * if mclk_In is 16MHz,
68 * @code
69 * CLOCK_SetMclkInFreq(160000000);
70 * @endcode
71 */
72extern volatile uint32_t g_mclkFreq;
73
74/*! @brief Clock ip name array for ACMP. */
75#define CMP_CLOCKS \
76 { \
77 kCLOCK_Acmp0 \
78 }
79/*! @brief Clock ip name array for FLEXCOMM. */
80#define FLEXCOMM_CLOCKS \
81 { \
82 kCLOCK_Flexcomm0, kCLOCK_Flexcomm1, kCLOCK_Flexcomm2, kCLOCK_Flexcomm3, kCLOCK_Flexcomm4, kCLOCK_Flexcomm5, \
83 kCLOCK_Flexcomm6, kCLOCK_Flexcomm7, kCLOCK_Flexcomm14, kCLOCK_Flexcomm15 \
84 }
85/*! @brief Clock ip name array for LPUART. */
86#define USART_CLOCKS \
87 { \
88 kCLOCK_Usart0, kCLOCK_Usart1, kCLOCK_Usart2, kCLOCK_Usart3, kCLOCK_Usart4, kCLOCK_Usart5, kCLOCK_Usart6, \
89 kCLOCK_Usart7 \
90 }
91
92/*! @brief Clock ip name array for I2C. */
93#define I2C_CLOCKS \
94 { \
95 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3, kCLOCK_I2c4, kCLOCK_I2c5, kCLOCK_I2c6, kCLOCK_I2c7, \
96 kCLOCK_I2c15 \
97 }
98/*! @brief Clock ip name array for I3C. */
99#define I3C_CLOCKS \
100 { \
101 kCLOCK_I3c0 \
102 }
103/*! @brief Clock ip name array for SPI. */
104#define SPI_CLOCKS \
105 { \
106 kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2, kCLOCK_Spi3, kCLOCK_Spi4, kCLOCK_Spi5, kCLOCK_Spi6, kCLOCK_Spi7, \
107 kCLOCK_Spi14 \
108 }
109/*! @brief Clock ip name array for FLEXI2S. */
110#define FLEXI2S_CLOCKS \
111 { \
112 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
113 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
114 }
115/*! @brief Clock ip name array for UTICK. */
116#define UTICK_CLOCKS \
117 { \
118 kCLOCK_Utick0 \
119 }
120/*! @brief Clock ip name array for DMIC. */
121#define DMIC_CLOCKS \
122 { \
123 kCLOCK_Dmic0 \
124 }
125/*! @brief Clock ip name array for CT32B. */
126#define CTIMER_CLOCKS \
127 { \
128 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
129 }
130
131/*! @brief Clock ip name array for GPIO. */
132#define GPIO_CLOCKS \
133 { \
134 kCLOCK_HsGpio0, kCLOCK_HsGpio1, kCLOCK_HsGpio2, kCLOCK_HsGpio3, kCLOCK_HsGpio4, kCLOCK_HsGpio5, \
135 kCLOCK_HsGpio6, kCLOCK_HsGpio7 \
136 }
137/*! @brief Clock ip name array for ADC. */
138#define LPADC_CLOCKS \
139 { \
140 kCLOCK_Adc0 \
141 }
142/*! @brief Clock ip name array for MRT. */
143#define MRT_CLOCKS \
144 { \
145 kCLOCK_Mrt0 \
146 }
147/*! @brief Clock ip name array for SCT. */
148#define SCT_CLOCKS \
149 { \
150 kCLOCK_Sct \
151 }
152/*! @brief Clock ip name array for RTC. */
153#define RTC_CLOCKS \
154 { \
155 kCLOCK_Rtc \
156 }
157/*! @brief Clock ip name array for WWDT. */
158#define WWDT_CLOCKS \
159 { \
160 kCLOCK_Wwdt0, kCLOCK_Wwdt1 \
161 }
162/*! @brief Clock ip name array for CRC. */
163#define CRC_CLOCKS \
164 { \
165 kCLOCK_Crc \
166 }
167/*! @brief Clock ip name array for USBD. */
168#define USBD_CLOCKS \
169 { \
170 kCLOCK_UsbhsDevice \
171 }
172/*! @brief Clock ip name array for DMA. */
173#define DMA_CLOCKS \
174 { \
175 kCLOCK_Dmac0, kCLOCK_Dmac1 \
176 }
177/*! @brief Clock ip name array for PINT. */
178#define PINT_CLOCKS \
179 { \
180 kCLOCK_Pint \
181 }
182/*! @brief Clock ip name array for FLEXSPI */
183#define FLEXSPI_CLOCKS \
184 { \
185 kCLOCK_Flexspi \
186 }
187/*! @brief Clock ip name array for Cache64 */
188#define CACHE64_CLOCKS \
189 { \
190 kCLOCK_Flexspi \
191 }
192/*! @brief Clock ip name array for MUA */
193#define MU_CLOCKS \
194 { \
195 kCLOCK_Mu \
196 }
197/*! @brief Clock ip name array for SEMA */
198#define SEMA42_CLOCKS \
199 { \
200 kCLOCK_Sema \
201 }
202/*! @brief Clock ip name array for RNG */
203#define TRNG_CLOCKS \
204 { \
205 kCLOCK_Rng \
206 }
207/*! @brief Clock ip name array for uSDHC */
208#define USDHC_CLOCKS \
209 { \
210 kCLOCK_Sdio0, kCLOCK_Sdio1 \
211 }
212/*! @brief Clock ip name array for OSTimer */
213#define OSTIMER_CLOCKS \
214 { \
215 kCLOCK_OsEventTimer \
216 }
217
218/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
219/*------------------------------------------------------------------------------
220 clock_ip_name_t definition:
221------------------------------------------------------------------------------*/
222
223#define CLK_GATE_REG_OFFSET_SHIFT 8U
224#define CLK_GATE_REG_OFFSET_MASK 0xFF00U
225#define CLK_GATE_BIT_SHIFT_SHIFT 0U
226#define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
227
228#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
229 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
230 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
231
232#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
233#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
234
235#define CLK_CTL0_PSCCTL0 0
236#define CLK_CTL0_PSCCTL1 1
237#define CLK_CTL0_PSCCTL2 2
238#define CLK_CTL1_PSCCTL0 3
239#define CLK_CTL1_PSCCTL1 4
240#define CLK_CTL1_PSCCTL2 5
241
242/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
243typedef enum _clock_ip_name
244{
245 kCLOCK_IpInvalid = 0U,
246 kCLOCK_RomCtrlr = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 2),
247 kCLOCK_PowerQuad = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 8),
248 kCLOCK_Casper = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 9),
249 kCLOCK_HashCrypt = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 10),
250 kCLOCK_Puf = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 11),
251 kCLOCK_Rng = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 12),
252 kCLOCK_Flexspi = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 16),
253 kCLOCK_OtpCtrl = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 17),
254 kCLOCK_UsbhsPhy = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 20),
255 kCLOCK_UsbhsDevice = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 21),
256 kCLOCK_UsbhsHost = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 22),
257 kCLOCK_UsbhsSram = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 23),
258 kCLOCK_Sct = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL0, 24),
259
260 kCLOCK_Sdio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 2),
261 kCLOCK_Sdio1 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 3),
262 kCLOCK_Acmp0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 15),
263 kCLOCK_Adc0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 16),
264 kCLOCK_ShsGpio0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL1, 24),
265
266 kCLOCK_Utick0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 0),
267 kCLOCK_Wwdt0 = CLK_GATE_DEFINE(CLK_CTL0_PSCCTL2, 1),
268
269 kCLOCK_Flexcomm0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
270 kCLOCK_Flexcomm1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
271 kCLOCK_Flexcomm2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
272 kCLOCK_Flexcomm3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
273 kCLOCK_Flexcomm4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
274 kCLOCK_Flexcomm5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
275 kCLOCK_Flexcomm6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
276 kCLOCK_Flexcomm7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
277 kCLOCK_Flexcomm14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22),
278 kCLOCK_Flexcomm15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23),
279 kCLOCK_Usart0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
280 kCLOCK_Usart1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
281 kCLOCK_Usart2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
282 kCLOCK_Usart3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
283 kCLOCK_Usart4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
284 kCLOCK_Usart5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
285 kCLOCK_Usart6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
286 kCLOCK_Usart7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
287 kCLOCK_I2s0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
288 kCLOCK_I2s1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
289 kCLOCK_I2s2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
290 kCLOCK_I2s3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
291 kCLOCK_I2s4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
292 kCLOCK_I2s5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
293 kCLOCK_I2s6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
294 kCLOCK_I2s7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
295 kCLOCK_I2c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
296 kCLOCK_I2c1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
297 kCLOCK_I2c2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
298 kCLOCK_I2c3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
299 kCLOCK_I2c4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
300 kCLOCK_I2c5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
301 kCLOCK_I2c6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
302 kCLOCK_I2c7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
303 kCLOCK_I2c15 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 23),
304 kCLOCK_Spi0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 8),
305 kCLOCK_Spi1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 9),
306 kCLOCK_Spi2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 10),
307 kCLOCK_Spi3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 11),
308 kCLOCK_Spi4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 12),
309 kCLOCK_Spi5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 13),
310 kCLOCK_Spi6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 14),
311 kCLOCK_Spi7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 15),
312 kCLOCK_Spi14 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 22),
313 kCLOCK_Dmic0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 24),
314 kCLOCK_OsEventTimer = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL0, 27),
315
316 kCLOCK_HsGpio0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 0),
317 kCLOCK_HsGpio1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 1),
318 kCLOCK_HsGpio2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 2),
319 kCLOCK_HsGpio3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 3),
320 kCLOCK_HsGpio4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 4),
321 kCLOCK_HsGpio5 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 5),
322 kCLOCK_HsGpio6 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 6),
323 kCLOCK_HsGpio7 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 7),
324 kCLOCK_Crc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 16),
325 kCLOCK_Dmac0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 23),
326 kCLOCK_Dmac1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 24),
327 kCLOCK_Mu = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 28),
328 kCLOCK_Sema = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 29),
329 kCLOCK_Freqme = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL1, 31),
330
331 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 0),
332 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 1),
333 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 2),
334 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 3),
335 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 4),
336 kCLOCK_Rtc = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 7),
337 kCLOCK_Mrt0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 8),
338 kCLOCK_Wwdt1 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 10),
339 kCLOCK_I3c0 = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 16),
340 kCLOCK_Pint = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 30),
341 kCLOCK_InputMux = CLK_GATE_DEFINE(CLK_CTL1_PSCCTL2, 31)
342} clock_ip_name_t;
343
344/*! @brief Clock name used to get clock frequency. */
345typedef enum _clock_name
346{
347 kCLOCK_CoreSysClk, /*!< Core clock (aka HCLK) */
348 kCLOCK_BusClk, /*!< Bus clock (AHB/APB clock, aka HCLK) */
349 kCLOCK_MclkClk, /*!< MCLK, to MCLK pin */
350 kCLOCK_ClockOutClk, /*!< CLOCKOUT */
351 kCLOCK_AdcClk, /*!< ADC */
352 kCLOCK_FlexspiClk, /*!< FLEXSPI */
353 kCLOCK_SctClk, /*!< SCT */
354 kCLOCK_Wdt0Clk, /*!< Watchdog0 */
355 kCLOCK_Wdt1Clk, /*!< Watchdog1 */
356 kCLOCK_SystickClk, /*!< Systick */
357 kCLOCK_Sdio0Clk, /*!< SDIO0 */
358 kCLOCK_Sdio1Clk, /*!< SDIO1 */
359 kCLOCK_I3cClk, /*!< I3C */
360 kCLOCK_UsbClk, /*!< USB */
361 kCLOCK_DmicClk, /*!< Digital Mic clock */
362 kCLOCK_DspCpuClk, /*!< DSP clock */
363 kCLOCK_AcmpClk, /*!< Acmp clock */
364 kCLOCK_Flexcomm0Clk, /*!< Flexcomm0Clock */
365 kCLOCK_Flexcomm1Clk, /*!< Flexcomm1Clock */
366 kCLOCK_Flexcomm2Clk, /*!< Flexcomm2Clock */
367 kCLOCK_Flexcomm3Clk, /*!< Flexcomm3Clock */
368 kCLOCK_Flexcomm4Clk, /*!< Flexcomm4Clock */
369 kCLOCK_Flexcomm5Clk, /*!< Flexcomm5Clock */
370 kCLOCK_Flexcomm6Clk, /*!< Flexcomm6Clock */
371 kCLOCK_Flexcomm7Clk, /*!< Flexcomm7Clock */
372 kCLOCK_Flexcomm14Clk, /*!< Flexcomm14Clock */
373 kCLOCK_Flexcomm15Clk, /*!< Flexcomm15Clock */
374} clock_name_t;
375
376/**
377 * PLL PFD clock name
378 */
379typedef enum _clock_pfd
380{
381 kCLOCK_Pfd0 = 0U, /*!< PLL PFD0 */
382 kCLOCK_Pfd1 = 1U, /*!< PLL PFD1 */
383 kCLOCK_Pfd2 = 2U, /*!< PLL PFD2 */
384 kCLOCK_Pfd3 = 3U, /*!< PLL PFD3 */
385} clock_pfd_t;
386
387/*! @brief Clock Mux Switches
388 * The encoding is as follows each connection identified is 32bits wide
389 * starting from LSB upwards
390 *
391 * [12 bits for reg offset, 0 means end of descriptor, 4 bits for choice] [bit 31 define CLKCTL0 or CLKCTL1]*
392 *
393 */
394/* CLKCTL0 SEL */
395#define SYSPLL0CLKSEL_OFFSET 0x200
396#define MAINCLKSELA_OFFSET 0x430
397#define MAINCLKSELB_OFFSET 0x434
398#define FLEXSPIFCLKSEL_OFFSET 0x620
399#define SCTFCLKSEL_OFFSET 0x640
400#define USBHSFCLKSEL_OFFSET 0x660
401#define SDIO0FCLKSEL_OFFSET 0x680
402#define SDIO1FCLKSEL_OFFSET 0x690
403#define ADC0FCLKSEL0_OFFSET 0x6D0
404#define ADC0FCLKSEL1_OFFSET 0x6D4
405#define UTICKFCLKSEL_OFFSET 0x700
406#define WDT0FCLKSEL_OFFSET 0x720
407#define WAKECLK32KHZSEL_OFFSET 0x730
408#define SYSTICKFCLKSEL_OFFSET 0x760
409/* CLKCTL1 SEL */
410#define AUDIOPLL0CLKSEL_OFFSET 0x200
411#define DSPCPUCLKSELA_OFFSET 0x430
412#define DSPCPUCLKSELB_OFFSET 0x434
413#define OSEVENTFCLKSEL_OFFSET 0x480
414#define FC0FCLKSEL_OFFSET 0x508
415#define FC1FCLKSEL_OFFSET 0x528
416#define FC2FCLKSEL_OFFSET 0x548
417#define FC3FCLKSEL_OFFSET 0x568
418#define FC4FCLKSEL_OFFSET 0x588
419#define FC5FCLKSEL_OFFSET 0x5A8
420#define FC6FCLKSEL_OFFSET 0x5C8
421#define FC7FCLKSEL_OFFSET 0x5E8
422#define FC14FCLKSEL_OFFSET 0x6C8
423#define FC15FCLKSEL_OFFSET 0x6E8
424#define DMIC0FCLKSEL_OFFSET 0x700
425#define CT32BIT0FCLKSEL_OFFSET 0x720
426#define CT32BIT1FCLKSEL_OFFSET 0x724
427#define CT32BIT2FCLKSEL_OFFSET 0x728
428#define CT32BIT3FCLKSEL_OFFSET 0x72C
429#define CT32BIT4FCLKSEL_OFFSET 0x730
430#define AUDIOMCLKSEL_OFFSET 0x740
431#define CLKOUTSEL0_OFFSET 0x760
432#define CLKOUTSEL1_OFFSET 0x764
433#define I3C0FCLKSEL_OFFSET 0x780
434#define I3C0FCLKSTCSEL_OFFSET 0x784
435#define WDT1FCLKSEL_OFFSET 0x7A0
436#define ACMP0FCLKSEL_OFFSET 0x7C0
437/* CLKCTL0 DIV */
438#define MAINPLLCLKDIV_OFFSET 0x240
439#define DSPPLLCLKDIV_OFFSET 0x244
440#define AUX0PLLCLKDIV_OFFSET 0x248
441#define AUX1PLLCLKDIV_OFFSET 0x24C
442#define SYSCPUAHBCLKDIV_OFFSET 0x400
443#define PFC0CLKDIV_OFFSET 0x500
444#define PFC1CLKDIV_OFFSET 0x504
445#define FLEXSPIFCLKDIV_OFFSET 0x624
446#define SCTFCLKDIV_OFFSET 0x644
447#define USBHSFCLKDIV_OFFSET 0x664
448#define SDIO0FCLKDIV_OFFSET 0x684
449#define SDIO1FCLKDIV_OFFSET 0x694
450#define ADC0FCLKDIV_OFFSET 0x6D8
451#define WAKECLK32KHZDIV_OFFSET 0x734
452#define SYSTICKFCLKDIV_OFFSET 0x764
453
454/* CLKCTL1 DIV */
455#define AUDIOPLLCLKDIV_OFFSET 0x240
456#define DSPCPUCLKDIV_OFFSET 0x400
457#define DSPMAINRAMCLKDIV_OFFSET 0x404
458#define FRGPLLCLKDIV_OFFSET 0x6FC
459#define DMIC0FCLKDIV_OFFSET 0x704
460#define AUDIOMCLKDIV_OFFSET 0x744
461#define CLKOUTDIV_OFFSET 0x768
462#define I3C0FCLKSTCDIV_OFFSET 0x788
463#define I3C0FCLKSDIV_OFFSET 0x78C
464#define I3C0FCLKDIV_OFFSET 0x790
465#define ACMP0FCLKDIV_OFFSET 0x7C4
466
467#define CLKCTL0_TUPLE_MUXA(reg, choice) (((reg)&0xFFFU) | ((choice) << 12U))
468#define CLKCTL0_TUPLE_MUXB(reg, choice) ((((reg)&0xFFFU) << 16) | ((choice) << 28U))
469#define CLKCTL1_TUPLE_MUXA(reg, choice) (0x80000000U | (((reg)&0xFFFU) | ((choice) << 12U)))
470#define CLKCTL1_TUPLE_MUXB(reg, choice) (0x80000000U | ((((reg)&0xFFFU) << 16) | ((choice) << 28U)))
471#define CLKCTL_TUPLE_REG(base, tuple) ((volatile uint32_t *)(((uint32_t)(base)) + ((uint32_t)(tuple)&0xFFFU)))
472#define CLKCTL_TUPLE_SEL(tuple) (((uint32_t)(tuple) >> 12U) & 0x7U)
473
474typedef enum _clock_attach_id
475{
476 kSFRO_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 0),
477 kXTALIN_CLK_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 1),
478 kFFRO_DIV2_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 2),
479 kNONE_to_SYS_PLL = CLKCTL0_TUPLE_MUXA(SYSPLL0CLKSEL_OFFSET, 7),
480
481 kSFRO_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 0),
482 kXTALIN_CLK_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 1),
483 kFFRO_DIV2_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 2),
484 kNONE_to_AUDIO_PLL = CLKCTL1_TUPLE_MUXA(AUDIOPLL0CLKSEL_OFFSET, 7),
485
486 kFFRO_DIV4_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 0) | CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0),
487 kXTALIN_CLK_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 1) | CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0),
488 kLPOSC_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 2) | CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0),
489 kFFRO_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELA_OFFSET, 3) | CLKCTL0_TUPLE_MUXB(MAINCLKSELB_OFFSET, 0),
490 kSFRO_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 1),
491 kMAIN_PLL_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 2),
492 kOSC32K_to_MAIN_CLK = CLKCTL0_TUPLE_MUXA(MAINCLKSELB_OFFSET, 3),
493
494 kFFRO_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 0) | CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0),
495 kXTALIN_CLK_to_DSP_MAIN_CLK =
496 CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 1) | CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0),
497 kLPOSC_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 2) | CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0),
498 kSFRO_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELA_OFFSET, 3) | CLKCTL1_TUPLE_MUXB(DSPCPUCLKSELB_OFFSET, 0),
499 kMAIN_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 1),
500 kDSP_PLL_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 2),
501 kOSC32K_to_DSP_MAIN_CLK = CLKCTL1_TUPLE_MUXA(DSPCPUCLKSELB_OFFSET, 3),
502
503 kSFRO_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 0) | CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0),
504 kXTALIN_CLK_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 1) | CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0),
505 kLPOSC_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 2) | CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0),
506 kFFRO_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL0_OFFSET, 3) | CLKCTL0_TUPLE_MUXB(ADC0FCLKSEL1_OFFSET, 0),
507 kMAIN_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 1),
508 kAUX0_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 3),
509 kAUX1_PLL_to_ADC_CLK = CLKCTL0_TUPLE_MUXA(ADC0FCLKSEL1_OFFSET, 5),
510
511 kSFRO_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 0) | CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0),
512 kXTALIN_CLK_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 1) | CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0),
513 kLPOSC_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 2) | CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0),
514 kFFRO_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 3) | CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0),
515 kMAIN_CLK_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 4) | CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0),
516 kDSP_MAIN_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL0_OFFSET, 6) | CLKCTL1_TUPLE_MUXB(CLKOUTSEL1_OFFSET, 0),
517 kMAIN_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 1),
518 kAUX0_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 2),
519 kDSP_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 3),
520 kAUX1_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 4),
521 kAUDIO_PLL_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 5),
522 kOSC32K_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 6),
523 kNONE_to_CLKOUT = CLKCTL1_TUPLE_MUXA(CLKOUTSEL1_OFFSET, 7),
524
525 kMAIN_CLK_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 0),
526 kFFRO_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 1),
527 kNONE_to_I3C_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSEL_OFFSET, 7),
528
529 kI3C_CLK_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 0),
530 kLPOSC_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 1),
531 kNONE_to_I3C_TC_CLK = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCSEL_OFFSET, 7),
532
533 kLPOSC_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 0),
534 kOSC32K_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 1),
535 kHCLK_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 2),
536 kNONE_to_OSTIMER_CLK = CLKCTL1_TUPLE_MUXA(OSEVENTFCLKSEL_OFFSET, 7),
537
538 kMAIN_CLK_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 0),
539 kMAIN_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 1),
540 kAUX0_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 2),
541 kFFRO_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 3),
542 kAUX1_PLL_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 4),
543 kNONE_to_FLEXSPI_CLK = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKSEL_OFFSET, 7),
544
545 kMAIN_CLK_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 0),
546 kMAIN_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 1),
547 kAUX0_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 2),
548 kFFRO_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 3),
549 kAUX1_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 4),
550 kAUDIO_PLL_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 5),
551 kNONE_to_SCT_CLK = CLKCTL0_TUPLE_MUXA(SCTFCLKSEL_OFFSET, 7),
552
553 kLPOSC_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 0),
554 kNONE_to_UTICK_CLK = CLKCTL0_TUPLE_MUXA(UTICKFCLKSEL_OFFSET, 7),
555
556 kLPOSC_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 0),
557 kNONE_to_WDT0_CLK = CLKCTL0_TUPLE_MUXA(WDT0FCLKSEL_OFFSET, 7),
558
559 kLPOSC_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 0),
560 kNONE_to_WDT1_CLK = CLKCTL1_TUPLE_MUXA(WDT1FCLKSEL_OFFSET, 7),
561
562 kOSC32K_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 0),
563 kLPOSC_DIV32_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 1),
564 kNONE_to_32KHZWAKE_CLK = CLKCTL0_TUPLE_MUXA(WAKECLK32KHZSEL_OFFSET, 7),
565
566 kMAIN_CLK_DIV_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 0),
567 kLPOSC_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 1),
568 kOSC32K_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 2),
569 kSFRO_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 3),
570 kNONE_to_SYSTICK_CLK = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKSEL_OFFSET, 7),
571
572 kMAIN_CLK_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 0),
573 kMAIN_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 1),
574 kAUX0_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 2),
575 kFFRO_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 3),
576 kAUX1_PLL_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 4),
577 kNONE_to_SDIO0_CLK = CLKCTL0_TUPLE_MUXA(SDIO0FCLKSEL_OFFSET, 7),
578
579 kMAIN_CLK_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 0),
580 kMAIN_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 1),
581 kAUX0_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 2),
582 kFFRO_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 3),
583 kAUX1_PLL_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 4),
584 kNONE_to_SDIO1_CLK = CLKCTL0_TUPLE_MUXA(SDIO1FCLKSEL_OFFSET, 7),
585
586 kXTALIN_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 0),
587 kMAIN_CLK_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 1),
588 kNONE_to_USB_CLK = CLKCTL0_TUPLE_MUXA(USBHSFCLKSEL_OFFSET, 7),
589
590 kFFRO_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 0),
591 kAUDIO_PLL_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 1),
592 kNONE_to_MCLK_CLK = CLKCTL1_TUPLE_MUXA(AUDIOMCLKSEL_OFFSET, 7),
593
594 kSFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 0),
595 kFFRO_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 1),
596 kAUDIO_PLL_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 2),
597 kMASTER_CLK_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 3),
598 kLPOSC_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 4),
599 k32K_WAKE_CLK_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 5),
600 kNONE_to_DMIC_CLK = CLKCTL1_TUPLE_MUXA(DMIC0FCLKSEL_OFFSET, 7),
601
602 kMAIN_CLK_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 0),
603 kSFRO_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 1),
604 kFFRO_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 2),
605 kAUX0_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 3),
606 kAUX1_PLL_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 4),
607 kNONE_to_ACMP_CLK = CLKCTL1_TUPLE_MUXA(ACMP0FCLKSEL_OFFSET, 7),
608
609 kSFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 0),
610 kFFRO_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 1),
611 kAUDIO_PLL_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 2),
612 kMASTER_CLK_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 3),
613 kFRG_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 4),
614 kNONE_to_FLEXCOMM0 = CLKCTL1_TUPLE_MUXA(FC0FCLKSEL_OFFSET, 7),
615
616 kSFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 0),
617 kFFRO_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 1),
618 kAUDIO_PLL_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 2),
619 kMASTER_CLK_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 3),
620 kFRG_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 4),
621 kNONE_to_FLEXCOMM1 = CLKCTL1_TUPLE_MUXA(FC1FCLKSEL_OFFSET, 7),
622
623 kSFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 0),
624 kFFRO_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 1),
625 kAUDIO_PLL_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 2),
626 kMASTER_CLK_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 3),
627 kFRG_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 4),
628 kNONE_to_FLEXCOMM2 = CLKCTL1_TUPLE_MUXA(FC2FCLKSEL_OFFSET, 7),
629
630 kSFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 0),
631 kFFRO_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 1),
632 kAUDIO_PLL_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 2),
633 kMASTER_CLK_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 3),
634 kFRG_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 4),
635 kNONE_to_FLEXCOMM3 = CLKCTL1_TUPLE_MUXA(FC3FCLKSEL_OFFSET, 7),
636
637 kSFRO_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 0),
638 kFFRO_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 1),
639 kAUDIO_PLL_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 2),
640 kMASTER_CLK_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 3),
641 kFRG_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 4),
642 kNONE_to_FLEXCOMM4 = CLKCTL1_TUPLE_MUXA(FC4FCLKSEL_OFFSET, 7),
643
644 kSFRO_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 0),
645 kFFRO_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 1),
646 kAUDIO_PLL_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 2),
647 kMASTER_CLK_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 3),
648 kFRG_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 4),
649 kNONE_to_FLEXCOMM5 = CLKCTL1_TUPLE_MUXA(FC5FCLKSEL_OFFSET, 7),
650
651 kSFRO_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 0),
652 kFFRO_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 1),
653 kAUDIO_PLL_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 2),
654 kMASTER_CLK_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 3),
655 kFRG_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 4),
656 kNONE_to_FLEXCOMM6 = CLKCTL1_TUPLE_MUXA(FC6FCLKSEL_OFFSET, 7),
657
658 kSFRO_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 0),
659 kFFRO_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 1),
660 kAUDIO_PLL_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 2),
661 kMASTER_CLK_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 3),
662 kFRG_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 4),
663 kNONE_to_FLEXCOMM7 = CLKCTL1_TUPLE_MUXA(FC7FCLKSEL_OFFSET, 7),
664
665 kSFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 0),
666 kFFRO_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 1),
667 kAUDIO_PLL_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 2),
668 kMASTER_CLK_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 3),
669 kFRG_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 4),
670 kNONE_to_FLEXCOMM14 = CLKCTL1_TUPLE_MUXA(FC14FCLKSEL_OFFSET, 7),
671
672 kSFRO_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 0),
673 kFFRO_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 1),
674 kAUDIO_PLL_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 2),
675 kMASTER_CLK_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 3),
676 kFRG_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 4),
677 kNONE_to_FLEXCOMM15 = CLKCTL1_TUPLE_MUXA(FC15FCLKSEL_OFFSET, 7),
678
679 kMAIN_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 0),
680 kSFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 1),
681 kFFRO_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 2),
682 kAUDIO_PLL_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 3),
683 kMASTER_CLK_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 4),
684 kLPOSC_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 5),
685 kNONE_to_CTIMER0 = CLKCTL1_TUPLE_MUXA(CT32BIT0FCLKSEL_OFFSET, 7),
686
687 kMAIN_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 0),
688 kSFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 1),
689 kFFRO_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 2),
690 kAUDIO_PLL_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 3),
691 kMASTER_CLK_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 4),
692 kLPOSC_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 5),
693 kNONE_to_CTIMER1 = CLKCTL1_TUPLE_MUXA(CT32BIT1FCLKSEL_OFFSET, 7),
694
695 kMAIN_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 0),
696 kSFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 1),
697 kFFRO_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 2),
698 kAUDIO_PLL_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 3),
699 kMASTER_CLK_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 4),
700 kLPOSC_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 5),
701 kNONE_to_CTIMER2 = CLKCTL1_TUPLE_MUXA(CT32BIT2FCLKSEL_OFFSET, 7),
702
703 kMAIN_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 0),
704 kSFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 1),
705 kFFRO_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 2),
706 kAUDIO_PLL_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 3),
707 kMASTER_CLK_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 4),
708 kLPOSC_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 5),
709 kNONE_to_CTIMER3 = CLKCTL1_TUPLE_MUXA(CT32BIT3FCLKSEL_OFFSET, 7),
710
711 kMAIN_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 0),
712 kSFRO_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 1),
713 kFFRO_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 2),
714 kAUDIO_PLL_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 3),
715 kMASTER_CLK_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 4),
716 kLPOSC_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 5),
717 kNONE_to_CTIMER4 = CLKCTL1_TUPLE_MUXA(CT32BIT4FCLKSEL_OFFSET, 7),
718
719} clock_attach_id_t;
720
721/* Clock dividers */
722typedef enum _clock_div_name
723{
724 kCLOCK_DivSysCpuAhbClk = CLKCTL0_TUPLE_MUXA(SYSCPUAHBCLKDIV_OFFSET, 0),
725 kCLOCK_DivMainPllClk = CLKCTL0_TUPLE_MUXA(MAINPLLCLKDIV_OFFSET, 0),
726 kCLOCK_DivDspPllClk = CLKCTL0_TUPLE_MUXA(DSPPLLCLKDIV_OFFSET, 0),
727 kCLOCK_DivAux0PllClk = CLKCTL0_TUPLE_MUXA(AUX0PLLCLKDIV_OFFSET, 0),
728 kCLOCK_DivAux1PllClk = CLKCTL0_TUPLE_MUXA(AUX1PLLCLKDIV_OFFSET, 0),
729 kCLOCK_DivPfc0Clk = CLKCTL0_TUPLE_MUXA(PFC0CLKDIV_OFFSET, 0),
730 kCLOCK_DivPfc1Clk = CLKCTL0_TUPLE_MUXA(PFC1CLKDIV_OFFSET, 0),
731 kCLOCK_DivAdcClk = CLKCTL0_TUPLE_MUXA(ADC0FCLKDIV_OFFSET, 0),
732 kCLOCK_DivFlexspiClk = CLKCTL0_TUPLE_MUXA(FLEXSPIFCLKDIV_OFFSET, 0),
733 kCLOCK_DivSctClk = CLKCTL0_TUPLE_MUXA(SCTFCLKDIV_OFFSET, 0),
734 kCLOCK_DivSdio0Clk = CLKCTL0_TUPLE_MUXA(SDIO0FCLKDIV_OFFSET, 0),
735 kCLOCK_DivSdio1Clk = CLKCTL0_TUPLE_MUXA(SDIO1FCLKDIV_OFFSET, 0),
736 kCLOCK_DivSystickClk = CLKCTL0_TUPLE_MUXA(SYSTICKFCLKDIV_OFFSET, 0),
737 kCLOCK_DivUsbHsFclk = CLKCTL0_TUPLE_MUXA(USBHSFCLKDIV_OFFSET, 0),
738 kCLOCK_DivAudioPllClk = CLKCTL1_TUPLE_MUXA(AUDIOPLLCLKDIV_OFFSET, 0),
739 kCLOCK_DivAcmpClk = CLKCTL1_TUPLE_MUXA(ACMP0FCLKDIV_OFFSET, 0),
740 kCLOCK_DivClockOut = CLKCTL1_TUPLE_MUXA(CLKOUTDIV_OFFSET, 0),
741 kCLOCK_DivDmicClk = CLKCTL1_TUPLE_MUXA(DMIC0FCLKDIV_OFFSET, 0),
742 kCLOCK_DivDspCpuClk = CLKCTL1_TUPLE_MUXA(DSPCPUCLKDIV_OFFSET, 0),
743 kCLOCK_DivDspRamClk = CLKCTL1_TUPLE_MUXA(DSPMAINRAMCLKDIV_OFFSET, 0),
744 kCLOCK_DivMclkClk = CLKCTL1_TUPLE_MUXA(AUDIOMCLKDIV_OFFSET, 0),
745 kCLOCK_DivPllFrgClk = CLKCTL1_TUPLE_MUXA(FRGPLLCLKDIV_OFFSET, 0),
746 kCLOCK_DivI3cClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKDIV_OFFSET, 0),
747 kCLOCK_DivI3cTcClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKSTCDIV_OFFSET, 0),
748 kCLOCK_DivI3cSlowClk = CLKCTL1_TUPLE_MUXA(I3C0FCLKSDIV_OFFSET, 0),
749} clock_div_name_t;
750
751/*! @brief FFRO frequence configuration */
752typedef enum _clock_ffro_freq
753{
754 kCLOCK_Ffro48M, /*!< 48MHz FFRO clock. */
755 kCLOCK_Ffro60M, /*!< 60MHz FFRO clock. */
756} clock_ffro_freq_t;
757/*! @brief SysPLL Reference Input Clock Source */
758typedef enum _sys_pll_src
759{
760 kCLOCK_SysPllSFroClk = 0, /*!< 16MHz FRO clock */
761 kCLOCK_SysPllXtalIn = 1, /*!< OSC clock */
762 kCLOCK_SysPllFFroDiv2 = 2, /*!< FRO48/60 div2 clock */
763 kCLOCK_SysPllNone = 7 /*!< Gated to reduce power */
764} sys_pll_src_t;
765
766/*! @brief SysPLL Multiplication Factor */
767typedef enum _sys_pll_mult
768{
769 kCLOCK_SysPllMult16 = 0, /*!< Divide by 16 */
770 kCLOCK_SysPllMult17, /*!< Divide by 17 */
771 kCLOCK_SysPllMult18, /*!< Divide by 18 */
772 kCLOCK_SysPllMult19, /*!< Divide by 19 */
773 kCLOCK_SysPllMult20, /*!< Divide by 20 */
774 kCLOCK_SysPllMult21, /*!< Divide by 21 */
775 kCLOCK_SysPllMult22, /*!< Divide by 22 */
776} sys_pll_mult_t;
777
778/*! @brief PLL configuration for SYSPLL */
779typedef struct _clock_sys_pll_config
780{
781 sys_pll_src_t sys_pll_src; /*!< Reference Input Clock Source */
782 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider. */
783 uint32_t denominator; /*!< 30 bit numerator of fractional loop divider. */
784 sys_pll_mult_t sys_pll_mult; /*!< Multiplication Factor */
785} clock_sys_pll_config_t;
786
787/*! @brief AudioPll Reference Input Clock Source */
788typedef enum _audio_pll_src
789{
790 kCLOCK_AudioPllSFroClk = 0, /*!< 16MHz FRO clock */
791 kCLOCK_AudioPllXtalIn = 1, /*!< OSC clock */
792 kCLOCK_AudioPllFFroDiv2 = 2, /*!< FRO48/60 div2 clock */
793 kCLOCK_AudioPllNone = 7 /*!< Gated to reduce power */
794} audio_pll_src_t;
795
796/*! @brief AudioPll Multiplication Factor */
797typedef enum _audio_pll_mult
798{
799 kCLOCK_AudioPllMult16 = 0, /*!< Divide by 16 */
800 kCLOCK_AudioPllMult17, /*!< Divide by 17 */
801 kCLOCK_AudioPllMult18, /*!< Divide by 18 */
802 kCLOCK_AudioPllMult19, /*!< Divide by 19 */
803 kCLOCK_AudioPllMult20, /*!< Divide by 20 */
804 kCLOCK_AudioPllMult21, /*!< Divide by 21 */
805 kCLOCK_AudioPllMult22, /*!< Divide by 22 */
806} audio_pll_mult_t;
807
808/*! @brief PLL configuration for SYSPLL */
809typedef struct _clock_audio_pll_config
810{
811 audio_pll_src_t audio_pll_src; /*!< Reference Input Clock Source */
812 uint32_t numerator; /*!< 30 bit numerator of fractional loop divider. */
813 uint32_t denominator; /*!< 30 bit numerator of fractional loop divider. */
814 audio_pll_mult_t audio_pll_mult; /*!< Multiplication Factor */
815} clock_audio_pll_config_t;
816/*! @brief PLL configuration for FRG */
817typedef struct _clock_frg_clk_config
818{
819 uint8_t num; /*!< FRG clock */
820 enum
821 {
822 kCLOCK_FrgMainClk = 0, /*!< Main System clock */
823 kCLOCK_FrgPllDiv, /*!< Main pll clock divider*/
824 kCLOCK_FrgSFro, /*!< 16MHz FRO */
825 kCLOCK_FrgFFro, /*!< FRO48/60 */
826 } sfg_clock_src;
827 uint8_t divider; /*!< Denominator of the fractional divider. */
828 uint8_t mult; /*!< Numerator of the fractional divider. */
829} clock_frg_clk_config_t;
830
831/*******************************************************************************
832 * API
833 ******************************************************************************/
834
835#if defined(__cplusplus)
836extern "C" {
837#endif /* __cplusplus */
838
839static inline void CLOCK_EnableClock(clock_ip_name_t clk)
840{
841 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
842
843 switch (index)
844 {
845 case CLK_CTL0_PSCCTL0:
846 CLKCTL0->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
847 break;
848 case CLK_CTL0_PSCCTL1:
849 CLKCTL0->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
850 break;
851 case CLK_CTL0_PSCCTL2:
852 CLKCTL0->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
853 break;
854 case CLK_CTL1_PSCCTL0:
855 CLKCTL1->PSCCTL0_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
856 break;
857 case CLK_CTL1_PSCCTL1:
858 CLKCTL1->PSCCTL1_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
859 break;
860 case CLK_CTL1_PSCCTL2:
861 CLKCTL1->PSCCTL2_SET = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
862 break;
863 default:
864 assert(false);
865 break;
866 }
867}
868
869static inline void CLOCK_DisableClock(clock_ip_name_t clk)
870{
871 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
872 switch (index)
873 {
874 case CLK_CTL0_PSCCTL0:
875 CLKCTL0->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
876 break;
877 case CLK_CTL0_PSCCTL1:
878 CLKCTL0->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
879 break;
880 case CLK_CTL0_PSCCTL2:
881 CLKCTL0->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
882 break;
883 case CLK_CTL1_PSCCTL0:
884 CLKCTL1->PSCCTL0_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
885 break;
886 case CLK_CTL1_PSCCTL1:
887 CLKCTL1->PSCCTL1_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
888 break;
889 case CLK_CTL1_PSCCTL2:
890 CLKCTL1->PSCCTL2_CLR = (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
891 break;
892 default:
893 assert(false);
894 break;
895 }
896}
897/**
898 * @brief Configure the clock selection muxes.
899 * @param connection : Clock to be configured.
900 * @return Nothing
901 */
902void CLOCK_AttachClk(clock_attach_id_t connection);
903/**
904 * @brief Setup peripheral clock dividers.
905 * @param div_name : Clock divider name
906 * @param divider : Value to be divided.
907 * @return Nothing
908 */
909void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divider);
910/*! @brief Return Frequency of selected clock
911 * @return Frequency of selected clock
912 */
913uint32_t CLOCK_GetFreq(clock_name_t clockName);
914
915/*! @brief Return Input frequency for the Fractional baud rate generator
916 * @return Input Frequency for FRG
917 */
918uint32_t CLOCK_GetFRGClock(uint32_t id);
919
920/*! @brief Set output of the Fractional baud rate generator
921 * @param config : Configuration to set to FRGn clock.
922 */
923void CLOCK_SetFRGClock(const clock_frg_clk_config_t *config);
924
925/*! @brief Return Frequency of FRO 16MHz
926 * @return Frequency of FRO 12MHz
927 */
928static inline uint32_t CLOCK_GetSFroFreq(void)
929{
930 return CLK_FRO_16MHZ;
931}
932/*! @brief Return Frequency of SYSPLL
933 * @return Frequency of SYSPLL
934 */
935uint32_t CLOCK_GetSysPllFreq(void);
936/*! @brief Get current output frequency of specific System PLL PFD.
937 * @param pfd : pfd name to get frequency.
938 * @return Frequency of SYSPLL PFD.
939 */
940uint32_t CLOCK_GetSysPfdFreq(clock_pfd_t pfd);
941/*! @brief Return Frequency of AUDIO PLL
942 * @return Frequency of AUDIO PLL
943 */
944uint32_t CLOCK_GetAudioPllFreq(void);
945/*! @brief Get current output frequency of specific Audio PLL PFD.
946 * @param pfd : pfd name to get frequency.
947 * @return Frequency of AUDIO PLL PFD.
948 */
949uint32_t CLOCK_GetAudioPfdFreq(clock_pfd_t pfd);
950/*! @brief Return Frequency of High-Freq output of FRO
951 * @return Frequency of High-Freq output of FRO
952 */
953uint32_t CLOCK_GetFFroFreq(void);
954/*! @brief Return Frequency of main clk
955 * @return Frequency of main clk
956 */
957uint32_t CLOCK_GetMainClkFreq(void);
958/*! @brief Return Frequency of DSP main clk
959 * @return Frequency of DSP main clk
960 */
961uint32_t CLOCK_GetDspMainClkFreq(void);
962/*! @brief Return Frequency of ACMP clk
963 * @return Frequency of ACMP clk
964 */
965uint32_t CLOCK_GetAcmpClkFreq(void);
966/*! @brief Return Frequency of DMIC clk
967 * @return Frequency of DMIC clk
968 */
969uint32_t CLOCK_GetDmicClkFreq(void);
970/*! @brief Return Frequency of USB clk
971 * @return Frequency of USB clk
972 */
973uint32_t CLOCK_GetUsbClkFreq(void);
974/*! @brief Return Frequency of SDIO clk
975 * @param id : SDIO index to get frequency.
976 * @return Frequency of SDIO clk
977 */
978uint32_t CLOCK_GetSdioClkFreq(uint32_t id);
979/*! @brief Return Frequency of I3C clk
980 * @return Frequency of I3C clk
981 */
982uint32_t CLOCK_GetI3cClkFreq(void);
983/*! @brief Return Frequency of systick clk
984 * @return Frequency of systick clk
985 */
986uint32_t CLOCK_GetSystickClkFreq(void);
987/*! @brief Return Frequency of WDT clk
988 * @param id : WDT index to get frequency.
989 * @return Frequency of WDT clk
990 */
991uint32_t CLOCK_GetWdtClkFreq(uint32_t id);
992/*! @brief Return Frequency of mclk
993 * @return Frequency of mclk clk
994 */
995uint32_t CLOCK_GetMclkClkFreq(void);
996/*! @brief Return Frequency of sct
997 * @return Frequency of sct clk
998 */
999uint32_t CLOCK_GetSctClkFreq(void);
1000/*! @brief Enable/Disable sys osc clock from external crystal clock.
1001 * @param enable : true to enable system osc clock, false to bypass system osc.
1002 * @param enableLowPower : true to enable low power mode, false to enable high gain mode.
1003 * @param delay_us : Delay time after OSC power up.
1004 */
1005void CLOCK_EnableSysOscClk(bool enable, bool enableLowPower, uint32_t delay_us);
1006/*! @brief Return Frequency of sys osc Clock
1007 * @return Frequency of sys osc Clock. Or CLK_IN pin frequency.
1008 */
1009static inline uint32_t CLOCK_GetXtalInClkFreq(void)
1010{
1011 return (CLKCTL0->SYSOSCBYPASS == 0U) ? g_xtalFreq : ((CLKCTL0->SYSOSCBYPASS == 1U) ? g_clkinFreq : 0U);
1012}
1013
1014/*! @brief Return Frequency of MCLK Input Clock
1015 * @return Frequency of MCLK input Clock.
1016 */
1017static inline uint32_t CLOCK_GetMclkInClkFreq(void)
1018{
1019 return g_mclkFreq;
1020}
1021
1022/*! @brief Return Frequency of Lower power osc
1023 * @return Frequency of LPOSC
1024 */
1025static inline uint32_t CLOCK_GetLpOscFreq(void)
1026{
1027 return CLK_LPOSC_1MHZ;
1028}
1029/*! @brief Return Frequency of 32kHz osc
1030 * @return Frequency of 32kHz osc
1031 */
1032static inline uint32_t CLOCK_GetOsc32KFreq(void)
1033{
1034 return ((CLKCTL0->OSC32KHZCTL0 & CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK) != 0UL) ? CLK_RTC_32K_CLK : 0U;
1035}
1036/*! @brief Enables and disables 32kHz osc
1037 * @param enable : true to enable 32k osc clock, false to disable clock
1038 */
1039static inline void CLOCK_EnableOsc32K(bool enable)
1040{
1041 if (enable)
1042 {
1043 CLKCTL0->OSC32KHZCTL0 |= CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK;
1044 }
1045 else
1046 {
1047 CLKCTL0->OSC32KHZCTL0 &= ~CLKCTL0_OSC32KHZCTL0_ENA32KHZ_MASK;
1048 }
1049}
1050
1051/*! @brief Return Frequency of 32khz wake clk
1052 * @return Frequency of 32kHz wake clk
1053 */
1054static inline uint32_t CLOCK_GetWakeClk32KFreq(void)
1055{
1056 return ((CLKCTL0->WAKECLK32KHZSEL & CLKCTL0_WAKECLK32KHZSEL_SEL_MASK) != 0UL) ?
1057 CLOCK_GetLpOscFreq() / ((CLKCTL0->WAKECLK32KHZDIV & 0xffU) + 1U) :
1058 CLOCK_GetOsc32KFreq();
1059}
1060/*!
1061 * @brief Set the XTALIN (system OSC) frequency based on board setting.
1062 *
1063 * @param freq : The XTAL input clock frequency in Hz.
1064 */
1065static inline void CLOCK_SetXtalFreq(uint32_t freq)
1066{
1067 g_xtalFreq = freq;
1068}
1069/*!
1070 * @brief Set the CLKIN (CLKIN pin) frequency based on board setting.
1071 *
1072 * @param freq : The CLK_IN pin input clock frequency in Hz.
1073 */
1074static inline void CLOCK_SetClkinFreq(uint32_t freq)
1075{
1076 g_clkinFreq = freq;
1077}
1078/*!
1079 * @brief Set the MCLK in (mclk_in) clock frequency based on board setting.
1080 *
1081 * @param freq : The MCLK input clock frequency in Hz.
1082 */
1083static inline void CLOCK_SetMclkFreq(uint32_t freq)
1084{
1085 g_mclkFreq = freq;
1086}
1087
1088/*! @brief Return Frequency of Flexcomm functional Clock
1089 * @param id : flexcomm index to get frequency.
1090 * @return Frequency of Flexcomm functional Clock
1091 */
1092uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
1093/*! @brief Return Frequency of Ctimer Clock
1094 * @param id : ctimer index to get frequency.
1095 * @return Frequency of Ctimer Clock
1096 */
1097uint32_t CLOCK_GetCtimerClkFreq(uint32_t id);
1098/*! @brief Return Frequency of ClockOut
1099 * @return Frequency of ClockOut
1100 */
1101uint32_t CLOCK_GetClockOutClkFreq(void);
1102/*! @brief Return Frequency of Adc Clock
1103 * @return Frequency of Adc Clock.
1104 */
1105uint32_t CLOCK_GetAdcClkFreq(void);
1106/*! @brief Return Frequency of Flexspi Clock
1107 * @return Frequency of Flexspi.
1108 */
1109uint32_t CLOCK_GetFlexspiClkFreq(void);
1110#ifndef __XCC__
1111/**
1112 * brief Enable FFRO 48M/60M clock.
1113 * param ffroFreq : target fro frequency.
1114 * return Nothing
1115 */
1116void CLOCK_EnableFfroClk(clock_ffro_freq_t ffroFreq);
1117/**
1118 * brief Enable SFRO clock.
1119 * param Nothing
1120 * return Nothing
1121 */
1122void CLOCK_EnableSfroClk(void);
1123/*! @brief Initialize the System PLL.
1124 * @param config : Configuration to set to PLL.
1125 */
1126#endif /* __XCC__ */
1127
1128void CLOCK_InitSysPll(const clock_sys_pll_config_t *config);
1129/*! brief Deinit the System PLL.
1130 * param none.
1131 */
1132static inline void CLOCK_DeinitSysPll(void)
1133{
1134 /* Set System PLL Reset & HOLDRINGOFF_ENA */
1135 CLKCTL0->SYSPLL0CTL0 |= CLKCTL0_SYSPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL0_SYSPLL0CTL0_RESET_MASK;
1136 /* Power down System PLL*/
1137 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_SYSPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_SYSPLLANA_PD_MASK;
1138}
1139/*! @brief Initialize the System PLL PFD.
1140 * @param pfd : Which PFD clock to enable.
1141 * @param divider : The PFD divider value.
1142 * @note It is recommended that PFD settings are kept between 12-35.
1143 */
1144void CLOCK_InitSysPfd(clock_pfd_t pfd, uint8_t divider);
1145/*! brief Disable the audio PLL PFD.
1146 * param pfd : Which PFD clock to disable.
1147 */
1148static inline void CLOCK_DeinitSysPfd(clock_pfd_t pfd)
1149{
1150 CLKCTL0->SYSPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd));
1151}
1152/*! @brief Initialize the audio PLL.
1153 * @param config : Configuration to set to PLL.
1154 */
1155void CLOCK_InitAudioPll(const clock_audio_pll_config_t *config);
1156/*! brief Deinit the Audio PLL.
1157 * param none.
1158 */
1159static inline void CLOCK_DeinitAudioPll(void)
1160{
1161 /* Set Audio PLL Reset & HOLDRINGOFF_ENA */
1162 CLKCTL1->AUDIOPLL0CTL0 |= CLKCTL1_AUDIOPLL0CTL0_HOLDRINGOFF_ENA_MASK | CLKCTL1_AUDIOPLL0CTL0_RESET_MASK;
1163 /* Power down Audio PLL */
1164 SYSCTL0->PDRUNCFG0_SET = SYSCTL0_PDRUNCFG0_AUDPLLLDO_PD_MASK | SYSCTL0_PDRUNCFG0_AUDPLLANA_PD_MASK;
1165}
1166/*! @brief Initialize the audio PLL PFD.
1167 * @param pfd : Which PFD clock to enable.
1168 * @param divider : The PFD divider value.
1169 * @note It is recommended that PFD settings are kept between 12-35.
1170 */
1171void CLOCK_InitAudioPfd(clock_pfd_t pfd, uint8_t divider);
1172/*! brief Disable the audio PLL PFD.
1173 * param pfd : Which PFD clock to disable.
1174 */
1175static inline void CLOCK_DeinitAudioPfd(uint32_t pfd)
1176{
1177 CLKCTL1->AUDIOPLL0PFD |= ((uint32_t)CLKCTL1_AUDIOPLL0PFD_PFD0_CLKGATE_MASK << (8UL * (uint32_t)pfd));
1178}
1179/*! @brief Enable USB HS device PLL clock.
1180 *
1181 * This function enables USB HS device PLL clock.
1182 */
1183void CLOCK_EnableUsbhsDeviceClock(void);
1184/*! @brief Enable USB HS host PLL clock.
1185 *
1186 * This function enables USB HS host PLL clock.
1187 */
1188void CLOCK_EnableUsbhsHostClock(void);
1189/*! brief Enable USB hs0PhyPll clock.
1190 *
1191 * param src USB HS clock source.
1192 * param freq The frequency specified by src.
1193 * retval true The clock is set successfully.
1194 * retval false The clock source is invalid to get proper USB HS clock.
1195 */
1196bool CLOCK_EnableUsbHs0PhyPllClock(clock_attach_id_t src, uint32_t freq);
1197#if defined(__cplusplus)
1198}
1199#endif /* __cplusplus */
1200
1201/*! @} */
1202
1203#endif /* _FSL_CLOCK_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_dsp.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_dsp.c
new file mode 100644
index 000000000..68eae4ac5
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_dsp.c
@@ -0,0 +1,107 @@
1/*
2 * Copyright 2019-2020, NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_dsp.h"
9#include "fsl_reset.h"
10#include "fsl_common.h"
11#include "fsl_power.h"
12
13/*******************************************************************************
14 * Definitions
15 ******************************************************************************/
16
17/* Component ID definition, used by tools. */
18#ifndef FSL_COMPONENT_ID
19#define FSL_COMPONENT_ID "platform.drivers.dsp"
20#endif
21
22/*******************************************************************************
23 * Variables
24 ******************************************************************************/
25
26/*******************************************************************************
27 * Prototypes
28 ******************************************************************************/
29
30/*******************************************************************************
31 * Code
32 ******************************************************************************/
33
34/*!
35 * @brief Initializing DSP core.
36 *
37 * Power up DSP TCM
38 * Enable DSP clock
39 * Reset DSP peripheral
40 */
41void DSP_Init(void)
42{
43 if ((SYSCTL0->PDRUNCFG1 & (SYSCTL0_PDRUNCFG1_DSPCACHE_REGF_APD_MASK | SYSCTL0_PDRUNCFG1_DSPCACHE_REGF_PPD_MASK |
44 SYSCTL0_PDRUNCFG1_DSPTCM_REGF_APD_MASK | SYSCTL0_PDRUNCFG1_DSPTCM_REGF_PPD_MASK)) != 0U)
45 {
46 /* Not powered on. */
47 POWER_DisablePD(kPDRUNCFG_APD_DSP_TCM_REGF);
48 POWER_DisablePD(kPDRUNCFG_PPD_DSP_TCM_REGF);
49 POWER_DisablePD(kPDRUNCFG_APD_DSP_CACHE_REGF);
50 POWER_DisablePD(kPDRUNCFG_PPD_DSP_CACHE_REGF);
51 POWER_ApplyPD();
52
53 RESET_PeripheralReset(kDSP_RST_SHIFT_RSTn);
54 }
55 else if ((RSTCTL0->PRSTCTL0 & RSTCTL0_PRSTCTL0_HIFI_DSP_MASK) != 0U)
56 {
57 /* Powered on but not reset. */
58 RESET_ClearPeripheralReset(kDSP_RST_SHIFT_RSTn);
59 }
60 else
61 {
62 /* Already powered on and reset, do nothing. */
63 }
64}
65
66/*!
67 * @brief Deinit DSP core.
68 *
69 * Power down DSP TCM
70 * Disable DSP clock
71 * Set DSP peripheral reset
72 */
73void DSP_Deinit(void)
74{
75 DSP_Stop();
76
77 POWER_EnablePD(kPDRUNCFG_APD_DSP_TCM_REGF);
78 POWER_EnablePD(kPDRUNCFG_PPD_DSP_TCM_REGF);
79 POWER_EnablePD(kPDRUNCFG_APD_DSP_CACHE_REGF);
80 POWER_EnablePD(kPDRUNCFG_PPD_DSP_CACHE_REGF);
81 POWER_ApplyPD();
82}
83/*!
84 * @brief Copy DSP image to destination address.
85 *
86 * Copy DSP image from source address to destination address with given size.
87 *
88 * @param dspCopyImage Structure contains information for DSP copy image to destination address.
89 */
90void DSP_CopyImage(dsp_copy_image_t *dspCopyImage)
91{
92 assert(dspCopyImage != NULL);
93 assert(dspCopyImage->srcAddr != NULL);
94 assert(dspCopyImage->destAddr != NULL);
95
96 uint32_t *srcAddr = dspCopyImage->srcAddr;
97 uint32_t *destAddr = dspCopyImage->destAddr;
98 uint32_t size = dspCopyImage->size;
99
100 assert((size & 3U) == 0U);
101
102 while (size > 0U)
103 {
104 *destAddr++ = *srcAddr++;
105 size -= 4U;
106 }
107}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_dsp.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_dsp.h
new file mode 100644
index 000000000..f858146cf
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_dsp.h
@@ -0,0 +1,96 @@
1/*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2019 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BS
7 */
8#ifndef _FSL_DSP_H_
9#define _FSL_DSP_H_
10
11#include <stdint.h>
12#include "fsl_device_registers.h"
13
14/*!
15 * @addtogroup dsp
16 * @{
17 */
18
19/*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
23/*! @name Driver version */
24/*@{*/
25/*! @brief reset driver version 2.1.1. */
26#define FSL_DSP_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
27/*@}*/
28
29/*!
30 * @brief Structure for DSP copy image to destination address
31 *
32 * Defines start and destination address for copying image with given size.
33 */
34typedef struct _dsp_copy_image
35{
36 uint32_t *srcAddr;
37 uint32_t *destAddr;
38 uint32_t size;
39} dsp_copy_image_t;
40
41/*******************************************************************************
42 * API
43 ******************************************************************************/
44#if defined(__cplusplus)
45extern "C" {
46#endif
47
48/*!
49 * @brief Initializing DSP core.
50 *
51 * Power up DSP TCM
52 * Enable DSP clock
53 * Reset DSP peripheral
54 */
55void DSP_Init(void);
56/*!
57 * @brief Deinit DSP core.
58 *
59 * Power down DSP TCM
60 * Disable DSP clock
61 * Set DSP peripheral reset
62 */
63void DSP_Deinit(void);
64
65/*!
66 * @brief Copy DSP image to destination address.
67 *
68 * Copy DSP image from source address to destination address with given size.
69 *
70 * @param dspCopyImage Structure contains information for DSP copy image to destination address.
71 */
72void DSP_CopyImage(dsp_copy_image_t *dspCopyImage);
73
74/*!
75 * @brief Start DSP core.
76 */
77static inline void DSP_Start(void)
78{
79 SYSCTL0->DSPSTALL = 0x0;
80}
81
82/*!
83 * @brief Stop DSP core.
84 */
85static inline void DSP_Stop(void)
86{
87 SYSCTL0->DSPSTALL = 0x1;
88}
89
90#if defined(__cplusplus)
91}
92#endif
93
94/*! @} */
95
96#endif /* _FSL_RESET_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_iap.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_iap.c
new file mode 100644
index 000000000..f8845bacc
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_iap.c
@@ -0,0 +1,222 @@
1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 *
7 */
8
9#include "fsl_iap.h"
10
11/* Component ID definition, used by tools. */
12#ifndef FSL_COMPONENT_ID
13#define FSL_COMPONENT_ID "platform.drivers.iap"
14#endif
15
16/*!
17 * @addtogroup rom_api
18 * @{
19 */
20
21/*******************************************************************************
22 * Definitions
23 ******************************************************************************/
24/*! @brief FLEXSPI Flash driver API Interface */
25typedef struct
26{
27 uint32_t version;
28 status_t (*init)(uint32_t instance, flexspi_nor_config_t *config);
29 status_t (*page_program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dstAddr, const uint32_t *src);
30 status_t (*erase_all)(uint32_t instance, flexspi_nor_config_t *config);
31 status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length);
32 status_t (*erase_sector)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
33 status_t (*erase_block)(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
34 status_t (*get_config)(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option);
35 status_t (*read)(uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes);
36 status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer);
37 status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq);
38 status_t (*set_clock_source)(uint32_t clockSrc);
39 void (*config_clock)(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode);
40} flexspi_nor_flash_driver_t;
41
42/*! @brief OTP driver API Interface */
43typedef struct
44{
45 status_t (*init)(uint32_t src_clk_freq);
46 status_t (*deinit)(void);
47 status_t (*fuse_read)(uint32_t addr, uint32_t *data);
48 status_t (*fuse_program)(uint32_t addr, uint32_t data, bool lock);
49 status_t (*crc_calc)(uint32_t *src, uint32_t numberOfWords, uint32_t *crcChecksum);
50 status_t (*reload)(void);
51 status_t (*crc_check)(uint32_t start_addr, uint32_t end_addr, uint32_t crc_addr);
52} ocotp_driver_t;
53
54/*!
55 * @brief Root of the bootloader API tree.
56 *
57 * An instance of this struct resides in read-only memory in the bootloader. It
58 * provides a user application access to APIs exported by the bootloader.
59 *
60 * @note The order of existing fields must not be changed.
61 */
62typedef struct BootloaderTree
63{
64 void (*runBootloader)(iap_boot_option_t *arg); /*!< Function to start the bootloader executing. */
65 uint32_t version; /*!< Bootloader version number. */
66 const char *copyright; /*!< Copyright string. */
67 const uint32_t reserved0;
68 const uint32_t reserved1;
69 const uint32_t reserved2;
70 const uint32_t reserved3;
71 const flexspi_nor_flash_driver_t *flexspiNorDriver; /*!< FlexSPI NOR FLASH Driver API. */
72 const ocotp_driver_t *otpDriver; /*!< OTP driver API. */
73 const uint32_t reserved4;
74} bootloader_tree_t;
75
76/*******************************************************************************
77 * Definitions
78 ******************************************************************************/
79#define ROM_API_TREE ((uint32_t *)FSL_ROM_API_BASE_ADDR)
80#define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)ROM_API_TREE)
81
82/*! Get pointer to flexspi/otp driver API table in ROM. */
83#define FLEXSPI_API_TREE BOOTLOADER_API_TREE_POINTER->flexspiNorDriver
84#define OTP_API_TREE BOOTLOADER_API_TREE_POINTER->otpDriver
85
86/*******************************************************************************
87 * Variables
88 ******************************************************************************/
89
90/*******************************************************************************
91 * runBootloader API
92 ******************************************************************************/
93void IAP_RunBootLoader(iap_boot_option_t *option)
94{
95 BOOTLOADER_API_TREE_POINTER->runBootloader(option);
96}
97
98/*******************************************************************************
99 * FlexSPI NOR driver
100 ******************************************************************************/
101status_t IAP_FlexspiNorInit(uint32_t instance, flexspi_nor_config_t *config)
102{
103 return FLEXSPI_API_TREE->init(instance, config);
104}
105
106status_t IAP_FlexspiNorPageProgram(uint32_t instance,
107 flexspi_nor_config_t *config,
108 uint32_t dstAddr,
109 const uint32_t *src)
110{
111 return FLEXSPI_API_TREE->page_program(instance, config, dstAddr, src);
112}
113
114status_t IAP_FlexspiNorEraseAll(uint32_t instance, flexspi_nor_config_t *config)
115{
116 return FLEXSPI_API_TREE->erase_all(instance, config);
117}
118
119status_t IAP_FlexspiNorErase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length)
120{
121 return FLEXSPI_API_TREE->erase(instance, config, start, length);
122}
123
124status_t IAP_FlexspiNorEraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address)
125{
126 return FLEXSPI_API_TREE->erase_sector(instance, config, address);
127}
128
129status_t IAP_FlexspiNorEraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t address)
130{
131 return FLEXSPI_API_TREE->erase_block(instance, config, address);
132}
133
134status_t IAP_FlexspiNorGetConfig(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option)
135{
136 return FLEXSPI_API_TREE->get_config(instance, config, option);
137}
138
139status_t IAP_FlexspiNorRead(
140 uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes)
141{
142 return FLEXSPI_API_TREE->read(instance, config, dst, start, bytes);
143}
144
145status_t IAP_FlexspiXfer(uint32_t instance, flexspi_xfer_t *xfer)
146{
147 return FLEXSPI_API_TREE->xfer(instance, xfer);
148}
149
150status_t IAP_FlexspiUpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq)
151{
152 return FLEXSPI_API_TREE->update_lut(instance, seqIndex, lutBase, numberOfSeq);
153}
154
155status_t IAP_FlexspiSetClockSource(uint32_t clockSrc)
156{
157 return FLEXSPI_API_TREE->set_clock_source(clockSrc);
158}
159
160void IAP_FlexspiConfigClock(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode)
161{
162 FLEXSPI_API_TREE->config_clock(instance, freqOption, sampleClkMode);
163}
164
165AT_QUICKACCESS_SECTION_CODE(status_t IAP_FlexspiNorAutoConfig(uint32_t instance,
166 flexspi_nor_config_t *config,
167 serial_nor_config_option_t *option))
168{
169 /* Wait until the FLEXSPI is idle */
170 register uint32_t delaycnt = 10000u;
171 status_t status;
172
173 while ((delaycnt--) != 0U)
174 {
175 }
176
177 status = FLEXSPI_API_TREE->get_config(instance, config, option);
178 if (status == kStatus_Success)
179 {
180 status = FLEXSPI_API_TREE->init(instance, config);
181 }
182
183 return status;
184}
185
186/*******************************************************************************
187 * OTP driver
188 ******************************************************************************/
189status_t IAP_OtpInit(uint32_t src_clk_freq)
190{
191 return OTP_API_TREE->init(src_clk_freq);
192}
193
194status_t IAP_OtpDeinit(void)
195{
196 return OTP_API_TREE->deinit();
197}
198
199status_t IAP_OtpFuseRead(uint32_t addr, uint32_t *data)
200{
201 return OTP_API_TREE->fuse_read(addr, data);
202}
203
204status_t IAP_OtpFuseProgram(uint32_t addr, uint32_t data, bool lock)
205{
206 return OTP_API_TREE->fuse_program(addr, data, lock);
207}
208
209status_t IAP_OtpCrcCalc(uint32_t *src, uint32_t numberOfWords, uint32_t *crcChecksum)
210{
211 return OTP_API_TREE->crc_calc(src, numberOfWords, crcChecksum);
212}
213
214status_t IAP_OtpShadowRegisterReload(void)
215{
216 return OTP_API_TREE->reload();
217}
218
219status_t IAP_OtpCrcCheck(uint32_t start_addr, uint32_t end_addr, uint32_t crc_addr)
220{
221 return OTP_API_TREE->crc_check(start_addr, end_addr, crc_addr);
222}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_iap.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_iap.h
new file mode 100644
index 000000000..3726c9609
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_iap.h
@@ -0,0 +1,726 @@
1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef __FSL_IAP_H_
9#define __FSL_IAP_H_
10
11#include "fsl_common.h"
12/*!
13 * @addtogroup IAP_driver
14 * @{
15 */
16
17/*! @file */
18
19/*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22/*! @name Driver version */
23/*@{*/
24/*! @brief IAP driver version 2.1.1. */
25#define FSL_IAP_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
26/*@}*/
27
28/*!
29 * @addtogroup iap_flexspi_driver
30 * @{
31 */
32
33/*! @brief FlexSPI LUT command */
34#define NOR_CMD_INDEX_READ CMD_INDEX_READ /*!< 0 */
35#define NOR_CMD_INDEX_READSTATUS CMD_INDEX_READSTATUS /*!< 1 */
36#define NOR_CMD_INDEX_WRITEENABLE CMD_INDEX_WRITEENABLE /*!< 2 */
37#define NOR_CMD_INDEX_ERASESECTOR 3 /*!< 3 */
38#define NOR_CMD_INDEX_PAGEPROGRAM CMD_INDEX_WRITE /*!< 4 */
39#define NOR_CMD_INDEX_CHIPERASE 5 /*!< 5 */
40#define NOR_CMD_INDEX_DUMMY 6 /*!< 6 */
41#define NOR_CMD_INDEX_ERASEBLOCK 7 /*!< 7 */
42
43#define NOR_CMD_LUT_SEQ_IDX_READ \
44 CMD_LUT_SEQ_IDX_READ /*!< 0 READ LUT sequence id in lookupTable stored in config block */
45#define NOR_CMD_LUT_SEQ_IDX_READSTATUS \
46 CMD_LUT_SEQ_IDX_READSTATUS /*!< 1 Read Status LUT sequence id in lookupTable stored in config block */
47#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
48 2 /*!< 2 Read status DPI/QPI/OPI sequence id in lookupTable stored in config block */
49#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE \
50 CMD_LUT_SEQ_IDX_WRITEENABLE /*!< 3 Write Enable sequence id in lookupTable stored in config block */
51#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
52 4 /*!< 4 Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block */
53#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5 /*!< 5 Erase Sector sequence id in lookupTable stored in config block */
54#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8 /*!< 8 Erase Block sequence id in lookupTable stored in config block */
55#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM \
56 CMD_LUT_SEQ_IDX_WRITE /*!< 9 Program sequence id in lookupTable stored in config block */
57#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11 /*!< 11 Chip Erase sequence in lookupTable id stored in config block */
58#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13 /*!< 13 Read SFDP sequence in lookupTable id stored in config block */
59#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
60 14 /*!< 14 Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */
61#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
62 15 /*!< 15 Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk */
63
64/*!
65 * @name FlexSPI status.
66 * @{
67 */
68/*! @brief FlexSPI Driver status group. */
69enum
70{
71 kStatusGroup_FlexSPI = 60,
72 kStatusGroup_FlexSPINOR = 201,
73};
74
75/*! @brief FlexSPI Driver status. */
76enum _flexspi_status
77{
78 kStatus_FLEXSPI_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< API is executed successfully*/
79 kStatus_FLEXSPI_Fail = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< API is executed fails*/
80 kStatus_FLEXSPI_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< Invalid argument*/
81 kStatus_FLEXSPI_SequenceExecutionTimeout =
82 MAKE_STATUS(kStatusGroup_FlexSPI, 0), /*!< The FlexSPI Sequence Execution timeout*/
83 kStatus_FLEXSPI_InvalidSequence = MAKE_STATUS(kStatusGroup_FlexSPI, 1), /*!< The FlexSPI LUT sequence invalid*/
84 kStatus_FLEXSPI_DeviceTimeout = MAKE_STATUS(kStatusGroup_FlexSPI, 2), /*!< The FlexSPI device timeout*/
85 kStatus_FLEXSPINOR_ProgramFail =
86 MAKE_STATUS(kStatusGroup_FlexSPINOR, 0), /*!< Status for Page programming failure */
87 kStatus_FLEXSPINOR_EraseSectorFail =
88 MAKE_STATUS(kStatusGroup_FlexSPINOR, 1), /*!< Status for Sector Erase failure */
89 kStatus_FLEXSPINOR_EraseAllFail = MAKE_STATUS(kStatusGroup_FlexSPINOR, 2), /*!< Status for Chip Erase failure */
90 kStatus_FLEXSPINOR_WaitTimeout = MAKE_STATUS(kStatusGroup_FlexSPINOR, 3), /*!< Status for timeout */
91 kStatus_FLEXSPINOR_NotSupported = MAKE_STATUS(kStatusGroup_FlexSPINOR, 4), /* Status for PageSize overflow */
92 kStatus_FLEXSPINOR_WriteAlignmentError =
93 MAKE_STATUS(kStatusGroup_FlexSPINOR, 5), /*!< Status for Alignement error */
94 kStatus_FLEXSPINOR_CommandFailure =
95 MAKE_STATUS(kStatusGroup_FlexSPINOR, 6), /*!< Status for Erase/Program Verify Error */
96 kStatus_FLEXSPINOR_SFDP_NotFound = MAKE_STATUS(kStatusGroup_FlexSPINOR, 7), /*!< Status for SFDP read failure */
97 kStatus_FLEXSPINOR_Unsupported_SFDP_Version =
98 MAKE_STATUS(kStatusGroup_FlexSPINOR, 8), /*!< Status for Unrecognized SFDP version */
99 kStatus_FLEXSPINOR_Flash_NotFound =
100 MAKE_STATUS(kStatusGroup_FlexSPINOR, 9), /*!< Status for Flash detection failure */
101 kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed =
102 MAKE_STATUS(kStatusGroup_FlexSPINOR, 10), /*!< Status for DDR Read dummy probe failure */
103};
104/*! @} */
105
106/*! @brief Flash Configuration Option0 device_type. */
107enum
108{
109 kSerialNorCfgOption_Tag = 0x0c,
110 kSerialNorCfgOption_DeviceType_ReadSFDP_SDR = 0,
111 kSerialNorCfgOption_DeviceType_ReadSFDP_DDR = 1,
112 kSerialNorCfgOption_DeviceType_HyperFLASH1V8 = 2,
113 kSerialNorCfgOption_DeviceType_HyperFLASH3V0 = 3,
114 kSerialNorCfgOption_DeviceType_MacronixOctalDDR = 4,
115 kSerialNorCfgOption_DeviceType_MacronixOctalSDR = 5, /* For RT600 devcies only. */
116 kSerialNorCfgOption_DeviceType_MicronOctalDDR = 6,
117 kSerialNorCfgOption_DeviceType_MicronOctalSDR = 7, /* For RT600 devcies only. */
118 kSerialNorCfgOption_DeviceType_AdestoOctalDDR = 8,
119 kSerialNorCfgOption_DeviceType_AdestoOctalSDR = 9, /* For RT600 devcies only. */
120};
121
122/*! @brief Flash Configuration Option0 quad_mode_setting. */
123enum
124{
125 kSerialNorQuadMode_NotConfig = 0,
126 kSerialNorQuadMode_StatusReg1_Bit6 = 1,
127 kSerialNorQuadMode_StatusReg2_Bit1 = 2,
128 kSerialNorQuadMode_StatusReg2_Bit7 = 3,
129 kSerialNorQuadMode_StatusReg2_Bit1_0x31 = 4,
130};
131
132/*! @brief Flash Configuration Option0 misc_mode. */
133enum
134{
135 kSerialNorEnhanceMode_Disabled = 0,
136 kSerialNorEnhanceMode_0_4_4_Mode = 1,
137 kSerialNorEnhanceMode_0_8_8_Mode = 2,
138 kSerialNorEnhanceMode_DataOrderSwapped = 3,
139 kSerialNorEnhanceMode_2ndPinMux = 4,
140};
141
142/*! @brief FLEXSPI_RESET_PIN boot configurations in OTP */
143enum
144{
145 kFlashResetLogic_Disabled = 0,
146 kFlashResetLogic_ResetPin = 1,
147 kFlashResetLogic_JedecHwReset = 2,
148};
149
150/*! @brief Flash Configuration Option1 flash_connection. */
151enum
152{
153 kSerialNorConnection_SinglePortA,
154 kSerialNorConnection_Parallel,
155 kSerialNorConnection_SinglePortB,
156 kSerialNorConnection_BothPorts
157};
158
159/*! @brief Serial NOR Configuration Option */
160typedef struct _serial_nor_config_option
161{
162 union
163 {
164 struct
165 {
166 uint32_t max_freq : 4; /*!< Maximum supported Frequency */
167 uint32_t misc_mode : 4; /*!< miscellaneous mode */
168 uint32_t quad_mode_setting : 4; /*!< Quad mode setting */
169 uint32_t cmd_pads : 4; /*!< Command pads */
170 uint32_t query_pads : 4; /*!< SFDP read pads */
171 uint32_t device_type : 4; /*!< Device type */
172 uint32_t option_size : 4; /*!< Option size, in terms of uint32_t, size = (option_size + 1) * 4 */
173 uint32_t tag : 4; /*!< Tag, must be 0x0E */
174 } B;
175 uint32_t U;
176 } option0;
177
178 union
179 {
180 struct
181 {
182 uint32_t dummy_cycles : 8; /*!< Dummy cycles before read */
183 uint32_t status_override : 8; /*!< Override status register value during device mode configuration */
184 uint32_t pinmux_group : 4; /*!< The pinmux group selection */
185 uint32_t dqs_pinmux_group : 4; /*!< The DQS Pinmux Group Selection */
186 uint32_t drive_strength : 4; /*!< The Drive Strength of FlexSPI Pads */
187 uint32_t flash_connection : 4; /*!< Flash connection option: 0 - Single Flash connected to port A, 1 - */
188 /*! Parallel mode, 2 - Single Flash connected to Port B */
189 } B;
190 uint32_t U;
191 } option1;
192
193} serial_nor_config_option_t;
194
195/*! @brief Flash Run Context */
196typedef union
197{
198 struct
199 {
200 uint8_t por_mode;
201 uint8_t current_mode;
202 uint8_t exit_no_cmd_sequence;
203 uint8_t restore_sequence;
204 } B;
205 uint32_t U;
206} flash_run_context_t;
207
208/*!@brief Flash Device Mode Configuration Sequence */
209enum
210{
211 kRestoreSequence_None = 0,
212 kRestoreSequence_HW_Reset = 1,
213 kRestoreSequence_4QPI_FF = 2,
214 kRestoreSequence_5QPI_FF = 3,
215 kRestoreSequence_8QPI_FF = 4,
216 kRestoreSequence_Send_F0 = 5,
217 kRestoreSequence_Send_66_99 = 6,
218 kRestoreSequence_Send_6699_9966 = 7,
219 kRestoreSequence_Send_06_FF = 8, /* Adesto EcoXIP */
220};
221
222/*!@brief Flash Config Mode Definition */
223enum
224{
225 kFlashInstMode_ExtendedSpi = 0x00,
226 kFlashInstMode_0_4_4_SDR = 0x01,
227 kFlashInstMode_0_4_4_DDR = 0x02,
228 kFlashInstMode_QPI_SDR = 0x41,
229 kFlashInstMode_QPI_DDR = 0x42,
230 kFlashInstMode_OPI_SDR = 0x81, /* For RT600 devices only. */
231 kFlashInstMode_OPI_DDR = 0x82,
232};
233
234/*!@brief Flash Device Type Definition */
235enum
236{
237 kFlexSpiDeviceType_SerialNOR = 1, /*!< Flash devices are Serial NOR */
238 kFlexSpiDeviceType_SerialNAND = 2, /*!< Flash devices are Serial NAND */
239 kFlexSpiDeviceType_SerialRAM = 3, /*!< Flash devices are Serial RAM/HyperFLASH */
240 kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, /*!< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */
241 kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, /*!< Flash deivce is MCP device, A1 is Serial NOR, A2 is Serial RAMs */
242};
243
244/*!@brief Flash Pad Definitions */
245enum
246{
247 kSerialFlash_1Pad = 1,
248 kSerialFlash_2Pads = 2,
249 kSerialFlash_4Pads = 4,
250 kSerialFlash_8Pads = 8,
251};
252
253/*!@brief FlexSPI LUT Sequence structure */
254typedef struct _lut_sequence
255{
256 uint8_t seqNum; /*!< Sequence Number, valid number: 1-16 */
257 uint8_t seqId; /*!< Sequence Index, valid number: 0-15 */
258 uint16_t reserved;
259} flexspi_lut_seq_t;
260
261/*!@brief Flash Configuration Command Type */
262enum
263{
264 kDeviceConfigCmdType_Generic, /*!< Generic command, for example: configure dummy cycles, drive strength, etc */
265 kDeviceConfigCmdType_QuadEnable, /*!< Quad Enable command */
266 kDeviceConfigCmdType_Spi2Xpi, /*!< Switch from SPI to DPI/QPI/OPI mode */
267 kDeviceConfigCmdType_Xpi2Spi, /*!< Switch from DPI/QPI/OPI to SPI mode */
268 kDeviceConfigCmdType_Spi2NoCmd, /*!< Switch to 0-4-4/0-8-8 mode */
269 kDeviceConfigCmdType_Reset, /*!< Reset device command */
270};
271
272/*!@brief FlexSPI Dll Time Block */
273typedef struct
274{
275 uint8_t time_100ps; /* Data valid time, in terms of 100ps */
276 uint8_t delay_cells; /* Data valid time, in terms of delay cells */
277} flexspi_dll_time_t;
278
279/*!@brief FlexSPI Memory Configuration Block */
280typedef struct _FlexSPIConfig
281{
282 uint32_t tag; /*!< [0x000-0x003] Tag, fixed value 0x42464346UL */
283 uint32_t version; /*!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */
284 uint32_t reserved0; /*!< [0x008-0x00b] Reserved for future use */
285 uint8_t readSampleClkSrc; /*!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */
286 uint8_t csHoldTime; /*!< [0x00d-0x00d] CS hold time, default value: 3 */
287 uint8_t csSetupTime; /*!< [0x00e-0x00e] CS setup time, default value: 3 */
288 uint8_t columnAddressWidth; /*!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For */
289 /*! Serial NAND, need to refer to datasheet */
290 uint8_t deviceModeCfgEnable; /*!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */
291 uint8_t
292 deviceModeType; /*!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, */
293 /*! Generic configuration, etc. */
294 uint16_t waitTimeCfgCommands; /*!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for */
295 /*! DPI/QPI/OPI switch or reset command */
296 flexspi_lut_seq_t
297 deviceModeSeq; /*!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt */
298 /*! sequence number, [31:16] Reserved */
299 uint32_t deviceModeArg; /*!< [0x018-0x01b] Argument/Parameter for device configuration */
300 uint8_t configCmdEnable; /*!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */
301 uint8_t configModeType[3]; /*!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */
302 flexspi_lut_seq_t
303 configCmdSeqs[3]; /*!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */
304 uint32_t reserved1; /*!< [0x02c-0x02f] Reserved for future use */
305 uint32_t configCmdArgs[3]; /*!< [0x030-0x03b] Arguments/Parameters for device Configuration commands */
306 uint32_t reserved2; /*!< [0x03c-0x03f] Reserved for future use */
307 uint32_t
308 controllerMiscOption; /*!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more */
309 /*! details */
310 uint8_t deviceType; /*!< [0x044-0x044] Device Type: See Flash Type Definition for more details */
311 uint8_t sflashPadType; /*!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */
312 uint8_t serialClkFreq; /*!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot */
313 /*! Chapter for more details */
314 uint8_t
315 lutCustomSeqEnable; /*!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot */
316 /*! be done using 1 LUT sequence, currently, only applicable to HyperFLASH */
317 uint32_t reserved3[2]; /*!< [0x048-0x04f] Reserved for future use */
318 uint32_t sflashA1Size; /*!< [0x050-0x053] Size of Flash connected to A1 */
319 uint32_t sflashA2Size; /*!< [0x054-0x057] Size of Flash connected to A2 */
320 uint32_t sflashB1Size; /*!< [0x058-0x05b] Size of Flash connected to B1 */
321 uint32_t sflashB2Size; /*!< [0x05c-0x05f] Size of Flash connected to B2 */
322 uint32_t csPadSettingOverride; /*!< [0x060-0x063] CS pad setting override value */
323 uint32_t sclkPadSettingOverride; /*!< [0x064-0x067] SCK pad setting override value */
324 uint32_t dataPadSettingOverride; /*!< [0x068-0x06b] data pad setting override value */
325 uint32_t dqsPadSettingOverride; /*!< [0x06c-0x06f] DQS pad setting override value */
326 uint32_t timeoutInMs; /*!< [0x070-0x073] Timeout threshold for read status command */
327 uint32_t commandInterval; /*!< [0x074-0x077] CS deselect interval between two commands */
328 flexspi_dll_time_t dataValidTime[2]; /*!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */
329 uint16_t busyOffset; /*!< [0x07c-0x07d] Busy offset, valid value: 0-31 */
330 uint16_t
331 busyBitPolarity; /*!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - */
332 /*! busy flag is 0 when flash device is busy */
333 uint32_t lookupTable[64]; /*!< [0x080-0x17f] Lookup table holds Flash command sequences */
334 flexspi_lut_seq_t lutCustomSeq[12]; /*!< [0x180-0x1af] Customizable LUT Sequences */
335 uint32_t reserved4[4]; /*!< [0x1b0-0x1bf] Reserved for future use */
336} flexspi_mem_config_t;
337
338/*!@brief FlexSPI Operation Type */
339typedef enum _FlexSPIOperationType
340{
341 kFlexSpiOperation_Command = 0, /*!< FlexSPI operation: Only command, both TX and */
342 /*! RX buffer are ignored. */
343 kFlexSpiOperation_Config = 1, /*!< FlexSPI operation: Configure device mode, the */
344 /*! TX FIFO size is fixed in LUT. */
345 kFlexSpiOperation_Write = 2, /*!< FlexSPI operation: Write, only TX buffer is */
346 /*! effective */
347 kFlexSpiOperation_Read = 3, /*!< FlexSPI operation: Read, only Rx Buffer is */
348 /*! effective. */
349 kFlexSpiOperation_End = kFlexSpiOperation_Read,
350} flexspi_operation_t;
351
352/*!@brief FlexSPI Transfer Context */
353typedef struct _FlexSpiXfer
354{
355 flexspi_operation_t operation; /*!< FlexSPI operation */
356 uint32_t baseAddress; /*!< FlexSPI operation base address */
357 uint32_t seqId; /*!< Sequence Id */
358 uint32_t seqNum; /*!< Sequence Number */
359 bool isParallelModeEnable; /*!< Is a parallel transfer */
360 uint32_t *txBuffer; /*!< Tx buffer */
361 uint32_t txSize; /*!< Tx size in bytes */
362 uint32_t *rxBuffer; /*!< Rx buffer */
363 uint32_t rxSize; /*!< Rx size in bytes */
364} flexspi_xfer_t;
365
366/*!@brief Serial NOR configuration block */
367typedef struct _flexspi_nor_config
368{
369 flexspi_mem_config_t memConfig; /*!< Common memory configuration info via FlexSPI */
370 uint32_t pageSize; /*!< Page size of Serial NOR */
371 uint32_t sectorSize; /*!< Sector size of Serial NOR */
372 uint8_t ipcmdSerialClkFreq; /*!< Clock frequency for IP command */
373 uint8_t isUniformBlockSize; /*!< Sector/Block size is the same */
374 uint8_t isDataOrderSwapped; /*!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */
375 uint8_t reserved0[1]; /*!< Reserved for future use */
376 uint8_t serialNorType; /*!< Serial NOR Flash type: 0/1/2/3 */
377 uint8_t needExitNoCmdMode; /*!< Need to exit NoCmd mode before other IP command */
378 uint8_t halfClkForNonReadCmd; /*!< Half the Serial Clock for non-read command: true/false */
379 uint8_t needRestoreNoCmdMode; /*!< Need to Restore NoCmd mode after IP commmand execution */
380 uint32_t blockSize; /*!< Block size */
381 uint32_t flashStateCtx; /*!< Flash State Context */
382 uint32_t reserve2[10]; /*!< Reserved for future use */
383} flexspi_nor_config_t;
384/*! @} */
385
386/*!
387 * @addtogroup iap_otp_driver
388 * @{
389 */
390
391/*! @brief OTP Status Group */
392enum
393{
394 kStatusGroup_OtpGroup = 0x210,
395};
396
397/*! @brief OTP Error Status definitions */
398enum
399{
400 kStatus_OTP_InvalidAddress = MAKE_STATUS(kStatusGroup_OtpGroup, 1), /*!< Invalid OTP address */
401 kStatus_OTP_ProgramFail = MAKE_STATUS(kStatusGroup_OtpGroup, 2), /*!< Program Fail */
402 kStatus_OTP_CrcFail = MAKE_STATUS(kStatusGroup_OtpGroup, 3), /*!< CrcCheck Fail */
403 kStatus_OTP_Error = MAKE_STATUS(kStatusGroup_OtpGroup, 4), /*!< Errors happened during OTP operation */
404 kStatus_OTP_EccCheckFail = MAKE_STATUS(kStatusGroup_OtpGroup, 5), /*!< Ecc Check failed during OTP operation */
405 kStatus_OTP_Locked = MAKE_STATUS(kStatusGroup_OtpGroup, 6), /*!< OTP Fuse field has been locked */
406 kStatus_OTP_Timeout = MAKE_STATUS(kStatusGroup_OtpGroup, 7), /*!< OTP operation time out */
407 kStatus_OTP_CrcCheckPass = MAKE_STATUS(kStatusGroup_OtpGroup, 8), /*!< OTP CRC Check Pass */
408};
409/*! @} */
410
411/*!
412 * @addtogroup iap_boot_driver
413 * @{
414 */
415
416/*! @brief IAP boot option. */
417typedef struct _iap_boot_option
418{
419 union
420 {
421 struct
422 {
423 uint32_t reserved : 8; /*! reserved field. */
424 uint32_t bootImageIndex : 4; /*! FlexSPI boot image index for FlexSPI NOR flash. */
425 uint32_t instance : 4; /*! Only used when boot interface is FlexSPI/SD/MMC. */
426 uint32_t bootInterface : 4; /*! RT500: 0: USART 2: SPI 3: USB HID 4:FlexSPI 6:SD 7:MMC.
427 RT600: 0: USART 1: I2C 2: SPI 3: USB HID 4:FlexSPI 7:SD 8:MMC*/
428 uint32_t mode : 4; /* boot mode, 0: Master boot mode; 1: ISP boot */
429 uint32_t tag : 8; /*! tag, should always be "0xEB". */
430 } B;
431 uint32_t U;
432 } option;
433} iap_boot_option_t;
434
435/*! IAP boot option tag */
436#define IAP_BOOT_OPTION_TAG (0xEBU)
437/*! IAP boot option mode */
438#define IAP_BOOT_OPTION_MODE_MASTER (0U)
439#define IAP_BOOT_OPTION_MODE_ISP (1U)
440
441/*! @} */
442
443/*******************************************************************************
444 * API
445 ******************************************************************************/
446#if defined(__cplusplus)
447extern "C" {
448#endif
449
450/*!
451 * @addtogroup iap_boot_driver
452 * @{
453 */
454
455/*!
456 * @brief Invoke into ROM with specified boot parameters.
457 *
458 * @param option Boot parameters. Refer to #iap_boot_option_t.
459 */
460void IAP_RunBootLoader(iap_boot_option_t *option);
461/*! @} */
462
463/*!
464 * @addtogroup iap_flexspi_driver
465 * @{
466 */
467
468/*!
469 * @brief Initialize Serial NOR devices via FlexSPI.
470 *
471 * This function configures the FlexSPI controller with the arguments pointed by param config.
472 *
473 * @param instance FlexSPI controller instance, only support 0.
474 * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
475 * @return The status flags. This is a member of the
476 * enumeration ::_flexspi_status
477 */
478status_t IAP_FlexspiNorInit(uint32_t instance, flexspi_nor_config_t *config);
479
480/*!
481 * @brief Program data to Serial NOR via FlexSPI.
482 *
483 * This function Program data to specified destination address.
484 *
485 * @param instance FlexSPI controller instance, only support 0.
486 * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
487 * @param dstAddr The destination address to be programmed.
488 * @param src Points to the buffer which hold the data to be programmed.
489 * @return The status flags. This is a member of the
490 * enumeration ::_flexspi_status
491 */
492status_t IAP_FlexspiNorPageProgram(uint32_t instance,
493 flexspi_nor_config_t *config,
494 uint32_t dstAddr,
495 const uint32_t *src);
496
497/*!
498 * @brief Erase all the Serial NOR devices connected on FlexSPI.
499 *
500 * @param instance FlexSPI controller instance, only support 0.
501 * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
502 * @return The status flags. This is a member of the
503 * enumeration ::_flexspi_status
504 */
505status_t IAP_FlexspiNorEraseAll(uint32_t instance, flexspi_nor_config_t *config);
506
507/*!
508 * @brief Erase Flash Region specified by address and length.
509 *
510 * @param instance FlexSPI controller instance, only support 0.
511 * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
512 * @param start The start address to be erased.
513 * @param length The length to be erased.
514 * @return The status flags. This is a member of the
515 * enumeration ::_flexspi_status
516 */
517status_t IAP_FlexspiNorErase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length);
518
519/*!
520 * @brief Erase one sector specified by address.
521 *
522 * @param instance FlexSPI controller instance, only support 0.
523 * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
524 * @param address The address of the sector to be erased.
525 * @return The status flags. This is a member of the
526 * enumeration ::_flexspi_status
527 */
528status_t IAP_FlexspiNorEraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
529
530/*!
531 * @brief Erase one block specified by address.
532 *
533 * @param instance FlexSPI controller instance, only support 0.
534 * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
535 * @param address The address of the block to be erased.
536 * @return The status flags. This is a member of the
537 * enumeration ::_flexspi_status
538 */
539status_t IAP_FlexspiNorEraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
540
541/*!
542 * @brief Get FlexSPI NOR Configuration Block based on specified option.
543 *
544 * @param instance FlexSPI controller instance, only support 0.
545 * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
546 * @param option The Flash Configuration Option block. Refer to #serial_nor_config_option_t.
547 * @return The status flags. This is a member of the
548 * enumeration ::_flexspi_status
549 */
550status_t IAP_FlexspiNorGetConfig(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option);
551
552/*!
553 * @brief Read data from Flexspi NOR Flash.
554 *
555 * @param instance FlexSPI controller instance, only support 0.
556 * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
557 * @param dst Buffer address used to store the read data.
558 * @param start The Read address.
559 * @param bytes The Read size
560 * @return The status flags. This is a member of the
561 * enumeration ::_flexspi_status
562 */
563status_t IAP_FlexspiNorRead(
564 uint32_t instance, flexspi_nor_config_t *config, uint32_t *dst, uint32_t start, uint32_t bytes);
565
566/*!
567 * @brief Get FlexSPI Xfer data.
568 *
569 * @param instance FlexSPI controller instance, only support 0.
570 * @param xfer The FlexSPI Transfer Context block. Refer to #flexspi_xfer_t.
571 * @return The status flags. This is a member of the
572 * enumeration ::_flexspi_status
573 */
574status_t IAP_FlexspiXfer(uint32_t instance, flexspi_xfer_t *xfer);
575
576/*!
577 * @brief Update FlexSPI Lookup table.
578 *
579 * @param instance FlexSPI controller instance, only support 0.
580 * @param seqIndex The index of FlexSPI LUT to be updated.
581 * @param lutBase Points to the buffer which hold the LUT data to be programmed.
582 * @param numberOfSeq The number of LUT seq that need to be updated.
583 * @return The status flags. This is a member of the
584 * enumeration ::_flexspi_status
585 */
586status_t IAP_FlexspiUpdateLut(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t numberOfSeq);
587
588/*!
589 * @brief Set the clock source for FlexSPI.
590 *
591 * @param clockSrc Clock source for flexspi interface.
592 * @return The status flags. This is a member of the
593 * enumeration ::_flexspi_status
594 */
595status_t IAP_FlexspiSetClockSource(uint32_t clockSrc);
596
597/*!
598 * @brief Configure the flexspi interface clock frequency and data sample mode.
599 *
600 * @param instance FlexSPI controller instance, only support 0.
601 * @param freqOption FlexSPI interface clock frequency selection.
602 * @param sampleClkMode FlexSPI controller data sample mode.
603 * @return The status flags. This is a member of the
604 * enumeration ::_flexspi_status
605 */
606void IAP_FlexspiConfigClock(uint32_t instance, uint32_t freqOption, uint32_t sampleClkMode);
607
608/*!
609 * @brief Configure flexspi nor automatically.
610 *
611 * @param instance FlexSPI controller instance, only support 0.
612 * @param config The Flash configuration block. Refer to #flexspi_nor_config_t.
613 * @param option The Flash Configuration Option block. Refer to #serial_nor_config_option_t.
614 * @return The status flags. This is a member of the
615 * enumeration ::_flexspi_status
616 */
617#if defined(DOXYGEN_OUTPUT) && DOXYGEN_OUTPUT
618status_t IAP_FlexspiNorAutoConfig(uint32_t instance, flexspi_nor_config_t *config, serial_nor_config_option_t *option);
619#else
620AT_QUICKACCESS_SECTION_CODE(status_t IAP_FlexspiNorAutoConfig(uint32_t instance,
621 flexspi_nor_config_t *config,
622 serial_nor_config_option_t *option));
623#endif
624/*! @} */
625
626/*!
627 * @addtogroup iap_otp_driver
628 * @{
629 */
630
631/*!
632 * @brief Initialize OTP controller
633 *
634 * This function enables OTP Controller clock.
635 *
636 * @param src_clk_freq The Frequency of the source clock of OTP controller
637 * @return kStatus_Success
638 */
639status_t IAP_OtpInit(uint32_t src_clk_freq);
640
641/*!
642 * @brief De-Initialize OTP controller
643 *
644 * This functin disables OTP Controller Clock.
645 * @return kStatus_Success
646 */
647status_t IAP_OtpDeinit(void);
648
649/*!
650 * @brief Read Fuse value from OTP Fuse Block
651 *
652 * This function read fuse data from OTP Fuse block to specified data buffer.
653 *
654 * @param addr Fuse address
655 * @param data Buffer to hold the data read from OTP Fuse block
656 * @return kStatus_Success - Data read from OTP Fuse block successfully
657 * kStatus_InvalidArgument - data pointer is invalid
658 * kStatus_OTP_EccCheckFail - Ecc Check Failed
659 * kStatus_OTP_Error - Other Errors
660 */
661status_t IAP_OtpFuseRead(uint32_t addr, uint32_t *data);
662
663/*!
664 * @brief Program value to OTP Fuse block
665 *
666 * This function program data to specified OTP Fuse address.
667 *
668 * @param addr Fuse address
669 * @param data data to be programmed into OTP Fuse block
670 * @param lock lock the fuse field or not
671 * @return kStatus_Success - Data has been programmed into OTP Fuse block successfully
672 * kStatus_OTP_ProgramFail - Fuse programming failed
673 * kStatus_OTP_Locked - The address to be programmed into is locked
674 * kStatus_OTP_Error - Other Errors
675 */
676status_t IAP_OtpFuseProgram(uint32_t addr, uint32_t data, bool lock);
677
678/*!
679 * @brief Reload all shadow registers from OTP fuse block
680 *
681 * This function reloads all the shadow registers from OTP Fuse block
682 *
683 * @return kStatus_Success - Shadow registers' reloadding succeeded.
684 * kStatus_OTP_EccCheckFail - Ecc Check Failed
685 * kStatus_OTP_Error - Other Errors
686 */
687status_t IAP_OtpShadowRegisterReload(void);
688
689/*!
690 * @brief Do CRC Check via OTP controller
691 *
692 * This function checks whether data in specified fuse address ranges match the crc value in the specified CRC address
693 * and return the actual crc value as needed.
694 *
695 * @param start_addr Start address of selected Fuse address range
696 * @param end_addr End address of selected Fuse address range
697 * @param crc_addr Address that hold CRC data
698 *
699 * @return kStatus_Success CRC check succeeded, CRC value matched.
700 * kStatus_InvalidArgument - Invalid Argument
701 * kStatus_OTP_EccCheckFail Ecc Check Failed
702 * kStatus_OTP_CrcFail CRC Check Failed
703 */
704status_t IAP_OtpCrcCheck(uint32_t start_addr, uint32_t end_addr, uint32_t crc_addr);
705
706/*!
707 * @brief Calculate the CRC checksum for specified data for OTP
708 *
709 * This function calculates the CRC checksum for specified data for OTP
710 *
711 * @param src the source address of data
712 * @param numberOfWords number of Fuse words
713 * @param crcChecksum Buffer to store the CRC checksum
714 *
715 * @return kStatus_Success CRC checksum is computed successfully.
716 * kStatus_InvalidArgument - Invalid Argument
717 */
718status_t IAP_OtpCrcCalc(uint32_t *src, uint32_t numberOfWords, uint32_t *crcChecksum);
719/*! @} */
720#if defined(__cplusplus)
721}
722#endif
723
724/*! @}*/
725
726#endif /* __FSL_IAP_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_inputmux_connections.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_inputmux_connections.h
new file mode 100644
index 000000000..8578ed239
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/drivers/fsl_inputmux_connections.h
@@ -0,0 +1,540 @@
1/*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2019, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_INPUTMUX_CONNECTIONS_
10#define _FSL_INPUTMUX_CONNECTIONS_
11
12/*******************************************************************************
13 * Definitions
14 ******************************************************************************/
15/* Component ID definition, used by tools. */
16#ifndef FSL_COMPONENT_ID
17#define FSL_COMPONENT_ID "platform.drivers.inputmux_connections"
18#endif
19
20/*!
21 * @addtogroup inputmux_driver
22 * @{
23 */
24
25/*! @brief Periphinmux IDs */
26#define SCT0_PMUX_ID 0x00U
27#define SHSGPIO_PMUX_ID 0x80U
28#define PINTSEL_PMUX_ID 0x100U
29#define DSP_INT_PMUX_ID 0x140U
30#define DMA0_ITRIG_PMUX_ID 0x200U
31#define DMA0_OTRIG_PMUX_ID 0x300U
32#define DMA1_ITRIG_PMUX_ID 0x400U
33#define DMA1_OTRIG_PMUX_ID 0x500U
34#define CT32BIT0_CAP_PMUX_ID 0x600U
35#define CT32BIT1_CAP_PMUX_ID 0x610U
36#define CT32BIT2_CAP_PMUX_ID 0x620U
37#define CT32BIT3_CAP_PMUX_ID 0x630U
38#define CT32BIT4_CAP_PMUX_ID 0x640U
39#define FREQMEAS_PMUX_ID 0x700U
40#define DMA0_REQ_ENA0_ID 0x740U
41#define DMA1_REQ_ENA0_ID 0x760U
42#define DMA0_ITRIG_EN0_ID 0x780U
43#define DMA1_ITRIG_EN0_ID 0x7A0U
44#define ENA_SHIFT 8U
45#define PMUX_SHIFT 20U
46
47/*! @brief INPUTMUX connections type */
48typedef enum _inputmux_connection_t
49{
50 /*!< SCT INMUX. */
51 kINPUTMUX_Sct0PinInp0ToSct0 = 0U + (SCT0_PMUX_ID << PMUX_SHIFT),
52 kINPUTMUX_Sct0PinInp1ToSct0 = 1U + (SCT0_PMUX_ID << PMUX_SHIFT),
53 kINPUTMUX_Sct0PinInp2ToSct0 = 2U + (SCT0_PMUX_ID << PMUX_SHIFT),
54 kINPUTMUX_Sct0PinInp3ToSct0 = 3U + (SCT0_PMUX_ID << PMUX_SHIFT),
55 kINPUTMUX_Sct0PinInp4ToSct0 = 4U + (SCT0_PMUX_ID << PMUX_SHIFT),
56 kINPUTMUX_Sct0PinInp5ToSct0 = 5U + (SCT0_PMUX_ID << PMUX_SHIFT),
57 kINPUTMUX_Sct0PinInp6ToSct0 = 6U + (SCT0_PMUX_ID << PMUX_SHIFT),
58 kINPUTMUX_Sct0PinInp7ToSct0 = 7U + (SCT0_PMUX_ID << PMUX_SHIFT),
59 kINPUTMUX_Ctimer0Mat0ToSct0 = 8U + (SCT0_PMUX_ID << PMUX_SHIFT),
60 kINPUTMUX_Ctimer1Mat0ToSct0 = 9U + (SCT0_PMUX_ID << PMUX_SHIFT),
61 kINPUTMUX_Ctimer2Mat0ToSct0 = 10U + (SCT0_PMUX_ID << PMUX_SHIFT),
62 kINPUTMUX_Ctimer3Mat0ToSct0 = 11U + (SCT0_PMUX_ID << PMUX_SHIFT),
63 kINPUTMUX_Ctimer4Mat0ToSct0 = 12U + (SCT0_PMUX_ID << PMUX_SHIFT),
64 kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_PMUX_ID << PMUX_SHIFT),
65 kINPUTMUX_GpioIntBmatchToSct0 = 14U + (SCT0_PMUX_ID << PMUX_SHIFT),
66 kINPUTMUX_Usb1FrameToggleToSct0 = 15U + (SCT0_PMUX_ID << PMUX_SHIFT),
67 kINPUTMUX_Cmp0OutToSct0 = 16U + (SCT0_PMUX_ID << PMUX_SHIFT),
68 kINPUTMUX_SharedI2s0SclkToSct0 = 17U + (SCT0_PMUX_ID << PMUX_SHIFT),
69 kINPUTMUX_SharedI2s1SclkToSct0 = 18U + (SCT0_PMUX_ID << PMUX_SHIFT),
70 kINPUTMUX_SharedI2s0WsToSct0 = 19U + (SCT0_PMUX_ID << PMUX_SHIFT),
71 kINPUTMUX_SharedI2s1WsToSct0 = 20U + (SCT0_PMUX_ID << PMUX_SHIFT),
72 kINPUTMUX_MclkToSct0 = 21U + (SCT0_PMUX_ID << PMUX_SHIFT),
73 kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_PMUX_ID << PMUX_SHIFT),
74 kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_PMUX_ID << PMUX_SHIFT),
75
76 /*!< Pin Interrupt. */
77 kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
78 kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
79 kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
80 kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
81 kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
82 kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
83 kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
84 kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
85 kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
86 kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
87 kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
88 kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
89 kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
90 kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
91 kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
92 kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
93 kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
94 kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
95 kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
96 kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
97 kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
98 kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
99 kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
100 kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
101 kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
102 kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
103 kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
104 kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
105 kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
106 kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
107 kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
108 kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
109 kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
110 kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
111 kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
112 kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
113 kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
114 kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
115 kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
116 kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
117 kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
118 kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
119 kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
120 kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
121 kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
122 kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
123 kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
124 kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
125 kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
126 kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
127 kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
128 kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
129 kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
130 kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
131 kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
132 kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
133 kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
134 kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
135 kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
136 kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
137 kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
138 kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
139 kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
140 kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
141
142 /*!< DSP Interrupt. */
143 kINPUTMUX_Flexcomm0ToDspInterrupt = 0U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
144 kINPUTMUX_Flexcomm1ToDspInterrupt = 1U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
145 kINPUTMUX_Flexcomm2ToDspInterrupt = 2U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
146 kINPUTMUX_Flexcomm3ToDspInterrupt = 3U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
147 kINPUTMUX_Flexcomm4ToDspInterrupt = 4U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
148 kINPUTMUX_Flexcomm5ToDspInterrupt = 5U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
149 kINPUTMUX_Flexcomm6ToDspInterrupt = 6U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
150 kINPUTMUX_Flexcomm7ToDspInterrupt = 7U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
151 kINPUTMUX_GpioInt0ToDspInterrupt = 8U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
152 kINPUTMUX_GpioInt1ToDspInterrupt = 9U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
153 kINPUTMUX_GpioInt2ToDspInterrupt = 10U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
154 kINPUTMUX_GpioInt3ToDspInterrupt = 11U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
155 kINPUTMUX_GpioInt4ToDspInterrupt = 12U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
156 kINPUTMUX_GpioInt5ToDspInterrupt = 13U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
157 kINPUTMUX_GpioInt6ToDspInterrupt = 14U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
158 kINPUTMUX_GpioInt7ToDspInterrupt = 15U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
159 kINPUTMUX_NsHsGpioInt0ToDspInterrupt = 16U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
160 kINPUTMUX_NsHsGpioInt1ToDspInterrupt = 17U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
161 kINPUTMUX_Wdt1ToDspInterrupt = 18U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
162 kINPUTMUX_Dmac0ToDspInterrupt = 19U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
163 kINPUTMUX_Dmac1ToDspInterrupt = 20U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
164 kINPUTMUX_MuBToDspInterrupt = 21U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
165 kINPUTMUX_Utick0ToDspInterrupt = 22U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
166 kINPUTMUX_Mrt0ToDspInterrupt = 23U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
167 kINPUTMUX_OsEventTimerToDspInterrupt = 24U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
168 kINPUTMUX_Ctimer0ToDspInterrupt = 25U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
169 kINPUTMUX_Ctimer1ToDspInterrupt = 26U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
170 kINPUTMUX_Ctimer2ToDspInterrupt = 27U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
171 kINPUTMUX_Ctimer3ToDspInterrupt = 28U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
172 kINPUTMUX_Ctimer4ToDspInterrupt = 29U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
173 kINPUTMUX_RtcToDspInterrupt = 30U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
174 kINPUTMUX_I3c0ToDspInterrupt = 31U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
175 kINPUTMUX_Dmic0ToDspInterrupt = 32U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
176 kINPUTMUX_Hwvad0ToDspInterrupt = 33U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
177 kINPUTMUX_FlexspiToDspInterrupt = 34U + (DSP_INT_PMUX_ID << PMUX_SHIFT),
178
179 /*!< Frequency measure. */
180 kINPUTMUX_XtalinToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
181 kINPUTMUX_SfroToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
182 kINPUTMUX_FfroToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
183 kINPUTMUX_LposcToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
184 kINPUTMUX_Rtc32KhzOscToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
185 kINPUTMUX_MainSysClkToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
186 kINPUTMUX_FreqmeGpioClkToFreqmeas = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
187
188 /*!< CTmier0 capture input mux. */
189 kINPUTMUX_CtInp0ToTimer0CaptureChannels = 0U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
190 kINPUTMUX_CtInp1ToTimer0CaptureChannels = 1U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
191 kINPUTMUX_CtInp2ToTimer0CaptureChannels = 2U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
192 kINPUTMUX_CtInp3ToTimer0CaptureChannels = 3U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
193 kINPUTMUX_CtInp4ToTimer0CaptureChannels = 4U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
194 kINPUTMUX_CtInp5ToTimer0CaptureChannels = 5U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
195 kINPUTMUX_CtInp6ToTimer0CaptureChannels = 6U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
196 kINPUTMUX_CtInp7ToTimer0CaptureChannels = 7U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
197 kINPUTMUX_CtInp8ToTimer0CaptureChannels = 8U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
198 kINPUTMUX_CtInp9ToTimer0CaptureChannels = 9U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
199 kINPUTMUX_CtInp10ToTimer0CaptureChannels = 10U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
200 kINPUTMUX_CtInp11ToTimer0CaptureChannels = 11U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
201 kINPUTMUX_CtInp12ToTimer0CaptureChannels = 12U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
202 kINPUTMUX_CtInp13ToTimer0CaptureChannels = 13U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
203 kINPUTMUX_CtInp14ToTimer0CaptureChannels = 14U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
204 kINPUTMUX_CtInp15ToTimer0CaptureChannels = 15U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
205 kINPUTMUX_SharedI2s0WsToTimer0CaptureChannels = 16U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
206 kINPUTMUX_SharedI2s1WsToTimer0CaptureChannels = 17U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
207 kINPUTMUX_Usb1FrameToggleToTimer0CaptureChannels = 18U + (CT32BIT0_CAP_PMUX_ID << PMUX_SHIFT),
208
209 /*!< CTmier1 capture input mux. */
210 kINPUTMUX_CtInp0ToTimer1CaptureChannels = 0U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
211 kINPUTMUX_CtInp1ToTimer1CaptureChannels = 1U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
212 kINPUTMUX_CtInp2ToTimer1CaptureChannels = 2U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
213 kINPUTMUX_CtInp3ToTimer1CaptureChannels = 3U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
214 kINPUTMUX_CtInp4ToTimer1CaptureChannels = 4U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
215 kINPUTMUX_CtInp5ToTimer1CaptureChannels = 5U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
216 kINPUTMUX_CtInp6ToTimer1CaptureChannels = 6U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
217 kINPUTMUX_CtInp7ToTimer1CaptureChannels = 7U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
218 kINPUTMUX_CtInp8ToTimer1CaptureChannels = 8U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
219 kINPUTMUX_CtInp9ToTimer1CaptureChannels = 9U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
220 kINPUTMUX_CtInp10ToTimer1CaptureChannels = 10U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
221 kINPUTMUX_CtInp11ToTimer1CaptureChannels = 11U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
222 kINPUTMUX_CtInp12ToTimer1CaptureChannels = 12U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
223 kINPUTMUX_CtInp13ToTimer1CaptureChannels = 13U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
224 kINPUTMUX_CtInp14ToTimer1CaptureChannels = 14U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
225 kINPUTMUX_CtInp15ToTimer1CaptureChannels = 15U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
226 kINPUTMUX_SharedI2s0WsToTimer1CaptureChannels = 16U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
227 kINPUTMUX_SharedI2s1WsToTimer1CaptureChannels = 17U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
228 kINPUTMUX_Usb1FrameToggleToTimer1CaptureChannels = 18U + (CT32BIT1_CAP_PMUX_ID << PMUX_SHIFT),
229
230 /*!< CTmier2 capture input mux. */
231 kINPUTMUX_CtInp0ToTimer2CaptureChannels = 0U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
232 kINPUTMUX_CtInp1ToTimer2CaptureChannels = 1U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
233 kINPUTMUX_CtInp2ToTimer2CaptureChannels = 2U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
234 kINPUTMUX_CtInp3ToTimer2CaptureChannels = 3U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
235 kINPUTMUX_CtInp4ToTimer2CaptureChannels = 4U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
236 kINPUTMUX_CtInp5ToTimer2CaptureChannels = 5U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
237 kINPUTMUX_CtInp6ToTimer2CaptureChannels = 6U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
238 kINPUTMUX_CtInp7ToTimer2CaptureChannels = 7U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
239 kINPUTMUX_CtInp8ToTimer2CaptureChannels = 8U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
240 kINPUTMUX_CtInp9ToTimer2CaptureChannels = 9U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
241 kINPUTMUX_CtInp10ToTimer2CaptureChannels = 10U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
242 kINPUTMUX_CtInp11ToTimer2CaptureChannels = 11U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
243 kINPUTMUX_CtInp12ToTimer2CaptureChannels = 12U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
244 kINPUTMUX_CtInp13ToTimer2CaptureChannels = 13U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
245 kINPUTMUX_CtInp14ToTimer2CaptureChannels = 14U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
246 kINPUTMUX_CtInp15ToTimer2CaptureChannels = 15U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
247 kINPUTMUX_SharedI2s0WsToTimer2CaptureChannels = 16U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
248 kINPUTMUX_SharedI2s1WsToTimer2CaptureChannels = 17U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
249 kINPUTMUX_Usb1FrameToggleToTimer2CaptureChannels = 18U + (CT32BIT2_CAP_PMUX_ID << PMUX_SHIFT),
250
251 /*!< CTmier3 capture input mux. */
252 kINPUTMUX_CtInp0ToTimer3CaptureChannels = 0U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
253 kINPUTMUX_CtInp1ToTimer3CaptureChannels = 1U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
254 kINPUTMUX_CtInp2ToTimer3CaptureChannels = 2U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
255 kINPUTMUX_CtInp3ToTimer3CaptureChannels = 3U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
256 kINPUTMUX_CtInp4ToTimer3CaptureChannels = 4U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
257 kINPUTMUX_CtInp5ToTimer3CaptureChannels = 5U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
258 kINPUTMUX_CtInp6ToTimer3CaptureChannels = 6U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
259 kINPUTMUX_CtInp7ToTimer3CaptureChannels = 7U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
260 kINPUTMUX_CtInp8ToTimer3CaptureChannels = 8U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
261 kINPUTMUX_CtInp9ToTimer3CaptureChannels = 9U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
262 kINPUTMUX_CtInp10ToTimer3CaptureChannels = 10U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
263 kINPUTMUX_CtInp11ToTimer3CaptureChannels = 11U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
264 kINPUTMUX_CtInp12ToTimer3CaptureChannels = 12U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
265 kINPUTMUX_CtInp13ToTimer3CaptureChannels = 13U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
266 kINPUTMUX_CtInp14ToTimer3CaptureChannels = 14U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
267 kINPUTMUX_CtInp15ToTimer3CaptureChannels = 15U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
268 kINPUTMUX_SharedI2s0WsToTimer3CaptureChannels = 16U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
269 kINPUTMUX_SharedI2s1WsToTimer3CaptureChannels = 17U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
270 kINPUTMUX_Usb1FrameToggleToTimer3CaptureChannels = 18U + (CT32BIT3_CAP_PMUX_ID << PMUX_SHIFT),
271
272 /*!< CTmier4 capture input mux. */
273 kINPUTMUX_CtInp0ToTimer4CaptureChannels = 0U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
274 kINPUTMUX_CtInp1ToTimer4CaptureChannels = 1U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
275 kINPUTMUX_CtInp2ToTimer4CaptureChannels = 2U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
276 kINPUTMUX_CtInp3ToTimer4CaptureChannels = 3U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
277 kINPUTMUX_CtInp4ToTimer4CaptureChannels = 4U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
278 kINPUTMUX_CtInp5ToTimer4CaptureChannels = 5U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
279 kINPUTMUX_CtInp6ToTimer4CaptureChannels = 6U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
280 kINPUTMUX_CtInp7ToTimer4CaptureChannels = 7U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
281 kINPUTMUX_CtInp8ToTimer4CaptureChannels = 8U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
282 kINPUTMUX_CtInp9ToTimer4CaptureChannels = 9U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
283 kINPUTMUX_CtInp10ToTimer4CaptureChannels = 10U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
284 kINPUTMUX_CtInp11ToTimer4CaptureChannels = 11U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
285 kINPUTMUX_CtInp12ToTimer4CaptureChannels = 12U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
286 kINPUTMUX_CtInp13ToTimer4CaptureChannels = 13U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
287 kINPUTMUX_CtInp14ToTimer4CaptureChannels = 14U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
288 kINPUTMUX_CtInp15ToTimer4CaptureChannels = 15U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
289 kINPUTMUX_SharedI2s0WsToTimer4CaptureChannels = 16U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
290 kINPUTMUX_SharedI2s1WsToTimer4CaptureChannels = 17U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
291 kINPUTMUX_Usb1FrameToggleToTimer4CaptureChannels = 18U + (CT32BIT4_CAP_PMUX_ID << PMUX_SHIFT),
292
293 /*!< DMA0 ITRIG. */
294 kINPUTMUX_NsGpioPint0Int0ToDma0 = 0U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
295 kINPUTMUX_NsGpioPint0Int1ToDma0 = 1U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
296 kINPUTMUX_NsGpioPint0Int2ToDma0 = 2U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
297 kINPUTMUX_NsGpioPint0Int3ToDma0 = 3U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
298 kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
299 kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
300 kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
301 kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
302 kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
303 kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
304 kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
305 kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
306 kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
307 kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
308 kINPUTMUX_Dma0TrigOutAToDma0 = 14U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
309 kINPUTMUX_Dma0TrigOutBToDma0 = 15U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
310 kINPUTMUX_Dma0TrigOutCToDma0 = 16U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
311 kINPUTMUX_Dma0TrigOutDToDma0 = 17U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
312 kINPUTMUX_Sct0Dmac0ToDma0 = 18U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
313 kINPUTMUX_Sct0Dmac1ToDma0 = 19U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
314 kINPUTMUX_HashCryptOutToDma0 = 20U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
315 kINPUTMUX_AcmpToDma0 = 21U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
316 kINPUTMUX_AdcToDma0 = 24U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
317 kINPUTMUX_FlexspiRxToDma0 = 28U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
318 kINPUTMUX_FlexspiTxToDma0 = 29U + (DMA0_ITRIG_PMUX_ID << PMUX_SHIFT),
319
320