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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/project_template/board.c
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@@ -0,0 +1,564 @@
1/*
2 * Copyright 2018 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#include <stdint.h>
10#include "fsl_common.h"
11#include "fsl_debug_console.h"
12#include "board.h"
13#include "fsl_clock.h"
14#include "fsl_flexspi.h"
15#include "fsl_cache.h"
16#include "fsl_power.h"
17#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
18#include "fsl_i2c.h"
19#endif /* SDK_I2C_BASED_COMPONENT_USED */
20#if defined BOARD_USE_CODEC
21#include "fsl_i3c.h"
22#endif
23
24/*******************************************************************************
25 * Definitions
26 ******************************************************************************/
27#define BOARD_FLEXSPI_DLL_LOCK_RETRY (10)
28#define BOARD_IS_XIP_FLEXSPI() \
29 ((((uint32_t)BOARD_InitDebugConsole >= 0x08000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x10000000U)) || \
30 (((uint32_t)BOARD_InitDebugConsole >= 0x18000000U) && ((uint32_t)BOARD_InitDebugConsole < 0x20000000U)))
31/*******************************************************************************
32 * Variables
33 ******************************************************************************/
34static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
35static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal);
36static status_t flexspi_hyper_ram_reset(FLEXSPI_Type *base);
37/*******************************************************************************
38 * Code
39 ******************************************************************************/
40/* Initialize debug console. */
41void BOARD_InitDebugConsole(void)
42{
43 uint32_t uartClkSrcFreq;
44
45 /* attach FRG0 clock to FLEXCOMM0 (debug console) */
46 CLOCK_SetFRGClock(BOARD_DEBUG_UART_FRG_CLK);
47 CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
48
49 uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
50
51 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
52}
53
54static status_t flexspi_hyper_ram_write_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal)
55{
56 flexspi_transfer_t flashXfer;
57 status_t status;
58
59 /* Write data */
60 flashXfer.deviceAddress = regAddr;
61 flashXfer.port = kFLEXSPI_PortA1;
62 flashXfer.cmdType = kFLEXSPI_Write;
63 flashXfer.SeqNumber = 1;
64 flashXfer.seqIndex = 3;
65 flashXfer.data = mrVal;
66 flashXfer.dataSize = 1;
67
68 status = FLEXSPI_TransferBlocking(base, &flashXfer);
69
70 return status;
71}
72
73static status_t flexspi_hyper_ram_get_mcr(FLEXSPI_Type *base, uint8_t regAddr, uint32_t *mrVal)
74{
75 flexspi_transfer_t flashXfer;
76 status_t status;
77
78 /* Read data */
79 flashXfer.deviceAddress = regAddr;
80 flashXfer.port = kFLEXSPI_PortA1;
81 flashXfer.cmdType = kFLEXSPI_Read;
82 flashXfer.SeqNumber = 1;
83 flashXfer.seqIndex = 2;
84 flashXfer.data = mrVal;
85 flashXfer.dataSize = 2;
86
87 status = FLEXSPI_TransferBlocking(base, &flashXfer);
88
89 return status;
90}
91
92static status_t flexspi_hyper_ram_reset(FLEXSPI_Type *base)
93{
94 flexspi_transfer_t flashXfer;
95 status_t status;
96
97 /* Write data */
98 flashXfer.deviceAddress = 0x0U;
99 flashXfer.port = kFLEXSPI_PortA1;
100 flashXfer.cmdType = kFLEXSPI_Command;
101 flashXfer.SeqNumber = 1;
102 flashXfer.seqIndex = 4;
103
104 status = FLEXSPI_TransferBlocking(base, &flashXfer);
105
106 if (status == kStatus_Success)
107 {
108 /* for loop of 50000 is about 1ms (@200 MHz CPU) */
109 for (uint32_t i = 2000000U; i > 0; i--)
110 {
111 __NOP();
112 }
113 }
114 return status;
115}
116
117/* Initialize psram. */
118status_t BOARD_InitPsRam(void)
119{
120 flexspi_device_config_t deviceconfig = {
121 .flexspiRootClk = 396000000, /* 396MHZ SPI serial clock, DDR serial clock 198M */
122 .isSck2Enabled = false,
123 .flashSize = 0x8000, /*64Mb/KByte*/
124 .CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
125 .CSInterval = 5,
126 .CSHoldTime = 3,
127 .CSSetupTime = 3,
128 .dataValidTime = 1,
129 .columnspace = 0,
130 .enableWordAddress = false,
131 .AWRSeqIndex = 1,
132 .AWRSeqNumber = 1,
133 .ARDSeqIndex = 0,
134 .ARDSeqNumber = 1,
135 .AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
136 .AHBWriteWaitInterval = 0,
137 .enableWriteMask = true,
138 };
139
140 uint32_t customLUT[64] = {
141 /* Read Data */
142 [0] =
143 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x20, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
144 [1] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_READ_DDR,
145 kFLEXSPI_8PAD, 0x04),
146
147 /* Write Data */
148 [4] =
149 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xA0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
150 [5] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_WRITE_DDR,
151 kFLEXSPI_8PAD, 0x04),
152
153 /* Read Register */
154 [8] =
155 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0x40, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
156 [9] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_RWDS_DDR, kFLEXSPI_8PAD, 0x07, kFLEXSPI_Command_READ_DDR,
157 kFLEXSPI_8PAD, 0x04),
158
159 /* Write Register */
160 [12] =
161 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xC0, kFLEXSPI_Command_RADDR_DDR, kFLEXSPI_8PAD, 0x20),
162 [13] = FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_DDR, kFLEXSPI_8PAD, 0x08, kFLEXSPI_Command_STOP, kFLEXSPI_1PAD,
163 0x00),
164
165 /* reset */
166 [16] =
167 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_8PAD, 0xFF, kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_8PAD, 0x03),
168
169 };
170
171 uint32_t mr0mr1[1];
172 uint32_t mr4mr8[1];
173 uint32_t mr0Val[1];
174 uint32_t mr4Val[1];
175 uint32_t mr8Val[1];
176 flexspi_config_t config;
177 cache64_config_t cacheCfg;
178 status_t status = kStatus_Success;
179
180 POWER_DisablePD(kPDRUNCFG_APD_FLEXSPI_SRAM);
181 POWER_DisablePD(kPDRUNCFG_PPD_FLEXSPI_SRAM);
182 POWER_ApplyPD();
183
184 CLOCK_AttachClk(kAUX0_PLL_to_FLEXSPI_CLK);
185 CLOCK_SetClkDiv(kCLOCK_DivFlexspiClk, 1);
186
187 RESET_PeripheralReset(kFLEXSPI_RST_SHIFT_RSTn);
188 /* Explicitly enable FlexSPI clock for PSRAM loader case which need to set FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL. */
189 CLOCK_EnableClock(kCLOCK_Flexspi);
190
191 /* As cache depends on FlexSPI power and clock, cache must be initialized after FlexSPI power/clock is set */
192 CACHE64_GetDefaultConfig(&cacheCfg);
193 CACHE64_Init(CACHE64_POLSEL, &cacheCfg);
194#if BOARD_ENABLE_PSRAM_CACHE
195 CACHE64_EnableCache(CACHE64);
196#endif
197
198 /* Get FLEXSPI default settings and configure the flexspi. */
199 FLEXSPI_GetDefaultConfig(&config);
200
201 /* Init FLEXSPI. */
202 config.rxSampleClock = kFLEXSPI_ReadSampleClkExternalInputFromDqsPad;
203 /*Set AHB buffer size for reading data through AHB bus. */
204 config.ahbConfig.enableAHBPrefetch = true;
205 config.ahbConfig.enableAHBBufferable = true;
206 config.ahbConfig.enableAHBCachable = true;
207 config.ahbConfig.enableReadAddressOpt = true;
208 for (uint8_t i = 1; i < FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1; i++)
209 {
210 config.ahbConfig.buffer[i].bufferSize = 0;
211 }
212 /* FlexSPI has total 1KB RX buffer.
213 * Set DMA0 master to use AHB Rx Buffer0.
214 */
215 config.ahbConfig.buffer[0].masterIndex = 4; /* DMA0 */
216 config.ahbConfig.buffer[0].bufferSize = 512; /* Allocate 512B bytes for DMA0 */
217 config.ahbConfig.buffer[0].enablePrefetch = true;
218 config.ahbConfig.buffer[0].priority = 0;
219 /* All other masters use last buffer with 512B bytes. */
220 config.ahbConfig.buffer[FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNT - 1].bufferSize = 512;
221 config.enableCombination = true;
222 FLEXSPI_Init(BOARD_FLEXSPI_PSRAM, &config);
223
224 /* Configure flash settings according to serial flash feature. */
225 FLEXSPI_SetFlashConfig(BOARD_FLEXSPI_PSRAM, &deviceconfig, kFLEXSPI_PortA1);
226
227 /* Update LUT table. */
228 FLEXSPI_UpdateLUT(BOARD_FLEXSPI_PSRAM, 0, customLUT, ARRAY_SIZE(customLUT));
229
230 /* Do software reset. */
231 FLEXSPI_SoftwareReset(BOARD_FLEXSPI_PSRAM);
232
233 /* Reset hyper ram. */
234 status = flexspi_hyper_ram_reset(BOARD_FLEXSPI_PSRAM);
235 if (status != kStatus_Success)
236 {
237 return status;
238 }
239
240 status = flexspi_hyper_ram_get_mcr(BOARD_FLEXSPI_PSRAM, 0x0, mr0mr1);
241 if (status != kStatus_Success)
242 {
243 return status;
244 }
245
246 status = flexspi_hyper_ram_get_mcr(BOARD_FLEXSPI_PSRAM, 0x4, mr4mr8);
247 if (status != kStatus_Success)
248 {
249 return status;
250 }
251
252 /* Enable RBX, burst length set to 1K. - MR8 */
253 mr8Val[0] = (mr4mr8[0] & 0xFF00U) >> 8U;
254 mr8Val[0] = mr8Val[0] | 0x0F;
255 status = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x8, mr8Val);
256 if (status != kStatus_Success)
257 {
258 return status;
259 }
260
261 /* Set LC code to 0x04(LC=7, maximum frequency 200M) - MR0. */
262 mr0Val[0] = mr0mr1[0] & 0x00FFU;
263 mr0Val[0] = (mr0Val[0] & ~0x3C) | (4 << 2U);
264 status = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x0, mr0Val);
265 if (status != kStatus_Success)
266 {
267 return status;
268 }
269
270 /* Set WLC code to 0x01(WLC=7, maximum frequency 200M) - MR4. */
271 mr4Val[0] = mr4mr8[0] & 0x00FFU;
272 mr4Val[0] = (mr4Val[0] & ~0xE0) | (1 << 5U);
273 status = flexspi_hyper_ram_write_mcr(BOARD_FLEXSPI_PSRAM, 0x4, mr4Val);
274 if (status != kStatus_Success)
275 {
276 return status;
277 }
278
279 return status;
280}
281
282void BOARD_DeinitXip(FLEXSPI_Type *base)
283{
284 /* Wait until FLEXSPI is not busy */
285 while (!((base->STS0 & FLEXSPI_STS0_ARBIDLE_MASK) && (base->STS0 & FLEXSPI_STS0_SEQIDLE_MASK)))
286 {
287 }
288 /* Disable module during the reset procedure */
289 base->MCR0 |= FLEXSPI_MCR0_MDIS_MASK;
290}
291
292void BOARD_InitXip(FLEXSPI_Type *base)
293{
294 uint32_t status;
295 uint32_t lastStatus;
296 uint32_t retry;
297 uint32_t mask = 0;
298
299 /* Enable FLEXSPI module */
300 base->MCR0 &= ~FLEXSPI_MCR0_MDIS_MASK;
301
302 base->MCR0 |= FLEXSPI_MCR0_SWRESET_MASK;
303 while (base->MCR0 & FLEXSPI_MCR0_SWRESET_MASK)
304 {
305 }
306
307 /* Need to wait DLL locked if DLL enabled */
308 if (0U != (base->DLLCR[0] & FLEXSPI_DLLCR_DLLEN_MASK))
309 {
310 lastStatus = base->STS2;
311 retry = BOARD_FLEXSPI_DLL_LOCK_RETRY;
312 /* Flash on port A */
313 if ((base->FLSHCR0[0] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0 ||
314 (base->FLSHCR0[1] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0)
315 {
316 mask |= FLEXSPI_STS2_AREFLOCK_MASK | FLEXSPI_STS2_ASLVLOCK_MASK;
317 }
318 /* Flash on port B */
319 if ((base->FLSHCR0[2] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0 ||
320 (base->FLSHCR0[3] & FLEXSPI_FLSHCR0_FLSHSZ_MASK) > 0)
321 {
322 mask |= FLEXSPI_STS2_BREFLOCK_MASK | FLEXSPI_STS2_BSLVLOCK_MASK;
323 }
324 /* Wait slave delay line locked and slave reference delay line locked. */
325 do
326 {
327 status = base->STS2;
328 if ((status & mask) == mask)
329 {
330 /* Locked */
331 retry = 100;
332 break;
333 }
334 else if (status == lastStatus)
335 {
336 /* Same delay cell number in calibration */
337 retry--;
338 }
339 else
340 {
341 retry = BOARD_FLEXSPI_DLL_LOCK_RETRY;
342 lastStatus = status;
343 }
344 } while (retry > 0);
345 /* According to ERR011377, need to delay at least 100 NOPs to ensure the DLL is locked. */
346 for (; retry > 0U; retry--)
347 {
348 __NOP();
349 }
350 }
351}
352
353/* BOARD_SetFlexspiClock run in RAM used to configure FlexSPI clock source and divider when XIP. */
354void BOARD_SetFlexspiClock(uint32_t src, uint32_t divider)
355{
356 if (CLKCTL0->FLEXSPIFCLKSEL != CLKCTL0_FLEXSPIFCLKSEL_SEL(src) ||
357 (CLKCTL0->FLEXSPIFCLKDIV & CLKCTL0_FLEXSPIFCLKDIV_DIV_MASK) != (divider - 1))
358 {
359 if (BOARD_IS_XIP_FLEXSPI())
360 {
361 BOARD_DeinitXip(FLEXSPI);
362 }
363 /* Disable clock before changing clock source */
364 CLKCTL0->PSCCTL0_CLR = CLKCTL0_PSCCTL0_CLR_FLEXSPI_OTFAD_CLK_MASK;
365 /* Update flexspi clock. */
366 CLKCTL0->FLEXSPIFCLKSEL = CLKCTL0_FLEXSPIFCLKSEL_SEL(src);
367 CLKCTL0->FLEXSPIFCLKDIV |= CLKCTL0_FLEXSPIFCLKDIV_RESET_MASK; /* Reset the divider counter */
368 CLKCTL0->FLEXSPIFCLKDIV = CLKCTL0_FLEXSPIFCLKDIV_DIV(divider - 1);
369 while ((CLKCTL0->FLEXSPIFCLKDIV) & CLKCTL0_FLEXSPIFCLKDIV_REQFLAG_MASK)
370 {
371 }
372 /* Enable FLEXSPI clock again */
373 CLKCTL0->PSCCTL0_SET = CLKCTL0_PSCCTL0_SET_FLEXSPI_OTFAD_CLK_MASK;
374 if (BOARD_IS_XIP_FLEXSPI())
375 {
376 BOARD_InitXip(FLEXSPI);
377 }
378 }
379}
380
381/* This function is used to change FlexSPI clock to a stable source before clock sources(Such as PLL and Main clock)
382 * updating in case XIP(execute code on FLEXSPI memory.) */
383void BOARD_FlexspiClockSafeConfig(void)
384{
385 /* Move FLEXSPI clock source from main clock to FFRO to avoid instruction/data fetch issue in XIP when
386 * updating PLL and main clock.
387 */
388 BOARD_SetFlexspiClock(3U, 1);
389}
390
391#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
392void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
393{
394 i2c_master_config_t i2cConfig = {0};
395
396 I2C_MasterGetDefaultConfig(&i2cConfig);
397 I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
398}
399
400status_t BOARD_I2C_Send(I2C_Type *base,
401 uint8_t deviceAddress,
402 uint32_t subAddress,
403 uint8_t subaddressSize,
404 uint8_t *txBuff,
405 uint8_t txBuffSize)
406{
407 i2c_master_transfer_t masterXfer;
408
409 /* Prepare transfer structure. */
410 masterXfer.slaveAddress = deviceAddress;
411 masterXfer.direction = kI2C_Write;
412 masterXfer.subaddress = subAddress;
413 masterXfer.subaddressSize = subaddressSize;
414 masterXfer.data = txBuff;
415 masterXfer.dataSize = txBuffSize;
416 masterXfer.flags = kI2C_TransferDefaultFlag;
417
418 return I2C_MasterTransferBlocking(base, &masterXfer);
419}
420
421status_t BOARD_I2C_Receive(I2C_Type *base,
422 uint8_t deviceAddress,
423 uint32_t subAddress,
424 uint8_t subaddressSize,
425 uint8_t *rxBuff,
426 uint8_t rxBuffSize)
427{
428 i2c_master_transfer_t masterXfer;
429
430 /* Prepare transfer structure. */
431 masterXfer.slaveAddress = deviceAddress;
432 masterXfer.subaddress = subAddress;
433 masterXfer.subaddressSize = subaddressSize;
434 masterXfer.data = rxBuff;
435 masterXfer.dataSize = rxBuffSize;
436 masterXfer.direction = kI2C_Read;
437 masterXfer.flags = kI2C_TransferDefaultFlag;
438
439 return I2C_MasterTransferBlocking(base, &masterXfer);
440}
441#endif
442
443#if defined BOARD_USE_CODEC
444void BOARD_I3C_Init(I3C_Type *base, uint32_t clkSrc_Hz)
445{
446 i3c_master_config_t i3cConfig;
447
448 I3C_MasterGetDefaultConfig(&i3cConfig);
449 I3C_MasterInit(base, &i3cConfig, clkSrc_Hz);
450}
451
452status_t BOARD_I3C_Send(I3C_Type *base,
453 uint8_t deviceAddress,
454 uint32_t subAddress,
455 uint8_t subaddressSize,
456 uint8_t *txBuff,
457 uint8_t txBuffSize)
458{
459 i3c_master_transfer_t masterXfer;
460
461 /* Prepare transfer structure. */
462 masterXfer.slaveAddress = deviceAddress;
463 masterXfer.direction = kI3C_Write;
464 masterXfer.busType = kI3C_TypeI2C;
465 masterXfer.subaddress = subAddress;
466 masterXfer.subaddressSize = subaddressSize;
467 masterXfer.data = txBuff;
468 masterXfer.dataSize = txBuffSize;
469 masterXfer.flags = kI3C_TransferDefaultFlag;
470
471 return I3C_MasterTransferBlocking(base, &masterXfer);
472}
473
474status_t BOARD_I3C_Receive(I3C_Type *base,
475 uint8_t deviceAddress,
476 uint32_t subAddress,
477 uint8_t subaddressSize,
478 uint8_t *rxBuff,
479 uint8_t rxBuffSize)
480{
481 i3c_master_transfer_t masterXfer;
482
483 /* Prepare transfer structure. */
484 masterXfer.slaveAddress = deviceAddress;
485 masterXfer.subaddress = subAddress;
486 masterXfer.subaddressSize = subaddressSize;
487 masterXfer.data = rxBuff;
488 masterXfer.dataSize = rxBuffSize;
489 masterXfer.direction = kI3C_Read;
490 masterXfer.busType = kI3C_TypeI2C;
491 masterXfer.flags = kI3C_TransferDefaultFlag;
492
493 return I3C_MasterTransferBlocking(base, &masterXfer);
494}
495
496void BOARD_Codec_I2C_Init(void)
497{
498#if BOARD_I3C_CODEC
499 BOARD_I3C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
500#else
501 BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
502#endif
503}
504
505status_t BOARD_Codec_I2C_Send(
506 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
507{
508#if BOARD_I3C_CODEC
509 return BOARD_I3C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
510#else
511 return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
512#endif
513 txBuffSize);
514}
515
516status_t BOARD_Codec_I2C_Receive(
517 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
518{
519#if BOARD_I3C_CODEC
520 return BOARD_I3C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
521#else
522 return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
523#endif
524}
525#endif
526
527#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
528void BOARD_PMIC_I2C_Init(void)
529{
530 BOARD_I2C_Init(BOARD_PMIC_I2C_BASEADDR, BOARD_PMIC_I2C_CLOCK_FREQ);
531}
532
533status_t BOARD_PMIC_I2C_Send(
534 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
535{
536 return BOARD_I2C_Send(BOARD_PMIC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
537 txBuffSize);
538}
539
540status_t BOARD_PMIC_I2C_Receive(
541 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
542{
543 return BOARD_I2C_Receive(BOARD_PMIC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
544}
545
546void BOARD_Accel_I2C_Init(void)
547{
548 BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
549}
550
551status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
552{
553 uint8_t data = (uint8_t)txBuff;
554
555 return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
556}
557
558status_t BOARD_Accel_I2C_Receive(
559 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
560{
561 return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
562}
563
564#endif /* SDK_I2C_BASED_COMPONENT_USED */
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