diff options
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa/sim/ldscripts/elf32xtensa.x')
-rwxr-xr-x | lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa/sim/ldscripts/elf32xtensa.x | 585 |
1 files changed, 585 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa/sim/ldscripts/elf32xtensa.x b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa/sim/ldscripts/elf32xtensa.x new file mode 100755 index 000000000..54cd29732 --- /dev/null +++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa/sim/ldscripts/elf32xtensa.x | |||
@@ -0,0 +1,585 @@ | |||
1 | /* This linker script generated from xt-genldscripts.tpp for LSP C:/usr/xtensa/Xplorer-8.0.10-workspaces/XtensaInfo/Models/nxp_rt600_sram_memmap/sim */ | ||
2 | /* Linker Script for default link */ | ||
3 | MEMORY | ||
4 | { | ||
5 | dsp_core_seg : org = 0x00200000, len = 0x280000 | ||
6 | dsp_uncached_seg : org = 0x20060000, len = 0x10000 | ||
7 | dram0_0_seg : org = 0x24000000, len = 0x10000 | ||
8 | iram0_0_seg : org = 0x24020000, len = 0x400 | ||
9 | iram0_1_seg : org = 0x24020400, len = 0x17C | ||
10 | iram0_2_seg : org = 0x2402057C, len = 0x20 | ||
11 | iram0_3_seg : org = 0x2402059C, len = 0x20 | ||
12 | iram0_4_seg : org = 0x240205BC, len = 0x20 | ||
13 | iram0_5_seg : org = 0x240205DC, len = 0x20 | ||
14 | iram0_6_seg : org = 0x240205FC, len = 0x20 | ||
15 | iram0_7_seg : org = 0x2402061C, len = 0x20 | ||
16 | iram0_8_seg : org = 0x2402063C, len = 0xF9C4 | ||
17 | } | ||
18 | |||
19 | PHDRS | ||
20 | { | ||
21 | dsp_core_phdr PT_LOAD; | ||
22 | dsp_core_bss_phdr PT_LOAD; | ||
23 | dsp_uncached_phdr PT_LOAD; | ||
24 | dram0_0_phdr PT_LOAD; | ||
25 | dram0_0_bss_phdr PT_LOAD; | ||
26 | iram0_0_phdr PT_LOAD; | ||
27 | iram0_1_phdr PT_LOAD; | ||
28 | iram0_2_phdr PT_LOAD; | ||
29 | iram0_3_phdr PT_LOAD; | ||
30 | iram0_4_phdr PT_LOAD; | ||
31 | iram0_5_phdr PT_LOAD; | ||
32 | iram0_6_phdr PT_LOAD; | ||
33 | iram0_7_phdr PT_LOAD; | ||
34 | iram0_8_phdr PT_LOAD; | ||
35 | } | ||
36 | |||
37 | |||
38 | /* Default entry point: */ | ||
39 | ENTRY(_ResetVector) | ||
40 | |||
41 | |||
42 | /* Memory boundary addresses: */ | ||
43 | _memmap_mem_sram_start = 0x0; | ||
44 | _memmap_mem_sram_end = 0x480000; | ||
45 | _memmap_mem_dram0_start = 0x24000000; | ||
46 | _memmap_mem_dram0_end = 0x24010000; | ||
47 | _memmap_mem_iram0_start = 0x24020000; | ||
48 | _memmap_mem_iram0_end = 0x24030000; | ||
49 | _memmap_mem_sram_uncached_start = 0x20000000; | ||
50 | _memmap_mem_sram_uncached_end = 0x20480000; | ||
51 | |||
52 | /* Memory segment boundary addresses: */ | ||
53 | _memmap_seg_dsp_core_start = 0x200000; | ||
54 | _memmap_seg_dsp_core_max = 0x480000; | ||
55 | _memmap_seg_dsp_uncached_start = 0x20060000; | ||
56 | _memmap_seg_dsp_uncached_max = 0x20070000; | ||
57 | _memmap_seg_dram0_0_start = 0x24000000; | ||
58 | _memmap_seg_dram0_0_max = 0x24010000; | ||
59 | _memmap_seg_iram0_0_start = 0x24020000; | ||
60 | _memmap_seg_iram0_0_max = 0x24020400; | ||
61 | _memmap_seg_iram0_1_start = 0x24020400; | ||
62 | _memmap_seg_iram0_1_max = 0x2402057c; | ||
63 | _memmap_seg_iram0_2_start = 0x2402057c; | ||
64 | _memmap_seg_iram0_2_max = 0x2402059c; | ||
65 | _memmap_seg_iram0_3_start = 0x2402059c; | ||
66 | _memmap_seg_iram0_3_max = 0x240205bc; | ||
67 | _memmap_seg_iram0_4_start = 0x240205bc; | ||
68 | _memmap_seg_iram0_4_max = 0x240205dc; | ||
69 | _memmap_seg_iram0_5_start = 0x240205dc; | ||
70 | _memmap_seg_iram0_5_max = 0x240205fc; | ||
71 | _memmap_seg_iram0_6_start = 0x240205fc; | ||
72 | _memmap_seg_iram0_6_max = 0x2402061c; | ||
73 | _memmap_seg_iram0_7_start = 0x2402061c; | ||
74 | _memmap_seg_iram0_7_max = 0x2402063c; | ||
75 | _memmap_seg_iram0_8_start = 0x2402063c; | ||
76 | _memmap_seg_iram0_8_max = 0x24030000; | ||
77 | |||
78 | _rom_store_table = 0; | ||
79 | PROVIDE(_memmap_reset_vector = 0x24020000); | ||
80 | PROVIDE(_memmap_vecbase_reset = 0x24020400); | ||
81 | /* Various memory-map dependent cache attribute settings: */ | ||
82 | _memmap_cacheattr_wb_base = 0x00000044; | ||
83 | _memmap_cacheattr_wt_base = 0x00000011; | ||
84 | _memmap_cacheattr_bp_base = 0x00000022; | ||
85 | _memmap_cacheattr_unused_mask = 0xFFFFFF00; | ||
86 | _memmap_cacheattr_wb_trapnull = 0x22222244; | ||
87 | _memmap_cacheattr_wba_trapnull = 0x22222244; | ||
88 | _memmap_cacheattr_wbna_trapnull = 0x22222255; | ||
89 | _memmap_cacheattr_wt_trapnull = 0x22222211; | ||
90 | _memmap_cacheattr_bp_trapnull = 0x22222222; | ||
91 | _memmap_cacheattr_wb_strict = 0xFFFFFF44; | ||
92 | _memmap_cacheattr_wt_strict = 0xFFFFFF11; | ||
93 | _memmap_cacheattr_bp_strict = 0xFFFFFF22; | ||
94 | _memmap_cacheattr_wb_allvalid = 0x22222244; | ||
95 | _memmap_cacheattr_wt_allvalid = 0x22222211; | ||
96 | _memmap_cacheattr_bp_allvalid = 0x22222222; | ||
97 | _memmap_region_map = 0x00000003; | ||
98 | PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull); | ||
99 | |||
100 | SECTIONS | ||
101 | { | ||
102 | |||
103 | NonCacheable.init : ALIGN(4) | ||
104 | { | ||
105 | NonCacheable_init_start = ABSOLUTE(.); | ||
106 | *(NonCacheable.init) | ||
107 | . = ALIGN (4); | ||
108 | NonCacheable_init_end = ABSOLUTE(.); | ||
109 | } >dsp_uncached_seg :dsp_uncached_phdr | ||
110 | |||
111 | NonCacheable : ALIGN(4) | ||
112 | { | ||
113 | NonCacheable_start = ABSOLUTE(.); | ||
114 | *(NonCacheable) | ||
115 | . = ALIGN (4); | ||
116 | NonCacheable_end = ABSOLUTE(.); | ||
117 | _memmap_seg_dsp_uncached_end = ALIGN(0x8); | ||
118 | } >dsp_uncached_seg :dsp_uncached_phdr | ||
119 | |||
120 | |||
121 | .dram0.rodata : ALIGN(4) | ||
122 | { | ||
123 | _dram0_rodata_start = ABSOLUTE(.); | ||
124 | *(.dram0.rodata) | ||
125 | *(.dram.rodata) | ||
126 | . = ALIGN (4); | ||
127 | _dram0_rodata_end = ABSOLUTE(.); | ||
128 | } >dram0_0_seg :dram0_0_phdr | ||
129 | |||
130 | .ResetVector.literal : ALIGN(4) | ||
131 | { | ||
132 | _ResetVector_literal_start = ABSOLUTE(.); | ||
133 | *(.ResetVector.literal) | ||
134 | . = ALIGN (4); | ||
135 | _ResetVector_literal_end = ABSOLUTE(.); | ||
136 | } >dram0_0_seg :dram0_0_phdr | ||
137 | |||
138 | .Level2InterruptVector.literal : ALIGN(4) | ||
139 | { | ||
140 | _Level2InterruptVector_literal_start = ABSOLUTE(.); | ||
141 | *(.Level2InterruptVector.literal) | ||
142 | . = ALIGN (4); | ||
143 | _Level2InterruptVector_literal_end = ABSOLUTE(.); | ||
144 | } >dram0_0_seg :dram0_0_phdr | ||
145 | |||
146 | .Level3InterruptVector.literal : ALIGN(4) | ||
147 | { | ||
148 | _Level3InterruptVector_literal_start = ABSOLUTE(.); | ||
149 | *(.Level3InterruptVector.literal) | ||
150 | . = ALIGN (4); | ||
151 | _Level3InterruptVector_literal_end = ABSOLUTE(.); | ||
152 | } >dram0_0_seg :dram0_0_phdr | ||
153 | |||
154 | .DebugExceptionVector.literal : ALIGN(4) | ||
155 | { | ||
156 | _DebugExceptionVector_literal_start = ABSOLUTE(.); | ||
157 | *(.DebugExceptionVector.literal) | ||
158 | . = ALIGN (4); | ||
159 | _DebugExceptionVector_literal_end = ABSOLUTE(.); | ||
160 | } >dram0_0_seg :dram0_0_phdr | ||
161 | |||
162 | .NMIExceptionVector.literal : ALIGN(4) | ||
163 | { | ||
164 | _NMIExceptionVector_literal_start = ABSOLUTE(.); | ||
165 | *(.NMIExceptionVector.literal) | ||
166 | . = ALIGN (4); | ||
167 | _NMIExceptionVector_literal_end = ABSOLUTE(.); | ||
168 | } >dram0_0_seg :dram0_0_phdr | ||
169 | |||
170 | .KernelExceptionVector.literal : ALIGN(4) | ||
171 | { | ||
172 | _KernelExceptionVector_literal_start = ABSOLUTE(.); | ||
173 | *(.KernelExceptionVector.literal) | ||
174 | . = ALIGN (4); | ||
175 | _KernelExceptionVector_literal_end = ABSOLUTE(.); | ||
176 | } >dram0_0_seg :dram0_0_phdr | ||
177 | |||
178 | .UserExceptionVector.literal : ALIGN(4) | ||
179 | { | ||
180 | _UserExceptionVector_literal_start = ABSOLUTE(.); | ||
181 | *(.UserExceptionVector.literal) | ||
182 | . = ALIGN (4); | ||
183 | _UserExceptionVector_literal_end = ABSOLUTE(.); | ||
184 | } >dram0_0_seg :dram0_0_phdr | ||
185 | |||
186 | .DoubleExceptionVector.literal : ALIGN(4) | ||
187 | { | ||
188 | _DoubleExceptionVector_literal_start = ABSOLUTE(.); | ||
189 | *(.DoubleExceptionVector.literal) | ||
190 | . = ALIGN (4); | ||
191 | _DoubleExceptionVector_literal_end = ABSOLUTE(.); | ||
192 | } >dram0_0_seg :dram0_0_phdr | ||
193 | |||
194 | .iram0.literal : ALIGN(4) | ||
195 | { | ||
196 | _iram0_literal_start = ABSOLUTE(.); | ||
197 | *(.iram0.literal) | ||
198 | *(.iram.literal) | ||
199 | *(.iram.text.literal) | ||
200 | . = ALIGN (4); | ||
201 | _iram0_literal_end = ABSOLUTE(.); | ||
202 | } >dram0_0_seg :dram0_0_phdr | ||
203 | |||
204 | .dram0.data : ALIGN(4) | ||
205 | { | ||
206 | _dram0_data_start = ABSOLUTE(.); | ||
207 | *(.dram0.data) | ||
208 | *(.dram.data) | ||
209 | . = ALIGN (4); | ||
210 | _dram0_data_end = ABSOLUTE(.); | ||
211 | } >dram0_0_seg :dram0_0_phdr | ||
212 | |||
213 | .dram0.bss (NOLOAD) : ALIGN(8) | ||
214 | { | ||
215 | . = ALIGN (8); | ||
216 | _dram0_bss_start = ABSOLUTE(.); | ||
217 | *(.dram0.bss) | ||
218 | . = ALIGN (8); | ||
219 | _dram0_bss_end = ABSOLUTE(.); | ||
220 | _memmap_seg_dram0_0_end = ALIGN(0x8); | ||
221 | } >dram0_0_seg :dram0_0_bss_phdr | ||
222 | |||
223 | |||
224 | .ResetVector.text : ALIGN(4) | ||
225 | { | ||
226 | _ResetVector_text_start = ABSOLUTE(.); | ||
227 | KEEP (*(.ResetVector.text)) | ||
228 | . = ALIGN (4); | ||
229 | _ResetVector_text_end = ABSOLUTE(.); | ||
230 | } >iram0_0_seg :iram0_0_phdr | ||
231 | |||
232 | .ResetHandler.text : ALIGN(4) | ||
233 | { | ||
234 | _ResetHandler_text_start = ABSOLUTE(.); | ||
235 | *(.ResetHandler.literal .ResetHandler.text) | ||
236 | . = ALIGN (4); | ||
237 | _ResetHandler_text_end = ABSOLUTE(.); | ||
238 | _memmap_seg_iram0_0_end = ALIGN(0x8); | ||
239 | } >iram0_0_seg :iram0_0_phdr | ||
240 | |||
241 | |||
242 | .WindowVectors.text : ALIGN(4) | ||
243 | { | ||
244 | _WindowVectors_text_start = ABSOLUTE(.); | ||
245 | KEEP (*(.WindowVectors.text)) | ||
246 | . = ALIGN (4); | ||
247 | _WindowVectors_text_end = ABSOLUTE(.); | ||
248 | _memmap_seg_iram0_1_end = ALIGN(0x8); | ||
249 | } >iram0_1_seg :iram0_1_phdr | ||
250 | |||
251 | |||
252 | .Level2InterruptVector.text : ALIGN(4) | ||
253 | { | ||
254 | _Level2InterruptVector_text_start = ABSOLUTE(.); | ||
255 | KEEP (*(.Level2InterruptVector.text)) | ||
256 | . = ALIGN (4); | ||
257 | _Level2InterruptVector_text_end = ABSOLUTE(.); | ||
258 | _memmap_seg_iram0_2_end = ALIGN(0x8); | ||
259 | } >iram0_2_seg :iram0_2_phdr | ||
260 | |||
261 | |||
262 | .Level3InterruptVector.text : ALIGN(4) | ||
263 | { | ||
264 | _Level3InterruptVector_text_start = ABSOLUTE(.); | ||
265 | KEEP (*(.Level3InterruptVector.text)) | ||
266 | . = ALIGN (4); | ||
267 | _Level3InterruptVector_text_end = ABSOLUTE(.); | ||
268 | _memmap_seg_iram0_3_end = ALIGN(0x8); | ||
269 | } >iram0_3_seg :iram0_3_phdr | ||
270 | |||
271 | |||
272 | .DebugExceptionVector.text : ALIGN(4) | ||
273 | { | ||
274 | _DebugExceptionVector_text_start = ABSOLUTE(.); | ||
275 | KEEP (*(.DebugExceptionVector.text)) | ||
276 | . = ALIGN (4); | ||
277 | _DebugExceptionVector_text_end = ABSOLUTE(.); | ||
278 | _memmap_seg_iram0_4_end = ALIGN(0x8); | ||
279 | } >iram0_4_seg :iram0_4_phdr | ||
280 | |||
281 | |||
282 | .NMIExceptionVector.text : ALIGN(4) | ||
283 | { | ||
284 | _NMIExceptionVector_text_start = ABSOLUTE(.); | ||
285 | KEEP (*(.NMIExceptionVector.text)) | ||
286 | . = ALIGN (4); | ||
287 | _NMIExceptionVector_text_end = ABSOLUTE(.); | ||
288 | _memmap_seg_iram0_5_end = ALIGN(0x8); | ||
289 | } >iram0_5_seg :iram0_5_phdr | ||
290 | |||
291 | |||
292 | .KernelExceptionVector.text : ALIGN(4) | ||
293 | { | ||
294 | _KernelExceptionVector_text_start = ABSOLUTE(.); | ||
295 | KEEP (*(.KernelExceptionVector.text)) | ||
296 | . = ALIGN (4); | ||
297 | _KernelExceptionVector_text_end = ABSOLUTE(.); | ||
298 | _memmap_seg_iram0_6_end = ALIGN(0x8); | ||
299 | } >iram0_6_seg :iram0_6_phdr | ||
300 | |||
301 | |||
302 | .UserExceptionVector.text : ALIGN(4) | ||
303 | { | ||
304 | _UserExceptionVector_text_start = ABSOLUTE(.); | ||
305 | KEEP (*(.UserExceptionVector.text)) | ||
306 | . = ALIGN (4); | ||
307 | _UserExceptionVector_text_end = ABSOLUTE(.); | ||
308 | _memmap_seg_iram0_7_end = ALIGN(0x8); | ||
309 | } >iram0_7_seg :iram0_7_phdr | ||
310 | |||
311 | |||
312 | .DoubleExceptionVector.text : ALIGN(4) | ||
313 | { | ||
314 | _DoubleExceptionVector_text_start = ABSOLUTE(.); | ||
315 | KEEP (*(.DoubleExceptionVector.text)) | ||
316 | . = ALIGN (4); | ||
317 | _DoubleExceptionVector_text_end = ABSOLUTE(.); | ||
318 | } >iram0_8_seg :iram0_8_phdr | ||
319 | |||
320 | .iram0.text : ALIGN(4) | ||
321 | { | ||
322 | _iram0_text_start = ABSOLUTE(.); | ||
323 | *(.iram0.text) | ||
324 | *(.iram.text) | ||
325 | . = ALIGN (4); | ||
326 | _iram0_text_end = ABSOLUTE(.); | ||
327 | _memmap_seg_iram0_8_end = ALIGN(0x8); | ||
328 | } >iram0_8_seg :iram0_8_phdr | ||
329 | |||
330 | |||
331 | .sram.rodata : ALIGN(4) | ||
332 | { | ||
333 | _sram_rodata_start = ABSOLUTE(.); | ||
334 | *(.sram.rodata) | ||
335 | . = ALIGN (4); | ||
336 | _sram_rodata_end = ABSOLUTE(.); | ||
337 | } >dsp_core_seg :dsp_core_phdr | ||
338 | |||
339 | .clib.rodata : ALIGN(4) | ||
340 | { | ||
341 | _clib_rodata_start = ABSOLUTE(.); | ||
342 | *(.clib.rodata) | ||
343 | . = ALIGN (4); | ||
344 | _clib_rodata_end = ABSOLUTE(.); | ||
345 | } >dsp_core_seg :dsp_core_phdr | ||
346 | |||
347 | .rtos.rodata : ALIGN(4) | ||
348 | { | ||
349 | _rtos_rodata_start = ABSOLUTE(.); | ||
350 | *(.rtos.rodata) | ||
351 | . = ALIGN (4); | ||
352 | _rtos_rodata_end = ABSOLUTE(.); | ||
353 | } >dsp_core_seg :dsp_core_phdr | ||
354 | |||
355 | .rodata : ALIGN(4) | ||
356 | { | ||
357 | _rodata_start = ABSOLUTE(.); | ||
358 | *(.rodata) | ||
359 | *(SORT(.rodata.sort.*)) | ||
360 | KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*)) | ||
361 | *(.rodata.*) | ||
362 | *(.gnu.linkonce.r.*) | ||
363 | *(.rodata1) | ||
364 | __XT_EXCEPTION_TABLE__ = ABSOLUTE(.); | ||
365 | KEEP (*(.xt_except_table)) | ||
366 | KEEP (*(.gcc_except_table)) | ||
367 | *(.gnu.linkonce.e.*) | ||
368 | *(.gnu.version_r) | ||
369 | KEEP (*(.eh_frame)) | ||
370 | /* C++ constructor and destructor tables, properly ordered: */ | ||
371 | KEEP (*crtbegin.o(.ctors)) | ||
372 | KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) | ||
373 | KEEP (*(SORT(.ctors.*))) | ||
374 | KEEP (*(.ctors)) | ||
375 | KEEP (*crtbegin.o(.dtors)) | ||
376 | KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) | ||
377 | KEEP (*(SORT(.dtors.*))) | ||
378 | KEEP (*(.dtors)) | ||
379 | /* C++ exception handlers table: */ | ||
380 | __XT_EXCEPTION_DESCS__ = ABSOLUTE(.); | ||
381 | *(.xt_except_desc) | ||
382 | *(.gnu.linkonce.h.*) | ||
383 | __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.); | ||
384 | *(.xt_except_desc_end) | ||
385 | *(.dynamic) | ||
386 | *(.gnu.version_d) | ||
387 | . = ALIGN(4); /* this table MUST be 4-byte aligned */ | ||
388 | _bss_table_start = ABSOLUTE(.); | ||
389 | LONG(_dram0_bss_start) | ||
390 | LONG(_dram0_bss_end) | ||
391 | LONG(_bss_start) | ||
392 | LONG(_bss_end) | ||
393 | _bss_table_end = ABSOLUTE(.); | ||
394 | . = ALIGN (4); | ||
395 | _rodata_end = ABSOLUTE(.); | ||
396 | } >dsp_core_seg :dsp_core_phdr | ||
397 | |||
398 | .sram.text : ALIGN(4) | ||
399 | { | ||
400 | _sram_text_start = ABSOLUTE(.); | ||
401 | *(.sram.literal .sram.text) | ||
402 | . = ALIGN (4); | ||
403 | _sram_text_end = ABSOLUTE(.); | ||
404 | } >dsp_core_seg :dsp_core_phdr | ||
405 | |||
406 | .text : ALIGN(4) | ||
407 | { | ||
408 | _stext = .; | ||
409 | _text_start = ABSOLUTE(.); | ||
410 | *(.entry.text) | ||
411 | *(.init.literal) | ||
412 | KEEP(*(.init)) | ||
413 | *(.literal.sort.* SORT(.text.sort.*)) | ||
414 | KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*)) | ||
415 | *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) | ||
416 | *(.fini.literal) | ||
417 | KEEP(*(.fini)) | ||
418 | *(.gnu.version) | ||
419 | . = ALIGN (4); | ||
420 | _text_end = ABSOLUTE(.); | ||
421 | _etext = .; | ||
422 | } >dsp_core_seg :dsp_core_phdr | ||
423 | |||
424 | .clib.text : ALIGN(4) | ||
425 | { | ||
426 | _clib_text_start = ABSOLUTE(.); | ||
427 | *(.clib.literal .clib.text) | ||
428 | . = ALIGN (4); | ||
429 | _clib_text_end = ABSOLUTE(.); | ||
430 | } >dsp_core_seg :dsp_core_phdr | ||
431 | |||
432 | .rtos.text : ALIGN(4) | ||
433 | { | ||
434 | _rtos_text_start = ABSOLUTE(.); | ||
435 | *(.rtos.literal .rtos.text) | ||
436 | . = ALIGN (4); | ||
437 | _rtos_text_end = ABSOLUTE(.); | ||
438 | } >dsp_core_seg :dsp_core_phdr | ||
439 | |||
440 | .clib.data : ALIGN(4) | ||
441 | { | ||
442 | _clib_data_start = ABSOLUTE(.); | ||
443 | *(.clib.data) | ||
444 | . = ALIGN (4); | ||
445 | _clib_data_end = ABSOLUTE(.); | ||
446 | } >dsp_core_seg :dsp_core_phdr | ||
447 | |||
448 | .clib.percpu.data : ALIGN(4) | ||
449 | { | ||
450 | _clib_percpu_data_start = ABSOLUTE(.); | ||
451 | *(.clib.percpu.data) | ||
452 | . = ALIGN (4); | ||
453 | _clib_percpu_data_end = ABSOLUTE(.); | ||
454 | } >dsp_core_seg :dsp_core_phdr | ||
455 | |||
456 | .rtos.percpu.data : ALIGN(4) | ||
457 | { | ||
458 | _rtos_percpu_data_start = ABSOLUTE(.); | ||
459 | *(.rtos.percpu.data) | ||
460 | . = ALIGN (4); | ||
461 | _rtos_percpu_data_end = ABSOLUTE(.); | ||
462 | } >dsp_core_seg :dsp_core_phdr | ||
463 | |||
464 | .rtos.data : ALIGN(4) | ||
465 | { | ||
466 | _rtos_data_start = ABSOLUTE(.); | ||
467 | *(.rtos.data) | ||
468 | . = ALIGN (4); | ||
469 | _rtos_data_end = ABSOLUTE(.); | ||
470 | } >dsp_core_seg :dsp_core_phdr | ||
471 | |||
472 | .sram.data : ALIGN(4) | ||
473 | { | ||
474 | _sram_data_start = ABSOLUTE(.); | ||
475 | *(.sram.data) | ||
476 | . = ALIGN (4); | ||
477 | _sram_data_end = ABSOLUTE(.); | ||
478 | } >dsp_core_seg :dsp_core_phdr | ||
479 | |||
480 | .data : ALIGN(4) | ||
481 | { | ||
482 | _data_start = ABSOLUTE(.); | ||
483 | *(.data) | ||
484 | *(SORT(.data.sort.*)) | ||
485 | KEEP (*(SORT(.data.keepsort.*) .data.keep.*)) | ||
486 | *(.data.*) | ||
487 | *(.gnu.linkonce.d.*) | ||
488 | KEEP(*(.gnu.linkonce.d.*personality*)) | ||
489 | *(.data1) | ||
490 | *(.sdata) | ||
491 | *(.sdata.*) | ||
492 | *(.gnu.linkonce.s.*) | ||
493 | *(.sdata2) | ||
494 | *(.sdata2.*) | ||
495 | *(.gnu.linkonce.s2.*) | ||
496 | KEEP(*(.jcr)) | ||
497 | *(__llvm_prf_cnts) | ||
498 | *(__llvm_prf_data) | ||
499 | *(__llvm_prf_vnds) | ||
500 | . = ALIGN (4); | ||
501 | _data_end = ABSOLUTE(.); | ||
502 | } >dsp_core_seg :dsp_core_phdr | ||
503 | |||
504 | __llvm_prf_names : ALIGN(4) | ||
505 | { | ||
506 | __llvm_prf_names_start = ABSOLUTE(.); | ||
507 | *(__llvm_prf_names) | ||
508 | . = ALIGN (4); | ||
509 | __llvm_prf_names_end = ABSOLUTE(.); | ||
510 | } >dsp_core_seg :dsp_core_phdr | ||
511 | |||
512 | .bss (NOLOAD) : ALIGN(8) | ||
513 | { | ||
514 | . = ALIGN (8); | ||
515 | _bss_start = ABSOLUTE(.); | ||
516 | *(.dynsbss) | ||
517 | *(.sbss) | ||
518 | *(.sbss.*) | ||
519 | *(.gnu.linkonce.sb.*) | ||
520 | *(.scommon) | ||
521 | *(.sbss2) | ||
522 | *(.sbss2.*) | ||
523 | *(.gnu.linkonce.sb2.*) | ||
524 | *(.dynbss) | ||
525 | *(.bss) | ||
526 | *(SORT(.bss.sort.*)) | ||
527 | KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*)) | ||
528 | *(.bss.*) | ||
529 | *(.gnu.linkonce.b.*) | ||
530 | *(COMMON) | ||
531 | *(.clib.bss) | ||
532 | *(.clib.percpu.bss) | ||
533 | *(.rtos.percpu.bss) | ||
534 | *(.rtos.bss) | ||
535 | *(.sram.bss) | ||
536 | . = ALIGN (8); | ||
537 | _bss_end = ABSOLUTE(.); | ||
538 | _end = ALIGN(0x8); | ||
539 | PROVIDE(end = ALIGN(0x8)); | ||
540 | _stack_sentry = ALIGN(0x8); | ||
541 | _memmap_seg_dsp_core_end = ALIGN(0x8); | ||
542 | } >dsp_core_seg :dsp_core_bss_phdr | ||
543 | |||
544 | PROVIDE(__stack = 0x480000); | ||
545 | _heap_sentry = 0x480000; | ||
546 | .debug 0 : { *(.debug) } | ||
547 | .line 0 : { *(.line) } | ||
548 | .debug_srcinfo 0 : { *(.debug_srcinfo) } | ||
549 | .debug_sfnames 0 : { *(.debug_sfnames) } | ||
550 | .debug_aranges 0 : { *(.debug_aranges) } | ||
551 | .debug_pubnames 0 : { *(.debug_pubnames) } | ||
552 | .debug_info 0 : { *(.debug_info) } | ||
553 | .debug_abbrev 0 : { *(.debug_abbrev) } | ||
554 | .debug_line 0 : { *(.debug_line) } | ||
555 | .debug_frame 0 : { *(.debug_frame) } | ||
556 | .debug_str 0 : { *(.debug_str) } | ||
557 | .debug_loc 0 : { *(.debug_loc) } | ||
558 | .debug_macinfo 0 : { *(.debug_macinfo) } | ||
559 | .debug_weaknames 0 : { *(.debug_weaknames) } | ||
560 | .debug_funcnames 0 : { *(.debug_funcnames) } | ||
561 | .debug_typenames 0 : { *(.debug_typenames) } | ||
562 | .debug_varnames 0 : { *(.debug_varnames) } | ||
563 | .xt.insn 0 : | ||
564 | { | ||
565 | KEEP (*(.xt.insn)) | ||
566 | KEEP (*(.gnu.linkonce.x.*)) | ||
567 | } | ||
568 | .xt.prop 0 : | ||
569 | { | ||
570 | KEEP (*(.xt.prop)) | ||
571 | KEEP (*(.xt.prop.*)) | ||
572 | KEEP (*(.gnu.linkonce.prop.*)) | ||
573 | } | ||
574 | .xt.lit 0 : | ||
575 | { | ||
576 | KEEP (*(.xt.lit)) | ||
577 | KEEP (*(.xt.lit.*)) | ||
578 | KEEP (*(.gnu.linkonce.p.*)) | ||
579 | } | ||
580 | .debug.xt.callgraph 0 : | ||
581 | { | ||
582 | KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*)) | ||
583 | } | ||
584 | } | ||
585 | |||