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Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim')
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.x585
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xbn585
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xn585
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xr61
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xu61
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/memmap.xmm78
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/specs36
7 files changed, 1991 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.x b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.x
new file mode 100644
index 000000000..8fd3ed122
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.x
@@ -0,0 +1,585 @@
1/* This linker script generated from xt-genldscripts.tpp for LSP C:/usr/xtensa/Xplorer-8.0.10-workspaces/XtensaInfo/Models/nxp_rt600_lowmem_memmap/sim */
2/* Linker Script for default link */
3MEMORY
4{
5 dsp_core_seg : org = 0x00300000, len = 0x180000
6 dsp_uncached_seg : org = 0x20040000, len = 0x40000
7 dram0_0_seg : org = 0x24000000, len = 0x10000
8 iram0_0_seg : org = 0x24020000, len = 0x400
9 iram0_1_seg : org = 0x24020400, len = 0x17C
10 iram0_2_seg : org = 0x2402057C, len = 0x20
11 iram0_3_seg : org = 0x2402059C, len = 0x20
12 iram0_4_seg : org = 0x240205BC, len = 0x20
13 iram0_5_seg : org = 0x240205DC, len = 0x20
14 iram0_6_seg : org = 0x240205FC, len = 0x20
15 iram0_7_seg : org = 0x2402061C, len = 0x20
16 iram0_8_seg : org = 0x2402063C, len = 0xF9C4
17}
18
19PHDRS
20{
21 dsp_core_phdr PT_LOAD;
22 dsp_core_bss_phdr PT_LOAD;
23 dsp_uncached_phdr PT_LOAD;
24 dram0_0_phdr PT_LOAD;
25 dram0_0_bss_phdr PT_LOAD;
26 iram0_0_phdr PT_LOAD;
27 iram0_1_phdr PT_LOAD;
28 iram0_2_phdr PT_LOAD;
29 iram0_3_phdr PT_LOAD;
30 iram0_4_phdr PT_LOAD;
31 iram0_5_phdr PT_LOAD;
32 iram0_6_phdr PT_LOAD;
33 iram0_7_phdr PT_LOAD;
34 iram0_8_phdr PT_LOAD;
35}
36
37
38/* Default entry point: */
39ENTRY(_ResetVector)
40
41
42/* Memory boundary addresses: */
43_memmap_mem_sram_start = 0x0;
44_memmap_mem_sram_end = 0x480000;
45_memmap_mem_dram0_start = 0x24000000;
46_memmap_mem_dram0_end = 0x24010000;
47_memmap_mem_iram0_start = 0x24020000;
48_memmap_mem_iram0_end = 0x24030000;
49_memmap_mem_sram_uncached_start = 0x20000000;
50_memmap_mem_sram_uncached_end = 0x20480000;
51
52/* Memory segment boundary addresses: */
53_memmap_seg_dsp_core_start = 0x300000;
54_memmap_seg_dsp_core_max = 0x480000;
55_memmap_seg_dsp_uncached_start = 0x20040000;
56_memmap_seg_dsp_uncached_max = 0x20080000;
57_memmap_seg_dram0_0_start = 0x24000000;
58_memmap_seg_dram0_0_max = 0x24010000;
59_memmap_seg_iram0_0_start = 0x24020000;
60_memmap_seg_iram0_0_max = 0x24020400;
61_memmap_seg_iram0_1_start = 0x24020400;
62_memmap_seg_iram0_1_max = 0x2402057c;
63_memmap_seg_iram0_2_start = 0x2402057c;
64_memmap_seg_iram0_2_max = 0x2402059c;
65_memmap_seg_iram0_3_start = 0x2402059c;
66_memmap_seg_iram0_3_max = 0x240205bc;
67_memmap_seg_iram0_4_start = 0x240205bc;
68_memmap_seg_iram0_4_max = 0x240205dc;
69_memmap_seg_iram0_5_start = 0x240205dc;
70_memmap_seg_iram0_5_max = 0x240205fc;
71_memmap_seg_iram0_6_start = 0x240205fc;
72_memmap_seg_iram0_6_max = 0x2402061c;
73_memmap_seg_iram0_7_start = 0x2402061c;
74_memmap_seg_iram0_7_max = 0x2402063c;
75_memmap_seg_iram0_8_start = 0x2402063c;
76_memmap_seg_iram0_8_max = 0x24030000;
77
78_rom_store_table = 0;
79PROVIDE(_memmap_reset_vector = 0x24020000);
80PROVIDE(_memmap_vecbase_reset = 0x24020400);
81/* Various memory-map dependent cache attribute settings: */
82_memmap_cacheattr_wb_base = 0x00000044;
83_memmap_cacheattr_wt_base = 0x00000011;
84_memmap_cacheattr_bp_base = 0x00000022;
85_memmap_cacheattr_unused_mask = 0xFFFFFF00;
86_memmap_cacheattr_wb_trapnull = 0x22222244;
87_memmap_cacheattr_wba_trapnull = 0x22222244;
88_memmap_cacheattr_wbna_trapnull = 0x22222255;
89_memmap_cacheattr_wt_trapnull = 0x22222211;
90_memmap_cacheattr_bp_trapnull = 0x22222222;
91_memmap_cacheattr_wb_strict = 0xFFFFFF44;
92_memmap_cacheattr_wt_strict = 0xFFFFFF11;
93_memmap_cacheattr_bp_strict = 0xFFFFFF22;
94_memmap_cacheattr_wb_allvalid = 0x22222244;
95_memmap_cacheattr_wt_allvalid = 0x22222211;
96_memmap_cacheattr_bp_allvalid = 0x22222222;
97_memmap_region_map = 0x00000003;
98PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
99
100SECTIONS
101{
102
103 NonCacheable.init : ALIGN(4)
104 {
105 NonCacheable_init_start = ABSOLUTE(.);
106 *(NonCacheable.init)
107 . = ALIGN (4);
108 NonCacheable_init_end = ABSOLUTE(.);
109 } >dsp_uncached_seg :dsp_uncached_phdr
110
111 NonCacheable : ALIGN(4)
112 {
113 NonCacheable_start = ABSOLUTE(.);
114 *(NonCacheable)
115 . = ALIGN (4);
116 NonCacheable_end = ABSOLUTE(.);
117 _memmap_seg_dsp_uncached_end = ALIGN(0x8);
118 } >dsp_uncached_seg :dsp_uncached_phdr
119
120
121 .dram0.rodata : ALIGN(4)
122 {
123 _dram0_rodata_start = ABSOLUTE(.);
124 *(.dram0.rodata)
125 *(.dram.rodata)
126 . = ALIGN (4);
127 _dram0_rodata_end = ABSOLUTE(.);
128 } >dram0_0_seg :dram0_0_phdr
129
130 .ResetVector.literal : ALIGN(4)
131 {
132 _ResetVector_literal_start = ABSOLUTE(.);
133 *(.ResetVector.literal)
134 . = ALIGN (4);
135 _ResetVector_literal_end = ABSOLUTE(.);
136 } >dram0_0_seg :dram0_0_phdr
137
138 .Level2InterruptVector.literal : ALIGN(4)
139 {
140 _Level2InterruptVector_literal_start = ABSOLUTE(.);
141 *(.Level2InterruptVector.literal)
142 . = ALIGN (4);
143 _Level2InterruptVector_literal_end = ABSOLUTE(.);
144 } >dram0_0_seg :dram0_0_phdr
145
146 .Level3InterruptVector.literal : ALIGN(4)
147 {
148 _Level3InterruptVector_literal_start = ABSOLUTE(.);
149 *(.Level3InterruptVector.literal)
150 . = ALIGN (4);
151 _Level3InterruptVector_literal_end = ABSOLUTE(.);
152 } >dram0_0_seg :dram0_0_phdr
153
154 .DebugExceptionVector.literal : ALIGN(4)
155 {
156 _DebugExceptionVector_literal_start = ABSOLUTE(.);
157 *(.DebugExceptionVector.literal)
158 . = ALIGN (4);
159 _DebugExceptionVector_literal_end = ABSOLUTE(.);
160 } >dram0_0_seg :dram0_0_phdr
161
162 .NMIExceptionVector.literal : ALIGN(4)
163 {
164 _NMIExceptionVector_literal_start = ABSOLUTE(.);
165 *(.NMIExceptionVector.literal)
166 . = ALIGN (4);
167 _NMIExceptionVector_literal_end = ABSOLUTE(.);
168 } >dram0_0_seg :dram0_0_phdr
169
170 .KernelExceptionVector.literal : ALIGN(4)
171 {
172 _KernelExceptionVector_literal_start = ABSOLUTE(.);
173 *(.KernelExceptionVector.literal)
174 . = ALIGN (4);
175 _KernelExceptionVector_literal_end = ABSOLUTE(.);
176 } >dram0_0_seg :dram0_0_phdr
177
178 .UserExceptionVector.literal : ALIGN(4)
179 {
180 _UserExceptionVector_literal_start = ABSOLUTE(.);
181 *(.UserExceptionVector.literal)
182 . = ALIGN (4);
183 _UserExceptionVector_literal_end = ABSOLUTE(.);
184 } >dram0_0_seg :dram0_0_phdr
185
186 .DoubleExceptionVector.literal : ALIGN(4)
187 {
188 _DoubleExceptionVector_literal_start = ABSOLUTE(.);
189 *(.DoubleExceptionVector.literal)
190 . = ALIGN (4);
191 _DoubleExceptionVector_literal_end = ABSOLUTE(.);
192 } >dram0_0_seg :dram0_0_phdr
193
194 .iram0.literal : ALIGN(4)
195 {
196 _iram0_literal_start = ABSOLUTE(.);
197 *(.iram0.literal)
198 *(.iram.literal)
199 *(.iram.text.literal)
200 . = ALIGN (4);
201 _iram0_literal_end = ABSOLUTE(.);
202 } >dram0_0_seg :dram0_0_phdr
203
204 .dram0.data : ALIGN(4)
205 {
206 _dram0_data_start = ABSOLUTE(.);
207 *(.dram0.data)
208 *(.dram.data)
209 . = ALIGN (4);
210 _dram0_data_end = ABSOLUTE(.);
211 } >dram0_0_seg :dram0_0_phdr
212
213 .dram0.bss (NOLOAD) : ALIGN(8)
214 {
215 . = ALIGN (8);
216 _dram0_bss_start = ABSOLUTE(.);
217 *(.dram0.bss)
218 . = ALIGN (8);
219 _dram0_bss_end = ABSOLUTE(.);
220 _memmap_seg_dram0_0_end = ALIGN(0x8);
221 } >dram0_0_seg :dram0_0_bss_phdr
222
223
224 .ResetVector.text : ALIGN(4)
225 {
226 _ResetVector_text_start = ABSOLUTE(.);
227 KEEP (*(.ResetVector.text))
228 . = ALIGN (4);
229 _ResetVector_text_end = ABSOLUTE(.);
230 } >iram0_0_seg :iram0_0_phdr
231
232 .ResetHandler.text : ALIGN(4)
233 {
234 _ResetHandler_text_start = ABSOLUTE(.);
235 *(.ResetHandler.literal .ResetHandler.text)
236 . = ALIGN (4);
237 _ResetHandler_text_end = ABSOLUTE(.);
238 _memmap_seg_iram0_0_end = ALIGN(0x8);
239 } >iram0_0_seg :iram0_0_phdr
240
241
242 .WindowVectors.text : ALIGN(4)
243 {
244 _WindowVectors_text_start = ABSOLUTE(.);
245 KEEP (*(.WindowVectors.text))
246 . = ALIGN (4);
247 _WindowVectors_text_end = ABSOLUTE(.);
248 _memmap_seg_iram0_1_end = ALIGN(0x8);
249 } >iram0_1_seg :iram0_1_phdr
250
251
252 .Level2InterruptVector.text : ALIGN(4)
253 {
254 _Level2InterruptVector_text_start = ABSOLUTE(.);
255 KEEP (*(.Level2InterruptVector.text))
256 . = ALIGN (4);
257 _Level2InterruptVector_text_end = ABSOLUTE(.);
258 _memmap_seg_iram0_2_end = ALIGN(0x8);
259 } >iram0_2_seg :iram0_2_phdr
260
261
262 .Level3InterruptVector.text : ALIGN(4)
263 {
264 _Level3InterruptVector_text_start = ABSOLUTE(.);
265 KEEP (*(.Level3InterruptVector.text))
266 . = ALIGN (4);
267 _Level3InterruptVector_text_end = ABSOLUTE(.);
268 _memmap_seg_iram0_3_end = ALIGN(0x8);
269 } >iram0_3_seg :iram0_3_phdr
270
271
272 .DebugExceptionVector.text : ALIGN(4)
273 {
274 _DebugExceptionVector_text_start = ABSOLUTE(.);
275 KEEP (*(.DebugExceptionVector.text))
276 . = ALIGN (4);
277 _DebugExceptionVector_text_end = ABSOLUTE(.);
278 _memmap_seg_iram0_4_end = ALIGN(0x8);
279 } >iram0_4_seg :iram0_4_phdr
280
281
282 .NMIExceptionVector.text : ALIGN(4)
283 {
284 _NMIExceptionVector_text_start = ABSOLUTE(.);
285 KEEP (*(.NMIExceptionVector.text))
286 . = ALIGN (4);
287 _NMIExceptionVector_text_end = ABSOLUTE(.);
288 _memmap_seg_iram0_5_end = ALIGN(0x8);
289 } >iram0_5_seg :iram0_5_phdr
290
291
292 .KernelExceptionVector.text : ALIGN(4)
293 {
294 _KernelExceptionVector_text_start = ABSOLUTE(.);
295 KEEP (*(.KernelExceptionVector.text))
296 . = ALIGN (4);
297 _KernelExceptionVector_text_end = ABSOLUTE(.);
298 _memmap_seg_iram0_6_end = ALIGN(0x8);
299 } >iram0_6_seg :iram0_6_phdr
300
301
302 .UserExceptionVector.text : ALIGN(4)
303 {
304 _UserExceptionVector_text_start = ABSOLUTE(.);
305 KEEP (*(.UserExceptionVector.text))
306 . = ALIGN (4);
307 _UserExceptionVector_text_end = ABSOLUTE(.);
308 _memmap_seg_iram0_7_end = ALIGN(0x8);
309 } >iram0_7_seg :iram0_7_phdr
310
311
312 .DoubleExceptionVector.text : ALIGN(4)
313 {
314 _DoubleExceptionVector_text_start = ABSOLUTE(.);
315 KEEP (*(.DoubleExceptionVector.text))
316 . = ALIGN (4);
317 _DoubleExceptionVector_text_end = ABSOLUTE(.);
318 } >iram0_8_seg :iram0_8_phdr
319
320 .iram0.text : ALIGN(4)
321 {
322 _iram0_text_start = ABSOLUTE(.);
323 *(.iram0.text)
324 *(.iram.text)
325 . = ALIGN (4);
326 _iram0_text_end = ABSOLUTE(.);
327 _memmap_seg_iram0_8_end = ALIGN(0x8);
328 } >iram0_8_seg :iram0_8_phdr
329
330
331 .sram.rodata : ALIGN(4)
332 {
333 _sram_rodata_start = ABSOLUTE(.);
334 *(.sram.rodata)
335 . = ALIGN (4);
336 _sram_rodata_end = ABSOLUTE(.);
337 } >dsp_core_seg :dsp_core_phdr
338
339 .clib.rodata : ALIGN(4)
340 {
341 _clib_rodata_start = ABSOLUTE(.);
342 *(.clib.rodata)
343 . = ALIGN (4);
344 _clib_rodata_end = ABSOLUTE(.);
345 } >dsp_core_seg :dsp_core_phdr
346
347 .rtos.rodata : ALIGN(4)
348 {
349 _rtos_rodata_start = ABSOLUTE(.);
350 *(.rtos.rodata)
351 . = ALIGN (4);
352 _rtos_rodata_end = ABSOLUTE(.);
353 } >dsp_core_seg :dsp_core_phdr
354
355 .rodata : ALIGN(4)
356 {
357 _rodata_start = ABSOLUTE(.);
358 *(.rodata)
359 *(SORT(.rodata.sort.*))
360 KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
361 *(.rodata.*)
362 *(.gnu.linkonce.r.*)
363 *(.rodata1)
364 __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
365 KEEP (*(.xt_except_table))
366 KEEP (*(.gcc_except_table))
367 *(.gnu.linkonce.e.*)
368 *(.gnu.version_r)
369 KEEP (*(.eh_frame))
370 /* C++ constructor and destructor tables, properly ordered: */
371 KEEP (*crtbegin.o(.ctors))
372 KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
373 KEEP (*(SORT(.ctors.*)))
374 KEEP (*(.ctors))
375 KEEP (*crtbegin.o(.dtors))
376 KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
377 KEEP (*(SORT(.dtors.*)))
378 KEEP (*(.dtors))
379 /* C++ exception handlers table: */
380 __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
381 *(.xt_except_desc)
382 *(.gnu.linkonce.h.*)
383 __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
384 *(.xt_except_desc_end)
385 *(.dynamic)
386 *(.gnu.version_d)
387 . = ALIGN(4); /* this table MUST be 4-byte aligned */
388 _bss_table_start = ABSOLUTE(.);
389 LONG(_dram0_bss_start)
390 LONG(_dram0_bss_end)
391 LONG(_bss_start)
392 LONG(_bss_end)
393 _bss_table_end = ABSOLUTE(.);
394 . = ALIGN (4);
395 _rodata_end = ABSOLUTE(.);
396 } >dsp_core_seg :dsp_core_phdr
397
398 .sram.text : ALIGN(4)
399 {
400 _sram_text_start = ABSOLUTE(.);
401 *(.sram.literal .sram.text)
402 . = ALIGN (4);
403 _sram_text_end = ABSOLUTE(.);
404 } >dsp_core_seg :dsp_core_phdr
405
406 .text : ALIGN(4)
407 {
408 _stext = .;
409 _text_start = ABSOLUTE(.);
410 *(.entry.text)
411 *(.init.literal)
412 KEEP(*(.init))
413 *(.literal.sort.* SORT(.text.sort.*))
414 KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
415 *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
416 *(.fini.literal)
417 KEEP(*(.fini))
418 *(.gnu.version)
419 . = ALIGN (4);
420 _text_end = ABSOLUTE(.);
421 _etext = .;
422 } >dsp_core_seg :dsp_core_phdr
423
424 .clib.text : ALIGN(4)
425 {
426 _clib_text_start = ABSOLUTE(.);
427 *(.clib.literal .clib.text)
428 . = ALIGN (4);
429 _clib_text_end = ABSOLUTE(.);
430 } >dsp_core_seg :dsp_core_phdr
431
432 .rtos.text : ALIGN(4)
433 {
434 _rtos_text_start = ABSOLUTE(.);
435 *(.rtos.literal .rtos.text)
436 . = ALIGN (4);
437 _rtos_text_end = ABSOLUTE(.);
438 } >dsp_core_seg :dsp_core_phdr
439
440 .clib.data : ALIGN(4)
441 {
442 _clib_data_start = ABSOLUTE(.);
443 *(.clib.data)
444 . = ALIGN (4);
445 _clib_data_end = ABSOLUTE(.);
446 } >dsp_core_seg :dsp_core_phdr
447
448 .clib.percpu.data : ALIGN(4)
449 {
450 _clib_percpu_data_start = ABSOLUTE(.);
451 *(.clib.percpu.data)
452 . = ALIGN (4);
453 _clib_percpu_data_end = ABSOLUTE(.);
454 } >dsp_core_seg :dsp_core_phdr
455
456 .rtos.percpu.data : ALIGN(4)
457 {
458 _rtos_percpu_data_start = ABSOLUTE(.);
459 *(.rtos.percpu.data)
460 . = ALIGN (4);
461 _rtos_percpu_data_end = ABSOLUTE(.);
462 } >dsp_core_seg :dsp_core_phdr
463
464 .rtos.data : ALIGN(4)
465 {
466 _rtos_data_start = ABSOLUTE(.);
467 *(.rtos.data)
468 . = ALIGN (4);
469 _rtos_data_end = ABSOLUTE(.);
470 } >dsp_core_seg :dsp_core_phdr
471
472 .sram.data : ALIGN(4)
473 {
474 _sram_data_start = ABSOLUTE(.);
475 *(.sram.data)
476 . = ALIGN (4);
477 _sram_data_end = ABSOLUTE(.);
478 } >dsp_core_seg :dsp_core_phdr
479
480 .data : ALIGN(4)
481 {
482 _data_start = ABSOLUTE(.);
483 *(.data)
484 *(SORT(.data.sort.*))
485 KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
486 *(.data.*)
487 *(.gnu.linkonce.d.*)
488 KEEP(*(.gnu.linkonce.d.*personality*))
489 *(.data1)
490 *(.sdata)
491 *(.sdata.*)
492 *(.gnu.linkonce.s.*)
493 *(.sdata2)
494 *(.sdata2.*)
495 *(.gnu.linkonce.s2.*)
496 KEEP(*(.jcr))
497 *(__llvm_prf_cnts)
498 *(__llvm_prf_data)
499 *(__llvm_prf_vnds)
500 . = ALIGN (4);
501 _data_end = ABSOLUTE(.);
502 } >dsp_core_seg :dsp_core_phdr
503
504 __llvm_prf_names : ALIGN(4)
505 {
506 __llvm_prf_names_start = ABSOLUTE(.);
507 *(__llvm_prf_names)
508 . = ALIGN (4);
509 __llvm_prf_names_end = ABSOLUTE(.);
510 } >dsp_core_seg :dsp_core_phdr
511
512 .bss (NOLOAD) : ALIGN(8)
513 {
514 . = ALIGN (8);
515 _bss_start = ABSOLUTE(.);
516 *(.dynsbss)
517 *(.sbss)
518 *(.sbss.*)
519 *(.gnu.linkonce.sb.*)
520 *(.scommon)
521 *(.sbss2)
522 *(.sbss2.*)
523 *(.gnu.linkonce.sb2.*)
524 *(.dynbss)
525 *(.bss)
526 *(SORT(.bss.sort.*))
527 KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
528 *(.bss.*)
529 *(.gnu.linkonce.b.*)
530 *(COMMON)
531 *(.clib.bss)
532 *(.clib.percpu.bss)
533 *(.rtos.percpu.bss)
534 *(.rtos.bss)
535 *(.sram.bss)
536 . = ALIGN (8);
537 _bss_end = ABSOLUTE(.);
538 _end = ALIGN(0x8);
539 PROVIDE(end = ALIGN(0x8));
540 _stack_sentry = ALIGN(0x8);
541 _memmap_seg_dsp_core_end = ALIGN(0x8);
542 } >dsp_core_seg :dsp_core_bss_phdr
543
544 PROVIDE(__stack = 0x480000);
545 _heap_sentry = 0x480000;
546 .debug 0 : { *(.debug) }
547 .line 0 : { *(.line) }
548 .debug_srcinfo 0 : { *(.debug_srcinfo) }
549 .debug_sfnames 0 : { *(.debug_sfnames) }
550 .debug_aranges 0 : { *(.debug_aranges) }
551 .debug_pubnames 0 : { *(.debug_pubnames) }
552 .debug_info 0 : { *(.debug_info) }
553 .debug_abbrev 0 : { *(.debug_abbrev) }
554 .debug_line 0 : { *(.debug_line) }
555 .debug_frame 0 : { *(.debug_frame) }
556 .debug_str 0 : { *(.debug_str) }
557 .debug_loc 0 : { *(.debug_loc) }
558 .debug_macinfo 0 : { *(.debug_macinfo) }
559 .debug_weaknames 0 : { *(.debug_weaknames) }
560 .debug_funcnames 0 : { *(.debug_funcnames) }
561 .debug_typenames 0 : { *(.debug_typenames) }
562 .debug_varnames 0 : { *(.debug_varnames) }
563 .xt.insn 0 :
564 {
565 KEEP (*(.xt.insn))
566 KEEP (*(.gnu.linkonce.x.*))
567 }
568 .xt.prop 0 :
569 {
570 KEEP (*(.xt.prop))
571 KEEP (*(.xt.prop.*))
572 KEEP (*(.gnu.linkonce.prop.*))
573 }
574 .xt.lit 0 :
575 {
576 KEEP (*(.xt.lit))
577 KEEP (*(.xt.lit.*))
578 KEEP (*(.gnu.linkonce.p.*))
579 }
580 .debug.xt.callgraph 0 :
581 {
582 KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
583 }
584}
585
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xbn b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xbn
new file mode 100644
index 000000000..ca273c0fa
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xbn
@@ -0,0 +1,585 @@
1/* This linker script generated from xt-genldscripts.tpp for LSP C:/usr/xtensa/Xplorer-8.0.10-workspaces/XtensaInfo/Models/nxp_rt600_lowmem_memmap/sim */
2/* Linker Script for ld -N */
3MEMORY
4{
5 dsp_core_seg : org = 0x00300000, len = 0x180000
6 dsp_uncached_seg : org = 0x20040000, len = 0x40000
7 dram0_0_seg : org = 0x24000000, len = 0x10000
8 iram0_0_seg : org = 0x24020000, len = 0x400
9 iram0_1_seg : org = 0x24020400, len = 0x17C
10 iram0_2_seg : org = 0x2402057C, len = 0x20
11 iram0_3_seg : org = 0x2402059C, len = 0x20
12 iram0_4_seg : org = 0x240205BC, len = 0x20
13 iram0_5_seg : org = 0x240205DC, len = 0x20
14 iram0_6_seg : org = 0x240205FC, len = 0x20
15 iram0_7_seg : org = 0x2402061C, len = 0x20
16 iram0_8_seg : org = 0x2402063C, len = 0xF9C4
17}
18
19PHDRS
20{
21 dsp_core_phdr PT_LOAD;
22 dsp_core_bss_phdr PT_LOAD;
23 dsp_uncached_phdr PT_LOAD;
24 dram0_0_phdr PT_LOAD;
25 dram0_0_bss_phdr PT_LOAD;
26 iram0_0_phdr PT_LOAD;
27 iram0_1_phdr PT_LOAD;
28 iram0_2_phdr PT_LOAD;
29 iram0_3_phdr PT_LOAD;
30 iram0_4_phdr PT_LOAD;
31 iram0_5_phdr PT_LOAD;
32 iram0_6_phdr PT_LOAD;
33 iram0_7_phdr PT_LOAD;
34 iram0_8_phdr PT_LOAD;
35}
36
37
38/* Default entry point: */
39ENTRY(_ResetVector)
40
41
42/* Memory boundary addresses: */
43_memmap_mem_sram_start = 0x0;
44_memmap_mem_sram_end = 0x480000;
45_memmap_mem_dram0_start = 0x24000000;
46_memmap_mem_dram0_end = 0x24010000;
47_memmap_mem_iram0_start = 0x24020000;
48_memmap_mem_iram0_end = 0x24030000;
49_memmap_mem_sram_uncached_start = 0x20000000;
50_memmap_mem_sram_uncached_end = 0x20480000;
51
52/* Memory segment boundary addresses: */
53_memmap_seg_dsp_core_start = 0x300000;
54_memmap_seg_dsp_core_max = 0x480000;
55_memmap_seg_dsp_uncached_start = 0x20040000;
56_memmap_seg_dsp_uncached_max = 0x20080000;
57_memmap_seg_dram0_0_start = 0x24000000;
58_memmap_seg_dram0_0_max = 0x24010000;
59_memmap_seg_iram0_0_start = 0x24020000;
60_memmap_seg_iram0_0_max = 0x24020400;
61_memmap_seg_iram0_1_start = 0x24020400;
62_memmap_seg_iram0_1_max = 0x2402057c;
63_memmap_seg_iram0_2_start = 0x2402057c;
64_memmap_seg_iram0_2_max = 0x2402059c;
65_memmap_seg_iram0_3_start = 0x2402059c;
66_memmap_seg_iram0_3_max = 0x240205bc;
67_memmap_seg_iram0_4_start = 0x240205bc;
68_memmap_seg_iram0_4_max = 0x240205dc;
69_memmap_seg_iram0_5_start = 0x240205dc;
70_memmap_seg_iram0_5_max = 0x240205fc;
71_memmap_seg_iram0_6_start = 0x240205fc;
72_memmap_seg_iram0_6_max = 0x2402061c;
73_memmap_seg_iram0_7_start = 0x2402061c;
74_memmap_seg_iram0_7_max = 0x2402063c;
75_memmap_seg_iram0_8_start = 0x2402063c;
76_memmap_seg_iram0_8_max = 0x24030000;
77
78_rom_store_table = 0;
79PROVIDE(_memmap_reset_vector = 0x24020000);
80PROVIDE(_memmap_vecbase_reset = 0x24020400);
81/* Various memory-map dependent cache attribute settings: */
82_memmap_cacheattr_wb_base = 0x00000044;
83_memmap_cacheattr_wt_base = 0x00000011;
84_memmap_cacheattr_bp_base = 0x00000022;
85_memmap_cacheattr_unused_mask = 0xFFFFFF00;
86_memmap_cacheattr_wb_trapnull = 0x22222244;
87_memmap_cacheattr_wba_trapnull = 0x22222244;
88_memmap_cacheattr_wbna_trapnull = 0x22222255;
89_memmap_cacheattr_wt_trapnull = 0x22222211;
90_memmap_cacheattr_bp_trapnull = 0x22222222;
91_memmap_cacheattr_wb_strict = 0xFFFFFF44;
92_memmap_cacheattr_wt_strict = 0xFFFFFF11;
93_memmap_cacheattr_bp_strict = 0xFFFFFF22;
94_memmap_cacheattr_wb_allvalid = 0x22222244;
95_memmap_cacheattr_wt_allvalid = 0x22222211;
96_memmap_cacheattr_bp_allvalid = 0x22222222;
97_memmap_region_map = 0x00000003;
98PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
99
100SECTIONS
101{
102
103 NonCacheable.init : ALIGN(4)
104 {
105 NonCacheable_init_start = ABSOLUTE(.);
106 *(NonCacheable.init)
107 . = ALIGN (4);
108 NonCacheable_init_end = ABSOLUTE(.);
109 } >dsp_uncached_seg :dsp_uncached_phdr
110
111 NonCacheable : ALIGN(4)
112 {
113 NonCacheable_start = ABSOLUTE(.);
114 *(NonCacheable)
115 . = ALIGN (4);
116 NonCacheable_end = ABSOLUTE(.);
117 _memmap_seg_dsp_uncached_end = ALIGN(0x8);
118 } >dsp_uncached_seg :dsp_uncached_phdr
119
120
121 .dram0.rodata : ALIGN(4)
122 {
123 _dram0_rodata_start = ABSOLUTE(.);
124 *(.dram0.rodata)
125 *(.dram.rodata)
126 . = ALIGN (4);
127 _dram0_rodata_end = ABSOLUTE(.);
128 } >dram0_0_seg :dram0_0_phdr
129
130 .ResetVector.literal : ALIGN(4)
131 {
132 _ResetVector_literal_start = ABSOLUTE(.);
133 *(.ResetVector.literal)
134 . = ALIGN (4);
135 _ResetVector_literal_end = ABSOLUTE(.);
136 } >dram0_0_seg :dram0_0_phdr
137
138 .Level2InterruptVector.literal : ALIGN(4)
139 {
140 _Level2InterruptVector_literal_start = ABSOLUTE(.);
141 *(.Level2InterruptVector.literal)
142 . = ALIGN (4);
143 _Level2InterruptVector_literal_end = ABSOLUTE(.);
144 } >dram0_0_seg :dram0_0_phdr
145
146 .Level3InterruptVector.literal : ALIGN(4)
147 {
148 _Level3InterruptVector_literal_start = ABSOLUTE(.);
149 *(.Level3InterruptVector.literal)
150 . = ALIGN (4);
151 _Level3InterruptVector_literal_end = ABSOLUTE(.);
152 } >dram0_0_seg :dram0_0_phdr
153
154 .DebugExceptionVector.literal : ALIGN(4)
155 {
156 _DebugExceptionVector_literal_start = ABSOLUTE(.);
157 *(.DebugExceptionVector.literal)
158 . = ALIGN (4);
159 _DebugExceptionVector_literal_end = ABSOLUTE(.);
160 } >dram0_0_seg :dram0_0_phdr
161
162 .NMIExceptionVector.literal : ALIGN(4)
163 {
164 _NMIExceptionVector_literal_start = ABSOLUTE(.);
165 *(.NMIExceptionVector.literal)
166 . = ALIGN (4);
167 _NMIExceptionVector_literal_end = ABSOLUTE(.);
168 } >dram0_0_seg :dram0_0_phdr
169
170 .KernelExceptionVector.literal : ALIGN(4)
171 {
172 _KernelExceptionVector_literal_start = ABSOLUTE(.);
173 *(.KernelExceptionVector.literal)
174 . = ALIGN (4);
175 _KernelExceptionVector_literal_end = ABSOLUTE(.);
176 } >dram0_0_seg :dram0_0_phdr
177
178 .UserExceptionVector.literal : ALIGN(4)
179 {
180 _UserExceptionVector_literal_start = ABSOLUTE(.);
181 *(.UserExceptionVector.literal)
182 . = ALIGN (4);
183 _UserExceptionVector_literal_end = ABSOLUTE(.);
184 } >dram0_0_seg :dram0_0_phdr
185
186 .DoubleExceptionVector.literal : ALIGN(4)
187 {
188 _DoubleExceptionVector_literal_start = ABSOLUTE(.);
189 *(.DoubleExceptionVector.literal)
190 . = ALIGN (4);
191 _DoubleExceptionVector_literal_end = ABSOLUTE(.);
192 } >dram0_0_seg :dram0_0_phdr
193
194 .iram0.literal : ALIGN(4)
195 {
196 _iram0_literal_start = ABSOLUTE(.);
197 *(.iram0.literal)
198 *(.iram.literal)
199 *(.iram.text.literal)
200 . = ALIGN (4);
201 _iram0_literal_end = ABSOLUTE(.);
202 } >dram0_0_seg :dram0_0_phdr
203
204 .dram0.data : ALIGN(4)
205 {
206 _dram0_data_start = ABSOLUTE(.);
207 *(.dram0.data)
208 *(.dram.data)
209 . = ALIGN (4);
210 _dram0_data_end = ABSOLUTE(.);
211 } >dram0_0_seg :dram0_0_phdr
212
213 .dram0.bss (NOLOAD) : ALIGN(8)
214 {
215 . = ALIGN (8);
216 _dram0_bss_start = ABSOLUTE(.);
217 *(.dram0.bss)
218 . = ALIGN (8);
219 _dram0_bss_end = ABSOLUTE(.);
220 _memmap_seg_dram0_0_end = ALIGN(0x8);
221 } >dram0_0_seg :dram0_0_bss_phdr
222
223
224 .ResetVector.text : ALIGN(4)
225 {
226 _ResetVector_text_start = ABSOLUTE(.);
227 KEEP (*(.ResetVector.text))
228 . = ALIGN (4);
229 _ResetVector_text_end = ABSOLUTE(.);
230 } >iram0_0_seg :iram0_0_phdr
231
232 .ResetHandler.text : ALIGN(4)
233 {
234 _ResetHandler_text_start = ABSOLUTE(.);
235 *(.ResetHandler.literal .ResetHandler.text)
236 . = ALIGN (4);
237 _ResetHandler_text_end = ABSOLUTE(.);
238 _memmap_seg_iram0_0_end = ALIGN(0x8);
239 } >iram0_0_seg :iram0_0_phdr
240
241
242 .WindowVectors.text : ALIGN(4)
243 {
244 _WindowVectors_text_start = ABSOLUTE(.);
245 KEEP (*(.WindowVectors.text))
246 . = ALIGN (4);
247 _WindowVectors_text_end = ABSOLUTE(.);
248 _memmap_seg_iram0_1_end = ALIGN(0x8);
249 } >iram0_1_seg :iram0_1_phdr
250
251
252 .Level2InterruptVector.text : ALIGN(4)
253 {
254 _Level2InterruptVector_text_start = ABSOLUTE(.);
255 KEEP (*(.Level2InterruptVector.text))
256 . = ALIGN (4);
257 _Level2InterruptVector_text_end = ABSOLUTE(.);
258 _memmap_seg_iram0_2_end = ALIGN(0x8);
259 } >iram0_2_seg :iram0_2_phdr
260
261
262 .Level3InterruptVector.text : ALIGN(4)
263 {
264 _Level3InterruptVector_text_start = ABSOLUTE(.);
265 KEEP (*(.Level3InterruptVector.text))
266 . = ALIGN (4);
267 _Level3InterruptVector_text_end = ABSOLUTE(.);
268 _memmap_seg_iram0_3_end = ALIGN(0x8);
269 } >iram0_3_seg :iram0_3_phdr
270
271
272 .DebugExceptionVector.text : ALIGN(4)
273 {
274 _DebugExceptionVector_text_start = ABSOLUTE(.);
275 KEEP (*(.DebugExceptionVector.text))
276 . = ALIGN (4);
277 _DebugExceptionVector_text_end = ABSOLUTE(.);
278 _memmap_seg_iram0_4_end = ALIGN(0x8);
279 } >iram0_4_seg :iram0_4_phdr
280
281
282 .NMIExceptionVector.text : ALIGN(4)
283 {
284 _NMIExceptionVector_text_start = ABSOLUTE(.);
285 KEEP (*(.NMIExceptionVector.text))
286 . = ALIGN (4);
287 _NMIExceptionVector_text_end = ABSOLUTE(.);
288 _memmap_seg_iram0_5_end = ALIGN(0x8);
289 } >iram0_5_seg :iram0_5_phdr
290
291
292 .KernelExceptionVector.text : ALIGN(4)
293 {
294 _KernelExceptionVector_text_start = ABSOLUTE(.);
295 KEEP (*(.KernelExceptionVector.text))
296 . = ALIGN (4);
297 _KernelExceptionVector_text_end = ABSOLUTE(.);
298 _memmap_seg_iram0_6_end = ALIGN(0x8);
299 } >iram0_6_seg :iram0_6_phdr
300
301
302 .UserExceptionVector.text : ALIGN(4)
303 {
304 _UserExceptionVector_text_start = ABSOLUTE(.);
305 KEEP (*(.UserExceptionVector.text))
306 . = ALIGN (4);
307 _UserExceptionVector_text_end = ABSOLUTE(.);
308 _memmap_seg_iram0_7_end = ALIGN(0x8);
309 } >iram0_7_seg :iram0_7_phdr
310
311
312 .DoubleExceptionVector.text : ALIGN(4)
313 {
314 _DoubleExceptionVector_text_start = ABSOLUTE(.);
315 KEEP (*(.DoubleExceptionVector.text))
316 . = ALIGN (4);
317 _DoubleExceptionVector_text_end = ABSOLUTE(.);
318 } >iram0_8_seg :iram0_8_phdr
319
320 .iram0.text : ALIGN(4)
321 {
322 _iram0_text_start = ABSOLUTE(.);
323 *(.iram0.text)
324 *(.iram.text)
325 . = ALIGN (4);
326 _iram0_text_end = ABSOLUTE(.);
327 _memmap_seg_iram0_8_end = ALIGN(0x8);
328 } >iram0_8_seg :iram0_8_phdr
329
330
331 .sram.rodata : ALIGN(4)
332 {
333 _sram_rodata_start = ABSOLUTE(.);
334 *(.sram.rodata)
335 . = ALIGN (4);
336 _sram_rodata_end = ABSOLUTE(.);
337 } >dsp_core_seg :dsp_core_phdr
338
339 .clib.rodata : ALIGN(4)
340 {
341 _clib_rodata_start = ABSOLUTE(.);
342 *(.clib.rodata)
343 . = ALIGN (4);
344 _clib_rodata_end = ABSOLUTE(.);
345 } >dsp_core_seg :dsp_core_phdr
346
347 .rtos.rodata : ALIGN(4)
348 {
349 _rtos_rodata_start = ABSOLUTE(.);
350 *(.rtos.rodata)
351 . = ALIGN (4);
352 _rtos_rodata_end = ABSOLUTE(.);
353 } >dsp_core_seg :dsp_core_phdr
354
355 .rodata : ALIGN(4)
356 {
357 _rodata_start = ABSOLUTE(.);
358 *(.rodata)
359 *(SORT(.rodata.sort.*))
360 KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
361 *(.rodata.*)
362 *(.gnu.linkonce.r.*)
363 *(.rodata1)
364 __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
365 KEEP (*(.xt_except_table))
366 KEEP (*(.gcc_except_table))
367 *(.gnu.linkonce.e.*)
368 *(.gnu.version_r)
369 KEEP (*(.eh_frame))
370 /* C++ constructor and destructor tables, properly ordered: */
371 KEEP (*crtbegin.o(.ctors))
372 KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
373 KEEP (*(SORT(.ctors.*)))
374 KEEP (*(.ctors))
375 KEEP (*crtbegin.o(.dtors))
376 KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
377 KEEP (*(SORT(.dtors.*)))
378 KEEP (*(.dtors))
379 /* C++ exception handlers table: */
380 __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
381 *(.xt_except_desc)
382 *(.gnu.linkonce.h.*)
383 __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
384 *(.xt_except_desc_end)
385 *(.dynamic)
386 *(.gnu.version_d)
387 . = ALIGN(4); /* this table MUST be 4-byte aligned */
388 _bss_table_start = ABSOLUTE(.);
389 LONG(_dram0_bss_start)
390 LONG(_dram0_bss_end)
391 LONG(_bss_start)
392 LONG(_bss_end)
393 _bss_table_end = ABSOLUTE(.);
394 . = ALIGN (4);
395 _rodata_end = ABSOLUTE(.);
396 } >dsp_core_seg :dsp_core_phdr
397
398 .sram.text : ALIGN(4)
399 {
400 _sram_text_start = ABSOLUTE(.);
401 *(.sram.literal .sram.text)
402 . = ALIGN (4);
403 _sram_text_end = ABSOLUTE(.);
404 } >dsp_core_seg :dsp_core_phdr
405
406 .text : ALIGN(4)
407 {
408 _stext = .;
409 _text_start = ABSOLUTE(.);
410 *(.entry.text)
411 *(.init.literal)
412 KEEP(*(.init))
413 *(.literal.sort.* SORT(.text.sort.*))
414 KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
415 *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
416 *(.fini.literal)
417 KEEP(*(.fini))
418 *(.gnu.version)
419 . = ALIGN (4);
420 _text_end = ABSOLUTE(.);
421 _etext = .;
422 } >dsp_core_seg :dsp_core_phdr
423
424 .clib.text : ALIGN(4)
425 {
426 _clib_text_start = ABSOLUTE(.);
427 *(.clib.literal .clib.text)
428 . = ALIGN (4);
429 _clib_text_end = ABSOLUTE(.);
430 } >dsp_core_seg :dsp_core_phdr
431
432 .rtos.text : ALIGN(4)
433 {
434 _rtos_text_start = ABSOLUTE(.);
435 *(.rtos.literal .rtos.text)
436 . = ALIGN (4);
437 _rtos_text_end = ABSOLUTE(.);
438 } >dsp_core_seg :dsp_core_phdr
439
440 .clib.data : ALIGN(4)
441 {
442 _clib_data_start = ABSOLUTE(.);
443 *(.clib.data)
444 . = ALIGN (4);
445 _clib_data_end = ABSOLUTE(.);
446 } >dsp_core_seg :dsp_core_phdr
447
448 .clib.percpu.data : ALIGN(4)
449 {
450 _clib_percpu_data_start = ABSOLUTE(.);
451 *(.clib.percpu.data)
452 . = ALIGN (4);
453 _clib_percpu_data_end = ABSOLUTE(.);
454 } >dsp_core_seg :dsp_core_phdr
455
456 .rtos.percpu.data : ALIGN(4)
457 {
458 _rtos_percpu_data_start = ABSOLUTE(.);
459 *(.rtos.percpu.data)
460 . = ALIGN (4);
461 _rtos_percpu_data_end = ABSOLUTE(.);
462 } >dsp_core_seg :dsp_core_phdr
463
464 .rtos.data : ALIGN(4)
465 {
466 _rtos_data_start = ABSOLUTE(.);
467 *(.rtos.data)
468 . = ALIGN (4);
469 _rtos_data_end = ABSOLUTE(.);
470 } >dsp_core_seg :dsp_core_phdr
471
472 .sram.data : ALIGN(4)
473 {
474 _sram_data_start = ABSOLUTE(.);
475 *(.sram.data)
476 . = ALIGN (4);
477 _sram_data_end = ABSOLUTE(.);
478 } >dsp_core_seg :dsp_core_phdr
479
480 .data : ALIGN(4)
481 {
482 _data_start = ABSOLUTE(.);
483 *(.data)
484 *(SORT(.data.sort.*))
485 KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
486 *(.data.*)
487 *(.gnu.linkonce.d.*)
488 KEEP(*(.gnu.linkonce.d.*personality*))
489 *(.data1)
490 *(.sdata)
491 *(.sdata.*)
492 *(.gnu.linkonce.s.*)
493 *(.sdata2)
494 *(.sdata2.*)
495 *(.gnu.linkonce.s2.*)
496 KEEP(*(.jcr))
497 *(__llvm_prf_cnts)
498 *(__llvm_prf_data)
499 *(__llvm_prf_vnds)
500 . = ALIGN (4);
501 _data_end = ABSOLUTE(.);
502 } >dsp_core_seg :dsp_core_phdr
503
504 __llvm_prf_names : ALIGN(4)
505 {
506 __llvm_prf_names_start = ABSOLUTE(.);
507 *(__llvm_prf_names)
508 . = ALIGN (4);
509 __llvm_prf_names_end = ABSOLUTE(.);
510 } >dsp_core_seg :dsp_core_phdr
511
512 .bss (NOLOAD) : ALIGN(8)
513 {
514 . = ALIGN (8);
515 _bss_start = ABSOLUTE(.);
516 *(.dynsbss)
517 *(.sbss)
518 *(.sbss.*)
519 *(.gnu.linkonce.sb.*)
520 *(.scommon)
521 *(.sbss2)
522 *(.sbss2.*)
523 *(.gnu.linkonce.sb2.*)
524 *(.dynbss)
525 *(.bss)
526 *(SORT(.bss.sort.*))
527 KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
528 *(.bss.*)
529 *(.gnu.linkonce.b.*)
530 *(COMMON)
531 *(.clib.bss)
532 *(.clib.percpu.bss)
533 *(.rtos.percpu.bss)
534 *(.rtos.bss)
535 *(.sram.bss)
536 . = ALIGN (8);
537 _bss_end = ABSOLUTE(.);
538 _end = ALIGN(0x8);
539 PROVIDE(end = ALIGN(0x8));
540 _stack_sentry = ALIGN(0x8);
541 _memmap_seg_dsp_core_end = ALIGN(0x8);
542 } >dsp_core_seg :dsp_core_bss_phdr
543
544 PROVIDE(__stack = 0x480000);
545 _heap_sentry = 0x480000;
546 .debug 0 : { *(.debug) }
547 .line 0 : { *(.line) }
548 .debug_srcinfo 0 : { *(.debug_srcinfo) }
549 .debug_sfnames 0 : { *(.debug_sfnames) }
550 .debug_aranges 0 : { *(.debug_aranges) }
551 .debug_pubnames 0 : { *(.debug_pubnames) }
552 .debug_info 0 : { *(.debug_info) }
553 .debug_abbrev 0 : { *(.debug_abbrev) }
554 .debug_line 0 : { *(.debug_line) }
555 .debug_frame 0 : { *(.debug_frame) }
556 .debug_str 0 : { *(.debug_str) }
557 .debug_loc 0 : { *(.debug_loc) }
558 .debug_macinfo 0 : { *(.debug_macinfo) }
559 .debug_weaknames 0 : { *(.debug_weaknames) }
560 .debug_funcnames 0 : { *(.debug_funcnames) }
561 .debug_typenames 0 : { *(.debug_typenames) }
562 .debug_varnames 0 : { *(.debug_varnames) }
563 .xt.insn 0 :
564 {
565 KEEP (*(.xt.insn))
566 KEEP (*(.gnu.linkonce.x.*))
567 }
568 .xt.prop 0 :
569 {
570 KEEP (*(.xt.prop))
571 KEEP (*(.xt.prop.*))
572 KEEP (*(.gnu.linkonce.prop.*))
573 }
574 .xt.lit 0 :
575 {
576 KEEP (*(.xt.lit))
577 KEEP (*(.xt.lit.*))
578 KEEP (*(.gnu.linkonce.p.*))
579 }
580 .debug.xt.callgraph 0 :
581 {
582 KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
583 }
584}
585
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xn b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xn
new file mode 100644
index 000000000..a38f1aeb6
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xn
@@ -0,0 +1,585 @@
1/* This linker script generated from xt-genldscripts.tpp for LSP C:/usr/xtensa/Xplorer-8.0.10-workspaces/XtensaInfo/Models/nxp_rt600_lowmem_memmap/sim */
2/* Linker Script for ld -n */
3MEMORY
4{
5 dsp_core_seg : org = 0x00300000, len = 0x180000
6 dsp_uncached_seg : org = 0x20040000, len = 0x40000
7 dram0_0_seg : org = 0x24000000, len = 0x10000
8 iram0_0_seg : org = 0x24020000, len = 0x400
9 iram0_1_seg : org = 0x24020400, len = 0x17C
10 iram0_2_seg : org = 0x2402057C, len = 0x20
11 iram0_3_seg : org = 0x2402059C, len = 0x20
12 iram0_4_seg : org = 0x240205BC, len = 0x20
13 iram0_5_seg : org = 0x240205DC, len = 0x20
14 iram0_6_seg : org = 0x240205FC, len = 0x20
15 iram0_7_seg : org = 0x2402061C, len = 0x20
16 iram0_8_seg : org = 0x2402063C, len = 0xF9C4
17}
18
19PHDRS
20{
21 dsp_core_phdr PT_LOAD;
22 dsp_core_bss_phdr PT_LOAD;
23 dsp_uncached_phdr PT_LOAD;
24 dram0_0_phdr PT_LOAD;
25 dram0_0_bss_phdr PT_LOAD;
26 iram0_0_phdr PT_LOAD;
27 iram0_1_phdr PT_LOAD;
28 iram0_2_phdr PT_LOAD;
29 iram0_3_phdr PT_LOAD;
30 iram0_4_phdr PT_LOAD;
31 iram0_5_phdr PT_LOAD;
32 iram0_6_phdr PT_LOAD;
33 iram0_7_phdr PT_LOAD;
34 iram0_8_phdr PT_LOAD;
35}
36
37
38/* Default entry point: */
39ENTRY(_ResetVector)
40
41
42/* Memory boundary addresses: */
43_memmap_mem_sram_start = 0x0;
44_memmap_mem_sram_end = 0x480000;
45_memmap_mem_dram0_start = 0x24000000;
46_memmap_mem_dram0_end = 0x24010000;
47_memmap_mem_iram0_start = 0x24020000;
48_memmap_mem_iram0_end = 0x24030000;
49_memmap_mem_sram_uncached_start = 0x20000000;
50_memmap_mem_sram_uncached_end = 0x20480000;
51
52/* Memory segment boundary addresses: */
53_memmap_seg_dsp_core_start = 0x300000;
54_memmap_seg_dsp_core_max = 0x480000;
55_memmap_seg_dsp_uncached_start = 0x20040000;
56_memmap_seg_dsp_uncached_max = 0x20080000;
57_memmap_seg_dram0_0_start = 0x24000000;
58_memmap_seg_dram0_0_max = 0x24010000;
59_memmap_seg_iram0_0_start = 0x24020000;
60_memmap_seg_iram0_0_max = 0x24020400;
61_memmap_seg_iram0_1_start = 0x24020400;
62_memmap_seg_iram0_1_max = 0x2402057c;
63_memmap_seg_iram0_2_start = 0x2402057c;
64_memmap_seg_iram0_2_max = 0x2402059c;
65_memmap_seg_iram0_3_start = 0x2402059c;
66_memmap_seg_iram0_3_max = 0x240205bc;
67_memmap_seg_iram0_4_start = 0x240205bc;
68_memmap_seg_iram0_4_max = 0x240205dc;
69_memmap_seg_iram0_5_start = 0x240205dc;
70_memmap_seg_iram0_5_max = 0x240205fc;
71_memmap_seg_iram0_6_start = 0x240205fc;
72_memmap_seg_iram0_6_max = 0x2402061c;
73_memmap_seg_iram0_7_start = 0x2402061c;
74_memmap_seg_iram0_7_max = 0x2402063c;
75_memmap_seg_iram0_8_start = 0x2402063c;
76_memmap_seg_iram0_8_max = 0x24030000;
77
78_rom_store_table = 0;
79PROVIDE(_memmap_reset_vector = 0x24020000);
80PROVIDE(_memmap_vecbase_reset = 0x24020400);
81/* Various memory-map dependent cache attribute settings: */
82_memmap_cacheattr_wb_base = 0x00000044;
83_memmap_cacheattr_wt_base = 0x00000011;
84_memmap_cacheattr_bp_base = 0x00000022;
85_memmap_cacheattr_unused_mask = 0xFFFFFF00;
86_memmap_cacheattr_wb_trapnull = 0x22222244;
87_memmap_cacheattr_wba_trapnull = 0x22222244;
88_memmap_cacheattr_wbna_trapnull = 0x22222255;
89_memmap_cacheattr_wt_trapnull = 0x22222211;
90_memmap_cacheattr_bp_trapnull = 0x22222222;
91_memmap_cacheattr_wb_strict = 0xFFFFFF44;
92_memmap_cacheattr_wt_strict = 0xFFFFFF11;
93_memmap_cacheattr_bp_strict = 0xFFFFFF22;
94_memmap_cacheattr_wb_allvalid = 0x22222244;
95_memmap_cacheattr_wt_allvalid = 0x22222211;
96_memmap_cacheattr_bp_allvalid = 0x22222222;
97_memmap_region_map = 0x00000003;
98PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
99
100SECTIONS
101{
102
103 NonCacheable.init : ALIGN(4)
104 {
105 NonCacheable_init_start = ABSOLUTE(.);
106 *(NonCacheable.init)
107 . = ALIGN (4);
108 NonCacheable_init_end = ABSOLUTE(.);
109 } >dsp_uncached_seg :dsp_uncached_phdr
110
111 NonCacheable : ALIGN(4)
112 {
113 NonCacheable_start = ABSOLUTE(.);
114 *(NonCacheable)
115 . = ALIGN (4);
116 NonCacheable_end = ABSOLUTE(.);
117 _memmap_seg_dsp_uncached_end = ALIGN(0x8);
118 } >dsp_uncached_seg :dsp_uncached_phdr
119
120
121 .dram0.rodata : ALIGN(4)
122 {
123 _dram0_rodata_start = ABSOLUTE(.);
124 *(.dram0.rodata)
125 *(.dram.rodata)
126 . = ALIGN (4);
127 _dram0_rodata_end = ABSOLUTE(.);
128 } >dram0_0_seg :dram0_0_phdr
129
130 .ResetVector.literal : ALIGN(4)
131 {
132 _ResetVector_literal_start = ABSOLUTE(.);
133 *(.ResetVector.literal)
134 . = ALIGN (4);
135 _ResetVector_literal_end = ABSOLUTE(.);
136 } >dram0_0_seg :dram0_0_phdr
137
138 .Level2InterruptVector.literal : ALIGN(4)
139 {
140 _Level2InterruptVector_literal_start = ABSOLUTE(.);
141 *(.Level2InterruptVector.literal)
142 . = ALIGN (4);
143 _Level2InterruptVector_literal_end = ABSOLUTE(.);
144 } >dram0_0_seg :dram0_0_phdr
145
146 .Level3InterruptVector.literal : ALIGN(4)
147 {
148 _Level3InterruptVector_literal_start = ABSOLUTE(.);
149 *(.Level3InterruptVector.literal)
150 . = ALIGN (4);
151 _Level3InterruptVector_literal_end = ABSOLUTE(.);
152 } >dram0_0_seg :dram0_0_phdr
153
154 .DebugExceptionVector.literal : ALIGN(4)
155 {
156 _DebugExceptionVector_literal_start = ABSOLUTE(.);
157 *(.DebugExceptionVector.literal)
158 . = ALIGN (4);
159 _DebugExceptionVector_literal_end = ABSOLUTE(.);
160 } >dram0_0_seg :dram0_0_phdr
161
162 .NMIExceptionVector.literal : ALIGN(4)
163 {
164 _NMIExceptionVector_literal_start = ABSOLUTE(.);
165 *(.NMIExceptionVector.literal)
166 . = ALIGN (4);
167 _NMIExceptionVector_literal_end = ABSOLUTE(.);
168 } >dram0_0_seg :dram0_0_phdr
169
170 .KernelExceptionVector.literal : ALIGN(4)
171 {
172 _KernelExceptionVector_literal_start = ABSOLUTE(.);
173 *(.KernelExceptionVector.literal)
174 . = ALIGN (4);
175 _KernelExceptionVector_literal_end = ABSOLUTE(.);
176 } >dram0_0_seg :dram0_0_phdr
177
178 .UserExceptionVector.literal : ALIGN(4)
179 {
180 _UserExceptionVector_literal_start = ABSOLUTE(.);
181 *(.UserExceptionVector.literal)
182 . = ALIGN (4);
183 _UserExceptionVector_literal_end = ABSOLUTE(.);
184 } >dram0_0_seg :dram0_0_phdr
185
186 .DoubleExceptionVector.literal : ALIGN(4)
187 {
188 _DoubleExceptionVector_literal_start = ABSOLUTE(.);
189 *(.DoubleExceptionVector.literal)
190 . = ALIGN (4);
191 _DoubleExceptionVector_literal_end = ABSOLUTE(.);
192 } >dram0_0_seg :dram0_0_phdr
193
194 .iram0.literal : ALIGN(4)
195 {
196 _iram0_literal_start = ABSOLUTE(.);
197 *(.iram0.literal)
198 *(.iram.literal)
199 *(.iram.text.literal)
200 . = ALIGN (4);
201 _iram0_literal_end = ABSOLUTE(.);
202 } >dram0_0_seg :dram0_0_phdr
203
204 .dram0.data : ALIGN(4)
205 {
206 _dram0_data_start = ABSOLUTE(.);
207 *(.dram0.data)
208 *(.dram.data)
209 . = ALIGN (4);
210 _dram0_data_end = ABSOLUTE(.);
211 } >dram0_0_seg :dram0_0_phdr
212
213 .dram0.bss (NOLOAD) : ALIGN(8)
214 {
215 . = ALIGN (8);
216 _dram0_bss_start = ABSOLUTE(.);
217 *(.dram0.bss)
218 . = ALIGN (8);
219 _dram0_bss_end = ABSOLUTE(.);
220 _memmap_seg_dram0_0_end = ALIGN(0x8);
221 } >dram0_0_seg :dram0_0_bss_phdr
222
223
224 .ResetVector.text : ALIGN(4)
225 {
226 _ResetVector_text_start = ABSOLUTE(.);
227 KEEP (*(.ResetVector.text))
228 . = ALIGN (4);
229 _ResetVector_text_end = ABSOLUTE(.);
230 } >iram0_0_seg :iram0_0_phdr
231
232 .ResetHandler.text : ALIGN(4)
233 {
234 _ResetHandler_text_start = ABSOLUTE(.);
235 *(.ResetHandler.literal .ResetHandler.text)
236 . = ALIGN (4);
237 _ResetHandler_text_end = ABSOLUTE(.);
238 _memmap_seg_iram0_0_end = ALIGN(0x8);
239 } >iram0_0_seg :iram0_0_phdr
240
241
242 .WindowVectors.text : ALIGN(4)
243 {
244 _WindowVectors_text_start = ABSOLUTE(.);
245 KEEP (*(.WindowVectors.text))
246 . = ALIGN (4);
247 _WindowVectors_text_end = ABSOLUTE(.);
248 _memmap_seg_iram0_1_end = ALIGN(0x8);
249 } >iram0_1_seg :iram0_1_phdr
250
251
252 .Level2InterruptVector.text : ALIGN(4)
253 {
254 _Level2InterruptVector_text_start = ABSOLUTE(.);
255 KEEP (*(.Level2InterruptVector.text))
256 . = ALIGN (4);
257 _Level2InterruptVector_text_end = ABSOLUTE(.);
258 _memmap_seg_iram0_2_end = ALIGN(0x8);
259 } >iram0_2_seg :iram0_2_phdr
260
261
262 .Level3InterruptVector.text : ALIGN(4)
263 {
264 _Level3InterruptVector_text_start = ABSOLUTE(.);
265 KEEP (*(.Level3InterruptVector.text))
266 . = ALIGN (4);
267 _Level3InterruptVector_text_end = ABSOLUTE(.);
268 _memmap_seg_iram0_3_end = ALIGN(0x8);
269 } >iram0_3_seg :iram0_3_phdr
270
271
272 .DebugExceptionVector.text : ALIGN(4)
273 {
274 _DebugExceptionVector_text_start = ABSOLUTE(.);
275 KEEP (*(.DebugExceptionVector.text))
276 . = ALIGN (4);
277 _DebugExceptionVector_text_end = ABSOLUTE(.);
278 _memmap_seg_iram0_4_end = ALIGN(0x8);
279 } >iram0_4_seg :iram0_4_phdr
280
281
282 .NMIExceptionVector.text : ALIGN(4)
283 {
284 _NMIExceptionVector_text_start = ABSOLUTE(.);
285 KEEP (*(.NMIExceptionVector.text))
286 . = ALIGN (4);
287 _NMIExceptionVector_text_end = ABSOLUTE(.);
288 _memmap_seg_iram0_5_end = ALIGN(0x8);
289 } >iram0_5_seg :iram0_5_phdr
290
291
292 .KernelExceptionVector.text : ALIGN(4)
293 {
294 _KernelExceptionVector_text_start = ABSOLUTE(.);
295 KEEP (*(.KernelExceptionVector.text))
296 . = ALIGN (4);
297 _KernelExceptionVector_text_end = ABSOLUTE(.);
298 _memmap_seg_iram0_6_end = ALIGN(0x8);
299 } >iram0_6_seg :iram0_6_phdr
300
301
302 .UserExceptionVector.text : ALIGN(4)
303 {
304 _UserExceptionVector_text_start = ABSOLUTE(.);
305 KEEP (*(.UserExceptionVector.text))
306 . = ALIGN (4);
307 _UserExceptionVector_text_end = ABSOLUTE(.);
308 _memmap_seg_iram0_7_end = ALIGN(0x8);
309 } >iram0_7_seg :iram0_7_phdr
310
311
312 .DoubleExceptionVector.text : ALIGN(4)
313 {
314 _DoubleExceptionVector_text_start = ABSOLUTE(.);
315 KEEP (*(.DoubleExceptionVector.text))
316 . = ALIGN (4);
317 _DoubleExceptionVector_text_end = ABSOLUTE(.);
318 } >iram0_8_seg :iram0_8_phdr
319
320 .iram0.text : ALIGN(4)
321 {
322 _iram0_text_start = ABSOLUTE(.);
323 *(.iram0.text)
324 *(.iram.text)
325 . = ALIGN (4);
326 _iram0_text_end = ABSOLUTE(.);
327 _memmap_seg_iram0_8_end = ALIGN(0x8);
328 } >iram0_8_seg :iram0_8_phdr
329
330
331 .sram.rodata : ALIGN(4)
332 {
333 _sram_rodata_start = ABSOLUTE(.);
334 *(.sram.rodata)
335 . = ALIGN (4);
336 _sram_rodata_end = ABSOLUTE(.);
337 } >dsp_core_seg :dsp_core_phdr
338
339 .clib.rodata : ALIGN(4)
340 {
341 _clib_rodata_start = ABSOLUTE(.);
342 *(.clib.rodata)
343 . = ALIGN (4);
344 _clib_rodata_end = ABSOLUTE(.);
345 } >dsp_core_seg :dsp_core_phdr
346
347 .rtos.rodata : ALIGN(4)
348 {
349 _rtos_rodata_start = ABSOLUTE(.);
350 *(.rtos.rodata)
351 . = ALIGN (4);
352 _rtos_rodata_end = ABSOLUTE(.);
353 } >dsp_core_seg :dsp_core_phdr
354
355 .rodata : ALIGN(4)
356 {
357 _rodata_start = ABSOLUTE(.);
358 *(.rodata)
359 *(SORT(.rodata.sort.*))
360 KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
361 *(.rodata.*)
362 *(.gnu.linkonce.r.*)
363 *(.rodata1)
364 __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
365 KEEP (*(.xt_except_table))
366 KEEP (*(.gcc_except_table))
367 *(.gnu.linkonce.e.*)
368 *(.gnu.version_r)
369 KEEP (*(.eh_frame))
370 /* C++ constructor and destructor tables, properly ordered: */
371 KEEP (*crtbegin.o(.ctors))
372 KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
373 KEEP (*(SORT(.ctors.*)))
374 KEEP (*(.ctors))
375 KEEP (*crtbegin.o(.dtors))
376 KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
377 KEEP (*(SORT(.dtors.*)))
378 KEEP (*(.dtors))
379 /* C++ exception handlers table: */
380 __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
381 *(.xt_except_desc)
382 *(.gnu.linkonce.h.*)
383 __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
384 *(.xt_except_desc_end)
385 *(.dynamic)
386 *(.gnu.version_d)
387 . = ALIGN(4); /* this table MUST be 4-byte aligned */
388 _bss_table_start = ABSOLUTE(.);
389 LONG(_dram0_bss_start)
390 LONG(_dram0_bss_end)
391 LONG(_bss_start)
392 LONG(_bss_end)
393 _bss_table_end = ABSOLUTE(.);
394 . = ALIGN (4);
395 _rodata_end = ABSOLUTE(.);
396 } >dsp_core_seg :dsp_core_phdr
397
398 .sram.text : ALIGN(4)
399 {
400 _sram_text_start = ABSOLUTE(.);
401 *(.sram.literal .sram.text)
402 . = ALIGN (4);
403 _sram_text_end = ABSOLUTE(.);
404 } >dsp_core_seg :dsp_core_phdr
405
406 .text : ALIGN(4)
407 {
408 _stext = .;
409 _text_start = ABSOLUTE(.);
410 *(.entry.text)
411 *(.init.literal)
412 KEEP(*(.init))
413 *(.literal.sort.* SORT(.text.sort.*))
414 KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
415 *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
416 *(.fini.literal)
417 KEEP(*(.fini))
418 *(.gnu.version)
419 . = ALIGN (4);
420 _text_end = ABSOLUTE(.);
421 _etext = .;
422 } >dsp_core_seg :dsp_core_phdr
423
424 .clib.text : ALIGN(4)
425 {
426 _clib_text_start = ABSOLUTE(.);
427 *(.clib.literal .clib.text)
428 . = ALIGN (4);
429 _clib_text_end = ABSOLUTE(.);
430 } >dsp_core_seg :dsp_core_phdr
431
432 .rtos.text : ALIGN(4)
433 {
434 _rtos_text_start = ABSOLUTE(.);
435 *(.rtos.literal .rtos.text)
436 . = ALIGN (4);
437 _rtos_text_end = ABSOLUTE(.);
438 } >dsp_core_seg :dsp_core_phdr
439
440 .clib.data : ALIGN(4)
441 {
442 _clib_data_start = ABSOLUTE(.);
443 *(.clib.data)
444 . = ALIGN (4);
445 _clib_data_end = ABSOLUTE(.);
446 } >dsp_core_seg :dsp_core_phdr
447
448 .clib.percpu.data : ALIGN(4)
449 {
450 _clib_percpu_data_start = ABSOLUTE(.);
451 *(.clib.percpu.data)
452 . = ALIGN (4);
453 _clib_percpu_data_end = ABSOLUTE(.);
454 } >dsp_core_seg :dsp_core_phdr
455
456 .rtos.percpu.data : ALIGN(4)
457 {
458 _rtos_percpu_data_start = ABSOLUTE(.);
459 *(.rtos.percpu.data)
460 . = ALIGN (4);
461 _rtos_percpu_data_end = ABSOLUTE(.);
462 } >dsp_core_seg :dsp_core_phdr
463
464 .rtos.data : ALIGN(4)
465 {
466 _rtos_data_start = ABSOLUTE(.);
467 *(.rtos.data)
468 . = ALIGN (4);
469 _rtos_data_end = ABSOLUTE(.);
470 } >dsp_core_seg :dsp_core_phdr
471
472 .sram.data : ALIGN(4)
473 {
474 _sram_data_start = ABSOLUTE(.);
475 *(.sram.data)
476 . = ALIGN (4);
477 _sram_data_end = ABSOLUTE(.);
478 } >dsp_core_seg :dsp_core_phdr
479
480 .data : ALIGN(4)
481 {
482 _data_start = ABSOLUTE(.);
483 *(.data)
484 *(SORT(.data.sort.*))
485 KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
486 *(.data.*)
487 *(.gnu.linkonce.d.*)
488 KEEP(*(.gnu.linkonce.d.*personality*))
489 *(.data1)
490 *(.sdata)
491 *(.sdata.*)
492 *(.gnu.linkonce.s.*)
493 *(.sdata2)
494 *(.sdata2.*)
495 *(.gnu.linkonce.s2.*)
496 KEEP(*(.jcr))
497 *(__llvm_prf_cnts)
498 *(__llvm_prf_data)
499 *(__llvm_prf_vnds)
500 . = ALIGN (4);
501 _data_end = ABSOLUTE(.);
502 } >dsp_core_seg :dsp_core_phdr
503
504 __llvm_prf_names : ALIGN(4)
505 {
506 __llvm_prf_names_start = ABSOLUTE(.);
507 *(__llvm_prf_names)
508 . = ALIGN (4);
509 __llvm_prf_names_end = ABSOLUTE(.);
510 } >dsp_core_seg :dsp_core_phdr
511
512 .bss (NOLOAD) : ALIGN(8)
513 {
514 . = ALIGN (8);
515 _bss_start = ABSOLUTE(.);
516 *(.dynsbss)
517 *(.sbss)
518 *(.sbss.*)
519 *(.gnu.linkonce.sb.*)
520 *(.scommon)
521 *(.sbss2)
522 *(.sbss2.*)
523 *(.gnu.linkonce.sb2.*)
524 *(.dynbss)
525 *(.bss)
526 *(SORT(.bss.sort.*))
527 KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
528 *(.bss.*)
529 *(.gnu.linkonce.b.*)
530 *(COMMON)
531 *(.clib.bss)
532 *(.clib.percpu.bss)
533 *(.rtos.percpu.bss)
534 *(.rtos.bss)
535 *(.sram.bss)
536 . = ALIGN (8);
537 _bss_end = ABSOLUTE(.);
538 _end = ALIGN(0x8);
539 PROVIDE(end = ALIGN(0x8));
540 _stack_sentry = ALIGN(0x8);
541 _memmap_seg_dsp_core_end = ALIGN(0x8);
542 } >dsp_core_seg :dsp_core_bss_phdr
543
544 PROVIDE(__stack = 0x480000);
545 _heap_sentry = 0x480000;
546 .debug 0 : { *(.debug) }
547 .line 0 : { *(.line) }
548 .debug_srcinfo 0 : { *(.debug_srcinfo) }
549 .debug_sfnames 0 : { *(.debug_sfnames) }
550 .debug_aranges 0 : { *(.debug_aranges) }
551 .debug_pubnames 0 : { *(.debug_pubnames) }
552 .debug_info 0 : { *(.debug_info) }
553 .debug_abbrev 0 : { *(.debug_abbrev) }
554 .debug_line 0 : { *(.debug_line) }
555 .debug_frame 0 : { *(.debug_frame) }
556 .debug_str 0 : { *(.debug_str) }
557 .debug_loc 0 : { *(.debug_loc) }
558 .debug_macinfo 0 : { *(.debug_macinfo) }
559 .debug_weaknames 0 : { *(.debug_weaknames) }
560 .debug_funcnames 0 : { *(.debug_funcnames) }
561 .debug_typenames 0 : { *(.debug_typenames) }
562 .debug_varnames 0 : { *(.debug_varnames) }
563 .xt.insn 0 :
564 {
565 KEEP (*(.xt.insn))
566 KEEP (*(.gnu.linkonce.x.*))
567 }
568 .xt.prop 0 :
569 {
570 KEEP (*(.xt.prop))
571 KEEP (*(.xt.prop.*))
572 KEEP (*(.gnu.linkonce.prop.*))
573 }
574 .xt.lit 0 :
575 {
576 KEEP (*(.xt.lit))
577 KEEP (*(.xt.lit.*))
578 KEEP (*(.gnu.linkonce.p.*))
579 }
580 .debug.xt.callgraph 0 :
581 {
582 KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
583 }
584}
585
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xr b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xr
new file mode 100644
index 000000000..b710852b8
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xr
@@ -0,0 +1,61 @@
1/* This linker script generated from xt-genldscripts.tpp for LSP C:/usr/xtensa/Xplorer-8.0.10-workspaces/XtensaInfo/Models/nxp_rt600_lowmem_memmap/sim */
2/* Linker Script for ld -r or ld -i */
3
4
5SECTIONS
6{
7
8 .text 0 :
9 {
10 *(.literal .text)
11 }
12
13 .bss 0 :
14 {
15 *(.dynsbss)
16 *(.sbss)
17 *(.scommon)
18 *(.dynbss)
19 *(.bss)
20 *(COMMON)
21 }
22 .debug 0 : { *(.debug) }
23 .line 0 : { *(.line) }
24 .debug_srcinfo 0 : { *(.debug_srcinfo) }
25 .debug_sfnames 0 : { *(.debug_sfnames) }
26 .debug_aranges 0 : { *(.debug_aranges) }
27 .debug_pubnames 0 : { *(.debug_pubnames) }
28 .debug_info 0 : { *(.debug_info) }
29 .debug_abbrev 0 : { *(.debug_abbrev) }
30 .debug_line 0 : { *(.debug_line) }
31 .debug_frame 0 : { *(.debug_frame) }
32 .debug_str 0 : { *(.debug_str) }
33 .debug_loc 0 : { *(.debug_loc) }
34 .debug_macinfo 0 : { *(.debug_macinfo) }
35 .debug_weaknames 0 : { *(.debug_weaknames) }
36 .debug_funcnames 0 : { *(.debug_funcnames) }
37 .debug_typenames 0 : { *(.debug_typenames) }
38 .debug_varnames 0 : { *(.debug_varnames) }
39 .xt.insn 0 :
40 {
41 KEEP (*(.xt.insn))
42 KEEP (*(.gnu.linkonce.x.*))
43 }
44 .xt.prop 0 :
45 {
46 KEEP (*(.xt.prop))
47 KEEP (*(.xt.prop.*))
48 KEEP (*(.gnu.linkonce.prop.*))
49 }
50 .xt.lit 0 :
51 {
52 KEEP (*(.xt.lit))
53 KEEP (*(.xt.lit.*))
54 KEEP (*(.gnu.linkonce.p.*))
55 }
56 .debug.xt.callgraph 0 :
57 {
58 KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
59 }
60}
61
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xu b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xu
new file mode 100644
index 000000000..9899e54d9
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/ldscripts/elf32xtensa.xu
@@ -0,0 +1,61 @@
1/* This linker script generated from xt-genldscripts.tpp for LSP C:/usr/xtensa/Xplorer-8.0.10-workspaces/XtensaInfo/Models/nxp_rt600_lowmem_memmap/sim */
2/* Linker Script for ld -Ur */
3
4
5SECTIONS
6{
7
8 .text 0 :
9 {
10 *(.literal .text)
11 }
12
13 .bss 0 :
14 {
15 *(.dynsbss)
16 *(.sbss)
17 *(.scommon)
18 *(.dynbss)
19 *(.bss)
20 *(COMMON)
21 }
22 .debug 0 : { *(.debug) }
23 .line 0 : { *(.line) }
24 .debug_srcinfo 0 : { *(.debug_srcinfo) }
25 .debug_sfnames 0 : { *(.debug_sfnames) }
26 .debug_aranges 0 : { *(.debug_aranges) }
27 .debug_pubnames 0 : { *(.debug_pubnames) }
28 .debug_info 0 : { *(.debug_info) }
29 .debug_abbrev 0 : { *(.debug_abbrev) }
30 .debug_line 0 : { *(.debug_line) }
31 .debug_frame 0 : { *(.debug_frame) }
32 .debug_str 0 : { *(.debug_str) }
33 .debug_loc 0 : { *(.debug_loc) }
34 .debug_macinfo 0 : { *(.debug_macinfo) }
35 .debug_weaknames 0 : { *(.debug_weaknames) }
36 .debug_funcnames 0 : { *(.debug_funcnames) }
37 .debug_typenames 0 : { *(.debug_typenames) }
38 .debug_varnames 0 : { *(.debug_varnames) }
39 .xt.insn 0 :
40 {
41 KEEP (*(.xt.insn))
42 KEEP (*(.gnu.linkonce.x.*))
43 }
44 .xt.prop 0 :
45 {
46 KEEP (*(.xt.prop))
47 KEEP (*(.xt.prop.*))
48 KEEP (*(.gnu.linkonce.prop.*))
49 }
50 .xt.lit 0 :
51 {
52 KEEP (*(.xt.lit))
53 KEEP (*(.xt.lit.*))
54 KEEP (*(.gnu.linkonce.p.*))
55 }
56 .debug.xt.callgraph 0 :
57 {
58 KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
59 }
60}
61
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/memmap.xmm b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/memmap.xmm
new file mode 100644
index 000000000..a21c5be30
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/memmap.xmm
@@ -0,0 +1,78 @@
1// Memory map file to generate linker scripts for programs run on the ISS.
2
3// Customer ID=13270; Build=0x802a5; Copyright (c) 2004-2015 Cadence Design Systems, Inc.
4//
5// Permission is hereby granted, free of charge, to any person obtaining
6// a copy of this software and associated documentation files (the
7// "Software"), to deal in the Software without restriction, including
8// without limitation the rights to use, copy, modify, merge, publish,
9// distribute, sublicense, and/or sell copies of the Software, and to
10// permit persons to whom the Software is furnished to do so, subject to
11// the following conditions:
12//
13// The above copyright notice and this permission notice shall be included
14// in all copies or substantial portions of the Software.
15//
16// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
20// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23
24
25// A memory map is a sequence of memory descriptions and
26// optional parameter assignments.
27//
28// Each memory description has the following format:
29// BEGIN <name>
30// <addr> [,<paddr>] : <mem-type> : <mem-name> : <size> [,<psize>]
31// : [writable] [,executable] [,device] ;
32// <segment>*
33// END <name>
34//
35// where each <segment> description has the following format:
36// <seg-name> : F|C : <start-addr> - <end-addr> [ : STACK ] [ : HEAP ]
37// : <section-name>* ;
38//
39// Each parameter assignment is a keyword/value pair in the following format:
40// <keyword> = <value> (no spaces in <value>)
41// or
42// <keyword> = "<value>" (spaces allowed in <value>)
43//
44// The following primitives are also defined:
45// PLACE SECTIONS( <section-name>* ) { WITH_SECTION(<section-name>)
46// | IN_SEGMENT(<seg-name>) }
47//
48// NOLOAD <section-name1> [ <section-name2> ... ]
49//
50// Please refer to the Xtensa LSP Reference Manual for more details.
51//
52
53BEGIN sram
540x0: sysram : sram : 0x480000 : executable, writable ;
55 dsp_core : C : 0x300000 - 0x47ffff : STACK : HEAP : .sram.rodata .clib.rodata .rtos.rodata .rodata .sram.literal .literal .rtos.literal .clib.literal .sram.text .text .clib.text .rtos.text .clib.data .clib.percpu.data .rtos.percpu.data .rtos.data .sram.data .data __llvm_prf_names .clib.bss .clib.percpu.bss .rtos.percpu.bss .rtos.bss .sram.bss .bss;
56END sram
57
58BEGIN dram0
590x24000000: dataRam : dram0 : 0x10000 : writable ;
60 dram0_0 : C : 0x24000000 - 0x2400ffff : .dram0.rodata .ResetVector.literal .Level2InterruptVector.literal .Level3InterruptVector.literal .DebugExceptionVector.literal .NMIExceptionVector.literal .KernelExceptionVector.literal .UserExceptionVector.literal .DoubleExceptionVector.literal .iram0.literal .dram0.data .dram0.bss;
61END dram0
62
63BEGIN iram0
640x24020000: instRam : iram0 : 0x10000 : executable, writable ;
65 iram0_0 : F : 0x24020000 - 0x240203ff : .ResetVector.text .ResetHandler.literal .ResetHandler.text;
66 iram0_1 : F : 0x24020400 - 0x2402057b : .WindowVectors.text;
67 iram0_2 : F : 0x2402057c - 0x2402059b : .Level2InterruptVector.text;
68 iram0_3 : F : 0x2402059c - 0x240205bb : .Level3InterruptVector.text;
69 iram0_4 : F : 0x240205bc - 0x240205db : .DebugExceptionVector.text;
70 iram0_5 : F : 0x240205dc - 0x240205fb : .NMIExceptionVector.text;
71 iram0_6 : F : 0x240205fc - 0x2402061b : .KernelExceptionVector.text;
72 iram0_7 : F : 0x2402061c - 0x2402063b : .UserExceptionVector.text;
73 iram0_8 : F : 0x2402063c - 0x2402ffff : .DoubleExceptionVector.text .iram0.text;
74END iram0
75BEGIN sram_uncached
760x20000000: sysram : sram_uncached : 0x480000 : writable ;
77 dsp_uncached : C : 0x20040000 - 0x2007ffff : NonCacheable.init NonCacheable;
78END sram_uncached \ No newline at end of file
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/specs b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/specs
new file mode 100644
index 000000000..0547d65a3
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MIMXRT685S/xtensa_lowmem/sim/specs
@@ -0,0 +1,36 @@
1# Customer ID=13270; Build=0x802a5; Copyright (c) 2004-2015 Cadence Design Systems, Inc.
2#
3# Permission is hereby granted, free of charge, to any person obtaining
4# a copy of this software and associated documentation files (the
5# "Software"), to deal in the Software without restriction, including
6# without limitation the rights to use, copy, modify, merge, publish,
7# distribute, sublicense, and/or sell copies of the Software, and to
8# permit persons to whom the Software is furnished to do so, subject to
9# the following conditions:
10#
11# The above copyright notice and this permission notice shall be included
12# in all copies or substantial portions of the Software.
13#
14# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
15# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
16# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
17# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
18# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
19# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
20# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
21
22
23# The %O suffix on the start and end files indicates that the system's
24# standard suffix for object files (e.g., ".o") should be appended.
25# The %s suffix tells the compiler driver to search for the file in the
26# list of known locations for startfiles.
27
28*startfile:
29crt1-sim%O%s crti%O%s crtbegin%O%s _sharedvectors%O%s _vectors%O%s
30
31*endfile:
32crtend%O%s crtn%O%s
33
34*lib:
35-lc -lsim -lc -lhandler-reset -lhandlers-sim -lhal -lc
36
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 19:17:59 +0100