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1/*
2** ###################################################################
3** Processors: MK02FN128VFM10
4** MK02FN128VLF10
5** MK02FN128VLH10
6** MK02FN64VFM10
7** MK02FN64VLF10
8** MK02FN64VLH10
9**
10** Compilers: Keil ARM C/C++ Compiler
11** Freescale C/C++ for Embedded ARM
12** GNU C Compiler
13** IAR ANSI C/C++ Compiler for ARM
14** MCUXpresso Compiler
15**
16** Reference manual: K02P64M100SFARM, Rev. 0, February 14, 2014
17** Version: rev. 0.5, 2015-02-19
18** Build: b180801
19**
20** Abstract:
21** CMSIS Peripheral Access Layer for MK02F12810
22**
23** Copyright 1997-2016 Freescale Semiconductor, Inc.
24** Copyright 2016-2018 NXP
25**
26** SPDX-License-Identifier: BSD-3-Clause
27**
28** http: www.nxp.com
29** mail: [email protected]
30**
31** Revisions:
32** - rev. 0.1 (2014-02-24)
33** Initial version
34** - rev. 0.2 (2014-07-15)
35** Module access macro module_BASES replaced by module_BASE_PTRS.
36** Update of system and startup files.
37** - rev. 0.3 (2014-08-28)
38** Update of system files - default clock configuration changed.
39** Update of startup files - possibility to override DefaultISR added.
40** - rev. 0.4 (2014-10-14)
41** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
42** - rev. 0.5 (2015-02-19)
43** Renamed interrupt vector LLW to LLWU.
44**
45** ###################################################################
46*/
47
48/*!
49 * @file MK02F12810.h
50 * @version 0.5
51 * @date 2015-02-19
52 * @brief CMSIS Peripheral Access Layer for MK02F12810
53 *
54 * CMSIS Peripheral Access Layer for MK02F12810
55 */
56
57#ifndef _MK02F12810_H_
58#define _MK02F12810_H_ /**< Symbol preventing repeated inclusion */
59
60/** Memory map major version (memory maps with equal major version number are
61 * compatible) */
62#define MCU_MEM_MAP_VERSION 0x0000U
63/** Memory map minor version */
64#define MCU_MEM_MAP_VERSION_MINOR 0x0005U
65
66/**
67 * @brief Macro to calculate address of an aliased word in the peripheral
68 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
69 * 0x400FFFFF).
70 * @param Reg Register to access.
71 * @param Bit Bit number to access.
72 * @return Address of the aliased word in the peripheral bitband area.
73 */
74#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
75/**
76 * @brief Macro to access a single bit of a peripheral register (bit band region
77 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
78 * be used for peripherals with 32bit access allowed.
79 * @param Reg Register to access.
80 * @param Bit Bit number to access.
81 * @return Value of the targeted bit in the bit band region.
82 */
83#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
84#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
85/**
86 * @brief Macro to access a single bit of a peripheral register (bit band region
87 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
88 * be used for peripherals with 16bit access allowed.
89 * @param Reg Register to access.
90 * @param Bit Bit number to access.
91 * @return Value of the targeted bit in the bit band region.
92 */
93#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
94/**
95 * @brief Macro to access a single bit of a peripheral register (bit band region
96 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
97 * be used for peripherals with 8bit access allowed.
98 * @param Reg Register to access.
99 * @param Bit Bit number to access.
100 * @return Value of the targeted bit in the bit band region.
101 */
102#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
103
104/* ----------------------------------------------------------------------------
105 -- Interrupt vector numbers
106 ---------------------------------------------------------------------------- */
107
108/*!
109 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
110 * @{
111 */
112
113/** Interrupt Number Definitions */
114#define NUMBER_OF_INT_VECTORS 90 /**< Number of interrupts in the Vector table */
115
116typedef enum IRQn {
117 /* Auxiliary constants */
118 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
119
120 /* Core interrupts */
121 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
122 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
123 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
124 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
125 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
126 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
127 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
128 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
129 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
130
131 /* Device specific interrupts */
132 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
133 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
134 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
135 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
136 Reserved20_IRQn = 4, /**< Reserved interrupt 20 */
137 Reserved21_IRQn = 5, /**< Reserved interrupt 21 */
138 Reserved22_IRQn = 6, /**< Reserved interrupt 22 */
139 Reserved23_IRQn = 7, /**< Reserved interrupt 23 */
140 Reserved24_IRQn = 8, /**< Reserved interrupt 24 */
141 Reserved25_IRQn = 9, /**< Reserved interrupt 25 */
142 Reserved26_IRQn = 10, /**< Reserved interrupt 26 */
143 Reserved27_IRQn = 11, /**< Reserved interrupt 27 */
144 Reserved28_IRQn = 12, /**< Reserved interrupt 28 */
145 Reserved29_IRQn = 13, /**< Reserved interrupt 29 */
146 Reserved30_IRQn = 14, /**< Reserved interrupt 30 */
147 Reserved31_IRQn = 15, /**< Reserved interrupt 31 */
148 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
149 MCM_IRQn = 17, /**< Normal Interrupt */
150 FTF_IRQn = 18, /**< FTFA Command complete interrupt */
151 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
152 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
153 LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */
154 WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */
155 Reserved39_IRQn = 23, /**< Reserved Interrupt 39 */
156 I2C0_IRQn = 24, /**< I2C0 interrupt */
157 Reserved41_IRQn = 25, /**< Reserved Interrupt 41 */
158 SPI0_IRQn = 26, /**< SPI0 Interrupt */
159 Reserved43_IRQn = 27, /**< Reserved Interrupt 43 */
160 Reserved44_IRQn = 28, /**< Reserved Interrupt 44 */
161 Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
162 Reserved46_IRQn = 30, /**< Reserved interrupt 46 */
163 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
164 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
165 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
166 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
167 Reserved51_IRQn = 35, /**< Reserved interrupt 51 */
168 Reserved52_IRQn = 36, /**< Reserved interrupt 52 */
169 Reserved53_IRQn = 37, /**< Reserved interrupt 53 */
170 Reserved54_IRQn = 38, /**< Reserved interrupt 54 */
171 ADC0_IRQn = 39, /**< ADC0 interrupt */
172 CMP0_IRQn = 40, /**< CMP0 interrupt */
173 CMP1_IRQn = 41, /**< CMP1 interrupt */
174 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
175 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
176 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
177 Reserved61_IRQn = 45, /**< Reserved interrupt 61 */
178 Reserved62_IRQn = 46, /**< Reserved interrupt 62 */
179 Reserved63_IRQn = 47, /**< Reserved interrupt 63 */
180 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
181 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
182 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
183 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
184 PDB0_IRQn = 52, /**< PDB0 Interrupt */
185 Reserved69_IRQn = 53, /**< Reserved interrupt 69 */
186 Reserved70_IRQn = 54, /**< Reserved interrupt 70 */
187 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
188 DAC0_IRQn = 56, /**< DAC0 interrupt */
189 MCG_IRQn = 57, /**< MCG Interrupt */
190 LPTMR0_IRQn = 58, /**< LPTimer interrupt */
191 PORTA_IRQn = 59, /**< Port A interrupt */
192 PORTB_IRQn = 60, /**< Port B interrupt */
193 PORTC_IRQn = 61, /**< Port C interrupt */
194 PORTD_IRQn = 62, /**< Port D interrupt */
195 PORTE_IRQn = 63, /**< Port E interrupt */
196 SWI_IRQn = 64, /**< Software interrupt */
197 Reserved81_IRQn = 65, /**< Reserved interrupt 81 */
198 Reserved82_IRQn = 66, /**< Reserved interrupt 82 */
199 Reserved83_IRQn = 67, /**< Reserved interrupt 83 */
200 Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
201 Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
202 Reserved86_IRQn = 70, /**< Reserved interrupt 86 */
203 Reserved87_IRQn = 71, /**< Reserved interrupt 87 */
204 Reserved88_IRQn = 72, /**< Reserved interrupt 88 */
205 Reserved89_IRQn = 73 /**< Reserved interrupt 89 */
206} IRQn_Type;
207
208/*!
209 * @}
210 */ /* end of group Interrupt_vector_numbers */
211
212
213/* ----------------------------------------------------------------------------
214 -- Cortex M4 Core Configuration
215 ---------------------------------------------------------------------------- */
216
217/*!
218 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
219 * @{
220 */
221
222#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
223#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
224#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
225#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
226
227#include "core_cm4.h" /* Core Peripheral Access Layer */
228#include "system_MK02F12810.h" /* Device specific configuration file */
229
230/*!
231 * @}
232 */ /* end of group Cortex_Core_Configuration */
233
234
235/* ----------------------------------------------------------------------------
236 -- Mapping Information
237 ---------------------------------------------------------------------------- */
238
239/*!
240 * @addtogroup Mapping_Information Mapping Information
241 * @{
242 */
243
244/** Mapping Information */
245/*!
246 * @addtogroup edma_request
247 * @{
248 */
249
250/*******************************************************************************
251 * Definitions
252 ******************************************************************************/
253
254/*!
255 * @brief Structure for the DMA hardware request
256 *
257 * Defines the structure for the DMA hardware request collections. The user can configure the
258 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
259 * of the hardware request varies according to the to SoC.
260 */
261typedef enum _dma_request_source
262{
263 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
264 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
265 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
266 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
267 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
268 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
269 kDmaRequestMux0Reserved6 = 6|0x100U, /**< Reserved6 */
270 kDmaRequestMux0Reserved7 = 7|0x100U, /**< Reserved7 */
271 kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */
272 kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */
273 kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */
274 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
275 kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */
276 kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */
277 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
278 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
279 kDmaRequestMux0Reserved16 = 16|0x100U, /**< Reserved16 */
280 kDmaRequestMux0Reserved17 = 17|0x100U, /**< Reserved17 */
281 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */
282 kDmaRequestMux0Reserved19 = 19|0x100U, /**< Reserved19 */
283 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
284 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
285 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
286 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
287 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
288 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
289 kDmaRequestMux0Reserved26 = 26|0x100U, /**< Reserved26 */
290 kDmaRequestMux0Reserved27 = 27|0x100U, /**< Reserved27 */
291 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
292 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
293 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
294 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
295 kDmaRequestMux0Reserved32 = 32|0x100U, /**< Reserved32 */
296 kDmaRequestMux0Reserved33 = 33|0x100U, /**< Reserved33 */
297 kDmaRequestMux0Reserved34 = 34|0x100U, /**< Reserved34 */
298 kDmaRequestMux0Reserved35 = 35|0x100U, /**< Reserved35 */
299 kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */
300 kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */
301 kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */
302 kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */
303 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
304 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */
305 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
306 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
307 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
308 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
309 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
310 kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */
311 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
312 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
313 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
314 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
315 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
316 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
317 kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */
318 kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */
319 kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */
320 kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
321 kDmaRequestMux0Reserved58 = 58|0x100U, /**< Reserved58 */
322 kDmaRequestMux0Reserved59 = 59|0x100U, /**< Reserved59 */
323 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
324 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
325 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
326 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
327} dma_request_source_t;
328
329/* @} */
330
331
332/*!
333 * @}
334 */ /* end of group Mapping_Information */
335
336
337/* ----------------------------------------------------------------------------
338 -- Device Peripheral Access Layer
339 ---------------------------------------------------------------------------- */
340
341/*!
342 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
343 * @{
344 */
345
346
347/*
348** Start of section using anonymous unions
349*/
350
351#if defined(__ARMCC_VERSION)
352 #if (__ARMCC_VERSION >= 6010050)
353 #pragma clang diagnostic push
354 #else
355 #pragma push
356 #pragma anon_unions
357 #endif
358#elif defined(__CWCC__)
359 #pragma push
360 #pragma cpp_extensions on
361#elif defined(__GNUC__)
362 /* anonymous unions are enabled by default */
363#elif defined(__IAR_SYSTEMS_ICC__)
364 #pragma language=extended
365#else
366 #error Not supported compiler type
367#endif
368
369/* ----------------------------------------------------------------------------
370 -- ADC Peripheral Access Layer
371 ---------------------------------------------------------------------------- */
372
373/*!
374 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
375 * @{
376 */
377
378/** ADC - Register Layout Typedef */
379typedef struct {
380 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
381 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
382 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
383 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
384 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
385 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
386 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
387 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
388 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
389 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
390 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
391 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
392 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
393 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
394 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
395 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
396 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
397 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
398 uint8_t RESERVED_0[4];
399 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
400 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
401 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
402 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
403 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
404 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
405 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
406} ADC_Type;
407
408/* ----------------------------------------------------------------------------
409 -- ADC Register Masks
410 ---------------------------------------------------------------------------- */
411
412/*!
413 * @addtogroup ADC_Register_Masks ADC Register Masks
414 * @{
415 */
416
417/*! @name SC1 - ADC Status and Control Registers 1 */
418/*! @{ */
419#define ADC_SC1_ADCH_MASK (0x1FU)
420#define ADC_SC1_ADCH_SHIFT (0U)
421/*! ADCH - Input channel select
422 * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
423 * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
424 * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
425 * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
426 * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
427 * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
428 * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
429 * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
430 * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
431 * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
432 * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
433 * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
434 * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
435 * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
436 * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
437 * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
438 * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
439 * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
440 * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
441 * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
442 * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
443 * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
444 * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
445 * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
446 * 0b11000..Reserved.
447 * 0b11001..Reserved.
448 * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
449 * 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
450 * 0b11100..Reserved.
451 * 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
452 * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
453 * 0b11111..Module is disabled.
454 */
455#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
456#define ADC_SC1_DIFF_MASK (0x20U)
457#define ADC_SC1_DIFF_SHIFT (5U)
458/*! DIFF - Differential Mode Enable
459 * 0b0..Single-ended conversions and input channels are selected.
460 * 0b1..Differential conversions and input channels are selected.
461 */
462#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
463#define ADC_SC1_AIEN_MASK (0x40U)
464#define ADC_SC1_AIEN_SHIFT (6U)
465/*! AIEN - Interrupt Enable
466 * 0b0..Conversion complete interrupt is disabled.
467 * 0b1..Conversion complete interrupt is enabled.
468 */
469#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
470#define ADC_SC1_COCO_MASK (0x80U)
471#define ADC_SC1_COCO_SHIFT (7U)
472/*! COCO - Conversion Complete Flag
473 * 0b0..Conversion is not completed.
474 * 0b1..Conversion is completed.
475 */
476#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
477/*! @} */
478
479/* The count of ADC_SC1 */
480#define ADC_SC1_COUNT (2U)
481
482/*! @name CFG1 - ADC Configuration Register 1 */
483/*! @{ */
484#define ADC_CFG1_ADICLK_MASK (0x3U)
485#define ADC_CFG1_ADICLK_SHIFT (0U)
486/*! ADICLK - Input Clock Select
487 * 0b00..Bus clock
488 * 0b01..Alternate clock 2 (ALTCLK2)
489 * 0b10..Alternate clock (ALTCLK)
490 * 0b11..Asynchronous clock (ADACK)
491 */
492#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
493#define ADC_CFG1_MODE_MASK (0xCU)
494#define ADC_CFG1_MODE_SHIFT (2U)
495/*! MODE - Conversion mode selection
496 * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
497 * 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
498 * 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
499 * 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
500 */
501#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
502#define ADC_CFG1_ADLSMP_MASK (0x10U)
503#define ADC_CFG1_ADLSMP_SHIFT (4U)
504/*! ADLSMP - Sample Time Configuration
505 * 0b0..Short sample time.
506 * 0b1..Long sample time.
507 */
508#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
509#define ADC_CFG1_ADIV_MASK (0x60U)
510#define ADC_CFG1_ADIV_SHIFT (5U)
511/*! ADIV - Clock Divide Select
512 * 0b00..The divide ratio is 1 and the clock rate is input clock.
513 * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2.
514 * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4.
515 * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.
516 */
517#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
518#define ADC_CFG1_ADLPC_MASK (0x80U)
519#define ADC_CFG1_ADLPC_SHIFT (7U)
520/*! ADLPC - Low-Power Configuration
521 * 0b0..Normal power configuration.
522 * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.
523 */
524#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
525/*! @} */
526
527/*! @name CFG2 - ADC Configuration Register 2 */
528/*! @{ */
529#define ADC_CFG2_ADLSTS_MASK (0x3U)
530#define ADC_CFG2_ADLSTS_SHIFT (0U)
531/*! ADLSTS - Long Sample Time Select
532 * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
533 * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time.
534 * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time.
535 * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.
536 */
537#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
538#define ADC_CFG2_ADHSC_MASK (0x4U)
539#define ADC_CFG2_ADHSC_SHIFT (2U)
540/*! ADHSC - High-Speed Configuration
541 * 0b0..Normal conversion sequence selected.
542 * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
543 */
544#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
545#define ADC_CFG2_ADACKEN_MASK (0x8U)
546#define ADC_CFG2_ADACKEN_SHIFT (3U)
547/*! ADACKEN - Asynchronous Clock Output Enable
548 * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
549 * 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.
550 */
551#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
552#define ADC_CFG2_MUXSEL_MASK (0x10U)
553#define ADC_CFG2_MUXSEL_SHIFT (4U)
554/*! MUXSEL - ADC Mux Select
555 * 0b0..ADxxa channels are selected.
556 * 0b1..ADxxb channels are selected.
557 */
558#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
559/*! @} */
560
561/*! @name R - ADC Data Result Register */
562/*! @{ */
563#define ADC_R_D_MASK (0xFFFFU)
564#define ADC_R_D_SHIFT (0U)
565#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
566/*! @} */
567
568/* The count of ADC_R */
569#define ADC_R_COUNT (2U)
570
571/*! @name CV1 - Compare Value Registers */
572/*! @{ */
573#define ADC_CV1_CV_MASK (0xFFFFU)
574#define ADC_CV1_CV_SHIFT (0U)
575#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
576/*! @} */
577
578/*! @name CV2 - Compare Value Registers */
579/*! @{ */
580#define ADC_CV2_CV_MASK (0xFFFFU)
581#define ADC_CV2_CV_SHIFT (0U)
582#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
583/*! @} */
584
585/*! @name SC2 - Status and Control Register 2 */
586/*! @{ */
587#define ADC_SC2_REFSEL_MASK (0x3U)
588#define ADC_SC2_REFSEL_SHIFT (0U)
589/*! REFSEL - Voltage Reference Selection
590 * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL
591 * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
592 * 0b10..Reserved
593 * 0b11..Reserved
594 */
595#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
596#define ADC_SC2_DMAEN_MASK (0x4U)
597#define ADC_SC2_DMAEN_SHIFT (2U)
598/*! DMAEN - DMA Enable
599 * 0b0..DMA is disabled.
600 * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
601 */
602#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
603#define ADC_SC2_ACREN_MASK (0x8U)
604#define ADC_SC2_ACREN_SHIFT (3U)
605/*! ACREN - Compare Function Range Enable
606 * 0b0..Range function disabled. Only CV1 is compared.
607 * 0b1..Range function enabled. Both CV1 and CV2 are compared.
608 */
609#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
610#define ADC_SC2_ACFGT_MASK (0x10U)
611#define ADC_SC2_ACFGT_SHIFT (4U)
612/*! ACFGT - Compare Function Greater Than Enable
613 * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
614 * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
615 */
616#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
617#define ADC_SC2_ACFE_MASK (0x20U)
618#define ADC_SC2_ACFE_SHIFT (5U)
619/*! ACFE - Compare Function Enable
620 * 0b0..Compare function disabled.
621 * 0b1..Compare function enabled.
622 */
623#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
624#define ADC_SC2_ADTRG_MASK (0x40U)
625#define ADC_SC2_ADTRG_SHIFT (6U)
626/*! ADTRG - Conversion Trigger Select
627 * 0b0..Software trigger selected.
628 * 0b1..Hardware trigger selected.
629 */
630#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
631#define ADC_SC2_ADACT_MASK (0x80U)
632#define ADC_SC2_ADACT_SHIFT (7U)
633/*! ADACT - Conversion Active
634 * 0b0..Conversion not in progress.
635 * 0b1..Conversion in progress.
636 */
637#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
638/*! @} */
639
640/*! @name SC3 - Status and Control Register 3 */
641/*! @{ */
642#define ADC_SC3_AVGS_MASK (0x3U)
643#define ADC_SC3_AVGS_SHIFT (0U)
644/*! AVGS - Hardware Average Select
645 * 0b00..4 samples averaged.
646 * 0b01..8 samples averaged.
647 * 0b10..16 samples averaged.
648 * 0b11..32 samples averaged.
649 */
650#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
651#define ADC_SC3_AVGE_MASK (0x4U)
652#define ADC_SC3_AVGE_SHIFT (2U)
653/*! AVGE - Hardware Average Enable
654 * 0b0..Hardware average function disabled.
655 * 0b1..Hardware average function enabled.
656 */
657#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
658#define ADC_SC3_ADCO_MASK (0x8U)
659#define ADC_SC3_ADCO_SHIFT (3U)
660/*! ADCO - Continuous Conversion Enable
661 * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
662 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
663 */
664#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
665#define ADC_SC3_CALF_MASK (0x40U)
666#define ADC_SC3_CALF_SHIFT (6U)
667/*! CALF - Calibration Failed Flag
668 * 0b0..Calibration completed normally.
669 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
670 */
671#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
672#define ADC_SC3_CAL_MASK (0x80U)
673#define ADC_SC3_CAL_SHIFT (7U)
674#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
675/*! @} */
676
677/*! @name OFS - ADC Offset Correction Register */
678/*! @{ */
679#define ADC_OFS_OFS_MASK (0xFFFFU)
680#define ADC_OFS_OFS_SHIFT (0U)
681#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
682/*! @} */
683
684/*! @name PG - ADC Plus-Side Gain Register */
685/*! @{ */
686#define ADC_PG_PG_MASK (0xFFFFU)
687#define ADC_PG_PG_SHIFT (0U)
688#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
689/*! @} */
690
691/*! @name MG - ADC Minus-Side Gain Register */
692/*! @{ */
693#define ADC_MG_MG_MASK (0xFFFFU)
694#define ADC_MG_MG_SHIFT (0U)
695#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
696/*! @} */
697
698/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
699/*! @{ */
700#define ADC_CLPD_CLPD_MASK (0x3FU)
701#define ADC_CLPD_CLPD_SHIFT (0U)
702#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
703/*! @} */
704
705/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
706/*! @{ */
707#define ADC_CLPS_CLPS_MASK (0x3FU)
708#define ADC_CLPS_CLPS_SHIFT (0U)
709#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
710/*! @} */
711
712/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
713/*! @{ */
714#define ADC_CLP4_CLP4_MASK (0x3FFU)
715#define ADC_CLP4_CLP4_SHIFT (0U)
716#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
717/*! @} */
718
719/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
720/*! @{ */
721#define ADC_CLP3_CLP3_MASK (0x1FFU)
722#define ADC_CLP3_CLP3_SHIFT (0U)
723#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
724/*! @} */
725
726/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
727/*! @{ */
728#define ADC_CLP2_CLP2_MASK (0xFFU)
729#define ADC_CLP2_CLP2_SHIFT (0U)
730#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
731/*! @} */
732
733/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
734/*! @{ */
735#define ADC_CLP1_CLP1_MASK (0x7FU)
736#define ADC_CLP1_CLP1_SHIFT (0U)
737#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
738/*! @} */
739
740/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
741/*! @{ */
742#define ADC_CLP0_CLP0_MASK (0x3FU)
743#define ADC_CLP0_CLP0_SHIFT (0U)
744#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
745/*! @} */
746
747/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
748/*! @{ */
749#define ADC_CLMD_CLMD_MASK (0x3FU)
750#define ADC_CLMD_CLMD_SHIFT (0U)
751#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
752/*! @} */
753
754/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
755/*! @{ */
756#define ADC_CLMS_CLMS_MASK (0x3FU)
757#define ADC_CLMS_CLMS_SHIFT (0U)
758#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
759/*! @} */
760
761/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
762/*! @{ */
763#define ADC_CLM4_CLM4_MASK (0x3FFU)
764#define ADC_CLM4_CLM4_SHIFT (0U)
765#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
766/*! @} */
767
768/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
769/*! @{ */
770#define ADC_CLM3_CLM3_MASK (0x1FFU)
771#define ADC_CLM3_CLM3_SHIFT (0U)
772#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
773/*! @} */
774
775/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
776/*! @{ */
777#define ADC_CLM2_CLM2_MASK (0xFFU)
778#define ADC_CLM2_CLM2_SHIFT (0U)
779#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
780/*! @} */
781
782/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
783/*! @{ */
784#define ADC_CLM1_CLM1_MASK (0x7FU)
785#define ADC_CLM1_CLM1_SHIFT (0U)
786#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
787/*! @} */
788
789/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
790/*! @{ */
791#define ADC_CLM0_CLM0_MASK (0x3FU)
792#define ADC_CLM0_CLM0_SHIFT (0U)
793#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
794/*! @} */
795
796
797/*!
798 * @}
799 */ /* end of group ADC_Register_Masks */
800
801
802/* ADC - Peripheral instance base addresses */
803/** Peripheral ADC0 base address */
804#define ADC0_BASE (0x4003B000u)
805/** Peripheral ADC0 base pointer */
806#define ADC0 ((ADC_Type *)ADC0_BASE)
807/** Array initializer of ADC peripheral base addresses */
808#define ADC_BASE_ADDRS { ADC0_BASE }
809/** Array initializer of ADC peripheral base pointers */
810#define ADC_BASE_PTRS { ADC0 }
811/** Interrupt vectors for the ADC peripheral type */
812#define ADC_IRQS { ADC0_IRQn }
813
814/*!
815 * @}
816 */ /* end of group ADC_Peripheral_Access_Layer */
817
818
819/* ----------------------------------------------------------------------------
820 -- CMP Peripheral Access Layer
821 ---------------------------------------------------------------------------- */
822
823/*!
824 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
825 * @{
826 */
827
828/** CMP - Register Layout Typedef */
829typedef struct {
830 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
831 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
832 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
833 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
834 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
835 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
836} CMP_Type;
837
838/* ----------------------------------------------------------------------------
839 -- CMP Register Masks
840 ---------------------------------------------------------------------------- */
841
842/*!
843 * @addtogroup CMP_Register_Masks CMP Register Masks
844 * @{
845 */
846
847/*! @name CR0 - CMP Control Register 0 */
848/*! @{ */
849#define CMP_CR0_HYSTCTR_MASK (0x3U)
850#define CMP_CR0_HYSTCTR_SHIFT (0U)
851/*! HYSTCTR - Comparator hard block hysteresis control
852 * 0b00..Level 0
853 * 0b01..Level 1
854 * 0b10..Level 2
855 * 0b11..Level 3
856 */
857#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
858#define CMP_CR0_FILTER_CNT_MASK (0x70U)
859#define CMP_CR0_FILTER_CNT_SHIFT (4U)
860/*! FILTER_CNT - Filter Sample Count
861 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
862 * 0b001..One sample must agree. The comparator output is simply sampled.
863 * 0b010..2 consecutive samples must agree.
864 * 0b011..3 consecutive samples must agree.
865 * 0b100..4 consecutive samples must agree.
866 * 0b101..5 consecutive samples must agree.
867 * 0b110..6 consecutive samples must agree.
868 * 0b111..7 consecutive samples must agree.
869 */
870#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
871/*! @} */
872
873/*! @name CR1 - CMP Control Register 1 */
874/*! @{ */
875#define CMP_CR1_EN_MASK (0x1U)
876#define CMP_CR1_EN_SHIFT (0U)
877/*! EN - Comparator Module Enable
878 * 0b0..Analog Comparator is disabled.
879 * 0b1..Analog Comparator is enabled.
880 */
881#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
882#define CMP_CR1_OPE_MASK (0x2U)
883#define CMP_CR1_OPE_SHIFT (1U)
884/*! OPE - Comparator Output Pin Enable
885 * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
886 * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
887 */
888#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
889#define CMP_CR1_COS_MASK (0x4U)
890#define CMP_CR1_COS_SHIFT (2U)
891/*! COS - Comparator Output Select
892 * 0b0..Set the filtered comparator output (CMPO) to equal COUT.
893 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
894 */
895#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
896#define CMP_CR1_INV_MASK (0x8U)
897#define CMP_CR1_INV_SHIFT (3U)
898/*! INV - Comparator INVERT
899 * 0b0..Does not invert the comparator output.
900 * 0b1..Inverts the comparator output.
901 */
902#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
903#define CMP_CR1_PMODE_MASK (0x10U)
904#define CMP_CR1_PMODE_SHIFT (4U)
905/*! PMODE - Power Mode Select
906 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
907 * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
908 */
909#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
910#define CMP_CR1_TRIGM_MASK (0x20U)
911#define CMP_CR1_TRIGM_SHIFT (5U)
912/*! TRIGM - Trigger Mode Enable
913 * 0b0..Trigger mode is disabled.
914 * 0b1..Trigger mode is enabled.
915 */
916#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
917#define CMP_CR1_WE_MASK (0x40U)
918#define CMP_CR1_WE_SHIFT (6U)
919/*! WE - Windowing Enable
920 * 0b0..Windowing mode is not selected.
921 * 0b1..Windowing mode is selected.
922 */
923#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
924#define CMP_CR1_SE_MASK (0x80U)
925#define CMP_CR1_SE_SHIFT (7U)
926/*! SE - Sample Enable
927 * 0b0..Sampling mode is not selected.
928 * 0b1..Sampling mode is selected.
929 */
930#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
931/*! @} */
932
933/*! @name FPR - CMP Filter Period Register */
934/*! @{ */
935#define CMP_FPR_FILT_PER_MASK (0xFFU)
936#define CMP_FPR_FILT_PER_SHIFT (0U)
937#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
938/*! @} */
939
940/*! @name SCR - CMP Status and Control Register */
941/*! @{ */
942#define CMP_SCR_COUT_MASK (0x1U)
943#define CMP_SCR_COUT_SHIFT (0U)
944#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
945#define CMP_SCR_CFF_MASK (0x2U)
946#define CMP_SCR_CFF_SHIFT (1U)
947/*! CFF - Analog Comparator Flag Falling
948 * 0b0..Falling-edge on COUT has not been detected.
949 * 0b1..Falling-edge on COUT has occurred.
950 */
951#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
952#define CMP_SCR_CFR_MASK (0x4U)
953#define CMP_SCR_CFR_SHIFT (2U)
954/*! CFR - Analog Comparator Flag Rising
955 * 0b0..Rising-edge on COUT has not been detected.
956 * 0b1..Rising-edge on COUT has occurred.
957 */
958#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
959#define CMP_SCR_IEF_MASK (0x8U)
960#define CMP_SCR_IEF_SHIFT (3U)
961/*! IEF - Comparator Interrupt Enable Falling
962 * 0b0..Interrupt is disabled.
963 * 0b1..Interrupt is enabled.
964 */
965#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
966#define CMP_SCR_IER_MASK (0x10U)
967#define CMP_SCR_IER_SHIFT (4U)
968/*! IER - Comparator Interrupt Enable Rising
969 * 0b0..Interrupt is disabled.
970 * 0b1..Interrupt is enabled.
971 */
972#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
973#define CMP_SCR_DMAEN_MASK (0x40U)
974#define CMP_SCR_DMAEN_SHIFT (6U)
975/*! DMAEN - DMA Enable Control
976 * 0b0..DMA is disabled.
977 * 0b1..DMA is enabled.
978 */
979#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
980/*! @} */
981
982/*! @name DACCR - DAC Control Register */
983/*! @{ */
984#define CMP_DACCR_VOSEL_MASK (0x3FU)
985#define CMP_DACCR_VOSEL_SHIFT (0U)
986#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
987#define CMP_DACCR_VRSEL_MASK (0x40U)
988#define CMP_DACCR_VRSEL_SHIFT (6U)
989/*! VRSEL - Supply Voltage Reference Source Select
990 * 0b0..V is selected as resistor ladder network supply reference V. in1 in
991 * 0b1..V is selected as resistor ladder network supply reference V. in2 in
992 */
993#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
994#define CMP_DACCR_DACEN_MASK (0x80U)
995#define CMP_DACCR_DACEN_SHIFT (7U)
996/*! DACEN - DAC Enable
997 * 0b0..DAC is disabled.
998 * 0b1..DAC is enabled.
999 */
1000#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
1001/*! @} */
1002
1003/*! @name MUXCR - MUX Control Register */
1004/*! @{ */
1005#define CMP_MUXCR_MSEL_MASK (0x7U)
1006#define CMP_MUXCR_MSEL_SHIFT (0U)
1007/*! MSEL - Minus Input Mux Control
1008 * 0b000..IN0
1009 * 0b001..IN1
1010 * 0b010..IN2
1011 * 0b011..IN3
1012 * 0b100..IN4
1013 * 0b101..IN5
1014 * 0b110..IN6
1015 * 0b111..IN7
1016 */
1017#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
1018#define CMP_MUXCR_PSEL_MASK (0x38U)
1019#define CMP_MUXCR_PSEL_SHIFT (3U)
1020/*! PSEL - Plus Input Mux Control
1021 * 0b000..IN0
1022 * 0b001..IN1
1023 * 0b010..IN2
1024 * 0b011..IN3
1025 * 0b100..IN4
1026 * 0b101..IN5
1027 * 0b110..IN6
1028 * 0b111..IN7
1029 */
1030#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
1031/*! @} */
1032
1033
1034/*!
1035 * @}
1036 */ /* end of group CMP_Register_Masks */
1037
1038
1039/* CMP - Peripheral instance base addresses */
1040/** Peripheral CMP0 base address */
1041#define CMP0_BASE (0x40073000u)
1042/** Peripheral CMP0 base pointer */
1043#define CMP0 ((CMP_Type *)CMP0_BASE)
1044/** Peripheral CMP1 base address */
1045#define CMP1_BASE (0x40073008u)
1046/** Peripheral CMP1 base pointer */
1047#define CMP1 ((CMP_Type *)CMP1_BASE)
1048/** Array initializer of CMP peripheral base addresses */
1049#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
1050/** Array initializer of CMP peripheral base pointers */
1051#define CMP_BASE_PTRS { CMP0, CMP1 }
1052/** Interrupt vectors for the CMP peripheral type */
1053#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
1054
1055/*!
1056 * @}
1057 */ /* end of group CMP_Peripheral_Access_Layer */
1058
1059
1060/* ----------------------------------------------------------------------------
1061 -- CRC Peripheral Access Layer
1062 ---------------------------------------------------------------------------- */
1063
1064/*!
1065 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
1066 * @{
1067 */
1068
1069/** CRC - Register Layout Typedef */
1070typedef struct {
1071 union { /* offset: 0x0 */
1072 struct { /* offset: 0x0 */
1073 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
1074 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
1075 } ACCESS16BIT;
1076 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
1077 struct { /* offset: 0x0 */
1078 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
1079 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
1080 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
1081 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
1082 } ACCESS8BIT;
1083 };
1084 union { /* offset: 0x4 */
1085 struct { /* offset: 0x4 */
1086 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
1087 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
1088 } GPOLY_ACCESS16BIT;
1089 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
1090 struct { /* offset: 0x4 */
1091 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
1092 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
1093 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
1094 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
1095 } GPOLY_ACCESS8BIT;
1096 };
1097 union { /* offset: 0x8 */
1098 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
1099 struct { /* offset: 0x8 */
1100 uint8_t RESERVED_0[3];
1101 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
1102 } CTRL_ACCESS8BIT;
1103 };
1104} CRC_Type;
1105
1106/* ----------------------------------------------------------------------------
1107 -- CRC Register Masks
1108 ---------------------------------------------------------------------------- */
1109
1110/*!
1111 * @addtogroup CRC_Register_Masks CRC Register Masks
1112 * @{
1113 */
1114
1115/*! @name DATAL - CRC_DATAL register. */
1116/*! @{ */
1117#define CRC_DATAL_DATAL_MASK (0xFFFFU)
1118#define CRC_DATAL_DATAL_SHIFT (0U)
1119#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
1120/*! @} */
1121
1122/*! @name DATAH - CRC_DATAH register. */
1123/*! @{ */
1124#define CRC_DATAH_DATAH_MASK (0xFFFFU)
1125#define CRC_DATAH_DATAH_SHIFT (0U)
1126#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
1127/*! @} */
1128
1129/*! @name DATA - CRC Data register */
1130/*! @{ */
1131#define CRC_DATA_LL_MASK (0xFFU)
1132#define CRC_DATA_LL_SHIFT (0U)
1133#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
1134#define CRC_DATA_LU_MASK (0xFF00U)
1135#define CRC_DATA_LU_SHIFT (8U)
1136#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
1137#define CRC_DATA_HL_MASK (0xFF0000U)
1138#define CRC_DATA_HL_SHIFT (16U)
1139#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
1140#define CRC_DATA_HU_MASK (0xFF000000U)
1141#define CRC_DATA_HU_SHIFT (24U)
1142#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
1143/*! @} */
1144
1145/*! @name DATALL - CRC_DATALL register. */
1146/*! @{ */
1147#define CRC_DATALL_DATALL_MASK (0xFFU)
1148#define CRC_DATALL_DATALL_SHIFT (0U)
1149#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
1150/*! @} */
1151
1152/*! @name DATALU - CRC_DATALU register. */
1153/*! @{ */
1154#define CRC_DATALU_DATALU_MASK (0xFFU)
1155#define CRC_DATALU_DATALU_SHIFT (0U)
1156#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
1157/*! @} */
1158
1159/*! @name DATAHL - CRC_DATAHL register. */
1160/*! @{ */
1161#define CRC_DATAHL_DATAHL_MASK (0xFFU)
1162#define CRC_DATAHL_DATAHL_SHIFT (0U)
1163#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
1164/*! @} */
1165
1166/*! @name DATAHU - CRC_DATAHU register. */
1167/*! @{ */
1168#define CRC_DATAHU_DATAHU_MASK (0xFFU)
1169#define CRC_DATAHU_DATAHU_SHIFT (0U)
1170#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
1171/*! @} */
1172
1173/*! @name GPOLYL - CRC_GPOLYL register. */
1174/*! @{ */
1175#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
1176#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
1177#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
1178/*! @} */
1179
1180/*! @name GPOLYH - CRC_GPOLYH register. */
1181/*! @{ */
1182#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
1183#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
1184#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
1185/*! @} */
1186
1187/*! @name GPOLY - CRC Polynomial register */
1188/*! @{ */
1189#define CRC_GPOLY_LOW_MASK (0xFFFFU)
1190#define CRC_GPOLY_LOW_SHIFT (0U)
1191#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
1192#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
1193#define CRC_GPOLY_HIGH_SHIFT (16U)
1194#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
1195/*! @} */
1196
1197/*! @name GPOLYLL - CRC_GPOLYLL register. */
1198/*! @{ */
1199#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
1200#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
1201#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
1202/*! @} */
1203
1204/*! @name GPOLYLU - CRC_GPOLYLU register. */
1205/*! @{ */
1206#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
1207#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
1208#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
1209/*! @} */
1210
1211/*! @name GPOLYHL - CRC_GPOLYHL register. */
1212/*! @{ */
1213#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
1214#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
1215#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
1216/*! @} */
1217
1218/*! @name GPOLYHU - CRC_GPOLYHU register. */
1219/*! @{ */
1220#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
1221#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
1222#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
1223/*! @} */
1224
1225/*! @name CTRL - CRC Control register */
1226/*! @{ */
1227#define CRC_CTRL_TCRC_MASK (0x1000000U)
1228#define CRC_CTRL_TCRC_SHIFT (24U)
1229/*! TCRC
1230 * 0b0..16-bit CRC protocol.
1231 * 0b1..32-bit CRC protocol.
1232 */
1233#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
1234#define CRC_CTRL_WAS_MASK (0x2000000U)
1235#define CRC_CTRL_WAS_SHIFT (25U)
1236/*! WAS - Write CRC Data Register As Seed
1237 * 0b0..Writes to the CRC data register are data values.
1238 * 0b1..Writes to the CRC data register are seed values.
1239 */
1240#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
1241#define CRC_CTRL_FXOR_MASK (0x4000000U)
1242#define CRC_CTRL_FXOR_SHIFT (26U)
1243/*! FXOR - Complement Read Of CRC Data Register
1244 * 0b0..No XOR on reading.
1245 * 0b1..Invert or complement the read value of the CRC Data register.
1246 */
1247#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
1248#define CRC_CTRL_TOTR_MASK (0x30000000U)
1249#define CRC_CTRL_TOTR_SHIFT (28U)
1250/*! TOTR - Type Of Transpose For Read
1251 * 0b00..No transposition.
1252 * 0b01..Bits in bytes are transposed; bytes are not transposed.
1253 * 0b10..Both bits in bytes and bytes are transposed.
1254 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
1255 */
1256#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
1257#define CRC_CTRL_TOT_MASK (0xC0000000U)
1258#define CRC_CTRL_TOT_SHIFT (30U)
1259/*! TOT - Type Of Transpose For Writes
1260 * 0b00..No transposition.
1261 * 0b01..Bits in bytes are transposed; bytes are not transposed.
1262 * 0b10..Both bits in bytes and bytes are transposed.
1263 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
1264 */
1265#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
1266/*! @} */
1267
1268/*! @name CTRLHU - CRC_CTRLHU register. */
1269/*! @{ */
1270#define CRC_CTRLHU_TCRC_MASK (0x1U)
1271#define CRC_CTRLHU_TCRC_SHIFT (0U)
1272/*! TCRC
1273 * 0b0..16-bit CRC protocol.
1274 * 0b1..32-bit CRC protocol.
1275 */
1276#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
1277#define CRC_CTRLHU_WAS_MASK (0x2U)
1278#define CRC_CTRLHU_WAS_SHIFT (1U)
1279/*! WAS
1280 * 0b0..Writes to CRC data register are data values.
1281 * 0b1..Writes to CRC data reguster are seed values.
1282 */
1283#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
1284#define CRC_CTRLHU_FXOR_MASK (0x4U)
1285#define CRC_CTRLHU_FXOR_SHIFT (2U)
1286/*! FXOR
1287 * 0b0..No XOR on reading.
1288 * 0b1..Invert or complement the read value of CRC data register.
1289 */
1290#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
1291#define CRC_CTRLHU_TOTR_MASK (0x30U)
1292#define CRC_CTRLHU_TOTR_SHIFT (4U)
1293/*! TOTR
1294 * 0b00..No Transposition.
1295 * 0b01..Bits in bytes are transposed, bytes are not transposed.
1296 * 0b10..Both bits in bytes and bytes are transposed.
1297 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
1298 */
1299#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
1300#define CRC_CTRLHU_TOT_MASK (0xC0U)
1301#define CRC_CTRLHU_TOT_SHIFT (6U)
1302/*! TOT
1303 * 0b00..No Transposition.
1304 * 0b01..Bits in bytes are transposed, bytes are not transposed.
1305 * 0b10..Both bits in bytes and bytes are transposed.
1306 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
1307 */
1308#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
1309/*! @} */
1310
1311
1312/*!
1313 * @}
1314 */ /* end of group CRC_Register_Masks */
1315
1316
1317/* CRC - Peripheral instance base addresses */
1318/** Peripheral CRC base address */
1319#define CRC_BASE (0x40032000u)
1320/** Peripheral CRC base pointer */
1321#define CRC0 ((CRC_Type *)CRC_BASE)
1322/** Array initializer of CRC peripheral base addresses */
1323#define CRC_BASE_ADDRS { CRC_BASE }
1324/** Array initializer of CRC peripheral base pointers */
1325#define CRC_BASE_PTRS { CRC0 }
1326
1327/*!
1328 * @}
1329 */ /* end of group CRC_Peripheral_Access_Layer */
1330
1331
1332/* ----------------------------------------------------------------------------
1333 -- DAC Peripheral Access Layer
1334 ---------------------------------------------------------------------------- */
1335
1336/*!
1337 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
1338 * @{
1339 */
1340
1341/** DAC - Register Layout Typedef */
1342typedef struct {
1343 struct { /* offset: 0x0, array step: 0x2 */
1344 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
1345 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
1346 } DAT[16];
1347 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
1348 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
1349 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
1350 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
1351} DAC_Type;
1352
1353/* ----------------------------------------------------------------------------
1354 -- DAC Register Masks
1355 ---------------------------------------------------------------------------- */
1356
1357/*!
1358 * @addtogroup DAC_Register_Masks DAC Register Masks
1359 * @{
1360 */
1361
1362/*! @name DATL - DAC Data Low Register */
1363/*! @{ */
1364#define DAC_DATL_DATA0_MASK (0xFFU)
1365#define DAC_DATL_DATA0_SHIFT (0U)
1366#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
1367/*! @} */
1368
1369/* The count of DAC_DATL */
1370#define DAC_DATL_COUNT (16U)
1371
1372/*! @name DATH - DAC Data High Register */
1373/*! @{ */
1374#define DAC_DATH_DATA1_MASK (0xFU)
1375#define DAC_DATH_DATA1_SHIFT (0U)
1376#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
1377/*! @} */
1378
1379/* The count of DAC_DATH */
1380#define DAC_DATH_COUNT (16U)
1381
1382/*! @name SR - DAC Status Register */
1383/*! @{ */
1384#define DAC_SR_DACBFRPBF_MASK (0x1U)
1385#define DAC_SR_DACBFRPBF_SHIFT (0U)
1386/*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag
1387 * 0b0..The DAC buffer read pointer is not equal to C2[DACBFUP].
1388 * 0b1..The DAC buffer read pointer is equal to C2[DACBFUP].
1389 */
1390#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
1391#define DAC_SR_DACBFRPTF_MASK (0x2U)
1392#define DAC_SR_DACBFRPTF_SHIFT (1U)
1393/*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag
1394 * 0b0..The DAC buffer read pointer is not zero.
1395 * 0b1..The DAC buffer read pointer is zero.
1396 */
1397#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
1398#define DAC_SR_DACBFWMF_MASK (0x4U)
1399#define DAC_SR_DACBFWMF_SHIFT (2U)
1400/*! DACBFWMF - DAC Buffer Watermark Flag
1401 * 0b0..The DAC buffer read pointer has not reached the watermark level.
1402 * 0b1..The DAC buffer read pointer has reached the watermark level.
1403 */
1404#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
1405/*! @} */
1406
1407/*! @name C0 - DAC Control Register */
1408/*! @{ */
1409#define DAC_C0_DACBBIEN_MASK (0x1U)
1410#define DAC_C0_DACBBIEN_SHIFT (0U)
1411/*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable
1412 * 0b0..The DAC buffer read pointer bottom flag interrupt is disabled.
1413 * 0b1..The DAC buffer read pointer bottom flag interrupt is enabled.
1414 */
1415#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
1416#define DAC_C0_DACBTIEN_MASK (0x2U)
1417#define DAC_C0_DACBTIEN_SHIFT (1U)
1418/*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable
1419 * 0b0..The DAC buffer read pointer top flag interrupt is disabled.
1420 * 0b1..The DAC buffer read pointer top flag interrupt is enabled.
1421 */
1422#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
1423#define DAC_C0_DACBWIEN_MASK (0x4U)
1424#define DAC_C0_DACBWIEN_SHIFT (2U)
1425/*! DACBWIEN - DAC Buffer Watermark Interrupt Enable
1426 * 0b0..The DAC buffer watermark interrupt is disabled.
1427 * 0b1..The DAC buffer watermark interrupt is enabled.
1428 */
1429#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
1430#define DAC_C0_LPEN_MASK (0x8U)
1431#define DAC_C0_LPEN_SHIFT (3U)
1432/*! LPEN - DAC Low Power Control
1433 * 0b0..High-Power mode
1434 * 0b1..Low-Power mode
1435 */
1436#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
1437#define DAC_C0_DACSWTRG_MASK (0x10U)
1438#define DAC_C0_DACSWTRG_SHIFT (4U)
1439/*! DACSWTRG - DAC Software Trigger
1440 * 0b0..The DAC soft trigger is not valid.
1441 * 0b1..The DAC soft trigger is valid.
1442 */
1443#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
1444#define DAC_C0_DACTRGSEL_MASK (0x20U)
1445#define DAC_C0_DACTRGSEL_SHIFT (5U)
1446/*! DACTRGSEL - DAC Trigger Select
1447 * 0b0..The DAC hardware trigger is selected.
1448 * 0b1..The DAC software trigger is selected.
1449 */
1450#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
1451#define DAC_C0_DACRFS_MASK (0x40U)
1452#define DAC_C0_DACRFS_SHIFT (6U)
1453/*! DACRFS - DAC Reference Select
1454 * 0b0..The DAC selects DACREF_1 as the reference voltage.
1455 * 0b1..The DAC selects DACREF_2 as the reference voltage.
1456 */
1457#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
1458#define DAC_C0_DACEN_MASK (0x80U)
1459#define DAC_C0_DACEN_SHIFT (7U)
1460/*! DACEN - DAC Enable
1461 * 0b0..The DAC system is disabled.
1462 * 0b1..The DAC system is enabled.
1463 */
1464#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
1465/*! @} */
1466
1467/*! @name C1 - DAC Control Register 1 */
1468/*! @{ */
1469#define DAC_C1_DACBFEN_MASK (0x1U)
1470#define DAC_C1_DACBFEN_SHIFT (0U)
1471/*! DACBFEN - DAC Buffer Enable
1472 * 0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer.
1473 * 0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
1474 */
1475#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
1476#define DAC_C1_DACBFMD_MASK (0x6U)
1477#define DAC_C1_DACBFMD_SHIFT (1U)
1478/*! DACBFMD - DAC Buffer Work Mode Select
1479 * 0b00..Normal mode
1480 * 0b01..Swing mode
1481 * 0b10..One-Time Scan mode
1482 * 0b11..FIFO mode
1483 */
1484#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
1485#define DAC_C1_DACBFWM_MASK (0x18U)
1486#define DAC_C1_DACBFWM_SHIFT (3U)
1487/*! DACBFWM - DAC Buffer Watermark Select
1488 * 0b00..In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining in FIFO will set watermark status bit.
1489 * 0b01..In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data remaining in FIFO will set watermark status bit.
1490 * 0b10..In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data remaining in FIFO will set watermark status bit.
1491 * 0b11..In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data remaining in FIFO will set watermark status bit.
1492 */
1493#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
1494#define DAC_C1_DMAEN_MASK (0x80U)
1495#define DAC_C1_DMAEN_SHIFT (7U)
1496/*! DMAEN - DMA Enable Select
1497 * 0b0..DMA is disabled.
1498 * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
1499 */
1500#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
1501/*! @} */
1502
1503/*! @name C2 - DAC Control Register 2 */
1504/*! @{ */
1505#define DAC_C2_DACBFUP_MASK (0xFU)
1506#define DAC_C2_DACBFUP_SHIFT (0U)
1507#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
1508#define DAC_C2_DACBFRP_MASK (0xF0U)
1509#define DAC_C2_DACBFRP_SHIFT (4U)
1510#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
1511/*! @} */
1512
1513
1514/*!
1515 * @}
1516 */ /* end of group DAC_Register_Masks */
1517
1518
1519/* DAC - Peripheral instance base addresses */
1520/** Peripheral DAC0 base address */
1521#define DAC0_BASE (0x4003F000u)
1522/** Peripheral DAC0 base pointer */
1523#define DAC0 ((DAC_Type *)DAC0_BASE)
1524/** Array initializer of DAC peripheral base addresses */
1525#define DAC_BASE_ADDRS { DAC0_BASE }
1526/** Array initializer of DAC peripheral base pointers */
1527#define DAC_BASE_PTRS { DAC0 }
1528/** Interrupt vectors for the DAC peripheral type */
1529#define DAC_IRQS { DAC0_IRQn }
1530
1531/*!
1532 * @}
1533 */ /* end of group DAC_Peripheral_Access_Layer */
1534
1535
1536/* ----------------------------------------------------------------------------
1537 -- DMA Peripheral Access Layer
1538 ---------------------------------------------------------------------------- */
1539
1540/*!
1541 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
1542 * @{
1543 */
1544
1545/** DMA - Register Layout Typedef */
1546typedef struct {
1547 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
1548 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
1549 uint8_t RESERVED_0[4];
1550 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
1551 uint8_t RESERVED_1[4];
1552 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
1553 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
1554 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
1555 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
1556 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
1557 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
1558 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
1559 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
1560 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
1561 uint8_t RESERVED_2[4];
1562 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
1563 uint8_t RESERVED_3[4];
1564 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
1565 uint8_t RESERVED_4[4];
1566 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
1567 uint8_t RESERVED_5[12];
1568 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
1569 uint8_t RESERVED_6[184];
1570 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
1571 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
1572 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
1573 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
1574 uint8_t RESERVED_7[3836];
1575 struct { /* offset: 0x1000, array step: 0x20 */
1576 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
1577 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
1578 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
1579 union { /* offset: 0x1008, array step: 0x20 */
1580 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
1581 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
1582 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
1583 };
1584 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
1585 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
1586 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
1587 union { /* offset: 0x1016, array step: 0x20 */
1588 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
1589 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
1590 };
1591 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
1592 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
1593 union { /* offset: 0x101E, array step: 0x20 */
1594 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
1595 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
1596 };
1597 } TCD[4];
1598} DMA_Type;
1599
1600/* ----------------------------------------------------------------------------
1601 -- DMA Register Masks
1602 ---------------------------------------------------------------------------- */
1603
1604/*!
1605 * @addtogroup DMA_Register_Masks DMA Register Masks
1606 * @{
1607 */
1608
1609/*! @name CR - Control Register */
1610/*! @{ */
1611#define DMA_CR_EDBG_MASK (0x2U)
1612#define DMA_CR_EDBG_SHIFT (1U)
1613/*! EDBG - Enable Debug
1614 * 0b0..When in debug mode, the DMA continues to operate.
1615 * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
1616 */
1617#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
1618#define DMA_CR_ERCA_MASK (0x4U)
1619#define DMA_CR_ERCA_SHIFT (2U)
1620/*! ERCA - Enable Round Robin Channel Arbitration
1621 * 0b0..Fixed priority arbitration is used for channel selection .
1622 * 0b1..Round robin arbitration is used for channel selection .
1623 */
1624#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
1625#define DMA_CR_HOE_MASK (0x10U)
1626#define DMA_CR_HOE_SHIFT (4U)
1627/*! HOE - Halt On Error
1628 * 0b0..Normal operation
1629 * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
1630 */
1631#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
1632#define DMA_CR_HALT_MASK (0x20U)
1633#define DMA_CR_HALT_SHIFT (5U)
1634/*! HALT - Halt DMA Operations
1635 * 0b0..Normal operation
1636 * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
1637 */
1638#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
1639#define DMA_CR_CLM_MASK (0x40U)
1640#define DMA_CR_CLM_SHIFT (6U)
1641/*! CLM - Continuous Link Mode
1642 * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
1643 * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
1644 */
1645#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
1646#define DMA_CR_EMLM_MASK (0x80U)
1647#define DMA_CR_EMLM_SHIFT (7U)
1648/*! EMLM - Enable Minor Loop Mapping
1649 * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
1650 * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
1651 */
1652#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
1653#define DMA_CR_ECX_MASK (0x10000U)
1654#define DMA_CR_ECX_SHIFT (16U)
1655/*! ECX - Error Cancel Transfer
1656 * 0b0..Normal operation
1657 * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
1658 */
1659#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
1660#define DMA_CR_CX_MASK (0x20000U)
1661#define DMA_CR_CX_SHIFT (17U)
1662/*! CX - Cancel Transfer
1663 * 0b0..Normal operation
1664 * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
1665 */
1666#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
1667/*! @} */
1668
1669/*! @name ES - Error Status Register */
1670/*! @{ */
1671#define DMA_ES_DBE_MASK (0x1U)
1672#define DMA_ES_DBE_SHIFT (0U)
1673/*! DBE - Destination Bus Error
1674 * 0b0..No destination bus error
1675 * 0b1..The last recorded error was a bus error on a destination write
1676 */
1677#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
1678#define DMA_ES_SBE_MASK (0x2U)
1679#define DMA_ES_SBE_SHIFT (1U)
1680/*! SBE - Source Bus Error
1681 * 0b0..No source bus error
1682 * 0b1..The last recorded error was a bus error on a source read
1683 */
1684#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
1685#define DMA_ES_SGE_MASK (0x4U)
1686#define DMA_ES_SGE_SHIFT (2U)
1687/*! SGE - Scatter/Gather Configuration Error
1688 * 0b0..No scatter/gather configuration error
1689 * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
1690 */
1691#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
1692#define DMA_ES_NCE_MASK (0x8U)
1693#define DMA_ES_NCE_SHIFT (3U)
1694/*! NCE - NBYTES/CITER Configuration Error
1695 * 0b0..No NBYTES/CITER configuration error
1696 * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
1697 */
1698#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
1699#define DMA_ES_DOE_MASK (0x10U)
1700#define DMA_ES_DOE_SHIFT (4U)
1701/*! DOE - Destination Offset Error
1702 * 0b0..No destination offset configuration error
1703 * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
1704 */
1705#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
1706#define DMA_ES_DAE_MASK (0x20U)
1707#define DMA_ES_DAE_SHIFT (5U)
1708/*! DAE - Destination Address Error
1709 * 0b0..No destination address configuration error
1710 * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
1711 */
1712#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
1713#define DMA_ES_SOE_MASK (0x40U)
1714#define DMA_ES_SOE_SHIFT (6U)
1715/*! SOE - Source Offset Error
1716 * 0b0..No source offset configuration error
1717 * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
1718 */
1719#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
1720#define DMA_ES_SAE_MASK (0x80U)
1721#define DMA_ES_SAE_SHIFT (7U)
1722/*! SAE - Source Address Error
1723 * 0b0..No source address configuration error.
1724 * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
1725 */
1726#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
1727#define DMA_ES_ERRCHN_MASK (0x300U)
1728#define DMA_ES_ERRCHN_SHIFT (8U)
1729#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
1730#define DMA_ES_CPE_MASK (0x4000U)
1731#define DMA_ES_CPE_SHIFT (14U)
1732/*! CPE - Channel Priority Error
1733 * 0b0..No channel priority error
1734 * 0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.
1735 */
1736#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
1737#define DMA_ES_ECX_MASK (0x10000U)
1738#define DMA_ES_ECX_SHIFT (16U)
1739/*! ECX - Transfer Canceled
1740 * 0b0..No canceled transfers
1741 * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
1742 */
1743#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
1744#define DMA_ES_VLD_MASK (0x80000000U)
1745#define DMA_ES_VLD_SHIFT (31U)
1746/*! VLD
1747 * 0b0..No ERR bits are set
1748 * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared
1749 */
1750#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
1751/*! @} */
1752
1753/*! @name ERQ - Enable Request Register */
1754/*! @{ */
1755#define DMA_ERQ_ERQ0_MASK (0x1U)
1756#define DMA_ERQ_ERQ0_SHIFT (0U)
1757/*! ERQ0 - Enable DMA Request 0
1758 * 0b0..The DMA request signal for the corresponding channel is disabled
1759 * 0b1..The DMA request signal for the corresponding channel is enabled
1760 */
1761#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
1762#define DMA_ERQ_ERQ1_MASK (0x2U)
1763#define DMA_ERQ_ERQ1_SHIFT (1U)
1764/*! ERQ1 - Enable DMA Request 1
1765 * 0b0..The DMA request signal for the corresponding channel is disabled
1766 * 0b1..The DMA request signal for the corresponding channel is enabled
1767 */
1768#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
1769#define DMA_ERQ_ERQ2_MASK (0x4U)
1770#define DMA_ERQ_ERQ2_SHIFT (2U)
1771/*! ERQ2 - Enable DMA Request 2
1772 * 0b0..The DMA request signal for the corresponding channel is disabled
1773 * 0b1..The DMA request signal for the corresponding channel is enabled
1774 */
1775#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
1776#define DMA_ERQ_ERQ3_MASK (0x8U)
1777#define DMA_ERQ_ERQ3_SHIFT (3U)
1778/*! ERQ3 - Enable DMA Request 3
1779 * 0b0..The DMA request signal for the corresponding channel is disabled
1780 * 0b1..The DMA request signal for the corresponding channel is enabled
1781 */
1782#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
1783/*! @} */
1784
1785/*! @name EEI - Enable Error Interrupt Register */
1786/*! @{ */
1787#define DMA_EEI_EEI0_MASK (0x1U)
1788#define DMA_EEI_EEI0_SHIFT (0U)
1789/*! EEI0 - Enable Error Interrupt 0
1790 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1791 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1792 */
1793#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
1794#define DMA_EEI_EEI1_MASK (0x2U)
1795#define DMA_EEI_EEI1_SHIFT (1U)
1796/*! EEI1 - Enable Error Interrupt 1
1797 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1798 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1799 */
1800#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
1801#define DMA_EEI_EEI2_MASK (0x4U)
1802#define DMA_EEI_EEI2_SHIFT (2U)
1803/*! EEI2 - Enable Error Interrupt 2
1804 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1805 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1806 */
1807#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
1808#define DMA_EEI_EEI3_MASK (0x8U)
1809#define DMA_EEI_EEI3_SHIFT (3U)
1810/*! EEI3 - Enable Error Interrupt 3
1811 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1812 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1813 */
1814#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
1815/*! @} */
1816
1817/*! @name CEEI - Clear Enable Error Interrupt Register */
1818/*! @{ */
1819#define DMA_CEEI_CEEI_MASK (0x3U)
1820#define DMA_CEEI_CEEI_SHIFT (0U)
1821#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
1822#define DMA_CEEI_CAEE_MASK (0x40U)
1823#define DMA_CEEI_CAEE_SHIFT (6U)
1824/*! CAEE - Clear All Enable Error Interrupts
1825 * 0b0..Clear only the EEI bit specified in the CEEI field
1826 * 0b1..Clear all bits in EEI
1827 */
1828#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
1829#define DMA_CEEI_NOP_MASK (0x80U)
1830#define DMA_CEEI_NOP_SHIFT (7U)
1831/*! NOP - No Op enable
1832 * 0b0..Normal operation
1833 * 0b1..No operation, ignore the other bits in this register
1834 */
1835#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
1836/*! @} */
1837
1838/*! @name SEEI - Set Enable Error Interrupt Register */
1839/*! @{ */
1840#define DMA_SEEI_SEEI_MASK (0x3U)
1841#define DMA_SEEI_SEEI_SHIFT (0U)
1842#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
1843#define DMA_SEEI_SAEE_MASK (0x40U)
1844#define DMA_SEEI_SAEE_SHIFT (6U)
1845/*! SAEE - Sets All Enable Error Interrupts
1846 * 0b0..Set only the EEI bit specified in the SEEI field.
1847 * 0b1..Sets all bits in EEI
1848 */
1849#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
1850#define DMA_SEEI_NOP_MASK (0x80U)
1851#define DMA_SEEI_NOP_SHIFT (7U)
1852/*! NOP - No Op enable
1853 * 0b0..Normal operation
1854 * 0b1..No operation, ignore the other bits in this register
1855 */
1856#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
1857/*! @} */
1858
1859/*! @name CERQ - Clear Enable Request Register */
1860/*! @{ */
1861#define DMA_CERQ_CERQ_MASK (0x3U)
1862#define DMA_CERQ_CERQ_SHIFT (0U)
1863#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
1864#define DMA_CERQ_CAER_MASK (0x40U)
1865#define DMA_CERQ_CAER_SHIFT (6U)
1866/*! CAER - Clear All Enable Requests
1867 * 0b0..Clear only the ERQ bit specified in the CERQ field
1868 * 0b1..Clear all bits in ERQ
1869 */
1870#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
1871#define DMA_CERQ_NOP_MASK (0x80U)
1872#define DMA_CERQ_NOP_SHIFT (7U)
1873/*! NOP - No Op enable
1874 * 0b0..Normal operation
1875 * 0b1..No operation, ignore the other bits in this register
1876 */
1877#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
1878/*! @} */
1879
1880/*! @name SERQ - Set Enable Request Register */
1881/*! @{ */
1882#define DMA_SERQ_SERQ_MASK (0x3U)
1883#define DMA_SERQ_SERQ_SHIFT (0U)
1884#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
1885#define DMA_SERQ_SAER_MASK (0x40U)
1886#define DMA_SERQ_SAER_SHIFT (6U)
1887/*! SAER - Set All Enable Requests
1888 * 0b0..Set only the ERQ bit specified in the SERQ field
1889 * 0b1..Set all bits in ERQ
1890 */
1891#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
1892#define DMA_SERQ_NOP_MASK (0x80U)
1893#define DMA_SERQ_NOP_SHIFT (7U)
1894/*! NOP - No Op enable
1895 * 0b0..Normal operation
1896 * 0b1..No operation, ignore the other bits in this register
1897 */
1898#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
1899/*! @} */
1900
1901/*! @name CDNE - Clear DONE Status Bit Register */
1902/*! @{ */
1903#define DMA_CDNE_CDNE_MASK (0x3U)
1904#define DMA_CDNE_CDNE_SHIFT (0U)
1905#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
1906#define DMA_CDNE_CADN_MASK (0x40U)
1907#define DMA_CDNE_CADN_SHIFT (6U)
1908/*! CADN - Clears All DONE Bits
1909 * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
1910 * 0b1..Clears all bits in TCDn_CSR[DONE]
1911 */
1912#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
1913#define DMA_CDNE_NOP_MASK (0x80U)
1914#define DMA_CDNE_NOP_SHIFT (7U)
1915/*! NOP - No Op enable
1916 * 0b0..Normal operation
1917 * 0b1..No operation, ignore the other bits in this register
1918 */
1919#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
1920/*! @} */
1921
1922/*! @name SSRT - Set START Bit Register */
1923/*! @{ */
1924#define DMA_SSRT_SSRT_MASK (0x3U)
1925#define DMA_SSRT_SSRT_SHIFT (0U)
1926#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
1927#define DMA_SSRT_SAST_MASK (0x40U)
1928#define DMA_SSRT_SAST_SHIFT (6U)
1929/*! SAST - Set All START Bits (activates all channels)
1930 * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
1931 * 0b1..Set all bits in TCDn_CSR[START]
1932 */
1933#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
1934#define DMA_SSRT_NOP_MASK (0x80U)
1935#define DMA_SSRT_NOP_SHIFT (7U)
1936/*! NOP - No Op enable
1937 * 0b0..Normal operation
1938 * 0b1..No operation, ignore the other bits in this register
1939 */
1940#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
1941/*! @} */
1942
1943/*! @name CERR - Clear Error Register */
1944/*! @{ */
1945#define DMA_CERR_CERR_MASK (0x3U)
1946#define DMA_CERR_CERR_SHIFT (0U)
1947#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
1948#define DMA_CERR_CAEI_MASK (0x40U)
1949#define DMA_CERR_CAEI_SHIFT (6U)
1950/*! CAEI - Clear All Error Indicators
1951 * 0b0..Clear only the ERR bit specified in the CERR field
1952 * 0b1..Clear all bits in ERR
1953 */
1954#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
1955#define DMA_CERR_NOP_MASK (0x80U)
1956#define DMA_CERR_NOP_SHIFT (7U)
1957/*! NOP - No Op enable
1958 * 0b0..Normal operation
1959 * 0b1..No operation, ignore the other bits in this register
1960 */
1961#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
1962/*! @} */
1963
1964/*! @name CINT - Clear Interrupt Request Register */
1965/*! @{ */
1966#define DMA_CINT_CINT_MASK (0x3U)
1967#define DMA_CINT_CINT_SHIFT (0U)
1968#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
1969#define DMA_CINT_CAIR_MASK (0x40U)
1970#define DMA_CINT_CAIR_SHIFT (6U)
1971/*! CAIR - Clear All Interrupt Requests
1972 * 0b0..Clear only the INT bit specified in the CINT field
1973 * 0b1..Clear all bits in INT
1974 */
1975#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
1976#define DMA_CINT_NOP_MASK (0x80U)
1977#define DMA_CINT_NOP_SHIFT (7U)
1978/*! NOP - No Op enable
1979 * 0b0..Normal operation
1980 * 0b1..No operation, ignore the other bits in this register
1981 */
1982#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
1983/*! @} */
1984
1985/*! @name INT - Interrupt Request Register */
1986/*! @{ */
1987#define DMA_INT_INT0_MASK (0x1U)
1988#define DMA_INT_INT0_SHIFT (0U)
1989/*! INT0 - Interrupt Request 0
1990 * 0b0..The interrupt request for corresponding channel is cleared
1991 * 0b1..The interrupt request for corresponding channel is active
1992 */
1993#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
1994#define DMA_INT_INT1_MASK (0x2U)
1995#define DMA_INT_INT1_SHIFT (1U)
1996/*! INT1 - Interrupt Request 1
1997 * 0b0..The interrupt request for corresponding channel is cleared
1998 * 0b1..The interrupt request for corresponding channel is active
1999 */
2000#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
2001#define DMA_INT_INT2_MASK (0x4U)
2002#define DMA_INT_INT2_SHIFT (2U)
2003/*! INT2 - Interrupt Request 2
2004 * 0b0..The interrupt request for corresponding channel is cleared
2005 * 0b1..The interrupt request for corresponding channel is active
2006 */
2007#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
2008#define DMA_INT_INT3_MASK (0x8U)
2009#define DMA_INT_INT3_SHIFT (3U)
2010/*! INT3 - Interrupt Request 3
2011 * 0b0..The interrupt request for corresponding channel is cleared
2012 * 0b1..The interrupt request for corresponding channel is active
2013 */
2014#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
2015/*! @} */
2016
2017/*! @name ERR - Error Register */
2018/*! @{ */
2019#define DMA_ERR_ERR0_MASK (0x1U)
2020#define DMA_ERR_ERR0_SHIFT (0U)
2021/*! ERR0 - Error In Channel 0
2022 * 0b0..An error in the corresponding channel has not occurred
2023 * 0b1..An error in the corresponding channel has occurred
2024 */
2025#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
2026#define DMA_ERR_ERR1_MASK (0x2U)
2027#define DMA_ERR_ERR1_SHIFT (1U)
2028/*! ERR1 - Error In Channel 1
2029 * 0b0..An error in the corresponding channel has not occurred
2030 * 0b1..An error in the corresponding channel has occurred
2031 */
2032#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
2033#define DMA_ERR_ERR2_MASK (0x4U)
2034#define DMA_ERR_ERR2_SHIFT (2U)
2035/*! ERR2 - Error In Channel 2
2036 * 0b0..An error in the corresponding channel has not occurred
2037 * 0b1..An error in the corresponding channel has occurred
2038 */
2039#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
2040#define DMA_ERR_ERR3_MASK (0x8U)
2041#define DMA_ERR_ERR3_SHIFT (3U)
2042/*! ERR3 - Error In Channel 3
2043 * 0b0..An error in the corresponding channel has not occurred
2044 * 0b1..An error in the corresponding channel has occurred
2045 */
2046#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
2047/*! @} */
2048
2049/*! @name HRS - Hardware Request Status Register */
2050/*! @{ */
2051#define DMA_HRS_HRS0_MASK (0x1U)
2052#define DMA_HRS_HRS0_SHIFT (0U)
2053/*! HRS0 - Hardware Request Status Channel 0
2054 * 0b0..A hardware service request for channel 0 is not present
2055 * 0b1..A hardware service request for channel 0 is present
2056 */
2057#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
2058#define DMA_HRS_HRS1_MASK (0x2U)
2059#define DMA_HRS_HRS1_SHIFT (1U)
2060/*! HRS1 - Hardware Request Status Channel 1
2061 * 0b0..A hardware service request for channel 1 is not present
2062 * 0b1..A hardware service request for channel 1 is present
2063 */
2064#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
2065#define DMA_HRS_HRS2_MASK (0x4U)
2066#define DMA_HRS_HRS2_SHIFT (2U)
2067/*! HRS2 - Hardware Request Status Channel 2
2068 * 0b0..A hardware service request for channel 2 is not present
2069 * 0b1..A hardware service request for channel 2 is present
2070 */
2071#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
2072#define DMA_HRS_HRS3_MASK (0x8U)
2073#define DMA_HRS_HRS3_SHIFT (3U)
2074/*! HRS3 - Hardware Request Status Channel 3
2075 * 0b0..A hardware service request for channel 3 is not present
2076 * 0b1..A hardware service request for channel 3 is present
2077 */
2078#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
2079/*! @} */
2080
2081/*! @name EARS - Enable Asynchronous Request in Stop Register */
2082/*! @{ */
2083#define DMA_EARS_EDREQ_0_MASK (0x1U)
2084#define DMA_EARS_EDREQ_0_SHIFT (0U)
2085/*! EDREQ_0 - Enable asynchronous DMA request in stop for channel 0.
2086 * 0b0..Disable asynchronous DMA request for channel 0.
2087 * 0b1..Enable asynchronous DMA request for channel 0.
2088 */
2089#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
2090#define DMA_EARS_EDREQ_1_MASK (0x2U)
2091#define DMA_EARS_EDREQ_1_SHIFT (1U)
2092/*! EDREQ_1 - Enable asynchronous DMA request in stop for channel 1.
2093 * 0b0..Disable asynchronous DMA request for channel 1
2094 * 0b1..Enable asynchronous DMA request for channel 1.
2095 */
2096#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
2097#define DMA_EARS_EDREQ_2_MASK (0x4U)
2098#define DMA_EARS_EDREQ_2_SHIFT (2U)
2099/*! EDREQ_2 - Enable asynchronous DMA request in stop for channel 2.
2100 * 0b0..Disable asynchronous DMA request for channel 2.
2101 * 0b1..Enable asynchronous DMA request for channel 2.
2102 */
2103#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
2104#define DMA_EARS_EDREQ_3_MASK (0x8U)
2105#define DMA_EARS_EDREQ_3_SHIFT (3U)
2106/*! EDREQ_3 - Enable asynchronous DMA request in stop for channel 3.
2107 * 0b0..Disable asynchronous DMA request for channel 3.
2108 * 0b1..Enable asynchronous DMA request for channel 3.
2109 */
2110#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
2111/*! @} */
2112
2113/*! @name DCHPRI3 - Channel n Priority Register */
2114/*! @{ */
2115#define DMA_DCHPRI3_CHPRI_MASK (0x3U)
2116#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
2117#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
2118#define DMA_DCHPRI3_DPA_MASK (0x40U)
2119#define DMA_DCHPRI3_DPA_SHIFT (6U)
2120/*! DPA - Disable Preempt Ability
2121 * 0b0..Channel n can suspend a lower priority channel
2122 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2123 */
2124#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
2125#define DMA_DCHPRI3_ECP_MASK (0x80U)
2126#define DMA_DCHPRI3_ECP_SHIFT (7U)
2127/*! ECP - Enable Channel Preemption
2128 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2129 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2130 */
2131#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
2132/*! @} */
2133
2134/*! @name DCHPRI2 - Channel n Priority Register */
2135/*! @{ */
2136#define DMA_DCHPRI2_CHPRI_MASK (0x3U)
2137#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
2138#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
2139#define DMA_DCHPRI2_DPA_MASK (0x40U)
2140#define DMA_DCHPRI2_DPA_SHIFT (6U)
2141/*! DPA - Disable Preempt Ability
2142 * 0b0..Channel n can suspend a lower priority channel
2143 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2144 */
2145#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
2146#define DMA_DCHPRI2_ECP_MASK (0x80U)
2147#define DMA_DCHPRI2_ECP_SHIFT (7U)
2148/*! ECP - Enable Channel Preemption
2149 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2150 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2151 */
2152#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
2153/*! @} */
2154
2155/*! @name DCHPRI1 - Channel n Priority Register */
2156/*! @{ */
2157#define DMA_DCHPRI1_CHPRI_MASK (0x3U)
2158#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
2159#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
2160#define DMA_DCHPRI1_DPA_MASK (0x40U)
2161#define DMA_DCHPRI1_DPA_SHIFT (6U)
2162/*! DPA - Disable Preempt Ability
2163 * 0b0..Channel n can suspend a lower priority channel
2164 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2165 */
2166#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
2167#define DMA_DCHPRI1_ECP_MASK (0x80U)
2168#define DMA_DCHPRI1_ECP_SHIFT (7U)
2169/*! ECP - Enable Channel Preemption
2170 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2171 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2172 */
2173#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
2174/*! @} */
2175
2176/*! @name DCHPRI0 - Channel n Priority Register */
2177/*! @{ */
2178#define DMA_DCHPRI0_CHPRI_MASK (0x3U)
2179#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
2180#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
2181#define DMA_DCHPRI0_DPA_MASK (0x40U)
2182#define DMA_DCHPRI0_DPA_SHIFT (6U)
2183/*! DPA - Disable Preempt Ability
2184 * 0b0..Channel n can suspend a lower priority channel
2185 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2186 */
2187#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
2188#define DMA_DCHPRI0_ECP_MASK (0x80U)
2189#define DMA_DCHPRI0_ECP_SHIFT (7U)
2190/*! ECP - Enable Channel Preemption
2191 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2192 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2193 */
2194#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
2195/*! @} */
2196
2197/*! @name SADDR - TCD Source Address */
2198/*! @{ */
2199#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
2200#define DMA_SADDR_SADDR_SHIFT (0U)
2201#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
2202/*! @} */
2203
2204/* The count of DMA_SADDR */
2205#define DMA_SADDR_COUNT (4U)
2206
2207/*! @name SOFF - TCD Signed Source Address Offset */
2208/*! @{ */
2209#define DMA_SOFF_SOFF_MASK (0xFFFFU)
2210#define DMA_SOFF_SOFF_SHIFT (0U)
2211#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
2212/*! @} */
2213
2214/* The count of DMA_SOFF */
2215#define DMA_SOFF_COUNT (4U)
2216
2217/*! @name ATTR - TCD Transfer Attributes */
2218/*! @{ */
2219#define DMA_ATTR_DSIZE_MASK (0x7U)
2220#define DMA_ATTR_DSIZE_SHIFT (0U)
2221#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
2222#define DMA_ATTR_DMOD_MASK (0xF8U)
2223#define DMA_ATTR_DMOD_SHIFT (3U)
2224#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
2225#define DMA_ATTR_SSIZE_MASK (0x700U)
2226#define DMA_ATTR_SSIZE_SHIFT (8U)
2227/*! SSIZE - Source data transfer size
2228 * 0b000..8-bit
2229 * 0b001..16-bit
2230 * 0b010..32-bit
2231 * 0b011..Reserved
2232 * 0b100..16-byte
2233 * 0b101..32-byte
2234 * 0b110..Reserved
2235 * 0b111..Reserved
2236 */
2237#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
2238#define DMA_ATTR_SMOD_MASK (0xF800U)
2239#define DMA_ATTR_SMOD_SHIFT (11U)
2240/*! SMOD - Source Address Modulo.
2241 * 0b00000..Source address modulo feature is disabled
2242 */
2243#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
2244/*! @} */
2245
2246/* The count of DMA_ATTR */
2247#define DMA_ATTR_COUNT (4U)
2248
2249/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */
2250/*! @{ */
2251#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
2252#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
2253#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
2254/*! @} */
2255
2256/* The count of DMA_NBYTES_MLNO */
2257#define DMA_NBYTES_MLNO_COUNT (4U)
2258
2259/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
2260/*! @{ */
2261#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
2262#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
2263#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
2264#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
2265#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
2266/*! DMLOE - Destination Minor Loop Offset enable
2267 * 0b0..The minor loop offset is not applied to the DADDR
2268 * 0b1..The minor loop offset is applied to the DADDR
2269 */
2270#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
2271#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
2272#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
2273/*! SMLOE - Source Minor Loop Offset Enable
2274 * 0b0..The minor loop offset is not applied to the SADDR
2275 * 0b1..The minor loop offset is applied to the SADDR
2276 */
2277#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
2278/*! @} */
2279
2280/* The count of DMA_NBYTES_MLOFFNO */
2281#define DMA_NBYTES_MLOFFNO_COUNT (4U)
2282
2283/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
2284/*! @{ */
2285#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
2286#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
2287#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
2288#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
2289#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
2290#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
2291#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
2292#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
2293/*! DMLOE - Destination Minor Loop Offset enable
2294 * 0b0..The minor loop offset is not applied to the DADDR
2295 * 0b1..The minor loop offset is applied to the DADDR
2296 */
2297#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
2298#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
2299#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
2300/*! SMLOE - Source Minor Loop Offset Enable
2301 * 0b0..The minor loop offset is not applied to the SADDR
2302 * 0b1..The minor loop offset is applied to the SADDR
2303 */
2304#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
2305/*! @} */
2306
2307/* The count of DMA_NBYTES_MLOFFYES */
2308#define DMA_NBYTES_MLOFFYES_COUNT (4U)
2309
2310/*! @name SLAST - TCD Last Source Address Adjustment */
2311/*! @{ */
2312#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
2313#define DMA_SLAST_SLAST_SHIFT (0U)
2314#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
2315/*! @} */
2316
2317/* The count of DMA_SLAST */
2318#define DMA_SLAST_COUNT (4U)
2319
2320/*! @name DADDR - TCD Destination Address */
2321/*! @{ */
2322#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
2323#define DMA_DADDR_DADDR_SHIFT (0U)
2324#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
2325/*! @} */
2326
2327/* The count of DMA_DADDR */
2328#define DMA_DADDR_COUNT (4U)
2329
2330/*! @name DOFF - TCD Signed Destination Address Offset */
2331/*! @{ */
2332#define DMA_DOFF_DOFF_MASK (0xFFFFU)
2333#define DMA_DOFF_DOFF_SHIFT (0U)
2334#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
2335/*! @} */
2336
2337/* The count of DMA_DOFF */
2338#define DMA_DOFF_COUNT (4U)
2339
2340/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
2341/*! @{ */
2342#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
2343#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
2344#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
2345#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
2346#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
2347/*! ELINK - Enable channel-to-channel linking on minor-loop complete
2348 * 0b0..The channel-to-channel linking is disabled
2349 * 0b1..The channel-to-channel linking is enabled
2350 */
2351#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
2352/*! @} */
2353
2354/* The count of DMA_CITER_ELINKNO */
2355#define DMA_CITER_ELINKNO_COUNT (4U)
2356
2357/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
2358/*! @{ */
2359#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
2360#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
2361#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
2362#define DMA_CITER_ELINKYES_LINKCH_MASK (0x600U)
2363#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
2364#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
2365#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
2366#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
2367/*! ELINK - Enable channel-to-channel linking on minor-loop complete
2368 * 0b0..The channel-to-channel linking is disabled
2369 * 0b1..The channel-to-channel linking is enabled
2370 */
2371#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
2372/*! @} */
2373
2374/* The count of DMA_CITER_ELINKYES */
2375#define DMA_CITER_ELINKYES_COUNT (4U)
2376
2377/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
2378/*! @{ */
2379#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
2380#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
2381#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
2382/*! @} */
2383
2384/* The count of DMA_DLAST_SGA */
2385#define DMA_DLAST_SGA_COUNT (4U)
2386
2387/*! @name CSR - TCD Control and Status */
2388/*! @{ */
2389#define DMA_CSR_START_MASK (0x1U)
2390#define DMA_CSR_START_SHIFT (0U)
2391/*! START - Channel Start
2392 * 0b0..The channel is not explicitly started
2393 * 0b1..The channel is explicitly started via a software initiated service request
2394 */
2395#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
2396#define DMA_CSR_INTMAJOR_MASK (0x2U)
2397#define DMA_CSR_INTMAJOR_SHIFT (1U)
2398/*! INTMAJOR - Enable an interrupt when major iteration count completes
2399 * 0b0..The end-of-major loop interrupt is disabled
2400 * 0b1..The end-of-major loop interrupt is enabled
2401 */
2402#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
2403#define DMA_CSR_INTHALF_MASK (0x4U)
2404#define DMA_CSR_INTHALF_SHIFT (2U)
2405/*! INTHALF - Enable an interrupt when major counter is half complete.
2406 * 0b0..The half-point interrupt is disabled
2407 * 0b1..The half-point interrupt is enabled
2408 */
2409#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
2410#define DMA_CSR_DREQ_MASK (0x8U)
2411#define DMA_CSR_DREQ_SHIFT (3U)
2412/*! DREQ - Disable Request
2413 * 0b0..The channel's ERQ bit is not affected
2414 * 0b1..The channel's ERQ bit is cleared when the major loop is complete
2415 */
2416#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
2417#define DMA_CSR_ESG_MASK (0x10U)
2418#define DMA_CSR_ESG_SHIFT (4U)
2419/*! ESG - Enable Scatter/Gather Processing
2420 * 0b0..The current channel's TCD is normal format.
2421 * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
2422 */
2423#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
2424#define DMA_CSR_MAJORELINK_MASK (0x20U)
2425#define DMA_CSR_MAJORELINK_SHIFT (5U)
2426/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
2427 * 0b0..The channel-to-channel linking is disabled
2428 * 0b1..The channel-to-channel linking is enabled
2429 */
2430#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
2431#define DMA_CSR_ACTIVE_MASK (0x40U)
2432#define DMA_CSR_ACTIVE_SHIFT (6U)
2433#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
2434#define DMA_CSR_DONE_MASK (0x80U)
2435#define DMA_CSR_DONE_SHIFT (7U)
2436#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
2437#define DMA_CSR_MAJORLINKCH_MASK (0x300U)
2438#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
2439#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
2440#define DMA_CSR_BWC_MASK (0xC000U)
2441#define DMA_CSR_BWC_SHIFT (14U)
2442/*! BWC - Bandwidth Control
2443 * 0b00..No eDMA engine stalls
2444 * 0b01..Reserved
2445 * 0b10..eDMA engine stalls for 4 cycles after each r/w
2446 * 0b11..eDMA engine stalls for 8 cycles after each r/w
2447 */
2448#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
2449/*! @} */
2450
2451/* The count of DMA_CSR */
2452#define DMA_CSR_COUNT (4U)
2453
2454/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
2455/*! @{ */
2456#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
2457#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
2458#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
2459#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
2460#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
2461/*! ELINK - Enables channel-to-channel linking on minor loop complete
2462 * 0b0..The channel-to-channel linking is disabled
2463 * 0b1..The channel-to-channel linking is enabled
2464 */
2465#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
2466/*! @} */
2467
2468/* The count of DMA_BITER_ELINKNO */
2469#define DMA_BITER_ELINKNO_COUNT (4U)
2470
2471/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
2472/*! @{ */
2473#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
2474#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
2475#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
2476#define DMA_BITER_ELINKYES_LINKCH_MASK (0x600U)
2477#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
2478#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
2479#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
2480#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
2481/*! ELINK - Enables channel-to-channel linking on minor loop complete
2482 * 0b0..The channel-to-channel linking is disabled
2483 * 0b1..The channel-to-channel linking is enabled
2484 */
2485#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
2486/*! @} */
2487
2488/* The count of DMA_BITER_ELINKYES */
2489#define DMA_BITER_ELINKYES_COUNT (4U)
2490
2491
2492/*!
2493 * @}
2494 */ /* end of group DMA_Register_Masks */
2495
2496
2497/* DMA - Peripheral instance base addresses */
2498/** Peripheral DMA base address */
2499#define DMA_BASE (0x40008000u)
2500/** Peripheral DMA base pointer */
2501#define DMA0 ((DMA_Type *)DMA_BASE)
2502/** Array initializer of DMA peripheral base addresses */
2503#define DMA_BASE_ADDRS { DMA_BASE }
2504/** Array initializer of DMA peripheral base pointers */
2505#define DMA_BASE_PTRS { DMA0 }
2506/** Interrupt vectors for the DMA peripheral type */
2507#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn } }
2508#define DMA_ERROR_IRQS { DMA_Error_IRQn }
2509
2510/*!
2511 * @}
2512 */ /* end of group DMA_Peripheral_Access_Layer */
2513
2514
2515/* ----------------------------------------------------------------------------
2516 -- DMAMUX Peripheral Access Layer
2517 ---------------------------------------------------------------------------- */
2518
2519/*!
2520 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
2521 * @{
2522 */
2523
2524/** DMAMUX - Register Layout Typedef */
2525typedef struct {
2526 __IO uint8_t CHCFG[4]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
2527} DMAMUX_Type;
2528
2529/* ----------------------------------------------------------------------------
2530 -- DMAMUX Register Masks
2531 ---------------------------------------------------------------------------- */
2532
2533/*!
2534 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
2535 * @{
2536 */
2537
2538/*! @name CHCFG - Channel Configuration register */
2539/*! @{ */
2540#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
2541#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
2542/*! SOURCE - DMA Channel Source (Slot)
2543 * 0b000000..Disable_Signal
2544 * 0b000010..UART0_Rx_Signal
2545 * 0b000011..UART0_Tx_Signal
2546 * 0b000100..UART1_Rx_Signal
2547 * 0b000101..UART1_Tx_Signal
2548 * 0b001110..SPI0_Rx_Signal
2549 * 0b001111..SPI0_Tx_Signal
2550 * 0b010010..I2C0_Signal
2551 * 0b010100..FTM0_Channel0_Signal
2552 * 0b010101..FTM0_Channel1_Signal
2553 * 0b010110..FTM0_Channel2_Signal
2554 * 0b010111..FTM0_Channel3_Signal
2555 * 0b011000..FTM0_Channel4_Signal
2556 * 0b011001..FTM0_Channel5_Signal
2557 * 0b011100..FTM1_Channel0_Signal
2558 * 0b011101..FTM1_Channel1_Signal
2559 * 0b011110..FTM2_Channel0_Signal
2560 * 0b011111..FTM2_Channel1_Signal
2561 * 0b101000..ADC0_Signal
2562 * 0b101010..CMP0_Signal
2563 * 0b101011..CMP1_Signal
2564 * 0b101101..DAC0_Signal
2565 * 0b110000..PDB_Signal
2566 * 0b110001..PortA_Signal
2567 * 0b110010..PortB_Signal
2568 * 0b110011..PortC_Signal
2569 * 0b110100..PortD_Signal
2570 * 0b110101..PortE_Signal
2571 * 0b111100..AlwaysOn60_Signal
2572 * 0b111101..AlwaysOn61_Signal
2573 * 0b111110..AlwaysOn62_Signal
2574 * 0b111111..AlwaysOn63_Signal
2575 */
2576#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
2577#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
2578#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
2579/*! TRIG - DMA Channel Trigger Enable
2580 * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
2581 * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
2582 */
2583#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
2584#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
2585#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
2586/*! ENBL - DMA Channel Enable
2587 * 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
2588 * 0b1..DMA channel is enabled
2589 */
2590#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
2591/*! @} */
2592
2593/* The count of DMAMUX_CHCFG */
2594#define DMAMUX_CHCFG_COUNT (4U)
2595
2596
2597/*!
2598 * @}
2599 */ /* end of group DMAMUX_Register_Masks */
2600
2601
2602/* DMAMUX - Peripheral instance base addresses */
2603/** Peripheral DMAMUX base address */
2604#define DMAMUX_BASE (0x40021000u)
2605/** Peripheral DMAMUX base pointer */
2606#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
2607/** Array initializer of DMAMUX peripheral base addresses */
2608#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
2609/** Array initializer of DMAMUX peripheral base pointers */
2610#define DMAMUX_BASE_PTRS { DMAMUX }
2611
2612/*!
2613 * @}
2614 */ /* end of group DMAMUX_Peripheral_Access_Layer */
2615
2616
2617/* ----------------------------------------------------------------------------
2618 -- EWM Peripheral Access Layer
2619 ---------------------------------------------------------------------------- */
2620
2621/*!
2622 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
2623 * @{
2624 */
2625
2626/** EWM - Register Layout Typedef */
2627typedef struct {
2628 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
2629 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
2630 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
2631 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
2632 uint8_t RESERVED_0[1];
2633 __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
2634} EWM_Type;
2635
2636/* ----------------------------------------------------------------------------
2637 -- EWM Register Masks
2638 ---------------------------------------------------------------------------- */
2639
2640/*!
2641 * @addtogroup EWM_Register_Masks EWM Register Masks
2642 * @{
2643 */
2644
2645/*! @name CTRL - Control Register */
2646/*! @{ */
2647#define EWM_CTRL_EWMEN_MASK (0x1U)
2648#define EWM_CTRL_EWMEN_SHIFT (0U)
2649#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
2650#define EWM_CTRL_ASSIN_MASK (0x2U)
2651#define EWM_CTRL_ASSIN_SHIFT (1U)
2652#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
2653#define EWM_CTRL_INEN_MASK (0x4U)
2654#define EWM_CTRL_INEN_SHIFT (2U)
2655#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
2656#define EWM_CTRL_INTEN_MASK (0x8U)
2657#define EWM_CTRL_INTEN_SHIFT (3U)
2658#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
2659/*! @} */
2660
2661/*! @name SERV - Service Register */
2662/*! @{ */
2663#define EWM_SERV_SERVICE_MASK (0xFFU)
2664#define EWM_SERV_SERVICE_SHIFT (0U)
2665#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
2666/*! @} */
2667
2668/*! @name CMPL - Compare Low Register */
2669/*! @{ */
2670#define EWM_CMPL_COMPAREL_MASK (0xFFU)
2671#define EWM_CMPL_COMPAREL_SHIFT (0U)
2672#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
2673/*! @} */
2674
2675/*! @name CMPH - Compare High Register */
2676/*! @{ */
2677#define EWM_CMPH_COMPAREH_MASK (0xFFU)
2678#define EWM_CMPH_COMPAREH_SHIFT (0U)
2679#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
2680/*! @} */
2681
2682/*! @name CLKPRESCALER - Clock Prescaler Register */
2683/*! @{ */
2684#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
2685#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
2686#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
2687/*! @} */
2688
2689
2690/*!
2691 * @}
2692 */ /* end of group EWM_Register_Masks */
2693
2694
2695/* EWM - Peripheral instance base addresses */
2696/** Peripheral EWM base address */
2697#define EWM_BASE (0x40061000u)
2698/** Peripheral EWM base pointer */
2699#define EWM ((EWM_Type *)EWM_BASE)
2700/** Array initializer of EWM peripheral base addresses */
2701#define EWM_BASE_ADDRS { EWM_BASE }
2702/** Array initializer of EWM peripheral base pointers */
2703#define EWM_BASE_PTRS { EWM }
2704/** Interrupt vectors for the EWM peripheral type */
2705#define EWM_IRQS { WDOG_EWM_IRQn }
2706
2707/*!
2708 * @}
2709 */ /* end of group EWM_Peripheral_Access_Layer */
2710
2711
2712/* ----------------------------------------------------------------------------
2713 -- FMC Peripheral Access Layer
2714 ---------------------------------------------------------------------------- */
2715
2716/*!
2717 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
2718 * @{
2719 */
2720
2721/** FMC - Register Layout Typedef */
2722typedef struct {
2723 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
2724 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
2725 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
2726 uint8_t RESERVED_0[244];
2727 __IO uint32_t TAGVDW0S[8]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
2728 __IO uint32_t TAGVDW1S[8]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
2729 __IO uint32_t TAGVDW2S[8]; /**< Cache Tag Storage, array offset: 0x140, array step: 0x4 */
2730 __IO uint32_t TAGVDW3S[8]; /**< Cache Tag Storage, array offset: 0x160, array step: 0x4 */
2731 uint8_t RESERVED_1[128];
2732 struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */
2733 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
2734 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
2735 } SET[4][8];
2736} FMC_Type;
2737
2738/* ----------------------------------------------------------------------------
2739 -- FMC Register Masks
2740 ---------------------------------------------------------------------------- */
2741
2742/*!
2743 * @addtogroup FMC_Register_Masks FMC Register Masks
2744 * @{
2745 */
2746
2747/*! @name PFAPR - Flash Access Protection Register */
2748/*! @{ */
2749#define FMC_PFAPR_M0AP_MASK (0x3U)
2750#define FMC_PFAPR_M0AP_SHIFT (0U)
2751/*! M0AP - Master 0 Access Protection
2752 * 0b00..No access may be performed by this master
2753 * 0b01..Only read accesses may be performed by this master
2754 * 0b10..Only write accesses may be performed by this master
2755 * 0b11..Both read and write accesses may be performed by this master
2756 */
2757#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
2758#define FMC_PFAPR_M1AP_MASK (0xCU)
2759#define FMC_PFAPR_M1AP_SHIFT (2U)
2760/*! M1AP - Master 1 Access Protection
2761 * 0b00..No access may be performed by this master
2762 * 0b01..Only read accesses may be performed by this master
2763 * 0b10..Only write accesses may be performed by this master
2764 * 0b11..Both read and write accesses may be performed by this master
2765 */
2766#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
2767#define FMC_PFAPR_M2AP_MASK (0x30U)
2768#define FMC_PFAPR_M2AP_SHIFT (4U)
2769/*! M2AP - Master 2 Access Protection
2770 * 0b00..No access may be performed by this master
2771 * 0b01..Only read accesses may be performed by this master
2772 * 0b10..Only write accesses may be performed by this master
2773 * 0b11..Both read and write accesses may be performed by this master
2774 */
2775#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
2776#define FMC_PFAPR_M3AP_MASK (0xC0U)
2777#define FMC_PFAPR_M3AP_SHIFT (6U)
2778/*! M3AP - Master 3 Access Protection
2779 * 0b00..No access may be performed by this master
2780 * 0b01..Only read accesses may be performed by this master
2781 * 0b10..Only write accesses may be performed by this master
2782 * 0b11..Both read and write accesses may be performed by this master
2783 */
2784#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
2785#define FMC_PFAPR_M4AP_MASK (0x300U)
2786#define FMC_PFAPR_M4AP_SHIFT (8U)
2787/*! M4AP - Master 4 Access Protection
2788 * 0b00..No access may be performed by this master
2789 * 0b01..Only read accesses may be performed by this master
2790 * 0b10..Only write accesses may be performed by this master
2791 * 0b11..Both read and write accesses may be performed by this master
2792 */
2793#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
2794#define FMC_PFAPR_M5AP_MASK (0xC00U)
2795#define FMC_PFAPR_M5AP_SHIFT (10U)
2796/*! M5AP - Master 5 Access Protection
2797 * 0b00..No access may be performed by this master
2798 * 0b01..Only read accesses may be performed by this master
2799 * 0b10..Only write accesses may be performed by this master
2800 * 0b11..Both read and write accesses may be performed by this master
2801 */
2802#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
2803#define FMC_PFAPR_M6AP_MASK (0x3000U)
2804#define FMC_PFAPR_M6AP_SHIFT (12U)
2805/*! M6AP - Master 6 Access Protection
2806 * 0b00..No access may be performed by this master
2807 * 0b01..Only read accesses may be performed by this master
2808 * 0b10..Only write accesses may be performed by this master
2809 * 0b11..Both read and write accesses may be performed by this master
2810 */
2811#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
2812#define FMC_PFAPR_M7AP_MASK (0xC000U)
2813#define FMC_PFAPR_M7AP_SHIFT (14U)
2814/*! M7AP - Master 7 Access Protection
2815 * 0b00..No access may be performed by this master.
2816 * 0b01..Only read accesses may be performed by this master.
2817 * 0b10..Only write accesses may be performed by this master.
2818 * 0b11..Both read and write accesses may be performed by this master.
2819 */
2820#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
2821#define FMC_PFAPR_M0PFD_MASK (0x10000U)
2822#define FMC_PFAPR_M0PFD_SHIFT (16U)
2823/*! M0PFD - Master 0 Prefetch Disable
2824 * 0b0..Prefetching for this master is enabled.
2825 * 0b1..Prefetching for this master is disabled.
2826 */
2827#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
2828#define FMC_PFAPR_M1PFD_MASK (0x20000U)
2829#define FMC_PFAPR_M1PFD_SHIFT (17U)
2830/*! M1PFD - Master 1 Prefetch Disable
2831 * 0b0..Prefetching for this master is enabled.
2832 * 0b1..Prefetching for this master is disabled.
2833 */
2834#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
2835#define FMC_PFAPR_M2PFD_MASK (0x40000U)
2836#define FMC_PFAPR_M2PFD_SHIFT (18U)
2837/*! M2PFD - Master 2 Prefetch Disable
2838 * 0b0..Prefetching for this master is enabled.
2839 * 0b1..Prefetching for this master is disabled.
2840 */
2841#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
2842#define FMC_PFAPR_M3PFD_MASK (0x80000U)
2843#define FMC_PFAPR_M3PFD_SHIFT (19U)
2844/*! M3PFD - Master 3 Prefetch Disable
2845 * 0b0..Prefetching for this master is enabled.
2846 * 0b1..Prefetching for this master is disabled.
2847 */
2848#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
2849#define FMC_PFAPR_M4PFD_MASK (0x100000U)
2850#define FMC_PFAPR_M4PFD_SHIFT (20U)
2851/*! M4PFD - Master 4 Prefetch Disable
2852 * 0b0..Prefetching for this master is enabled.
2853 * 0b1..Prefetching for this master is disabled.
2854 */
2855#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
2856#define FMC_PFAPR_M5PFD_MASK (0x200000U)
2857#define FMC_PFAPR_M5PFD_SHIFT (21U)
2858/*! M5PFD - Master 5 Prefetch Disable
2859 * 0b0..Prefetching for this master is enabled.
2860 * 0b1..Prefetching for this master is disabled.
2861 */
2862#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
2863#define FMC_PFAPR_M6PFD_MASK (0x400000U)
2864#define FMC_PFAPR_M6PFD_SHIFT (22U)
2865/*! M6PFD - Master 6 Prefetch Disable
2866 * 0b0..Prefetching for this master is enabled.
2867 * 0b1..Prefetching for this master is disabled.
2868 */
2869#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
2870#define FMC_PFAPR_M7PFD_MASK (0x800000U)
2871#define FMC_PFAPR_M7PFD_SHIFT (23U)
2872/*! M7PFD - Master 7 Prefetch Disable
2873 * 0b0..Prefetching for this master is enabled.
2874 * 0b1..Prefetching for this master is disabled.
2875 */
2876#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
2877/*! @} */
2878
2879/*! @name PFB0CR - Flash Bank 0 Control Register */
2880/*! @{ */
2881#define FMC_PFB0CR_B0SEBE_MASK (0x1U)
2882#define FMC_PFB0CR_B0SEBE_SHIFT (0U)
2883/*! B0SEBE - Bank 0 Single Entry Buffer Enable
2884 * 0b0..Single entry buffer is disabled.
2885 * 0b1..Single entry buffer is enabled.
2886 */
2887#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
2888#define FMC_PFB0CR_B0IPE_MASK (0x2U)
2889#define FMC_PFB0CR_B0IPE_SHIFT (1U)
2890/*! B0IPE - Bank 0 Instruction Prefetch Enable
2891 * 0b0..Do not prefetch in response to instruction fetches.
2892 * 0b1..Enable prefetches in response to instruction fetches.
2893 */
2894#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
2895#define FMC_PFB0CR_B0DPE_MASK (0x4U)
2896#define FMC_PFB0CR_B0DPE_SHIFT (2U)
2897/*! B0DPE - Bank 0 Data Prefetch Enable
2898 * 0b0..Do not prefetch in response to data references.
2899 * 0b1..Enable prefetches in response to data references.
2900 */
2901#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
2902#define FMC_PFB0CR_B0ICE_MASK (0x8U)
2903#define FMC_PFB0CR_B0ICE_SHIFT (3U)
2904/*! B0ICE - Bank 0 Instruction Cache Enable
2905 * 0b0..Do not cache instruction fetches.
2906 * 0b1..Cache instruction fetches.
2907 */
2908#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
2909#define FMC_PFB0CR_B0DCE_MASK (0x10U)
2910#define FMC_PFB0CR_B0DCE_SHIFT (4U)
2911/*! B0DCE - Bank 0 Data Cache Enable
2912 * 0b0..Do not cache data references.
2913 * 0b1..Cache data references.
2914 */
2915#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
2916#define FMC_PFB0CR_CRC_MASK (0xE0U)
2917#define FMC_PFB0CR_CRC_SHIFT (5U)
2918/*! CRC - Cache Replacement Control
2919 * 0b000..LRU replacement algorithm per set across all four ways
2920 * 0b001..Reserved
2921 * 0b010..Independent LRU with ways [0-1] for ifetches, [2-3] for data
2922 * 0b011..Independent LRU with ways [0-2] for ifetches, [3] for data
2923 * 0b1xx..Reserved
2924 */
2925#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
2926#define FMC_PFB0CR_B0MW_MASK (0x60000U)
2927#define FMC_PFB0CR_B0MW_SHIFT (17U)
2928/*! B0MW - Bank 0 Memory Width
2929 * 0b00..32 bits
2930 * 0b01..64 bits
2931 * 0b10..Reserved
2932 * 0b11..Reserved
2933 */
2934#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
2935#define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
2936#define FMC_PFB0CR_S_B_INV_SHIFT (19U)
2937/*! S_B_INV - Invalidate Prefetch Speculation Buffer
2938 * 0b0..Speculation buffer and single entry buffer are not affected.
2939 * 0b1..Invalidate (clear) speculation buffer and single entry buffer.
2940 */
2941#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
2942#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
2943#define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
2944/*! CINV_WAY - Cache Invalidate Way x
2945 * 0b0000..No cache way invalidation for the corresponding cache
2946 * 0b0001..Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
2947 */
2948#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
2949#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
2950#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
2951/*! CLCK_WAY - Cache Lock Way x
2952 * 0b0000..Cache way is unlocked and may be displaced
2953 * 0b0001..Cache way is locked and its contents are not displaced
2954 */
2955#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
2956#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
2957#define FMC_PFB0CR_B0RWSC_SHIFT (28U)
2958#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
2959/*! @} */
2960
2961/*! @name PFB1CR - Flash Bank 1 Control Register */
2962/*! @{ */
2963#define FMC_PFB1CR_B1SEBE_MASK (0x1U)
2964#define FMC_PFB1CR_B1SEBE_SHIFT (0U)
2965/*! B1SEBE - Bank 1 Single Entry Buffer Enable
2966 * 0b0..Single entry buffer is disabled.
2967 * 0b1..Single entry buffer is enabled.
2968 */
2969#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
2970#define FMC_PFB1CR_B1IPE_MASK (0x2U)
2971#define FMC_PFB1CR_B1IPE_SHIFT (1U)
2972/*! B1IPE - Bank 1 Instruction Prefetch Enable
2973 * 0b0..Do not prefetch in response to instruction fetches.
2974 * 0b1..Enable prefetches in response to instruction fetches.
2975 */
2976#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
2977#define FMC_PFB1CR_B1DPE_MASK (0x4U)
2978#define FMC_PFB1CR_B1DPE_SHIFT (2U)
2979/*! B1DPE - Bank 1 Data Prefetch Enable
2980 * 0b0..Do not prefetch in response to data references.
2981 * 0b1..Enable prefetches in response to data references.
2982 */
2983#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
2984#define FMC_PFB1CR_B1ICE_MASK (0x8U)
2985#define FMC_PFB1CR_B1ICE_SHIFT (3U)
2986/*! B1ICE - Bank 1 Instruction Cache Enable
2987 * 0b0..Do not cache instruction fetches.
2988 * 0b1..Cache instruction fetches.
2989 */
2990#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
2991#define FMC_PFB1CR_B1DCE_MASK (0x10U)
2992#define FMC_PFB1CR_B1DCE_SHIFT (4U)
2993/*! B1DCE - Bank 1 Data Cache Enable
2994 * 0b0..Do not cache data references.
2995 * 0b1..Cache data references.
2996 */
2997#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
2998#define FMC_PFB1CR_B1MW_MASK (0x60000U)
2999#define FMC_PFB1CR_B1MW_SHIFT (17U)
3000/*! B1MW - Bank 1 Memory Width
3001 * 0b00..32 bits
3002 * 0b01..64 bits
3003 * 0b10..Reserved
3004 * 0b11..Reserved
3005 */
3006#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
3007#define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U)
3008#define FMC_PFB1CR_B1RWSC_SHIFT (28U)
3009#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
3010/*! @} */
3011
3012/*! @name TAGVDW0S - Cache Tag Storage */
3013/*! @{ */
3014#define FMC_TAGVDW0S_valid_MASK (0x1U)
3015#define FMC_TAGVDW0S_valid_SHIFT (0U)
3016#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
3017#define FMC_TAGVDW0S_tag_MASK (0x7FFE0U)
3018#define FMC_TAGVDW0S_tag_SHIFT (5U)
3019#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
3020/*! @} */
3021
3022/* The count of FMC_TAGVDW0S */
3023#define FMC_TAGVDW0S_COUNT (8U)
3024
3025/*! @name TAGVDW1S - Cache Tag Storage */
3026/*! @{ */
3027#define FMC_TAGVDW1S_valid_MASK (0x1U)
3028#define FMC_TAGVDW1S_valid_SHIFT (0U)
3029#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
3030#define FMC_TAGVDW1S_tag_MASK (0x7FFE0U)
3031#define FMC_TAGVDW1S_tag_SHIFT (5U)
3032#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
3033/*! @} */
3034
3035/* The count of FMC_TAGVDW1S */
3036#define FMC_TAGVDW1S_COUNT (8U)
3037
3038/*! @name TAGVDW2S - Cache Tag Storage */
3039/*! @{ */
3040#define FMC_TAGVDW2S_valid_MASK (0x1U)
3041#define FMC_TAGVDW2S_valid_SHIFT (0U)
3042#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
3043#define FMC_TAGVDW2S_tag_MASK (0x7FFE0U)
3044#define FMC_TAGVDW2S_tag_SHIFT (5U)
3045#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
3046/*! @} */
3047
3048/* The count of FMC_TAGVDW2S */
3049#define FMC_TAGVDW2S_COUNT (8U)
3050
3051/*! @name TAGVDW3S - Cache Tag Storage */
3052/*! @{ */
3053#define FMC_TAGVDW3S_valid_MASK (0x1U)
3054#define FMC_TAGVDW3S_valid_SHIFT (0U)
3055#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
3056#define FMC_TAGVDW3S_tag_MASK (0x7FFE0U)
3057#define FMC_TAGVDW3S_tag_SHIFT (5U)
3058#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
3059/*! @} */
3060
3061/* The count of FMC_TAGVDW3S */
3062#define FMC_TAGVDW3S_COUNT (8U)
3063
3064/*! @name DATA_U - Cache Data Storage (upper word) */
3065/*! @{ */
3066#define FMC_DATA_U_data_MASK (0xFFFFFFFFU)
3067#define FMC_DATA_U_data_SHIFT (0U)
3068#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
3069/*! @} */
3070
3071/* The count of FMC_DATA_U */
3072#define FMC_DATA_U_COUNT (4U)
3073
3074/* The count of FMC_DATA_U */
3075#define FMC_DATA_U_COUNT2 (8U)
3076
3077/*! @name DATA_L - Cache Data Storage (lower word) */
3078/*! @{ */
3079#define FMC_DATA_L_data_MASK (0xFFFFFFFFU)
3080#define FMC_DATA_L_data_SHIFT (0U)
3081#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
3082/*! @} */
3083
3084/* The count of FMC_DATA_L */
3085#define FMC_DATA_L_COUNT (4U)
3086
3087/* The count of FMC_DATA_L */
3088#define FMC_DATA_L_COUNT2 (8U)
3089
3090
3091/*!
3092 * @}
3093 */ /* end of group FMC_Register_Masks */
3094
3095
3096/* FMC - Peripheral instance base addresses */
3097/** Peripheral FMC base address */
3098#define FMC_BASE (0x4001F000u)
3099/** Peripheral FMC base pointer */
3100#define FMC ((FMC_Type *)FMC_BASE)
3101/** Array initializer of FMC peripheral base addresses */
3102#define FMC_BASE_ADDRS { FMC_BASE }
3103/** Array initializer of FMC peripheral base pointers */
3104#define FMC_BASE_PTRS { FMC }
3105
3106/*!
3107 * @}
3108 */ /* end of group FMC_Peripheral_Access_Layer */
3109
3110
3111/* ----------------------------------------------------------------------------
3112 -- FTFA Peripheral Access Layer
3113 ---------------------------------------------------------------------------- */
3114
3115/*!
3116 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
3117 * @{
3118 */
3119
3120/** FTFA - Register Layout Typedef */
3121typedef struct {
3122 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
3123 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
3124 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
3125 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
3126 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
3127 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
3128 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
3129 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
3130 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
3131 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
3132 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
3133 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
3134 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
3135 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
3136 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
3137 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
3138 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
3139 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
3140 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
3141 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
3142 uint8_t RESERVED_0[4];
3143 __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
3144 __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
3145 __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
3146 __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
3147 __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
3148 __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
3149 __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
3150 __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
3151 __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
3152 __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
3153 __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
3154 __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
3155 __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
3156 __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
3157 __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
3158 __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
3159 __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
3160 uint8_t RESERVED_1[2];
3161 __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
3162} FTFA_Type;
3163
3164/* ----------------------------------------------------------------------------
3165 -- FTFA Register Masks
3166 ---------------------------------------------------------------------------- */
3167
3168/*!
3169 * @addtogroup FTFA_Register_Masks FTFA Register Masks
3170 * @{
3171 */
3172
3173/*! @name FSTAT - Flash Status Register */
3174/*! @{ */
3175#define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
3176#define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
3177#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
3178#define FTFA_FSTAT_FPVIOL_MASK (0x10U)
3179#define FTFA_FSTAT_FPVIOL_SHIFT (4U)
3180/*! FPVIOL - Flash Protection Violation Flag
3181 * 0b0..No protection violation detected
3182 * 0b1..Protection violation detected
3183 */
3184#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
3185#define FTFA_FSTAT_ACCERR_MASK (0x20U)
3186#define FTFA_FSTAT_ACCERR_SHIFT (5U)
3187/*! ACCERR - Flash Access Error Flag
3188 * 0b0..No access error detected
3189 * 0b1..Access error detected
3190 */
3191#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
3192#define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
3193#define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
3194/*! RDCOLERR - Flash Read Collision Error Flag
3195 * 0b0..No collision error detected
3196 * 0b1..Collision error detected
3197 */
3198#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
3199#define FTFA_FSTAT_CCIF_MASK (0x80U)
3200#define FTFA_FSTAT_CCIF_SHIFT (7U)
3201/*! CCIF - Command Complete Interrupt Flag
3202 * 0b0..Flash command in progress
3203 * 0b1..Flash command has completed
3204 */
3205#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
3206/*! @} */
3207
3208/*! @name FCNFG - Flash Configuration Register */
3209/*! @{ */
3210#define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
3211#define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
3212/*! ERSSUSP - Erase Suspend
3213 * 0b0..No suspend requested
3214 * 0b1..Suspend the current Erase Flash Sector command execution.
3215 */
3216#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
3217#define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
3218#define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
3219/*! ERSAREQ - Erase All Request
3220 * 0b0..No request or request complete
3221 * 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.
3222 */
3223#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
3224#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
3225#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
3226/*! RDCOLLIE - Read Collision Error Interrupt Enable
3227 * 0b0..Read collision error interrupt disabled
3228 * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).
3229 */
3230#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
3231#define FTFA_FCNFG_CCIE_MASK (0x80U)
3232#define FTFA_FCNFG_CCIE_SHIFT (7U)
3233/*! CCIE - Command Complete Interrupt Enable
3234 * 0b0..Command complete interrupt disabled
3235 * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
3236 */
3237#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
3238/*! @} */
3239
3240/*! @name FSEC - Flash Security Register */
3241/*! @{ */
3242#define FTFA_FSEC_SEC_MASK (0x3U)
3243#define FTFA_FSEC_SEC_SHIFT (0U)
3244/*! SEC - Flash Security
3245 * 0b00..MCU security status is secure.
3246 * 0b01..MCU security status is secure.
3247 * 0b10..MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
3248 * 0b11..MCU security status is secure.
3249 */
3250#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
3251#define FTFA_FSEC_FSLACC_MASK (0xCU)
3252#define FTFA_FSEC_FSLACC_SHIFT (2U)
3253/*! FSLACC - Freescale Failure Analysis Access Code
3254 * 0b00..Freescale factory access granted
3255 * 0b01..Freescale factory access denied
3256 * 0b10..Freescale factory access denied
3257 * 0b11..Freescale factory access granted
3258 */
3259#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
3260#define FTFA_FSEC_MEEN_MASK (0x30U)
3261#define FTFA_FSEC_MEEN_SHIFT (4U)
3262/*! MEEN - Mass Erase Enable Bits
3263 * 0b00..Mass erase is enabled
3264 * 0b01..Mass erase is enabled
3265 * 0b10..Mass erase is disabled
3266 * 0b11..Mass erase is enabled
3267 */
3268#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
3269#define FTFA_FSEC_KEYEN_MASK (0xC0U)
3270#define FTFA_FSEC_KEYEN_SHIFT (6U)
3271/*! KEYEN - Backdoor Key Security Enable
3272 * 0b00..Backdoor key access disabled
3273 * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
3274 * 0b10..Backdoor key access enabled
3275 * 0b11..Backdoor key access disabled
3276 */
3277#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
3278/*! @} */
3279
3280/*! @name FOPT - Flash Option Register */
3281/*! @{ */
3282#define FTFA_FOPT_OPT_MASK (0xFFU)
3283#define FTFA_FOPT_OPT_SHIFT (0U)
3284#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
3285/*! @} */
3286
3287/*! @name FCCOB3 - Flash Common Command Object Registers */
3288/*! @{ */
3289#define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
3290#define FTFA_FCCOB3_CCOBn_SHIFT (0U)
3291#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
3292/*! @} */
3293
3294/*! @name FCCOB2 - Flash Common Command Object Registers */
3295/*! @{ */
3296#define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
3297#define FTFA_FCCOB2_CCOBn_SHIFT (0U)
3298#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
3299/*! @} */
3300
3301/*! @name FCCOB1 - Flash Common Command Object Registers */
3302/*! @{ */
3303#define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
3304#define FTFA_FCCOB1_CCOBn_SHIFT (0U)
3305#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
3306/*! @} */
3307
3308/*! @name FCCOB0 - Flash Common Command Object Registers */
3309/*! @{ */
3310#define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
3311#define FTFA_FCCOB0_CCOBn_SHIFT (0U)
3312#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
3313/*! @} */
3314
3315/*! @name FCCOB7 - Flash Common Command Object Registers */
3316/*! @{ */
3317#define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
3318#define FTFA_FCCOB7_CCOBn_SHIFT (0U)
3319#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
3320/*! @} */
3321
3322/*! @name FCCOB6 - Flash Common Command Object Registers */
3323/*! @{ */
3324#define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
3325#define FTFA_FCCOB6_CCOBn_SHIFT (0U)
3326#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
3327/*! @} */
3328
3329/*! @name FCCOB5 - Flash Common Command Object Registers */
3330/*! @{ */
3331#define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
3332#define FTFA_FCCOB5_CCOBn_SHIFT (0U)
3333#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
3334/*! @} */
3335
3336/*! @name FCCOB4 - Flash Common Command Object Registers */
3337/*! @{ */
3338#define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
3339#define FTFA_FCCOB4_CCOBn_SHIFT (0U)
3340#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
3341/*! @} */
3342
3343/*! @name FCCOBB - Flash Common Command Object Registers */
3344/*! @{ */
3345#define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
3346#define FTFA_FCCOBB_CCOBn_SHIFT (0U)
3347#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
3348/*! @} */
3349
3350/*! @name FCCOBA - Flash Common Command Object Registers */
3351/*! @{ */
3352#define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
3353#define FTFA_FCCOBA_CCOBn_SHIFT (0U)
3354#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
3355/*! @} */
3356
3357/*! @name FCCOB9 - Flash Common Command Object Registers */
3358/*! @{ */
3359#define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
3360#define FTFA_FCCOB9_CCOBn_SHIFT (0U)
3361#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
3362/*! @} */
3363
3364/*! @name FCCOB8 - Flash Common Command Object Registers */
3365/*! @{ */
3366#define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
3367#define FTFA_FCCOB8_CCOBn_SHIFT (0U)
3368#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
3369/*! @} */
3370
3371/*! @name FPROT3 - Program Flash Protection Registers */
3372/*! @{ */
3373#define FTFA_FPROT3_PROT_MASK (0xFFU)
3374#define FTFA_FPROT3_PROT_SHIFT (0U)
3375/*! PROT - Program Flash Region Protect
3376 * 0b00000000..Program flash region is protected.
3377 * 0b00000001..Program flash region is not protected
3378 */
3379#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
3380/*! @} */
3381
3382/*! @name FPROT2 - Program Flash Protection Registers */
3383/*! @{ */
3384#define FTFA_FPROT2_PROT_MASK (0xFFU)
3385#define FTFA_FPROT2_PROT_SHIFT (0U)
3386/*! PROT - Program Flash Region Protect
3387 * 0b00000000..Program flash region is protected.
3388 * 0b00000001..Program flash region is not protected
3389 */
3390#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
3391/*! @} */
3392
3393/*! @name FPROT1 - Program Flash Protection Registers */
3394/*! @{ */
3395#define FTFA_FPROT1_PROT_MASK (0xFFU)
3396#define FTFA_FPROT1_PROT_SHIFT (0U)
3397/*! PROT - Program Flash Region Protect
3398 * 0b00000000..Program flash region is protected.
3399 * 0b00000001..Program flash region is not protected
3400 */
3401#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
3402/*! @} */
3403
3404/*! @name FPROT0 - Program Flash Protection Registers */
3405/*! @{ */
3406#define FTFA_FPROT0_PROT_MASK (0xFFU)
3407#define FTFA_FPROT0_PROT_SHIFT (0U)
3408/*! PROT - Program Flash Region Protect
3409 * 0b00000000..Program flash region is protected.
3410 * 0b00000001..Program flash region is not protected
3411 */
3412#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
3413/*! @} */
3414
3415/*! @name XACCH3 - Execute-only Access Registers */
3416/*! @{ */
3417#define FTFA_XACCH3_XA_MASK (0xFFU)
3418#define FTFA_XACCH3_XA_SHIFT (0U)
3419/*! XA - Execute-only access control
3420 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3421 * 0b00000001..Associated segment is accessible as data or in execute mode
3422 */
3423#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK)
3424/*! @} */
3425
3426/*! @name XACCH2 - Execute-only Access Registers */
3427/*! @{ */
3428#define FTFA_XACCH2_XA_MASK (0xFFU)
3429#define FTFA_XACCH2_XA_SHIFT (0U)
3430/*! XA - Execute-only access control
3431 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3432 * 0b00000001..Associated segment is accessible as data or in execute mode
3433 */
3434#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK)
3435/*! @} */
3436
3437/*! @name XACCH1 - Execute-only Access Registers */
3438/*! @{ */
3439#define FTFA_XACCH1_XA_MASK (0xFFU)
3440#define FTFA_XACCH1_XA_SHIFT (0U)
3441/*! XA - Execute-only access control
3442 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3443 * 0b00000001..Associated segment is accessible as data or in execute mode
3444 */
3445#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK)
3446/*! @} */
3447
3448/*! @name XACCH0 - Execute-only Access Registers */
3449/*! @{ */
3450#define FTFA_XACCH0_XA_MASK (0xFFU)
3451#define FTFA_XACCH0_XA_SHIFT (0U)
3452/*! XA - Execute-only access control
3453 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3454 * 0b00000001..Associated segment is accessible as data or in execute mode
3455 */
3456#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK)
3457/*! @} */
3458
3459/*! @name XACCL3 - Execute-only Access Registers */
3460/*! @{ */
3461#define FTFA_XACCL3_XA_MASK (0xFFU)
3462#define FTFA_XACCL3_XA_SHIFT (0U)
3463/*! XA - Execute-only access control
3464 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3465 * 0b00000001..Associated segment is accessible as data or in execute mode
3466 */
3467#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK)
3468/*! @} */
3469
3470/*! @name XACCL2 - Execute-only Access Registers */
3471/*! @{ */
3472#define FTFA_XACCL2_XA_MASK (0xFFU)
3473#define FTFA_XACCL2_XA_SHIFT (0U)
3474/*! XA - Execute-only access control
3475 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3476 * 0b00000001..Associated segment is accessible as data or in execute mode
3477 */
3478#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK)
3479/*! @} */
3480
3481/*! @name XACCL1 - Execute-only Access Registers */
3482/*! @{ */
3483#define FTFA_XACCL1_XA_MASK (0xFFU)
3484#define FTFA_XACCL1_XA_SHIFT (0U)
3485/*! XA - Execute-only access control
3486 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3487 * 0b00000001..Associated segment is accessible as data or in execute mode
3488 */
3489#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK)
3490/*! @} */
3491
3492/*! @name XACCL0 - Execute-only Access Registers */
3493/*! @{ */
3494#define FTFA_XACCL0_XA_MASK (0xFFU)
3495#define FTFA_XACCL0_XA_SHIFT (0U)
3496/*! XA - Execute-only access control
3497 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
3498 * 0b00000001..Associated segment is accessible as data or in execute mode
3499 */
3500#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK)
3501/*! @} */
3502
3503/*! @name SACCH3 - Supervisor-only Access Registers */
3504/*! @{ */
3505#define FTFA_SACCH3_SA_MASK (0xFFU)
3506#define FTFA_SACCH3_SA_SHIFT (0U)
3507/*! SA - Supervisor-only access control
3508 * 0b00000000..Associated segment is accessible in supervisor mode only
3509 * 0b00000001..Associated segment is accessible in user or supervisor mode
3510 */
3511#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK)
3512/*! @} */
3513
3514/*! @name SACCH2 - Supervisor-only Access Registers */
3515/*! @{ */
3516#define FTFA_SACCH2_SA_MASK (0xFFU)
3517#define FTFA_SACCH2_SA_SHIFT (0U)
3518/*! SA - Supervisor-only access control
3519 * 0b00000000..Associated segment is accessible in supervisor mode only
3520 * 0b00000001..Associated segment is accessible in user or supervisor mode
3521 */
3522#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK)
3523/*! @} */
3524
3525/*! @name SACCH1 - Supervisor-only Access Registers */
3526/*! @{ */
3527#define FTFA_SACCH1_SA_MASK (0xFFU)
3528#define FTFA_SACCH1_SA_SHIFT (0U)
3529/*! SA - Supervisor-only access control
3530 * 0b00000000..Associated segment is accessible in supervisor mode only
3531 * 0b00000001..Associated segment is accessible in user or supervisor mode
3532 */
3533#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK)
3534/*! @} */
3535
3536/*! @name SACCH0 - Supervisor-only Access Registers */
3537/*! @{ */
3538#define FTFA_SACCH0_SA_MASK (0xFFU)
3539#define FTFA_SACCH0_SA_SHIFT (0U)
3540/*! SA - Supervisor-only access control
3541 * 0b00000000..Associated segment is accessible in supervisor mode only
3542 * 0b00000001..Associated segment is accessible in user or supervisor mode
3543 */
3544#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK)
3545/*! @} */
3546
3547/*! @name SACCL3 - Supervisor-only Access Registers */
3548/*! @{ */
3549#define FTFA_SACCL3_SA_MASK (0xFFU)
3550#define FTFA_SACCL3_SA_SHIFT (0U)
3551/*! SA - Supervisor-only access control
3552 * 0b00000000..Associated segment is accessible in supervisor mode only
3553 * 0b00000001..Associated segment is accessible in user or supervisor mode
3554 */
3555#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK)
3556/*! @} */
3557
3558/*! @name SACCL2 - Supervisor-only Access Registers */
3559/*! @{ */
3560#define FTFA_SACCL2_SA_MASK (0xFFU)
3561#define FTFA_SACCL2_SA_SHIFT (0U)
3562/*! SA - Supervisor-only access control
3563 * 0b00000000..Associated segment is accessible in supervisor mode only
3564 * 0b00000001..Associated segment is accessible in user or supervisor mode
3565 */
3566#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK)
3567/*! @} */
3568
3569/*! @name SACCL1 - Supervisor-only Access Registers */
3570/*! @{ */
3571#define FTFA_SACCL1_SA_MASK (0xFFU)
3572#define FTFA_SACCL1_SA_SHIFT (0U)
3573/*! SA - Supervisor-only access control
3574 * 0b00000000..Associated segment is accessible in supervisor mode only
3575 * 0b00000001..Associated segment is accessible in user or supervisor mode
3576 */
3577#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK)
3578/*! @} */
3579
3580/*! @name SACCL0 - Supervisor-only Access Registers */
3581/*! @{ */
3582#define FTFA_SACCL0_SA_MASK (0xFFU)
3583#define FTFA_SACCL0_SA_SHIFT (0U)
3584/*! SA - Supervisor-only access control
3585 * 0b00000000..Associated segment is accessible in supervisor mode only
3586 * 0b00000001..Associated segment is accessible in user or supervisor mode
3587 */
3588#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK)
3589/*! @} */
3590
3591/*! @name FACSS - Flash Access Segment Size Register */
3592/*! @{ */
3593#define FTFA_FACSS_SGSIZE_MASK (0xFFU)
3594#define FTFA_FACSS_SGSIZE_SHIFT (0U)
3595#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK)
3596/*! @} */
3597
3598/*! @name FACSN - Flash Access Segment Number Register */
3599/*! @{ */
3600#define FTFA_FACSN_NUMSG_MASK (0xFFU)
3601#define FTFA_FACSN_NUMSG_SHIFT (0U)
3602/*! NUMSG - Number of Segments Indicator
3603 * 0b00100000..Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes)
3604 * 0b00101000..Program flash memory is divided into 40 segments (160 Kbytes)
3605 * 0b01000000..Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes)
3606 */
3607#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK)
3608/*! @} */
3609
3610
3611/*!
3612 * @}
3613 */ /* end of group FTFA_Register_Masks */
3614
3615
3616/* FTFA - Peripheral instance base addresses */
3617/** Peripheral FTFA base address */
3618#define FTFA_BASE (0x40020000u)
3619/** Peripheral FTFA base pointer */
3620#define FTFA ((FTFA_Type *)FTFA_BASE)
3621/** Array initializer of FTFA peripheral base addresses */
3622#define FTFA_BASE_ADDRS { FTFA_BASE }
3623/** Array initializer of FTFA peripheral base pointers */
3624#define FTFA_BASE_PTRS { FTFA }
3625/** Interrupt vectors for the FTFA peripheral type */
3626#define FTFA_COMMAND_COMPLETE_IRQS { FTF_IRQn }
3627#define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn }
3628
3629/*!
3630 * @}
3631 */ /* end of group FTFA_Peripheral_Access_Layer */
3632
3633
3634/* ----------------------------------------------------------------------------
3635 -- FTM Peripheral Access Layer
3636 ---------------------------------------------------------------------------- */
3637
3638/*!
3639 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
3640 * @{
3641 */
3642
3643/** FTM - Register Layout Typedef */
3644typedef struct {
3645 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
3646 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
3647 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
3648 struct { /* offset: 0xC, array step: 0x8 */
3649 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
3650 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
3651 } CONTROLS[6];
3652 uint8_t RESERVED_0[16];
3653 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
3654 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
3655 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
3656 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
3657 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
3658 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
3659 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
3660 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
3661 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
3662 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
3663 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
3664 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
3665 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
3666 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
3667 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
3668 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
3669 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
3670 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
3671 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
3672 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
3673} FTM_Type;
3674
3675/* ----------------------------------------------------------------------------
3676 -- FTM Register Masks
3677 ---------------------------------------------------------------------------- */
3678
3679/*!
3680 * @addtogroup FTM_Register_Masks FTM Register Masks
3681 * @{
3682 */
3683
3684/*! @name SC - Status And Control */
3685/*! @{ */
3686#define FTM_SC_PS_MASK (0x7U)
3687#define FTM_SC_PS_SHIFT (0U)
3688/*! PS - Prescale Factor Selection
3689 * 0b000..Divide by 1
3690 * 0b001..Divide by 2
3691 * 0b010..Divide by 4
3692 * 0b011..Divide by 8
3693 * 0b100..Divide by 16
3694 * 0b101..Divide by 32
3695 * 0b110..Divide by 64
3696 * 0b111..Divide by 128
3697 */
3698#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
3699#define FTM_SC_CLKS_MASK (0x18U)
3700#define FTM_SC_CLKS_SHIFT (3U)
3701/*! CLKS - Clock Source Selection
3702 * 0b00..No clock selected. This in effect disables the FTM counter.
3703 * 0b01..System clock
3704 * 0b10..Fixed frequency clock
3705 * 0b11..External clock
3706 */
3707#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
3708#define FTM_SC_CPWMS_MASK (0x20U)
3709#define FTM_SC_CPWMS_SHIFT (5U)
3710/*! CPWMS - Center-Aligned PWM Select
3711 * 0b0..FTM counter operates in Up Counting mode.
3712 * 0b1..FTM counter operates in Up-Down Counting mode.
3713 */
3714#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
3715#define FTM_SC_TOIE_MASK (0x40U)
3716#define FTM_SC_TOIE_SHIFT (6U)
3717/*! TOIE - Timer Overflow Interrupt Enable
3718 * 0b0..Disable TOF interrupts. Use software polling.
3719 * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
3720 */
3721#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
3722#define FTM_SC_TOF_MASK (0x80U)
3723#define FTM_SC_TOF_SHIFT (7U)
3724/*! TOF - Timer Overflow Flag
3725 * 0b0..FTM counter has not overflowed.
3726 * 0b1..FTM counter has overflowed.
3727 */
3728#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
3729/*! @} */
3730
3731/*! @name CNT - Counter */
3732/*! @{ */
3733#define FTM_CNT_COUNT_MASK (0xFFFFU)
3734#define FTM_CNT_COUNT_SHIFT (0U)
3735#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
3736/*! @} */
3737
3738/*! @name MOD - Modulo */
3739/*! @{ */
3740#define FTM_MOD_MOD_MASK (0xFFFFU)
3741#define FTM_MOD_MOD_SHIFT (0U)
3742#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
3743/*! @} */
3744
3745/*! @name CnSC - Channel (n) Status And Control */
3746/*! @{ */
3747#define FTM_CnSC_DMA_MASK (0x1U)
3748#define FTM_CnSC_DMA_SHIFT (0U)
3749/*! DMA - DMA Enable
3750 * 0b0..Disable DMA transfers.
3751 * 0b1..Enable DMA transfers.
3752 */
3753#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
3754#define FTM_CnSC_ICRST_MASK (0x2U)
3755#define FTM_CnSC_ICRST_SHIFT (1U)
3756/*! ICRST - FTM counter reset by the selected input capture event.
3757 * 0b0..FTM counter is not reset when the selected channel (n) input event is detected.
3758 * 0b1..FTM counter is reset when the selected channel (n) input event is detected.
3759 */
3760#define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)
3761#define FTM_CnSC_ELSA_MASK (0x4U)
3762#define FTM_CnSC_ELSA_SHIFT (2U)
3763#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
3764#define FTM_CnSC_ELSB_MASK (0x8U)
3765#define FTM_CnSC_ELSB_SHIFT (3U)
3766#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
3767#define FTM_CnSC_MSA_MASK (0x10U)
3768#define FTM_CnSC_MSA_SHIFT (4U)
3769#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
3770#define FTM_CnSC_MSB_MASK (0x20U)
3771#define FTM_CnSC_MSB_SHIFT (5U)
3772#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
3773#define FTM_CnSC_CHIE_MASK (0x40U)
3774#define FTM_CnSC_CHIE_SHIFT (6U)
3775/*! CHIE - Channel Interrupt Enable
3776 * 0b0..Disable channel interrupts. Use software polling.
3777 * 0b1..Enable channel interrupts.
3778 */
3779#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
3780#define FTM_CnSC_CHF_MASK (0x80U)
3781#define FTM_CnSC_CHF_SHIFT (7U)
3782/*! CHF - Channel Flag
3783 * 0b0..No channel event has occurred.
3784 * 0b1..A channel event has occurred.
3785 */
3786#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
3787/*! @} */
3788
3789/* The count of FTM_CnSC */
3790#define FTM_CnSC_COUNT (6U)
3791
3792/*! @name CnV - Channel (n) Value */
3793/*! @{ */
3794#define FTM_CnV_VAL_MASK (0xFFFFU)
3795#define FTM_CnV_VAL_SHIFT (0U)
3796#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
3797/*! @} */
3798
3799/* The count of FTM_CnV */
3800#define FTM_CnV_COUNT (6U)
3801
3802/*! @name CNTIN - Counter Initial Value */
3803/*! @{ */
3804#define FTM_CNTIN_INIT_MASK (0xFFFFU)
3805#define FTM_CNTIN_INIT_SHIFT (0U)
3806#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
3807/*! @} */
3808
3809/*! @name STATUS - Capture And Compare Status */
3810/*! @{ */
3811#define FTM_STATUS_CH0F_MASK (0x1U)
3812#define FTM_STATUS_CH0F_SHIFT (0U)
3813/*! CH0F - Channel 0 Flag
3814 * 0b0..No channel event has occurred.
3815 * 0b1..A channel event has occurred.
3816 */
3817#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
3818#define FTM_STATUS_CH1F_MASK (0x2U)
3819#define FTM_STATUS_CH1F_SHIFT (1U)
3820/*! CH1F - Channel 1 Flag
3821 * 0b0..No channel event has occurred.
3822 * 0b1..A channel event has occurred.
3823 */
3824#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
3825#define FTM_STATUS_CH2F_MASK (0x4U)
3826#define FTM_STATUS_CH2F_SHIFT (2U)
3827/*! CH2F - Channel 2 Flag
3828 * 0b0..No channel event has occurred.
3829 * 0b1..A channel event has occurred.
3830 */
3831#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
3832#define FTM_STATUS_CH3F_MASK (0x8U)
3833#define FTM_STATUS_CH3F_SHIFT (3U)
3834/*! CH3F - Channel 3 Flag
3835 * 0b0..No channel event has occurred.
3836 * 0b1..A channel event has occurred.
3837 */
3838#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
3839#define FTM_STATUS_CH4F_MASK (0x10U)
3840#define FTM_STATUS_CH4F_SHIFT (4U)
3841/*! CH4F - Channel 4 Flag
3842 * 0b0..No channel event has occurred.
3843 * 0b1..A channel event has occurred.
3844 */
3845#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
3846#define FTM_STATUS_CH5F_MASK (0x20U)
3847#define FTM_STATUS_CH5F_SHIFT (5U)
3848/*! CH5F - Channel 5 Flag
3849 * 0b0..No channel event has occurred.
3850 * 0b1..A channel event has occurred.
3851 */
3852#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
3853#define FTM_STATUS_CH6F_MASK (0x40U)
3854#define FTM_STATUS_CH6F_SHIFT (6U)
3855/*! CH6F - Channel 6 Flag
3856 * 0b0..No channel event has occurred.
3857 * 0b1..A channel event has occurred.
3858 */
3859#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
3860#define FTM_STATUS_CH7F_MASK (0x80U)
3861#define FTM_STATUS_CH7F_SHIFT (7U)
3862/*! CH7F - Channel 7 Flag
3863 * 0b0..No channel event has occurred.
3864 * 0b1..A channel event has occurred.
3865 */
3866#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
3867/*! @} */
3868
3869/*! @name MODE - Features Mode Selection */
3870/*! @{ */
3871#define FTM_MODE_FTMEN_MASK (0x1U)
3872#define FTM_MODE_FTMEN_SHIFT (0U)
3873/*! FTMEN - FTM Enable
3874 * 0b0..Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.
3875 * 0b1..All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.
3876 */
3877#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
3878#define FTM_MODE_INIT_MASK (0x2U)
3879#define FTM_MODE_INIT_SHIFT (1U)
3880#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
3881#define FTM_MODE_WPDIS_MASK (0x4U)
3882#define FTM_MODE_WPDIS_SHIFT (2U)
3883/*! WPDIS - Write Protection Disable
3884 * 0b0..Write protection is enabled.
3885 * 0b1..Write protection is disabled.
3886 */
3887#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
3888#define FTM_MODE_PWMSYNC_MASK (0x8U)
3889#define FTM_MODE_PWMSYNC_SHIFT (3U)
3890/*! PWMSYNC - PWM Synchronization Mode
3891 * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
3892 * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
3893 */
3894#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
3895#define FTM_MODE_CAPTEST_MASK (0x10U)
3896#define FTM_MODE_CAPTEST_SHIFT (4U)
3897/*! CAPTEST - Capture Test Mode Enable
3898 * 0b0..Capture test mode is disabled.
3899 * 0b1..Capture test mode is enabled.
3900 */
3901#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
3902#define FTM_MODE_FAULTM_MASK (0x60U)
3903#define FTM_MODE_FAULTM_SHIFT (5U)
3904/*! FAULTM - Fault Control Mode
3905 * 0b00..Fault control is disabled for all channels.
3906 * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
3907 * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
3908 * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
3909 */
3910#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
3911#define FTM_MODE_FAULTIE_MASK (0x80U)
3912#define FTM_MODE_FAULTIE_SHIFT (7U)
3913/*! FAULTIE - Fault Interrupt Enable
3914 * 0b0..Fault control interrupt is disabled.
3915 * 0b1..Fault control interrupt is enabled.
3916 */
3917#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
3918/*! @} */
3919
3920/*! @name SYNC - Synchronization */
3921/*! @{ */
3922#define FTM_SYNC_CNTMIN_MASK (0x1U)
3923#define FTM_SYNC_CNTMIN_SHIFT (0U)
3924/*! CNTMIN - Minimum Loading Point Enable
3925 * 0b0..The minimum loading point is disabled.
3926 * 0b1..The minimum loading point is enabled.
3927 */
3928#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
3929#define FTM_SYNC_CNTMAX_MASK (0x2U)
3930#define FTM_SYNC_CNTMAX_SHIFT (1U)
3931/*! CNTMAX - Maximum Loading Point Enable
3932 * 0b0..The maximum loading point is disabled.
3933 * 0b1..The maximum loading point is enabled.
3934 */
3935#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
3936#define FTM_SYNC_REINIT_MASK (0x4U)
3937#define FTM_SYNC_REINIT_SHIFT (2U)
3938/*! REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
3939 * 0b0..FTM counter continues to count normally.
3940 * 0b1..FTM counter is updated with its initial value when the selected trigger is detected.
3941 */
3942#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
3943#define FTM_SYNC_SYNCHOM_MASK (0x8U)
3944#define FTM_SYNC_SYNCHOM_SHIFT (3U)
3945/*! SYNCHOM - Output Mask Synchronization
3946 * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
3947 * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
3948 */
3949#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
3950#define FTM_SYNC_TRIG0_MASK (0x10U)
3951#define FTM_SYNC_TRIG0_SHIFT (4U)
3952/*! TRIG0 - PWM Synchronization Hardware Trigger 0
3953 * 0b0..Trigger is disabled.
3954 * 0b1..Trigger is enabled.
3955 */
3956#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
3957#define FTM_SYNC_TRIG1_MASK (0x20U)
3958#define FTM_SYNC_TRIG1_SHIFT (5U)
3959/*! TRIG1 - PWM Synchronization Hardware Trigger 1
3960 * 0b0..Trigger is disabled.
3961 * 0b1..Trigger is enabled.
3962 */
3963#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
3964#define FTM_SYNC_TRIG2_MASK (0x40U)
3965#define FTM_SYNC_TRIG2_SHIFT (6U)
3966/*! TRIG2 - PWM Synchronization Hardware Trigger 2
3967 * 0b0..Trigger is disabled.
3968 * 0b1..Trigger is enabled.
3969 */
3970#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
3971#define FTM_SYNC_SWSYNC_MASK (0x80U)
3972#define FTM_SYNC_SWSYNC_SHIFT (7U)
3973/*! SWSYNC - PWM Synchronization Software Trigger
3974 * 0b0..Software trigger is not selected.
3975 * 0b1..Software trigger is selected.
3976 */
3977#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
3978/*! @} */
3979
3980/*! @name OUTINIT - Initial State For Channels Output */
3981/*! @{ */
3982#define FTM_OUTINIT_CH0OI_MASK (0x1U)
3983#define FTM_OUTINIT_CH0OI_SHIFT (0U)
3984/*! CH0OI - Channel 0 Output Initialization Value
3985 * 0b0..The initialization value is 0.
3986 * 0b1..The initialization value is 1.
3987 */
3988#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
3989#define FTM_OUTINIT_CH1OI_MASK (0x2U)
3990#define FTM_OUTINIT_CH1OI_SHIFT (1U)
3991/*! CH1OI - Channel 1 Output Initialization Value
3992 * 0b0..The initialization value is 0.
3993 * 0b1..The initialization value is 1.
3994 */
3995#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
3996#define FTM_OUTINIT_CH2OI_MASK (0x4U)
3997#define FTM_OUTINIT_CH2OI_SHIFT (2U)
3998/*! CH2OI - Channel 2 Output Initialization Value
3999 * 0b0..The initialization value is 0.
4000 * 0b1..The initialization value is 1.
4001 */
4002#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
4003#define FTM_OUTINIT_CH3OI_MASK (0x8U)
4004#define FTM_OUTINIT_CH3OI_SHIFT (3U)
4005/*! CH3OI - Channel 3 Output Initialization Value
4006 * 0b0..The initialization value is 0.
4007 * 0b1..The initialization value is 1.
4008 */
4009#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
4010#define FTM_OUTINIT_CH4OI_MASK (0x10U)
4011#define FTM_OUTINIT_CH4OI_SHIFT (4U)
4012/*! CH4OI - Channel 4 Output Initialization Value
4013 * 0b0..The initialization value is 0.
4014 * 0b1..The initialization value is 1.
4015 */
4016#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
4017#define FTM_OUTINIT_CH5OI_MASK (0x20U)
4018#define FTM_OUTINIT_CH5OI_SHIFT (5U)
4019/*! CH5OI - Channel 5 Output Initialization Value
4020 * 0b0..The initialization value is 0.
4021 * 0b1..The initialization value is 1.
4022 */
4023#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
4024#define FTM_OUTINIT_CH6OI_MASK (0x40U)
4025#define FTM_OUTINIT_CH6OI_SHIFT (6U)
4026/*! CH6OI - Channel 6 Output Initialization Value
4027 * 0b0..The initialization value is 0.
4028 * 0b1..The initialization value is 1.
4029 */
4030#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
4031#define FTM_OUTINIT_CH7OI_MASK (0x80U)
4032#define FTM_OUTINIT_CH7OI_SHIFT (7U)
4033/*! CH7OI - Channel 7 Output Initialization Value
4034 * 0b0..The initialization value is 0.
4035 * 0b1..The initialization value is 1.
4036 */
4037#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
4038/*! @} */
4039
4040/*! @name OUTMASK - Output Mask */
4041/*! @{ */
4042#define FTM_OUTMASK_CH0OM_MASK (0x1U)
4043#define FTM_OUTMASK_CH0OM_SHIFT (0U)
4044/*! CH0OM - Channel 0 Output Mask
4045 * 0b0..Channel output is not masked. It continues to operate normally.
4046 * 0b1..Channel output is masked. It is forced to its inactive state.
4047 */
4048#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
4049#define FTM_OUTMASK_CH1OM_MASK (0x2U)
4050#define FTM_OUTMASK_CH1OM_SHIFT (1U)
4051/*! CH1OM - Channel 1 Output Mask
4052 * 0b0..Channel output is not masked. It continues to operate normally.
4053 * 0b1..Channel output is masked. It is forced to its inactive state.
4054 */
4055#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
4056#define FTM_OUTMASK_CH2OM_MASK (0x4U)
4057#define FTM_OUTMASK_CH2OM_SHIFT (2U)
4058/*! CH2OM - Channel 2 Output Mask
4059 * 0b0..Channel output is not masked. It continues to operate normally.
4060 * 0b1..Channel output is masked. It is forced to its inactive state.
4061 */
4062#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
4063#define FTM_OUTMASK_CH3OM_MASK (0x8U)
4064#define FTM_OUTMASK_CH3OM_SHIFT (3U)
4065/*! CH3OM - Channel 3 Output Mask
4066 * 0b0..Channel output is not masked. It continues to operate normally.
4067 * 0b1..Channel output is masked. It is forced to its inactive state.
4068 */
4069#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
4070#define FTM_OUTMASK_CH4OM_MASK (0x10U)
4071#define FTM_OUTMASK_CH4OM_SHIFT (4U)
4072/*! CH4OM - Channel 4 Output Mask
4073 * 0b0..Channel output is not masked. It continues to operate normally.
4074 * 0b1..Channel output is masked. It is forced to its inactive state.
4075 */
4076#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
4077#define FTM_OUTMASK_CH5OM_MASK (0x20U)
4078#define FTM_OUTMASK_CH5OM_SHIFT (5U)
4079/*! CH5OM - Channel 5 Output Mask
4080 * 0b0..Channel output is not masked. It continues to operate normally.
4081 * 0b1..Channel output is masked. It is forced to its inactive state.
4082 */
4083#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
4084#define FTM_OUTMASK_CH6OM_MASK (0x40U)
4085#define FTM_OUTMASK_CH6OM_SHIFT (6U)
4086/*! CH6OM - Channel 6 Output Mask
4087 * 0b0..Channel output is not masked. It continues to operate normally.
4088 * 0b1..Channel output is masked. It is forced to its inactive state.
4089 */
4090#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
4091#define FTM_OUTMASK_CH7OM_MASK (0x80U)
4092#define FTM_OUTMASK_CH7OM_SHIFT (7U)
4093/*! CH7OM - Channel 7 Output Mask
4094 * 0b0..Channel output is not masked. It continues to operate normally.
4095 * 0b1..Channel output is masked. It is forced to its inactive state.
4096 */
4097#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
4098/*! @} */
4099
4100/*! @name COMBINE - Function For Linked Channels */
4101/*! @{ */
4102#define FTM_COMBINE_COMBINE0_MASK (0x1U)
4103#define FTM_COMBINE_COMBINE0_SHIFT (0U)
4104/*! COMBINE0 - Combine Channels For n = 0
4105 * 0b0..Channels (n) and (n+1) are independent.
4106 * 0b1..Channels (n) and (n+1) are combined.
4107 */
4108#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
4109#define FTM_COMBINE_COMP0_MASK (0x2U)
4110#define FTM_COMBINE_COMP0_SHIFT (1U)
4111/*! COMP0 - Complement Of Channel (n) For n = 0
4112 * 0b0..The channel (n+1) output is the same as the channel (n) output.
4113 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
4114 */
4115#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
4116#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
4117#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
4118/*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0
4119 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
4120 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
4121 */
4122#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
4123#define FTM_COMBINE_DECAP0_MASK (0x8U)
4124#define FTM_COMBINE_DECAP0_SHIFT (3U)
4125/*! DECAP0 - Dual Edge Capture Mode Captures For n = 0
4126 * 0b0..The dual edge captures are inactive.
4127 * 0b1..The dual edge captures are active.
4128 */
4129#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
4130#define FTM_COMBINE_DTEN0_MASK (0x10U)
4131#define FTM_COMBINE_DTEN0_SHIFT (4U)
4132/*! DTEN0 - Deadtime Enable For n = 0
4133 * 0b0..The deadtime insertion in this pair of channels is disabled.
4134 * 0b1..The deadtime insertion in this pair of channels is enabled.
4135 */
4136#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
4137#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
4138#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
4139/*! SYNCEN0 - Synchronization Enable For n = 0
4140 * 0b0..The PWM synchronization in this pair of channels is disabled.
4141 * 0b1..The PWM synchronization in this pair of channels is enabled.
4142 */
4143#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
4144#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
4145#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
4146/*! FAULTEN0 - Fault Control Enable For n = 0
4147 * 0b0..The fault control in this pair of channels is disabled.
4148 * 0b1..The fault control in this pair of channels is enabled.
4149 */
4150#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
4151#define FTM_COMBINE_COMBINE1_MASK (0x100U)
4152#define FTM_COMBINE_COMBINE1_SHIFT (8U)
4153/*! COMBINE1 - Combine Channels For n = 2
4154 * 0b0..Channels (n) and (n+1) are independent.
4155 * 0b1..Channels (n) and (n+1) are combined.
4156 */
4157#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
4158#define FTM_COMBINE_COMP1_MASK (0x200U)
4159#define FTM_COMBINE_COMP1_SHIFT (9U)
4160/*! COMP1 - Complement Of Channel (n) For n = 2
4161 * 0b0..The channel (n+1) output is the same as the channel (n) output.
4162 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
4163 */
4164#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
4165#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
4166#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
4167/*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2
4168 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
4169 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
4170 */
4171#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
4172#define FTM_COMBINE_DECAP1_MASK (0x800U)
4173#define FTM_COMBINE_DECAP1_SHIFT (11U)
4174/*! DECAP1 - Dual Edge Capture Mode Captures For n = 2
4175 * 0b0..The dual edge captures are inactive.
4176 * 0b1..The dual edge captures are active.
4177 */
4178#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
4179#define FTM_COMBINE_DTEN1_MASK (0x1000U)
4180#define FTM_COMBINE_DTEN1_SHIFT (12U)
4181/*! DTEN1 - Deadtime Enable For n = 2
4182 * 0b0..The deadtime insertion in this pair of channels is disabled.
4183 * 0b1..The deadtime insertion in this pair of channels is enabled.
4184 */
4185#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
4186#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
4187#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
4188/*! SYNCEN1 - Synchronization Enable For n = 2
4189 * 0b0..The PWM synchronization in this pair of channels is disabled.
4190 * 0b1..The PWM synchronization in this pair of channels is enabled.
4191 */
4192#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
4193#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
4194#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
4195/*! FAULTEN1 - Fault Control Enable For n = 2
4196 * 0b0..The fault control in this pair of channels is disabled.
4197 * 0b1..The fault control in this pair of channels is enabled.
4198 */
4199#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
4200#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
4201#define FTM_COMBINE_COMBINE2_SHIFT (16U)
4202/*! COMBINE2 - Combine Channels For n = 4
4203 * 0b0..Channels (n) and (n+1) are independent.
4204 * 0b1..Channels (n) and (n+1) are combined.
4205 */
4206#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
4207#define FTM_COMBINE_COMP2_MASK (0x20000U)
4208#define FTM_COMBINE_COMP2_SHIFT (17U)
4209/*! COMP2 - Complement Of Channel (n) For n = 4
4210 * 0b0..The channel (n+1) output is the same as the channel (n) output.
4211 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
4212 */
4213#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
4214#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
4215#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
4216/*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4
4217 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
4218 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
4219 */
4220#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
4221#define FTM_COMBINE_DECAP2_MASK (0x80000U)
4222#define FTM_COMBINE_DECAP2_SHIFT (19U)
4223/*! DECAP2 - Dual Edge Capture Mode Captures For n = 4
4224 * 0b0..The dual edge captures are inactive.
4225 * 0b1..The dual edge captures are active.
4226 */
4227#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
4228#define FTM_COMBINE_DTEN2_MASK (0x100000U)
4229#define FTM_COMBINE_DTEN2_SHIFT (20U)
4230/*! DTEN2 - Deadtime Enable For n = 4
4231 * 0b0..The deadtime insertion in this pair of channels is disabled.
4232 * 0b1..The deadtime insertion in this pair of channels is enabled.
4233 */
4234#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
4235#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
4236#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
4237/*! SYNCEN2 - Synchronization Enable For n = 4
4238 * 0b0..The PWM synchronization in this pair of channels is disabled.
4239 * 0b1..The PWM synchronization in this pair of channels is enabled.
4240 */
4241#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
4242#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
4243#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
4244/*! FAULTEN2 - Fault Control Enable For n = 4
4245 * 0b0..The fault control in this pair of channels is disabled.
4246 * 0b1..The fault control in this pair of channels is enabled.
4247 */
4248#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
4249#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
4250#define FTM_COMBINE_COMBINE3_SHIFT (24U)
4251/*! COMBINE3 - Combine Channels For n = 6
4252 * 0b0..Channels (n) and (n+1) are independent.
4253 * 0b1..Channels (n) and (n+1) are combined.
4254 */
4255#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
4256#define FTM_COMBINE_COMP3_MASK (0x2000000U)
4257#define FTM_COMBINE_COMP3_SHIFT (25U)
4258/*! COMP3 - Complement Of Channel (n) for n = 6
4259 * 0b0..The channel (n+1) output is the same as the channel (n) output.
4260 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
4261 */
4262#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
4263#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
4264#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
4265/*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6
4266 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
4267 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
4268 */
4269#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
4270#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
4271#define FTM_COMBINE_DECAP3_SHIFT (27U)
4272/*! DECAP3 - Dual Edge Capture Mode Captures For n = 6
4273 * 0b0..The dual edge captures are inactive.
4274 * 0b1..The dual edge captures are active.
4275 */
4276#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
4277#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
4278#define FTM_COMBINE_DTEN3_SHIFT (28U)
4279/*! DTEN3 - Deadtime Enable For n = 6
4280 * 0b0..The deadtime insertion in this pair of channels is disabled.
4281 * 0b1..The deadtime insertion in this pair of channels is enabled.
4282 */
4283#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
4284#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
4285#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
4286/*! SYNCEN3 - Synchronization Enable For n = 6
4287 * 0b0..The PWM synchronization in this pair of channels is disabled.
4288 * 0b1..The PWM synchronization in this pair of channels is enabled.
4289 */
4290#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
4291#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
4292#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
4293/*! FAULTEN3 - Fault Control Enable For n = 6
4294 * 0b0..The fault control in this pair of channels is disabled.
4295 * 0b1..The fault control in this pair of channels is enabled.
4296 */
4297#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
4298/*! @} */
4299
4300/*! @name DEADTIME - Deadtime Insertion Control */
4301/*! @{ */
4302#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
4303#define FTM_DEADTIME_DTVAL_SHIFT (0U)
4304#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
4305#define FTM_DEADTIME_DTPS_MASK (0xC0U)
4306#define FTM_DEADTIME_DTPS_SHIFT (6U)
4307/*! DTPS - Deadtime Prescaler Value
4308 * 0b0x..Divide the system clock by 1.
4309 * 0b10..Divide the system clock by 4.
4310 * 0b11..Divide the system clock by 16.
4311 */
4312#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
4313/*! @} */
4314
4315/*! @name EXTTRIG - FTM External Trigger */
4316/*! @{ */
4317#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
4318#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
4319/*! CH2TRIG - Channel 2 Trigger Enable
4320 * 0b0..The generation of the channel trigger is disabled.
4321 * 0b1..The generation of the channel trigger is enabled.
4322 */
4323#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
4324#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
4325#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
4326/*! CH3TRIG - Channel 3 Trigger Enable
4327 * 0b0..The generation of the channel trigger is disabled.
4328 * 0b1..The generation of the channel trigger is enabled.
4329 */
4330#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
4331#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
4332#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
4333/*! CH4TRIG - Channel 4 Trigger Enable
4334 * 0b0..The generation of the channel trigger is disabled.
4335 * 0b1..The generation of the channel trigger is enabled.
4336 */
4337#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
4338#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
4339#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
4340/*! CH5TRIG - Channel 5 Trigger Enable
4341 * 0b0..The generation of the channel trigger is disabled.
4342 * 0b1..The generation of the channel trigger is enabled.
4343 */
4344#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
4345#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
4346#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
4347/*! CH0TRIG - Channel 0 Trigger Enable
4348 * 0b0..The generation of the channel trigger is disabled.
4349 * 0b1..The generation of the channel trigger is enabled.
4350 */
4351#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
4352#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
4353#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
4354/*! CH1TRIG - Channel 1 Trigger Enable
4355 * 0b0..The generation of the channel trigger is disabled.
4356 * 0b1..The generation of the channel trigger is enabled.
4357 */
4358#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
4359#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
4360#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
4361/*! INITTRIGEN - Initialization Trigger Enable
4362 * 0b0..The generation of initialization trigger is disabled.
4363 * 0b1..The generation of initialization trigger is enabled.
4364 */
4365#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
4366#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
4367#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
4368/*! TRIGF - Channel Trigger Flag
4369 * 0b0..No channel trigger was generated.
4370 * 0b1..A channel trigger was generated.
4371 */
4372#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
4373/*! @} */
4374
4375/*! @name POL - Channels Polarity */
4376/*! @{ */
4377#define FTM_POL_POL0_MASK (0x1U)
4378#define FTM_POL_POL0_SHIFT (0U)
4379/*! POL0 - Channel 0 Polarity
4380 * 0b0..The channel polarity is active high.
4381 * 0b1..The channel polarity is active low.
4382 */
4383#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
4384#define FTM_POL_POL1_MASK (0x2U)
4385#define FTM_POL_POL1_SHIFT (1U)
4386/*! POL1 - Channel 1 Polarity
4387 * 0b0..The channel polarity is active high.
4388 * 0b1..The channel polarity is active low.
4389 */
4390#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
4391#define FTM_POL_POL2_MASK (0x4U)
4392#define FTM_POL_POL2_SHIFT (2U)
4393/*! POL2 - Channel 2 Polarity
4394 * 0b0..The channel polarity is active high.
4395 * 0b1..The channel polarity is active low.
4396 */
4397#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
4398#define FTM_POL_POL3_MASK (0x8U)
4399#define FTM_POL_POL3_SHIFT (3U)
4400/*! POL3 - Channel 3 Polarity
4401 * 0b0..The channel polarity is active high.
4402 * 0b1..The channel polarity is active low.
4403 */
4404#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
4405#define FTM_POL_POL4_MASK (0x10U)
4406#define FTM_POL_POL4_SHIFT (4U)
4407/*! POL4 - Channel 4 Polarity
4408 * 0b0..The channel polarity is active high.
4409 * 0b1..The channel polarity is active low.
4410 */
4411#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
4412#define FTM_POL_POL5_MASK (0x20U)
4413#define FTM_POL_POL5_SHIFT (5U)
4414/*! POL5 - Channel 5 Polarity
4415 * 0b0..The channel polarity is active high.
4416 * 0b1..The channel polarity is active low.
4417 */
4418#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
4419#define FTM_POL_POL6_MASK (0x40U)
4420#define FTM_POL_POL6_SHIFT (6U)
4421/*! POL6 - Channel 6 Polarity
4422 * 0b0..The channel polarity is active high.
4423 * 0b1..The channel polarity is active low.
4424 */
4425#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
4426#define FTM_POL_POL7_MASK (0x80U)
4427#define FTM_POL_POL7_SHIFT (7U)
4428/*! POL7 - Channel 7 Polarity
4429 * 0b0..The channel polarity is active high.
4430 * 0b1..The channel polarity is active low.
4431 */
4432#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
4433/*! @} */
4434
4435/*! @name FMS - Fault Mode Status */
4436/*! @{ */
4437#define FTM_FMS_FAULTF0_MASK (0x1U)
4438#define FTM_FMS_FAULTF0_SHIFT (0U)
4439/*! FAULTF0 - Fault Detection Flag 0
4440 * 0b0..No fault condition was detected at the fault input.
4441 * 0b1..A fault condition was detected at the fault input.
4442 */
4443#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
4444#define FTM_FMS_FAULTF1_MASK (0x2U)
4445#define FTM_FMS_FAULTF1_SHIFT (1U)
4446/*! FAULTF1 - Fault Detection Flag 1
4447 * 0b0..No fault condition was detected at the fault input.
4448 * 0b1..A fault condition was detected at the fault input.
4449 */
4450#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
4451#define FTM_FMS_FAULTF2_MASK (0x4U)
4452#define FTM_FMS_FAULTF2_SHIFT (2U)
4453/*! FAULTF2 - Fault Detection Flag 2
4454 * 0b0..No fault condition was detected at the fault input.
4455 * 0b1..A fault condition was detected at the fault input.
4456 */
4457#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
4458#define FTM_FMS_FAULTF3_MASK (0x8U)
4459#define FTM_FMS_FAULTF3_SHIFT (3U)
4460/*! FAULTF3 - Fault Detection Flag 3
4461 * 0b0..No fault condition was detected at the fault input.
4462 * 0b1..A fault condition was detected at the fault input.
4463 */
4464#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
4465#define FTM_FMS_FAULTIN_MASK (0x20U)
4466#define FTM_FMS_FAULTIN_SHIFT (5U)
4467/*! FAULTIN - Fault Inputs
4468 * 0b0..The logic OR of the enabled fault inputs is 0.
4469 * 0b1..The logic OR of the enabled fault inputs is 1.
4470 */
4471#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
4472#define FTM_FMS_WPEN_MASK (0x40U)
4473#define FTM_FMS_WPEN_SHIFT (6U)
4474/*! WPEN - Write Protection Enable
4475 * 0b0..Write protection is disabled. Write protected bits can be written.
4476 * 0b1..Write protection is enabled. Write protected bits cannot be written.
4477 */
4478#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
4479#define FTM_FMS_FAULTF_MASK (0x80U)
4480#define FTM_FMS_FAULTF_SHIFT (7U)
4481/*! FAULTF - Fault Detection Flag
4482 * 0b0..No fault condition was detected.
4483 * 0b1..A fault condition was detected.
4484 */
4485#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
4486/*! @} */
4487
4488/*! @name FILTER - Input Capture Filter Control */
4489/*! @{ */
4490#define FTM_FILTER_CH0FVAL_MASK (0xFU)
4491#define FTM_FILTER_CH0FVAL_SHIFT (0U)
4492#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
4493#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
4494#define FTM_FILTER_CH1FVAL_SHIFT (4U)
4495#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
4496#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
4497#define FTM_FILTER_CH2FVAL_SHIFT (8U)
4498#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
4499#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
4500#define FTM_FILTER_CH3FVAL_SHIFT (12U)
4501#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
4502/*! @} */
4503
4504/*! @name FLTCTRL - Fault Control */
4505/*! @{ */
4506#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
4507#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
4508/*! FAULT0EN - Fault Input 0 Enable
4509 * 0b0..Fault input is disabled.
4510 * 0b1..Fault input is enabled.
4511 */
4512#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
4513#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
4514#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
4515/*! FAULT1EN - Fault Input 1 Enable
4516 * 0b0..Fault input is disabled.
4517 * 0b1..Fault input is enabled.
4518 */
4519#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
4520#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
4521#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
4522/*! FAULT2EN - Fault Input 2 Enable
4523 * 0b0..Fault input is disabled.
4524 * 0b1..Fault input is enabled.
4525 */
4526#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
4527#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
4528#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
4529/*! FAULT3EN - Fault Input 3 Enable
4530 * 0b0..Fault input is disabled.
4531 * 0b1..Fault input is enabled.
4532 */
4533#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
4534#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
4535#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
4536/*! FFLTR0EN - Fault Input 0 Filter Enable
4537 * 0b0..Fault input filter is disabled.
4538 * 0b1..Fault input filter is enabled.
4539 */
4540#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
4541#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
4542#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
4543/*! FFLTR1EN - Fault Input 1 Filter Enable
4544 * 0b0..Fault input filter is disabled.
4545 * 0b1..Fault input filter is enabled.
4546 */
4547#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
4548#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
4549#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
4550/*! FFLTR2EN - Fault Input 2 Filter Enable
4551 * 0b0..Fault input filter is disabled.
4552 * 0b1..Fault input filter is enabled.
4553 */
4554#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
4555#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
4556#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
4557/*! FFLTR3EN - Fault Input 3 Filter Enable
4558 * 0b0..Fault input filter is disabled.
4559 * 0b1..Fault input filter is enabled.
4560 */
4561#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
4562#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
4563#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
4564#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
4565/*! @} */
4566
4567/*! @name QDCTRL - Quadrature Decoder Control And Status */
4568/*! @{ */
4569#define FTM_QDCTRL_QUADEN_MASK (0x1U)
4570#define FTM_QDCTRL_QUADEN_SHIFT (0U)
4571/*! QUADEN - Quadrature Decoder Mode Enable
4572 * 0b0..Quadrature Decoder mode is disabled.
4573 * 0b1..Quadrature Decoder mode is enabled.
4574 */
4575#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
4576#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
4577#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
4578/*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode
4579 * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
4580 * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
4581 */
4582#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
4583#define FTM_QDCTRL_QUADIR_MASK (0x4U)
4584#define FTM_QDCTRL_QUADIR_SHIFT (2U)
4585/*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode
4586 * 0b0..Counting direction is decreasing (FTM counter decrement).
4587 * 0b1..Counting direction is increasing (FTM counter increment).
4588 */
4589#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
4590#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
4591#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
4592/*! QUADMODE - Quadrature Decoder Mode
4593 * 0b0..Phase A and phase B encoding mode.
4594 * 0b1..Count and direction encoding mode.
4595 */
4596#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
4597#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
4598#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
4599/*! PHBPOL - Phase B Input Polarity
4600 * 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
4601 * 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
4602 */
4603#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
4604#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
4605#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
4606/*! PHAPOL - Phase A Input Polarity
4607 * 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
4608 * 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
4609 */
4610#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
4611#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
4612#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
4613/*! PHBFLTREN - Phase B Input Filter Enable
4614 * 0b0..Phase B input filter is disabled.
4615 * 0b1..Phase B input filter is enabled.
4616 */
4617#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
4618#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
4619#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
4620/*! PHAFLTREN - Phase A Input Filter Enable
4621 * 0b0..Phase A input filter is disabled.
4622 * 0b1..Phase A input filter is enabled.
4623 */
4624#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
4625/*! @} */
4626
4627/*! @name CONF - Configuration */
4628/*! @{ */
4629#define FTM_CONF_NUMTOF_MASK (0x1FU)
4630#define FTM_CONF_NUMTOF_SHIFT (0U)
4631#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
4632#define FTM_CONF_BDMMODE_MASK (0xC0U)
4633#define FTM_CONF_BDMMODE_SHIFT (6U)
4634#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
4635#define FTM_CONF_GTBEEN_MASK (0x200U)
4636#define FTM_CONF_GTBEEN_SHIFT (9U)
4637/*! GTBEEN - Global Time Base Enable
4638 * 0b0..Use of an external global time base is disabled.
4639 * 0b1..Use of an external global time base is enabled.
4640 */
4641#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
4642#define FTM_CONF_GTBEOUT_MASK (0x400U)
4643#define FTM_CONF_GTBEOUT_SHIFT (10U)
4644/*! GTBEOUT - Global Time Base Output
4645 * 0b0..A global time base signal generation is disabled.
4646 * 0b1..A global time base signal generation is enabled.
4647 */
4648#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
4649/*! @} */
4650
4651/*! @name FLTPOL - FTM Fault Input Polarity */
4652/*! @{ */
4653#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
4654#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
4655/*! FLT0POL - Fault Input 0 Polarity
4656 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
4657 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
4658 */
4659#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
4660#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
4661#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
4662/*! FLT1POL - Fault Input 1 Polarity
4663 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
4664 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
4665 */
4666#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
4667#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
4668#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
4669/*! FLT2POL - Fault Input 2 Polarity
4670 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
4671 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
4672 */
4673#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
4674#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
4675#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
4676/*! FLT3POL - Fault Input 3 Polarity
4677 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
4678 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
4679 */
4680#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
4681/*! @} */
4682
4683/*! @name SYNCONF - Synchronization Configuration */
4684/*! @{ */
4685#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
4686#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
4687/*! HWTRIGMODE - Hardware Trigger Mode
4688 * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
4689 * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
4690 */
4691#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
4692#define FTM_SYNCONF_CNTINC_MASK (0x4U)
4693#define FTM_SYNCONF_CNTINC_SHIFT (2U)
4694/*! CNTINC - CNTIN Register Synchronization
4695 * 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock.
4696 * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization.
4697 */
4698#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
4699#define FTM_SYNCONF_INVC_MASK (0x10U)
4700#define FTM_SYNCONF_INVC_SHIFT (4U)
4701/*! INVC - INVCTRL Register Synchronization
4702 * 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock.
4703 * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.
4704 */
4705#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
4706#define FTM_SYNCONF_SWOC_MASK (0x20U)
4707#define FTM_SYNCONF_SWOC_SHIFT (5U)
4708/*! SWOC - SWOCTRL Register Synchronization
4709 * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock.
4710 * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.
4711 */
4712#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
4713#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
4714#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
4715/*! SYNCMODE - Synchronization Mode
4716 * 0b0..Legacy PWM synchronization is selected.
4717 * 0b1..Enhanced PWM synchronization is selected.
4718 */
4719#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
4720#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
4721#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
4722/*! SWRSTCNT
4723 * 0b0..The software trigger does not activate the FTM counter synchronization.
4724 * 0b1..The software trigger activates the FTM counter synchronization.
4725 */
4726#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
4727#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
4728#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
4729/*! SWWRBUF
4730 * 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
4731 * 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization.
4732 */
4733#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
4734#define FTM_SYNCONF_SWOM_MASK (0x400U)
4735#define FTM_SYNCONF_SWOM_SHIFT (10U)
4736/*! SWOM
4737 * 0b0..The software trigger does not activate the OUTMASK register synchronization.
4738 * 0b1..The software trigger activates the OUTMASK register synchronization.
4739 */
4740#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
4741#define FTM_SYNCONF_SWINVC_MASK (0x800U)
4742#define FTM_SYNCONF_SWINVC_SHIFT (11U)
4743/*! SWINVC
4744 * 0b0..The software trigger does not activate the INVCTRL register synchronization.
4745 * 0b1..The software trigger activates the INVCTRL register synchronization.
4746 */
4747#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
4748#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
4749#define FTM_SYNCONF_SWSOC_SHIFT (12U)
4750/*! SWSOC
4751 * 0b0..The software trigger does not activate the SWOCTRL register synchronization.
4752 * 0b1..The software trigger activates the SWOCTRL register synchronization.
4753 */
4754#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
4755#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
4756#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
4757/*! HWRSTCNT
4758 * 0b0..A hardware trigger does not activate the FTM counter synchronization.
4759 * 0b1..A hardware trigger activates the FTM counter synchronization.
4760 */
4761#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
4762#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
4763#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
4764/*! HWWRBUF
4765 * 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
4766 * 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
4767 */
4768#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
4769#define FTM_SYNCONF_HWOM_MASK (0x40000U)
4770#define FTM_SYNCONF_HWOM_SHIFT (18U)
4771/*! HWOM
4772 * 0b0..A hardware trigger does not activate the OUTMASK register synchronization.
4773 * 0b1..A hardware trigger activates the OUTMASK register synchronization.
4774 */
4775#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
4776#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
4777#define FTM_SYNCONF_HWINVC_SHIFT (19U)
4778/*! HWINVC
4779 * 0b0..A hardware trigger does not activate the INVCTRL register synchronization.
4780 * 0b1..A hardware trigger activates the INVCTRL register synchronization.
4781 */
4782#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
4783#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
4784#define FTM_SYNCONF_HWSOC_SHIFT (20U)
4785/*! HWSOC
4786 * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization.
4787 * 0b1..A hardware trigger activates the SWOCTRL register synchronization.
4788 */
4789#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
4790/*! @} */
4791
4792/*! @name INVCTRL - FTM Inverting Control */
4793/*! @{ */
4794#define FTM_INVCTRL_INV0EN_MASK (0x1U)
4795#define FTM_INVCTRL_INV0EN_SHIFT (0U)
4796/*! INV0EN - Pair Channels 0 Inverting Enable
4797 * 0b0..Inverting is disabled.
4798 * 0b1..Inverting is enabled.
4799 */
4800#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
4801#define FTM_INVCTRL_INV1EN_MASK (0x2U)
4802#define FTM_INVCTRL_INV1EN_SHIFT (1U)
4803/*! INV1EN - Pair Channels 1 Inverting Enable
4804 * 0b0..Inverting is disabled.
4805 * 0b1..Inverting is enabled.
4806 */
4807#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
4808#define FTM_INVCTRL_INV2EN_MASK (0x4U)
4809#define FTM_INVCTRL_INV2EN_SHIFT (2U)
4810/*! INV2EN - Pair Channels 2 Inverting Enable
4811 * 0b0..Inverting is disabled.
4812 * 0b1..Inverting is enabled.
4813 */
4814#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
4815#define FTM_INVCTRL_INV3EN_MASK (0x8U)
4816#define FTM_INVCTRL_INV3EN_SHIFT (3U)
4817/*! INV3EN - Pair Channels 3 Inverting Enable
4818 * 0b0..Inverting is disabled.
4819 * 0b1..Inverting is enabled.
4820 */
4821#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
4822/*! @} */
4823
4824/*! @name SWOCTRL - FTM Software Output Control */
4825/*! @{ */
4826#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
4827#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
4828/*! CH0OC - Channel 0 Software Output Control Enable
4829 * 0b0..The channel output is not affected by software output control.
4830 * 0b1..The channel output is affected by software output control.
4831 */
4832#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
4833#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
4834#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
4835/*! CH1OC - Channel 1 Software Output Control Enable
4836 * 0b0..The channel output is not affected by software output control.
4837 * 0b1..The channel output is affected by software output control.
4838 */
4839#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
4840#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
4841#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
4842/*! CH2OC - Channel 2 Software Output Control Enable
4843 * 0b0..The channel output is not affected by software output control.
4844 * 0b1..The channel output is affected by software output control.
4845 */
4846#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
4847#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
4848#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
4849/*! CH3OC - Channel 3 Software Output Control Enable
4850 * 0b0..The channel output is not affected by software output control.
4851 * 0b1..The channel output is affected by software output control.
4852 */
4853#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
4854#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
4855#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
4856/*! CH4OC - Channel 4 Software Output Control Enable
4857 * 0b0..The channel output is not affected by software output control.
4858 * 0b1..The channel output is affected by software output control.
4859 */
4860#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
4861#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
4862#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
4863/*! CH5OC - Channel 5 Software Output Control Enable
4864 * 0b0..The channel output is not affected by software output control.
4865 * 0b1..The channel output is affected by software output control.
4866 */
4867#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
4868#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
4869#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
4870/*! CH6OC - Channel 6 Software Output Control Enable
4871 * 0b0..The channel output is not affected by software output control.
4872 * 0b1..The channel output is affected by software output control.
4873 */
4874#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
4875#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
4876#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
4877/*! CH7OC - Channel 7 Software Output Control Enable
4878 * 0b0..The channel output is not affected by software output control.
4879 * 0b1..The channel output is affected by software output control.
4880 */
4881#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
4882#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
4883#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
4884/*! CH0OCV - Channel 0 Software Output Control Value
4885 * 0b0..The software output control forces 0 to the channel output.
4886 * 0b1..The software output control forces 1 to the channel output.
4887 */
4888#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
4889#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
4890#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
4891/*! CH1OCV - Channel 1 Software Output Control Value
4892 * 0b0..The software output control forces 0 to the channel output.
4893 * 0b1..The software output control forces 1 to the channel output.
4894 */
4895#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
4896#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
4897#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
4898/*! CH2OCV - Channel 2 Software Output Control Value
4899 * 0b0..The software output control forces 0 to the channel output.
4900 * 0b1..The software output control forces 1 to the channel output.
4901 */
4902#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
4903#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
4904#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
4905/*! CH3OCV - Channel 3 Software Output Control Value
4906 * 0b0..The software output control forces 0 to the channel output.
4907 * 0b1..The software output control forces 1 to the channel output.
4908 */
4909#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
4910#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
4911#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
4912/*! CH4OCV - Channel 4 Software Output Control Value
4913 * 0b0..The software output control forces 0 to the channel output.
4914 * 0b1..The software output control forces 1 to the channel output.
4915 */
4916#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
4917#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
4918#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
4919/*! CH5OCV - Channel 5 Software Output Control Value
4920 * 0b0..The software output control forces 0 to the channel output.
4921 * 0b1..The software output control forces 1 to the channel output.
4922 */
4923#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
4924#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
4925#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
4926/*! CH6OCV - Channel 6 Software Output Control Value
4927 * 0b0..The software output control forces 0 to the channel output.
4928 * 0b1..The software output control forces 1 to the channel output.
4929 */
4930#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
4931#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
4932#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
4933/*! CH7OCV - Channel 7 Software Output Control Value
4934 * 0b0..The software output control forces 0 to the channel output.
4935 * 0b1..The software output control forces 1 to the channel output.
4936 */
4937#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
4938/*! @} */
4939
4940/*! @name PWMLOAD - FTM PWM Load */
4941/*! @{ */
4942#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
4943#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
4944/*! CH0SEL - Channel 0 Select
4945 * 0b0..Do not include the channel in the matching process.
4946 * 0b1..Include the channel in the matching process.
4947 */
4948#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
4949#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
4950#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
4951/*! CH1SEL - Channel 1 Select
4952 * 0b0..Do not include the channel in the matching process.
4953 * 0b1..Include the channel in the matching process.
4954 */
4955#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
4956#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
4957#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
4958/*! CH2SEL - Channel 2 Select
4959 * 0b0..Do not include the channel in the matching process.
4960 * 0b1..Include the channel in the matching process.
4961 */
4962#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
4963#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
4964#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
4965/*! CH3SEL - Channel 3 Select
4966 * 0b0..Do not include the channel in the matching process.
4967 * 0b1..Include the channel in the matching process.
4968 */
4969#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
4970#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
4971#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
4972/*! CH4SEL - Channel 4 Select
4973 * 0b0..Do not include the channel in the matching process.
4974 * 0b1..Include the channel in the matching process.
4975 */
4976#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
4977#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
4978#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
4979/*! CH5SEL - Channel 5 Select
4980 * 0b0..Do not include the channel in the matching process.
4981 * 0b1..Include the channel in the matching process.
4982 */
4983#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
4984#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
4985#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
4986/*! CH6SEL - Channel 6 Select
4987 * 0b0..Do not include the channel in the matching process.
4988 * 0b1..Include the channel in the matching process.
4989 */
4990#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
4991#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
4992#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
4993/*! CH7SEL - Channel 7 Select
4994 * 0b0..Do not include the channel in the matching process.
4995 * 0b1..Include the channel in the matching process.
4996 */
4997#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
4998#define FTM_PWMLOAD_LDOK_MASK (0x200U)
4999#define FTM_PWMLOAD_LDOK_SHIFT (9U)
5000/*! LDOK - Load Enable
5001 * 0b0..Loading updated values is disabled.
5002 * 0b1..Loading updated values is enabled.
5003 */
5004#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
5005/*! @} */
5006
5007
5008/*!
5009 * @}
5010 */ /* end of group FTM_Register_Masks */
5011
5012
5013/* FTM - Peripheral instance base addresses */
5014/** Peripheral FTM0 base address */
5015#define FTM0_BASE (0x40038000u)
5016/** Peripheral FTM0 base pointer */
5017#define FTM0 ((FTM_Type *)FTM0_BASE)
5018/** Peripheral FTM1 base address */
5019#define FTM1_BASE (0x40039000u)
5020/** Peripheral FTM1 base pointer */
5021#define FTM1 ((FTM_Type *)FTM1_BASE)
5022/** Peripheral FTM2 base address */
5023#define FTM2_BASE (0x4003A000u)
5024/** Peripheral FTM2 base pointer */
5025#define FTM2 ((FTM_Type *)FTM2_BASE)
5026/** Array initializer of FTM peripheral base addresses */
5027#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE }
5028/** Array initializer of FTM peripheral base pointers */
5029#define FTM_BASE_PTRS { FTM0, FTM1, FTM2 }
5030/** Interrupt vectors for the FTM peripheral type */
5031#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn }
5032
5033/*!
5034 * @}
5035 */ /* end of group FTM_Peripheral_Access_Layer */
5036
5037
5038/* ----------------------------------------------------------------------------
5039 -- GPIO Peripheral Access Layer
5040 ---------------------------------------------------------------------------- */
5041
5042/*!
5043 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
5044 * @{
5045 */
5046
5047/** GPIO - Register Layout Typedef */
5048typedef struct {
5049 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
5050 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
5051 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
5052 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
5053 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
5054 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
5055} GPIO_Type;
5056
5057/* ----------------------------------------------------------------------------
5058 -- GPIO Register Masks
5059 ---------------------------------------------------------------------------- */
5060
5061/*!
5062 * @addtogroup GPIO_Register_Masks GPIO Register Masks
5063 * @{
5064 */
5065
5066/*! @name PDOR - Port Data Output Register */
5067/*! @{ */
5068#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
5069#define GPIO_PDOR_PDO_SHIFT (0U)
5070/*! PDO - Port Data Output
5071 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
5072 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
5073 */
5074#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
5075/*! @} */
5076
5077/*! @name PSOR - Port Set Output Register */
5078/*! @{ */
5079#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
5080#define GPIO_PSOR_PTSO_SHIFT (0U)
5081/*! PTSO - Port Set Output
5082 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
5083 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1.
5084 */
5085#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
5086/*! @} */
5087
5088/*! @name PCOR - Port Clear Output Register */
5089/*! @{ */
5090#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
5091#define GPIO_PCOR_PTCO_SHIFT (0U)
5092/*! PTCO - Port Clear Output
5093 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
5094 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0.
5095 */
5096#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
5097/*! @} */
5098
5099/*! @name PTOR - Port Toggle Output Register */
5100/*! @{ */
5101#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
5102#define GPIO_PTOR_PTTO_SHIFT (0U)
5103/*! PTTO - Port Toggle Output
5104 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
5105 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state.
5106 */
5107#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
5108/*! @} */
5109
5110/*! @name PDIR - Port Data Input Register */
5111/*! @{ */
5112#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
5113#define GPIO_PDIR_PDI_SHIFT (0U)
5114/*! PDI - Port Data Input
5115 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function.
5116 * 0b00000000000000000000000000000001..Pin logic level is logic 1.
5117 */
5118#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
5119/*! @} */
5120
5121/*! @name PDDR - Port Data Direction Register */
5122/*! @{ */
5123#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
5124#define GPIO_PDDR_PDD_SHIFT (0U)
5125/*! PDD - Port Data Direction
5126 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function.
5127 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function.
5128 */
5129#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
5130/*! @} */
5131
5132
5133/*!
5134 * @}
5135 */ /* end of group GPIO_Register_Masks */
5136
5137
5138/* GPIO - Peripheral instance base addresses */
5139/** Peripheral GPIOA base address */
5140#define GPIOA_BASE (0x400FF000u)
5141/** Peripheral GPIOA base pointer */
5142#define GPIOA ((GPIO_Type *)GPIOA_BASE)
5143/** Peripheral GPIOB base address */
5144#define GPIOB_BASE (0x400FF040u)
5145/** Peripheral GPIOB base pointer */
5146#define GPIOB ((GPIO_Type *)GPIOB_BASE)
5147/** Peripheral GPIOC base address */
5148#define GPIOC_BASE (0x400FF080u)
5149/** Peripheral GPIOC base pointer */
5150#define GPIOC ((GPIO_Type *)GPIOC_BASE)
5151/** Peripheral GPIOD base address */
5152#define GPIOD_BASE (0x400FF0C0u)
5153/** Peripheral GPIOD base pointer */
5154#define GPIOD ((GPIO_Type *)GPIOD_BASE)
5155/** Peripheral GPIOE base address */
5156#define GPIOE_BASE (0x400FF100u)
5157/** Peripheral GPIOE base pointer */
5158#define GPIOE ((GPIO_Type *)GPIOE_BASE)
5159/** Array initializer of GPIO peripheral base addresses */
5160#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
5161/** Array initializer of GPIO peripheral base pointers */
5162#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
5163
5164/*!
5165 * @}
5166 */ /* end of group GPIO_Peripheral_Access_Layer */
5167
5168
5169/* ----------------------------------------------------------------------------
5170 -- I2C Peripheral Access Layer
5171 ---------------------------------------------------------------------------- */
5172
5173/*!
5174 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
5175 * @{
5176 */
5177
5178/** I2C - Register Layout Typedef */
5179typedef struct {
5180 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
5181 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
5182 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
5183 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
5184 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
5185 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
5186 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
5187 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
5188 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
5189 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
5190 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
5191 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
5192} I2C_Type;
5193
5194/* ----------------------------------------------------------------------------
5195 -- I2C Register Masks
5196 ---------------------------------------------------------------------------- */
5197
5198/*!
5199 * @addtogroup I2C_Register_Masks I2C Register Masks
5200 * @{
5201 */
5202
5203/*! @name A1 - I2C Address Register 1 */
5204/*! @{ */
5205#define I2C_A1_AD_MASK (0xFEU)
5206#define I2C_A1_AD_SHIFT (1U)
5207#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
5208/*! @} */
5209
5210/*! @name F - I2C Frequency Divider register */
5211/*! @{ */
5212#define I2C_F_ICR_MASK (0x3FU)
5213#define I2C_F_ICR_SHIFT (0U)
5214#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
5215#define I2C_F_MULT_MASK (0xC0U)
5216#define I2C_F_MULT_SHIFT (6U)
5217/*! MULT - Multiplier Factor
5218 * 0b00..mul = 1
5219 * 0b01..mul = 2
5220 * 0b10..mul = 4
5221 * 0b11..Reserved
5222 */
5223#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
5224/*! @} */
5225
5226/*! @name C1 - I2C Control Register 1 */
5227/*! @{ */
5228#define I2C_C1_DMAEN_MASK (0x1U)
5229#define I2C_C1_DMAEN_SHIFT (0U)
5230/*! DMAEN - DMA Enable
5231 * 0b0..All DMA signalling disabled.
5232 * 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
5233 */
5234#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
5235#define I2C_C1_WUEN_MASK (0x2U)
5236#define I2C_C1_WUEN_SHIFT (1U)
5237/*! WUEN - Wakeup Enable
5238 * 0b0..Normal operation. No interrupt generated when address matching in low power mode.
5239 * 0b1..Enables the wakeup function in low power mode.
5240 */
5241#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
5242#define I2C_C1_RSTA_MASK (0x4U)
5243#define I2C_C1_RSTA_SHIFT (2U)
5244#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
5245#define I2C_C1_TXAK_MASK (0x8U)
5246#define I2C_C1_TXAK_SHIFT (3U)
5247/*! TXAK - Transmit Acknowledge Enable
5248 * 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
5249 * 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
5250 */
5251#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
5252#define I2C_C1_TX_MASK (0x10U)
5253#define I2C_C1_TX_SHIFT (4U)
5254/*! TX - Transmit Mode Select
5255 * 0b0..Receive
5256 * 0b1..Transmit
5257 */
5258#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
5259#define I2C_C1_MST_MASK (0x20U)
5260#define I2C_C1_MST_SHIFT (5U)
5261/*! MST - Master Mode Select
5262 * 0b0..Slave mode
5263 * 0b1..Master mode
5264 */
5265#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
5266#define I2C_C1_IICIE_MASK (0x40U)
5267#define I2C_C1_IICIE_SHIFT (6U)
5268/*! IICIE - I2C Interrupt Enable
5269 * 0b0..Disabled
5270 * 0b1..Enabled
5271 */
5272#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
5273#define I2C_C1_IICEN_MASK (0x80U)
5274#define I2C_C1_IICEN_SHIFT (7U)
5275/*! IICEN - I2C Enable
5276 * 0b0..Disabled
5277 * 0b1..Enabled
5278 */
5279#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
5280/*! @} */
5281
5282/*! @name S - I2C Status register */
5283/*! @{ */
5284#define I2C_S_RXAK_MASK (0x1U)
5285#define I2C_S_RXAK_SHIFT (0U)
5286/*! RXAK - Receive Acknowledge
5287 * 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus
5288 * 0b1..No acknowledge signal detected
5289 */
5290#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
5291#define I2C_S_IICIF_MASK (0x2U)
5292#define I2C_S_IICIF_SHIFT (1U)
5293/*! IICIF - Interrupt Flag
5294 * 0b0..No interrupt pending
5295 * 0b1..Interrupt pending
5296 */
5297#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
5298#define I2C_S_SRW_MASK (0x4U)
5299#define I2C_S_SRW_SHIFT (2U)
5300/*! SRW - Slave Read/Write
5301 * 0b0..Slave receive, master writing to slave
5302 * 0b1..Slave transmit, master reading from slave
5303 */
5304#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
5305#define I2C_S_RAM_MASK (0x8U)
5306#define I2C_S_RAM_SHIFT (3U)
5307/*! RAM - Range Address Match
5308 * 0b0..Not addressed
5309 * 0b1..Addressed as a slave
5310 */
5311#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
5312#define I2C_S_ARBL_MASK (0x10U)
5313#define I2C_S_ARBL_SHIFT (4U)
5314/*! ARBL - Arbitration Lost
5315 * 0b0..Standard bus operation.
5316 * 0b1..Loss of arbitration.
5317 */
5318#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
5319#define I2C_S_BUSY_MASK (0x20U)
5320#define I2C_S_BUSY_SHIFT (5U)
5321/*! BUSY - Bus Busy
5322 * 0b0..Bus is idle
5323 * 0b1..Bus is busy
5324 */
5325#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
5326#define I2C_S_IAAS_MASK (0x40U)
5327#define I2C_S_IAAS_SHIFT (6U)
5328/*! IAAS - Addressed As A Slave
5329 * 0b0..Not addressed
5330 * 0b1..Addressed as a slave
5331 */
5332#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
5333#define I2C_S_TCF_MASK (0x80U)
5334#define I2C_S_TCF_SHIFT (7U)
5335/*! TCF - Transfer Complete Flag
5336 * 0b0..Transfer in progress
5337 * 0b1..Transfer complete
5338 */
5339#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
5340/*! @} */
5341
5342/*! @name D - I2C Data I/O register */
5343/*! @{ */
5344#define I2C_D_DATA_MASK (0xFFU)
5345#define I2C_D_DATA_SHIFT (0U)
5346#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
5347/*! @} */
5348
5349/*! @name C2 - I2C Control Register 2 */
5350/*! @{ */
5351#define I2C_C2_AD_MASK (0x7U)
5352#define I2C_C2_AD_SHIFT (0U)
5353#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
5354#define I2C_C2_RMEN_MASK (0x8U)
5355#define I2C_C2_RMEN_SHIFT (3U)
5356/*! RMEN - Range Address Matching Enable
5357 * 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
5358 * 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
5359 */
5360#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
5361#define I2C_C2_SBRC_MASK (0x10U)
5362#define I2C_C2_SBRC_SHIFT (4U)
5363/*! SBRC - Slave Baud Rate Control
5364 * 0b0..The slave baud rate follows the master baud rate and clock stretching may occur
5365 * 0b1..Slave baud rate is independent of the master baud rate
5366 */
5367#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
5368#define I2C_C2_HDRS_MASK (0x20U)
5369#define I2C_C2_HDRS_SHIFT (5U)
5370/*! HDRS - High Drive Select
5371 * 0b0..Normal drive mode
5372 * 0b1..High drive mode
5373 */
5374#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
5375#define I2C_C2_ADEXT_MASK (0x40U)
5376#define I2C_C2_ADEXT_SHIFT (6U)
5377/*! ADEXT - Address Extension
5378 * 0b0..7-bit address scheme
5379 * 0b1..10-bit address scheme
5380 */
5381#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
5382#define I2C_C2_GCAEN_MASK (0x80U)
5383#define I2C_C2_GCAEN_SHIFT (7U)
5384/*! GCAEN - General Call Address Enable
5385 * 0b0..Disabled
5386 * 0b1..Enabled
5387 */
5388#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
5389/*! @} */
5390
5391/*! @name FLT - I2C Programmable Input Glitch Filter register */
5392/*! @{ */
5393#define I2C_FLT_FLT_MASK (0xFU)
5394#define I2C_FLT_FLT_SHIFT (0U)
5395/*! FLT - I2C Programmable Filter Factor
5396 * 0b0000..No filter/bypass
5397 */
5398#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
5399#define I2C_FLT_STARTF_MASK (0x10U)
5400#define I2C_FLT_STARTF_SHIFT (4U)
5401/*! STARTF - I2C Bus Start Detect Flag
5402 * 0b0..No start happens on I2C bus
5403 * 0b1..Start detected on I2C bus
5404 */
5405#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
5406#define I2C_FLT_SSIE_MASK (0x20U)
5407#define I2C_FLT_SSIE_SHIFT (5U)
5408/*! SSIE - I2C Bus Stop or Start Interrupt Enable
5409 * 0b0..Stop or start detection interrupt is disabled
5410 * 0b1..Stop or start detection interrupt is enabled
5411 */
5412#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
5413#define I2C_FLT_STOPF_MASK (0x40U)
5414#define I2C_FLT_STOPF_SHIFT (6U)
5415/*! STOPF - I2C Bus Stop Detect Flag
5416 * 0b0..No stop happens on I2C bus
5417 * 0b1..Stop detected on I2C bus
5418 */
5419#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
5420#define I2C_FLT_SHEN_MASK (0x80U)
5421#define I2C_FLT_SHEN_SHIFT (7U)
5422/*! SHEN - Stop Hold Enable
5423 * 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
5424 * 0b1..Stop holdoff is enabled.
5425 */
5426#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
5427/*! @} */
5428
5429/*! @name RA - I2C Range Address register */
5430/*! @{ */
5431#define I2C_RA_RAD_MASK (0xFEU)
5432#define I2C_RA_RAD_SHIFT (1U)
5433#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
5434/*! @} */
5435
5436/*! @name SMB - I2C SMBus Control and Status register */
5437/*! @{ */
5438#define I2C_SMB_SHTF2IE_MASK (0x1U)
5439#define I2C_SMB_SHTF2IE_SHIFT (0U)
5440/*! SHTF2IE - SHTF2 Interrupt Enable
5441 * 0b0..SHTF2 interrupt is disabled
5442 * 0b1..SHTF2 interrupt is enabled
5443 */
5444#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
5445#define I2C_SMB_SHTF2_MASK (0x2U)
5446#define I2C_SMB_SHTF2_SHIFT (1U)
5447/*! SHTF2 - SCL High Timeout Flag 2
5448 * 0b0..No SCL high and SDA low timeout occurs
5449 * 0b1..SCL high and SDA low timeout occurs
5450 */
5451#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
5452#define I2C_SMB_SHTF1_MASK (0x4U)
5453#define I2C_SMB_SHTF1_SHIFT (2U)
5454/*! SHTF1 - SCL High Timeout Flag 1
5455 * 0b0..No SCL high and SDA high timeout occurs
5456 * 0b1..SCL high and SDA high timeout occurs
5457 */
5458#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
5459#define I2C_SMB_SLTF_MASK (0x8U)
5460#define I2C_SMB_SLTF_SHIFT (3U)
5461/*! SLTF - SCL Low Timeout Flag
5462 * 0b0..No low timeout occurs
5463 * 0b1..Low timeout occurs
5464 */
5465#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
5466#define I2C_SMB_TCKSEL_MASK (0x10U)
5467#define I2C_SMB_TCKSEL_SHIFT (4U)
5468/*! TCKSEL - Timeout Counter Clock Select
5469 * 0b0..Timeout counter counts at the frequency of the I2C module clock / 64
5470 * 0b1..Timeout counter counts at the frequency of the I2C module clock
5471 */
5472#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
5473#define I2C_SMB_SIICAEN_MASK (0x20U)
5474#define I2C_SMB_SIICAEN_SHIFT (5U)
5475/*! SIICAEN - Second I2C Address Enable
5476 * 0b0..I2C address register 2 matching is disabled
5477 * 0b1..I2C address register 2 matching is enabled
5478 */
5479#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
5480#define I2C_SMB_ALERTEN_MASK (0x40U)
5481#define I2C_SMB_ALERTEN_SHIFT (6U)
5482/*! ALERTEN - SMBus Alert Response Address Enable
5483 * 0b0..SMBus alert response address matching is disabled
5484 * 0b1..SMBus alert response address matching is enabled
5485 */
5486#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
5487#define I2C_SMB_FACK_MASK (0x80U)
5488#define I2C_SMB_FACK_SHIFT (7U)
5489/*! FACK - Fast NACK/ACK Enable
5490 * 0b0..An ACK or NACK is sent on the following receiving data byte
5491 * 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
5492 */
5493#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
5494/*! @} */
5495
5496/*! @name A2 - I2C Address Register 2 */
5497/*! @{ */
5498#define I2C_A2_SAD_MASK (0xFEU)
5499#define I2C_A2_SAD_SHIFT (1U)
5500#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
5501/*! @} */
5502
5503/*! @name SLTH - I2C SCL Low Timeout Register High */
5504/*! @{ */
5505#define I2C_SLTH_SSLT_MASK (0xFFU)
5506#define I2C_SLTH_SSLT_SHIFT (0U)
5507#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
5508/*! @} */
5509
5510/*! @name SLTL - I2C SCL Low Timeout Register Low */
5511/*! @{ */
5512#define I2C_SLTL_SSLT_MASK (0xFFU)
5513#define I2C_SLTL_SSLT_SHIFT (0U)
5514#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
5515/*! @} */
5516
5517
5518/*!
5519 * @}
5520 */ /* end of group I2C_Register_Masks */
5521
5522
5523/* I2C - Peripheral instance base addresses */
5524/** Peripheral I2C0 base address */
5525#define I2C0_BASE (0x40066000u)
5526/** Peripheral I2C0 base pointer */
5527#define I2C0 ((I2C_Type *)I2C0_BASE)
5528/** Array initializer of I2C peripheral base addresses */
5529#define I2C_BASE_ADDRS { I2C0_BASE }
5530/** Array initializer of I2C peripheral base pointers */
5531#define I2C_BASE_PTRS { I2C0 }
5532/** Interrupt vectors for the I2C peripheral type */
5533#define I2C_IRQS { I2C0_IRQn }
5534
5535/*!
5536 * @}
5537 */ /* end of group I2C_Peripheral_Access_Layer */
5538
5539
5540/* ----------------------------------------------------------------------------
5541 -- LLWU Peripheral Access Layer
5542 ---------------------------------------------------------------------------- */
5543
5544/*!
5545 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
5546 * @{
5547 */
5548
5549/** LLWU - Register Layout Typedef */
5550typedef struct {
5551 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
5552 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
5553 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
5554 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
5555 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
5556 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
5557 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
5558 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
5559 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
5560 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
5561} LLWU_Type;
5562
5563/* ----------------------------------------------------------------------------
5564 -- LLWU Register Masks
5565 ---------------------------------------------------------------------------- */
5566
5567/*!
5568 * @addtogroup LLWU_Register_Masks LLWU Register Masks
5569 * @{
5570 */
5571
5572/*! @name PE1 - LLWU Pin Enable 1 register */
5573/*! @{ */
5574#define LLWU_PE1_WUPE0_MASK (0x3U)
5575#define LLWU_PE1_WUPE0_SHIFT (0U)
5576/*! WUPE0 - Wakeup Pin Enable For LLWU_P0
5577 * 0b00..External input pin disabled as wakeup input
5578 * 0b01..External input pin enabled with rising edge detection
5579 * 0b10..External input pin enabled with falling edge detection
5580 * 0b11..External input pin enabled with any change detection
5581 */
5582#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
5583#define LLWU_PE1_WUPE1_MASK (0xCU)
5584#define LLWU_PE1_WUPE1_SHIFT (2U)
5585/*! WUPE1 - Wakeup Pin Enable For LLWU_P1
5586 * 0b00..External input pin disabled as wakeup input
5587 * 0b01..External input pin enabled with rising edge detection
5588 * 0b10..External input pin enabled with falling edge detection
5589 * 0b11..External input pin enabled with any change detection
5590 */
5591#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
5592#define LLWU_PE1_WUPE2_MASK (0x30U)
5593#define LLWU_PE1_WUPE2_SHIFT (4U)
5594/*! WUPE2 - Wakeup Pin Enable For LLWU_P2
5595 * 0b00..External input pin disabled as wakeup input
5596 * 0b01..External input pin enabled with rising edge detection
5597 * 0b10..External input pin enabled with falling edge detection
5598 * 0b11..External input pin enabled with any change detection
5599 */
5600#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
5601#define LLWU_PE1_WUPE3_MASK (0xC0U)
5602#define LLWU_PE1_WUPE3_SHIFT (6U)
5603/*! WUPE3 - Wakeup Pin Enable For LLWU_P3
5604 * 0b00..External input pin disabled as wakeup input
5605 * 0b01..External input pin enabled with rising edge detection
5606 * 0b10..External input pin enabled with falling edge detection
5607 * 0b11..External input pin enabled with any change detection
5608 */
5609#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
5610/*! @} */
5611
5612/*! @name PE2 - LLWU Pin Enable 2 register */
5613/*! @{ */
5614#define LLWU_PE2_WUPE4_MASK (0x3U)
5615#define LLWU_PE2_WUPE4_SHIFT (0U)
5616/*! WUPE4 - Wakeup Pin Enable For LLWU_P4
5617 * 0b00..External input pin disabled as wakeup input
5618 * 0b01..External input pin enabled with rising edge detection
5619 * 0b10..External input pin enabled with falling edge detection
5620 * 0b11..External input pin enabled with any change detection
5621 */
5622#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
5623#define LLWU_PE2_WUPE5_MASK (0xCU)
5624#define LLWU_PE2_WUPE5_SHIFT (2U)
5625/*! WUPE5 - Wakeup Pin Enable For LLWU_P5
5626 * 0b00..External input pin disabled as wakeup input
5627 * 0b01..External input pin enabled with rising edge detection
5628 * 0b10..External input pin enabled with falling edge detection
5629 * 0b11..External input pin enabled with any change detection
5630 */
5631#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
5632#define LLWU_PE2_WUPE6_MASK (0x30U)
5633#define LLWU_PE2_WUPE6_SHIFT (4U)
5634/*! WUPE6 - Wakeup Pin Enable For LLWU_P6
5635 * 0b00..External input pin disabled as wakeup input
5636 * 0b01..External input pin enabled with rising edge detection
5637 * 0b10..External input pin enabled with falling edge detection
5638 * 0b11..External input pin enabled with any change detection
5639 */
5640#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
5641#define LLWU_PE2_WUPE7_MASK (0xC0U)
5642#define LLWU_PE2_WUPE7_SHIFT (6U)
5643/*! WUPE7 - Wakeup Pin Enable For LLWU_P7
5644 * 0b00..External input pin disabled as wakeup input
5645 * 0b01..External input pin enabled with rising edge detection
5646 * 0b10..External input pin enabled with falling edge detection
5647 * 0b11..External input pin enabled with any change detection
5648 */
5649#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
5650/*! @} */
5651
5652/*! @name PE3 - LLWU Pin Enable 3 register */
5653/*! @{ */
5654#define LLWU_PE3_WUPE8_MASK (0x3U)
5655#define LLWU_PE3_WUPE8_SHIFT (0U)
5656/*! WUPE8 - Wakeup Pin Enable For LLWU_P8
5657 * 0b00..External input pin disabled as wakeup input
5658 * 0b01..External input pin enabled with rising edge detection
5659 * 0b10..External input pin enabled with falling edge detection
5660 * 0b11..External input pin enabled with any change detection
5661 */
5662#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
5663#define LLWU_PE3_WUPE9_MASK (0xCU)
5664#define LLWU_PE3_WUPE9_SHIFT (2U)
5665/*! WUPE9 - Wakeup Pin Enable For LLWU_P9
5666 * 0b00..External input pin disabled as wakeup input
5667 * 0b01..External input pin enabled with rising edge detection
5668 * 0b10..External input pin enabled with falling edge detection
5669 * 0b11..External input pin enabled with any change detection
5670 */
5671#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
5672#define LLWU_PE3_WUPE10_MASK (0x30U)
5673#define LLWU_PE3_WUPE10_SHIFT (4U)
5674/*! WUPE10 - Wakeup Pin Enable For LLWU_P10
5675 * 0b00..External input pin disabled as wakeup input
5676 * 0b01..External input pin enabled with rising edge detection
5677 * 0b10..External input pin enabled with falling edge detection
5678 * 0b11..External input pin enabled with any change detection
5679 */
5680#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
5681#define LLWU_PE3_WUPE11_MASK (0xC0U)
5682#define LLWU_PE3_WUPE11_SHIFT (6U)
5683/*! WUPE11 - Wakeup Pin Enable For LLWU_P11
5684 * 0b00..External input pin disabled as wakeup input
5685 * 0b01..External input pin enabled with rising edge detection
5686 * 0b10..External input pin enabled with falling edge detection
5687 * 0b11..External input pin enabled with any change detection
5688 */
5689#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
5690/*! @} */
5691
5692/*! @name PE4 - LLWU Pin Enable 4 register */
5693/*! @{ */
5694#define LLWU_PE4_WUPE12_MASK (0x3U)
5695#define LLWU_PE4_WUPE12_SHIFT (0U)
5696/*! WUPE12 - Wakeup Pin Enable For LLWU_P12
5697 * 0b00..External input pin disabled as wakeup input
5698 * 0b01..External input pin enabled with rising edge detection
5699 * 0b10..External input pin enabled with falling edge detection
5700 * 0b11..External input pin enabled with any change detection
5701 */
5702#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
5703#define LLWU_PE4_WUPE13_MASK (0xCU)
5704#define LLWU_PE4_WUPE13_SHIFT (2U)
5705/*! WUPE13 - Wakeup Pin Enable For LLWU_P13
5706 * 0b00..External input pin disabled as wakeup input
5707 * 0b01..External input pin enabled with rising edge detection
5708 * 0b10..External input pin enabled with falling edge detection
5709 * 0b11..External input pin enabled with any change detection
5710 */
5711#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
5712#define LLWU_PE4_WUPE14_MASK (0x30U)
5713#define LLWU_PE4_WUPE14_SHIFT (4U)
5714/*! WUPE14 - Wakeup Pin Enable For LLWU_P14
5715 * 0b00..External input pin disabled as wakeup input
5716 * 0b01..External input pin enabled with rising edge detection
5717 * 0b10..External input pin enabled with falling edge detection
5718 * 0b11..External input pin enabled with any change detection
5719 */
5720#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
5721#define LLWU_PE4_WUPE15_MASK (0xC0U)
5722#define LLWU_PE4_WUPE15_SHIFT (6U)
5723/*! WUPE15 - Wakeup Pin Enable For LLWU_P15
5724 * 0b00..External input pin disabled as wakeup input
5725 * 0b01..External input pin enabled with rising edge detection
5726 * 0b10..External input pin enabled with falling edge detection
5727 * 0b11..External input pin enabled with any change detection
5728 */
5729#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
5730/*! @} */
5731
5732/*! @name ME - LLWU Module Enable register */
5733/*! @{ */
5734#define LLWU_ME_WUME0_MASK (0x1U)
5735#define LLWU_ME_WUME0_SHIFT (0U)
5736/*! WUME0 - Wakeup Module Enable For Module 0
5737 * 0b0..Internal module flag not used as wakeup source
5738 * 0b1..Internal module flag used as wakeup source
5739 */
5740#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
5741#define LLWU_ME_WUME1_MASK (0x2U)
5742#define LLWU_ME_WUME1_SHIFT (1U)
5743/*! WUME1 - Wakeup Module Enable for Module 1
5744 * 0b0..Internal module flag not used as wakeup source
5745 * 0b1..Internal module flag used as wakeup source
5746 */
5747#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
5748#define LLWU_ME_WUME2_MASK (0x4U)
5749#define LLWU_ME_WUME2_SHIFT (2U)
5750/*! WUME2 - Wakeup Module Enable For Module 2
5751 * 0b0..Internal module flag not used as wakeup source
5752 * 0b1..Internal module flag used as wakeup source
5753 */
5754#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
5755#define LLWU_ME_WUME3_MASK (0x8U)
5756#define LLWU_ME_WUME3_SHIFT (3U)
5757/*! WUME3 - Wakeup Module Enable For Module 3
5758 * 0b0..Internal module flag not used as wakeup source
5759 * 0b1..Internal module flag used as wakeup source
5760 */
5761#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
5762#define LLWU_ME_WUME4_MASK (0x10U)
5763#define LLWU_ME_WUME4_SHIFT (4U)
5764/*! WUME4 - Wakeup Module Enable For Module 4
5765 * 0b0..Internal module flag not used as wakeup source
5766 * 0b1..Internal module flag used as wakeup source
5767 */
5768#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
5769#define LLWU_ME_WUME5_MASK (0x20U)
5770#define LLWU_ME_WUME5_SHIFT (5U)
5771/*! WUME5 - Wakeup Module Enable For Module 5
5772 * 0b0..Internal module flag not used as wakeup source
5773 * 0b1..Internal module flag used as wakeup source
5774 */
5775#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
5776#define LLWU_ME_WUME6_MASK (0x40U)
5777#define LLWU_ME_WUME6_SHIFT (6U)
5778/*! WUME6 - Wakeup Module Enable For Module 6
5779 * 0b0..Internal module flag not used as wakeup source
5780 * 0b1..Internal module flag used as wakeup source
5781 */
5782#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
5783#define LLWU_ME_WUME7_MASK (0x80U)
5784#define LLWU_ME_WUME7_SHIFT (7U)
5785/*! WUME7 - Wakeup Module Enable For Module 7
5786 * 0b0..Internal module flag not used as wakeup source
5787 * 0b1..Internal module flag used as wakeup source
5788 */
5789#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
5790/*! @} */
5791
5792/*! @name F1 - LLWU Flag 1 register */
5793/*! @{ */
5794#define LLWU_F1_WUF0_MASK (0x1U)
5795#define LLWU_F1_WUF0_SHIFT (0U)
5796/*! WUF0 - Wakeup Flag For LLWU_P0
5797 * 0b0..LLWU_P0 input was not a wakeup source
5798 * 0b1..LLWU_P0 input was a wakeup source
5799 */
5800#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
5801#define LLWU_F1_WUF1_MASK (0x2U)
5802#define LLWU_F1_WUF1_SHIFT (1U)
5803/*! WUF1 - Wakeup Flag For LLWU_P1
5804 * 0b0..LLWU_P1 input was not a wakeup source
5805 * 0b1..LLWU_P1 input was a wakeup source
5806 */
5807#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
5808#define LLWU_F1_WUF2_MASK (0x4U)
5809#define LLWU_F1_WUF2_SHIFT (2U)
5810/*! WUF2 - Wakeup Flag For LLWU_P2
5811 * 0b0..LLWU_P2 input was not a wakeup source
5812 * 0b1..LLWU_P2 input was a wakeup source
5813 */
5814#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
5815#define LLWU_F1_WUF3_MASK (0x8U)
5816#define LLWU_F1_WUF3_SHIFT (3U)
5817/*! WUF3 - Wakeup Flag For LLWU_P3
5818 * 0b0..LLWU_P3 input was not a wake-up source
5819 * 0b1..LLWU_P3 input was a wake-up source
5820 */
5821#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
5822#define LLWU_F1_WUF4_MASK (0x10U)
5823#define LLWU_F1_WUF4_SHIFT (4U)
5824/*! WUF4 - Wakeup Flag For LLWU_P4
5825 * 0b0..LLWU_P4 input was not a wakeup source
5826 * 0b1..LLWU_P4 input was a wakeup source
5827 */
5828#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
5829#define LLWU_F1_WUF5_MASK (0x20U)
5830#define LLWU_F1_WUF5_SHIFT (5U)
5831/*! WUF5 - Wakeup Flag For LLWU_P5
5832 * 0b0..LLWU_P5 input was not a wakeup source
5833 * 0b1..LLWU_P5 input was a wakeup source
5834 */
5835#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
5836#define LLWU_F1_WUF6_MASK (0x40U)
5837#define LLWU_F1_WUF6_SHIFT (6U)
5838/*! WUF6 - Wakeup Flag For LLWU_P6
5839 * 0b0..LLWU_P6 input was not a wakeup source
5840 * 0b1..LLWU_P6 input was a wakeup source
5841 */
5842#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
5843#define LLWU_F1_WUF7_MASK (0x80U)
5844#define LLWU_F1_WUF7_SHIFT (7U)
5845/*! WUF7 - Wakeup Flag For LLWU_P7
5846 * 0b0..LLWU_P7 input was not a wakeup source
5847 * 0b1..LLWU_P7 input was a wakeup source
5848 */
5849#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
5850/*! @} */
5851
5852/*! @name F2 - LLWU Flag 2 register */
5853/*! @{ */
5854#define LLWU_F2_WUF8_MASK (0x1U)
5855#define LLWU_F2_WUF8_SHIFT (0U)
5856/*! WUF8 - Wakeup Flag For LLWU_P8
5857 * 0b0..LLWU_P8 input was not a wakeup source
5858 * 0b1..LLWU_P8 input was a wakeup source
5859 */
5860#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
5861#define LLWU_F2_WUF9_MASK (0x2U)
5862#define LLWU_F2_WUF9_SHIFT (1U)
5863/*! WUF9 - Wakeup Flag For LLWU_P9
5864 * 0b0..LLWU_P9 input was not a wakeup source
5865 * 0b1..LLWU_P9 input was a wakeup source
5866 */
5867#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
5868#define LLWU_F2_WUF10_MASK (0x4U)
5869#define LLWU_F2_WUF10_SHIFT (2U)
5870/*! WUF10 - Wakeup Flag For LLWU_P10
5871 * 0b0..LLWU_P10 input was not a wakeup source
5872 * 0b1..LLWU_P10 input was a wakeup source
5873 */
5874#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
5875#define LLWU_F2_WUF11_MASK (0x8U)
5876#define LLWU_F2_WUF11_SHIFT (3U)
5877/*! WUF11 - Wakeup Flag For LLWU_P11
5878 * 0b0..LLWU_P11 input was not a wakeup source
5879 * 0b1..LLWU_P11 input was a wakeup source
5880 */
5881#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
5882#define LLWU_F2_WUF12_MASK (0x10U)
5883#define LLWU_F2_WUF12_SHIFT (4U)
5884/*! WUF12 - Wakeup Flag For LLWU_P12
5885 * 0b0..LLWU_P12 input was not a wakeup source
5886 * 0b1..LLWU_P12 input was a wakeup source
5887 */
5888#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
5889#define LLWU_F2_WUF13_MASK (0x20U)
5890#define LLWU_F2_WUF13_SHIFT (5U)
5891/*! WUF13 - Wakeup Flag For LLWU_P13
5892 * 0b0..LLWU_P13 input was not a wakeup source
5893 * 0b1..LLWU_P13 input was a wakeup source
5894 */
5895#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
5896#define LLWU_F2_WUF14_MASK (0x40U)
5897#define LLWU_F2_WUF14_SHIFT (6U)
5898/*! WUF14 - Wakeup Flag For LLWU_P14
5899 * 0b0..LLWU_P14 input was not a wakeup source
5900 * 0b1..LLWU_P14 input was a wakeup source
5901 */
5902#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
5903#define LLWU_F2_WUF15_MASK (0x80U)
5904#define LLWU_F2_WUF15_SHIFT (7U)
5905/*! WUF15 - Wakeup Flag For LLWU_P15
5906 * 0b0..LLWU_P15 input was not a wakeup source
5907 * 0b1..LLWU_P15 input was a wakeup source
5908 */
5909#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
5910/*! @} */
5911
5912/*! @name F3 - LLWU Flag 3 register */
5913/*! @{ */
5914#define LLWU_F3_MWUF0_MASK (0x1U)
5915#define LLWU_F3_MWUF0_SHIFT (0U)
5916/*! MWUF0 - Wakeup flag For module 0
5917 * 0b0..Module 0 input was not a wakeup source
5918 * 0b1..Module 0 input was a wakeup source
5919 */
5920#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
5921#define LLWU_F3_MWUF1_MASK (0x2U)
5922#define LLWU_F3_MWUF1_SHIFT (1U)
5923/*! MWUF1 - Wakeup flag For module 1
5924 * 0b0..Module 1 input was not a wakeup source
5925 * 0b1..Module 1 input was a wakeup source
5926 */
5927#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
5928#define LLWU_F3_MWUF2_MASK (0x4U)
5929#define LLWU_F3_MWUF2_SHIFT (2U)
5930/*! MWUF2 - Wakeup flag For module 2
5931 * 0b0..Module 2 input was not a wakeup source
5932 * 0b1..Module 2 input was a wakeup source
5933 */
5934#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
5935#define LLWU_F3_MWUF3_MASK (0x8U)
5936#define LLWU_F3_MWUF3_SHIFT (3U)
5937/*! MWUF3 - Wakeup flag For module 3
5938 * 0b0..Module 3 input was not a wakeup source
5939 * 0b1..Module 3 input was a wakeup source
5940 */
5941#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
5942#define LLWU_F3_MWUF4_MASK (0x10U)
5943#define LLWU_F3_MWUF4_SHIFT (4U)
5944/*! MWUF4 - Wakeup flag For module 4
5945 * 0b0..Module 4 input was not a wakeup source
5946 * 0b1..Module 4 input was a wakeup source
5947 */
5948#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
5949#define LLWU_F3_MWUF5_MASK (0x20U)
5950#define LLWU_F3_MWUF5_SHIFT (5U)
5951/*! MWUF5 - Wakeup flag For module 5
5952 * 0b0..Module 5 input was not a wakeup source
5953 * 0b1..Module 5 input was a wakeup source
5954 */
5955#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
5956#define LLWU_F3_MWUF6_MASK (0x40U)
5957#define LLWU_F3_MWUF6_SHIFT (6U)
5958/*! MWUF6 - Wakeup flag For module 6
5959 * 0b0..Module 6 input was not a wakeup source
5960 * 0b1..Module 6 input was a wakeup source
5961 */
5962#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
5963#define LLWU_F3_MWUF7_MASK (0x80U)
5964#define LLWU_F3_MWUF7_SHIFT (7U)
5965/*! MWUF7 - Wakeup flag For module 7
5966 * 0b0..Module 7 input was not a wakeup source
5967 * 0b1..Module 7 input was a wakeup source
5968 */
5969#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
5970/*! @} */
5971
5972/*! @name FILT1 - LLWU Pin Filter 1 register */
5973/*! @{ */
5974#define LLWU_FILT1_FILTSEL_MASK (0xFU)
5975#define LLWU_FILT1_FILTSEL_SHIFT (0U)
5976/*! FILTSEL - Filter Pin Select
5977 * 0b0000..Select LLWU_P0 for filter
5978 * 0b1111..Select LLWU_P15 for filter
5979 */
5980#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
5981#define LLWU_FILT1_FILTE_MASK (0x60U)
5982#define LLWU_FILT1_FILTE_SHIFT (5U)
5983/*! FILTE - Digital Filter On External Pin
5984 * 0b00..Filter disabled
5985 * 0b01..Filter posedge detect enabled
5986 * 0b10..Filter negedge detect enabled
5987 * 0b11..Filter any edge detect enabled
5988 */
5989#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
5990#define LLWU_FILT1_FILTF_MASK (0x80U)
5991#define LLWU_FILT1_FILTF_SHIFT (7U)
5992/*! FILTF - Filter Detect Flag
5993 * 0b0..Pin Filter 1 was not a wakeup source
5994 * 0b1..Pin Filter 1 was a wakeup source
5995 */
5996#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
5997/*! @} */
5998
5999/*! @name FILT2 - LLWU Pin Filter 2 register */
6000/*! @{ */
6001#define LLWU_FILT2_FILTSEL_MASK (0xFU)
6002#define LLWU_FILT2_FILTSEL_SHIFT (0U)
6003/*! FILTSEL - Filter Pin Select
6004 * 0b0000..Select LLWU_P0 for filter
6005 * 0b1111..Select LLWU_P15 for filter
6006 */
6007#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
6008#define LLWU_FILT2_FILTE_MASK (0x60U)
6009#define LLWU_FILT2_FILTE_SHIFT (5U)
6010/*! FILTE - Digital Filter On External Pin
6011 * 0b00..Filter disabled
6012 * 0b01..Filter posedge detect enabled
6013 * 0b10..Filter negedge detect enabled
6014 * 0b11..Filter any edge detect enabled
6015 */
6016#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
6017#define LLWU_FILT2_FILTF_MASK (0x80U)
6018#define LLWU_FILT2_FILTF_SHIFT (7U)
6019/*! FILTF - Filter Detect Flag
6020 * 0b0..Pin Filter 2 was not a wakeup source
6021 * 0b1..Pin Filter 2 was a wakeup source
6022 */
6023#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
6024/*! @} */
6025
6026
6027/*!
6028 * @}
6029 */ /* end of group LLWU_Register_Masks */
6030
6031
6032/* LLWU - Peripheral instance base addresses */
6033/** Peripheral LLWU base address */
6034#define LLWU_BASE (0x4007C000u)
6035/** Peripheral LLWU base pointer */
6036#define LLWU ((LLWU_Type *)LLWU_BASE)
6037/** Array initializer of LLWU peripheral base addresses */
6038#define LLWU_BASE_ADDRS { LLWU_BASE }
6039/** Array initializer of LLWU peripheral base pointers */
6040#define LLWU_BASE_PTRS { LLWU }
6041/** Interrupt vectors for the LLWU peripheral type */
6042#define LLWU_IRQS { LLWU_IRQn }
6043
6044/*!
6045 * @}
6046 */ /* end of group LLWU_Peripheral_Access_Layer */
6047
6048
6049/* ----------------------------------------------------------------------------
6050 -- LPTMR Peripheral Access Layer
6051 ---------------------------------------------------------------------------- */
6052
6053/*!
6054 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
6055 * @{
6056 */
6057
6058/** LPTMR - Register Layout Typedef */
6059typedef struct {
6060 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
6061 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
6062 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
6063 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
6064} LPTMR_Type;
6065
6066/* ----------------------------------------------------------------------------
6067 -- LPTMR Register Masks
6068 ---------------------------------------------------------------------------- */
6069
6070/*!
6071 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
6072 * @{
6073 */
6074
6075/*! @name CSR - Low Power Timer Control Status Register */
6076/*! @{ */
6077#define LPTMR_CSR_TEN_MASK (0x1U)
6078#define LPTMR_CSR_TEN_SHIFT (0U)
6079/*! TEN - Timer Enable
6080 * 0b0..LPTMR is disabled and internal logic is reset.
6081 * 0b1..LPTMR is enabled.
6082 */
6083#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
6084#define LPTMR_CSR_TMS_MASK (0x2U)
6085#define LPTMR_CSR_TMS_SHIFT (1U)
6086/*! TMS - Timer Mode Select
6087 * 0b0..Time Counter mode.
6088 * 0b1..Pulse Counter mode.
6089 */
6090#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
6091#define LPTMR_CSR_TFC_MASK (0x4U)
6092#define LPTMR_CSR_TFC_SHIFT (2U)
6093/*! TFC - Timer Free-Running Counter
6094 * 0b0..CNR is reset whenever TCF is set.
6095 * 0b1..CNR is reset on overflow.
6096 */
6097#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
6098#define LPTMR_CSR_TPP_MASK (0x8U)
6099#define LPTMR_CSR_TPP_SHIFT (3U)
6100/*! TPP - Timer Pin Polarity
6101 * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
6102 * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
6103 */
6104#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
6105#define LPTMR_CSR_TPS_MASK (0x30U)
6106#define LPTMR_CSR_TPS_SHIFT (4U)
6107/*! TPS - Timer Pin Select
6108 * 0b00..Pulse counter input 0 is selected.
6109 * 0b01..Pulse counter input 1 is selected.
6110 * 0b10..Pulse counter input 2 is selected.
6111 * 0b11..Pulse counter input 3 is selected.
6112 */
6113#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
6114#define LPTMR_CSR_TIE_MASK (0x40U)
6115#define LPTMR_CSR_TIE_SHIFT (6U)
6116/*! TIE - Timer Interrupt Enable
6117 * 0b0..Timer interrupt disabled.
6118 * 0b1..Timer interrupt enabled.
6119 */
6120#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
6121#define LPTMR_CSR_TCF_MASK (0x80U)
6122#define LPTMR_CSR_TCF_SHIFT (7U)
6123/*! TCF - Timer Compare Flag
6124 * 0b0..The value of CNR is not equal to CMR and increments.
6125 * 0b1..The value of CNR is equal to CMR and increments.
6126 */
6127#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
6128/*! @} */
6129
6130/*! @name PSR - Low Power Timer Prescale Register */
6131/*! @{ */
6132#define LPTMR_PSR_PCS_MASK (0x3U)
6133#define LPTMR_PSR_PCS_SHIFT (0U)
6134/*! PCS - Prescaler Clock Select
6135 * 0b00..Prescaler/glitch filter clock 0 selected.
6136 * 0b01..Prescaler/glitch filter clock 1 selected.
6137 * 0b10..Prescaler/glitch filter clock 2 selected.
6138 * 0b11..Prescaler/glitch filter clock 3 selected.
6139 */
6140#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
6141#define LPTMR_PSR_PBYP_MASK (0x4U)
6142#define LPTMR_PSR_PBYP_SHIFT (2U)
6143/*! PBYP - Prescaler Bypass
6144 * 0b0..Prescaler/glitch filter is enabled.
6145 * 0b1..Prescaler/glitch filter is bypassed.
6146 */
6147#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
6148#define LPTMR_PSR_PRESCALE_MASK (0x78U)
6149#define LPTMR_PSR_PRESCALE_SHIFT (3U)
6150/*! PRESCALE - Prescale Value
6151 * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
6152 * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
6153 * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
6154 * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
6155 * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
6156 * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
6157 * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
6158 * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
6159 * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
6160 * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
6161 * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
6162 * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
6163 * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
6164 * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
6165 * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
6166 * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
6167 */
6168#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
6169/*! @} */
6170
6171/*! @name CMR - Low Power Timer Compare Register */
6172/*! @{ */
6173#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
6174#define LPTMR_CMR_COMPARE_SHIFT (0U)
6175#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
6176/*! @} */
6177
6178/*! @name CNR - Low Power Timer Counter Register */
6179/*! @{ */
6180#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
6181#define LPTMR_CNR_COUNTER_SHIFT (0U)
6182#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
6183/*! @} */
6184
6185
6186/*!
6187 * @}
6188 */ /* end of group LPTMR_Register_Masks */
6189
6190
6191/* LPTMR - Peripheral instance base addresses */
6192/** Peripheral LPTMR0 base address */
6193#define LPTMR0_BASE (0x40040000u)
6194/** Peripheral LPTMR0 base pointer */
6195#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
6196/** Array initializer of LPTMR peripheral base addresses */
6197#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
6198/** Array initializer of LPTMR peripheral base pointers */
6199#define LPTMR_BASE_PTRS { LPTMR0 }
6200/** Interrupt vectors for the LPTMR peripheral type */
6201#define LPTMR_IRQS { LPTMR0_IRQn }
6202
6203/*!
6204 * @}
6205 */ /* end of group LPTMR_Peripheral_Access_Layer */
6206
6207
6208/* ----------------------------------------------------------------------------
6209 -- MCG Peripheral Access Layer
6210 ---------------------------------------------------------------------------- */
6211
6212/*!
6213 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
6214 * @{
6215 */
6216
6217/** MCG - Register Layout Typedef */
6218typedef struct {
6219 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
6220 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
6221 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
6222 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
6223 uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
6224 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
6225 __I uint8_t S; /**< MCG Status Register, offset: 0x6 */
6226 uint8_t RESERVED_0[1];
6227 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
6228 uint8_t RESERVED_1[1];
6229 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
6230 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
6231 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
6232 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
6233} MCG_Type;
6234
6235/* ----------------------------------------------------------------------------
6236 -- MCG Register Masks
6237 ---------------------------------------------------------------------------- */
6238
6239/*!
6240 * @addtogroup MCG_Register_Masks MCG Register Masks
6241 * @{
6242 */
6243
6244/*! @name C1 - MCG Control 1 Register */
6245/*! @{ */
6246#define MCG_C1_IREFSTEN_MASK (0x1U)
6247#define MCG_C1_IREFSTEN_SHIFT (0U)
6248/*! IREFSTEN - Internal Reference Stop Enable
6249 * 0b0..Internal reference clock is disabled in Stop mode.
6250 * 0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
6251 */
6252#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
6253#define MCG_C1_IRCLKEN_MASK (0x2U)
6254#define MCG_C1_IRCLKEN_SHIFT (1U)
6255/*! IRCLKEN - Internal Reference Clock Enable
6256 * 0b0..MCGIRCLK inactive.
6257 * 0b1..MCGIRCLK active.
6258 */
6259#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
6260#define MCG_C1_IREFS_MASK (0x4U)
6261#define MCG_C1_IREFS_SHIFT (2U)
6262/*! IREFS - Internal Reference Select
6263 * 0b0..External reference clock is selected.
6264 * 0b1..The slow internal reference clock is selected.
6265 */
6266#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
6267#define MCG_C1_FRDIV_MASK (0x38U)
6268#define MCG_C1_FRDIV_SHIFT (3U)
6269/*! FRDIV - FLL External Reference Divider
6270 * 0b000..If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.
6271 * 0b001..If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.
6272 * 0b010..If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.
6273 * 0b011..If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
6274 * 0b100..If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.
6275 * 0b101..If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.
6276 * 0b110..If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 .
6277 * 0b111..If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .
6278 */
6279#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
6280#define MCG_C1_CLKS_MASK (0xC0U)
6281#define MCG_C1_CLKS_SHIFT (6U)
6282/*! CLKS - Clock Source Select
6283 * 0b00..Encoding 0 - Output of FLL is selected.
6284 * 0b01..Encoding 1 - Internal reference clock is selected.
6285 * 0b10..Encoding 2 - External reference clock is selected.
6286 * 0b11..Encoding 3 - Reserved.
6287 */
6288#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
6289/*! @} */
6290
6291/*! @name C2 - MCG Control 2 Register */
6292/*! @{ */
6293#define MCG_C2_IRCS_MASK (0x1U)
6294#define MCG_C2_IRCS_SHIFT (0U)
6295/*! IRCS - Internal Reference Clock Select
6296 * 0b0..Slow internal reference clock selected.
6297 * 0b1..Fast internal reference clock selected.
6298 */
6299#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
6300#define MCG_C2_LP_MASK (0x2U)
6301#define MCG_C2_LP_SHIFT (1U)
6302/*! LP - Low Power Select
6303 * 0b0..FLL is not disabled in bypass modes.
6304 * 0b1..FLL is disabled in bypass modes (lower power)
6305 */
6306#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
6307#define MCG_C2_EREFS_MASK (0x4U)
6308#define MCG_C2_EREFS_SHIFT (2U)
6309/*! EREFS - External Reference Select
6310 * 0b0..External reference clock requested.
6311 * 0b1..Oscillator requested.
6312 */
6313#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
6314#define MCG_C2_HGO_MASK (0x8U)
6315#define MCG_C2_HGO_SHIFT (3U)
6316/*! HGO - High Gain Oscillator Select
6317 * 0b0..Configure crystal oscillator for low-power operation.
6318 * 0b1..Configure crystal oscillator for high-gain operation.
6319 */
6320#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
6321#define MCG_C2_RANGE_MASK (0x30U)
6322#define MCG_C2_RANGE_SHIFT (4U)
6323/*! RANGE - Frequency Range Select
6324 * 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator .
6325 * 0b01..Encoding 1 - High frequency range selected for the crystal oscillator .
6326 * 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator .
6327 */
6328#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
6329#define MCG_C2_FCFTRIM_MASK (0x40U)
6330#define MCG_C2_FCFTRIM_SHIFT (6U)
6331#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
6332#define MCG_C2_LOCRE0_MASK (0x80U)
6333#define MCG_C2_LOCRE0_SHIFT (7U)
6334/*! LOCRE0 - Loss of Clock Reset Enable
6335 * 0b0..Interrupt request is generated on a loss of OSC0 external reference clock.
6336 * 0b1..Generate a reset request on a loss of OSC0 external reference clock.
6337 */
6338#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
6339/*! @} */
6340
6341/*! @name C3 - MCG Control 3 Register */
6342/*! @{ */
6343#define MCG_C3_SCTRIM_MASK (0xFFU)
6344#define MCG_C3_SCTRIM_SHIFT (0U)
6345#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
6346/*! @} */
6347
6348/*! @name C4 - MCG Control 4 Register */
6349/*! @{ */
6350#define MCG_C4_SCFTRIM_MASK (0x1U)
6351#define MCG_C4_SCFTRIM_SHIFT (0U)
6352#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
6353#define MCG_C4_FCTRIM_MASK (0x1EU)
6354#define MCG_C4_FCTRIM_SHIFT (1U)
6355#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
6356#define MCG_C4_DRST_DRS_MASK (0x60U)
6357#define MCG_C4_DRST_DRS_SHIFT (5U)
6358/*! DRST_DRS - DCO Range Select
6359 * 0b00..Encoding 0 - Low range (reset default).
6360 * 0b01..Encoding 1 - Mid range.
6361 * 0b10..Encoding 2 - Mid-high range.
6362 * 0b11..Encoding 3 - High range.
6363 */
6364#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
6365#define MCG_C4_DMX32_MASK (0x80U)
6366#define MCG_C4_DMX32_SHIFT (7U)
6367/*! DMX32 - DCO Maximum Frequency with 32.768 kHz Reference
6368 * 0b0..DCO has a default range of 25%.
6369 * 0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
6370 */
6371#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
6372/*! @} */
6373
6374/*! @name C6 - MCG Control 6 Register */
6375/*! @{ */
6376#define MCG_C6_CME_MASK (0x20U)
6377#define MCG_C6_CME_SHIFT (5U)
6378/*! CME - Clock Monitor Enable
6379 * 0b0..External clock monitor is disabled.
6380 * 0b1..Generate a reset request on loss of external clock.
6381 */
6382#define MCG_C6_CME(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME_SHIFT)) & MCG_C6_CME_MASK)
6383/*! @} */
6384
6385/*! @name S - MCG Status Register */
6386/*! @{ */
6387#define MCG_S_IRCST_MASK (0x1U)
6388#define MCG_S_IRCST_SHIFT (0U)
6389/*! IRCST - Internal Reference Clock Status
6390 * 0b0..Source of internal reference clock is the slow clock (32 kHz IRC).
6391 * 0b1..Source of internal reference clock is the fast clock (4 MHz IRC).
6392 */
6393#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
6394#define MCG_S_OSCINIT0_MASK (0x2U)
6395#define MCG_S_OSCINIT0_SHIFT (1U)
6396#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
6397#define MCG_S_CLKST_MASK (0xCU)
6398#define MCG_S_CLKST_SHIFT (2U)
6399/*! CLKST - Clock Mode Status
6400 * 0b00..Encoding 0 - Output of the FLL is selected (reset default).
6401 * 0b01..Encoding 1 - Internal reference clock is selected.
6402 * 0b10..Encoding 2 - External reference clock is selected.
6403 * 0b11..Reserved.
6404 */
6405#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
6406#define MCG_S_IREFST_MASK (0x10U)
6407#define MCG_S_IREFST_SHIFT (4U)
6408/*! IREFST - Internal Reference Status
6409 * 0b0..Source of FLL reference clock is the external reference clock.
6410 * 0b1..Source of FLL reference clock is the internal reference clock.
6411 */
6412#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
6413/*! @} */
6414
6415/*! @name SC - MCG Status and Control Register */
6416/*! @{ */
6417#define MCG_SC_LOCS0_MASK (0x1U)
6418#define MCG_SC_LOCS0_SHIFT (0U)
6419/*! LOCS0 - OSC0 Loss of Clock Status
6420 * 0b0..Loss of OSC0 has not occurred.
6421 * 0b1..Loss of OSC0 has occurred.
6422 */
6423#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
6424#define MCG_SC_FCRDIV_MASK (0xEU)
6425#define MCG_SC_FCRDIV_SHIFT (1U)
6426/*! FCRDIV - Fast Clock Internal Reference Divider
6427 * 0b000..Divide Factor is 1
6428 * 0b001..Divide Factor is 2.
6429 * 0b010..Divide Factor is 4.
6430 * 0b011..Divide Factor is 8.
6431 * 0b100..Divide Factor is 16
6432 * 0b101..Divide Factor is 32
6433 * 0b110..Divide Factor is 64
6434 * 0b111..Divide Factor is 128.
6435 */
6436#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
6437#define MCG_SC_FLTPRSRV_MASK (0x10U)
6438#define MCG_SC_FLTPRSRV_SHIFT (4U)
6439/*! FLTPRSRV - FLL Filter Preserve Enable
6440 * 0b0..FLL filter and FLL frequency will reset on changes to currect clock mode.
6441 * 0b1..Fll filter and FLL frequency retain their previous values during new clock mode change.
6442 */
6443#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
6444#define MCG_SC_ATMF_MASK (0x20U)
6445#define MCG_SC_ATMF_SHIFT (5U)
6446/*! ATMF - Automatic Trim Machine Fail Flag
6447 * 0b0..Automatic Trim Machine completed normally.
6448 * 0b1..Automatic Trim Machine failed.
6449 */
6450#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
6451#define MCG_SC_ATMS_MASK (0x40U)
6452#define MCG_SC_ATMS_SHIFT (6U)
6453/*! ATMS - Automatic Trim Machine Select
6454 * 0b0..32 kHz Internal Reference Clock selected.
6455 * 0b1..4 MHz Internal Reference Clock selected.
6456 */
6457#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
6458#define MCG_SC_ATME_MASK (0x80U)
6459#define MCG_SC_ATME_SHIFT (7U)
6460/*! ATME - Automatic Trim Machine Enable
6461 * 0b0..Auto Trim Machine disabled.
6462 * 0b1..Auto Trim Machine enabled.
6463 */
6464#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
6465/*! @} */
6466
6467/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
6468/*! @{ */
6469#define MCG_ATCVH_ATCVH_MASK (0xFFU)
6470#define MCG_ATCVH_ATCVH_SHIFT (0U)
6471#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
6472/*! @} */
6473
6474/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
6475/*! @{ */
6476#define MCG_ATCVL_ATCVL_MASK (0xFFU)
6477#define MCG_ATCVL_ATCVL_SHIFT (0U)
6478#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
6479/*! @} */
6480
6481/*! @name C7 - MCG Control 7 Register */
6482/*! @{ */
6483#define MCG_C7_OSCSEL_MASK (0x3U)
6484#define MCG_C7_OSCSEL_SHIFT (0U)
6485/*! OSCSEL - MCG OSC Clock Select
6486 * 0b00..Selects Oscillator (OSCCLK0).
6487 * 0b01..Selects 32 kHz RTC Oscillator.
6488 * 0b10..Selects Oscillator (OSCCLK1).
6489 * 0b11..RESERVED
6490 */
6491#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
6492/*! @} */
6493
6494/*! @name C8 - MCG Control 8 Register */
6495/*! @{ */
6496#define MCG_C8_LOCS1_MASK (0x1U)
6497#define MCG_C8_LOCS1_SHIFT (0U)
6498/*! LOCS1 - RTC Loss of Clock Status
6499 * 0b0..Loss of RTC has not occur.
6500 * 0b1..Loss of RTC has occur
6501 */
6502#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
6503#define MCG_C8_CME1_MASK (0x20U)
6504#define MCG_C8_CME1_SHIFT (5U)
6505/*! CME1 - Clock Monitor Enable1
6506 * 0b0..External clock monitor is disabled for RTC clock.
6507 * 0b1..External clock monitor is enabled for RTC clock.
6508 */
6509#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
6510#define MCG_C8_LOCRE1_MASK (0x80U)
6511#define MCG_C8_LOCRE1_SHIFT (7U)
6512/*! LOCRE1 - Loss of Clock Reset Enable
6513 * 0b0..Interrupt request is generated on a loss of RTC external reference clock.
6514 * 0b1..Generate a reset request on a loss of RTC external reference clock
6515 */
6516#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
6517/*! @} */
6518
6519
6520/*!
6521 * @}
6522 */ /* end of group MCG_Register_Masks */
6523
6524
6525/* MCG - Peripheral instance base addresses */
6526/** Peripheral MCG base address */
6527#define MCG_BASE (0x40064000u)
6528/** Peripheral MCG base pointer */
6529#define MCG ((MCG_Type *)MCG_BASE)
6530/** Array initializer of MCG peripheral base addresses */
6531#define MCG_BASE_ADDRS { MCG_BASE }
6532/** Array initializer of MCG peripheral base pointers */
6533#define MCG_BASE_PTRS { MCG }
6534
6535/*!
6536 * @}
6537 */ /* end of group MCG_Peripheral_Access_Layer */
6538
6539
6540/* ----------------------------------------------------------------------------
6541 -- MCM Peripheral Access Layer
6542 ---------------------------------------------------------------------------- */
6543
6544/*!
6545 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
6546 * @{
6547 */
6548
6549/** MCM - Register Layout Typedef */
6550typedef struct {
6551 uint8_t RESERVED_0[8];
6552 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
6553 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
6554 __IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
6555 __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
6556 uint8_t RESERVED_1[44];
6557 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
6558} MCM_Type;
6559
6560/* ----------------------------------------------------------------------------
6561 -- MCM Register Masks
6562 ---------------------------------------------------------------------------- */
6563
6564/*!
6565 * @addtogroup MCM_Register_Masks MCM Register Masks
6566 * @{
6567 */
6568
6569/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
6570/*! @{ */
6571#define MCM_PLASC_ASC_MASK (0xFFU)
6572#define MCM_PLASC_ASC_SHIFT (0U)
6573/*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
6574 * 0b00000000..A bus slave connection to AXBS input port n is absent
6575 * 0b00000001..A bus slave connection to AXBS input port n is present
6576 */
6577#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
6578/*! @} */
6579
6580/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
6581/*! @{ */
6582#define MCM_PLAMC_AMC_MASK (0xFFU)
6583#define MCM_PLAMC_AMC_SHIFT (0U)
6584/*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
6585 * 0b00000000..A bus master connection to AXBS input port n is absent
6586 * 0b00000001..A bus master connection to AXBS input port n is present
6587 */
6588#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
6589/*! @} */
6590
6591/*! @name PLACR - Crossbar Switch (AXBS) Control Register */
6592/*! @{ */
6593#define MCM_PLACR_ARB_MASK (0x200U)
6594#define MCM_PLACR_ARB_SHIFT (9U)
6595/*! ARB - Arbitration select
6596 * 0b0..Fixed-priority arbitration for the crossbar masters
6597 * 0b1..Round-robin arbitration for the crossbar masters
6598 */
6599#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
6600/*! @} */
6601
6602/*! @name ISCR - Interrupt Status and Control Register */
6603/*! @{ */
6604#define MCM_ISCR_FIOC_MASK (0x100U)
6605#define MCM_ISCR_FIOC_SHIFT (8U)
6606/*! FIOC - FPU invalid operation interrupt status
6607 * 0b0..No interrupt
6608 * 0b1..Interrupt occurred
6609 */
6610#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
6611#define MCM_ISCR_FDZC_MASK (0x200U)
6612#define MCM_ISCR_FDZC_SHIFT (9U)
6613/*! FDZC - FPU divide-by-zero interrupt status
6614 * 0b0..No interrupt
6615 * 0b1..Interrupt occurred
6616 */
6617#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
6618#define MCM_ISCR_FOFC_MASK (0x400U)
6619#define MCM_ISCR_FOFC_SHIFT (10U)
6620/*! FOFC - FPU overflow interrupt status
6621 * 0b0..No interrupt
6622 * 0b1..Interrupt occurred
6623 */
6624#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
6625#define MCM_ISCR_FUFC_MASK (0x800U)
6626#define MCM_ISCR_FUFC_SHIFT (11U)
6627/*! FUFC - FPU underflow interrupt status
6628 * 0b0..No interrupt
6629 * 0b1..Interrupt occurred
6630 */
6631#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
6632#define MCM_ISCR_FIXC_MASK (0x1000U)
6633#define MCM_ISCR_FIXC_SHIFT (12U)
6634/*! FIXC - FPU inexact interrupt status
6635 * 0b0..No interrupt
6636 * 0b1..Interrupt occurred
6637 */
6638#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
6639#define MCM_ISCR_FIDC_MASK (0x8000U)
6640#define MCM_ISCR_FIDC_SHIFT (15U)
6641/*! FIDC - FPU input denormal interrupt status
6642 * 0b0..No interrupt
6643 * 0b1..Interrupt occurred
6644 */
6645#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
6646#define MCM_ISCR_FIOCE_MASK (0x1000000U)
6647#define MCM_ISCR_FIOCE_SHIFT (24U)
6648/*! FIOCE - FPU invalid operation interrupt enable
6649 * 0b0..Disable interrupt
6650 * 0b1..Enable interrupt
6651 */
6652#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
6653#define MCM_ISCR_FDZCE_MASK (0x2000000U)
6654#define MCM_ISCR_FDZCE_SHIFT (25U)
6655/*! FDZCE - FPU divide-by-zero interrupt enable
6656 * 0b0..Disable interrupt
6657 * 0b1..Enable interrupt
6658 */
6659#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
6660#define MCM_ISCR_FOFCE_MASK (0x4000000U)
6661#define MCM_ISCR_FOFCE_SHIFT (26U)
6662/*! FOFCE - FPU overflow interrupt enable
6663 * 0b0..Disable interrupt
6664 * 0b1..Enable interrupt
6665 */
6666#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
6667#define MCM_ISCR_FUFCE_MASK (0x8000000U)
6668#define MCM_ISCR_FUFCE_SHIFT (27U)
6669/*! FUFCE - FPU underflow interrupt enable
6670 * 0b0..Disable interrupt
6671 * 0b1..Enable interrupt
6672 */
6673#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
6674#define MCM_ISCR_FIXCE_MASK (0x10000000U)
6675#define MCM_ISCR_FIXCE_SHIFT (28U)
6676/*! FIXCE - FPU inexact interrupt enable
6677 * 0b0..Disable interrupt
6678 * 0b1..Enable interrupt
6679 */
6680#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
6681#define MCM_ISCR_FIDCE_MASK (0x80000000U)
6682#define MCM_ISCR_FIDCE_SHIFT (31U)
6683/*! FIDCE - FPU input denormal interrupt enable
6684 * 0b0..Disable interrupt
6685 * 0b1..Enable interrupt
6686 */
6687#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
6688/*! @} */
6689
6690/*! @name CPO - Compute Operation Control Register */
6691/*! @{ */
6692#define MCM_CPO_CPOREQ_MASK (0x1U)
6693#define MCM_CPO_CPOREQ_SHIFT (0U)
6694/*! CPOREQ - Compute Operation request
6695 * 0b0..Request is cleared.
6696 * 0b1..Request Compute Operation.
6697 */
6698#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
6699#define MCM_CPO_CPOACK_MASK (0x2U)
6700#define MCM_CPO_CPOACK_SHIFT (1U)
6701/*! CPOACK - Compute Operation acknowledge
6702 * 0b0..Compute operation entry has not completed or compute operation exit has completed.
6703 * 0b1..Compute operation entry has completed or compute operation exit has not completed.
6704 */
6705#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
6706#define MCM_CPO_CPOWOI_MASK (0x4U)
6707#define MCM_CPO_CPOWOI_SHIFT (2U)
6708/*! CPOWOI - Compute Operation wakeup on interrupt
6709 * 0b0..No effect.
6710 * 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
6711 */
6712#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
6713/*! @} */
6714
6715
6716/*!
6717 * @}
6718 */ /* end of group MCM_Register_Masks */
6719
6720
6721/* MCM - Peripheral instance base addresses */
6722/** Peripheral MCM base address */
6723#define MCM_BASE (0xE0080000u)
6724/** Peripheral MCM base pointer */
6725#define MCM ((MCM_Type *)MCM_BASE)
6726/** Array initializer of MCM peripheral base addresses */
6727#define MCM_BASE_ADDRS { MCM_BASE }
6728/** Array initializer of MCM peripheral base pointers */
6729#define MCM_BASE_PTRS { MCM }
6730/** Interrupt vectors for the MCM peripheral type */
6731#define MCM_IRQS { MCM_IRQn }
6732
6733/*!
6734 * @}
6735 */ /* end of group MCM_Peripheral_Access_Layer */
6736
6737
6738/* ----------------------------------------------------------------------------
6739 -- NV Peripheral Access Layer
6740 ---------------------------------------------------------------------------- */
6741
6742/*!
6743 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
6744 * @{
6745 */
6746
6747/** NV - Register Layout Typedef */
6748typedef struct {
6749 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
6750 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
6751 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
6752 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
6753 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
6754 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
6755 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
6756 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
6757 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
6758 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
6759 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
6760 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
6761 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
6762 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
6763} NV_Type;
6764
6765/* ----------------------------------------------------------------------------
6766 -- NV Register Masks
6767 ---------------------------------------------------------------------------- */
6768
6769/*!
6770 * @addtogroup NV_Register_Masks NV Register Masks
6771 * @{
6772 */
6773
6774/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
6775/*! @{ */
6776#define NV_BACKKEY3_KEY_MASK (0xFFU)
6777#define NV_BACKKEY3_KEY_SHIFT (0U)
6778#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
6779/*! @} */
6780
6781/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
6782/*! @{ */
6783#define NV_BACKKEY2_KEY_MASK (0xFFU)
6784#define NV_BACKKEY2_KEY_SHIFT (0U)
6785#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
6786/*! @} */
6787
6788/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
6789/*! @{ */
6790#define NV_BACKKEY1_KEY_MASK (0xFFU)
6791#define NV_BACKKEY1_KEY_SHIFT (0U)
6792#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
6793/*! @} */
6794
6795/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
6796/*! @{ */
6797#define NV_BACKKEY0_KEY_MASK (0xFFU)
6798#define NV_BACKKEY0_KEY_SHIFT (0U)
6799#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
6800/*! @} */
6801
6802/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
6803/*! @{ */
6804#define NV_BACKKEY7_KEY_MASK (0xFFU)
6805#define NV_BACKKEY7_KEY_SHIFT (0U)
6806#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
6807/*! @} */
6808
6809/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
6810/*! @{ */
6811#define NV_BACKKEY6_KEY_MASK (0xFFU)
6812#define NV_BACKKEY6_KEY_SHIFT (0U)
6813#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
6814/*! @} */
6815
6816/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
6817/*! @{ */
6818#define NV_BACKKEY5_KEY_MASK (0xFFU)
6819#define NV_BACKKEY5_KEY_SHIFT (0U)
6820#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
6821/*! @} */
6822
6823/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
6824/*! @{ */
6825#define NV_BACKKEY4_KEY_MASK (0xFFU)
6826#define NV_BACKKEY4_KEY_SHIFT (0U)
6827#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
6828/*! @} */
6829
6830/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
6831/*! @{ */
6832#define NV_FPROT3_PROT_MASK (0xFFU)
6833#define NV_FPROT3_PROT_SHIFT (0U)
6834#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
6835/*! @} */
6836
6837/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
6838/*! @{ */
6839#define NV_FPROT2_PROT_MASK (0xFFU)
6840#define NV_FPROT2_PROT_SHIFT (0U)
6841#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
6842/*! @} */
6843
6844/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
6845/*! @{ */
6846#define NV_FPROT1_PROT_MASK (0xFFU)
6847#define NV_FPROT1_PROT_SHIFT (0U)
6848#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
6849/*! @} */
6850
6851/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
6852/*! @{ */
6853#define NV_FPROT0_PROT_MASK (0xFFU)
6854#define NV_FPROT0_PROT_SHIFT (0U)
6855#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
6856/*! @} */
6857
6858/*! @name FSEC - Non-volatile Flash Security Register */
6859/*! @{ */
6860#define NV_FSEC_SEC_MASK (0x3U)
6861#define NV_FSEC_SEC_SHIFT (0U)
6862/*! SEC - Flash Security
6863 * 0b10..MCU security status is unsecure
6864 * 0b11..MCU security status is secure
6865 */
6866#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
6867#define NV_FSEC_FSLACC_MASK (0xCU)
6868#define NV_FSEC_FSLACC_SHIFT (2U)
6869/*! FSLACC - Freescale Failure Analysis Access Code
6870 * 0b10..Freescale factory access denied
6871 * 0b11..Freescale factory access granted
6872 */
6873#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
6874#define NV_FSEC_MEEN_MASK (0x30U)
6875#define NV_FSEC_MEEN_SHIFT (4U)
6876/*! MEEN
6877 * 0b10..Mass erase is disabled
6878 * 0b11..Mass erase is enabled
6879 */
6880#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
6881#define NV_FSEC_KEYEN_MASK (0xC0U)
6882#define NV_FSEC_KEYEN_SHIFT (6U)
6883/*! KEYEN - Backdoor Key Security Enable
6884 * 0b10..Backdoor key access enabled
6885 * 0b11..Backdoor key access disabled
6886 */
6887#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
6888/*! @} */
6889
6890/*! @name FOPT - Non-volatile Flash Option Register */
6891/*! @{ */
6892#define NV_FOPT_LPBOOT_MASK (0x1U)
6893#define NV_FOPT_LPBOOT_SHIFT (0U)
6894/*! LPBOOT
6895 * 0b0..Low-power boot
6896 * 0b1..Normal boot
6897 */
6898#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
6899#define NV_FOPT_EZPORT_DIS_MASK (0x2U)
6900#define NV_FOPT_EZPORT_DIS_SHIFT (1U)
6901/*! EZPORT_DIS
6902 * 0b0..EzPort operation is disabled
6903 * 0b1..EzPort operation is enabled
6904 */
6905#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
6906#define NV_FOPT_NMI_DIS_MASK (0x4U)
6907#define NV_FOPT_NMI_DIS_SHIFT (2U)
6908/*! NMI_DIS
6909 * 0b0..NMI interrupts are always blocked
6910 * 0b1..NMI_b pin/interrupts reset default to enabled
6911 */
6912#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
6913#define NV_FOPT_FAST_INIT_MASK (0x20U)
6914#define NV_FOPT_FAST_INIT_SHIFT (5U)
6915/*! FAST_INIT
6916 * 0b0..Slower initialization
6917 * 0b1..Fast Initialization
6918 */
6919#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
6920/*! @} */
6921
6922
6923/*!
6924 * @}
6925 */ /* end of group NV_Register_Masks */
6926
6927
6928/* NV - Peripheral instance base addresses */
6929/** Peripheral FTFA_FlashConfig base address */
6930#define FTFA_FlashConfig_BASE (0x400u)
6931/** Peripheral FTFA_FlashConfig base pointer */
6932#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
6933/** Array initializer of NV peripheral base addresses */
6934#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
6935/** Array initializer of NV peripheral base pointers */
6936#define NV_BASE_PTRS { FTFA_FlashConfig }
6937
6938/*!
6939 * @}
6940 */ /* end of group NV_Peripheral_Access_Layer */
6941
6942
6943/* ----------------------------------------------------------------------------
6944 -- OSC Peripheral Access Layer
6945 ---------------------------------------------------------------------------- */
6946
6947/*!
6948 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
6949 * @{
6950 */
6951
6952/** OSC - Register Layout Typedef */
6953typedef struct {
6954 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
6955 uint8_t RESERVED_0[1];
6956 __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
6957} OSC_Type;
6958
6959/* ----------------------------------------------------------------------------
6960 -- OSC Register Masks
6961 ---------------------------------------------------------------------------- */
6962
6963/*!
6964 * @addtogroup OSC_Register_Masks OSC Register Masks
6965 * @{
6966 */
6967
6968/*! @name CR - OSC Control Register */
6969/*! @{ */
6970#define OSC_CR_SC16P_MASK (0x1U)
6971#define OSC_CR_SC16P_SHIFT (0U)
6972/*! SC16P - Oscillator 16 pF Capacitor Load Configure
6973 * 0b0..Disable the selection.
6974 * 0b1..Add 16 pF capacitor to the oscillator load.
6975 */
6976#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
6977#define OSC_CR_SC8P_MASK (0x2U)
6978#define OSC_CR_SC8P_SHIFT (1U)
6979/*! SC8P - Oscillator 8 pF Capacitor Load Configure
6980 * 0b0..Disable the selection.
6981 * 0b1..Add 8 pF capacitor to the oscillator load.
6982 */
6983#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
6984#define OSC_CR_SC4P_MASK (0x4U)
6985#define OSC_CR_SC4P_SHIFT (2U)
6986/*! SC4P - Oscillator 4 pF Capacitor Load Configure
6987 * 0b0..Disable the selection.
6988 * 0b1..Add 4 pF capacitor to the oscillator load.
6989 */
6990#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
6991#define OSC_CR_SC2P_MASK (0x8U)
6992#define OSC_CR_SC2P_SHIFT (3U)
6993/*! SC2P - Oscillator 2 pF Capacitor Load Configure
6994 * 0b0..Disable the selection.
6995 * 0b1..Add 2 pF capacitor to the oscillator load.
6996 */
6997#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
6998#define OSC_CR_EREFSTEN_MASK (0x20U)
6999#define OSC_CR_EREFSTEN_SHIFT (5U)
7000/*! EREFSTEN - External Reference Stop Enable
7001 * 0b0..External reference clock is disabled in Stop mode.
7002 * 0b1..External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
7003 */
7004#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
7005#define OSC_CR_ERCLKEN_MASK (0x80U)
7006#define OSC_CR_ERCLKEN_SHIFT (7U)
7007/*! ERCLKEN - External Reference Enable
7008 * 0b0..External reference clock is inactive.
7009 * 0b1..External reference clock is enabled.
7010 */
7011#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
7012/*! @} */
7013
7014/*! @name DIV - OSC_DIV */
7015/*! @{ */
7016#define OSC_DIV_ERPS_MASK (0xC0U)
7017#define OSC_DIV_ERPS_SHIFT (6U)
7018/*! ERPS
7019 * 0b00..The divisor ratio is 1.
7020 * 0b01..The divisor ratio is 2.
7021 * 0b10..The divisor ratio is 4.
7022 * 0b11..The divisor ratio is 8.
7023 */
7024#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
7025/*! @} */
7026
7027
7028/*!
7029 * @}
7030 */ /* end of group OSC_Register_Masks */
7031
7032
7033/* OSC - Peripheral instance base addresses */
7034/** Peripheral OSC base address */
7035#define OSC_BASE (0x40065000u)
7036/** Peripheral OSC base pointer */
7037#define OSC ((OSC_Type *)OSC_BASE)
7038/** Array initializer of OSC peripheral base addresses */
7039#define OSC_BASE_ADDRS { OSC_BASE }
7040/** Array initializer of OSC peripheral base pointers */
7041#define OSC_BASE_PTRS { OSC }
7042
7043/*!
7044 * @}
7045 */ /* end of group OSC_Peripheral_Access_Layer */
7046
7047
7048/* ----------------------------------------------------------------------------
7049 -- PDB Peripheral Access Layer
7050 ---------------------------------------------------------------------------- */
7051
7052/*!
7053 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
7054 * @{
7055 */
7056
7057/** PDB - Register Layout Typedef */
7058typedef struct {
7059 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
7060 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
7061 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
7062 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
7063 struct { /* offset: 0x10, array step: 0x28 */
7064 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
7065 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
7066 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
7067 uint8_t RESERVED_0[24];
7068 } CH[2];
7069 uint8_t RESERVED_0[240];
7070 struct { /* offset: 0x150, array step: 0x8 */
7071 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
7072 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
7073 } DAC[1];
7074 uint8_t RESERVED_1[56];
7075 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
7076 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
7077} PDB_Type;
7078
7079/* ----------------------------------------------------------------------------
7080 -- PDB Register Masks
7081 ---------------------------------------------------------------------------- */
7082
7083/*!
7084 * @addtogroup PDB_Register_Masks PDB Register Masks
7085 * @{
7086 */
7087
7088/*! @name SC - Status and Control register */
7089/*! @{ */
7090#define PDB_SC_LDOK_MASK (0x1U)
7091#define PDB_SC_LDOK_SHIFT (0U)
7092#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
7093#define PDB_SC_CONT_MASK (0x2U)
7094#define PDB_SC_CONT_SHIFT (1U)
7095/*! CONT - Continuous Mode Enable
7096 * 0b0..PDB operation in One-Shot mode
7097 * 0b1..PDB operation in Continuous mode
7098 */
7099#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
7100#define PDB_SC_MULT_MASK (0xCU)
7101#define PDB_SC_MULT_SHIFT (2U)
7102/*! MULT - Multiplication Factor Select for Prescaler
7103 * 0b00..Multiplication factor is 1.
7104 * 0b01..Multiplication factor is 10.
7105 * 0b10..Multiplication factor is 20.
7106 * 0b11..Multiplication factor is 40.
7107 */
7108#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
7109#define PDB_SC_PDBIE_MASK (0x20U)
7110#define PDB_SC_PDBIE_SHIFT (5U)
7111/*! PDBIE - PDB Interrupt Enable
7112 * 0b0..PDB interrupt disabled.
7113 * 0b1..PDB interrupt enabled.
7114 */
7115#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
7116#define PDB_SC_PDBIF_MASK (0x40U)
7117#define PDB_SC_PDBIF_SHIFT (6U)
7118#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
7119#define PDB_SC_PDBEN_MASK (0x80U)
7120#define PDB_SC_PDBEN_SHIFT (7U)
7121/*! PDBEN - PDB Enable
7122 * 0b0..PDB disabled. Counter is off.
7123 * 0b1..PDB enabled.
7124 */
7125#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
7126#define PDB_SC_TRGSEL_MASK (0xF00U)
7127#define PDB_SC_TRGSEL_SHIFT (8U)
7128/*! TRGSEL - Trigger Input Source Select
7129 * 0b0000..Trigger-In 0 is selected.
7130 * 0b0001..Trigger-In 1 is selected.
7131 * 0b0010..Trigger-In 2 is selected.
7132 * 0b0011..Trigger-In 3 is selected.
7133 * 0b0100..Trigger-In 4 is selected.
7134 * 0b0101..Trigger-In 5 is selected.
7135 * 0b0110..Trigger-In 6 is selected.
7136 * 0b0111..Trigger-In 7 is selected.
7137 * 0b1000..Trigger-In 8 is selected.
7138 * 0b1001..Trigger-In 9 is selected.
7139 * 0b1010..Trigger-In 10 is selected.
7140 * 0b1011..Trigger-In 11 is selected.
7141 * 0b1100..Trigger-In 12 is selected.
7142 * 0b1101..Trigger-In 13 is selected.
7143 * 0b1110..Trigger-In 14 is selected.
7144 * 0b1111..Software trigger is selected.
7145 */
7146#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
7147#define PDB_SC_PRESCALER_MASK (0x7000U)
7148#define PDB_SC_PRESCALER_SHIFT (12U)
7149/*! PRESCALER - Prescaler Divider Select
7150 * 0b000..Counting uses the peripheral clock divided by multiplication factor selected by MULT.
7151 * 0b001..Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.
7152 * 0b010..Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT.
7153 * 0b011..Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT.
7154 * 0b100..Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT.
7155 * 0b101..Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT.
7156 * 0b110..Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT.
7157 * 0b111..Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT.
7158 */
7159#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
7160#define PDB_SC_DMAEN_MASK (0x8000U)
7161#define PDB_SC_DMAEN_SHIFT (15U)
7162/*! DMAEN - DMA Enable
7163 * 0b0..DMA disabled.
7164 * 0b1..DMA enabled.
7165 */
7166#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
7167#define PDB_SC_SWTRIG_MASK (0x10000U)
7168#define PDB_SC_SWTRIG_SHIFT (16U)
7169#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
7170#define PDB_SC_PDBEIE_MASK (0x20000U)
7171#define PDB_SC_PDBEIE_SHIFT (17U)
7172/*! PDBEIE - PDB Sequence Error Interrupt Enable
7173 * 0b0..PDB sequence error interrupt disabled.
7174 * 0b1..PDB sequence error interrupt enabled.
7175 */
7176#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
7177#define PDB_SC_LDMOD_MASK (0xC0000U)
7178#define PDB_SC_LDMOD_SHIFT (18U)
7179/*! LDMOD - Load Mode Select
7180 * 0b00..The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.
7181 * 0b01..The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK.
7182 * 0b10..The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK.
7183 * 0b11..The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.
7184 */
7185#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
7186/*! @} */
7187
7188/*! @name MOD - Modulus register */
7189/*! @{ */
7190#define PDB_MOD_MOD_MASK (0xFFFFU)
7191#define PDB_MOD_MOD_SHIFT (0U)
7192#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
7193/*! @} */
7194
7195/*! @name CNT - Counter register */
7196/*! @{ */
7197#define PDB_CNT_CNT_MASK (0xFFFFU)
7198#define PDB_CNT_CNT_SHIFT (0U)
7199#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
7200/*! @} */
7201
7202/*! @name IDLY - Interrupt Delay register */
7203/*! @{ */
7204#define PDB_IDLY_IDLY_MASK (0xFFFFU)
7205#define PDB_IDLY_IDLY_SHIFT (0U)
7206#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
7207/*! @} */
7208
7209/*! @name C1 - Channel n Control register 1 */
7210/*! @{ */
7211#define PDB_C1_EN_MASK (0xFFU)
7212#define PDB_C1_EN_SHIFT (0U)
7213/*! EN - PDB Channel Pre-Trigger Enable
7214 * 0b00000000..PDB channel's corresponding pre-trigger disabled.
7215 * 0b00000001..PDB channel's corresponding pre-trigger enabled.
7216 */
7217#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
7218#define PDB_C1_TOS_MASK (0xFF00U)
7219#define PDB_C1_TOS_SHIFT (8U)
7220/*! TOS - PDB Channel Pre-Trigger Output Select
7221 * 0b00000000..PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
7222 * 0b00000001..PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
7223 */
7224#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
7225#define PDB_C1_BB_MASK (0xFF0000U)
7226#define PDB_C1_BB_SHIFT (16U)
7227/*! BB - PDB Channel Pre-Trigger Back-to-Back Operation Enable
7228 * 0b00000000..PDB channel's corresponding pre-trigger back-to-back operation disabled.
7229 * 0b00000001..PDB channel's corresponding pre-trigger back-to-back operation enabled.
7230 */
7231#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
7232/*! @} */
7233
7234/* The count of PDB_C1 */
7235#define PDB_C1_COUNT (2U)
7236
7237/*! @name S - Channel n Status register */
7238/*! @{ */
7239#define PDB_S_ERR_MASK (0xFFU)
7240#define PDB_S_ERR_SHIFT (0U)
7241/*! ERR - PDB Channel Sequence Error Flags
7242 * 0b00000000..Sequence error not detected on PDB channel's corresponding pre-trigger.
7243 * 0b00000001..Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
7244 */
7245#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
7246#define PDB_S_CF_MASK (0xFF0000U)
7247#define PDB_S_CF_SHIFT (16U)
7248#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
7249/*! @} */
7250
7251/* The count of PDB_S */
7252#define PDB_S_COUNT (2U)
7253
7254/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
7255/*! @{ */
7256#define PDB_DLY_DLY_MASK (0xFFFFU)
7257#define PDB_DLY_DLY_SHIFT (0U)
7258#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
7259/*! @} */
7260
7261/* The count of PDB_DLY */
7262#define PDB_DLY_COUNT (2U)
7263
7264/* The count of PDB_DLY */
7265#define PDB_DLY_COUNT2 (2U)
7266
7267/*! @name INTC - DAC Interval Trigger n Control register */
7268/*! @{ */
7269#define PDB_INTC_TOE_MASK (0x1U)
7270#define PDB_INTC_TOE_SHIFT (0U)
7271/*! TOE - DAC Interval Trigger Enable
7272 * 0b0..DAC interval trigger disabled.
7273 * 0b1..DAC interval trigger enabled.
7274 */
7275#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
7276#define PDB_INTC_EXT_MASK (0x2U)
7277#define PDB_INTC_EXT_SHIFT (1U)
7278/*! EXT - DAC External Trigger Input Enable
7279 * 0b0..DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
7280 * 0b1..DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger.
7281 */
7282#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
7283/*! @} */
7284
7285/* The count of PDB_INTC */
7286#define PDB_INTC_COUNT (1U)
7287
7288/*! @name INT - DAC Interval n register */
7289/*! @{ */
7290#define PDB_INT_INT_MASK (0xFFFFU)
7291#define PDB_INT_INT_SHIFT (0U)
7292#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
7293/*! @} */
7294
7295/* The count of PDB_INT */
7296#define PDB_INT_COUNT (1U)
7297
7298/*! @name POEN - Pulse-Out n Enable register */
7299/*! @{ */
7300#define PDB_POEN_POEN_MASK (0xFFU)
7301#define PDB_POEN_POEN_SHIFT (0U)
7302/*! POEN - PDB Pulse-Out Enable
7303 * 0b00000000..PDB Pulse-Out disabled
7304 * 0b00000001..PDB Pulse-Out enabled
7305 */
7306#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
7307/*! @} */
7308
7309/*! @name PODLY - Pulse-Out n Delay register */
7310/*! @{ */
7311#define PDB_PODLY_DLY2_MASK (0xFFFFU)
7312#define PDB_PODLY_DLY2_SHIFT (0U)
7313#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
7314#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
7315#define PDB_PODLY_DLY1_SHIFT (16U)
7316#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
7317/*! @} */
7318
7319/* The count of PDB_PODLY */
7320#define PDB_PODLY_COUNT (2U)
7321
7322
7323/*!
7324 * @}
7325 */ /* end of group PDB_Register_Masks */
7326
7327
7328/* PDB - Peripheral instance base addresses */
7329/** Peripheral PDB0 base address */
7330#define PDB0_BASE (0x40036000u)
7331/** Peripheral PDB0 base pointer */
7332#define PDB0 ((PDB_Type *)PDB0_BASE)
7333/** Array initializer of PDB peripheral base addresses */
7334#define PDB_BASE_ADDRS { PDB0_BASE }
7335/** Array initializer of PDB peripheral base pointers */
7336#define PDB_BASE_PTRS { PDB0 }
7337/** Interrupt vectors for the PDB peripheral type */
7338#define PDB_IRQS { PDB0_IRQn }
7339
7340/*!
7341 * @}
7342 */ /* end of group PDB_Peripheral_Access_Layer */
7343
7344
7345/* ----------------------------------------------------------------------------
7346 -- PIT Peripheral Access Layer
7347 ---------------------------------------------------------------------------- */
7348
7349/*!
7350 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
7351 * @{
7352 */
7353
7354/** PIT - Register Layout Typedef */
7355typedef struct {
7356 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
7357 uint8_t RESERVED_0[252];
7358 struct { /* offset: 0x100, array step: 0x10 */
7359 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
7360 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
7361 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
7362 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
7363 } CHANNEL[4];
7364} PIT_Type;
7365
7366/* ----------------------------------------------------------------------------
7367 -- PIT Register Masks
7368 ---------------------------------------------------------------------------- */
7369
7370/*!
7371 * @addtogroup PIT_Register_Masks PIT Register Masks
7372 * @{
7373 */
7374
7375/*! @name MCR - PIT Module Control Register */
7376/*! @{ */
7377#define PIT_MCR_FRZ_MASK (0x1U)
7378#define PIT_MCR_FRZ_SHIFT (0U)
7379/*! FRZ - Freeze
7380 * 0b0..Timers continue to run in Debug mode.
7381 * 0b1..Timers are stopped in Debug mode.
7382 */
7383#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
7384#define PIT_MCR_MDIS_MASK (0x2U)
7385#define PIT_MCR_MDIS_SHIFT (1U)
7386/*! MDIS - Module Disable - (PIT section)
7387 * 0b0..Clock for standard PIT timers is enabled.
7388 * 0b1..Clock for standard PIT timers is disabled.
7389 */
7390#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
7391/*! @} */
7392
7393/*! @name LDVAL - Timer Load Value Register */
7394/*! @{ */
7395#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
7396#define PIT_LDVAL_TSV_SHIFT (0U)
7397#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
7398/*! @} */
7399
7400/* The count of PIT_LDVAL */
7401#define PIT_LDVAL_COUNT (4U)
7402
7403/*! @name CVAL - Current Timer Value Register */
7404/*! @{ */
7405#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
7406#define PIT_CVAL_TVL_SHIFT (0U)
7407#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
7408/*! @} */
7409
7410/* The count of PIT_CVAL */
7411#define PIT_CVAL_COUNT (4U)
7412
7413/*! @name TCTRL - Timer Control Register */
7414/*! @{ */
7415#define PIT_TCTRL_TEN_MASK (0x1U)
7416#define PIT_TCTRL_TEN_SHIFT (0U)
7417/*! TEN - Timer Enable
7418 * 0b0..Timer n is disabled.
7419 * 0b1..Timer n is enabled.
7420 */
7421#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
7422#define PIT_TCTRL_TIE_MASK (0x2U)
7423#define PIT_TCTRL_TIE_SHIFT (1U)
7424/*! TIE - Timer Interrupt Enable
7425 * 0b0..Interrupt requests from Timer n are disabled.
7426 * 0b1..Interrupt will be requested whenever TIF is set.
7427 */
7428#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
7429#define PIT_TCTRL_CHN_MASK (0x4U)
7430#define PIT_TCTRL_CHN_SHIFT (2U)
7431/*! CHN - Chain Mode
7432 * 0b0..Timer is not chained.
7433 * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
7434 */
7435#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
7436/*! @} */
7437
7438/* The count of PIT_TCTRL */
7439#define PIT_TCTRL_COUNT (4U)
7440
7441/*! @name TFLG - Timer Flag Register */
7442/*! @{ */
7443#define PIT_TFLG_TIF_MASK (0x1U)
7444#define PIT_TFLG_TIF_SHIFT (0U)
7445/*! TIF - Timer Interrupt Flag
7446 * 0b0..Timeout has not yet occurred.
7447 * 0b1..Timeout has occurred.
7448 */
7449#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
7450/*! @} */
7451
7452/* The count of PIT_TFLG */
7453#define PIT_TFLG_COUNT (4U)
7454
7455
7456/*!
7457 * @}
7458 */ /* end of group PIT_Register_Masks */
7459
7460
7461/* PIT - Peripheral instance base addresses */
7462/** Peripheral PIT base address */
7463#define PIT_BASE (0x40037000u)
7464/** Peripheral PIT base pointer */
7465#define PIT ((PIT_Type *)PIT_BASE)
7466/** Array initializer of PIT peripheral base addresses */
7467#define PIT_BASE_ADDRS { PIT_BASE }
7468/** Array initializer of PIT peripheral base pointers */
7469#define PIT_BASE_PTRS { PIT }
7470/** Interrupt vectors for the PIT peripheral type */
7471#define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
7472
7473/*!
7474 * @}
7475 */ /* end of group PIT_Peripheral_Access_Layer */
7476
7477
7478/* ----------------------------------------------------------------------------
7479 -- PMC Peripheral Access Layer
7480 ---------------------------------------------------------------------------- */
7481
7482/*!
7483 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
7484 * @{
7485 */
7486
7487/** PMC - Register Layout Typedef */
7488typedef struct {
7489 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
7490 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
7491 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
7492} PMC_Type;
7493
7494/* ----------------------------------------------------------------------------
7495 -- PMC Register Masks
7496 ---------------------------------------------------------------------------- */
7497
7498/*!
7499 * @addtogroup PMC_Register_Masks PMC Register Masks
7500 * @{
7501 */
7502
7503/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
7504/*! @{ */
7505#define PMC_LVDSC1_LVDV_MASK (0x3U)
7506#define PMC_LVDSC1_LVDV_SHIFT (0U)
7507/*! LVDV - Low-Voltage Detect Voltage Select
7508 * 0b00..Low trip point selected (V LVD = V LVDL )
7509 * 0b01..High trip point selected (V LVD = V LVDH )
7510 * 0b10..Reserved
7511 * 0b11..Reserved
7512 */
7513#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
7514#define PMC_LVDSC1_LVDRE_MASK (0x10U)
7515#define PMC_LVDSC1_LVDRE_SHIFT (4U)
7516/*! LVDRE - Low-Voltage Detect Reset Enable
7517 * 0b0..LVDF does not generate hardware resets
7518 * 0b1..Force an MCU reset when LVDF = 1
7519 */
7520#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
7521#define PMC_LVDSC1_LVDIE_MASK (0x20U)
7522#define PMC_LVDSC1_LVDIE_SHIFT (5U)
7523/*! LVDIE - Low-Voltage Detect Interrupt Enable
7524 * 0b0..Hardware interrupt disabled (use polling)
7525 * 0b1..Request a hardware interrupt when LVDF = 1
7526 */
7527#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
7528#define PMC_LVDSC1_LVDACK_MASK (0x40U)
7529#define PMC_LVDSC1_LVDACK_SHIFT (6U)
7530#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
7531#define PMC_LVDSC1_LVDF_MASK (0x80U)
7532#define PMC_LVDSC1_LVDF_SHIFT (7U)
7533/*! LVDF - Low-Voltage Detect Flag
7534 * 0b0..Low-voltage event not detected
7535 * 0b1..Low-voltage event detected
7536 */
7537#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
7538/*! @} */
7539
7540/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
7541/*! @{ */
7542#define PMC_LVDSC2_LVWV_MASK (0x3U)
7543#define PMC_LVDSC2_LVWV_SHIFT (0U)
7544/*! LVWV - Low-Voltage Warning Voltage Select
7545 * 0b00..Low trip point selected (VLVW = VLVW1)
7546 * 0b01..Mid 1 trip point selected (VLVW = VLVW2)
7547 * 0b10..Mid 2 trip point selected (VLVW = VLVW3)
7548 * 0b11..High trip point selected (VLVW = VLVW4)
7549 */
7550#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
7551#define PMC_LVDSC2_LVWIE_MASK (0x20U)
7552#define PMC_LVDSC2_LVWIE_SHIFT (5U)
7553/*! LVWIE - Low-Voltage Warning Interrupt Enable
7554 * 0b0..Hardware interrupt disabled (use polling)
7555 * 0b1..Request a hardware interrupt when LVWF = 1
7556 */
7557#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
7558#define PMC_LVDSC2_LVWACK_MASK (0x40U)
7559#define PMC_LVDSC2_LVWACK_SHIFT (6U)
7560#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
7561#define PMC_LVDSC2_LVWF_MASK (0x80U)
7562#define PMC_LVDSC2_LVWF_SHIFT (7U)
7563/*! LVWF - Low-Voltage Warning Flag
7564 * 0b0..Low-voltage warning event not detected
7565 * 0b1..Low-voltage warning event detected
7566 */
7567#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
7568/*! @} */
7569
7570/*! @name REGSC - Regulator Status And Control register */
7571/*! @{ */
7572#define PMC_REGSC_BGBE_MASK (0x1U)
7573#define PMC_REGSC_BGBE_SHIFT (0U)
7574/*! BGBE - Bandgap Buffer Enable
7575 * 0b0..Bandgap buffer not enabled
7576 * 0b1..Bandgap buffer enabled
7577 */
7578#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
7579#define PMC_REGSC_REGONS_MASK (0x4U)
7580#define PMC_REGSC_REGONS_SHIFT (2U)
7581/*! REGONS - Regulator In Run Regulation Status
7582 * 0b0..Regulator is in stop regulation or in transition to/from it
7583 * 0b1..Regulator is in run regulation
7584 */
7585#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
7586#define PMC_REGSC_ACKISO_MASK (0x8U)
7587#define PMC_REGSC_ACKISO_SHIFT (3U)
7588/*! ACKISO - Acknowledge Isolation
7589 * 0b0..Peripherals and I/O pads are in normal run state.
7590 * 0b1..Certain peripherals and I/O pads are in an isolated and latched state.
7591 */
7592#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
7593#define PMC_REGSC_BGEN_MASK (0x10U)
7594#define PMC_REGSC_BGEN_SHIFT (4U)
7595/*! BGEN - Bandgap Enable In VLPx Operation
7596 * 0b0..Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
7597 * 0b1..Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
7598 */
7599#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
7600/*! @} */
7601
7602
7603/*!
7604 * @}
7605 */ /* end of group PMC_Register_Masks */
7606
7607
7608/* PMC - Peripheral instance base addresses */
7609/** Peripheral PMC base address */
7610#define PMC_BASE (0x4007D000u)
7611/** Peripheral PMC base pointer */
7612#define PMC ((PMC_Type *)PMC_BASE)
7613/** Array initializer of PMC peripheral base addresses */
7614#define PMC_BASE_ADDRS { PMC_BASE }
7615/** Array initializer of PMC peripheral base pointers */
7616#define PMC_BASE_PTRS { PMC }
7617/** Interrupt vectors for the PMC peripheral type */
7618#define PMC_IRQS { LVD_LVW_IRQn }
7619
7620/*!
7621 * @}
7622 */ /* end of group PMC_Peripheral_Access_Layer */
7623
7624
7625/* ----------------------------------------------------------------------------
7626 -- PORT Peripheral Access Layer
7627 ---------------------------------------------------------------------------- */
7628
7629/*!
7630 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
7631 * @{
7632 */
7633
7634/** PORT - Register Layout Typedef */
7635typedef struct {
7636 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
7637 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
7638 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
7639 uint8_t RESERVED_0[24];
7640 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
7641 uint8_t RESERVED_1[28];
7642 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
7643 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
7644 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
7645} PORT_Type;
7646
7647/* ----------------------------------------------------------------------------
7648 -- PORT Register Masks
7649 ---------------------------------------------------------------------------- */
7650
7651/*!
7652 * @addtogroup PORT_Register_Masks PORT Register Masks
7653 * @{
7654 */
7655
7656/*! @name PCR - Pin Control Register n */
7657/*! @{ */
7658#define PORT_PCR_PS_MASK (0x1U)
7659#define PORT_PCR_PS_SHIFT (0U)
7660/*! PS - Pull Select
7661 * 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
7662 * 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
7663 */
7664#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
7665#define PORT_PCR_PE_MASK (0x2U)
7666#define PORT_PCR_PE_SHIFT (1U)
7667/*! PE - Pull Enable
7668 * 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin.
7669 * 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
7670 */
7671#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
7672#define PORT_PCR_SRE_MASK (0x4U)
7673#define PORT_PCR_SRE_SHIFT (2U)
7674/*! SRE - Slew Rate Enable
7675 * 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
7676 * 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
7677 */
7678#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
7679#define PORT_PCR_PFE_MASK (0x10U)
7680#define PORT_PCR_PFE_SHIFT (4U)
7681/*! PFE - Passive Filter Enable
7682 * 0b0..Passive input filter is disabled on the corresponding pin.
7683 * 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
7684 */
7685#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
7686#define PORT_PCR_ODE_MASK (0x20U)
7687#define PORT_PCR_ODE_SHIFT (5U)
7688/*! ODE - Open Drain Enable
7689 * 0b0..Open drain output is disabled on the corresponding pin.
7690 * 0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
7691 */
7692#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
7693#define PORT_PCR_DSE_MASK (0x40U)
7694#define PORT_PCR_DSE_SHIFT (6U)
7695/*! DSE - Drive Strength Enable
7696 * 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
7697 * 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
7698 */
7699#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
7700#define PORT_PCR_MUX_MASK (0x700U)
7701#define PORT_PCR_MUX_SHIFT (8U)
7702/*! MUX - Pin Mux Control
7703 * 0b000..Pin disabled (analog).
7704 * 0b001..Alternative 1 (GPIO).
7705 * 0b010..Alternative 2 (chip-specific).
7706 * 0b011..Alternative 3 (chip-specific).
7707 * 0b100..Alternative 4 (chip-specific).
7708 * 0b101..Alternative 5 (chip-specific).
7709 * 0b110..Alternative 6 (chip-specific).
7710 * 0b111..Alternative 7 (chip-specific).
7711 */
7712#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
7713#define PORT_PCR_LK_MASK (0x8000U)
7714#define PORT_PCR_LK_SHIFT (15U)
7715/*! LK - Lock Register
7716 * 0b0..Pin Control Register fields [15:0] are not locked.
7717 * 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
7718 */
7719#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
7720#define PORT_PCR_IRQC_MASK (0xF0000U)
7721#define PORT_PCR_IRQC_SHIFT (16U)
7722/*! IRQC - Interrupt Configuration
7723 * 0b0000..Interrupt/DMA request disabled.
7724 * 0b0001..DMA request on rising edge.
7725 * 0b0010..DMA request on falling edge.
7726 * 0b0011..DMA request on either edge.
7727 * 0b1000..Interrupt when logic 0.
7728 * 0b1001..Interrupt on rising-edge.
7729 * 0b1010..Interrupt on falling-edge.
7730 * 0b1011..Interrupt on either edge.
7731 * 0b1100..Interrupt when logic 1.
7732 */
7733#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
7734#define PORT_PCR_ISF_MASK (0x1000000U)
7735#define PORT_PCR_ISF_SHIFT (24U)
7736/*! ISF - Interrupt Status Flag
7737 * 0b0..Configured interrupt is not detected.
7738 * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
7739 */
7740#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
7741/*! @} */
7742
7743/* The count of PORT_PCR */
7744#define PORT_PCR_COUNT (32U)
7745
7746/*! @name GPCLR - Global Pin Control Low Register */
7747/*! @{ */
7748#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
7749#define PORT_GPCLR_GPWD_SHIFT (0U)
7750#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
7751#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
7752#define PORT_GPCLR_GPWE_SHIFT (16U)
7753/*! GPWE - Global Pin Write Enable
7754 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
7755 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
7756 */
7757#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
7758/*! @} */
7759
7760/*! @name GPCHR - Global Pin Control High Register */
7761/*! @{ */
7762#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
7763#define PORT_GPCHR_GPWD_SHIFT (0U)
7764#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
7765#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
7766#define PORT_GPCHR_GPWE_SHIFT (16U)
7767/*! GPWE - Global Pin Write Enable
7768 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
7769 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
7770 */
7771#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
7772/*! @} */
7773
7774/*! @name ISFR - Interrupt Status Flag Register */
7775/*! @{ */
7776#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
7777#define PORT_ISFR_ISF_SHIFT (0U)
7778/*! ISF - Interrupt Status Flag
7779 * 0b00000000000000000000000000000000..Configured interrupt is not detected.
7780 * 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
7781 */
7782#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
7783/*! @} */
7784
7785/*! @name DFER - Digital Filter Enable Register */
7786/*! @{ */
7787#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
7788#define PORT_DFER_DFE_SHIFT (0U)
7789/*! DFE - Digital Filter Enable
7790 * 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
7791 * 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
7792 */
7793#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
7794/*! @} */
7795
7796/*! @name DFCR - Digital Filter Clock Register */
7797/*! @{ */
7798#define PORT_DFCR_CS_MASK (0x1U)
7799#define PORT_DFCR_CS_SHIFT (0U)
7800/*! CS - Clock Source
7801 * 0b0..Digital filters are clocked by the bus clock.
7802 * 0b1..Digital filters are clocked by the 1 kHz LPO clock.
7803 */
7804#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
7805/*! @} */
7806
7807/*! @name DFWR - Digital Filter Width Register */
7808/*! @{ */
7809#define PORT_DFWR_FILT_MASK (0x1FU)
7810#define PORT_DFWR_FILT_SHIFT (0U)
7811#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
7812/*! @} */
7813
7814
7815/*!
7816 * @}
7817 */ /* end of group PORT_Register_Masks */
7818
7819
7820/* PORT - Peripheral instance base addresses */
7821/** Peripheral PORTA base address */
7822#define PORTA_BASE (0x40049000u)
7823/** Peripheral PORTA base pointer */
7824#define PORTA ((PORT_Type *)PORTA_BASE)
7825/** Peripheral PORTB base address */
7826#define PORTB_BASE (0x4004A000u)
7827/** Peripheral PORTB base pointer */
7828#define PORTB ((PORT_Type *)PORTB_BASE)
7829/** Peripheral PORTC base address */
7830#define PORTC_BASE (0x4004B000u)
7831/** Peripheral PORTC base pointer */
7832#define PORTC ((PORT_Type *)PORTC_BASE)
7833/** Peripheral PORTD base address */
7834#define PORTD_BASE (0x4004C000u)
7835/** Peripheral PORTD base pointer */
7836#define PORTD ((PORT_Type *)PORTD_BASE)
7837/** Peripheral PORTE base address */
7838#define PORTE_BASE (0x4004D000u)
7839/** Peripheral PORTE base pointer */
7840#define PORTE ((PORT_Type *)PORTE_BASE)
7841/** Array initializer of PORT peripheral base addresses */
7842#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
7843/** Array initializer of PORT peripheral base pointers */
7844#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
7845/** Interrupt vectors for the PORT peripheral type */
7846#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
7847
7848/*!
7849 * @}
7850 */ /* end of group PORT_Peripheral_Access_Layer */
7851
7852
7853/* ----------------------------------------------------------------------------
7854 -- RCM Peripheral Access Layer
7855 ---------------------------------------------------------------------------- */
7856
7857/*!
7858 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
7859 * @{
7860 */
7861
7862/** RCM - Register Layout Typedef */
7863typedef struct {
7864 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
7865 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
7866 uint8_t RESERVED_0[2];
7867 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
7868 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
7869 uint8_t RESERVED_1[2];
7870 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
7871 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
7872} RCM_Type;
7873
7874/* ----------------------------------------------------------------------------
7875 -- RCM Register Masks
7876 ---------------------------------------------------------------------------- */
7877
7878/*!
7879 * @addtogroup RCM_Register_Masks RCM Register Masks
7880 * @{
7881 */
7882
7883/*! @name SRS0 - System Reset Status Register 0 */
7884/*! @{ */
7885#define RCM_SRS0_WAKEUP_MASK (0x1U)
7886#define RCM_SRS0_WAKEUP_SHIFT (0U)
7887/*! WAKEUP - Low Leakage Wakeup Reset
7888 * 0b0..Reset not caused by LLWU module wakeup source
7889 * 0b1..Reset caused by LLWU module wakeup source
7890 */
7891#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
7892#define RCM_SRS0_LVD_MASK (0x2U)
7893#define RCM_SRS0_LVD_SHIFT (1U)
7894/*! LVD - Low-Voltage Detect Reset
7895 * 0b0..Reset not caused by LVD trip or POR
7896 * 0b1..Reset caused by LVD trip or POR
7897 */
7898#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
7899#define RCM_SRS0_LOC_MASK (0x4U)
7900#define RCM_SRS0_LOC_SHIFT (2U)
7901/*! LOC - Loss-of-Clock Reset
7902 * 0b0..Reset not caused by a loss of external clock.
7903 * 0b1..Reset caused by a loss of external clock.
7904 */
7905#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
7906#define RCM_SRS0_WDOG_MASK (0x20U)
7907#define RCM_SRS0_WDOG_SHIFT (5U)
7908/*! WDOG - Watchdog
7909 * 0b0..Reset not caused by watchdog timeout
7910 * 0b1..Reset caused by watchdog timeout
7911 */
7912#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
7913#define RCM_SRS0_PIN_MASK (0x40U)
7914#define RCM_SRS0_PIN_SHIFT (6U)
7915/*! PIN - External Reset Pin
7916 * 0b0..Reset not caused by external reset pin
7917 * 0b1..Reset caused by external reset pin
7918 */
7919#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
7920#define RCM_SRS0_POR_MASK (0x80U)
7921#define RCM_SRS0_POR_SHIFT (7U)
7922/*! POR - Power-On Reset
7923 * 0b0..Reset not caused by POR
7924 * 0b1..Reset caused by POR
7925 */
7926#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
7927/*! @} */
7928
7929/*! @name SRS1 - System Reset Status Register 1 */
7930/*! @{ */
7931#define RCM_SRS1_JTAG_MASK (0x1U)
7932#define RCM_SRS1_JTAG_SHIFT (0U)
7933/*! JTAG - JTAG Generated Reset
7934 * 0b0..Reset not caused by JTAG
7935 * 0b1..Reset caused by JTAG
7936 */
7937#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
7938#define RCM_SRS1_LOCKUP_MASK (0x2U)
7939#define RCM_SRS1_LOCKUP_SHIFT (1U)
7940/*! LOCKUP - Core Lockup
7941 * 0b0..Reset not caused by core LOCKUP event
7942 * 0b1..Reset caused by core LOCKUP event
7943 */
7944#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
7945#define RCM_SRS1_SW_MASK (0x4U)
7946#define RCM_SRS1_SW_SHIFT (2U)
7947/*! SW - Software
7948 * 0b0..Reset not caused by software setting of SYSRESETREQ bit
7949 * 0b1..Reset caused by software setting of SYSRESETREQ bit
7950 */
7951#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
7952#define RCM_SRS1_MDM_AP_MASK (0x8U)
7953#define RCM_SRS1_MDM_AP_SHIFT (3U)
7954/*! MDM_AP - MDM-AP System Reset Request
7955 * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit
7956 * 0b1..Reset caused by host debugger system setting of the System Reset Request bit
7957 */
7958#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
7959#define RCM_SRS1_SACKERR_MASK (0x20U)
7960#define RCM_SRS1_SACKERR_SHIFT (5U)
7961/*! SACKERR - Stop Mode Acknowledge Error Reset
7962 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
7963 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
7964 */
7965#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
7966/*! @} */
7967
7968/*! @name RPFC - Reset Pin Filter Control register */
7969/*! @{ */
7970#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
7971#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
7972/*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes
7973 * 0b00..All filtering disabled
7974 * 0b01..Bus clock filter enabled for normal operation
7975 * 0b10..LPO clock filter enabled for normal operation
7976 * 0b11..Reserved
7977 */
7978#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
7979#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
7980#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
7981/*! RSTFLTSS - Reset Pin Filter Select in Stop Mode
7982 * 0b0..All filtering disabled
7983 * 0b1..LPO clock filter enabled
7984 */
7985#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
7986/*! @} */
7987
7988/*! @name RPFW - Reset Pin Filter Width register */
7989/*! @{ */
7990#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
7991#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
7992/*! RSTFLTSEL - Reset Pin Filter Bus Clock Select
7993 * 0b00000..Bus clock filter count is 1
7994 * 0b00001..Bus clock filter count is 2
7995 * 0b00010..Bus clock filter count is 3
7996 * 0b00011..Bus clock filter count is 4
7997 * 0b00100..Bus clock filter count is 5
7998 * 0b00101..Bus clock filter count is 6
7999 * 0b00110..Bus clock filter count is 7
8000 * 0b00111..Bus clock filter count is 8
8001 * 0b01000..Bus clock filter count is 9
8002 * 0b01001..Bus clock filter count is 10
8003 * 0b01010..Bus clock filter count is 11
8004 * 0b01011..Bus clock filter count is 12
8005 * 0b01100..Bus clock filter count is 13
8006 * 0b01101..Bus clock filter count is 14
8007 * 0b01110..Bus clock filter count is 15
8008 * 0b01111..Bus clock filter count is 16
8009 * 0b10000..Bus clock filter count is 17
8010 * 0b10001..Bus clock filter count is 18
8011 * 0b10010..Bus clock filter count is 19
8012 * 0b10011..Bus clock filter count is 20
8013 * 0b10100..Bus clock filter count is 21
8014 * 0b10101..Bus clock filter count is 22
8015 * 0b10110..Bus clock filter count is 23
8016 * 0b10111..Bus clock filter count is 24
8017 * 0b11000..Bus clock filter count is 25
8018 * 0b11001..Bus clock filter count is 26
8019 * 0b11010..Bus clock filter count is 27
8020 * 0b11011..Bus clock filter count is 28
8021 * 0b11100..Bus clock filter count is 29
8022 * 0b11101..Bus clock filter count is 30
8023 * 0b11110..Bus clock filter count is 31
8024 * 0b11111..Bus clock filter count is 32
8025 */
8026#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
8027/*! @} */
8028
8029/*! @name SSRS0 - Sticky System Reset Status Register 0 */
8030/*! @{ */
8031#define RCM_SSRS0_SWAKEUP_MASK (0x1U)
8032#define RCM_SSRS0_SWAKEUP_SHIFT (0U)
8033/*! SWAKEUP - Sticky Low Leakage Wakeup Reset
8034 * 0b0..Reset not caused by LLWU module wakeup source
8035 * 0b1..Reset caused by LLWU module wakeup source
8036 */
8037#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
8038#define RCM_SSRS0_SLVD_MASK (0x2U)
8039#define RCM_SSRS0_SLVD_SHIFT (1U)
8040/*! SLVD - Sticky Low-Voltage Detect Reset
8041 * 0b0..Reset not caused by LVD trip or POR
8042 * 0b1..Reset caused by LVD trip or POR
8043 */
8044#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
8045#define RCM_SSRS0_SLOC_MASK (0x4U)
8046#define RCM_SSRS0_SLOC_SHIFT (2U)
8047/*! SLOC - Sticky Loss-of-Clock Reset
8048 * 0b0..Reset not caused by a loss of external clock.
8049 * 0b1..Reset caused by a loss of external clock.
8050 */
8051#define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
8052#define RCM_SSRS0_SWDOG_MASK (0x20U)
8053#define RCM_SSRS0_SWDOG_SHIFT (5U)
8054/*! SWDOG - Sticky Watchdog
8055 * 0b0..Reset not caused by watchdog timeout
8056 * 0b1..Reset caused by watchdog timeout
8057 */
8058#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
8059#define RCM_SSRS0_SPIN_MASK (0x40U)
8060#define RCM_SSRS0_SPIN_SHIFT (6U)
8061/*! SPIN - Sticky External Reset Pin
8062 * 0b0..Reset not caused by external reset pin
8063 * 0b1..Reset caused by external reset pin
8064 */
8065#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
8066#define RCM_SSRS0_SPOR_MASK (0x80U)
8067#define RCM_SSRS0_SPOR_SHIFT (7U)
8068/*! SPOR - Sticky Power-On Reset
8069 * 0b0..Reset not caused by POR
8070 * 0b1..Reset caused by POR
8071 */
8072#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
8073/*! @} */
8074
8075/*! @name SSRS1 - Sticky System Reset Status Register 1 */
8076/*! @{ */
8077#define RCM_SSRS1_SJTAG_MASK (0x1U)
8078#define RCM_SSRS1_SJTAG_SHIFT (0U)
8079/*! SJTAG - Sticky JTAG Generated Reset
8080 * 0b0..Reset not caused by JTAG
8081 * 0b1..Reset caused by JTAG
8082 */
8083#define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
8084#define RCM_SSRS1_SLOCKUP_MASK (0x2U)
8085#define RCM_SSRS1_SLOCKUP_SHIFT (1U)
8086/*! SLOCKUP - Sticky Core Lockup
8087 * 0b0..Reset not caused by core LOCKUP event
8088 * 0b1..Reset caused by core LOCKUP event
8089 */
8090#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
8091#define RCM_SSRS1_SSW_MASK (0x4U)
8092#define RCM_SSRS1_SSW_SHIFT (2U)
8093/*! SSW - Sticky Software
8094 * 0b0..Reset not caused by software setting of SYSRESETREQ bit
8095 * 0b1..Reset caused by software setting of SYSRESETREQ bit
8096 */
8097#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
8098#define RCM_SSRS1_SMDM_AP_MASK (0x8U)
8099#define RCM_SSRS1_SMDM_AP_SHIFT (3U)
8100/*! SMDM_AP - Sticky MDM-AP System Reset Request
8101 * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit
8102 * 0b1..Reset caused by host debugger system setting of the System Reset Request bit
8103 */
8104#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
8105#define RCM_SSRS1_SSACKERR_MASK (0x20U)
8106#define RCM_SSRS1_SSACKERR_SHIFT (5U)
8107/*! SSACKERR - Sticky Stop Mode Acknowledge Error Reset
8108 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
8109 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
8110 */
8111#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
8112/*! @} */
8113
8114
8115/*!
8116 * @}
8117 */ /* end of group RCM_Register_Masks */
8118
8119
8120/* RCM - Peripheral instance base addresses */
8121/** Peripheral RCM base address */
8122#define RCM_BASE (0x4007F000u)
8123/** Peripheral RCM base pointer */
8124#define RCM ((RCM_Type *)RCM_BASE)
8125/** Array initializer of RCM peripheral base addresses */
8126#define RCM_BASE_ADDRS { RCM_BASE }
8127/** Array initializer of RCM peripheral base pointers */
8128#define RCM_BASE_PTRS { RCM }
8129
8130/*!
8131 * @}
8132 */ /* end of group RCM_Peripheral_Access_Layer */
8133
8134
8135/* ----------------------------------------------------------------------------
8136 -- SIM Peripheral Access Layer
8137 ---------------------------------------------------------------------------- */
8138
8139/*!
8140 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
8141 * @{
8142 */
8143
8144/** SIM - Register Layout Typedef */
8145typedef struct {
8146 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
8147 uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
8148 uint8_t RESERVED_0[4092];
8149 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
8150 uint8_t RESERVED_1[4];
8151 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
8152 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
8153 uint8_t RESERVED_2[4];
8154 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
8155 __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
8156 uint8_t RESERVED_3[4];
8157 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
8158 uint8_t RESERVED_4[12];
8159 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
8160 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
8161 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
8162 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
8163 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
8164 uint8_t RESERVED_5[4];
8165 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
8166 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
8167 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
8168 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
8169 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
8170 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
8171} SIM_Type;
8172
8173/* ----------------------------------------------------------------------------
8174 -- SIM Register Masks
8175 ---------------------------------------------------------------------------- */
8176
8177/*!
8178 * @addtogroup SIM_Register_Masks SIM Register Masks
8179 * @{
8180 */
8181
8182/*! @name SOPT1 - System Options Register 1 */
8183/*! @{ */
8184#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
8185#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
8186/*! RAMSIZE - RAM size
8187 * 0b0001..8 KB
8188 * 0b0011..16 KB
8189 * 0b0100..24 KB
8190 * 0b0101..32 KB
8191 * 0b0110..48 KB
8192 * 0b0111..64 KB
8193 * 0b1000..96 KB
8194 * 0b1001..128 KB
8195 * 0b1011..256 KB
8196 */
8197#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
8198#define SIM_SOPT1_OSC32KOUT_MASK (0x30000U)
8199#define SIM_SOPT1_OSC32KOUT_SHIFT (16U)
8200/*! OSC32KOUT - 32K Oscillator Clock Output
8201 * 0b00..ERCLK32K is not output.
8202 * 0b01..ERCLK32K is output on PTE0.
8203 * 0b10..ERCLK32K is output on PTE26.
8204 * 0b11..Reserved.
8205 */
8206#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK)
8207#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
8208#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
8209/*! OSC32KSEL - 32K oscillator clock select
8210 * 0b00..System oscillator (OSC32KCLK)
8211 * 0b01..Reserved
8212 * 0b10..Reserved
8213 * 0b11..LPO 1 kHz
8214 */
8215#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
8216/*! @} */
8217
8218/*! @name SOPT2 - System Options Register 2 */
8219/*! @{ */
8220#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
8221#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
8222/*! CLKOUTSEL - CLKOUT select
8223 * 0b000..Reserved
8224 * 0b001..Reserved
8225 * 0b010..Flash clock
8226 * 0b011..LPO clock (1 kHz)
8227 * 0b100..MCGIRCLK
8228 * 0b101..Reserved
8229 * 0b110..OSCERCLK0
8230 * 0b111..IRC 48 MHz clock
8231 */
8232#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
8233#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
8234#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
8235/*! TRACECLKSEL - Debug trace clock select
8236 * 0b0..MCGOUTCLK
8237 * 0b1..Core/system clock
8238 */
8239#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
8240#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
8241#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
8242/*! PLLFLLSEL - PLL/FLL clock select
8243 * 0b00..MCGFLLCLK clock
8244 * 0b01..Reserved
8245 * 0b10..Reserved
8246 * 0b11..IRC48 MHz clock
8247 */
8248#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
8249/*! @} */
8250
8251/*! @name SOPT4 - System Options Register 4 */
8252/*! @{ */
8253#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
8254#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
8255/*! FTM0FLT0 - FTM0 Fault 0 Select
8256 * 0b0..FTM0_FLT0 pin
8257 * 0b1..CMP0 out
8258 */
8259#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
8260#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
8261#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
8262/*! FTM0FLT1 - FTM0 Fault 1 Select
8263 * 0b0..FTM0_FLT1 pin
8264 * 0b1..CMP1 out
8265 */
8266#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
8267#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
8268#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
8269/*! FTM1FLT0 - FTM1 Fault 0 Select
8270 * 0b0..FTM1_FLT0 pin
8271 * 0b1..CMP0 out
8272 */
8273#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
8274#define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
8275#define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
8276/*! FTM2FLT0 - FTM2 Fault 0 Select
8277 * 0b0..FTM2_FLT0 pin
8278 * 0b1..CMP0 out
8279 */
8280#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
8281#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
8282#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
8283/*! FTM1CH0SRC - FTM1 channel 0 input capture source select
8284 * 0b00..FTM1_CH0 signal
8285 * 0b01..CMP0 output
8286 * 0b10..CMP1 output
8287 * 0b11..Reserved
8288 */
8289#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
8290#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
8291#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
8292/*! FTM2CH0SRC - FTM2 channel 0 input capture source select
8293 * 0b00..FTM2_CH0 signal
8294 * 0b01..CMP0 output
8295 * 0b10..CMP1 output
8296 * 0b11..Reserved
8297 */
8298#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
8299#define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U)
8300#define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U)
8301/*! FTM2CH1SRC - FTM2 channel 1 input capture source select
8302 * 0b0..FTM2_CH1 signal
8303 * 0b1..Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1.
8304 */
8305#define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
8306#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
8307#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
8308/*! FTM0CLKSEL - FlexTimer 0 External Clock Pin Select
8309 * 0b0..FTM_CLK0 pin
8310 * 0b1..FTM_CLK1 pin
8311 */
8312#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
8313#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
8314#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
8315/*! FTM1CLKSEL - FTM1 External Clock Pin Select
8316 * 0b0..FTM_CLK0 pin
8317 * 0b1..FTM_CLK1 pin
8318 */
8319#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
8320#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
8321#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
8322/*! FTM2CLKSEL - FlexTimer 2 External Clock Pin Select
8323 * 0b0..FTM2 external clock driven by FTM_CLK0 pin.
8324 * 0b1..FTM2 external clock driven by FTM_CLK1 pin.
8325 */
8326#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
8327#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
8328#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
8329/*! FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select
8330 * 0b0..HSCMP0 output drives FTM0 hardware trigger 0
8331 * 0b1..FTM1 channel match drives FTM0 hardware trigger 0
8332 */
8333#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
8334#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
8335#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
8336/*! FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select
8337 * 0b0..PDB output trigger 1 drives FTM0 hardware trigger 1
8338 * 0b1..FTM2 channel match drives FTM0 hardware trigger 1
8339 */
8340#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
8341/*! @} */
8342
8343/*! @name SOPT5 - System Options Register 5 */
8344/*! @{ */
8345#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
8346#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
8347/*! UART0TXSRC - UART 0 transmit data source select
8348 * 0b00..UART0_TX pin
8349 * 0b01..UART0_TX pin modulated with FTM1 channel 0 output
8350 * 0b10..UART0_TX pin modulated with FTM2 channel 0 output
8351 * 0b11..Reserved
8352 */
8353#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
8354#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
8355#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
8356/*! UART0RXSRC - UART 0 receive data source select
8357 * 0b00..UART0_RX pin
8358 * 0b01..CMP0
8359 * 0b10..CMP1
8360 * 0b11..Reserved
8361 */
8362#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
8363#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
8364#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
8365/*! UART1TXSRC - UART 1 transmit data source select
8366 * 0b00..UART1_TX pin
8367 * 0b01..UART1_TX pin modulated with FTM1 channel 0 output
8368 * 0b10..UART1_TX pin modulated with FTM2 channel 0 output
8369 * 0b11..Reserved
8370 */
8371#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
8372#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
8373#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
8374/*! UART1RXSRC - UART 1 receive data source select
8375 * 0b00..UART1_RX pin
8376 * 0b01..CMP0
8377 * 0b10..CMP1
8378 * 0b11..Reserved
8379 */
8380#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
8381/*! @} */
8382
8383/*! @name SOPT7 - System Options Register 7 */
8384/*! @{ */
8385#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
8386#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
8387/*! ADC0TRGSEL - ADC0 trigger select
8388 * 0b0000..PDB external trigger pin input (PDB0_EXTRG)
8389 * 0b0001..High speed comparator 0 output
8390 * 0b0010..High speed comparator 1 output
8391 * 0b0011..Reserved
8392 * 0b0100..PIT trigger 0
8393 * 0b0101..PIT trigger 1
8394 * 0b0110..PIT trigger 2
8395 * 0b0111..PIT trigger 3
8396 * 0b1000..FTM0 trigger
8397 * 0b1001..FTM1 trigger
8398 * 0b1010..FTM2 trigger
8399 * 0b1011..Reserved
8400 * 0b1100..Reserved
8401 * 0b1101..Reserved
8402 * 0b1110..Low-power timer (LPTMR) trigger
8403 * 0b1111..Reserved
8404 */
8405#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
8406#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
8407#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
8408/*! ADC0PRETRGSEL - ADC0 pretrigger select
8409 * 0b0..Pre-trigger A
8410 * 0b1..Pre-trigger B
8411 */
8412#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
8413#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
8414#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
8415/*! ADC0ALTTRGEN - ADC0 alternate trigger enable
8416 * 0b0..PDB trigger selected for ADC0.
8417 * 0b1..Alternate trigger selected for ADC0.
8418 */
8419#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
8420/*! @} */
8421
8422/*! @name SOPT8 - System Options Register 8 */
8423/*! @{ */
8424#define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U)
8425#define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U)
8426/*! FTM0SYNCBIT - FTM0 Hardware Trigger 0 Software Synchronization
8427 * 0b0..No effect
8428 * 0b1..Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert.
8429 */
8430#define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
8431#define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U)
8432#define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U)
8433/*! FTM1SYNCBIT - FTM1 Hardware Trigger 0 Software Synchronization
8434 * 0b0..No effect.
8435 * 0b1..Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert.
8436 */
8437#define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
8438#define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U)
8439#define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U)
8440/*! FTM2SYNCBIT - FTM2 Hardware Trigger 0 Software Synchronization
8441 * 0b0..No effect.
8442 * 0b1..Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert.
8443 */
8444#define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
8445#define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U)
8446#define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U)
8447/*! FTM0OCH0SRC - FTM0 channel 0 output source
8448 * 0b0..FTM0_CH0 pin is output of FTM0 channel 0 output
8449 * 0b1..FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output
8450 */
8451#define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
8452#define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U)
8453#define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U)
8454/*! FTM0OCH1SRC - FTM0 channel 1 output source
8455 * 0b0..FTM0_CH1 pin is output of FTM0 channel 1 output
8456 * 0b1..FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output
8457 */
8458#define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
8459#define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U)
8460#define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U)
8461/*! FTM0OCH2SRC - FTM0 channel 2 output source
8462 * 0b0..FTM0_CH2 pin is output of FTM0 channel 2 output
8463 * 0b1..FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output
8464 */
8465#define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
8466#define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U)
8467#define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U)
8468/*! FTM0OCH3SRC - FTM0 channel 3 output source
8469 * 0b0..FTM0_CH3 pin is output of FTM0 channel 3 output
8470 * 0b1..FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output
8471 */
8472#define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
8473#define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U)
8474#define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U)
8475/*! FTM0OCH4SRC - FTM0 channel 4 output source
8476 * 0b0..FTM0_CH4 pin is output of FTM0 channel 4 output
8477 * 0b1..FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output
8478 */
8479#define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
8480#define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U)
8481#define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U)
8482/*! FTM0OCH5SRC - FTM0 channel 5 output source
8483 * 0b0..FTM0_CH5 pin is output of FTM0 channel 5 output
8484 * 0b1..FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output
8485 */
8486#define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
8487/*! @} */
8488
8489/*! @name SDID - System Device Identification Register */
8490/*! @{ */
8491#define SIM_SDID_PINID_MASK (0xFU)
8492#define SIM_SDID_PINID_SHIFT (0U)
8493/*! PINID - Pincount identification
8494 * 0b0000..Reserved
8495 * 0b0001..Reserved
8496 * 0b0010..32-pin
8497 * 0b0011..Reserved
8498 * 0b0100..48-pin
8499 * 0b0101..64-pin
8500 * 0b0110..80-pin
8501 * 0b0111..81-pin or 121-pin
8502 * 0b1000..100-pin
8503 * 0b1001..121-pin
8504 * 0b1010..144-pin
8505 * 0b1011..Custom pinout (WLCSP)
8506 * 0b1100..169-pin
8507 * 0b1101..Reserved
8508 * 0b1110..256-pin
8509 * 0b1111..Reserved
8510 */
8511#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
8512#define SIM_SDID_FAMID_MASK (0x70U)
8513#define SIM_SDID_FAMID_SHIFT (4U)
8514/*! FAMID - Kinetis family identification
8515 * 0b000..K1x Family (without tamper)
8516 * 0b001..K2x Family (without tamper)
8517 * 0b010..K3x Family or K1x/K6x Family (with tamper)
8518 * 0b011..K4x Family or K2x Family (with tamper)
8519 * 0b100..K6x Family (without tamper)
8520 * 0b101..K7x Family
8521 * 0b110..Reserved
8522 * 0b111..Reserved
8523 */
8524#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
8525#define SIM_SDID_DIEID_MASK (0xF80U)
8526#define SIM_SDID_DIEID_SHIFT (7U)
8527#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
8528#define SIM_SDID_REVID_MASK (0xF000U)
8529#define SIM_SDID_REVID_SHIFT (12U)
8530#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
8531#define SIM_SDID_SERIESID_MASK (0xF00000U)
8532#define SIM_SDID_SERIESID_SHIFT (20U)
8533/*! SERIESID - Kinetis Series ID
8534 * 0b0000..Kinetis K series
8535 * 0b0001..Kinetis L series
8536 * 0b0101..Kinetis W series
8537 * 0b0110..Kinetis V series
8538 */
8539#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
8540#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
8541#define SIM_SDID_SUBFAMID_SHIFT (24U)
8542/*! SUBFAMID - Kinetis Sub-Family ID
8543 * 0b0000..Kx0 Subfamily
8544 * 0b0001..Kx1 Subfamily (tamper detect)
8545 * 0b0010..Kx2 Subfamily
8546 * 0b0011..Kx3 Subfamily (tamper detect)
8547 * 0b0100..Kx4 Subfamily
8548 * 0b0101..Kx5 Subfamily (tamper detect)
8549 * 0b0110..Kx6 Subfamily
8550 */
8551#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
8552#define SIM_SDID_FAMILYID_MASK (0xF0000000U)
8553#define SIM_SDID_FAMILYID_SHIFT (28U)
8554/*! FAMILYID - Kinetis Family ID
8555 * 0b0000..K0x Family
8556 * 0b0001..K1x Family
8557 * 0b0010..K2x Family
8558 * 0b0011..K3x Family
8559 * 0b0100..K4x Family
8560 * 0b0110..K6x Family
8561 * 0b0111..K7x Family
8562 */
8563#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
8564/*! @} */
8565
8566/*! @name SCGC4 - System Clock Gating Control Register 4 */
8567/*! @{ */
8568#define SIM_SCGC4_EWM_MASK (0x2U)
8569#define SIM_SCGC4_EWM_SHIFT (1U)
8570/*! EWM - EWM Clock Gate Control
8571 * 0b0..Clock disabled
8572 * 0b1..Clock enabled
8573 */
8574#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
8575#define SIM_SCGC4_I2C0_MASK (0x40U)
8576#define SIM_SCGC4_I2C0_SHIFT (6U)
8577/*! I2C0 - I2C0 Clock Gate Control
8578 * 0b0..Clock disabled
8579 * 0b1..Clock enabled
8580 */
8581#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
8582#define SIM_SCGC4_UART0_MASK (0x400U)
8583#define SIM_SCGC4_UART0_SHIFT (10U)
8584/*! UART0 - UART0 Clock Gate Control
8585 * 0b0..Clock disabled
8586 * 0b1..Clock enabled
8587 */
8588#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
8589#define SIM_SCGC4_UART1_MASK (0x800U)
8590#define SIM_SCGC4_UART1_SHIFT (11U)
8591/*! UART1 - UART1 Clock Gate Control
8592 * 0b0..Clock disabled
8593 * 0b1..Clock enabled
8594 */
8595#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
8596#define SIM_SCGC4_CMP_MASK (0x80000U)
8597#define SIM_SCGC4_CMP_SHIFT (19U)
8598/*! CMP - Comparator Clock Gate Control
8599 * 0b0..Clock disabled
8600 * 0b1..Clock enabled
8601 */
8602#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
8603#define SIM_SCGC4_VREF_MASK (0x100000U)
8604#define SIM_SCGC4_VREF_SHIFT (20U)
8605/*! VREF - VREF Clock Gate Control
8606 * 0b0..Clock disabled
8607 * 0b1..Clock enabled
8608 */
8609#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
8610/*! @} */
8611
8612/*! @name SCGC5 - System Clock Gating Control Register 5 */
8613/*! @{ */
8614#define SIM_SCGC5_LPTMR_MASK (0x1U)
8615#define SIM_SCGC5_LPTMR_SHIFT (0U)
8616/*! LPTMR - Low Power Timer Access Control
8617 * 0b0..Access disabled
8618 * 0b1..Access enabled
8619 */
8620#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
8621#define SIM_SCGC5_PORTA_MASK (0x200U)
8622#define SIM_SCGC5_PORTA_SHIFT (9U)
8623/*! PORTA - Port A Clock Gate Control
8624 * 0b0..Clock disabled
8625 * 0b1..Clock enabled
8626 */
8627#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
8628#define SIM_SCGC5_PORTB_MASK (0x400U)
8629#define SIM_SCGC5_PORTB_SHIFT (10U)
8630/*! PORTB - Port B Clock Gate Control
8631 * 0b0..Clock disabled
8632 * 0b1..Clock enabled
8633 */
8634#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
8635#define SIM_SCGC5_PORTC_MASK (0x800U)
8636#define SIM_SCGC5_PORTC_SHIFT (11U)
8637/*! PORTC - Port C Clock Gate Control
8638 * 0b0..Clock disabled
8639 * 0b1..Clock enabled
8640 */
8641#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
8642#define SIM_SCGC5_PORTD_MASK (0x1000U)
8643#define SIM_SCGC5_PORTD_SHIFT (12U)
8644/*! PORTD - Port D Clock Gate Control
8645 * 0b0..Clock disabled
8646 * 0b1..Clock enabled
8647 */
8648#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
8649#define SIM_SCGC5_PORTE_MASK (0x2000U)
8650#define SIM_SCGC5_PORTE_SHIFT (13U)
8651/*! PORTE - Port E Clock Gate Control
8652 * 0b0..Clock disabled
8653 * 0b1..Clock enabled
8654 */
8655#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
8656/*! @} */
8657
8658/*! @name SCGC6 - System Clock Gating Control Register 6 */
8659/*! @{ */
8660#define SIM_SCGC6_FTF_MASK (0x1U)
8661#define SIM_SCGC6_FTF_SHIFT (0U)
8662/*! FTF - Flash Memory Clock Gate Control
8663 * 0b0..Clock disabled
8664 * 0b1..Clock enabled
8665 */
8666#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
8667#define SIM_SCGC6_DMAMUX_MASK (0x2U)
8668#define SIM_SCGC6_DMAMUX_SHIFT (1U)
8669/*! DMAMUX - DMA Mux Clock Gate Control
8670 * 0b0..Clock disabled
8671 * 0b1..Clock enabled
8672 */
8673#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
8674#define SIM_SCGC6_SPI0_MASK (0x1000U)
8675#define SIM_SCGC6_SPI0_SHIFT (12U)
8676/*! SPI0 - SPI0 Clock Gate Control
8677 * 0b0..Clock disabled
8678 * 0b1..Clock enabled
8679 */
8680#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
8681#define SIM_SCGC6_CRC_MASK (0x40000U)
8682#define SIM_SCGC6_CRC_SHIFT (18U)
8683/*! CRC - CRC Clock Gate Control
8684 * 0b0..Clock disabled
8685 * 0b1..Clock enabled
8686 */
8687#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
8688#define SIM_SCGC6_PDB_MASK (0x400000U)
8689#define SIM_SCGC6_PDB_SHIFT (22U)
8690/*! PDB - PDB Clock Gate Control
8691 * 0b0..Clock disabled
8692 * 0b1..Clock enabled
8693 */
8694#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
8695#define SIM_SCGC6_PIT_MASK (0x800000U)
8696#define SIM_SCGC6_PIT_SHIFT (23U)
8697/*! PIT - PIT Clock Gate Control
8698 * 0b0..Clock disabled
8699 * 0b1..Clock enabled
8700 */
8701#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
8702#define SIM_SCGC6_FTM0_MASK (0x1000000U)
8703#define SIM_SCGC6_FTM0_SHIFT (24U)
8704/*! FTM0 - FTM0 Clock Gate Control
8705 * 0b0..Clock disabled
8706 * 0b1..Clock enabled
8707 */
8708#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
8709#define SIM_SCGC6_FTM1_MASK (0x2000000U)
8710#define SIM_SCGC6_FTM1_SHIFT (25U)
8711/*! FTM1 - FTM1 Clock Gate Control
8712 * 0b0..Clock disabled