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1/*
2** ###################################################################
3** Version: rev. 0.9, 2015-06-08
4** Build: b200921
5**
6** Abstract:
7** Chip specific module features.
8**
9** Copyright 2016 Freescale Semiconductor, Inc.
10** Copyright 2016-2020 NXP
11** All rights reserved.
12**
13** SPDX-License-Identifier: BSD-3-Clause
14**
15** http: www.nxp.com
16** mail: [email protected]
17**
18** Revisions:
19** - rev. 0.1 (2014-02-24)
20** Initial version
21** - rev. 0.2 (2014-07-15)
22** Module access macro module_BASES replaced by module_BASE_PTRS.
23** Update of system and startup files.
24** - rev. 0.3 (2014-08-28)
25** Update of system files - default clock configuration changed.
26** Update of startup files - possibility to override DefaultISR added.
27** - rev. 0.4 (2014-10-14)
28** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
29** - rev. 0.5 (2015-01-21)
30** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
31** - rev. 0.6 (2015-02-19)
32** Renamed interrupt vector LLW to LLWU.
33** - rev. 0.7 (2015-05-19)
34** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
35** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
36** Added features for PDB and PORT.
37** - rev. 0.8 (2015-05-25)
38** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
39** - rev. 0.9 (2015-06-08)
40** FTM features BUS_CLOCK and FAST_CLOCK removed.
41**
42** ###################################################################
43*/
44
45#ifndef _MK02F12810_FEATURES_H_
46#define _MK02F12810_FEATURES_H_
47
48/* SOC module features */
49
50/* @brief ADC16 availability on the SoC. */
51#define FSL_FEATURE_SOC_ADC16_COUNT (1)
52/* @brief CMP availability on the SoC. */
53#define FSL_FEATURE_SOC_CMP_COUNT (2)
54/* @brief CRC availability on the SoC. */
55#define FSL_FEATURE_SOC_CRC_COUNT (1)
56/* @brief DAC availability on the SoC. */
57#define FSL_FEATURE_SOC_DAC_COUNT (1)
58/* @brief EDMA availability on the SoC. */
59#define FSL_FEATURE_SOC_EDMA_COUNT (1)
60/* @brief DMAMUX availability on the SoC. */
61#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
62/* @brief DSPI availability on the SoC. */
63#define FSL_FEATURE_SOC_DSPI_COUNT (1)
64/* @brief EWM availability on the SoC. */
65#define FSL_FEATURE_SOC_EWM_COUNT (1)
66/* @brief FMC availability on the SoC. */
67#define FSL_FEATURE_SOC_FMC_COUNT (1)
68/* @brief FTFA availability on the SoC. */
69#define FSL_FEATURE_SOC_FTFA_COUNT (1)
70/* @brief FTM availability on the SoC. */
71#define FSL_FEATURE_SOC_FTM_COUNT (3)
72/* @brief GPIO availability on the SoC. */
73#define FSL_FEATURE_SOC_GPIO_COUNT (5)
74/* @brief I2C availability on the SoC. */
75#define FSL_FEATURE_SOC_I2C_COUNT (1)
76/* @brief LLWU availability on the SoC. */
77#define FSL_FEATURE_SOC_LLWU_COUNT (1)
78/* @brief LPTMR availability on the SoC. */
79#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
80/* @brief MCG availability on the SoC. */
81#define FSL_FEATURE_SOC_MCG_COUNT (1)
82/* @brief MCM availability on the SoC. */
83#define FSL_FEATURE_SOC_MCM_COUNT (1)
84/* @brief OSC availability on the SoC. */
85#define FSL_FEATURE_SOC_OSC_COUNT (1)
86/* @brief PDB availability on the SoC. */
87#define FSL_FEATURE_SOC_PDB_COUNT (1)
88/* @brief PIT availability on the SoC. */
89#define FSL_FEATURE_SOC_PIT_COUNT (1)
90/* @brief PMC availability on the SoC. */
91#define FSL_FEATURE_SOC_PMC_COUNT (1)
92/* @brief PORT availability on the SoC. */
93#define FSL_FEATURE_SOC_PORT_COUNT (5)
94/* @brief RCM availability on the SoC. */
95#define FSL_FEATURE_SOC_RCM_COUNT (1)
96/* @brief SIM availability on the SoC. */
97#define FSL_FEATURE_SOC_SIM_COUNT (1)
98/* @brief SMC availability on the SoC. */
99#define FSL_FEATURE_SOC_SMC_COUNT (1)
100/* @brief UART availability on the SoC. */
101#define FSL_FEATURE_SOC_UART_COUNT (2)
102/* @brief VREF availability on the SoC. */
103#define FSL_FEATURE_SOC_VREF_COUNT (1)
104/* @brief WDOG availability on the SoC. */
105#define FSL_FEATURE_SOC_WDOG_COUNT (1)
106
107/* ADC16 module features */
108
109/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
110#define FSL_FEATURE_ADC16_HAS_PGA (0)
111/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
112#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
113/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
114#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
115/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
116#define FSL_FEATURE_ADC16_HAS_DMA (1)
117/* @brief Has differential mode (bitfield SC1x[DIFF]). */
118#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
119/* @brief Has FIFO (bit SC4[AFDEP]). */
120#define FSL_FEATURE_ADC16_HAS_FIFO (0)
121/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
122#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
123/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
124#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
125/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
126#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
127/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
128#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
129/* @brief Has HW averaging (bit SC3[AVGE]). */
130#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
131/* @brief Has offset correction (register OFS). */
132#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
133/* @brief Maximum ADC resolution. */
134#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
135/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
136#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
137
138/* CMP module features */
139
140/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
141#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
142/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
143#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
144/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
145#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
146/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
147#define FSL_FEATURE_CMP_HAS_DMA (1)
148/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
149#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0)
150/* @brief Has DAC Test function in CMP (register DACTEST). */
151#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
152
153/* CRC module features */
154
155/* @brief Has data register with name CRC */
156#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
157
158/* DAC module features */
159
160/* @brief Define the size of hardware buffer */
161#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
162/* @brief Define whether the buffer supports watermark event detection or not. */
163#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
164/* @brief Define whether the buffer supports watermark selection detection or not. */
165#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
166/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
167#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
168/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
169#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
170/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
171#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
172/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
173#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
174/* @brief Define whether FIFO buffer mode is available or not. */
175#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (1)
176/* @brief Define whether swing buffer mode is available or not.. */
177#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
178
179/* EDMA module features */
180
181/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
182#define FSL_FEATURE_EDMA_MODULE_CHANNEL (4)
183/* @brief Total number of DMA channels on all modules. */
184#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (4)
185/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
186#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
187/* @brief Has DMA_Error interrupt vector. */
188#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
189/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
190#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4)
191/* @brief Channel IRQ entry shared offset. */
192#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (0)
193/* @brief If 8 bytes transfer supported. */
194#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0)
195/* @brief If 16 bytes transfer supported. */
196#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
197
198/* DMAMUX module features */
199
200/* @brief Number of DMA channels (related to number of register CHCFGn). */
201#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4)
202/* @brief Total number of DMA channels on all modules. */
203#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (4)
204/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
205#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
206/* @brief Register CHCFGn width. */
207#define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8)
208
209/* EWM module features */
210
211/* @brief Has clock select (register CLKCTRL). */
212#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0)
213/* @brief Has clock prescaler (register CLKPRESCALER). */
214#define FSL_FEATURE_EWM_HAS_PRESCALER (1)
215
216/* FLASH module features */
217
218#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN128VLH10)
219 /* @brief Is of type FTFA. */
220 #define FSL_FEATURE_FLASH_IS_FTFA (1)
221 /* @brief Is of type FTFE. */
222 #define FSL_FEATURE_FLASH_IS_FTFE (0)
223 /* @brief Is of type FTFL. */
224 #define FSL_FEATURE_FLASH_IS_FTFL (0)
225 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
226 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
227 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
228 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
229 /* @brief Has EEPROM region protection (register FEPROT). */
230 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
231 /* @brief Has data flash region protection (register FDPROT). */
232 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
233 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
234 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
235 /* @brief Has flash cache control in FMC module. */
236 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
237 /* @brief Has flash cache control in MCM module. */
238 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
239 /* @brief Has flash cache control in MSCM module. */
240 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
241 /* @brief Has prefetch speculation control in flash, such as kv5x. */
242 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
243 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
244 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
245 /* @brief P-Flash start address. */
246 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
247 /* @brief P-Flash block count. */
248 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
249 /* @brief P-Flash block size. */
250 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072)
251 /* @brief P-Flash sector size. */
252 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
253 /* @brief P-Flash write unit size. */
254 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
255 /* @brief P-Flash data path width. */
256 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
257 /* @brief P-Flash block swap feature. */
258 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
259 /* @brief P-Flash protection region count. */
260 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
261 /* @brief Has FlexNVM memory. */
262 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
263 /* @brief Has FlexNVM alias. */
264 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0)
265 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
266 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
267 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */
268 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000)
269 /* @brief FlexNVM block count. */
270 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
271 /* @brief FlexNVM block size. */
272 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
273 /* @brief FlexNVM sector size. */
274 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
275 /* @brief FlexNVM write unit size. */
276 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
277 /* @brief FlexNVM data path width. */
278 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
279 /* @brief Has FlexRAM memory. */
280 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
281 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
282 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
283 /* @brief FlexRAM size. */
284 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
285 /* @brief Has 0x00 Read 1s Block command. */
286 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
287 /* @brief Has 0x01 Read 1s Section command. */
288 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
289 /* @brief Has 0x02 Program Check command. */
290 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
291 /* @brief Has 0x03 Read Resource command. */
292 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
293 /* @brief Has 0x06 Program Longword command. */
294 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
295 /* @brief Has 0x07 Program Phrase command. */
296 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
297 /* @brief Has 0x08 Erase Flash Block command. */
298 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
299 /* @brief Has 0x09 Erase Flash Sector command. */
300 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
301 /* @brief Has 0x0B Program Section command. */
302 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
303 /* @brief Has 0x40 Read 1s All Blocks command. */
304 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
305 /* @brief Has 0x41 Read Once command. */
306 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
307 /* @brief Has 0x43 Program Once command. */
308 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
309 /* @brief Has 0x44 Erase All Blocks command. */
310 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
311 /* @brief Has 0x45 Verify Backdoor Access Key command. */
312 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
313 /* @brief Has 0x46 Swap Control command. */
314 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
315 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
316 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
317 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
318 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
319 /* @brief Has 0x4B Erase All Execute-only Segments command. */
320 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
321 /* @brief Has 0x80 Program Partition command. */
322 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
323 /* @brief Has 0x81 Set FlexRAM Function command. */
324 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
325 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
326 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
327 /* @brief P-Flash Erase sector command address alignment. */
328 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
329 /* @brief P-Flash Rrogram/Verify section command address alignment. */
330 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
331 /* @brief P-Flash Read resource command address alignment. */
332 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
333 /* @brief P-Flash Program check command address alignment. */
334 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
335 /* @brief P-Flash Program check command address alignment. */
336 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
337 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
338 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
339 /* @brief FlexNVM Erase sector command address alignment. */
340 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
341 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
342 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
343 /* @brief FlexNVM Read resource command address alignment. */
344 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
345 /* @brief FlexNVM Program check command address alignment. */
346 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
347 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
348 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU)
349 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
350 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU)
351 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
352 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU)
353 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
354 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU)
355 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
356 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU)
357 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
358 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU)
359 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
360 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU)
361 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
362 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU)
363 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
364 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU)
365 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
366 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU)
367 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
368 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU)
369 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
370 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU)
371 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
372 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU)
373 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
374 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU)
375 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
376 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU)
377 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
378 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU)
379 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
380 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
381 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
382 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
383 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
384 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
385 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
386 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
387 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
388 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
389 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
390 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
391 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
392 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
393 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
394 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
395 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
396 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
397 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
398 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
399 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
400 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
401 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
402 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
403 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
404 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
405 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
406 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
407 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
408 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
409 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
410 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
411#elif defined(CPU_MK02FN64VFM10) || defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN64VLH10)
412 /* @brief Is of type FTFA. */
413 #define FSL_FEATURE_FLASH_IS_FTFA (1)
414 /* @brief Is of type FTFE. */
415 #define FSL_FEATURE_FLASH_IS_FTFE (0)
416 /* @brief Is of type FTFL. */
417 #define FSL_FEATURE_FLASH_IS_FTFL (0)
418 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
419 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0)
420 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
421 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0)
422 /* @brief Has EEPROM region protection (register FEPROT). */
423 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
424 /* @brief Has data flash region protection (register FDPROT). */
425 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
426 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
427 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
428 /* @brief Has flash cache control in FMC module. */
429 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
430 /* @brief Has flash cache control in MCM module. */
431 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
432 /* @brief Has flash cache control in MSCM module. */
433 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
434 /* @brief Has prefetch speculation control in flash, such as kv5x. */
435 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
436 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
437 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
438 /* @brief P-Flash start address. */
439 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
440 /* @brief P-Flash block count. */
441 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1)
442 /* @brief P-Flash block size. */
443 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536)
444 /* @brief P-Flash sector size. */
445 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048)
446 /* @brief P-Flash write unit size. */
447 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4)
448 /* @brief P-Flash data path width. */
449 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8)
450 /* @brief P-Flash block swap feature. */
451 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0)
452 /* @brief P-Flash protection region count. */
453 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
454 /* @brief Has FlexNVM memory. */
455 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
456 /* @brief Has FlexNVM alias. */
457 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0)
458 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
459 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
460 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */
461 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000)
462 /* @brief FlexNVM block count. */
463 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
464 /* @brief FlexNVM block size. */
465 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
466 /* @brief FlexNVM sector size. */
467 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
468 /* @brief FlexNVM write unit size. */
469 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
470 /* @brief FlexNVM data path width. */
471 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
472 /* @brief Has FlexRAM memory. */
473 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0)
474 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
475 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000)
476 /* @brief FlexRAM size. */
477 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0)
478 /* @brief Has 0x00 Read 1s Block command. */
479 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0)
480 /* @brief Has 0x01 Read 1s Section command. */
481 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
482 /* @brief Has 0x02 Program Check command. */
483 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
484 /* @brief Has 0x03 Read Resource command. */
485 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
486 /* @brief Has 0x06 Program Longword command. */
487 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1)
488 /* @brief Has 0x07 Program Phrase command. */
489 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0)
490 /* @brief Has 0x08 Erase Flash Block command. */
491 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0)
492 /* @brief Has 0x09 Erase Flash Sector command. */
493 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
494 /* @brief Has 0x0B Program Section command. */
495 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0)
496 /* @brief Has 0x40 Read 1s All Blocks command. */
497 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
498 /* @brief Has 0x41 Read Once command. */
499 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
500 /* @brief Has 0x43 Program Once command. */
501 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
502 /* @brief Has 0x44 Erase All Blocks command. */
503 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
504 /* @brief Has 0x45 Verify Backdoor Access Key command. */
505 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
506 /* @brief Has 0x46 Swap Control command. */
507 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0)
508 /* @brief Has 0x49 Erase All Blocks Unsecure command. */
509 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
510 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */
511 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
512 /* @brief Has 0x4B Erase All Execute-only Segments command. */
513 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
514 /* @brief Has 0x80 Program Partition command. */
515 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
516 /* @brief Has 0x81 Set FlexRAM Function command. */
517 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
518 /* @brief P-Flash Erase/Read 1st all block command address alignment. */
519 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4)
520 /* @brief P-Flash Erase sector command address alignment. */
521 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8)
522 /* @brief P-Flash Rrogram/Verify section command address alignment. */
523 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8)
524 /* @brief P-Flash Read resource command address alignment. */
525 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4)
526 /* @brief P-Flash Program check command address alignment. */
527 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
528 /* @brief P-Flash Program check command address alignment. */
529 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0)
530 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */
531 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
532 /* @brief FlexNVM Erase sector command address alignment. */
533 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
534 /* @brief FlexNVM Rrogram/Verify section command address alignment. */
535 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
536 /* @brief FlexNVM Read resource command address alignment. */
537 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
538 /* @brief FlexNVM Program check command address alignment. */
539 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
540 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
541 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU)
542 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
543 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU)
544 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
545 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU)
546 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
547 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU)
548 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
549 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU)
550 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
551 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU)
552 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
553 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU)
554 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
555 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU)
556 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
557 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU)
558 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
559 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU)
560 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
561 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU)
562 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
563 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU)
564 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
565 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU)
566 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
567 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU)
568 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
569 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU)
570 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
571 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU)
572 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
573 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
574 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
575 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
576 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
577 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF)
578 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
579 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF)
580 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
581 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF)
582 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
583 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF)
584 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
585 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF)
586 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
587 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF)
588 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
589 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF)
590 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
591 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF)
592 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
593 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
594 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
595 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
596 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
597 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
598 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
599 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
600 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
601 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
602 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
603 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF)
604#endif /* defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN128VLH10) */
605
606/* FTM module features */
607
608/* @brief Number of channels. */
609#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
610 (((x) == FTM0) ? (6) : \
611 (((x) == FTM1) ? (2) : \
612 (((x) == FTM2) ? (2) : (-1))))
613/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
614#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1)
615/* @brief Has extended deadtime value. */
616#define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0)
617/* @brief Enable pwm output for the module. */
618#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0)
619/* @brief Has half-cycle reload for the module. */
620#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0)
621/* @brief Has reload interrupt. */
622#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0)
623/* @brief Has reload initialization trigger. */
624#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0)
625/* @brief Has DMA support, bitfield CnSC[DMA]. */
626#define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1)
627/* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */
628#define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0)
629/* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */
630#define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0)
631/* @brief Has no QDCTRL. */
632#define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0)
633/* @brief If instance has only TPM function. */
634#define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0)
635
636/* GPIO module features */
637
638/* @brief Has GPIO attribute checker register (GACR). */
639#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
640
641/* I2C module features */
642
643/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
644#define FSL_FEATURE_I2C_HAS_SMBUS (1)
645/* @brief Maximum supported baud rate in kilobit per second. */
646#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
647/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
648#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
649/* @brief Has DMA support (register bit C1[DMAEN]). */
650#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
651/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
652#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
653/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
654#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
655/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
656#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
657/* @brief Maximum width of the glitch filter in number of bus clocks. */
658#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
659/* @brief Has control of the drive capability of the I2C pins. */
660#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
661/* @brief Has double buffering support (register S2). */
662#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
663/* @brief Has double buffer enable. */
664#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
665
666/* LLWU module features */
667
668#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10)
669 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
670 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
671 /* @brief Has pins 8-15 connected to LLWU device. */
672 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
673 /* @brief Maximum number of internal modules connected to LLWU device. */
674 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3)
675 /* @brief Number of digital filters. */
676 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
677 /* @brief Has MF register. */
678 #define FSL_FEATURE_LLWU_HAS_MF (0)
679 /* @brief Has PF register. */
680 #define FSL_FEATURE_LLWU_HAS_PF (0)
681 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
682 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
683 /* @brief Has no internal module wakeup flag register. */
684 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
685 /* @brief Has external pin 0 connected to LLWU device. */
686 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0)
687 /* @brief Index of port of external pin. */
688 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0)
689 /* @brief Number of external pin port on specified port. */
690 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0)
691 /* @brief Has external pin 1 connected to LLWU device. */
692 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0)
693 /* @brief Index of port of external pin. */
694 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0)
695 /* @brief Number of external pin port on specified port. */
696 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0)
697 /* @brief Has external pin 2 connected to LLWU device. */
698 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0)
699 /* @brief Index of port of external pin. */
700 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0)
701 /* @brief Number of external pin port on specified port. */
702 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0)
703 /* @brief Has external pin 3 connected to LLWU device. */
704 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
705 /* @brief Index of port of external pin. */
706 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
707 /* @brief Number of external pin port on specified port. */
708 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
709 /* @brief Has external pin 4 connected to LLWU device. */
710 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0)
711 /* @brief Index of port of external pin. */
712 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0)
713 /* @brief Number of external pin port on specified port. */
714 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0)
715 /* @brief Has external pin 5 connected to LLWU device. */
716 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
717 /* @brief Index of port of external pin. */
718 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
719 /* @brief Number of external pin port on specified port. */
720 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
721 /* @brief Has external pin 6 connected to LLWU device. */
722 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
723 /* @brief Index of port of external pin. */
724 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
725 /* @brief Number of external pin port on specified port. */
726 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
727 /* @brief Has external pin 7 connected to LLWU device. */
728 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
729 /* @brief Index of port of external pin. */
730 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
731 /* @brief Number of external pin port on specified port. */
732 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
733 /* @brief Has external pin 8 connected to LLWU device. */
734 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
735 /* @brief Index of port of external pin. */
736 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
737 /* @brief Number of external pin port on specified port. */
738 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
739 /* @brief Has external pin 9 connected to LLWU device. */
740 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
741 /* @brief Index of port of external pin. */
742 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
743 /* @brief Number of external pin port on specified port. */
744 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
745 /* @brief Has external pin 10 connected to LLWU device. */
746 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
747 /* @brief Index of port of external pin. */
748 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
749 /* @brief Number of external pin port on specified port. */
750 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
751 /* @brief Has external pin 11 connected to LLWU device. */
752 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0)
753 /* @brief Index of port of external pin. */
754 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0)
755 /* @brief Number of external pin port on specified port. */
756 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0)
757 /* @brief Has external pin 12 connected to LLWU device. */
758 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0)
759 /* @brief Index of port of external pin. */
760 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0)
761 /* @brief Number of external pin port on specified port. */
762 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
763 /* @brief Has external pin 13 connected to LLWU device. */
764 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0)
765 /* @brief Index of port of external pin. */
766 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0)
767 /* @brief Number of external pin port on specified port. */
768 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0)
769 /* @brief Has external pin 14 connected to LLWU device. */
770 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
771 /* @brief Index of port of external pin. */
772 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
773 /* @brief Number of external pin port on specified port. */
774 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
775 /* @brief Has external pin 15 connected to LLWU device. */
776 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
777 /* @brief Index of port of external pin. */
778 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
779 /* @brief Number of external pin port on specified port. */
780 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
781 /* @brief Has external pin 16 connected to LLWU device. */
782 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
783 /* @brief Index of port of external pin. */
784 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
785 /* @brief Number of external pin port on specified port. */
786 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
787 /* @brief Has external pin 17 connected to LLWU device. */
788 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
789 /* @brief Index of port of external pin. */
790 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
791 /* @brief Number of external pin port on specified port. */
792 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
793 /* @brief Has external pin 18 connected to LLWU device. */
794 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
795 /* @brief Index of port of external pin. */
796 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
797 /* @brief Number of external pin port on specified port. */
798 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
799 /* @brief Has external pin 19 connected to LLWU device. */
800 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
801 /* @brief Index of port of external pin. */
802 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
803 /* @brief Number of external pin port on specified port. */
804 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
805 /* @brief Has external pin 20 connected to LLWU device. */
806 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
807 /* @brief Index of port of external pin. */
808 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
809 /* @brief Number of external pin port on specified port. */
810 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
811 /* @brief Has external pin 21 connected to LLWU device. */
812 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
813 /* @brief Index of port of external pin. */
814 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
815 /* @brief Number of external pin port on specified port. */
816 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
817 /* @brief Has external pin 22 connected to LLWU device. */
818 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
819 /* @brief Index of port of external pin. */
820 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
821 /* @brief Number of external pin port on specified port. */
822 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
823 /* @brief Has external pin 23 connected to LLWU device. */
824 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
825 /* @brief Index of port of external pin. */
826 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
827 /* @brief Number of external pin port on specified port. */
828 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
829 /* @brief Has external pin 24 connected to LLWU device. */
830 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
831 /* @brief Index of port of external pin. */
832 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
833 /* @brief Number of external pin port on specified port. */
834 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
835 /* @brief Has external pin 25 connected to LLWU device. */
836 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
837 /* @brief Index of port of external pin. */
838 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
839 /* @brief Number of external pin port on specified port. */
840 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
841 /* @brief Has external pin 26 connected to LLWU device. */
842 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
843 /* @brief Index of port of external pin. */
844 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
845 /* @brief Number of external pin port on specified port. */
846 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
847 /* @brief Has external pin 27 connected to LLWU device. */
848 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
849 /* @brief Index of port of external pin. */
850 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
851 /* @brief Number of external pin port on specified port. */
852 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
853 /* @brief Has external pin 28 connected to LLWU device. */
854 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
855 /* @brief Index of port of external pin. */
856 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
857 /* @brief Number of external pin port on specified port. */
858 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
859 /* @brief Has external pin 29 connected to LLWU device. */
860 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
861 /* @brief Index of port of external pin. */
862 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
863 /* @brief Number of external pin port on specified port. */
864 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
865 /* @brief Has external pin 30 connected to LLWU device. */
866 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
867 /* @brief Index of port of external pin. */
868 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
869 /* @brief Number of external pin port on specified port. */
870 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
871 /* @brief Has external pin 31 connected to LLWU device. */
872 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
873 /* @brief Index of port of external pin. */
874 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
875 /* @brief Number of external pin port on specified port. */
876 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
877 /* @brief Has internal module 0 connected to LLWU device. */
878 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
879 /* @brief Has internal module 1 connected to LLWU device. */
880 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
881 /* @brief Has internal module 2 connected to LLWU device. */
882 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
883 /* @brief Has internal module 3 connected to LLWU device. */
884 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
885 /* @brief Has internal module 4 connected to LLWU device. */
886 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
887 /* @brief Has internal module 5 connected to LLWU device. */
888 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0)
889 /* @brief Has internal module 6 connected to LLWU device. */
890 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
891 /* @brief Has internal module 7 connected to LLWU device. */
892 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0)
893 /* @brief Has Version ID Register (LLWU_VERID). */
894 #define FSL_FEATURE_LLWU_HAS_VERID (0)
895 /* @brief Has Parameter Register (LLWU_PARAM). */
896 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
897 /* @brief Width of registers of the LLWU. */
898 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
899 /* @brief Has DMA Enable register (LLWU_DE). */
900 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
901#elif defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN64VLF10)
902 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
903 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
904 /* @brief Has pins 8-15 connected to LLWU device. */
905 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
906 /* @brief Maximum number of internal modules connected to LLWU device. */
907 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3)
908 /* @brief Number of digital filters. */
909 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
910 /* @brief Has MF register. */
911 #define FSL_FEATURE_LLWU_HAS_MF (0)
912 /* @brief Has PF register. */
913 #define FSL_FEATURE_LLWU_HAS_PF (0)
914 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
915 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
916 /* @brief Has no internal module wakeup flag register. */
917 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
918 /* @brief Has external pin 0 connected to LLWU device. */
919 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0)
920 /* @brief Index of port of external pin. */
921 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0)
922 /* @brief Number of external pin port on specified port. */
923 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0)
924 /* @brief Has external pin 1 connected to LLWU device. */
925 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0)
926 /* @brief Index of port of external pin. */
927 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0)
928 /* @brief Number of external pin port on specified port. */
929 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0)
930 /* @brief Has external pin 2 connected to LLWU device. */
931 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0)
932 /* @brief Index of port of external pin. */
933 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0)
934 /* @brief Number of external pin port on specified port. */
935 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0)
936 /* @brief Has external pin 3 connected to LLWU device. */
937 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
938 /* @brief Index of port of external pin. */
939 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
940 /* @brief Number of external pin port on specified port. */
941 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
942 /* @brief Has external pin 4 connected to LLWU device. */
943 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0)
944 /* @brief Index of port of external pin. */
945 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0)
946 /* @brief Number of external pin port on specified port. */
947 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0)
948 /* @brief Has external pin 5 connected to LLWU device. */
949 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
950 /* @brief Index of port of external pin. */
951 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
952 /* @brief Number of external pin port on specified port. */
953 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
954 /* @brief Has external pin 6 connected to LLWU device. */
955 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
956 /* @brief Index of port of external pin. */
957 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
958 /* @brief Number of external pin port on specified port. */
959 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
960 /* @brief Has external pin 7 connected to LLWU device. */
961 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
962 /* @brief Index of port of external pin. */
963 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
964 /* @brief Number of external pin port on specified port. */
965 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
966 /* @brief Has external pin 8 connected to LLWU device. */
967 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
968 /* @brief Index of port of external pin. */
969 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
970 /* @brief Number of external pin port on specified port. */
971 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
972 /* @brief Has external pin 9 connected to LLWU device. */
973 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
974 /* @brief Index of port of external pin. */
975 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
976 /* @brief Number of external pin port on specified port. */
977 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
978 /* @brief Has external pin 10 connected to LLWU device. */
979 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
980 /* @brief Index of port of external pin. */
981 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
982 /* @brief Number of external pin port on specified port. */
983 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
984 /* @brief Has external pin 11 connected to LLWU device. */
985 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0)
986 /* @brief Index of port of external pin. */
987 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0)
988 /* @brief Number of external pin port on specified port. */
989 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0)
990 /* @brief Has external pin 12 connected to LLWU device. */
991 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
992 /* @brief Index of port of external pin. */
993 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
994 /* @brief Number of external pin port on specified port. */
995 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
996 /* @brief Has external pin 13 connected to LLWU device. */
997 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
998 /* @brief Index of port of external pin. */
999 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
1000 /* @brief Number of external pin port on specified port. */
1001 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
1002 /* @brief Has external pin 14 connected to LLWU device. */
1003 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
1004 /* @brief Index of port of external pin. */
1005 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
1006 /* @brief Number of external pin port on specified port. */
1007 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
1008 /* @brief Has external pin 15 connected to LLWU device. */
1009 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
1010 /* @brief Index of port of external pin. */
1011 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
1012 /* @brief Number of external pin port on specified port. */
1013 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
1014 /* @brief Has external pin 16 connected to LLWU device. */
1015 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
1016 /* @brief Index of port of external pin. */
1017 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
1018 /* @brief Number of external pin port on specified port. */
1019 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
1020 /* @brief Has external pin 17 connected to LLWU device. */
1021 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
1022 /* @brief Index of port of external pin. */
1023 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
1024 /* @brief Number of external pin port on specified port. */
1025 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
1026 /* @brief Has external pin 18 connected to LLWU device. */
1027 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
1028 /* @brief Index of port of external pin. */
1029 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
1030 /* @brief Number of external pin port on specified port. */
1031 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
1032 /* @brief Has external pin 19 connected to LLWU device. */
1033 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
1034 /* @brief Index of port of external pin. */
1035 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
1036 /* @brief Number of external pin port on specified port. */
1037 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
1038 /* @brief Has external pin 20 connected to LLWU device. */
1039 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
1040 /* @brief Index of port of external pin. */
1041 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
1042 /* @brief Number of external pin port on specified port. */
1043 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
1044 /* @brief Has external pin 21 connected to LLWU device. */
1045 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
1046 /* @brief Index of port of external pin. */
1047 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
1048 /* @brief Number of external pin port on specified port. */
1049 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
1050 /* @brief Has external pin 22 connected to LLWU device. */
1051 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
1052 /* @brief Index of port of external pin. */
1053 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
1054 /* @brief Number of external pin port on specified port. */
1055 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
1056 /* @brief Has external pin 23 connected to LLWU device. */
1057 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
1058 /* @brief Index of port of external pin. */
1059 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
1060 /* @brief Number of external pin port on specified port. */
1061 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
1062 /* @brief Has external pin 24 connected to LLWU device. */
1063 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
1064 /* @brief Index of port of external pin. */
1065 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
1066 /* @brief Number of external pin port on specified port. */
1067 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
1068 /* @brief Has external pin 25 connected to LLWU device. */
1069 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
1070 /* @brief Index of port of external pin. */
1071 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
1072 /* @brief Number of external pin port on specified port. */
1073 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
1074 /* @brief Has external pin 26 connected to LLWU device. */
1075 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
1076 /* @brief Index of port of external pin. */
1077 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
1078 /* @brief Number of external pin port on specified port. */
1079 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
1080 /* @brief Has external pin 27 connected to LLWU device. */
1081 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
1082 /* @brief Index of port of external pin. */
1083 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
1084 /* @brief Number of external pin port on specified port. */
1085 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
1086 /* @brief Has external pin 28 connected to LLWU device. */
1087 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
1088 /* @brief Index of port of external pin. */
1089 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
1090 /* @brief Number of external pin port on specified port. */
1091 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
1092 /* @brief Has external pin 29 connected to LLWU device. */
1093 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
1094 /* @brief Index of port of external pin. */
1095 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
1096 /* @brief Number of external pin port on specified port. */
1097 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
1098 /* @brief Has external pin 30 connected to LLWU device. */
1099 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
1100 /* @brief Index of port of external pin. */
1101 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
1102 /* @brief Number of external pin port on specified port. */
1103 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
1104 /* @brief Has external pin 31 connected to LLWU device. */
1105 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
1106 /* @brief Index of port of external pin. */
1107 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
1108 /* @brief Number of external pin port on specified port. */
1109 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
1110 /* @brief Has internal module 0 connected to LLWU device. */
1111 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
1112 /* @brief Has internal module 1 connected to LLWU device. */
1113 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
1114 /* @brief Has internal module 2 connected to LLWU device. */
1115 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
1116 /* @brief Has internal module 3 connected to LLWU device. */
1117 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
1118 /* @brief Has internal module 4 connected to LLWU device. */
1119 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
1120 /* @brief Has internal module 5 connected to LLWU device. */
1121 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0)
1122 /* @brief Has internal module 6 connected to LLWU device. */
1123 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
1124 /* @brief Has internal module 7 connected to LLWU device. */
1125 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0)
1126 /* @brief Has Version ID Register (LLWU_VERID). */
1127 #define FSL_FEATURE_LLWU_HAS_VERID (0)
1128 /* @brief Has Parameter Register (LLWU_PARAM). */
1129 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
1130 /* @brief Width of registers of the LLWU. */
1131 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
1132 /* @brief Has DMA Enable register (LLWU_DE). */
1133 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
1134#elif defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLH10)
1135 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
1136 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
1137 /* @brief Has pins 8-15 connected to LLWU device. */
1138 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
1139 /* @brief Maximum number of internal modules connected to LLWU device. */
1140 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3)
1141 /* @brief Number of digital filters. */
1142 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
1143 /* @brief Has MF register. */
1144 #define FSL_FEATURE_LLWU_HAS_MF (0)
1145 /* @brief Has PF register. */
1146 #define FSL_FEATURE_LLWU_HAS_PF (0)
1147 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
1148 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
1149 /* @brief Has no internal module wakeup flag register. */
1150 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
1151 /* @brief Has external pin 0 connected to LLWU device. */
1152 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
1153 /* @brief Index of port of external pin. */
1154 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
1155 /* @brief Number of external pin port on specified port. */
1156 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
1157 /* @brief Has external pin 1 connected to LLWU device. */
1158 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0)
1159 /* @brief Index of port of external pin. */
1160 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0)
1161 /* @brief Number of external pin port on specified port. */
1162 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0)
1163 /* @brief Has external pin 2 connected to LLWU device. */
1164 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0)
1165 /* @brief Index of port of external pin. */
1166 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0)
1167 /* @brief Number of external pin port on specified port. */
1168 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0)
1169 /* @brief Has external pin 3 connected to LLWU device. */
1170 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
1171 /* @brief Index of port of external pin. */
1172 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
1173 /* @brief Number of external pin port on specified port. */
1174 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
1175 /* @brief Has external pin 4 connected to LLWU device. */
1176 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
1177 /* @brief Index of port of external pin. */
1178 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
1179 /* @brief Number of external pin port on specified port. */
1180 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
1181 /* @brief Has external pin 5 connected to LLWU device. */
1182 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
1183 /* @brief Index of port of external pin. */
1184 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
1185 /* @brief Number of external pin port on specified port. */
1186 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
1187 /* @brief Has external pin 6 connected to LLWU device. */
1188 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
1189 /* @brief Index of port of external pin. */
1190 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
1191 /* @brief Number of external pin port on specified port. */
1192 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
1193 /* @brief Has external pin 7 connected to LLWU device. */
1194 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
1195 /* @brief Index of port of external pin. */
1196 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
1197 /* @brief Number of external pin port on specified port. */
1198 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
1199 /* @brief Has external pin 8 connected to LLWU device. */
1200 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
1201 /* @brief Index of port of external pin. */
1202 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
1203 /* @brief Number of external pin port on specified port. */
1204 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
1205 /* @brief Has external pin 9 connected to LLWU device. */
1206 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
1207 /* @brief Index of port of external pin. */
1208 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
1209 /* @brief Number of external pin port on specified port. */
1210 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
1211 /* @brief Has external pin 10 connected to LLWU device. */
1212 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
1213 /* @brief Index of port of external pin. */
1214 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
1215 /* @brief Number of external pin port on specified port. */
1216 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
1217 /* @brief Has external pin 11 connected to LLWU device. */
1218 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
1219 /* @brief Index of port of external pin. */
1220 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
1221 /* @brief Number of external pin port on specified port. */
1222 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
1223 /* @brief Has external pin 12 connected to LLWU device. */
1224 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
1225 /* @brief Index of port of external pin. */
1226 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
1227 /* @brief Number of external pin port on specified port. */
1228 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
1229 /* @brief Has external pin 13 connected to LLWU device. */
1230 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
1231 /* @brief Index of port of external pin. */
1232 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
1233 /* @brief Number of external pin port on specified port. */
1234 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
1235 /* @brief Has external pin 14 connected to LLWU device. */
1236 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
1237 /* @brief Index of port of external pin. */
1238 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
1239 /* @brief Number of external pin port on specified port. */
1240 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
1241 /* @brief Has external pin 15 connected to LLWU device. */
1242 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
1243 /* @brief Index of port of external pin. */
1244 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
1245 /* @brief Number of external pin port on specified port. */
1246 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
1247 /* @brief Has external pin 16 connected to LLWU device. */
1248 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
1249 /* @brief Index of port of external pin. */
1250 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
1251 /* @brief Number of external pin port on specified port. */
1252 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
1253 /* @brief Has external pin 17 connected to LLWU device. */
1254 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
1255 /* @brief Index of port of external pin. */
1256 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
1257 /* @brief Number of external pin port on specified port. */
1258 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
1259 /* @brief Has external pin 18 connected to LLWU device. */
1260 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
1261 /* @brief Index of port of external pin. */
1262 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
1263 /* @brief Number of external pin port on specified port. */
1264 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
1265 /* @brief Has external pin 19 connected to LLWU device. */
1266 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
1267 /* @brief Index of port of external pin. */
1268 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
1269 /* @brief Number of external pin port on specified port. */
1270 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
1271 /* @brief Has external pin 20 connected to LLWU device. */
1272 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
1273 /* @brief Index of port of external pin. */
1274 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
1275 /* @brief Number of external pin port on specified port. */
1276 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
1277 /* @brief Has external pin 21 connected to LLWU device. */
1278 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
1279 /* @brief Index of port of external pin. */
1280 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
1281 /* @brief Number of external pin port on specified port. */
1282 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
1283 /* @brief Has external pin 22 connected to LLWU device. */
1284 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
1285 /* @brief Index of port of external pin. */
1286 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
1287 /* @brief Number of external pin port on specified port. */
1288 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
1289 /* @brief Has external pin 23 connected to LLWU device. */
1290 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
1291 /* @brief Index of port of external pin. */
1292 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
1293 /* @brief Number of external pin port on specified port. */
1294 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
1295 /* @brief Has external pin 24 connected to LLWU device. */
1296 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
1297 /* @brief Index of port of external pin. */
1298 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
1299 /* @brief Number of external pin port on specified port. */
1300 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
1301 /* @brief Has external pin 25 connected to LLWU device. */
1302 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
1303 /* @brief Index of port of external pin. */
1304 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
1305 /* @brief Number of external pin port on specified port. */
1306 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
1307 /* @brief Has external pin 26 connected to LLWU device. */
1308 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
1309 /* @brief Index of port of external pin. */
1310 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
1311 /* @brief Number of external pin port on specified port. */
1312 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
1313 /* @brief Has external pin 27 connected to LLWU device. */
1314 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
1315 /* @brief Index of port of external pin. */
1316 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
1317 /* @brief Number of external pin port on specified port. */
1318 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
1319 /* @brief Has external pin 28 connected to LLWU device. */
1320 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
1321 /* @brief Index of port of external pin. */
1322 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
1323 /* @brief Number of external pin port on specified port. */
1324 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
1325 /* @brief Has external pin 29 connected to LLWU device. */
1326 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
1327 /* @brief Index of port of external pin. */
1328 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
1329 /* @brief Number of external pin port on specified port. */
1330 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
1331 /* @brief Has external pin 30 connected to LLWU device. */
1332 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
1333 /* @brief Index of port of external pin. */
1334 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
1335 /* @brief Number of external pin port on specified port. */
1336 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
1337 /* @brief Has external pin 31 connected to LLWU device. */
1338 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
1339 /* @brief Index of port of external pin. */
1340 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
1341 /* @brief Number of external pin port on specified port. */
1342 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
1343 /* @brief Has internal module 0 connected to LLWU device. */
1344 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
1345 /* @brief Has internal module 1 connected to LLWU device. */
1346 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
1347 /* @brief Has internal module 2 connected to LLWU device. */
1348 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
1349 /* @brief Has internal module 3 connected to LLWU device. */
1350 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0)
1351 /* @brief Has internal module 4 connected to LLWU device. */
1352 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
1353 /* @brief Has internal module 5 connected to LLWU device. */
1354 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0)
1355 /* @brief Has internal module 6 connected to LLWU device. */
1356 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
1357 /* @brief Has internal module 7 connected to LLWU device. */
1358 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0)
1359 /* @brief Has Version ID Register (LLWU_VERID). */
1360 #define FSL_FEATURE_LLWU_HAS_VERID (0)
1361 /* @brief Has Parameter Register (LLWU_PARAM). */
1362 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
1363 /* @brief Width of registers of the LLWU. */
1364 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
1365 /* @brief Has DMA Enable register (LLWU_DE). */
1366 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
1367#endif /* defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) */
1368
1369/* LPTMR module features */
1370
1371/* @brief Has shared interrupt handler with another LPTMR module. */
1372#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
1373/* @brief Whether LPTMR counter is 32 bits width. */
1374#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
1375/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
1376#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
1377
1378/* MCG module features */
1379
1380/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
1381#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0)
1382/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
1383#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0)
1384/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
1385#define FSL_FEATURE_MCG_PLL_VDIV_BASE (0)
1386/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
1387#define FSL_FEATURE_MCG_PLL_REF_MIN (0)
1388/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
1389#define FSL_FEATURE_MCG_PLL_REF_MAX (0)
1390/* @brief The PLL clock is divided by 2 before VCO divider. */
1391#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
1392/* @brief FRDIV supports 1280. */
1393#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
1394/* @brief FRDIV supports 1536. */
1395#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
1396/* @brief MCGFFCLK divider. */
1397#define FSL_FEATURE_MCG_FFCLK_DIV (1)
1398/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
1399#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
1400/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
1401#define FSL_FEATURE_MCG_HAS_RTC_32K (0)
1402/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
1403#define FSL_FEATURE_MCG_HAS_PLL1 (0)
1404/* @brief Has 48MHz internal oscillator. */
1405#define FSL_FEATURE_MCG_HAS_IRC_48M (1)
1406/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
1407#define FSL_FEATURE_MCG_HAS_OSC1 (0)
1408/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
1409#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
1410/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
1411#define FSL_FEATURE_MCG_HAS_LOLRE (0)
1412/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
1413#define FSL_FEATURE_MCG_USE_OSCSEL (1)
1414/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
1415#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
1416/* @brief TBD */
1417#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
1418/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
1419#define FSL_FEATURE_MCG_HAS_PLL (0)
1420/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
1421#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0)
1422/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
1423#define FSL_FEATURE_MCG_HAS_PLL_VDIV (0)
1424/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
1425#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
1426/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
1427#define FSL_FEATURE_MCG_HAS_FLL (1)
1428/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
1429#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
1430/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
1431#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
1432/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
1433#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0)
1434/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
1435#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
1436/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
1437#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
1438/* @brief Has external clock monitor (register bit C6[CME]). */
1439#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
1440/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
1441#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
1442/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
1443#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
1444/* @brief Has PEI mode or PBI mode. */
1445#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
1446/* @brief Reset clock mode is BLPI. */
1447#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
1448
1449/* interrupt module features */
1450
1451/* @brief Lowest interrupt request number. */
1452#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
1453/* @brief Highest interrupt request number. */
1454#define FSL_FEATURE_INTERRUPT_IRQ_MAX (73)
1455
1456/* OSC module features */
1457
1458/* @brief Has OSC1 external oscillator. */
1459#define FSL_FEATURE_OSC_HAS_OSC1 (0)
1460/* @brief Has OSC0 external oscillator. */
1461#define FSL_FEATURE_OSC_HAS_OSC0 (0)
1462/* @brief Has OSC external oscillator (without index). */
1463#define FSL_FEATURE_OSC_HAS_OSC (1)
1464/* @brief Number of OSC external oscillators. */
1465#define FSL_FEATURE_OSC_OSC_COUNT (1)
1466/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
1467#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1)
1468
1469/* PDB module features */
1470
1471/* @brief Has DAC support. */
1472#define FSL_FEATURE_PDB_HAS_DAC (1)
1473/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
1474#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
1475/* @brief PDB channel number). */
1476#define FSL_FEATURE_PDB_CHANNEL_COUNT (2)
1477/* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */
1478#define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2)
1479/* @brief DAC interval trigger number). */
1480#define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (1)
1481/* @brief Pulse out number). */
1482#define FSL_FEATURE_PDB_PULSE_OUT_COUNT (2)
1483
1484/* PIT module features */
1485
1486/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
1487#define FSL_FEATURE_PIT_TIMER_COUNT (4)
1488/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
1489#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
1490/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
1491#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
1492/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
1493#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
1494/* @brief Has timer enable control. */
1495#define FSL_FEATURE_PIT_HAS_MDIS (1)
1496
1497/* PMC module features */
1498
1499/* @brief Has Bandgap Enable In VLPx Operation support. */
1500#define FSL_FEATURE_PMC_HAS_BGEN (1)
1501/* @brief Has Bandgap Buffer Enable. */
1502#define FSL_FEATURE_PMC_HAS_BGBE (1)
1503/* @brief Has Bandgap Buffer Drive Select. */
1504#define FSL_FEATURE_PMC_HAS_BGBDS (0)
1505/* @brief Has Low-Voltage Detect Voltage Select support. */
1506#define FSL_FEATURE_PMC_HAS_LVDV (1)
1507/* @brief Has Low-Voltage Warning Voltage Select support. */
1508#define FSL_FEATURE_PMC_HAS_LVWV (1)
1509/* @brief Has LPO. */
1510#define FSL_FEATURE_PMC_HAS_LPO (0)
1511/* @brief Has VLPx option PMC_REGSC[VLPO]. */
1512#define FSL_FEATURE_PMC_HAS_VLPO (0)
1513/* @brief Has acknowledge isolation support. */
1514#define FSL_FEATURE_PMC_HAS_ACKISO (1)
1515/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
1516#define FSL_FEATURE_PMC_HAS_REGFPM (0)
1517/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
1518#define FSL_FEATURE_PMC_HAS_REGONS (1)
1519/* @brief Has PMC_HVDSC1. */
1520#define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
1521/* @brief Has PMC_PARAM. */
1522#define FSL_FEATURE_PMC_HAS_PARAM (0)
1523/* @brief Has PMC_VERID. */
1524#define FSL_FEATURE_PMC_HAS_VERID (0)
1525
1526/* PORT module features */
1527
1528/* @brief Has control lock (register bit PCR[LK]). */
1529#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
1530/* @brief Has open drain control (register bit PCR[ODE]). */
1531#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
1532/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
1533#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
1534/* @brief Has DMA request (register bit field PCR[IRQC] values). */
1535#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
1536/* @brief Has pull resistor selection available. */
1537#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
1538/* @brief Has pull resistor enable (register bit PCR[PE]). */
1539#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
1540/* @brief Has slew rate control (register bit PCR[SRE]). */
1541#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
1542/* @brief Has passive filter (register bit field PCR[PFE]). */
1543#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
1544/* @brief Has drive strength control (register bit PCR[DSE]). */
1545#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
1546/* @brief Has separate drive strength register (HDRVE). */
1547#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
1548/* @brief Has glitch filter (register IOFLT). */
1549#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
1550/* @brief Defines width of PCR[MUX] field. */
1551#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
1552/* @brief Has dedicated interrupt vector. */
1553#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
1554/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
1555#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
1556/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
1557#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
1558/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
1559#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
1560
1561/* RCM module features */
1562
1563/* @brief Has Loss-of-Lock Reset support. */
1564#define FSL_FEATURE_RCM_HAS_LOL (0)
1565/* @brief Has Loss-of-Clock Reset support. */
1566#define FSL_FEATURE_RCM_HAS_LOC (1)
1567/* @brief Has JTAG generated Reset support. */
1568#define FSL_FEATURE_RCM_HAS_JTAG (1)
1569/* @brief Has EzPort generated Reset support. */
1570#define FSL_FEATURE_RCM_HAS_EZPORT (0)
1571/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
1572#define FSL_FEATURE_RCM_HAS_EZPMS (0)
1573/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
1574#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
1575/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
1576#define FSL_FEATURE_RCM_HAS_SSRS (1)
1577/* @brief Has Version ID Register (RCM_VERID). */
1578#define FSL_FEATURE_RCM_HAS_VERID (0)
1579/* @brief Has Parameter Register (RCM_PARAM). */
1580#define FSL_FEATURE_RCM_HAS_PARAM (0)
1581/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
1582#define FSL_FEATURE_RCM_HAS_SRIE (0)
1583/* @brief Width of registers of the RCM. */
1584#define FSL_FEATURE_RCM_REG_WIDTH (8)
1585/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
1586#define FSL_FEATURE_RCM_HAS_CORE1 (0)
1587/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
1588#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
1589/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
1590#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
1591
1592/* SIM module features */
1593
1594/* @brief Has USB FS divider. */
1595#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1596/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1597#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
1598/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1599#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
1600/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1601#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1)
1602/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1603#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
1604/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1605#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
1606/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1607#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0)
1608/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1609#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0)
1610/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1611#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1612/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1613#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
1614/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1615#define FSL_FEATURE_SIM_OPT_HAS_FBSL (0)
1616/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1617#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1618/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1619#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1620/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1621#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1622/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
1623#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
1624/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1625#define FSL_FEATURE_SIM_OPT_UART_COUNT (2)
1626/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
1627#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
1628/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
1629#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
1630/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
1631#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
1632/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1633#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1634/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1635#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1636/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1637#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1638/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1639#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
1640/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1641#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
1642/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1643#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1644/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1645#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1646/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1647#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
1648/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1649#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
1650/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1651#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
1652/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1653#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
1654/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1655#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
1656/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1657#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
1658/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1659#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
1660/* @brief Has FTM module(s) configuration. */
1661#define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
1662/* @brief Number of FTM modules. */
1663#define FSL_FEATURE_SIM_OPT_FTM_COUNT (3)
1664/* @brief Number of FTM triggers with selectable source. */
1665#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
1666/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1667#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
1668/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1669#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0)
1670/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1671#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
1672/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1673#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
1674/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1675#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1676/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1677#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1)
1678/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1679#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2)
1680/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1681#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
1682/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1683#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
1684/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1685#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0)
1686/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1687#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
1688/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1689#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
1690/* @brief Has TPM module(s) configuration. */
1691#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
1692/* @brief The highest TPM module index. */
1693#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
1694/* @brief Has TPM module with index 0. */
1695#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
1696/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
1697#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
1698/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1699#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
1700/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1701#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
1702/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
1703#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
1704/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1705#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
1706/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1707#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
1708/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1709#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
1710/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1711#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
1712/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1713#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
1714/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1715#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1716/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1717#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1718/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1719#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0)
1720/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1721#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1722/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1723#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
1724/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1725#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1726/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1727#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0)
1728/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1729#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1730/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1731#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1732/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1733#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1734/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1735#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1736/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1737#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1738/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1739#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1740/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1741#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1742/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1743#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
1744/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1745#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
1746/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1747#define FSL_FEATURE_SIM_OPT_ADC_COUNT (1)
1748/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
1749#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
1750/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
1751#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0)
1752/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
1753#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
1754/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
1755#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
1756/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
1757#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
1758/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
1759#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
1760/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
1761#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
1762/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
1763#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
1764/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
1765#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
1766/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
1767#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
1768/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1769#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
1770/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1771#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0)
1772/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1773#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
1774/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1775#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
1776/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
1777#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
1778/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1779#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0)
1780/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1781#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1782/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1783#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1784/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1785#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1786/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1787#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1788/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1789#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
1790/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1791#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1792/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1793#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
1794/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1795#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1796/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1797#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1798/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1799#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1800/* @brief Has device die ID (register bit field SDID[DIEID]). */
1801#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
1802/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1803#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
1804/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1805#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1806/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1807#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1808/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1809#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1810/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1811#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0)
1812/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1813#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0)
1814/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1815#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0)
1816/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1817#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
1818/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1819#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0)
1820/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1821#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
1822/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1823#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1824/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1825#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0)
1826/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1827#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
1828/* @brief Has miscellanious control register (register MCR). */
1829#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1830/* @brief Has COP watchdog (registers COPC and SRVCOP). */
1831#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
1832/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1833#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1834/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
1835#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
1836
1837/* SMC module features */
1838
1839/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
1840#define FSL_FEATURE_SMC_HAS_PSTOPO (1)
1841/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
1842#define FSL_FEATURE_SMC_HAS_LPOPO (0)
1843/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
1844#define FSL_FEATURE_SMC_HAS_PORPO (1)
1845/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
1846#define FSL_FEATURE_SMC_HAS_LPWUI (0)
1847/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
1848#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1)
1849/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
1850#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
1851/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
1852#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
1853/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
1854#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
1855/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
1856#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
1857/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
1858#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
1859/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
1860#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
1861/* @brief Has stop submode. */
1862#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
1863/* @brief Has stop submode 0(VLLS0). */
1864#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
1865/* @brief Has stop submode 1(VLLS1). */
1866#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1)
1867/* @brief Has stop submode 2(VLLS2). */
1868#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
1869/* @brief Has SMC_PARAM. */
1870#define FSL_FEATURE_SMC_HAS_PARAM (0)
1871/* @brief Has SMC_VERID. */
1872#define FSL_FEATURE_SMC_HAS_VERID (0)
1873/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
1874#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
1875/* @brief Has tamper reset (register bit SRS[TAMPER]). */
1876#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
1877/* @brief Has security violation reset (register bit SRS[SECVIO]). */
1878#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
1879/* @brief Width of SMC registers. */
1880#define FSL_FEATURE_SMC_REG_WIDTH (8)
1881
1882/* DSPI module features */
1883
1884#if defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10)
1885 /* @brief Receive/transmit FIFO size in number of items. */
1886 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4)
1887 /* @brief Maximum transfer data width in bits. */
1888 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
1889 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
1890 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
1891 /* @brief Number of chip select pins. */
1892 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (4)
1893 /* @brief Number of CTAR registers. */
1894 #define FSL_FEATURE_DSPI_CTAR_COUNT (2)
1895 /* @brief Has chip select strobe capability on the PCS5 pin. */
1896 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
1897 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
1898 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
1899 /* @brief Has 16-bit data transfer support. */
1900 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
1901 /* @brief Has separate DMA RX and TX requests. */
1902 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
1903#elif defined(CPU_MK02FN128VLF10) || defined(CPU_MK02FN128VLH10) || defined(CPU_MK02FN64VLF10) || defined(CPU_MK02FN64VLH10)
1904 /* @brief Receive/transmit FIFO size in number of items. */
1905 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4)
1906 /* @brief Maximum transfer data width in bits. */
1907 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
1908 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
1909 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
1910 /* @brief Number of chip select pins. */
1911 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5)
1912 /* @brief Number of CTAR registers. */
1913 #define FSL_FEATURE_DSPI_CTAR_COUNT (2)
1914 /* @brief Has chip select strobe capability on the PCS5 pin. */
1915 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
1916 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
1917 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
1918 /* @brief Has 16-bit data transfer support. */
1919 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
1920 /* @brief Has separate DMA RX and TX requests. */
1921 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
1922#endif /* defined(CPU_MK02FN128VFM10) || defined(CPU_MK02FN64VFM10) */
1923
1924/* SysTick module features */
1925
1926/* @brief Systick has external reference clock. */
1927#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
1928/* @brief Systick external reference clock is core clock divided by this value. */
1929#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
1930
1931/* UART module features */
1932
1933/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
1934#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
1935/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
1936#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
1937/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
1938#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
1939/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1940#define FSL_FEATURE_UART_HAS_FIFO (1)
1941/* @brief Hardware flow control (RTS, CTS) is supported. */
1942#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
1943/* @brief Infrared (modulation) is supported. */
1944#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
1945/* @brief 2 bits long stop bit is available. */
1946#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (0)
1947/* @brief If 10-bit mode is supported. */
1948#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
1949/* @brief Baud rate fine adjustment is available. */
1950#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
1951/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
1952#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
1953/* @brief Baud rate oversampling is available. */
1954#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
1955/* @brief Baud rate oversampling is available. */
1956#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
1957/* @brief Peripheral type. */
1958#define FSL_FEATURE_UART_IS_SCI (0)
1959/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1960#define FSL_FEATURE_UART_FIFO_SIZEn(x) \
1961 (((x) == UART0) ? (8) : \
1962 (((x) == UART1) ? (1) : (-1)))
1963/* @brief Supports two match addresses to filter incoming frames. */
1964#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
1965/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
1966#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
1967/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
1968#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
1969/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
1970#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
1971/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
1972#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0)
1973/* @brief Has improved smart card (ISO7816 protocol) support. */
1974#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
1975/* @brief Has local operation network (CEA709.1-B protocol) support. */
1976#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
1977/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
1978#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
1979/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
1980#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
1981/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
1982#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
1983/* @brief Has separate DMA RX and TX requests. */
1984#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
1985
1986/* VREF module features */
1987
1988/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
1989#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
1990/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
1991#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
1992/* @brief If high/low buffer mode supported */
1993#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
1994/* @brief Module has also low reference (registers VREFL/VREFH) */
1995#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
1996/* @brief Has VREF_TRM4. */
1997#define FSL_FEATURE_VREF_HAS_TRM4 (0)
1998
1999/* WDOG module features */
2000
2001/* @brief Watchdog is available. */
2002#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
2003/* @brief Has Wait mode support. */
2004#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
2005
2006#endif /* _MK02F12810_FEATURES_H_ */
2007
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