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1/*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_CLOCK_H_
10#define _FSL_CLOCK_H_
11
12#include "fsl_common.h"
13
14/*! @addtogroup clock */
15/*! @{ */
16
17/*! @file */
18
19/*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23/*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37#ifndef MCG_CONFIG_CHECK_PARAM
38#define MCG_CONFIG_CHECK_PARAM 0U
39#endif
40
41/*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53#endif
54
55/*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59/*! @name Driver version */
60/*@{*/
61/*! @brief CLOCK driver version 2.5.1. */
62#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
63/*@}*/
64
65/*! @brief External XTAL0 (OSC0) clock frequency.
66 *
67 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
68 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
69 * if XTAL0 is 8 MHz:
70 * @code
71 * Set up the OSC0
72 * CLOCK_InitOsc0(...);
73 * Set the XTAL0 value to the clock driver.
74 * CLOCK_SetXtal0Freq(80000000);
75 * @endcode
76 *
77 * This is important for the multicore platforms where only one core needs to set up the
78 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
79 * to get a valid clock frequency.
80 */
81extern volatile uint32_t g_xtal0Freq;
82
83/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
84 *
85 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
86 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
87 *
88 * This is important for the multicore platforms where only one core needs to set up
89 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
90 * to get a valid clock frequency.
91 */
92extern volatile uint32_t g_xtal32Freq;
93
94/*! @brief IRC48M clock frequency in Hz. */
95#define MCG_INTERNAL_IRC_48M 48000000U
96
97#if (defined(OSC) && !(defined(OSC0)))
98#define OSC0 OSC
99#endif
100
101/* Definition for delay API in clock driver, users can redefine it to the real application. */
102#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
103#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (120000000UL)
104#endif
105
106/*! @brief Clock ip name array for DMAMUX. */
107#define DMAMUX_CLOCKS \
108 { \
109 kCLOCK_Dmamux0 \
110 }
111
112/*! @brief Clock ip name array for RTC. */
113#define RTC_CLOCKS \
114 { \
115 kCLOCK_Rtc0 \
116 }
117
118/*! @brief Clock ip name array for SAI. */
119#define SAI_CLOCKS \
120 { \
121 kCLOCK_Sai0 \
122 }
123
124/*! @brief Clock ip name array for PORT. */
125#define PORT_CLOCKS \
126 { \
127 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
128 }
129
130/*! @brief Clock ip name array for EWM. */
131#define EWM_CLOCKS \
132 { \
133 kCLOCK_Ewm0 \
134 }
135
136/*! @brief Clock ip name array for PIT. */
137#define PIT_CLOCKS \
138 { \
139 kCLOCK_Pit0 \
140 }
141
142/*! @brief Clock ip name array for DSPI. */
143#define DSPI_CLOCKS \
144 { \
145 kCLOCK_Spi0, kCLOCK_Spi1 \
146 }
147
148/*! @brief Clock ip name array for LPTMR. */
149#define LPTMR_CLOCKS \
150 { \
151 kCLOCK_Lptmr0 \
152 }
153
154/*! @brief Clock ip name array for FTM. */
155#define FTM_CLOCKS \
156 { \
157 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2 \
158 }
159
160/*! @brief Clock ip name array for EDMA. */
161#define EDMA_CLOCKS \
162 { \
163 kCLOCK_Dma0 \
164 }
165
166/*! @brief Clock ip name array for LPUART. */
167#define LPUART_CLOCKS \
168 { \
169 kCLOCK_Lpuart0 \
170 }
171
172/*! @brief Clock ip name array for DAC. */
173#define DAC_CLOCKS \
174 { \
175 kCLOCK_Dac0 \
176 }
177
178/*! @brief Clock ip name array for ADC16. */
179#define ADC16_CLOCKS \
180 { \
181 kCLOCK_Adc0, kCLOCK_Adc1 \
182 }
183
184/*! @brief Clock ip name array for VREF. */
185#define VREF_CLOCKS \
186 { \
187 kCLOCK_Vref0 \
188 }
189
190/*! @brief Clock ip name array for UART. */
191#define UART_CLOCKS \
192 { \
193 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2 \
194 }
195
196/*! @brief Clock ip name array for RNGA. */
197#define RNGA_CLOCKS \
198 { \
199 kCLOCK_Rnga0 \
200 }
201
202/*! @brief Clock ip name array for CRC. */
203#define CRC_CLOCKS \
204 { \
205 kCLOCK_Crc0 \
206 }
207
208/*! @brief Clock ip name array for I2C. */
209#define I2C_CLOCKS \
210 { \
211 kCLOCK_I2c0, kCLOCK_I2c1 \
212 }
213
214/*! @brief Clock ip name array for FTF. */
215#define FTF_CLOCKS \
216 { \
217 kCLOCK_Ftf0 \
218 }
219
220/*! @brief Clock ip name array for PDB. */
221#define PDB_CLOCKS \
222 { \
223 kCLOCK_Pdb0 \
224 }
225
226/*! @brief Clock ip name array for CMP. */
227#define CMP_CLOCKS \
228 { \
229 kCLOCK_Cmp0, kCLOCK_Cmp1 \
230 }
231
232/*!
233 * @brief LPO clock frequency.
234 */
235#define LPO_CLK_FREQ 1000U
236
237/*! @brief Peripherals clock source definition. */
238#define SYS_CLK kCLOCK_CoreSysClk
239#define BUS_CLK kCLOCK_BusClk
240#define FAST_CLK kCLOCK_FastPeriphClk
241
242#define I2C0_CLK_SRC BUS_CLK
243#define I2C1_CLK_SRC BUS_CLK
244#define DSPI0_CLK_SRC BUS_CLK
245#define DSPI1_CLK_SRC BUS_CLK
246#define UART0_CLK_SRC SYS_CLK
247#define UART1_CLK_SRC SYS_CLK
248#define UART2_CLK_SRC BUS_CLK
249
250/*! @brief Clock name used to get clock frequency. */
251typedef enum _clock_name
252{
253
254 /* ----------------------------- System layer clock -------------------------------*/
255 kCLOCK_CoreSysClk, /*!< Core/system clock */
256 kCLOCK_PlatClk, /*!< Platform clock */
257 kCLOCK_BusClk, /*!< Bus clock */
258 kCLOCK_FlexBusClk, /*!< FlexBus clock */
259 kCLOCK_FlashClk, /*!< Flash clock */
260 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
261 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
262
263 /* ---------------------------------- OSC clock -----------------------------------*/
264 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
265 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
266 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
267 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
268
269 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
270 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
271 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
272 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
273 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
274 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
275 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
276 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
277 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
278
279 /* --------------------------------- Other clock ----------------------------------*/
280 kCLOCK_LpoClk, /*!< LPO clock */
281
282} clock_name_t;
283
284/*! @brief USB clock source definition. */
285typedef enum _clock_usb_src
286{
287 kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */
288 kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */
289 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */
290} clock_usb_src_t;
291/*------------------------------------------------------------------------------
292
293 clock_gate_t definition:
294
295 31 16 0
296 -----------------------------------------------------------------
297 | SIM_SCGC register offset | control bit offset in SCGC |
298 -----------------------------------------------------------------
299
300 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
301 SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as
302
303 kCLOCK_GateSdhc0 = (0x1030 << 16) | 17;
304
305------------------------------------------------------------------------------*/
306
307#define CLK_GATE_REG_OFFSET_SHIFT 16U
308#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
309#define CLK_GATE_BIT_SHIFT_SHIFT 0U
310#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
311
312#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
313 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
314 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
315
316#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
317#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
318
319/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
320typedef enum _clock_ip_name
321{
322 kCLOCK_IpInvalid = 0U,
323
324 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
325 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
326 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
327 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
328 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
329 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
330 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
331 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
332 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
333 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
334
335 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
336 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
337 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
338 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
339 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
340 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
341
342 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
343 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
344 kCLOCK_Adc1 = CLK_GATE_DEFINE(0x103CU, 7U),
345 kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x103CU, 9U),
346 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x103CU, 10U),
347 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
348 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
349 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
350 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
351 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
352 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
353 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
354 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
355 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
356 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
357 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
358 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
359
360 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
361} clock_ip_name_t;
362
363/*!@brief SIM configuration structure for clock setting. */
364typedef struct _sim_clock_config
365{
366 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
367 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
368 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
369} sim_clock_config_t;
370
371/*! @brief OSC work mode. */
372typedef enum _osc_mode
373{
374 kOSC_ModeExt = 0U, /*!< Use an external clock. */
375#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
376 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
377#else
378 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
379#endif
380 kOSC_ModeOscHighGain = 0U
381#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
382 | MCG_C2_EREFS_MASK
383#else
384 | MCG_C2_EREFS0_MASK
385#endif
386#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
387 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
388#else
389 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
390#endif
391} osc_mode_t;
392
393/*! @brief Oscillator capacitor load setting.*/
394enum _osc_cap_load
395{
396 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
397 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
398 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
399 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
400};
401
402/*! @brief OSCERCLK enable mode. */
403enum _oscer_enable_mode
404{
405 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
406 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
407};
408
409/*! @brief OSC configuration for OSCERCLK. */
410typedef struct _oscer_config
411{
412 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
413
414 uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/
415} oscer_config_t;
416
417/*!
418 * @brief OSC Initialization Configuration Structure
419 *
420 * Defines the configuration data structure to initialize the OSC.
421 * When porting to a new board, set the following members
422 * according to the board setting:
423 * 1. freq: The external frequency.
424 * 2. workMode: The OSC module mode.
425 */
426typedef struct _osc_config
427{
428 uint32_t freq; /*!< External clock frequency. */
429 uint8_t capLoad; /*!< Capacitor load setting. */
430 osc_mode_t workMode; /*!< OSC work mode setting. */
431 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
432} osc_config_t;
433
434/*! @brief MCG FLL reference clock source select. */
435typedef enum _mcg_fll_src
436{
437 kMCG_FllSrcExternal, /*!< External reference clock is selected */
438 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
439} mcg_fll_src_t;
440
441/*! @brief MCG internal reference clock select */
442typedef enum _mcg_irc_mode
443{
444 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
445 kMCG_IrcFast /*!< Fast internal reference clock selected */
446} mcg_irc_mode_t;
447
448/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
449typedef enum _mcg_dmx32
450{
451 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
452 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
453} mcg_dmx32_t;
454
455/*! @brief MCG DCO range select */
456typedef enum _mcg_drs
457{
458 kMCG_DrsLow, /*!< Low frequency range */
459 kMCG_DrsMid, /*!< Mid frequency range */
460 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
461 kMCG_DrsHigh /*!< High frequency range */
462} mcg_drs_t;
463
464/*! @brief MCG PLL reference clock select */
465typedef enum _mcg_pll_ref_src
466{
467 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
468 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
469} mcg_pll_ref_src_t;
470
471/*! @brief MCGOUT clock source. */
472typedef enum _mcg_clkout_src
473{
474 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
475 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
476 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
477} mcg_clkout_src_t;
478
479/*! @brief MCG Automatic Trim Machine Select */
480typedef enum _mcg_atm_select
481{
482 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
483 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
484} mcg_atm_select_t;
485
486/*! @brief MCG OSC Clock Select */
487typedef enum _mcg_oscsel
488{
489 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
490 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
491 kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */
492} mcg_oscsel_t;
493
494/*! @brief MCG PLLCS select */
495typedef enum _mcg_pll_clk_select
496{
497 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
498 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
499} mcg_pll_clk_select_t;
500
501/*! @brief MCG clock monitor mode. */
502typedef enum _mcg_monitor_mode
503{
504 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
505 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
506 kMCG_MonitorReset /*!< System reset when clock lost. */
507} mcg_monitor_mode_t;
508
509/*! @brief MCG status. Enumeration _mcg_status */
510enum
511{
512 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), /*!< Can't switch to target mode. */
513 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), /*!< Current mode invalid for the specific
514 function. */
515 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), /*!< Invalid bus clock for ATM. */
516 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), /*!< Invalid desired frequency for ATM. */
517 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), /*!< IRC is used when using ATM. */
518 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), /*!< Hardware fail occurs during ATM. */
519 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) /*!< Can't change the clock source because
520 it is in use. */
521};
522
523/*! @brief MCG status flags. Enumeration _mcg_status_flags_t */
524enum
525{
526 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
527 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
528 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
529 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
530 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
531};
532
533/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. Enumeration _mcg_irclk_enable_mode */
534enum
535{
536 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
537 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
538};
539
540/*! @brief MCG PLL clock enable mode definition. Enumeration _mcg_pll_enable_mode */
541enum
542{
543 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
544 MCG clock mode. Generally, the PLL
545 is disabled in FLL modes
546 (FEI/FBI/FEE/FBE). Setting the PLL clock
547 enable independent, enables the
548 PLL in the FLL modes. */
549 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
550};
551
552/*! @brief MCG mode definitions */
553typedef enum _mcg_mode
554{
555 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
556 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
557 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
558 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
559 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
560 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
561 kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
562 kMCG_ModePEE, /*!< PEE - PLL Engaged External */
563 kMCG_ModeError /*!< Unknown mode */
564} mcg_mode_t;
565
566/*! @brief MCG PLL configuration. */
567typedef struct _mcg_pll_config
568{
569 uint8_t enableMode; /*!< Enable mode. OR'ed value of enumeration _mcg_pll_enable_mode. */
570 uint8_t prdiv; /*!< Reference divider PRDIV. */
571 uint8_t vdiv; /*!< VCO divider VDIV. */
572} mcg_pll_config_t;
573
574/*! @brief MCG mode change configuration structure
575 *
576 * When porting to a new board, set the following members
577 * according to the board setting:
578 * 1. frdiv: If the FLL uses the external reference clock, set this
579 * value to ensure that the external reference clock divided by frdiv is
580 * in the 31.25 kHz to 39.0625 kHz range.
581 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
582 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
583 * FSL_FEATURE_MCG_PLL_REF_MAX range.
584 */
585typedef struct _mcg_config
586{
587 mcg_mode_t mcgMode; /*!< MCG mode. */
588
589 /* ----------------------- MCGIRCCLK settings ------------------------ */
590 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
591 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
592 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
593
594 /* ------------------------ MCG FLL settings ------------------------- */
595 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
596 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
597 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
598 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
599
600 /* ------------------------ MCG PLL settings ------------------------- */
601 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
602
603} mcg_config_t;
604
605/*******************************************************************************
606 * API
607 ******************************************************************************/
608
609#if defined(__cplusplus)
610extern "C" {
611#endif /* __cplusplus */
612
613/*!
614 * @brief Enable the clock for specific IP.
615 *
616 * @param name Which clock to enable, see \ref clock_ip_name_t.
617 */
618static inline void CLOCK_EnableClock(clock_ip_name_t name)
619{
620 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
621 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
622}
623
624/*!
625 * @brief Disable the clock for specific IP.
626 *
627 * @param name Which clock to disable, see \ref clock_ip_name_t.
628 */
629static inline void CLOCK_DisableClock(clock_ip_name_t name)
630{
631 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
632 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
633}
634
635/*!
636 * @brief Set LPUART clock source.
637 *
638 * @param src The value to set LPUART clock source.
639 */
640static inline void CLOCK_SetLpuartClock(uint32_t src)
641{
642 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) | SIM_SOPT2_LPUARTSRC(src));
643}
644
645/*!
646 * @brief Set ERCLK32K source.
647 *
648 * @param src The value to set ERCLK32K clock source.
649 */
650static inline void CLOCK_SetEr32kClock(uint32_t src)
651{
652 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
653}
654
655/*!
656 * @brief Set debug trace clock source.
657 *
658 * @param src The value to set debug trace clock source.
659 */
660static inline void CLOCK_SetTraceClock(uint32_t src)
661{
662 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
663}
664
665/*!
666 * @brief Set PLLFLLSEL clock source.
667 *
668 * @param src The value to set PLLFLLSEL clock source.
669 */
670static inline void CLOCK_SetPllFllSelClock(uint32_t src)
671{
672 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
673}
674
675/*!
676 * @brief Set CLKOUT source.
677 *
678 * @param src The value to set CLKOUT source.
679 */
680static inline void CLOCK_SetClkOutClock(uint32_t src)
681{
682 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
683}
684
685/*!
686 * @brief Set RTC_CLKOUT source.
687 *
688 * @param src The value to set RTC_CLKOUT source.
689 */
690static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
691{
692 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
693}
694
695/*! @brief Enable USB FS clock.
696 *
697 * @param src USB FS clock source.
698 * @param freq The frequency specified by src.
699 * @retval true The clock is set successfully.
700 * @retval false The clock source is invalid to get proper USB FS clock.
701 */
702bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
703
704/*! @brief Disable USB FS clock.
705 *
706 * Disable USB FS clock.
707 */
708static inline void CLOCK_DisableUsbfs0Clock(void)
709{
710 CLOCK_DisableClock(kCLOCK_Usbfs0);
711}
712
713/*!
714 * @brief System clock divider
715 *
716 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV4].
717 *
718 * @param outdiv1 Clock 1 output divider value.
719 *
720 * @param outdiv2 Clock 2 output divider value.
721 *
722 * @param outdiv4 Clock 4 output divider value.
723 */
724static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv4)
725{
726 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV4(outdiv4);
727}
728
729/*!
730 * @brief Gets the clock frequency for a specific clock name.
731 *
732 * This function checks the current clock configurations and then calculates
733 * the clock frequency for a specific clock name defined in clock_name_t.
734 * The MCG must be properly configured before using this function.
735 *
736 * @param clockName Clock names defined in clock_name_t
737 * @return Clock frequency value in Hertz
738 */
739uint32_t CLOCK_GetFreq(clock_name_t clockName);
740
741/*!
742 * @brief Get the core clock or system clock frequency.
743 *
744 * @return Clock frequency in Hz.
745 */
746uint32_t CLOCK_GetCoreSysClkFreq(void);
747
748/*!
749 * @brief Get the platform clock frequency.
750 *
751 * @return Clock frequency in Hz.
752 */
753uint32_t CLOCK_GetPlatClkFreq(void);
754
755/*!
756 * @brief Get the bus clock frequency.
757 *
758 * @return Clock frequency in Hz.
759 */
760uint32_t CLOCK_GetBusClkFreq(void);
761
762/*!
763 * @brief Get the flash clock frequency.
764 *
765 * @return Clock frequency in Hz.
766 */
767uint32_t CLOCK_GetFlashClkFreq(void);
768
769/*!
770 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
771 *
772 * @return Clock frequency in Hz.
773 */
774uint32_t CLOCK_GetPllFllSelClkFreq(void);
775
776/*!
777 * @brief Get the external reference 32K clock frequency (ERCLK32K).
778 *
779 * @return Clock frequency in Hz.
780 */
781uint32_t CLOCK_GetEr32kClkFreq(void);
782
783/*!
784 * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV).
785 *
786 * @return Clock frequency in Hz.
787 */
788uint32_t CLOCK_GetOsc0ErClkUndivFreq(void);
789
790/*!
791 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
792 *
793 * @return Clock frequency in Hz.
794 */
795uint32_t CLOCK_GetOsc0ErClkFreq(void);
796
797/*!
798 * @brief Get the OSC0 external reference divided clock frequency.
799 *
800 * @return Clock frequency in Hz.
801 */
802uint32_t CLOCK_GetOsc0ErClkDivFreq(void);
803
804/*!
805 * @brief Set the clock configure in SIM module.
806 *
807 * This function sets system layer clock settings in SIM module.
808 *
809 * @param config Pointer to the configure structure.
810 */
811void CLOCK_SetSimConfig(sim_clock_config_t const *config);
812
813/*!
814 * @brief Set the system clock dividers in SIM to safe value.
815 *
816 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
817 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
818 * changes then the system level clocks may be out of range. This function could
819 * be used before MCG mode change, to make sure system level clocks are in allowed
820 * range.
821 *
822 * @param config Pointer to the configure structure.
823 */
824static inline void CLOCK_SetSimSafeDivs(void)
825{
826 SIM->CLKDIV1 = 0x13070000U;
827}
828
829/*! @name MCG frequency functions. */
830/*@{*/
831
832/*!
833 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
834 *
835 * This function gets the MCG output clock frequency in Hz based on the current MCG
836 * register value.
837 *
838 * @return The frequency of MCGOUTCLK.
839 */
840uint32_t CLOCK_GetOutClkFreq(void);
841
842/*!
843 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
844 *
845 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
846 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
847 * disabled in low power state in other modes.
848 *
849 * @return The frequency of MCGFLLCLK.
850 */
851uint32_t CLOCK_GetFllFreq(void);
852
853/*!
854 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
855 *
856 * This function gets the MCG internal reference clock frequency in Hz based
857 * on the current MCG register value.
858 *
859 * @return The frequency of MCGIRCLK.
860 */
861uint32_t CLOCK_GetInternalRefClkFreq(void);
862
863/*!
864 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
865 *
866 * This function gets the MCG fixed frequency clock frequency in Hz based
867 * on the current MCG register value.
868 *
869 * @return The frequency of MCGFFCLK.
870 */
871uint32_t CLOCK_GetFixedFreqClkFreq(void);
872
873/*!
874 * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
875 *
876 * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
877 * register value.
878 *
879 * @return The frequency of MCGPLL0CLK.
880 */
881uint32_t CLOCK_GetPll0Freq(void);
882
883/*@}*/
884
885/*! @name MCG clock configuration. */
886/*@{*/
887
888/*!
889 * @brief Enables or disables the MCG low power.
890 *
891 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
892 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
893 * PBI modes, enabling low power sets the MCG to BLPI mode.
894 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
895 *
896 * @param enable True to enable MCG low power, false to disable MCG low power.
897 */
898static inline void CLOCK_SetLowPowerEnable(bool enable)
899{
900 if (enable)
901 {
902 MCG->C2 |= MCG_C2_LP_MASK;
903 }
904 else
905 {
906 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
907 }
908}
909
910/*!
911 * @brief Configures the Internal Reference clock (MCGIRCLK).
912 *
913 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
914 * source. If the fast IRC is used, this function sets the fast IRC divider.
915 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
916 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
917 * using the function in these modes it is not allowed.
918 *
919 * @param enableMode MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
920 * @param ircs MCGIRCLK clock source, choose fast or slow.
921 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
922 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
923 * the configuration should not be changed. Otherwise, a glitch occurs.
924 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
925 */
926status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
927
928/*!
929 * @brief Selects the MCG external reference clock.
930 *
931 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
932 * and waits for the clock source to be stable. Because the external reference
933 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
934 *
935 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
936 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
937 * the configuration should not be changed. Otherwise, a glitch occurs.
938 * @retval kStatus_Success External reference clock set successfully.
939 */
940status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
941
942/*!
943 * @brief Set the FLL external reference clock divider value.
944 *
945 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
946 *
947 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
948 */
949static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
950{
951 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
952}
953
954/*!
955 * @brief Enables the PLL0 in FLL mode.
956 *
957 * This function sets us the PLL0 in FLL mode and reconfigures
958 * the PLL0. Ensure that the PLL reference
959 * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
960 * The function CLOCK_CalcPllDiv gets the correct PLL
961 * divider values.
962 *
963 * @param config Pointer to the configuration structure.
964 */
965void CLOCK_EnablePll0(mcg_pll_config_t const *config);
966
967/*!
968 * @brief Disables the PLL0 in FLL mode.
969 *
970 * This function disables the PLL0 in FLL mode. It should be used together with the
971 * @ref CLOCK_EnablePll0.
972 */
973static inline void CLOCK_DisablePll0(void)
974{
975 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK));
976}
977
978/*!
979 * @brief Calculates the PLL divider setting for a desired output frequency.
980 *
981 * This function calculates the correct reference clock divider (\c PRDIV) and
982 * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
983 * closest frequency match with the corresponding \c PRDIV/VDIV
984 * returned from parameters. If a desired frequency is not valid, this function
985 * returns 0.
986 *
987 * @param refFreq PLL reference clock frequency.
988 * @param desireFreq Desired PLL output frequency.
989 * @param prdiv PRDIV value to generate desired PLL frequency.
990 * @param vdiv VDIV value to generate desired PLL frequency.
991 * @return Closest frequency match that the PLL was able generate.
992 */
993uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
994
995/*@}*/
996
997/*! @name MCG clock lock monitor functions. */
998/*@{*/
999
1000/*!
1001 * @brief Sets the OSC0 clock monitor mode.
1002 *
1003 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1004 *
1005 * @param mode Monitor mode to set.
1006 */
1007void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
1008
1009/*!
1010 * @brief Sets the RTC OSC clock monitor mode.
1011 *
1012 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
1013 *
1014 * @param mode Monitor mode to set.
1015 */
1016void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
1017
1018/*!
1019 * @brief Sets the PLL0 clock monitor mode.
1020 *
1021 * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1022 *
1023 * @param mode Monitor mode to set.
1024 */
1025void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
1026
1027/*!
1028 * @brief Gets the MCG status flags.
1029 *
1030 * This function gets the MCG clock status flags. All status flags are
1031 * returned as a logical OR of the enumeration refer to _mcg_status_flags_t. To
1032 * check a specific flag, compare the return value with the flag.
1033 *
1034 * Example:
1035 * @code
1036 * To check the clock lost lock status of OSC0 and PLL0.
1037 * uint32_t mcgFlags;
1038 *
1039 * mcgFlags = CLOCK_GetStatusFlags();
1040 *
1041 * if (mcgFlags & kMCG_Osc0LostFlag)
1042 * {
1043 * OSC0 clock lock lost. Do something.
1044 * }
1045 * if (mcgFlags & kMCG_Pll0LostFlag)
1046 * {
1047 * PLL0 clock lock lost. Do something.
1048 * }
1049 * @endcode
1050 *
1051 * @return Logical OR value of the enumeration _mcg_status_flags_t.
1052 */
1053uint32_t CLOCK_GetStatusFlags(void);
1054
1055/*!
1056 * @brief Clears the MCG status flags.
1057 *
1058 * This function clears the MCG clock lock lost status. The parameter is a logical
1059 * OR value of the flags to clear. See the enumeration _mcg_status_flags_t.
1060 *
1061 * Example:
1062 * @code
1063 * To clear the clock lost lock status flags of OSC0 and PLL0.
1064 *
1065 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
1066 * @endcode
1067 *
1068 * @param mask The status flags to clear. This is a logical OR of members of the
1069 * enumeration _mcg_status_flags_t.
1070 */
1071void CLOCK_ClearStatusFlags(uint32_t mask);
1072
1073/*@}*/
1074
1075/*!
1076 * @name OSC configuration
1077 * @{
1078 */
1079
1080/*!
1081 * @brief Configures the OSC external reference clock (OSCERCLK).
1082 *
1083 * This function configures the OSC external reference clock (OSCERCLK).
1084 * This is an example to enable the OSCERCLK in normal and stop modes and also set
1085 * the output divider to 1:
1086 *
1087 @code
1088 oscer_config_t config =
1089 {
1090 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
1091 .erclkDiv = 1U,
1092 };
1093
1094 OSC_SetExtRefClkConfig(OSC, &config);
1095 @endcode
1096 *
1097 * @param base OSC peripheral address.
1098 * @param config Pointer to the configuration structure.
1099 */
1100static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
1101{
1102 uint8_t reg = base->CR;
1103
1104 reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
1105 reg |= config->enableMode;
1106
1107 base->CR = reg;
1108
1109 base->DIV = OSC_DIV_ERPS(config->erclkDiv);
1110}
1111
1112/*!
1113 * @brief Sets the capacitor load configuration for the oscillator.
1114 *
1115 * This function sets the specified capacitors configuration for the oscillator.
1116 * This should be done in the early system level initialization function call
1117 * based on the system configuration.
1118 *
1119 * @param base OSC peripheral address.
1120 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
1121 *
1122 * Example:
1123 @code
1124 To enable only 2 pF and 8 pF capacitor load, please use like this.
1125 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
1126 @endcode
1127 */
1128static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
1129{
1130 uint8_t reg = base->CR;
1131
1132 reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
1133 reg |= capLoad;
1134
1135 base->CR = reg;
1136}
1137
1138/*!
1139 * @brief Initializes the OSC0.
1140 *
1141 * This function initializes the OSC0 according to the board configuration.
1142 *
1143 * @param config Pointer to the OSC0 configuration structure.
1144 */
1145void CLOCK_InitOsc0(osc_config_t const *config);
1146
1147/*!
1148 * @brief Deinitializes the OSC0.
1149 *
1150 * This function deinitializes the OSC0.
1151 */
1152void CLOCK_DeinitOsc0(void);
1153
1154/* @} */
1155
1156/*!
1157 * @name External clock frequency
1158 * @{
1159 */
1160
1161/*!
1162 * @brief Sets the XTAL0 frequency based on board settings.
1163 *
1164 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
1165 */
1166static inline void CLOCK_SetXtal0Freq(uint32_t freq)
1167{
1168 g_xtal0Freq = freq;
1169}
1170
1171/*!
1172 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
1173 *
1174 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
1175 */
1176static inline void CLOCK_SetXtal32Freq(uint32_t freq)
1177{
1178 g_xtal32Freq = freq;
1179}
1180/* @} */
1181
1182/*!
1183 * @name IRCs frequency
1184 * @{
1185 */
1186
1187/*!
1188 * @brief Set the Slow IRC frequency based on the trimmed value
1189 *
1190 * @param freq The Slow IRC frequency input clock frequency in Hz.
1191 */
1192void CLOCK_SetSlowIrcFreq(uint32_t freq);
1193
1194/*!
1195 * @brief Set the Fast IRC frequency based on the trimmed value
1196 *
1197 * @param freq The Fast IRC frequency input clock frequency in Hz.
1198 */
1199void CLOCK_SetFastIrcFreq(uint32_t freq);
1200/* @} */
1201
1202/*!
1203 * @name MCG auto-trim machine.
1204 * @{
1205 */
1206
1207/*!
1208 * @brief Auto trims the internal reference clock.
1209 *
1210 * This function trims the internal reference clock by using the external clock. If
1211 * successful, it returns the kStatus_Success and the frequency after
1212 * trimming is received in the parameter @p actualFreq. If an error occurs,
1213 * the error code is returned.
1214 *
1215 * @param extFreq External clock frequency, which should be a bus clock.
1216 * @param desireFreq Frequency to trim to.
1217 * @param actualFreq Actual frequency after trimming.
1218 * @param atms Trim fast or slow internal reference clock.
1219 * @retval kStatus_Success ATM success.
1220 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
1221 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
1222 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
1223 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
1224 */
1225status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
1226/* @} */
1227
1228/*! @name MCG mode functions. */
1229/*@{*/
1230
1231/*!
1232 * @brief Gets the current MCG mode.
1233 *
1234 * This function checks the MCG registers and determines the current MCG mode.
1235 *
1236 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1237 */
1238mcg_mode_t CLOCK_GetMode(void);
1239
1240/*!
1241 * @brief Sets the MCG to FEI mode.
1242 *
1243 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1244 * from the current mode, this function returns an error.
1245 *
1246 * @param dmx32 DMX32 in FEI mode.
1247 * @param drs The DCO range selection.
1248 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1249 * NULL does not cause a delay.
1250 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1251 * @retval kStatus_Success Switched to the target mode successfully.
1252 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1253 * to a frequency above 32768 Hz.
1254 */
1255status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1256
1257/*!
1258 * @brief Sets the MCG to FEE mode.
1259 *
1260 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1261 * from the current mode, this function returns an error.
1262 *
1263 * @param frdiv FLL reference clock divider setting, FRDIV.
1264 * @param dmx32 DMX32 in FEE mode.
1265 * @param drs The DCO range selection.
1266 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1267 * NULL does not cause a delay.
1268 *
1269 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1270 * @retval kStatus_Success Switched to the target mode successfully.
1271 */
1272status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1273
1274/*!
1275 * @brief Sets the MCG to FBI mode.
1276 *
1277 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1278 * from the current mode, this function returns an error.
1279 *
1280 * @param dmx32 DMX32 in FBI mode.
1281 * @param drs The DCO range selection.
1282 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1283 * is not used in FBI mode, this parameter can be NULL. Passing
1284 * NULL does not cause a delay.
1285 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1286 * @retval kStatus_Success Switched to the target mode successfully.
1287 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1288 * to frequency above 32768 Hz.
1289 */
1290status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1291
1292/*!
1293 * @brief Sets the MCG to FBE mode.
1294 *
1295 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1296 * from the current mode, this function returns an error.
1297 *
1298 * @param frdiv FLL reference clock divider setting, FRDIV.
1299 * @param dmx32 DMX32 in FBE mode.
1300 * @param drs The DCO range selection.
1301 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1302 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1303 * does not cause a delay.
1304 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1305 * @retval kStatus_Success Switched to the target mode successfully.
1306 */
1307status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1308
1309/*!
1310 * @brief Sets the MCG to BLPI mode.
1311 *
1312 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1313 * from the current mode, this function returns an error.
1314 *
1315 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1316 * @retval kStatus_Success Switched to the target mode successfully.
1317 */
1318status_t CLOCK_SetBlpiMode(void);
1319
1320/*!
1321 * @brief Sets the MCG to BLPE mode.
1322 *
1323 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1324 * from the current mode, this function returns an error.
1325 *
1326 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1327 * @retval kStatus_Success Switched to the target mode successfully.
1328 */
1329status_t CLOCK_SetBlpeMode(void);
1330
1331/*!
1332 * @brief Sets the MCG to PBE mode.
1333 *
1334 * This function sets the MCG to PBE mode. If setting to PBE mode fails
1335 * from the current mode, this function returns an error.
1336 *
1337 * @param pllcs The PLL selection, PLLCS.
1338 * @param config Pointer to the PLL configuration.
1339 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1340 * @retval kStatus_Success Switched to the target mode successfully.
1341 *
1342 * @note
1343 * 1. The parameter \c pllcs selects the PLL. For platforms with
1344 * only one PLL, the parameter pllcs is kept for interface compatibility.
1345 * 2. The parameter \c config is the PLL configuration structure. On some
1346 * platforms, it is possible to choose the external PLL directly, which renders the
1347 * configuration structure not necessary. In this case, pass in NULL.
1348 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
1349 */
1350status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1351
1352/*!
1353 * @brief Sets the MCG to PEE mode.
1354 *
1355 * This function sets the MCG to PEE mode.
1356 *
1357 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1358 * @retval kStatus_Success Switched to the target mode successfully.
1359 *
1360 * @note This function only changes the CLKS to use the PLL/FLL output. If the
1361 * PRDIV/VDIV are different than in the PBE mode, set them up
1362 * in PBE mode and wait. When the clock is stable, switch to PEE mode.
1363 */
1364status_t CLOCK_SetPeeMode(void);
1365
1366/*!
1367 * @brief Switches the MCG to FBE mode from the external mode.
1368 *
1369 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1370 * The external clock is used as the system clock source and PLL is disabled. However,
1371 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1372 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1373 *
1374 * @code
1375 * CLOCK_ExternalModeToFbeModeQuick();
1376 * CLOCK_SetFeiMode(...);
1377 * @endcode
1378 *
1379 * @retval kStatus_Success Switched successfully.
1380 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1381 */
1382status_t CLOCK_ExternalModeToFbeModeQuick(void);
1383
1384/*!
1385 * @brief Switches the MCG to FBI mode from internal modes.
1386 *
1387 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1388 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1389 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1390 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1391 *
1392 * @code
1393 * CLOCK_InternalModeToFbiModeQuick();
1394 * CLOCK_SetFeeMode(...);
1395 * @endcode
1396 *
1397 * @retval kStatus_Success Switched successfully.
1398 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1399 */
1400status_t CLOCK_InternalModeToFbiModeQuick(void);
1401
1402/*!
1403 * @brief Sets the MCG to FEI mode during system boot up.
1404 *
1405 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1406 * set up MCG during system boot up.
1407 *
1408 * @param dmx32 DMX32 in FEI mode.
1409 * @param drs The DCO range selection.
1410 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1411 *
1412 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1413 * @retval kStatus_Success Switched to the target mode successfully.
1414 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1415 * to frequency above 32768 Hz.
1416 */
1417status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1418
1419/*!
1420 * @brief Sets the MCG to FEE mode during system bootup.
1421 *
1422 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1423 * set up the MCG during system boot up.
1424 *
1425 * @param oscsel OSC clock select, OSCSEL.
1426 * @param frdiv FLL reference clock divider setting, FRDIV.
1427 * @param dmx32 DMX32 in FEE mode.
1428 * @param drs The DCO range selection.
1429 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1430 *
1431 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1432 * @retval kStatus_Success Switched to the target mode successfully.
1433 */
1434status_t CLOCK_BootToFeeMode(
1435 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1436
1437/*!
1438 * @brief Sets the MCG to BLPI mode during system boot up.
1439 *
1440 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1441 * set up the MCG during system boot up.
1442 *
1443 * @param fcrdiv Fast IRC divider, FCRDIV.
1444 * @param ircs The internal reference clock to select, IRCS.
1445 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
1446 *
1447 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1448 * @retval kStatus_Success Switched to the target mode successfully.
1449 */
1450status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1451
1452/*!
1453 * @brief Sets the MCG to BLPE mode during system boot up.
1454 *
1455 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1456 * set up the MCG during system boot up.
1457 *
1458 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1459 *
1460 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1461 * @retval kStatus_Success Switched to the target mode successfully.
1462 */
1463status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1464
1465/*!
1466 * @brief Sets the MCG to PEE mode during system boot up.
1467 *
1468 * This function sets the MCG to PEE mode from reset mode. It can also be used to
1469 * set up the MCG during system boot up.
1470 *
1471 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1472 * @param pllcs The PLL selection, PLLCS.
1473 * @param config Pointer to the PLL configuration.
1474 *
1475 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1476 * @retval kStatus_Success Switched to the target mode successfully.
1477 */
1478status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1479
1480/*!
1481 * @brief Sets the MCG to a target mode.
1482 *
1483 * This function sets MCG to a target mode defined by the configuration
1484 * structure. If switching to the target mode fails, this function
1485 * chooses the correct path.
1486 *
1487 * @param config Pointer to the target MCG mode configuration structure.
1488 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code _mcg_status.
1489 *
1490 * @note If the external clock is used in the target mode, ensure that it is
1491 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1492 * function.
1493 */
1494status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1495
1496/*@}*/
1497
1498#if defined(__cplusplus)
1499}
1500#endif /* __cplusplus */
1501
1502/*! @} */
1503
1504#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 05:24:47 +0100