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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK22F51212/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MK22F51212/drivers/fsl_clock.h
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1/*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_CLOCK_H_
10#define _FSL_CLOCK_H_
11
12#include "fsl_common.h"
13
14/*! @addtogroup clock */
15/*! @{ */
16
17/*! @file */
18
19/*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23/*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37#ifndef MCG_CONFIG_CHECK_PARAM
38#define MCG_CONFIG_CHECK_PARAM 0U
39#endif
40
41/*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53#endif
54
55/*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59/*! @name Driver version */
60/*@{*/
61/*! @brief CLOCK driver version 2.5.1. */
62#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
63/*@}*/
64
65/*! @brief External XTAL0 (OSC0) clock frequency.
66 *
67 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
68 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
69 * if XTAL0 is 8 MHz:
70 * @code
71 * Set up the OSC0
72 * CLOCK_InitOsc0(...);
73 * Set the XTAL0 value to the clock driver.
74 * CLOCK_SetXtal0Freq(80000000);
75 * @endcode
76 *
77 * This is important for the multicore platforms where only one core needs to set up the
78 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
79 * to get a valid clock frequency.
80 */
81extern volatile uint32_t g_xtal0Freq;
82
83/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
84 *
85 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
86 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
87 *
88 * This is important for the multicore platforms where only one core needs to set up
89 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
90 * to get a valid clock frequency.
91 */
92extern volatile uint32_t g_xtal32Freq;
93
94/*! @brief IRC48M clock frequency in Hz. */
95#define MCG_INTERNAL_IRC_48M 48000000U
96
97#if (defined(OSC) && !(defined(OSC0)))
98#define OSC0 OSC
99#endif
100
101/* Definition for delay API in clock driver, users can redefine it to the real application. */
102#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
103#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (120000000UL)
104#endif
105
106/*! @brief Clock ip name array for DMAMUX. */
107#define DMAMUX_CLOCKS \
108 { \
109 kCLOCK_Dmamux0 \
110 }
111
112/*! @brief Clock ip name array for RTC. */
113#define RTC_CLOCKS \
114 { \
115 kCLOCK_Rtc0 \
116 }
117
118/*! @brief Clock ip name array for SAI. */
119#define SAI_CLOCKS \
120 { \
121 kCLOCK_Sai0 \
122 }
123
124/*! @brief Clock ip name array for PORT. */
125#define PORT_CLOCKS \
126 { \
127 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
128 }
129
130/*! @brief Clock ip name array for FLEXBUS. */
131#define FLEXBUS_CLOCKS \
132 { \
133 kCLOCK_Flexbus0 \
134 }
135
136/*! @brief Clock ip name array for EWM. */
137#define EWM_CLOCKS \
138 { \
139 kCLOCK_Ewm0 \
140 }
141
142/*! @brief Clock ip name array for PIT. */
143#define PIT_CLOCKS \
144 { \
145 kCLOCK_Pit0 \
146 }
147
148/*! @brief Clock ip name array for DSPI. */
149#define DSPI_CLOCKS \
150 { \
151 kCLOCK_Spi0, kCLOCK_Spi1 \
152 }
153
154/*! @brief Clock ip name array for LPTMR. */
155#define LPTMR_CLOCKS \
156 { \
157 kCLOCK_Lptmr0 \
158 }
159
160/*! @brief Clock ip name array for FTM. */
161#define FTM_CLOCKS \
162 { \
163 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
164 }
165
166/*! @brief Clock ip name array for EDMA. */
167#define EDMA_CLOCKS \
168 { \
169 kCLOCK_Dma0 \
170 }
171
172/*! @brief Clock ip name array for LPUART. */
173#define LPUART_CLOCKS \
174 { \
175 kCLOCK_Lpuart0 \
176 }
177
178/*! @brief Clock ip name array for DAC. */
179#define DAC_CLOCKS \
180 { \
181 kCLOCK_Dac0, kCLOCK_Dac1 \
182 }
183
184/*! @brief Clock ip name array for ADC16. */
185#define ADC16_CLOCKS \
186 { \
187 kCLOCK_Adc0, kCLOCK_Adc1 \
188 }
189
190/*! @brief Clock ip name array for VREF. */
191#define VREF_CLOCKS \
192 { \
193 kCLOCK_Vref0 \
194 }
195
196/*! @brief Clock ip name array for UART. */
197#define UART_CLOCKS \
198 { \
199 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2 \
200 }
201
202/*! @brief Clock ip name array for RNGA. */
203#define RNGA_CLOCKS \
204 { \
205 kCLOCK_Rnga0 \
206 }
207
208/*! @brief Clock ip name array for CRC. */
209#define CRC_CLOCKS \
210 { \
211 kCLOCK_Crc0 \
212 }
213
214/*! @brief Clock ip name array for I2C. */
215#define I2C_CLOCKS \
216 { \
217 kCLOCK_I2c0, kCLOCK_I2c1 \
218 }
219
220/*! @brief Clock ip name array for FTF. */
221#define FTF_CLOCKS \
222 { \
223 kCLOCK_Ftf0 \
224 }
225
226/*! @brief Clock ip name array for PDB. */
227#define PDB_CLOCKS \
228 { \
229 kCLOCK_Pdb0 \
230 }
231
232/*! @brief Clock ip name array for CMP. */
233#define CMP_CLOCKS \
234 { \
235 kCLOCK_Cmp0, kCLOCK_Cmp1 \
236 }
237
238/*!
239 * @brief LPO clock frequency.
240 */
241#define LPO_CLK_FREQ 1000U
242
243/*! @brief Peripherals clock source definition. */
244#define SYS_CLK kCLOCK_CoreSysClk
245#define BUS_CLK kCLOCK_BusClk
246#define FAST_CLK kCLOCK_FastPeriphClk
247
248#define I2C0_CLK_SRC BUS_CLK
249#define I2C1_CLK_SRC BUS_CLK
250#define DSPI0_CLK_SRC BUS_CLK
251#define DSPI1_CLK_SRC BUS_CLK
252#define UART0_CLK_SRC SYS_CLK
253#define UART1_CLK_SRC SYS_CLK
254#define UART2_CLK_SRC BUS_CLK
255
256/*! @brief Clock name used to get clock frequency. */
257typedef enum _clock_name
258{
259
260 /* ----------------------------- System layer clock -------------------------------*/
261 kCLOCK_CoreSysClk, /*!< Core/system clock */
262 kCLOCK_PlatClk, /*!< Platform clock */
263 kCLOCK_BusClk, /*!< Bus clock */
264 kCLOCK_FlexBusClk, /*!< FlexBus clock */
265 kCLOCK_FlashClk, /*!< Flash clock */
266 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
267 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
268
269 /* ---------------------------------- OSC clock -----------------------------------*/
270 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
271 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
272 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
273 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
274
275 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
276 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
277 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
278 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
279 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
280 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
281 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
282 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
283 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
284
285 /* --------------------------------- Other clock ----------------------------------*/
286 kCLOCK_LpoClk, /*!< LPO clock */
287
288} clock_name_t;
289
290/*! @brief USB clock source definition. */
291typedef enum _clock_usb_src
292{
293 kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */
294 kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */
295 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U) /*!< Use USB_CLKIN. */
296} clock_usb_src_t;
297/*------------------------------------------------------------------------------
298
299 clock_gate_t definition:
300
301 31 16 0
302 -----------------------------------------------------------------
303 | SIM_SCGC register offset | control bit offset in SCGC |
304 -----------------------------------------------------------------
305
306 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
307 SIM_SCGC3 offset in SIM is 0x1030, then kCLOCK_GateSdhc0 is defined as
308
309 kCLOCK_GateSdhc0 = (0x1030 << 16) | 17;
310
311------------------------------------------------------------------------------*/
312
313#define CLK_GATE_REG_OFFSET_SHIFT 16U
314#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
315#define CLK_GATE_BIT_SHIFT_SHIFT 0U
316#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
317
318#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
319 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
320 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
321
322#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
323#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
324
325/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
326typedef enum _clock_ip_name
327{
328 kCLOCK_IpInvalid = 0U,
329
330 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
331 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
332 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
333 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
334 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
335 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
336 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
337 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
338 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
339 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
340
341 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
342 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
343 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
344 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
345 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
346 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
347
348 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
349 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
350 kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x103CU, 6U),
351 kCLOCK_Adc1 = CLK_GATE_DEFINE(0x103CU, 7U),
352 kCLOCK_Dac1 = CLK_GATE_DEFINE(0x103CU, 8U),
353 kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x103CU, 9U),
354 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x103CU, 10U),
355 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
356 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
357 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
358 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
359 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
360 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
361 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
362 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
363 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
364 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
365 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
366 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
367
368 kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
369 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
370} clock_ip_name_t;
371
372/*!@brief SIM configuration structure for clock setting. */
373typedef struct _sim_clock_config
374{
375 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
376 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
377 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
378} sim_clock_config_t;
379
380/*! @brief OSC work mode. */
381typedef enum _osc_mode
382{
383 kOSC_ModeExt = 0U, /*!< Use an external clock. */
384#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
385 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
386#else
387 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
388#endif
389 kOSC_ModeOscHighGain = 0U
390#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
391 | MCG_C2_EREFS_MASK
392#else
393 | MCG_C2_EREFS0_MASK
394#endif
395#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
396 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
397#else
398 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
399#endif
400} osc_mode_t;
401
402/*! @brief Oscillator capacitor load setting.*/
403enum _osc_cap_load
404{
405 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
406 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
407 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
408 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
409};
410
411/*! @brief OSCERCLK enable mode. */
412enum _oscer_enable_mode
413{
414 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
415 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
416};
417
418/*! @brief OSC configuration for OSCERCLK. */
419typedef struct _oscer_config
420{
421 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
422
423 uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/
424} oscer_config_t;
425
426/*!
427 * @brief OSC Initialization Configuration Structure
428 *
429 * Defines the configuration data structure to initialize the OSC.
430 * When porting to a new board, set the following members
431 * according to the board setting:
432 * 1. freq: The external frequency.
433 * 2. workMode: The OSC module mode.
434 */
435typedef struct _osc_config
436{
437 uint32_t freq; /*!< External clock frequency. */
438 uint8_t capLoad; /*!< Capacitor load setting. */
439 osc_mode_t workMode; /*!< OSC work mode setting. */
440 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
441} osc_config_t;
442
443/*! @brief MCG FLL reference clock source select. */
444typedef enum _mcg_fll_src
445{
446 kMCG_FllSrcExternal, /*!< External reference clock is selected */
447 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
448} mcg_fll_src_t;
449
450/*! @brief MCG internal reference clock select */
451typedef enum _mcg_irc_mode
452{
453 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
454 kMCG_IrcFast /*!< Fast internal reference clock selected */
455} mcg_irc_mode_t;
456
457/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
458typedef enum _mcg_dmx32
459{
460 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
461 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
462} mcg_dmx32_t;
463
464/*! @brief MCG DCO range select */
465typedef enum _mcg_drs
466{
467 kMCG_DrsLow, /*!< Low frequency range */
468 kMCG_DrsMid, /*!< Mid frequency range */
469 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
470 kMCG_DrsHigh /*!< High frequency range */
471} mcg_drs_t;
472
473/*! @brief MCG PLL reference clock select */
474typedef enum _mcg_pll_ref_src
475{
476 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
477 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
478} mcg_pll_ref_src_t;
479
480/*! @brief MCGOUT clock source. */
481typedef enum _mcg_clkout_src
482{
483 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
484 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
485 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
486} mcg_clkout_src_t;
487
488/*! @brief MCG Automatic Trim Machine Select */
489typedef enum _mcg_atm_select
490{
491 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
492 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
493} mcg_atm_select_t;
494
495/*! @brief MCG OSC Clock Select */
496typedef enum _mcg_oscsel
497{
498 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
499 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
500 kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */
501} mcg_oscsel_t;
502
503/*! @brief MCG PLLCS select */
504typedef enum _mcg_pll_clk_select
505{
506 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
507 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
508} mcg_pll_clk_select_t;
509
510/*! @brief MCG clock monitor mode. */
511typedef enum _mcg_monitor_mode
512{
513 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
514 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
515 kMCG_MonitorReset /*!< System reset when clock lost. */
516} mcg_monitor_mode_t;
517
518/*! @brief MCG status. Enumeration _mcg_status */
519enum
520{
521 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), /*!< Can't switch to target mode. */
522 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), /*!< Current mode invalid for the specific
523 function. */
524 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), /*!< Invalid bus clock for ATM. */
525 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), /*!< Invalid desired frequency for ATM. */
526 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), /*!< IRC is used when using ATM. */
527 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), /*!< Hardware fail occurs during ATM. */
528 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) /*!< Can't change the clock source because
529 it is in use. */
530};
531
532/*! @brief MCG status flags. Enumeration _mcg_status_flags_t */
533enum
534{
535 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
536 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
537 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
538 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
539 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
540};
541
542/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. Enumeration _mcg_irclk_enable_mode */
543enum
544{
545 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
546 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
547};
548
549/*! @brief MCG PLL clock enable mode definition. Enumeration _mcg_pll_enable_mode */
550enum
551{
552 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
553 MCG clock mode. Generally, the PLL
554 is disabled in FLL modes
555 (FEI/FBI/FEE/FBE). Setting the PLL clock
556 enable independent, enables the
557 PLL in the FLL modes. */
558 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
559};
560
561/*! @brief MCG mode definitions */
562typedef enum _mcg_mode
563{
564 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
565 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
566 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
567 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
568 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
569 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
570 kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
571 kMCG_ModePEE, /*!< PEE - PLL Engaged External */
572 kMCG_ModeError /*!< Unknown mode */
573} mcg_mode_t;
574
575/*! @brief MCG PLL configuration. */
576typedef struct _mcg_pll_config
577{
578 uint8_t enableMode; /*!< Enable mode. OR'ed value of enumeration _mcg_pll_enable_mode. */
579 uint8_t prdiv; /*!< Reference divider PRDIV. */
580 uint8_t vdiv; /*!< VCO divider VDIV. */
581} mcg_pll_config_t;
582
583/*! @brief MCG mode change configuration structure
584 *
585 * When porting to a new board, set the following members
586 * according to the board setting:
587 * 1. frdiv: If the FLL uses the external reference clock, set this
588 * value to ensure that the external reference clock divided by frdiv is
589 * in the 31.25 kHz to 39.0625 kHz range.
590 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
591 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
592 * FSL_FEATURE_MCG_PLL_REF_MAX range.
593 */
594typedef struct _mcg_config
595{
596 mcg_mode_t mcgMode; /*!< MCG mode. */
597
598 /* ----------------------- MCGIRCCLK settings ------------------------ */
599 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
600 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
601 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
602
603 /* ------------------------ MCG FLL settings ------------------------- */
604 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
605 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
606 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
607 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
608
609 /* ------------------------ MCG PLL settings ------------------------- */
610 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
611
612} mcg_config_t;
613
614/*******************************************************************************
615 * API
616 ******************************************************************************/
617
618#if defined(__cplusplus)
619extern "C" {
620#endif /* __cplusplus */
621
622/*!
623 * @brief Enable the clock for specific IP.
624 *
625 * @param name Which clock to enable, see \ref clock_ip_name_t.
626 */
627static inline void CLOCK_EnableClock(clock_ip_name_t name)
628{
629 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
630 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
631}
632
633/*!
634 * @brief Disable the clock for specific IP.
635 *
636 * @param name Which clock to disable, see \ref clock_ip_name_t.
637 */
638static inline void CLOCK_DisableClock(clock_ip_name_t name)
639{
640 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
641 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
642}
643
644/*!
645 * @brief Set LPUART clock source.
646 *
647 * @param src The value to set LPUART clock source.
648 */
649static inline void CLOCK_SetLpuartClock(uint32_t src)
650{
651 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) | SIM_SOPT2_LPUARTSRC(src));
652}
653
654/*!
655 * @brief Set ERCLK32K source.
656 *
657 * @param src The value to set ERCLK32K clock source.
658 */
659static inline void CLOCK_SetEr32kClock(uint32_t src)
660{
661 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
662}
663
664/*!
665 * @brief Set debug trace clock source.
666 *
667 * @param src The value to set debug trace clock source.
668 */
669static inline void CLOCK_SetTraceClock(uint32_t src)
670{
671 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
672}
673
674/*!
675 * @brief Set PLLFLLSEL clock source.
676 *
677 * @param src The value to set PLLFLLSEL clock source.
678 */
679static inline void CLOCK_SetPllFllSelClock(uint32_t src)
680{
681 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
682}
683
684/*!
685 * @brief Set CLKOUT source.
686 *
687 * @param src The value to set CLKOUT source.
688 */
689static inline void CLOCK_SetClkOutClock(uint32_t src)
690{
691 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
692}
693
694/*!
695 * @brief Set RTC_CLKOUT source.
696 *
697 * @param src The value to set RTC_CLKOUT source.
698 */
699static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
700{
701 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
702}
703
704/*! @brief Enable USB FS clock.
705 *
706 * @param src USB FS clock source.
707 * @param freq The frequency specified by src.
708 * @retval true The clock is set successfully.
709 * @retval false The clock source is invalid to get proper USB FS clock.
710 */
711bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
712
713/*! @brief Disable USB FS clock.
714 *
715 * Disable USB FS clock.
716 */
717static inline void CLOCK_DisableUsbfs0Clock(void)
718{
719 CLOCK_DisableClock(kCLOCK_Usbfs0);
720}
721
722/*!
723 * @brief System clock divider
724 *
725 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
726 *
727 * @param outdiv1 Clock 1 output divider value.
728 *
729 * @param outdiv2 Clock 2 output divider value.
730 *
731 * @param outdiv3 Clock 3 output divider value.
732 *
733 * @param outdiv4 Clock 4 output divider value.
734 */
735static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
736{
737 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) |
738 SIM_CLKDIV1_OUTDIV4(outdiv4);
739}
740
741/*!
742 * @brief Gets the clock frequency for a specific clock name.
743 *
744 * This function checks the current clock configurations and then calculates
745 * the clock frequency for a specific clock name defined in clock_name_t.
746 * The MCG must be properly configured before using this function.
747 *
748 * @param clockName Clock names defined in clock_name_t
749 * @return Clock frequency value in Hertz
750 */
751uint32_t CLOCK_GetFreq(clock_name_t clockName);
752
753/*!
754 * @brief Get the core clock or system clock frequency.
755 *
756 * @return Clock frequency in Hz.
757 */
758uint32_t CLOCK_GetCoreSysClkFreq(void);
759
760/*!
761 * @brief Get the platform clock frequency.
762 *
763 * @return Clock frequency in Hz.
764 */
765uint32_t CLOCK_GetPlatClkFreq(void);
766
767/*!
768 * @brief Get the bus clock frequency.
769 *
770 * @return Clock frequency in Hz.
771 */
772uint32_t CLOCK_GetBusClkFreq(void);
773
774/*!
775 * @brief Get the flexbus clock frequency.
776 *
777 * @return Clock frequency in Hz.
778 */
779uint32_t CLOCK_GetFlexBusClkFreq(void);
780
781/*!
782 * @brief Get the flash clock frequency.
783 *
784 * @return Clock frequency in Hz.
785 */
786uint32_t CLOCK_GetFlashClkFreq(void);
787
788/*!
789 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
790 *
791 * @return Clock frequency in Hz.
792 */
793uint32_t CLOCK_GetPllFllSelClkFreq(void);
794
795/*!
796 * @brief Get the external reference 32K clock frequency (ERCLK32K).
797 *
798 * @return Clock frequency in Hz.
799 */
800uint32_t CLOCK_GetEr32kClkFreq(void);
801
802/*!
803 * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV).
804 *
805 * @return Clock frequency in Hz.
806 */
807uint32_t CLOCK_GetOsc0ErClkUndivFreq(void);
808
809/*!
810 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
811 *
812 * @return Clock frequency in Hz.
813 */
814uint32_t CLOCK_GetOsc0ErClkFreq(void);
815
816/*!
817 * @brief Get the OSC0 external reference divided clock frequency.
818 *
819 * @return Clock frequency in Hz.
820 */
821uint32_t CLOCK_GetOsc0ErClkDivFreq(void);
822
823/*!
824 * @brief Set the clock configure in SIM module.
825 *
826 * This function sets system layer clock settings in SIM module.
827 *
828 * @param config Pointer to the configure structure.
829 */
830void CLOCK_SetSimConfig(sim_clock_config_t const *config);
831
832/*!
833 * @brief Set the system clock dividers in SIM to safe value.
834 *
835 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
836 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
837 * changes then the system level clocks may be out of range. This function could
838 * be used before MCG mode change, to make sure system level clocks are in allowed
839 * range.
840 *
841 */
842static inline void CLOCK_SetSimSafeDivs(void)
843{
844 SIM->CLKDIV1 = 0x01230000U;
845}
846
847/*! @name MCG frequency functions. */
848/*@{*/
849
850/*!
851 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
852 *
853 * This function gets the MCG output clock frequency in Hz based on the current MCG
854 * register value.
855 *
856 * @return The frequency of MCGOUTCLK.
857 */
858uint32_t CLOCK_GetOutClkFreq(void);
859
860/*!
861 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
862 *
863 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
864 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
865 * disabled in low power state in other modes.
866 *
867 * @return The frequency of MCGFLLCLK.
868 */
869uint32_t CLOCK_GetFllFreq(void);
870
871/*!
872 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
873 *
874 * This function gets the MCG internal reference clock frequency in Hz based
875 * on the current MCG register value.
876 *
877 * @return The frequency of MCGIRCLK.
878 */
879uint32_t CLOCK_GetInternalRefClkFreq(void);
880
881/*!
882 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
883 *
884 * This function gets the MCG fixed frequency clock frequency in Hz based
885 * on the current MCG register value.
886 *
887 * @return The frequency of MCGFFCLK.
888 */
889uint32_t CLOCK_GetFixedFreqClkFreq(void);
890
891/*!
892 * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
893 *
894 * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
895 * register value.
896 *
897 * @return The frequency of MCGPLL0CLK.
898 */
899uint32_t CLOCK_GetPll0Freq(void);
900
901/*@}*/
902
903/*! @name MCG clock configuration. */
904/*@{*/
905
906/*!
907 * @brief Enables or disables the MCG low power.
908 *
909 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
910 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
911 * PBI modes, enabling low power sets the MCG to BLPI mode.
912 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
913 *
914 * @param enable True to enable MCG low power, false to disable MCG low power.
915 */
916static inline void CLOCK_SetLowPowerEnable(bool enable)
917{
918 if (enable)
919 {
920 MCG->C2 |= MCG_C2_LP_MASK;
921 }
922 else
923 {
924 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
925 }
926}
927
928/*!
929 * @brief Configures the Internal Reference clock (MCGIRCLK).
930 *
931 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
932 * source. If the fast IRC is used, this function sets the fast IRC divider.
933 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
934 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
935 * using the function in these modes it is not allowed.
936 *
937 * @param enableMode MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
938 * @param ircs MCGIRCLK clock source, choose fast or slow.
939 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
940 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
941 * the configuration should not be changed. Otherwise, a glitch occurs.
942 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
943 */
944status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
945
946/*!
947 * @brief Selects the MCG external reference clock.
948 *
949 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
950 * and waits for the clock source to be stable. Because the external reference
951 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
952 *
953 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
954 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
955 * the configuration should not be changed. Otherwise, a glitch occurs.
956 * @retval kStatus_Success External reference clock set successfully.
957 */
958status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
959
960/*!
961 * @brief Set the FLL external reference clock divider value.
962 *
963 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
964 *
965 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
966 */
967static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
968{
969 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
970}
971
972/*!
973 * @brief Enables the PLL0 in FLL mode.
974 *
975 * This function sets us the PLL0 in FLL mode and reconfigures
976 * the PLL0. Ensure that the PLL reference
977 * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
978 * The function CLOCK_CalcPllDiv gets the correct PLL
979 * divider values.
980 *
981 * @param config Pointer to the configuration structure.
982 */
983void CLOCK_EnablePll0(mcg_pll_config_t const *config);
984
985/*!
986 * @brief Disables the PLL0 in FLL mode.
987 *
988 * This function disables the PLL0 in FLL mode. It should be used together with the
989 * @ref CLOCK_EnablePll0.
990 */
991static inline void CLOCK_DisablePll0(void)
992{
993 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK));
994}
995
996/*!
997 * @brief Calculates the PLL divider setting for a desired output frequency.
998 *
999 * This function calculates the correct reference clock divider (\c PRDIV) and
1000 * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
1001 * closest frequency match with the corresponding \c PRDIV/VDIV
1002 * returned from parameters. If a desired frequency is not valid, this function
1003 * returns 0.
1004 *
1005 * @param refFreq PLL reference clock frequency.
1006 * @param desireFreq Desired PLL output frequency.
1007 * @param prdiv PRDIV value to generate desired PLL frequency.
1008 * @param vdiv VDIV value to generate desired PLL frequency.
1009 * @return Closest frequency match that the PLL was able generate.
1010 */
1011uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
1012
1013/*@}*/
1014
1015/*! @name MCG clock lock monitor functions. */
1016/*@{*/
1017
1018/*!
1019 * @brief Sets the OSC0 clock monitor mode.
1020 *
1021 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1022 *
1023 * @param mode Monitor mode to set.
1024 */
1025void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
1026
1027/*!
1028 * @brief Sets the RTC OSC clock monitor mode.
1029 *
1030 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
1031 *
1032 * @param mode Monitor mode to set.
1033 */
1034void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
1035
1036/*!
1037 * @brief Sets the PLL0 clock monitor mode.
1038 *
1039 * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1040 *
1041 * @param mode Monitor mode to set.
1042 */
1043void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
1044
1045/*!
1046 * @brief Gets the MCG status flags.
1047 *
1048 * This function gets the MCG clock status flags. All status flags are
1049 * returned as a logical OR of the enumeration refer to _mcg_status_flags_t. To
1050 * check a specific flag, compare the return value with the flag.
1051 *
1052 * Example:
1053 * @code
1054 * To check the clock lost lock status of OSC0 and PLL0.
1055 * uint32_t mcgFlags;
1056 *
1057 * mcgFlags = CLOCK_GetStatusFlags();
1058 *
1059 * if (mcgFlags & kMCG_Osc0LostFlag)
1060 * {
1061 * OSC0 clock lock lost. Do something.
1062 * }
1063 * if (mcgFlags & kMCG_Pll0LostFlag)
1064 * {
1065 * PLL0 clock lock lost. Do something.
1066 * }
1067 * @endcode
1068 *
1069 * @return Logical OR value of the enumeration _mcg_status_flags_t.
1070 */
1071uint32_t CLOCK_GetStatusFlags(void);
1072
1073/*!
1074 * @brief Clears the MCG status flags.
1075 *
1076 * This function clears the MCG clock lock lost status. The parameter is a logical
1077 * OR value of the flags to clear. See the enumeration _mcg_status_flags_t.
1078 *
1079 * Example:
1080 * @code
1081 * To clear the clock lost lock status flags of OSC0 and PLL0.
1082 *
1083 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
1084 * @endcode
1085 *
1086 * @param mask The status flags to clear. This is a logical OR of members of the
1087 * enumeration _mcg_status_flags_t.
1088 */
1089void CLOCK_ClearStatusFlags(uint32_t mask);
1090
1091/*@}*/
1092
1093/*!
1094 * @name OSC configuration
1095 * @{
1096 */
1097
1098/*!
1099 * @brief Configures the OSC external reference clock (OSCERCLK).
1100 *
1101 * This function configures the OSC external reference clock (OSCERCLK).
1102 * This is an example to enable the OSCERCLK in normal and stop modes and also set
1103 * the output divider to 1:
1104 *
1105 @code
1106 oscer_config_t config =
1107 {
1108 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
1109 .erclkDiv = 1U,
1110 };
1111
1112 OSC_SetExtRefClkConfig(OSC, &config);
1113 @endcode
1114 *
1115 * @param base OSC peripheral address.
1116 * @param config Pointer to the configuration structure.
1117 */
1118static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
1119{
1120 uint8_t reg = base->CR;
1121
1122 reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
1123 reg |= config->enableMode;
1124
1125 base->CR = reg;
1126
1127 base->DIV = OSC_DIV_ERPS(config->erclkDiv);
1128}
1129
1130/*!
1131 * @brief Sets the capacitor load configuration for the oscillator.
1132 *
1133 * This function sets the specified capacitors configuration for the oscillator.
1134 * This should be done in the early system level initialization function call
1135 * based on the system configuration.
1136 *
1137 * @param base OSC peripheral address.
1138 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
1139 *
1140 * Example:
1141 @code
1142 To enable only 2 pF and 8 pF capacitor load, please use like this.
1143 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
1144 @endcode
1145 */
1146static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
1147{
1148 uint8_t reg = base->CR;
1149
1150 reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
1151 reg |= capLoad;
1152
1153 base->CR = reg;
1154}
1155
1156/*!
1157 * @brief Initializes the OSC0.
1158 *
1159 * This function initializes the OSC0 according to the board configuration.
1160 *
1161 * @param config Pointer to the OSC0 configuration structure.
1162 */
1163void CLOCK_InitOsc0(osc_config_t const *config);
1164
1165/*!
1166 * @brief Deinitializes the OSC0.
1167 *
1168 * This function deinitializes the OSC0.
1169 */
1170void CLOCK_DeinitOsc0(void);
1171
1172/* @} */
1173
1174/*!
1175 * @name External clock frequency
1176 * @{
1177 */
1178
1179/*!
1180 * @brief Sets the XTAL0 frequency based on board settings.
1181 *
1182 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
1183 */
1184static inline void CLOCK_SetXtal0Freq(uint32_t freq)
1185{
1186 g_xtal0Freq = freq;
1187}
1188
1189/*!
1190 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
1191 *
1192 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
1193 */
1194static inline void CLOCK_SetXtal32Freq(uint32_t freq)
1195{
1196 g_xtal32Freq = freq;
1197}
1198/* @} */
1199
1200/*!
1201 * @name IRCs frequency
1202 * @{
1203 */
1204
1205/*!
1206 * @brief Set the Slow IRC frequency based on the trimmed value
1207 *
1208 * @param freq The Slow IRC frequency input clock frequency in Hz.
1209 */
1210void CLOCK_SetSlowIrcFreq(uint32_t freq);
1211
1212/*!
1213 * @brief Set the Fast IRC frequency based on the trimmed value
1214 *
1215 * @param freq The Fast IRC frequency input clock frequency in Hz.
1216 */
1217void CLOCK_SetFastIrcFreq(uint32_t freq);
1218/* @} */
1219
1220/*!
1221 * @name MCG auto-trim machine.
1222 * @{
1223 */
1224
1225/*!
1226 * @brief Auto trims the internal reference clock.
1227 *
1228 * This function trims the internal reference clock by using the external clock. If
1229 * successful, it returns the kStatus_Success and the frequency after
1230 * trimming is received in the parameter @p actualFreq. If an error occurs,
1231 * the error code is returned.
1232 *
1233 * @param extFreq External clock frequency, which should be a bus clock.
1234 * @param desireFreq Frequency to trim to.
1235 * @param actualFreq Actual frequency after trimming.
1236 * @param atms Trim fast or slow internal reference clock.
1237 * @retval kStatus_Success ATM success.
1238 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
1239 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
1240 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
1241 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
1242 */
1243status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
1244/* @} */
1245
1246/*! @name MCG mode functions. */
1247/*@{*/
1248
1249/*!
1250 * @brief Gets the current MCG mode.
1251 *
1252 * This function checks the MCG registers and determines the current MCG mode.
1253 *
1254 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1255 */
1256mcg_mode_t CLOCK_GetMode(void);
1257
1258/*!
1259 * @brief Sets the MCG to FEI mode.
1260 *
1261 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1262 * from the current mode, this function returns an error.
1263 *
1264 * @param dmx32 DMX32 in FEI mode.
1265 * @param drs The DCO range selection.
1266 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1267 * NULL does not cause a delay.
1268 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1269 * @retval kStatus_Success Switched to the target mode successfully.
1270 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1271 * to a frequency above 32768 Hz.
1272 */
1273status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1274
1275/*!
1276 * @brief Sets the MCG to FEE mode.
1277 *
1278 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1279 * from the current mode, this function returns an error.
1280 *
1281 * @param frdiv FLL reference clock divider setting, FRDIV.
1282 * @param dmx32 DMX32 in FEE mode.
1283 * @param drs The DCO range selection.
1284 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1285 * NULL does not cause a delay.
1286 *
1287 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1288 * @retval kStatus_Success Switched to the target mode successfully.
1289 */
1290status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1291
1292/*!
1293 * @brief Sets the MCG to FBI mode.
1294 *
1295 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1296 * from the current mode, this function returns an error.
1297 *
1298 * @param dmx32 DMX32 in FBI mode.
1299 * @param drs The DCO range selection.
1300 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1301 * is not used in FBI mode, this parameter can be NULL. Passing
1302 * NULL does not cause a delay.
1303 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1304 * @retval kStatus_Success Switched to the target mode successfully.
1305 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1306 * to frequency above 32768 Hz.
1307 */
1308status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1309
1310/*!
1311 * @brief Sets the MCG to FBE mode.
1312 *
1313 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1314 * from the current mode, this function returns an error.
1315 *
1316 * @param frdiv FLL reference clock divider setting, FRDIV.
1317 * @param dmx32 DMX32 in FBE mode.
1318 * @param drs The DCO range selection.
1319 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1320 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1321 * does not cause a delay.
1322 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1323 * @retval kStatus_Success Switched to the target mode successfully.
1324 */
1325status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1326
1327/*!
1328 * @brief Sets the MCG to BLPI mode.
1329 *
1330 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1331 * from the current mode, this function returns an error.
1332 *
1333 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1334 * @retval kStatus_Success Switched to the target mode successfully.
1335 */
1336status_t CLOCK_SetBlpiMode(void);
1337
1338/*!
1339 * @brief Sets the MCG to BLPE mode.
1340 *
1341 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1342 * from the current mode, this function returns an error.
1343 *
1344 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1345 * @retval kStatus_Success Switched to the target mode successfully.
1346 */
1347status_t CLOCK_SetBlpeMode(void);
1348
1349/*!
1350 * @brief Sets the MCG to PBE mode.
1351 *
1352 * This function sets the MCG to PBE mode. If setting to PBE mode fails
1353 * from the current mode, this function returns an error.
1354 *
1355 * @param pllcs The PLL selection, PLLCS.
1356 * @param config Pointer to the PLL configuration.
1357 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1358 * @retval kStatus_Success Switched to the target mode successfully.
1359 *
1360 * @note
1361 * 1. The parameter \c pllcs selects the PLL. For platforms with
1362 * only one PLL, the parameter pllcs is kept for interface compatibility.
1363 * 2. The parameter \c config is the PLL configuration structure. On some
1364 * platforms, it is possible to choose the external PLL directly, which renders the
1365 * configuration structure not necessary. In this case, pass in NULL.
1366 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
1367 */
1368status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1369
1370/*!
1371 * @brief Sets the MCG to PEE mode.
1372 *
1373 * This function sets the MCG to PEE mode.
1374 *
1375 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1376 * @retval kStatus_Success Switched to the target mode successfully.
1377 *
1378 * @note This function only changes the CLKS to use the PLL/FLL output. If the
1379 * PRDIV/VDIV are different than in the PBE mode, set them up
1380 * in PBE mode and wait. When the clock is stable, switch to PEE mode.
1381 */
1382status_t CLOCK_SetPeeMode(void);
1383
1384/*!
1385 * @brief Switches the MCG to FBE mode from the external mode.
1386 *
1387 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1388 * The external clock is used as the system clock source and PLL is disabled. However,
1389 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1390 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1391 *
1392 * @code
1393 * CLOCK_ExternalModeToFbeModeQuick();
1394 * CLOCK_SetFeiMode(...);
1395 * @endcode
1396 *
1397 * @retval kStatus_Success Switched successfully.
1398 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1399 */
1400status_t CLOCK_ExternalModeToFbeModeQuick(void);
1401
1402/*!
1403 * @brief Switches the MCG to FBI mode from internal modes.
1404 *
1405 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1406 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1407 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1408 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1409 *
1410 * @code
1411 * CLOCK_InternalModeToFbiModeQuick();
1412 * CLOCK_SetFeeMode(...);
1413 * @endcode
1414 *
1415 * @retval kStatus_Success Switched successfully.
1416 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1417 */
1418status_t CLOCK_InternalModeToFbiModeQuick(void);
1419
1420/*!
1421 * @brief Sets the MCG to FEI mode during system boot up.
1422 *
1423 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1424 * set up MCG during system boot up.
1425 *
1426 * @param dmx32 DMX32 in FEI mode.
1427 * @param drs The DCO range selection.
1428 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1429 *
1430 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1431 * @retval kStatus_Success Switched to the target mode successfully.
1432 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1433 * to frequency above 32768 Hz.
1434 */
1435status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1436
1437/*!
1438 * @brief Sets the MCG to FEE mode during system bootup.
1439 *
1440 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1441 * set up the MCG during system boot up.
1442 *
1443 * @param oscsel OSC clock select, OSCSEL.
1444 * @param frdiv FLL reference clock divider setting, FRDIV.
1445 * @param dmx32 DMX32 in FEE mode.
1446 * @param drs The DCO range selection.
1447 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1448 *
1449 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1450 * @retval kStatus_Success Switched to the target mode successfully.
1451 */
1452status_t CLOCK_BootToFeeMode(
1453 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1454
1455/*!
1456 * @brief Sets the MCG to BLPI mode during system boot up.
1457 *
1458 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1459 * set up the MCG during system boot up.
1460 *
1461 * @param fcrdiv Fast IRC divider, FCRDIV.
1462 * @param ircs The internal reference clock to select, IRCS.
1463 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of the enumeration _mcg_irclk_enable_mode.
1464 *
1465 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1466 * @retval kStatus_Success Switched to the target mode successfully.
1467 */
1468status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1469
1470/*!
1471 * @brief Sets the MCG to BLPE mode during system boot up.
1472 *
1473 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1474 * set up the MCG during system boot up.
1475 *
1476 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1477 *
1478 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1479 * @retval kStatus_Success Switched to the target mode successfully.
1480 */
1481status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1482
1483/*!
1484 * @brief Sets the MCG to PEE mode during system boot up.
1485 *
1486 * This function sets the MCG to PEE mode from reset mode. It can also be used to
1487 * set up the MCG during system boot up.
1488 *
1489 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1490 * @param pllcs The PLL selection, PLLCS.
1491 * @param config Pointer to the PLL configuration.
1492 *
1493 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1494 * @retval kStatus_Success Switched to the target mode successfully.
1495 */
1496status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1497
1498/*!
1499 * @brief Sets the MCG to a target mode.
1500 *
1501 * This function sets MCG to a target mode defined by the configuration
1502 * structure. If switching to the target mode fails, this function
1503 * chooses the correct path.
1504 *
1505 * @param config Pointer to the target MCG mode configuration structure.
1506 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code _mcg_status.
1507 *
1508 * @note If the external clock is used in the target mode, ensure that it is
1509 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1510 * function.
1511 */
1512status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1513
1514/*@}*/
1515
1516#if defined(__cplusplus)
1517}
1518#endif /* __cplusplus */
1519
1520/*! @} */
1521
1522#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 05:24:51 +0100