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1/*
2** ###################################################################
3** Version: rev. 2.14, 2016-03-21
4** Build: b200921
5**
6** Abstract:
7** Chip specific module features.
8**
9** Copyright 2016 Freescale Semiconductor, Inc.
10** Copyright 2016-2020 NXP
11** All rights reserved.
12**
13** SPDX-License-Identifier: BSD-3-Clause
14**
15** http: www.nxp.com
16** mail: [email protected]
17**
18** Revisions:
19** - rev. 1.0 (2013-08-12)
20** Initial version.
21** - rev. 2.0 (2013-10-29)
22** Register accessor macros added to the memory map.
23** Symbols for Processor Expert memory map compatibility added to the memory map.
24** Startup file for gcc has been updated according to CMSIS 3.2.
25** System initialization updated.
26** MCG - registers updated.
27** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
28** - rev. 2.1 (2013-10-30)
29** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
30** - rev. 2.2 (2013-12-09)
31** DMA - EARS register removed.
32** AIPS0, AIPS1 - MPRA register updated.
33** - rev. 2.3 (2014-01-24)
34** Update according to reference manual rev. 2
35** ENET, MCG, MCM, SIM, USB - registers updated
36** - rev. 2.4 (2014-01-30)
37** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum.
38** - rev. 2.5 (2014-02-10)
39** The declaration of clock configurations has been moved to separate header file system_MK24F12.h
40** Update of SystemInit() and SystemCoreClockUpdate() functions.
41** Module access macro module_BASES replaced by module_BASE_PTRS.
42** - rev. 2.6 (2014-08-28)
43** Update of system files - default clock configuration changed.
44** Update of startup files - possibility to override DefaultISR added.
45** - rev. 2.7 (2014-10-14)
46** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
47** - rev. 2.8 (2015-01-21)
48** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
49** - rev. 2.9 (2015-02-19)
50** Renamed interrupt vector LLW to LLWU.
51** - rev. 2.10 (2015-05-19)
52** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
53** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
54** Added features for PDB and PORT.
55** - rev. 2.11 (2015-05-25)
56** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
57** - rev. 2.12 (2015-05-27)
58** Several USB features added.
59** - rev. 2.13 (2015-06-08)
60** FTM features BUS_CLOCK and FAST_CLOCK removed.
61** - rev. 2.14 (2016-03-21)
62** Added MK24FN1M0CAJ12 part.
63**
64** ###################################################################
65*/
66
67#ifndef _MK24F12_FEATURES_H_
68#define _MK24F12_FEATURES_H_
69
70/* SOC module features */
71
72#if defined(CPU_MK24FN1M0CAJ12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12)
73 /* @brief ADC16 availability on the SoC. */
74 #define FSL_FEATURE_SOC_ADC16_COUNT (2)
75 /* @brief AIPS availability on the SoC. */
76 #define FSL_FEATURE_SOC_AIPS_COUNT (2)
77 /* @brief AXBS availability on the SoC. */
78 #define FSL_FEATURE_SOC_AXBS_COUNT (1)
79 /* @brief FLEXCAN availability on the SoC. */
80 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
81 /* @brief MMCAU availability on the SoC. */
82 #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
83 /* @brief CMP availability on the SoC. */
84 #define FSL_FEATURE_SOC_CMP_COUNT (3)
85 /* @brief CMT availability on the SoC. */
86 #define FSL_FEATURE_SOC_CMT_COUNT (1)
87 /* @brief CRC availability on the SoC. */
88 #define FSL_FEATURE_SOC_CRC_COUNT (1)
89 /* @brief DAC availability on the SoC. */
90 #define FSL_FEATURE_SOC_DAC_COUNT (2)
91 /* @brief EDMA availability on the SoC. */
92 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
93 /* @brief DMAMUX availability on the SoC. */
94 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
95 /* @brief DSPI availability on the SoC. */
96 #define FSL_FEATURE_SOC_DSPI_COUNT (3)
97 /* @brief EWM availability on the SoC. */
98 #define FSL_FEATURE_SOC_EWM_COUNT (1)
99 /* @brief FB availability on the SoC. */
100 #define FSL_FEATURE_SOC_FB_COUNT (1)
101 /* @brief FMC availability on the SoC. */
102 #define FSL_FEATURE_SOC_FMC_COUNT (1)
103 /* @brief FTFE availability on the SoC. */
104 #define FSL_FEATURE_SOC_FTFE_COUNT (1)
105 /* @brief FTM availability on the SoC. */
106 #define FSL_FEATURE_SOC_FTM_COUNT (4)
107 /* @brief GPIO availability on the SoC. */
108 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
109 /* @brief I2C availability on the SoC. */
110 #define FSL_FEATURE_SOC_I2C_COUNT (3)
111 /* @brief I2S availability on the SoC. */
112 #define FSL_FEATURE_SOC_I2S_COUNT (1)
113 /* @brief LLWU availability on the SoC. */
114 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
115 /* @brief LPTMR availability on the SoC. */
116 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
117 /* @brief MCG availability on the SoC. */
118 #define FSL_FEATURE_SOC_MCG_COUNT (1)
119 /* @brief MCM availability on the SoC. */
120 #define FSL_FEATURE_SOC_MCM_COUNT (1)
121 /* @brief SYSMPU availability on the SoC. */
122 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
123 /* @brief OSC availability on the SoC. */
124 #define FSL_FEATURE_SOC_OSC_COUNT (1)
125 /* @brief PDB availability on the SoC. */
126 #define FSL_FEATURE_SOC_PDB_COUNT (1)
127 /* @brief PIT availability on the SoC. */
128 #define FSL_FEATURE_SOC_PIT_COUNT (1)
129 /* @brief PMC availability on the SoC. */
130 #define FSL_FEATURE_SOC_PMC_COUNT (1)
131 /* @brief PORT availability on the SoC. */
132 #define FSL_FEATURE_SOC_PORT_COUNT (5)
133 /* @brief RCM availability on the SoC. */
134 #define FSL_FEATURE_SOC_RCM_COUNT (1)
135 /* @brief RFSYS availability on the SoC. */
136 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
137 /* @brief RFVBAT availability on the SoC. */
138 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
139 /* @brief RNG availability on the SoC. */
140 #define FSL_FEATURE_SOC_RNG_COUNT (1)
141 /* @brief RTC availability on the SoC. */
142 #define FSL_FEATURE_SOC_RTC_COUNT (1)
143 /* @brief SDHC availability on the SoC. */
144 #define FSL_FEATURE_SOC_SDHC_COUNT (1)
145 /* @brief SIM availability on the SoC. */
146 #define FSL_FEATURE_SOC_SIM_COUNT (1)
147 /* @brief SMC availability on the SoC. */
148 #define FSL_FEATURE_SOC_SMC_COUNT (1)
149 /* @brief UART availability on the SoC. */
150 #define FSL_FEATURE_SOC_UART_COUNT (6)
151 /* @brief USB availability on the SoC. */
152 #define FSL_FEATURE_SOC_USB_COUNT (1)
153 /* @brief USBDCD availability on the SoC. */
154 #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
155 /* @brief VREF availability on the SoC. */
156 #define FSL_FEATURE_SOC_VREF_COUNT (1)
157 /* @brief WDOG availability on the SoC. */
158 #define FSL_FEATURE_SOC_WDOG_COUNT (1)
159#elif defined(CPU_MK24FN1M0VLL12)
160 /* @brief ADC16 availability on the SoC. */
161 #define FSL_FEATURE_SOC_ADC16_COUNT (2)
162 /* @brief AIPS availability on the SoC. */
163 #define FSL_FEATURE_SOC_AIPS_COUNT (2)
164 /* @brief AXBS availability on the SoC. */
165 #define FSL_FEATURE_SOC_AXBS_COUNT (1)
166 /* @brief FLEXCAN availability on the SoC. */
167 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1)
168 /* @brief MMCAU availability on the SoC. */
169 #define FSL_FEATURE_SOC_MMCAU_COUNT (1)
170 /* @brief CMP availability on the SoC. */
171 #define FSL_FEATURE_SOC_CMP_COUNT (3)
172 /* @brief CMT availability on the SoC. */
173 #define FSL_FEATURE_SOC_CMT_COUNT (1)
174 /* @brief CRC availability on the SoC. */
175 #define FSL_FEATURE_SOC_CRC_COUNT (1)
176 /* @brief DAC availability on the SoC. */
177 #define FSL_FEATURE_SOC_DAC_COUNT (1)
178 /* @brief EDMA availability on the SoC. */
179 #define FSL_FEATURE_SOC_EDMA_COUNT (1)
180 /* @brief DMAMUX availability on the SoC. */
181 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
182 /* @brief DSPI availability on the SoC. */
183 #define FSL_FEATURE_SOC_DSPI_COUNT (3)
184 /* @brief EWM availability on the SoC. */
185 #define FSL_FEATURE_SOC_EWM_COUNT (1)
186 /* @brief FB availability on the SoC. */
187 #define FSL_FEATURE_SOC_FB_COUNT (1)
188 /* @brief FMC availability on the SoC. */
189 #define FSL_FEATURE_SOC_FMC_COUNT (1)
190 /* @brief FTFE availability on the SoC. */
191 #define FSL_FEATURE_SOC_FTFE_COUNT (1)
192 /* @brief FTM availability on the SoC. */
193 #define FSL_FEATURE_SOC_FTM_COUNT (4)
194 /* @brief GPIO availability on the SoC. */
195 #define FSL_FEATURE_SOC_GPIO_COUNT (5)
196 /* @brief I2C availability on the SoC. */
197 #define FSL_FEATURE_SOC_I2C_COUNT (3)
198 /* @brief I2S availability on the SoC. */
199 #define FSL_FEATURE_SOC_I2S_COUNT (1)
200 /* @brief LLWU availability on the SoC. */
201 #define FSL_FEATURE_SOC_LLWU_COUNT (1)
202 /* @brief LPTMR availability on the SoC. */
203 #define FSL_FEATURE_SOC_LPTMR_COUNT (1)
204 /* @brief MCG availability on the SoC. */
205 #define FSL_FEATURE_SOC_MCG_COUNT (1)
206 /* @brief MCM availability on the SoC. */
207 #define FSL_FEATURE_SOC_MCM_COUNT (1)
208 /* @brief SYSMPU availability on the SoC. */
209 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
210 /* @brief OSC availability on the SoC. */
211 #define FSL_FEATURE_SOC_OSC_COUNT (1)
212 /* @brief PDB availability on the SoC. */
213 #define FSL_FEATURE_SOC_PDB_COUNT (1)
214 /* @brief PIT availability on the SoC. */
215 #define FSL_FEATURE_SOC_PIT_COUNT (1)
216 /* @brief PMC availability on the SoC. */
217 #define FSL_FEATURE_SOC_PMC_COUNT (1)
218 /* @brief PORT availability on the SoC. */
219 #define FSL_FEATURE_SOC_PORT_COUNT (5)
220 /* @brief RCM availability on the SoC. */
221 #define FSL_FEATURE_SOC_RCM_COUNT (1)
222 /* @brief RFSYS availability on the SoC. */
223 #define FSL_FEATURE_SOC_RFSYS_COUNT (1)
224 /* @brief RFVBAT availability on the SoC. */
225 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
226 /* @brief RNG availability on the SoC. */
227 #define FSL_FEATURE_SOC_RNG_COUNT (1)
228 /* @brief RTC availability on the SoC. */
229 #define FSL_FEATURE_SOC_RTC_COUNT (1)
230 /* @brief SDHC availability on the SoC. */
231 #define FSL_FEATURE_SOC_SDHC_COUNT (1)
232 /* @brief SIM availability on the SoC. */
233 #define FSL_FEATURE_SOC_SIM_COUNT (1)
234 /* @brief SMC availability on the SoC. */
235 #define FSL_FEATURE_SOC_SMC_COUNT (1)
236 /* @brief UART availability on the SoC. */
237 #define FSL_FEATURE_SOC_UART_COUNT (5)
238 /* @brief USB availability on the SoC. */
239 #define FSL_FEATURE_SOC_USB_COUNT (1)
240 /* @brief USBDCD availability on the SoC. */
241 #define FSL_FEATURE_SOC_USBDCD_COUNT (1)
242 /* @brief VREF availability on the SoC. */
243 #define FSL_FEATURE_SOC_VREF_COUNT (1)
244 /* @brief WDOG availability on the SoC. */
245 #define FSL_FEATURE_SOC_WDOG_COUNT (1)
246#endif
247
248/* ADC16 module features */
249
250/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
251#define FSL_FEATURE_ADC16_HAS_PGA (0)
252/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
253#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
254/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
255#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
256/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
257#define FSL_FEATURE_ADC16_HAS_DMA (1)
258/* @brief Has differential mode (bitfield SC1x[DIFF]). */
259#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
260/* @brief Has FIFO (bit SC4[AFDEP]). */
261#define FSL_FEATURE_ADC16_HAS_FIFO (0)
262/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
263#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
264/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
265#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
266/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
267#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
268/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
269#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
270/* @brief Has HW averaging (bit SC3[AVGE]). */
271#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
272/* @brief Has offset correction (register OFS). */
273#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
274/* @brief Maximum ADC resolution. */
275#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
276/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
277#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
278
279/* FLEXCAN module features */
280
281/* @brief Message buffer size */
282#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16)
283/* @brief Has doze mode support (register bit field MCR[DOZE]). */
284#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
285/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
286#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0)
287/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
288#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
289/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
290#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
291/* @brief Instance has extended bit timing register (register CBT). */
292#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0)
293/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
294#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
295/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
296#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0)
297/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
298#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
299/* @brief Has bitfield name BUF31TO0M. */
300#define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0)
301/* @brief Number of interrupt vectors. */
302#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
303/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
304#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
305
306/* CMP module features */
307
308/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
309#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0)
310/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
311#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
312/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
313#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
314/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
315#define FSL_FEATURE_CMP_HAS_DMA (1)
316/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
317#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
318/* @brief Has DAC Test function in CMP (register DACTEST). */
319#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
320
321/* CRC module features */
322
323/* @brief Has data register with name CRC */
324#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
325
326/* DAC module features */
327
328/* @brief Define the size of hardware buffer */
329#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
330/* @brief Define whether the buffer supports watermark event detection or not. */
331#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
332/* @brief Define whether the buffer supports watermark selection detection or not. */
333#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
334/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
335#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
336/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
337#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
338/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
339#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
340/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
341#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
342/* @brief Define whether FIFO buffer mode is available or not. */
343#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
344/* @brief Define whether swing buffer mode is available or not.. */
345#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
346
347/* EDMA module features */
348
349/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
350#define FSL_FEATURE_EDMA_MODULE_CHANNEL (16)
351/* @brief Total number of DMA channels on all modules. */
352#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16)
353/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
354#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1)
355/* @brief Has DMA_Error interrupt vector. */
356#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
357/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
358#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0)
359/* @brief Channel IRQ entry shared offset. */
360#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (0)
361/* @brief If 8 bytes transfer supported. */
362#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0)
363/* @brief If 16 bytes transfer supported. */
364#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
365
366/* DMAMUX module features */
367
368/* @brief Number of DMA channels (related to number of register CHCFGn). */
369#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16)
370/* @brief Total number of DMA channels on all modules. */
371#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (16)
372/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
373#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
374/* @brief Register CHCFGn width. */
375#define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8)
376
377/* EWM module features */
378
379/* @brief Has clock select (register CLKCTRL). */
380#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0)
381/* @brief Has clock prescaler (register CLKPRESCALER). */
382#define FSL_FEATURE_EWM_HAS_PRESCALER (0)
383
384/* FLEXBUS module features */
385
386/* No feature definitions */
387
388/* FLASH module features */
389
390/* @brief Is of type FTFA. */
391#define FSL_FEATURE_FLASH_IS_FTFA (0)
392/* @brief Is of type FTFE. */
393#define FSL_FEATURE_FLASH_IS_FTFE (1)
394/* @brief Is of type FTFL. */
395#define FSL_FEATURE_FLASH_IS_FTFL (0)
396/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
397#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
398/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
399#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
400/* @brief Has EEPROM region protection (register FEPROT). */
401#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0)
402/* @brief Has data flash region protection (register FDPROT). */
403#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0)
404/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
405#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0)
406/* @brief Has flash cache control in FMC module. */
407#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
408/* @brief Has flash cache control in MCM module. */
409#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
410/* @brief Has flash cache control in MSCM module. */
411#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
412/* @brief Has prefetch speculation control in flash, such as kv5x. */
413#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
414/* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
415#define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
416/* @brief P-Flash start address. */
417#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
418/* @brief P-Flash block count. */
419#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2)
420/* @brief P-Flash block size. */
421#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
422/* @brief P-Flash sector size. */
423#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
424/* @brief P-Flash write unit size. */
425#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
426/* @brief P-Flash data path width. */
427#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
428/* @brief P-Flash block swap feature. */
429#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
430/* @brief P-Flash protection region count. */
431#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
432/* @brief Has FlexNVM memory. */
433#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
434/* @brief Has FlexNVM alias. */
435#define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0)
436/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
437#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
438/* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */
439#define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000)
440/* @brief FlexNVM block count. */
441#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
442/* @brief FlexNVM block size. */
443#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
444/* @brief FlexNVM sector size. */
445#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
446/* @brief FlexNVM write unit size. */
447#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
448/* @brief FlexNVM data path width. */
449#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
450/* @brief Has FlexRAM memory. */
451#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
452/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
453#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
454/* @brief FlexRAM size. */
455#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
456/* @brief Has 0x00 Read 1s Block command. */
457#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
458/* @brief Has 0x01 Read 1s Section command. */
459#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
460/* @brief Has 0x02 Program Check command. */
461#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
462/* @brief Has 0x03 Read Resource command. */
463#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
464/* @brief Has 0x06 Program Longword command. */
465#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
466/* @brief Has 0x07 Program Phrase command. */
467#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
468/* @brief Has 0x08 Erase Flash Block command. */
469#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
470/* @brief Has 0x09 Erase Flash Sector command. */
471#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
472/* @brief Has 0x0B Program Section command. */
473#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
474/* @brief Has 0x40 Read 1s All Blocks command. */
475#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
476/* @brief Has 0x41 Read Once command. */
477#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
478/* @brief Has 0x43 Program Once command. */
479#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
480/* @brief Has 0x44 Erase All Blocks command. */
481#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
482/* @brief Has 0x45 Verify Backdoor Access Key command. */
483#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
484/* @brief Has 0x46 Swap Control command. */
485#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
486/* @brief Has 0x49 Erase All Blocks Unsecure command. */
487#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
488/* @brief Has 0x4A Read 1s All Execute-only Segments command. */
489#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
490/* @brief Has 0x4B Erase All Execute-only Segments command. */
491#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
492/* @brief Has 0x80 Program Partition command. */
493#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
494/* @brief Has 0x81 Set FlexRAM Function command. */
495#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
496/* @brief P-Flash Erase/Read 1st all block command address alignment. */
497#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
498/* @brief P-Flash Erase sector command address alignment. */
499#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
500/* @brief P-Flash Rrogram/Verify section command address alignment. */
501#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
502/* @brief P-Flash Read resource command address alignment. */
503#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
504/* @brief P-Flash Program check command address alignment. */
505#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
506/* @brief P-Flash Program check command address alignment. */
507#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
508/* @brief FlexNVM Erase/Read 1st all block command address alignment. */
509#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
510/* @brief FlexNVM Erase sector command address alignment. */
511#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
512/* @brief FlexNVM Rrogram/Verify section command address alignment. */
513#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
514/* @brief FlexNVM Read resource command address alignment. */
515#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
516/* @brief FlexNVM Program check command address alignment. */
517#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
518/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
519#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU)
520/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
521#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU)
522/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
523#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU)
524/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
525#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU)
526/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
527#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU)
528/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
529#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU)
530/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
531#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU)
532/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
533#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU)
534/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
535#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU)
536/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
537#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU)
538/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
539#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU)
540/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
541#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU)
542/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
543#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU)
544/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
545#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU)
546/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
547#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU)
548/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
549#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU)
550/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
551#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
552/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
553#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
554/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
555#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
556/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
557#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
558/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
559#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
560/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
561#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
562/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
563#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
564/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
565#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
566/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
567#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
568/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
569#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
570/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
571#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
572/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
573#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
574/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
575#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
576/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
577#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
578/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
579#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
580/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
581#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
582
583/* FTM module features */
584
585/* @brief Number of channels. */
586#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
587 (((x) == FTM0) ? (8) : \
588 (((x) == FTM1) ? (2) : \
589 (((x) == FTM2) ? (2) : \
590 (((x) == FTM3) ? (8) : (-1)))))
591/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
592#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
593/* @brief Has extended deadtime value. */
594#define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0)
595/* @brief Enable pwm output for the module. */
596#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0)
597/* @brief Has half-cycle reload for the module. */
598#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0)
599/* @brief Has reload interrupt. */
600#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0)
601/* @brief Has reload initialization trigger. */
602#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0)
603/* @brief Has DMA support, bitfield CnSC[DMA]. */
604#define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1)
605/* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */
606#define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0)
607/* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */
608#define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0)
609/* @brief Has no QDCTRL. */
610#define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0)
611/* @brief If instance has only TPM function. */
612#define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0)
613
614/* GPIO module features */
615
616/* @brief Has GPIO attribute checker register (GACR). */
617#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
618
619/* I2C module features */
620
621/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
622#define FSL_FEATURE_I2C_HAS_SMBUS (1)
623/* @brief Maximum supported baud rate in kilobit per second. */
624#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
625/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
626#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
627/* @brief Has DMA support (register bit C1[DMAEN]). */
628#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
629/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
630#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
631/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
632#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
633/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
634#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
635/* @brief Maximum width of the glitch filter in number of bus clocks. */
636#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
637/* @brief Has control of the drive capability of the I2C pins. */
638#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
639/* @brief Has double buffering support (register S2). */
640#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
641/* @brief Has double buffer enable. */
642#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
643
644/* SAI module features */
645
646/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
647#define FSL_FEATURE_SAI_FIFO_COUNT (8)
648/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
649#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2)
650/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
651#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
652/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
653#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0)
654/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
655#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0)
656/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
657#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0)
658/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
659#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0)
660/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
661#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
662/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
663#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
664/* @brief Ihe interrupt source number */
665#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
666/* @brief Has register of MCR. */
667#define FSL_FEATURE_SAI_HAS_MCR (1)
668/* @brief Has register of MDR */
669#define FSL_FEATURE_SAI_HAS_MDR (1)
670/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
671#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
672/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
673#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0)
674
675/* LLWU module features */
676
677/* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
678#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16)
679/* @brief Has pins 8-15 connected to LLWU device. */
680#define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
681/* @brief Maximum number of internal modules connected to LLWU device. */
682#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
683/* @brief Number of digital filters. */
684#define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2)
685/* @brief Has MF register. */
686#define FSL_FEATURE_LLWU_HAS_MF (0)
687/* @brief Has PF register. */
688#define FSL_FEATURE_LLWU_HAS_PF (0)
689/* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
690#define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1)
691/* @brief Has no internal module wakeup flag register. */
692#define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
693/* @brief Has external pin 0 connected to LLWU device. */
694#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
695/* @brief Index of port of external pin. */
696#define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
697/* @brief Number of external pin port on specified port. */
698#define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
699/* @brief Has external pin 1 connected to LLWU device. */
700#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
701/* @brief Index of port of external pin. */
702#define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
703/* @brief Number of external pin port on specified port. */
704#define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
705/* @brief Has external pin 2 connected to LLWU device. */
706#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
707/* @brief Index of port of external pin. */
708#define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
709/* @brief Number of external pin port on specified port. */
710#define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
711/* @brief Has external pin 3 connected to LLWU device. */
712#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
713/* @brief Index of port of external pin. */
714#define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
715/* @brief Number of external pin port on specified port. */
716#define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
717/* @brief Has external pin 4 connected to LLWU device. */
718#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
719/* @brief Index of port of external pin. */
720#define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
721/* @brief Number of external pin port on specified port. */
722#define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
723/* @brief Has external pin 5 connected to LLWU device. */
724#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
725/* @brief Index of port of external pin. */
726#define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
727/* @brief Number of external pin port on specified port. */
728#define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
729/* @brief Has external pin 6 connected to LLWU device. */
730#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
731/* @brief Index of port of external pin. */
732#define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
733/* @brief Number of external pin port on specified port. */
734#define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
735/* @brief Has external pin 7 connected to LLWU device. */
736#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
737/* @brief Index of port of external pin. */
738#define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
739/* @brief Number of external pin port on specified port. */
740#define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
741/* @brief Has external pin 8 connected to LLWU device. */
742#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
743/* @brief Index of port of external pin. */
744#define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
745/* @brief Number of external pin port on specified port. */
746#define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
747/* @brief Has external pin 9 connected to LLWU device. */
748#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
749/* @brief Index of port of external pin. */
750#define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
751/* @brief Number of external pin port on specified port. */
752#define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
753/* @brief Has external pin 10 connected to LLWU device. */
754#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
755/* @brief Index of port of external pin. */
756#define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
757/* @brief Number of external pin port on specified port. */
758#define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
759/* @brief Has external pin 11 connected to LLWU device. */
760#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
761/* @brief Index of port of external pin. */
762#define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
763/* @brief Number of external pin port on specified port. */
764#define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
765/* @brief Has external pin 12 connected to LLWU device. */
766#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
767/* @brief Index of port of external pin. */
768#define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
769/* @brief Number of external pin port on specified port. */
770#define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
771/* @brief Has external pin 13 connected to LLWU device. */
772#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
773/* @brief Index of port of external pin. */
774#define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
775/* @brief Number of external pin port on specified port. */
776#define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
777/* @brief Has external pin 14 connected to LLWU device. */
778#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
779/* @brief Index of port of external pin. */
780#define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
781/* @brief Number of external pin port on specified port. */
782#define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
783/* @brief Has external pin 15 connected to LLWU device. */
784#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
785/* @brief Index of port of external pin. */
786#define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
787/* @brief Number of external pin port on specified port. */
788#define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
789/* @brief Has external pin 16 connected to LLWU device. */
790#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0)
791/* @brief Index of port of external pin. */
792#define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0)
793/* @brief Number of external pin port on specified port. */
794#define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0)
795/* @brief Has external pin 17 connected to LLWU device. */
796#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0)
797/* @brief Index of port of external pin. */
798#define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0)
799/* @brief Number of external pin port on specified port. */
800#define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0)
801/* @brief Has external pin 18 connected to LLWU device. */
802#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0)
803/* @brief Index of port of external pin. */
804#define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0)
805/* @brief Number of external pin port on specified port. */
806#define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0)
807/* @brief Has external pin 19 connected to LLWU device. */
808#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
809/* @brief Index of port of external pin. */
810#define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
811/* @brief Number of external pin port on specified port. */
812#define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
813/* @brief Has external pin 20 connected to LLWU device. */
814#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
815/* @brief Index of port of external pin. */
816#define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
817/* @brief Number of external pin port on specified port. */
818#define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
819/* @brief Has external pin 21 connected to LLWU device. */
820#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0)
821/* @brief Index of port of external pin. */
822#define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0)
823/* @brief Number of external pin port on specified port. */
824#define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0)
825/* @brief Has external pin 22 connected to LLWU device. */
826#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0)
827/* @brief Index of port of external pin. */
828#define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0)
829/* @brief Number of external pin port on specified port. */
830#define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0)
831/* @brief Has external pin 23 connected to LLWU device. */
832#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0)
833/* @brief Index of port of external pin. */
834#define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0)
835/* @brief Number of external pin port on specified port. */
836#define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0)
837/* @brief Has external pin 24 connected to LLWU device. */
838#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0)
839/* @brief Index of port of external pin. */
840#define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0)
841/* @brief Number of external pin port on specified port. */
842#define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0)
843/* @brief Has external pin 25 connected to LLWU device. */
844#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0)
845/* @brief Index of port of external pin. */
846#define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0)
847/* @brief Number of external pin port on specified port. */
848#define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0)
849/* @brief Has external pin 26 connected to LLWU device. */
850#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
851/* @brief Index of port of external pin. */
852#define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
853/* @brief Number of external pin port on specified port. */
854#define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
855/* @brief Has external pin 27 connected to LLWU device. */
856#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
857/* @brief Index of port of external pin. */
858#define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
859/* @brief Number of external pin port on specified port. */
860#define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
861/* @brief Has external pin 28 connected to LLWU device. */
862#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
863/* @brief Index of port of external pin. */
864#define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
865/* @brief Number of external pin port on specified port. */
866#define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
867/* @brief Has external pin 29 connected to LLWU device. */
868#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0)
869/* @brief Index of port of external pin. */
870#define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
871/* @brief Number of external pin port on specified port. */
872#define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
873/* @brief Has external pin 30 connected to LLWU device. */
874#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0)
875/* @brief Index of port of external pin. */
876#define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
877/* @brief Number of external pin port on specified port. */
878#define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
879/* @brief Has external pin 31 connected to LLWU device. */
880#define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0)
881/* @brief Index of port of external pin. */
882#define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
883/* @brief Number of external pin port on specified port. */
884#define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
885/* @brief Has internal module 0 connected to LLWU device. */
886#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
887/* @brief Has internal module 1 connected to LLWU device. */
888#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
889/* @brief Has internal module 2 connected to LLWU device. */
890#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
891/* @brief Has internal module 3 connected to LLWU device. */
892#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
893/* @brief Has internal module 4 connected to LLWU device. */
894#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0)
895/* @brief Has internal module 5 connected to LLWU device. */
896#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
897/* @brief Has internal module 6 connected to LLWU device. */
898#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
899/* @brief Has internal module 7 connected to LLWU device. */
900#define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
901/* @brief Has Version ID Register (LLWU_VERID). */
902#define FSL_FEATURE_LLWU_HAS_VERID (0)
903/* @brief Has Parameter Register (LLWU_PARAM). */
904#define FSL_FEATURE_LLWU_HAS_PARAM (0)
905/* @brief Width of registers of the LLWU. */
906#define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
907/* @brief Has DMA Enable register (LLWU_DE). */
908#define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
909
910/* LPTMR module features */
911
912/* @brief Has shared interrupt handler with another LPTMR module. */
913#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
914/* @brief Whether LPTMR counter is 32 bits width. */
915#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
916/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
917#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
918
919/* MCG module features */
920
921/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
922#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
923/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
924#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24)
925/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
926#define FSL_FEATURE_MCG_PLL_VDIV_BASE (24)
927/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
928#define FSL_FEATURE_MCG_PLL_REF_MIN (2000000)
929/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
930#define FSL_FEATURE_MCG_PLL_REF_MAX (4000000)
931/* @brief The PLL clock is divided by 2 before VCO divider. */
932#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0)
933/* @brief FRDIV supports 1280. */
934#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
935/* @brief FRDIV supports 1536. */
936#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
937/* @brief MCGFFCLK divider. */
938#define FSL_FEATURE_MCG_FFCLK_DIV (1)
939/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
940#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
941/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
942#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
943/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
944#define FSL_FEATURE_MCG_HAS_PLL1 (0)
945/* @brief Has 48MHz internal oscillator. */
946#define FSL_FEATURE_MCG_HAS_IRC_48M (1)
947/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
948#define FSL_FEATURE_MCG_HAS_OSC1 (0)
949/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
950#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
951/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
952#define FSL_FEATURE_MCG_HAS_LOLRE (1)
953/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
954#define FSL_FEATURE_MCG_USE_OSCSEL (1)
955/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
956#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
957/* @brief TBD */
958#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
959/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
960#define FSL_FEATURE_MCG_HAS_PLL (1)
961/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
962#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
963/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
964#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
965/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
966#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
967/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
968#define FSL_FEATURE_MCG_HAS_FLL (1)
969/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
970#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0)
971/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
972#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
973/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
974#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
975/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
976#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0)
977/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
978#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
979/* @brief Has external clock monitor (register bit C6[CME]). */
980#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
981/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
982#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
983/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
984#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
985/* @brief Has PEI mode or PBI mode. */
986#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
987/* @brief Reset clock mode is BLPI. */
988#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
989
990/* interrupt module features */
991
992/* @brief Lowest interrupt request number. */
993#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
994/* @brief Highest interrupt request number. */
995#define FSL_FEATURE_INTERRUPT_IRQ_MAX (85)
996
997/* OSC module features */
998
999/* @brief Has OSC1 external oscillator. */
1000#define FSL_FEATURE_OSC_HAS_OSC1 (0)
1001/* @brief Has OSC0 external oscillator. */
1002#define FSL_FEATURE_OSC_HAS_OSC0 (0)
1003/* @brief Has OSC external oscillator (without index). */
1004#define FSL_FEATURE_OSC_HAS_OSC (1)
1005/* @brief Number of OSC external oscillators. */
1006#define FSL_FEATURE_OSC_OSC_COUNT (1)
1007/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
1008#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0)
1009
1010/* PDB module features */
1011
1012/* @brief Has DAC support. */
1013#define FSL_FEATURE_PDB_HAS_DAC (1)
1014/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
1015#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
1016/* @brief PDB channel number). */
1017#define FSL_FEATURE_PDB_CHANNEL_COUNT (2)
1018/* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */
1019#define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2)
1020/* @brief DAC interval trigger number). */
1021#define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (2)
1022/* @brief Pulse out number). */
1023#define FSL_FEATURE_PDB_PULSE_OUT_COUNT (3)
1024
1025/* PIT module features */
1026
1027/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
1028#define FSL_FEATURE_PIT_TIMER_COUNT (4)
1029/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
1030#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0)
1031/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
1032#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
1033/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
1034#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
1035/* @brief Has timer enable control. */
1036#define FSL_FEATURE_PIT_HAS_MDIS (1)
1037
1038/* PMC module features */
1039
1040/* @brief Has Bandgap Enable In VLPx Operation support. */
1041#define FSL_FEATURE_PMC_HAS_BGEN (1)
1042/* @brief Has Bandgap Buffer Enable. */
1043#define FSL_FEATURE_PMC_HAS_BGBE (1)
1044/* @brief Has Bandgap Buffer Drive Select. */
1045#define FSL_FEATURE_PMC_HAS_BGBDS (0)
1046/* @brief Has Low-Voltage Detect Voltage Select support. */
1047#define FSL_FEATURE_PMC_HAS_LVDV (1)
1048/* @brief Has Low-Voltage Warning Voltage Select support. */
1049#define FSL_FEATURE_PMC_HAS_LVWV (1)
1050/* @brief Has LPO. */
1051#define FSL_FEATURE_PMC_HAS_LPO (0)
1052/* @brief Has VLPx option PMC_REGSC[VLPO]. */
1053#define FSL_FEATURE_PMC_HAS_VLPO (0)
1054/* @brief Has acknowledge isolation support. */
1055#define FSL_FEATURE_PMC_HAS_ACKISO (1)
1056/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
1057#define FSL_FEATURE_PMC_HAS_REGFPM (0)
1058/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
1059#define FSL_FEATURE_PMC_HAS_REGONS (1)
1060/* @brief Has PMC_HVDSC1. */
1061#define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
1062/* @brief Has PMC_PARAM. */
1063#define FSL_FEATURE_PMC_HAS_PARAM (0)
1064/* @brief Has PMC_VERID. */
1065#define FSL_FEATURE_PMC_HAS_VERID (0)
1066
1067/* PORT module features */
1068
1069/* @brief Has control lock (register bit PCR[LK]). */
1070#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
1071/* @brief Has open drain control (register bit PCR[ODE]). */
1072#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
1073/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
1074#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
1075/* @brief Has DMA request (register bit field PCR[IRQC] values). */
1076#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
1077/* @brief Has pull resistor selection available. */
1078#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
1079/* @brief Has pull resistor enable (register bit PCR[PE]). */
1080#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
1081/* @brief Has slew rate control (register bit PCR[SRE]). */
1082#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
1083/* @brief Has passive filter (register bit field PCR[PFE]). */
1084#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
1085/* @brief Has drive strength control (register bit PCR[DSE]). */
1086#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
1087/* @brief Has separate drive strength register (HDRVE). */
1088#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
1089/* @brief Has glitch filter (register IOFLT). */
1090#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
1091/* @brief Defines width of PCR[MUX] field. */
1092#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
1093/* @brief Has dedicated interrupt vector. */
1094#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
1095/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
1096#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
1097/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
1098#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
1099/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
1100#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
1101
1102/* RCM module features */
1103
1104/* @brief Has Loss-of-Lock Reset support. */
1105#define FSL_FEATURE_RCM_HAS_LOL (1)
1106/* @brief Has Loss-of-Clock Reset support. */
1107#define FSL_FEATURE_RCM_HAS_LOC (1)
1108/* @brief Has JTAG generated Reset support. */
1109#define FSL_FEATURE_RCM_HAS_JTAG (1)
1110/* @brief Has EzPort generated Reset support. */
1111#define FSL_FEATURE_RCM_HAS_EZPORT (1)
1112/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
1113#define FSL_FEATURE_RCM_HAS_EZPMS (1)
1114/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
1115#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
1116/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
1117#define FSL_FEATURE_RCM_HAS_SSRS (0)
1118/* @brief Has Version ID Register (RCM_VERID). */
1119#define FSL_FEATURE_RCM_HAS_VERID (0)
1120/* @brief Has Parameter Register (RCM_PARAM). */
1121#define FSL_FEATURE_RCM_HAS_PARAM (0)
1122/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
1123#define FSL_FEATURE_RCM_HAS_SRIE (0)
1124/* @brief Width of registers of the RCM. */
1125#define FSL_FEATURE_RCM_REG_WIDTH (8)
1126/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
1127#define FSL_FEATURE_RCM_HAS_CORE1 (0)
1128/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
1129#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
1130/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
1131#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
1132
1133/* RTC module features */
1134
1135/* @brief Has wakeup pin. */
1136#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
1137/* @brief Has wakeup pin selection (bit field CR[WPS]). */
1138#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
1139/* @brief Has low power features (registers MER, MCLR and MCHR). */
1140#define FSL_FEATURE_RTC_HAS_MONOTONIC (0)
1141/* @brief Has read/write access control (registers WAR and RAR). */
1142#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
1143/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
1144#define FSL_FEATURE_RTC_HAS_SECURITY (0)
1145/* @brief Has RTC_CLKIN available. */
1146#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
1147/* @brief Has prescaler adjust for LPO. */
1148#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
1149/* @brief Has Clock Pin Enable field. */
1150#define FSL_FEATURE_RTC_HAS_CPE (0)
1151/* @brief Has Timer Seconds Interrupt Configuration field. */
1152#define FSL_FEATURE_RTC_HAS_TSIC (0)
1153/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
1154#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
1155/* @brief Has Tamper Interrupt Register (register TIR). */
1156#define FSL_FEATURE_RTC_HAS_TIR (0)
1157/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
1158#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
1159/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
1160#define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
1161/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
1162#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
1163/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
1164#define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
1165/* @brief Has Tamper Detect Register (register TDR). */
1166#define FSL_FEATURE_RTC_HAS_TDR (0)
1167/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
1168#define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
1169/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
1170#define FSL_FEATURE_RTC_HAS_TDR_STF (0)
1171/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
1172#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
1173/* @brief Has Tamper Time Seconds Register (register TTSR). */
1174#define FSL_FEATURE_RTC_HAS_TTSR (0)
1175/* @brief Has Pin Configuration Register (register PCR). */
1176#define FSL_FEATURE_RTC_HAS_PCR (0)
1177
1178/* SDHC module features */
1179
1180/* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */
1181#define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1)
1182/* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */
1183#define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0)
1184/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
1185#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0)
1186
1187/* SIM module features */
1188
1189/* @brief Has USB FS divider. */
1190#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1191/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1192#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
1193/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1194#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
1195/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1196#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
1197/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1198#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
1199/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1200#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
1201/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1202#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
1203/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1204#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
1205/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1206#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0)
1207/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1208#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1)
1209/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1210#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
1211/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1212#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1213/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1214#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1215/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1216#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1217/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
1218#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0)
1219/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1220#define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
1221/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
1222#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
1223/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
1224#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
1225/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
1226#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
1227/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1228#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1229/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1230#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1231/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1232#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1233/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1234#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0)
1235/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1236#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0)
1237/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1238#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1239/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1240#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1241/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1242#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
1243/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1244#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
1245/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1246#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
1247/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1248#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
1249/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1250#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
1251/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1252#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
1253/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1254#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
1255/* @brief Has FTM module(s) configuration. */
1256#define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
1257/* @brief Number of FTM modules. */
1258#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
1259/* @brief Number of FTM triggers with selectable source. */
1260#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
1261/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1262#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
1263/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1264#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
1265/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1266#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
1267/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1268#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
1269/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1270#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1271/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1272#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0)
1273/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1274#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3)
1275/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1276#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
1277/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1278#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
1279/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1280#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
1281/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1282#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0)
1283/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1284#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0)
1285/* @brief Has TPM module(s) configuration. */
1286#define FSL_FEATURE_SIM_OPT_HAS_TPM (0)
1287/* @brief The highest TPM module index. */
1288#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0)
1289/* @brief Has TPM module with index 0. */
1290#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
1291/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
1292#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
1293/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1294#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
1295/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1296#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0)
1297/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
1298#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
1299/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1300#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0)
1301/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1302#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
1303/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1304#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
1305/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1306#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
1307/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1308#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
1309/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1310#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1311/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1312#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1313/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1314#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
1315/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1316#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1317/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1318#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
1319/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1320#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1321/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1322#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
1323/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1324#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1325/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1326#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1327/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1328#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0)
1329/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1330#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1331/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1332#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1333/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1334#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1335/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1336#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1337/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1338#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0)
1339/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1340#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
1341/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1342#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
1343/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
1344#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
1345/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
1346#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1)
1347/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
1348#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
1349/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
1350#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
1351/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
1352#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
1353/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
1354#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
1355/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
1356#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
1357/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
1358#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
1359/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
1360#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
1361/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
1362#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
1363/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1364#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
1365/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1366#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
1367/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1368#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
1369/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1370#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
1371/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
1372#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
1373/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1374#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
1375/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1376#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1377/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1378#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1379/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1380#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0)
1381/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1382#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1383/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1384#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0)
1385/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1386#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1387/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1388#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
1389/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1390#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1391/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1392#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1393/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1394#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1395/* @brief Has device die ID (register bit field SDID[DIEID]). */
1396#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
1397/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1398#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
1399/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1400#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1401/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1402#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1403/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1404#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1405/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1406#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
1407/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1408#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
1409/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1410#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
1411/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1412#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
1413/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1414#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
1415/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1416#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
1417/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1418#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1419/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1420#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
1421/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1422#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0)
1423/* @brief Has miscellanious control register (register MCR). */
1424#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1425/* @brief Has COP watchdog (registers COPC and SRVCOP). */
1426#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
1427/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1428#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1429/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
1430#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
1431
1432/* SMC module features */
1433
1434/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
1435#define FSL_FEATURE_SMC_HAS_PSTOPO (0)
1436/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
1437#define FSL_FEATURE_SMC_HAS_LPOPO (0)
1438/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
1439#define FSL_FEATURE_SMC_HAS_PORPO (1)
1440/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
1441#define FSL_FEATURE_SMC_HAS_LPWUI (1)
1442/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
1443#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0)
1444/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
1445#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1)
1446/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
1447#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
1448/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
1449#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0)
1450/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
1451#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0)
1452/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
1453#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
1454/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
1455#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
1456/* @brief Has stop submode. */
1457#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
1458/* @brief Has stop submode 0(VLLS0). */
1459#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
1460/* @brief Has stop submode 1(VLLS1). */
1461#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1)
1462/* @brief Has stop submode 2(VLLS2). */
1463#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
1464/* @brief Has SMC_PARAM. */
1465#define FSL_FEATURE_SMC_HAS_PARAM (0)
1466/* @brief Has SMC_VERID. */
1467#define FSL_FEATURE_SMC_HAS_VERID (0)
1468/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
1469#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
1470/* @brief Has tamper reset (register bit SRS[TAMPER]). */
1471#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
1472/* @brief Has security violation reset (register bit SRS[SECVIO]). */
1473#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
1474/* @brief Width of SMC registers. */
1475#define FSL_FEATURE_SMC_REG_WIDTH (8)
1476
1477/* DSPI module features */
1478
1479/* @brief Receive/transmit FIFO size in number of items. */
1480#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
1481 (((x) == SPI0) ? (4) : \
1482 (((x) == SPI1) ? (1) : \
1483 (((x) == SPI2) ? (1) : (-1))))
1484/* @brief Maximum transfer data width in bits. */
1485#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
1486/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
1487#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
1488/* @brief Number of chip select pins. */
1489#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
1490/* @brief Number of CTAR registers. */
1491#define FSL_FEATURE_DSPI_CTAR_COUNT (2)
1492/* @brief Has chip select strobe capability on the PCS5 pin. */
1493#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
1494/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
1495#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
1496/* @brief Has 16-bit data transfer support. */
1497#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
1498/* @brief Has separate DMA RX and TX requests. */
1499#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
1500 (((x) == SPI0) ? (1) : \
1501 (((x) == SPI1) ? (0) : \
1502 (((x) == SPI2) ? (0) : (-1))))
1503
1504/* SYSMPU module features */
1505
1506/* @brief Specifies number of descriptors available. */
1507#define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12)
1508/* @brief Has process identifier support. */
1509#define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1)
1510/* @brief Total number of MPU slave. */
1511#define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5)
1512/* @brief Total number of MPU master. */
1513#define FSL_FEATURE_SYSMPU_MASTER_COUNT (6)
1514
1515/* SysTick module features */
1516
1517/* @brief Systick has external reference clock. */
1518#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
1519/* @brief Systick external reference clock is core clock divided by this value. */
1520#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
1521
1522/* UART module features */
1523
1524#if defined(CPU_MK24FN1M0CAJ12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12)
1525 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
1526 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
1527 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
1528 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
1529 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
1530 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
1531 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1532 #define FSL_FEATURE_UART_HAS_FIFO (1)
1533 /* @brief Hardware flow control (RTS, CTS) is supported. */
1534 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
1535 /* @brief Infrared (modulation) is supported. */
1536 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
1537 /* @brief 2 bits long stop bit is available. */
1538 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
1539 /* @brief If 10-bit mode is supported. */
1540 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
1541 /* @brief Baud rate fine adjustment is available. */
1542 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
1543 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
1544 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
1545 /* @brief Baud rate oversampling is available. */
1546 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
1547 /* @brief Baud rate oversampling is available. */
1548 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
1549 /* @brief Peripheral type. */
1550 #define FSL_FEATURE_UART_IS_SCI (0)
1551 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1552 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
1553 (((x) == UART0) ? (8) : \
1554 (((x) == UART1) ? (8) : \
1555 (((x) == UART2) ? (1) : \
1556 (((x) == UART3) ? (1) : \
1557 (((x) == UART4) ? (1) : \
1558 (((x) == UART5) ? (1) : (-1)))))))
1559 /* @brief Supports two match addresses to filter incoming frames. */
1560 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
1561 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
1562 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
1563 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
1564 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
1565 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
1566 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
1567 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
1568 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
1569 /* @brief Has improved smart card (ISO7816 protocol) support. */
1570 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
1571 /* @brief Has local operation network (CEA709.1-B protocol) support. */
1572 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
1573 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
1574 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
1575 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
1576 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
1577 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
1578 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
1579 /* @brief Has separate DMA RX and TX requests. */
1580 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
1581 (((x) == UART0) ? (1) : \
1582 (((x) == UART1) ? (1) : \
1583 (((x) == UART2) ? (1) : \
1584 (((x) == UART3) ? (1) : \
1585 (((x) == UART4) ? (0) : \
1586 (((x) == UART5) ? (0) : (-1)))))))
1587#elif defined(CPU_MK24FN1M0VLL12)
1588 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
1589 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
1590 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
1591 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
1592 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
1593 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
1594 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1595 #define FSL_FEATURE_UART_HAS_FIFO (1)
1596 /* @brief Hardware flow control (RTS, CTS) is supported. */
1597 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
1598 /* @brief Infrared (modulation) is supported. */
1599 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
1600 /* @brief 2 bits long stop bit is available. */
1601 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
1602 /* @brief If 10-bit mode is supported. */
1603 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
1604 /* @brief Baud rate fine adjustment is available. */
1605 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
1606 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
1607 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
1608 /* @brief Baud rate oversampling is available. */
1609 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
1610 /* @brief Baud rate oversampling is available. */
1611 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
1612 /* @brief Peripheral type. */
1613 #define FSL_FEATURE_UART_IS_SCI (0)
1614 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1615 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \
1616 (((x) == UART0) ? (8) : \
1617 (((x) == UART1) ? (8) : \
1618 (((x) == UART2) ? (1) : \
1619 (((x) == UART3) ? (1) : \
1620 (((x) == UART4) ? (1) : (-1))))))
1621 /* @brief Supports two match addresses to filter incoming frames. */
1622 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
1623 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
1624 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
1625 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
1626 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
1627 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
1628 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
1629 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
1630 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
1631 /* @brief Has improved smart card (ISO7816 protocol) support. */
1632 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
1633 /* @brief Has local operation network (CEA709.1-B protocol) support. */
1634 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
1635 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
1636 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
1637 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */
1638 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
1639 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
1640 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
1641 /* @brief Has separate DMA RX and TX requests. */
1642 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
1643 (((x) == UART0) ? (1) : \
1644 (((x) == UART1) ? (1) : \
1645 (((x) == UART2) ? (1) : \
1646 (((x) == UART3) ? (1) : \
1647 (((x) == UART4) ? (0) : (-1))))))
1648#endif /* defined(CPU_MK24FN1M0CAJ12) || defined(CPU_MK24FN1M0VDC12) || defined(CPU_MK24FN1M0VLQ12) */
1649
1650/* USB module features */
1651
1652/* @brief KHCI module instance count */
1653#define FSL_FEATURE_USB_KHCI_COUNT (1)
1654/* @brief HOST mode enabled */
1655#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
1656/* @brief OTG mode enabled */
1657#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
1658/* @brief Size of the USB dedicated RAM */
1659#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
1660/* @brief Has KEEP_ALIVE_CTRL register */
1661#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
1662/* @brief Has the Dynamic SOF threshold compare support */
1663#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
1664/* @brief Has the VBUS detect support */
1665#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
1666/* @brief Has the IRC48M module clock support */
1667#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
1668/* @brief Number of endpoints supported */
1669#define FSL_FEATURE_USB_ENDPT_COUNT (16)
1670/* @brief Has STALL_IL/OL_DIS registers */
1671#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0)
1672/* @brief Has STALL_IH/OH_DIS registers */
1673#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0)
1674
1675/* VREF module features */
1676
1677/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
1678#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
1679/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
1680#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
1681/* @brief If high/low buffer mode supported */
1682#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
1683/* @brief Module has also low reference (registers VREFL/VREFH) */
1684#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
1685/* @brief Has VREF_TRM4. */
1686#define FSL_FEATURE_VREF_HAS_TRM4 (0)
1687
1688/* WDOG module features */
1689
1690/* @brief Watchdog is available. */
1691#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
1692/* @brief Has Wait mode support. */
1693#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
1694
1695#endif /* _MK24F12_FEATURES_H_ */
1696
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