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1/*
2** ###################################################################
3** Processors: MK26FN2M0CAC18
4** MK26FN2M0VLQ18
5** MK26FN2M0VMD18
6** MK26FN2M0VMI18
7**
8** Compilers: Keil ARM C/C++ Compiler
9** Freescale C/C++ for Embedded ARM
10** GNU C Compiler
11** IAR ANSI C/C++ Compiler for ARM
12** MCUXpresso Compiler
13**
14** Reference manual: MK26P169M180SF5RM, Rev. 1, Mar 2015
15** Version: rev. 2.0, 2015-03-25
16** Build: b180801
17**
18** Abstract:
19** CMSIS Peripheral Access Layer for MK26F18
20**
21** Copyright 1997-2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2018 NXP
23**
24** SPDX-License-Identifier: BSD-3-Clause
25**
26** http: www.nxp.com
27** mail: [email protected]
28**
29** Revisions:
30** - rev. 1.0 (2014-12-04)
31** Initial version.
32** - rev. 1.1 (2015-02-19)
33** Renamed interrupt vector LLW to LLWU.
34** - rev. 2.0 (2015-03-25)
35** Registers updated according to the reference manual revision 1, March 2015
36**
37** ###################################################################
38*/
39
40/*!
41 * @file MK26F18.h
42 * @version 2.0
43 * @date 2015-03-25
44 * @brief CMSIS Peripheral Access Layer for MK26F18
45 *
46 * CMSIS Peripheral Access Layer for MK26F18
47 */
48
49#ifndef _MK26F18_H_
50#define _MK26F18_H_ /**< Symbol preventing repeated inclusion */
51
52/** Memory map major version (memory maps with equal major version number are
53 * compatible) */
54#define MCU_MEM_MAP_VERSION 0x0200U
55/** Memory map minor version */
56#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
57
58/**
59 * @brief Macro to calculate address of an aliased word in the peripheral
60 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
61 * 0x400FFFFF).
62 * @param Reg Register to access.
63 * @param Bit Bit number to access.
64 * @return Address of the aliased word in the peripheral bitband area.
65 */
66#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
67/**
68 * @brief Macro to access a single bit of a peripheral register (bit band region
69 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
70 * be used for peripherals with 32bit access allowed.
71 * @param Reg Register to access.
72 * @param Bit Bit number to access.
73 * @return Value of the targeted bit in the bit band region.
74 */
75#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
76#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
77/**
78 * @brief Macro to access a single bit of a peripheral register (bit band region
79 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
80 * be used for peripherals with 16bit access allowed.
81 * @param Reg Register to access.
82 * @param Bit Bit number to access.
83 * @return Value of the targeted bit in the bit band region.
84 */
85#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
86/**
87 * @brief Macro to access a single bit of a peripheral register (bit band region
88 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
89 * be used for peripherals with 8bit access allowed.
90 * @param Reg Register to access.
91 * @param Bit Bit number to access.
92 * @return Value of the targeted bit in the bit band region.
93 */
94#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
95
96/* ----------------------------------------------------------------------------
97 -- Interrupt vector numbers
98 ---------------------------------------------------------------------------- */
99
100/*!
101 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
102 * @{
103 */
104
105/** Interrupt Number Definitions */
106#define NUMBER_OF_INT_VECTORS 116 /**< Number of interrupts in the Vector table */
107
108typedef enum IRQn {
109 /* Auxiliary constants */
110 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
111
112 /* Core interrupts */
113 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
114 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
115 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
116 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
117 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
118 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
119 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
120 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
121 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
122
123 /* Device specific interrupts */
124 DMA0_DMA16_IRQn = 0, /**< DMA Channel 0, 16 Transfer Complete */
125 DMA1_DMA17_IRQn = 1, /**< DMA Channel 1, 17 Transfer Complete */
126 DMA2_DMA18_IRQn = 2, /**< DMA Channel 2, 18 Transfer Complete */
127 DMA3_DMA19_IRQn = 3, /**< DMA Channel 3, 19 Transfer Complete */
128 DMA4_DMA20_IRQn = 4, /**< DMA Channel 4, 20 Transfer Complete */
129 DMA5_DMA21_IRQn = 5, /**< DMA Channel 5, 21 Transfer Complete */
130 DMA6_DMA22_IRQn = 6, /**< DMA Channel 6, 22 Transfer Complete */
131 DMA7_DMA23_IRQn = 7, /**< DMA Channel 7, 23 Transfer Complete */
132 DMA8_DMA24_IRQn = 8, /**< DMA Channel 8, 24 Transfer Complete */
133 DMA9_DMA25_IRQn = 9, /**< DMA Channel 9, 25 Transfer Complete */
134 DMA10_DMA26_IRQn = 10, /**< DMA Channel 10, 26 Transfer Complete */
135 DMA11_DMA27_IRQn = 11, /**< DMA Channel 11, 27 Transfer Complete */
136 DMA12_DMA28_IRQn = 12, /**< DMA Channel 12, 28 Transfer Complete */
137 DMA13_DMA29_IRQn = 13, /**< DMA Channel 13, 29 Transfer Complete */
138 DMA14_DMA30_IRQn = 14, /**< DMA Channel 14, 30 Transfer Complete */
139 DMA15_DMA31_IRQn = 15, /**< DMA Channel 15, 31 Transfer Complete */
140 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
141 MCM_IRQn = 17, /**< Normal Interrupt */
142 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
143 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
144 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
145 LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */
146 WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */
147 RNG_IRQn = 23, /**< RNG Interrupt */
148 I2C0_IRQn = 24, /**< I2C0 interrupt */
149 I2C1_IRQn = 25, /**< I2C1 interrupt */
150 SPI0_IRQn = 26, /**< SPI0 Interrupt */
151 SPI1_IRQn = 27, /**< SPI1 Interrupt */
152 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
153 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
154 Reserved46_IRQn = 30, /**< Reserved interrupt 46 */
155 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
156 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
157 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
158 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
159 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
160 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
161 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
162 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
163 ADC0_IRQn = 39, /**< ADC0 interrupt */
164 CMP0_IRQn = 40, /**< CMP0 interrupt */
165 CMP1_IRQn = 41, /**< CMP1 interrupt */
166 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
167 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
168 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
169 CMT_IRQn = 45, /**< CMT interrupt */
170 RTC_IRQn = 46, /**< RTC interrupt */
171 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
172 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
173 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
174 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
175 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
176 PDB0_IRQn = 52, /**< PDB0 Interrupt */
177 USB0_IRQn = 53, /**< USB0 interrupt */
178 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
179 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
180 DAC0_IRQn = 56, /**< DAC0 interrupt */
181 MCG_IRQn = 57, /**< MCG Interrupt */
182 LPTMR0_IRQn = 58, /**< LPTimer interrupt */
183 PORTA_IRQn = 59, /**< Port A interrupt */
184 PORTB_IRQn = 60, /**< Port B interrupt */
185 PORTC_IRQn = 61, /**< Port C interrupt */
186 PORTD_IRQn = 62, /**< Port D interrupt */
187 PORTE_IRQn = 63, /**< Port E interrupt */
188 SWI_IRQn = 64, /**< Software interrupt */
189 SPI2_IRQn = 65, /**< SPI2 Interrupt */
190 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
191 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
192 Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
193 Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
194 CMP2_IRQn = 70, /**< CMP2 interrupt */
195 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
196 DAC1_IRQn = 72, /**< DAC1 interrupt */
197 ADC1_IRQn = 73, /**< ADC1 interrupt */
198 I2C2_IRQn = 74, /**< I2C2 interrupt */
199 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
200 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
201 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
202 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
203 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
204 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
205 SDHC_IRQn = 81, /**< SDHC interrupt */
206 Reserved98_IRQn = 82, /**< Reserved Interrupt 98 */
207 Reserved99_IRQn = 83, /**< Reserved Interrupt 99 */
208 Reserved100_IRQn = 84, /**< Reserved Interrupt 100 */
209 Reserved101_IRQn = 85, /**< Reserved Interrupt 101 */
210 LPUART0_IRQn = 86, /**< LPUART0 status/error interrupt */
211 TSI0_IRQn = 87, /**< TSI0 interrupt */
212 TPM1_IRQn = 88, /**< TPM1 fault, overflow and channels interrupt */
213 TPM2_IRQn = 89, /**< TPM2 fault, overflow and channels interrupt */
214 USBHSDCD_IRQn = 90, /**< USBHSDCD, USBHS Phy Interrupt */
215 I2C3_IRQn = 91, /**< I2C3 interrupt */
216 CMP3_IRQn = 92, /**< CMP3 interrupt */
217 USBHS_IRQn = 93, /**< USB high speed OTG interrupt */
218 CAN1_ORed_Message_buffer_IRQn = 94, /**< CAN1 OR'd message buffers interrupt */
219 CAN1_Bus_Off_IRQn = 95, /**< CAN1 bus off interrupt */
220 CAN1_Error_IRQn = 96, /**< CAN1 error interrupt */
221 CAN1_Tx_Warning_IRQn = 97, /**< CAN1 Tx warning interrupt */
222 CAN1_Rx_Warning_IRQn = 98, /**< CAN1 Rx warning interrupt */
223 CAN1_Wake_Up_IRQn = 99 /**< CAN1 wake up interrupt */
224} IRQn_Type;
225
226/*!
227 * @}
228 */ /* end of group Interrupt_vector_numbers */
229
230
231/* ----------------------------------------------------------------------------
232 -- Cortex M4 Core Configuration
233 ---------------------------------------------------------------------------- */
234
235/*!
236 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
237 * @{
238 */
239
240#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
241#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
242#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
243#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
244
245#include "core_cm4.h" /* Core Peripheral Access Layer */
246#include "system_MK26F18.h" /* Device specific configuration file */
247
248/*!
249 * @}
250 */ /* end of group Cortex_Core_Configuration */
251
252
253/* ----------------------------------------------------------------------------
254 -- Mapping Information
255 ---------------------------------------------------------------------------- */
256
257/*!
258 * @addtogroup Mapping_Information Mapping Information
259 * @{
260 */
261
262/** Mapping Information */
263/*!
264 * @addtogroup edma_request
265 * @{
266 */
267
268/*******************************************************************************
269 * Definitions
270 ******************************************************************************/
271
272/*!
273 * @brief Structure for the DMA hardware request
274 *
275 * Defines the structure for the DMA hardware request collections. The user can configure the
276 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
277 * of the hardware request varies according to the to SoC.
278 */
279typedef enum _dma_request_source
280{
281 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
282 kDmaRequestMux0TSI0 = 1|0x100U, /**< TSI0. */
283 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
284 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
285 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
286 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
287 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
288 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
289 kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */
290 kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */
291 kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */
292 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
293 kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
294 kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
295 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
296 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
297 kDmaRequestMux0SPI1Rx = 16|0x100U, /**< SPI1 Receive. */
298 kDmaRequestMux0SPI1Tx = 17|0x100U, /**< SPI1 Transmit. */
299 kDmaRequestMux0I2C0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
300 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0 and I2C3. */
301 kDmaRequestMux0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
302 kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
303 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
304 kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
305 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
306 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
307 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
308 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
309 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
310 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
311 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
312 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
313 kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
314 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
315 kDmaRequestMux0TPM1Channel0 = 28|0x100U, /**< FTM1 C0V and TPM1 C0V. */
316 kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
317 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
318 kDmaRequestMux0TPM1Channel1 = 29|0x100U, /**< FTM1 C1V and TPM1 C1V. */
319 kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
320 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
321 kDmaRequestMux0TPM2Channel0 = 30|0x100U, /**< FTM2 C0V and TPM2 C0V. */
322 kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
323 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
324 kDmaRequestMux0TPM2Channel1 = 31|0x100U, /**< FTM2 C1V and TPM2 C1V. */
325 kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
326 kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
327 kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
328 kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
329 kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
330 kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
331 kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
332 kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
333 kDmaRequestMux0SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
334 kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
335 kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
336 kDmaRequestMux0SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
337 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
338 kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
339 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
340 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
341 kDmaRequestMux0CMP2CMP3 = 44|0x100U, /**< CMP2 and CMP3. */
342 kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2 and CMP3. */
343 kDmaRequestMux0CMP3 = 44|0x100U, /**< CMP2 and CMP3. */
344 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
345 kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */
346 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
347 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
348 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
349 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
350 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
351 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
352 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
353 kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */
354 kDmaRequestMux0TPM1Overflow = 55|0x100U, /**< TPM1. */
355 kDmaRequestMux0TPM2Overflow = 56|0x100U, /**< TPM2. */
356 kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
357 kDmaRequestMux0LPUART0Rx = 58|0x100U, /**< LPUART0 Receive. */
358 kDmaRequestMux0LPUART0Tx = 59|0x100U, /**< LPUART0 Transmit. */
359 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
360 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
361 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
362 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
363} dma_request_source_t;
364
365/* @} */
366
367
368/*!
369 * @}
370 */ /* end of group Mapping_Information */
371
372
373/* ----------------------------------------------------------------------------
374 -- Device Peripheral Access Layer
375 ---------------------------------------------------------------------------- */
376
377/*!
378 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
379 * @{
380 */
381
382
383/*
384** Start of section using anonymous unions
385*/
386
387#if defined(__ARMCC_VERSION)
388 #if (__ARMCC_VERSION >= 6010050)
389 #pragma clang diagnostic push
390 #else
391 #pragma push
392 #pragma anon_unions
393 #endif
394#elif defined(__CWCC__)
395 #pragma push
396 #pragma cpp_extensions on
397#elif defined(__GNUC__)
398 /* anonymous unions are enabled by default */
399#elif defined(__IAR_SYSTEMS_ICC__)
400 #pragma language=extended
401#else
402 #error Not supported compiler type
403#endif
404
405/* ----------------------------------------------------------------------------
406 -- ADC Peripheral Access Layer
407 ---------------------------------------------------------------------------- */
408
409/*!
410 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
411 * @{
412 */
413
414/** ADC - Register Layout Typedef */
415typedef struct {
416 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
417 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
418 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
419 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
420 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
421 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
422 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
423 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
424 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
425 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
426 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
427 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
428 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
429 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
430 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
431 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
432 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
433 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
434 uint8_t RESERVED_0[4];
435 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
436 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
437 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
438 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
439 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
440 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
441 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
442} ADC_Type;
443
444/* ----------------------------------------------------------------------------
445 -- ADC Register Masks
446 ---------------------------------------------------------------------------- */
447
448/*!
449 * @addtogroup ADC_Register_Masks ADC Register Masks
450 * @{
451 */
452
453/*! @name SC1 - ADC Status and Control Registers 1 */
454/*! @{ */
455#define ADC_SC1_ADCH_MASK (0x1FU)
456#define ADC_SC1_ADCH_SHIFT (0U)
457/*! ADCH - Input channel select
458 * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
459 * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
460 * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
461 * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
462 * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
463 * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
464 * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
465 * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
466 * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
467 * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
468 * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
469 * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
470 * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
471 * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
472 * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
473 * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
474 * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
475 * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
476 * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
477 * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
478 * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
479 * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
480 * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
481 * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
482 * 0b11000..Reserved.
483 * 0b11001..Reserved.
484 * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
485 * 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
486 * 0b11100..Reserved.
487 * 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
488 * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
489 * 0b11111..Module is disabled.
490 */
491#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
492#define ADC_SC1_DIFF_MASK (0x20U)
493#define ADC_SC1_DIFF_SHIFT (5U)
494/*! DIFF - Differential Mode Enable
495 * 0b0..Single-ended conversions and input channels are selected.
496 * 0b1..Differential conversions and input channels are selected.
497 */
498#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
499#define ADC_SC1_AIEN_MASK (0x40U)
500#define ADC_SC1_AIEN_SHIFT (6U)
501/*! AIEN - Interrupt Enable
502 * 0b0..Conversion complete interrupt is disabled.
503 * 0b1..Conversion complete interrupt is enabled.
504 */
505#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
506#define ADC_SC1_COCO_MASK (0x80U)
507#define ADC_SC1_COCO_SHIFT (7U)
508/*! COCO - Conversion Complete Flag
509 * 0b0..Conversion is not completed.
510 * 0b1..Conversion is completed.
511 */
512#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
513/*! @} */
514
515/* The count of ADC_SC1 */
516#define ADC_SC1_COUNT (2U)
517
518/*! @name CFG1 - ADC Configuration Register 1 */
519/*! @{ */
520#define ADC_CFG1_ADICLK_MASK (0x3U)
521#define ADC_CFG1_ADICLK_SHIFT (0U)
522/*! ADICLK - Input Clock Select
523 * 0b00..Bus clock
524 * 0b01..Bus clock divided by 2(BUSCLK/2)
525 * 0b10..Alternate clock (ALTCLK)
526 * 0b11..Asynchronous clock (ADACK)
527 */
528#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
529#define ADC_CFG1_MODE_MASK (0xCU)
530#define ADC_CFG1_MODE_SHIFT (2U)
531/*! MODE - Conversion mode selection
532 * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
533 * 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
534 * 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
535 * 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
536 */
537#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
538#define ADC_CFG1_ADLSMP_MASK (0x10U)
539#define ADC_CFG1_ADLSMP_SHIFT (4U)
540/*! ADLSMP - Sample Time Configuration
541 * 0b0..Short sample time.
542 * 0b1..Long sample time.
543 */
544#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
545#define ADC_CFG1_ADIV_MASK (0x60U)
546#define ADC_CFG1_ADIV_SHIFT (5U)
547/*! ADIV - Clock Divide Select
548 * 0b00..The divide ratio is 1 and the clock rate is input clock.
549 * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2.
550 * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4.
551 * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.
552 */
553#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
554#define ADC_CFG1_ADLPC_MASK (0x80U)
555#define ADC_CFG1_ADLPC_SHIFT (7U)
556/*! ADLPC - Low-Power Configuration
557 * 0b0..Normal power configuration.
558 * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.
559 */
560#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
561/*! @} */
562
563/*! @name CFG2 - ADC Configuration Register 2 */
564/*! @{ */
565#define ADC_CFG2_ADLSTS_MASK (0x3U)
566#define ADC_CFG2_ADLSTS_SHIFT (0U)
567/*! ADLSTS - Long Sample Time Select
568 * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
569 * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time.
570 * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time.
571 * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.
572 */
573#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
574#define ADC_CFG2_ADHSC_MASK (0x4U)
575#define ADC_CFG2_ADHSC_SHIFT (2U)
576/*! ADHSC - High-Speed Configuration
577 * 0b0..Normal conversion sequence selected.
578 * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
579 */
580#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
581#define ADC_CFG2_ADACKEN_MASK (0x8U)
582#define ADC_CFG2_ADACKEN_SHIFT (3U)
583/*! ADACKEN - Asynchronous Clock Output Enable
584 * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
585 * 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.
586 */
587#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
588#define ADC_CFG2_MUXSEL_MASK (0x10U)
589#define ADC_CFG2_MUXSEL_SHIFT (4U)
590/*! MUXSEL - ADC Mux Select
591 * 0b0..ADxxa channels are selected.
592 * 0b1..ADxxb channels are selected.
593 */
594#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
595/*! @} */
596
597/*! @name R - ADC Data Result Register */
598/*! @{ */
599#define ADC_R_D_MASK (0xFFFFU)
600#define ADC_R_D_SHIFT (0U)
601#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
602/*! @} */
603
604/* The count of ADC_R */
605#define ADC_R_COUNT (2U)
606
607/*! @name CV1 - Compare Value Registers */
608/*! @{ */
609#define ADC_CV1_CV_MASK (0xFFFFU)
610#define ADC_CV1_CV_SHIFT (0U)
611#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
612/*! @} */
613
614/*! @name CV2 - Compare Value Registers */
615/*! @{ */
616#define ADC_CV2_CV_MASK (0xFFFFU)
617#define ADC_CV2_CV_SHIFT (0U)
618#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
619/*! @} */
620
621/*! @name SC2 - Status and Control Register 2 */
622/*! @{ */
623#define ADC_SC2_REFSEL_MASK (0x3U)
624#define ADC_SC2_REFSEL_SHIFT (0U)
625/*! REFSEL - Voltage Reference Selection
626 * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL
627 * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
628 * 0b10..Reserved
629 * 0b11..Reserved
630 */
631#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
632#define ADC_SC2_DMAEN_MASK (0x4U)
633#define ADC_SC2_DMAEN_SHIFT (2U)
634/*! DMAEN - DMA Enable
635 * 0b0..DMA is disabled.
636 * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
637 */
638#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
639#define ADC_SC2_ACREN_MASK (0x8U)
640#define ADC_SC2_ACREN_SHIFT (3U)
641/*! ACREN - Compare Function Range Enable
642 * 0b0..Range function disabled. Only CV1 is compared.
643 * 0b1..Range function enabled. Both CV1 and CV2 are compared.
644 */
645#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
646#define ADC_SC2_ACFGT_MASK (0x10U)
647#define ADC_SC2_ACFGT_SHIFT (4U)
648/*! ACFGT - Compare Function Greater Than Enable
649 * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
650 * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
651 */
652#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
653#define ADC_SC2_ACFE_MASK (0x20U)
654#define ADC_SC2_ACFE_SHIFT (5U)
655/*! ACFE - Compare Function Enable
656 * 0b0..Compare function disabled.
657 * 0b1..Compare function enabled.
658 */
659#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
660#define ADC_SC2_ADTRG_MASK (0x40U)
661#define ADC_SC2_ADTRG_SHIFT (6U)
662/*! ADTRG - Conversion Trigger Select
663 * 0b0..Software trigger selected.
664 * 0b1..Hardware trigger selected.
665 */
666#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
667#define ADC_SC2_ADACT_MASK (0x80U)
668#define ADC_SC2_ADACT_SHIFT (7U)
669/*! ADACT - Conversion Active
670 * 0b0..Conversion not in progress.
671 * 0b1..Conversion in progress.
672 */
673#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
674/*! @} */
675
676/*! @name SC3 - Status and Control Register 3 */
677/*! @{ */
678#define ADC_SC3_AVGS_MASK (0x3U)
679#define ADC_SC3_AVGS_SHIFT (0U)
680/*! AVGS - Hardware Average Select
681 * 0b00..4 samples averaged.
682 * 0b01..8 samples averaged.
683 * 0b10..16 samples averaged.
684 * 0b11..32 samples averaged.
685 */
686#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
687#define ADC_SC3_AVGE_MASK (0x4U)
688#define ADC_SC3_AVGE_SHIFT (2U)
689/*! AVGE - Hardware Average Enable
690 * 0b0..Hardware average function disabled.
691 * 0b1..Hardware average function enabled.
692 */
693#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
694#define ADC_SC3_ADCO_MASK (0x8U)
695#define ADC_SC3_ADCO_SHIFT (3U)
696/*! ADCO - Continuous Conversion Enable
697 * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
698 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
699 */
700#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
701#define ADC_SC3_CALF_MASK (0x40U)
702#define ADC_SC3_CALF_SHIFT (6U)
703/*! CALF - Calibration Failed Flag
704 * 0b0..Calibration completed normally.
705 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
706 */
707#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
708#define ADC_SC3_CAL_MASK (0x80U)
709#define ADC_SC3_CAL_SHIFT (7U)
710#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
711/*! @} */
712
713/*! @name OFS - ADC Offset Correction Register */
714/*! @{ */
715#define ADC_OFS_OFS_MASK (0xFFFFU)
716#define ADC_OFS_OFS_SHIFT (0U)
717#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
718/*! @} */
719
720/*! @name PG - ADC Plus-Side Gain Register */
721/*! @{ */
722#define ADC_PG_PG_MASK (0xFFFFU)
723#define ADC_PG_PG_SHIFT (0U)
724#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
725/*! @} */
726
727/*! @name MG - ADC Minus-Side Gain Register */
728/*! @{ */
729#define ADC_MG_MG_MASK (0xFFFFU)
730#define ADC_MG_MG_SHIFT (0U)
731#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
732/*! @} */
733
734/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
735/*! @{ */
736#define ADC_CLPD_CLPD_MASK (0x3FU)
737#define ADC_CLPD_CLPD_SHIFT (0U)
738#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
739/*! @} */
740
741/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
742/*! @{ */
743#define ADC_CLPS_CLPS_MASK (0x3FU)
744#define ADC_CLPS_CLPS_SHIFT (0U)
745#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
746/*! @} */
747
748/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
749/*! @{ */
750#define ADC_CLP4_CLP4_MASK (0x3FFU)
751#define ADC_CLP4_CLP4_SHIFT (0U)
752#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
753/*! @} */
754
755/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
756/*! @{ */
757#define ADC_CLP3_CLP3_MASK (0x1FFU)
758#define ADC_CLP3_CLP3_SHIFT (0U)
759#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
760/*! @} */
761
762/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
763/*! @{ */
764#define ADC_CLP2_CLP2_MASK (0xFFU)
765#define ADC_CLP2_CLP2_SHIFT (0U)
766#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
767/*! @} */
768
769/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
770/*! @{ */
771#define ADC_CLP1_CLP1_MASK (0x7FU)
772#define ADC_CLP1_CLP1_SHIFT (0U)
773#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
774/*! @} */
775
776/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
777/*! @{ */
778#define ADC_CLP0_CLP0_MASK (0x3FU)
779#define ADC_CLP0_CLP0_SHIFT (0U)
780#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
781/*! @} */
782
783/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
784/*! @{ */
785#define ADC_CLMD_CLMD_MASK (0x3FU)
786#define ADC_CLMD_CLMD_SHIFT (0U)
787#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
788/*! @} */
789
790/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
791/*! @{ */
792#define ADC_CLMS_CLMS_MASK (0x3FU)
793#define ADC_CLMS_CLMS_SHIFT (0U)
794#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
795/*! @} */
796
797/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
798/*! @{ */
799#define ADC_CLM4_CLM4_MASK (0x3FFU)
800#define ADC_CLM4_CLM4_SHIFT (0U)
801#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
802/*! @} */
803
804/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
805/*! @{ */
806#define ADC_CLM3_CLM3_MASK (0x1FFU)
807#define ADC_CLM3_CLM3_SHIFT (0U)
808#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
809/*! @} */
810
811/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
812/*! @{ */
813#define ADC_CLM2_CLM2_MASK (0xFFU)
814#define ADC_CLM2_CLM2_SHIFT (0U)
815#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
816/*! @} */
817
818/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
819/*! @{ */
820#define ADC_CLM1_CLM1_MASK (0x7FU)
821#define ADC_CLM1_CLM1_SHIFT (0U)
822#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
823/*! @} */
824
825/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
826/*! @{ */
827#define ADC_CLM0_CLM0_MASK (0x3FU)
828#define ADC_CLM0_CLM0_SHIFT (0U)
829#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
830/*! @} */
831
832
833/*!
834 * @}
835 */ /* end of group ADC_Register_Masks */
836
837
838/* ADC - Peripheral instance base addresses */
839/** Peripheral ADC0 base address */
840#define ADC0_BASE (0x4003B000u)
841/** Peripheral ADC0 base pointer */
842#define ADC0 ((ADC_Type *)ADC0_BASE)
843/** Peripheral ADC1 base address */
844#define ADC1_BASE (0x400BB000u)
845/** Peripheral ADC1 base pointer */
846#define ADC1 ((ADC_Type *)ADC1_BASE)
847/** Array initializer of ADC peripheral base addresses */
848#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
849/** Array initializer of ADC peripheral base pointers */
850#define ADC_BASE_PTRS { ADC0, ADC1 }
851/** Interrupt vectors for the ADC peripheral type */
852#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
853
854/*!
855 * @}
856 */ /* end of group ADC_Peripheral_Access_Layer */
857
858
859/* ----------------------------------------------------------------------------
860 -- AIPS Peripheral Access Layer
861 ---------------------------------------------------------------------------- */
862
863/*!
864 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
865 * @{
866 */
867
868/** AIPS - Register Layout Typedef */
869typedef struct {
870 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
871 uint8_t RESERVED_0[28];
872 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
873 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
874 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
875 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
876 uint8_t RESERVED_1[16];
877 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
878 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
879 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
880 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
881 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
882 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
883 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
884 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
885 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
886 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
887 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
888 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
889} AIPS_Type;
890
891/* ----------------------------------------------------------------------------
892 -- AIPS Register Masks
893 ---------------------------------------------------------------------------- */
894
895/*!
896 * @addtogroup AIPS_Register_Masks AIPS Register Masks
897 * @{
898 */
899
900/*! @name MPRA - Master Privilege Register A */
901/*! @{ */
902#define AIPS_MPRA_MPL6_MASK (0x10U)
903#define AIPS_MPRA_MPL6_SHIFT (4U)
904/*! MPL6 - Master 6 Privilege Level
905 * 0b0..Accesses from this master are forced to user-mode.
906 * 0b1..Accesses from this master are not forced to user-mode.
907 */
908#define AIPS_MPRA_MPL6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)
909#define AIPS_MPRA_MTW6_MASK (0x20U)
910#define AIPS_MPRA_MTW6_SHIFT (5U)
911/*! MTW6 - Master 6 Trusted for Writes
912 * 0b0..This master is not trusted for write accesses.
913 * 0b1..This master is trusted for write accesses.
914 */
915#define AIPS_MPRA_MTW6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)
916#define AIPS_MPRA_MTR6_MASK (0x40U)
917#define AIPS_MPRA_MTR6_SHIFT (6U)
918/*! MTR6 - Master 6 Trusted for Read
919 * 0b0..This master is not trusted for read accesses.
920 * 0b1..This master is trusted for read accesses.
921 */
922#define AIPS_MPRA_MTR6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)
923#define AIPS_MPRA_MPL5_MASK (0x100U)
924#define AIPS_MPRA_MPL5_SHIFT (8U)
925/*! MPL5 - Master 5 Privilege Level
926 * 0b0..Accesses from this master are forced to user-mode.
927 * 0b1..Accesses from this master are not forced to user-mode.
928 */
929#define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
930#define AIPS_MPRA_MTW5_MASK (0x200U)
931#define AIPS_MPRA_MTW5_SHIFT (9U)
932/*! MTW5 - Master 5 Trusted For Writes
933 * 0b0..This master is not trusted for write accesses.
934 * 0b1..This master is trusted for write accesses.
935 */
936#define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
937#define AIPS_MPRA_MTR5_MASK (0x400U)
938#define AIPS_MPRA_MTR5_SHIFT (10U)
939/*! MTR5 - Master 5 Trusted For Read
940 * 0b0..This master is not trusted for read accesses.
941 * 0b1..This master is trusted for read accesses.
942 */
943#define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
944#define AIPS_MPRA_MPL4_MASK (0x1000U)
945#define AIPS_MPRA_MPL4_SHIFT (12U)
946/*! MPL4 - Master 4 Privilege Level
947 * 0b0..Accesses from this master are forced to user-mode.
948 * 0b1..Accesses from this master are not forced to user-mode.
949 */
950#define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
951#define AIPS_MPRA_MTW4_MASK (0x2000U)
952#define AIPS_MPRA_MTW4_SHIFT (13U)
953/*! MTW4 - Master 4 Trusted For Writes
954 * 0b0..This master is not trusted for write accesses.
955 * 0b1..This master is trusted for write accesses.
956 */
957#define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
958#define AIPS_MPRA_MTR4_MASK (0x4000U)
959#define AIPS_MPRA_MTR4_SHIFT (14U)
960/*! MTR4 - Master 4 Trusted For Read
961 * 0b0..This master is not trusted for read accesses.
962 * 0b1..This master is trusted for read accesses.
963 */
964#define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
965#define AIPS_MPRA_MPL3_MASK (0x10000U)
966#define AIPS_MPRA_MPL3_SHIFT (16U)
967/*! MPL3 - Master 3 Privilege Level
968 * 0b0..Accesses from this master are forced to user-mode.
969 * 0b1..Accesses from this master are not forced to user-mode.
970 */
971#define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
972#define AIPS_MPRA_MTW3_MASK (0x20000U)
973#define AIPS_MPRA_MTW3_SHIFT (17U)
974/*! MTW3 - Master 3 Trusted For Writes
975 * 0b0..This master is not trusted for write accesses.
976 * 0b1..This master is trusted for write accesses.
977 */
978#define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
979#define AIPS_MPRA_MTR3_MASK (0x40000U)
980#define AIPS_MPRA_MTR3_SHIFT (18U)
981/*! MTR3 - Master 3 Trusted For Read
982 * 0b0..This master is not trusted for read accesses.
983 * 0b1..This master is trusted for read accesses.
984 */
985#define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
986#define AIPS_MPRA_MPL2_MASK (0x100000U)
987#define AIPS_MPRA_MPL2_SHIFT (20U)
988/*! MPL2 - Master 2 Privilege Level
989 * 0b0..Accesses from this master are forced to user-mode.
990 * 0b1..Accesses from this master are not forced to user-mode.
991 */
992#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
993#define AIPS_MPRA_MTW2_MASK (0x200000U)
994#define AIPS_MPRA_MTW2_SHIFT (21U)
995/*! MTW2 - Master 2 Trusted For Writes
996 * 0b0..This master is not trusted for write accesses.
997 * 0b1..This master is trusted for write accesses.
998 */
999#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
1000#define AIPS_MPRA_MTR2_MASK (0x400000U)
1001#define AIPS_MPRA_MTR2_SHIFT (22U)
1002/*! MTR2 - Master 2 Trusted For Read
1003 * 0b0..This master is not trusted for read accesses.
1004 * 0b1..This master is trusted for read accesses.
1005 */
1006#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
1007#define AIPS_MPRA_MPL1_MASK (0x1000000U)
1008#define AIPS_MPRA_MPL1_SHIFT (24U)
1009/*! MPL1 - Master 1 Privilege Level
1010 * 0b0..Accesses from this master are forced to user-mode.
1011 * 0b1..Accesses from this master are not forced to user-mode.
1012 */
1013#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
1014#define AIPS_MPRA_MTW1_MASK (0x2000000U)
1015#define AIPS_MPRA_MTW1_SHIFT (25U)
1016/*! MTW1 - Master 1 Trusted for Writes
1017 * 0b0..This master is not trusted for write accesses.
1018 * 0b1..This master is trusted for write accesses.
1019 */
1020#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
1021#define AIPS_MPRA_MTR1_MASK (0x4000000U)
1022#define AIPS_MPRA_MTR1_SHIFT (26U)
1023/*! MTR1 - Master 1 Trusted for Read
1024 * 0b0..This master is not trusted for read accesses.
1025 * 0b1..This master is trusted for read accesses.
1026 */
1027#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
1028#define AIPS_MPRA_MPL0_MASK (0x10000000U)
1029#define AIPS_MPRA_MPL0_SHIFT (28U)
1030/*! MPL0 - Master 0 Privilege Level
1031 * 0b0..Accesses from this master are forced to user-mode.
1032 * 0b1..Accesses from this master are not forced to user-mode.
1033 */
1034#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
1035#define AIPS_MPRA_MTW0_MASK (0x20000000U)
1036#define AIPS_MPRA_MTW0_SHIFT (29U)
1037/*! MTW0 - Master 0 Trusted For Writes
1038 * 0b0..This master is not trusted for write accesses.
1039 * 0b1..This master is trusted for write accesses.
1040 */
1041#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
1042#define AIPS_MPRA_MTR0_MASK (0x40000000U)
1043#define AIPS_MPRA_MTR0_SHIFT (30U)
1044/*! MTR0 - Master 0 Trusted For Read
1045 * 0b0..This master is not trusted for read accesses.
1046 * 0b1..This master is trusted for read accesses.
1047 */
1048#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
1049/*! @} */
1050
1051/*! @name PACRA - Peripheral Access Control Register */
1052/*! @{ */
1053#define AIPS_PACRA_TP7_MASK (0x1U)
1054#define AIPS_PACRA_TP7_SHIFT (0U)
1055/*! TP7 - Trusted Protect
1056 * 0b0..Accesses from an untrusted master are allowed.
1057 * 0b1..Accesses from an untrusted master are not allowed.
1058 */
1059#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
1060#define AIPS_PACRA_WP7_MASK (0x2U)
1061#define AIPS_PACRA_WP7_SHIFT (1U)
1062/*! WP7 - Write Protect
1063 * 0b0..This peripheral allows write accesses.
1064 * 0b1..This peripheral is write protected.
1065 */
1066#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
1067#define AIPS_PACRA_SP7_MASK (0x4U)
1068#define AIPS_PACRA_SP7_SHIFT (2U)
1069/*! SP7 - Supervisor Protect
1070 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1071 * 0b1..This peripheral requires supervisor privilege level for accesses.
1072 */
1073#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
1074#define AIPS_PACRA_TP6_MASK (0x10U)
1075#define AIPS_PACRA_TP6_SHIFT (4U)
1076/*! TP6 - Trusted Protect
1077 * 0b0..Accesses from an untrusted master are allowed.
1078 * 0b1..Accesses from an untrusted master are not allowed.
1079 */
1080#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
1081#define AIPS_PACRA_WP6_MASK (0x20U)
1082#define AIPS_PACRA_WP6_SHIFT (5U)
1083/*! WP6 - Write Protect
1084 * 0b0..This peripheral allows write accesses.
1085 * 0b1..This peripheral is write protected.
1086 */
1087#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
1088#define AIPS_PACRA_SP6_MASK (0x40U)
1089#define AIPS_PACRA_SP6_SHIFT (6U)
1090/*! SP6 - Supervisor Protect
1091 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1092 * 0b1..This peripheral requires supervisor privilege level for accesses.
1093 */
1094#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
1095#define AIPS_PACRA_TP5_MASK (0x100U)
1096#define AIPS_PACRA_TP5_SHIFT (8U)
1097/*! TP5 - Trusted Protect
1098 * 0b0..Accesses from an untrusted master are allowed.
1099 * 0b1..Accesses from an untrusted master are not allowed.
1100 */
1101#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
1102#define AIPS_PACRA_WP5_MASK (0x200U)
1103#define AIPS_PACRA_WP5_SHIFT (9U)
1104/*! WP5 - Write Protect
1105 * 0b0..This peripheral allows write accesses.
1106 * 0b1..This peripheral is write protected.
1107 */
1108#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
1109#define AIPS_PACRA_SP5_MASK (0x400U)
1110#define AIPS_PACRA_SP5_SHIFT (10U)
1111/*! SP5 - Supervisor Protect
1112 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1113 * 0b1..This peripheral requires supervisor privilege level for accesses.
1114 */
1115#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
1116#define AIPS_PACRA_TP4_MASK (0x1000U)
1117#define AIPS_PACRA_TP4_SHIFT (12U)
1118/*! TP4 - Trusted Protect
1119 * 0b0..Accesses from an untrusted master are allowed.
1120 * 0b1..Accesses from an untrusted master are not allowed.
1121 */
1122#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
1123#define AIPS_PACRA_WP4_MASK (0x2000U)
1124#define AIPS_PACRA_WP4_SHIFT (13U)
1125/*! WP4 - Write Protect
1126 * 0b0..This peripheral allows write accesses.
1127 * 0b1..This peripheral is write protected.
1128 */
1129#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
1130#define AIPS_PACRA_SP4_MASK (0x4000U)
1131#define AIPS_PACRA_SP4_SHIFT (14U)
1132/*! SP4 - Supervisor Protect
1133 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1134 * 0b1..This peripheral requires supervisor privilege level for accesses.
1135 */
1136#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
1137#define AIPS_PACRA_TP3_MASK (0x10000U)
1138#define AIPS_PACRA_TP3_SHIFT (16U)
1139/*! TP3 - Trusted Protect
1140 * 0b0..Accesses from an untrusted master are allowed.
1141 * 0b1..Accesses from an untrusted master are not allowed.
1142 */
1143#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
1144#define AIPS_PACRA_WP3_MASK (0x20000U)
1145#define AIPS_PACRA_WP3_SHIFT (17U)
1146/*! WP3 - Write Protect
1147 * 0b0..This peripheral allows write accesses.
1148 * 0b1..This peripheral is write protected.
1149 */
1150#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
1151#define AIPS_PACRA_SP3_MASK (0x40000U)
1152#define AIPS_PACRA_SP3_SHIFT (18U)
1153/*! SP3 - Supervisor Protect
1154 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1155 * 0b1..This peripheral requires supervisor privilege level for accesses.
1156 */
1157#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
1158#define AIPS_PACRA_TP2_MASK (0x100000U)
1159#define AIPS_PACRA_TP2_SHIFT (20U)
1160/*! TP2 - Trusted Protect
1161 * 0b0..Accesses from an untrusted master are allowed.
1162 * 0b1..Accesses from an untrusted master are not allowed.
1163 */
1164#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
1165#define AIPS_PACRA_WP2_MASK (0x200000U)
1166#define AIPS_PACRA_WP2_SHIFT (21U)
1167/*! WP2 - Write Protect
1168 * 0b0..This peripheral allows write accesses.
1169 * 0b1..This peripheral is write protected.
1170 */
1171#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
1172#define AIPS_PACRA_SP2_MASK (0x400000U)
1173#define AIPS_PACRA_SP2_SHIFT (22U)
1174/*! SP2 - Supervisor Protect
1175 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1176 * 0b1..This peripheral requires supervisor privilege level for accesses.
1177 */
1178#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
1179#define AIPS_PACRA_TP1_MASK (0x1000000U)
1180#define AIPS_PACRA_TP1_SHIFT (24U)
1181/*! TP1 - Trusted Protect
1182 * 0b0..Accesses from an untrusted master are allowed.
1183 * 0b1..Accesses from an untrusted master are not allowed.
1184 */
1185#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
1186#define AIPS_PACRA_WP1_MASK (0x2000000U)
1187#define AIPS_PACRA_WP1_SHIFT (25U)
1188/*! WP1 - Write Protect
1189 * 0b0..This peripheral allows write accesses.
1190 * 0b1..This peripheral is write protected.
1191 */
1192#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
1193#define AIPS_PACRA_SP1_MASK (0x4000000U)
1194#define AIPS_PACRA_SP1_SHIFT (26U)
1195/*! SP1 - Supervisor Protect
1196 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1197 * 0b1..This peripheral requires supervisor privilege level for accesses.
1198 */
1199#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
1200#define AIPS_PACRA_TP0_MASK (0x10000000U)
1201#define AIPS_PACRA_TP0_SHIFT (28U)
1202/*! TP0 - Trusted Protect
1203 * 0b0..Accesses from an untrusted master are allowed.
1204 * 0b1..Accesses from an untrusted master are not allowed.
1205 */
1206#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
1207#define AIPS_PACRA_WP0_MASK (0x20000000U)
1208#define AIPS_PACRA_WP0_SHIFT (29U)
1209/*! WP0 - Write Protect
1210 * 0b0..This peripheral allows write accesses.
1211 * 0b1..This peripheral is write protected.
1212 */
1213#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
1214#define AIPS_PACRA_SP0_MASK (0x40000000U)
1215#define AIPS_PACRA_SP0_SHIFT (30U)
1216/*! SP0 - Supervisor Protect
1217 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1218 * 0b1..This peripheral requires supervisor privilege level for accesses.
1219 */
1220#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
1221/*! @} */
1222
1223/*! @name PACRB - Peripheral Access Control Register */
1224/*! @{ */
1225#define AIPS_PACRB_TP7_MASK (0x1U)
1226#define AIPS_PACRB_TP7_SHIFT (0U)
1227/*! TP7 - Trusted Protect
1228 * 0b0..Accesses from an untrusted master are allowed.
1229 * 0b1..Accesses from an untrusted master are not allowed.
1230 */
1231#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
1232#define AIPS_PACRB_WP7_MASK (0x2U)
1233#define AIPS_PACRB_WP7_SHIFT (1U)
1234/*! WP7 - Write Protect
1235 * 0b0..This peripheral allows write accesses.
1236 * 0b1..This peripheral is write protected.
1237 */
1238#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
1239#define AIPS_PACRB_SP7_MASK (0x4U)
1240#define AIPS_PACRB_SP7_SHIFT (2U)
1241/*! SP7 - Supervisor Protect
1242 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1243 * 0b1..This peripheral requires supervisor privilege level for accesses.
1244 */
1245#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
1246#define AIPS_PACRB_TP6_MASK (0x10U)
1247#define AIPS_PACRB_TP6_SHIFT (4U)
1248/*! TP6 - Trusted Protect
1249 * 0b0..Accesses from an untrusted master are allowed.
1250 * 0b1..Accesses from an untrusted master are not allowed.
1251 */
1252#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
1253#define AIPS_PACRB_WP6_MASK (0x20U)
1254#define AIPS_PACRB_WP6_SHIFT (5U)
1255/*! WP6 - Write Protect
1256 * 0b0..This peripheral allows write accesses.
1257 * 0b1..This peripheral is write protected.
1258 */
1259#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
1260#define AIPS_PACRB_SP6_MASK (0x40U)
1261#define AIPS_PACRB_SP6_SHIFT (6U)
1262/*! SP6 - Supervisor Protect
1263 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1264 * 0b1..This peripheral requires supervisor privilege level for accesses.
1265 */
1266#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
1267#define AIPS_PACRB_TP5_MASK (0x100U)
1268#define AIPS_PACRB_TP5_SHIFT (8U)
1269/*! TP5 - Trusted Protect
1270 * 0b0..Accesses from an untrusted master are allowed.
1271 * 0b1..Accesses from an untrusted master are not allowed.
1272 */
1273#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
1274#define AIPS_PACRB_WP5_MASK (0x200U)
1275#define AIPS_PACRB_WP5_SHIFT (9U)
1276/*! WP5 - Write Protect
1277 * 0b0..This peripheral allows write accesses.
1278 * 0b1..This peripheral is write protected.
1279 */
1280#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
1281#define AIPS_PACRB_SP5_MASK (0x400U)
1282#define AIPS_PACRB_SP5_SHIFT (10U)
1283/*! SP5 - Supervisor Protect
1284 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1285 * 0b1..This peripheral requires supervisor privilege level for accesses.
1286 */
1287#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
1288#define AIPS_PACRB_TP4_MASK (0x1000U)
1289#define AIPS_PACRB_TP4_SHIFT (12U)
1290/*! TP4 - Trusted Protect
1291 * 0b0..Accesses from an untrusted master are allowed.
1292 * 0b1..Accesses from an untrusted master are not allowed.
1293 */
1294#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
1295#define AIPS_PACRB_WP4_MASK (0x2000U)
1296#define AIPS_PACRB_WP4_SHIFT (13U)
1297/*! WP4 - Write Protect
1298 * 0b0..This peripheral allows write accesses.
1299 * 0b1..This peripheral is write protected.
1300 */
1301#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
1302#define AIPS_PACRB_SP4_MASK (0x4000U)
1303#define AIPS_PACRB_SP4_SHIFT (14U)
1304/*! SP4 - Supervisor Protect
1305 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1306 * 0b1..This peripheral requires supervisor privilege level for accesses.
1307 */
1308#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
1309#define AIPS_PACRB_TP3_MASK (0x10000U)
1310#define AIPS_PACRB_TP3_SHIFT (16U)
1311/*! TP3 - Trusted Protect
1312 * 0b0..Accesses from an untrusted master are allowed.
1313 * 0b1..Accesses from an untrusted master are not allowed.
1314 */
1315#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
1316#define AIPS_PACRB_WP3_MASK (0x20000U)
1317#define AIPS_PACRB_WP3_SHIFT (17U)
1318/*! WP3 - Write Protect
1319 * 0b0..This peripheral allows write accesses.
1320 * 0b1..This peripheral is write protected.
1321 */
1322#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
1323#define AIPS_PACRB_SP3_MASK (0x40000U)
1324#define AIPS_PACRB_SP3_SHIFT (18U)
1325/*! SP3 - Supervisor Protect
1326 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1327 * 0b1..This peripheral requires supervisor privilege level for accesses.
1328 */
1329#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
1330#define AIPS_PACRB_TP2_MASK (0x100000U)
1331#define AIPS_PACRB_TP2_SHIFT (20U)
1332/*! TP2 - Trusted Protect
1333 * 0b0..Accesses from an untrusted master are allowed.
1334 * 0b1..Accesses from an untrusted master are not allowed.
1335 */
1336#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
1337#define AIPS_PACRB_WP2_MASK (0x200000U)
1338#define AIPS_PACRB_WP2_SHIFT (21U)
1339/*! WP2 - Write Protect
1340 * 0b0..This peripheral allows write accesses.
1341 * 0b1..This peripheral is write protected.
1342 */
1343#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
1344#define AIPS_PACRB_SP2_MASK (0x400000U)
1345#define AIPS_PACRB_SP2_SHIFT (22U)
1346/*! SP2 - Supervisor Protect
1347 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1348 * 0b1..This peripheral requires supervisor privilege level for accesses.
1349 */
1350#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
1351#define AIPS_PACRB_TP1_MASK (0x1000000U)
1352#define AIPS_PACRB_TP1_SHIFT (24U)
1353/*! TP1 - Trusted Protect
1354 * 0b0..Accesses from an untrusted master are allowed.
1355 * 0b1..Accesses from an untrusted master are not allowed.
1356 */
1357#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
1358#define AIPS_PACRB_WP1_MASK (0x2000000U)
1359#define AIPS_PACRB_WP1_SHIFT (25U)
1360/*! WP1 - Write Protect
1361 * 0b0..This peripheral allows write accesses.
1362 * 0b1..This peripheral is write protected.
1363 */
1364#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
1365#define AIPS_PACRB_SP1_MASK (0x4000000U)
1366#define AIPS_PACRB_SP1_SHIFT (26U)
1367/*! SP1 - Supervisor Protect
1368 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1369 * 0b1..This peripheral requires supervisor privilege level for accesses.
1370 */
1371#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
1372#define AIPS_PACRB_TP0_MASK (0x10000000U)
1373#define AIPS_PACRB_TP0_SHIFT (28U)
1374/*! TP0 - Trusted Protect
1375 * 0b0..Accesses from an untrusted master are allowed.
1376 * 0b1..Accesses from an untrusted master are not allowed.
1377 */
1378#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
1379#define AIPS_PACRB_WP0_MASK (0x20000000U)
1380#define AIPS_PACRB_WP0_SHIFT (29U)
1381/*! WP0 - Write Protect
1382 * 0b0..This peripheral allows write accesses.
1383 * 0b1..This peripheral is write protected.
1384 */
1385#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
1386#define AIPS_PACRB_SP0_MASK (0x40000000U)
1387#define AIPS_PACRB_SP0_SHIFT (30U)
1388/*! SP0 - Supervisor Protect
1389 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1390 * 0b1..This peripheral requires supervisor privilege level for accesses.
1391 */
1392#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
1393/*! @} */
1394
1395/*! @name PACRC - Peripheral Access Control Register */
1396/*! @{ */
1397#define AIPS_PACRC_TP7_MASK (0x1U)
1398#define AIPS_PACRC_TP7_SHIFT (0U)
1399/*! TP7 - Trusted Protect
1400 * 0b0..Accesses from an untrusted master are allowed.
1401 * 0b1..Accesses from an untrusted master are not allowed.
1402 */
1403#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
1404#define AIPS_PACRC_WP7_MASK (0x2U)
1405#define AIPS_PACRC_WP7_SHIFT (1U)
1406/*! WP7 - Write Protect
1407 * 0b0..This peripheral allows write accesses.
1408 * 0b1..This peripheral is write protected.
1409 */
1410#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
1411#define AIPS_PACRC_SP7_MASK (0x4U)
1412#define AIPS_PACRC_SP7_SHIFT (2U)
1413/*! SP7 - Supervisor Protect
1414 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1415 * 0b1..This peripheral requires supervisor privilege level for accesses.
1416 */
1417#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
1418#define AIPS_PACRC_TP6_MASK (0x10U)
1419#define AIPS_PACRC_TP6_SHIFT (4U)
1420/*! TP6 - Trusted Protect
1421 * 0b0..Accesses from an untrusted master are allowed.
1422 * 0b1..Accesses from an untrusted master are not allowed.
1423 */
1424#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
1425#define AIPS_PACRC_WP6_MASK (0x20U)
1426#define AIPS_PACRC_WP6_SHIFT (5U)
1427/*! WP6 - Write Protect
1428 * 0b0..This peripheral allows write accesses.
1429 * 0b1..This peripheral is write protected.
1430 */
1431#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
1432#define AIPS_PACRC_SP6_MASK (0x40U)
1433#define AIPS_PACRC_SP6_SHIFT (6U)
1434/*! SP6 - Supervisor Protect
1435 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1436 * 0b1..This peripheral requires supervisor privilege level for accesses.
1437 */
1438#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
1439#define AIPS_PACRC_TP5_MASK (0x100U)
1440#define AIPS_PACRC_TP5_SHIFT (8U)
1441/*! TP5 - Trusted Protect
1442 * 0b0..Accesses from an untrusted master are allowed.
1443 * 0b1..Accesses from an untrusted master are not allowed.
1444 */
1445#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
1446#define AIPS_PACRC_WP5_MASK (0x200U)
1447#define AIPS_PACRC_WP5_SHIFT (9U)
1448/*! WP5 - Write Protect
1449 * 0b0..This peripheral allows write accesses.
1450 * 0b1..This peripheral is write protected.
1451 */
1452#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
1453#define AIPS_PACRC_SP5_MASK (0x400U)
1454#define AIPS_PACRC_SP5_SHIFT (10U)
1455/*! SP5 - Supervisor Protect
1456 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1457 * 0b1..This peripheral requires supervisor privilege level for accesses.
1458 */
1459#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
1460#define AIPS_PACRC_TP4_MASK (0x1000U)
1461#define AIPS_PACRC_TP4_SHIFT (12U)
1462/*! TP4 - Trusted Protect
1463 * 0b0..Accesses from an untrusted master are allowed.
1464 * 0b1..Accesses from an untrusted master are not allowed.
1465 */
1466#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
1467#define AIPS_PACRC_WP4_MASK (0x2000U)
1468#define AIPS_PACRC_WP4_SHIFT (13U)
1469/*! WP4 - Write Protect
1470 * 0b0..This peripheral allows write accesses.
1471 * 0b1..This peripheral is write protected.
1472 */
1473#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
1474#define AIPS_PACRC_SP4_MASK (0x4000U)
1475#define AIPS_PACRC_SP4_SHIFT (14U)
1476/*! SP4 - Supervisor Protect
1477 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1478 * 0b1..This peripheral requires supervisor privilege level for accesses.
1479 */
1480#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
1481#define AIPS_PACRC_TP3_MASK (0x10000U)
1482#define AIPS_PACRC_TP3_SHIFT (16U)
1483/*! TP3 - Trusted Protect
1484 * 0b0..Accesses from an untrusted master are allowed.
1485 * 0b1..Accesses from an untrusted master are not allowed.
1486 */
1487#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
1488#define AIPS_PACRC_WP3_MASK (0x20000U)
1489#define AIPS_PACRC_WP3_SHIFT (17U)
1490/*! WP3 - Write Protect
1491 * 0b0..This peripheral allows write accesses.
1492 * 0b1..This peripheral is write protected.
1493 */
1494#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
1495#define AIPS_PACRC_SP3_MASK (0x40000U)
1496#define AIPS_PACRC_SP3_SHIFT (18U)
1497/*! SP3 - Supervisor Protect
1498 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1499 * 0b1..This peripheral requires supervisor privilege level for accesses.
1500 */
1501#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
1502#define AIPS_PACRC_TP2_MASK (0x100000U)
1503#define AIPS_PACRC_TP2_SHIFT (20U)
1504/*! TP2 - Trusted Protect
1505 * 0b0..Accesses from an untrusted master are allowed.
1506 * 0b1..Accesses from an untrusted master are not allowed.
1507 */
1508#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
1509#define AIPS_PACRC_WP2_MASK (0x200000U)
1510#define AIPS_PACRC_WP2_SHIFT (21U)
1511/*! WP2 - Write Protect
1512 * 0b0..This peripheral allows write accesses.
1513 * 0b1..This peripheral is write protected.
1514 */
1515#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
1516#define AIPS_PACRC_SP2_MASK (0x400000U)
1517#define AIPS_PACRC_SP2_SHIFT (22U)
1518/*! SP2 - Supervisor Protect
1519 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1520 * 0b1..This peripheral requires supervisor privilege level for accesses.
1521 */
1522#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
1523#define AIPS_PACRC_TP1_MASK (0x1000000U)
1524#define AIPS_PACRC_TP1_SHIFT (24U)
1525/*! TP1 - Trusted Protect
1526 * 0b0..Accesses from an untrusted master are allowed.
1527 * 0b1..Accesses from an untrusted master are not allowed.
1528 */
1529#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
1530#define AIPS_PACRC_WP1_MASK (0x2000000U)
1531#define AIPS_PACRC_WP1_SHIFT (25U)
1532/*! WP1 - Write Protect
1533 * 0b0..This peripheral allows write accesses.
1534 * 0b1..This peripheral is write protected.
1535 */
1536#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
1537#define AIPS_PACRC_SP1_MASK (0x4000000U)
1538#define AIPS_PACRC_SP1_SHIFT (26U)
1539/*! SP1 - Supervisor Protect
1540 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1541 * 0b1..This peripheral requires supervisor privilege level for accesses.
1542 */
1543#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
1544#define AIPS_PACRC_TP0_MASK (0x10000000U)
1545#define AIPS_PACRC_TP0_SHIFT (28U)
1546/*! TP0 - Trusted Protect
1547 * 0b0..Accesses from an untrusted master are allowed.
1548 * 0b1..Accesses from an untrusted master are not allowed.
1549 */
1550#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
1551#define AIPS_PACRC_WP0_MASK (0x20000000U)
1552#define AIPS_PACRC_WP0_SHIFT (29U)
1553/*! WP0 - Write Protect
1554 * 0b0..This peripheral allows write accesses.
1555 * 0b1..This peripheral is write protected.
1556 */
1557#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
1558#define AIPS_PACRC_SP0_MASK (0x40000000U)
1559#define AIPS_PACRC_SP0_SHIFT (30U)
1560/*! SP0 - Supervisor Protect
1561 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1562 * 0b1..This peripheral requires supervisor privilege level for accesses.
1563 */
1564#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
1565/*! @} */
1566
1567/*! @name PACRD - Peripheral Access Control Register */
1568/*! @{ */
1569#define AIPS_PACRD_TP7_MASK (0x1U)
1570#define AIPS_PACRD_TP7_SHIFT (0U)
1571/*! TP7 - Trusted Protect
1572 * 0b0..Accesses from an untrusted master are allowed.
1573 * 0b1..Accesses from an untrusted master are not allowed.
1574 */
1575#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
1576#define AIPS_PACRD_WP7_MASK (0x2U)
1577#define AIPS_PACRD_WP7_SHIFT (1U)
1578/*! WP7 - Write Protect
1579 * 0b0..This peripheral allows write accesses.
1580 * 0b1..This peripheral is write protected.
1581 */
1582#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
1583#define AIPS_PACRD_SP7_MASK (0x4U)
1584#define AIPS_PACRD_SP7_SHIFT (2U)
1585/*! SP7 - Supervisor Protect
1586 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1587 * 0b1..This peripheral requires supervisor privilege level for accesses.
1588 */
1589#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
1590#define AIPS_PACRD_TP6_MASK (0x10U)
1591#define AIPS_PACRD_TP6_SHIFT (4U)
1592/*! TP6 - Trusted Protect
1593 * 0b0..Accesses from an untrusted master are allowed.
1594 * 0b1..Accesses from an untrusted master are not allowed.
1595 */
1596#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
1597#define AIPS_PACRD_WP6_MASK (0x20U)
1598#define AIPS_PACRD_WP6_SHIFT (5U)
1599/*! WP6 - Write Protect
1600 * 0b0..This peripheral allows write accesses.
1601 * 0b1..This peripheral is write protected.
1602 */
1603#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
1604#define AIPS_PACRD_SP6_MASK (0x40U)
1605#define AIPS_PACRD_SP6_SHIFT (6U)
1606/*! SP6 - Supervisor Protect
1607 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1608 * 0b1..This peripheral requires supervisor privilege level for accesses.
1609 */
1610#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
1611#define AIPS_PACRD_TP5_MASK (0x100U)
1612#define AIPS_PACRD_TP5_SHIFT (8U)
1613/*! TP5 - Trusted Protect
1614 * 0b0..Accesses from an untrusted master are allowed.
1615 * 0b1..Accesses from an untrusted master are not allowed.
1616 */
1617#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
1618#define AIPS_PACRD_WP5_MASK (0x200U)
1619#define AIPS_PACRD_WP5_SHIFT (9U)
1620/*! WP5 - Write Protect
1621 * 0b0..This peripheral allows write accesses.
1622 * 0b1..This peripheral is write protected.
1623 */
1624#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
1625#define AIPS_PACRD_SP5_MASK (0x400U)
1626#define AIPS_PACRD_SP5_SHIFT (10U)
1627/*! SP5 - Supervisor Protect
1628 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1629 * 0b1..This peripheral requires supervisor privilege level for accesses.
1630 */
1631#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
1632#define AIPS_PACRD_TP4_MASK (0x1000U)
1633#define AIPS_PACRD_TP4_SHIFT (12U)
1634/*! TP4 - Trusted Protect
1635 * 0b0..Accesses from an untrusted master are allowed.
1636 * 0b1..Accesses from an untrusted master are not allowed.
1637 */
1638#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
1639#define AIPS_PACRD_WP4_MASK (0x2000U)
1640#define AIPS_PACRD_WP4_SHIFT (13U)
1641/*! WP4 - Write Protect
1642 * 0b0..This peripheral allows write accesses.
1643 * 0b1..This peripheral is write protected.
1644 */
1645#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
1646#define AIPS_PACRD_SP4_MASK (0x4000U)
1647#define AIPS_PACRD_SP4_SHIFT (14U)
1648/*! SP4 - Supervisor Protect
1649 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1650 * 0b1..This peripheral requires supervisor privilege level for accesses.
1651 */
1652#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
1653#define AIPS_PACRD_TP3_MASK (0x10000U)
1654#define AIPS_PACRD_TP3_SHIFT (16U)
1655/*! TP3 - Trusted Protect
1656 * 0b0..Accesses from an untrusted master are allowed.
1657 * 0b1..Accesses from an untrusted master are not allowed.
1658 */
1659#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
1660#define AIPS_PACRD_WP3_MASK (0x20000U)
1661#define AIPS_PACRD_WP3_SHIFT (17U)
1662/*! WP3 - Write Protect
1663 * 0b0..This peripheral allows write accesses.
1664 * 0b1..This peripheral is write protected.
1665 */
1666#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
1667#define AIPS_PACRD_SP3_MASK (0x40000U)
1668#define AIPS_PACRD_SP3_SHIFT (18U)
1669/*! SP3 - Supervisor Protect
1670 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1671 * 0b1..This peripheral requires supervisor privilege level for accesses.
1672 */
1673#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
1674#define AIPS_PACRD_TP2_MASK (0x100000U)
1675#define AIPS_PACRD_TP2_SHIFT (20U)
1676/*! TP2 - Trusted Protect
1677 * 0b0..Accesses from an untrusted master are allowed.
1678 * 0b1..Accesses from an untrusted master are not allowed.
1679 */
1680#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
1681#define AIPS_PACRD_WP2_MASK (0x200000U)
1682#define AIPS_PACRD_WP2_SHIFT (21U)
1683/*! WP2 - Write Protect
1684 * 0b0..This peripheral allows write accesses.
1685 * 0b1..This peripheral is write protected.
1686 */
1687#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
1688#define AIPS_PACRD_SP2_MASK (0x400000U)
1689#define AIPS_PACRD_SP2_SHIFT (22U)
1690/*! SP2 - Supervisor Protect
1691 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1692 * 0b1..This peripheral requires supervisor privilege level for accesses.
1693 */
1694#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
1695#define AIPS_PACRD_TP1_MASK (0x1000000U)
1696#define AIPS_PACRD_TP1_SHIFT (24U)
1697/*! TP1 - Trusted Protect
1698 * 0b0..Accesses from an untrusted master are allowed.
1699 * 0b1..Accesses from an untrusted master are not allowed.
1700 */
1701#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
1702#define AIPS_PACRD_WP1_MASK (0x2000000U)
1703#define AIPS_PACRD_WP1_SHIFT (25U)
1704/*! WP1 - Write Protect
1705 * 0b0..This peripheral allows write accesses.
1706 * 0b1..This peripheral is write protected.
1707 */
1708#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
1709#define AIPS_PACRD_SP1_MASK (0x4000000U)
1710#define AIPS_PACRD_SP1_SHIFT (26U)
1711/*! SP1 - Supervisor Protect
1712 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1713 * 0b1..This peripheral requires supervisor privilege level for accesses.
1714 */
1715#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
1716#define AIPS_PACRD_TP0_MASK (0x10000000U)
1717#define AIPS_PACRD_TP0_SHIFT (28U)
1718/*! TP0 - Trusted Protect
1719 * 0b0..Accesses from an untrusted master are allowed.
1720 * 0b1..Accesses from an untrusted master are not allowed.
1721 */
1722#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
1723#define AIPS_PACRD_WP0_MASK (0x20000000U)
1724#define AIPS_PACRD_WP0_SHIFT (29U)
1725/*! WP0 - Write Protect
1726 * 0b0..This peripheral allows write accesses.
1727 * 0b1..This peripheral is write protected.
1728 */
1729#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
1730#define AIPS_PACRD_SP0_MASK (0x40000000U)
1731#define AIPS_PACRD_SP0_SHIFT (30U)
1732/*! SP0 - Supervisor Protect
1733 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1734 * 0b1..This peripheral requires supervisor privilege level for accesses.
1735 */
1736#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
1737/*! @} */
1738
1739/*! @name PACRE - Peripheral Access Control Register */
1740/*! @{ */
1741#define AIPS_PACRE_TP7_MASK (0x1U)
1742#define AIPS_PACRE_TP7_SHIFT (0U)
1743/*! TP7 - Trusted Protect
1744 * 0b0..Accesses from an untrusted master are allowed.
1745 * 0b1..Accesses from an untrusted master are not allowed.
1746 */
1747#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
1748#define AIPS_PACRE_WP7_MASK (0x2U)
1749#define AIPS_PACRE_WP7_SHIFT (1U)
1750/*! WP7 - Write Protect
1751 * 0b0..This peripheral allows write accesses.
1752 * 0b1..This peripheral is write protected.
1753 */
1754#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
1755#define AIPS_PACRE_SP7_MASK (0x4U)
1756#define AIPS_PACRE_SP7_SHIFT (2U)
1757/*! SP7 - Supervisor Protect
1758 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1759 * 0b1..This peripheral requires supervisor privilege level for accesses.
1760 */
1761#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
1762#define AIPS_PACRE_TP6_MASK (0x10U)
1763#define AIPS_PACRE_TP6_SHIFT (4U)
1764/*! TP6 - Trusted Protect
1765 * 0b0..Accesses from an untrusted master are allowed.
1766 * 0b1..Accesses from an untrusted master are not allowed.
1767 */
1768#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
1769#define AIPS_PACRE_WP6_MASK (0x20U)
1770#define AIPS_PACRE_WP6_SHIFT (5U)
1771/*! WP6 - Write Protect
1772 * 0b0..This peripheral allows write accesses.
1773 * 0b1..This peripheral is write protected.
1774 */
1775#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
1776#define AIPS_PACRE_SP6_MASK (0x40U)
1777#define AIPS_PACRE_SP6_SHIFT (6U)
1778/*! SP6 - Supervisor Protect
1779 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1780 * 0b1..This peripheral requires supervisor privilege level for accesses.
1781 */
1782#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
1783#define AIPS_PACRE_TP5_MASK (0x100U)
1784#define AIPS_PACRE_TP5_SHIFT (8U)
1785/*! TP5 - Trusted Protect
1786 * 0b0..Accesses from an untrusted master are allowed.
1787 * 0b1..Accesses from an untrusted master are not allowed.
1788 */
1789#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
1790#define AIPS_PACRE_WP5_MASK (0x200U)
1791#define AIPS_PACRE_WP5_SHIFT (9U)
1792/*! WP5 - Write Protect
1793 * 0b0..This peripheral allows write accesses.
1794 * 0b1..This peripheral is write protected.
1795 */
1796#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
1797#define AIPS_PACRE_SP5_MASK (0x400U)
1798#define AIPS_PACRE_SP5_SHIFT (10U)
1799/*! SP5 - Supervisor Protect
1800 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1801 * 0b1..This peripheral requires supervisor privilege level for accesses.
1802 */
1803#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
1804#define AIPS_PACRE_TP4_MASK (0x1000U)
1805#define AIPS_PACRE_TP4_SHIFT (12U)
1806/*! TP4 - Trusted Protect
1807 * 0b0..Accesses from an untrusted master are allowed.
1808 * 0b1..Accesses from an untrusted master are not allowed.
1809 */
1810#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
1811#define AIPS_PACRE_WP4_MASK (0x2000U)
1812#define AIPS_PACRE_WP4_SHIFT (13U)
1813/*! WP4 - Write Protect
1814 * 0b0..This peripheral allows write accesses.
1815 * 0b1..This peripheral is write protected.
1816 */
1817#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
1818#define AIPS_PACRE_SP4_MASK (0x4000U)
1819#define AIPS_PACRE_SP4_SHIFT (14U)
1820/*! SP4 - Supervisor Protect
1821 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1822 * 0b1..This peripheral requires supervisor privilege level for accesses.
1823 */
1824#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
1825#define AIPS_PACRE_TP3_MASK (0x10000U)
1826#define AIPS_PACRE_TP3_SHIFT (16U)
1827/*! TP3 - Trusted Protect
1828 * 0b0..Accesses from an untrusted master are allowed.
1829 * 0b1..Accesses from an untrusted master are not allowed.
1830 */
1831#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
1832#define AIPS_PACRE_WP3_MASK (0x20000U)
1833#define AIPS_PACRE_WP3_SHIFT (17U)
1834/*! WP3 - Write Protect
1835 * 0b0..This peripheral allows write accesses.
1836 * 0b1..This peripheral is write protected.
1837 */
1838#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
1839#define AIPS_PACRE_SP3_MASK (0x40000U)
1840#define AIPS_PACRE_SP3_SHIFT (18U)
1841/*! SP3 - Supervisor Protect
1842 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1843 * 0b1..This peripheral requires supervisor privilege level for accesses.
1844 */
1845#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
1846#define AIPS_PACRE_TP2_MASK (0x100000U)
1847#define AIPS_PACRE_TP2_SHIFT (20U)
1848/*! TP2 - Trusted Protect
1849 * 0b0..Accesses from an untrusted master are allowed.
1850 * 0b1..Accesses from an untrusted master are not allowed.
1851 */
1852#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
1853#define AIPS_PACRE_WP2_MASK (0x200000U)
1854#define AIPS_PACRE_WP2_SHIFT (21U)
1855/*! WP2 - Write Protect
1856 * 0b0..This peripheral allows write accesses.
1857 * 0b1..This peripheral is write protected.
1858 */
1859#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
1860#define AIPS_PACRE_SP2_MASK (0x400000U)
1861#define AIPS_PACRE_SP2_SHIFT (22U)
1862/*! SP2 - Supervisor Protect
1863 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1864 * 0b1..This peripheral requires supervisor privilege level for accesses.
1865 */
1866#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
1867#define AIPS_PACRE_TP1_MASK (0x1000000U)
1868#define AIPS_PACRE_TP1_SHIFT (24U)
1869/*! TP1 - Trusted Protect
1870 * 0b0..Accesses from an untrusted master are allowed.
1871 * 0b1..Accesses from an untrusted master are not allowed.
1872 */
1873#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
1874#define AIPS_PACRE_WP1_MASK (0x2000000U)
1875#define AIPS_PACRE_WP1_SHIFT (25U)
1876/*! WP1 - Write Protect
1877 * 0b0..This peripheral allows write accesses.
1878 * 0b1..This peripheral is write protected.
1879 */
1880#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
1881#define AIPS_PACRE_SP1_MASK (0x4000000U)
1882#define AIPS_PACRE_SP1_SHIFT (26U)
1883/*! SP1 - Supervisor Protect
1884 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1885 * 0b1..This peripheral requires supervisor privilege level for accesses.
1886 */
1887#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
1888#define AIPS_PACRE_TP0_MASK (0x10000000U)
1889#define AIPS_PACRE_TP0_SHIFT (28U)
1890/*! TP0 - Trusted Protect
1891 * 0b0..Accesses from an untrusted master are allowed.
1892 * 0b1..Accesses from an untrusted master are not allowed.
1893 */
1894#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
1895#define AIPS_PACRE_WP0_MASK (0x20000000U)
1896#define AIPS_PACRE_WP0_SHIFT (29U)
1897/*! WP0 - Write Protect
1898 * 0b0..This peripheral allows write accesses.
1899 * 0b1..This peripheral is write protected.
1900 */
1901#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
1902#define AIPS_PACRE_SP0_MASK (0x40000000U)
1903#define AIPS_PACRE_SP0_SHIFT (30U)
1904/*! SP0 - Supervisor Protect
1905 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1906 * 0b1..This peripheral requires supervisor privilege level for accesses.
1907 */
1908#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
1909/*! @} */
1910
1911/*! @name PACRF - Peripheral Access Control Register */
1912/*! @{ */
1913#define AIPS_PACRF_TP7_MASK (0x1U)
1914#define AIPS_PACRF_TP7_SHIFT (0U)
1915/*! TP7 - Trusted Protect
1916 * 0b0..Accesses from an untrusted master are allowed.
1917 * 0b1..Accesses from an untrusted master are not allowed.
1918 */
1919#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
1920#define AIPS_PACRF_WP7_MASK (0x2U)
1921#define AIPS_PACRF_WP7_SHIFT (1U)
1922/*! WP7 - Write Protect
1923 * 0b0..This peripheral allows write accesses.
1924 * 0b1..This peripheral is write protected.
1925 */
1926#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
1927#define AIPS_PACRF_SP7_MASK (0x4U)
1928#define AIPS_PACRF_SP7_SHIFT (2U)
1929/*! SP7 - Supervisor Protect
1930 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1931 * 0b1..This peripheral requires supervisor privilege level for accesses.
1932 */
1933#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
1934#define AIPS_PACRF_TP6_MASK (0x10U)
1935#define AIPS_PACRF_TP6_SHIFT (4U)
1936/*! TP6 - Trusted Protect
1937 * 0b0..Accesses from an untrusted master are allowed.
1938 * 0b1..Accesses from an untrusted master are not allowed.
1939 */
1940#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
1941#define AIPS_PACRF_WP6_MASK (0x20U)
1942#define AIPS_PACRF_WP6_SHIFT (5U)
1943/*! WP6 - Write Protect
1944 * 0b0..This peripheral allows write accesses.
1945 * 0b1..This peripheral is write protected.
1946 */
1947#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
1948#define AIPS_PACRF_SP6_MASK (0x40U)
1949#define AIPS_PACRF_SP6_SHIFT (6U)
1950/*! SP6 - Supervisor Protect
1951 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1952 * 0b1..This peripheral requires supervisor privilege level for accesses.
1953 */
1954#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
1955#define AIPS_PACRF_TP5_MASK (0x100U)
1956#define AIPS_PACRF_TP5_SHIFT (8U)
1957/*! TP5 - Trusted Protect
1958 * 0b0..Accesses from an untrusted master are allowed.
1959 * 0b1..Accesses from an untrusted master are not allowed.
1960 */
1961#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
1962#define AIPS_PACRF_WP5_MASK (0x200U)
1963#define AIPS_PACRF_WP5_SHIFT (9U)
1964/*! WP5 - Write Protect
1965 * 0b0..This peripheral allows write accesses.
1966 * 0b1..This peripheral is write protected.
1967 */
1968#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
1969#define AIPS_PACRF_SP5_MASK (0x400U)
1970#define AIPS_PACRF_SP5_SHIFT (10U)
1971/*! SP5 - Supervisor Protect
1972 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1973 * 0b1..This peripheral requires supervisor privilege level for accesses.
1974 */
1975#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
1976#define AIPS_PACRF_TP4_MASK (0x1000U)
1977#define AIPS_PACRF_TP4_SHIFT (12U)
1978/*! TP4 - Trusted Protect
1979 * 0b0..Accesses from an untrusted master are allowed.
1980 * 0b1..Accesses from an untrusted master are not allowed.
1981 */
1982#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
1983#define AIPS_PACRF_WP4_MASK (0x2000U)
1984#define AIPS_PACRF_WP4_SHIFT (13U)
1985/*! WP4 - Write Protect
1986 * 0b0..This peripheral allows write accesses.
1987 * 0b1..This peripheral is write protected.
1988 */
1989#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
1990#define AIPS_PACRF_SP4_MASK (0x4000U)
1991#define AIPS_PACRF_SP4_SHIFT (14U)
1992/*! SP4 - Supervisor Protect
1993 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1994 * 0b1..This peripheral requires supervisor privilege level for accesses.
1995 */
1996#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
1997#define AIPS_PACRF_TP3_MASK (0x10000U)
1998#define AIPS_PACRF_TP3_SHIFT (16U)
1999/*! TP3 - Trusted Protect
2000 * 0b0..Accesses from an untrusted master are allowed.
2001 * 0b1..Accesses from an untrusted master are not allowed.
2002 */
2003#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
2004#define AIPS_PACRF_WP3_MASK (0x20000U)
2005#define AIPS_PACRF_WP3_SHIFT (17U)
2006/*! WP3 - Write Protect
2007 * 0b0..This peripheral allows write accesses.
2008 * 0b1..This peripheral is write protected.
2009 */
2010#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
2011#define AIPS_PACRF_SP3_MASK (0x40000U)
2012#define AIPS_PACRF_SP3_SHIFT (18U)
2013/*! SP3 - Supervisor Protect
2014 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2015 * 0b1..This peripheral requires supervisor privilege level for accesses.
2016 */
2017#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
2018#define AIPS_PACRF_TP2_MASK (0x100000U)
2019#define AIPS_PACRF_TP2_SHIFT (20U)
2020/*! TP2 - Trusted Protect
2021 * 0b0..Accesses from an untrusted master are allowed.
2022 * 0b1..Accesses from an untrusted master are not allowed.
2023 */
2024#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
2025#define AIPS_PACRF_WP2_MASK (0x200000U)
2026#define AIPS_PACRF_WP2_SHIFT (21U)
2027/*! WP2 - Write Protect
2028 * 0b0..This peripheral allows write accesses.
2029 * 0b1..This peripheral is write protected.
2030 */
2031#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
2032#define AIPS_PACRF_SP2_MASK (0x400000U)
2033#define AIPS_PACRF_SP2_SHIFT (22U)
2034/*! SP2 - Supervisor Protect
2035 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2036 * 0b1..This peripheral requires supervisor privilege level for accesses.
2037 */
2038#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
2039#define AIPS_PACRF_TP1_MASK (0x1000000U)
2040#define AIPS_PACRF_TP1_SHIFT (24U)
2041/*! TP1 - Trusted Protect
2042 * 0b0..Accesses from an untrusted master are allowed.
2043 * 0b1..Accesses from an untrusted master are not allowed.
2044 */
2045#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
2046#define AIPS_PACRF_WP1_MASK (0x2000000U)
2047#define AIPS_PACRF_WP1_SHIFT (25U)
2048/*! WP1 - Write Protect
2049 * 0b0..This peripheral allows write accesses.
2050 * 0b1..This peripheral is write protected.
2051 */
2052#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
2053#define AIPS_PACRF_SP1_MASK (0x4000000U)
2054#define AIPS_PACRF_SP1_SHIFT (26U)
2055/*! SP1 - Supervisor Protect
2056 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2057 * 0b1..This peripheral requires supervisor privilege level for accesses.
2058 */
2059#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
2060#define AIPS_PACRF_TP0_MASK (0x10000000U)
2061#define AIPS_PACRF_TP0_SHIFT (28U)
2062/*! TP0 - Trusted Protect
2063 * 0b0..Accesses from an untrusted master are allowed.
2064 * 0b1..Accesses from an untrusted master are not allowed.
2065 */
2066#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
2067#define AIPS_PACRF_WP0_MASK (0x20000000U)
2068#define AIPS_PACRF_WP0_SHIFT (29U)
2069/*! WP0 - Write Protect
2070 * 0b0..This peripheral allows write accesses.
2071 * 0b1..This peripheral is write protected.
2072 */
2073#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
2074#define AIPS_PACRF_SP0_MASK (0x40000000U)
2075#define AIPS_PACRF_SP0_SHIFT (30U)
2076/*! SP0 - Supervisor Protect
2077 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2078 * 0b1..This peripheral requires supervisor privilege level for accesses.
2079 */
2080#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
2081/*! @} */
2082
2083/*! @name PACRG - Peripheral Access Control Register */
2084/*! @{ */
2085#define AIPS_PACRG_TP7_MASK (0x1U)
2086#define AIPS_PACRG_TP7_SHIFT (0U)
2087/*! TP7 - Trusted Protect
2088 * 0b0..Accesses from an untrusted master are allowed.
2089 * 0b1..Accesses from an untrusted master are not allowed.
2090 */
2091#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
2092#define AIPS_PACRG_WP7_MASK (0x2U)
2093#define AIPS_PACRG_WP7_SHIFT (1U)
2094/*! WP7 - Write Protect
2095 * 0b0..This peripheral allows write accesses.
2096 * 0b1..This peripheral is write protected.
2097 */
2098#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
2099#define AIPS_PACRG_SP7_MASK (0x4U)
2100#define AIPS_PACRG_SP7_SHIFT (2U)
2101/*! SP7 - Supervisor Protect
2102 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2103 * 0b1..This peripheral requires supervisor privilege level for accesses.
2104 */
2105#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
2106#define AIPS_PACRG_TP6_MASK (0x10U)
2107#define AIPS_PACRG_TP6_SHIFT (4U)
2108/*! TP6 - Trusted Protect
2109 * 0b0..Accesses from an untrusted master are allowed.
2110 * 0b1..Accesses from an untrusted master are not allowed.
2111 */
2112#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
2113#define AIPS_PACRG_WP6_MASK (0x20U)
2114#define AIPS_PACRG_WP6_SHIFT (5U)
2115/*! WP6 - Write Protect
2116 * 0b0..This peripheral allows write accesses.
2117 * 0b1..This peripheral is write protected.
2118 */
2119#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
2120#define AIPS_PACRG_SP6_MASK (0x40U)
2121#define AIPS_PACRG_SP6_SHIFT (6U)
2122/*! SP6 - Supervisor Protect
2123 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2124 * 0b1..This peripheral requires supervisor privilege level for accesses.
2125 */
2126#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
2127#define AIPS_PACRG_TP5_MASK (0x100U)
2128#define AIPS_PACRG_TP5_SHIFT (8U)
2129/*! TP5 - Trusted Protect
2130 * 0b0..Accesses from an untrusted master are allowed.
2131 * 0b1..Accesses from an untrusted master are not allowed.
2132 */
2133#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
2134#define AIPS_PACRG_WP5_MASK (0x200U)
2135#define AIPS_PACRG_WP5_SHIFT (9U)
2136/*! WP5 - Write Protect
2137 * 0b0..This peripheral allows write accesses.
2138 * 0b1..This peripheral is write protected.
2139 */
2140#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
2141#define AIPS_PACRG_SP5_MASK (0x400U)
2142#define AIPS_PACRG_SP5_SHIFT (10U)
2143/*! SP5 - Supervisor Protect
2144 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2145 * 0b1..This peripheral requires supervisor privilege level for accesses.
2146 */
2147#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
2148#define AIPS_PACRG_TP4_MASK (0x1000U)
2149#define AIPS_PACRG_TP4_SHIFT (12U)
2150/*! TP4 - Trusted Protect
2151 * 0b0..Accesses from an untrusted master are allowed.
2152 * 0b1..Accesses from an untrusted master are not allowed.
2153 */
2154#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
2155#define AIPS_PACRG_WP4_MASK (0x2000U)
2156#define AIPS_PACRG_WP4_SHIFT (13U)
2157/*! WP4 - Write Protect
2158 * 0b0..This peripheral allows write accesses.
2159 * 0b1..This peripheral is write protected.
2160 */
2161#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
2162#define AIPS_PACRG_SP4_MASK (0x4000U)
2163#define AIPS_PACRG_SP4_SHIFT (14U)
2164/*! SP4 - Supervisor Protect
2165 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2166 * 0b1..This peripheral requires supervisor privilege level for accesses.
2167 */
2168#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
2169#define AIPS_PACRG_TP3_MASK (0x10000U)
2170#define AIPS_PACRG_TP3_SHIFT (16U)
2171/*! TP3 - Trusted Protect
2172 * 0b0..Accesses from an untrusted master are allowed.
2173 * 0b1..Accesses from an untrusted master are not allowed.
2174 */
2175#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
2176#define AIPS_PACRG_WP3_MASK (0x20000U)
2177#define AIPS_PACRG_WP3_SHIFT (17U)
2178/*! WP3 - Write Protect
2179 * 0b0..This peripheral allows write accesses.
2180 * 0b1..This peripheral is write protected.
2181 */
2182#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
2183#define AIPS_PACRG_SP3_MASK (0x40000U)
2184#define AIPS_PACRG_SP3_SHIFT (18U)
2185/*! SP3 - Supervisor Protect
2186 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2187 * 0b1..This peripheral requires supervisor privilege level for accesses.
2188 */
2189#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
2190#define AIPS_PACRG_TP2_MASK (0x100000U)
2191#define AIPS_PACRG_TP2_SHIFT (20U)
2192/*! TP2 - Trusted Protect
2193 * 0b0..Accesses from an untrusted master are allowed.
2194 * 0b1..Accesses from an untrusted master are not allowed.
2195 */
2196#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
2197#define AIPS_PACRG_WP2_MASK (0x200000U)
2198#define AIPS_PACRG_WP2_SHIFT (21U)
2199/*! WP2 - Write Protect
2200 * 0b0..This peripheral allows write accesses.
2201 * 0b1..This peripheral is write protected.
2202 */
2203#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
2204#define AIPS_PACRG_SP2_MASK (0x400000U)
2205#define AIPS_PACRG_SP2_SHIFT (22U)
2206/*! SP2 - Supervisor Protect
2207 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2208 * 0b1..This peripheral requires supervisor privilege level for accesses.
2209 */
2210#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
2211#define AIPS_PACRG_TP1_MASK (0x1000000U)
2212#define AIPS_PACRG_TP1_SHIFT (24U)
2213/*! TP1 - Trusted Protect
2214 * 0b0..Accesses from an untrusted master are allowed.
2215 * 0b1..Accesses from an untrusted master are not allowed.
2216 */
2217#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
2218#define AIPS_PACRG_WP1_MASK (0x2000000U)
2219#define AIPS_PACRG_WP1_SHIFT (25U)
2220/*! WP1 - Write Protect
2221 * 0b0..This peripheral allows write accesses.
2222 * 0b1..This peripheral is write protected.
2223 */
2224#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
2225#define AIPS_PACRG_SP1_MASK (0x4000000U)
2226#define AIPS_PACRG_SP1_SHIFT (26U)
2227/*! SP1 - Supervisor Protect
2228 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2229 * 0b1..This peripheral requires supervisor privilege level for accesses.
2230 */
2231#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
2232#define AIPS_PACRG_TP0_MASK (0x10000000U)
2233#define AIPS_PACRG_TP0_SHIFT (28U)
2234/*! TP0 - Trusted Protect
2235 * 0b0..Accesses from an untrusted master are allowed.
2236 * 0b1..Accesses from an untrusted master are not allowed.
2237 */
2238#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
2239#define AIPS_PACRG_WP0_MASK (0x20000000U)
2240#define AIPS_PACRG_WP0_SHIFT (29U)
2241/*! WP0 - Write Protect
2242 * 0b0..This peripheral allows write accesses.
2243 * 0b1..This peripheral is write protected.
2244 */
2245#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
2246#define AIPS_PACRG_SP0_MASK (0x40000000U)
2247#define AIPS_PACRG_SP0_SHIFT (30U)
2248/*! SP0 - Supervisor Protect
2249 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2250 * 0b1..This peripheral requires supervisor privilege level for accesses.
2251 */
2252#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
2253/*! @} */
2254
2255/*! @name PACRH - Peripheral Access Control Register */
2256/*! @{ */
2257#define AIPS_PACRH_TP7_MASK (0x1U)
2258#define AIPS_PACRH_TP7_SHIFT (0U)
2259/*! TP7 - Trusted Protect
2260 * 0b0..Accesses from an untrusted master are allowed.
2261 * 0b1..Accesses from an untrusted master are not allowed.
2262 */
2263#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
2264#define AIPS_PACRH_WP7_MASK (0x2U)
2265#define AIPS_PACRH_WP7_SHIFT (1U)
2266/*! WP7 - Write Protect
2267 * 0b0..This peripheral allows write accesses.
2268 * 0b1..This peripheral is write protected.
2269 */
2270#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
2271#define AIPS_PACRH_SP7_MASK (0x4U)
2272#define AIPS_PACRH_SP7_SHIFT (2U)
2273/*! SP7 - Supervisor Protect
2274 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2275 * 0b1..This peripheral requires supervisor privilege level for accesses.
2276 */
2277#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
2278#define AIPS_PACRH_TP6_MASK (0x10U)
2279#define AIPS_PACRH_TP6_SHIFT (4U)
2280/*! TP6 - Trusted Protect
2281 * 0b0..Accesses from an untrusted master are allowed.
2282 * 0b1..Accesses from an untrusted master are not allowed.
2283 */
2284#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
2285#define AIPS_PACRH_WP6_MASK (0x20U)
2286#define AIPS_PACRH_WP6_SHIFT (5U)
2287/*! WP6 - Write Protect
2288 * 0b0..This peripheral allows write accesses.
2289 * 0b1..This peripheral is write protected.
2290 */
2291#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
2292#define AIPS_PACRH_SP6_MASK (0x40U)
2293#define AIPS_PACRH_SP6_SHIFT (6U)
2294/*! SP6 - Supervisor Protect
2295 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2296 * 0b1..This peripheral requires supervisor privilege level for accesses.
2297 */
2298#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
2299#define AIPS_PACRH_TP5_MASK (0x100U)
2300#define AIPS_PACRH_TP5_SHIFT (8U)
2301/*! TP5 - Trusted Protect
2302 * 0b0..Accesses from an untrusted master are allowed.
2303 * 0b1..Accesses from an untrusted master are not allowed.
2304 */
2305#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
2306#define AIPS_PACRH_WP5_MASK (0x200U)
2307#define AIPS_PACRH_WP5_SHIFT (9U)
2308/*! WP5 - Write Protect
2309 * 0b0..This peripheral allows write accesses.
2310 * 0b1..This peripheral is write protected.
2311 */
2312#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
2313#define AIPS_PACRH_SP5_MASK (0x400U)
2314#define AIPS_PACRH_SP5_SHIFT (10U)
2315/*! SP5 - Supervisor Protect
2316 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2317 * 0b1..This peripheral requires supervisor privilege level for accesses.
2318 */
2319#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
2320#define AIPS_PACRH_TP4_MASK (0x1000U)
2321#define AIPS_PACRH_TP4_SHIFT (12U)
2322/*! TP4 - Trusted Protect
2323 * 0b0..Accesses from an untrusted master are allowed.
2324 * 0b1..Accesses from an untrusted master are not allowed.
2325 */
2326#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
2327#define AIPS_PACRH_WP4_MASK (0x2000U)
2328#define AIPS_PACRH_WP4_SHIFT (13U)
2329/*! WP4 - Write Protect
2330 * 0b0..This peripheral allows write accesses.
2331 * 0b1..This peripheral is write protected.
2332 */
2333#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
2334#define AIPS_PACRH_SP4_MASK (0x4000U)
2335#define AIPS_PACRH_SP4_SHIFT (14U)
2336/*! SP4 - Supervisor Protect
2337 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2338 * 0b1..This peripheral requires supervisor privilege level for accesses.
2339 */
2340#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
2341#define AIPS_PACRH_TP3_MASK (0x10000U)
2342#define AIPS_PACRH_TP3_SHIFT (16U)
2343/*! TP3 - Trusted Protect
2344 * 0b0..Accesses from an untrusted master are allowed.
2345 * 0b1..Accesses from an untrusted master are not allowed.
2346 */
2347#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
2348#define AIPS_PACRH_WP3_MASK (0x20000U)
2349#define AIPS_PACRH_WP3_SHIFT (17U)
2350/*! WP3 - Write Protect
2351 * 0b0..This peripheral allows write accesses.
2352 * 0b1..This peripheral is write protected.
2353 */
2354#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
2355#define AIPS_PACRH_SP3_MASK (0x40000U)
2356#define AIPS_PACRH_SP3_SHIFT (18U)
2357/*! SP3 - Supervisor Protect
2358 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2359 * 0b1..This peripheral requires supervisor privilege level for accesses.
2360 */
2361#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
2362#define AIPS_PACRH_TP2_MASK (0x100000U)
2363#define AIPS_PACRH_TP2_SHIFT (20U)
2364/*! TP2 - Trusted Protect
2365 * 0b0..Accesses from an untrusted master are allowed.
2366 * 0b1..Accesses from an untrusted master are not allowed.
2367 */
2368#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
2369#define AIPS_PACRH_WP2_MASK (0x200000U)
2370#define AIPS_PACRH_WP2_SHIFT (21U)
2371/*! WP2 - Write Protect
2372 * 0b0..This peripheral allows write accesses.
2373 * 0b1..This peripheral is write protected.
2374 */
2375#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
2376#define AIPS_PACRH_SP2_MASK (0x400000U)
2377#define AIPS_PACRH_SP2_SHIFT (22U)
2378/*! SP2 - Supervisor Protect
2379 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2380 * 0b1..This peripheral requires supervisor privilege level for accesses.
2381 */
2382#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
2383#define AIPS_PACRH_TP1_MASK (0x1000000U)
2384#define AIPS_PACRH_TP1_SHIFT (24U)
2385/*! TP1 - Trusted Protect
2386 * 0b0..Accesses from an untrusted master are allowed.
2387 * 0b1..Accesses from an untrusted master are not allowed.
2388 */
2389#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
2390#define AIPS_PACRH_WP1_MASK (0x2000000U)
2391#define AIPS_PACRH_WP1_SHIFT (25U)
2392/*! WP1 - Write Protect
2393 * 0b0..This peripheral allows write accesses.
2394 * 0b1..This peripheral is write protected.
2395 */
2396#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
2397#define AIPS_PACRH_SP1_MASK (0x4000000U)
2398#define AIPS_PACRH_SP1_SHIFT (26U)
2399/*! SP1 - Supervisor Protect
2400 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2401 * 0b1..This peripheral requires supervisor privilege level for accesses.
2402 */
2403#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
2404#define AIPS_PACRH_TP0_MASK (0x10000000U)
2405#define AIPS_PACRH_TP0_SHIFT (28U)
2406/*! TP0 - Trusted Protect
2407 * 0b0..Accesses from an untrusted master are allowed.
2408 * 0b1..Accesses from an untrusted master are not allowed.
2409 */
2410#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
2411#define AIPS_PACRH_WP0_MASK (0x20000000U)
2412#define AIPS_PACRH_WP0_SHIFT (29U)
2413/*! WP0 - Write Protect
2414 * 0b0..This peripheral allows write accesses.
2415 * 0b1..This peripheral is write protected.
2416 */
2417#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
2418#define AIPS_PACRH_SP0_MASK (0x40000000U)
2419#define AIPS_PACRH_SP0_SHIFT (30U)
2420/*! SP0 - Supervisor Protect
2421 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2422 * 0b1..This peripheral requires supervisor privilege level for accesses.
2423 */
2424#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
2425/*! @} */
2426
2427/*! @name PACRI - Peripheral Access Control Register */
2428/*! @{ */
2429#define AIPS_PACRI_TP7_MASK (0x1U)
2430#define AIPS_PACRI_TP7_SHIFT (0U)
2431/*! TP7 - Trusted Protect
2432 * 0b0..Accesses from an untrusted master are allowed.
2433 * 0b1..Accesses from an untrusted master are not allowed.
2434 */
2435#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
2436#define AIPS_PACRI_WP7_MASK (0x2U)
2437#define AIPS_PACRI_WP7_SHIFT (1U)
2438/*! WP7 - Write Protect
2439 * 0b0..This peripheral allows write accesses.
2440 * 0b1..This peripheral is write protected.
2441 */
2442#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
2443#define AIPS_PACRI_SP7_MASK (0x4U)
2444#define AIPS_PACRI_SP7_SHIFT (2U)
2445/*! SP7 - Supervisor Protect
2446 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2447 * 0b1..This peripheral requires supervisor privilege level for accesses.
2448 */
2449#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
2450#define AIPS_PACRI_TP6_MASK (0x10U)
2451#define AIPS_PACRI_TP6_SHIFT (4U)
2452/*! TP6 - Trusted Protect
2453 * 0b0..Accesses from an untrusted master are allowed.
2454 * 0b1..Accesses from an untrusted master are not allowed.
2455 */
2456#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
2457#define AIPS_PACRI_WP6_MASK (0x20U)
2458#define AIPS_PACRI_WP6_SHIFT (5U)
2459/*! WP6 - Write Protect
2460 * 0b0..This peripheral allows write accesses.
2461 * 0b1..This peripheral is write protected.
2462 */
2463#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
2464#define AIPS_PACRI_SP6_MASK (0x40U)
2465#define AIPS_PACRI_SP6_SHIFT (6U)
2466/*! SP6 - Supervisor Protect
2467 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2468 * 0b1..This peripheral requires supervisor privilege level for accesses.
2469 */
2470#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
2471#define AIPS_PACRI_TP5_MASK (0x100U)
2472#define AIPS_PACRI_TP5_SHIFT (8U)
2473/*! TP5 - Trusted Protect
2474 * 0b0..Accesses from an untrusted master are allowed.
2475 * 0b1..Accesses from an untrusted master are not allowed.
2476 */
2477#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
2478#define AIPS_PACRI_WP5_MASK (0x200U)
2479#define AIPS_PACRI_WP5_SHIFT (9U)
2480/*! WP5 - Write Protect
2481 * 0b0..This peripheral allows write accesses.
2482 * 0b1..This peripheral is write protected.
2483 */
2484#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
2485#define AIPS_PACRI_SP5_MASK (0x400U)
2486#define AIPS_PACRI_SP5_SHIFT (10U)
2487/*! SP5 - Supervisor Protect
2488 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2489 * 0b1..This peripheral requires supervisor privilege level for accesses.
2490 */
2491#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
2492#define AIPS_PACRI_TP4_MASK (0x1000U)
2493#define AIPS_PACRI_TP4_SHIFT (12U)
2494/*! TP4 - Trusted Protect
2495 * 0b0..Accesses from an untrusted master are allowed.
2496 * 0b1..Accesses from an untrusted master are not allowed.
2497 */
2498#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
2499#define AIPS_PACRI_WP4_MASK (0x2000U)
2500#define AIPS_PACRI_WP4_SHIFT (13U)
2501/*! WP4 - Write Protect
2502 * 0b0..This peripheral allows write accesses.
2503 * 0b1..This peripheral is write protected.
2504 */
2505#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
2506#define AIPS_PACRI_SP4_MASK (0x4000U)
2507#define AIPS_PACRI_SP4_SHIFT (14U)
2508/*! SP4 - Supervisor Protect
2509 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2510 * 0b1..This peripheral requires supervisor privilege level for accesses.
2511 */
2512#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
2513#define AIPS_PACRI_TP3_MASK (0x10000U)
2514#define AIPS_PACRI_TP3_SHIFT (16U)
2515/*! TP3 - Trusted Protect
2516 * 0b0..Accesses from an untrusted master are allowed.
2517 * 0b1..Accesses from an untrusted master are not allowed.
2518 */
2519#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
2520#define AIPS_PACRI_WP3_MASK (0x20000U)
2521#define AIPS_PACRI_WP3_SHIFT (17U)
2522/*! WP3 - Write Protect
2523 * 0b0..This peripheral allows write accesses.
2524 * 0b1..This peripheral is write protected.
2525 */
2526#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
2527#define AIPS_PACRI_SP3_MASK (0x40000U)
2528#define AIPS_PACRI_SP3_SHIFT (18U)
2529/*! SP3 - Supervisor Protect
2530 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2531 * 0b1..This peripheral requires supervisor privilege level for accesses.
2532 */
2533#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
2534#define AIPS_PACRI_TP2_MASK (0x100000U)
2535#define AIPS_PACRI_TP2_SHIFT (20U)
2536/*! TP2 - Trusted Protect
2537 * 0b0..Accesses from an untrusted master are allowed.
2538 * 0b1..Accesses from an untrusted master are not allowed.
2539 */
2540#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
2541#define AIPS_PACRI_WP2_MASK (0x200000U)
2542#define AIPS_PACRI_WP2_SHIFT (21U)
2543/*! WP2 - Write Protect
2544 * 0b0..This peripheral allows write accesses.
2545 * 0b1..This peripheral is write protected.
2546 */
2547#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
2548#define AIPS_PACRI_SP2_MASK (0x400000U)
2549#define AIPS_PACRI_SP2_SHIFT (22U)
2550/*! SP2 - Supervisor Protect
2551 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2552 * 0b1..This peripheral requires supervisor privilege level for accesses.
2553 */
2554#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
2555#define AIPS_PACRI_TP1_MASK (0x1000000U)
2556#define AIPS_PACRI_TP1_SHIFT (24U)
2557/*! TP1 - Trusted Protect
2558 * 0b0..Accesses from an untrusted master are allowed.
2559 * 0b1..Accesses from an untrusted master are not allowed.
2560 */
2561#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
2562#define AIPS_PACRI_WP1_MASK (0x2000000U)
2563#define AIPS_PACRI_WP1_SHIFT (25U)
2564/*! WP1 - Write Protect
2565 * 0b0..This peripheral allows write accesses.
2566 * 0b1..This peripheral is write protected.
2567 */
2568#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
2569#define AIPS_PACRI_SP1_MASK (0x4000000U)
2570#define AIPS_PACRI_SP1_SHIFT (26U)
2571/*! SP1 - Supervisor Protect
2572 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2573 * 0b1..This peripheral requires supervisor privilege level for accesses.
2574 */
2575#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
2576#define AIPS_PACRI_TP0_MASK (0x10000000U)
2577#define AIPS_PACRI_TP0_SHIFT (28U)
2578/*! TP0 - Trusted Protect
2579 * 0b0..Accesses from an untrusted master are allowed.
2580 * 0b1..Accesses from an untrusted master are not allowed.
2581 */
2582#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
2583#define AIPS_PACRI_WP0_MASK (0x20000000U)
2584#define AIPS_PACRI_WP0_SHIFT (29U)
2585/*! WP0 - Write Protect
2586 * 0b0..This peripheral allows write accesses.
2587 * 0b1..This peripheral is write protected.
2588 */
2589#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
2590#define AIPS_PACRI_SP0_MASK (0x40000000U)
2591#define AIPS_PACRI_SP0_SHIFT (30U)
2592/*! SP0 - Supervisor Protect
2593 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2594 * 0b1..This peripheral requires supervisor privilege level for accesses.
2595 */
2596#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
2597/*! @} */
2598
2599/*! @name PACRJ - Peripheral Access Control Register */
2600/*! @{ */
2601#define AIPS_PACRJ_TP7_MASK (0x1U)
2602#define AIPS_PACRJ_TP7_SHIFT (0U)
2603/*! TP7 - Trusted Protect
2604 * 0b0..Accesses from an untrusted master are allowed.
2605 * 0b1..Accesses from an untrusted master are not allowed.
2606 */
2607#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
2608#define AIPS_PACRJ_WP7_MASK (0x2U)
2609#define AIPS_PACRJ_WP7_SHIFT (1U)
2610/*! WP7 - Write Protect
2611 * 0b0..This peripheral allows write accesses.
2612 * 0b1..This peripheral is write protected.
2613 */
2614#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
2615#define AIPS_PACRJ_SP7_MASK (0x4U)
2616#define AIPS_PACRJ_SP7_SHIFT (2U)
2617/*! SP7 - Supervisor Protect
2618 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2619 * 0b1..This peripheral requires supervisor privilege level for accesses.
2620 */
2621#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
2622#define AIPS_PACRJ_TP6_MASK (0x10U)
2623#define AIPS_PACRJ_TP6_SHIFT (4U)
2624/*! TP6 - Trusted Protect
2625 * 0b0..Accesses from an untrusted master are allowed.
2626 * 0b1..Accesses from an untrusted master are not allowed.
2627 */
2628#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
2629#define AIPS_PACRJ_WP6_MASK (0x20U)
2630#define AIPS_PACRJ_WP6_SHIFT (5U)
2631/*! WP6 - Write Protect
2632 * 0b0..This peripheral allows write accesses.
2633 * 0b1..This peripheral is write protected.
2634 */
2635#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
2636#define AIPS_PACRJ_SP6_MASK (0x40U)
2637#define AIPS_PACRJ_SP6_SHIFT (6U)
2638/*! SP6 - Supervisor Protect
2639 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2640 * 0b1..This peripheral requires supervisor privilege level for accesses.
2641 */
2642#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
2643#define AIPS_PACRJ_TP5_MASK (0x100U)
2644#define AIPS_PACRJ_TP5_SHIFT (8U)
2645/*! TP5 - Trusted Protect
2646 * 0b0..Accesses from an untrusted master are allowed.
2647 * 0b1..Accesses from an untrusted master are not allowed.
2648 */
2649#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
2650#define AIPS_PACRJ_WP5_MASK (0x200U)
2651#define AIPS_PACRJ_WP5_SHIFT (9U)
2652/*! WP5 - Write Protect
2653 * 0b0..This peripheral allows write accesses.
2654 * 0b1..This peripheral is write protected.
2655 */
2656#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
2657#define AIPS_PACRJ_SP5_MASK (0x400U)
2658#define AIPS_PACRJ_SP5_SHIFT (10U)
2659/*! SP5 - Supervisor Protect
2660 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2661 * 0b1..This peripheral requires supervisor privilege level for accesses.
2662 */
2663#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
2664#define AIPS_PACRJ_TP4_MASK (0x1000U)
2665#define AIPS_PACRJ_TP4_SHIFT (12U)
2666/*! TP4 - Trusted Protect
2667 * 0b0..Accesses from an untrusted master are allowed.
2668 * 0b1..Accesses from an untrusted master are not allowed.
2669 */
2670#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
2671#define AIPS_PACRJ_WP4_MASK (0x2000U)
2672#define AIPS_PACRJ_WP4_SHIFT (13U)
2673/*! WP4 - Write Protect
2674 * 0b0..This peripheral allows write accesses.
2675 * 0b1..This peripheral is write protected.
2676 */
2677#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
2678#define AIPS_PACRJ_SP4_MASK (0x4000U)
2679#define AIPS_PACRJ_SP4_SHIFT (14U)
2680/*! SP4 - Supervisor Protect
2681 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2682 * 0b1..This peripheral requires supervisor privilege level for accesses.
2683 */
2684#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
2685#define AIPS_PACRJ_TP3_MASK (0x10000U)
2686#define AIPS_PACRJ_TP3_SHIFT (16U)
2687/*! TP3 - Trusted Protect
2688 * 0b0..Accesses from an untrusted master are allowed.
2689 * 0b1..Accesses from an untrusted master are not allowed.
2690 */
2691#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
2692#define AIPS_PACRJ_WP3_MASK (0x20000U)
2693#define AIPS_PACRJ_WP3_SHIFT (17U)
2694/*! WP3 - Write Protect
2695 * 0b0..This peripheral allows write accesses.
2696 * 0b1..This peripheral is write protected.
2697 */
2698#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
2699#define AIPS_PACRJ_SP3_MASK (0x40000U)
2700#define AIPS_PACRJ_SP3_SHIFT (18U)
2701/*! SP3 - Supervisor Protect
2702 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2703 * 0b1..This peripheral requires supervisor privilege level for accesses.
2704 */
2705#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
2706#define AIPS_PACRJ_TP2_MASK (0x100000U)
2707#define AIPS_PACRJ_TP2_SHIFT (20U)
2708/*! TP2 - Trusted Protect
2709 * 0b0..Accesses from an untrusted master are allowed.
2710 * 0b1..Accesses from an untrusted master are not allowed.
2711 */
2712#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
2713#define AIPS_PACRJ_WP2_MASK (0x200000U)
2714#define AIPS_PACRJ_WP2_SHIFT (21U)
2715/*! WP2 - Write Protect
2716 * 0b0..This peripheral allows write accesses.
2717 * 0b1..This peripheral is write protected.
2718 */
2719#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
2720#define AIPS_PACRJ_SP2_MASK (0x400000U)
2721#define AIPS_PACRJ_SP2_SHIFT (22U)
2722/*! SP2 - Supervisor Protect
2723 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2724 * 0b1..This peripheral requires supervisor privilege level for accesses.
2725 */
2726#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
2727#define AIPS_PACRJ_TP1_MASK (0x1000000U)
2728#define AIPS_PACRJ_TP1_SHIFT (24U)
2729/*! TP1 - Trusted Protect
2730 * 0b0..Accesses from an untrusted master are allowed.
2731 * 0b1..Accesses from an untrusted master are not allowed.
2732 */
2733#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
2734#define AIPS_PACRJ_WP1_MASK (0x2000000U)
2735#define AIPS_PACRJ_WP1_SHIFT (25U)
2736/*! WP1 - Write Protect
2737 * 0b0..This peripheral allows write accesses.
2738 * 0b1..This peripheral is write protected.
2739 */
2740#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
2741#define AIPS_PACRJ_SP1_MASK (0x4000000U)
2742#define AIPS_PACRJ_SP1_SHIFT (26U)
2743/*! SP1 - Supervisor Protect
2744 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2745 * 0b1..This peripheral requires supervisor privilege level for accesses.
2746 */
2747#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
2748#define AIPS_PACRJ_TP0_MASK (0x10000000U)
2749#define AIPS_PACRJ_TP0_SHIFT (28U)
2750/*! TP0 - Trusted Protect
2751 * 0b0..Accesses from an untrusted master are allowed.
2752 * 0b1..Accesses from an untrusted master are not allowed.
2753 */
2754#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
2755#define AIPS_PACRJ_WP0_MASK (0x20000000U)
2756#define AIPS_PACRJ_WP0_SHIFT (29U)
2757/*! WP0 - Write Protect
2758 * 0b0..This peripheral allows write accesses.
2759 * 0b1..This peripheral is write protected.
2760 */
2761#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
2762#define AIPS_PACRJ_SP0_MASK (0x40000000U)
2763#define AIPS_PACRJ_SP0_SHIFT (30U)
2764/*! SP0 - Supervisor Protect
2765 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2766 * 0b1..This peripheral requires supervisor privilege level for accesses.
2767 */
2768#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
2769/*! @} */
2770
2771/*! @name PACRK - Peripheral Access Control Register */
2772/*! @{ */
2773#define AIPS_PACRK_TP7_MASK (0x1U)
2774#define AIPS_PACRK_TP7_SHIFT (0U)
2775/*! TP7 - Trusted Protect
2776 * 0b0..Accesses from an untrusted master are allowed.
2777 * 0b1..Accesses from an untrusted master are not allowed.
2778 */
2779#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
2780#define AIPS_PACRK_WP7_MASK (0x2U)
2781#define AIPS_PACRK_WP7_SHIFT (1U)
2782/*! WP7 - Write Protect
2783 * 0b0..This peripheral allows write accesses.
2784 * 0b1..This peripheral is write protected.
2785 */
2786#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
2787#define AIPS_PACRK_SP7_MASK (0x4U)
2788#define AIPS_PACRK_SP7_SHIFT (2U)
2789/*! SP7 - Supervisor Protect
2790 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2791 * 0b1..This peripheral requires supervisor privilege level for accesses.
2792 */
2793#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
2794#define AIPS_PACRK_TP6_MASK (0x10U)
2795#define AIPS_PACRK_TP6_SHIFT (4U)
2796/*! TP6 - Trusted Protect
2797 * 0b0..Accesses from an untrusted master are allowed.
2798 * 0b1..Accesses from an untrusted master are not allowed.
2799 */
2800#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
2801#define AIPS_PACRK_WP6_MASK (0x20U)
2802#define AIPS_PACRK_WP6_SHIFT (5U)
2803/*! WP6 - Write Protect
2804 * 0b0..This peripheral allows write accesses.
2805 * 0b1..This peripheral is write protected.
2806 */
2807#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
2808#define AIPS_PACRK_SP6_MASK (0x40U)
2809#define AIPS_PACRK_SP6_SHIFT (6U)
2810/*! SP6 - Supervisor Protect
2811 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2812 * 0b1..This peripheral requires supervisor privilege level for accesses.
2813 */
2814#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
2815#define AIPS_PACRK_TP5_MASK (0x100U)
2816#define AIPS_PACRK_TP5_SHIFT (8U)
2817/*! TP5 - Trusted Protect
2818 * 0b0..Accesses from an untrusted master are allowed.
2819 * 0b1..Accesses from an untrusted master are not allowed.
2820 */
2821#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
2822#define AIPS_PACRK_WP5_MASK (0x200U)
2823#define AIPS_PACRK_WP5_SHIFT (9U)
2824/*! WP5 - Write Protect
2825 * 0b0..This peripheral allows write accesses.
2826 * 0b1..This peripheral is write protected.
2827 */
2828#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
2829#define AIPS_PACRK_SP5_MASK (0x400U)
2830#define AIPS_PACRK_SP5_SHIFT (10U)
2831/*! SP5 - Supervisor Protect
2832 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2833 * 0b1..This peripheral requires supervisor privilege level for accesses.
2834 */
2835#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
2836#define AIPS_PACRK_TP4_MASK (0x1000U)
2837#define AIPS_PACRK_TP4_SHIFT (12U)
2838/*! TP4 - Trusted Protect
2839 * 0b0..Accesses from an untrusted master are allowed.
2840 * 0b1..Accesses from an untrusted master are not allowed.
2841 */
2842#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
2843#define AIPS_PACRK_WP4_MASK (0x2000U)
2844#define AIPS_PACRK_WP4_SHIFT (13U)
2845/*! WP4 - Write Protect
2846 * 0b0..This peripheral allows write accesses.
2847 * 0b1..This peripheral is write protected.
2848 */
2849#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
2850#define AIPS_PACRK_SP4_MASK (0x4000U)
2851#define AIPS_PACRK_SP4_SHIFT (14U)
2852/*! SP4 - Supervisor Protect
2853 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2854 * 0b1..This peripheral requires supervisor privilege level for accesses.
2855 */
2856#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
2857#define AIPS_PACRK_TP3_MASK (0x10000U)
2858#define AIPS_PACRK_TP3_SHIFT (16U)
2859/*! TP3 - Trusted Protect
2860 * 0b0..Accesses from an untrusted master are allowed.
2861 * 0b1..Accesses from an untrusted master are not allowed.
2862 */
2863#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
2864#define AIPS_PACRK_WP3_MASK (0x20000U)
2865#define AIPS_PACRK_WP3_SHIFT (17U)
2866/*! WP3 - Write Protect
2867 * 0b0..This peripheral allows write accesses.
2868 * 0b1..This peripheral is write protected.
2869 */
2870#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
2871#define AIPS_PACRK_SP3_MASK (0x40000U)
2872#define AIPS_PACRK_SP3_SHIFT (18U)
2873/*! SP3 - Supervisor Protect
2874 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2875 * 0b1..This peripheral requires supervisor privilege level for accesses.
2876 */
2877#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
2878#define AIPS_PACRK_TP2_MASK (0x100000U)
2879#define AIPS_PACRK_TP2_SHIFT (20U)
2880/*! TP2 - Trusted Protect
2881 * 0b0..Accesses from an untrusted master are allowed.
2882 * 0b1..Accesses from an untrusted master are not allowed.
2883 */
2884#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
2885#define AIPS_PACRK_WP2_MASK (0x200000U)
2886#define AIPS_PACRK_WP2_SHIFT (21U)
2887/*! WP2 - Write Protect
2888 * 0b0..This peripheral allows write accesses.
2889 * 0b1..This peripheral is write protected.
2890 */
2891#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
2892#define AIPS_PACRK_SP2_MASK (0x400000U)
2893#define AIPS_PACRK_SP2_SHIFT (22U)
2894/*! SP2 - Supervisor Protect
2895 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2896 * 0b1..This peripheral requires supervisor privilege level for accesses.
2897 */
2898#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
2899#define AIPS_PACRK_TP1_MASK (0x1000000U)
2900#define AIPS_PACRK_TP1_SHIFT (24U)
2901/*! TP1 - Trusted Protect
2902 * 0b0..Accesses from an untrusted master are allowed.
2903 * 0b1..Accesses from an untrusted master are not allowed.
2904 */
2905#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
2906#define AIPS_PACRK_WP1_MASK (0x2000000U)
2907#define AIPS_PACRK_WP1_SHIFT (25U)
2908/*! WP1 - Write Protect
2909 * 0b0..This peripheral allows write accesses.
2910 * 0b1..This peripheral is write protected.
2911 */
2912#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
2913#define AIPS_PACRK_SP1_MASK (0x4000000U)
2914#define AIPS_PACRK_SP1_SHIFT (26U)
2915/*! SP1 - Supervisor Protect
2916 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2917 * 0b1..This peripheral requires supervisor privilege level for accesses.
2918 */
2919#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
2920#define AIPS_PACRK_TP0_MASK (0x10000000U)
2921#define AIPS_PACRK_TP0_SHIFT (28U)
2922/*! TP0 - Trusted Protect
2923 * 0b0..Accesses from an untrusted master are allowed.
2924 * 0b1..Accesses from an untrusted master are not allowed.
2925 */
2926#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
2927#define AIPS_PACRK_WP0_MASK (0x20000000U)
2928#define AIPS_PACRK_WP0_SHIFT (29U)
2929/*! WP0 - Write Protect
2930 * 0b0..This peripheral allows write accesses.
2931 * 0b1..This peripheral is write protected.
2932 */
2933#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
2934#define AIPS_PACRK_SP0_MASK (0x40000000U)
2935#define AIPS_PACRK_SP0_SHIFT (30U)
2936/*! SP0 - Supervisor Protect
2937 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2938 * 0b1..This peripheral requires supervisor privilege level for accesses.
2939 */
2940#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
2941/*! @} */
2942
2943/*! @name PACRL - Peripheral Access Control Register */
2944/*! @{ */
2945#define AIPS_PACRL_TP7_MASK (0x1U)
2946#define AIPS_PACRL_TP7_SHIFT (0U)
2947/*! TP7 - Trusted Protect
2948 * 0b0..Accesses from an untrusted master are allowed.
2949 * 0b1..Accesses from an untrusted master are not allowed.
2950 */
2951#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
2952#define AIPS_PACRL_WP7_MASK (0x2U)
2953#define AIPS_PACRL_WP7_SHIFT (1U)
2954/*! WP7 - Write Protect
2955 * 0b0..This peripheral allows write accesses.
2956 * 0b1..This peripheral is write protected.
2957 */
2958#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
2959#define AIPS_PACRL_SP7_MASK (0x4U)
2960#define AIPS_PACRL_SP7_SHIFT (2U)
2961/*! SP7 - Supervisor Protect
2962 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2963 * 0b1..This peripheral requires supervisor privilege level for accesses.
2964 */
2965#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
2966#define AIPS_PACRL_TP6_MASK (0x10U)
2967#define AIPS_PACRL_TP6_SHIFT (4U)
2968/*! TP6 - Trusted Protect
2969 * 0b0..Accesses from an untrusted master are allowed.
2970 * 0b1..Accesses from an untrusted master are not allowed.
2971 */
2972#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
2973#define AIPS_PACRL_WP6_MASK (0x20U)
2974#define AIPS_PACRL_WP6_SHIFT (5U)
2975/*! WP6 - Write Protect
2976 * 0b0..This peripheral allows write accesses.
2977 * 0b1..This peripheral is write protected.
2978 */
2979#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
2980#define AIPS_PACRL_SP6_MASK (0x40U)
2981#define AIPS_PACRL_SP6_SHIFT (6U)
2982/*! SP6 - Supervisor Protect
2983 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2984 * 0b1..This peripheral requires supervisor privilege level for accesses.
2985 */
2986#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
2987#define AIPS_PACRL_TP5_MASK (0x100U)
2988#define AIPS_PACRL_TP5_SHIFT (8U)
2989/*! TP5 - Trusted Protect
2990 * 0b0..Accesses from an untrusted master are allowed.
2991 * 0b1..Accesses from an untrusted master are not allowed.
2992 */
2993#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
2994#define AIPS_PACRL_WP5_MASK (0x200U)
2995#define AIPS_PACRL_WP5_SHIFT (9U)
2996/*! WP5 - Write Protect
2997 * 0b0..This peripheral allows write accesses.
2998 * 0b1..This peripheral is write protected.
2999 */
3000#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
3001#define AIPS_PACRL_SP5_MASK (0x400U)
3002#define AIPS_PACRL_SP5_SHIFT (10U)
3003/*! SP5 - Supervisor Protect
3004 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3005 * 0b1..This peripheral requires supervisor privilege level for accesses.
3006 */
3007#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
3008#define AIPS_PACRL_TP4_MASK (0x1000U)
3009#define AIPS_PACRL_TP4_SHIFT (12U)
3010/*! TP4 - Trusted Protect
3011 * 0b0..Accesses from an untrusted master are allowed.
3012 * 0b1..Accesses from an untrusted master are not allowed.
3013 */
3014#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
3015#define AIPS_PACRL_WP4_MASK (0x2000U)
3016#define AIPS_PACRL_WP4_SHIFT (13U)
3017/*! WP4 - Write Protect
3018 * 0b0..This peripheral allows write accesses.
3019 * 0b1..This peripheral is write protected.
3020 */
3021#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
3022#define AIPS_PACRL_SP4_MASK (0x4000U)
3023#define AIPS_PACRL_SP4_SHIFT (14U)
3024/*! SP4 - Supervisor Protect
3025 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3026 * 0b1..This peripheral requires supervisor privilege level for accesses.
3027 */
3028#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
3029#define AIPS_PACRL_TP3_MASK (0x10000U)
3030#define AIPS_PACRL_TP3_SHIFT (16U)
3031/*! TP3 - Trusted Protect
3032 * 0b0..Accesses from an untrusted master are allowed.
3033 * 0b1..Accesses from an untrusted master are not allowed.
3034 */
3035#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
3036#define AIPS_PACRL_WP3_MASK (0x20000U)
3037#define AIPS_PACRL_WP3_SHIFT (17U)
3038/*! WP3 - Write Protect
3039 * 0b0..This peripheral allows write accesses.
3040 * 0b1..This peripheral is write protected.
3041 */
3042#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
3043#define AIPS_PACRL_SP3_MASK (0x40000U)
3044#define AIPS_PACRL_SP3_SHIFT (18U)
3045/*! SP3 - Supervisor Protect
3046 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3047 * 0b1..This peripheral requires supervisor privilege level for accesses.
3048 */
3049#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
3050#define AIPS_PACRL_TP2_MASK (0x100000U)
3051#define AIPS_PACRL_TP2_SHIFT (20U)
3052/*! TP2 - Trusted Protect
3053 * 0b0..Accesses from an untrusted master are allowed.
3054 * 0b1..Accesses from an untrusted master are not allowed.
3055 */
3056#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
3057#define AIPS_PACRL_WP2_MASK (0x200000U)
3058#define AIPS_PACRL_WP2_SHIFT (21U)
3059/*! WP2 - Write Protect
3060 * 0b0..This peripheral allows write accesses.
3061 * 0b1..This peripheral is write protected.
3062 */
3063#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
3064#define AIPS_PACRL_SP2_MASK (0x400000U)
3065#define AIPS_PACRL_SP2_SHIFT (22U)
3066/*! SP2 - Supervisor Protect
3067 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3068 * 0b1..This peripheral requires supervisor privilege level for accesses.
3069 */
3070#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
3071#define AIPS_PACRL_TP1_MASK (0x1000000U)
3072#define AIPS_PACRL_TP1_SHIFT (24U)
3073/*! TP1 - Trusted Protect
3074 * 0b0..Accesses from an untrusted master are allowed.
3075 * 0b1..Accesses from an untrusted master are not allowed.
3076 */
3077#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
3078#define AIPS_PACRL_WP1_MASK (0x2000000U)
3079#define AIPS_PACRL_WP1_SHIFT (25U)
3080/*! WP1 - Write Protect
3081 * 0b0..This peripheral allows write accesses.
3082 * 0b1..This peripheral is write protected.
3083 */
3084#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
3085#define AIPS_PACRL_SP1_MASK (0x4000000U)
3086#define AIPS_PACRL_SP1_SHIFT (26U)
3087/*! SP1 - Supervisor Protect
3088 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3089 * 0b1..This peripheral requires supervisor privilege level for accesses.
3090 */
3091#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
3092#define AIPS_PACRL_TP0_MASK (0x10000000U)
3093#define AIPS_PACRL_TP0_SHIFT (28U)
3094/*! TP0 - Trusted Protect
3095 * 0b0..Accesses from an untrusted master are allowed.
3096 * 0b1..Accesses from an untrusted master are not allowed.
3097 */
3098#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
3099#define AIPS_PACRL_WP0_MASK (0x20000000U)
3100#define AIPS_PACRL_WP0_SHIFT (29U)
3101/*! WP0 - Write Protect
3102 * 0b0..This peripheral allows write accesses.
3103 * 0b1..This peripheral is write protected.
3104 */
3105#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
3106#define AIPS_PACRL_SP0_MASK (0x40000000U)
3107#define AIPS_PACRL_SP0_SHIFT (30U)
3108/*! SP0 - Supervisor Protect
3109 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3110 * 0b1..This peripheral requires supervisor privilege level for accesses.
3111 */
3112#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
3113/*! @} */
3114
3115/*! @name PACRM - Peripheral Access Control Register */
3116/*! @{ */
3117#define AIPS_PACRM_TP7_MASK (0x1U)
3118#define AIPS_PACRM_TP7_SHIFT (0U)
3119/*! TP7 - Trusted Protect
3120 * 0b0..Accesses from an untrusted master are allowed.
3121 * 0b1..Accesses from an untrusted master are not allowed.
3122 */
3123#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
3124#define AIPS_PACRM_WP7_MASK (0x2U)
3125#define AIPS_PACRM_WP7_SHIFT (1U)
3126/*! WP7 - Write Protect
3127 * 0b0..This peripheral allows write accesses.
3128 * 0b1..This peripheral is write protected.
3129 */
3130#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
3131#define AIPS_PACRM_SP7_MASK (0x4U)
3132#define AIPS_PACRM_SP7_SHIFT (2U)
3133/*! SP7 - Supervisor Protect
3134 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3135 * 0b1..This peripheral requires supervisor privilege level for accesses.
3136 */
3137#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
3138#define AIPS_PACRM_TP6_MASK (0x10U)
3139#define AIPS_PACRM_TP6_SHIFT (4U)
3140/*! TP6 - Trusted Protect
3141 * 0b0..Accesses from an untrusted master are allowed.
3142 * 0b1..Accesses from an untrusted master are not allowed.
3143 */
3144#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
3145#define AIPS_PACRM_WP6_MASK (0x20U)
3146#define AIPS_PACRM_WP6_SHIFT (5U)
3147/*! WP6 - Write Protect
3148 * 0b0..This peripheral allows write accesses.
3149 * 0b1..This peripheral is write protected.
3150 */
3151#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
3152#define AIPS_PACRM_SP6_MASK (0x40U)
3153#define AIPS_PACRM_SP6_SHIFT (6U)
3154/*! SP6 - Supervisor Protect
3155 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3156 * 0b1..This peripheral requires supervisor privilege level for accesses.
3157 */
3158#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
3159#define AIPS_PACRM_TP5_MASK (0x100U)
3160#define AIPS_PACRM_TP5_SHIFT (8U)
3161/*! TP5 - Trusted Protect
3162 * 0b0..Accesses from an untrusted master are allowed.
3163 * 0b1..Accesses from an untrusted master are not allowed.
3164 */
3165#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
3166#define AIPS_PACRM_WP5_MASK (0x200U)
3167#define AIPS_PACRM_WP5_SHIFT (9U)
3168/*! WP5 - Write Protect
3169 * 0b0..This peripheral allows write accesses.
3170 * 0b1..This peripheral is write protected.
3171 */
3172#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
3173#define AIPS_PACRM_SP5_MASK (0x400U)
3174#define AIPS_PACRM_SP5_SHIFT (10U)
3175/*! SP5 - Supervisor Protect
3176 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3177 * 0b1..This peripheral requires supervisor privilege level for accesses.
3178 */
3179#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
3180#define AIPS_PACRM_TP4_MASK (0x1000U)
3181#define AIPS_PACRM_TP4_SHIFT (12U)
3182/*! TP4 - Trusted Protect
3183 * 0b0..Accesses from an untrusted master are allowed.
3184 * 0b1..Accesses from an untrusted master are not allowed.
3185 */
3186#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
3187#define AIPS_PACRM_WP4_MASK (0x2000U)
3188#define AIPS_PACRM_WP4_SHIFT (13U)
3189/*! WP4 - Write Protect
3190 * 0b0..This peripheral allows write accesses.
3191 * 0b1..This peripheral is write protected.
3192 */
3193#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
3194#define AIPS_PACRM_SP4_MASK (0x4000U)
3195#define AIPS_PACRM_SP4_SHIFT (14U)
3196/*! SP4 - Supervisor Protect
3197 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3198 * 0b1..This peripheral requires supervisor privilege level for accesses.
3199 */
3200#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
3201#define AIPS_PACRM_TP3_MASK (0x10000U)
3202#define AIPS_PACRM_TP3_SHIFT (16U)
3203/*! TP3 - Trusted Protect
3204 * 0b0..Accesses from an untrusted master are allowed.
3205 * 0b1..Accesses from an untrusted master are not allowed.
3206 */
3207#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
3208#define AIPS_PACRM_WP3_MASK (0x20000U)
3209#define AIPS_PACRM_WP3_SHIFT (17U)
3210/*! WP3 - Write Protect
3211 * 0b0..This peripheral allows write accesses.
3212 * 0b1..This peripheral is write protected.
3213 */
3214#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
3215#define AIPS_PACRM_SP3_MASK (0x40000U)
3216#define AIPS_PACRM_SP3_SHIFT (18U)
3217/*! SP3 - Supervisor Protect
3218 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3219 * 0b1..This peripheral requires supervisor privilege level for accesses.
3220 */
3221#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
3222#define AIPS_PACRM_TP2_MASK (0x100000U)
3223#define AIPS_PACRM_TP2_SHIFT (20U)
3224/*! TP2 - Trusted Protect
3225 * 0b0..Accesses from an untrusted master are allowed.
3226 * 0b1..Accesses from an untrusted master are not allowed.
3227 */
3228#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
3229#define AIPS_PACRM_WP2_MASK (0x200000U)
3230#define AIPS_PACRM_WP2_SHIFT (21U)
3231/*! WP2 - Write Protect
3232 * 0b0..This peripheral allows write accesses.
3233 * 0b1..This peripheral is write protected.
3234 */
3235#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
3236#define AIPS_PACRM_SP2_MASK (0x400000U)
3237#define AIPS_PACRM_SP2_SHIFT (22U)
3238/*! SP2 - Supervisor Protect
3239 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3240 * 0b1..This peripheral requires supervisor privilege level for accesses.
3241 */
3242#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
3243#define AIPS_PACRM_TP1_MASK (0x1000000U)
3244#define AIPS_PACRM_TP1_SHIFT (24U)
3245/*! TP1 - Trusted Protect
3246 * 0b0..Accesses from an untrusted master are allowed.
3247 * 0b1..Accesses from an untrusted master are not allowed.
3248 */
3249#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
3250#define AIPS_PACRM_WP1_MASK (0x2000000U)
3251#define AIPS_PACRM_WP1_SHIFT (25U)
3252/*! WP1 - Write Protect
3253 * 0b0..This peripheral allows write accesses.
3254 * 0b1..This peripheral is write protected.
3255 */
3256#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
3257#define AIPS_PACRM_SP1_MASK (0x4000000U)
3258#define AIPS_PACRM_SP1_SHIFT (26U)
3259/*! SP1 - Supervisor Protect
3260 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3261 * 0b1..This peripheral requires supervisor privilege level for accesses.
3262 */
3263#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
3264#define AIPS_PACRM_TP0_MASK (0x10000000U)
3265#define AIPS_PACRM_TP0_SHIFT (28U)
3266/*! TP0 - Trusted Protect
3267 * 0b0..Accesses from an untrusted master are allowed.
3268 * 0b1..Accesses from an untrusted master are not allowed.
3269 */
3270#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
3271#define AIPS_PACRM_WP0_MASK (0x20000000U)
3272#define AIPS_PACRM_WP0_SHIFT (29U)
3273/*! WP0 - Write Protect
3274 * 0b0..This peripheral allows write accesses.
3275 * 0b1..This peripheral is write protected.
3276 */
3277#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
3278#define AIPS_PACRM_SP0_MASK (0x40000000U)
3279#define AIPS_PACRM_SP0_SHIFT (30U)
3280/*! SP0 - Supervisor Protect
3281 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3282 * 0b1..This peripheral requires supervisor privilege level for accesses.
3283 */
3284#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
3285/*! @} */
3286
3287/*! @name PACRN - Peripheral Access Control Register */
3288/*! @{ */
3289#define AIPS_PACRN_TP7_MASK (0x1U)
3290#define AIPS_PACRN_TP7_SHIFT (0U)
3291/*! TP7 - Trusted Protect
3292 * 0b0..Accesses from an untrusted master are allowed.
3293 * 0b1..Accesses from an untrusted master are not allowed.
3294 */
3295#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
3296#define AIPS_PACRN_WP7_MASK (0x2U)
3297#define AIPS_PACRN_WP7_SHIFT (1U)
3298/*! WP7 - Write Protect
3299 * 0b0..This peripheral allows write accesses.
3300 * 0b1..This peripheral is write protected.
3301 */
3302#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
3303#define AIPS_PACRN_SP7_MASK (0x4U)
3304#define AIPS_PACRN_SP7_SHIFT (2U)
3305/*! SP7 - Supervisor Protect
3306 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3307 * 0b1..This peripheral requires supervisor privilege level for accesses.
3308 */
3309#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
3310#define AIPS_PACRN_TP6_MASK (0x10U)
3311#define AIPS_PACRN_TP6_SHIFT (4U)
3312/*! TP6 - Trusted Protect
3313 * 0b0..Accesses from an untrusted master are allowed.
3314 * 0b1..Accesses from an untrusted master are not allowed.
3315 */
3316#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
3317#define AIPS_PACRN_WP6_MASK (0x20U)
3318#define AIPS_PACRN_WP6_SHIFT (5U)
3319/*! WP6 - Write Protect
3320 * 0b0..This peripheral allows write accesses.
3321 * 0b1..This peripheral is write protected.
3322 */
3323#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
3324#define AIPS_PACRN_SP6_MASK (0x40U)
3325#define AIPS_PACRN_SP6_SHIFT (6U)
3326/*! SP6 - Supervisor Protect
3327 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3328 * 0b1..This peripheral requires supervisor privilege level for accesses.
3329 */
3330#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
3331#define AIPS_PACRN_TP5_MASK (0x100U)
3332#define AIPS_PACRN_TP5_SHIFT (8U)
3333/*! TP5 - Trusted Protect
3334 * 0b0..Accesses from an untrusted master are allowed.
3335 * 0b1..Accesses from an untrusted master are not allowed.
3336 */
3337#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
3338#define AIPS_PACRN_WP5_MASK (0x200U)
3339#define AIPS_PACRN_WP5_SHIFT (9U)
3340/*! WP5 - Write Protect
3341 * 0b0..This peripheral allows write accesses.
3342 * 0b1..This peripheral is write protected.
3343 */
3344#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
3345#define AIPS_PACRN_SP5_MASK (0x400U)
3346#define AIPS_PACRN_SP5_SHIFT (10U)
3347/*! SP5 - Supervisor Protect
3348 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3349 * 0b1..This peripheral requires supervisor privilege level for accesses.
3350 */
3351#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
3352#define AIPS_PACRN_TP4_MASK (0x1000U)
3353#define AIPS_PACRN_TP4_SHIFT (12U)
3354/*! TP4 - Trusted Protect
3355 * 0b0..Accesses from an untrusted master are allowed.
3356 * 0b1..Accesses from an untrusted master are not allowed.
3357 */
3358#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
3359#define AIPS_PACRN_WP4_MASK (0x2000U)
3360#define AIPS_PACRN_WP4_SHIFT (13U)
3361/*! WP4 - Write Protect
3362 * 0b0..This peripheral allows write accesses.
3363 * 0b1..This peripheral is write protected.
3364 */
3365#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
3366#define AIPS_PACRN_SP4_MASK (0x4000U)
3367#define AIPS_PACRN_SP4_SHIFT (14U)
3368/*! SP4 - Supervisor Protect
3369 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3370 * 0b1..This peripheral requires supervisor privilege level for accesses.
3371 */
3372#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
3373#define AIPS_PACRN_TP3_MASK (0x10000U)
3374#define AIPS_PACRN_TP3_SHIFT (16U)
3375/*! TP3 - Trusted Protect
3376 * 0b0..Accesses from an untrusted master are allowed.
3377 * 0b1..Accesses from an untrusted master are not allowed.
3378 */
3379#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
3380#define AIPS_PACRN_WP3_MASK (0x20000U)
3381#define AIPS_PACRN_WP3_SHIFT (17U)
3382/*! WP3 - Write Protect
3383 * 0b0..This peripheral allows write accesses.
3384 * 0b1..This peripheral is write protected.
3385 */
3386#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
3387#define AIPS_PACRN_SP3_MASK (0x40000U)
3388#define AIPS_PACRN_SP3_SHIFT (18U)
3389/*! SP3 - Supervisor Protect
3390 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3391 * 0b1..This peripheral requires supervisor privilege level for accesses.
3392 */
3393#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
3394#define AIPS_PACRN_TP2_MASK (0x100000U)
3395#define AIPS_PACRN_TP2_SHIFT (20U)
3396/*! TP2 - Trusted Protect
3397 * 0b0..Accesses from an untrusted master are allowed.
3398 * 0b1..Accesses from an untrusted master are not allowed.
3399 */
3400#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
3401#define AIPS_PACRN_WP2_MASK (0x200000U)
3402#define AIPS_PACRN_WP2_SHIFT (21U)
3403/*! WP2 - Write Protect
3404 * 0b0..This peripheral allows write accesses.
3405 * 0b1..This peripheral is write protected.
3406 */
3407#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
3408#define AIPS_PACRN_SP2_MASK (0x400000U)
3409#define AIPS_PACRN_SP2_SHIFT (22U)
3410/*! SP2 - Supervisor Protect
3411 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3412 * 0b1..This peripheral requires supervisor privilege level for accesses.
3413 */
3414#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
3415#define AIPS_PACRN_TP1_MASK (0x1000000U)
3416#define AIPS_PACRN_TP1_SHIFT (24U)
3417/*! TP1 - Trusted Protect
3418 * 0b0..Accesses from an untrusted master are allowed.
3419 * 0b1..Accesses from an untrusted master are not allowed.
3420 */
3421#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
3422#define AIPS_PACRN_WP1_MASK (0x2000000U)
3423#define AIPS_PACRN_WP1_SHIFT (25U)
3424/*! WP1 - Write Protect
3425 * 0b0..This peripheral allows write accesses.
3426 * 0b1..This peripheral is write protected.
3427 */
3428#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
3429#define AIPS_PACRN_SP1_MASK (0x4000000U)
3430#define AIPS_PACRN_SP1_SHIFT (26U)
3431/*! SP1 - Supervisor Protect
3432 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3433 * 0b1..This peripheral requires supervisor privilege level for accesses.
3434 */
3435#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
3436#define AIPS_PACRN_TP0_MASK (0x10000000U)
3437#define AIPS_PACRN_TP0_SHIFT (28U)
3438/*! TP0 - Trusted Protect
3439 * 0b0..Accesses from an untrusted master are allowed.
3440 * 0b1..Accesses from an untrusted master are not allowed.
3441 */
3442#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
3443#define AIPS_PACRN_WP0_MASK (0x20000000U)
3444#define AIPS_PACRN_WP0_SHIFT (29U)
3445/*! WP0 - Write Protect
3446 * 0b0..This peripheral allows write accesses.
3447 * 0b1..This peripheral is write protected.
3448 */
3449#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
3450#define AIPS_PACRN_SP0_MASK (0x40000000U)
3451#define AIPS_PACRN_SP0_SHIFT (30U)
3452/*! SP0 - Supervisor Protect
3453 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3454 * 0b1..This peripheral requires supervisor privilege level for accesses.
3455 */
3456#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
3457/*! @} */
3458
3459/*! @name PACRO - Peripheral Access Control Register */
3460/*! @{ */
3461#define AIPS_PACRO_TP7_MASK (0x1U)
3462#define AIPS_PACRO_TP7_SHIFT (0U)
3463/*! TP7 - Trusted Protect
3464 * 0b0..Accesses from an untrusted master are allowed.
3465 * 0b1..Accesses from an untrusted master are not allowed.
3466 */
3467#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
3468#define AIPS_PACRO_WP7_MASK (0x2U)
3469#define AIPS_PACRO_WP7_SHIFT (1U)
3470/*! WP7 - Write Protect
3471 * 0b0..This peripheral allows write accesses.
3472 * 0b1..This peripheral is write protected.
3473 */
3474#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
3475#define AIPS_PACRO_SP7_MASK (0x4U)
3476#define AIPS_PACRO_SP7_SHIFT (2U)
3477/*! SP7 - Supervisor Protect
3478 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3479 * 0b1..This peripheral requires supervisor privilege level for accesses.
3480 */
3481#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
3482#define AIPS_PACRO_TP6_MASK (0x10U)
3483#define AIPS_PACRO_TP6_SHIFT (4U)
3484/*! TP6 - Trusted Protect
3485 * 0b0..Accesses from an untrusted master are allowed.
3486 * 0b1..Accesses from an untrusted master are not allowed.
3487 */
3488#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
3489#define AIPS_PACRO_WP6_MASK (0x20U)
3490#define AIPS_PACRO_WP6_SHIFT (5U)
3491/*! WP6 - Write Protect
3492 * 0b0..This peripheral allows write accesses.
3493 * 0b1..This peripheral is write protected.
3494 */
3495#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
3496#define AIPS_PACRO_SP6_MASK (0x40U)
3497#define AIPS_PACRO_SP6_SHIFT (6U)
3498/*! SP6 - Supervisor Protect
3499 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3500 * 0b1..This peripheral requires supervisor privilege level for accesses.
3501 */
3502#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
3503#define AIPS_PACRO_TP5_MASK (0x100U)
3504#define AIPS_PACRO_TP5_SHIFT (8U)
3505/*! TP5 - Trusted Protect
3506 * 0b0..Accesses from an untrusted master are allowed.
3507 * 0b1..Accesses from an untrusted master are not allowed.
3508 */
3509#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
3510#define AIPS_PACRO_WP5_MASK (0x200U)
3511#define AIPS_PACRO_WP5_SHIFT (9U)
3512/*! WP5 - Write Protect
3513 * 0b0..This peripheral allows write accesses.
3514 * 0b1..This peripheral is write protected.
3515 */
3516#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
3517#define AIPS_PACRO_SP5_MASK (0x400U)
3518#define AIPS_PACRO_SP5_SHIFT (10U)
3519/*! SP5 - Supervisor Protect
3520 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3521 * 0b1..This peripheral requires supervisor privilege level for accesses.
3522 */
3523#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
3524#define AIPS_PACRO_TP4_MASK (0x1000U)
3525#define AIPS_PACRO_TP4_SHIFT (12U)
3526/*! TP4 - Trusted Protect
3527 * 0b0..Accesses from an untrusted master are allowed.
3528 * 0b1..Accesses from an untrusted master are not allowed.
3529 */
3530#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
3531#define AIPS_PACRO_WP4_MASK (0x2000U)
3532#define AIPS_PACRO_WP4_SHIFT (13U)
3533/*! WP4 - Write Protect
3534 * 0b0..This peripheral allows write accesses.
3535 * 0b1..This peripheral is write protected.
3536 */
3537#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
3538#define AIPS_PACRO_SP4_MASK (0x4000U)
3539#define AIPS_PACRO_SP4_SHIFT (14U)
3540/*! SP4 - Supervisor Protect
3541 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3542 * 0b1..This peripheral requires supervisor privilege level for accesses.
3543 */
3544#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
3545#define AIPS_PACRO_TP3_MASK (0x10000U)
3546#define AIPS_PACRO_TP3_SHIFT (16U)
3547/*! TP3 - Trusted Protect
3548 * 0b0..Accesses from an untrusted master are allowed.
3549 * 0b1..Accesses from an untrusted master are not allowed.
3550 */
3551#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
3552#define AIPS_PACRO_WP3_MASK (0x20000U)
3553#define AIPS_PACRO_WP3_SHIFT (17U)
3554/*! WP3 - Write Protect
3555 * 0b0..This peripheral allows write accesses.
3556 * 0b1..This peripheral is write protected.
3557 */
3558#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
3559#define AIPS_PACRO_SP3_MASK (0x40000U)
3560#define AIPS_PACRO_SP3_SHIFT (18U)
3561/*! SP3 - Supervisor Protect
3562 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3563 * 0b1..This peripheral requires supervisor privilege level for accesses.
3564 */
3565#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
3566#define AIPS_PACRO_TP2_MASK (0x100000U)
3567#define AIPS_PACRO_TP2_SHIFT (20U)
3568/*! TP2 - Trusted Protect
3569 * 0b0..Accesses from an untrusted master are allowed.
3570 * 0b1..Accesses from an untrusted master are not allowed.
3571 */
3572#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
3573#define AIPS_PACRO_WP2_MASK (0x200000U)
3574#define AIPS_PACRO_WP2_SHIFT (21U)
3575/*! WP2 - Write Protect
3576 * 0b0..This peripheral allows write accesses.
3577 * 0b1..This peripheral is write protected.
3578 */
3579#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
3580#define AIPS_PACRO_SP2_MASK (0x400000U)
3581#define AIPS_PACRO_SP2_SHIFT (22U)
3582/*! SP2 - Supervisor Protect
3583 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3584 * 0b1..This peripheral requires supervisor privilege level for accesses.
3585 */
3586#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
3587#define AIPS_PACRO_TP1_MASK (0x1000000U)
3588#define AIPS_PACRO_TP1_SHIFT (24U)
3589/*! TP1 - Trusted Protect
3590 * 0b0..Accesses from an untrusted master are allowed.
3591 * 0b1..Accesses from an untrusted master are not allowed.
3592 */
3593#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
3594#define AIPS_PACRO_WP1_MASK (0x2000000U)
3595#define AIPS_PACRO_WP1_SHIFT (25U)
3596/*! WP1 - Write Protect
3597 * 0b0..This peripheral allows write accesses.
3598 * 0b1..This peripheral is write protected.
3599 */
3600#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
3601#define AIPS_PACRO_SP1_MASK (0x4000000U)
3602#define AIPS_PACRO_SP1_SHIFT (26U)
3603/*! SP1 - Supervisor Protect
3604 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3605 * 0b1..This peripheral requires supervisor privilege level for accesses.
3606 */
3607#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
3608#define AIPS_PACRO_TP0_MASK (0x10000000U)
3609#define AIPS_PACRO_TP0_SHIFT (28U)
3610/*! TP0 - Trusted Protect
3611 * 0b0..Accesses from an untrusted master are allowed.
3612 * 0b1..Accesses from an untrusted master are not allowed.
3613 */
3614#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
3615#define AIPS_PACRO_WP0_MASK (0x20000000U)
3616#define AIPS_PACRO_WP0_SHIFT (29U)
3617/*! WP0 - Write Protect
3618 * 0b0..This peripheral allows write accesses.
3619 * 0b1..This peripheral is write protected.
3620 */
3621#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
3622#define AIPS_PACRO_SP0_MASK (0x40000000U)
3623#define AIPS_PACRO_SP0_SHIFT (30U)
3624/*! SP0 - Supervisor Protect
3625 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3626 * 0b1..This peripheral requires supervisor privilege level for accesses.
3627 */
3628#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
3629/*! @} */
3630
3631/*! @name PACRP - Peripheral Access Control Register */
3632/*! @{ */
3633#define AIPS_PACRP_TP7_MASK (0x1U)
3634#define AIPS_PACRP_TP7_SHIFT (0U)
3635/*! TP7 - Trusted Protect
3636 * 0b0..Accesses from an untrusted master are allowed.
3637 * 0b1..Accesses from an untrusted master are not allowed.
3638 */
3639#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
3640#define AIPS_PACRP_WP7_MASK (0x2U)
3641#define AIPS_PACRP_WP7_SHIFT (1U)
3642/*! WP7 - Write Protect
3643 * 0b0..This peripheral allows write accesses.
3644 * 0b1..This peripheral is write protected.
3645 */
3646#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
3647#define AIPS_PACRP_SP7_MASK (0x4U)
3648#define AIPS_PACRP_SP7_SHIFT (2U)
3649/*! SP7 - Supervisor Protect
3650 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3651 * 0b1..This peripheral requires supervisor privilege level for accesses.
3652 */
3653#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
3654#define AIPS_PACRP_TP6_MASK (0x10U)
3655#define AIPS_PACRP_TP6_SHIFT (4U)
3656/*! TP6 - Trusted Protect
3657 * 0b0..Accesses from an untrusted master are allowed.
3658 * 0b1..Accesses from an untrusted master are not allowed.
3659 */
3660#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
3661#define AIPS_PACRP_WP6_MASK (0x20U)
3662#define AIPS_PACRP_WP6_SHIFT (5U)
3663/*! WP6 - Write Protect
3664 * 0b0..This peripheral allows write accesses.
3665 * 0b1..This peripheral is write protected.
3666 */
3667#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
3668#define AIPS_PACRP_SP6_MASK (0x40U)
3669#define AIPS_PACRP_SP6_SHIFT (6U)
3670/*! SP6 - Supervisor Protect
3671 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3672 * 0b1..This peripheral requires supervisor privilege level for accesses.
3673 */
3674#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
3675#define AIPS_PACRP_TP5_MASK (0x100U)
3676#define AIPS_PACRP_TP5_SHIFT (8U)
3677/*! TP5 - Trusted Protect
3678 * 0b0..Accesses from an untrusted master are allowed.
3679 * 0b1..Accesses from an untrusted master are not allowed.
3680 */
3681#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
3682#define AIPS_PACRP_WP5_MASK (0x200U)
3683#define AIPS_PACRP_WP5_SHIFT (9U)
3684/*! WP5 - Write Protect
3685 * 0b0..This peripheral allows write accesses.
3686 * 0b1..This peripheral is write protected.
3687 */
3688#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
3689#define AIPS_PACRP_SP5_MASK (0x400U)
3690#define AIPS_PACRP_SP5_SHIFT (10U)
3691/*! SP5 - Supervisor Protect
3692 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3693 * 0b1..This peripheral requires supervisor privilege level for accesses.
3694 */
3695#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
3696#define AIPS_PACRP_TP4_MASK (0x1000U)
3697#define AIPS_PACRP_TP4_SHIFT (12U)
3698/*! TP4 - Trusted Protect
3699 * 0b0..Accesses from an untrusted master are allowed.
3700 * 0b1..Accesses from an untrusted master are not allowed.
3701 */
3702#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
3703#define AIPS_PACRP_WP4_MASK (0x2000U)
3704#define AIPS_PACRP_WP4_SHIFT (13U)
3705/*! WP4 - Write Protect
3706 * 0b0..This peripheral allows write accesses.
3707 * 0b1..This peripheral is write protected.
3708 */
3709#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
3710#define AIPS_PACRP_SP4_MASK (0x4000U)
3711#define AIPS_PACRP_SP4_SHIFT (14U)
3712/*! SP4 - Supervisor Protect
3713 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3714 * 0b1..This peripheral requires supervisor privilege level for accesses.
3715 */
3716#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
3717#define AIPS_PACRP_TP3_MASK (0x10000U)
3718#define AIPS_PACRP_TP3_SHIFT (16U)
3719/*! TP3 - Trusted Protect
3720 * 0b0..Accesses from an untrusted master are allowed.
3721 * 0b1..Accesses from an untrusted master are not allowed.
3722 */
3723#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
3724#define AIPS_PACRP_WP3_MASK (0x20000U)
3725#define AIPS_PACRP_WP3_SHIFT (17U)
3726/*! WP3 - Write Protect
3727 * 0b0..This peripheral allows write accesses.
3728 * 0b1..This peripheral is write protected.
3729 */
3730#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
3731#define AIPS_PACRP_SP3_MASK (0x40000U)
3732#define AIPS_PACRP_SP3_SHIFT (18U)
3733/*! SP3 - Supervisor Protect
3734 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3735 * 0b1..This peripheral requires supervisor privilege level for accesses.
3736 */
3737#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
3738#define AIPS_PACRP_TP2_MASK (0x100000U)
3739#define AIPS_PACRP_TP2_SHIFT (20U)
3740/*! TP2 - Trusted Protect
3741 * 0b0..Accesses from an untrusted master are allowed.
3742 * 0b1..Accesses from an untrusted master are not allowed.
3743 */
3744#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
3745#define AIPS_PACRP_WP2_MASK (0x200000U)
3746#define AIPS_PACRP_WP2_SHIFT (21U)
3747/*! WP2 - Write Protect
3748 * 0b0..This peripheral allows write accesses.
3749 * 0b1..This peripheral is write protected.
3750 */
3751#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
3752#define AIPS_PACRP_SP2_MASK (0x400000U)
3753#define AIPS_PACRP_SP2_SHIFT (22U)
3754/*! SP2 - Supervisor Protect
3755 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3756 * 0b1..This peripheral requires supervisor privilege level for accesses.
3757 */
3758#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
3759#define AIPS_PACRP_TP1_MASK (0x1000000U)
3760#define AIPS_PACRP_TP1_SHIFT (24U)
3761/*! TP1 - Trusted Protect
3762 * 0b0..Accesses from an untrusted master are allowed.
3763 * 0b1..Accesses from an untrusted master are not allowed.
3764 */
3765#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
3766#define AIPS_PACRP_WP1_MASK (0x2000000U)
3767#define AIPS_PACRP_WP1_SHIFT (25U)
3768/*! WP1 - Write Protect
3769 * 0b0..This peripheral allows write accesses.
3770 * 0b1..This peripheral is write protected.
3771 */
3772#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
3773#define AIPS_PACRP_SP1_MASK (0x4000000U)
3774#define AIPS_PACRP_SP1_SHIFT (26U)
3775/*! SP1 - Supervisor Protect
3776 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3777 * 0b1..This peripheral requires supervisor privilege level for accesses.
3778 */
3779#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
3780#define AIPS_PACRP_TP0_MASK (0x10000000U)
3781#define AIPS_PACRP_TP0_SHIFT (28U)
3782/*! TP0 - Trusted Protect
3783 * 0b0..Accesses from an untrusted master are allowed.
3784 * 0b1..Accesses from an untrusted master are not allowed.
3785 */
3786#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
3787#define AIPS_PACRP_WP0_MASK (0x20000000U)
3788#define AIPS_PACRP_WP0_SHIFT (29U)
3789/*! WP0 - Write Protect
3790 * 0b0..This peripheral allows write accesses.
3791 * 0b1..This peripheral is write protected.
3792 */
3793#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
3794#define AIPS_PACRP_SP0_MASK (0x40000000U)
3795#define AIPS_PACRP_SP0_SHIFT (30U)
3796/*! SP0 - Supervisor Protect
3797 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3798 * 0b1..This peripheral requires supervisor privilege level for accesses.
3799 */
3800#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
3801/*! @} */
3802
3803
3804/*!
3805 * @}
3806 */ /* end of group AIPS_Register_Masks */
3807
3808
3809/* AIPS - Peripheral instance base addresses */
3810/** Peripheral AIPS0 base address */
3811#define AIPS0_BASE (0x40000000u)
3812/** Peripheral AIPS0 base pointer */
3813#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
3814/** Peripheral AIPS1 base address */
3815#define AIPS1_BASE (0x40080000u)
3816/** Peripheral AIPS1 base pointer */
3817#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
3818/** Array initializer of AIPS peripheral base addresses */
3819#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
3820/** Array initializer of AIPS peripheral base pointers */
3821#define AIPS_BASE_PTRS { AIPS0, AIPS1 }
3822
3823/*!
3824 * @}
3825 */ /* end of group AIPS_Peripheral_Access_Layer */
3826
3827
3828/* ----------------------------------------------------------------------------
3829 -- AXBS Peripheral Access Layer
3830 ---------------------------------------------------------------------------- */
3831
3832/*!
3833 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
3834 * @{
3835 */
3836
3837/** AXBS - Register Layout Typedef */
3838typedef struct {
3839 struct { /* offset: 0x0, array step: 0x100 */
3840 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
3841 uint8_t RESERVED_0[12];
3842 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
3843 uint8_t RESERVED_1[236];
3844 } SLAVE[5];
3845 uint8_t RESERVED_0[768];
3846 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
3847 uint8_t RESERVED_1[252];
3848 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
3849 uint8_t RESERVED_2[252];
3850 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
3851 uint8_t RESERVED_3[508];
3852 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
3853 uint8_t RESERVED_4[252];
3854 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
3855 uint8_t RESERVED_5[252];
3856 __IO uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */
3857} AXBS_Type;
3858
3859/* ----------------------------------------------------------------------------
3860 -- AXBS Register Masks
3861 ---------------------------------------------------------------------------- */
3862
3863/*!
3864 * @addtogroup AXBS_Register_Masks AXBS Register Masks
3865 * @{
3866 */
3867
3868/*! @name PRS - Priority Registers Slave */
3869/*! @{ */
3870#define AXBS_PRS_M0_MASK (0x7U)
3871#define AXBS_PRS_M0_SHIFT (0U)
3872/*! M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port.
3873 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3874 * 0b001..This master has level 2 priority when accessing the slave port.
3875 * 0b010..This master has level 3 priority when accessing the slave port.
3876 * 0b011..This master has level 4 priority when accessing the slave port.
3877 * 0b100..This master has level 5 priority when accessing the slave port.
3878 * 0b101..This master has level 6 priority when accessing the slave port.
3879 * 0b110..This master has level 7 priority when accessing the slave port.
3880 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3881 */
3882#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
3883#define AXBS_PRS_M1_MASK (0x70U)
3884#define AXBS_PRS_M1_SHIFT (4U)
3885/*! M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port.
3886 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3887 * 0b001..This master has level 2 priority when accessing the slave port.
3888 * 0b010..This master has level 3 priority when accessing the slave port.
3889 * 0b011..This master has level 4 priority when accessing the slave port.
3890 * 0b100..This master has level 5 priority when accessing the slave port.
3891 * 0b101..This master has level 6 priority when accessing the slave port.
3892 * 0b110..This master has level 7 priority when accessing the slave port.
3893 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3894 */
3895#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
3896#define AXBS_PRS_M2_MASK (0x700U)
3897#define AXBS_PRS_M2_SHIFT (8U)
3898/*! M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port.
3899 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3900 * 0b001..This master has level 2 priority when accessing the slave port.
3901 * 0b010..This master has level 3 priority when accessing the slave port.
3902 * 0b011..This master has level 4 priority when accessing the slave port.
3903 * 0b100..This master has level 5 priority when accessing the slave port.
3904 * 0b101..This master has level 6 priority when accessing the slave port.
3905 * 0b110..This master has level 7 priority when accessing the slave port.
3906 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3907 */
3908#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
3909#define AXBS_PRS_M4_MASK (0x70000U)
3910#define AXBS_PRS_M4_SHIFT (16U)
3911/*! M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port.
3912 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3913 * 0b001..This master has level 2 priority when accessing the slave port.
3914 * 0b010..This master has level 3 priority when accessing the slave port.
3915 * 0b011..This master has level 4 priority when accessing the slave port.
3916 * 0b100..This master has level 5 priority when accessing the slave port.
3917 * 0b101..This master has level 6 priority when accessing the slave port.
3918 * 0b110..This master has level 7 priority when accessing the slave port.
3919 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3920 */
3921#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
3922#define AXBS_PRS_M5_MASK (0x700000U)
3923#define AXBS_PRS_M5_SHIFT (20U)
3924/*! M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port.
3925 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3926 * 0b001..This master has level 2 priority when accessing the slave port.
3927 * 0b010..This master has level 3 priority when accessing the slave port.
3928 * 0b011..This master has level 4 priority when accessing the slave port.
3929 * 0b100..This master has level 5 priority when accessing the slave port.
3930 * 0b101..This master has level 6 priority when accessing the slave port.
3931 * 0b110..This master has level 7 priority when accessing the slave port.
3932 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3933 */
3934#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
3935#define AXBS_PRS_M6_MASK (0x7000000U)
3936#define AXBS_PRS_M6_SHIFT (24U)
3937/*! M6 - Master 6 Priority. Sets the arbitration priority for this port on the associated slave port.
3938 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3939 * 0b001..This master has level 2 priority when accessing the slave port.
3940 * 0b010..This master has level 3 priority when accessing the slave port.
3941 * 0b011..This master has level 4 priority when accessing the slave port.
3942 * 0b100..This master has level 5 priority when accessing the slave port.
3943 * 0b101..This master has level 6 priority when accessing the slave port.
3944 * 0b110..This master has level 7 priority when accessing the slave port.
3945 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3946 */
3947#define AXBS_PRS_M6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)
3948/*! @} */
3949
3950/* The count of AXBS_PRS */
3951#define AXBS_PRS_COUNT (5U)
3952
3953/*! @name CRS - Control Register */
3954/*! @{ */
3955#define AXBS_CRS_PARK_MASK (0x7U)
3956#define AXBS_CRS_PARK_SHIFT (0U)
3957/*! PARK - Park
3958 * 0b000..Park on master port M0
3959 * 0b001..Park on master port M1
3960 * 0b010..Park on master port M2
3961 * 0b011..Park on master port M3
3962 * 0b100..Park on master port M4
3963 * 0b101..Park on master port M5
3964 * 0b110..Park on master port M6
3965 * 0b111..Park on master port M7
3966 */
3967#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
3968#define AXBS_CRS_PCTL_MASK (0x30U)
3969#define AXBS_CRS_PCTL_SHIFT (4U)
3970/*! PCTL - Parking Control
3971 * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field
3972 * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port
3973 * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state
3974 * 0b11..Reserved
3975 */
3976#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
3977#define AXBS_CRS_ARB_MASK (0x300U)
3978#define AXBS_CRS_ARB_SHIFT (8U)
3979/*! ARB - Arbitration Mode
3980 * 0b00..Fixed priority
3981 * 0b01..Round-robin, or rotating, priority
3982 * 0b10..Reserved
3983 * 0b11..Reserved
3984 */
3985#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
3986#define AXBS_CRS_HLP_MASK (0x40000000U)
3987#define AXBS_CRS_HLP_SHIFT (30U)
3988/*! HLP - Halt Low Priority
3989 * 0b0..The low power mode request has the highest priority for arbitration on this slave port
3990 * 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port
3991 */
3992#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
3993#define AXBS_CRS_RO_MASK (0x80000000U)
3994#define AXBS_CRS_RO_SHIFT (31U)
3995/*! RO - Read Only
3996 * 0b0..The slave port's registers are writeable
3997 * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.
3998 */
3999#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
4000/*! @} */
4001
4002/* The count of AXBS_CRS */
4003#define AXBS_CRS_COUNT (5U)
4004
4005/*! @name MGPCR0 - Master General Purpose Control Register */
4006/*! @{ */
4007#define AXBS_MGPCR0_AULB_MASK (0x7U)
4008#define AXBS_MGPCR0_AULB_SHIFT (0U)
4009/*! AULB - Arbitrates On Undefined Length Bursts
4010 * 0b000..No arbitration is allowed during an undefined length burst
4011 * 0b001..Arbitration is allowed at any time during an undefined length burst
4012 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4013 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4014 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4015 * 0b101..Reserved
4016 * 0b110..Reserved
4017 * 0b111..Reserved
4018 */
4019#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
4020/*! @} */
4021
4022/*! @name MGPCR1 - Master General Purpose Control Register */
4023/*! @{ */
4024#define AXBS_MGPCR1_AULB_MASK (0x7U)
4025#define AXBS_MGPCR1_AULB_SHIFT (0U)
4026/*! AULB - Arbitrates On Undefined Length Bursts
4027 * 0b000..No arbitration is allowed during an undefined length burst
4028 * 0b001..Arbitration is allowed at any time during an undefined length burst
4029 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4030 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4031 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4032 * 0b101..Reserved
4033 * 0b110..Reserved
4034 * 0b111..Reserved
4035 */
4036#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
4037/*! @} */
4038
4039/*! @name MGPCR2 - Master General Purpose Control Register */
4040/*! @{ */
4041#define AXBS_MGPCR2_AULB_MASK (0x7U)
4042#define AXBS_MGPCR2_AULB_SHIFT (0U)
4043/*! AULB - Arbitrates On Undefined Length Bursts
4044 * 0b000..No arbitration is allowed during an undefined length burst
4045 * 0b001..Arbitration is allowed at any time during an undefined length burst
4046 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4047 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4048 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4049 * 0b101..Reserved
4050 * 0b110..Reserved
4051 * 0b111..Reserved
4052 */
4053#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
4054/*! @} */
4055
4056/*! @name MGPCR4 - Master General Purpose Control Register */
4057/*! @{ */
4058#define AXBS_MGPCR4_AULB_MASK (0x7U)
4059#define AXBS_MGPCR4_AULB_SHIFT (0U)
4060/*! AULB - Arbitrates On Undefined Length Bursts
4061 * 0b000..No arbitration is allowed during an undefined length burst
4062 * 0b001..Arbitration is allowed at any time during an undefined length burst
4063 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4064 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4065 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4066 * 0b101..Reserved
4067 * 0b110..Reserved
4068 * 0b111..Reserved
4069 */
4070#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
4071/*! @} */
4072
4073/*! @name MGPCR5 - Master General Purpose Control Register */
4074/*! @{ */
4075#define AXBS_MGPCR5_AULB_MASK (0x7U)
4076#define AXBS_MGPCR5_AULB_SHIFT (0U)
4077/*! AULB - Arbitrates On Undefined Length Bursts
4078 * 0b000..No arbitration is allowed during an undefined length burst
4079 * 0b001..Arbitration is allowed at any time during an undefined length burst
4080 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4081 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4082 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4083 * 0b101..Reserved
4084 * 0b110..Reserved
4085 * 0b111..Reserved
4086 */
4087#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
4088/*! @} */
4089
4090/*! @name MGPCR6 - Master General Purpose Control Register */
4091/*! @{ */
4092#define AXBS_MGPCR6_AULB_MASK (0x7U)
4093#define AXBS_MGPCR6_AULB_SHIFT (0U)
4094/*! AULB - Arbitrates On Undefined Length Bursts
4095 * 0b000..No arbitration is allowed during an undefined length burst
4096 * 0b001..Arbitration is allowed at any time during an undefined length burst
4097 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4098 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4099 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4100 * 0b101..Reserved
4101 * 0b110..Reserved
4102 * 0b111..Reserved
4103 */
4104#define AXBS_MGPCR6_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)
4105/*! @} */
4106
4107
4108/*!
4109 * @}
4110 */ /* end of group AXBS_Register_Masks */
4111
4112
4113/* AXBS - Peripheral instance base addresses */
4114/** Peripheral AXBS base address */
4115#define AXBS_BASE (0x40004000u)
4116/** Peripheral AXBS base pointer */
4117#define AXBS ((AXBS_Type *)AXBS_BASE)
4118/** Array initializer of AXBS peripheral base addresses */
4119#define AXBS_BASE_ADDRS { AXBS_BASE }
4120/** Array initializer of AXBS peripheral base pointers */
4121#define AXBS_BASE_PTRS { AXBS }
4122
4123/*!
4124 * @}
4125 */ /* end of group AXBS_Peripheral_Access_Layer */
4126
4127
4128/* ----------------------------------------------------------------------------
4129 -- CAN Peripheral Access Layer
4130 ---------------------------------------------------------------------------- */
4131
4132/*!
4133 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
4134 * @{
4135 */
4136
4137/** CAN - Register Layout Typedef */
4138typedef struct {
4139 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
4140 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
4141 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
4142 uint8_t RESERVED_0[4];
4143 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
4144 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
4145 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
4146 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
4147 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
4148 uint8_t RESERVED_1[4];
4149 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
4150 uint8_t RESERVED_2[4];
4151 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
4152 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
4153 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
4154 uint8_t RESERVED_3[8];
4155 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
4156 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
4157 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
4158 uint8_t RESERVED_4[48];
4159 struct { /* offset: 0x80, array step: 0x10 */
4160 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
4161 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
4162 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
4163 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
4164 } MB[16];
4165 uint8_t RESERVED_5[1792];
4166 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
4167} CAN_Type;
4168
4169/* ----------------------------------------------------------------------------
4170 -- CAN Register Masks
4171 ---------------------------------------------------------------------------- */
4172
4173/*!
4174 * @addtogroup CAN_Register_Masks CAN Register Masks
4175 * @{
4176 */
4177
4178/*! @name MCR - Module Configuration Register */
4179/*! @{ */
4180#define CAN_MCR_MAXMB_MASK (0x7FU)
4181#define CAN_MCR_MAXMB_SHIFT (0U)
4182#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
4183#define CAN_MCR_IDAM_MASK (0x300U)
4184#define CAN_MCR_IDAM_SHIFT (8U)
4185/*! IDAM - ID Acceptance Mode
4186 * 0b00..Format A: One full ID (standard and extended) per ID Filter Table element.
4187 * 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element.
4188 * 0b10..Format C: Four partial 8-bit Standard IDs per ID Filter Table element.
4189 * 0b11..Format D: All frames rejected.
4190 */
4191#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
4192#define CAN_MCR_AEN_MASK (0x1000U)
4193#define CAN_MCR_AEN_SHIFT (12U)
4194/*! AEN - Abort Enable
4195 * 0b0..Abort disabled.
4196 * 0b1..Abort enabled.
4197 */
4198#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
4199#define CAN_MCR_LPRIOEN_MASK (0x2000U)
4200#define CAN_MCR_LPRIOEN_SHIFT (13U)
4201/*! LPRIOEN - Local Priority Enable
4202 * 0b0..Local Priority disabled.
4203 * 0b1..Local Priority enabled.
4204 */
4205#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
4206#define CAN_MCR_IRMQ_MASK (0x10000U)
4207#define CAN_MCR_IRMQ_SHIFT (16U)
4208/*! IRMQ - Individual Rx Masking And Queue Enable
4209 * 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy applications, the reading of C/S word locks the MB even if it is EMPTY.
4210 * 0b1..Individual Rx masking and queue feature are enabled.
4211 */
4212#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
4213#define CAN_MCR_SRXDIS_MASK (0x20000U)
4214#define CAN_MCR_SRXDIS_SHIFT (17U)
4215/*! SRXDIS - Self Reception Disable
4216 * 0b0..Self reception enabled.
4217 * 0b1..Self reception disabled.
4218 */
4219#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
4220#define CAN_MCR_WAKSRC_MASK (0x80000U)
4221#define CAN_MCR_WAKSRC_SHIFT (19U)
4222/*! WAKSRC - Wake Up Source
4223 * 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
4224 * 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
4225 */
4226#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
4227#define CAN_MCR_LPMACK_MASK (0x100000U)
4228#define CAN_MCR_LPMACK_SHIFT (20U)
4229/*! LPMACK - Low-Power Mode Acknowledge
4230 * 0b0..FlexCAN is not in a low-power mode.
4231 * 0b1..FlexCAN is in a low-power mode.
4232 */
4233#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
4234#define CAN_MCR_WRNEN_MASK (0x200000U)
4235#define CAN_MCR_WRNEN_SHIFT (21U)
4236/*! WRNEN - Warning Interrupt Enable
4237 * 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
4238 * 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
4239 */
4240#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
4241#define CAN_MCR_SLFWAK_MASK (0x400000U)
4242#define CAN_MCR_SLFWAK_SHIFT (22U)
4243/*! SLFWAK - Self Wake Up
4244 * 0b0..FlexCAN Self Wake Up feature is disabled.
4245 * 0b1..FlexCAN Self Wake Up feature is enabled.
4246 */
4247#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
4248#define CAN_MCR_SUPV_MASK (0x800000U)
4249#define CAN_MCR_SUPV_SHIFT (23U)
4250/*! SUPV - Supervisor Mode
4251 * 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses .
4252 * 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location .
4253 */
4254#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
4255#define CAN_MCR_FRZACK_MASK (0x1000000U)
4256#define CAN_MCR_FRZACK_SHIFT (24U)
4257/*! FRZACK - Freeze Mode Acknowledge
4258 * 0b0..FlexCAN not in Freeze mode, prescaler running.
4259 * 0b1..FlexCAN in Freeze mode, prescaler stopped.
4260 */
4261#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
4262#define CAN_MCR_SOFTRST_MASK (0x2000000U)
4263#define CAN_MCR_SOFTRST_SHIFT (25U)
4264/*! SOFTRST - Soft Reset
4265 * 0b0..No reset request.
4266 * 0b1..Resets the registers affected by soft reset.
4267 */
4268#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
4269#define CAN_MCR_WAKMSK_MASK (0x4000000U)
4270#define CAN_MCR_WAKMSK_SHIFT (26U)
4271/*! WAKMSK - Wake Up Interrupt Mask
4272 * 0b0..Wake Up Interrupt is disabled.
4273 * 0b1..Wake Up Interrupt is enabled.
4274 */
4275#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
4276#define CAN_MCR_NOTRDY_MASK (0x8000000U)
4277#define CAN_MCR_NOTRDY_SHIFT (27U)
4278/*! NOTRDY - FlexCAN Not Ready
4279 * 0b0..FlexCAN module is either in Normal mode, Listen-Only mode or Loop-Back mode.
4280 * 0b1..FlexCAN module is either in Disable mode , Stop mode or Freeze mode.
4281 */
4282#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
4283#define CAN_MCR_HALT_MASK (0x10000000U)
4284#define CAN_MCR_HALT_SHIFT (28U)
4285/*! HALT - Halt FlexCAN
4286 * 0b0..No Freeze mode request.
4287 * 0b1..Enters Freeze mode if the FRZ bit is asserted.
4288 */
4289#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
4290#define CAN_MCR_RFEN_MASK (0x20000000U)
4291#define CAN_MCR_RFEN_SHIFT (29U)
4292/*! RFEN - Rx FIFO Enable
4293 * 0b0..Rx FIFO not enabled.
4294 * 0b1..Rx FIFO enabled.
4295 */
4296#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
4297#define CAN_MCR_FRZ_MASK (0x40000000U)
4298#define CAN_MCR_FRZ_SHIFT (30U)
4299/*! FRZ - Freeze Enable
4300 * 0b0..Not enabled to enter Freeze mode.
4301 * 0b1..Enabled to enter Freeze mode.
4302 */
4303#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
4304#define CAN_MCR_MDIS_MASK (0x80000000U)
4305#define CAN_MCR_MDIS_SHIFT (31U)
4306/*! MDIS - Module Disable
4307 * 0b0..Enable the FlexCAN module.
4308 * 0b1..Disable the FlexCAN module.
4309 */
4310#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
4311/*! @} */
4312
4313/*! @name CTRL1 - Control 1 register */
4314/*! @{ */
4315#define CAN_CTRL1_PROPSEG_MASK (0x7U)
4316#define CAN_CTRL1_PROPSEG_SHIFT (0U)
4317#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
4318#define CAN_CTRL1_LOM_MASK (0x8U)
4319#define CAN_CTRL1_LOM_SHIFT (3U)
4320/*! LOM - Listen-Only Mode
4321 * 0b0..Listen-Only mode is deactivated.
4322 * 0b1..FlexCAN module operates in Listen-Only mode.
4323 */
4324#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
4325#define CAN_CTRL1_LBUF_MASK (0x10U)
4326#define CAN_CTRL1_LBUF_SHIFT (4U)
4327/*! LBUF - Lowest Buffer Transmitted First
4328 * 0b0..Buffer with highest priority is transmitted first.
4329 * 0b1..Lowest number buffer is transmitted first.
4330 */
4331#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
4332#define CAN_CTRL1_TSYN_MASK (0x20U)
4333#define CAN_CTRL1_TSYN_SHIFT (5U)
4334/*! TSYN - Timer Sync
4335 * 0b0..Timer Sync feature disabled
4336 * 0b1..Timer Sync feature enabled
4337 */
4338#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
4339#define CAN_CTRL1_BOFFREC_MASK (0x40U)
4340#define CAN_CTRL1_BOFFREC_SHIFT (6U)
4341/*! BOFFREC - Bus Off Recovery
4342 * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B.
4343 * 0b1..Automatic recovering from Bus Off state disabled.
4344 */
4345#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
4346#define CAN_CTRL1_SMP_MASK (0x80U)
4347#define CAN_CTRL1_SMP_SHIFT (7U)
4348/*! SMP - CAN Bit Sampling
4349 * 0b0..Just one sample is used to determine the bit value.
4350 * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used.
4351 */
4352#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
4353#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
4354#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
4355/*! RWRNMSK - Rx Warning Interrupt Mask
4356 * 0b0..Rx Warning Interrupt disabled.
4357 * 0b1..Rx Warning Interrupt enabled.
4358 */
4359#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
4360#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
4361#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
4362/*! TWRNMSK - Tx Warning Interrupt Mask
4363 * 0b0..Tx Warning Interrupt disabled.
4364 * 0b1..Tx Warning Interrupt enabled.
4365 */
4366#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
4367#define CAN_CTRL1_LPB_MASK (0x1000U)
4368#define CAN_CTRL1_LPB_SHIFT (12U)
4369/*! LPB - Loop Back Mode
4370 * 0b0..Loop Back disabled.
4371 * 0b1..Loop Back enabled.
4372 */
4373#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
4374#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
4375#define CAN_CTRL1_CLKSRC_SHIFT (13U)
4376/*! CLKSRC - CAN Engine Clock Source
4377 * 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
4378 * 0b1..The CAN engine clock source is the peripheral clock.
4379 */
4380#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
4381#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
4382#define CAN_CTRL1_ERRMSK_SHIFT (14U)
4383/*! ERRMSK - Error Mask
4384 * 0b0..Error interrupt disabled.
4385 * 0b1..Error interrupt enabled.
4386 */
4387#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
4388#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
4389#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
4390/*! BOFFMSK - Bus Off Mask
4391 * 0b0..Bus Off interrupt disabled.
4392 * 0b1..Bus Off interrupt enabled.
4393 */
4394#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
4395#define CAN_CTRL1_PSEG2_MASK (0x70000U)
4396#define CAN_CTRL1_PSEG2_SHIFT (16U)
4397#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
4398#define CAN_CTRL1_PSEG1_MASK (0x380000U)
4399#define CAN_CTRL1_PSEG1_SHIFT (19U)
4400#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
4401#define CAN_CTRL1_RJW_MASK (0xC00000U)
4402#define CAN_CTRL1_RJW_SHIFT (22U)
4403#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
4404#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
4405#define CAN_CTRL1_PRESDIV_SHIFT (24U)
4406#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
4407/*! @} */
4408
4409/*! @name TIMER - Free Running Timer */
4410/*! @{ */
4411#define CAN_TIMER_TIMER_MASK (0xFFFFU)
4412#define CAN_TIMER_TIMER_SHIFT (0U)
4413#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
4414/*! @} */
4415
4416/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
4417/*! @{ */
4418#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
4419#define CAN_RXMGMASK_MG_SHIFT (0U)
4420/*! MG - Rx Mailboxes Global Mask Bits
4421 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
4422 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
4423 */
4424#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
4425/*! @} */
4426
4427/*! @name RX14MASK - Rx 14 Mask register */
4428/*! @{ */
4429#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
4430#define CAN_RX14MASK_RX14M_SHIFT (0U)
4431/*! RX14M - Rx Buffer 14 Mask Bits
4432 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
4433 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
4434 */
4435#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
4436/*! @} */
4437
4438/*! @name RX15MASK - Rx 15 Mask register */
4439/*! @{ */
4440#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
4441#define CAN_RX15MASK_RX15M_SHIFT (0U)
4442/*! RX15M - Rx Buffer 15 Mask Bits
4443 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
4444 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
4445 */
4446#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
4447/*! @} */
4448
4449/*! @name ECR - Error Counter */
4450/*! @{ */
4451#define CAN_ECR_TXERRCNT_MASK (0xFFU)
4452#define CAN_ECR_TXERRCNT_SHIFT (0U)
4453#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
4454#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
4455#define CAN_ECR_RXERRCNT_SHIFT (8U)
4456#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
4457/*! @} */
4458
4459/*! @name ESR1 - Error and Status 1 register */
4460/*! @{ */
4461#define CAN_ESR1_WAKINT_MASK (0x1U)
4462#define CAN_ESR1_WAKINT_SHIFT (0U)
4463/*! WAKINT - Wake-Up Interrupt
4464 * 0b0..No such occurrence.
4465 * 0b1..Indicates a recessive to dominant transition was received on the CAN bus.
4466 */
4467#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
4468#define CAN_ESR1_ERRINT_MASK (0x2U)
4469#define CAN_ESR1_ERRINT_SHIFT (1U)
4470/*! ERRINT - Error Interrupt
4471 * 0b0..No such occurrence.
4472 * 0b1..Indicates setting of any Error Bit in the Error and Status Register.
4473 */
4474#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
4475#define CAN_ESR1_BOFFINT_MASK (0x4U)
4476#define CAN_ESR1_BOFFINT_SHIFT (2U)
4477/*! BOFFINT - Bus Off Interrupt
4478 * 0b0..No such occurrence.
4479 * 0b1..FlexCAN module entered Bus Off state.
4480 */
4481#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
4482#define CAN_ESR1_RX_MASK (0x8U)
4483#define CAN_ESR1_RX_SHIFT (3U)
4484/*! RX - FlexCAN In Reception
4485 * 0b0..FlexCAN is not receiving a message.
4486 * 0b1..FlexCAN is receiving a message.
4487 */
4488#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
4489#define CAN_ESR1_FLTCONF_MASK (0x30U)
4490#define CAN_ESR1_FLTCONF_SHIFT (4U)
4491/*! FLTCONF - Fault Confinement State
4492 * 0b00..Error Active
4493 * 0b01..Error Passive
4494 * 0b1x..Bus Off
4495 */
4496#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
4497#define CAN_ESR1_TX_MASK (0x40U)
4498#define CAN_ESR1_TX_SHIFT (6U)
4499/*! TX - FlexCAN In Transmission
4500 * 0b0..FlexCAN is not transmitting a message.
4501 * 0b1..FlexCAN is transmitting a message.
4502 */
4503#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
4504#define CAN_ESR1_IDLE_MASK (0x80U)
4505#define CAN_ESR1_IDLE_SHIFT (7U)
4506/*! IDLE
4507 * 0b0..No such occurrence.
4508 * 0b1..CAN bus is now IDLE.
4509 */
4510#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
4511#define CAN_ESR1_RXWRN_MASK (0x100U)
4512#define CAN_ESR1_RXWRN_SHIFT (8U)
4513/*! RXWRN - Rx Error Warning
4514 * 0b0..No such occurrence.
4515 * 0b1..RXERRCNT is greater than or equal to 96.
4516 */
4517#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
4518#define CAN_ESR1_TXWRN_MASK (0x200U)
4519#define CAN_ESR1_TXWRN_SHIFT (9U)
4520/*! TXWRN - TX Error Warning
4521 * 0b0..No such occurrence.
4522 * 0b1..TXERRCNT is greater than or equal to 96.
4523 */
4524#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
4525#define CAN_ESR1_STFERR_MASK (0x400U)
4526#define CAN_ESR1_STFERR_SHIFT (10U)
4527/*! STFERR - Stuffing Error
4528 * 0b0..No such occurrence.
4529 * 0b1..A Stuffing Error occurred since last read of this register.
4530 */
4531#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
4532#define CAN_ESR1_FRMERR_MASK (0x800U)
4533#define CAN_ESR1_FRMERR_SHIFT (11U)
4534/*! FRMERR - Form Error
4535 * 0b0..No such occurrence.
4536 * 0b1..A Form Error occurred since last read of this register.
4537 */
4538#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
4539#define CAN_ESR1_CRCERR_MASK (0x1000U)
4540#define CAN_ESR1_CRCERR_SHIFT (12U)
4541/*! CRCERR - Cyclic Redundancy Check Error
4542 * 0b0..No such occurrence.
4543 * 0b1..A CRC error occurred since last read of this register.
4544 */
4545#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
4546#define CAN_ESR1_ACKERR_MASK (0x2000U)
4547#define CAN_ESR1_ACKERR_SHIFT (13U)
4548/*! ACKERR - Acknowledge Error
4549 * 0b0..No such occurrence.
4550 * 0b1..An ACK error occurred since last read of this register.
4551 */
4552#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
4553#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
4554#define CAN_ESR1_BIT0ERR_SHIFT (14U)
4555/*! BIT0ERR - Bit0 Error
4556 * 0b0..No such occurrence.
4557 * 0b1..At least one bit sent as dominant is received as recessive.
4558 */
4559#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
4560#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
4561#define CAN_ESR1_BIT1ERR_SHIFT (15U)
4562/*! BIT1ERR - Bit1 Error
4563 * 0b0..No such occurrence.
4564 * 0b1..At least one bit sent as recessive is received as dominant.
4565 */
4566#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
4567#define CAN_ESR1_RWRNINT_MASK (0x10000U)
4568#define CAN_ESR1_RWRNINT_SHIFT (16U)
4569/*! RWRNINT - Rx Warning Interrupt Flag
4570 * 0b0..No such occurrence.
4571 * 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
4572 */
4573#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
4574#define CAN_ESR1_TWRNINT_MASK (0x20000U)
4575#define CAN_ESR1_TWRNINT_SHIFT (17U)
4576/*! TWRNINT - Tx Warning Interrupt Flag
4577 * 0b0..No such occurrence.
4578 * 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
4579 */
4580#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
4581#define CAN_ESR1_SYNCH_MASK (0x40000U)
4582#define CAN_ESR1_SYNCH_SHIFT (18U)
4583/*! SYNCH - CAN Synchronization Status
4584 * 0b0..FlexCAN is not synchronized to the CAN bus.
4585 * 0b1..FlexCAN is synchronized to the CAN bus.
4586 */
4587#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
4588/*! @} */
4589
4590/*! @name IMASK1 - Interrupt Masks 1 register */
4591/*! @{ */
4592#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
4593#define CAN_IMASK1_BUFLM_SHIFT (0U)
4594/*! BUFLM - Buffer MB i Mask
4595 * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled.
4596 * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled.
4597 */
4598#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
4599/*! @} */
4600
4601/*! @name IFLAG1 - Interrupt Flags 1 register */
4602/*! @{ */
4603#define CAN_IFLAG1_BUF0I_MASK (0x1U)
4604#define CAN_IFLAG1_BUF0I_SHIFT (0U)
4605/*! BUF0I - Buffer MB0 Interrupt Or "reserved"
4606 * 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
4607 * 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
4608 */
4609#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
4610#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
4611#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
4612/*! BUF4TO1I - Buffer MB i Interrupt Or "reserved"
4613 * 0b0000..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
4614 * 0b0001..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
4615 */
4616#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
4617#define CAN_IFLAG1_BUF5I_MASK (0x20U)
4618#define CAN_IFLAG1_BUF5I_SHIFT (5U)
4619/*! BUF5I - Buffer MB5 Interrupt Or "Frames available in Rx FIFO"
4620 * 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
4621 * 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when MCR[RFEN]=1
4622 */
4623#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
4624#define CAN_IFLAG1_BUF6I_MASK (0x40U)
4625#define CAN_IFLAG1_BUF6I_SHIFT (6U)
4626/*! BUF6I - Buffer MB6 Interrupt Or "Rx FIFO Warning"
4627 * 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
4628 * 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
4629 */
4630#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
4631#define CAN_IFLAG1_BUF7I_MASK (0x80U)
4632#define CAN_IFLAG1_BUF7I_SHIFT (7U)
4633/*! BUF7I - Buffer MB7 Interrupt Or "Rx FIFO Overflow"
4634 * 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
4635 * 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
4636 */
4637#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
4638#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
4639#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
4640/*! BUF31TO8I - Buffer MBi Interrupt
4641 * 0b000000000000000000000000..The corresponding buffer has no occurrence of successfully completed transmission or reception.
4642 * 0b000000000000000000000001..The corresponding buffer has successfully completed transmission or reception.
4643 */
4644#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
4645/*! @} */
4646
4647/*! @name CTRL2 - Control 2 register */
4648/*! @{ */
4649#define CAN_CTRL2_EACEN_MASK (0x10000U)
4650#define CAN_CTRL2_EACEN_SHIFT (16U)
4651/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
4652 * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
4653 * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply.
4654 */
4655#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
4656#define CAN_CTRL2_RRS_MASK (0x20000U)
4657#define CAN_CTRL2_RRS_SHIFT (17U)
4658/*! RRS - Remote Request Storing
4659 * 0b0..Remote Response Frame is generated.
4660 * 0b1..Remote Request Frame is stored.
4661 */
4662#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
4663#define CAN_CTRL2_MRP_MASK (0x40000U)
4664#define CAN_CTRL2_MRP_SHIFT (18U)
4665/*! MRP - Mailboxes Reception Priority
4666 * 0b0..Matching starts from Rx FIFO and continues on Mailboxes.
4667 * 0b1..Matching starts from Mailboxes and continues on Rx FIFO.
4668 */
4669#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
4670#define CAN_CTRL2_TASD_MASK (0xF80000U)
4671#define CAN_CTRL2_TASD_SHIFT (19U)
4672#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
4673#define CAN_CTRL2_RFFN_MASK (0xF000000U)
4674#define CAN_CTRL2_RFFN_SHIFT (24U)
4675#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
4676#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
4677#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
4678/*! WRMFRZ - Write-Access To Memory In Freeze Mode
4679 * 0b0..Maintain the write access restrictions.
4680 * 0b1..Enable unrestricted write access to FlexCAN memory.
4681 */
4682#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
4683/*! @} */
4684
4685/*! @name ESR2 - Error and Status 2 register */
4686/*! @{ */
4687#define CAN_ESR2_IMB_MASK (0x2000U)
4688#define CAN_ESR2_IMB_SHIFT (13U)
4689/*! IMB - Inactive Mailbox
4690 * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
4691 * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.
4692 */
4693#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
4694#define CAN_ESR2_VPS_MASK (0x4000U)
4695#define CAN_ESR2_VPS_SHIFT (14U)
4696/*! VPS - Valid Priority Status
4697 * 0b0..Contents of IMB and LPTM are invalid.
4698 * 0b1..Contents of IMB and LPTM are valid.
4699 */
4700#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
4701#define CAN_ESR2_LPTM_MASK (0x7F0000U)
4702#define CAN_ESR2_LPTM_SHIFT (16U)
4703#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
4704/*! @} */
4705
4706/*! @name CRCR - CRC Register */
4707/*! @{ */
4708#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
4709#define CAN_CRCR_TXCRC_SHIFT (0U)
4710#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
4711#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
4712#define CAN_CRCR_MBCRC_SHIFT (16U)
4713#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
4714/*! @} */
4715
4716/*! @name RXFGMASK - Rx FIFO Global Mask register */
4717/*! @{ */
4718#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
4719#define CAN_RXFGMASK_FGM_SHIFT (0U)
4720/*! FGM - Rx FIFO Global Mask Bits
4721 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
4722 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
4723 */
4724#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
4725/*! @} */
4726
4727/*! @name RXFIR - Rx FIFO Information Register */
4728/*! @{ */
4729#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
4730#define CAN_RXFIR_IDHIT_SHIFT (0U)
4731#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
4732/*! @} */
4733
4734/*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
4735/*! @{ */
4736#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
4737#define CAN_CS_TIME_STAMP_SHIFT (0U)
4738#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
4739#define CAN_CS_DLC_MASK (0xF0000U)
4740#define CAN_CS_DLC_SHIFT (16U)
4741#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
4742#define CAN_CS_RTR_MASK (0x100000U)
4743#define CAN_CS_RTR_SHIFT (20U)
4744#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
4745#define CAN_CS_IDE_MASK (0x200000U)
4746#define CAN_CS_IDE_SHIFT (21U)
4747#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
4748#define CAN_CS_SRR_MASK (0x400000U)
4749#define CAN_CS_SRR_SHIFT (22U)
4750#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
4751#define CAN_CS_CODE_MASK (0xF000000U)
4752#define CAN_CS_CODE_SHIFT (24U)
4753#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
4754/*! @} */
4755
4756/* The count of CAN_CS */
4757#define CAN_CS_COUNT (16U)
4758
4759/*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
4760/*! @{ */
4761#define CAN_ID_EXT_MASK (0x3FFFFU)
4762#define CAN_ID_EXT_SHIFT (0U)
4763#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
4764#define CAN_ID_STD_MASK (0x1FFC0000U)
4765#define CAN_ID_STD_SHIFT (18U)
4766#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
4767#define CAN_ID_PRIO_MASK (0xE0000000U)
4768#define CAN_ID_PRIO_SHIFT (29U)
4769#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
4770/*! @} */
4771
4772/* The count of CAN_ID */
4773#define CAN_ID_COUNT (16U)
4774
4775/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
4776/*! @{ */
4777#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
4778#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
4779#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
4780#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
4781#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
4782#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
4783#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
4784#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
4785#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
4786#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
4787#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
4788#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
4789/*! @} */
4790
4791/* The count of CAN_WORD0 */
4792#define CAN_WORD0_COUNT (16U)
4793
4794/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
4795/*! @{ */
4796#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
4797#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
4798#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
4799#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
4800#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
4801#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
4802#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
4803#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
4804#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
4805#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
4806#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
4807#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
4808/*! @} */
4809
4810/* The count of CAN_WORD1 */
4811#define CAN_WORD1_COUNT (16U)
4812
4813/*! @name RXIMR - Rx Individual Mask Registers */
4814/*! @{ */
4815#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
4816#define CAN_RXIMR_MI_SHIFT (0U)
4817/*! MI - Individual Mask Bits
4818 * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care."
4819 * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked.
4820 */
4821#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
4822/*! @} */
4823
4824/* The count of CAN_RXIMR */
4825#define CAN_RXIMR_COUNT (16U)
4826
4827
4828/*!
4829 * @}
4830 */ /* end of group CAN_Register_Masks */
4831
4832
4833/* CAN - Peripheral instance base addresses */
4834/** Peripheral CAN0 base address */
4835#define CAN0_BASE (0x40024000u)
4836/** Peripheral CAN0 base pointer */
4837#define CAN0 ((CAN_Type *)CAN0_BASE)
4838/** Peripheral CAN1 base address */
4839#define CAN1_BASE (0x400A4000u)
4840/** Peripheral CAN1 base pointer */
4841#define CAN1 ((CAN_Type *)CAN1_BASE)
4842/** Array initializer of CAN peripheral base addresses */
4843#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
4844/** Array initializer of CAN peripheral base pointers */
4845#define CAN_BASE_PTRS { CAN0, CAN1 }
4846/** Interrupt vectors for the CAN peripheral type */
4847#define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn }
4848#define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn }
4849#define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn }
4850#define CAN_Error_IRQS { CAN0_Error_IRQn, CAN1_Error_IRQn }
4851#define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn }
4852#define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn }
4853
4854/*!
4855 * @}
4856 */ /* end of group CAN_Peripheral_Access_Layer */
4857
4858
4859/* ----------------------------------------------------------------------------
4860 -- CAU Peripheral Access Layer
4861 ---------------------------------------------------------------------------- */
4862
4863/*!
4864 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
4865 * @{
4866 */
4867
4868/** CAU - Register Layout Typedef */
4869typedef struct {
4870 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
4871 uint8_t RESERVED_0[2048];
4872 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
4873 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
4874 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
4875 uint8_t RESERVED_1[20];
4876 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
4877 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
4878 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
4879 uint8_t RESERVED_2[20];
4880 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
4881 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
4882 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
4883 uint8_t RESERVED_3[20];
4884 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
4885 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
4886 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
4887 uint8_t RESERVED_4[84];
4888 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
4889 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
4890 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
4891 uint8_t RESERVED_5[20];
4892 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
4893 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
4894 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
4895 uint8_t RESERVED_6[276];
4896 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
4897 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
4898 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
4899 uint8_t RESERVED_7[20];
4900 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
4901 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
4902 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
4903} CAU_Type;
4904
4905/* ----------------------------------------------------------------------------
4906 -- CAU Register Masks
4907 ---------------------------------------------------------------------------- */
4908
4909/*!
4910 * @addtogroup CAU_Register_Masks CAU Register Masks
4911 * @{
4912 */
4913
4914/*! @name DIRECT - Direct access register 0..Direct access register 15 */
4915/*! @{ */
4916#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
4917#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
4918#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
4919#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
4920#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
4921#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
4922#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
4923#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
4924#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
4925#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
4926#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
4927#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
4928#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
4929#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
4930#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
4931#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
4932#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
4933#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
4934#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
4935#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
4936#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
4937#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
4938#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
4939#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
4940#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
4941#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
4942#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
4943#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
4944#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
4945#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
4946#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
4947#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
4948#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
4949#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
4950#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
4951#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
4952#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
4953#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
4954#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
4955#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
4956#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
4957#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
4958#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
4959#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
4960#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
4961#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
4962#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
4963#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
4964/*! @} */
4965
4966/* The count of CAU_DIRECT */
4967#define CAU_DIRECT_COUNT (16U)
4968
4969/*! @name LDR_CASR - Status register - Load Register command */
4970/*! @{ */
4971#define CAU_LDR_CASR_IC_MASK (0x1U)
4972#define CAU_LDR_CASR_IC_SHIFT (0U)
4973/*! IC
4974 * 0b0..No illegal commands issued
4975 * 0b1..Illegal command issued
4976 */
4977#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
4978#define CAU_LDR_CASR_DPE_MASK (0x2U)
4979#define CAU_LDR_CASR_DPE_SHIFT (1U)
4980/*! DPE
4981 * 0b0..No error detected
4982 * 0b1..DES key parity error detected
4983 */
4984#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
4985#define CAU_LDR_CASR_VER_MASK (0xF0000000U)
4986#define CAU_LDR_CASR_VER_SHIFT (28U)
4987/*! VER - CAU version
4988 * 0b0001..Initial CAU version
4989 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4990 */
4991#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
4992/*! @} */
4993
4994/*! @name LDR_CAA - Accumulator register - Load Register command */
4995/*! @{ */
4996#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
4997#define CAU_LDR_CAA_ACC_SHIFT (0U)
4998#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
4999/*! @} */
5000
5001/*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
5002/*! @{ */
5003#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
5004#define CAU_LDR_CA_CA0_SHIFT (0U)
5005#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
5006#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
5007#define CAU_LDR_CA_CA1_SHIFT (0U)
5008#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
5009#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
5010#define CAU_LDR_CA_CA2_SHIFT (0U)
5011#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
5012#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
5013#define CAU_LDR_CA_CA3_SHIFT (0U)
5014#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
5015#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
5016#define CAU_LDR_CA_CA4_SHIFT (0U)
5017#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
5018#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
5019#define CAU_LDR_CA_CA5_SHIFT (0U)
5020#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
5021#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
5022#define CAU_LDR_CA_CA6_SHIFT (0U)
5023#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
5024#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
5025#define CAU_LDR_CA_CA7_SHIFT (0U)
5026#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
5027#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
5028#define CAU_LDR_CA_CA8_SHIFT (0U)
5029#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
5030/*! @} */
5031
5032/* The count of CAU_LDR_CA */
5033#define CAU_LDR_CA_COUNT (9U)
5034
5035/*! @name STR_CASR - Status register - Store Register command */
5036/*! @{ */
5037#define CAU_STR_CASR_IC_MASK (0x1U)
5038#define CAU_STR_CASR_IC_SHIFT (0U)
5039/*! IC
5040 * 0b0..No illegal commands issued
5041 * 0b1..Illegal command issued
5042 */
5043#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
5044#define CAU_STR_CASR_DPE_MASK (0x2U)
5045#define CAU_STR_CASR_DPE_SHIFT (1U)
5046/*! DPE
5047 * 0b0..No error detected
5048 * 0b1..DES key parity error detected
5049 */
5050#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
5051#define CAU_STR_CASR_VER_MASK (0xF0000000U)
5052#define CAU_STR_CASR_VER_SHIFT (28U)
5053/*! VER - CAU version
5054 * 0b0001..Initial CAU version
5055 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5056 */
5057#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
5058/*! @} */
5059
5060/*! @name STR_CAA - Accumulator register - Store Register command */
5061/*! @{ */
5062#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
5063#define CAU_STR_CAA_ACC_SHIFT (0U)
5064#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
5065/*! @} */
5066
5067/*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
5068/*! @{ */
5069#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
5070#define CAU_STR_CA_CA0_SHIFT (0U)
5071#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
5072#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
5073#define CAU_STR_CA_CA1_SHIFT (0U)
5074#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
5075#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
5076#define CAU_STR_CA_CA2_SHIFT (0U)
5077#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
5078#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
5079#define CAU_STR_CA_CA3_SHIFT (0U)
5080#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
5081#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
5082#define CAU_STR_CA_CA4_SHIFT (0U)
5083#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
5084#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
5085#define CAU_STR_CA_CA5_SHIFT (0U)
5086#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
5087#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
5088#define CAU_STR_CA_CA6_SHIFT (0U)
5089#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
5090#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
5091#define CAU_STR_CA_CA7_SHIFT (0U)
5092#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
5093#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
5094#define CAU_STR_CA_CA8_SHIFT (0U)
5095#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
5096/*! @} */
5097
5098/* The count of CAU_STR_CA */
5099#define CAU_STR_CA_COUNT (9U)
5100
5101/*! @name ADR_CASR - Status register - Add Register command */
5102/*! @{ */
5103#define CAU_ADR_CASR_IC_MASK (0x1U)
5104#define CAU_ADR_CASR_IC_SHIFT (0U)
5105/*! IC
5106 * 0b0..No illegal commands issued
5107 * 0b1..Illegal command issued
5108 */
5109#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
5110#define CAU_ADR_CASR_DPE_MASK (0x2U)
5111#define CAU_ADR_CASR_DPE_SHIFT (1U)
5112/*! DPE
5113 * 0b0..No error detected
5114 * 0b1..DES key parity error detected
5115 */
5116#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
5117#define CAU_ADR_CASR_VER_MASK (0xF0000000U)
5118#define CAU_ADR_CASR_VER_SHIFT (28U)
5119/*! VER - CAU version
5120 * 0b0001..Initial CAU version
5121 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5122 */
5123#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
5124/*! @} */
5125
5126/*! @name ADR_CAA - Accumulator register - Add to register command */
5127/*! @{ */
5128#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
5129#define CAU_ADR_CAA_ACC_SHIFT (0U)
5130#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
5131/*! @} */
5132
5133/*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
5134/*! @{ */
5135#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
5136#define CAU_ADR_CA_CA0_SHIFT (0U)
5137#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
5138#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
5139#define CAU_ADR_CA_CA1_SHIFT (0U)
5140#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
5141#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
5142#define CAU_ADR_CA_CA2_SHIFT (0U)
5143#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
5144#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
5145#define CAU_ADR_CA_CA3_SHIFT (0U)
5146#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
5147#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
5148#define CAU_ADR_CA_CA4_SHIFT (0U)
5149#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
5150#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
5151#define CAU_ADR_CA_CA5_SHIFT (0U)
5152#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
5153#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
5154#define CAU_ADR_CA_CA6_SHIFT (0U)
5155#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
5156#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
5157#define CAU_ADR_CA_CA7_SHIFT (0U)
5158#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
5159#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
5160#define CAU_ADR_CA_CA8_SHIFT (0U)
5161#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
5162/*! @} */
5163
5164/* The count of CAU_ADR_CA */
5165#define CAU_ADR_CA_COUNT (9U)
5166
5167/*! @name RADR_CASR - Status register - Reverse and Add to Register command */
5168/*! @{ */
5169#define CAU_RADR_CASR_IC_MASK (0x1U)
5170#define CAU_RADR_CASR_IC_SHIFT (0U)
5171/*! IC
5172 * 0b0..No illegal commands issued
5173 * 0b1..Illegal command issued
5174 */
5175#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
5176#define CAU_RADR_CASR_DPE_MASK (0x2U)
5177#define CAU_RADR_CASR_DPE_SHIFT (1U)
5178/*! DPE
5179 * 0b0..No error detected
5180 * 0b1..DES key parity error detected
5181 */
5182#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
5183#define CAU_RADR_CASR_VER_MASK (0xF0000000U)
5184#define CAU_RADR_CASR_VER_SHIFT (28U)
5185/*! VER - CAU version
5186 * 0b0001..Initial CAU version
5187 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5188 */
5189#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
5190/*! @} */
5191
5192/*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
5193/*! @{ */
5194#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
5195#define CAU_RADR_CAA_ACC_SHIFT (0U)
5196#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
5197/*! @} */
5198
5199/*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
5200/*! @{ */
5201#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
5202#define CAU_RADR_CA_CA0_SHIFT (0U)
5203#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
5204#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
5205#define CAU_RADR_CA_CA1_SHIFT (0U)
5206#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
5207#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
5208#define CAU_RADR_CA_CA2_SHIFT (0U)
5209#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
5210#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
5211#define CAU_RADR_CA_CA3_SHIFT (0U)
5212#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
5213#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
5214#define CAU_RADR_CA_CA4_SHIFT (0U)
5215#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
5216#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
5217#define CAU_RADR_CA_CA5_SHIFT (0U)
5218#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
5219#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
5220#define CAU_RADR_CA_CA6_SHIFT (0U)
5221#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
5222#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
5223#define CAU_RADR_CA_CA7_SHIFT (0U)
5224#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
5225#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
5226#define CAU_RADR_CA_CA8_SHIFT (0U)
5227#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
5228/*! @} */
5229
5230/* The count of CAU_RADR_CA */
5231#define CAU_RADR_CA_COUNT (9U)
5232
5233/*! @name XOR_CASR - Status register - Exclusive Or command */
5234/*! @{ */
5235#define CAU_XOR_CASR_IC_MASK (0x1U)
5236#define CAU_XOR_CASR_IC_SHIFT (0U)
5237/*! IC
5238 * 0b0..No illegal commands issued
5239 * 0b1..Illegal command issued
5240 */
5241#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
5242#define CAU_XOR_CASR_DPE_MASK (0x2U)
5243#define CAU_XOR_CASR_DPE_SHIFT (1U)
5244/*! DPE
5245 * 0b0..No error detected
5246 * 0b1..DES key parity error detected
5247 */
5248#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
5249#define CAU_XOR_CASR_VER_MASK (0xF0000000U)
5250#define CAU_XOR_CASR_VER_SHIFT (28U)
5251/*! VER - CAU version
5252 * 0b0001..Initial CAU version
5253 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5254 */
5255#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
5256/*! @} */
5257
5258/*! @name XOR_CAA - Accumulator register - Exclusive Or command */
5259/*! @{ */
5260#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
5261#define CAU_XOR_CAA_ACC_SHIFT (0U)
5262#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
5263/*! @} */
5264
5265/*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
5266/*! @{ */
5267#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
5268#define CAU_XOR_CA_CA0_SHIFT (0U)
5269#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
5270#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
5271#define CAU_XOR_CA_CA1_SHIFT (0U)
5272#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
5273#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
5274#define CAU_XOR_CA_CA2_SHIFT (0U)
5275#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
5276#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
5277#define CAU_XOR_CA_CA3_SHIFT (0U)
5278#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
5279#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
5280#define CAU_XOR_CA_CA4_SHIFT (0U)
5281#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
5282#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
5283#define CAU_XOR_CA_CA5_SHIFT (0U)
5284#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
5285#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
5286#define CAU_XOR_CA_CA6_SHIFT (0U)
5287#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
5288#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
5289#define CAU_XOR_CA_CA7_SHIFT (0U)
5290#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
5291#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
5292#define CAU_XOR_CA_CA8_SHIFT (0U)
5293#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
5294/*! @} */
5295
5296/* The count of CAU_XOR_CA */
5297#define CAU_XOR_CA_COUNT (9U)
5298
5299/*! @name ROTL_CASR - Status register - Rotate Left command */
5300/*! @{ */
5301#define CAU_ROTL_CASR_IC_MASK (0x1U)
5302#define CAU_ROTL_CASR_IC_SHIFT (0U)
5303/*! IC
5304 * 0b0..No illegal commands issued
5305 * 0b1..Illegal command issued
5306 */
5307#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
5308#define CAU_ROTL_CASR_DPE_MASK (0x2U)
5309#define CAU_ROTL_CASR_DPE_SHIFT (1U)
5310/*! DPE
5311 * 0b0..No error detected
5312 * 0b1..DES key parity error detected
5313 */
5314#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
5315#define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
5316#define CAU_ROTL_CASR_VER_SHIFT (28U)
5317/*! VER - CAU version
5318 * 0b0001..Initial CAU version
5319 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5320 */
5321#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
5322/*! @} */
5323
5324/*! @name ROTL_CAA - Accumulator register - Rotate Left command */
5325/*! @{ */
5326#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
5327#define CAU_ROTL_CAA_ACC_SHIFT (0U)
5328#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
5329/*! @} */
5330
5331/*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
5332/*! @{ */
5333#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
5334#define CAU_ROTL_CA_CA0_SHIFT (0U)
5335#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
5336#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
5337#define CAU_ROTL_CA_CA1_SHIFT (0U)
5338#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
5339#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
5340#define CAU_ROTL_CA_CA2_SHIFT (0U)
5341#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
5342#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
5343#define CAU_ROTL_CA_CA3_SHIFT (0U)
5344#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
5345#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
5346#define CAU_ROTL_CA_CA4_SHIFT (0U)
5347#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
5348#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
5349#define CAU_ROTL_CA_CA5_SHIFT (0U)
5350#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
5351#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
5352#define CAU_ROTL_CA_CA6_SHIFT (0U)
5353#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
5354#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
5355#define CAU_ROTL_CA_CA7_SHIFT (0U)
5356#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
5357#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
5358#define CAU_ROTL_CA_CA8_SHIFT (0U)
5359#define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
5360/*! @} */
5361
5362/* The count of CAU_ROTL_CA */
5363#define CAU_ROTL_CA_COUNT (9U)
5364
5365/*! @name AESC_CASR - Status register - AES Column Operation command */
5366/*! @{ */
5367#define CAU_AESC_CASR_IC_MASK (0x1U)
5368#define CAU_AESC_CASR_IC_SHIFT (0U)
5369/*! IC
5370 * 0b0..No illegal commands issued
5371 * 0b1..Illegal command issued
5372 */
5373#define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
5374#define CAU_AESC_CASR_DPE_MASK (0x2U)
5375#define CAU_AESC_CASR_DPE_SHIFT (1U)
5376/*! DPE
5377 * 0b0..No error detected
5378 * 0b1..DES key parity error detected
5379 */
5380#define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
5381#define CAU_AESC_CASR_VER_MASK (0xF0000000U)
5382#define CAU_AESC_CASR_VER_SHIFT (28U)
5383/*! VER - CAU version
5384 * 0b0001..Initial CAU version
5385 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5386 */
5387#define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
5388/*! @} */
5389
5390/*! @name AESC_CAA - Accumulator register - AES Column Operation command */
5391/*! @{ */
5392#define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
5393#define CAU_AESC_CAA_ACC_SHIFT (0U)
5394#define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
5395/*! @} */
5396
5397/*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
5398/*! @{ */
5399#define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
5400#define CAU_AESC_CA_CA0_SHIFT (0U)
5401#define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
5402#define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
5403#define CAU_AESC_CA_CA1_SHIFT (0U)
5404#define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
5405#define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
5406#define CAU_AESC_CA_CA2_SHIFT (0U)
5407#define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
5408#define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
5409#define CAU_AESC_CA_CA3_SHIFT (0U)
5410#define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
5411#define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
5412#define CAU_AESC_CA_CA4_SHIFT (0U)
5413#define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
5414#define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
5415#define CAU_AESC_CA_CA5_SHIFT (0U)
5416#define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
5417#define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
5418#define CAU_AESC_CA_CA6_SHIFT (0U)
5419#define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
5420#define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
5421#define CAU_AESC_CA_CA7_SHIFT (0U)
5422#define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
5423#define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
5424#define CAU_AESC_CA_CA8_SHIFT (0U)
5425#define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
5426/*! @} */
5427
5428/* The count of CAU_AESC_CA */
5429#define CAU_AESC_CA_COUNT (9U)
5430
5431/*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
5432/*! @{ */
5433#define CAU_AESIC_CASR_IC_MASK (0x1U)
5434#define CAU_AESIC_CASR_IC_SHIFT (0U)
5435/*! IC
5436 * 0b0..No illegal commands issued
5437 * 0b1..Illegal command issued
5438 */
5439#define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
5440#define CAU_AESIC_CASR_DPE_MASK (0x2U)
5441#define CAU_AESIC_CASR_DPE_SHIFT (1U)
5442/*! DPE
5443 * 0b0..No error detected
5444 * 0b1..DES key parity error detected
5445 */
5446#define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
5447#define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
5448#define CAU_AESIC_CASR_VER_SHIFT (28U)
5449/*! VER - CAU version
5450 * 0b0001..Initial CAU version
5451 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
5452 */
5453#define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
5454/*! @} */
5455
5456/*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
5457/*! @{ */
5458#define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
5459#define CAU_AESIC_CAA_ACC_SHIFT (0U)
5460#define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
5461/*! @} */
5462
5463/*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
5464/*! @{ */
5465#define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
5466#define CAU_AESIC_CA_CA0_SHIFT (0U)
5467#define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
5468#define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
5469#define CAU_AESIC_CA_CA1_SHIFT (0U)
5470#define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
5471#define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
5472#define CAU_AESIC_CA_CA2_SHIFT (0U)
5473#define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
5474#define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
5475#define CAU_AESIC_CA_CA3_SHIFT (0U)
5476#define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
5477#define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
5478#define CAU_AESIC_CA_CA4_SHIFT (0U)
5479#define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
5480#define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
5481#define CAU_AESIC_CA_CA5_SHIFT (0U)
5482#define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
5483#define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
5484#define CAU_AESIC_CA_CA6_SHIFT (0U)
5485#define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
5486#define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
5487#define CAU_AESIC_CA_CA7_SHIFT (0U)
5488#define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
5489#define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
5490#define CAU_AESIC_CA_CA8_SHIFT (0U)
5491#define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
5492/*! @} */
5493
5494/* The count of CAU_AESIC_CA */
5495#define CAU_AESIC_CA_COUNT (9U)
5496
5497
5498/*!
5499 * @}
5500 */ /* end of group CAU_Register_Masks */
5501
5502
5503/* CAU - Peripheral instance base addresses */
5504/** Peripheral CAU base address */
5505#define CAU_BASE (0xE0081000u)
5506/** Peripheral CAU base pointer */
5507#define CAU ((CAU_Type *)CAU_BASE)
5508/** Array initializer of CAU peripheral base addresses */
5509#define CAU_BASE_ADDRS { CAU_BASE }
5510/** Array initializer of CAU peripheral base pointers */
5511#define CAU_BASE_PTRS { CAU }
5512
5513/*!
5514 * @}
5515 */ /* end of group CAU_Peripheral_Access_Layer */
5516
5517
5518/* ----------------------------------------------------------------------------
5519 -- CMP Peripheral Access Layer
5520 ---------------------------------------------------------------------------- */
5521
5522/*!
5523 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
5524 * @{
5525 */
5526
5527/** CMP - Register Layout Typedef */
5528typedef struct {
5529 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
5530 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
5531 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
5532 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
5533 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
5534 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
5535} CMP_Type;
5536
5537/* ----------------------------------------------------------------------------
5538 -- CMP Register Masks
5539 ---------------------------------------------------------------------------- */
5540
5541/*!
5542 * @addtogroup CMP_Register_Masks CMP Register Masks
5543 * @{
5544 */
5545
5546/*! @name CR0 - CMP Control Register 0 */
5547/*! @{ */
5548#define CMP_CR0_HYSTCTR_MASK (0x3U)
5549#define CMP_CR0_HYSTCTR_SHIFT (0U)
5550/*! HYSTCTR - Comparator hard block hysteresis control
5551 * 0b00..Level 0
5552 * 0b01..Level 1
5553 * 0b10..Level 2
5554 * 0b11..Level 3
5555 */
5556#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
5557#define CMP_CR0_FILTER_CNT_MASK (0x70U)
5558#define CMP_CR0_FILTER_CNT_SHIFT (4U)
5559/*! FILTER_CNT - Filter Sample Count
5560 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
5561 * 0b001..One sample must agree. The comparator output is simply sampled.
5562 * 0b010..2 consecutive samples must agree.
5563 * 0b011..3 consecutive samples must agree.
5564 * 0b100..4 consecutive samples must agree.
5565 * 0b101..5 consecutive samples must agree.
5566 * 0b110..6 consecutive samples must agree.
5567 * 0b111..7 consecutive samples must agree.
5568 */
5569#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
5570/*! @} */
5571
5572/*! @name CR1 - CMP Control Register 1 */
5573/*! @{ */
5574#define CMP_CR1_EN_MASK (0x1U)
5575#define CMP_CR1_EN_SHIFT (0U)
5576/*! EN - Comparator Module Enable
5577 * 0b0..Analog Comparator is disabled.
5578 * 0b1..Analog Comparator is enabled.
5579 */
5580#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
5581#define CMP_CR1_OPE_MASK (0x2U)
5582#define CMP_CR1_OPE_SHIFT (1U)
5583/*! OPE - Comparator Output Pin Enable
5584 * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
5585 * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
5586 */
5587#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
5588#define CMP_CR1_COS_MASK (0x4U)
5589#define CMP_CR1_COS_SHIFT (2U)
5590/*! COS - Comparator Output Select
5591 * 0b0..Set the filtered comparator output (CMPO) to equal COUT.
5592 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
5593 */
5594#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
5595#define CMP_CR1_INV_MASK (0x8U)
5596#define CMP_CR1_INV_SHIFT (3U)
5597/*! INV - Comparator INVERT
5598 * 0b0..Does not invert the comparator output.
5599 * 0b1..Inverts the comparator output.
5600 */
5601#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
5602#define CMP_CR1_PMODE_MASK (0x10U)
5603#define CMP_CR1_PMODE_SHIFT (4U)
5604/*! PMODE - Power Mode Select
5605 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
5606 * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
5607 */
5608#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
5609#define CMP_CR1_TRIGM_MASK (0x20U)
5610#define CMP_CR1_TRIGM_SHIFT (5U)
5611/*! TRIGM - Trigger Mode Enable
5612 * 0b0..Trigger mode is disabled.
5613 * 0b1..Trigger mode is enabled.
5614 */
5615#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
5616#define CMP_CR1_WE_MASK (0x40U)
5617#define CMP_CR1_WE_SHIFT (6U)
5618/*! WE - Windowing Enable
5619 * 0b0..Windowing mode is not selected.
5620 * 0b1..Windowing mode is selected.
5621 */
5622#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
5623#define CMP_CR1_SE_MASK (0x80U)
5624#define CMP_CR1_SE_SHIFT (7U)
5625/*! SE - Sample Enable
5626 * 0b0..Sampling mode is not selected.
5627 * 0b1..Sampling mode is selected.
5628 */
5629#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
5630/*! @} */
5631
5632/*! @name FPR - CMP Filter Period Register */
5633/*! @{ */
5634#define CMP_FPR_FILT_PER_MASK (0xFFU)
5635#define CMP_FPR_FILT_PER_SHIFT (0U)
5636#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
5637/*! @} */
5638
5639/*! @name SCR - CMP Status and Control Register */
5640/*! @{ */
5641#define CMP_SCR_COUT_MASK (0x1U)
5642#define CMP_SCR_COUT_SHIFT (0U)
5643#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
5644#define CMP_SCR_CFF_MASK (0x2U)
5645#define CMP_SCR_CFF_SHIFT (1U)
5646/*! CFF - Analog Comparator Flag Falling
5647 * 0b0..Falling-edge on COUT has not been detected.
5648 * 0b1..Falling-edge on COUT has occurred.
5649 */
5650#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
5651#define CMP_SCR_CFR_MASK (0x4U)
5652#define CMP_SCR_CFR_SHIFT (2U)
5653/*! CFR - Analog Comparator Flag Rising
5654 * 0b0..Rising-edge on COUT has not been detected.
5655 * 0b1..Rising-edge on COUT has occurred.
5656 */
5657#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
5658#define CMP_SCR_IEF_MASK (0x8U)
5659#define CMP_SCR_IEF_SHIFT (3U)
5660/*! IEF - Comparator Interrupt Enable Falling
5661 * 0b0..Interrupt is disabled.
5662 * 0b1..Interrupt is enabled.
5663 */
5664#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
5665#define CMP_SCR_IER_MASK (0x10U)
5666#define CMP_SCR_IER_SHIFT (4U)
5667/*! IER - Comparator Interrupt Enable Rising
5668 * 0b0..Interrupt is disabled.
5669 * 0b1..Interrupt is enabled.
5670 */
5671#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
5672#define CMP_SCR_DMAEN_MASK (0x40U)
5673#define CMP_SCR_DMAEN_SHIFT (6U)
5674/*! DMAEN - DMA Enable Control
5675 * 0b0..DMA is disabled.
5676 * 0b1..DMA is enabled.
5677 */
5678#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
5679/*! @} */
5680
5681/*! @name DACCR - DAC Control Register */
5682/*! @{ */
5683#define CMP_DACCR_VOSEL_MASK (0x3FU)
5684#define CMP_DACCR_VOSEL_SHIFT (0U)
5685#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
5686#define CMP_DACCR_VRSEL_MASK (0x40U)
5687#define CMP_DACCR_VRSEL_SHIFT (6U)
5688/*! VRSEL - Supply Voltage Reference Source Select
5689 * 0b0..Vin1 is selected as resistor ladder network supply reference.
5690 * 0b1..Vin2 is selected as resistor ladder network supply reference.
5691 */
5692#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
5693#define CMP_DACCR_DACEN_MASK (0x80U)
5694#define CMP_DACCR_DACEN_SHIFT (7U)
5695/*! DACEN - DAC Enable
5696 * 0b0..DAC is disabled.
5697 * 0b1..DAC is enabled.
5698 */
5699#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
5700/*! @} */
5701
5702/*! @name MUXCR - MUX Control Register */
5703/*! @{ */
5704#define CMP_MUXCR_MSEL_MASK (0x7U)
5705#define CMP_MUXCR_MSEL_SHIFT (0U)
5706/*! MSEL - Minus Input Mux Control
5707 * 0b000..IN0
5708 * 0b001..IN1
5709 * 0b010..IN2
5710 * 0b011..IN3
5711 * 0b100..IN4
5712 * 0b101..IN5
5713 * 0b110..IN6
5714 * 0b111..IN7
5715 */
5716#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
5717#define CMP_MUXCR_PSEL_MASK (0x38U)
5718#define CMP_MUXCR_PSEL_SHIFT (3U)
5719/*! PSEL - Plus Input Mux Control
5720 * 0b000..IN0
5721 * 0b001..IN1
5722 * 0b010..IN2
5723 * 0b011..IN3
5724 * 0b100..IN4
5725 * 0b101..IN5
5726 * 0b110..IN6
5727 * 0b111..IN7
5728 */
5729#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
5730#define CMP_MUXCR_PSTM_MASK (0x80U)
5731#define CMP_MUXCR_PSTM_SHIFT (7U)
5732/*! PSTM - Pass Through Mode Enable
5733 * 0b0..Pass Through Mode is disabled.
5734 * 0b1..Pass Through Mode is enabled.
5735 */
5736#define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
5737/*! @} */
5738
5739
5740/*!
5741 * @}
5742 */ /* end of group CMP_Register_Masks */
5743
5744
5745/* CMP - Peripheral instance base addresses */
5746/** Peripheral CMP0 base address */
5747#define CMP0_BASE (0x40073000u)
5748/** Peripheral CMP0 base pointer */
5749#define CMP0 ((CMP_Type *)CMP0_BASE)
5750/** Peripheral CMP1 base address */
5751#define CMP1_BASE (0x40073008u)
5752/** Peripheral CMP1 base pointer */
5753#define CMP1 ((CMP_Type *)CMP1_BASE)
5754/** Peripheral CMP2 base address */
5755#define CMP2_BASE (0x40073010u)
5756/** Peripheral CMP2 base pointer */
5757#define CMP2 ((CMP_Type *)CMP2_BASE)
5758/** Peripheral CMP3 base address */
5759#define CMP3_BASE (0x40073018u)
5760/** Peripheral CMP3 base pointer */
5761#define CMP3 ((CMP_Type *)CMP3_BASE)
5762/** Array initializer of CMP peripheral base addresses */
5763#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
5764/** Array initializer of CMP peripheral base pointers */
5765#define CMP_BASE_PTRS { CMP0, CMP1, CMP2, CMP3 }
5766/** Interrupt vectors for the CMP peripheral type */
5767#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }
5768
5769/*!
5770 * @}
5771 */ /* end of group CMP_Peripheral_Access_Layer */
5772
5773
5774/* ----------------------------------------------------------------------------
5775 -- CMT Peripheral Access Layer
5776 ---------------------------------------------------------------------------- */
5777
5778/*!
5779 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
5780 * @{
5781 */
5782
5783/** CMT - Register Layout Typedef */
5784typedef struct {
5785 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
5786 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
5787 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
5788 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
5789 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
5790 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
5791 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
5792 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
5793 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
5794 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
5795 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
5796 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
5797} CMT_Type;
5798
5799/* ----------------------------------------------------------------------------
5800 -- CMT Register Masks
5801 ---------------------------------------------------------------------------- */
5802
5803/*!
5804 * @addtogroup CMT_Register_Masks CMT Register Masks
5805 * @{
5806 */
5807
5808/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
5809/*! @{ */
5810#define CMT_CGH1_PH_MASK (0xFFU)
5811#define CMT_CGH1_PH_SHIFT (0U)
5812#define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
5813/*! @} */
5814
5815/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
5816/*! @{ */
5817#define CMT_CGL1_PL_MASK (0xFFU)
5818#define CMT_CGL1_PL_SHIFT (0U)
5819#define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
5820/*! @} */
5821
5822/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
5823/*! @{ */
5824#define CMT_CGH2_SH_MASK (0xFFU)
5825#define CMT_CGH2_SH_SHIFT (0U)
5826#define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
5827/*! @} */
5828
5829/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
5830/*! @{ */
5831#define CMT_CGL2_SL_MASK (0xFFU)
5832#define CMT_CGL2_SL_SHIFT (0U)
5833#define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
5834/*! @} */
5835
5836/*! @name OC - CMT Output Control Register */
5837/*! @{ */
5838#define CMT_OC_IROPEN_MASK (0x20U)
5839#define CMT_OC_IROPEN_SHIFT (5U)
5840/*! IROPEN - IRO Pin Enable
5841 * 0b0..The IRO signal is disabled.
5842 * 0b1..The IRO signal is enabled as output.
5843 */
5844#define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
5845#define CMT_OC_CMTPOL_MASK (0x40U)
5846#define CMT_OC_CMTPOL_SHIFT (6U)
5847/*! CMTPOL - CMT Output Polarity
5848 * 0b0..The IRO signal is active-low.
5849 * 0b1..The IRO signal is active-high.
5850 */
5851#define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
5852#define CMT_OC_IROL_MASK (0x80U)
5853#define CMT_OC_IROL_SHIFT (7U)
5854#define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
5855/*! @} */
5856
5857/*! @name MSC - CMT Modulator Status and Control Register */
5858/*! @{ */
5859#define CMT_MSC_MCGEN_MASK (0x1U)
5860#define CMT_MSC_MCGEN_SHIFT (0U)
5861/*! MCGEN - Modulator and Carrier Generator Enable
5862 * 0b0..Modulator and carrier generator disabled
5863 * 0b1..Modulator and carrier generator enabled
5864 */
5865#define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
5866#define CMT_MSC_EOCIE_MASK (0x2U)
5867#define CMT_MSC_EOCIE_SHIFT (1U)
5868/*! EOCIE - End of Cycle Interrupt Enable
5869 * 0b0..CPU interrupt is disabled.
5870 * 0b1..CPU interrupt is enabled.
5871 */
5872#define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
5873#define CMT_MSC_FSK_MASK (0x4U)
5874#define CMT_MSC_FSK_SHIFT (2U)
5875/*! FSK - FSK Mode Select
5876 * 0b0..The CMT operates in Time or Baseband mode.
5877 * 0b1..The CMT operates in FSK mode.
5878 */
5879#define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
5880#define CMT_MSC_BASE_MASK (0x8U)
5881#define CMT_MSC_BASE_SHIFT (3U)
5882/*! BASE - Baseband Enable
5883 * 0b0..Baseband mode is disabled.
5884 * 0b1..Baseband mode is enabled.
5885 */
5886#define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
5887#define CMT_MSC_EXSPC_MASK (0x10U)
5888#define CMT_MSC_EXSPC_SHIFT (4U)
5889/*! EXSPC - Extended Space Enable
5890 * 0b0..Extended space is disabled.
5891 * 0b1..Extended space is enabled.
5892 */
5893#define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
5894#define CMT_MSC_CMTDIV_MASK (0x60U)
5895#define CMT_MSC_CMTDIV_SHIFT (5U)
5896/*! CMTDIV - CMT Clock Divide Prescaler
5897 * 0b00..IF * 1
5898 * 0b01..IF * 2
5899 * 0b10..IF * 4
5900 * 0b11..IF * 8
5901 */
5902#define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
5903#define CMT_MSC_EOCF_MASK (0x80U)
5904#define CMT_MSC_EOCF_SHIFT (7U)
5905/*! EOCF - End Of Cycle Status Flag
5906 * 0b0..End of modulation cycle has not occured since the flag last cleared.
5907 * 0b1..End of modulator cycle has occurred.
5908 */
5909#define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
5910/*! @} */
5911
5912/*! @name CMD1 - CMT Modulator Data Register Mark High */
5913/*! @{ */
5914#define CMT_CMD1_MB_MASK (0xFFU)
5915#define CMT_CMD1_MB_SHIFT (0U)
5916#define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
5917/*! @} */
5918
5919/*! @name CMD2 - CMT Modulator Data Register Mark Low */
5920/*! @{ */
5921#define CMT_CMD2_MB_MASK (0xFFU)
5922#define CMT_CMD2_MB_SHIFT (0U)
5923#define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
5924/*! @} */
5925
5926/*! @name CMD3 - CMT Modulator Data Register Space High */
5927/*! @{ */
5928#define CMT_CMD3_SB_MASK (0xFFU)
5929#define CMT_CMD3_SB_SHIFT (0U)
5930#define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
5931/*! @} */
5932
5933/*! @name CMD4 - CMT Modulator Data Register Space Low */
5934/*! @{ */
5935#define CMT_CMD4_SB_MASK (0xFFU)
5936#define CMT_CMD4_SB_SHIFT (0U)
5937#define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
5938/*! @} */
5939
5940/*! @name PPS - CMT Primary Prescaler Register */
5941/*! @{ */
5942#define CMT_PPS_PPSDIV_MASK (0xFU)
5943#define CMT_PPS_PPSDIV_SHIFT (0U)
5944/*! PPSDIV - Primary Prescaler Divider
5945 * 0b0000..Bus clock * 1
5946 * 0b0001..Bus clock * 2
5947 * 0b0010..Bus clock * 3
5948 * 0b0011..Bus clock * 4
5949 * 0b0100..Bus clock * 5
5950 * 0b0101..Bus clock * 6
5951 * 0b0110..Bus clock * 7
5952 * 0b0111..Bus clock * 8
5953 * 0b1000..Bus clock * 9
5954 * 0b1001..Bus clock * 10
5955 * 0b1010..Bus clock * 11
5956 * 0b1011..Bus clock * 12
5957 * 0b1100..Bus clock * 13
5958 * 0b1101..Bus clock * 14
5959 * 0b1110..Bus clock * 15
5960 * 0b1111..Bus clock * 16
5961 */
5962#define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
5963/*! @} */
5964
5965/*! @name DMA - CMT Direct Memory Access Register */
5966/*! @{ */
5967#define CMT_DMA_DMA_MASK (0x1U)
5968#define CMT_DMA_DMA_SHIFT (0U)
5969/*! DMA - DMA Enable
5970 * 0b0..DMA transfer request and done are disabled.
5971 * 0b1..DMA transfer request and done are enabled.
5972 */
5973#define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
5974/*! @} */
5975
5976
5977/*!
5978 * @}
5979 */ /* end of group CMT_Register_Masks */
5980
5981
5982/* CMT - Peripheral instance base addresses */
5983/** Peripheral CMT base address */
5984#define CMT_BASE (0x40062000u)
5985/** Peripheral CMT base pointer */
5986#define CMT ((CMT_Type *)CMT_BASE)
5987/** Array initializer of CMT peripheral base addresses */
5988#define CMT_BASE_ADDRS { CMT_BASE }
5989/** Array initializer of CMT peripheral base pointers */
5990#define CMT_BASE_PTRS { CMT }
5991/** Interrupt vectors for the CMT peripheral type */
5992#define CMT_IRQS { CMT_IRQn }
5993
5994/*!
5995 * @}
5996 */ /* end of group CMT_Peripheral_Access_Layer */
5997
5998
5999/* ----------------------------------------------------------------------------
6000 -- CRC Peripheral Access Layer
6001 ---------------------------------------------------------------------------- */
6002
6003/*!
6004 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
6005 * @{
6006 */
6007
6008/** CRC - Register Layout Typedef */
6009typedef struct {
6010 union { /* offset: 0x0 */
6011 struct { /* offset: 0x0 */
6012 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
6013 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
6014 } ACCESS16BIT;
6015 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
6016 struct { /* offset: 0x0 */
6017 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
6018 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
6019 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
6020 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
6021 } ACCESS8BIT;
6022 };
6023 union { /* offset: 0x4 */
6024 struct { /* offset: 0x4 */
6025 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
6026 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
6027 } GPOLY_ACCESS16BIT;
6028 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
6029 struct { /* offset: 0x4 */
6030 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
6031 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
6032 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
6033 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
6034 } GPOLY_ACCESS8BIT;
6035 };
6036 union { /* offset: 0x8 */
6037 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
6038 struct { /* offset: 0x8 */
6039 uint8_t RESERVED_0[3];
6040 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
6041 } CTRL_ACCESS8BIT;
6042 };
6043} CRC_Type;
6044
6045/* ----------------------------------------------------------------------------
6046 -- CRC Register Masks
6047 ---------------------------------------------------------------------------- */
6048
6049/*!
6050 * @addtogroup CRC_Register_Masks CRC Register Masks
6051 * @{
6052 */
6053
6054/*! @name DATAL - CRC_DATAL register. */
6055/*! @{ */
6056#define CRC_DATAL_DATAL_MASK (0xFFFFU)
6057#define CRC_DATAL_DATAL_SHIFT (0U)
6058#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
6059/*! @} */
6060
6061/*! @name DATAH - CRC_DATAH register. */
6062/*! @{ */
6063#define CRC_DATAH_DATAH_MASK (0xFFFFU)
6064#define CRC_DATAH_DATAH_SHIFT (0U)
6065#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
6066/*! @} */
6067
6068/*! @name DATA - CRC Data register */
6069/*! @{ */
6070#define CRC_DATA_LL_MASK (0xFFU)
6071#define CRC_DATA_LL_SHIFT (0U)
6072#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
6073#define CRC_DATA_LU_MASK (0xFF00U)
6074#define CRC_DATA_LU_SHIFT (8U)
6075#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
6076#define CRC_DATA_HL_MASK (0xFF0000U)
6077#define CRC_DATA_HL_SHIFT (16U)
6078#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
6079#define CRC_DATA_HU_MASK (0xFF000000U)
6080#define CRC_DATA_HU_SHIFT (24U)
6081#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
6082/*! @} */
6083
6084/*! @name DATALL - CRC_DATALL register. */
6085/*! @{ */
6086#define CRC_DATALL_DATALL_MASK (0xFFU)
6087#define CRC_DATALL_DATALL_SHIFT (0U)
6088#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
6089/*! @} */
6090
6091/*! @name DATALU - CRC_DATALU register. */
6092/*! @{ */
6093#define CRC_DATALU_DATALU_MASK (0xFFU)
6094#define CRC_DATALU_DATALU_SHIFT (0U)
6095#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
6096/*! @} */
6097
6098/*! @name DATAHL - CRC_DATAHL register. */
6099/*! @{ */
6100#define CRC_DATAHL_DATAHL_MASK (0xFFU)
6101#define CRC_DATAHL_DATAHL_SHIFT (0U)
6102#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
6103/*! @} */
6104
6105/*! @name DATAHU - CRC_DATAHU register. */
6106/*! @{ */
6107#define CRC_DATAHU_DATAHU_MASK (0xFFU)
6108#define CRC_DATAHU_DATAHU_SHIFT (0U)
6109#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
6110/*! @} */
6111
6112/*! @name GPOLYL - CRC_GPOLYL register. */
6113/*! @{ */
6114#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
6115#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
6116#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
6117/*! @} */
6118
6119/*! @name GPOLYH - CRC_GPOLYH register. */
6120/*! @{ */
6121#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
6122#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
6123#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
6124/*! @} */
6125
6126/*! @name GPOLY - CRC Polynomial register */
6127/*! @{ */
6128#define CRC_GPOLY_LOW_MASK (0xFFFFU)
6129#define CRC_GPOLY_LOW_SHIFT (0U)
6130#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
6131#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
6132#define CRC_GPOLY_HIGH_SHIFT (16U)
6133#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
6134/*! @} */
6135
6136/*! @name GPOLYLL - CRC_GPOLYLL register. */
6137/*! @{ */
6138#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
6139#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
6140#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
6141/*! @} */
6142
6143/*! @name GPOLYLU - CRC_GPOLYLU register. */
6144/*! @{ */
6145#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
6146#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
6147#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
6148/*! @} */
6149
6150/*! @name GPOLYHL - CRC_GPOLYHL register. */
6151/*! @{ */
6152#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
6153#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
6154#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
6155/*! @} */
6156
6157/*! @name GPOLYHU - CRC_GPOLYHU register. */
6158/*! @{ */
6159#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
6160#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
6161#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
6162/*! @} */
6163
6164/*! @name CTRL - CRC Control register */
6165/*! @{ */
6166#define CRC_CTRL_TCRC_MASK (0x1000000U)
6167#define CRC_CTRL_TCRC_SHIFT (24U)
6168/*! TCRC
6169 * 0b0..16-bit CRC protocol.
6170 * 0b1..32-bit CRC protocol.
6171 */
6172#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
6173#define CRC_CTRL_WAS_MASK (0x2000000U)
6174#define CRC_CTRL_WAS_SHIFT (25U)
6175/*! WAS - Write CRC Data Register As Seed
6176 * 0b0..Writes to the CRC data register are data values.
6177 * 0b1..Writes to the CRC data register are seed values.
6178 */
6179#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
6180#define CRC_CTRL_FXOR_MASK (0x4000000U)
6181#define CRC_CTRL_FXOR_SHIFT (26U)
6182/*! FXOR - Complement Read Of CRC Data Register
6183 * 0b0..No XOR on reading.
6184 * 0b1..Invert or complement the read value of the CRC Data register.
6185 */
6186#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
6187#define CRC_CTRL_TOTR_MASK (0x30000000U)
6188#define CRC_CTRL_TOTR_SHIFT (28U)
6189/*! TOTR - Type Of Transpose For Read
6190 * 0b00..No transposition.
6191 * 0b01..Bits in bytes are transposed; bytes are not transposed.
6192 * 0b10..Both bits in bytes and bytes are transposed.
6193 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
6194 */
6195#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
6196#define CRC_CTRL_TOT_MASK (0xC0000000U)
6197#define CRC_CTRL_TOT_SHIFT (30U)
6198/*! TOT - Type Of Transpose For Writes
6199 * 0b00..No transposition.
6200 * 0b01..Bits in bytes are transposed; bytes are not transposed.
6201 * 0b10..Both bits in bytes and bytes are transposed.
6202 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
6203 */
6204#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
6205/*! @} */
6206
6207/*! @name CTRLHU - CRC_CTRLHU register. */
6208/*! @{ */
6209#define CRC_CTRLHU_TCRC_MASK (0x1U)
6210#define CRC_CTRLHU_TCRC_SHIFT (0U)
6211/*! TCRC
6212 * 0b0..16-bit CRC protocol.
6213 * 0b1..32-bit CRC protocol.
6214 */
6215#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
6216#define CRC_CTRLHU_WAS_MASK (0x2U)
6217#define CRC_CTRLHU_WAS_SHIFT (1U)
6218/*! WAS
6219 * 0b0..Writes to CRC data register are data values.
6220 * 0b1..Writes to CRC data reguster are seed values.
6221 */
6222#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
6223#define CRC_CTRLHU_FXOR_MASK (0x4U)
6224#define CRC_CTRLHU_FXOR_SHIFT (2U)
6225/*! FXOR
6226 * 0b0..No XOR on reading.
6227 * 0b1..Invert or complement the read value of CRC data register.
6228 */
6229#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
6230#define CRC_CTRLHU_TOTR_MASK (0x30U)
6231#define CRC_CTRLHU_TOTR_SHIFT (4U)
6232/*! TOTR
6233 * 0b00..No Transposition.
6234 * 0b01..Bits in bytes are transposed, bytes are not transposed.
6235 * 0b10..Both bits in bytes and bytes are transposed.
6236 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
6237 */
6238#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
6239#define CRC_CTRLHU_TOT_MASK (0xC0U)
6240#define CRC_CTRLHU_TOT_SHIFT (6U)
6241/*! TOT
6242 * 0b00..No Transposition.
6243 * 0b01..Bits in bytes are transposed, bytes are not transposed.
6244 * 0b10..Both bits in bytes and bytes are transposed.
6245 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
6246 */
6247#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
6248/*! @} */
6249
6250
6251/*!
6252 * @}
6253 */ /* end of group CRC_Register_Masks */
6254
6255
6256/* CRC - Peripheral instance base addresses */
6257/** Peripheral CRC base address */
6258#define CRC_BASE (0x40032000u)
6259/** Peripheral CRC base pointer */
6260#define CRC0 ((CRC_Type *)CRC_BASE)
6261/** Array initializer of CRC peripheral base addresses */
6262#define CRC_BASE_ADDRS { CRC_BASE }
6263/** Array initializer of CRC peripheral base pointers */
6264#define CRC_BASE_PTRS { CRC0 }
6265
6266/*!
6267 * @}
6268 */ /* end of group CRC_Peripheral_Access_Layer */
6269
6270
6271/* ----------------------------------------------------------------------------
6272 -- DAC Peripheral Access Layer
6273 ---------------------------------------------------------------------------- */
6274
6275/*!
6276 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
6277 * @{
6278 */
6279
6280/** DAC - Register Layout Typedef */
6281typedef struct {
6282 struct { /* offset: 0x0, array step: 0x2 */
6283 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
6284 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
6285 } DAT[16];
6286 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
6287 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
6288 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
6289 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
6290} DAC_Type;
6291
6292/* ----------------------------------------------------------------------------
6293 -- DAC Register Masks
6294 ---------------------------------------------------------------------------- */
6295
6296/*!
6297 * @addtogroup DAC_Register_Masks DAC Register Masks
6298 * @{
6299 */
6300
6301/*! @name DATL - DAC Data Low Register */
6302/*! @{ */
6303#define DAC_DATL_DATA0_MASK (0xFFU)
6304#define DAC_DATL_DATA0_SHIFT (0U)
6305#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
6306/*! @} */
6307
6308/* The count of DAC_DATL */
6309#define DAC_DATL_COUNT (16U)
6310
6311/*! @name DATH - DAC Data High Register */
6312/*! @{ */
6313#define DAC_DATH_DATA1_MASK (0xFU)
6314#define DAC_DATH_DATA1_SHIFT (0U)
6315#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
6316/*! @} */
6317
6318/* The count of DAC_DATH */
6319#define DAC_DATH_COUNT (16U)
6320
6321/*! @name SR - DAC Status Register */
6322/*! @{ */
6323#define DAC_SR_DACBFRPBF_MASK (0x1U)
6324#define DAC_SR_DACBFRPBF_SHIFT (0U)
6325/*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag
6326 * 0b0..The DAC buffer read pointer is not equal to C2[DACBFUP].
6327 * 0b1..The DAC buffer read pointer is equal to C2[DACBFUP].
6328 */
6329#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
6330#define DAC_SR_DACBFRPTF_MASK (0x2U)
6331#define DAC_SR_DACBFRPTF_SHIFT (1U)
6332/*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag
6333 * 0b0..The DAC buffer read pointer is not zero.
6334 * 0b1..The DAC buffer read pointer is zero.
6335 */
6336#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
6337#define DAC_SR_DACBFWMF_MASK (0x4U)
6338#define DAC_SR_DACBFWMF_SHIFT (2U)
6339/*! DACBFWMF - DAC Buffer Watermark Flag
6340 * 0b0..The DAC buffer read pointer has not reached the watermark level.
6341 * 0b1..The DAC buffer read pointer has reached the watermark level.
6342 */
6343#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
6344/*! @} */
6345
6346/*! @name C0 - DAC Control Register */
6347/*! @{ */
6348#define DAC_C0_DACBBIEN_MASK (0x1U)
6349#define DAC_C0_DACBBIEN_SHIFT (0U)
6350/*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable
6351 * 0b0..The DAC buffer read pointer bottom flag interrupt is disabled.
6352 * 0b1..The DAC buffer read pointer bottom flag interrupt is enabled.
6353 */
6354#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
6355#define DAC_C0_DACBTIEN_MASK (0x2U)
6356#define DAC_C0_DACBTIEN_SHIFT (1U)
6357/*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable
6358 * 0b0..The DAC buffer read pointer top flag interrupt is disabled.
6359 * 0b1..The DAC buffer read pointer top flag interrupt is enabled.
6360 */
6361#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
6362#define DAC_C0_DACBWIEN_MASK (0x4U)
6363#define DAC_C0_DACBWIEN_SHIFT (2U)
6364/*! DACBWIEN - DAC Buffer Watermark Interrupt Enable
6365 * 0b0..The DAC buffer watermark interrupt is disabled.
6366 * 0b1..The DAC buffer watermark interrupt is enabled.
6367 */
6368#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
6369#define DAC_C0_LPEN_MASK (0x8U)
6370#define DAC_C0_LPEN_SHIFT (3U)
6371/*! LPEN - DAC Low Power Control
6372 * 0b0..High-Power mode
6373 * 0b1..Low-Power mode
6374 */
6375#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
6376#define DAC_C0_DACSWTRG_MASK (0x10U)
6377#define DAC_C0_DACSWTRG_SHIFT (4U)
6378/*! DACSWTRG - DAC Software Trigger
6379 * 0b0..The DAC soft trigger is not valid.
6380 * 0b1..The DAC soft trigger is valid.
6381 */
6382#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
6383#define DAC_C0_DACTRGSEL_MASK (0x20U)
6384#define DAC_C0_DACTRGSEL_SHIFT (5U)
6385/*! DACTRGSEL - DAC Trigger Select
6386 * 0b0..The DAC hardware trigger is selected.
6387 * 0b1..The DAC software trigger is selected.
6388 */
6389#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
6390#define DAC_C0_DACRFS_MASK (0x40U)
6391#define DAC_C0_DACRFS_SHIFT (6U)
6392/*! DACRFS - DAC Reference Select
6393 * 0b0..The DAC selects DACREF_1 as the reference voltage.
6394 * 0b1..The DAC selects DACREF_2 as the reference voltage.
6395 */
6396#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
6397#define DAC_C0_DACEN_MASK (0x80U)
6398#define DAC_C0_DACEN_SHIFT (7U)
6399/*! DACEN - DAC Enable
6400 * 0b0..The DAC system is disabled.
6401 * 0b1..The DAC system is enabled.
6402 */
6403#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
6404/*! @} */
6405
6406/*! @name C1 - DAC Control Register 1 */
6407/*! @{ */
6408#define DAC_C1_DACBFEN_MASK (0x1U)
6409#define DAC_C1_DACBFEN_SHIFT (0U)
6410/*! DACBFEN - DAC Buffer Enable
6411 * 0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer.
6412 * 0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
6413 */
6414#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
6415#define DAC_C1_DACBFMD_MASK (0x6U)
6416#define DAC_C1_DACBFMD_SHIFT (1U)
6417/*! DACBFMD - DAC Buffer Work Mode Select
6418 * 0b00..Normal mode
6419 * 0b01..Swing mode
6420 * 0b10..One-Time Scan mode
6421 * 0b11..Reserved
6422 */
6423#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
6424#define DAC_C1_DACBFWM_MASK (0x18U)
6425#define DAC_C1_DACBFWM_SHIFT (3U)
6426/*! DACBFWM - DAC Buffer Watermark Select
6427 * 0b00..1 word
6428 * 0b01..2 words
6429 * 0b10..3 words
6430 * 0b11..4 words
6431 */
6432#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
6433#define DAC_C1_DMAEN_MASK (0x80U)
6434#define DAC_C1_DMAEN_SHIFT (7U)
6435/*! DMAEN - DMA Enable Select
6436 * 0b0..DMA is disabled.
6437 * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
6438 */
6439#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
6440/*! @} */
6441
6442/*! @name C2 - DAC Control Register 2 */
6443/*! @{ */
6444#define DAC_C2_DACBFUP_MASK (0xFU)
6445#define DAC_C2_DACBFUP_SHIFT (0U)
6446#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
6447#define DAC_C2_DACBFRP_MASK (0xF0U)
6448#define DAC_C2_DACBFRP_SHIFT (4U)
6449#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
6450/*! @} */
6451
6452
6453/*!
6454 * @}
6455 */ /* end of group DAC_Register_Masks */
6456
6457
6458/* DAC - Peripheral instance base addresses */
6459/** Peripheral DAC0 base address */
6460#define DAC0_BASE (0x400CC000u)
6461/** Peripheral DAC0 base pointer */
6462#define DAC0 ((DAC_Type *)DAC0_BASE)
6463/** Peripheral DAC1 base address */
6464#define DAC1_BASE (0x400CD000u)
6465/** Peripheral DAC1 base pointer */
6466#define DAC1 ((DAC_Type *)DAC1_BASE)
6467/** Array initializer of DAC peripheral base addresses */
6468#define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
6469/** Array initializer of DAC peripheral base pointers */
6470#define DAC_BASE_PTRS { DAC0, DAC1 }
6471/** Interrupt vectors for the DAC peripheral type */
6472#define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
6473
6474/*!
6475 * @}
6476 */ /* end of group DAC_Peripheral_Access_Layer */
6477
6478
6479/* ----------------------------------------------------------------------------
6480 -- DMA Peripheral Access Layer
6481 ---------------------------------------------------------------------------- */
6482
6483/*!
6484 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
6485 * @{
6486 */
6487
6488/** DMA - Register Layout Typedef */
6489typedef struct {
6490 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
6491 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
6492 uint8_t RESERVED_0[4];
6493 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
6494 uint8_t RESERVED_1[4];
6495 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
6496 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
6497 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
6498 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
6499 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
6500 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
6501 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
6502 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
6503 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
6504 uint8_t RESERVED_2[4];
6505 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
6506 uint8_t RESERVED_3[4];
6507 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
6508 uint8_t RESERVED_4[4];
6509 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
6510 uint8_t RESERVED_5[12];
6511 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
6512 uint8_t RESERVED_6[184];
6513 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
6514 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
6515 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
6516 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
6517 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
6518 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
6519 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
6520 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
6521 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
6522 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
6523 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
6524 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
6525 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
6526 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
6527 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
6528 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
6529 __IO uint8_t DCHPRI19; /**< Channel n Priority Register, offset: 0x110 */
6530 __IO uint8_t DCHPRI18; /**< Channel n Priority Register, offset: 0x111 */
6531 __IO uint8_t DCHPRI17; /**< Channel n Priority Register, offset: 0x112 */
6532 __IO uint8_t DCHPRI16; /**< Channel n Priority Register, offset: 0x113 */
6533 __IO uint8_t DCHPRI23; /**< Channel n Priority Register, offset: 0x114 */
6534 __IO uint8_t DCHPRI22; /**< Channel n Priority Register, offset: 0x115 */
6535 __IO uint8_t DCHPRI21; /**< Channel n Priority Register, offset: 0x116 */
6536 __IO uint8_t DCHPRI20; /**< Channel n Priority Register, offset: 0x117 */
6537 __IO uint8_t DCHPRI27; /**< Channel n Priority Register, offset: 0x118 */
6538 __IO uint8_t DCHPRI26; /**< Channel n Priority Register, offset: 0x119 */
6539 __IO uint8_t DCHPRI25; /**< Channel n Priority Register, offset: 0x11A */
6540 __IO uint8_t DCHPRI24; /**< Channel n Priority Register, offset: 0x11B */
6541 __IO uint8_t DCHPRI31; /**< Channel n Priority Register, offset: 0x11C */
6542 __IO uint8_t DCHPRI30; /**< Channel n Priority Register, offset: 0x11D */
6543 __IO uint8_t DCHPRI29; /**< Channel n Priority Register, offset: 0x11E */
6544 __IO uint8_t DCHPRI28; /**< Channel n Priority Register, offset: 0x11F */
6545 uint8_t RESERVED_7[3808];
6546 struct { /* offset: 0x1000, array step: 0x20 */
6547 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
6548 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
6549 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
6550 union { /* offset: 0x1008, array step: 0x20 */
6551 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
6552 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
6553 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
6554 };
6555 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
6556 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
6557 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
6558 union { /* offset: 0x1016, array step: 0x20 */
6559 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
6560 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
6561 };
6562 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
6563 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
6564 union { /* offset: 0x101E, array step: 0x20 */
6565 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
6566 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
6567 };
6568 } TCD[32];
6569} DMA_Type;
6570
6571/* ----------------------------------------------------------------------------
6572 -- DMA Register Masks
6573 ---------------------------------------------------------------------------- */
6574
6575/*!
6576 * @addtogroup DMA_Register_Masks DMA Register Masks
6577 * @{
6578 */
6579
6580/*! @name CR - Control Register */
6581/*! @{ */
6582#define DMA_CR_EDBG_MASK (0x2U)
6583#define DMA_CR_EDBG_SHIFT (1U)
6584/*! EDBG - Enable Debug
6585 * 0b0..When in debug mode, the DMA continues to operate.
6586 * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
6587 */
6588#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
6589#define DMA_CR_ERCA_MASK (0x4U)
6590#define DMA_CR_ERCA_SHIFT (2U)
6591/*! ERCA - Enable Round Robin Channel Arbitration
6592 * 0b0..Fixed priority arbitration is used for channel selection within each group.
6593 * 0b1..Round robin arbitration is used for channel selection within each group.
6594 */
6595#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
6596#define DMA_CR_ERGA_MASK (0x8U)
6597#define DMA_CR_ERGA_SHIFT (3U)
6598/*! ERGA - Enable Round Robin Group Arbitration
6599 * 0b0..Fixed priority arbitration is used for selection among the groups.
6600 * 0b1..Round robin arbitration is used for selection among the groups.
6601 */
6602#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
6603#define DMA_CR_HOE_MASK (0x10U)
6604#define DMA_CR_HOE_SHIFT (4U)
6605/*! HOE - Halt On Error
6606 * 0b0..Normal operation
6607 * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
6608 */
6609#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
6610#define DMA_CR_HALT_MASK (0x20U)
6611#define DMA_CR_HALT_SHIFT (5U)
6612/*! HALT - Halt DMA Operations
6613 * 0b0..Normal operation
6614 * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
6615 */
6616#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
6617#define DMA_CR_CLM_MASK (0x40U)
6618#define DMA_CR_CLM_SHIFT (6U)
6619/*! CLM - Continuous Link Mode
6620 * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
6621 * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
6622 */
6623#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
6624#define DMA_CR_EMLM_MASK (0x80U)
6625#define DMA_CR_EMLM_SHIFT (7U)
6626/*! EMLM - Enable Minor Loop Mapping
6627 * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
6628 * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
6629 */
6630#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
6631#define DMA_CR_GRP0PRI_MASK (0x100U)
6632#define DMA_CR_GRP0PRI_SHIFT (8U)
6633#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
6634#define DMA_CR_GRP1PRI_MASK (0x400U)
6635#define DMA_CR_GRP1PRI_SHIFT (10U)
6636#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
6637#define DMA_CR_ECX_MASK (0x10000U)
6638#define DMA_CR_ECX_SHIFT (16U)
6639/*! ECX - Error Cancel Transfer
6640 * 0b0..Normal operation
6641 * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
6642 */
6643#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
6644#define DMA_CR_CX_MASK (0x20000U)
6645#define DMA_CR_CX_SHIFT (17U)
6646/*! CX - Cancel Transfer
6647 * 0b0..Normal operation
6648 * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
6649 */
6650#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
6651/*! @} */
6652
6653/*! @name ES - Error Status Register */
6654/*! @{ */
6655#define DMA_ES_DBE_MASK (0x1U)
6656#define DMA_ES_DBE_SHIFT (0U)
6657/*! DBE - Destination Bus Error
6658 * 0b0..No destination bus error
6659 * 0b1..The last recorded error was a bus error on a destination write
6660 */
6661#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
6662#define DMA_ES_SBE_MASK (0x2U)
6663#define DMA_ES_SBE_SHIFT (1U)
6664/*! SBE - Source Bus Error
6665 * 0b0..No source bus error
6666 * 0b1..The last recorded error was a bus error on a source read
6667 */
6668#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
6669#define DMA_ES_SGE_MASK (0x4U)
6670#define DMA_ES_SGE_SHIFT (2U)
6671/*! SGE - Scatter/Gather Configuration Error
6672 * 0b0..No scatter/gather configuration error
6673 * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
6674 */
6675#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
6676#define DMA_ES_NCE_MASK (0x8U)
6677#define DMA_ES_NCE_SHIFT (3U)
6678/*! NCE - NBYTES/CITER Configuration Error
6679 * 0b0..No NBYTES/CITER configuration error
6680 * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
6681 */
6682#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
6683#define DMA_ES_DOE_MASK (0x10U)
6684#define DMA_ES_DOE_SHIFT (4U)
6685/*! DOE - Destination Offset Error
6686 * 0b0..No destination offset configuration error
6687 * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
6688 */
6689#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
6690#define DMA_ES_DAE_MASK (0x20U)
6691#define DMA_ES_DAE_SHIFT (5U)
6692/*! DAE - Destination Address Error
6693 * 0b0..No destination address configuration error
6694 * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
6695 */
6696#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
6697#define DMA_ES_SOE_MASK (0x40U)
6698#define DMA_ES_SOE_SHIFT (6U)
6699/*! SOE - Source Offset Error
6700 * 0b0..No source offset configuration error
6701 * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
6702 */
6703#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
6704#define DMA_ES_SAE_MASK (0x80U)
6705#define DMA_ES_SAE_SHIFT (7U)
6706/*! SAE - Source Address Error
6707 * 0b0..No source address configuration error.
6708 * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
6709 */
6710#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
6711#define DMA_ES_ERRCHN_MASK (0x1F00U)
6712#define DMA_ES_ERRCHN_SHIFT (8U)
6713#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
6714#define DMA_ES_CPE_MASK (0x4000U)
6715#define DMA_ES_CPE_SHIFT (14U)
6716/*! CPE - Channel Priority Error
6717 * 0b0..No channel priority error
6718 * 0b1..The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique.
6719 */
6720#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
6721#define DMA_ES_GPE_MASK (0x8000U)
6722#define DMA_ES_GPE_SHIFT (15U)
6723/*! GPE - Group Priority Error
6724 * 0b0..No group priority error
6725 * 0b1..The last recorded error was a configuration error among the group priorities. All group priorities are not unique.
6726 */
6727#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
6728#define DMA_ES_ECX_MASK (0x10000U)
6729#define DMA_ES_ECX_SHIFT (16U)
6730/*! ECX - Transfer Canceled
6731 * 0b0..No canceled transfers
6732 * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
6733 */
6734#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
6735#define DMA_ES_VLD_MASK (0x80000000U)
6736#define DMA_ES_VLD_SHIFT (31U)
6737/*! VLD
6738 * 0b0..No ERR bits are set.
6739 * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared.
6740 */
6741#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
6742/*! @} */
6743
6744/*! @name ERQ - Enable Request Register */
6745/*! @{ */
6746#define DMA_ERQ_ERQ0_MASK (0x1U)
6747#define DMA_ERQ_ERQ0_SHIFT (0U)
6748/*! ERQ0 - Enable DMA Request 0
6749 * 0b0..The DMA request signal for the corresponding channel is disabled
6750 * 0b1..The DMA request signal for the corresponding channel is enabled
6751 */
6752#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
6753#define DMA_ERQ_ERQ1_MASK (0x2U)
6754#define DMA_ERQ_ERQ1_SHIFT (1U)
6755/*! ERQ1 - Enable DMA Request 1
6756 * 0b0..The DMA request signal for the corresponding channel is disabled
6757 * 0b1..The DMA request signal for the corresponding channel is enabled
6758 */
6759#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
6760#define DMA_ERQ_ERQ2_MASK (0x4U)
6761#define DMA_ERQ_ERQ2_SHIFT (2U)
6762/*! ERQ2 - Enable DMA Request 2
6763 * 0b0..The DMA request signal for the corresponding channel is disabled
6764 * 0b1..The DMA request signal for the corresponding channel is enabled
6765 */
6766#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
6767#define DMA_ERQ_ERQ3_MASK (0x8U)
6768#define DMA_ERQ_ERQ3_SHIFT (3U)
6769/*! ERQ3 - Enable DMA Request 3
6770 * 0b0..The DMA request signal for the corresponding channel is disabled
6771 * 0b1..The DMA request signal for the corresponding channel is enabled
6772 */
6773#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
6774#define DMA_ERQ_ERQ4_MASK (0x10U)
6775#define DMA_ERQ_ERQ4_SHIFT (4U)
6776/*! ERQ4 - Enable DMA Request 4
6777 * 0b0..The DMA request signal for the corresponding channel is disabled
6778 * 0b1..The DMA request signal for the corresponding channel is enabled
6779 */
6780#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
6781#define DMA_ERQ_ERQ5_MASK (0x20U)
6782#define DMA_ERQ_ERQ5_SHIFT (5U)
6783/*! ERQ5 - Enable DMA Request 5
6784 * 0b0..The DMA request signal for the corresponding channel is disabled
6785 * 0b1..The DMA request signal for the corresponding channel is enabled
6786 */
6787#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
6788#define DMA_ERQ_ERQ6_MASK (0x40U)
6789#define DMA_ERQ_ERQ6_SHIFT (6U)
6790/*! ERQ6 - Enable DMA Request 6
6791 * 0b0..The DMA request signal for the corresponding channel is disabled
6792 * 0b1..The DMA request signal for the corresponding channel is enabled
6793 */
6794#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
6795#define DMA_ERQ_ERQ7_MASK (0x80U)
6796#define DMA_ERQ_ERQ7_SHIFT (7U)
6797/*! ERQ7 - Enable DMA Request 7
6798 * 0b0..The DMA request signal for the corresponding channel is disabled
6799 * 0b1..The DMA request signal for the corresponding channel is enabled
6800 */
6801#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
6802#define DMA_ERQ_ERQ8_MASK (0x100U)
6803#define DMA_ERQ_ERQ8_SHIFT (8U)
6804/*! ERQ8 - Enable DMA Request 8
6805 * 0b0..The DMA request signal for the corresponding channel is disabled
6806 * 0b1..The DMA request signal for the corresponding channel is enabled
6807 */
6808#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
6809#define DMA_ERQ_ERQ9_MASK (0x200U)
6810#define DMA_ERQ_ERQ9_SHIFT (9U)
6811/*! ERQ9 - Enable DMA Request 9
6812 * 0b0..The DMA request signal for the corresponding channel is disabled
6813 * 0b1..The DMA request signal for the corresponding channel is enabled
6814 */
6815#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
6816#define DMA_ERQ_ERQ10_MASK (0x400U)
6817#define DMA_ERQ_ERQ10_SHIFT (10U)
6818/*! ERQ10 - Enable DMA Request 10
6819 * 0b0..The DMA request signal for the corresponding channel is disabled
6820 * 0b1..The DMA request signal for the corresponding channel is enabled
6821 */
6822#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
6823#define DMA_ERQ_ERQ11_MASK (0x800U)
6824#define DMA_ERQ_ERQ11_SHIFT (11U)
6825/*! ERQ11 - Enable DMA Request 11
6826 * 0b0..The DMA request signal for the corresponding channel is disabled
6827 * 0b1..The DMA request signal for the corresponding channel is enabled
6828 */
6829#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
6830#define DMA_ERQ_ERQ12_MASK (0x1000U)
6831#define DMA_ERQ_ERQ12_SHIFT (12U)
6832/*! ERQ12 - Enable DMA Request 12
6833 * 0b0..The DMA request signal for the corresponding channel is disabled
6834 * 0b1..The DMA request signal for the corresponding channel is enabled
6835 */
6836#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
6837#define DMA_ERQ_ERQ13_MASK (0x2000U)
6838#define DMA_ERQ_ERQ13_SHIFT (13U)
6839/*! ERQ13 - Enable DMA Request 13
6840 * 0b0..The DMA request signal for the corresponding channel is disabled
6841 * 0b1..The DMA request signal for the corresponding channel is enabled
6842 */
6843#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
6844#define DMA_ERQ_ERQ14_MASK (0x4000U)
6845#define DMA_ERQ_ERQ14_SHIFT (14U)
6846/*! ERQ14 - Enable DMA Request 14
6847 * 0b0..The DMA request signal for the corresponding channel is disabled
6848 * 0b1..The DMA request signal for the corresponding channel is enabled
6849 */
6850#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
6851#define DMA_ERQ_ERQ15_MASK (0x8000U)
6852#define DMA_ERQ_ERQ15_SHIFT (15U)
6853/*! ERQ15 - Enable DMA Request 15
6854 * 0b0..The DMA request signal for the corresponding channel is disabled
6855 * 0b1..The DMA request signal for the corresponding channel is enabled
6856 */
6857#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
6858#define DMA_ERQ_ERQ16_MASK (0x10000U)
6859#define DMA_ERQ_ERQ16_SHIFT (16U)
6860/*! ERQ16 - Enable DMA Request 16
6861 * 0b0..The DMA request signal for the corresponding channel is disabled
6862 * 0b1..The DMA request signal for the corresponding channel is enabled
6863 */
6864#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
6865#define DMA_ERQ_ERQ17_MASK (0x20000U)
6866#define DMA_ERQ_ERQ17_SHIFT (17U)
6867/*! ERQ17 - Enable DMA Request 17
6868 * 0b0..The DMA request signal for the corresponding channel is disabled
6869 * 0b1..The DMA request signal for the corresponding channel is enabled
6870 */
6871#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
6872#define DMA_ERQ_ERQ18_MASK (0x40000U)
6873#define DMA_ERQ_ERQ18_SHIFT (18U)
6874/*! ERQ18 - Enable DMA Request 18
6875 * 0b0..The DMA request signal for the corresponding channel is disabled
6876 * 0b1..The DMA request signal for the corresponding channel is enabled
6877 */
6878#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
6879#define DMA_ERQ_ERQ19_MASK (0x80000U)
6880#define DMA_ERQ_ERQ19_SHIFT (19U)
6881/*! ERQ19 - Enable DMA Request 19
6882 * 0b0..The DMA request signal for the corresponding channel is disabled
6883 * 0b1..The DMA request signal for the corresponding channel is enabled
6884 */
6885#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
6886#define DMA_ERQ_ERQ20_MASK (0x100000U)
6887#define DMA_ERQ_ERQ20_SHIFT (20U)
6888/*! ERQ20 - Enable DMA Request 20
6889 * 0b0..The DMA request signal for the corresponding channel is disabled
6890 * 0b1..The DMA request signal for the corresponding channel is enabled
6891 */
6892#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
6893#define DMA_ERQ_ERQ21_MASK (0x200000U)
6894#define DMA_ERQ_ERQ21_SHIFT (21U)
6895/*! ERQ21 - Enable DMA Request 21
6896 * 0b0..The DMA request signal for the corresponding channel is disabled
6897 * 0b1..The DMA request signal for the corresponding channel is enabled
6898 */
6899#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
6900#define DMA_ERQ_ERQ22_MASK (0x400000U)
6901#define DMA_ERQ_ERQ22_SHIFT (22U)
6902/*! ERQ22 - Enable DMA Request 22
6903 * 0b0..The DMA request signal for the corresponding channel is disabled
6904 * 0b1..The DMA request signal for the corresponding channel is enabled
6905 */
6906#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
6907#define DMA_ERQ_ERQ23_MASK (0x800000U)
6908#define DMA_ERQ_ERQ23_SHIFT (23U)
6909/*! ERQ23 - Enable DMA Request 23
6910 * 0b0..The DMA request signal for the corresponding channel is disabled
6911 * 0b1..The DMA request signal for the corresponding channel is enabled
6912 */
6913#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
6914#define DMA_ERQ_ERQ24_MASK (0x1000000U)
6915#define DMA_ERQ_ERQ24_SHIFT (24U)
6916/*! ERQ24 - Enable DMA Request 24
6917 * 0b0..The DMA request signal for the corresponding channel is disabled
6918 * 0b1..The DMA request signal for the corresponding channel is enabled
6919 */
6920#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
6921#define DMA_ERQ_ERQ25_MASK (0x2000000U)
6922#define DMA_ERQ_ERQ25_SHIFT (25U)
6923/*! ERQ25 - Enable DMA Request 25
6924 * 0b0..The DMA request signal for the corresponding channel is disabled
6925 * 0b1..The DMA request signal for the corresponding channel is enabled
6926 */
6927#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
6928#define DMA_ERQ_ERQ26_MASK (0x4000000U)
6929#define DMA_ERQ_ERQ26_SHIFT (26U)
6930/*! ERQ26 - Enable DMA Request 26
6931 * 0b0..The DMA request signal for the corresponding channel is disabled
6932 * 0b1..The DMA request signal for the corresponding channel is enabled
6933 */
6934#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
6935#define DMA_ERQ_ERQ27_MASK (0x8000000U)
6936#define DMA_ERQ_ERQ27_SHIFT (27U)
6937/*! ERQ27 - Enable DMA Request 27
6938 * 0b0..The DMA request signal for the corresponding channel is disabled
6939 * 0b1..The DMA request signal for the corresponding channel is enabled
6940 */
6941#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
6942#define DMA_ERQ_ERQ28_MASK (0x10000000U)
6943#define DMA_ERQ_ERQ28_SHIFT (28U)
6944/*! ERQ28 - Enable DMA Request 28
6945 * 0b0..The DMA request signal for the corresponding channel is disabled
6946 * 0b1..The DMA request signal for the corresponding channel is enabled
6947 */
6948#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
6949#define DMA_ERQ_ERQ29_MASK (0x20000000U)
6950#define DMA_ERQ_ERQ29_SHIFT (29U)
6951/*! ERQ29 - Enable DMA Request 29
6952 * 0b0..The DMA request signal for the corresponding channel is disabled
6953 * 0b1..The DMA request signal for the corresponding channel is enabled
6954 */
6955#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
6956#define DMA_ERQ_ERQ30_MASK (0x40000000U)
6957#define DMA_ERQ_ERQ30_SHIFT (30U)
6958/*! ERQ30 - Enable DMA Request 30
6959 * 0b0..The DMA request signal for the corresponding channel is disabled
6960 * 0b1..The DMA request signal for the corresponding channel is enabled
6961 */
6962#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
6963#define DMA_ERQ_ERQ31_MASK (0x80000000U)
6964#define DMA_ERQ_ERQ31_SHIFT (31U)
6965/*! ERQ31 - Enable DMA Request 31
6966 * 0b0..The DMA request signal for the corresponding channel is disabled
6967 * 0b1..The DMA request signal for the corresponding channel is enabled
6968 */
6969#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
6970/*! @} */
6971
6972/*! @name EEI - Enable Error Interrupt Register */
6973/*! @{ */
6974#define DMA_EEI_EEI0_MASK (0x1U)
6975#define DMA_EEI_EEI0_SHIFT (0U)
6976/*! EEI0 - Enable Error Interrupt 0
6977 * 0b0..The error signal for corresponding channel does not generate an error interrupt
6978 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
6979 */
6980#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
6981#define DMA_EEI_EEI1_MASK (0x2U)
6982#define DMA_EEI_EEI1_SHIFT (1U)
6983/*! EEI1 - Enable Error Interrupt 1
6984 * 0b0..The error signal for corresponding channel does not generate an error interrupt
6985 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
6986 */
6987#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
6988#define DMA_EEI_EEI2_MASK (0x4U)
6989#define DMA_EEI_EEI2_SHIFT (2U)
6990/*! EEI2 - Enable Error Interrupt 2
6991 * 0b0..The error signal for corresponding channel does not generate an error interrupt
6992 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
6993 */
6994#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
6995#define DMA_EEI_EEI3_MASK (0x8U)
6996#define DMA_EEI_EEI3_SHIFT (3U)
6997/*! EEI3 - Enable Error Interrupt 3
6998 * 0b0..The error signal for corresponding channel does not generate an error interrupt
6999 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7000 */
7001#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
7002#define DMA_EEI_EEI4_MASK (0x10U)
7003#define DMA_EEI_EEI4_SHIFT (4U)
7004/*! EEI4 - Enable Error Interrupt 4
7005 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7006 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7007 */
7008#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
7009#define DMA_EEI_EEI5_MASK (0x20U)
7010#define DMA_EEI_EEI5_SHIFT (5U)
7011/*! EEI5 - Enable Error Interrupt 5
7012 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7013 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7014 */
7015#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
7016#define DMA_EEI_EEI6_MASK (0x40U)
7017#define DMA_EEI_EEI6_SHIFT (6U)
7018/*! EEI6 - Enable Error Interrupt 6
7019 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7020 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7021 */
7022#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
7023#define DMA_EEI_EEI7_MASK (0x80U)
7024#define DMA_EEI_EEI7_SHIFT (7U)
7025/*! EEI7 - Enable Error Interrupt 7
7026 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7027 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7028 */
7029#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
7030#define DMA_EEI_EEI8_MASK (0x100U)
7031#define DMA_EEI_EEI8_SHIFT (8U)
7032/*! EEI8 - Enable Error Interrupt 8
7033 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7034 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7035 */
7036#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
7037#define DMA_EEI_EEI9_MASK (0x200U)
7038#define DMA_EEI_EEI9_SHIFT (9U)
7039/*! EEI9 - Enable Error Interrupt 9
7040 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7041 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7042 */
7043#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
7044#define DMA_EEI_EEI10_MASK (0x400U)
7045#define DMA_EEI_EEI10_SHIFT (10U)
7046/*! EEI10 - Enable Error Interrupt 10
7047 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7048 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7049 */
7050#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
7051#define DMA_EEI_EEI11_MASK (0x800U)
7052#define DMA_EEI_EEI11_SHIFT (11U)
7053/*! EEI11 - Enable Error Interrupt 11
7054 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7055 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7056 */
7057#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
7058#define DMA_EEI_EEI12_MASK (0x1000U)
7059#define DMA_EEI_EEI12_SHIFT (12U)
7060/*! EEI12 - Enable Error Interrupt 12
7061 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7062 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7063 */
7064#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
7065#define DMA_EEI_EEI13_MASK (0x2000U)
7066#define DMA_EEI_EEI13_SHIFT (13U)
7067/*! EEI13 - Enable Error Interrupt 13
7068 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7069 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7070 */
7071#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
7072#define DMA_EEI_EEI14_MASK (0x4000U)
7073#define DMA_EEI_EEI14_SHIFT (14U)
7074/*! EEI14 - Enable Error Interrupt 14
7075 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7076 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7077 */
7078#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
7079#define DMA_EEI_EEI15_MASK (0x8000U)
7080#define DMA_EEI_EEI15_SHIFT (15U)
7081/*! EEI15 - Enable Error Interrupt 15
7082 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7083 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7084 */
7085#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
7086#define DMA_EEI_EEI16_MASK (0x10000U)
7087#define DMA_EEI_EEI16_SHIFT (16U)
7088/*! EEI16 - Enable Error Interrupt 16
7089 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7090 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7091 */
7092#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
7093#define DMA_EEI_EEI17_MASK (0x20000U)
7094#define DMA_EEI_EEI17_SHIFT (17U)
7095/*! EEI17 - Enable Error Interrupt 17
7096 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7097 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7098 */
7099#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
7100#define DMA_EEI_EEI18_MASK (0x40000U)
7101#define DMA_EEI_EEI18_SHIFT (18U)
7102/*! EEI18 - Enable Error Interrupt 18
7103 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7104 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7105 */
7106#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
7107#define DMA_EEI_EEI19_MASK (0x80000U)
7108#define DMA_EEI_EEI19_SHIFT (19U)
7109/*! EEI19 - Enable Error Interrupt 19
7110 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7111 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7112 */
7113#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
7114#define DMA_EEI_EEI20_MASK (0x100000U)
7115#define DMA_EEI_EEI20_SHIFT (20U)
7116/*! EEI20 - Enable Error Interrupt 20
7117 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7118 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7119 */
7120#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
7121#define DMA_EEI_EEI21_MASK (0x200000U)
7122#define DMA_EEI_EEI21_SHIFT (21U)
7123/*! EEI21 - Enable Error Interrupt 21
7124 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7125 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7126 */
7127#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
7128#define DMA_EEI_EEI22_MASK (0x400000U)
7129#define DMA_EEI_EEI22_SHIFT (22U)
7130/*! EEI22 - Enable Error Interrupt 22
7131 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7132 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7133 */
7134#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
7135#define DMA_EEI_EEI23_MASK (0x800000U)
7136#define DMA_EEI_EEI23_SHIFT (23U)
7137/*! EEI23 - Enable Error Interrupt 23
7138 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7139 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7140 */
7141#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
7142#define DMA_EEI_EEI24_MASK (0x1000000U)
7143#define DMA_EEI_EEI24_SHIFT (24U)
7144/*! EEI24 - Enable Error Interrupt 24
7145 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7146 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7147 */
7148#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
7149#define DMA_EEI_EEI25_MASK (0x2000000U)
7150#define DMA_EEI_EEI25_SHIFT (25U)
7151/*! EEI25 - Enable Error Interrupt 25
7152 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7153 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7154 */
7155#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
7156#define DMA_EEI_EEI26_MASK (0x4000000U)
7157#define DMA_EEI_EEI26_SHIFT (26U)
7158/*! EEI26 - Enable Error Interrupt 26
7159 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7160 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7161 */
7162#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
7163#define DMA_EEI_EEI27_MASK (0x8000000U)
7164#define DMA_EEI_EEI27_SHIFT (27U)
7165/*! EEI27 - Enable Error Interrupt 27
7166 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7167 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7168 */
7169#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
7170#define DMA_EEI_EEI28_MASK (0x10000000U)
7171#define DMA_EEI_EEI28_SHIFT (28U)
7172/*! EEI28 - Enable Error Interrupt 28
7173 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7174 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7175 */
7176#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
7177#define DMA_EEI_EEI29_MASK (0x20000000U)
7178#define DMA_EEI_EEI29_SHIFT (29U)
7179/*! EEI29 - Enable Error Interrupt 29
7180 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7181 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7182 */
7183#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
7184#define DMA_EEI_EEI30_MASK (0x40000000U)
7185#define DMA_EEI_EEI30_SHIFT (30U)
7186/*! EEI30 - Enable Error Interrupt 30
7187 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7188 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7189 */
7190#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
7191#define DMA_EEI_EEI31_MASK (0x80000000U)
7192#define DMA_EEI_EEI31_SHIFT (31U)
7193/*! EEI31 - Enable Error Interrupt 31
7194 * 0b0..The error signal for corresponding channel does not generate an error interrupt
7195 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
7196 */
7197#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
7198/*! @} */
7199
7200/*! @name CEEI - Clear Enable Error Interrupt Register */
7201/*! @{ */
7202#define DMA_CEEI_CEEI_MASK (0x1FU)
7203#define DMA_CEEI_CEEI_SHIFT (0U)
7204#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
7205#define DMA_CEEI_CAEE_MASK (0x40U)
7206#define DMA_CEEI_CAEE_SHIFT (6U)
7207/*! CAEE - Clear All Enable Error Interrupts
7208 * 0b0..Clear only the EEI bit specified in the CEEI field
7209 * 0b1..Clear all bits in EEI
7210 */
7211#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
7212#define DMA_CEEI_NOP_MASK (0x80U)
7213#define DMA_CEEI_NOP_SHIFT (7U)
7214/*! NOP - No Op enable
7215 * 0b0..Normal operation
7216 * 0b1..No operation, ignore the other bits in this register
7217 */
7218#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
7219/*! @} */
7220
7221/*! @name SEEI - Set Enable Error Interrupt Register */
7222/*! @{ */
7223#define DMA_SEEI_SEEI_MASK (0x1FU)
7224#define DMA_SEEI_SEEI_SHIFT (0U)
7225#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
7226#define DMA_SEEI_SAEE_MASK (0x40U)
7227#define DMA_SEEI_SAEE_SHIFT (6U)
7228/*! SAEE - Sets All Enable Error Interrupts
7229 * 0b0..Set only the EEI bit specified in the SEEI field.
7230 * 0b1..Sets all bits in EEI
7231 */
7232#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
7233#define DMA_SEEI_NOP_MASK (0x80U)
7234#define DMA_SEEI_NOP_SHIFT (7U)
7235/*! NOP - No Op enable
7236 * 0b0..Normal operation
7237 * 0b1..No operation, ignore the other bits in this register
7238 */
7239#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
7240/*! @} */
7241
7242/*! @name CERQ - Clear Enable Request Register */
7243/*! @{ */
7244#define DMA_CERQ_CERQ_MASK (0x1FU)
7245#define DMA_CERQ_CERQ_SHIFT (0U)
7246#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
7247#define DMA_CERQ_CAER_MASK (0x40U)
7248#define DMA_CERQ_CAER_SHIFT (6U)
7249/*! CAER - Clear All Enable Requests
7250 * 0b0..Clear only the ERQ bit specified in the CERQ field
7251 * 0b1..Clear all bits in ERQ
7252 */
7253#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
7254#define DMA_CERQ_NOP_MASK (0x80U)
7255#define DMA_CERQ_NOP_SHIFT (7U)
7256/*! NOP - No Op enable
7257 * 0b0..Normal operation
7258 * 0b1..No operation, ignore the other bits in this register
7259 */
7260#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
7261/*! @} */
7262
7263/*! @name SERQ - Set Enable Request Register */
7264/*! @{ */
7265#define DMA_SERQ_SERQ_MASK (0x1FU)
7266#define DMA_SERQ_SERQ_SHIFT (0U)
7267#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
7268#define DMA_SERQ_SAER_MASK (0x40U)
7269#define DMA_SERQ_SAER_SHIFT (6U)
7270/*! SAER - Set All Enable Requests
7271 * 0b0..Set only the ERQ bit specified in the SERQ field
7272 * 0b1..Set all bits in ERQ
7273 */
7274#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
7275#define DMA_SERQ_NOP_MASK (0x80U)
7276#define DMA_SERQ_NOP_SHIFT (7U)
7277/*! NOP - No Op enable
7278 * 0b0..Normal operation
7279 * 0b1..No operation, ignore the other bits in this register
7280 */
7281#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
7282/*! @} */
7283
7284/*! @name CDNE - Clear DONE Status Bit Register */
7285/*! @{ */
7286#define DMA_CDNE_CDNE_MASK (0x1FU)
7287#define DMA_CDNE_CDNE_SHIFT (0U)
7288#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
7289#define DMA_CDNE_CADN_MASK (0x40U)
7290#define DMA_CDNE_CADN_SHIFT (6U)
7291/*! CADN - Clears All DONE Bits
7292 * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
7293 * 0b1..Clears all bits in TCDn_CSR[DONE]
7294 */
7295#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
7296#define DMA_CDNE_NOP_MASK (0x80U)
7297#define DMA_CDNE_NOP_SHIFT (7U)
7298/*! NOP - No Op enable
7299 * 0b0..Normal operation
7300 * 0b1..No operation, ignore the other bits in this register
7301 */
7302#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
7303/*! @} */
7304
7305/*! @name SSRT - Set START Bit Register */
7306/*! @{ */
7307#define DMA_SSRT_SSRT_MASK (0x1FU)
7308#define DMA_SSRT_SSRT_SHIFT (0U)
7309#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
7310#define DMA_SSRT_SAST_MASK (0x40U)
7311#define DMA_SSRT_SAST_SHIFT (6U)
7312/*! SAST - Set All START Bits (activates all channels)
7313 * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
7314 * 0b1..Set all bits in TCDn_CSR[START]
7315 */
7316#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
7317#define DMA_SSRT_NOP_MASK (0x80U)
7318#define DMA_SSRT_NOP_SHIFT (7U)
7319/*! NOP - No Op enable
7320 * 0b0..Normal operation
7321 * 0b1..No operation, ignore the other bits in this register
7322 */
7323#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
7324/*! @} */
7325
7326/*! @name CERR - Clear Error Register */
7327/*! @{ */
7328#define DMA_CERR_CERR_MASK (0x1FU)
7329#define DMA_CERR_CERR_SHIFT (0U)
7330#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
7331#define DMA_CERR_CAEI_MASK (0x40U)
7332#define DMA_CERR_CAEI_SHIFT (6U)
7333/*! CAEI - Clear All Error Indicators
7334 * 0b0..Clear only the ERR bit specified in the CERR field
7335 * 0b1..Clear all bits in ERR
7336 */
7337#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
7338#define DMA_CERR_NOP_MASK (0x80U)
7339#define DMA_CERR_NOP_SHIFT (7U)
7340/*! NOP - No Op enable
7341 * 0b0..Normal operation
7342 * 0b1..No operation, ignore the other bits in this register
7343 */
7344#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
7345/*! @} */
7346
7347/*! @name CINT - Clear Interrupt Request Register */
7348/*! @{ */
7349#define DMA_CINT_CINT_MASK (0x1FU)
7350#define DMA_CINT_CINT_SHIFT (0U)
7351#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
7352#define DMA_CINT_CAIR_MASK (0x40U)
7353#define DMA_CINT_CAIR_SHIFT (6U)
7354/*! CAIR - Clear All Interrupt Requests
7355 * 0b0..Clear only the INT bit specified in the CINT field
7356 * 0b1..Clear all bits in INT
7357 */
7358#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
7359#define DMA_CINT_NOP_MASK (0x80U)
7360#define DMA_CINT_NOP_SHIFT (7U)
7361/*! NOP - No Op enable
7362 * 0b0..Normal operation
7363 * 0b1..No operation, ignore the other bits in this register
7364 */
7365#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
7366/*! @} */
7367
7368/*! @name INT - Interrupt Request Register */
7369/*! @{ */
7370#define DMA_INT_INT0_MASK (0x1U)
7371#define DMA_INT_INT0_SHIFT (0U)
7372/*! INT0 - Interrupt Request 0
7373 * 0b0..The interrupt request for corresponding channel is cleared
7374 * 0b1..The interrupt request for corresponding channel is active
7375 */
7376#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
7377#define DMA_INT_INT1_MASK (0x2U)
7378#define DMA_INT_INT1_SHIFT (1U)
7379/*! INT1 - Interrupt Request 1
7380 * 0b0..The interrupt request for corresponding channel is cleared
7381 * 0b1..The interrupt request for corresponding channel is active
7382 */
7383#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
7384#define DMA_INT_INT2_MASK (0x4U)
7385#define DMA_INT_INT2_SHIFT (2U)
7386/*! INT2 - Interrupt Request 2
7387 * 0b0..The interrupt request for corresponding channel is cleared
7388 * 0b1..The interrupt request for corresponding channel is active
7389 */
7390#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
7391#define DMA_INT_INT3_MASK (0x8U)
7392#define DMA_INT_INT3_SHIFT (3U)
7393/*! INT3 - Interrupt Request 3
7394 * 0b0..The interrupt request for corresponding channel is cleared
7395 * 0b1..The interrupt request for corresponding channel is active
7396 */
7397#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
7398#define DMA_INT_INT4_MASK (0x10U)
7399#define DMA_INT_INT4_SHIFT (4U)
7400/*! INT4 - Interrupt Request 4
7401 * 0b0..The interrupt request for corresponding channel is cleared
7402 * 0b1..The interrupt request for corresponding channel is active
7403 */
7404#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
7405#define DMA_INT_INT5_MASK (0x20U)
7406#define DMA_INT_INT5_SHIFT (5U)
7407/*! INT5 - Interrupt Request 5
7408 * 0b0..The interrupt request for corresponding channel is cleared
7409 * 0b1..The interrupt request for corresponding channel is active
7410 */
7411#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
7412#define DMA_INT_INT6_MASK (0x40U)
7413#define DMA_INT_INT6_SHIFT (6U)
7414/*! INT6 - Interrupt Request 6
7415 * 0b0..The interrupt request for corresponding channel is cleared
7416 * 0b1..The interrupt request for corresponding channel is active
7417 */
7418#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
7419#define DMA_INT_INT7_MASK (0x80U)
7420#define DMA_INT_INT7_SHIFT (7U)
7421/*! INT7 - Interrupt Request 7
7422 * 0b0..The interrupt request for corresponding channel is cleared
7423 * 0b1..The interrupt request for corresponding channel is active
7424 */
7425#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
7426#define DMA_INT_INT8_MASK (0x100U)
7427#define DMA_INT_INT8_SHIFT (8U)
7428/*! INT8 - Interrupt Request 8
7429 * 0b0..The interrupt request for corresponding channel is cleared
7430 * 0b1..The interrupt request for corresponding channel is active
7431 */
7432#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
7433#define DMA_INT_INT9_MASK (0x200U)
7434#define DMA_INT_INT9_SHIFT (9U)
7435/*! INT9 - Interrupt Request 9
7436 * 0b0..The interrupt request for corresponding channel is cleared
7437 * 0b1..The interrupt request for corresponding channel is active
7438 */
7439#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
7440#define DMA_INT_INT10_MASK (0x400U)
7441#define DMA_INT_INT10_SHIFT (10U)
7442/*! INT10 - Interrupt Request 10
7443 * 0b0..The interrupt request for corresponding channel is cleared
7444 * 0b1..The interrupt request for corresponding channel is active
7445 */
7446#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
7447#define DMA_INT_INT11_MASK (0x800U)
7448#define DMA_INT_INT11_SHIFT (11U)
7449/*! INT11 - Interrupt Request 11
7450 * 0b0..The interrupt request for corresponding channel is cleared
7451 * 0b1..The interrupt request for corresponding channel is active
7452 */
7453#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
7454#define DMA_INT_INT12_MASK (0x1000U)
7455#define DMA_INT_INT12_SHIFT (12U)
7456/*! INT12 - Interrupt Request 12
7457 * 0b0..The interrupt request for corresponding channel is cleared
7458 * 0b1..The interrupt request for corresponding channel is active
7459 */
7460#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
7461#define DMA_INT_INT13_MASK (0x2000U)
7462#define DMA_INT_INT13_SHIFT (13U)
7463/*! INT13 - Interrupt Request 13
7464 * 0b0..The interrupt request for corresponding channel is cleared
7465 * 0b1..The interrupt request for corresponding channel is active
7466 */
7467#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
7468#define DMA_INT_INT14_MASK (0x4000U)
7469#define DMA_INT_INT14_SHIFT (14U)
7470/*! INT14 - Interrupt Request 14
7471 * 0b0..The interrupt request for corresponding channel is cleared
7472 * 0b1..The interrupt request for corresponding channel is active
7473 */
7474#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
7475#define DMA_INT_INT15_MASK (0x8000U)
7476#define DMA_INT_INT15_SHIFT (15U)
7477/*! INT15 - Interrupt Request 15
7478 * 0b0..The interrupt request for corresponding channel is cleared
7479 * 0b1..The interrupt request for corresponding channel is active
7480 */
7481#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
7482#define DMA_INT_INT16_MASK (0x10000U)
7483#define DMA_INT_INT16_SHIFT (16U)
7484/*! INT16 - Interrupt Request 16
7485 * 0b0..The interrupt request for corresponding channel is cleared
7486 * 0b1..The interrupt request for corresponding channel is active
7487 */
7488#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
7489#define DMA_INT_INT17_MASK (0x20000U)
7490#define DMA_INT_INT17_SHIFT (17U)
7491/*! INT17 - Interrupt Request 17
7492 * 0b0..The interrupt request for corresponding channel is cleared
7493 * 0b1..The interrupt request for corresponding channel is active
7494 */
7495#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
7496#define DMA_INT_INT18_MASK (0x40000U)
7497#define DMA_INT_INT18_SHIFT (18U)
7498/*! INT18 - Interrupt Request 18
7499 * 0b0..The interrupt request for corresponding channel is cleared
7500 * 0b1..The interrupt request for corresponding channel is active
7501 */
7502#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
7503#define DMA_INT_INT19_MASK (0x80000U)
7504#define DMA_INT_INT19_SHIFT (19U)
7505/*! INT19 - Interrupt Request 19
7506 * 0b0..The interrupt request for corresponding channel is cleared
7507 * 0b1..The interrupt request for corresponding channel is active
7508 */
7509#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
7510#define DMA_INT_INT20_MASK (0x100000U)
7511#define DMA_INT_INT20_SHIFT (20U)
7512/*! INT20 - Interrupt Request 20
7513 * 0b0..The interrupt request for corresponding channel is cleared
7514 * 0b1..The interrupt request for corresponding channel is active
7515 */
7516#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
7517#define DMA_INT_INT21_MASK (0x200000U)
7518#define DMA_INT_INT21_SHIFT (21U)
7519/*! INT21 - Interrupt Request 21
7520 * 0b0..The interrupt request for corresponding channel is cleared
7521 * 0b1..The interrupt request for corresponding channel is active
7522 */
7523#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
7524#define DMA_INT_INT22_MASK (0x400000U)
7525#define DMA_INT_INT22_SHIFT (22U)
7526/*! INT22 - Interrupt Request 22
7527 * 0b0..The interrupt request for corresponding channel is cleared
7528 * 0b1..The interrupt request for corresponding channel is active
7529 */
7530#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
7531#define DMA_INT_INT23_MASK (0x800000U)
7532#define DMA_INT_INT23_SHIFT (23U)
7533/*! INT23 - Interrupt Request 23
7534 * 0b0..The interrupt request for corresponding channel is cleared
7535 * 0b1..The interrupt request for corresponding channel is active
7536 */
7537#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
7538#define DMA_INT_INT24_MASK (0x1000000U)
7539#define DMA_INT_INT24_SHIFT (24U)
7540/*! INT24 - Interrupt Request 24
7541 * 0b0..The interrupt request for corresponding channel is cleared
7542 * 0b1..The interrupt request for corresponding channel is active
7543 */
7544#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
7545#define DMA_INT_INT25_MASK (0x2000000U)
7546#define DMA_INT_INT25_SHIFT (25U)
7547/*! INT25 - Interrupt Request 25
7548 * 0b0..The interrupt request for corresponding channel is cleared
7549 * 0b1..The interrupt request for corresponding channel is active
7550 */
7551#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
7552#define DMA_INT_INT26_MASK (0x4000000U)
7553#define DMA_INT_INT26_SHIFT (26U)
7554/*! INT26 - Interrupt Request 26
7555 * 0b0..The interrupt request for corresponding channel is cleared
7556 * 0b1..The interrupt request for corresponding channel is active
7557 */
7558#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
7559#define DMA_INT_INT27_MASK (0x8000000U)
7560#define DMA_INT_INT27_SHIFT (27U)
7561/*! INT27 - Interrupt Request 27
7562 * 0b0..The interrupt request for corresponding channel is cleared
7563 * 0b1..The interrupt request for corresponding channel is active
7564 */
7565#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
7566#define DMA_INT_INT28_MASK (0x10000000U)
7567#define DMA_INT_INT28_SHIFT (28U)
7568/*! INT28 - Interrupt Request 28
7569 * 0b0..The interrupt request for corresponding channel is cleared
7570 * 0b1..The interrupt request for corresponding channel is active
7571 */
7572#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
7573#define DMA_INT_INT29_MASK (0x20000000U)
7574#define DMA_INT_INT29_SHIFT (29U)
7575/*! INT29 - Interrupt Request 29
7576 * 0b0..The interrupt request for corresponding channel is cleared
7577 * 0b1..The interrupt request for corresponding channel is active
7578 */
7579#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
7580#define DMA_INT_INT30_MASK (0x40000000U)
7581#define DMA_INT_INT30_SHIFT (30U)
7582/*! INT30 - Interrupt Request 30
7583 * 0b0..The interrupt request for corresponding channel is cleared
7584 * 0b1..The interrupt request for corresponding channel is active
7585 */
7586#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
7587#define DMA_INT_INT31_MASK (0x80000000U)
7588#define DMA_INT_INT31_SHIFT (31U)
7589/*! INT31 - Interrupt Request 31
7590 * 0b0..The interrupt request for corresponding channel is cleared
7591 * 0b1..The interrupt request for corresponding channel is active
7592 */
7593#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
7594/*! @} */
7595
7596/*! @name ERR - Error Register */
7597/*! @{ */
7598#define DMA_ERR_ERR0_MASK (0x1U)
7599#define DMA_ERR_ERR0_SHIFT (0U)
7600/*! ERR0 - Error In Channel 0
7601 * 0b0..An error in this channel has not occurred
7602 * 0b1..An error in this channel has occurred
7603 */
7604#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
7605#define DMA_ERR_ERR1_MASK (0x2U)
7606#define DMA_ERR_ERR1_SHIFT (1U)
7607/*! ERR1 - Error In Channel 1
7608 * 0b0..An error in this channel has not occurred
7609 * 0b1..An error in this channel has occurred
7610 */
7611#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
7612#define DMA_ERR_ERR2_MASK (0x4U)
7613#define DMA_ERR_ERR2_SHIFT (2U)
7614/*! ERR2 - Error In Channel 2
7615 * 0b0..An error in this channel has not occurred
7616 * 0b1..An error in this channel has occurred
7617 */
7618#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
7619#define DMA_ERR_ERR3_MASK (0x8U)
7620#define DMA_ERR_ERR3_SHIFT (3U)
7621/*! ERR3 - Error In Channel 3
7622 * 0b0..An error in this channel has not occurred
7623 * 0b1..An error in this channel has occurred
7624 */
7625#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
7626#define DMA_ERR_ERR4_MASK (0x10U)
7627#define DMA_ERR_ERR4_SHIFT (4U)
7628/*! ERR4 - Error In Channel 4
7629 * 0b0..An error in this channel has not occurred
7630 * 0b1..An error in this channel has occurred
7631 */
7632#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
7633#define DMA_ERR_ERR5_MASK (0x20U)
7634#define DMA_ERR_ERR5_SHIFT (5U)
7635/*! ERR5 - Error In Channel 5
7636 * 0b0..An error in this channel has not occurred
7637 * 0b1..An error in this channel has occurred
7638 */
7639#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
7640#define DMA_ERR_ERR6_MASK (0x40U)
7641#define DMA_ERR_ERR6_SHIFT (6U)
7642/*! ERR6 - Error In Channel 6
7643 * 0b0..An error in this channel has not occurred
7644 * 0b1..An error in this channel has occurred
7645 */
7646#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
7647#define DMA_ERR_ERR7_MASK (0x80U)
7648#define DMA_ERR_ERR7_SHIFT (7U)
7649/*! ERR7 - Error In Channel 7
7650 * 0b0..An error in this channel has not occurred
7651 * 0b1..An error in this channel has occurred
7652 */
7653#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
7654#define DMA_ERR_ERR8_MASK (0x100U)
7655#define DMA_ERR_ERR8_SHIFT (8U)
7656/*! ERR8 - Error In Channel 8
7657 * 0b0..An error in this channel has not occurred
7658 * 0b1..An error in this channel has occurred
7659 */
7660#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
7661#define DMA_ERR_ERR9_MASK (0x200U)
7662#define DMA_ERR_ERR9_SHIFT (9U)
7663/*! ERR9 - Error In Channel 9
7664 * 0b0..An error in this channel has not occurred
7665 * 0b1..An error in this channel has occurred
7666 */
7667#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
7668#define DMA_ERR_ERR10_MASK (0x400U)
7669#define DMA_ERR_ERR10_SHIFT (10U)
7670/*! ERR10 - Error In Channel 10
7671 * 0b0..An error in this channel has not occurred
7672 * 0b1..An error in this channel has occurred
7673 */
7674#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
7675#define DMA_ERR_ERR11_MASK (0x800U)
7676#define DMA_ERR_ERR11_SHIFT (11U)
7677/*! ERR11 - Error In Channel 11
7678 * 0b0..An error in this channel has not occurred
7679 * 0b1..An error in this channel has occurred
7680 */
7681#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
7682#define DMA_ERR_ERR12_MASK (0x1000U)
7683#define DMA_ERR_ERR12_SHIFT (12U)
7684/*! ERR12 - Error In Channel 12
7685 * 0b0..An error in this channel has not occurred
7686 * 0b1..An error in this channel has occurred
7687 */
7688#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
7689#define DMA_ERR_ERR13_MASK (0x2000U)
7690#define DMA_ERR_ERR13_SHIFT (13U)
7691/*! ERR13 - Error In Channel 13
7692 * 0b0..An error in this channel has not occurred
7693 * 0b1..An error in this channel has occurred
7694 */
7695#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
7696#define DMA_ERR_ERR14_MASK (0x4000U)
7697#define DMA_ERR_ERR14_SHIFT (14U)
7698/*! ERR14 - Error In Channel 14
7699 * 0b0..An error in this channel has not occurred
7700 * 0b1..An error in this channel has occurred
7701 */
7702#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
7703#define DMA_ERR_ERR15_MASK (0x8000U)
7704#define DMA_ERR_ERR15_SHIFT (15U)
7705/*! ERR15 - Error In Channel 15
7706 * 0b0..An error in this channel has not occurred
7707 * 0b1..An error in this channel has occurred
7708 */
7709#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
7710#define DMA_ERR_ERR16_MASK (0x10000U)
7711#define DMA_ERR_ERR16_SHIFT (16U)
7712/*! ERR16 - Error In Channel 16
7713 * 0b0..An error in this channel has not occurred
7714 * 0b1..An error in this channel has occurred
7715 */
7716#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
7717#define DMA_ERR_ERR17_MASK (0x20000U)
7718#define DMA_ERR_ERR17_SHIFT (17U)
7719/*! ERR17 - Error In Channel 17
7720 * 0b0..An error in this channel has not occurred
7721 * 0b1..An error in this channel has occurred
7722 */
7723#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
7724#define DMA_ERR_ERR18_MASK (0x40000U)
7725#define DMA_ERR_ERR18_SHIFT (18U)
7726/*! ERR18 - Error In Channel 18
7727 * 0b0..An error in this channel has not occurred
7728 * 0b1..An error in this channel has occurred
7729 */
7730#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
7731#define DMA_ERR_ERR19_MASK (0x80000U)
7732#define DMA_ERR_ERR19_SHIFT (19U)
7733/*! ERR19 - Error In Channel 19
7734 * 0b0..An error in this channel has not occurred
7735 * 0b1..An error in this channel has occurred
7736 */
7737#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
7738#define DMA_ERR_ERR20_MASK (0x100000U)
7739#define DMA_ERR_ERR20_SHIFT (20U)
7740/*! ERR20 - Error In Channel 20
7741 * 0b0..An error in this channel has not occurred
7742 * 0b1..An error in this channel has occurred
7743 */
7744#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
7745#define DMA_ERR_ERR21_MASK (0x200000U)
7746#define DMA_ERR_ERR21_SHIFT (21U)
7747/*! ERR21 - Error In Channel 21
7748 * 0b0..An error in this channel has not occurred
7749 * 0b1..An error in this channel has occurred
7750 */
7751#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
7752#define DMA_ERR_ERR22_MASK (0x400000U)
7753#define DMA_ERR_ERR22_SHIFT (22U)
7754/*! ERR22 - Error In Channel 22
7755 * 0b0..An error in this channel has not occurred
7756 * 0b1..An error in this channel has occurred
7757 */
7758#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
7759#define DMA_ERR_ERR23_MASK (0x800000U)
7760#define DMA_ERR_ERR23_SHIFT (23U)
7761/*! ERR23 - Error In Channel 23
7762 * 0b0..An error in this channel has not occurred
7763 * 0b1..An error in this channel has occurred
7764 */
7765#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
7766#define DMA_ERR_ERR24_MASK (0x1000000U)
7767#define DMA_ERR_ERR24_SHIFT (24U)
7768/*! ERR24 - Error In Channel 24
7769 * 0b0..An error in this channel has not occurred
7770 * 0b1..An error in this channel has occurred
7771 */
7772#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
7773#define DMA_ERR_ERR25_MASK (0x2000000U)
7774#define DMA_ERR_ERR25_SHIFT (25U)
7775/*! ERR25 - Error In Channel 25
7776 * 0b0..An error in this channel has not occurred
7777 * 0b1..An error in this channel has occurred
7778 */
7779#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
7780#define DMA_ERR_ERR26_MASK (0x4000000U)
7781#define DMA_ERR_ERR26_SHIFT (26U)
7782/*! ERR26 - Error In Channel 26
7783 * 0b0..An error in this channel has not occurred
7784 * 0b1..An error in this channel has occurred
7785 */
7786#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
7787#define DMA_ERR_ERR27_MASK (0x8000000U)
7788#define DMA_ERR_ERR27_SHIFT (27U)
7789/*! ERR27 - Error In Channel 27
7790 * 0b0..An error in this channel has not occurred
7791 * 0b1..An error in this channel has occurred
7792 */
7793#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
7794#define DMA_ERR_ERR28_MASK (0x10000000U)
7795#define DMA_ERR_ERR28_SHIFT (28U)
7796/*! ERR28 - Error In Channel 28
7797 * 0b0..An error in this channel has not occurred
7798 * 0b1..An error in this channel has occurred
7799 */
7800#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
7801#define DMA_ERR_ERR29_MASK (0x20000000U)
7802#define DMA_ERR_ERR29_SHIFT (29U)
7803/*! ERR29 - Error In Channel 29
7804 * 0b0..An error in this channel has not occurred
7805 * 0b1..An error in this channel has occurred
7806 */
7807#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
7808#define DMA_ERR_ERR30_MASK (0x40000000U)
7809#define DMA_ERR_ERR30_SHIFT (30U)
7810/*! ERR30 - Error In Channel 30
7811 * 0b0..An error in this channel has not occurred
7812 * 0b1..An error in this channel has occurred
7813 */
7814#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
7815#define DMA_ERR_ERR31_MASK (0x80000000U)
7816#define DMA_ERR_ERR31_SHIFT (31U)
7817/*! ERR31 - Error In Channel 31
7818 * 0b0..An error in this channel has not occurred
7819 * 0b1..An error in this channel has occurred
7820 */
7821#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
7822/*! @} */
7823
7824/*! @name HRS - Hardware Request Status Register */
7825/*! @{ */
7826#define DMA_HRS_HRS0_MASK (0x1U)
7827#define DMA_HRS_HRS0_SHIFT (0U)
7828/*! HRS0 - Hardware Request Status Channel 0
7829 * 0b0..A hardware service request for channel 0 is not present
7830 * 0b1..A hardware service request for channel 0 is present
7831 */
7832#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
7833#define DMA_HRS_HRS1_MASK (0x2U)
7834#define DMA_HRS_HRS1_SHIFT (1U)
7835/*! HRS1 - Hardware Request Status Channel 1
7836 * 0b0..A hardware service request for channel 1 is not present
7837 * 0b1..A hardware service request for channel 1 is present
7838 */
7839#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
7840#define DMA_HRS_HRS2_MASK (0x4U)
7841#define DMA_HRS_HRS2_SHIFT (2U)
7842/*! HRS2 - Hardware Request Status Channel 2
7843 * 0b0..A hardware service request for channel 2 is not present
7844 * 0b1..A hardware service request for channel 2 is present
7845 */
7846#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
7847#define DMA_HRS_HRS3_MASK (0x8U)
7848#define DMA_HRS_HRS3_SHIFT (3U)
7849/*! HRS3 - Hardware Request Status Channel 3
7850 * 0b0..A hardware service request for channel 3 is not present
7851 * 0b1..A hardware service request for channel 3 is present
7852 */
7853#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
7854#define DMA_HRS_HRS4_MASK (0x10U)
7855#define DMA_HRS_HRS4_SHIFT (4U)
7856/*! HRS4 - Hardware Request Status Channel 4
7857 * 0b0..A hardware service request for channel 4 is not present
7858 * 0b1..A hardware service request for channel 4 is present
7859 */
7860#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
7861#define DMA_HRS_HRS5_MASK (0x20U)
7862#define DMA_HRS_HRS5_SHIFT (5U)
7863/*! HRS5 - Hardware Request Status Channel 5
7864 * 0b0..A hardware service request for channel 5 is not present
7865 * 0b1..A hardware service request for channel 5 is present
7866 */
7867#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
7868#define DMA_HRS_HRS6_MASK (0x40U)
7869#define DMA_HRS_HRS6_SHIFT (6U)
7870/*! HRS6 - Hardware Request Status Channel 6
7871 * 0b0..A hardware service request for channel 6 is not present
7872 * 0b1..A hardware service request for channel 6 is present
7873 */
7874#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
7875#define DMA_HRS_HRS7_MASK (0x80U)
7876#define DMA_HRS_HRS7_SHIFT (7U)
7877/*! HRS7 - Hardware Request Status Channel 7
7878 * 0b0..A hardware service request for channel 7 is not present
7879 * 0b1..A hardware service request for channel 7 is present
7880 */
7881#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
7882#define DMA_HRS_HRS8_MASK (0x100U)
7883#define DMA_HRS_HRS8_SHIFT (8U)
7884/*! HRS8 - Hardware Request Status Channel 8
7885 * 0b0..A hardware service request for channel 8 is not present
7886 * 0b1..A hardware service request for channel 8 is present
7887 */
7888#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
7889#define DMA_HRS_HRS9_MASK (0x200U)
7890#define DMA_HRS_HRS9_SHIFT (9U)
7891/*! HRS9 - Hardware Request Status Channel 9
7892 * 0b0..A hardware service request for channel 9 is not present
7893 * 0b1..A hardware service request for channel 9 is present
7894 */
7895#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
7896#define DMA_HRS_HRS10_MASK (0x400U)
7897#define DMA_HRS_HRS10_SHIFT (10U)
7898/*! HRS10 - Hardware Request Status Channel 10
7899 * 0b0..A hardware service request for channel 10 is not present
7900 * 0b1..A hardware service request for channel 10 is present
7901 */
7902#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
7903#define DMA_HRS_HRS11_MASK (0x800U)
7904#define DMA_HRS_HRS11_SHIFT (11U)
7905/*! HRS11 - Hardware Request Status Channel 11
7906 * 0b0..A hardware service request for channel 11 is not present
7907 * 0b1..A hardware service request for channel 11 is present
7908 */
7909#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
7910#define DMA_HRS_HRS12_MASK (0x1000U)
7911#define DMA_HRS_HRS12_SHIFT (12U)
7912/*! HRS12 - Hardware Request Status Channel 12
7913 * 0b0..A hardware service request for channel 12 is not present
7914 * 0b1..A hardware service request for channel 12 is present
7915 */
7916#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
7917#define DMA_HRS_HRS13_MASK (0x2000U)
7918#define DMA_HRS_HRS13_SHIFT (13U)
7919/*! HRS13 - Hardware Request Status Channel 13
7920 * 0b0..A hardware service request for channel 13 is not present
7921 * 0b1..A hardware service request for channel 13 is present
7922 */
7923#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
7924#define DMA_HRS_HRS14_MASK (0x4000U)
7925#define DMA_HRS_HRS14_SHIFT (14U)
7926/*! HRS14 - Hardware Request Status Channel 14
7927 * 0b0..A hardware service request for channel 14 is not present
7928 * 0b1..A hardware service request for channel 14 is present
7929 */
7930#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
7931#define DMA_HRS_HRS15_MASK (0x8000U)
7932#define DMA_HRS_HRS15_SHIFT (15U)
7933/*! HRS15 - Hardware Request Status Channel 15
7934 * 0b0..A hardware service request for channel 15 is not present
7935 * 0b1..A hardware service request for channel 15 is present
7936 */
7937#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
7938#define DMA_HRS_HRS16_MASK (0x10000U)
7939#define DMA_HRS_HRS16_SHIFT (16U)
7940/*! HRS16 - Hardware Request Status Channel 16
7941 * 0b0..A hardware service request for channel 16 is not present
7942 * 0b1..A hardware service request for channel 16 is present
7943 */
7944#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
7945#define DMA_HRS_HRS17_MASK (0x20000U)
7946#define DMA_HRS_HRS17_SHIFT (17U)
7947/*! HRS17 - Hardware Request Status Channel 17
7948 * 0b0..A hardware service request for channel 17 is not present
7949 * 0b1..A hardware service request for channel 17 is present
7950 */
7951#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
7952#define DMA_HRS_HRS18_MASK (0x40000U)
7953#define DMA_HRS_HRS18_SHIFT (18U)
7954/*! HRS18 - Hardware Request Status Channel 18
7955 * 0b0..A hardware service request for channel 18 is not present
7956 * 0b1..A hardware service request for channel 18 is present
7957 */
7958#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
7959#define DMA_HRS_HRS19_MASK (0x80000U)
7960#define DMA_HRS_HRS19_SHIFT (19U)
7961/*! HRS19 - Hardware Request Status Channel 19
7962 * 0b0..A hardware service request for channel 19 is not present
7963 * 0b1..A hardware service request for channel 19 is present
7964 */
7965#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
7966#define DMA_HRS_HRS20_MASK (0x100000U)
7967#define DMA_HRS_HRS20_SHIFT (20U)
7968/*! HRS20 - Hardware Request Status Channel 20
7969 * 0b0..A hardware service request for channel 20 is not present
7970 * 0b1..A hardware service request for channel 20 is present
7971 */
7972#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
7973#define DMA_HRS_HRS21_MASK (0x200000U)
7974#define DMA_HRS_HRS21_SHIFT (21U)
7975/*! HRS21 - Hardware Request Status Channel 21
7976 * 0b0..A hardware service request for channel 21 is not present
7977 * 0b1..A hardware service request for channel 21 is present
7978 */
7979#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
7980#define DMA_HRS_HRS22_MASK (0x400000U)
7981#define DMA_HRS_HRS22_SHIFT (22U)
7982/*! HRS22 - Hardware Request Status Channel 22
7983 * 0b0..A hardware service request for channel 22 is not present
7984 * 0b1..A hardware service request for channel 22 is present
7985 */
7986#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
7987#define DMA_HRS_HRS23_MASK (0x800000U)
7988#define DMA_HRS_HRS23_SHIFT (23U)
7989/*! HRS23 - Hardware Request Status Channel 23
7990 * 0b0..A hardware service request for channel 23 is not present
7991 * 0b1..A hardware service request for channel 23 is present
7992 */
7993#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
7994#define DMA_HRS_HRS24_MASK (0x1000000U)
7995#define DMA_HRS_HRS24_SHIFT (24U)
7996/*! HRS24 - Hardware Request Status Channel 24
7997 * 0b0..A hardware service request for channel 24 is not present
7998 * 0b1..A hardware service request for channel 24 is present
7999 */
8000#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
8001#define DMA_HRS_HRS25_MASK (0x2000000U)
8002#define DMA_HRS_HRS25_SHIFT (25U)
8003/*! HRS25 - Hardware Request Status Channel 25
8004 * 0b0..A hardware service request for channel 25 is not present
8005 * 0b1..A hardware service request for channel 25 is present
8006 */
8007#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
8008#define DMA_HRS_HRS26_MASK (0x4000000U)
8009#define DMA_HRS_HRS26_SHIFT (26U)
8010/*! HRS26 - Hardware Request Status Channel 26
8011 * 0b0..A hardware service request for channel 26 is not present
8012 * 0b1..A hardware service request for channel 26 is present
8013 */
8014#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
8015#define DMA_HRS_HRS27_MASK (0x8000000U)
8016#define DMA_HRS_HRS27_SHIFT (27U)
8017/*! HRS27 - Hardware Request Status Channel 27
8018 * 0b0..A hardware service request for channel 27 is not present
8019 * 0b1..A hardware service request for channel 27 is present
8020 */
8021#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
8022#define DMA_HRS_HRS28_MASK (0x10000000U)
8023#define DMA_HRS_HRS28_SHIFT (28U)
8024/*! HRS28 - Hardware Request Status Channel 28
8025 * 0b0..A hardware service request for channel 28 is not present
8026 * 0b1..A hardware service request for channel 28 is present
8027 */
8028#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
8029#define DMA_HRS_HRS29_MASK (0x20000000U)
8030#define DMA_HRS_HRS29_SHIFT (29U)
8031/*! HRS29 - Hardware Request Status Channel 29
8032 * 0b0..A hardware service request for channel 29 is not preset
8033 * 0b1..A hardware service request for channel 29 is present
8034 */
8035#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
8036#define DMA_HRS_HRS30_MASK (0x40000000U)
8037#define DMA_HRS_HRS30_SHIFT (30U)
8038/*! HRS30 - Hardware Request Status Channel 30
8039 * 0b0..A hardware service request for channel 30 is not present
8040 * 0b1..A hardware service request for for channel 30 is present
8041 */
8042#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
8043#define DMA_HRS_HRS31_MASK (0x80000000U)
8044#define DMA_HRS_HRS31_SHIFT (31U)
8045/*! HRS31 - Hardware Request Status Channel 31
8046 * 0b0..A hardware service request for channel 31 is not present
8047 * 0b1..A hardware service request for channel 31 is present
8048 */
8049#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
8050/*! @} */
8051
8052/*! @name EARS - Enable Asynchronous Request in Stop Register */
8053/*! @{ */
8054#define DMA_EARS_EDREQ_0_MASK (0x1U)
8055#define DMA_EARS_EDREQ_0_SHIFT (0U)
8056/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
8057 * 0b0..Disable asynchronous DMA request for channel 0.
8058 * 0b1..Enable asynchronous DMA request for channel 0.
8059 */
8060#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
8061#define DMA_EARS_EDREQ_1_MASK (0x2U)
8062#define DMA_EARS_EDREQ_1_SHIFT (1U)
8063/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
8064 * 0b0..Disable asynchronous DMA request for channel 1
8065 * 0b1..Enable asynchronous DMA request for channel 1.
8066 */
8067#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
8068#define DMA_EARS_EDREQ_2_MASK (0x4U)
8069#define DMA_EARS_EDREQ_2_SHIFT (2U)
8070/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
8071 * 0b0..Disable asynchronous DMA request for channel 2.
8072 * 0b1..Enable asynchronous DMA request for channel 2.
8073 */
8074#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
8075#define DMA_EARS_EDREQ_3_MASK (0x8U)
8076#define DMA_EARS_EDREQ_3_SHIFT (3U)
8077/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
8078 * 0b0..Disable asynchronous DMA request for channel 3.
8079 * 0b1..Enable asynchronous DMA request for channel 3.
8080 */
8081#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
8082#define DMA_EARS_EDREQ_4_MASK (0x10U)
8083#define DMA_EARS_EDREQ_4_SHIFT (4U)
8084/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4
8085 * 0b0..Disable asynchronous DMA request for channel 4.
8086 * 0b1..Enable asynchronous DMA request for channel 4.
8087 */
8088#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
8089#define DMA_EARS_EDREQ_5_MASK (0x20U)
8090#define DMA_EARS_EDREQ_5_SHIFT (5U)
8091/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5
8092 * 0b0..Disable asynchronous DMA request for channel 5.
8093 * 0b1..Enable asynchronous DMA request for channel 5.
8094 */
8095#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
8096#define DMA_EARS_EDREQ_6_MASK (0x40U)
8097#define DMA_EARS_EDREQ_6_SHIFT (6U)
8098/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6
8099 * 0b0..Disable asynchronous DMA request for channel 6.
8100 * 0b1..Enable asynchronous DMA request for channel 6.
8101 */
8102#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
8103#define DMA_EARS_EDREQ_7_MASK (0x80U)
8104#define DMA_EARS_EDREQ_7_SHIFT (7U)
8105/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7
8106 * 0b0..Disable asynchronous DMA request for channel 7.
8107 * 0b1..Enable asynchronous DMA request for channel 7.
8108 */
8109#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
8110#define DMA_EARS_EDREQ_8_MASK (0x100U)
8111#define DMA_EARS_EDREQ_8_SHIFT (8U)
8112/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8
8113 * 0b0..Disable asynchronous DMA request for channel 8.
8114 * 0b1..Enable asynchronous DMA request for channel 8.
8115 */
8116#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
8117#define DMA_EARS_EDREQ_9_MASK (0x200U)
8118#define DMA_EARS_EDREQ_9_SHIFT (9U)
8119/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9
8120 * 0b0..Disable asynchronous DMA request for channel 9.
8121 * 0b1..Enable asynchronous DMA request for channel 9.
8122 */
8123#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
8124#define DMA_EARS_EDREQ_10_MASK (0x400U)
8125#define DMA_EARS_EDREQ_10_SHIFT (10U)
8126/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10
8127 * 0b0..Disable asynchronous DMA request for channel 10.
8128 * 0b1..Enable asynchronous DMA request for channel 10.
8129 */
8130#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
8131#define DMA_EARS_EDREQ_11_MASK (0x800U)
8132#define DMA_EARS_EDREQ_11_SHIFT (11U)
8133/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11
8134 * 0b0..Disable asynchronous DMA request for channel 11.
8135 * 0b1..Enable asynchronous DMA request for channel 11.
8136 */
8137#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
8138#define DMA_EARS_EDREQ_12_MASK (0x1000U)
8139#define DMA_EARS_EDREQ_12_SHIFT (12U)
8140/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12
8141 * 0b0..Disable asynchronous DMA request for channel 12.
8142 * 0b1..Enable asynchronous DMA request for channel 12.
8143 */
8144#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
8145#define DMA_EARS_EDREQ_13_MASK (0x2000U)
8146#define DMA_EARS_EDREQ_13_SHIFT (13U)
8147/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13
8148 * 0b0..Disable asynchronous DMA request for channel 13.
8149 * 0b1..Enable asynchronous DMA request for channel 13.
8150 */
8151#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
8152#define DMA_EARS_EDREQ_14_MASK (0x4000U)
8153#define DMA_EARS_EDREQ_14_SHIFT (14U)
8154/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14
8155 * 0b0..Disable asynchronous DMA request for channel 14.
8156 * 0b1..Enable asynchronous DMA request for channel 14.
8157 */
8158#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
8159#define DMA_EARS_EDREQ_15_MASK (0x8000U)
8160#define DMA_EARS_EDREQ_15_SHIFT (15U)
8161/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15
8162 * 0b0..Disable asynchronous DMA request for channel 15.
8163 * 0b1..Enable asynchronous DMA request for channel 15.
8164 */
8165#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
8166#define DMA_EARS_EDREQ_16_MASK (0x10000U)
8167#define DMA_EARS_EDREQ_16_SHIFT (16U)
8168/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16
8169 * 0b0..Disable asynchronous DMA request for channel 16
8170 * 0b1..Enable asynchronous DMA request for channel 16
8171 */
8172#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
8173#define DMA_EARS_EDREQ_17_MASK (0x20000U)
8174#define DMA_EARS_EDREQ_17_SHIFT (17U)
8175/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17
8176 * 0b0..Disable asynchronous DMA request for channel 17
8177 * 0b1..Enable asynchronous DMA request for channel 17
8178 */
8179#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
8180#define DMA_EARS_EDREQ_18_MASK (0x40000U)
8181#define DMA_EARS_EDREQ_18_SHIFT (18U)
8182/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18
8183 * 0b0..Disable asynchronous DMA request for channel 18
8184 * 0b1..Enable asynchronous DMA request for channel 18
8185 */
8186#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
8187#define DMA_EARS_EDREQ_19_MASK (0x80000U)
8188#define DMA_EARS_EDREQ_19_SHIFT (19U)
8189/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19
8190 * 0b0..Disable asynchronous DMA request for channel 19
8191 * 0b1..Enable asynchronous DMA request for channel 19
8192 */
8193#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
8194#define DMA_EARS_EDREQ_20_MASK (0x100000U)
8195#define DMA_EARS_EDREQ_20_SHIFT (20U)
8196/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20
8197 * 0b0..Disable asynchronous DMA request for channel 20
8198 * 0b1..Enable asynchronous DMA request for channel 20
8199 */
8200#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
8201#define DMA_EARS_EDREQ_21_MASK (0x200000U)
8202#define DMA_EARS_EDREQ_21_SHIFT (21U)
8203/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21
8204 * 0b0..Disable asynchronous DMA request for channel 21
8205 * 0b1..Enable asynchronous DMA request for channel 21
8206 */
8207#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
8208#define DMA_EARS_EDREQ_22_MASK (0x400000U)
8209#define DMA_EARS_EDREQ_22_SHIFT (22U)
8210/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22
8211 * 0b0..Disable asynchronous DMA request for channel 22
8212 * 0b1..Enable asynchronous DMA request for channel 22
8213 */
8214#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
8215#define DMA_EARS_EDREQ_23_MASK (0x800000U)
8216#define DMA_EARS_EDREQ_23_SHIFT (23U)
8217/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23
8218 * 0b0..Disable asynchronous DMA request for channel 23
8219 * 0b1..Enable asynchronous DMA request for channel 23
8220 */
8221#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
8222#define DMA_EARS_EDREQ_24_MASK (0x1000000U)
8223#define DMA_EARS_EDREQ_24_SHIFT (24U)
8224/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24
8225 * 0b0..Disable asynchronous DMA request for channel 24
8226 * 0b1..Enable asynchronous DMA request for channel 24
8227 */
8228#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
8229#define DMA_EARS_EDREQ_25_MASK (0x2000000U)
8230#define DMA_EARS_EDREQ_25_SHIFT (25U)
8231/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25
8232 * 0b0..Disable asynchronous DMA request for channel 25
8233 * 0b1..Enable asynchronous DMA request for channel 25
8234 */
8235#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
8236#define DMA_EARS_EDREQ_26_MASK (0x4000000U)
8237#define DMA_EARS_EDREQ_26_SHIFT (26U)
8238/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26
8239 * 0b0..Disable asynchronous DMA request for channel 26
8240 * 0b1..Enable asynchronous DMA request for channel 26
8241 */
8242#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
8243#define DMA_EARS_EDREQ_27_MASK (0x8000000U)
8244#define DMA_EARS_EDREQ_27_SHIFT (27U)
8245/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27
8246 * 0b0..Disable asynchronous DMA request for channel 27
8247 * 0b1..Enable asynchronous DMA request for channel 27
8248 */
8249#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
8250#define DMA_EARS_EDREQ_28_MASK (0x10000000U)
8251#define DMA_EARS_EDREQ_28_SHIFT (28U)
8252/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28
8253 * 0b0..Disable asynchronous DMA request for channel 28
8254 * 0b1..Enable asynchronous DMA request for channel 28
8255 */
8256#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
8257#define DMA_EARS_EDREQ_29_MASK (0x20000000U)
8258#define DMA_EARS_EDREQ_29_SHIFT (29U)
8259/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29
8260 * 0b0..Disable asynchronous DMA request for channel 29
8261 * 0b1..Enable asynchronous DMA request for channel 29
8262 */
8263#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
8264#define DMA_EARS_EDREQ_30_MASK (0x40000000U)
8265#define DMA_EARS_EDREQ_30_SHIFT (30U)
8266/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30
8267 * 0b0..Disable asynchronous DMA request for channel 30
8268 * 0b1..Enable asynchronous DMA request for channel 30
8269 */
8270#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
8271#define DMA_EARS_EDREQ_31_MASK (0x80000000U)
8272#define DMA_EARS_EDREQ_31_SHIFT (31U)
8273/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31
8274 * 0b0..Disable asynchronous DMA request for channel 31
8275 * 0b1..Enable asynchronous DMA request for channel 31
8276 */
8277#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
8278/*! @} */
8279
8280/*! @name DCHPRI3 - Channel n Priority Register */
8281/*! @{ */
8282#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
8283#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
8284#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
8285#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
8286#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
8287#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
8288#define DMA_DCHPRI3_DPA_MASK (0x40U)
8289#define DMA_DCHPRI3_DPA_SHIFT (6U)
8290/*! DPA - Disable Preempt Ability.
8291 * 0b0..Channel n can suspend a lower priority channel.
8292 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8293 */
8294#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
8295#define DMA_DCHPRI3_ECP_MASK (0x80U)
8296#define DMA_DCHPRI3_ECP_SHIFT (7U)
8297/*! ECP - Enable Channel Preemption.
8298 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8299 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8300 */
8301#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
8302/*! @} */
8303
8304/*! @name DCHPRI2 - Channel n Priority Register */
8305/*! @{ */
8306#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
8307#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
8308#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
8309#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
8310#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
8311#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
8312#define DMA_DCHPRI2_DPA_MASK (0x40U)
8313#define DMA_DCHPRI2_DPA_SHIFT (6U)
8314/*! DPA - Disable Preempt Ability.
8315 * 0b0..Channel n can suspend a lower priority channel.
8316 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8317 */
8318#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
8319#define DMA_DCHPRI2_ECP_MASK (0x80U)
8320#define DMA_DCHPRI2_ECP_SHIFT (7U)
8321/*! ECP - Enable Channel Preemption.
8322 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8323 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8324 */
8325#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
8326/*! @} */
8327
8328/*! @name DCHPRI1 - Channel n Priority Register */
8329/*! @{ */
8330#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
8331#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
8332#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
8333#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
8334#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
8335#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
8336#define DMA_DCHPRI1_DPA_MASK (0x40U)
8337#define DMA_DCHPRI1_DPA_SHIFT (6U)
8338/*! DPA - Disable Preempt Ability.
8339 * 0b0..Channel n can suspend a lower priority channel.
8340 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8341 */
8342#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
8343#define DMA_DCHPRI1_ECP_MASK (0x80U)
8344#define DMA_DCHPRI1_ECP_SHIFT (7U)
8345/*! ECP - Enable Channel Preemption.
8346 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8347 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8348 */
8349#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
8350/*! @} */
8351
8352/*! @name DCHPRI0 - Channel n Priority Register */
8353/*! @{ */
8354#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
8355#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
8356#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
8357#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
8358#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
8359#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
8360#define DMA_DCHPRI0_DPA_MASK (0x40U)
8361#define DMA_DCHPRI0_DPA_SHIFT (6U)
8362/*! DPA - Disable Preempt Ability.
8363 * 0b0..Channel n can suspend a lower priority channel.
8364 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8365 */
8366#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
8367#define DMA_DCHPRI0_ECP_MASK (0x80U)
8368#define DMA_DCHPRI0_ECP_SHIFT (7U)
8369/*! ECP - Enable Channel Preemption.
8370 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8371 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8372 */
8373#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
8374/*! @} */
8375
8376/*! @name DCHPRI7 - Channel n Priority Register */
8377/*! @{ */
8378#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
8379#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
8380#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
8381#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
8382#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
8383#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
8384#define DMA_DCHPRI7_DPA_MASK (0x40U)
8385#define DMA_DCHPRI7_DPA_SHIFT (6U)
8386/*! DPA - Disable Preempt Ability.
8387 * 0b0..Channel n can suspend a lower priority channel.
8388 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8389 */
8390#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
8391#define DMA_DCHPRI7_ECP_MASK (0x80U)
8392#define DMA_DCHPRI7_ECP_SHIFT (7U)
8393/*! ECP - Enable Channel Preemption.
8394 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8395 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8396 */
8397#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
8398/*! @} */
8399
8400/*! @name DCHPRI6 - Channel n Priority Register */
8401/*! @{ */
8402#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
8403#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
8404#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
8405#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
8406#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
8407#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
8408#define DMA_DCHPRI6_DPA_MASK (0x40U)
8409#define DMA_DCHPRI6_DPA_SHIFT (6U)
8410/*! DPA - Disable Preempt Ability.
8411 * 0b0..Channel n can suspend a lower priority channel.
8412 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8413 */
8414#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
8415#define DMA_DCHPRI6_ECP_MASK (0x80U)
8416#define DMA_DCHPRI6_ECP_SHIFT (7U)
8417/*! ECP - Enable Channel Preemption.
8418 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8419 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8420 */
8421#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
8422/*! @} */
8423
8424/*! @name DCHPRI5 - Channel n Priority Register */
8425/*! @{ */
8426#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
8427#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
8428#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
8429#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
8430#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
8431#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
8432#define DMA_DCHPRI5_DPA_MASK (0x40U)
8433#define DMA_DCHPRI5_DPA_SHIFT (6U)
8434/*! DPA - Disable Preempt Ability.
8435 * 0b0..Channel n can suspend a lower priority channel.
8436 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8437 */
8438#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
8439#define DMA_DCHPRI5_ECP_MASK (0x80U)
8440#define DMA_DCHPRI5_ECP_SHIFT (7U)
8441/*! ECP - Enable Channel Preemption.
8442 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8443 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8444 */
8445#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
8446/*! @} */
8447
8448/*! @name DCHPRI4 - Channel n Priority Register */
8449/*! @{ */
8450#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
8451#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
8452#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
8453#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
8454#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
8455#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
8456#define DMA_DCHPRI4_DPA_MASK (0x40U)
8457#define DMA_DCHPRI4_DPA_SHIFT (6U)
8458/*! DPA - Disable Preempt Ability.
8459 * 0b0..Channel n can suspend a lower priority channel.
8460 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8461 */
8462#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
8463#define DMA_DCHPRI4_ECP_MASK (0x80U)
8464#define DMA_DCHPRI4_ECP_SHIFT (7U)
8465/*! ECP - Enable Channel Preemption.
8466 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8467 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8468 */
8469#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
8470/*! @} */
8471
8472/*! @name DCHPRI11 - Channel n Priority Register */
8473/*! @{ */
8474#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
8475#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
8476#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
8477#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
8478#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
8479#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
8480#define DMA_DCHPRI11_DPA_MASK (0x40U)
8481#define DMA_DCHPRI11_DPA_SHIFT (6U)
8482/*! DPA - Disable Preempt Ability.
8483 * 0b0..Channel n can suspend a lower priority channel.
8484 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8485 */
8486#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
8487#define DMA_DCHPRI11_ECP_MASK (0x80U)
8488#define DMA_DCHPRI11_ECP_SHIFT (7U)
8489/*! ECP - Enable Channel Preemption.
8490 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8491 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8492 */
8493#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
8494/*! @} */
8495
8496/*! @name DCHPRI10 - Channel n Priority Register */
8497/*! @{ */
8498#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
8499#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
8500#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
8501#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
8502#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
8503#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
8504#define DMA_DCHPRI10_DPA_MASK (0x40U)
8505#define DMA_DCHPRI10_DPA_SHIFT (6U)
8506/*! DPA - Disable Preempt Ability.
8507 * 0b0..Channel n can suspend a lower priority channel.
8508 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8509 */
8510#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
8511#define DMA_DCHPRI10_ECP_MASK (0x80U)
8512#define DMA_DCHPRI10_ECP_SHIFT (7U)
8513/*! ECP - Enable Channel Preemption.
8514 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8515 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8516 */
8517#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
8518/*! @} */
8519
8520/*! @name DCHPRI9 - Channel n Priority Register */
8521/*! @{ */
8522#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
8523#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
8524#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
8525#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
8526#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
8527#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
8528#define DMA_DCHPRI9_DPA_MASK (0x40U)
8529#define DMA_DCHPRI9_DPA_SHIFT (6U)
8530/*! DPA - Disable Preempt Ability.
8531 * 0b0..Channel n can suspend a lower priority channel.
8532 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8533 */
8534#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
8535#define DMA_DCHPRI9_ECP_MASK (0x80U)
8536#define DMA_DCHPRI9_ECP_SHIFT (7U)
8537/*! ECP - Enable Channel Preemption.
8538 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8539 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8540 */
8541#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
8542/*! @} */
8543
8544/*! @name DCHPRI8 - Channel n Priority Register */
8545/*! @{ */
8546#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
8547#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
8548#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
8549#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
8550#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
8551#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
8552#define DMA_DCHPRI8_DPA_MASK (0x40U)
8553#define DMA_DCHPRI8_DPA_SHIFT (6U)
8554/*! DPA - Disable Preempt Ability.
8555 * 0b0..Channel n can suspend a lower priority channel.
8556 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8557 */
8558#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
8559#define DMA_DCHPRI8_ECP_MASK (0x80U)
8560#define DMA_DCHPRI8_ECP_SHIFT (7U)
8561/*! ECP - Enable Channel Preemption.
8562 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8563 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8564 */
8565#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
8566/*! @} */
8567
8568/*! @name DCHPRI15 - Channel n Priority Register */
8569/*! @{ */
8570#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
8571#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
8572#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
8573#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
8574#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
8575#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
8576#define DMA_DCHPRI15_DPA_MASK (0x40U)
8577#define DMA_DCHPRI15_DPA_SHIFT (6U)
8578/*! DPA - Disable Preempt Ability.
8579 * 0b0..Channel n can suspend a lower priority channel.
8580 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8581 */
8582#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
8583#define DMA_DCHPRI15_ECP_MASK (0x80U)
8584#define DMA_DCHPRI15_ECP_SHIFT (7U)
8585/*! ECP - Enable Channel Preemption.
8586 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8587 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8588 */
8589#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
8590/*! @} */
8591
8592/*! @name DCHPRI14 - Channel n Priority Register */
8593/*! @{ */
8594#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
8595#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
8596#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
8597#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
8598#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
8599#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
8600#define DMA_DCHPRI14_DPA_MASK (0x40U)
8601#define DMA_DCHPRI14_DPA_SHIFT (6U)
8602/*! DPA - Disable Preempt Ability.
8603 * 0b0..Channel n can suspend a lower priority channel.
8604 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8605 */
8606#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
8607#define DMA_DCHPRI14_ECP_MASK (0x80U)
8608#define DMA_DCHPRI14_ECP_SHIFT (7U)
8609/*! ECP - Enable Channel Preemption.
8610 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8611 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8612 */
8613#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
8614/*! @} */
8615
8616/*! @name DCHPRI13 - Channel n Priority Register */
8617/*! @{ */
8618#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
8619#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
8620#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
8621#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
8622#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
8623#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
8624#define DMA_DCHPRI13_DPA_MASK (0x40U)
8625#define DMA_DCHPRI13_DPA_SHIFT (6U)
8626/*! DPA - Disable Preempt Ability.
8627 * 0b0..Channel n can suspend a lower priority channel.
8628 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8629 */
8630#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
8631#define DMA_DCHPRI13_ECP_MASK (0x80U)
8632#define DMA_DCHPRI13_ECP_SHIFT (7U)
8633/*! ECP - Enable Channel Preemption.
8634 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8635 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8636 */
8637#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
8638/*! @} */
8639
8640/*! @name DCHPRI12 - Channel n Priority Register */
8641/*! @{ */
8642#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
8643#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
8644#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
8645#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
8646#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
8647#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
8648#define DMA_DCHPRI12_DPA_MASK (0x40U)
8649#define DMA_DCHPRI12_DPA_SHIFT (6U)
8650/*! DPA - Disable Preempt Ability.
8651 * 0b0..Channel n can suspend a lower priority channel.
8652 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8653 */
8654#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
8655#define DMA_DCHPRI12_ECP_MASK (0x80U)
8656#define DMA_DCHPRI12_ECP_SHIFT (7U)
8657/*! ECP - Enable Channel Preemption.
8658 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8659 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8660 */
8661#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
8662/*! @} */
8663
8664/*! @name DCHPRI19 - Channel n Priority Register */
8665/*! @{ */
8666#define DMA_DCHPRI19_CHPRI_MASK (0xFU)
8667#define DMA_DCHPRI19_CHPRI_SHIFT (0U)
8668#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
8669#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
8670#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
8671#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
8672#define DMA_DCHPRI19_DPA_MASK (0x40U)
8673#define DMA_DCHPRI19_DPA_SHIFT (6U)
8674/*! DPA - Disable Preempt Ability.
8675 * 0b0..Channel n can suspend a lower priority channel.
8676 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8677 */
8678#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
8679#define DMA_DCHPRI19_ECP_MASK (0x80U)
8680#define DMA_DCHPRI19_ECP_SHIFT (7U)
8681/*! ECP - Enable Channel Preemption.
8682 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8683 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8684 */
8685#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
8686/*! @} */
8687
8688/*! @name DCHPRI18 - Channel n Priority Register */
8689/*! @{ */
8690#define DMA_DCHPRI18_CHPRI_MASK (0xFU)
8691#define DMA_DCHPRI18_CHPRI_SHIFT (0U)
8692#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
8693#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
8694#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
8695#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
8696#define DMA_DCHPRI18_DPA_MASK (0x40U)
8697#define DMA_DCHPRI18_DPA_SHIFT (6U)
8698/*! DPA - Disable Preempt Ability.
8699 * 0b0..Channel n can suspend a lower priority channel.
8700 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8701 */
8702#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
8703#define DMA_DCHPRI18_ECP_MASK (0x80U)
8704#define DMA_DCHPRI18_ECP_SHIFT (7U)
8705/*! ECP - Enable Channel Preemption.
8706 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8707 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8708 */
8709#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
8710/*! @} */
8711
8712/*! @name DCHPRI17 - Channel n Priority Register */
8713/*! @{ */
8714#define DMA_DCHPRI17_CHPRI_MASK (0xFU)
8715#define DMA_DCHPRI17_CHPRI_SHIFT (0U)
8716#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
8717#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
8718#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
8719#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
8720#define DMA_DCHPRI17_DPA_MASK (0x40U)
8721#define DMA_DCHPRI17_DPA_SHIFT (6U)
8722/*! DPA - Disable Preempt Ability.
8723 * 0b0..Channel n can suspend a lower priority channel.
8724 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8725 */
8726#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
8727#define DMA_DCHPRI17_ECP_MASK (0x80U)
8728#define DMA_DCHPRI17_ECP_SHIFT (7U)
8729/*! ECP - Enable Channel Preemption.
8730 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8731 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8732 */
8733#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
8734/*! @} */
8735
8736/*! @name DCHPRI16 - Channel n Priority Register */
8737/*! @{ */
8738#define DMA_DCHPRI16_CHPRI_MASK (0xFU)
8739#define DMA_DCHPRI16_CHPRI_SHIFT (0U)
8740#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
8741#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
8742#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
8743#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
8744#define DMA_DCHPRI16_DPA_MASK (0x40U)
8745#define DMA_DCHPRI16_DPA_SHIFT (6U)
8746/*! DPA - Disable Preempt Ability.
8747 * 0b0..Channel n can suspend a lower priority channel.
8748 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8749 */
8750#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
8751#define DMA_DCHPRI16_ECP_MASK (0x80U)
8752#define DMA_DCHPRI16_ECP_SHIFT (7U)
8753/*! ECP - Enable Channel Preemption.
8754 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8755 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8756 */
8757#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
8758/*! @} */
8759
8760/*! @name DCHPRI23 - Channel n Priority Register */
8761/*! @{ */
8762#define DMA_DCHPRI23_CHPRI_MASK (0xFU)
8763#define DMA_DCHPRI23_CHPRI_SHIFT (0U)
8764#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
8765#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
8766#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
8767#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
8768#define DMA_DCHPRI23_DPA_MASK (0x40U)
8769#define DMA_DCHPRI23_DPA_SHIFT (6U)
8770/*! DPA - Disable Preempt Ability.
8771 * 0b0..Channel n can suspend a lower priority channel.
8772 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8773 */
8774#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
8775#define DMA_DCHPRI23_ECP_MASK (0x80U)
8776#define DMA_DCHPRI23_ECP_SHIFT (7U)
8777/*! ECP - Enable Channel Preemption.
8778 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8779 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8780 */
8781#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
8782/*! @} */
8783
8784/*! @name DCHPRI22 - Channel n Priority Register */
8785/*! @{ */
8786#define DMA_DCHPRI22_CHPRI_MASK (0xFU)
8787#define DMA_DCHPRI22_CHPRI_SHIFT (0U)
8788#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
8789#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
8790#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
8791#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
8792#define DMA_DCHPRI22_DPA_MASK (0x40U)
8793#define DMA_DCHPRI22_DPA_SHIFT (6U)
8794/*! DPA - Disable Preempt Ability.
8795 * 0b0..Channel n can suspend a lower priority channel.
8796 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8797 */
8798#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
8799#define DMA_DCHPRI22_ECP_MASK (0x80U)
8800#define DMA_DCHPRI22_ECP_SHIFT (7U)
8801/*! ECP - Enable Channel Preemption.
8802 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8803 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8804 */
8805#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
8806/*! @} */
8807
8808/*! @name DCHPRI21 - Channel n Priority Register */
8809/*! @{ */
8810#define DMA_DCHPRI21_CHPRI_MASK (0xFU)
8811#define DMA_DCHPRI21_CHPRI_SHIFT (0U)
8812#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
8813#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
8814#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
8815#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
8816#define DMA_DCHPRI21_DPA_MASK (0x40U)
8817#define DMA_DCHPRI21_DPA_SHIFT (6U)
8818/*! DPA - Disable Preempt Ability.
8819 * 0b0..Channel n can suspend a lower priority channel.
8820 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8821 */
8822#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
8823#define DMA_DCHPRI21_ECP_MASK (0x80U)
8824#define DMA_DCHPRI21_ECP_SHIFT (7U)
8825/*! ECP - Enable Channel Preemption.
8826 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8827 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8828 */
8829#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
8830/*! @} */
8831
8832/*! @name DCHPRI20 - Channel n Priority Register */
8833/*! @{ */
8834#define DMA_DCHPRI20_CHPRI_MASK (0xFU)
8835#define DMA_DCHPRI20_CHPRI_SHIFT (0U)
8836#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
8837#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
8838#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
8839#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
8840#define DMA_DCHPRI20_DPA_MASK (0x40U)
8841#define DMA_DCHPRI20_DPA_SHIFT (6U)
8842/*! DPA - Disable Preempt Ability.
8843 * 0b0..Channel n can suspend a lower priority channel.
8844 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8845 */
8846#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
8847#define DMA_DCHPRI20_ECP_MASK (0x80U)
8848#define DMA_DCHPRI20_ECP_SHIFT (7U)
8849/*! ECP - Enable Channel Preemption.
8850 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8851 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8852 */
8853#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
8854/*! @} */
8855
8856/*! @name DCHPRI27 - Channel n Priority Register */
8857/*! @{ */
8858#define DMA_DCHPRI27_CHPRI_MASK (0xFU)
8859#define DMA_DCHPRI27_CHPRI_SHIFT (0U)
8860#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
8861#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
8862#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
8863#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
8864#define DMA_DCHPRI27_DPA_MASK (0x40U)
8865#define DMA_DCHPRI27_DPA_SHIFT (6U)
8866/*! DPA - Disable Preempt Ability.
8867 * 0b0..Channel n can suspend a lower priority channel.
8868 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8869 */
8870#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
8871#define DMA_DCHPRI27_ECP_MASK (0x80U)
8872#define DMA_DCHPRI27_ECP_SHIFT (7U)
8873/*! ECP - Enable Channel Preemption.
8874 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8875 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8876 */
8877#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
8878/*! @} */
8879
8880/*! @name DCHPRI26 - Channel n Priority Register */
8881/*! @{ */
8882#define DMA_DCHPRI26_CHPRI_MASK (0xFU)
8883#define DMA_DCHPRI26_CHPRI_SHIFT (0U)
8884#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
8885#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
8886#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
8887#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
8888#define DMA_DCHPRI26_DPA_MASK (0x40U)
8889#define DMA_DCHPRI26_DPA_SHIFT (6U)
8890/*! DPA - Disable Preempt Ability.
8891 * 0b0..Channel n can suspend a lower priority channel.
8892 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8893 */
8894#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
8895#define DMA_DCHPRI26_ECP_MASK (0x80U)
8896#define DMA_DCHPRI26_ECP_SHIFT (7U)
8897/*! ECP - Enable Channel Preemption.
8898 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8899 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8900 */
8901#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
8902/*! @} */
8903
8904/*! @name DCHPRI25 - Channel n Priority Register */
8905/*! @{ */
8906#define DMA_DCHPRI25_CHPRI_MASK (0xFU)
8907#define DMA_DCHPRI25_CHPRI_SHIFT (0U)
8908#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
8909#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
8910#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
8911#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
8912#define DMA_DCHPRI25_DPA_MASK (0x40U)
8913#define DMA_DCHPRI25_DPA_SHIFT (6U)
8914/*! DPA - Disable Preempt Ability.
8915 * 0b0..Channel n can suspend a lower priority channel.
8916 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8917 */
8918#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
8919#define DMA_DCHPRI25_ECP_MASK (0x80U)
8920#define DMA_DCHPRI25_ECP_SHIFT (7U)
8921/*! ECP - Enable Channel Preemption.
8922 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8923 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8924 */
8925#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
8926/*! @} */
8927
8928/*! @name DCHPRI24 - Channel n Priority Register */
8929/*! @{ */
8930#define DMA_DCHPRI24_CHPRI_MASK (0xFU)
8931#define DMA_DCHPRI24_CHPRI_SHIFT (0U)
8932#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
8933#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
8934#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
8935#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
8936#define DMA_DCHPRI24_DPA_MASK (0x40U)
8937#define DMA_DCHPRI24_DPA_SHIFT (6U)
8938/*! DPA - Disable Preempt Ability.
8939 * 0b0..Channel n can suspend a lower priority channel.
8940 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8941 */
8942#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
8943#define DMA_DCHPRI24_ECP_MASK (0x80U)
8944#define DMA_DCHPRI24_ECP_SHIFT (7U)
8945/*! ECP - Enable Channel Preemption.
8946 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8947 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8948 */
8949#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
8950/*! @} */
8951
8952/*! @name DCHPRI31 - Channel n Priority Register */
8953/*! @{ */
8954#define DMA_DCHPRI31_CHPRI_MASK (0xFU)
8955#define DMA_DCHPRI31_CHPRI_SHIFT (0U)
8956#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
8957#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
8958#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
8959#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
8960#define DMA_DCHPRI31_DPA_MASK (0x40U)
8961#define DMA_DCHPRI31_DPA_SHIFT (6U)
8962/*! DPA - Disable Preempt Ability.
8963 * 0b0..Channel n can suspend a lower priority channel.
8964 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8965 */
8966#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
8967#define DMA_DCHPRI31_ECP_MASK (0x80U)
8968#define DMA_DCHPRI31_ECP_SHIFT (7U)
8969/*! ECP - Enable Channel Preemption.
8970 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8971 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8972 */
8973#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
8974/*! @} */
8975
8976/*! @name DCHPRI30 - Channel n Priority Register */
8977/*! @{ */
8978#define DMA_DCHPRI30_CHPRI_MASK (0xFU)
8979#define DMA_DCHPRI30_CHPRI_SHIFT (0U)
8980#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
8981#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
8982#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
8983#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
8984#define DMA_DCHPRI30_DPA_MASK (0x40U)
8985#define DMA_DCHPRI30_DPA_SHIFT (6U)
8986/*! DPA - Disable Preempt Ability.
8987 * 0b0..Channel n can suspend a lower priority channel.
8988 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
8989 */
8990#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
8991#define DMA_DCHPRI30_ECP_MASK (0x80U)
8992#define DMA_DCHPRI30_ECP_SHIFT (7U)
8993/*! ECP - Enable Channel Preemption.
8994 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
8995 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
8996 */
8997#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
8998/*! @} */
8999
9000/*! @name DCHPRI29 - Channel n Priority Register */
9001/*! @{ */
9002#define DMA_DCHPRI29_CHPRI_MASK (0xFU)
9003#define DMA_DCHPRI29_CHPRI_SHIFT (0U)
9004#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
9005#define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
9006#define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
9007#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
9008#define DMA_DCHPRI29_DPA_MASK (0x40U)
9009#define DMA_DCHPRI29_DPA_SHIFT (6U)
9010/*! DPA - Disable Preempt Ability.
9011 * 0b0..Channel n can suspend a lower priority channel.
9012 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
9013 */
9014#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
9015#define DMA_DCHPRI29_ECP_MASK (0x80U)
9016#define DMA_DCHPRI29_ECP_SHIFT (7U)
9017/*! ECP - Enable Channel Preemption.
9018 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
9019 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
9020 */
9021#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
9022/*! @} */
9023
9024/*! @name DCHPRI28 - Channel n Priority Register */
9025/*! @{ */
9026#define DMA_DCHPRI28_CHPRI_MASK (0xFU)
9027#define DMA_DCHPRI28_CHPRI_SHIFT (0U)
9028#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
9029#define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
9030#define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
9031#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
9032#define DMA_DCHPRI28_DPA_MASK (0x40U)
9033#define DMA_DCHPRI28_DPA_SHIFT (6U)
9034/*! DPA - Disable Preempt Ability.
9035 * 0b0..Channel n can suspend a lower priority channel.
9036 * 0b1..Channel n cannot suspend any channel, regardless of channel priority.
9037 */
9038#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
9039#define DMA_DCHPRI28_ECP_MASK (0x80U)
9040#define DMA_DCHPRI28_ECP_SHIFT (7U)
9041/*! ECP - Enable Channel Preemption.
9042 * 0b0..Channel n cannot be suspended by a higher priority channel's service request.
9043 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel.
9044 */
9045#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
9046/*! @} */
9047
9048/*! @name SADDR - TCD Source Address */
9049/*! @{ */
9050#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
9051#define DMA_SADDR_SADDR_SHIFT (0U)
9052#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
9053/*! @} */
9054
9055/* The count of DMA_SADDR */
9056#define DMA_SADDR_COUNT (32U)
9057
9058/*! @name SOFF - TCD Signed Source Address Offset */
9059/*! @{ */
9060#define DMA_SOFF_SOFF_MASK (0xFFFFU)
9061#define DMA_SOFF_SOFF_SHIFT (0U)
9062#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
9063/*! @} */
9064
9065/* The count of DMA_SOFF */
9066#define DMA_SOFF_COUNT (32U)
9067
9068/*! @name ATTR - TCD Transfer Attributes */
9069/*! @{ */
9070#define DMA_ATTR_DSIZE_MASK (0x7U)
9071#define DMA_ATTR_DSIZE_SHIFT (0U)
9072#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
9073#define DMA_ATTR_DMOD_MASK (0xF8U)
9074#define DMA_ATTR_DMOD_SHIFT (3U)
9075#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
9076#define DMA_ATTR_SSIZE_MASK (0x700U)
9077#define DMA_ATTR_SSIZE_SHIFT (8U)
9078/*! SSIZE - Source data transfer size
9079 * 0b000..8-bit
9080 * 0b001..16-bit
9081 * 0b010..32-bit
9082 * 0b011..Reserved
9083 * 0b100..16-byte burst
9084 * 0b101..32-byte burst
9085 * 0b110..Reserved
9086 * 0b111..Reserved
9087 */
9088#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
9089#define DMA_ATTR_SMOD_MASK (0xF800U)
9090#define DMA_ATTR_SMOD_SHIFT (11U)
9091/*! SMOD - Source Address Modulo
9092 * 0b00000..Source address modulo feature is disabled
9093 */
9094#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
9095/*! @} */
9096
9097/* The count of DMA_ATTR */
9098#define DMA_ATTR_COUNT (32U)
9099
9100/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
9101/*! @{ */
9102#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
9103#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
9104#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
9105/*! @} */
9106
9107/* The count of DMA_NBYTES_MLNO */
9108#define DMA_NBYTES_MLNO_COUNT (32U)
9109
9110/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
9111/*! @{ */
9112#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
9113#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
9114#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
9115#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
9116#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
9117/*! DMLOE - Destination Minor Loop Offset enable
9118 * 0b0..The minor loop offset is not applied to the DADDR
9119 * 0b1..The minor loop offset is applied to the DADDR
9120 */
9121#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
9122#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
9123#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
9124/*! SMLOE - Source Minor Loop Offset Enable
9125 * 0b0..The minor loop offset is not applied to the SADDR
9126 * 0b1..The minor loop offset is applied to the SADDR
9127 */
9128#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
9129/*! @} */
9130
9131/* The count of DMA_NBYTES_MLOFFNO */
9132#define DMA_NBYTES_MLOFFNO_COUNT (32U)
9133
9134/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
9135/*! @{ */
9136#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
9137#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
9138#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
9139#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
9140#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
9141#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
9142#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
9143#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
9144/*! DMLOE - Destination Minor Loop Offset enable
9145 * 0b0..The minor loop offset is not applied to the DADDR
9146 * 0b1..The minor loop offset is applied to the DADDR
9147 */
9148#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
9149#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
9150#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
9151/*! SMLOE - Source Minor Loop Offset Enable
9152 * 0b0..The minor loop offset is not applied to the SADDR
9153 * 0b1..The minor loop offset is applied to the SADDR
9154 */
9155#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
9156/*! @} */
9157
9158/* The count of DMA_NBYTES_MLOFFYES */
9159#define DMA_NBYTES_MLOFFYES_COUNT (32U)
9160
9161/*! @name SLAST - TCD Last Source Address Adjustment */
9162/*! @{ */
9163#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
9164#define DMA_SLAST_SLAST_SHIFT (0U)
9165#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
9166/*! @} */
9167
9168/* The count of DMA_SLAST */
9169#define DMA_SLAST_COUNT (32U)
9170
9171/*! @name DADDR - TCD Destination Address */
9172/*! @{ */
9173#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
9174#define DMA_DADDR_DADDR_SHIFT (0U)
9175#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
9176/*! @} */
9177
9178/* The count of DMA_DADDR */
9179#define DMA_DADDR_COUNT (32U)
9180
9181/*! @name DOFF - TCD Signed Destination Address Offset */
9182/*! @{ */
9183#define DMA_DOFF_DOFF_MASK (0xFFFFU)
9184#define DMA_DOFF_DOFF_SHIFT (0U)
9185#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
9186/*! @} */
9187
9188/* The count of DMA_DOFF */
9189#define DMA_DOFF_COUNT (32U)
9190
9191/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
9192/*! @{ */
9193#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
9194#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
9195#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
9196#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
9197#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
9198/*! ELINK - Enable channel-to-channel linking on minor-loop complete
9199 * 0b0..The channel-to-channel linking is disabled
9200 * 0b1..The channel-to-channel linking is enabled
9201 */
9202#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
9203/*! @} */
9204
9205/* The count of DMA_CITER_ELINKNO */
9206#define DMA_CITER_ELINKNO_COUNT (32U)
9207
9208/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
9209/*! @{ */
9210#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
9211#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
9212#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
9213#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
9214#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
9215#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
9216#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
9217#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
9218/*! ELINK - Enable channel-to-channel linking on minor-loop complete
9219 * 0b0..The channel-to-channel linking is disabled
9220 * 0b1..The channel-to-channel linking is enabled
9221 */
9222#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
9223/*! @} */
9224
9225/* The count of DMA_CITER_ELINKYES */
9226#define DMA_CITER_ELINKYES_COUNT (32U)
9227
9228/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
9229/*! @{ */
9230#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
9231#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
9232#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
9233/*! @} */
9234
9235/* The count of DMA_DLAST_SGA */
9236#define DMA_DLAST_SGA_COUNT (32U)
9237
9238/*! @name CSR - TCD Control and Status */
9239/*! @{ */
9240#define DMA_CSR_START_MASK (0x1U)
9241#define DMA_CSR_START_SHIFT (0U)
9242/*! START - Channel Start
9243 * 0b0..The channel is not explicitly started.
9244 * 0b1..The channel is explicitly started via a software initiated service request.
9245 */
9246#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
9247#define DMA_CSR_INTMAJOR_MASK (0x2U)
9248#define DMA_CSR_INTMAJOR_SHIFT (1U)
9249/*! INTMAJOR - Enable an interrupt when major iteration count completes.
9250 * 0b0..The end-of-major loop interrupt is disabled.
9251 * 0b1..The end-of-major loop interrupt is enabled.
9252 */
9253#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
9254#define DMA_CSR_INTHALF_MASK (0x4U)
9255#define DMA_CSR_INTHALF_SHIFT (2U)
9256/*! INTHALF - Enable an interrupt when major counter is half complete.
9257 * 0b0..The half-point interrupt is disabled.
9258 * 0b1..The half-point interrupt is enabled.
9259 */
9260#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
9261#define DMA_CSR_DREQ_MASK (0x8U)
9262#define DMA_CSR_DREQ_SHIFT (3U)
9263/*! DREQ - Disable Request
9264 * 0b0..The channel's ERQ bit is not affected.
9265 * 0b1..The channel's ERQ bit is cleared when the major loop is complete.
9266 */
9267#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
9268#define DMA_CSR_ESG_MASK (0x10U)
9269#define DMA_CSR_ESG_SHIFT (4U)
9270/*! ESG - Enable Scatter/Gather Processing
9271 * 0b0..The current channel's TCD is normal format.
9272 * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
9273 */
9274#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
9275#define DMA_CSR_MAJORELINK_MASK (0x20U)
9276#define DMA_CSR_MAJORELINK_SHIFT (5U)
9277/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
9278 * 0b0..The channel-to-channel linking is disabled.
9279 * 0b1..The channel-to-channel linking is enabled.
9280 */
9281#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
9282#define DMA_CSR_ACTIVE_MASK (0x40U)
9283#define DMA_CSR_ACTIVE_SHIFT (6U)
9284#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
9285#define DMA_CSR_DONE_MASK (0x80U)
9286#define DMA_CSR_DONE_SHIFT (7U)
9287#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
9288#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
9289#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
9290#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
9291#define DMA_CSR_BWC_MASK (0xC000U)
9292#define DMA_CSR_BWC_SHIFT (14U)
9293/*! BWC - Bandwidth Control
9294 * 0b00..No eDMA engine stalls
9295 * 0b01..Reserved
9296 * 0b10..eDMA engine stalls for 4 cycles after each R/W.
9297 * 0b11..eDMA engine stalls for 8 cycles after each R/W.
9298 */
9299#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
9300/*! @} */
9301
9302/* The count of DMA_CSR */
9303#define DMA_CSR_COUNT (32U)
9304
9305/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
9306/*! @{ */
9307#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
9308#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
9309#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
9310#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
9311#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
9312/*! ELINK - Enables channel-to-channel linking on minor loop complete
9313 * 0b0..The channel-to-channel linking is disabled
9314 * 0b1..The channel-to-channel linking is enabled
9315 */
9316#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
9317/*! @} */
9318
9319/* The count of DMA_BITER_ELINKNO */
9320#define DMA_BITER_ELINKNO_COUNT (32U)
9321
9322/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
9323/*! @{ */
9324#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
9325#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
9326#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
9327#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
9328#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
9329#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
9330#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
9331#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
9332/*! ELINK - Enables channel-to-channel linking on minor loop complete
9333 * 0b0..The channel-to-channel linking is disabled
9334 * 0b1..The channel-to-channel linking is enabled
9335 */
9336#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
9337/*! @} */
9338
9339/* The count of DMA_BITER_ELINKYES */
9340#define DMA_BITER_ELINKYES_COUNT (32U)
9341
9342
9343/*!
9344 * @}
9345 */ /* end of group DMA_Register_Masks */
9346
9347
9348/* DMA - Peripheral instance base addresses */
9349/** Peripheral DMA base address */
9350#define DMA_BASE (0x40008000u)
9351/** Peripheral DMA base pointer */
9352#define DMA0 ((DMA_Type *)DMA_BASE)
9353/** Array initializer of DMA peripheral base addresses */
9354#define DMA_BASE_ADDRS { DMA_BASE }
9355/** Array initializer of DMA peripheral base pointers */
9356#define DMA_BASE_PTRS { DMA0 }
9357/** Interrupt vectors for the DMA peripheral type */
9358#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
9359#define DMA_ERROR_IRQS { DMA_Error_IRQn }
9360
9361/*!
9362 * @}
9363 */ /* end of group DMA_Peripheral_Access_Layer */
9364
9365
9366/* ----------------------------------------------------------------------------
9367 -- DMAMUX Peripheral Access Layer
9368 ---------------------------------------------------------------------------- */
9369
9370/*!
9371 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
9372 * @{
9373 */
9374
9375/** DMAMUX - Register Layout Typedef */
9376typedef struct {
9377 __IO uint8_t CHCFG[32]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
9378} DMAMUX_Type;
9379
9380/* ----------------------------------------------------------------------------
9381 -- DMAMUX Register Masks
9382 ---------------------------------------------------------------------------- */
9383
9384/*!
9385 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
9386 * @{
9387 */
9388
9389/*! @name CHCFG - Channel Configuration register */
9390/*! @{ */
9391#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
9392#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
9393/*! SOURCE - DMA Channel Source (Slot)
9394 * 0b000000..Disable_Signal
9395 * 0b000001..TSI0_Signal
9396 * 0b000010..UART0_Rx_Signal
9397 * 0b000011..UART0_Tx_Signal
9398 * 0b000100..UART1_Rx_Signal
9399 * 0b000101..UART1_Tx_Signal
9400 * 0b000110..UART2_Rx_Signal
9401 * 0b000111..UART2_Tx_Signal
9402 * 0b001000..UART3_Rx_Signal
9403 * 0b001001..UART3_Tx_Signal
9404 * 0b001010..UART4_Signal
9405 * 0b001100..I2S0_Rx_Signal
9406 * 0b001101..I2S0_Tx_Signal
9407 * 0b001110..SPI0_Rx_Signal
9408 * 0b001111..SPI0_Tx_Signal
9409 * 0b010000..SPI1_Rx_Signal
9410 * 0b010001..SPI1_Tx_Signal
9411 * 0b010010..I2C0_I2C3_Signal
9412 * 0b010011..I2C1_I2C2_Signal
9413 * 0b010100..FTM0_Channel0_Signal
9414 * 0b010101..FTM0_Channel1_Signal
9415 * 0b010110..FTM0_Channel2_Signal
9416 * 0b010111..FTM0_Channel3_Signal
9417 * 0b011000..FTM0_Channel4_Signal
9418 * 0b011001..FTM0_Channel5_Signal
9419 * 0b011010..FTM0_Channel6_Signal
9420 * 0b011011..FTM0_Channel7_Signal
9421 * 0b011100..FTM1_TPM1_Channel0_Signal
9422 * 0b011101..FTM1_TPM1_Channel1_Signal
9423 * 0b011110..FTM2_TPM2_Channel0_Signal
9424 * 0b011111..FTM2_TPM2_Channel1_Signal
9425 * 0b100000..FTM3_Channel0_Signal
9426 * 0b100001..FTM3_Channel1_Signal
9427 * 0b100010..FTM3_Channel2_Signal
9428 * 0b100011..FTM3_Channel3_Signal
9429 * 0b100100..FTM3_Channel4_Signal
9430 * 0b100101..FTM3_Channel5_Signal
9431 * 0b100110..FTM3_Channel6_SPI2_Rx_Signal
9432 * 0b100111..FTM3_Channel7_SPI2_Tx_Signal
9433 * 0b101000..ADC0_Signal
9434 * 0b101001..ADC1_Signal
9435 * 0b101010..CMP0_Signal
9436 * 0b101011..CMP1_Signal
9437 * 0b101100..CMP2_CMP3_Signal
9438 * 0b101101..DAC0_Signal
9439 * 0b101110..DAC1_Signal
9440 * 0b101111..CMT_Signal
9441 * 0b110000..PDB_Signal
9442 * 0b110001..PortA_Signal
9443 * 0b110010..PortB_Signal
9444 * 0b110011..PortC_Signal
9445 * 0b110100..PortD_Signal
9446 * 0b110101..PortE_Signal
9447 * 0b110111..TPM1_Overflow_Signal
9448 * 0b111000..TPM2_Overflow_Signal
9449 * 0b111010..LPUART0_Rx_Signal
9450 * 0b111011..LPUART0_Tx_Signal
9451 * 0b111100..AlwaysOn60_Signal
9452 * 0b111101..AlwaysOn61_Signal
9453 * 0b111110..AlwaysOn62_Signal
9454 * 0b111111..AlwaysOn63_Signal
9455 */
9456#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
9457#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
9458#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
9459/*! TRIG - DMA Channel Trigger Enable
9460 * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
9461 * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
9462 */
9463#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
9464#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
9465#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
9466/*! ENBL - DMA Channel Enable
9467 * 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
9468 * 0b1..DMA channel is enabled
9469 */
9470#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
9471/*! @} */
9472
9473/* The count of DMAMUX_CHCFG */
9474#define DMAMUX_CHCFG_COUNT (32U)
9475
9476
9477/*!
9478 * @}
9479 */ /* end of group DMAMUX_Register_Masks */
9480
9481
9482/* DMAMUX - Peripheral instance base addresses */
9483/** Peripheral DMAMUX base address */
9484#define DMAMUX_BASE (0x40021000u)
9485/** Peripheral DMAMUX base pointer */
9486#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
9487/** Array initializer of DMAMUX peripheral base addresses */
9488#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
9489/** Array initializer of DMAMUX peripheral base pointers */
9490#define DMAMUX_BASE_PTRS { DMAMUX }
9491
9492/*!
9493 * @}
9494 */ /* end of group DMAMUX_Peripheral_Access_Layer */
9495
9496
9497/* ----------------------------------------------------------------------------
9498 -- EWM Peripheral Access Layer
9499 ---------------------------------------------------------------------------- */
9500
9501/*!
9502 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
9503 * @{
9504 */
9505
9506/** EWM - Register Layout Typedef */
9507typedef struct {
9508 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
9509 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
9510 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
9511 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
9512} EWM_Type;
9513
9514/* ----------------------------------------------------------------------------
9515 -- EWM Register Masks
9516 ---------------------------------------------------------------------------- */
9517
9518/*!
9519 * @addtogroup EWM_Register_Masks EWM Register Masks
9520 * @{
9521 */
9522
9523/*! @name CTRL - Control Register */
9524/*! @{ */
9525#define EWM_CTRL_EWMEN_MASK (0x1U)
9526#define EWM_CTRL_EWMEN_SHIFT (0U)
9527#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
9528#define EWM_CTRL_ASSIN_MASK (0x2U)
9529#define EWM_CTRL_ASSIN_SHIFT (1U)
9530#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
9531#define EWM_CTRL_INEN_MASK (0x4U)
9532#define EWM_CTRL_INEN_SHIFT (2U)
9533#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
9534#define EWM_CTRL_INTEN_MASK (0x8U)
9535#define EWM_CTRL_INTEN_SHIFT (3U)
9536#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
9537/*! @} */
9538
9539/*! @name SERV - Service Register */
9540/*! @{ */
9541#define EWM_SERV_SERVICE_MASK (0xFFU)
9542#define EWM_SERV_SERVICE_SHIFT (0U)
9543#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
9544/*! @} */
9545
9546/*! @name CMPL - Compare Low Register */
9547/*! @{ */
9548#define EWM_CMPL_COMPAREL_MASK (0xFFU)
9549#define EWM_CMPL_COMPAREL_SHIFT (0U)
9550#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
9551/*! @} */
9552
9553/*! @name CMPH - Compare High Register */
9554/*! @{ */
9555#define EWM_CMPH_COMPAREH_MASK (0xFFU)
9556#define EWM_CMPH_COMPAREH_SHIFT (0U)
9557#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
9558/*! @} */
9559
9560
9561/*!
9562 * @}
9563 */ /* end of group EWM_Register_Masks */
9564
9565
9566/* EWM - Peripheral instance base addresses */
9567/** Peripheral EWM base address */
9568#define EWM_BASE (0x40061000u)
9569/** Peripheral EWM base pointer */
9570#define EWM ((EWM_Type *)EWM_BASE)
9571/** Array initializer of EWM peripheral base addresses */
9572#define EWM_BASE_ADDRS { EWM_BASE }
9573/** Array initializer of EWM peripheral base pointers */
9574#define EWM_BASE_PTRS { EWM }
9575/** Interrupt vectors for the EWM peripheral type */
9576#define EWM_IRQS { WDOG_EWM_IRQn }
9577
9578/*!
9579 * @}
9580 */ /* end of group EWM_Peripheral_Access_Layer */
9581
9582
9583/* ----------------------------------------------------------------------------
9584 -- FB Peripheral Access Layer
9585 ---------------------------------------------------------------------------- */
9586
9587/*!
9588 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
9589 * @{
9590 */
9591
9592/** FB - Register Layout Typedef */
9593typedef struct {
9594 struct { /* offset: 0x0, array step: 0xC */
9595 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
9596 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
9597 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
9598 } CS[6];
9599 uint8_t RESERVED_0[24];
9600 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
9601} FB_Type;
9602
9603/* ----------------------------------------------------------------------------
9604 -- FB Register Masks
9605 ---------------------------------------------------------------------------- */
9606
9607/*!
9608 * @addtogroup FB_Register_Masks FB Register Masks
9609 * @{
9610 */
9611
9612/*! @name CSAR - Chip Select Address Register */
9613/*! @{ */
9614#define FB_CSAR_BA_MASK (0xFFFF0000U)
9615#define FB_CSAR_BA_SHIFT (16U)
9616#define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
9617/*! @} */
9618
9619/* The count of FB_CSAR */
9620#define FB_CSAR_COUNT (6U)
9621
9622/*! @name CSMR - Chip Select Mask Register */
9623/*! @{ */
9624#define FB_CSMR_V_MASK (0x1U)
9625#define FB_CSMR_V_SHIFT (0U)
9626/*! V - Valid
9627 * 0b0..Chip-select is invalid.
9628 * 0b1..Chip-select is valid.
9629 */
9630#define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
9631#define FB_CSMR_WP_MASK (0x100U)
9632#define FB_CSMR_WP_SHIFT (8U)
9633/*! WP - Write Protect
9634 * 0b0..Write accesses are allowed.
9635 * 0b1..Write accesses are not allowed. Attempting to write to the range of addresses for which the WP bit is set results in a bus error termination of the internal cycle and no external cycle.
9636 */
9637#define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
9638#define FB_CSMR_BAM_MASK (0xFFFF0000U)
9639#define FB_CSMR_BAM_SHIFT (16U)
9640/*! BAM - Base Address Mask
9641 * 0b0000000000000000..The corresponding address bit in CSAR is used in the chip-select decode.
9642 * 0b0000000000000001..The corresponding address bit in CSAR is a don't care in the chip-select decode.
9643 */
9644#define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
9645/*! @} */
9646
9647/* The count of FB_CSMR */
9648#define FB_CSMR_COUNT (6U)
9649
9650/*! @name CSCR - Chip Select Control Register */
9651/*! @{ */
9652#define FB_CSCR_BSTW_MASK (0x8U)
9653#define FB_CSCR_BSTW_SHIFT (3U)
9654/*! BSTW - Burst-Write Enable
9655 * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst writes. For example, a 32-bit write to an 8-bit port takes four byte writes.
9656 * 0b1..Enabled. Enables burst write of data larger than the specified port size, including 32-bit writes to 8- and 16-bit ports, 16-bit writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports.
9657 */
9658#define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
9659#define FB_CSCR_BSTR_MASK (0x10U)
9660#define FB_CSCR_BSTR_SHIFT (4U)
9661/*! BSTR - Burst-Read Enable
9662 * 0b0..Disabled. Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a 32-bit read from an 8-bit port is broken into four 8-bit reads.
9663 * 0b1..Enabled. Enables data burst reads larger than the specified port size, including 32-bit reads from 8- and 16-bit ports, 16-bit reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
9664 */
9665#define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
9666#define FB_CSCR_BEM_MASK (0x20U)
9667#define FB_CSCR_BEM_SHIFT (5U)
9668/*! BEM - Byte-Enable Mode
9669 * 0b0..FB_BE is asserted for data write only.
9670 * 0b1..FB_BE is asserted for data read and write accesses.
9671 */
9672#define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
9673#define FB_CSCR_PS_MASK (0xC0U)
9674#define FB_CSCR_PS_SHIFT (6U)
9675/*! PS - Port Size
9676 * 0b00..32-bit port size. Valid data is sampled and driven on FB_D[31:0].
9677 * 0b01..8-bit port size. Valid data is sampled and driven on FB_D[31:24] when BLS is 0b, or FB_D[7:0] when BLS is 1b.
9678 * 0b1x..16-bit port size. Valid data is sampled and driven on FB_D[31:16] when BLS is 0b, or FB_D[15:0] when BLS is 1b.
9679 */
9680#define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
9681#define FB_CSCR_AA_MASK (0x100U)
9682#define FB_CSCR_AA_SHIFT (8U)
9683/*! AA - Auto-Acknowledge Enable
9684 * 0b0..Disabled. No internal transfer acknowledge is asserted and the cycle is terminated externally.
9685 * 0b1..Enabled. Internal transfer acknowledge is asserted as specified by WS.
9686 */
9687#define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
9688#define FB_CSCR_BLS_MASK (0x200U)
9689#define FB_CSCR_BLS_SHIFT (9U)
9690/*! BLS - Byte-Lane Shift
9691 * 0b0..Not shifted. Data is left-aligned on FB_AD.
9692 * 0b1..Shifted. Data is right-aligned on FB_AD.
9693 */
9694#define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
9695#define FB_CSCR_WS_MASK (0xFC00U)
9696#define FB_CSCR_WS_SHIFT (10U)
9697#define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
9698#define FB_CSCR_WRAH_MASK (0x30000U)
9699#define FB_CSCR_WRAH_SHIFT (16U)
9700/*! WRAH - Write Address Hold or Deselect
9701 * 0b00..1 cycle (default for all but FB_CS0 )
9702 * 0b01..2 cycles
9703 * 0b10..3 cycles
9704 * 0b11..4 cycles (default for FB_CS0 )
9705 */
9706#define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
9707#define FB_CSCR_RDAH_MASK (0xC0000U)
9708#define FB_CSCR_RDAH_SHIFT (18U)
9709/*! RDAH - Read Address Hold or Deselect
9710 * 0b00..When AA is 1b, 1 cycle. When AA is 0b, 0 cycles.
9711 * 0b01..When AA is 1b, 2 cycles. When AA is 0b, 1 cycle.
9712 * 0b10..When AA is 1b, 3 cycles. When AA is 0b, 2 cycles.
9713 * 0b11..When AA is 1b, 4 cycles. When AA is 0b, 3 cycles.
9714 */
9715#define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
9716#define FB_CSCR_ASET_MASK (0x300000U)
9717#define FB_CSCR_ASET_SHIFT (20U)
9718/*! ASET - Address Setup
9719 * 0b00..Assert FB_CSn on the first rising clock edge after the address is asserted (default for all but FB_CS0 ).
9720 * 0b01..Assert FB_CSn on the second rising clock edge after the address is asserted.
9721 * 0b10..Assert FB_CSn on the third rising clock edge after the address is asserted.
9722 * 0b11..Assert FB_CSn on the fourth rising clock edge after the address is asserted (default for FB_CS0 ).
9723 */
9724#define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
9725#define FB_CSCR_EXTS_MASK (0x400000U)
9726#define FB_CSCR_EXTS_SHIFT (22U)
9727/*! EXTS
9728 * 0b0..Disabled. FB_TS /FB_ALE asserts for one bus clock cycle.
9729 * 0b1..Enabled. FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts.
9730 */
9731#define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
9732#define FB_CSCR_SWSEN_MASK (0x800000U)
9733#define FB_CSCR_SWSEN_SHIFT (23U)
9734/*! SWSEN - Secondary Wait State Enable
9735 * 0b0..Disabled. A number of wait states (specified by WS) are inserted before an internal transfer acknowledge is generated for all transfers.
9736 * 0b1..Enabled. A number of wait states (specified by SWS) are inserted before an internal transfer acknowledge is generated for burst transfer secondary terminations.
9737 */
9738#define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
9739#define FB_CSCR_SWS_MASK (0xFC000000U)
9740#define FB_CSCR_SWS_SHIFT (26U)
9741#define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
9742/*! @} */
9743
9744/* The count of FB_CSCR */
9745#define FB_CSCR_COUNT (6U)
9746
9747/*! @name CSPMCR - Chip Select port Multiplexing Control Register */
9748/*! @{ */
9749#define FB_CSPMCR_GROUP5_MASK (0xF000U)
9750#define FB_CSPMCR_GROUP5_SHIFT (12U)
9751/*! GROUP5 - FlexBus Signal Group 5 Multiplex control
9752 * 0b0000..FB_TA
9753 * 0b0001..FB_CS3 . You must also write 1b to CSCR[AA].
9754 * 0b0010..FB_BE_7_0 . You must also write 1b to CSCR[AA].
9755 */
9756#define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
9757#define FB_CSPMCR_GROUP4_MASK (0xF0000U)
9758#define FB_CSPMCR_GROUP4_SHIFT (16U)
9759/*! GROUP4 - FlexBus Signal Group 4 Multiplex control
9760 * 0b0000..FB_TBST
9761 * 0b0001..FB_CS2
9762 * 0b0010..FB_BE_15_8
9763 */
9764#define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
9765#define FB_CSPMCR_GROUP3_MASK (0xF00000U)
9766#define FB_CSPMCR_GROUP3_SHIFT (20U)
9767/*! GROUP3 - FlexBus Signal Group 3 Multiplex control
9768 * 0b0000..FB_CS5
9769 * 0b0001..FB_TSIZ1
9770 * 0b0010..FB_BE_23_16
9771 */
9772#define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
9773#define FB_CSPMCR_GROUP2_MASK (0xF000000U)
9774#define FB_CSPMCR_GROUP2_SHIFT (24U)
9775/*! GROUP2 - FlexBus Signal Group 2 Multiplex control
9776 * 0b0000..FB_CS4
9777 * 0b0001..FB_TSIZ0
9778 * 0b0010..FB_BE_31_24
9779 */
9780#define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
9781#define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
9782#define FB_CSPMCR_GROUP1_SHIFT (28U)
9783/*! GROUP1 - FlexBus Signal Group 1 Multiplex control
9784 * 0b0000..FB_ALE
9785 * 0b0001..FB_CS1
9786 * 0b0010..FB_TS
9787 */
9788#define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
9789/*! @} */
9790
9791
9792/*!
9793 * @}
9794 */ /* end of group FB_Register_Masks */
9795
9796
9797/* FB - Peripheral instance base addresses */
9798/** Peripheral FB base address */
9799#define FB_BASE (0x4000C000u)
9800/** Peripheral FB base pointer */
9801#define FB ((FB_Type *)FB_BASE)
9802/** Array initializer of FB peripheral base addresses */
9803#define FB_BASE_ADDRS { FB_BASE }
9804/** Array initializer of FB peripheral base pointers */
9805#define FB_BASE_PTRS { FB }
9806
9807/*!
9808 * @}
9809 */ /* end of group FB_Peripheral_Access_Layer */
9810
9811
9812/* ----------------------------------------------------------------------------
9813 -- FMC Peripheral Access Layer
9814 ---------------------------------------------------------------------------- */
9815
9816/*!
9817 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
9818 * @{
9819 */
9820
9821/** FMC - Register Layout Typedef */
9822typedef struct {
9823 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
9824 __IO uint32_t PFB01CR; /**< Flash Bank 0-1 Control Register, offset: 0x4 */
9825 __IO uint32_t PFB23CR; /**< Flash Bank 2-3 Control Register, offset: 0x8 */
9826 uint8_t RESERVED_0[244];
9827 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
9828 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
9829 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
9830 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
9831 uint8_t RESERVED_1[192];
9832 struct { /* offset: 0x200, array step: index*0x40, index2*0x10 */
9833 __IO uint32_t DATA_UM; /**< Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 */
9834 __IO uint32_t DATA_MU; /**< Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 */
9835 __IO uint32_t DATA_ML; /**< Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 */
9836 __IO uint32_t DATA_LM; /**< Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 */
9837 } SET[4][4];
9838} FMC_Type;
9839
9840/* ----------------------------------------------------------------------------
9841 -- FMC Register Masks
9842 ---------------------------------------------------------------------------- */
9843
9844/*!
9845 * @addtogroup FMC_Register_Masks FMC Register Masks
9846 * @{
9847 */
9848
9849/*! @name PFAPR - Flash Access Protection Register */
9850/*! @{ */
9851#define FMC_PFAPR_M0AP_MASK (0x3U)
9852#define FMC_PFAPR_M0AP_SHIFT (0U)
9853/*! M0AP - Master 0 Access Protection
9854 * 0b00..No access may be performed by this master
9855 * 0b01..Only read accesses may be performed by this master
9856 * 0b10..Only write accesses may be performed by this master
9857 * 0b11..Both read and write accesses may be performed by this master
9858 */
9859#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
9860#define FMC_PFAPR_M1AP_MASK (0xCU)
9861#define FMC_PFAPR_M1AP_SHIFT (2U)
9862/*! M1AP - Master 1 Access Protection
9863 * 0b00..No access may be performed by this master
9864 * 0b01..Only read accesses may be performed by this master
9865 * 0b10..Only write accesses may be performed by this master
9866 * 0b11..Both read and write accesses may be performed by this master
9867 */
9868#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
9869#define FMC_PFAPR_M2AP_MASK (0x30U)
9870#define FMC_PFAPR_M2AP_SHIFT (4U)
9871/*! M2AP - Master 2 Access Protection
9872 * 0b00..No access may be performed by this master
9873 * 0b01..Only read accesses may be performed by this master
9874 * 0b10..Only write accesses may be performed by this master
9875 * 0b11..Both read and write accesses may be performed by this master
9876 */
9877#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
9878#define FMC_PFAPR_M3AP_MASK (0xC0U)
9879#define FMC_PFAPR_M3AP_SHIFT (6U)
9880/*! M3AP - Master 3 Access Protection
9881 * 0b00..No access may be performed by this master
9882 * 0b01..Only read accesses may be performed by this master
9883 * 0b10..Only write accesses may be performed by this master
9884 * 0b11..Both read and write accesses may be performed by this master
9885 */
9886#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
9887#define FMC_PFAPR_M4AP_MASK (0x300U)
9888#define FMC_PFAPR_M4AP_SHIFT (8U)
9889/*! M4AP - Master 4 Access Protection
9890 * 0b00..No access may be performed by this master
9891 * 0b01..Only read accesses may be performed by this master
9892 * 0b10..Only write accesses may be performed by this master
9893 * 0b11..Both read and write accesses may be performed by this master
9894 */
9895#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
9896#define FMC_PFAPR_M5AP_MASK (0xC00U)
9897#define FMC_PFAPR_M5AP_SHIFT (10U)
9898/*! M5AP - Master 5 Access Protection
9899 * 0b00..No access may be performed by this master
9900 * 0b01..Only read accesses may be performed by this master
9901 * 0b10..Only write accesses may be performed by this master
9902 * 0b11..Both read and write accesses may be performed by this master
9903 */
9904#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
9905#define FMC_PFAPR_M6AP_MASK (0x3000U)
9906#define FMC_PFAPR_M6AP_SHIFT (12U)
9907/*! M6AP - Master 6 Access Protection
9908 * 0b00..No access may be performed by this master
9909 * 0b01..Only read accesses may be performed by this master
9910 * 0b10..Only write accesses may be performed by this master
9911 * 0b11..Both read and write accesses may be performed by this master
9912 */
9913#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
9914#define FMC_PFAPR_M7AP_MASK (0xC000U)
9915#define FMC_PFAPR_M7AP_SHIFT (14U)
9916/*! M7AP - Master 7 Access Protection
9917 * 0b00..No access may be performed by this master.
9918 * 0b01..Only read accesses may be performed by this master.
9919 * 0b10..Only write accesses may be performed by this master.
9920 * 0b11..Both read and write accesses may be performed by this master.
9921 */
9922#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
9923#define FMC_PFAPR_M0PFD_MASK (0x10000U)
9924#define FMC_PFAPR_M0PFD_SHIFT (16U)
9925/*! M0PFD - Master 0 Prefetch Disable
9926 * 0b0..Prefetching for this master is enabled.
9927 * 0b1..Prefetching for this master is disabled.
9928 */
9929#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
9930#define FMC_PFAPR_M1PFD_MASK (0x20000U)
9931#define FMC_PFAPR_M1PFD_SHIFT (17U)
9932/*! M1PFD - Master 1 Prefetch Disable
9933 * 0b0..Prefetching for this master is enabled.
9934 * 0b1..Prefetching for this master is disabled.
9935 */
9936#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
9937#define FMC_PFAPR_M2PFD_MASK (0x40000U)
9938#define FMC_PFAPR_M2PFD_SHIFT (18U)
9939/*! M2PFD - Master 2 Prefetch Disable
9940 * 0b0..Prefetching for this master is enabled.
9941 * 0b1..Prefetching for this master is disabled.
9942 */
9943#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
9944#define FMC_PFAPR_M3PFD_MASK (0x80000U)
9945#define FMC_PFAPR_M3PFD_SHIFT (19U)
9946/*! M3PFD - Master 3 Prefetch Disable
9947 * 0b0..Prefetching for this master is enabled.
9948 * 0b1..Prefetching for this master is disabled.
9949 */
9950#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
9951#define FMC_PFAPR_M4PFD_MASK (0x100000U)
9952#define FMC_PFAPR_M4PFD_SHIFT (20U)
9953/*! M4PFD - Master 4 Prefetch Disable
9954 * 0b0..Prefetching for this master is enabled.
9955 * 0b1..Prefetching for this master is disabled.
9956 */
9957#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
9958#define FMC_PFAPR_M5PFD_MASK (0x200000U)
9959#define FMC_PFAPR_M5PFD_SHIFT (21U)
9960/*! M5PFD - Master 5 Prefetch Disable
9961 * 0b0..Prefetching for this master is enabled.
9962 * 0b1..Prefetching for this master is disabled.
9963 */
9964#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
9965#define FMC_PFAPR_M6PFD_MASK (0x400000U)
9966#define FMC_PFAPR_M6PFD_SHIFT (22U)
9967/*! M6PFD - Master 6 Prefetch Disable
9968 * 0b0..Prefetching for this master is enabled.
9969 * 0b1..Prefetching for this master is disabled.
9970 */
9971#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
9972#define FMC_PFAPR_M7PFD_MASK (0x800000U)
9973#define FMC_PFAPR_M7PFD_SHIFT (23U)
9974/*! M7PFD - Master 7 Prefetch Disable
9975 * 0b0..Prefetching for this master is enabled.
9976 * 0b1..Prefetching for this master is disabled.
9977 */
9978#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
9979/*! @} */
9980
9981/*! @name PFB01CR - Flash Bank 0-1 Control Register */
9982/*! @{ */
9983#define FMC_PFB01CR_RFU_MASK (0x1U)
9984#define FMC_PFB01CR_RFU_SHIFT (0U)
9985#define FMC_PFB01CR_RFU(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_RFU_SHIFT)) & FMC_PFB01CR_RFU_MASK)
9986#define FMC_PFB01CR_B0IPE_MASK (0x2U)
9987#define FMC_PFB01CR_B0IPE_SHIFT (1U)
9988/*! B0IPE - Bank 0 Instruction Prefetch Enable
9989 * 0b0..Do not prefetch in response to instruction fetches.
9990 * 0b1..Enable prefetches in response to instruction fetches.
9991 */
9992#define FMC_PFB01CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0IPE_SHIFT)) & FMC_PFB01CR_B0IPE_MASK)
9993#define FMC_PFB01CR_B0DPE_MASK (0x4U)
9994#define FMC_PFB01CR_B0DPE_SHIFT (2U)
9995/*! B0DPE - Bank 0 Data Prefetch Enable
9996 * 0b0..Do not prefetch in response to data references.
9997 * 0b1..Enable prefetches in response to data references.
9998 */
9999#define FMC_PFB01CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DPE_SHIFT)) & FMC_PFB01CR_B0DPE_MASK)
10000#define FMC_PFB01CR_B0ICE_MASK (0x8U)
10001#define FMC_PFB01CR_B0ICE_SHIFT (3U)
10002/*! B0ICE - Bank 0 Instruction Cache Enable
10003 * 0b0..Do not cache instruction fetches.
10004 * 0b1..Cache instruction fetches.
10005 */
10006#define FMC_PFB01CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0ICE_SHIFT)) & FMC_PFB01CR_B0ICE_MASK)
10007#define FMC_PFB01CR_B0DCE_MASK (0x10U)
10008#define FMC_PFB01CR_B0DCE_SHIFT (4U)
10009/*! B0DCE - Bank 0 Data Cache Enable
10010 * 0b0..Do not cache data references.
10011 * 0b1..Cache data references.
10012 */
10013#define FMC_PFB01CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DCE_SHIFT)) & FMC_PFB01CR_B0DCE_MASK)
10014#define FMC_PFB01CR_CRC_MASK (0xE0U)
10015#define FMC_PFB01CR_CRC_SHIFT (5U)
10016/*! CRC - Cache Replacement Control
10017 * 0b000..LRU replacement algorithm per set across all four ways
10018 * 0b001..Reserved
10019 * 0b010..Independent LRU with ways [0-1] for ifetches, [2-3] for data
10020 * 0b011..Independent LRU with ways [0-2] for ifetches, [3] for data
10021 * 0b1xx..Reserved
10022 */
10023#define FMC_PFB01CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CRC_SHIFT)) & FMC_PFB01CR_CRC_MASK)
10024#define FMC_PFB01CR_B0MW_MASK (0x60000U)
10025#define FMC_PFB01CR_B0MW_SHIFT (17U)
10026/*! B0MW - Bank 0 Memory Width
10027 * 0b00..32 bits
10028 * 0b01..64 bits
10029 * 0b10..128 bits
10030 * 0b11..Reserved
10031 */
10032#define FMC_PFB01CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0MW_SHIFT)) & FMC_PFB01CR_B0MW_MASK)
10033#define FMC_PFB01CR_S_B_INV_MASK (0x80000U)
10034#define FMC_PFB01CR_S_B_INV_SHIFT (19U)
10035/*! S_B_INV - Invalidate Prefetch Speculation Buffer
10036 * 0b0..Speculation buffer is not affected
10037 * 0b1..Invalidate (clear) speculation buffer
10038 */
10039#define FMC_PFB01CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_S_B_INV_SHIFT)) & FMC_PFB01CR_S_B_INV_MASK)
10040#define FMC_PFB01CR_CINV_WAY_MASK (0xF00000U)
10041#define FMC_PFB01CR_CINV_WAY_SHIFT (20U)
10042/*! CINV_WAY - Cache Invalidate Way x
10043 * 0b0000..No cache way invalidation for the corresponding cache
10044 * 0b0001..Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
10045 */
10046#define FMC_PFB01CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CINV_WAY_SHIFT)) & FMC_PFB01CR_CINV_WAY_MASK)
10047#define FMC_PFB01CR_CLCK_WAY_MASK (0xF000000U)
10048#define FMC_PFB01CR_CLCK_WAY_SHIFT (24U)
10049/*! CLCK_WAY - Cache Lock Way x
10050 * 0b0000..Cache way is unlocked and may be displaced
10051 * 0b0001..Cache way is locked and its contents are not displaced
10052 */
10053#define FMC_PFB01CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CLCK_WAY_SHIFT)) & FMC_PFB01CR_CLCK_WAY_MASK)
10054#define FMC_PFB01CR_B0RWSC_MASK (0xF0000000U)
10055#define FMC_PFB01CR_B0RWSC_SHIFT (28U)
10056#define FMC_PFB01CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0RWSC_SHIFT)) & FMC_PFB01CR_B0RWSC_MASK)
10057/*! @} */
10058
10059/*! @name PFB23CR - Flash Bank 2-3 Control Register */
10060/*! @{ */
10061#define FMC_PFB23CR_RFU_MASK (0x1U)
10062#define FMC_PFB23CR_RFU_SHIFT (0U)
10063#define FMC_PFB23CR_RFU(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_RFU_SHIFT)) & FMC_PFB23CR_RFU_MASK)
10064#define FMC_PFB23CR_B1IPE_MASK (0x2U)
10065#define FMC_PFB23CR_B1IPE_SHIFT (1U)
10066/*! B1IPE - Bank 1 Instruction Prefetch Enable
10067 * 0b0..Do not prefetch in response to instruction fetches.
10068 * 0b1..Enable prefetches in response to instruction fetches.
10069 */
10070#define FMC_PFB23CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1IPE_SHIFT)) & FMC_PFB23CR_B1IPE_MASK)
10071#define FMC_PFB23CR_B1DPE_MASK (0x4U)
10072#define FMC_PFB23CR_B1DPE_SHIFT (2U)
10073/*! B1DPE - Bank 1 Data Prefetch Enable
10074 * 0b0..Do not prefetch in response to data references.
10075 * 0b1..Enable prefetches in response to data references.
10076 */
10077#define FMC_PFB23CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DPE_SHIFT)) & FMC_PFB23CR_B1DPE_MASK)
10078#define FMC_PFB23CR_B1ICE_MASK (0x8U)
10079#define FMC_PFB23CR_B1ICE_SHIFT (3U)
10080/*! B1ICE - Bank 1 Instruction Cache Enable
10081 * 0b0..Do not cache instruction fetches.
10082 * 0b1..Cache instruction fetches.
10083 */
10084#define FMC_PFB23CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1ICE_SHIFT)) & FMC_PFB23CR_B1ICE_MASK)
10085#define FMC_PFB23CR_B1DCE_MASK (0x10U)
10086#define FMC_PFB23CR_B1DCE_SHIFT (4U)
10087/*! B1DCE - Bank 1 Data Cache Enable
10088 * 0b0..Do not cache data references.
10089 * 0b1..Cache data references.
10090 */
10091#define FMC_PFB23CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DCE_SHIFT)) & FMC_PFB23CR_B1DCE_MASK)
10092#define FMC_PFB23CR_B1MW_MASK (0x60000U)
10093#define FMC_PFB23CR_B1MW_SHIFT (17U)
10094/*! B1MW - Bank 1 Memory Width
10095 * 0b00..32 bits
10096 * 0b01..64 bits
10097 * 0b10..128 bits
10098 * 0b11..Reserved
10099 */
10100#define FMC_PFB23CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1MW_SHIFT)) & FMC_PFB23CR_B1MW_MASK)
10101#define FMC_PFB23CR_B1RWSC_MASK (0xF0000000U)
10102#define FMC_PFB23CR_B1RWSC_SHIFT (28U)
10103#define FMC_PFB23CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1RWSC_SHIFT)) & FMC_PFB23CR_B1RWSC_MASK)
10104/*! @} */
10105
10106/*! @name TAGVDW0S - Cache Tag Storage */
10107/*! @{ */
10108#define FMC_TAGVDW0S_valid_MASK (0x1U)
10109#define FMC_TAGVDW0S_valid_SHIFT (0U)
10110#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
10111#define FMC_TAGVDW0S_tag_MASK (0x3FFFC0U)
10112#define FMC_TAGVDW0S_tag_SHIFT (6U)
10113#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
10114/*! @} */
10115
10116/* The count of FMC_TAGVDW0S */
10117#define FMC_TAGVDW0S_COUNT (4U)
10118
10119/*! @name TAGVDW1S - Cache Tag Storage */
10120/*! @{ */
10121#define FMC_TAGVDW1S_valid_MASK (0x1U)
10122#define FMC_TAGVDW1S_valid_SHIFT (0U)
10123#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
10124#define FMC_TAGVDW1S_tag_MASK (0x3FFFC0U)
10125#define FMC_TAGVDW1S_tag_SHIFT (6U)
10126#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
10127/*! @} */
10128
10129/* The count of FMC_TAGVDW1S */
10130#define FMC_TAGVDW1S_COUNT (4U)
10131
10132/*! @name TAGVDW2S - Cache Tag Storage */
10133/*! @{ */
10134#define FMC_TAGVDW2S_valid_MASK (0x1U)
10135#define FMC_TAGVDW2S_valid_SHIFT (0U)
10136#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
10137#define FMC_TAGVDW2S_tag_MASK (0x3FFFC0U)
10138#define FMC_TAGVDW2S_tag_SHIFT (6U)
10139#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
10140/*! @} */
10141
10142/* The count of FMC_TAGVDW2S */
10143#define FMC_TAGVDW2S_COUNT (4U)
10144
10145/*! @name TAGVDW3S - Cache Tag Storage */
10146/*! @{ */
10147#define FMC_TAGVDW3S_valid_MASK (0x1U)
10148#define FMC_TAGVDW3S_valid_SHIFT (0U)
10149#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
10150#define FMC_TAGVDW3S_tag_MASK (0x3FFFC0U)
10151#define FMC_TAGVDW3S_tag_SHIFT (6U)
10152#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
10153/*! @} */
10154
10155/* The count of FMC_TAGVDW3S */
10156#define FMC_TAGVDW3S_COUNT (4U)
10157
10158/*! @name DATA_UM - Cache Data Storage (uppermost word) */
10159/*! @{ */
10160#define FMC_DATA_UM_data_MASK (0xFFFFFFFFU)
10161#define FMC_DATA_UM_data_SHIFT (0U)
10162#define FMC_DATA_UM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK)
10163/*! @} */
10164
10165/* The count of FMC_DATA_UM */
10166#define FMC_DATA_UM_COUNT (4U)
10167
10168/* The count of FMC_DATA_UM */
10169#define FMC_DATA_UM_COUNT2 (4U)
10170
10171/*! @name DATA_MU - Cache Data Storage (mid-upper word) */
10172/*! @{ */
10173#define FMC_DATA_MU_data_MASK (0xFFFFFFFFU)
10174#define FMC_DATA_MU_data_SHIFT (0U)
10175#define FMC_DATA_MU_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK)
10176/*! @} */
10177
10178/* The count of FMC_DATA_MU */
10179#define FMC_DATA_MU_COUNT (4U)
10180
10181/* The count of FMC_DATA_MU */
10182#define FMC_DATA_MU_COUNT2 (4U)
10183
10184/*! @name DATA_ML - Cache Data Storage (mid-lower word) */
10185/*! @{ */
10186#define FMC_DATA_ML_data_MASK (0xFFFFFFFFU)
10187#define FMC_DATA_ML_data_SHIFT (0U)
10188#define FMC_DATA_ML_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK)
10189/*! @} */
10190
10191/* The count of FMC_DATA_ML */
10192#define FMC_DATA_ML_COUNT (4U)
10193
10194/* The count of FMC_DATA_ML */
10195#define FMC_DATA_ML_COUNT2 (4U)
10196
10197/*! @name DATA_LM - Cache Data Storage (lowermost word) */
10198/*! @{ */
10199#define FMC_DATA_LM_data_MASK (0xFFFFFFFFU)
10200#define FMC_DATA_LM_data_SHIFT (0U)
10201#define FMC_DATA_LM_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK)
10202/*! @} */
10203
10204/* The count of FMC_DATA_LM */
10205#define FMC_DATA_LM_COUNT (4U)
10206
10207/* The count of FMC_DATA_LM */
10208#define FMC_DATA_LM_COUNT2 (4U)
10209
10210
10211/*!
10212 * @}
10213 */ /* end of group FMC_Register_Masks */
10214
10215
10216/* FMC - Peripheral instance base addresses */
10217/** Peripheral FMC base address */
10218#define FMC_BASE (0x4001F000u)
10219/** Peripheral FMC base pointer */
10220#define FMC ((FMC_Type *)FMC_BASE)
10221/** Array initializer of FMC peripheral base addresses */
10222#define FMC_BASE_ADDRS { FMC_BASE }
10223/** Array initializer of FMC peripheral base pointers */
10224#define FMC_BASE_PTRS { FMC }
10225
10226/*!
10227 * @}
10228 */ /* end of group FMC_Peripheral_Access_Layer */
10229
10230
10231/* ----------------------------------------------------------------------------
10232 -- FTFE Peripheral Access Layer
10233 ---------------------------------------------------------------------------- */
10234
10235/*!
10236 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
10237 * @{
10238 */
10239
10240/** FTFE - Register Layout Typedef */
10241typedef struct {
10242 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
10243 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
10244 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
10245 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
10246 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
10247 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
10248 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
10249 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
10250 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
10251 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
10252 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
10253 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
10254 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
10255 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
10256 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
10257 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
10258 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
10259 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
10260 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
10261 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
10262 uint8_t RESERVED_0[2];
10263 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
10264 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
10265 __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
10266 __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
10267 __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
10268 __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
10269 __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
10270 __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
10271 __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
10272 __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
10273 __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
10274 __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
10275 __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
10276 __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
10277 __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
10278 __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
10279 __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
10280 __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
10281 __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
10282 uint8_t RESERVED_1[2];
10283 __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
10284} FTFE_Type;
10285
10286/* ----------------------------------------------------------------------------
10287 -- FTFE Register Masks
10288 ---------------------------------------------------------------------------- */
10289
10290/*!
10291 * @addtogroup FTFE_Register_Masks FTFE Register Masks
10292 * @{
10293 */
10294
10295/*! @name FSTAT - Flash Status Register */
10296/*! @{ */
10297#define FTFE_FSTAT_MGSTAT0_MASK (0x1U)
10298#define FTFE_FSTAT_MGSTAT0_SHIFT (0U)
10299#define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
10300#define FTFE_FSTAT_FPVIOL_MASK (0x10U)
10301#define FTFE_FSTAT_FPVIOL_SHIFT (4U)
10302/*! FPVIOL - Flash Protection Violation Flag
10303 * 0b0..No protection violation detected
10304 * 0b1..Protection violation detected
10305 */
10306#define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
10307#define FTFE_FSTAT_ACCERR_MASK (0x20U)
10308#define FTFE_FSTAT_ACCERR_SHIFT (5U)
10309/*! ACCERR - Flash Access Error Flag
10310 * 0b0..No access error detected
10311 * 0b1..Access error detected
10312 */
10313#define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
10314#define FTFE_FSTAT_RDCOLERR_MASK (0x40U)
10315#define FTFE_FSTAT_RDCOLERR_SHIFT (6U)
10316/*! RDCOLERR - FTFE Read Collision Error Flag
10317 * 0b0..No collision error detected
10318 * 0b1..Collision error detected
10319 */
10320#define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
10321#define FTFE_FSTAT_CCIF_MASK (0x80U)
10322#define FTFE_FSTAT_CCIF_SHIFT (7U)
10323/*! CCIF - Command Complete Interrupt Flag
10324 * 0b0..FTFE command or EEPROM file system operation in progress
10325 * 0b1..FTFE command or EEPROM file system operation has completed
10326 */
10327#define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
10328/*! @} */
10329
10330/*! @name FCNFG - Flash Configuration Register */
10331/*! @{ */
10332#define FTFE_FCNFG_EEERDY_MASK (0x1U)
10333#define FTFE_FCNFG_EEERDY_SHIFT (0U)
10334/*! EEERDY
10335 * 0b0..For devices with FlexNVM: FlexRAM is not available for EEPROM operation For devices without FlexNVM: See RAMRDY for availability of programming acceleration RAM
10336 * 0b1..For devices with FlexNVM: FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup For devices without FlexNVM: Reserved
10337 */
10338#define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
10339#define FTFE_FCNFG_RAMRDY_MASK (0x2U)
10340#define FTFE_FCNFG_RAMRDY_SHIFT (1U)
10341/*! RAMRDY - RAM Ready
10342 * 0b0..For devices with FlexNVM: FlexRAM is not available for traditional RAM access For devices without FlexNVM: Programming acceleration RAM is not available
10343 * 0b1..For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations For devices without FlexNVM: Programming acceleration RAM is available
10344 */
10345#define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
10346#define FTFE_FCNFG_PFLSH_MASK (0x4U)
10347#define FTFE_FCNFG_PFLSH_SHIFT (2U)
10348/*! PFLSH - FTFE configuration
10349 * 0b0..For devices with FlexNVM: FTFE configuration supports two or three program flash blocks and two FlexNVM blocks For devices with program flash only: Reserved
10350 * 0b1..For devices with FlexNVM: Reserved For devices with program flash only: FTFE configuration supports four program flash blocks
10351 */
10352#define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
10353#define FTFE_FCNFG_SWAP_MASK (0x8U)
10354#define FTFE_FCNFG_SWAP_SHIFT (3U)
10355/*! SWAP - Swap
10356 * 0b0..For devices with FlexNVM: Program flash 0 block is located at relative address 0x0000 For devices with program flash only: Program flash 0/1 blocks are located at relative address 0x0000
10357 * 0b1..For devices with FlexNVM: Reserved For devices with program flash only: Program flash 2/3 blocks are located at relative address 0x0000
10358 */
10359#define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
10360#define FTFE_FCNFG_ERSSUSP_MASK (0x10U)
10361#define FTFE_FCNFG_ERSSUSP_SHIFT (4U)
10362/*! ERSSUSP - Erase Suspend
10363 * 0b0..No suspend requested
10364 * 0b1..Suspend the current Erase Flash Sector command execution
10365 */
10366#define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
10367#define FTFE_FCNFG_ERSAREQ_MASK (0x20U)
10368#define FTFE_FCNFG_ERSAREQ_SHIFT (5U)
10369/*! ERSAREQ - Erase All Request
10370 * 0b0..No request or request complete
10371 * 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state
10372 */
10373#define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
10374#define FTFE_FCNFG_RDCOLLIE_MASK (0x40U)
10375#define FTFE_FCNFG_RDCOLLIE_SHIFT (6U)
10376/*! RDCOLLIE - Read Collision Error Interrupt Enable
10377 * 0b0..Read collision error interrupt disabled
10378 * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]).
10379 */
10380#define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
10381#define FTFE_FCNFG_CCIE_MASK (0x80U)
10382#define FTFE_FCNFG_CCIE_SHIFT (7U)
10383/*! CCIE - Command Complete Interrupt Enable
10384 * 0b0..Command complete interrupt disabled
10385 * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
10386 */
10387#define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
10388/*! @} */
10389
10390/*! @name FSEC - Flash Security Register */
10391/*! @{ */
10392#define FTFE_FSEC_SEC_MASK (0x3U)
10393#define FTFE_FSEC_SEC_SHIFT (0U)
10394/*! SEC - Flash Security
10395 * 0b00..MCU security status is secure
10396 * 0b01..MCU security status is secure
10397 * 0b10..MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.)
10398 * 0b11..MCU security status is secure
10399 */
10400#define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
10401#define FTFE_FSEC_FSLACC_MASK (0xCU)
10402#define FTFE_FSEC_FSLACC_SHIFT (2U)
10403/*! FSLACC - Freescale Failure Analysis Access Code
10404 * 0b00..Freescale factory access granted
10405 * 0b01..Freescale factory access denied
10406 * 0b10..Freescale factory access denied
10407 * 0b11..Freescale factory access granted
10408 */
10409#define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
10410#define FTFE_FSEC_MEEN_MASK (0x30U)
10411#define FTFE_FSEC_MEEN_SHIFT (4U)
10412/*! MEEN - Mass Erase Enable Bits
10413 * 0b00..Mass erase is enabled
10414 * 0b01..Mass erase is enabled
10415 * 0b10..Mass erase is disabled
10416 * 0b11..Mass erase is enabled
10417 */
10418#define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
10419#define FTFE_FSEC_KEYEN_MASK (0xC0U)
10420#define FTFE_FSEC_KEYEN_SHIFT (6U)
10421/*! KEYEN - Backdoor Key Security Enable
10422 * 0b00..Backdoor key access disabled
10423 * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
10424 * 0b10..Backdoor key access enabled
10425 * 0b11..Backdoor key access disabled
10426 */
10427#define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
10428/*! @} */
10429
10430/*! @name FOPT - Flash Option Register */
10431/*! @{ */
10432#define FTFE_FOPT_OPT_MASK (0xFFU)
10433#define FTFE_FOPT_OPT_SHIFT (0U)
10434#define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
10435/*! @} */
10436
10437/*! @name FCCOB3 - Flash Common Command Object Registers */
10438/*! @{ */
10439#define FTFE_FCCOB3_CCOBn_MASK (0xFFU)
10440#define FTFE_FCCOB3_CCOBn_SHIFT (0U)
10441#define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
10442/*! @} */
10443
10444/*! @name FCCOB2 - Flash Common Command Object Registers */
10445/*! @{ */
10446#define FTFE_FCCOB2_CCOBn_MASK (0xFFU)
10447#define FTFE_FCCOB2_CCOBn_SHIFT (0U)
10448#define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
10449/*! @} */
10450
10451/*! @name FCCOB1 - Flash Common Command Object Registers */
10452/*! @{ */
10453#define FTFE_FCCOB1_CCOBn_MASK (0xFFU)
10454#define FTFE_FCCOB1_CCOBn_SHIFT (0U)
10455#define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
10456/*! @} */
10457
10458/*! @name FCCOB0 - Flash Common Command Object Registers */
10459/*! @{ */
10460#define FTFE_FCCOB0_CCOBn_MASK (0xFFU)
10461#define FTFE_FCCOB0_CCOBn_SHIFT (0U)
10462#define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
10463/*! @} */
10464
10465/*! @name FCCOB7 - Flash Common Command Object Registers */
10466/*! @{ */
10467#define FTFE_FCCOB7_CCOBn_MASK (0xFFU)
10468#define FTFE_FCCOB7_CCOBn_SHIFT (0U)
10469#define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
10470/*! @} */
10471
10472/*! @name FCCOB6 - Flash Common Command Object Registers */
10473/*! @{ */
10474#define FTFE_FCCOB6_CCOBn_MASK (0xFFU)
10475#define FTFE_FCCOB6_CCOBn_SHIFT (0U)
10476#define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
10477/*! @} */
10478
10479/*! @name FCCOB5 - Flash Common Command Object Registers */
10480/*! @{ */
10481#define FTFE_FCCOB5_CCOBn_MASK (0xFFU)
10482#define FTFE_FCCOB5_CCOBn_SHIFT (0U)
10483#define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
10484/*! @} */
10485
10486/*! @name FCCOB4 - Flash Common Command Object Registers */
10487/*! @{ */
10488#define FTFE_FCCOB4_CCOBn_MASK (0xFFU)
10489#define FTFE_FCCOB4_CCOBn_SHIFT (0U)
10490#define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
10491/*! @} */
10492
10493/*! @name FCCOBB - Flash Common Command Object Registers */
10494/*! @{ */
10495#define FTFE_FCCOBB_CCOBn_MASK (0xFFU)
10496#define FTFE_FCCOBB_CCOBn_SHIFT (0U)
10497#define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
10498/*! @} */
10499
10500/*! @name FCCOBA - Flash Common Command Object Registers */
10501/*! @{ */
10502#define FTFE_FCCOBA_CCOBn_MASK (0xFFU)
10503#define FTFE_FCCOBA_CCOBn_SHIFT (0U)
10504#define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
10505/*! @} */
10506
10507/*! @name FCCOB9 - Flash Common Command Object Registers */
10508/*! @{ */
10509#define FTFE_FCCOB9_CCOBn_MASK (0xFFU)
10510#define FTFE_FCCOB9_CCOBn_SHIFT (0U)
10511#define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
10512/*! @} */
10513
10514/*! @name FCCOB8 - Flash Common Command Object Registers */
10515/*! @{ */
10516#define FTFE_FCCOB8_CCOBn_MASK (0xFFU)
10517#define FTFE_FCCOB8_CCOBn_SHIFT (0U)
10518#define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
10519/*! @} */
10520
10521/*! @name FPROT3 - Program Flash Protection Registers */
10522/*! @{ */
10523#define FTFE_FPROT3_PROT_MASK (0xFFU)
10524#define FTFE_FPROT3_PROT_SHIFT (0U)
10525/*! PROT - Program Flash Region Protect
10526 * 0b00000000..Program flash region is protected.
10527 * 0b00000001..Program flash region is not protected
10528 */
10529#define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
10530/*! @} */
10531
10532/*! @name FPROT2 - Program Flash Protection Registers */
10533/*! @{ */
10534#define FTFE_FPROT2_PROT_MASK (0xFFU)
10535#define FTFE_FPROT2_PROT_SHIFT (0U)
10536/*! PROT - Program Flash Region Protect
10537 * 0b00000000..Program flash region is protected.
10538 * 0b00000001..Program flash region is not protected
10539 */
10540#define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
10541/*! @} */
10542
10543/*! @name FPROT1 - Program Flash Protection Registers */
10544/*! @{ */
10545#define FTFE_FPROT1_PROT_MASK (0xFFU)
10546#define FTFE_FPROT1_PROT_SHIFT (0U)
10547/*! PROT - Program Flash Region Protect
10548 * 0b00000000..Program flash region is protected.
10549 * 0b00000001..Program flash region is not protected
10550 */
10551#define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
10552/*! @} */
10553
10554/*! @name FPROT0 - Program Flash Protection Registers */
10555/*! @{ */
10556#define FTFE_FPROT0_PROT_MASK (0xFFU)
10557#define FTFE_FPROT0_PROT_SHIFT (0U)
10558/*! PROT - Program Flash Region Protect
10559 * 0b00000000..Program flash region is protected.
10560 * 0b00000001..Program flash region is not protected
10561 */
10562#define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
10563/*! @} */
10564
10565/*! @name FEPROT - EEPROM Protection Register */
10566/*! @{ */
10567#define FTFE_FEPROT_EPROT_MASK (0xFFU)
10568#define FTFE_FEPROT_EPROT_SHIFT (0U)
10569/*! EPROT - EEPROM Region Protect
10570 * 0b00000000..For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is protected
10571 * 0b00000001..For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is not protected
10572 */
10573#define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
10574/*! @} */
10575
10576/*! @name FDPROT - Data Flash Protection Register */
10577/*! @{ */
10578#define FTFE_FDPROT_DPROT_MASK (0xFFU)
10579#define FTFE_FDPROT_DPROT_SHIFT (0U)
10580/*! DPROT - Data Flash Region Protect
10581 * 0b00000000..Data Flash region is protected
10582 * 0b00000001..Data Flash region is not protected
10583 */
10584#define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
10585/*! @} */
10586
10587/*! @name XACCH3 - Execute-only Access Registers */
10588/*! @{ */
10589#define FTFE_XACCH3_XA_MASK (0xFFU)
10590#define FTFE_XACCH3_XA_SHIFT (0U)
10591/*! XA - Execute-only access control
10592 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
10593 * 0b00000001..Associated segment is accessible as data or in execute mode
10594 */
10595#define FTFE_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK)
10596/*! @} */
10597
10598/*! @name XACCH2 - Execute-only Access Registers */
10599/*! @{ */
10600#define FTFE_XACCH2_XA_MASK (0xFFU)
10601#define FTFE_XACCH2_XA_SHIFT (0U)
10602/*! XA - Execute-only access control
10603 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
10604 * 0b00000001..Associated segment is accessible as data or in execute mode
10605 */
10606#define FTFE_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK)
10607/*! @} */
10608
10609/*! @name XACCH1 - Execute-only Access Registers */
10610/*! @{ */
10611#define FTFE_XACCH1_XA_MASK (0xFFU)
10612#define FTFE_XACCH1_XA_SHIFT (0U)
10613/*! XA - Execute-only access control
10614 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
10615 * 0b00000001..Associated segment is accessible as data or in execute mode
10616 */
10617#define FTFE_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK)
10618/*! @} */
10619
10620/*! @name XACCH0 - Execute-only Access Registers */
10621/*! @{ */
10622#define FTFE_XACCH0_XA_MASK (0xFFU)
10623#define FTFE_XACCH0_XA_SHIFT (0U)
10624/*! XA - Execute-only access control
10625 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
10626 * 0b00000001..Associated segment is accessible as data or in execute mode
10627 */
10628#define FTFE_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)
10629/*! @} */
10630
10631/*! @name XACCL3 - Execute-only Access Registers */
10632/*! @{ */
10633#define FTFE_XACCL3_XA_MASK (0xFFU)
10634#define FTFE_XACCL3_XA_SHIFT (0U)
10635/*! XA - Execute-only access control
10636 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
10637 * 0b00000001..Associated segment is accessible as data or in execute mode
10638 */
10639#define FTFE_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK)
10640/*! @} */
10641
10642/*! @name XACCL2 - Execute-only Access Registers */
10643/*! @{ */
10644#define FTFE_XACCL2_XA_MASK (0xFFU)
10645#define FTFE_XACCL2_XA_SHIFT (0U)
10646/*! XA - Execute-only access control
10647 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
10648 * 0b00000001..Associated segment is accessible as data or in execute mode
10649 */
10650#define FTFE_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK)
10651/*! @} */
10652
10653/*! @name XACCL1 - Execute-only Access Registers */
10654/*! @{ */
10655#define FTFE_XACCL1_XA_MASK (0xFFU)
10656#define FTFE_XACCL1_XA_SHIFT (0U)
10657/*! XA - Execute-only access control
10658 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
10659 * 0b00000001..Associated segment is accessible as data or in execute mode
10660 */
10661#define FTFE_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK)
10662/*! @} */
10663
10664/*! @name XACCL0 - Execute-only Access Registers */
10665/*! @{ */
10666#define FTFE_XACCL0_XA_MASK (0xFFU)
10667#define FTFE_XACCL0_XA_SHIFT (0U)
10668/*! XA - Execute-only access control
10669 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
10670 * 0b00000001..Associated segment is accessible as data or in execute mode
10671 */
10672#define FTFE_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK)
10673/*! @} */
10674
10675/*! @name SACCH3 - Supervisor-only Access Registers */
10676/*! @{ */
10677#define FTFE_SACCH3_SA_MASK (0xFFU)
10678#define FTFE_SACCH3_SA_SHIFT (0U)
10679/*! SA - Supervisor-only access control
10680 * 0b00000000..Associated segment is accessible in supervisor mode only
10681 * 0b00000001..Associated segment is accessible in user or supervisor mode
10682 */
10683#define FTFE_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)
10684/*! @} */
10685
10686/*! @name SACCH2 - Supervisor-only Access Registers */
10687/*! @{ */
10688#define FTFE_SACCH2_SA_MASK (0xFFU)
10689#define FTFE_SACCH2_SA_SHIFT (0U)
10690/*! SA - Supervisor-only access control
10691 * 0b00000000..Associated segment is accessible in supervisor mode only
10692 * 0b00000001..Associated segment is accessible in user or supervisor mode
10693 */
10694#define FTFE_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)
10695/*! @} */
10696
10697/*! @name SACCH1 - Supervisor-only Access Registers */
10698/*! @{ */
10699#define FTFE_SACCH1_SA_MASK (0xFFU)
10700#define FTFE_SACCH1_SA_SHIFT (0U)
10701/*! SA - Supervisor-only access control
10702 * 0b00000000..Associated segment is accessible in supervisor mode only
10703 * 0b00000001..Associated segment is accessible in user or supervisor mode
10704 */
10705#define FTFE_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)
10706/*! @} */
10707
10708/*! @name SACCH0 - Supervisor-only Access Registers */
10709/*! @{ */
10710#define FTFE_SACCH0_SA_MASK (0xFFU)
10711#define FTFE_SACCH0_SA_SHIFT (0U)
10712/*! SA - Supervisor-only access control
10713 * 0b00000000..Associated segment is accessible in supervisor mode only
10714 * 0b00000001..Associated segment is accessible in user or supervisor mode
10715 */
10716#define FTFE_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)
10717/*! @} */
10718
10719/*! @name SACCL3 - Supervisor-only Access Registers */
10720/*! @{ */
10721#define FTFE_SACCL3_SA_MASK (0xFFU)
10722#define FTFE_SACCL3_SA_SHIFT (0U)
10723/*! SA - Supervisor-only access control
10724 * 0b00000000..Associated segment is accessible in supervisor mode only
10725 * 0b00000001..Associated segment is accessible in user or supervisor mode
10726 */
10727#define FTFE_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)
10728/*! @} */
10729
10730/*! @name SACCL2 - Supervisor-only Access Registers */
10731/*! @{ */
10732#define FTFE_SACCL2_SA_MASK (0xFFU)
10733#define FTFE_SACCL2_SA_SHIFT (0U)
10734/*! SA - Supervisor-only access control
10735 * 0b00000000..Associated segment is accessible in supervisor mode only
10736 * 0b00000001..Associated segment is accessible in user or supervisor mode
10737 */
10738#define FTFE_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)
10739/*! @} */
10740
10741/*! @name SACCL1 - Supervisor-only Access Registers */
10742/*! @{ */
10743#define FTFE_SACCL1_SA_MASK (0xFFU)
10744#define FTFE_SACCL1_SA_SHIFT (0U)
10745/*! SA - Supervisor-only access control
10746 * 0b00000000..Associated segment is accessible in supervisor mode only
10747 * 0b00000001..Associated segment is accessible in user or supervisor mode
10748 */
10749#define FTFE_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)
10750/*! @} */
10751
10752/*! @name SACCL0 - Supervisor-only Access Registers */
10753/*! @{ */
10754#define FTFE_SACCL0_SA_MASK (0xFFU)
10755#define FTFE_SACCL0_SA_SHIFT (0U)
10756/*! SA - Supervisor-only access control
10757 * 0b00000000..Associated segment is accessible in supervisor mode only
10758 * 0b00000001..Associated segment is accessible in user or supervisor mode
10759 */
10760#define FTFE_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)
10761/*! @} */
10762
10763/*! @name FACSS - Flash Access Segment Size Register */
10764/*! @{ */
10765#define FTFE_FACSS_SGSIZE_MASK (0xFFU)
10766#define FTFE_FACSS_SGSIZE_SHIFT (0U)
10767#define FTFE_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK)
10768/*! @} */
10769
10770/*! @name FACSN - Flash Access Segment Number Register */
10771/*! @{ */
10772#define FTFE_FACSN_NUMSG_MASK (0xFFU)
10773#define FTFE_FACSN_NUMSG_SHIFT (0U)
10774/*! NUMSG - Number of Segments Indicator
10775 * 0b00110000..Program flash memory is divided into 48 segments (768 Kbytes, 1.5 Mbytes)
10776 * 0b01000000..Program flash memory is divided into 64 segments (512 Kbytes, 1 Mbyte, 2 Mbytes)
10777 */
10778#define FTFE_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)
10779/*! @} */
10780
10781
10782/*!
10783 * @}
10784 */ /* end of group FTFE_Register_Masks */
10785
10786
10787/* FTFE - Peripheral instance base addresses */
10788/** Peripheral FTFE base address */
10789#define FTFE_BASE (0x40020000u)
10790/** Peripheral FTFE base pointer */
10791#define FTFE ((FTFE_Type *)FTFE_BASE)
10792/** Array initializer of FTFE peripheral base addresses */
10793#define FTFE_BASE_ADDRS { FTFE_BASE }
10794/** Array initializer of FTFE peripheral base pointers */
10795#define FTFE_BASE_PTRS { FTFE }
10796/** Interrupt vectors for the FTFE peripheral type */
10797#define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
10798#define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
10799
10800/*!
10801 * @}
10802 */ /* end of group FTFE_Peripheral_Access_Layer */
10803
10804
10805/* ----------------------------------------------------------------------------
10806 -- FTM Peripheral Access Layer
10807 ---------------------------------------------------------------------------- */
10808
10809/*!
10810 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
10811 * @{
10812 */
10813
10814/** FTM - Register Layout Typedef */
10815typedef struct {
10816 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
10817 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
10818 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
10819 struct { /* offset: 0xC, array step: 0x8 */
10820 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
10821 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
10822 } CONTROLS[8];
10823 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
10824 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
10825 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
10826 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
10827 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
10828 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
10829 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
10830 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
10831 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
10832 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
10833 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
10834 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
10835 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
10836 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
10837 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
10838 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
10839 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
10840 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
10841 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
10842 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
10843} FTM_Type;
10844
10845/* ----------------------------------------------------------------------------
10846 -- FTM Register Masks
10847 ---------------------------------------------------------------------------- */
10848
10849/*!
10850 * @addtogroup FTM_Register_Masks FTM Register Masks
10851 * @{
10852 */
10853
10854/*! @name SC - Status And Control */
10855/*! @{ */
10856#define FTM_SC_PS_MASK (0x7U)
10857#define FTM_SC_PS_SHIFT (0U)
10858/*! PS - Prescale Factor Selection
10859 * 0b000..Divide by 1
10860 * 0b001..Divide by 2
10861 * 0b010..Divide by 4
10862 * 0b011..Divide by 8
10863 * 0b100..Divide by 16
10864 * 0b101..Divide by 32
10865 * 0b110..Divide by 64
10866 * 0b111..Divide by 128
10867 */
10868#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
10869#define FTM_SC_CLKS_MASK (0x18U)
10870#define FTM_SC_CLKS_SHIFT (3U)
10871/*! CLKS - Clock Source Selection
10872 * 0b00..No clock selected. This in effect disables the FTM counter.
10873 * 0b01..System clock
10874 * 0b10..Fixed frequency clock
10875 * 0b11..External clock
10876 */
10877#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
10878#define FTM_SC_CPWMS_MASK (0x20U)
10879#define FTM_SC_CPWMS_SHIFT (5U)
10880/*! CPWMS - Center-Aligned PWM Select
10881 * 0b0..FTM counter operates in Up Counting mode.
10882 * 0b1..FTM counter operates in Up-Down Counting mode.
10883 */
10884#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
10885#define FTM_SC_TOIE_MASK (0x40U)
10886#define FTM_SC_TOIE_SHIFT (6U)
10887/*! TOIE - Timer Overflow Interrupt Enable
10888 * 0b0..Disable TOF interrupts. Use software polling.
10889 * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
10890 */
10891#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
10892#define FTM_SC_TOF_MASK (0x80U)
10893#define FTM_SC_TOF_SHIFT (7U)
10894/*! TOF - Timer Overflow Flag
10895 * 0b0..FTM counter has not overflowed.
10896 * 0b1..FTM counter has overflowed.
10897 */
10898#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
10899/*! @} */
10900
10901/*! @name CNT - Counter */
10902/*! @{ */
10903#define FTM_CNT_COUNT_MASK (0xFFFFU)
10904#define FTM_CNT_COUNT_SHIFT (0U)
10905#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
10906/*! @} */
10907
10908/*! @name MOD - Modulo */
10909/*! @{ */
10910#define FTM_MOD_MOD_MASK (0xFFFFU)
10911#define FTM_MOD_MOD_SHIFT (0U)
10912#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
10913/*! @} */
10914
10915/*! @name CnSC - Channel (n) Status And Control */
10916/*! @{ */
10917#define FTM_CnSC_DMA_MASK (0x1U)
10918#define FTM_CnSC_DMA_SHIFT (0U)
10919/*! DMA - DMA Enable
10920 * 0b0..Disable DMA transfers.
10921 * 0b1..Enable DMA transfers.
10922 */
10923#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
10924#define FTM_CnSC_ELSA_MASK (0x4U)
10925#define FTM_CnSC_ELSA_SHIFT (2U)
10926#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
10927#define FTM_CnSC_ELSB_MASK (0x8U)
10928#define FTM_CnSC_ELSB_SHIFT (3U)
10929#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
10930#define FTM_CnSC_MSA_MASK (0x10U)
10931#define FTM_CnSC_MSA_SHIFT (4U)
10932#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
10933#define FTM_CnSC_MSB_MASK (0x20U)
10934#define FTM_CnSC_MSB_SHIFT (5U)
10935#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
10936#define FTM_CnSC_CHIE_MASK (0x40U)
10937#define FTM_CnSC_CHIE_SHIFT (6U)
10938/*! CHIE - Channel Interrupt Enable
10939 * 0b0..Disable channel interrupts. Use software polling.
10940 * 0b1..Enable channel interrupts.
10941 */
10942#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
10943#define FTM_CnSC_CHF_MASK (0x80U)
10944#define FTM_CnSC_CHF_SHIFT (7U)
10945/*! CHF - Channel Flag
10946 * 0b0..No channel event has occurred.
10947 * 0b1..A channel event has occurred.
10948 */
10949#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
10950/*! @} */
10951
10952/* The count of FTM_CnSC */
10953#define FTM_CnSC_COUNT (8U)
10954
10955/*! @name CnV - Channel (n) Value */
10956/*! @{ */
10957#define FTM_CnV_VAL_MASK (0xFFFFU)
10958#define FTM_CnV_VAL_SHIFT (0U)
10959#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
10960/*! @} */
10961
10962/* The count of FTM_CnV */
10963#define FTM_CnV_COUNT (8U)
10964
10965/*! @name CNTIN - Counter Initial Value */
10966/*! @{ */
10967#define FTM_CNTIN_INIT_MASK (0xFFFFU)
10968#define FTM_CNTIN_INIT_SHIFT (0U)
10969#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
10970/*! @} */
10971
10972/*! @name STATUS - Capture And Compare Status */
10973/*! @{ */
10974#define FTM_STATUS_CH0F_MASK (0x1U)
10975#define FTM_STATUS_CH0F_SHIFT (0U)
10976/*! CH0F - Channel 0 Flag
10977 * 0b0..No channel event has occurred.
10978 * 0b1..A channel event has occurred.
10979 */
10980#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
10981#define FTM_STATUS_CH1F_MASK (0x2U)
10982#define FTM_STATUS_CH1F_SHIFT (1U)
10983/*! CH1F - Channel 1 Flag
10984 * 0b0..No channel event has occurred.
10985 * 0b1..A channel event has occurred.
10986 */
10987#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
10988#define FTM_STATUS_CH2F_MASK (0x4U)
10989#define FTM_STATUS_CH2F_SHIFT (2U)
10990/*! CH2F - Channel 2 Flag
10991 * 0b0..No channel event has occurred.
10992 * 0b1..A channel event has occurred.
10993 */
10994#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
10995#define FTM_STATUS_CH3F_MASK (0x8U)
10996#define FTM_STATUS_CH3F_SHIFT (3U)
10997/*! CH3F - Channel 3 Flag
10998 * 0b0..No channel event has occurred.
10999 * 0b1..A channel event has occurred.
11000 */
11001#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
11002#define FTM_STATUS_CH4F_MASK (0x10U)
11003#define FTM_STATUS_CH4F_SHIFT (4U)
11004/*! CH4F - Channel 4 Flag
11005 * 0b0..No channel event has occurred.
11006 * 0b1..A channel event has occurred.
11007 */
11008#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
11009#define FTM_STATUS_CH5F_MASK (0x20U)
11010#define FTM_STATUS_CH5F_SHIFT (5U)
11011/*! CH5F - Channel 5 Flag
11012 * 0b0..No channel event has occurred.
11013 * 0b1..A channel event has occurred.
11014 */
11015#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
11016#define FTM_STATUS_CH6F_MASK (0x40U)
11017#define FTM_STATUS_CH6F_SHIFT (6U)
11018/*! CH6F - Channel 6 Flag
11019 * 0b0..No channel event has occurred.
11020 * 0b1..A channel event has occurred.
11021 */
11022#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
11023#define FTM_STATUS_CH7F_MASK (0x80U)
11024#define FTM_STATUS_CH7F_SHIFT (7U)
11025/*! CH7F - Channel 7 Flag
11026 * 0b0..No channel event has occurred.
11027 * 0b1..A channel event has occurred.
11028 */
11029#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
11030/*! @} */
11031
11032/*! @name MODE - Features Mode Selection */
11033/*! @{ */
11034#define FTM_MODE_FTMEN_MASK (0x1U)
11035#define FTM_MODE_FTMEN_SHIFT (0U)
11036/*! FTMEN - FTM Enable
11037 * 0b0..TPM compatibility. Free running counter and synchronization compatible with TPM.
11038 * 0b1..Free running counter and synchronization are different from TPM behavior.
11039 */
11040#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
11041#define FTM_MODE_INIT_MASK (0x2U)
11042#define FTM_MODE_INIT_SHIFT (1U)
11043#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
11044#define FTM_MODE_WPDIS_MASK (0x4U)
11045#define FTM_MODE_WPDIS_SHIFT (2U)
11046/*! WPDIS - Write Protection Disable
11047 * 0b0..Write protection is enabled.
11048 * 0b1..Write protection is disabled.
11049 */
11050#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
11051#define FTM_MODE_PWMSYNC_MASK (0x8U)
11052#define FTM_MODE_PWMSYNC_SHIFT (3U)
11053/*! PWMSYNC - PWM Synchronization Mode
11054 * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
11055 * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
11056 */
11057#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
11058#define FTM_MODE_CAPTEST_MASK (0x10U)
11059#define FTM_MODE_CAPTEST_SHIFT (4U)
11060/*! CAPTEST - Capture Test Mode Enable
11061 * 0b0..Capture test mode is disabled.
11062 * 0b1..Capture test mode is enabled.
11063 */
11064#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
11065#define FTM_MODE_FAULTM_MASK (0x60U)
11066#define FTM_MODE_FAULTM_SHIFT (5U)
11067/*! FAULTM - Fault Control Mode
11068 * 0b00..Fault control is disabled for all channels.
11069 * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
11070 * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
11071 * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
11072 */
11073#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
11074#define FTM_MODE_FAULTIE_MASK (0x80U)
11075#define FTM_MODE_FAULTIE_SHIFT (7U)
11076/*! FAULTIE - Fault Interrupt Enable
11077 * 0b0..Fault control interrupt is disabled.
11078 * 0b1..Fault control interrupt is enabled.
11079 */
11080#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
11081/*! @} */
11082
11083/*! @name SYNC - Synchronization */
11084/*! @{ */
11085#define FTM_SYNC_CNTMIN_MASK (0x1U)
11086#define FTM_SYNC_CNTMIN_SHIFT (0U)
11087/*! CNTMIN - Minimum Loading Point Enable
11088 * 0b0..The minimum loading point is disabled.
11089 * 0b1..The minimum loading point is enabled.
11090 */
11091#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
11092#define FTM_SYNC_CNTMAX_MASK (0x2U)
11093#define FTM_SYNC_CNTMAX_SHIFT (1U)
11094/*! CNTMAX - Maximum Loading Point Enable
11095 * 0b0..The maximum loading point is disabled.
11096 * 0b1..The maximum loading point is enabled.
11097 */
11098#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
11099#define FTM_SYNC_REINIT_MASK (0x4U)
11100#define FTM_SYNC_REINIT_SHIFT (2U)
11101/*! REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
11102 * 0b0..FTM counter continues to count normally.
11103 * 0b1..FTM counter is updated with its initial value when the selected trigger is detected.
11104 */
11105#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
11106#define FTM_SYNC_SYNCHOM_MASK (0x8U)
11107#define FTM_SYNC_SYNCHOM_SHIFT (3U)
11108/*! SYNCHOM - Output Mask Synchronization
11109 * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
11110 * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
11111 */
11112#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
11113#define FTM_SYNC_TRIG0_MASK (0x10U)
11114#define FTM_SYNC_TRIG0_SHIFT (4U)
11115/*! TRIG0 - PWM Synchronization Hardware Trigger 0
11116 * 0b0..Trigger is disabled.
11117 * 0b1..Trigger is enabled.
11118 */
11119#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
11120#define FTM_SYNC_TRIG1_MASK (0x20U)
11121#define FTM_SYNC_TRIG1_SHIFT (5U)
11122/*! TRIG1 - PWM Synchronization Hardware Trigger 1
11123 * 0b0..Trigger is disabled.
11124 * 0b1..Trigger is enabled.
11125 */
11126#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
11127#define FTM_SYNC_TRIG2_MASK (0x40U)
11128#define FTM_SYNC_TRIG2_SHIFT (6U)
11129/*! TRIG2 - PWM Synchronization Hardware Trigger 2
11130 * 0b0..Trigger is disabled.
11131 * 0b1..Trigger is enabled.
11132 */
11133#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
11134#define FTM_SYNC_SWSYNC_MASK (0x80U)
11135#define FTM_SYNC_SWSYNC_SHIFT (7U)
11136/*! SWSYNC - PWM Synchronization Software Trigger
11137 * 0b0..Software trigger is not selected.
11138 * 0b1..Software trigger is selected.
11139 */
11140#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
11141/*! @} */
11142
11143/*! @name OUTINIT - Initial State For Channels Output */
11144/*! @{ */
11145#define FTM_OUTINIT_CH0OI_MASK (0x1U)
11146#define FTM_OUTINIT_CH0OI_SHIFT (0U)
11147/*! CH0OI - Channel 0 Output Initialization Value
11148 * 0b0..The initialization value is 0.
11149 * 0b1..The initialization value is 1.
11150 */
11151#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
11152#define FTM_OUTINIT_CH1OI_MASK (0x2U)
11153#define FTM_OUTINIT_CH1OI_SHIFT (1U)
11154/*! CH1OI - Channel 1 Output Initialization Value
11155 * 0b0..The initialization value is 0.
11156 * 0b1..The initialization value is 1.
11157 */
11158#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
11159#define FTM_OUTINIT_CH2OI_MASK (0x4U)
11160#define FTM_OUTINIT_CH2OI_SHIFT (2U)
11161/*! CH2OI - Channel 2 Output Initialization Value
11162 * 0b0..The initialization value is 0.
11163 * 0b1..The initialization value is 1.
11164 */
11165#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
11166#define FTM_OUTINIT_CH3OI_MASK (0x8U)
11167#define FTM_OUTINIT_CH3OI_SHIFT (3U)
11168/*! CH3OI - Channel 3 Output Initialization Value
11169 * 0b0..The initialization value is 0.
11170 * 0b1..The initialization value is 1.
11171 */
11172#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
11173#define FTM_OUTINIT_CH4OI_MASK (0x10U)
11174#define FTM_OUTINIT_CH4OI_SHIFT (4U)
11175/*! CH4OI - Channel 4 Output Initialization Value
11176 * 0b0..The initialization value is 0.
11177 * 0b1..The initialization value is 1.
11178 */
11179#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
11180#define FTM_OUTINIT_CH5OI_MASK (0x20U)
11181#define FTM_OUTINIT_CH5OI_SHIFT (5U)
11182/*! CH5OI - Channel 5 Output Initialization Value
11183 * 0b0..The initialization value is 0.
11184 * 0b1..The initialization value is 1.
11185 */
11186#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
11187#define FTM_OUTINIT_CH6OI_MASK (0x40U)
11188#define FTM_OUTINIT_CH6OI_SHIFT (6U)
11189/*! CH6OI - Channel 6 Output Initialization Value
11190 * 0b0..The initialization value is 0.
11191 * 0b1..The initialization value is 1.
11192 */
11193#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
11194#define FTM_OUTINIT_CH7OI_MASK (0x80U)
11195#define FTM_OUTINIT_CH7OI_SHIFT (7U)
11196/*! CH7OI - Channel 7 Output Initialization Value
11197 * 0b0..The initialization value is 0.
11198 * 0b1..The initialization value is 1.
11199 */
11200#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
11201/*! @} */
11202
11203/*! @name OUTMASK - Output Mask */
11204/*! @{ */
11205#define FTM_OUTMASK_CH0OM_MASK (0x1U)
11206#define FTM_OUTMASK_CH0OM_SHIFT (0U)
11207/*! CH0OM - Channel 0 Output Mask
11208 * 0b0..Channel output is not masked. It continues to operate normally.
11209 * 0b1..Channel output is masked. It is forced to its inactive state.
11210 */
11211#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
11212#define FTM_OUTMASK_CH1OM_MASK (0x2U)
11213#define FTM_OUTMASK_CH1OM_SHIFT (1U)
11214/*! CH1OM - Channel 1 Output Mask
11215 * 0b0..Channel output is not masked. It continues to operate normally.
11216 * 0b1..Channel output is masked. It is forced to its inactive state.
11217 */
11218#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
11219#define FTM_OUTMASK_CH2OM_MASK (0x4U)
11220#define FTM_OUTMASK_CH2OM_SHIFT (2U)
11221/*! CH2OM - Channel 2 Output Mask
11222 * 0b0..Channel output is not masked. It continues to operate normally.
11223 * 0b1..Channel output is masked. It is forced to its inactive state.
11224 */
11225#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
11226#define FTM_OUTMASK_CH3OM_MASK (0x8U)
11227#define FTM_OUTMASK_CH3OM_SHIFT (3U)
11228/*! CH3OM - Channel 3 Output Mask
11229 * 0b0..Channel output is not masked. It continues to operate normally.
11230 * 0b1..Channel output is masked. It is forced to its inactive state.
11231 */
11232#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
11233#define FTM_OUTMASK_CH4OM_MASK (0x10U)
11234#define FTM_OUTMASK_CH4OM_SHIFT (4U)
11235/*! CH4OM - Channel 4 Output Mask
11236 * 0b0..Channel output is not masked. It continues to operate normally.
11237 * 0b1..Channel output is masked. It is forced to its inactive state.
11238 */
11239#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
11240#define FTM_OUTMASK_CH5OM_MASK (0x20U)
11241#define FTM_OUTMASK_CH5OM_SHIFT (5U)
11242/*! CH5OM - Channel 5 Output Mask
11243 * 0b0..Channel output is not masked. It continues to operate normally.
11244 * 0b1..Channel output is masked. It is forced to its inactive state.
11245 */
11246#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
11247#define FTM_OUTMASK_CH6OM_MASK (0x40U)
11248#define FTM_OUTMASK_CH6OM_SHIFT (6U)
11249/*! CH6OM - Channel 6 Output Mask
11250 * 0b0..Channel output is not masked. It continues to operate normally.
11251 * 0b1..Channel output is masked. It is forced to its inactive state.
11252 */
11253#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
11254#define FTM_OUTMASK_CH7OM_MASK (0x80U)
11255#define FTM_OUTMASK_CH7OM_SHIFT (7U)
11256/*! CH7OM - Channel 7 Output Mask
11257 * 0b0..Channel output is not masked. It continues to operate normally.
11258 * 0b1..Channel output is masked. It is forced to its inactive state.
11259 */
11260#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
11261/*! @} */
11262
11263/*! @name COMBINE - Function For Linked Channels */
11264/*! @{ */
11265#define FTM_COMBINE_COMBINE0_MASK (0x1U)
11266#define FTM_COMBINE_COMBINE0_SHIFT (0U)
11267/*! COMBINE0 - Combine Channels For n = 0
11268 * 0b0..Channels (n) and (n+1) are independent.
11269 * 0b1..Channels (n) and (n+1) are combined.
11270 */
11271#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
11272#define FTM_COMBINE_COMP0_MASK (0x2U)
11273#define FTM_COMBINE_COMP0_SHIFT (1U)
11274/*! COMP0 - Complement Of Channel (n) For n = 0
11275 * 0b0..The channel (n+1) output is the same as the channel (n) output.
11276 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
11277 */
11278#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
11279#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
11280#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
11281/*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0
11282 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
11283 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
11284 */
11285#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
11286#define FTM_COMBINE_DECAP0_MASK (0x8U)
11287#define FTM_COMBINE_DECAP0_SHIFT (3U)
11288/*! DECAP0 - Dual Edge Capture Mode Captures For n = 0
11289 * 0b0..The dual edge captures are inactive.
11290 * 0b1..The dual edge captures are active.
11291 */
11292#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
11293#define FTM_COMBINE_DTEN0_MASK (0x10U)
11294#define FTM_COMBINE_DTEN0_SHIFT (4U)
11295/*! DTEN0 - Deadtime Enable For n = 0
11296 * 0b0..The deadtime insertion in this pair of channels is disabled.
11297 * 0b1..The deadtime insertion in this pair of channels is enabled.
11298 */
11299#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
11300#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
11301#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
11302/*! SYNCEN0 - Synchronization Enable For n = 0
11303 * 0b0..The PWM synchronization in this pair of channels is disabled.
11304 * 0b1..The PWM synchronization in this pair of channels is enabled.
11305 */
11306#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
11307#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
11308#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
11309/*! FAULTEN0 - Fault Control Enable For n = 0
11310 * 0b0..The fault control in this pair of channels is disabled.
11311 * 0b1..The fault control in this pair of channels is enabled.
11312 */
11313#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
11314#define FTM_COMBINE_COMBINE1_MASK (0x100U)
11315#define FTM_COMBINE_COMBINE1_SHIFT (8U)
11316/*! COMBINE1 - Combine Channels For n = 2
11317 * 0b0..Channels (n) and (n+1) are independent.
11318 * 0b1..Channels (n) and (n+1) are combined.
11319 */
11320#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
11321#define FTM_COMBINE_COMP1_MASK (0x200U)
11322#define FTM_COMBINE_COMP1_SHIFT (9U)
11323/*! COMP1 - Complement Of Channel (n) For n = 2
11324 * 0b0..The channel (n+1) output is the same as the channel (n) output.
11325 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
11326 */
11327#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
11328#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
11329#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
11330/*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2
11331 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
11332 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
11333 */
11334#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
11335#define FTM_COMBINE_DECAP1_MASK (0x800U)
11336#define FTM_COMBINE_DECAP1_SHIFT (11U)
11337/*! DECAP1 - Dual Edge Capture Mode Captures For n = 2
11338 * 0b0..The dual edge captures are inactive.
11339 * 0b1..The dual edge captures are active.
11340 */
11341#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
11342#define FTM_COMBINE_DTEN1_MASK (0x1000U)
11343#define FTM_COMBINE_DTEN1_SHIFT (12U)
11344/*! DTEN1 - Deadtime Enable For n = 2
11345 * 0b0..The deadtime insertion in this pair of channels is disabled.
11346 * 0b1..The deadtime insertion in this pair of channels is enabled.
11347 */
11348#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
11349#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
11350#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
11351/*! SYNCEN1 - Synchronization Enable For n = 2
11352 * 0b0..The PWM synchronization in this pair of channels is disabled.
11353 * 0b1..The PWM synchronization in this pair of channels is enabled.
11354 */
11355#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
11356#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
11357#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
11358/*! FAULTEN1 - Fault Control Enable For n = 2
11359 * 0b0..The fault control in this pair of channels is disabled.
11360 * 0b1..The fault control in this pair of channels is enabled.
11361 */
11362#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
11363#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
11364#define FTM_COMBINE_COMBINE2_SHIFT (16U)
11365/*! COMBINE2 - Combine Channels For n = 4
11366 * 0b0..Channels (n) and (n+1) are independent.
11367 * 0b1..Channels (n) and (n+1) are combined.
11368 */
11369#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
11370#define FTM_COMBINE_COMP2_MASK (0x20000U)
11371#define FTM_COMBINE_COMP2_SHIFT (17U)
11372/*! COMP2 - Complement Of Channel (n) For n = 4
11373 * 0b0..The channel (n+1) output is the same as the channel (n) output.
11374 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
11375 */
11376#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
11377#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
11378#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
11379/*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4
11380 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
11381 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
11382 */
11383#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
11384#define FTM_COMBINE_DECAP2_MASK (0x80000U)
11385#define FTM_COMBINE_DECAP2_SHIFT (19U)
11386/*! DECAP2 - Dual Edge Capture Mode Captures For n = 4
11387 * 0b0..The dual edge captures are inactive.
11388 * 0b1..The dual edge captures are active.
11389 */
11390#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
11391#define FTM_COMBINE_DTEN2_MASK (0x100000U)
11392#define FTM_COMBINE_DTEN2_SHIFT (20U)
11393/*! DTEN2 - Deadtime Enable For n = 4
11394 * 0b0..The deadtime insertion in this pair of channels is disabled.
11395 * 0b1..The deadtime insertion in this pair of channels is enabled.
11396 */
11397#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
11398#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
11399#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
11400/*! SYNCEN2 - Synchronization Enable For n = 4
11401 * 0b0..The PWM synchronization in this pair of channels is disabled.
11402 * 0b1..The PWM synchronization in this pair of channels is enabled.
11403 */
11404#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
11405#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
11406#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
11407/*! FAULTEN2 - Fault Control Enable For n = 4
11408 * 0b0..The fault control in this pair of channels is disabled.
11409 * 0b1..The fault control in this pair of channels is enabled.
11410 */
11411#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
11412#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
11413#define FTM_COMBINE_COMBINE3_SHIFT (24U)
11414/*! COMBINE3 - Combine Channels For n = 6
11415 * 0b0..Channels (n) and (n+1) are independent.
11416 * 0b1..Channels (n) and (n+1) are combined.
11417 */
11418#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
11419#define FTM_COMBINE_COMP3_MASK (0x2000000U)
11420#define FTM_COMBINE_COMP3_SHIFT (25U)
11421/*! COMP3 - Complement Of Channel (n) for n = 6
11422 * 0b0..The channel (n+1) output is the same as the channel (n) output.
11423 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
11424 */
11425#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
11426#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
11427#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
11428/*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6
11429 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
11430 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
11431 */
11432#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
11433#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
11434#define FTM_COMBINE_DECAP3_SHIFT (27U)
11435/*! DECAP3 - Dual Edge Capture Mode Captures For n = 6
11436 * 0b0..The dual edge captures are inactive.
11437 * 0b1..The dual edge captures are active.
11438 */
11439#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
11440#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
11441#define FTM_COMBINE_DTEN3_SHIFT (28U)
11442/*! DTEN3 - Deadtime Enable For n = 6
11443 * 0b0..The deadtime insertion in this pair of channels is disabled.
11444 * 0b1..The deadtime insertion in this pair of channels is enabled.
11445 */
11446#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
11447#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
11448#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
11449/*! SYNCEN3 - Synchronization Enable For n = 6
11450 * 0b0..The PWM synchronization in this pair of channels is disabled.
11451 * 0b1..The PWM synchronization in this pair of channels is enabled.
11452 */
11453#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
11454#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
11455#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
11456/*! FAULTEN3 - Fault Control Enable For n = 6
11457 * 0b0..The fault control in this pair of channels is disabled.
11458 * 0b1..The fault control in this pair of channels is enabled.
11459 */
11460#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
11461/*! @} */
11462
11463/*! @name DEADTIME - Deadtime Insertion Control */
11464/*! @{ */
11465#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
11466#define FTM_DEADTIME_DTVAL_SHIFT (0U)
11467#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
11468#define FTM_DEADTIME_DTPS_MASK (0xC0U)
11469#define FTM_DEADTIME_DTPS_SHIFT (6U)
11470/*! DTPS - Deadtime Prescaler Value
11471 * 0b0x..Divide the system clock by 1.
11472 * 0b10..Divide the system clock by 4.
11473 * 0b11..Divide the system clock by 16.
11474 */
11475#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
11476/*! @} */
11477
11478/*! @name EXTTRIG - FTM External Trigger */
11479/*! @{ */
11480#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
11481#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
11482/*! CH2TRIG - Channel 2 Trigger Enable
11483 * 0b0..The generation of the channel trigger is disabled.
11484 * 0b1..The generation of the channel trigger is enabled.
11485 */
11486#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
11487#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
11488#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
11489/*! CH3TRIG - Channel 3 Trigger Enable
11490 * 0b0..The generation of the channel trigger is disabled.
11491 * 0b1..The generation of the channel trigger is enabled.
11492 */
11493#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
11494#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
11495#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
11496/*! CH4TRIG - Channel 4 Trigger Enable
11497 * 0b0..The generation of the channel trigger is disabled.
11498 * 0b1..The generation of the channel trigger is enabled.
11499 */
11500#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
11501#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
11502#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
11503/*! CH5TRIG - Channel 5 Trigger Enable
11504 * 0b0..The generation of the channel trigger is disabled.
11505 * 0b1..The generation of the channel trigger is enabled.
11506 */
11507#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
11508#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
11509#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
11510/*! CH0TRIG - Channel 0 Trigger Enable
11511 * 0b0..The generation of the channel trigger is disabled.
11512 * 0b1..The generation of the channel trigger is enabled.
11513 */
11514#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
11515#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
11516#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
11517/*! CH1TRIG - Channel 1 Trigger Enable
11518 * 0b0..The generation of the channel trigger is disabled.
11519 * 0b1..The generation of the channel trigger is enabled.
11520 */
11521#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
11522#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
11523#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
11524/*! INITTRIGEN - Initialization Trigger Enable
11525 * 0b0..The generation of initialization trigger is disabled.
11526 * 0b1..The generation of initialization trigger is enabled.
11527 */
11528#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
11529#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
11530#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
11531/*! TRIGF - Channel Trigger Flag
11532 * 0b0..No channel trigger was generated.
11533 * 0b1..A channel trigger was generated.
11534 */
11535#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
11536/*! @} */
11537
11538/*! @name POL - Channels Polarity */
11539/*! @{ */
11540#define FTM_POL_POL0_MASK (0x1U)
11541#define FTM_POL_POL0_SHIFT (0U)
11542/*! POL0 - Channel 0 Polarity
11543 * 0b0..The channel polarity is active high.
11544 * 0b1..The channel polarity is active low.
11545 */
11546#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
11547#define FTM_POL_POL1_MASK (0x2U)
11548#define FTM_POL_POL1_SHIFT (1U)
11549/*! POL1 - Channel 1 Polarity
11550 * 0b0..The channel polarity is active high.
11551 * 0b1..The channel polarity is active low.
11552 */
11553#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
11554#define FTM_POL_POL2_MASK (0x4U)
11555#define FTM_POL_POL2_SHIFT (2U)
11556/*! POL2 - Channel 2 Polarity
11557 * 0b0..The channel polarity is active high.
11558 * 0b1..The channel polarity is active low.
11559 */
11560#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
11561#define FTM_POL_POL3_MASK (0x8U)
11562#define FTM_POL_POL3_SHIFT (3U)
11563/*! POL3 - Channel 3 Polarity
11564 * 0b0..The channel polarity is active high.
11565 * 0b1..The channel polarity is active low.
11566 */
11567#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
11568#define FTM_POL_POL4_MASK (0x10U)
11569#define FTM_POL_POL4_SHIFT (4U)
11570/*! POL4 - Channel 4 Polarity
11571 * 0b0..The channel polarity is active high.
11572 * 0b1..The channel polarity is active low.
11573 */
11574#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
11575#define FTM_POL_POL5_MASK (0x20U)
11576#define FTM_POL_POL5_SHIFT (5U)
11577/*! POL5 - Channel 5 Polarity
11578 * 0b0..The channel polarity is active high.
11579 * 0b1..The channel polarity is active low.
11580 */
11581#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
11582#define FTM_POL_POL6_MASK (0x40U)
11583#define FTM_POL_POL6_SHIFT (6U)
11584/*! POL6 - Channel 6 Polarity
11585 * 0b0..The channel polarity is active high.
11586 * 0b1..The channel polarity is active low.
11587 */
11588#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
11589#define FTM_POL_POL7_MASK (0x80U)
11590#define FTM_POL_POL7_SHIFT (7U)
11591/*! POL7 - Channel 7 Polarity
11592 * 0b0..The channel polarity is active high.
11593 * 0b1..The channel polarity is active low.
11594 */
11595#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
11596/*! @} */
11597
11598/*! @name FMS - Fault Mode Status */
11599/*! @{ */
11600#define FTM_FMS_FAULTF0_MASK (0x1U)
11601#define FTM_FMS_FAULTF0_SHIFT (0U)
11602/*! FAULTF0 - Fault Detection Flag 0
11603 * 0b0..No fault condition was detected at the fault input.
11604 * 0b1..A fault condition was detected at the fault input.
11605 */
11606#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
11607#define FTM_FMS_FAULTF1_MASK (0x2U)
11608#define FTM_FMS_FAULTF1_SHIFT (1U)
11609/*! FAULTF1 - Fault Detection Flag 1
11610 * 0b0..No fault condition was detected at the fault input.
11611 * 0b1..A fault condition was detected at the fault input.
11612 */
11613#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
11614#define FTM_FMS_FAULTF2_MASK (0x4U)
11615#define FTM_FMS_FAULTF2_SHIFT (2U)
11616/*! FAULTF2 - Fault Detection Flag 2
11617 * 0b0..No fault condition was detected at the fault input.
11618 * 0b1..A fault condition was detected at the fault input.
11619 */
11620#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
11621#define FTM_FMS_FAULTF3_MASK (0x8U)
11622#define FTM_FMS_FAULTF3_SHIFT (3U)
11623/*! FAULTF3 - Fault Detection Flag 3
11624 * 0b0..No fault condition was detected at the fault input.
11625 * 0b1..A fault condition was detected at the fault input.
11626 */
11627#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
11628#define FTM_FMS_FAULTIN_MASK (0x20U)
11629#define FTM_FMS_FAULTIN_SHIFT (5U)
11630/*! FAULTIN - Fault Inputs
11631 * 0b0..The logic OR of the enabled fault inputs is 0.
11632 * 0b1..The logic OR of the enabled fault inputs is 1.
11633 */
11634#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
11635#define FTM_FMS_WPEN_MASK (0x40U)
11636#define FTM_FMS_WPEN_SHIFT (6U)
11637/*! WPEN - Write Protection Enable
11638 * 0b0..Write protection is disabled. Write protected bits can be written.
11639 * 0b1..Write protection is enabled. Write protected bits cannot be written.
11640 */
11641#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
11642#define FTM_FMS_FAULTF_MASK (0x80U)
11643#define FTM_FMS_FAULTF_SHIFT (7U)
11644/*! FAULTF - Fault Detection Flag
11645 * 0b0..No fault condition was detected.
11646 * 0b1..A fault condition was detected.
11647 */
11648#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
11649/*! @} */
11650
11651/*! @name FILTER - Input Capture Filter Control */
11652/*! @{ */
11653#define FTM_FILTER_CH0FVAL_MASK (0xFU)
11654#define FTM_FILTER_CH0FVAL_SHIFT (0U)
11655#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
11656#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
11657#define FTM_FILTER_CH1FVAL_SHIFT (4U)
11658#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
11659#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
11660#define FTM_FILTER_CH2FVAL_SHIFT (8U)
11661#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
11662#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
11663#define FTM_FILTER_CH3FVAL_SHIFT (12U)
11664#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
11665/*! @} */
11666
11667/*! @name FLTCTRL - Fault Control */
11668/*! @{ */
11669#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
11670#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
11671/*! FAULT0EN - Fault Input 0 Enable
11672 * 0b0..Fault input is disabled.
11673 * 0b1..Fault input is enabled.
11674 */
11675#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
11676#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
11677#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
11678/*! FAULT1EN - Fault Input 1 Enable
11679 * 0b0..Fault input is disabled.
11680 * 0b1..Fault input is enabled.
11681 */
11682#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
11683#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
11684#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
11685/*! FAULT2EN - Fault Input 2 Enable
11686 * 0b0..Fault input is disabled.
11687 * 0b1..Fault input is enabled.
11688 */
11689#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
11690#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
11691#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
11692/*! FAULT3EN - Fault Input 3 Enable
11693 * 0b0..Fault input is disabled.
11694 * 0b1..Fault input is enabled.
11695 */
11696#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
11697#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
11698#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
11699/*! FFLTR0EN - Fault Input 0 Filter Enable
11700 * 0b0..Fault input filter is disabled.
11701 * 0b1..Fault input filter is enabled.
11702 */
11703#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
11704#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
11705#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
11706/*! FFLTR1EN - Fault Input 1 Filter Enable
11707 * 0b0..Fault input filter is disabled.
11708 * 0b1..Fault input filter is enabled.
11709 */
11710#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
11711#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
11712#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
11713/*! FFLTR2EN - Fault Input 2 Filter Enable
11714 * 0b0..Fault input filter is disabled.
11715 * 0b1..Fault input filter is enabled.
11716 */
11717#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
11718#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
11719#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
11720/*! FFLTR3EN - Fault Input 3 Filter Enable
11721 * 0b0..Fault input filter is disabled.
11722 * 0b1..Fault input filter is enabled.
11723 */
11724#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
11725#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
11726#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
11727#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
11728/*! @} */
11729
11730/*! @name QDCTRL - Quadrature Decoder Control And Status */
11731/*! @{ */
11732#define FTM_QDCTRL_QUADEN_MASK (0x1U)
11733#define FTM_QDCTRL_QUADEN_SHIFT (0U)
11734/*! QUADEN - Quadrature Decoder Mode Enable
11735 * 0b0..Quadrature Decoder mode is disabled.
11736 * 0b1..Quadrature Decoder mode is enabled.
11737 */
11738#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
11739#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
11740#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
11741/*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode
11742 * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
11743 * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
11744 */
11745#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
11746#define FTM_QDCTRL_QUADIR_MASK (0x4U)
11747#define FTM_QDCTRL_QUADIR_SHIFT (2U)
11748/*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode
11749 * 0b0..Counting direction is decreasing (FTM counter decrement).
11750 * 0b1..Counting direction is increasing (FTM counter increment).
11751 */
11752#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
11753#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
11754#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
11755/*! QUADMODE - Quadrature Decoder Mode
11756 * 0b0..Phase A and phase B encoding mode.
11757 * 0b1..Count and direction encoding mode.
11758 */
11759#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
11760#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
11761#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
11762/*! PHBPOL - Phase B Input Polarity
11763 * 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
11764 * 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
11765 */
11766#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
11767#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
11768#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
11769/*! PHAPOL - Phase A Input Polarity
11770 * 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
11771 * 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
11772 */
11773#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
11774#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
11775#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
11776/*! PHBFLTREN - Phase B Input Filter Enable
11777 * 0b0..Phase B input filter is disabled.
11778 * 0b1..Phase B input filter is enabled.
11779 */
11780#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
11781#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
11782#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
11783/*! PHAFLTREN - Phase A Input Filter Enable
11784 * 0b0..Phase A input filter is disabled.
11785 * 0b1..Phase A input filter is enabled.
11786 */
11787#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
11788/*! @} */
11789
11790/*! @name CONF - Configuration */
11791/*! @{ */
11792#define FTM_CONF_NUMTOF_MASK (0x1FU)
11793#define FTM_CONF_NUMTOF_SHIFT (0U)
11794#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
11795#define FTM_CONF_BDMMODE_MASK (0xC0U)
11796#define FTM_CONF_BDMMODE_SHIFT (6U)
11797#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
11798#define FTM_CONF_GTBEEN_MASK (0x200U)
11799#define FTM_CONF_GTBEEN_SHIFT (9U)
11800/*! GTBEEN - Global Time Base Enable
11801 * 0b0..Use of an external global time base is disabled.
11802 * 0b1..Use of an external global time base is enabled.
11803 */
11804#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
11805#define FTM_CONF_GTBEOUT_MASK (0x400U)
11806#define FTM_CONF_GTBEOUT_SHIFT (10U)
11807/*! GTBEOUT - Global Time Base Output
11808 * 0b0..A global time base signal generation is disabled.
11809 * 0b1..A global time base signal generation is enabled.
11810 */
11811#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
11812/*! @} */
11813
11814/*! @name FLTPOL - FTM Fault Input Polarity */
11815/*! @{ */
11816#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
11817#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
11818/*! FLT0POL - Fault Input 0 Polarity
11819 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
11820 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
11821 */
11822#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
11823#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
11824#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
11825/*! FLT1POL - Fault Input 1 Polarity
11826 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
11827 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
11828 */
11829#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
11830#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
11831#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
11832/*! FLT2POL - Fault Input 2 Polarity
11833 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
11834 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
11835 */
11836#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
11837#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
11838#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
11839/*! FLT3POL - Fault Input 3 Polarity
11840 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
11841 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
11842 */
11843#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
11844/*! @} */
11845
11846/*! @name SYNCONF - Synchronization Configuration */
11847/*! @{ */
11848#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
11849#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
11850/*! HWTRIGMODE - Hardware Trigger Mode
11851 * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
11852 * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
11853 */
11854#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
11855#define FTM_SYNCONF_CNTINC_MASK (0x4U)
11856#define FTM_SYNCONF_CNTINC_SHIFT (2U)
11857/*! CNTINC - CNTIN Register Synchronization
11858 * 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock.
11859 * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization.
11860 */
11861#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
11862#define FTM_SYNCONF_INVC_MASK (0x10U)
11863#define FTM_SYNCONF_INVC_SHIFT (4U)
11864/*! INVC - INVCTRL Register Synchronization
11865 * 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock.
11866 * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.
11867 */
11868#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
11869#define FTM_SYNCONF_SWOC_MASK (0x20U)
11870#define FTM_SYNCONF_SWOC_SHIFT (5U)
11871/*! SWOC - SWOCTRL Register Synchronization
11872 * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock.
11873 * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.
11874 */
11875#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
11876#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
11877#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
11878/*! SYNCMODE - Synchronization Mode
11879 * 0b0..Legacy PWM synchronization is selected.
11880 * 0b1..Enhanced PWM synchronization is selected.
11881 */
11882#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
11883#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
11884#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
11885/*! SWRSTCNT
11886 * 0b0..The software trigger does not activate the FTM counter synchronization.
11887 * 0b1..The software trigger activates the FTM counter synchronization.
11888 */
11889#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
11890#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
11891#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
11892/*! SWWRBUF
11893 * 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
11894 * 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization.
11895 */
11896#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
11897#define FTM_SYNCONF_SWOM_MASK (0x400U)
11898#define FTM_SYNCONF_SWOM_SHIFT (10U)
11899/*! SWOM
11900 * 0b0..The software trigger does not activate the OUTMASK register synchronization.
11901 * 0b1..The software trigger activates the OUTMASK register synchronization.
11902 */
11903#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
11904#define FTM_SYNCONF_SWINVC_MASK (0x800U)
11905#define FTM_SYNCONF_SWINVC_SHIFT (11U)
11906/*! SWINVC
11907 * 0b0..The software trigger does not activate the INVCTRL register synchronization.
11908 * 0b1..The software trigger activates the INVCTRL register synchronization.
11909 */
11910#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
11911#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
11912#define FTM_SYNCONF_SWSOC_SHIFT (12U)
11913/*! SWSOC
11914 * 0b0..The software trigger does not activate the SWOCTRL register synchronization.
11915 * 0b1..The software trigger activates the SWOCTRL register synchronization.
11916 */
11917#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
11918#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
11919#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
11920/*! HWRSTCNT
11921 * 0b0..A hardware trigger does not activate the FTM counter synchronization.
11922 * 0b1..A hardware trigger activates the FTM counter synchronization.
11923 */
11924#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
11925#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
11926#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
11927/*! HWWRBUF
11928 * 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
11929 * 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
11930 */
11931#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
11932#define FTM_SYNCONF_HWOM_MASK (0x40000U)
11933#define FTM_SYNCONF_HWOM_SHIFT (18U)
11934/*! HWOM
11935 * 0b0..A hardware trigger does not activate the OUTMASK register synchronization.
11936 * 0b1..A hardware trigger activates the OUTMASK register synchronization.
11937 */
11938#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
11939#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
11940#define FTM_SYNCONF_HWINVC_SHIFT (19U)
11941/*! HWINVC
11942 * 0b0..A hardware trigger does not activate the INVCTRL register synchronization.
11943 * 0b1..A hardware trigger activates the INVCTRL register synchronization.
11944 */
11945#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
11946#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
11947#define FTM_SYNCONF_HWSOC_SHIFT (20U)
11948/*! HWSOC
11949 * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization.
11950 * 0b1..A hardware trigger activates the SWOCTRL register synchronization.
11951 */
11952#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
11953/*! @} */
11954
11955/*! @name INVCTRL - FTM Inverting Control */
11956/*! @{ */
11957#define FTM_INVCTRL_INV0EN_MASK (0x1U)
11958#define FTM_INVCTRL_INV0EN_SHIFT (0U)
11959/*! INV0EN - Pair Channels 0 Inverting Enable
11960 * 0b0..Inverting is disabled.
11961 * 0b1..Inverting is enabled.
11962 */
11963#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
11964#define FTM_INVCTRL_INV1EN_MASK (0x2U)
11965#define FTM_INVCTRL_INV1EN_SHIFT (1U)
11966/*! INV1EN - Pair Channels 1 Inverting Enable
11967 * 0b0..Inverting is disabled.
11968 * 0b1..Inverting is enabled.
11969 */
11970#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
11971#define FTM_INVCTRL_INV2EN_MASK (0x4U)
11972#define FTM_INVCTRL_INV2EN_SHIFT (2U)
11973/*! INV2EN - Pair Channels 2 Inverting Enable
11974 * 0b0..Inverting is disabled.
11975 * 0b1..Inverting is enabled.
11976 */
11977#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
11978#define FTM_INVCTRL_INV3EN_MASK (0x8U)
11979#define FTM_INVCTRL_INV3EN_SHIFT (3U)
11980/*! INV3EN - Pair Channels 3 Inverting Enable
11981 * 0b0..Inverting is disabled.
11982 * 0b1..Inverting is enabled.
11983 */
11984#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
11985/*! @} */
11986
11987/*! @name SWOCTRL - FTM Software Output Control */
11988/*! @{ */
11989#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
11990#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
11991/*! CH0OC - Channel 0 Software Output Control Enable
11992 * 0b0..The channel output is not affected by software output control.
11993 * 0b1..The channel output is affected by software output control.
11994 */
11995#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
11996#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
11997#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
11998/*! CH1OC - Channel 1 Software Output Control Enable
11999 * 0b0..The channel output is not affected by software output control.
12000 * 0b1..The channel output is affected by software output control.
12001 */
12002#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
12003#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
12004#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
12005/*! CH2OC - Channel 2 Software Output Control Enable
12006 * 0b0..The channel output is not affected by software output control.
12007 * 0b1..The channel output is affected by software output control.
12008 */
12009#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
12010#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
12011#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
12012/*! CH3OC - Channel 3 Software Output Control Enable
12013 * 0b0..The channel output is not affected by software output control.
12014 * 0b1..The channel output is affected by software output control.
12015 */
12016#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
12017#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
12018#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
12019/*! CH4OC - Channel 4 Software Output Control Enable
12020 * 0b0..The channel output is not affected by software output control.
12021 * 0b1..The channel output is affected by software output control.
12022 */
12023#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
12024#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
12025#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
12026/*! CH5OC - Channel 5 Software Output Control Enable
12027 * 0b0..The channel output is not affected by software output control.
12028 * 0b1..The channel output is affected by software output control.
12029 */
12030#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
12031#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
12032#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
12033/*! CH6OC - Channel 6 Software Output Control Enable
12034 * 0b0..The channel output is not affected by software output control.
12035 * 0b1..The channel output is affected by software output control.
12036 */
12037#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
12038#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
12039#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
12040/*! CH7OC - Channel 7 Software Output Control Enable
12041 * 0b0..The channel output is not affected by software output control.
12042 * 0b1..The channel output is affected by software output control.
12043 */
12044#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
12045#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
12046#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
12047/*! CH0OCV - Channel 0 Software Output Control Value
12048 * 0b0..The software output control forces 0 to the channel output.
12049 * 0b1..The software output control forces 1 to the channel output.
12050 */
12051#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
12052#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
12053#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
12054/*! CH1OCV - Channel 1 Software Output Control Value
12055 * 0b0..The software output control forces 0 to the channel output.
12056 * 0b1..The software output control forces 1 to the channel output.
12057 */
12058#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
12059#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
12060#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
12061/*! CH2OCV - Channel 2 Software Output Control Value
12062 * 0b0..The software output control forces 0 to the channel output.
12063 * 0b1..The software output control forces 1 to the channel output.
12064 */
12065#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
12066#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
12067#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
12068/*! CH3OCV - Channel 3 Software Output Control Value
12069 * 0b0..The software output control forces 0 to the channel output.
12070 * 0b1..The software output control forces 1 to the channel output.
12071 */
12072#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
12073#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
12074#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
12075/*! CH4OCV - Channel 4 Software Output Control Value
12076 * 0b0..The software output control forces 0 to the channel output.
12077 * 0b1..The software output control forces 1 to the channel output.
12078 */
12079#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
12080#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
12081#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
12082/*! CH5OCV - Channel 5 Software Output Control Value
12083 * 0b0..The software output control forces 0 to the channel output.
12084 * 0b1..The software output control forces 1 to the channel output.
12085 */
12086#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
12087#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
12088#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
12089/*! CH6OCV - Channel 6 Software Output Control Value
12090 * 0b0..The software output control forces 0 to the channel output.
12091 * 0b1..The software output control forces 1 to the channel output.
12092 */
12093#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
12094#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
12095#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
12096/*! CH7OCV - Channel 7 Software Output Control Value
12097 * 0b0..The software output control forces 0 to the channel output.
12098 * 0b1..The software output control forces 1 to the channel output.
12099 */
12100#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
12101/*! @} */
12102
12103/*! @name PWMLOAD - FTM PWM Load */
12104/*! @{ */
12105#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
12106#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
12107/*! CH0SEL - Channel 0 Select
12108 * 0b0..Do not include the channel in the matching process.
12109 * 0b1..Include the channel in the matching process.
12110 */
12111#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
12112#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
12113#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
12114/*! CH1SEL - Channel 1 Select
12115 * 0b0..Do not include the channel in the matching process.
12116 * 0b1..Include the channel in the matching process.
12117 */
12118#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
12119#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
12120#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
12121/*! CH2SEL - Channel 2 Select
12122 * 0b0..Do not include the channel in the matching process.
12123 * 0b1..Include the channel in the matching process.
12124 */
12125#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
12126#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
12127#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
12128/*! CH3SEL - Channel 3 Select
12129 * 0b0..Do not include the channel in the matching process.
12130 * 0b1..Include the channel in the matching process.
12131 */
12132#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
12133#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
12134#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
12135/*! CH4SEL - Channel 4 Select
12136 * 0b0..Do not include the channel in the matching process.
12137 * 0b1..Include the channel in the matching process.
12138 */
12139#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
12140#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
12141#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
12142/*! CH5SEL - Channel 5 Select
12143 * 0b0..Do not include the channel in the matching process.
12144 * 0b1..Include the channel in the matching process.
12145 */
12146#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
12147#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
12148#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
12149/*! CH6SEL - Channel 6 Select
12150 * 0b0..Do not include the channel in the matching process.
12151 * 0b1..Include the channel in the matching process.
12152 */
12153#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
12154#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
12155#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
12156/*! CH7SEL - Channel 7 Select
12157 * 0b0..Do not include the channel in the matching process.
12158 * 0b1..Include the channel in the matching process.
12159 */
12160#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
12161#define FTM_PWMLOAD_LDOK_MASK (0x200U)
12162#define FTM_PWMLOAD_LDOK_SHIFT (9U)
12163/*! LDOK - Load Enable
12164 * 0b0..Loading updated values is disabled.
12165 * 0b1..Loading updated values is enabled.
12166 */
12167#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
12168/*! @} */
12169
12170
12171/*!
12172 * @}
12173 */ /* end of group FTM_Register_Masks */
12174
12175
12176/* FTM - Peripheral instance base addresses */
12177/** Peripheral FTM0 base address */
12178#define FTM0_BASE (0x40038000u)
12179/** Peripheral FTM0 base pointer */
12180#define FTM0 ((FTM_Type *)FTM0_BASE)
12181/** Peripheral FTM1 base address */
12182#define FTM1_BASE (0x40039000u)
12183/** Peripheral FTM1 base pointer */
12184#define FTM1 ((FTM_Type *)FTM1_BASE)
12185/** Peripheral FTM2 base address */
12186#define FTM2_BASE (0x4003A000u)
12187/** Peripheral FTM2 base pointer */
12188#define FTM2 ((FTM_Type *)FTM2_BASE)
12189/** Peripheral FTM3 base address */
12190#define FTM3_BASE (0x400B9000u)
12191/** Peripheral FTM3 base pointer */
12192#define FTM3 ((FTM_Type *)FTM3_BASE)
12193/** Array initializer of FTM peripheral base addresses */
12194#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
12195/** Array initializer of FTM peripheral base pointers */
12196#define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
12197/** Interrupt vectors for the FTM peripheral type */
12198#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
12199
12200/*!
12201 * @}
12202 */ /* end of group FTM_Peripheral_Access_Layer */
12203
12204
12205/* ----------------------------------------------------------------------------
12206 -- GPIO Peripheral Access Layer
12207 ---------------------------------------------------------------------------- */
12208
12209/*!
12210 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
12211 * @{
12212 */
12213
12214/** GPIO - Register Layout Typedef */
12215typedef struct {
12216 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
12217 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
12218 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
12219 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
12220 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
12221 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
12222} GPIO_Type;
12223
12224/* ----------------------------------------------------------------------------
12225 -- GPIO Register Masks
12226 ---------------------------------------------------------------------------- */
12227
12228/*!
12229 * @addtogroup GPIO_Register_Masks GPIO Register Masks
12230 * @{
12231 */
12232
12233/*! @name PDOR - Port Data Output Register */
12234/*! @{ */
12235#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
12236#define GPIO_PDOR_PDO_SHIFT (0U)
12237/*! PDO - Port Data Output
12238 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
12239 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
12240 */
12241#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
12242/*! @} */
12243
12244/*! @name PSOR - Port Set Output Register */
12245/*! @{ */
12246#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
12247#define GPIO_PSOR_PTSO_SHIFT (0U)
12248/*! PTSO - Port Set Output
12249 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
12250 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1.
12251 */
12252#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
12253/*! @} */
12254
12255/*! @name PCOR - Port Clear Output Register */
12256/*! @{ */
12257#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
12258#define GPIO_PCOR_PTCO_SHIFT (0U)
12259/*! PTCO - Port Clear Output
12260 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
12261 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0.
12262 */
12263#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
12264/*! @} */
12265
12266/*! @name PTOR - Port Toggle Output Register */
12267/*! @{ */
12268#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
12269#define GPIO_PTOR_PTTO_SHIFT (0U)
12270/*! PTTO - Port Toggle Output
12271 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
12272 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state.
12273 */
12274#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
12275/*! @} */
12276
12277/*! @name PDIR - Port Data Input Register */
12278/*! @{ */
12279#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
12280#define GPIO_PDIR_PDI_SHIFT (0U)
12281/*! PDI - Port Data Input
12282 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function.
12283 * 0b00000000000000000000000000000001..Pin logic level is logic 1.
12284 */
12285#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
12286/*! @} */
12287
12288/*! @name PDDR - Port Data Direction Register */
12289/*! @{ */
12290#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
12291#define GPIO_PDDR_PDD_SHIFT (0U)
12292/*! PDD - Port Data Direction
12293 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function.
12294 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function.
12295 */
12296#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
12297/*! @} */
12298
12299
12300/*!
12301 * @}
12302 */ /* end of group GPIO_Register_Masks */
12303
12304
12305/* GPIO - Peripheral instance base addresses */
12306/** Peripheral GPIOA base address */
12307#define GPIOA_BASE (0x400FF000u)
12308/** Peripheral GPIOA base pointer */
12309#define GPIOA ((GPIO_Type *)GPIOA_BASE)
12310/** Peripheral GPIOB base address */
12311#define GPIOB_BASE (0x400FF040u)
12312/** Peripheral GPIOB base pointer */
12313#define GPIOB ((GPIO_Type *)GPIOB_BASE)
12314/** Peripheral GPIOC base address */
12315#define GPIOC_BASE (0x400FF080u)
12316/** Peripheral GPIOC base pointer */
12317#define GPIOC ((GPIO_Type *)GPIOC_BASE)
12318/** Peripheral GPIOD base address */
12319#define GPIOD_BASE (0x400FF0C0u)
12320/** Peripheral GPIOD base pointer */
12321#define GPIOD ((GPIO_Type *)GPIOD_BASE)
12322/** Peripheral GPIOE base address */
12323#define GPIOE_BASE (0x400FF100u)
12324/** Peripheral GPIOE base pointer */
12325#define GPIOE ((GPIO_Type *)GPIOE_BASE)
12326/** Array initializer of GPIO peripheral base addresses */
12327#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
12328/** Array initializer of GPIO peripheral base pointers */
12329#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
12330
12331/*!
12332 * @}
12333 */ /* end of group GPIO_Peripheral_Access_Layer */
12334
12335
12336/* ----------------------------------------------------------------------------
12337 -- I2C Peripheral Access Layer
12338 ---------------------------------------------------------------------------- */
12339
12340/*!
12341 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
12342 * @{
12343 */
12344
12345/** I2C - Register Layout Typedef */
12346typedef struct {
12347 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
12348 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
12349 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
12350 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
12351 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
12352 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
12353 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
12354 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
12355 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
12356 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
12357 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
12358 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
12359} I2C_Type;
12360
12361/* ----------------------------------------------------------------------------
12362 -- I2C Register Masks
12363 ---------------------------------------------------------------------------- */
12364
12365/*!
12366 * @addtogroup I2C_Register_Masks I2C Register Masks
12367 * @{
12368 */
12369
12370/*! @name A1 - I2C Address Register 1 */
12371/*! @{ */
12372#define I2C_A1_AD_MASK (0xFEU)
12373#define I2C_A1_AD_SHIFT (1U)
12374#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
12375/*! @} */
12376
12377/*! @name F - I2C Frequency Divider register */
12378/*! @{ */
12379#define I2C_F_ICR_MASK (0x3FU)
12380#define I2C_F_ICR_SHIFT (0U)
12381#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
12382#define I2C_F_MULT_MASK (0xC0U)
12383#define I2C_F_MULT_SHIFT (6U)
12384/*! MULT - Multiplier Factor
12385 * 0b00..mul = 1
12386 * 0b01..mul = 2
12387 * 0b10..mul = 4
12388 * 0b11..Reserved
12389 */
12390#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
12391/*! @} */
12392
12393/*! @name C1 - I2C Control Register 1 */
12394/*! @{ */
12395#define I2C_C1_DMAEN_MASK (0x1U)
12396#define I2C_C1_DMAEN_SHIFT (0U)
12397/*! DMAEN - DMA Enable
12398 * 0b0..All DMA signalling disabled.
12399 * 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
12400 */
12401#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
12402#define I2C_C1_WUEN_MASK (0x2U)
12403#define I2C_C1_WUEN_SHIFT (1U)
12404/*! WUEN - Wakeup Enable
12405 * 0b0..Normal operation. No interrupt generated when address matching in low power mode.
12406 * 0b1..Enables the wakeup function in low power mode.
12407 */
12408#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
12409#define I2C_C1_RSTA_MASK (0x4U)
12410#define I2C_C1_RSTA_SHIFT (2U)
12411#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
12412#define I2C_C1_TXAK_MASK (0x8U)
12413#define I2C_C1_TXAK_SHIFT (3U)
12414/*! TXAK - Transmit Acknowledge Enable
12415 * 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
12416 * 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
12417 */
12418#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
12419#define I2C_C1_TX_MASK (0x10U)
12420#define I2C_C1_TX_SHIFT (4U)
12421/*! TX - Transmit Mode Select
12422 * 0b0..Receive
12423 * 0b1..Transmit
12424 */
12425#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
12426#define I2C_C1_MST_MASK (0x20U)
12427#define I2C_C1_MST_SHIFT (5U)
12428/*! MST - Master Mode Select
12429 * 0b0..Slave mode
12430 * 0b1..Master mode
12431 */
12432#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
12433#define I2C_C1_IICIE_MASK (0x40U)
12434#define I2C_C1_IICIE_SHIFT (6U)
12435/*! IICIE - I2C Interrupt Enable
12436 * 0b0..Disabled
12437 * 0b1..Enabled
12438 */
12439#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
12440#define I2C_C1_IICEN_MASK (0x80U)
12441#define I2C_C1_IICEN_SHIFT (7U)
12442/*! IICEN - I2C Enable
12443 * 0b0..Disabled
12444 * 0b1..Enabled
12445 */
12446#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
12447/*! @} */
12448
12449/*! @name S - I2C Status register */
12450/*! @{ */
12451#define I2C_S_RXAK_MASK (0x1U)
12452#define I2C_S_RXAK_SHIFT (0U)
12453/*! RXAK - Receive Acknowledge
12454 * 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus
12455 * 0b1..No acknowledge signal detected
12456 */
12457#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
12458#define I2C_S_IICIF_MASK (0x2U)
12459#define I2C_S_IICIF_SHIFT (1U)
12460/*! IICIF - Interrupt Flag
12461 * 0b0..No interrupt pending
12462 * 0b1..Interrupt pending
12463 */
12464#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
12465#define I2C_S_SRW_MASK (0x4U)
12466#define I2C_S_SRW_SHIFT (2U)
12467/*! SRW - Slave Read/Write
12468 * 0b0..Slave receive, master writing to slave
12469 * 0b1..Slave transmit, master reading from slave
12470 */
12471#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
12472#define I2C_S_RAM_MASK (0x8U)
12473#define I2C_S_RAM_SHIFT (3U)
12474/*! RAM - Range Address Match
12475 * 0b0..Not addressed
12476 * 0b1..Addressed as a slave
12477 */
12478#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
12479#define I2C_S_ARBL_MASK (0x10U)
12480#define I2C_S_ARBL_SHIFT (4U)
12481/*! ARBL - Arbitration Lost
12482 * 0b0..Standard bus operation.
12483 * 0b1..Loss of arbitration.
12484 */
12485#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
12486#define I2C_S_BUSY_MASK (0x20U)
12487#define I2C_S_BUSY_SHIFT (5U)
12488/*! BUSY - Bus Busy
12489 * 0b0..Bus is idle
12490 * 0b1..Bus is busy
12491 */
12492#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
12493#define I2C_S_IAAS_MASK (0x40U)
12494#define I2C_S_IAAS_SHIFT (6U)
12495/*! IAAS - Addressed As A Slave
12496 * 0b0..Not addressed
12497 * 0b1..Addressed as a slave
12498 */
12499#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
12500#define I2C_S_TCF_MASK (0x80U)
12501#define I2C_S_TCF_SHIFT (7U)
12502/*! TCF - Transfer Complete Flag
12503 * 0b0..Transfer in progress
12504 * 0b1..Transfer complete
12505 */
12506#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
12507/*! @} */
12508
12509/*! @name D - I2C Data I/O register */
12510/*! @{ */
12511#define I2C_D_DATA_MASK (0xFFU)
12512#define I2C_D_DATA_SHIFT (0U)
12513#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
12514/*! @} */
12515
12516/*! @name C2 - I2C Control Register 2 */
12517/*! @{ */
12518#define I2C_C2_AD_MASK (0x7U)
12519#define I2C_C2_AD_SHIFT (0U)
12520#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
12521#define I2C_C2_RMEN_MASK (0x8U)
12522#define I2C_C2_RMEN_SHIFT (3U)
12523/*! RMEN - Range Address Matching Enable
12524 * 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
12525 * 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
12526 */
12527#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
12528#define I2C_C2_SBRC_MASK (0x10U)
12529#define I2C_C2_SBRC_SHIFT (4U)
12530/*! SBRC - Slave Baud Rate Control
12531 * 0b0..The slave baud rate follows the master baud rate and clock stretching may occur
12532 * 0b1..Slave baud rate is independent of the master baud rate
12533 */
12534#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
12535#define I2C_C2_HDRS_MASK (0x20U)
12536#define I2C_C2_HDRS_SHIFT (5U)
12537/*! HDRS - High Drive Select
12538 * 0b0..Normal drive mode
12539 * 0b1..High drive mode
12540 */
12541#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
12542#define I2C_C2_ADEXT_MASK (0x40U)
12543#define I2C_C2_ADEXT_SHIFT (6U)
12544/*! ADEXT - Address Extension
12545 * 0b0..7-bit address scheme
12546 * 0b1..10-bit address scheme
12547 */
12548#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
12549#define I2C_C2_GCAEN_MASK (0x80U)
12550#define I2C_C2_GCAEN_SHIFT (7U)
12551/*! GCAEN - General Call Address Enable
12552 * 0b0..Disabled
12553 * 0b1..Enabled
12554 */
12555#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
12556/*! @} */
12557
12558/*! @name FLT - I2C Programmable Input Glitch Filter Register */
12559/*! @{ */
12560#define I2C_FLT_FLT_MASK (0xFU)
12561#define I2C_FLT_FLT_SHIFT (0U)
12562/*! FLT - I2C Programmable Filter Factor
12563 * 0b0000..No filter/bypass
12564 */
12565#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
12566#define I2C_FLT_STARTF_MASK (0x10U)
12567#define I2C_FLT_STARTF_SHIFT (4U)
12568/*! STARTF - I2C Bus Start Detect Flag
12569 * 0b0..No start happens on I2C bus
12570 * 0b1..Start detected on I2C bus
12571 */
12572#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
12573#define I2C_FLT_SSIE_MASK (0x20U)
12574#define I2C_FLT_SSIE_SHIFT (5U)
12575/*! SSIE - I2C Bus Stop or Start Interrupt Enable
12576 * 0b0..Stop or start detection interrupt is disabled
12577 * 0b1..Stop or start detection interrupt is enabled
12578 */
12579#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
12580#define I2C_FLT_STOPF_MASK (0x40U)
12581#define I2C_FLT_STOPF_SHIFT (6U)
12582/*! STOPF - I2C Bus Stop Detect Flag
12583 * 0b0..No stop happens on I2C bus
12584 * 0b1..Stop detected on I2C bus
12585 */
12586#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
12587#define I2C_FLT_SHEN_MASK (0x80U)
12588#define I2C_FLT_SHEN_SHIFT (7U)
12589/*! SHEN - Stop Hold Enable
12590 * 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
12591 * 0b1..Stop holdoff is enabled.
12592 */
12593#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
12594/*! @} */
12595
12596/*! @name RA - I2C Range Address register */
12597/*! @{ */
12598#define I2C_RA_RAD_MASK (0xFEU)
12599#define I2C_RA_RAD_SHIFT (1U)
12600#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
12601/*! @} */
12602
12603/*! @name SMB - I2C SMBus Control and Status register */
12604/*! @{ */
12605#define I2C_SMB_SHTF2IE_MASK (0x1U)
12606#define I2C_SMB_SHTF2IE_SHIFT (0U)
12607/*! SHTF2IE - SHTF2 Interrupt Enable
12608 * 0b0..SHTF2 interrupt is disabled
12609 * 0b1..SHTF2 interrupt is enabled
12610 */
12611#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
12612#define I2C_SMB_SHTF2_MASK (0x2U)
12613#define I2C_SMB_SHTF2_SHIFT (1U)
12614/*! SHTF2 - SCL High Timeout Flag 2
12615 * 0b0..No SCL high and SDA low timeout occurs
12616 * 0b1..SCL high and SDA low timeout occurs
12617 */
12618#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
12619#define I2C_SMB_SHTF1_MASK (0x4U)
12620#define I2C_SMB_SHTF1_SHIFT (2U)
12621/*! SHTF1 - SCL High Timeout Flag 1
12622 * 0b0..No SCL high and SDA high timeout occurs
12623 * 0b1..SCL high and SDA high timeout occurs
12624 */
12625#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
12626#define I2C_SMB_SLTF_MASK (0x8U)
12627#define I2C_SMB_SLTF_SHIFT (3U)
12628/*! SLTF - SCL Low Timeout Flag
12629 * 0b0..No low timeout occurs
12630 * 0b1..Low timeout occurs
12631 */
12632#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
12633#define I2C_SMB_TCKSEL_MASK (0x10U)
12634#define I2C_SMB_TCKSEL_SHIFT (4U)
12635/*! TCKSEL - Timeout Counter Clock Select
12636 * 0b0..Timeout counter counts at the frequency of the I2C module clock / 64
12637 * 0b1..Timeout counter counts at the frequency of the I2C module clock
12638 */
12639#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
12640#define I2C_SMB_SIICAEN_MASK (0x20U)
12641#define I2C_SMB_SIICAEN_SHIFT (5U)
12642/*! SIICAEN - Second I2C Address Enable
12643 * 0b0..I2C address register 2 matching is disabled
12644 * 0b1..I2C address register 2 matching is enabled
12645 */
12646#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
12647#define I2C_SMB_ALERTEN_MASK (0x40U)
12648#define I2C_SMB_ALERTEN_SHIFT (6U)
12649/*! ALERTEN - SMBus Alert Response Address Enable
12650 * 0b0..SMBus alert response address matching is disabled
12651 * 0b1..SMBus alert response address matching is enabled
12652 */
12653#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
12654#define I2C_SMB_FACK_MASK (0x80U)
12655#define I2C_SMB_FACK_SHIFT (7U)
12656/*! FACK - Fast NACK/ACK Enable
12657 * 0b0..An ACK or NACK is sent on the following receiving data byte
12658 * 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
12659 */
12660#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
12661/*! @} */
12662
12663/*! @name A2 - I2C Address Register 2 */
12664/*! @{ */
12665#define I2C_A2_SAD_MASK (0xFEU)
12666#define I2C_A2_SAD_SHIFT (1U)
12667#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
12668/*! @} */
12669
12670/*! @name SLTH - I2C SCL Low Timeout Register High */
12671/*! @{ */
12672#define I2C_SLTH_SSLT_MASK (0xFFU)
12673#define I2C_SLTH_SSLT_SHIFT (0U)
12674#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
12675/*! @} */
12676
12677/*! @name SLTL - I2C SCL Low Timeout Register Low */
12678/*! @{ */
12679#define I2C_SLTL_SSLT_MASK (0xFFU)
12680#define I2C_SLTL_SSLT_SHIFT (0U)
12681#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
12682/*! @} */
12683
12684
12685/*!
12686 * @}
12687 */ /* end of group I2C_Register_Masks */
12688
12689
12690/* I2C - Peripheral instance base addresses */
12691/** Peripheral I2C0 base address */
12692#define I2C0_BASE (0x40066000u)
12693/** Peripheral I2C0 base pointer */
12694#define I2C0 ((I2C_Type *)I2C0_BASE)
12695/** Peripheral I2C1 base address */
12696#define I2C1_BASE (0x40067000u)
12697/** Peripheral I2C1 base pointer */
12698#define I2C1 ((I2C_Type *)I2C1_BASE)
12699/** Peripheral I2C2 base address */
12700#define I2C2_BASE (0x400E6000u)
12701/** Peripheral I2C2 base pointer */
12702#define I2C2 ((I2C_Type *)I2C2_BASE)
12703/** Peripheral I2C3 base address */
12704#define I2C3_BASE (0x400E7000u)
12705/** Peripheral I2C3 base pointer */
12706#define I2C3 ((I2C_Type *)I2C3_BASE)
12707/** Array initializer of I2C peripheral base addresses */
12708#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE }
12709/** Array initializer of I2C peripheral base pointers */
12710#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3 }
12711/** Interrupt vectors for the I2C peripheral type */
12712#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn }
12713
12714/*!
12715 * @}
12716 */ /* end of group I2C_Peripheral_Access_Layer */
12717
12718
12719/* ----------------------------------------------------------------------------
12720 -- I2S Peripheral Access Layer
12721 ---------------------------------------------------------------------------- */
12722
12723/*!
12724 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
12725 * @{
12726 */
12727
12728/** I2S - Register Layout Typedef */
12729typedef struct {
12730 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
12731 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
12732 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
12733 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
12734 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
12735 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
12736 uint8_t RESERVED_0[8];
12737 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
12738 uint8_t RESERVED_1[24];
12739 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
12740 uint8_t RESERVED_2[24];
12741 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
12742 uint8_t RESERVED_3[28];
12743 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
12744 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
12745 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
12746 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
12747 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
12748 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
12749 uint8_t RESERVED_4[8];
12750 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
12751 uint8_t RESERVED_5[24];
12752 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
12753 uint8_t RESERVED_6[24];
12754 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
12755 uint8_t RESERVED_7[28];
12756 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
12757 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
12758} I2S_Type;
12759
12760/* ----------------------------------------------------------------------------
12761 -- I2S Register Masks
12762 ---------------------------------------------------------------------------- */
12763
12764/*!
12765 * @addtogroup I2S_Register_Masks I2S Register Masks
12766 * @{
12767 */
12768
12769/*! @name TCSR - SAI Transmit Control Register */
12770/*! @{ */
12771#define I2S_TCSR_FRDE_MASK (0x1U)
12772#define I2S_TCSR_FRDE_SHIFT (0U)
12773/*! FRDE - FIFO Request DMA Enable
12774 * 0b0..Disables the DMA request.
12775 * 0b1..Enables the DMA request.
12776 */
12777#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
12778#define I2S_TCSR_FWDE_MASK (0x2U)
12779#define I2S_TCSR_FWDE_SHIFT (1U)
12780/*! FWDE - FIFO Warning DMA Enable
12781 * 0b0..Disables the DMA request.
12782 * 0b1..Enables the DMA request.
12783 */
12784#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
12785#define I2S_TCSR_FRIE_MASK (0x100U)
12786#define I2S_TCSR_FRIE_SHIFT (8U)
12787/*! FRIE - FIFO Request Interrupt Enable
12788 * 0b0..Disables the interrupt.
12789 * 0b1..Enables the interrupt.
12790 */
12791#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
12792#define I2S_TCSR_FWIE_MASK (0x200U)
12793#define I2S_TCSR_FWIE_SHIFT (9U)
12794/*! FWIE - FIFO Warning Interrupt Enable
12795 * 0b0..Disables the interrupt.
12796 * 0b1..Enables the interrupt.
12797 */
12798#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
12799#define I2S_TCSR_FEIE_MASK (0x400U)
12800#define I2S_TCSR_FEIE_SHIFT (10U)
12801/*! FEIE - FIFO Error Interrupt Enable
12802 * 0b0..Disables the interrupt.
12803 * 0b1..Enables the interrupt.
12804 */
12805#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
12806#define I2S_TCSR_SEIE_MASK (0x800U)
12807#define I2S_TCSR_SEIE_SHIFT (11U)
12808/*! SEIE - Sync Error Interrupt Enable
12809 * 0b0..Disables interrupt.
12810 * 0b1..Enables interrupt.
12811 */
12812#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
12813#define I2S_TCSR_WSIE_MASK (0x1000U)
12814#define I2S_TCSR_WSIE_SHIFT (12U)
12815/*! WSIE - Word Start Interrupt Enable
12816 * 0b0..Disables interrupt.
12817 * 0b1..Enables interrupt.
12818 */
12819#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
12820#define I2S_TCSR_FRF_MASK (0x10000U)
12821#define I2S_TCSR_FRF_SHIFT (16U)
12822/*! FRF - FIFO Request Flag
12823 * 0b0..Transmit FIFO watermark has not been reached.
12824 * 0b1..Transmit FIFO watermark has been reached.
12825 */
12826#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
12827#define I2S_TCSR_FWF_MASK (0x20000U)
12828#define I2S_TCSR_FWF_SHIFT (17U)
12829/*! FWF - FIFO Warning Flag
12830 * 0b0..No enabled transmit FIFO is empty.
12831 * 0b1..Enabled transmit FIFO is empty.
12832 */
12833#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
12834#define I2S_TCSR_FEF_MASK (0x40000U)
12835#define I2S_TCSR_FEF_SHIFT (18U)
12836/*! FEF - FIFO Error Flag
12837 * 0b0..Transmit underrun not detected.
12838 * 0b1..Transmit underrun detected.
12839 */
12840#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
12841#define I2S_TCSR_SEF_MASK (0x80000U)
12842#define I2S_TCSR_SEF_SHIFT (19U)
12843/*! SEF - Sync Error Flag
12844 * 0b0..Sync error not detected.
12845 * 0b1..Frame sync error detected.
12846 */
12847#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
12848#define I2S_TCSR_WSF_MASK (0x100000U)
12849#define I2S_TCSR_WSF_SHIFT (20U)
12850/*! WSF - Word Start Flag
12851 * 0b0..Start of word not detected.
12852 * 0b1..Start of word detected.
12853 */
12854#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
12855#define I2S_TCSR_SR_MASK (0x1000000U)
12856#define I2S_TCSR_SR_SHIFT (24U)
12857/*! SR - Software Reset
12858 * 0b0..No effect.
12859 * 0b1..Software reset.
12860 */
12861#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
12862#define I2S_TCSR_FR_MASK (0x2000000U)
12863#define I2S_TCSR_FR_SHIFT (25U)
12864/*! FR - FIFO Reset
12865 * 0b0..No effect.
12866 * 0b1..FIFO reset.
12867 */
12868#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
12869#define I2S_TCSR_BCE_MASK (0x10000000U)
12870#define I2S_TCSR_BCE_SHIFT (28U)
12871/*! BCE - Bit Clock Enable
12872 * 0b0..Transmit bit clock is disabled.
12873 * 0b1..Transmit bit clock is enabled.
12874 */
12875#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
12876#define I2S_TCSR_DBGE_MASK (0x20000000U)
12877#define I2S_TCSR_DBGE_SHIFT (29U)
12878/*! DBGE - Debug Enable
12879 * 0b0..Transmitter is disabled in Debug mode, after completing the current frame.
12880 * 0b1..Transmitter is enabled in Debug mode.
12881 */
12882#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
12883#define I2S_TCSR_STOPE_MASK (0x40000000U)
12884#define I2S_TCSR_STOPE_SHIFT (30U)
12885/*! STOPE - Stop Enable
12886 * 0b0..Transmitter disabled in Stop mode.
12887 * 0b1..Transmitter enabled in Stop mode.
12888 */
12889#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
12890#define I2S_TCSR_TE_MASK (0x80000000U)
12891#define I2S_TCSR_TE_SHIFT (31U)
12892/*! TE - Transmitter Enable
12893 * 0b0..Transmitter is disabled.
12894 * 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
12895 */
12896#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
12897/*! @} */
12898
12899/*! @name TCR1 - SAI Transmit Configuration 1 Register */
12900/*! @{ */
12901#define I2S_TCR1_TFW_MASK (0x7U)
12902#define I2S_TCR1_TFW_SHIFT (0U)
12903#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
12904/*! @} */
12905
12906/*! @name TCR2 - SAI Transmit Configuration 2 Register */
12907/*! @{ */
12908#define I2S_TCR2_DIV_MASK (0xFFU)
12909#define I2S_TCR2_DIV_SHIFT (0U)
12910#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
12911#define I2S_TCR2_BCD_MASK (0x1000000U)
12912#define I2S_TCR2_BCD_SHIFT (24U)
12913/*! BCD - Bit Clock Direction
12914 * 0b0..Bit clock is generated externally in Slave mode.
12915 * 0b1..Bit clock is generated internally in Master mode.
12916 */
12917#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
12918#define I2S_TCR2_BCP_MASK (0x2000000U)
12919#define I2S_TCR2_BCP_SHIFT (25U)
12920/*! BCP - Bit Clock Polarity
12921 * 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
12922 * 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
12923 */
12924#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
12925#define I2S_TCR2_MSEL_MASK (0xC000000U)
12926#define I2S_TCR2_MSEL_SHIFT (26U)
12927/*! MSEL - MCLK Select
12928 * 0b00..Bus Clock selected.
12929 * 0b01..Master Clock (MCLK) 1 option selected.
12930 * 0b10..Master Clock (MCLK) 2 option selected.
12931 * 0b11..Master Clock (MCLK) 3 option selected.
12932 */
12933#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
12934#define I2S_TCR2_BCI_MASK (0x10000000U)
12935#define I2S_TCR2_BCI_SHIFT (28U)
12936/*! BCI - Bit Clock Input
12937 * 0b0..No effect.
12938 * 0b1..Internal logic is clocked as if bit clock was externally generated.
12939 */
12940#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
12941#define I2S_TCR2_BCS_MASK (0x20000000U)
12942#define I2S_TCR2_BCS_SHIFT (29U)
12943/*! BCS - Bit Clock Swap
12944 * 0b0..Use the normal bit clock source.
12945 * 0b1..Swap the bit clock source.
12946 */
12947#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
12948#define I2S_TCR2_SYNC_MASK (0xC0000000U)
12949#define I2S_TCR2_SYNC_SHIFT (30U)
12950/*! SYNC - Synchronous Mode
12951 * 0b00..Asynchronous mode.
12952 * 0b01..Synchronous with receiver.
12953 * 0b10..Synchronous with another SAI transmitter.
12954 * 0b11..Synchronous with another SAI receiver.
12955 */
12956#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
12957/*! @} */
12958
12959/*! @name TCR3 - SAI Transmit Configuration 3 Register */
12960/*! @{ */
12961#define I2S_TCR3_WDFL_MASK (0x1FU)
12962#define I2S_TCR3_WDFL_SHIFT (0U)
12963#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
12964#define I2S_TCR3_TCE_MASK (0x30000U)
12965#define I2S_TCR3_TCE_SHIFT (16U)
12966/*! TCE - Transmit Channel Enable
12967 * 0b00..Transmit data channel N is disabled.
12968 * 0b01..Transmit data channel N is enabled.
12969 */
12970#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
12971#define I2S_TCR3_CFR_MASK (0x3000000U)
12972#define I2S_TCR3_CFR_SHIFT (24U)
12973/*! CFR - Channel FIFO Reset
12974 * 0b00..No effect.
12975 * 0b01..Transmit data channel N FIFO is reset.
12976 */
12977#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
12978/*! @} */
12979
12980/*! @name TCR4 - SAI Transmit Configuration 4 Register */
12981/*! @{ */
12982#define I2S_TCR4_FSD_MASK (0x1U)
12983#define I2S_TCR4_FSD_SHIFT (0U)
12984/*! FSD - Frame Sync Direction
12985 * 0b0..Frame sync is generated externally in Slave mode.
12986 * 0b1..Frame sync is generated internally in Master mode.
12987 */
12988#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
12989#define I2S_TCR4_FSP_MASK (0x2U)
12990#define I2S_TCR4_FSP_SHIFT (1U)
12991/*! FSP - Frame Sync Polarity
12992 * 0b0..Frame sync is active high.
12993 * 0b1..Frame sync is active low.
12994 */
12995#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
12996#define I2S_TCR4_ONDEM_MASK (0x4U)
12997#define I2S_TCR4_ONDEM_SHIFT (2U)
12998/*! ONDEM - On Demand Mode
12999 * 0b0..Internal frame sync is generated continuously.
13000 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
13001 */
13002#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
13003#define I2S_TCR4_FSE_MASK (0x8U)
13004#define I2S_TCR4_FSE_SHIFT (3U)
13005/*! FSE - Frame Sync Early
13006 * 0b0..Frame sync asserts with the first bit of the frame.
13007 * 0b1..Frame sync asserts one bit before the first bit of the frame.
13008 */
13009#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
13010#define I2S_TCR4_MF_MASK (0x10U)
13011#define I2S_TCR4_MF_SHIFT (4U)
13012/*! MF - MSB First
13013 * 0b0..LSB is transmitted first.
13014 * 0b1..MSB is transmitted first.
13015 */
13016#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
13017#define I2S_TCR4_SYWD_MASK (0x1F00U)
13018#define I2S_TCR4_SYWD_SHIFT (8U)
13019#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
13020#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
13021#define I2S_TCR4_FRSZ_SHIFT (16U)
13022#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
13023#define I2S_TCR4_FPACK_MASK (0x3000000U)
13024#define I2S_TCR4_FPACK_SHIFT (24U)
13025/*! FPACK - FIFO Packing Mode
13026 * 0b00..FIFO packing is disabled
13027 * 0b01..Reserved
13028 * 0b10..8-bit FIFO packing is enabled
13029 * 0b11..16-bit FIFO packing is enabled
13030 */
13031#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
13032#define I2S_TCR4_FCOMB_MASK (0xC000000U)
13033#define I2S_TCR4_FCOMB_SHIFT (26U)
13034/*! FCOMB - FIFO Combine Mode
13035 * 0b00..FIFO combine mode disabled.
13036 * 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
13037 * 0b10..FIFO combine mode enabled on FIFO writes (by software).
13038 * 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
13039 */
13040#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
13041#define I2S_TCR4_FCONT_MASK (0x10000000U)
13042#define I2S_TCR4_FCONT_SHIFT (28U)
13043/*! FCONT - FIFO Continue on Error
13044 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
13045 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
13046 */
13047#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
13048/*! @} */
13049
13050/*! @name TCR5 - SAI Transmit Configuration 5 Register */
13051/*! @{ */
13052#define I2S_TCR5_FBT_MASK (0x1F00U)
13053#define I2S_TCR5_FBT_SHIFT (8U)
13054#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
13055#define I2S_TCR5_W0W_MASK (0x1F0000U)
13056#define I2S_TCR5_W0W_SHIFT (16U)
13057#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
13058#define I2S_TCR5_WNW_MASK (0x1F000000U)
13059#define I2S_TCR5_WNW_SHIFT (24U)
13060#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
13061/*! @} */
13062
13063/*! @name TDR - SAI Transmit Data Register */
13064/*! @{ */
13065#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
13066#define I2S_TDR_TDR_SHIFT (0U)
13067#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
13068/*! @} */
13069
13070/* The count of I2S_TDR */
13071#define I2S_TDR_COUNT (2U)
13072
13073/*! @name TFR - SAI Transmit FIFO Register */
13074/*! @{ */
13075#define I2S_TFR_RFP_MASK (0xFU)
13076#define I2S_TFR_RFP_SHIFT (0U)
13077#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
13078#define I2S_TFR_WFP_MASK (0xF0000U)
13079#define I2S_TFR_WFP_SHIFT (16U)
13080#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
13081#define I2S_TFR_WCP_MASK (0x80000000U)
13082#define I2S_TFR_WCP_SHIFT (31U)
13083/*! WCP - Write Channel Pointer
13084 * 0b0..No effect.
13085 * 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
13086 */
13087#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
13088/*! @} */
13089
13090/* The count of I2S_TFR */
13091#define I2S_TFR_COUNT (2U)
13092
13093/*! @name TMR - SAI Transmit Mask Register */
13094/*! @{ */
13095#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
13096#define I2S_TMR_TWM_SHIFT (0U)
13097/*! TWM - Transmit Word Mask
13098 * 0b00000000000000000000000000000000..Word N is enabled.
13099 * 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated when masked.
13100 */
13101#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
13102/*! @} */
13103
13104/*! @name RCSR - SAI Receive Control Register */
13105/*! @{ */
13106#define I2S_RCSR_FRDE_MASK (0x1U)
13107#define I2S_RCSR_FRDE_SHIFT (0U)
13108/*! FRDE - FIFO Request DMA Enable
13109 * 0b0..Disables the DMA request.
13110 * 0b1..Enables the DMA request.
13111 */
13112#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
13113#define I2S_RCSR_FWDE_MASK (0x2U)
13114#define I2S_RCSR_FWDE_SHIFT (1U)
13115/*! FWDE - FIFO Warning DMA Enable
13116 * 0b0..Disables the DMA request.
13117 * 0b1..Enables the DMA request.
13118 */
13119#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
13120#define I2S_RCSR_FRIE_MASK (0x100U)
13121#define I2S_RCSR_FRIE_SHIFT (8U)
13122/*! FRIE - FIFO Request Interrupt Enable
13123 * 0b0..Disables the interrupt.
13124 * 0b1..Enables the interrupt.
13125 */
13126#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
13127#define I2S_RCSR_FWIE_MASK (0x200U)
13128#define I2S_RCSR_FWIE_SHIFT (9U)
13129/*! FWIE - FIFO Warning Interrupt Enable
13130 * 0b0..Disables the interrupt.
13131 * 0b1..Enables the interrupt.
13132 */
13133#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
13134#define I2S_RCSR_FEIE_MASK (0x400U)
13135#define I2S_RCSR_FEIE_SHIFT (10U)
13136/*! FEIE - FIFO Error Interrupt Enable
13137 * 0b0..Disables the interrupt.
13138 * 0b1..Enables the interrupt.
13139 */
13140#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
13141#define I2S_RCSR_SEIE_MASK (0x800U)
13142#define I2S_RCSR_SEIE_SHIFT (11U)
13143/*! SEIE - Sync Error Interrupt Enable
13144 * 0b0..Disables interrupt.
13145 * 0b1..Enables interrupt.
13146 */
13147#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
13148#define I2S_RCSR_WSIE_MASK (0x1000U)
13149#define I2S_RCSR_WSIE_SHIFT (12U)
13150/*! WSIE - Word Start Interrupt Enable
13151 * 0b0..Disables interrupt.
13152 * 0b1..Enables interrupt.
13153 */
13154#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
13155#define I2S_RCSR_FRF_MASK (0x10000U)
13156#define I2S_RCSR_FRF_SHIFT (16U)
13157/*! FRF - FIFO Request Flag
13158 * 0b0..Receive FIFO watermark not reached.
13159 * 0b1..Receive FIFO watermark has been reached.
13160 */
13161#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
13162#define I2S_RCSR_FWF_MASK (0x20000U)
13163#define I2S_RCSR_FWF_SHIFT (17U)
13164/*! FWF - FIFO Warning Flag
13165 * 0b0..No enabled receive FIFO is full.
13166 * 0b1..Enabled receive FIFO is full.
13167 */
13168#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
13169#define I2S_RCSR_FEF_MASK (0x40000U)
13170#define I2S_RCSR_FEF_SHIFT (18U)
13171/*! FEF - FIFO Error Flag
13172 * 0b0..Receive overflow not detected.
13173 * 0b1..Receive overflow detected.
13174 */
13175#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
13176#define I2S_RCSR_SEF_MASK (0x80000U)
13177#define I2S_RCSR_SEF_SHIFT (19U)
13178/*! SEF - Sync Error Flag
13179 * 0b0..Sync error not detected.
13180 * 0b1..Frame sync error detected.
13181 */
13182#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
13183#define I2S_RCSR_WSF_MASK (0x100000U)
13184#define I2S_RCSR_WSF_SHIFT (20U)
13185/*! WSF - Word Start Flag
13186 * 0b0..Start of word not detected.
13187 * 0b1..Start of word detected.
13188 */
13189#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
13190#define I2S_RCSR_SR_MASK (0x1000000U)
13191#define I2S_RCSR_SR_SHIFT (24U)
13192/*! SR - Software Reset
13193 * 0b0..No effect.
13194 * 0b1..Software reset.
13195 */
13196#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
13197#define I2S_RCSR_FR_MASK (0x2000000U)
13198#define I2S_RCSR_FR_SHIFT (25U)
13199/*! FR - FIFO Reset
13200 * 0b0..No effect.
13201 * 0b1..FIFO reset.
13202 */
13203#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
13204#define I2S_RCSR_BCE_MASK (0x10000000U)
13205#define I2S_RCSR_BCE_SHIFT (28U)
13206/*! BCE - Bit Clock Enable
13207 * 0b0..Receive bit clock is disabled.
13208 * 0b1..Receive bit clock is enabled.
13209 */
13210#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
13211#define I2S_RCSR_DBGE_MASK (0x20000000U)
13212#define I2S_RCSR_DBGE_SHIFT (29U)
13213/*! DBGE - Debug Enable
13214 * 0b0..Receiver is disabled in Debug mode, after completing the current frame.
13215 * 0b1..Receiver is enabled in Debug mode.
13216 */
13217#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
13218#define I2S_RCSR_STOPE_MASK (0x40000000U)
13219#define I2S_RCSR_STOPE_SHIFT (30U)
13220/*! STOPE - Stop Enable
13221 * 0b0..Receiver disabled in Stop mode.
13222 * 0b1..Receiver enabled in Stop mode.
13223 */
13224#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
13225#define I2S_RCSR_RE_MASK (0x80000000U)
13226#define I2S_RCSR_RE_SHIFT (31U)
13227/*! RE - Receiver Enable
13228 * 0b0..Receiver is disabled.
13229 * 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
13230 */
13231#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
13232/*! @} */
13233
13234/*! @name RCR1 - SAI Receive Configuration 1 Register */
13235/*! @{ */
13236#define I2S_RCR1_RFW_MASK (0x7U)
13237#define I2S_RCR1_RFW_SHIFT (0U)
13238#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
13239/*! @} */
13240
13241/*! @name RCR2 - SAI Receive Configuration 2 Register */
13242/*! @{ */
13243#define I2S_RCR2_DIV_MASK (0xFFU)
13244#define I2S_RCR2_DIV_SHIFT (0U)
13245#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
13246#define I2S_RCR2_BCD_MASK (0x1000000U)
13247#define I2S_RCR2_BCD_SHIFT (24U)
13248/*! BCD - Bit Clock Direction
13249 * 0b0..Bit clock is generated externally in Slave mode.
13250 * 0b1..Bit clock is generated internally in Master mode.
13251 */
13252#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
13253#define I2S_RCR2_BCP_MASK (0x2000000U)
13254#define I2S_RCR2_BCP_SHIFT (25U)
13255/*! BCP - Bit Clock Polarity
13256 * 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
13257 * 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
13258 */
13259#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
13260#define I2S_RCR2_MSEL_MASK (0xC000000U)
13261#define I2S_RCR2_MSEL_SHIFT (26U)
13262/*! MSEL - MCLK Select
13263 * 0b00..Bus Clock selected.
13264 * 0b01..Master Clock (MCLK) 1 option selected.
13265 * 0b10..Master Clock (MCLK) 2 option selected.
13266 * 0b11..Master Clock (MCLK) 3 option selected.
13267 */
13268#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
13269#define I2S_RCR2_BCI_MASK (0x10000000U)
13270#define I2S_RCR2_BCI_SHIFT (28U)
13271/*! BCI - Bit Clock Input
13272 * 0b0..No effect.
13273 * 0b1..Internal logic is clocked as if bit clock was externally generated.
13274 */
13275#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
13276#define I2S_RCR2_BCS_MASK (0x20000000U)
13277#define I2S_RCR2_BCS_SHIFT (29U)
13278/*! BCS - Bit Clock Swap
13279 * 0b0..Use the normal bit clock source.
13280 * 0b1..Swap the bit clock source.
13281 */
13282#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
13283#define I2S_RCR2_SYNC_MASK (0xC0000000U)
13284#define I2S_RCR2_SYNC_SHIFT (30U)
13285/*! SYNC - Synchronous Mode
13286 * 0b00..Asynchronous mode.
13287 * 0b01..Synchronous with transmitter.
13288 * 0b10..Synchronous with another SAI receiver.
13289 * 0b11..Synchronous with another SAI transmitter.
13290 */
13291#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
13292/*! @} */
13293
13294/*! @name RCR3 - SAI Receive Configuration 3 Register */
13295/*! @{ */
13296#define I2S_RCR3_WDFL_MASK (0x1FU)
13297#define I2S_RCR3_WDFL_SHIFT (0U)
13298#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
13299#define I2S_RCR3_RCE_MASK (0x30000U)
13300#define I2S_RCR3_RCE_SHIFT (16U)
13301/*! RCE - Receive Channel Enable
13302 * 0b00..Receive data channel N is disabled.
13303 * 0b01..Receive data channel N is enabled.
13304 */
13305#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
13306#define I2S_RCR3_CFR_MASK (0x3000000U)
13307#define I2S_RCR3_CFR_SHIFT (24U)
13308/*! CFR - Channel FIFO Reset
13309 * 0b00..No effect.
13310 * 0b01..Receive data channel N FIFO is reset.
13311 */
13312#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
13313/*! @} */
13314
13315/*! @name RCR4 - SAI Receive Configuration 4 Register */
13316/*! @{ */
13317#define I2S_RCR4_FSD_MASK (0x1U)
13318#define I2S_RCR4_FSD_SHIFT (0U)
13319/*! FSD - Frame Sync Direction
13320 * 0b0..Frame Sync is generated externally in Slave mode.
13321 * 0b1..Frame Sync is generated internally in Master mode.
13322 */
13323#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
13324#define I2S_RCR4_FSP_MASK (0x2U)
13325#define I2S_RCR4_FSP_SHIFT (1U)
13326/*! FSP - Frame Sync Polarity
13327 * 0b0..Frame sync is active high.
13328 * 0b1..Frame sync is active low.
13329 */
13330#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
13331#define I2S_RCR4_ONDEM_MASK (0x4U)
13332#define I2S_RCR4_ONDEM_SHIFT (2U)
13333/*! ONDEM - On Demand Mode
13334 * 0b0..Internal frame sync is generated continuously.
13335 * 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
13336 */
13337#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
13338#define I2S_RCR4_FSE_MASK (0x8U)
13339#define I2S_RCR4_FSE_SHIFT (3U)
13340/*! FSE - Frame Sync Early
13341 * 0b0..Frame sync asserts with the first bit of the frame.
13342 * 0b1..Frame sync asserts one bit before the first bit of the frame.
13343 */
13344#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
13345#define I2S_RCR4_MF_MASK (0x10U)
13346#define I2S_RCR4_MF_SHIFT (4U)
13347/*! MF - MSB First
13348 * 0b0..LSB is received first.
13349 * 0b1..MSB is received first.
13350 */
13351#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
13352#define I2S_RCR4_SYWD_MASK (0x1F00U)
13353#define I2S_RCR4_SYWD_SHIFT (8U)
13354#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
13355#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
13356#define I2S_RCR4_FRSZ_SHIFT (16U)
13357#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
13358#define I2S_RCR4_FPACK_MASK (0x3000000U)
13359#define I2S_RCR4_FPACK_SHIFT (24U)
13360/*! FPACK - FIFO Packing Mode
13361 * 0b00..FIFO packing is disabled
13362 * 0b01..Reserved.
13363 * 0b10..8-bit FIFO packing is enabled
13364 * 0b11..16-bit FIFO packing is enabled
13365 */
13366#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
13367#define I2S_RCR4_FCOMB_MASK (0xC000000U)
13368#define I2S_RCR4_FCOMB_SHIFT (26U)
13369/*! FCOMB - FIFO Combine Mode
13370 * 0b00..FIFO combine mode disabled.
13371 * 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
13372 * 0b10..FIFO combine mode enabled on FIFO reads (by software).
13373 * 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
13374 */
13375#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
13376#define I2S_RCR4_FCONT_MASK (0x10000000U)
13377#define I2S_RCR4_FCONT_SHIFT (28U)
13378/*! FCONT - FIFO Continue on Error
13379 * 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
13380 * 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
13381 */
13382#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
13383/*! @} */
13384
13385/*! @name RCR5 - SAI Receive Configuration 5 Register */
13386/*! @{ */
13387#define I2S_RCR5_FBT_MASK (0x1F00U)
13388#define I2S_RCR5_FBT_SHIFT (8U)
13389#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
13390#define I2S_RCR5_W0W_MASK (0x1F0000U)
13391#define I2S_RCR5_W0W_SHIFT (16U)
13392#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
13393#define I2S_RCR5_WNW_MASK (0x1F000000U)
13394#define I2S_RCR5_WNW_SHIFT (24U)
13395#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
13396/*! @} */
13397
13398/*! @name RDR - SAI Receive Data Register */
13399/*! @{ */
13400#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
13401#define I2S_RDR_RDR_SHIFT (0U)
13402#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
13403/*! @} */
13404
13405/* The count of I2S_RDR */
13406#define I2S_RDR_COUNT (2U)
13407
13408/*! @name RFR - SAI Receive FIFO Register */
13409/*! @{ */
13410#define I2S_RFR_RFP_MASK (0xFU)
13411#define I2S_RFR_RFP_SHIFT (0U)
13412#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
13413#define I2S_RFR_RCP_MASK (0x8000U)
13414#define I2S_RFR_RCP_SHIFT (15U)
13415/*! RCP - Receive Channel Pointer
13416 * 0b0..No effect.
13417 * 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
13418 */
13419#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
13420#define I2S_RFR_WFP_MASK (0xF0000U)
13421#define I2S_RFR_WFP_SHIFT (16U)
13422#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
13423/*! @} */
13424
13425/* The count of I2S_RFR */
13426#define I2S_RFR_COUNT (2U)
13427
13428/*! @name RMR - SAI Receive Mask Register */
13429/*! @{ */
13430#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
13431#define I2S_RMR_RWM_SHIFT (0U)
13432/*! RWM - Receive Word Mask
13433 * 0b00000000000000000000000000000000..Word N is enabled.
13434 * 0b00000000000000000000000000000001..Word N is masked.
13435 */
13436#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
13437/*! @} */
13438
13439/*! @name MCR - SAI MCLK Control Register */
13440/*! @{ */
13441#define I2S_MCR_MICS_MASK (0x3000000U)
13442#define I2S_MCR_MICS_SHIFT (24U)
13443/*! MICS - MCLK Input Clock Select
13444 * 0b00..MCLK divider input clock 0 is selected.
13445 * 0b01..MCLK divider input clock 1 is selected.
13446 * 0b10..MCLK divider input clock 2 is selected.
13447 * 0b11..MCLK divider input clock 3 is selected.
13448 */
13449#define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
13450#define I2S_MCR_MOE_MASK (0x40000000U)
13451#define I2S_MCR_MOE_SHIFT (30U)
13452/*! MOE - MCLK Output Enable
13453 * 0b0..MCLK signal pin is configured as an input that bypasses the MCLK divider.
13454 * 0b1..MCLK signal pin is configured as an output from the MCLK divider and the MCLK divider is enabled.
13455 */
13456#define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
13457#define I2S_MCR_DUF_MASK (0x80000000U)
13458#define I2S_MCR_DUF_SHIFT (31U)
13459/*! DUF - Divider Update Flag
13460 * 0b0..MCLK divider ratio is not being updated currently.
13461 * 0b1..MCLK divider ratio is updating on-the-fly. Further updates to the MCLK divider ratio are blocked while this flag remains set.
13462 */
13463#define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
13464/*! @} */
13465
13466/*! @name MDR - SAI MCLK Divide Register */
13467/*! @{ */
13468#define I2S_MDR_DIVIDE_MASK (0xFFFU)
13469#define I2S_MDR_DIVIDE_SHIFT (0U)
13470#define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
13471#define I2S_MDR_FRACT_MASK (0xFF000U)
13472#define I2S_MDR_FRACT_SHIFT (12U)
13473#define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
13474/*! @} */
13475
13476
13477/*!
13478 * @}
13479 */ /* end of group I2S_Register_Masks */
13480
13481
13482/* I2S - Peripheral instance base addresses */
13483/** Peripheral I2S0 base address */
13484#define I2S0_BASE (0x4002F000u)
13485/** Peripheral I2S0 base pointer */
13486#define I2S0 ((I2S_Type *)I2S0_BASE)
13487/** Array initializer of I2S peripheral base addresses */
13488#define I2S_BASE_ADDRS { I2S0_BASE }
13489/** Array initializer of I2S peripheral base pointers */
13490#define I2S_BASE_PTRS { I2S0 }
13491/** Interrupt vectors for the I2S peripheral type */
13492#define I2S_RX_IRQS { I2S0_Rx_IRQn }
13493#define I2S_TX_IRQS { I2S0_Tx_IRQn }
13494
13495/*!
13496 * @}
13497 */ /* end of group I2S_Peripheral_Access_Layer */
13498
13499
13500/* ----------------------------------------------------------------------------
13501 -- LLWU Peripheral Access Layer
13502 ---------------------------------------------------------------------------- */
13503
13504/*!
13505 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
13506 * @{
13507 */
13508
13509/** LLWU - Register Layout Typedef */
13510typedef struct {
13511 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
13512 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
13513 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
13514 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
13515 __IO uint8_t PE5; /**< LLWU Pin Enable 5 register, offset: 0x4 */
13516 __IO uint8_t PE6; /**< LLWU Pin Enable 6 register, offset: 0x5 */
13517 __IO uint8_t PE7; /**< LLWU Pin Enable 7 register, offset: 0x6 */
13518 __IO uint8_t PE8; /**< LLWU Pin Enable 8 register, offset: 0x7 */
13519 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x8 */
13520 __IO uint8_t PF1; /**< LLWU Pin Flag 1 register, offset: 0x9 */
13521 __IO uint8_t PF2; /**< LLWU Pin Flag 2 register, offset: 0xA */
13522 __IO uint8_t PF3; /**< LLWU Pin Flag 3 register, offset: 0xB */
13523 __IO uint8_t PF4; /**< LLWU Pin Flag 4 register, offset: 0xC */
13524 __I uint8_t MF5; /**< LLWU Module Flag 5 register, offset: 0xD */
13525 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0xE */
13526 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0xF */
13527 __IO uint8_t FILT3; /**< LLWU Pin Filter 3 register, offset: 0x10 */
13528 __IO uint8_t FILT4; /**< LLWU Pin Filter 4 register, offset: 0x11 */
13529} LLWU_Type;
13530
13531/* ----------------------------------------------------------------------------
13532 -- LLWU Register Masks
13533 ---------------------------------------------------------------------------- */
13534
13535/*!
13536 * @addtogroup LLWU_Register_Masks LLWU Register Masks
13537 * @{
13538 */
13539
13540/*! @name PE1 - LLWU Pin Enable 1 register */
13541/*! @{ */
13542#define LLWU_PE1_WUPE0_MASK (0x3U)
13543#define LLWU_PE1_WUPE0_SHIFT (0U)
13544/*! WUPE0 - Wakeup Pin Enable For LLWU_P0
13545 * 0b00..External input pin disabled as wakeup input
13546 * 0b01..External input pin enabled with rising edge detection
13547 * 0b10..External input pin enabled with falling edge detection
13548 * 0b11..External input pin enabled with any change detection
13549 */
13550#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
13551#define LLWU_PE1_WUPE1_MASK (0xCU)
13552#define LLWU_PE1_WUPE1_SHIFT (2U)
13553/*! WUPE1 - Wakeup Pin Enable For LLWU_P1
13554 * 0b00..External input pin disabled as wakeup input
13555 * 0b01..External input pin enabled with rising edge detection
13556 * 0b10..External input pin enabled with falling edge detection
13557 * 0b11..External input pin enabled with any change detection
13558 */
13559#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
13560#define LLWU_PE1_WUPE2_MASK (0x30U)
13561#define LLWU_PE1_WUPE2_SHIFT (4U)
13562/*! WUPE2 - Wakeup Pin Enable For LLWU_P2
13563 * 0b00..External input pin disabled as wakeup input
13564 * 0b01..External input pin enabled with rising edge detection
13565 * 0b10..External input pin enabled with falling edge detection
13566 * 0b11..External input pin enabled with any change detection
13567 */
13568#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
13569#define LLWU_PE1_WUPE3_MASK (0xC0U)
13570#define LLWU_PE1_WUPE3_SHIFT (6U)
13571/*! WUPE3 - Wakeup Pin Enable For LLWU_P3
13572 * 0b00..External input pin disabled as wakeup input
13573 * 0b01..External input pin enabled with rising edge detection
13574 * 0b10..External input pin enabled with falling edge detection
13575 * 0b11..External input pin enabled with any change detection
13576 */
13577#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
13578/*! @} */
13579
13580/*! @name PE2 - LLWU Pin Enable 2 register */
13581/*! @{ */
13582#define LLWU_PE2_WUPE4_MASK (0x3U)
13583#define LLWU_PE2_WUPE4_SHIFT (0U)
13584/*! WUPE4 - Wakeup Pin Enable For LLWU_P4
13585 * 0b00..External input pin disabled as wakeup input
13586 * 0b01..External input pin enabled with rising edge detection
13587 * 0b10..External input pin enabled with falling edge detection
13588 * 0b11..External input pin enabled with any change detection
13589 */
13590#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
13591#define LLWU_PE2_WUPE5_MASK (0xCU)
13592#define LLWU_PE2_WUPE5_SHIFT (2U)
13593/*! WUPE5 - Wakeup Pin Enable For LLWU_P5
13594 * 0b00..External input pin disabled as wakeup input
13595 * 0b01..External input pin enabled with rising edge detection
13596 * 0b10..External input pin enabled with falling edge detection
13597 * 0b11..External input pin enabled with any change detection
13598 */
13599#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
13600#define LLWU_PE2_WUPE6_MASK (0x30U)
13601#define LLWU_PE2_WUPE6_SHIFT (4U)
13602/*! WUPE6 - Wakeup Pin Enable For LLWU_P6
13603 * 0b00..External input pin disabled as wakeup input
13604 * 0b01..External input pin enabled with rising edge detection
13605 * 0b10..External input pin enabled with falling edge detection
13606 * 0b11..External input pin enabled with any change detection
13607 */
13608#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
13609#define LLWU_PE2_WUPE7_MASK (0xC0U)
13610#define LLWU_PE2_WUPE7_SHIFT (6U)
13611/*! WUPE7 - Wakeup Pin Enable For LLWU_P7
13612 * 0b00..External input pin disabled as wakeup input
13613 * 0b01..External input pin enabled with rising edge detection
13614 * 0b10..External input pin enabled with falling edge detection
13615 * 0b11..External input pin enabled with any change detection
13616 */
13617#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
13618/*! @} */
13619
13620/*! @name PE3 - LLWU Pin Enable 3 register */
13621/*! @{ */
13622#define LLWU_PE3_WUPE8_MASK (0x3U)
13623#define LLWU_PE3_WUPE8_SHIFT (0U)
13624/*! WUPE8 - Wakeup Pin Enable For LLWU_P8
13625 * 0b00..External input pin disabled as wakeup input
13626 * 0b01..External input pin enabled with rising edge detection
13627 * 0b10..External input pin enabled with falling edge detection
13628 * 0b11..External input pin enabled with any change detection
13629 */
13630#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
13631#define LLWU_PE3_WUPE9_MASK (0xCU)
13632#define LLWU_PE3_WUPE9_SHIFT (2U)
13633/*! WUPE9 - Wakeup Pin Enable For LLWU_P9
13634 * 0b00..External input pin disabled as wakeup input
13635 * 0b01..External input pin enabled with rising edge detection
13636 * 0b10..External input pin enabled with falling edge detection
13637 * 0b11..External input pin enabled with any change detection
13638 */
13639#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
13640#define LLWU_PE3_WUPE10_MASK (0x30U)
13641#define LLWU_PE3_WUPE10_SHIFT (4U)
13642/*! WUPE10 - Wakeup Pin Enable For LLWU_P10
13643 * 0b00..External input pin disabled as wakeup input
13644 * 0b01..External input pin enabled with rising edge detection
13645 * 0b10..External input pin enabled with falling edge detection
13646 * 0b11..External input pin enabled with any change detection
13647 */
13648#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
13649#define LLWU_PE3_WUPE11_MASK (0xC0U)
13650#define LLWU_PE3_WUPE11_SHIFT (6U)
13651/*! WUPE11 - Wakeup Pin Enable For LLWU_P11
13652 * 0b00..External input pin disabled as wakeup input
13653 * 0b01..External input pin enabled with rising edge detection
13654 * 0b10..External input pin enabled with falling edge detection
13655 * 0b11..External input pin enabled with any change detection
13656 */
13657#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
13658/*! @} */
13659
13660/*! @name PE4 - LLWU Pin Enable 4 register */
13661/*! @{ */
13662#define LLWU_PE4_WUPE12_MASK (0x3U)
13663#define LLWU_PE4_WUPE12_SHIFT (0U)
13664/*! WUPE12 - Wakeup Pin Enable For LLWU_P12
13665 * 0b00..External input pin disabled as wakeup input
13666 * 0b01..External input pin enabled with rising edge detection
13667 * 0b10..External input pin enabled with falling edge detection
13668 * 0b11..External input pin enabled with any change detection
13669 */
13670#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
13671#define LLWU_PE4_WUPE13_MASK (0xCU)
13672#define LLWU_PE4_WUPE13_SHIFT (2U)
13673/*! WUPE13 - Wakeup Pin Enable For LLWU_P13
13674 * 0b00..External input pin disabled as wakeup input
13675 * 0b01..External input pin enabled with rising edge detection
13676 * 0b10..External input pin enabled with falling edge detection
13677 * 0b11..External input pin enabled with any change detection
13678 */
13679#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
13680#define LLWU_PE4_WUPE14_MASK (0x30U)
13681#define LLWU_PE4_WUPE14_SHIFT (4U)
13682/*! WUPE14 - Wakeup Pin Enable For LLWU_P14
13683 * 0b00..External input pin disabled as wakeup input
13684 * 0b01..External input pin enabled with rising edge detection
13685 * 0b10..External input pin enabled with falling edge detection
13686 * 0b11..External input pin enabled with any change detection
13687 */
13688#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
13689#define LLWU_PE4_WUPE15_MASK (0xC0U)
13690#define LLWU_PE4_WUPE15_SHIFT (6U)
13691/*! WUPE15 - Wakeup Pin Enable For LLWU_P15
13692 * 0b00..External input pin disabled as wakeup input
13693 * 0b01..External input pin enabled with rising edge detection
13694 * 0b10..External input pin enabled with falling edge detection
13695 * 0b11..External input pin enabled with any change detection
13696 */
13697#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
13698/*! @} */
13699
13700/*! @name PE5 - LLWU Pin Enable 5 register */
13701/*! @{ */
13702#define LLWU_PE5_WUPE16_MASK (0x3U)
13703#define LLWU_PE5_WUPE16_SHIFT (0U)
13704/*! WUPE16 - Wakeup Pin Enable For LLWU_P16
13705 * 0b00..External input pin disabled as wakeup input
13706 * 0b01..External input pin enabled with rising edge detection
13707 * 0b10..External input pin enabled with falling edge detection
13708 * 0b11..External input pin enabled with any change detection
13709 */
13710#define LLWU_PE5_WUPE16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK)
13711#define LLWU_PE5_WUPE17_MASK (0xCU)
13712#define LLWU_PE5_WUPE17_SHIFT (2U)
13713/*! WUPE17 - Wakeup Pin Enable For LLWU_P17
13714 * 0b00..External input pin disabled as wakeup input
13715 * 0b01..External input pin enabled with rising edge detection
13716 * 0b10..External input pin enabled with falling edge detection
13717 * 0b11..External input pin enabled with any change detection
13718 */
13719#define LLWU_PE5_WUPE17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK)
13720#define LLWU_PE5_WUPE18_MASK (0x30U)
13721#define LLWU_PE5_WUPE18_SHIFT (4U)
13722/*! WUPE18 - Wakeup Pin Enable For LLWU_P18
13723 * 0b00..External input pin disabled as wakeup input
13724 * 0b01..External input pin enabled with rising edge detection
13725 * 0b10..External input pin enabled with falling edge detection
13726 * 0b11..External input pin enabled with any change detection
13727 */
13728#define LLWU_PE5_WUPE18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK)
13729#define LLWU_PE5_WUPE19_MASK (0xC0U)
13730#define LLWU_PE5_WUPE19_SHIFT (6U)
13731/*! WUPE19 - Wakeup Pin Enable For LLWU_P19
13732 * 0b00..External input pin disabled as wakeup input
13733 * 0b01..External input pin enabled with rising edge detection
13734 * 0b10..External input pin enabled with falling edge detection
13735 * 0b11..External input pin enabled with any change detection
13736 */
13737#define LLWU_PE5_WUPE19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK)
13738/*! @} */
13739
13740/*! @name PE6 - LLWU Pin Enable 6 register */
13741/*! @{ */
13742#define LLWU_PE6_WUPE20_MASK (0x3U)
13743#define LLWU_PE6_WUPE20_SHIFT (0U)
13744/*! WUPE20 - Wakeup Pin Enable For LLWU_P20
13745 * 0b00..External input pin disabled as wakeup input
13746 * 0b01..External input pin enabled with rising edge detection
13747 * 0b10..External input pin enabled with falling edge detection
13748 * 0b11..External input pin enabled with any change detection
13749 */
13750#define LLWU_PE6_WUPE20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK)
13751#define LLWU_PE6_WUPE21_MASK (0xCU)
13752#define LLWU_PE6_WUPE21_SHIFT (2U)
13753/*! WUPE21 - Wakeup Pin Enable For LLWU_P21
13754 * 0b00..External input pin disabled as wakeup input
13755 * 0b01..External input pin enabled with rising edge detection
13756 * 0b10..External input pin enabled with falling edge detection
13757 * 0b11..External input pin enabled with any change detection
13758 */
13759#define LLWU_PE6_WUPE21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK)
13760#define LLWU_PE6_WUPE22_MASK (0x30U)
13761#define LLWU_PE6_WUPE22_SHIFT (4U)
13762/*! WUPE22 - Wakeup Pin Enable For LLWU_P22
13763 * 0b00..External input pin disabled as wakeup input
13764 * 0b01..External input pin enabled with rising edge detection
13765 * 0b10..External input pin enabled with falling edge detection
13766 * 0b11..External input pin enabled with any change detection
13767 */
13768#define LLWU_PE6_WUPE22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK)
13769#define LLWU_PE6_WUPE23_MASK (0xC0U)
13770#define LLWU_PE6_WUPE23_SHIFT (6U)
13771/*! WUPE23 - Wakeup Pin Enable For LLWU_P23
13772 * 0b00..External input pin disabled as wakeup input
13773 * 0b01..External input pin enabled with rising edge detection
13774 * 0b10..External input pin enabled with falling edge detection
13775 * 0b11..External input pin enabled with any change detection
13776 */
13777#define LLWU_PE6_WUPE23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK)
13778/*! @} */
13779
13780/*! @name PE7 - LLWU Pin Enable 7 register */
13781/*! @{ */
13782#define LLWU_PE7_WUPE24_MASK (0x3U)
13783#define LLWU_PE7_WUPE24_SHIFT (0U)
13784/*! WUPE24 - Wakeup Pin Enable For LLWU_P24
13785 * 0b00..External input pin disabled as wakeup input
13786 * 0b01..External input pin enabled with rising edge detection
13787 * 0b10..External input pin enabled with falling edge detection
13788 * 0b11..External input pin enabled with any change detection
13789 */
13790#define LLWU_PE7_WUPE24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK)
13791#define LLWU_PE7_WUPE25_MASK (0xCU)
13792#define LLWU_PE7_WUPE25_SHIFT (2U)
13793/*! WUPE25 - Wakeup Pin Enable For LLWU_P25
13794 * 0b00..External input pin disabled as wakeup input
13795 * 0b01..External input pin enabled with rising edge detection
13796 * 0b10..External input pin enabled with falling edge detection
13797 * 0b11..External input pin enabled with any change detection
13798 */
13799#define LLWU_PE7_WUPE25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK)
13800#define LLWU_PE7_WUPE26_MASK (0x30U)
13801#define LLWU_PE7_WUPE26_SHIFT (4U)
13802/*! WUPE26 - Wakeup Pin Enable For LLWU_P26
13803 * 0b00..External input pin disabled as wakeup input
13804 * 0b01..External input pin enabled with rising edge detection
13805 * 0b10..External input pin enabled with falling edge detection
13806 * 0b11..External input pin enabled with any change detection
13807 */
13808#define LLWU_PE7_WUPE26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK)
13809#define LLWU_PE7_WUPE27_MASK (0xC0U)
13810#define LLWU_PE7_WUPE27_SHIFT (6U)
13811/*! WUPE27 - Wakeup Pin Enable For LLWU_P27
13812 * 0b00..External input pin disabled as wakeup input
13813 * 0b01..External input pin enabled with rising edge detection
13814 * 0b10..External input pin enabled with falling edge detection
13815 * 0b11..External input pin enabled with any change detection
13816 */
13817#define LLWU_PE7_WUPE27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK)
13818/*! @} */
13819
13820/*! @name PE8 - LLWU Pin Enable 8 register */
13821/*! @{ */
13822#define LLWU_PE8_WUPE28_MASK (0x3U)
13823#define LLWU_PE8_WUPE28_SHIFT (0U)
13824/*! WUPE28 - Wakeup Pin Enable For LLWU_P28
13825 * 0b00..External input pin disabled as wakeup input
13826 * 0b01..External input pin enabled with rising edge detection
13827 * 0b10..External input pin enabled with falling edge detection
13828 * 0b11..External input pin enabled with any change detection
13829 */
13830#define LLWU_PE8_WUPE28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK)
13831#define LLWU_PE8_WUPE29_MASK (0xCU)
13832#define LLWU_PE8_WUPE29_SHIFT (2U)
13833/*! WUPE29 - Wakeup Pin Enable For LLWU_P29
13834 * 0b00..External input pin disabled as wakeup input
13835 * 0b01..External input pin enabled with rising edge detection
13836 * 0b10..External input pin enabled with falling edge detection
13837 * 0b11..External input pin enabled with any change detection
13838 */
13839#define LLWU_PE8_WUPE29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK)
13840#define LLWU_PE8_WUPE30_MASK (0x30U)
13841#define LLWU_PE8_WUPE30_SHIFT (4U)
13842/*! WUPE30 - Wakeup Pin Enable For LLWU_P30
13843 * 0b00..External input pin disabled as wakeup input
13844 * 0b01..External input pin enabled with rising edge detection
13845 * 0b10..External input pin enabled with falling edge detection
13846 * 0b11..External input pin enabled with any change detection
13847 */
13848#define LLWU_PE8_WUPE30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK)
13849#define LLWU_PE8_WUPE31_MASK (0xC0U)
13850#define LLWU_PE8_WUPE31_SHIFT (6U)
13851/*! WUPE31 - Wakeup Pin Enable For LLWU_P31
13852 * 0b00..External input pin disabled as wakeup input
13853 * 0b01..External input pin enabled with rising edge detection
13854 * 0b10..External input pin enabled with falling edge detection
13855 * 0b11..External input pin enabled with any change detection
13856 */
13857#define LLWU_PE8_WUPE31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK)
13858/*! @} */
13859
13860/*! @name ME - LLWU Module Enable register */
13861/*! @{ */
13862#define LLWU_ME_WUME0_MASK (0x1U)
13863#define LLWU_ME_WUME0_SHIFT (0U)
13864/*! WUME0 - Wakeup Module Enable For Module 0
13865 * 0b0..Internal module flag not used as wakeup source
13866 * 0b1..Internal module flag used as wakeup source
13867 */
13868#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
13869#define LLWU_ME_WUME1_MASK (0x2U)
13870#define LLWU_ME_WUME1_SHIFT (1U)
13871/*! WUME1 - Wakeup Module Enable for Module 1
13872 * 0b0..Internal module flag not used as wakeup source
13873 * 0b1..Internal module flag used as wakeup source
13874 */
13875#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
13876#define LLWU_ME_WUME2_MASK (0x4U)
13877#define LLWU_ME_WUME2_SHIFT (2U)
13878/*! WUME2 - Wakeup Module Enable For Module 2
13879 * 0b0..Internal module flag not used as wakeup source
13880 * 0b1..Internal module flag used as wakeup source
13881 */
13882#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
13883#define LLWU_ME_WUME3_MASK (0x8U)
13884#define LLWU_ME_WUME3_SHIFT (3U)
13885/*! WUME3 - Wakeup Module Enable For Module 3
13886 * 0b0..Internal module flag not used as wakeup source
13887 * 0b1..Internal module flag used as wakeup source
13888 */
13889#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
13890#define LLWU_ME_WUME4_MASK (0x10U)
13891#define LLWU_ME_WUME4_SHIFT (4U)
13892/*! WUME4 - Wakeup Module Enable For Module 4
13893 * 0b0..Internal module flag not used as wakeup source
13894 * 0b1..Internal module flag used as wakeup source
13895 */
13896#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
13897#define LLWU_ME_WUME5_MASK (0x20U)
13898#define LLWU_ME_WUME5_SHIFT (5U)
13899/*! WUME5 - Wakeup Module Enable For Module 5
13900 * 0b0..Internal module flag not used as wakeup source
13901 * 0b1..Internal module flag used as wakeup source
13902 */
13903#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
13904#define LLWU_ME_WUME6_MASK (0x40U)
13905#define LLWU_ME_WUME6_SHIFT (6U)
13906/*! WUME6 - Wakeup Module Enable For Module 6
13907 * 0b0..Internal module flag not used as wakeup source
13908 * 0b1..Internal module flag used as wakeup source
13909 */
13910#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
13911#define LLWU_ME_WUME7_MASK (0x80U)
13912#define LLWU_ME_WUME7_SHIFT (7U)
13913/*! WUME7 - Wakeup Module Enable For Module 7
13914 * 0b0..Internal module flag not used as wakeup source
13915 * 0b1..Internal module flag used as wakeup source
13916 */
13917#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
13918/*! @} */
13919
13920/*! @name PF1 - LLWU Pin Flag 1 register */
13921/*! @{ */
13922#define LLWU_PF1_WUF0_MASK (0x1U)
13923#define LLWU_PF1_WUF0_SHIFT (0U)
13924/*! WUF0 - Wakeup Flag For LLWU_P0
13925 * 0b0..LLWU_P0 input was not a wakeup source
13926 * 0b1..LLWU_P0 input was a wakeup source
13927 */
13928#define LLWU_PF1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK)
13929#define LLWU_PF1_WUF1_MASK (0x2U)
13930#define LLWU_PF1_WUF1_SHIFT (1U)
13931/*! WUF1 - Wakeup Flag For LLWU_P1
13932 * 0b0..LLWU_P1 input was not a wakeup source
13933 * 0b1..LLWU_P1 input was a wakeup source
13934 */
13935#define LLWU_PF1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK)
13936#define LLWU_PF1_WUF2_MASK (0x4U)
13937#define LLWU_PF1_WUF2_SHIFT (2U)
13938/*! WUF2 - Wakeup Flag For LLWU_P2
13939 * 0b0..LLWU_P2 input was not a wakeup source
13940 * 0b1..LLWU_P2 input was a wakeup source
13941 */
13942#define LLWU_PF1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK)
13943#define LLWU_PF1_WUF3_MASK (0x8U)
13944#define LLWU_PF1_WUF3_SHIFT (3U)
13945/*! WUF3 - Wakeup Flag For LLWU_P3
13946 * 0b0..LLWU_P3 input was not a wakeup source
13947 * 0b1..LLWU_P3 input was a wakeup source
13948 */
13949#define LLWU_PF1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK)
13950#define LLWU_PF1_WUF4_MASK (0x10U)
13951#define LLWU_PF1_WUF4_SHIFT (4U)
13952/*! WUF4 - Wakeup Flag For LLWU_P4
13953 * 0b0..LLWU_P4 input was not a wakeup source
13954 * 0b1..LLWU_P4 input was a wakeup source
13955 */
13956#define LLWU_PF1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK)
13957#define LLWU_PF1_WUF5_MASK (0x20U)
13958#define LLWU_PF1_WUF5_SHIFT (5U)
13959/*! WUF5 - Wakeup Flag For LLWU_P5
13960 * 0b0..LLWU_P5 input was not a wakeup source
13961 * 0b1..LLWU_P5 input was a wakeup source
13962 */
13963#define LLWU_PF1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK)
13964#define LLWU_PF1_WUF6_MASK (0x40U)
13965#define LLWU_PF1_WUF6_SHIFT (6U)
13966/*! WUF6 - Wakeup Flag For LLWU_P6
13967 * 0b0..LLWU_P6 input was not a wakeup source
13968 * 0b1..LLWU_P6 input was a wakeup source
13969 */
13970#define LLWU_PF1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK)
13971#define LLWU_PF1_WUF7_MASK (0x80U)
13972#define LLWU_PF1_WUF7_SHIFT (7U)
13973/*! WUF7 - Wakeup Flag For LLWU_P7
13974 * 0b0..LLWU_P7 input was not a wakeup source
13975 * 0b1..LLWU_P7 input was a wakeup source
13976 */
13977#define LLWU_PF1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK)
13978/*! @} */
13979
13980/*! @name PF2 - LLWU Pin Flag 2 register */
13981/*! @{ */
13982#define LLWU_PF2_WUF8_MASK (0x1U)
13983#define LLWU_PF2_WUF8_SHIFT (0U)
13984/*! WUF8 - Wakeup Flag For LLWU_P8
13985 * 0b0..LLWU_P8 input was not a wakeup source
13986 * 0b1..LLWU_P8 input was a wakeup source
13987 */
13988#define LLWU_PF2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK)
13989#define LLWU_PF2_WUF9_MASK (0x2U)
13990#define LLWU_PF2_WUF9_SHIFT (1U)
13991/*! WUF9 - Wakeup Flag For LLWU_P9
13992 * 0b0..LLWU_P9 input was not a wakeup source
13993 * 0b1..LLWU_P9 input was a wakeup source
13994 */
13995#define LLWU_PF2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK)
13996#define LLWU_PF2_WUF10_MASK (0x4U)
13997#define LLWU_PF2_WUF10_SHIFT (2U)
13998/*! WUF10 - Wakeup Flag For LLWU_P10
13999 * 0b0..LLWU_P10 input was not a wakeup source
14000 * 0b1..LLWU_P10 input was a wakeup source
14001 */
14002#define LLWU_PF2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK)
14003#define LLWU_PF2_WUF11_MASK (0x8U)
14004#define LLWU_PF2_WUF11_SHIFT (3U)
14005/*! WUF11 - Wakeup Flag For LLWU_P11
14006 * 0b0..LLWU_P11 input was not a wakeup source
14007 * 0b1..LLWU_P11 input was a wakeup source
14008 */
14009#define LLWU_PF2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK)
14010#define LLWU_PF2_WUF12_MASK (0x10U)
14011#define LLWU_PF2_WUF12_SHIFT (4U)
14012/*! WUF12 - Wakeup Flag For LLWU_P12
14013 * 0b0..LLWU_P12 input was not a wakeup source
14014 * 0b1..LLWU_P12 input was a wakeup source
14015 */
14016#define LLWU_PF2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK)
14017#define LLWU_PF2_WUF13_MASK (0x20U)
14018#define LLWU_PF2_WUF13_SHIFT (5U)
14019/*! WUF13 - Wakeup Flag For LLWU_P13
14020 * 0b0..LLWU_P13 input was not a wakeup source
14021 * 0b1..LLWU_P13 input was a wakeup source
14022 */
14023#define LLWU_PF2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK)
14024#define LLWU_PF2_WUF14_MASK (0x40U)
14025#define LLWU_PF2_WUF14_SHIFT (6U)
14026/*! WUF14 - Wakeup Flag For LLWU_P14
14027 * 0b0..LLWU_P14 input was not a wakeup source
14028 * 0b1..LLWU_P14 input was a wakeup source
14029 */
14030#define LLWU_PF2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK)
14031#define LLWU_PF2_WUF15_MASK (0x80U)
14032#define LLWU_PF2_WUF15_SHIFT (7U)
14033/*! WUF15 - Wakeup Flag For LLWU_P15
14034 * 0b0..LLWU_P15 input was not a wakeup source
14035 * 0b1..LLWU_P15 input was a wakeup source
14036 */
14037#define LLWU_PF2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK)
14038/*! @} */
14039
14040/*! @name PF3 - LLWU Pin Flag 3 register */
14041/*! @{ */
14042#define LLWU_PF3_WUF16_MASK (0x1U)
14043#define LLWU_PF3_WUF16_SHIFT (0U)
14044/*! WUF16 - Wakeup Flag For LLWU_P16
14045 * 0b0..LLWU_P16 input was not a wakeup source
14046 * 0b1..LLWU_P16 input was a wakeup source
14047 */
14048#define LLWU_PF3_WUF16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK)
14049#define LLWU_PF3_WUF17_MASK (0x2U)
14050#define LLWU_PF3_WUF17_SHIFT (1U)
14051/*! WUF17 - Wakeup Flag For LLWU_P17
14052 * 0b0..LLWU_P17 input was not a wakeup source
14053 * 0b1..LLWU_P17 input was a wakeup source
14054 */
14055#define LLWU_PF3_WUF17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK)
14056#define LLWU_PF3_WUF18_MASK (0x4U)
14057#define LLWU_PF3_WUF18_SHIFT (2U)
14058/*! WUF18 - Wakeup Flag For LLWU_P18
14059 * 0b0..LLWU_P18 input was not a wakeup source
14060 * 0b1..LLWU_P18 input was a wakeup source
14061 */
14062#define LLWU_PF3_WUF18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK)
14063#define LLWU_PF3_WUF19_MASK (0x8U)
14064#define LLWU_PF3_WUF19_SHIFT (3U)
14065/*! WUF19 - Wakeup Flag For LLWU_P19
14066 * 0b0..LLWU_P19 input was not a wakeup source
14067 * 0b1..LLWU_P19 input was a wakeup source
14068 */
14069#define LLWU_PF3_WUF19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK)
14070#define LLWU_PF3_WUF20_MASK (0x10U)
14071#define LLWU_PF3_WUF20_SHIFT (4U)
14072/*! WUF20 - Wakeup Flag For LLWU_P20
14073 * 0b0..LLWU_P20 input was not a wakeup source
14074 * 0b1..LLWU_P20 input was a wakeup source
14075 */
14076#define LLWU_PF3_WUF20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK)
14077#define LLWU_PF3_WUF21_MASK (0x20U)
14078#define LLWU_PF3_WUF21_SHIFT (5U)
14079/*! WUF21 - Wakeup Flag For LLWU_P21
14080 * 0b0..LLWU_P21 input was not a wakeup source
14081 * 0b1..LLWU_P21 input was a wakeup source
14082 */
14083#define LLWU_PF3_WUF21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK)
14084#define LLWU_PF3_WUF22_MASK (0x40U)
14085#define LLWU_PF3_WUF22_SHIFT (6U)
14086/*! WUF22 - Wakeup Flag For LLWU_P22
14087 * 0b0..LLWU_P22 input was not a wakeup source
14088 * 0b1..LLWU_P22 input was a wakeup source
14089 */
14090#define LLWU_PF3_WUF22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK)
14091#define LLWU_PF3_WUF23_MASK (0x80U)
14092#define LLWU_PF3_WUF23_SHIFT (7U)
14093/*! WUF23 - Wakeup Flag For LLWU_P23
14094 * 0b0..LLWU_P23 input was not a wakeup source
14095 * 0b1..LLWU_P23 input was a wakeup source
14096 */
14097#define LLWU_PF3_WUF23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK)
14098/*! @} */
14099
14100/*! @name PF4 - LLWU Pin Flag 4 register */
14101/*! @{ */
14102#define LLWU_PF4_WUF24_MASK (0x1U)
14103#define LLWU_PF4_WUF24_SHIFT (0U)
14104/*! WUF24 - Wakeup Flag For LLWU_P24
14105 * 0b0..LLWU_P24 input was not a wakeup source
14106 * 0b1..LLWU_P24 input was a wakeup source
14107 */
14108#define LLWU_PF4_WUF24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK)
14109#define LLWU_PF4_WUF25_MASK (0x2U)
14110#define LLWU_PF4_WUF25_SHIFT (1U)
14111/*! WUF25 - Wakeup Flag For LLWU_P25
14112 * 0b0..LLWU_P25 input was not a wakeup source
14113 * 0b1..LLWU_P25 input was a wakeup source
14114 */
14115#define LLWU_PF4_WUF25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK)
14116#define LLWU_PF4_WUF26_MASK (0x4U)
14117#define LLWU_PF4_WUF26_SHIFT (2U)
14118/*! WUF26 - Wakeup Flag For LLWU_P26
14119 * 0b0..LLWU_P26 input was not a wakeup source
14120 * 0b1..LLWU_P26 input was a wakeup source
14121 */
14122#define LLWU_PF4_WUF26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK)
14123#define LLWU_PF4_WUF27_MASK (0x8U)
14124#define LLWU_PF4_WUF27_SHIFT (3U)
14125/*! WUF27 - Wakeup Flag For LLWU_P27
14126 * 0b0..LLWU_P27 input was not a wakeup source
14127 * 0b1..LLWU_P27 input was a wakeup source
14128 */
14129#define LLWU_PF4_WUF27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK)
14130#define LLWU_PF4_WUF28_MASK (0x10U)
14131#define LLWU_PF4_WUF28_SHIFT (4U)
14132/*! WUF28 - Wakeup Flag For LLWU_P28
14133 * 0b0..LLWU_P28 input was not a wakeup source
14134 * 0b1..LLWU_P28 input was a wakeup source
14135 */
14136#define LLWU_PF4_WUF28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK)
14137#define LLWU_PF4_WUF29_MASK (0x20U)
14138#define LLWU_PF4_WUF29_SHIFT (5U)
14139/*! WUF29 - Wakeup Flag For LLWU_P29
14140 * 0b0..LLWU_P29 input was not a wakeup source
14141 * 0b1..LLWU_P29 input was a wakeup source
14142 */
14143#define LLWU_PF4_WUF29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK)
14144#define LLWU_PF4_WUF30_MASK (0x40U)
14145#define LLWU_PF4_WUF30_SHIFT (6U)
14146/*! WUF30 - Wakeup Flag For LLWU_P30
14147 * 0b0..LLWU_P30 input was not a wakeup source
14148 * 0b1..LLWU_P30 input was a wakeup source
14149 */
14150#define LLWU_PF4_WUF30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK)
14151#define LLWU_PF4_WUF31_MASK (0x80U)
14152#define LLWU_PF4_WUF31_SHIFT (7U)
14153/*! WUF31 - Wakeup Flag For LLWU_P31
14154 * 0b0..LLWU_P31 input was not a wakeup source
14155 * 0b1..LLWU_P31 input was a wakeup source
14156 */
14157#define LLWU_PF4_WUF31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK)
14158/*! @} */
14159
14160/*! @name MF5 - LLWU Module Flag 5 register */
14161/*! @{ */
14162#define LLWU_MF5_MWUF0_MASK (0x1U)
14163#define LLWU_MF5_MWUF0_SHIFT (0U)
14164/*! MWUF0 - Wakeup flag For module 0
14165 * 0b0..Module 0 input was not a wakeup source
14166 * 0b1..Module 0 input was a wakeup source
14167 */
14168#define LLWU_MF5_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK)
14169#define LLWU_MF5_MWUF1_MASK (0x2U)
14170#define LLWU_MF5_MWUF1_SHIFT (1U)
14171/*! MWUF1 - Wakeup flag For module 1
14172 * 0b0..Module 1 input was not a wakeup source
14173 * 0b1..Module 1 input was a wakeup source
14174 */
14175#define LLWU_MF5_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK)
14176#define LLWU_MF5_MWUF2_MASK (0x4U)
14177#define LLWU_MF5_MWUF2_SHIFT (2U)
14178/*! MWUF2 - Wakeup flag For module 2
14179 * 0b0..Module 2 input was not a wakeup source
14180 * 0b1..Module 2 input was a wakeup source
14181 */
14182#define LLWU_MF5_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK)
14183#define LLWU_MF5_MWUF3_MASK (0x8U)
14184#define LLWU_MF5_MWUF3_SHIFT (3U)
14185/*! MWUF3 - Wakeup flag For module 3
14186 * 0b0..Module 3 input was not a wakeup source
14187 * 0b1..Module 3 input was a wakeup source
14188 */
14189#define LLWU_MF5_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK)
14190#define LLWU_MF5_MWUF4_MASK (0x10U)
14191#define LLWU_MF5_MWUF4_SHIFT (4U)
14192/*! MWUF4 - Wakeup flag For module 4
14193 * 0b0..Module 4 input was not a wakeup source
14194 * 0b1..Module 4 input was a wakeup source
14195 */
14196#define LLWU_MF5_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK)
14197#define LLWU_MF5_MWUF5_MASK (0x20U)
14198#define LLWU_MF5_MWUF5_SHIFT (5U)
14199/*! MWUF5 - Wakeup flag For module 5
14200 * 0b0..Module 5 input was not a wakeup source
14201 * 0b1..Module 5 input was a wakeup source
14202 */
14203#define LLWU_MF5_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK)
14204#define LLWU_MF5_MWUF6_MASK (0x40U)
14205#define LLWU_MF5_MWUF6_SHIFT (6U)
14206/*! MWUF6 - Wakeup flag For module 6
14207 * 0b0..Module 6 input was not a wakeup source
14208 * 0b1..Module 6 input was a wakeup source
14209 */
14210#define LLWU_MF5_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK)
14211#define LLWU_MF5_MWUF7_MASK (0x80U)
14212#define LLWU_MF5_MWUF7_SHIFT (7U)
14213/*! MWUF7 - Wakeup flag For module 7
14214 * 0b0..Module 7 input was not a wakeup source
14215 * 0b1..Module 7 input was a wakeup source
14216 */
14217#define LLWU_MF5_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK)
14218/*! @} */
14219
14220/*! @name FILT1 - LLWU Pin Filter 1 register */
14221/*! @{ */
14222#define LLWU_FILT1_FILTSEL_MASK (0x1FU)
14223#define LLWU_FILT1_FILTSEL_SHIFT (0U)
14224/*! FILTSEL - Filter Pin Select
14225 * 0b00000..Select LLWU_P0 for filter
14226 * 0b11111..Select LLWU_P31 for filter
14227 */
14228#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
14229#define LLWU_FILT1_FILTE_MASK (0x60U)
14230#define LLWU_FILT1_FILTE_SHIFT (5U)
14231/*! FILTE - Digital Filter On External Pin
14232 * 0b00..Filter disabled
14233 * 0b01..Filter posedge detect enabled
14234 * 0b10..Filter negedge detect enabled
14235 * 0b11..Filter any edge detect enabled
14236 */
14237#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
14238#define LLWU_FILT1_FILTF_MASK (0x80U)
14239#define LLWU_FILT1_FILTF_SHIFT (7U)
14240/*! FILTF - Filter Detect Flag
14241 * 0b0..Pin Filter 1 was not a wakeup source
14242 * 0b1..Pin Filter 1 was a wakeup source
14243 */
14244#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
14245/*! @} */
14246
14247/*! @name FILT2 - LLWU Pin Filter 2 register */
14248/*! @{ */
14249#define LLWU_FILT2_FILTSEL_MASK (0x1FU)
14250#define LLWU_FILT2_FILTSEL_SHIFT (0U)
14251/*! FILTSEL - Filter Pin Select
14252 * 0b00000..Select LLWU_P0 for filter
14253 * 0b11111..Select LLWU_P31 for filter
14254 */
14255#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
14256#define LLWU_FILT2_FILTE_MASK (0x60U)
14257#define LLWU_FILT2_FILTE_SHIFT (5U)
14258/*! FILTE - Digital Filter On External Pin
14259 * 0b00..Filter disabled
14260 * 0b01..Filter posedge detect enabled
14261 * 0b10..Filter negedge detect enabled
14262 * 0b11..Filter any edge detect enabled
14263 */
14264#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
14265#define LLWU_FILT2_FILTF_MASK (0x80U)
14266#define LLWU_FILT2_FILTF_SHIFT (7U)
14267/*! FILTF - Filter Detect Flag
14268 * 0b0..Pin Filter 2 was not a wakeup source
14269 * 0b1..Pin Filter 2 was a wakeup source
14270 */
14271#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
14272/*! @} */
14273
14274/*! @name FILT3 - LLWU Pin Filter 3 register */
14275/*! @{ */
14276#define LLWU_FILT3_FILTSEL_MASK (0x1FU)
14277#define LLWU_FILT3_FILTSEL_SHIFT (0U)
14278/*! FILTSEL - Filter Pin Select
14279 * 0b00000..Select LLWU_P0 for filter
14280 * 0b11111..Select LLWU_P31 for filter
14281 */
14282#define LLWU_FILT3_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTSEL_SHIFT)) & LLWU_FILT3_FILTSEL_MASK)
14283#define LLWU_FILT3_FILTE_MASK (0x60U)
14284#define LLWU_FILT3_FILTE_SHIFT (5U)
14285/*! FILTE - Digital Filter On External Pin
14286 * 0b00..Filter disabled
14287 * 0b01..Filter posedge detect enabled
14288 * 0b10..Filter negedge detect enabled
14289 * 0b11..Filter any edge detect enabled
14290 */
14291#define LLWU_FILT3_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTE_SHIFT)) & LLWU_FILT3_FILTE_MASK)
14292#define LLWU_FILT3_FILTF_MASK (0x80U)
14293#define LLWU_FILT3_FILTF_SHIFT (7U)
14294/*! FILTF - Filter Detect Flag
14295 * 0b0..Pin Filter 3 was not a wakeup source
14296 * 0b1..Pin Filter 3 was a wakeup source
14297 */
14298#define LLWU_FILT3_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTF_SHIFT)) & LLWU_FILT3_FILTF_MASK)
14299/*! @} */
14300
14301/*! @name FILT4 - LLWU Pin Filter 4 register */
14302/*! @{ */
14303#define LLWU_FILT4_FILTSEL_MASK (0x1FU)
14304#define LLWU_FILT4_FILTSEL_SHIFT (0U)
14305/*! FILTSEL - Filter Pin Select
14306 * 0b00000..Select LLWU_P0 for filter
14307 * 0b11111..Select LLWU_P31 for filter
14308 */
14309#define LLWU_FILT4_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTSEL_SHIFT)) & LLWU_FILT4_FILTSEL_MASK)
14310#define LLWU_FILT4_FILTE_MASK (0x60U)
14311#define LLWU_FILT4_FILTE_SHIFT (5U)
14312/*! FILTE - Digital Filter On External Pin
14313 * 0b00..Filter disabled
14314 * 0b01..Filter posedge detect enabled
14315 * 0b10..Filter negedge detect enabled
14316 * 0b11..Filter any edge detect enabled
14317 */
14318#define LLWU_FILT4_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTE_SHIFT)) & LLWU_FILT4_FILTE_MASK)
14319#define LLWU_FILT4_FILTF_MASK (0x80U)
14320#define LLWU_FILT4_FILTF_SHIFT (7U)
14321/*! FILTF - Filter Detect Flag
14322 * 0b0..Pin Filter 4 was not a wakeup source
14323 * 0b1..Pin Filter 4 was a wakeup source
14324 */
14325#define LLWU_FILT4_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTF_SHIFT)) & LLWU_FILT4_FILTF_MASK)
14326/*! @} */
14327
14328
14329/*!
14330 * @}
14331 */ /* end of group LLWU_Register_Masks */
14332
14333
14334/* LLWU - Peripheral instance base addresses */
14335/** Peripheral LLWU base address */
14336#define LLWU_BASE (0x4007C000u)
14337/** Peripheral LLWU base pointer */
14338#define LLWU ((LLWU_Type *)LLWU_BASE)
14339/** Array initializer of LLWU peripheral base addresses */
14340#define LLWU_BASE_ADDRS { LLWU_BASE }
14341/** Array initializer of LLWU peripheral base pointers */
14342#define LLWU_BASE_PTRS { LLWU }
14343/** Interrupt vectors for the LLWU peripheral type */
14344#define LLWU_IRQS { LLWU_IRQn }
14345
14346/*!
14347 * @}
14348 */ /* end of group LLWU_Peripheral_Access_Layer */
14349
14350
14351/* ----------------------------------------------------------------------------
14352 -- LMEM Peripheral Access Layer
14353 ---------------------------------------------------------------------------- */
14354
14355/*!
14356 * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
14357 * @{
14358 */
14359
14360/** LMEM - Register Layout Typedef */
14361typedef struct {
14362 __IO uint32_t PCCCR; /**< Cache control register, offset: 0x0 */
14363 __IO uint32_t PCCLCR; /**< Cache line control register, offset: 0x4 */
14364 __IO uint32_t PCCSAR; /**< Cache search address register, offset: 0x8 */
14365 __IO uint32_t PCCCVR; /**< Cache read/write value register, offset: 0xC */
14366 uint8_t RESERVED_0[16];
14367 __IO uint32_t PCCRMR; /**< Cache regions mode register, offset: 0x20 */
14368} LMEM_Type;
14369
14370/* ----------------------------------------------------------------------------
14371 -- LMEM Register Masks
14372 ---------------------------------------------------------------------------- */
14373
14374/*!
14375 * @addtogroup LMEM_Register_Masks LMEM Register Masks
14376 * @{
14377 */
14378
14379/*! @name PCCCR - Cache control register */
14380/*! @{ */
14381#define LMEM_PCCCR_ENCACHE_MASK (0x1U)
14382#define LMEM_PCCCR_ENCACHE_SHIFT (0U)
14383/*! ENCACHE - Cache enable
14384 * 0b0..Cache disabled
14385 * 0b1..Cache enabled
14386 */
14387#define LMEM_PCCCR_ENCACHE(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
14388#define LMEM_PCCCR_ENWRBUF_MASK (0x2U)
14389#define LMEM_PCCCR_ENWRBUF_SHIFT (1U)
14390/*! ENWRBUF - Enable Write Buffer
14391 * 0b0..Write buffer disabled
14392 * 0b1..Write buffer enabled
14393 */
14394#define LMEM_PCCCR_ENWRBUF(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
14395#define LMEM_PCCCR_PCCR2_MASK (0x4U)
14396#define LMEM_PCCCR_PCCR2_SHIFT (2U)
14397#define LMEM_PCCCR_PCCR2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
14398#define LMEM_PCCCR_PCCR3_MASK (0x8U)
14399#define LMEM_PCCCR_PCCR3_SHIFT (3U)
14400#define LMEM_PCCCR_PCCR3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
14401#define LMEM_PCCCR_INVW0_MASK (0x1000000U)
14402#define LMEM_PCCCR_INVW0_SHIFT (24U)
14403/*! INVW0 - Invalidate Way 0
14404 * 0b0..No operation
14405 * 0b1..When setting the GO bit, invalidate all lines in way 0.
14406 */
14407#define LMEM_PCCCR_INVW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
14408#define LMEM_PCCCR_PUSHW0_MASK (0x2000000U)
14409#define LMEM_PCCCR_PUSHW0_SHIFT (25U)
14410/*! PUSHW0 - Push Way 0
14411 * 0b0..No operation
14412 * 0b1..When setting the GO bit, push all modified lines in way 0
14413 */
14414#define LMEM_PCCCR_PUSHW0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
14415#define LMEM_PCCCR_INVW1_MASK (0x4000000U)
14416#define LMEM_PCCCR_INVW1_SHIFT (26U)
14417/*! INVW1 - Invalidate Way 1
14418 * 0b0..No operation
14419 * 0b1..When setting the GO bit, invalidate all lines in way 1
14420 */
14421#define LMEM_PCCCR_INVW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
14422#define LMEM_PCCCR_PUSHW1_MASK (0x8000000U)
14423#define LMEM_PCCCR_PUSHW1_SHIFT (27U)
14424/*! PUSHW1 - Push Way 1
14425 * 0b0..No operation
14426 * 0b1..When setting the GO bit, push all modified lines in way 1
14427 */
14428#define LMEM_PCCCR_PUSHW1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
14429#define LMEM_PCCCR_GO_MASK (0x80000000U)
14430#define LMEM_PCCCR_GO_SHIFT (31U)
14431/*! GO - Initiate Cache Command
14432 * 0b0..Write: no effect. Read: no cache command active.
14433 * 0b1..Write: initiate command indicated by bits 27-24. Read: cache command active.
14434 */
14435#define LMEM_PCCCR_GO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
14436/*! @} */
14437
14438/*! @name PCCLCR - Cache line control register */
14439/*! @{ */
14440#define LMEM_PCCLCR_LGO_MASK (0x1U)
14441#define LMEM_PCCLCR_LGO_SHIFT (0U)
14442/*! LGO - Initiate Cache Line Command
14443 * 0b0..Write: no effect. Read: no line command active.
14444 * 0b1..Write: initiate line command indicated by bits 27-24. Read: line command active.
14445 */
14446#define LMEM_PCCLCR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
14447#define LMEM_PCCLCR_CACHEADDR_MASK (0xFFCU)
14448#define LMEM_PCCLCR_CACHEADDR_SHIFT (2U)
14449#define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
14450#define LMEM_PCCLCR_WSEL_MASK (0x4000U)
14451#define LMEM_PCCLCR_WSEL_SHIFT (14U)
14452/*! WSEL - Way select
14453 * 0b0..Way 0
14454 * 0b1..Way 1
14455 */
14456#define LMEM_PCCLCR_WSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
14457#define LMEM_PCCLCR_TDSEL_MASK (0x10000U)
14458#define LMEM_PCCLCR_TDSEL_SHIFT (16U)
14459/*! TDSEL - Tag/Data Select
14460 * 0b0..Data
14461 * 0b1..Tag
14462 */
14463#define LMEM_PCCLCR_TDSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
14464#define LMEM_PCCLCR_LCIVB_MASK (0x100000U)
14465#define LMEM_PCCLCR_LCIVB_SHIFT (20U)
14466#define LMEM_PCCLCR_LCIVB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
14467#define LMEM_PCCLCR_LCIMB_MASK (0x200000U)
14468#define LMEM_PCCLCR_LCIMB_SHIFT (21U)
14469#define LMEM_PCCLCR_LCIMB(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
14470#define LMEM_PCCLCR_LCWAY_MASK (0x400000U)
14471#define LMEM_PCCLCR_LCWAY_SHIFT (22U)
14472#define LMEM_PCCLCR_LCWAY(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
14473#define LMEM_PCCLCR_LCMD_MASK (0x3000000U)
14474#define LMEM_PCCLCR_LCMD_SHIFT (24U)
14475/*! LCMD - Line Command
14476 * 0b00..Search and read or write
14477 * 0b01..Invalidate
14478 * 0b10..Push
14479 * 0b11..Clear
14480 */
14481#define LMEM_PCCLCR_LCMD(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
14482#define LMEM_PCCLCR_LADSEL_MASK (0x4000000U)
14483#define LMEM_PCCLCR_LADSEL_SHIFT (26U)
14484/*! LADSEL - Line Address Select
14485 * 0b0..Cache address
14486 * 0b1..Physical address
14487 */
14488#define LMEM_PCCLCR_LADSEL(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
14489#define LMEM_PCCLCR_LACC_MASK (0x8000000U)
14490#define LMEM_PCCLCR_LACC_SHIFT (27U)
14491/*! LACC - Line access type
14492 * 0b0..Read
14493 * 0b1..Write
14494 */
14495#define LMEM_PCCLCR_LACC(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
14496/*! @} */
14497
14498/*! @name PCCSAR - Cache search address register */
14499/*! @{ */
14500#define LMEM_PCCSAR_LGO_MASK (0x1U)
14501#define LMEM_PCCSAR_LGO_SHIFT (0U)
14502/*! LGO - Initiate Cache Line Command
14503 * 0b0..Write: no effect. Read: no line command active.
14504 * 0b1..Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active.
14505 */
14506#define LMEM_PCCSAR_LGO(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
14507#define LMEM_PCCSAR_PHYADDR_MASK (0xFFFFFFFCU)
14508#define LMEM_PCCSAR_PHYADDR_SHIFT (2U)
14509#define LMEM_PCCSAR_PHYADDR(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
14510/*! @} */
14511
14512/*! @name PCCCVR - Cache read/write value register */
14513/*! @{ */
14514#define LMEM_PCCCVR_DATA_MASK (0xFFFFFFFFU)
14515#define LMEM_PCCCVR_DATA_SHIFT (0U)
14516#define LMEM_PCCCVR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
14517/*! @} */
14518
14519/*! @name PCCRMR - Cache regions mode register */
14520/*! @{ */
14521#define LMEM_PCCRMR_R15_MASK (0x3U)
14522#define LMEM_PCCRMR_R15_SHIFT (0U)
14523/*! R15 - Region 15 mode
14524 * 0b00..Non-cacheable
14525 * 0b01..Non-cacheable
14526 * 0b10..Write-through
14527 * 0b11..Write-back
14528 */
14529#define LMEM_PCCRMR_R15(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)
14530#define LMEM_PCCRMR_R14_MASK (0xCU)
14531#define LMEM_PCCRMR_R14_SHIFT (2U)
14532/*! R14 - Region 14 mode
14533 * 0b00..Non-cacheable
14534 * 0b01..Non-cacheable
14535 * 0b10..Write-through
14536 * 0b11..Write-back
14537 */
14538#define LMEM_PCCRMR_R14(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)
14539#define LMEM_PCCRMR_R13_MASK (0x30U)
14540#define LMEM_PCCRMR_R13_SHIFT (4U)
14541/*! R13 - Region 13 mode
14542 * 0b00..Non-cacheable
14543 * 0b01..Non-cacheable
14544 * 0b10..Write-through
14545 * 0b11..Write-back
14546 */
14547#define LMEM_PCCRMR_R13(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)
14548#define LMEM_PCCRMR_R12_MASK (0xC0U)
14549#define LMEM_PCCRMR_R12_SHIFT (6U)
14550/*! R12 - Region 12 mode
14551 * 0b00..Non-cacheable
14552 * 0b01..Non-cacheable
14553 * 0b10..Write-through
14554 * 0b11..Write-back
14555 */
14556#define LMEM_PCCRMR_R12(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)
14557#define LMEM_PCCRMR_R11_MASK (0x300U)
14558#define LMEM_PCCRMR_R11_SHIFT (8U)
14559/*! R11 - Region 11 mode
14560 * 0b00..Non-cacheable
14561 * 0b01..Non-cacheable
14562 * 0b10..Write-through
14563 * 0b11..Write-back
14564 */
14565#define LMEM_PCCRMR_R11(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)
14566#define LMEM_PCCRMR_R10_MASK (0xC00U)
14567#define LMEM_PCCRMR_R10_SHIFT (10U)
14568/*! R10 - Region 10 mode
14569 * 0b00..Non-cacheable
14570 * 0b01..Non-cacheable
14571 * 0b10..Write-through
14572 * 0b11..Write-back
14573 */
14574#define LMEM_PCCRMR_R10(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)
14575#define LMEM_PCCRMR_R9_MASK (0x3000U)
14576#define LMEM_PCCRMR_R9_SHIFT (12U)
14577/*! R9 - Region 9 mode
14578 * 0b00..Non-cacheable
14579 * 0b01..Non-cacheable
14580 * 0b10..Write-through
14581 * 0b11..Write-back
14582 */
14583#define LMEM_PCCRMR_R9(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)
14584#define LMEM_PCCRMR_R8_MASK (0xC000U)
14585#define LMEM_PCCRMR_R8_SHIFT (14U)
14586/*! R8 - Region 8 mode
14587 * 0b00..Non-cacheable
14588 * 0b01..Non-cacheable
14589 * 0b10..Write-through
14590 * 0b11..Write-back
14591 */
14592#define LMEM_PCCRMR_R8(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)
14593#define LMEM_PCCRMR_R7_MASK (0x30000U)
14594#define LMEM_PCCRMR_R7_SHIFT (16U)
14595/*! R7 - Region 7 mode
14596 * 0b00..Non-cacheable
14597 * 0b01..Non-cacheable
14598 * 0b10..Write-through
14599 * 0b11..Write-back
14600 */
14601#define LMEM_PCCRMR_R7(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)
14602#define LMEM_PCCRMR_R6_MASK (0xC0000U)
14603#define LMEM_PCCRMR_R6_SHIFT (18U)
14604/*! R6 - Region 6 mode
14605 * 0b00..Non-cacheable
14606 * 0b01..Non-cacheable
14607 * 0b10..Write-through
14608 * 0b11..Write-back
14609 */
14610#define LMEM_PCCRMR_R6(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)
14611#define LMEM_PCCRMR_R5_MASK (0x300000U)
14612#define LMEM_PCCRMR_R5_SHIFT (20U)
14613/*! R5 - Region 5 mode
14614 * 0b00..Non-cacheable
14615 * 0b01..Non-cacheable
14616 * 0b10..Write-through
14617 * 0b11..Write-back
14618 */
14619#define LMEM_PCCRMR_R5(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)
14620#define LMEM_PCCRMR_R4_MASK (0xC00000U)
14621#define LMEM_PCCRMR_R4_SHIFT (22U)
14622/*! R4 - Region 4 mode
14623 * 0b00..Non-cacheable
14624 * 0b01..Non-cacheable
14625 * 0b10..Write-through
14626 * 0b11..Write-back
14627 */
14628#define LMEM_PCCRMR_R4(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)
14629#define LMEM_PCCRMR_R3_MASK (0x3000000U)
14630#define LMEM_PCCRMR_R3_SHIFT (24U)
14631/*! R3 - Region 3 mode
14632 * 0b00..Non-cacheable
14633 * 0b01..Non-cacheable
14634 * 0b10..Write-through
14635 * 0b11..Write-back
14636 */
14637#define LMEM_PCCRMR_R3(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)
14638#define LMEM_PCCRMR_R2_MASK (0xC000000U)
14639#define LMEM_PCCRMR_R2_SHIFT (26U)
14640/*! R2 - Region 2 mode
14641 * 0b00..Non-cacheable
14642 * 0b01..Non-cacheable
14643 * 0b10..Write-through
14644 * 0b11..Write-back
14645 */
14646#define LMEM_PCCRMR_R2(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)
14647#define LMEM_PCCRMR_R1_MASK (0x30000000U)
14648#define LMEM_PCCRMR_R1_SHIFT (28U)
14649/*! R1 - Region 1 mode
14650 * 0b00..Non-cacheable
14651 * 0b01..Non-cacheable
14652 * 0b10..Write-through
14653 * 0b11..Write-back
14654 */
14655#define LMEM_PCCRMR_R1(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)
14656#define LMEM_PCCRMR_R0_MASK (0xC0000000U)
14657#define LMEM_PCCRMR_R0_SHIFT (30U)
14658/*! R0 - Region 0 mode
14659 * 0b00..Non-cacheable
14660 * 0b01..Non-cacheable
14661 * 0b10..Write-through
14662 * 0b11..Write-back
14663 */
14664#define LMEM_PCCRMR_R0(x) (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)
14665/*! @} */
14666
14667
14668/*!
14669 * @}
14670 */ /* end of group LMEM_Register_Masks */
14671
14672
14673/* LMEM - Peripheral instance base addresses */
14674/** Peripheral LMEM base address */
14675#define LMEM_BASE (0xE0082000u)
14676/** Peripheral LMEM base pointer */
14677#define LMEM ((LMEM_Type *)LMEM_BASE)
14678/** Array initializer of LMEM peripheral base addresses */
14679#define LMEM_BASE_ADDRS { LMEM_BASE }
14680/** Array initializer of LMEM peripheral base pointers */
14681#define LMEM_BASE_PTRS { LMEM }
14682
14683/*!
14684 * @}
14685 */ /* end of group LMEM_Peripheral_Access_Layer */
14686
14687
14688/* ----------------------------------------------------------------------------
14689 -- LPTMR Peripheral Access Layer
14690 ---------------------------------------------------------------------------- */
14691
14692/*!
14693 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
14694 * @{
14695 */
14696
14697/** LPTMR - Register Layout Typedef */
14698typedef struct {
14699 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
14700 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
14701 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
14702 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
14703} LPTMR_Type;
14704
14705/* ----------------------------------------------------------------------------
14706 -- LPTMR Register Masks
14707 ---------------------------------------------------------------------------- */
14708
14709/*!
14710 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
14711 * @{
14712 */
14713
14714/*! @name CSR - Low Power Timer Control Status Register */
14715/*! @{ */
14716#define LPTMR_CSR_TEN_MASK (0x1U)
14717#define LPTMR_CSR_TEN_SHIFT (0U)
14718/*! TEN - Timer Enable
14719 * 0b0..LPTMR is disabled and internal logic is reset.
14720 * 0b1..LPTMR is enabled.
14721 */
14722#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
14723#define LPTMR_CSR_TMS_MASK (0x2U)
14724#define LPTMR_CSR_TMS_SHIFT (1U)
14725/*! TMS - Timer Mode Select
14726 * 0b0..Time Counter mode.
14727 * 0b1..Pulse Counter mode.
14728 */
14729#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
14730#define LPTMR_CSR_TFC_MASK (0x4U)
14731#define LPTMR_CSR_TFC_SHIFT (2U)
14732/*! TFC - Timer Free-Running Counter
14733 * 0b0..CNR is reset whenever TCF is set.
14734 * 0b1..CNR is reset on overflow.
14735 */
14736#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
14737#define LPTMR_CSR_TPP_MASK (0x8U)
14738#define LPTMR_CSR_TPP_SHIFT (3U)
14739/*! TPP - Timer Pin Polarity
14740 * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
14741 * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
14742 */
14743#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
14744#define LPTMR_CSR_TPS_MASK (0x30U)
14745#define LPTMR_CSR_TPS_SHIFT (4U)
14746/*! TPS - Timer Pin Select
14747 * 0b00..Pulse counter input 0 is selected.
14748 * 0b01..Pulse counter input 1 is selected.
14749 * 0b10..Pulse counter input 2 is selected.
14750 * 0b11..Pulse counter input 3 is selected.
14751 */
14752#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
14753#define LPTMR_CSR_TIE_MASK (0x40U)
14754#define LPTMR_CSR_TIE_SHIFT (6U)
14755/*! TIE - Timer Interrupt Enable
14756 * 0b0..Timer interrupt disabled.
14757 * 0b1..Timer interrupt enabled.
14758 */
14759#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
14760#define LPTMR_CSR_TCF_MASK (0x80U)
14761#define LPTMR_CSR_TCF_SHIFT (7U)
14762/*! TCF - Timer Compare Flag
14763 * 0b0..The value of CNR is not equal to CMR and increments.
14764 * 0b1..The value of CNR is equal to CMR and increments.
14765 */
14766#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
14767/*! @} */
14768
14769/*! @name PSR - Low Power Timer Prescale Register */
14770/*! @{ */
14771#define LPTMR_PSR_PCS_MASK (0x3U)
14772#define LPTMR_PSR_PCS_SHIFT (0U)
14773/*! PCS - Prescaler Clock Select
14774 * 0b00..Prescaler/glitch filter clock 0 selected.
14775 * 0b01..Prescaler/glitch filter clock 1 selected.
14776 * 0b10..Prescaler/glitch filter clock 2 selected.
14777 * 0b11..Prescaler/glitch filter clock 3 selected.
14778 */
14779#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
14780#define LPTMR_PSR_PBYP_MASK (0x4U)
14781#define LPTMR_PSR_PBYP_SHIFT (2U)
14782/*! PBYP - Prescaler Bypass
14783 * 0b0..Prescaler/glitch filter is enabled.
14784 * 0b1..Prescaler/glitch filter is bypassed.
14785 */
14786#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
14787#define LPTMR_PSR_PRESCALE_MASK (0x78U)
14788#define LPTMR_PSR_PRESCALE_SHIFT (3U)
14789/*! PRESCALE - Prescale Value
14790 * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
14791 * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
14792 * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
14793 * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
14794 * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
14795 * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
14796 * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
14797 * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
14798 * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
14799 * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
14800 * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
14801 * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
14802 * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
14803 * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
14804 * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
14805 * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
14806 */
14807#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
14808/*! @} */
14809
14810/*! @name CMR - Low Power Timer Compare Register */
14811/*! @{ */
14812#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
14813#define LPTMR_CMR_COMPARE_SHIFT (0U)
14814#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
14815/*! @} */
14816
14817/*! @name CNR - Low Power Timer Counter Register */
14818/*! @{ */
14819#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
14820#define LPTMR_CNR_COUNTER_SHIFT (0U)
14821#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
14822/*! @} */
14823
14824
14825/*!
14826 * @}
14827 */ /* end of group LPTMR_Register_Masks */
14828
14829
14830/* LPTMR - Peripheral instance base addresses */
14831/** Peripheral LPTMR0 base address */
14832#define LPTMR0_BASE (0x40040000u)
14833/** Peripheral LPTMR0 base pointer */
14834#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
14835/** Array initializer of LPTMR peripheral base addresses */
14836#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
14837/** Array initializer of LPTMR peripheral base pointers */
14838#define LPTMR_BASE_PTRS { LPTMR0 }
14839/** Interrupt vectors for the LPTMR peripheral type */
14840#define LPTMR_IRQS { LPTMR0_IRQn }
14841
14842/*!
14843 * @}
14844 */ /* end of group LPTMR_Peripheral_Access_Layer */
14845
14846
14847/* ----------------------------------------------------------------------------
14848 -- LPUART Peripheral Access Layer
14849 ---------------------------------------------------------------------------- */
14850
14851/*!
14852 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
14853 * @{
14854 */
14855
14856/** LPUART - Register Layout Typedef */
14857typedef struct {
14858 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
14859 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
14860 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
14861 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
14862 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
14863 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
14864} LPUART_Type;
14865
14866/* ----------------------------------------------------------------------------
14867 -- LPUART Register Masks
14868 ---------------------------------------------------------------------------- */
14869
14870/*!
14871 * @addtogroup LPUART_Register_Masks LPUART Register Masks
14872 * @{
14873 */
14874
14875/*! @name BAUD - LPUART Baud Rate Register */
14876/*! @{ */
14877#define LPUART_BAUD_SBR_MASK (0x1FFFU)
14878#define LPUART_BAUD_SBR_SHIFT (0U)
14879#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
14880#define LPUART_BAUD_SBNS_MASK (0x2000U)
14881#define LPUART_BAUD_SBNS_SHIFT (13U)
14882/*! SBNS - Stop Bit Number Select
14883 * 0b0..One stop bit.
14884 * 0b1..Two stop bits.
14885 */
14886#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
14887#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
14888#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
14889/*! RXEDGIE - RX Input Active Edge Interrupt Enable
14890 * 0b0..Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
14891 * 0b1..Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
14892 */
14893#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
14894#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
14895#define LPUART_BAUD_LBKDIE_SHIFT (15U)
14896/*! LBKDIE - LIN Break Detect Interrupt Enable
14897 * 0b0..Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
14898 * 0b1..Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
14899 */
14900#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
14901#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
14902#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
14903/*! RESYNCDIS - Resynchronization Disable
14904 * 0b0..Resynchronization during received data word is supported
14905 * 0b1..Resynchronization during received data word is disabled
14906 */
14907#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
14908#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
14909#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
14910/*! BOTHEDGE - Both Edge Sampling
14911 * 0b0..Receiver samples input data using the rising edge of the baud rate clock.
14912 * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
14913 */
14914#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
14915#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
14916#define LPUART_BAUD_MATCFG_SHIFT (18U)
14917/*! MATCFG - Match Configuration
14918 * 0b00..Address Match Wakeup
14919 * 0b01..Idle Match Wakeup
14920 * 0b10..Match On and Match Off
14921 * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
14922 */
14923#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
14924#define LPUART_BAUD_RDMAE_MASK (0x200000U)
14925#define LPUART_BAUD_RDMAE_SHIFT (21U)
14926/*! RDMAE - Receiver Full DMA Enable
14927 * 0b0..DMA request disabled.
14928 * 0b1..DMA request enabled.
14929 */
14930#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
14931#define LPUART_BAUD_TDMAE_MASK (0x800000U)
14932#define LPUART_BAUD_TDMAE_SHIFT (23U)
14933/*! TDMAE - Transmitter DMA Enable
14934 * 0b0..DMA request disabled.
14935 * 0b1..DMA request enabled.
14936 */
14937#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
14938#define LPUART_BAUD_OSR_MASK (0x1F000000U)
14939#define LPUART_BAUD_OSR_SHIFT (24U)
14940#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
14941#define LPUART_BAUD_M10_MASK (0x20000000U)
14942#define LPUART_BAUD_M10_SHIFT (29U)
14943/*! M10 - 10-bit Mode select
14944 * 0b0..Receiver and transmitter use 8-bit or 9-bit data characters.
14945 * 0b1..Receiver and transmitter use 10-bit data characters.
14946 */
14947#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
14948#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
14949#define LPUART_BAUD_MAEN2_SHIFT (30U)
14950/*! MAEN2 - Match Address Mode Enable 2
14951 * 0b0..Normal operation.
14952 * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
14953 */
14954#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
14955#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
14956#define LPUART_BAUD_MAEN1_SHIFT (31U)
14957/*! MAEN1 - Match Address Mode Enable 1
14958 * 0b0..Normal operation.
14959 * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
14960 */
14961#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
14962/*! @} */
14963
14964/*! @name STAT - LPUART Status Register */
14965/*! @{ */
14966#define LPUART_STAT_MA2F_MASK (0x4000U)
14967#define LPUART_STAT_MA2F_SHIFT (14U)
14968/*! MA2F - Match 2 Flag
14969 * 0b0..Received data is not equal to MA2
14970 * 0b1..Received data is equal to MA2
14971 */
14972#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
14973#define LPUART_STAT_MA1F_MASK (0x8000U)
14974#define LPUART_STAT_MA1F_SHIFT (15U)
14975/*! MA1F - Match 1 Flag
14976 * 0b0..Received data is not equal to MA1
14977 * 0b1..Received data is equal to MA1
14978 */
14979#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
14980#define LPUART_STAT_PF_MASK (0x10000U)
14981#define LPUART_STAT_PF_SHIFT (16U)
14982/*! PF - Parity Error Flag
14983 * 0b0..No parity error.
14984 * 0b1..Parity error.
14985 */
14986#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
14987#define LPUART_STAT_FE_MASK (0x20000U)
14988#define LPUART_STAT_FE_SHIFT (17U)
14989/*! FE - Framing Error Flag
14990 * 0b0..No framing error detected. This does not guarantee the framing is correct.
14991 * 0b1..Framing error.
14992 */
14993#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
14994#define LPUART_STAT_NF_MASK (0x40000U)
14995#define LPUART_STAT_NF_SHIFT (18U)
14996/*! NF - Noise Flag
14997 * 0b0..No noise detected.
14998 * 0b1..Noise detected in the received character in LPUART_DATA.
14999 */
15000#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
15001#define LPUART_STAT_OR_MASK (0x80000U)
15002#define LPUART_STAT_OR_SHIFT (19U)
15003/*! OR - Receiver Overrun Flag
15004 * 0b0..No overrun.
15005 * 0b1..Receive overrun (new LPUART data lost).
15006 */
15007#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
15008#define LPUART_STAT_IDLE_MASK (0x100000U)
15009#define LPUART_STAT_IDLE_SHIFT (20U)
15010/*! IDLE - Idle Line Flag
15011 * 0b0..No idle line detected.
15012 * 0b1..Idle line was detected.
15013 */
15014#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
15015#define LPUART_STAT_RDRF_MASK (0x200000U)
15016#define LPUART_STAT_RDRF_SHIFT (21U)
15017/*! RDRF - Receive Data Register Full Flag
15018 * 0b0..Receive data buffer empty.
15019 * 0b1..Receive data buffer full.
15020 */
15021#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
15022#define LPUART_STAT_TC_MASK (0x400000U)
15023#define LPUART_STAT_TC_SHIFT (22U)
15024/*! TC - Transmission Complete Flag
15025 * 0b0..Transmitter active (sending data, a preamble, or a break).
15026 * 0b1..Transmitter idle (transmission activity complete).
15027 */
15028#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
15029#define LPUART_STAT_TDRE_MASK (0x800000U)
15030#define LPUART_STAT_TDRE_SHIFT (23U)
15031/*! TDRE - Transmit Data Register Empty Flag
15032 * 0b0..Transmit data buffer full.
15033 * 0b1..Transmit data buffer empty.
15034 */
15035#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
15036#define LPUART_STAT_RAF_MASK (0x1000000U)
15037#define LPUART_STAT_RAF_SHIFT (24U)
15038/*! RAF - Receiver Active Flag
15039 * 0b0..LPUART receiver idle waiting for a start bit.
15040 * 0b1..LPUART receiver active (LPUART_RX input not idle).
15041 */
15042#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
15043#define LPUART_STAT_LBKDE_MASK (0x2000000U)
15044#define LPUART_STAT_LBKDE_SHIFT (25U)
15045/*! LBKDE - LIN Break Detection Enable
15046 * 0b0..Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
15047 * 0b1..Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
15048 */
15049#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
15050#define LPUART_STAT_BRK13_MASK (0x4000000U)
15051#define LPUART_STAT_BRK13_SHIFT (26U)
15052/*! BRK13 - Break Character Generation Length
15053 * 0b0..Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
15054 * 0b1..Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
15055 */
15056#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
15057#define LPUART_STAT_RWUID_MASK (0x8000000U)
15058#define LPUART_STAT_RWUID_SHIFT (27U)
15059/*! RWUID - Receive Wake Up Idle Detect
15060 * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.
15061 * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.
15062 */
15063#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
15064#define LPUART_STAT_RXINV_MASK (0x10000000U)
15065#define LPUART_STAT_RXINV_SHIFT (28U)
15066/*! RXINV - Receive Data Inversion
15067 * 0b0..Receive data not inverted.
15068 * 0b1..Receive data inverted.
15069 */
15070#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
15071#define LPUART_STAT_MSBF_MASK (0x20000000U)
15072#define LPUART_STAT_MSBF_SHIFT (29U)
15073/*! MSBF - MSB First
15074 * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
15075 * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
15076 */
15077#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
15078#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
15079#define LPUART_STAT_RXEDGIF_SHIFT (30U)
15080/*! RXEDGIF - LPUART_RX Pin Active Edge Interrupt Flag
15081 * 0b0..No active edge on the receive pin has occurred.
15082 * 0b1..An active edge on the receive pin has occurred.
15083 */
15084#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
15085#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
15086#define LPUART_STAT_LBKDIF_SHIFT (31U)
15087/*! LBKDIF - LIN Break Detect Interrupt Flag
15088 * 0b0..No LIN break character has been detected.
15089 * 0b1..LIN break character has been detected.
15090 */
15091#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
15092/*! @} */
15093
15094/*! @name CTRL - LPUART Control Register */
15095/*! @{ */
15096#define LPUART_CTRL_PT_MASK (0x1U)
15097#define LPUART_CTRL_PT_SHIFT (0U)
15098/*! PT - Parity Type
15099 * 0b0..Even parity.
15100 * 0b1..Odd parity.
15101 */
15102#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
15103#define LPUART_CTRL_PE_MASK (0x2U)
15104#define LPUART_CTRL_PE_SHIFT (1U)
15105/*! PE - Parity Enable
15106 * 0b0..No hardware parity generation or checking.
15107 * 0b1..Parity enabled.
15108 */
15109#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
15110#define LPUART_CTRL_ILT_MASK (0x4U)
15111#define LPUART_CTRL_ILT_SHIFT (2U)
15112/*! ILT - Idle Line Type Select
15113 * 0b0..Idle character bit count starts after start bit.
15114 * 0b1..Idle character bit count starts after stop bit.
15115 */
15116#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
15117#define LPUART_CTRL_WAKE_MASK (0x8U)
15118#define LPUART_CTRL_WAKE_SHIFT (3U)
15119/*! WAKE - Receiver Wakeup Method Select
15120 * 0b0..Configures RWU for idle-line wakeup.
15121 * 0b1..Configures RWU with address-mark wakeup.
15122 */
15123#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
15124#define LPUART_CTRL_M_MASK (0x10U)
15125#define LPUART_CTRL_M_SHIFT (4U)
15126/*! M - 9-Bit or 8-Bit Mode Select
15127 * 0b0..Receiver and transmitter use 8-bit data characters.
15128 * 0b1..Receiver and transmitter use 9-bit data characters.
15129 */
15130#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
15131#define LPUART_CTRL_RSRC_MASK (0x20U)
15132#define LPUART_CTRL_RSRC_SHIFT (5U)
15133/*! RSRC - Receiver Source Select
15134 * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin.
15135 * 0b1..Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input.
15136 */
15137#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
15138#define LPUART_CTRL_DOZEEN_MASK (0x40U)
15139#define LPUART_CTRL_DOZEEN_SHIFT (6U)
15140/*! DOZEEN - Doze Enable
15141 * 0b0..LPUART is enabled in Doze mode.
15142 * 0b1..LPUART is disabled in Doze mode.
15143 */
15144#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
15145#define LPUART_CTRL_LOOPS_MASK (0x80U)
15146#define LPUART_CTRL_LOOPS_SHIFT (7U)
15147/*! LOOPS - Loop Mode Select
15148 * 0b0..Normal operation - LPUART_RX and LPUART_TX use separate pins.
15149 * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
15150 */
15151#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
15152#define LPUART_CTRL_IDLECFG_MASK (0x700U)
15153#define LPUART_CTRL_IDLECFG_SHIFT (8U)
15154/*! IDLECFG - Idle Configuration
15155 * 0b000..1 idle character
15156 * 0b001..2 idle characters
15157 * 0b010..4 idle characters
15158 * 0b011..8 idle characters
15159 * 0b100..16 idle characters
15160 * 0b101..32 idle characters
15161 * 0b110..64 idle characters
15162 * 0b111..128 idle characters
15163 */
15164#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
15165#define LPUART_CTRL_MA2IE_MASK (0x4000U)
15166#define LPUART_CTRL_MA2IE_SHIFT (14U)
15167/*! MA2IE - Match 2 Interrupt Enable
15168 * 0b0..MA2F interrupt disabled
15169 * 0b1..MA2F interrupt enabled
15170 */
15171#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
15172#define LPUART_CTRL_MA1IE_MASK (0x8000U)
15173#define LPUART_CTRL_MA1IE_SHIFT (15U)
15174/*! MA1IE - Match 1 Interrupt Enable
15175 * 0b0..MA1F interrupt disabled
15176 * 0b1..MA1F interrupt enabled
15177 */
15178#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
15179#define LPUART_CTRL_SBK_MASK (0x10000U)
15180#define LPUART_CTRL_SBK_SHIFT (16U)
15181/*! SBK - Send Break
15182 * 0b0..Normal transmitter operation.
15183 * 0b1..Queue break character(s) to be sent.
15184 */
15185#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
15186#define LPUART_CTRL_RWU_MASK (0x20000U)
15187#define LPUART_CTRL_RWU_SHIFT (17U)
15188/*! RWU - Receiver Wakeup Control
15189 * 0b0..Normal receiver operation.
15190 * 0b1..LPUART receiver in standby waiting for wakeup condition.
15191 */
15192#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
15193#define LPUART_CTRL_RE_MASK (0x40000U)
15194#define LPUART_CTRL_RE_SHIFT (18U)
15195/*! RE - Receiver Enable
15196 * 0b0..Receiver disabled.
15197 * 0b1..Receiver enabled.
15198 */
15199#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
15200#define LPUART_CTRL_TE_MASK (0x80000U)
15201#define LPUART_CTRL_TE_SHIFT (19U)
15202/*! TE - Transmitter Enable
15203 * 0b0..Transmitter disabled.
15204 * 0b1..Transmitter enabled.
15205 */
15206#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
15207#define LPUART_CTRL_ILIE_MASK (0x100000U)
15208#define LPUART_CTRL_ILIE_SHIFT (20U)
15209/*! ILIE - Idle Line Interrupt Enable
15210 * 0b0..Hardware interrupts from IDLE disabled; use polling.
15211 * 0b1..Hardware interrupt requested when IDLE flag is 1.
15212 */
15213#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
15214#define LPUART_CTRL_RIE_MASK (0x200000U)
15215#define LPUART_CTRL_RIE_SHIFT (21U)
15216/*! RIE - Receiver Interrupt Enable
15217 * 0b0..Hardware interrupts from RDRF disabled; use polling.
15218 * 0b1..Hardware interrupt requested when RDRF flag is 1.
15219 */
15220#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
15221#define LPUART_CTRL_TCIE_MASK (0x400000U)
15222#define LPUART_CTRL_TCIE_SHIFT (22U)
15223/*! TCIE - Transmission Complete Interrupt Enable for
15224 * 0b0..Hardware interrupts from TC disabled; use polling.
15225 * 0b1..Hardware interrupt requested when TC flag is 1.
15226 */
15227#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
15228#define LPUART_CTRL_TIE_MASK (0x800000U)
15229#define LPUART_CTRL_TIE_SHIFT (23U)
15230/*! TIE - Transmit Interrupt Enable
15231 * 0b0..Hardware interrupts from TDRE disabled; use polling.
15232 * 0b1..Hardware interrupt requested when TDRE flag is 1.
15233 */
15234#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
15235#define LPUART_CTRL_PEIE_MASK (0x1000000U)
15236#define LPUART_CTRL_PEIE_SHIFT (24U)
15237/*! PEIE - Parity Error Interrupt Enable
15238 * 0b0..PF interrupts disabled; use polling).
15239 * 0b1..Hardware interrupt requested when PF is set.
15240 */
15241#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
15242#define LPUART_CTRL_FEIE_MASK (0x2000000U)
15243#define LPUART_CTRL_FEIE_SHIFT (25U)
15244/*! FEIE - Framing Error Interrupt Enable
15245 * 0b0..FE interrupts disabled; use polling.
15246 * 0b1..Hardware interrupt requested when FE is set.
15247 */
15248#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
15249#define LPUART_CTRL_NEIE_MASK (0x4000000U)
15250#define LPUART_CTRL_NEIE_SHIFT (26U)
15251/*! NEIE - Noise Error Interrupt Enable
15252 * 0b0..NF interrupts disabled; use polling.
15253 * 0b1..Hardware interrupt requested when NF is set.
15254 */
15255#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
15256#define LPUART_CTRL_ORIE_MASK (0x8000000U)
15257#define LPUART_CTRL_ORIE_SHIFT (27U)
15258/*! ORIE - Overrun Interrupt Enable
15259 * 0b0..OR interrupts disabled; use polling.
15260 * 0b1..Hardware interrupt requested when OR is set.
15261 */
15262#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
15263#define LPUART_CTRL_TXINV_MASK (0x10000000U)
15264#define LPUART_CTRL_TXINV_SHIFT (28U)
15265/*! TXINV - Transmit Data Inversion
15266 * 0b0..Transmit data not inverted.
15267 * 0b1..Transmit data inverted.
15268 */
15269#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
15270#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
15271#define LPUART_CTRL_TXDIR_SHIFT (29U)
15272/*! TXDIR - LPUART_TX Pin Direction in Single-Wire Mode
15273 * 0b0..LPUART_TX pin is an input in single-wire mode.
15274 * 0b1..LPUART_TX pin is an output in single-wire mode.
15275 */
15276#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
15277#define LPUART_CTRL_R9T8_MASK (0x40000000U)
15278#define LPUART_CTRL_R9T8_SHIFT (30U)
15279#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
15280#define LPUART_CTRL_R8T9_MASK (0x80000000U)
15281#define LPUART_CTRL_R8T9_SHIFT (31U)
15282#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
15283/*! @} */
15284
15285/*! @name DATA - LPUART Data Register */
15286/*! @{ */
15287#define LPUART_DATA_R0T0_MASK (0x1U)
15288#define LPUART_DATA_R0T0_SHIFT (0U)
15289#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
15290#define LPUART_DATA_R1T1_MASK (0x2U)
15291#define LPUART_DATA_R1T1_SHIFT (1U)
15292#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
15293#define LPUART_DATA_R2T2_MASK (0x4U)
15294#define LPUART_DATA_R2T2_SHIFT (2U)
15295#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
15296#define LPUART_DATA_R3T3_MASK (0x8U)
15297#define LPUART_DATA_R3T3_SHIFT (3U)
15298#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
15299#define LPUART_DATA_R4T4_MASK (0x10U)
15300#define LPUART_DATA_R4T4_SHIFT (4U)
15301#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
15302#define LPUART_DATA_R5T5_MASK (0x20U)
15303#define LPUART_DATA_R5T5_SHIFT (5U)
15304#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
15305#define LPUART_DATA_R6T6_MASK (0x40U)
15306#define LPUART_DATA_R6T6_SHIFT (6U)
15307#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
15308#define LPUART_DATA_R7T7_MASK (0x80U)
15309#define LPUART_DATA_R7T7_SHIFT (7U)
15310#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
15311#define LPUART_DATA_R8T8_MASK (0x100U)
15312#define LPUART_DATA_R8T8_SHIFT (8U)
15313#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
15314#define LPUART_DATA_R9T9_MASK (0x200U)
15315#define LPUART_DATA_R9T9_SHIFT (9U)
15316#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
15317#define LPUART_DATA_IDLINE_MASK (0x800U)
15318#define LPUART_DATA_IDLINE_SHIFT (11U)
15319/*! IDLINE - Idle Line
15320 * 0b0..Receiver was not idle before receiving this character.
15321 * 0b1..Receiver was idle before receiving this character.
15322 */
15323#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
15324#define LPUART_DATA_RXEMPT_MASK (0x1000U)
15325#define LPUART_DATA_RXEMPT_SHIFT (12U)
15326/*! RXEMPT - Receive Buffer Empty
15327 * 0b0..Receive buffer contains valid data.
15328 * 0b1..Receive buffer is empty, data returned on read is not valid.
15329 */
15330#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
15331#define LPUART_DATA_FRETSC_MASK (0x2000U)
15332#define LPUART_DATA_FRETSC_SHIFT (13U)
15333/*! FRETSC - Frame Error / Transmit Special Character
15334 * 0b0..The dataword was received without a frame error on read, transmit a normal character on write.
15335 * 0b1..The dataword was received with a frame error, transmit an idle or break character on transmit.
15336 */
15337#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
15338#define LPUART_DATA_PARITYE_MASK (0x4000U)
15339#define LPUART_DATA_PARITYE_SHIFT (14U)
15340/*! PARITYE
15341 * 0b0..The dataword was received without a parity error.
15342 * 0b1..The dataword was received with a parity error.
15343 */
15344#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
15345#define LPUART_DATA_NOISY_MASK (0x8000U)
15346#define LPUART_DATA_NOISY_SHIFT (15U)
15347/*! NOISY
15348 * 0b0..The dataword was received without noise.
15349 * 0b1..The data was received with noise.
15350 */
15351#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
15352/*! @} */
15353
15354/*! @name MATCH - LPUART Match Address Register */
15355/*! @{ */
15356#define LPUART_MATCH_MA1_MASK (0x3FFU)
15357#define LPUART_MATCH_MA1_SHIFT (0U)
15358#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
15359#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
15360#define LPUART_MATCH_MA2_SHIFT (16U)
15361#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
15362/*! @} */
15363
15364/*! @name MODIR - LPUART Modem IrDA Register */
15365/*! @{ */
15366#define LPUART_MODIR_TXCTSE_MASK (0x1U)
15367#define LPUART_MODIR_TXCTSE_SHIFT (0U)
15368/*! TXCTSE - Transmitter clear-to-send enable
15369 * 0b0..CTS has no effect on the transmitter.
15370 * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
15371 */
15372#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
15373#define LPUART_MODIR_TXRTSE_MASK (0x2U)
15374#define LPUART_MODIR_TXRTSE_SHIFT (1U)
15375/*! TXRTSE - Transmitter request-to-send enable
15376 * 0b0..The transmitter has no effect on RTS.
15377 * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.
15378 */
15379#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
15380#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
15381#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
15382/*! TXRTSPOL - Transmitter request-to-send polarity
15383 * 0b0..Transmitter RTS is active low.
15384 * 0b1..Transmitter RTS is active high.
15385 */
15386#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
15387#define LPUART_MODIR_RXRTSE_MASK (0x8U)
15388#define LPUART_MODIR_RXRTSE_SHIFT (3U)
15389/*! RXRTSE - Receiver request-to-send enable
15390 * 0b0..The receiver has no effect on RTS.
15391 * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.
15392 */
15393#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
15394#define LPUART_MODIR_TXCTSC_MASK (0x10U)
15395#define LPUART_MODIR_TXCTSC_SHIFT (4U)
15396/*! TXCTSC - Transmit CTS Configuration
15397 * 0b0..CTS input is sampled at the start of each character.
15398 * 0b1..CTS input is sampled when the transmitter is idle.
15399 */
15400#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
15401#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
15402#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
15403/*! TXCTSSRC - Transmit CTS Source
15404 * 0b0..CTS input is the LPUART_CTS pin.
15405 * 0b1..CTS input is the inverted Receiver Match result.
15406 */
15407#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
15408#define LPUART_MODIR_TNP_MASK (0x30000U)
15409#define LPUART_MODIR_TNP_SHIFT (16U)
15410/*! TNP - Transmitter narrow pulse
15411 * 0b00..1/OSR.
15412 * 0b01..2/OSR.
15413 * 0b10..3/OSR.
15414 * 0b11..4/OSR.
15415 */
15416#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
15417#define LPUART_MODIR_IREN_MASK (0x40000U)
15418#define LPUART_MODIR_IREN_SHIFT (18U)
15419/*! IREN - Infrared enable
15420 * 0b0..IR disabled.
15421 * 0b1..IR enabled.
15422 */
15423#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
15424/*! @} */
15425
15426
15427/*!
15428 * @}
15429 */ /* end of group LPUART_Register_Masks */
15430
15431
15432/* LPUART - Peripheral instance base addresses */
15433/** Peripheral LPUART0 base address */
15434#define LPUART0_BASE (0x400C4000u)
15435/** Peripheral LPUART0 base pointer */
15436#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
15437/** Array initializer of LPUART peripheral base addresses */
15438#define LPUART_BASE_ADDRS { LPUART0_BASE }
15439/** Array initializer of LPUART peripheral base pointers */
15440#define LPUART_BASE_PTRS { LPUART0 }
15441/** Interrupt vectors for the LPUART peripheral type */
15442#define LPUART_RX_TX_IRQS { LPUART0_IRQn }
15443#define LPUART_ERR_IRQS { LPUART0_IRQn }
15444
15445/*!
15446 * @}
15447 */ /* end of group LPUART_Peripheral_Access_Layer */
15448
15449
15450/* ----------------------------------------------------------------------------
15451 -- MCG Peripheral Access Layer
15452 ---------------------------------------------------------------------------- */
15453
15454/*!
15455 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
15456 * @{
15457 */
15458
15459/** MCG - Register Layout Typedef */
15460typedef struct {
15461 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
15462 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
15463 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
15464 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
15465 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
15466 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
15467 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
15468 uint8_t RESERVED_0[1];
15469 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
15470 uint8_t RESERVED_1[1];
15471 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
15472 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
15473 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
15474 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
15475 __IO uint8_t C9; /**< MCG Control 9 Register, offset: 0xE */
15476 uint8_t RESERVED_2[1];
15477 __IO uint8_t C11; /**< MCG Control 11 Register, offset: 0x10 */
15478 uint8_t RESERVED_3[1];
15479 __I uint8_t S2; /**< MCG Status 2 Register, offset: 0x12 */
15480} MCG_Type;
15481
15482/* ----------------------------------------------------------------------------
15483 -- MCG Register Masks
15484 ---------------------------------------------------------------------------- */
15485
15486/*!
15487 * @addtogroup MCG_Register_Masks MCG Register Masks
15488 * @{
15489 */
15490
15491/*! @name C1 - MCG Control 1 Register */
15492/*! @{ */
15493#define MCG_C1_IREFSTEN_MASK (0x1U)
15494#define MCG_C1_IREFSTEN_SHIFT (0U)
15495/*! IREFSTEN - Internal Reference Stop Enable
15496 * 0b0..Internal reference clock is disabled in Stop mode.
15497 * 0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
15498 */
15499#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
15500#define MCG_C1_IRCLKEN_MASK (0x2U)
15501#define MCG_C1_IRCLKEN_SHIFT (1U)
15502/*! IRCLKEN - Internal Reference Clock Enable
15503 * 0b0..MCGIRCLK inactive.
15504 * 0b1..MCGIRCLK active.
15505 */
15506#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
15507#define MCG_C1_IREFS_MASK (0x4U)
15508#define MCG_C1_IREFS_SHIFT (2U)
15509/*! IREFS - Internal Reference Select
15510 * 0b0..External reference clock is selected.
15511 * 0b1..The slow internal reference clock is selected.
15512 */
15513#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
15514#define MCG_C1_FRDIV_MASK (0x38U)
15515#define MCG_C1_FRDIV_SHIFT (3U)
15516/*! FRDIV - FLL External Reference Divider
15517 * 0b000..If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.
15518 * 0b001..If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.
15519 * 0b010..If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.
15520 * 0b011..If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
15521 * 0b100..If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.
15522 * 0b101..If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.
15523 * 0b110..If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 .
15524 * 0b111..If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .
15525 */
15526#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
15527#define MCG_C1_CLKS_MASK (0xC0U)
15528#define MCG_C1_CLKS_SHIFT (6U)
15529/*! CLKS - Clock Source Select
15530 * 0b00..Encoding 0 - Output of FLL or PLLCS is selected (depends on PLLS control bit).
15531 * 0b01..Encoding 1 - Internal reference clock is selected.
15532 * 0b10..Encoding 2 - External reference clock is selected.
15533 * 0b11..Encoding 3 - Reserved.
15534 */
15535#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
15536/*! @} */
15537
15538/*! @name C2 - MCG Control 2 Register */
15539/*! @{ */
15540#define MCG_C2_IRCS_MASK (0x1U)
15541#define MCG_C2_IRCS_SHIFT (0U)
15542/*! IRCS - Internal Reference Clock Select
15543 * 0b0..Slow internal reference clock selected.
15544 * 0b1..Fast internal reference clock selected.
15545 */
15546#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
15547#define MCG_C2_LP_MASK (0x2U)
15548#define MCG_C2_LP_SHIFT (1U)
15549/*! LP - Low Power Select
15550 * 0b0..FLL or PLL is not disabled in bypass modes.
15551 * 0b1..FLL or PLL is disabled in bypass modes (lower power)
15552 */
15553#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
15554#define MCG_C2_EREFS_MASK (0x4U)
15555#define MCG_C2_EREFS_SHIFT (2U)
15556/*! EREFS - External Reference Select
15557 * 0b0..External reference clock requested.
15558 * 0b1..Oscillator requested.
15559 */
15560#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
15561#define MCG_C2_HGO_MASK (0x8U)
15562#define MCG_C2_HGO_SHIFT (3U)
15563/*! HGO - High Gain Oscillator Select
15564 * 0b0..Configure crystal oscillator for low-power operation.
15565 * 0b1..Configure crystal oscillator for high-gain operation.
15566 */
15567#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
15568#define MCG_C2_RANGE_MASK (0x30U)
15569#define MCG_C2_RANGE_SHIFT (4U)
15570/*! RANGE - Frequency Range Select
15571 * 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator .
15572 * 0b01..Encoding 1 - High frequency range selected for the crystal oscillator .
15573 * 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator .
15574 */
15575#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
15576#define MCG_C2_FCFTRIM_MASK (0x40U)
15577#define MCG_C2_FCFTRIM_SHIFT (6U)
15578#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
15579#define MCG_C2_LOCRE0_MASK (0x80U)
15580#define MCG_C2_LOCRE0_SHIFT (7U)
15581/*! LOCRE0 - Loss of Clock Reset Enable
15582 * 0b0..Interrupt request is generated on a loss of OSC0 external reference clock.
15583 * 0b1..Generate a reset request on a loss of OSC0 external reference clock.
15584 */
15585#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
15586/*! @} */
15587
15588/*! @name C3 - MCG Control 3 Register */
15589/*! @{ */
15590#define MCG_C3_SCTRIM_MASK (0xFFU)
15591#define MCG_C3_SCTRIM_SHIFT (0U)
15592#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
15593/*! @} */
15594
15595/*! @name C4 - MCG Control 4 Register */
15596/*! @{ */
15597#define MCG_C4_SCFTRIM_MASK (0x1U)
15598#define MCG_C4_SCFTRIM_SHIFT (0U)
15599#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
15600#define MCG_C4_FCTRIM_MASK (0x1EU)
15601#define MCG_C4_FCTRIM_SHIFT (1U)
15602#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
15603#define MCG_C4_DRST_DRS_MASK (0x60U)
15604#define MCG_C4_DRST_DRS_SHIFT (5U)
15605/*! DRST_DRS - DCO Range Select
15606 * 0b00..Encoding 0 - Low range (reset default).
15607 * 0b01..Encoding 1 - Mid range.
15608 * 0b10..Encoding 2 - Mid-high range.
15609 * 0b11..Encoding 3 - High range.
15610 */
15611#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
15612#define MCG_C4_DMX32_MASK (0x80U)
15613#define MCG_C4_DMX32_SHIFT (7U)
15614/*! DMX32 - DCO Maximum Frequency with 32.768 kHz Reference
15615 * 0b0..DCO has a default range of 25%.
15616 * 0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
15617 */
15618#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
15619/*! @} */
15620
15621/*! @name C5 - MCG Control 5 Register */
15622/*! @{ */
15623#define MCG_C5_PRDIV_MASK (0x7U)
15624#define MCG_C5_PRDIV_SHIFT (0U)
15625/*! PRDIV - PLL External Reference Divider
15626 * 0b000..Divide Factor is 1
15627 * 0b001..Divide Factor is 2
15628 * 0b010..Divide Factor is 3
15629 * 0b011..Divide Factor is 4
15630 * 0b100..Divide Factor is 5
15631 * 0b101..Divide Factor is 6
15632 * 0b110..Divide Factor is 7
15633 * 0b111..Divide Factor is 8
15634 */
15635#define MCG_C5_PRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
15636#define MCG_C5_PLLSTEN_MASK (0x20U)
15637#define MCG_C5_PLLSTEN_SHIFT (5U)
15638/*! PLLSTEN - PLL Stop Enable
15639 * 0b0..MCGPLLCLK and MCGPLLCLK2X are disabled in any of the Stop modes.
15640 * 0b1..MCGPLLCLK and MCGPLLCLK2X are enabled if system is in Normal Stop mode.
15641 */
15642#define MCG_C5_PLLSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
15643#define MCG_C5_PLLCLKEN_MASK (0x40U)
15644#define MCG_C5_PLLCLKEN_SHIFT (6U)
15645/*! PLLCLKEN - PLL Clock Enable
15646 * 0b0..MCGPLLCLK is inactive.
15647 * 0b1..MCGPLLCLK is active.
15648 */
15649#define MCG_C5_PLLCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
15650/*! @} */
15651
15652/*! @name C6 - MCG Control 6 Register */
15653/*! @{ */
15654#define MCG_C6_VDIV_MASK (0x1FU)
15655#define MCG_C6_VDIV_SHIFT (0U)
15656/*! VDIV - VCO Divider
15657 * 0b00000..Multiply Factor is 16
15658 * 0b00001..Multiply Factor is 17
15659 * 0b00010..Multiply Factor is 18
15660 * 0b00011..Multiply Factor is 19
15661 * 0b00100..Multiply Factor is 20
15662 * 0b00101..Multiply Factor is 21
15663 * 0b00110..Multiply Factor is 22
15664 * 0b00111..Multiply Factor is 23
15665 * 0b01000..Multiply Factor is 24
15666 * 0b01001..Multiply Factor is 25
15667 * 0b01010..Multiply Factor is 26
15668 * 0b01011..Multiply Factor is 27
15669 * 0b01100..Multiply Factor is 28
15670 * 0b01101..Multiply Factor is 29
15671 * 0b01110..Multiply Factor is 30
15672 * 0b01111..Multiply Factor is 31
15673 * 0b10000..Multiply Factor is 32
15674 * 0b10001..Multiply Factor is 33
15675 * 0b10010..Multiply Factor is 34
15676 * 0b10011..Multiply Factor is 35
15677 * 0b10100..Multiply Factor is 36
15678 * 0b10101..Multiply Factor is 37
15679 * 0b10110..Multiply Factor is 38
15680 * 0b10111..Multiply Factor is 39
15681 * 0b11000..Multiply Factor is 40
15682 * 0b11001..Multiply Factor is 41
15683 * 0b11010..Multiply Factor is 42
15684 * 0b11011..Multiply Factor is 43
15685 * 0b11100..Multiply Factor is 44
15686 * 0b11101..Multiply Factor is 45
15687 * 0b11110..Multiply Factor is 46
15688 * 0b11111..Multiply Factor is 47
15689 */
15690#define MCG_C6_VDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
15691#define MCG_C6_CME0_MASK (0x20U)
15692#define MCG_C6_CME0_SHIFT (5U)
15693/*! CME0 - Clock Monitor Enable
15694 * 0b0..External clock monitor is disabled for OSC0.
15695 * 0b1..External clock monitor is enabled for OSC0.
15696 */
15697#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
15698#define MCG_C6_PLLS_MASK (0x40U)
15699#define MCG_C6_PLLS_SHIFT (6U)
15700/*! PLLS - PLL Select
15701 * 0b0..FLL is selected.
15702 * 0b1..PLLCS output clock is selected (PRDIV0 bits of PLL in the C5 register need to be programmed to the correct divider to generate a PLL reference clock in the range specified in the data sheet (fpll_ref) prior to setting the PLLS bit).
15703 */
15704#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
15705#define MCG_C6_LOLIE0_MASK (0x80U)
15706#define MCG_C6_LOLIE0_SHIFT (7U)
15707/*! LOLIE0 - Loss of Lock Interrrupt Enable
15708 * 0b0..No interrupt request is generated on loss of lock.
15709 * 0b1..Generate an interrupt request on loss of lock.
15710 */
15711#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
15712/*! @} */
15713
15714/*! @name S - MCG Status Register */
15715/*! @{ */
15716#define MCG_S_IRCST_MASK (0x1U)
15717#define MCG_S_IRCST_SHIFT (0U)
15718/*! IRCST - Internal Reference Clock Status
15719 * 0b0..Source of internal reference clock is the slow clock (32 kHz IRC).
15720 * 0b1..Source of internal reference clock is the fast clock (4 MHz IRC).
15721 */
15722#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
15723#define MCG_S_OSCINIT0_MASK (0x2U)
15724#define MCG_S_OSCINIT0_SHIFT (1U)
15725#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
15726#define MCG_S_CLKST_MASK (0xCU)
15727#define MCG_S_CLKST_SHIFT (2U)
15728/*! CLKST - Clock Mode Status
15729 * 0b00..Encoding 0 - Output of the FLL is selected (reset default).
15730 * 0b01..Encoding 1 - Internal reference clock is selected.
15731 * 0b10..Encoding 2 - External reference clock is selected.
15732 * 0b11..Encoding 3 - Output of the PLL is selected.
15733 */
15734#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
15735#define MCG_S_IREFST_MASK (0x10U)
15736#define MCG_S_IREFST_SHIFT (4U)
15737/*! IREFST - Internal Reference Status
15738 * 0b0..Source of FLL reference clock is the external reference clock.
15739 * 0b1..Source of FLL reference clock is the internal reference clock.
15740 */
15741#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
15742#define MCG_S_PLLST_MASK (0x20U)
15743#define MCG_S_PLLST_SHIFT (5U)
15744/*! PLLST - PLL Select Status
15745 * 0b0..Source of PLLS clock is FLL clock.
15746 * 0b1..Source of PLLS clock is PLLCS output clock.
15747 */
15748#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
15749#define MCG_S_LOCK0_MASK (0x40U)
15750#define MCG_S_LOCK0_SHIFT (6U)
15751/*! LOCK0 - Lock Status
15752 * 0b0..PLL is currently unlocked.
15753 * 0b1..PLL is currently locked.
15754 */
15755#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
15756#define MCG_S_LOLS0_MASK (0x80U)
15757#define MCG_S_LOLS0_SHIFT (7U)
15758/*! LOLS0 - Loss of Lock Status
15759 * 0b0..PLL has not lost lock since LOLS 0 was last cleared.
15760 * 0b1..PLL has lost lock since LOLS 0 was last cleared.
15761 */
15762#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
15763/*! @} */
15764
15765/*! @name SC - MCG Status and Control Register */
15766/*! @{ */
15767#define MCG_SC_LOCS0_MASK (0x1U)
15768#define MCG_SC_LOCS0_SHIFT (0U)
15769/*! LOCS0 - OSC0 Loss of Clock Status
15770 * 0b0..Loss of OSC0 has not occurred.
15771 * 0b1..Loss of OSC0 has occurred.
15772 */
15773#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
15774#define MCG_SC_FCRDIV_MASK (0xEU)
15775#define MCG_SC_FCRDIV_SHIFT (1U)
15776/*! FCRDIV - Fast Clock Internal Reference Divider
15777 * 0b000..Divide Factor is 1
15778 * 0b001..Divide Factor is 2.
15779 * 0b010..Divide Factor is 4.
15780 * 0b011..Divide Factor is 8.
15781 * 0b100..Divide Factor is 16
15782 * 0b101..Divide Factor is 32
15783 * 0b110..Divide Factor is 64
15784 * 0b111..Divide Factor is 128.
15785 */
15786#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
15787#define MCG_SC_FLTPRSRV_MASK (0x10U)
15788#define MCG_SC_FLTPRSRV_SHIFT (4U)
15789/*! FLTPRSRV - FLL Filter Preserve Enable
15790 * 0b0..FLL filter and FLL frequency will reset on changes to currect clock mode.
15791 * 0b1..Fll filter and FLL frequency retain their previous values during new clock mode change.
15792 */
15793#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
15794#define MCG_SC_ATMF_MASK (0x20U)
15795#define MCG_SC_ATMF_SHIFT (5U)
15796/*! ATMF - Automatic Trim Machine Fail Flag
15797 * 0b0..Automatic Trim Machine completed normally.
15798 * 0b1..Automatic Trim Machine failed.
15799 */
15800#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
15801#define MCG_SC_ATMS_MASK (0x40U)
15802#define MCG_SC_ATMS_SHIFT (6U)
15803/*! ATMS - Automatic Trim Machine Select
15804 * 0b0..32 kHz Internal Reference Clock selected.
15805 * 0b1..4 MHz Internal Reference Clock selected.
15806 */
15807#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
15808#define MCG_SC_ATME_MASK (0x80U)
15809#define MCG_SC_ATME_SHIFT (7U)
15810/*! ATME - Automatic Trim Machine Enable
15811 * 0b0..Auto Trim Machine disabled.
15812 * 0b1..Auto Trim Machine enabled.
15813 */
15814#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
15815/*! @} */
15816
15817/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
15818/*! @{ */
15819#define MCG_ATCVH_ATCVH_MASK (0xFFU)
15820#define MCG_ATCVH_ATCVH_SHIFT (0U)
15821#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
15822/*! @} */
15823
15824/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
15825/*! @{ */
15826#define MCG_ATCVL_ATCVL_MASK (0xFFU)
15827#define MCG_ATCVL_ATCVL_SHIFT (0U)
15828#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
15829/*! @} */
15830
15831/*! @name C7 - MCG Control 7 Register */
15832/*! @{ */
15833#define MCG_C7_OSCSEL_MASK (0x3U)
15834#define MCG_C7_OSCSEL_SHIFT (0U)
15835/*! OSCSEL - MCG OSC Clock Select
15836 * 0b00..Selects Oscillator (OSCCLK0).
15837 * 0b01..Selects 32 kHz RTC Oscillator.
15838 * 0b10..Selects Oscillator (OSCCLK1).
15839 * 0b11..RESERVED
15840 */
15841#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
15842/*! @} */
15843
15844/*! @name C8 - MCG Control 8 Register */
15845/*! @{ */
15846#define MCG_C8_LOCS1_MASK (0x1U)
15847#define MCG_C8_LOCS1_SHIFT (0U)
15848/*! LOCS1 - RTC Loss of Clock Status
15849 * 0b0..Loss of RTC has not occur.
15850 * 0b1..Loss of RTC has occur
15851 */
15852#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
15853#define MCG_C8_CME1_MASK (0x20U)
15854#define MCG_C8_CME1_SHIFT (5U)
15855/*! CME1 - Clock Monitor Enable1
15856 * 0b0..External clock monitor is disabled for RTC clock.
15857 * 0b1..External clock monitor is enabled for RTC clock.
15858 */
15859#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
15860#define MCG_C8_LOLRE_MASK (0x40U)
15861#define MCG_C8_LOLRE_SHIFT (6U)
15862/*! LOLRE - PLL Loss of Lock Reset Enable
15863 * 0b0..Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request.
15864 * 0b1..Generate a reset request on a PLL loss of lock indication.
15865 */
15866#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
15867#define MCG_C8_LOCRE1_MASK (0x80U)
15868#define MCG_C8_LOCRE1_SHIFT (7U)
15869/*! LOCRE1 - Loss of Clock Reset Enable
15870 * 0b0..Interrupt request is generated on a loss of RTC external reference clock.
15871 * 0b1..Generate a reset request on a loss of RTC external reference clock
15872 */
15873#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
15874/*! @} */
15875
15876/*! @name C9 - MCG Control 9 Register */
15877/*! @{ */
15878#define MCG_C9_EXT_PLL_LOCS_MASK (0x1U)
15879#define MCG_C9_EXT_PLL_LOCS_SHIFT (0U)
15880/*! EXT_PLL_LOCS - External PLL Loss of Clock Status
15881 * 0b0..Loss of MCG EXT_PLL has not occurred.
15882 * 0b1..Loss of MCG EXT_PLL has occurred.
15883 */
15884#define MCG_C9_EXT_PLL_LOCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_EXT_PLL_LOCS_SHIFT)) & MCG_C9_EXT_PLL_LOCS_MASK)
15885#define MCG_C9_PLL_LOCRE_MASK (0x10U)
15886#define MCG_C9_PLL_LOCRE_SHIFT (4U)
15887/*! PLL_LOCRE - MCG External PLL Loss of Clock Reset Enable
15888 * 0b0..Interrupt request is generated on a invalid or loss of the MCG external PLL clock.
15889 * 0b1..Generates a system reset request on a invalid or loss of the MCG external PLL clock.
15890 */
15891#define MCG_C9_PLL_LOCRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_LOCRE_SHIFT)) & MCG_C9_PLL_LOCRE_MASK)
15892#define MCG_C9_PLL_CME_MASK (0x20U)
15893#define MCG_C9_PLL_CME_SHIFT (5U)
15894/*! PLL_CME - MCG External PLL Clock Monitor Enable
15895 * 0b0..External clock monitor is disabled for EXT_PLL clock.
15896 * 0b1..External clock monitor is enabled for EXT_PLL clock.
15897 */
15898#define MCG_C9_PLL_CME(x) (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_CME_SHIFT)) & MCG_C9_PLL_CME_MASK)
15899/*! @} */
15900
15901/*! @name C11 - MCG Control 11 Register */
15902/*! @{ */
15903#define MCG_C11_PLLCS_MASK (0x10U)
15904#define MCG_C11_PLLCS_SHIFT (4U)
15905/*! PLLCS - PLL Clock Select
15906 * 0b0..PLL0 output clock is selected.
15907 * 0b1..External PLL clock is selected.
15908 */
15909#define MCG_C11_PLLCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C11_PLLCS_SHIFT)) & MCG_C11_PLLCS_MASK)
15910/*! @} */
15911
15912/*! @name S2 - MCG Status 2 Register */
15913/*! @{ */
15914#define MCG_S2_PLLCST_MASK (0x10U)
15915#define MCG_S2_PLLCST_SHIFT (4U)
15916/*! PLLCST - PLL Clock Select Status
15917 * 0b0..Source of PLLCS is PLL clock.
15918 * 0b1..Source of PLLCS is EXT_PLL clock.
15919 */
15920#define MCG_S2_PLLCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S2_PLLCST_SHIFT)) & MCG_S2_PLLCST_MASK)
15921/*! @} */
15922
15923
15924/*!
15925 * @}
15926 */ /* end of group MCG_Register_Masks */
15927
15928
15929/* MCG - Peripheral instance base addresses */
15930/** Peripheral MCG base address */
15931#define MCG_BASE (0x40064000u)
15932/** Peripheral MCG base pointer */
15933#define MCG ((MCG_Type *)MCG_BASE)
15934/** Array initializer of MCG peripheral base addresses */
15935#define MCG_BASE_ADDRS { MCG_BASE }
15936/** Array initializer of MCG peripheral base pointers */
15937#define MCG_BASE_PTRS { MCG }
15938/* MCG C5[PLLCLKEN0] backward compatibility */
15939#define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK)
15940#define MCG_C5_PLLCLKEN0_SHIFT (MCG_C5_PLLCLKEN_SHIFT)
15941#define MCG_C5_PLLCLKEN0_WIDTH (MCG_C5_PLLCLKEN_WIDTH)
15942#define MCG_C5_PLLCLKEN0(x) (MCG_C5_PLLCLKEN(x))
15943
15944/* MCG C5[PLLSTEN0] backward compatibility */
15945#define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK)
15946#define MCG_C5_PLLSTEN0_SHIFT (MCG_C5_PLLSTEN_SHIFT)
15947#define MCG_C5_PLLSTEN0_WIDTH (MCG_C5_PLLSTEN_WIDTH)
15948#define MCG_C5_PLLSTEN0(x) (MCG_C5_PLLSTEN(x))
15949
15950/* MCG C5[PRDIV0] backward compatibility */
15951#define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK)
15952#define MCG_C5_PRDIV0_SHIFT (MCG_C5_PRDIV_SHIFT)
15953#define MCG_C5_PRDIV0_WIDTH (MCG_C5_PRDIV_WIDTH)
15954#define MCG_C5_PRDIV0(x) (MCG_C5_PRDIV(x))
15955
15956/* MCG C6[VDIV0] backward compatibility */
15957#define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK)
15958#define MCG_C6_VDIV0_SHIFT (MCG_C6_VDIV_SHIFT)
15959#define MCG_C6_VDIV0_WIDTH (MCG_C6_VDIV_WIDTH)
15960#define MCG_C6_VDIV0(x) (MCG_C6_VDIV(x))
15961
15962
15963/*!
15964 * @}
15965 */ /* end of group MCG_Peripheral_Access_Layer */
15966
15967
15968/* ----------------------------------------------------------------------------
15969 -- MCM Peripheral Access Layer
15970 ---------------------------------------------------------------------------- */
15971
15972/*!
15973 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
15974 * @{
15975 */
15976
15977/** MCM - Register Layout Typedef */
15978typedef struct {
15979 uint8_t RESERVED_0[8];
15980 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
15981 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
15982 __IO uint32_t CR; /**< Control Register, offset: 0xC */
15983 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
15984 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
15985 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
15986 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
15987 __I uint32_t FADR; /**< Fault address register, offset: 0x20 */
15988 __I uint32_t FATR; /**< Fault attributes register, offset: 0x24 */
15989 __I uint32_t FDR; /**< Fault data register, offset: 0x28 */
15990 uint8_t RESERVED_1[4];
15991 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
15992 uint8_t RESERVED_2[12];
15993 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
15994} MCM_Type;
15995
15996/* ----------------------------------------------------------------------------
15997 -- MCM Register Masks
15998 ---------------------------------------------------------------------------- */
15999
16000/*!
16001 * @addtogroup MCM_Register_Masks MCM Register Masks
16002 * @{
16003 */
16004
16005/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
16006/*! @{ */
16007#define MCM_PLASC_ASC_MASK (0xFFU)
16008#define MCM_PLASC_ASC_SHIFT (0U)
16009/*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
16010 * 0b00000000..A bus slave connection to AXBS input port n is absent
16011 * 0b00000001..A bus slave connection to AXBS input port n is present
16012 */
16013#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
16014/*! @} */
16015
16016/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
16017/*! @{ */
16018#define MCM_PLAMC_AMC_MASK (0xFFU)
16019#define MCM_PLAMC_AMC_SHIFT (0U)
16020/*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
16021 * 0b00000000..A bus master connection to AXBS input port n is absent
16022 * 0b00000001..A bus master connection to AXBS input port n is present
16023 */
16024#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
16025/*! @} */
16026
16027/*! @name CR - Control Register */
16028/*! @{ */
16029#define MCM_CR_SRAMUAP_MASK (0x3000000U)
16030#define MCM_CR_SRAMUAP_SHIFT (24U)
16031/*! SRAMUAP - SRAM_U arbitration priority
16032 * 0b00..Round robin
16033 * 0b01..Special round robin (favors SRAM backoor accesses over the processor)
16034 * 0b10..Fixed priority. Processor has highest, backdoor has lowest
16035 * 0b11..Fixed priority. Backdoor has highest, processor has lowest
16036 */
16037#define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
16038#define MCM_CR_SRAMUWP_MASK (0x4000000U)
16039#define MCM_CR_SRAMUWP_SHIFT (26U)
16040#define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
16041#define MCM_CR_SRAMLAP_MASK (0x30000000U)
16042#define MCM_CR_SRAMLAP_SHIFT (28U)
16043/*! SRAMLAP - SRAM_L arbitration priority
16044 * 0b00..Round robin
16045 * 0b01..Special round robin (favors SRAM backoor accesses over the processor)
16046 * 0b10..Fixed priority. Processor has highest, backdoor has lowest
16047 * 0b11..Fixed priority. Backdoor has highest, processor has lowest
16048 */
16049#define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
16050#define MCM_CR_SRAMLWP_MASK (0x40000000U)
16051#define MCM_CR_SRAMLWP_SHIFT (30U)
16052#define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
16053/*! @} */
16054
16055/*! @name ISCR - Interrupt Status Register */
16056/*! @{ */
16057#define MCM_ISCR_IRQ_MASK (0x2U)
16058#define MCM_ISCR_IRQ_SHIFT (1U)
16059/*! IRQ - Normal Interrupt Pending
16060 * 0b0..No pending interrupt
16061 * 0b1..Due to the ETB counter expiring, a normal interrupt is pending
16062 */
16063#define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
16064#define MCM_ISCR_NMI_MASK (0x4U)
16065#define MCM_ISCR_NMI_SHIFT (2U)
16066/*! NMI - Non-maskable Interrupt Pending
16067 * 0b0..No pending NMI
16068 * 0b1..Due to the ETB counter expiring, an NMI is pending
16069 */
16070#define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
16071#define MCM_ISCR_DHREQ_MASK (0x8U)
16072#define MCM_ISCR_DHREQ_SHIFT (3U)
16073/*! DHREQ - Debug Halt Request Indicator
16074 * 0b0..No debug halt request
16075 * 0b1..Debug halt request initiated
16076 */
16077#define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
16078#define MCM_ISCR_FIOC_MASK (0x100U)
16079#define MCM_ISCR_FIOC_SHIFT (8U)
16080/*! FIOC - FPU invalid operation interrupt status
16081 * 0b0..No interrupt
16082 * 0b1..Interrupt occurred
16083 */
16084#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
16085#define MCM_ISCR_FDZC_MASK (0x200U)
16086#define MCM_ISCR_FDZC_SHIFT (9U)
16087/*! FDZC - FPU divide-by-zero interrupt status
16088 * 0b0..No interrupt
16089 * 0b1..Interrupt occurred
16090 */
16091#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
16092#define MCM_ISCR_FOFC_MASK (0x400U)
16093#define MCM_ISCR_FOFC_SHIFT (10U)
16094/*! FOFC - FPU overflow interrupt status
16095 * 0b0..No interrupt
16096 * 0b1..Interrupt occurred
16097 */
16098#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
16099#define MCM_ISCR_FUFC_MASK (0x800U)
16100#define MCM_ISCR_FUFC_SHIFT (11U)
16101/*! FUFC - FPU underflow interrupt status
16102 * 0b0..No interrupt
16103 * 0b1..Interrupt occurred
16104 */
16105#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
16106#define MCM_ISCR_FIXC_MASK (0x1000U)
16107#define MCM_ISCR_FIXC_SHIFT (12U)
16108/*! FIXC - FPU inexact interrupt status
16109 * 0b0..No interrupt
16110 * 0b1..Interrupt occurred
16111 */
16112#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
16113#define MCM_ISCR_FIDC_MASK (0x8000U)
16114#define MCM_ISCR_FIDC_SHIFT (15U)
16115/*! FIDC - FPU input denormal interrupt status
16116 * 0b0..No interrupt
16117 * 0b1..Interrupt occurred
16118 */
16119#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
16120#define MCM_ISCR_FIOCE_MASK (0x1000000U)
16121#define MCM_ISCR_FIOCE_SHIFT (24U)
16122/*! FIOCE - FPU invalid operation interrupt enable
16123 * 0b0..Disable interrupt
16124 * 0b1..Enable interrupt
16125 */
16126#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
16127#define MCM_ISCR_FDZCE_MASK (0x2000000U)
16128#define MCM_ISCR_FDZCE_SHIFT (25U)
16129/*! FDZCE - FPU divide-by-zero interrupt enable
16130 * 0b0..Disable interrupt
16131 * 0b1..Enable interrupt
16132 */
16133#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
16134#define MCM_ISCR_FOFCE_MASK (0x4000000U)
16135#define MCM_ISCR_FOFCE_SHIFT (26U)
16136/*! FOFCE - FPU overflow interrupt enable
16137 * 0b0..Disable interrupt
16138 * 0b1..Enable interrupt
16139 */
16140#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
16141#define MCM_ISCR_FUFCE_MASK (0x8000000U)
16142#define MCM_ISCR_FUFCE_SHIFT (27U)
16143/*! FUFCE - FPU underflow interrupt enable
16144 * 0b0..Disable interrupt
16145 * 0b1..Enable interrupt
16146 */
16147#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
16148#define MCM_ISCR_FIXCE_MASK (0x10000000U)
16149#define MCM_ISCR_FIXCE_SHIFT (28U)
16150/*! FIXCE - FPU inexact interrupt enable
16151 * 0b0..Disable interrupt
16152 * 0b1..Enable interrupt
16153 */
16154#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
16155#define MCM_ISCR_FIDCE_MASK (0x80000000U)
16156#define MCM_ISCR_FIDCE_SHIFT (31U)
16157/*! FIDCE - FPU input denormal interrupt enable
16158 * 0b0..Disable interrupt
16159 * 0b1..Enable interrupt
16160 */
16161#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
16162/*! @} */
16163
16164/*! @name ETBCC - ETB Counter Control register */
16165/*! @{ */
16166#define MCM_ETBCC_CNTEN_MASK (0x1U)
16167#define MCM_ETBCC_CNTEN_SHIFT (0U)
16168/*! CNTEN - Counter Enable
16169 * 0b0..ETB counter disabled
16170 * 0b1..ETB counter enabled
16171 */
16172#define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
16173#define MCM_ETBCC_RSPT_MASK (0x6U)
16174#define MCM_ETBCC_RSPT_SHIFT (1U)
16175/*! RSPT - Response Type
16176 * 0b00..No response when the ETB count expires
16177 * 0b01..Generate a normal interrupt when the ETB count expires
16178 * 0b10..Generate an NMI when the ETB count expires
16179 * 0b11..Generate a debug halt when the ETB count expires
16180 */
16181#define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
16182#define MCM_ETBCC_RLRQ_MASK (0x8U)
16183#define MCM_ETBCC_RLRQ_SHIFT (3U)
16184/*! RLRQ - Reload Request
16185 * 0b0..No effect
16186 * 0b1..Clears pending debug halt, NMI, or IRQ interrupt requests
16187 */
16188#define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
16189#define MCM_ETBCC_ETDIS_MASK (0x10U)
16190#define MCM_ETBCC_ETDIS_SHIFT (4U)
16191/*! ETDIS - ETM-To-TPIU Disable
16192 * 0b0..ETM-to-TPIU trace path enabled
16193 * 0b1..ETM-to-TPIU trace path disabled
16194 */
16195#define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
16196#define MCM_ETBCC_ITDIS_MASK (0x20U)
16197#define MCM_ETBCC_ITDIS_SHIFT (5U)
16198/*! ITDIS - ITM-To-TPIU Disable
16199 * 0b0..ITM-to-TPIU trace path enabled
16200 * 0b1..ITM-to-TPIU trace path disabled
16201 */
16202#define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
16203/*! @} */
16204
16205/*! @name ETBRL - ETB Reload register */
16206/*! @{ */
16207#define MCM_ETBRL_RELOAD_MASK (0x7FFU)
16208#define MCM_ETBRL_RELOAD_SHIFT (0U)
16209#define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
16210/*! @} */
16211
16212/*! @name ETBCNT - ETB Counter Value register */
16213/*! @{ */
16214#define MCM_ETBCNT_COUNTER_MASK (0x7FFU)
16215#define MCM_ETBCNT_COUNTER_SHIFT (0U)
16216#define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
16217/*! @} */
16218
16219/*! @name FADR - Fault address register */
16220/*! @{ */
16221#define MCM_FADR_ADDRESS_MASK (0xFFFFFFFFU)
16222#define MCM_FADR_ADDRESS_SHIFT (0U)
16223#define MCM_FADR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
16224/*! @} */
16225
16226/*! @name FATR - Fault attributes register */
16227/*! @{ */
16228#define MCM_FATR_BEDA_MASK (0x1U)
16229#define MCM_FATR_BEDA_SHIFT (0U)
16230/*! BEDA - Bus error access type
16231 * 0b0..Instruction
16232 * 0b1..Data
16233 */
16234#define MCM_FATR_BEDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
16235#define MCM_FATR_BEMD_MASK (0x2U)
16236#define MCM_FATR_BEMD_SHIFT (1U)
16237/*! BEMD - Bus error privilege level
16238 * 0b0..User mode
16239 * 0b1..Supervisor/privileged mode
16240 */
16241#define MCM_FATR_BEMD(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
16242#define MCM_FATR_BESZ_MASK (0x30U)
16243#define MCM_FATR_BESZ_SHIFT (4U)
16244/*! BESZ - Bus error size
16245 * 0b00..8-bit access
16246 * 0b01..16-bit access
16247 * 0b10..32-bit access
16248 * 0b11..Reserved
16249 */
16250#define MCM_FATR_BESZ(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
16251#define MCM_FATR_BEWT_MASK (0x80U)
16252#define MCM_FATR_BEWT_SHIFT (7U)
16253/*! BEWT - Bus error write
16254 * 0b0..Read access
16255 * 0b1..Write access
16256 */
16257#define MCM_FATR_BEWT(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
16258#define MCM_FATR_BEMN_MASK (0xF00U)
16259#define MCM_FATR_BEMN_SHIFT (8U)
16260#define MCM_FATR_BEMN(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
16261#define MCM_FATR_BEOVR_MASK (0x80000000U)
16262#define MCM_FATR_BEOVR_SHIFT (31U)
16263/*! BEOVR - Bus error overrun
16264 * 0b0..No bus error overrun
16265 * 0b1..Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error.
16266 */
16267#define MCM_FATR_BEOVR(x) (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
16268/*! @} */
16269
16270/*! @name FDR - Fault data register */
16271/*! @{ */
16272#define MCM_FDR_DATA_MASK (0xFFFFFFFFU)
16273#define MCM_FDR_DATA_SHIFT (0U)
16274#define MCM_FDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
16275/*! @} */
16276
16277/*! @name PID - Process ID register */
16278/*! @{ */
16279#define MCM_PID_PID_MASK (0xFFU)
16280#define MCM_PID_PID_SHIFT (0U)
16281#define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
16282/*! @} */
16283
16284/*! @name CPO - Compute Operation Control Register */
16285/*! @{ */
16286#define MCM_CPO_CPOREQ_MASK (0x1U)
16287#define MCM_CPO_CPOREQ_SHIFT (0U)
16288/*! CPOREQ - Compute Operation request
16289 * 0b0..Request is cleared.
16290 * 0b1..Request Compute Operation.
16291 */
16292#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
16293#define MCM_CPO_CPOACK_MASK (0x2U)
16294#define MCM_CPO_CPOACK_SHIFT (1U)
16295/*! CPOACK - Compute Operation acknowledge
16296 * 0b0..Compute operation entry has not completed or compute operation exit has completed.
16297 * 0b1..Compute operation entry has completed or compute operation exit has not completed.
16298 */
16299#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
16300#define MCM_CPO_CPOWOI_MASK (0x4U)
16301#define MCM_CPO_CPOWOI_SHIFT (2U)
16302/*! CPOWOI - Compute Operation wakeup on interrupt
16303 * 0b0..No effect.
16304 * 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
16305 */
16306#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
16307/*! @} */
16308
16309
16310/*!
16311 * @}
16312 */ /* end of group MCM_Register_Masks */
16313
16314
16315/* MCM - Peripheral instance base addresses */
16316/** Peripheral MCM base address */
16317#define MCM_BASE (0xE0080000u)
16318/** Peripheral MCM base pointer */
16319#define MCM ((MCM_Type *)MCM_BASE)
16320/** Array initializer of MCM peripheral base addresses */
16321#define MCM_BASE_ADDRS { MCM_BASE }
16322/** Array initializer of MCM peripheral base pointers */
16323#define MCM_BASE_PTRS { MCM }
16324/** Interrupt vectors for the MCM peripheral type */
16325#define MCM_IRQS { MCM_IRQn }
16326
16327/*!
16328 * @}
16329 */ /* end of group MCM_Peripheral_Access_Layer */
16330
16331
16332/* ----------------------------------------------------------------------------
16333 -- NV Peripheral Access Layer
16334 ---------------------------------------------------------------------------- */
16335
16336/*!
16337 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
16338 * @{
16339 */
16340
16341/** NV - Register Layout Typedef */
16342typedef struct {
16343 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
16344 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
16345 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
16346 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
16347 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
16348 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
16349 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
16350 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
16351 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
16352 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
16353 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
16354 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
16355 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
16356 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
16357 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
16358 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
16359} NV_Type;
16360
16361/* ----------------------------------------------------------------------------
16362 -- NV Register Masks
16363 ---------------------------------------------------------------------------- */
16364
16365/*!
16366 * @addtogroup NV_Register_Masks NV Register Masks
16367 * @{
16368 */
16369
16370/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
16371/*! @{ */
16372#define NV_BACKKEY3_KEY_MASK (0xFFU)
16373#define NV_BACKKEY3_KEY_SHIFT (0U)
16374#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
16375/*! @} */
16376
16377/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
16378/*! @{ */
16379#define NV_BACKKEY2_KEY_MASK (0xFFU)
16380#define NV_BACKKEY2_KEY_SHIFT (0U)
16381#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
16382/*! @} */
16383
16384/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
16385/*! @{ */
16386#define NV_BACKKEY1_KEY_MASK (0xFFU)
16387#define NV_BACKKEY1_KEY_SHIFT (0U)
16388#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
16389/*! @} */
16390
16391/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
16392/*! @{ */
16393#define NV_BACKKEY0_KEY_MASK (0xFFU)
16394#define NV_BACKKEY0_KEY_SHIFT (0U)
16395#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
16396/*! @} */
16397
16398/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
16399/*! @{ */
16400#define NV_BACKKEY7_KEY_MASK (0xFFU)
16401#define NV_BACKKEY7_KEY_SHIFT (0U)
16402#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
16403/*! @} */
16404
16405/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
16406/*! @{ */
16407#define NV_BACKKEY6_KEY_MASK (0xFFU)
16408#define NV_BACKKEY6_KEY_SHIFT (0U)
16409#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
16410/*! @} */
16411
16412/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
16413/*! @{ */
16414#define NV_BACKKEY5_KEY_MASK (0xFFU)
16415#define NV_BACKKEY5_KEY_SHIFT (0U)
16416#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
16417/*! @} */
16418
16419/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
16420/*! @{ */
16421#define NV_BACKKEY4_KEY_MASK (0xFFU)
16422#define NV_BACKKEY4_KEY_SHIFT (0U)
16423#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
16424/*! @} */
16425
16426/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
16427/*! @{ */
16428#define NV_FPROT3_PROT_MASK (0xFFU)
16429#define NV_FPROT3_PROT_SHIFT (0U)
16430#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
16431/*! @} */
16432
16433/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
16434/*! @{ */
16435#define NV_FPROT2_PROT_MASK (0xFFU)
16436#define NV_FPROT2_PROT_SHIFT (0U)
16437#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
16438/*! @} */
16439
16440/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
16441/*! @{ */
16442#define NV_FPROT1_PROT_MASK (0xFFU)
16443#define NV_FPROT1_PROT_SHIFT (0U)
16444#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
16445/*! @} */
16446
16447/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
16448/*! @{ */
16449#define NV_FPROT0_PROT_MASK (0xFFU)
16450#define NV_FPROT0_PROT_SHIFT (0U)
16451#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
16452/*! @} */
16453
16454/*! @name FSEC - Non-volatile Flash Security Register */
16455/*! @{ */
16456#define NV_FSEC_SEC_MASK (0x3U)
16457#define NV_FSEC_SEC_SHIFT (0U)
16458/*! SEC - Flash Security
16459 * 0b10..MCU security status is unsecure
16460 * 0b11..MCU security status is secure
16461 */
16462#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
16463#define NV_FSEC_FSLACC_MASK (0xCU)
16464#define NV_FSEC_FSLACC_SHIFT (2U)
16465/*! FSLACC - Freescale Failure Analysis Access Code
16466 * 0b10..Freescale factory access denied
16467 * 0b11..Freescale factory access granted
16468 */
16469#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
16470#define NV_FSEC_MEEN_MASK (0x30U)
16471#define NV_FSEC_MEEN_SHIFT (4U)
16472/*! MEEN
16473 * 0b10..Mass erase is disabled
16474 * 0b11..Mass erase is enabled
16475 */
16476#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
16477#define NV_FSEC_KEYEN_MASK (0xC0U)
16478#define NV_FSEC_KEYEN_SHIFT (6U)
16479/*! KEYEN - Backdoor Key Security Enable
16480 * 0b10..Backdoor key access enabled
16481 * 0b11..Backdoor key access disabled
16482 */
16483#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
16484/*! @} */
16485
16486/*! @name FOPT - Non-volatile Flash Option Register */
16487/*! @{ */
16488#define NV_FOPT_LPBOOT_MASK (0x1U)
16489#define NV_FOPT_LPBOOT_SHIFT (0U)
16490/*! LPBOOT
16491 * 0b0..Low-power boot
16492 * 0b1..Normal boot
16493 */
16494#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
16495#define NV_FOPT_EZPORT_DIS_MASK (0x2U)
16496#define NV_FOPT_EZPORT_DIS_SHIFT (1U)
16497/*! EZPORT_DIS
16498 * 0b0..EzPort operation is disabled
16499 * 0b1..EzPort operation is enabled
16500 */
16501#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
16502#define NV_FOPT_NMI_DIS_MASK (0x4U)
16503#define NV_FOPT_NMI_DIS_SHIFT (2U)
16504/*! NMI_DIS
16505 * 0b0..NMI interrupts are always blocked
16506 * 0b1..NMI_b pin/interrupts reset default to enabled
16507 */
16508#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
16509/*! @} */
16510
16511/*! @name FEPROT - Non-volatile EERAM Protection Register */
16512/*! @{ */
16513#define NV_FEPROT_EPROT_MASK (0xFFU)
16514#define NV_FEPROT_EPROT_SHIFT (0U)
16515#define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
16516/*! @} */
16517
16518/*! @name FDPROT - Non-volatile D-Flash Protection Register */
16519/*! @{ */
16520#define NV_FDPROT_DPROT_MASK (0xFFU)
16521#define NV_FDPROT_DPROT_SHIFT (0U)
16522#define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
16523/*! @} */
16524
16525
16526/*!
16527 * @}
16528 */ /* end of group NV_Register_Masks */
16529
16530
16531/* NV - Peripheral instance base addresses */
16532/** Peripheral FTFE_FlashConfig base address */
16533#define FTFE_FlashConfig_BASE (0x400u)
16534/** Peripheral FTFE_FlashConfig base pointer */
16535#define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
16536/** Array initializer of NV peripheral base addresses */
16537#define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
16538/** Array initializer of NV peripheral base pointers */
16539#define NV_BASE_PTRS { FTFE_FlashConfig }
16540
16541/*!
16542 * @}
16543 */ /* end of group NV_Peripheral_Access_Layer */
16544
16545
16546/* ----------------------------------------------------------------------------
16547 -- OSC Peripheral Access Layer
16548 ---------------------------------------------------------------------------- */
16549
16550/*!
16551 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
16552 * @{
16553 */
16554
16555/** OSC - Register Layout Typedef */
16556typedef struct {
16557 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
16558 uint8_t RESERVED_0[1];
16559 __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
16560} OSC_Type;
16561
16562/* ----------------------------------------------------------------------------
16563 -- OSC Register Masks
16564 ---------------------------------------------------------------------------- */
16565
16566/*!
16567 * @addtogroup OSC_Register_Masks OSC Register Masks
16568 * @{
16569 */
16570
16571/*! @name CR - OSC Control Register */
16572/*! @{ */
16573#define OSC_CR_SC16P_MASK (0x1U)
16574#define OSC_CR_SC16P_SHIFT (0U)
16575/*! SC16P - Oscillator 16 pF Capacitor Load Configure
16576 * 0b0..Disable the selection.
16577 * 0b1..Add 16 pF capacitor to the oscillator load.
16578 */
16579#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
16580#define OSC_CR_SC8P_MASK (0x2U)
16581#define OSC_CR_SC8P_SHIFT (1U)
16582/*! SC8P - Oscillator 8 pF Capacitor Load Configure
16583 * 0b0..Disable the selection.
16584 * 0b1..Add 8 pF capacitor to the oscillator load.
16585 */
16586#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
16587#define OSC_CR_SC4P_MASK (0x4U)
16588#define OSC_CR_SC4P_SHIFT (2U)
16589/*! SC4P - Oscillator 4 pF Capacitor Load Configure
16590 * 0b0..Disable the selection.
16591 * 0b1..Add 4 pF capacitor to the oscillator load.
16592 */
16593#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
16594#define OSC_CR_SC2P_MASK (0x8U)
16595#define OSC_CR_SC2P_SHIFT (3U)
16596/*! SC2P - Oscillator 2 pF Capacitor Load Configure
16597 * 0b0..Disable the selection.
16598 * 0b1..Add 2 pF capacitor to the oscillator load.
16599 */
16600#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
16601#define OSC_CR_EREFSTEN_MASK (0x20U)
16602#define OSC_CR_EREFSTEN_SHIFT (5U)
16603/*! EREFSTEN - External Reference Stop Enable
16604 * 0b0..External reference clock is disabled in Stop mode.
16605 * 0b1..External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
16606 */
16607#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
16608#define OSC_CR_ERCLKEN_MASK (0x80U)
16609#define OSC_CR_ERCLKEN_SHIFT (7U)
16610/*! ERCLKEN - External Reference Enable
16611 * 0b0..External reference clock is inactive.
16612 * 0b1..External reference clock is enabled.
16613 */
16614#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
16615/*! @} */
16616
16617/*! @name DIV - OSC_DIV */
16618/*! @{ */
16619#define OSC_DIV_ERPS_MASK (0xC0U)
16620#define OSC_DIV_ERPS_SHIFT (6U)
16621/*! ERPS
16622 * 0b00..The divisor ratio is 1.
16623 * 0b01..The divisor ratio is 2.
16624 * 0b10..The divisor ratio is 4.
16625 * 0b11..The divisor ratio is 8.
16626 */
16627#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
16628/*! @} */
16629
16630
16631/*!
16632 * @}
16633 */ /* end of group OSC_Register_Masks */
16634
16635
16636/* OSC - Peripheral instance base addresses */
16637/** Peripheral OSC base address */
16638#define OSC_BASE (0x40065000u)
16639/** Peripheral OSC base pointer */
16640#define OSC ((OSC_Type *)OSC_BASE)
16641/** Array initializer of OSC peripheral base addresses */
16642#define OSC_BASE_ADDRS { OSC_BASE }
16643/** Array initializer of OSC peripheral base pointers */
16644#define OSC_BASE_PTRS { OSC }
16645
16646/*!
16647 * @}
16648 */ /* end of group OSC_Peripheral_Access_Layer */
16649
16650
16651/* ----------------------------------------------------------------------------
16652 -- PDB Peripheral Access Layer
16653 ---------------------------------------------------------------------------- */
16654
16655/*!
16656 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
16657 * @{
16658 */
16659
16660/** PDB - Register Layout Typedef */
16661typedef struct {
16662 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
16663 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
16664 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
16665 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
16666 struct { /* offset: 0x10, array step: 0x28 */
16667 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
16668 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
16669 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
16670 uint8_t RESERVED_0[24];
16671 } CH[2];
16672 uint8_t RESERVED_0[240];
16673 struct { /* offset: 0x150, array step: 0x8 */
16674 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
16675 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
16676 } DAC[2];
16677 uint8_t RESERVED_1[48];
16678 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
16679 __IO uint32_t PODLY[4]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
16680} PDB_Type;
16681
16682/* ----------------------------------------------------------------------------
16683 -- PDB Register Masks
16684 ---------------------------------------------------------------------------- */
16685
16686/*!
16687 * @addtogroup PDB_Register_Masks PDB Register Masks
16688 * @{
16689 */
16690
16691/*! @name SC - Status and Control register */
16692/*! @{ */
16693#define PDB_SC_LDOK_MASK (0x1U)
16694#define PDB_SC_LDOK_SHIFT (0U)
16695#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
16696#define PDB_SC_CONT_MASK (0x2U)
16697#define PDB_SC_CONT_SHIFT (1U)
16698/*! CONT - Continuous Mode Enable
16699 * 0b0..PDB operation in One-Shot mode
16700 * 0b1..PDB operation in Continuous mode
16701 */
16702#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
16703#define PDB_SC_MULT_MASK (0xCU)
16704#define PDB_SC_MULT_SHIFT (2U)
16705/*! MULT - Multiplication Factor Select for Prescaler
16706 * 0b00..Multiplication factor is 1.
16707 * 0b01..Multiplication factor is 10.
16708 * 0b10..Multiplication factor is 20.
16709 * 0b11..Multiplication factor is 40.
16710 */
16711#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
16712#define PDB_SC_PDBIE_MASK (0x20U)
16713#define PDB_SC_PDBIE_SHIFT (5U)
16714/*! PDBIE - PDB Interrupt Enable
16715 * 0b0..PDB interrupt disabled.
16716 * 0b1..PDB interrupt enabled.
16717 */
16718#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
16719#define PDB_SC_PDBIF_MASK (0x40U)
16720#define PDB_SC_PDBIF_SHIFT (6U)
16721#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
16722#define PDB_SC_PDBEN_MASK (0x80U)
16723#define PDB_SC_PDBEN_SHIFT (7U)
16724/*! PDBEN - PDB Enable
16725 * 0b0..PDB disabled. Counter is off.
16726 * 0b1..PDB enabled.
16727 */
16728#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
16729#define PDB_SC_TRGSEL_MASK (0xF00U)
16730#define PDB_SC_TRGSEL_SHIFT (8U)
16731/*! TRGSEL - Trigger Input Source Select
16732 * 0b0000..Trigger-In 0 is selected.
16733 * 0b0001..Trigger-In 1 is selected.
16734 * 0b0010..Trigger-In 2 is selected.
16735 * 0b0011..Trigger-In 3 is selected.
16736 * 0b0100..Trigger-In 4 is selected.
16737 * 0b0101..Trigger-In 5 is selected.
16738 * 0b0110..Trigger-In 6 is selected.
16739 * 0b0111..Trigger-In 7 is selected.
16740 * 0b1000..Trigger-In 8 is selected.
16741 * 0b1001..Trigger-In 9 is selected.
16742 * 0b1010..Trigger-In 10 is selected.
16743 * 0b1011..Trigger-In 11 is selected.
16744 * 0b1100..Trigger-In 12 is selected.
16745 * 0b1101..Trigger-In 13 is selected.
16746 * 0b1110..Trigger-In 14 is selected.
16747 * 0b1111..Software trigger is selected.
16748 */
16749#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
16750#define PDB_SC_PRESCALER_MASK (0x7000U)
16751#define PDB_SC_PRESCALER_SHIFT (12U)
16752/*! PRESCALER - Prescaler Divider Select
16753 * 0b000..Counting uses the peripheral clock divided by multiplication factor selected by MULT.
16754 * 0b001..Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.
16755 * 0b010..Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT.
16756 * 0b011..Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT.
16757 * 0b100..Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT.
16758 * 0b101..Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT.
16759 * 0b110..Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT.
16760 * 0b111..Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT.
16761 */
16762#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
16763#define PDB_SC_DMAEN_MASK (0x8000U)
16764#define PDB_SC_DMAEN_SHIFT (15U)
16765/*! DMAEN - DMA Enable
16766 * 0b0..DMA disabled.
16767 * 0b1..DMA enabled.
16768 */
16769#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
16770#define PDB_SC_SWTRIG_MASK (0x10000U)
16771#define PDB_SC_SWTRIG_SHIFT (16U)
16772#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
16773#define PDB_SC_PDBEIE_MASK (0x20000U)
16774#define PDB_SC_PDBEIE_SHIFT (17U)
16775/*! PDBEIE - PDB Sequence Error Interrupt Enable
16776 * 0b0..PDB sequence error interrupt disabled.
16777 * 0b1..PDB sequence error interrupt enabled.
16778 */
16779#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
16780#define PDB_SC_LDMOD_MASK (0xC0000U)
16781#define PDB_SC_LDMOD_SHIFT (18U)
16782/*! LDMOD - Load Mode Select
16783 * 0b00..The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.
16784 * 0b01..The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK.
16785 * 0b10..The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK.
16786 * 0b11..The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.
16787 */
16788#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
16789/*! @} */
16790
16791/*! @name MOD - Modulus register */
16792/*! @{ */
16793#define PDB_MOD_MOD_MASK (0xFFFFU)
16794#define PDB_MOD_MOD_SHIFT (0U)
16795#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
16796/*! @} */
16797
16798/*! @name CNT - Counter register */
16799/*! @{ */
16800#define PDB_CNT_CNT_MASK (0xFFFFU)
16801#define PDB_CNT_CNT_SHIFT (0U)
16802#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
16803/*! @} */
16804
16805/*! @name IDLY - Interrupt Delay register */
16806/*! @{ */
16807#define PDB_IDLY_IDLY_MASK (0xFFFFU)
16808#define PDB_IDLY_IDLY_SHIFT (0U)
16809#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
16810/*! @} */
16811
16812/*! @name C1 - Channel n Control register 1 */
16813/*! @{ */
16814#define PDB_C1_EN_MASK (0xFFU)
16815#define PDB_C1_EN_SHIFT (0U)
16816/*! EN - PDB Channel Pre-Trigger Enable
16817 * 0b00000000..PDB channel's corresponding pre-trigger disabled.
16818 * 0b00000001..PDB channel's corresponding pre-trigger enabled.
16819 */
16820#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
16821#define PDB_C1_TOS_MASK (0xFF00U)
16822#define PDB_C1_TOS_SHIFT (8U)
16823/*! TOS - PDB Channel Pre-Trigger Output Select
16824 * 0b00000000..PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
16825 * 0b00000001..PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
16826 */
16827#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
16828#define PDB_C1_BB_MASK (0xFF0000U)
16829#define PDB_C1_BB_SHIFT (16U)
16830/*! BB - PDB Channel Pre-Trigger Back-to-Back Operation Enable
16831 * 0b00000000..PDB channel's corresponding pre-trigger back-to-back operation disabled.
16832 * 0b00000001..PDB channel's corresponding pre-trigger back-to-back operation enabled.
16833 */
16834#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
16835/*! @} */
16836
16837/* The count of PDB_C1 */
16838#define PDB_C1_COUNT (2U)
16839
16840/*! @name S - Channel n Status register */
16841/*! @{ */
16842#define PDB_S_ERR_MASK (0xFFU)
16843#define PDB_S_ERR_SHIFT (0U)
16844/*! ERR - PDB Channel Sequence Error Flags
16845 * 0b00000000..Sequence error not detected on PDB channel's corresponding pre-trigger.
16846 * 0b00000001..Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
16847 */
16848#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
16849#define PDB_S_CF_MASK (0xFF0000U)
16850#define PDB_S_CF_SHIFT (16U)
16851#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
16852/*! @} */
16853
16854/* The count of PDB_S */
16855#define PDB_S_COUNT (2U)
16856
16857/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
16858/*! @{ */
16859#define PDB_DLY_DLY_MASK (0xFFFFU)
16860#define PDB_DLY_DLY_SHIFT (0U)
16861#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
16862/*! @} */
16863
16864/* The count of PDB_DLY */
16865#define PDB_DLY_COUNT (2U)
16866
16867/* The count of PDB_DLY */
16868#define PDB_DLY_COUNT2 (2U)
16869
16870/*! @name INTC - DAC Interval Trigger n Control register */
16871/*! @{ */
16872#define PDB_INTC_TOE_MASK (0x1U)
16873#define PDB_INTC_TOE_SHIFT (0U)
16874/*! TOE - DAC Interval Trigger Enable
16875 * 0b0..DAC interval trigger disabled.
16876 * 0b1..DAC interval trigger enabled.
16877 */
16878#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
16879#define PDB_INTC_EXT_MASK (0x2U)
16880#define PDB_INTC_EXT_SHIFT (1U)
16881/*! EXT - DAC External Trigger Input Enable
16882 * 0b0..DAC external trigger input disabled. DAC interval counter is reset and counting starts when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
16883 * 0b1..DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger.
16884 */
16885#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
16886/*! @} */
16887
16888/* The count of PDB_INTC */
16889#define PDB_INTC_COUNT (2U)
16890
16891/*! @name INT - DAC Interval n register */
16892/*! @{ */
16893#define PDB_INT_INT_MASK (0xFFFFU)
16894#define PDB_INT_INT_SHIFT (0U)
16895#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
16896/*! @} */
16897
16898/* The count of PDB_INT */
16899#define PDB_INT_COUNT (2U)
16900
16901/*! @name POEN - Pulse-Out n Enable register */
16902/*! @{ */
16903#define PDB_POEN_POEN_MASK (0xFFU)
16904#define PDB_POEN_POEN_SHIFT (0U)
16905/*! POEN - PDB Pulse-Out Enable
16906 * 0b00000000..PDB Pulse-Out disabled
16907 * 0b00000001..PDB Pulse-Out enabled
16908 */
16909#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
16910/*! @} */
16911
16912/*! @name PODLY - Pulse-Out n Delay register */
16913/*! @{ */
16914#define PDB_PODLY_DLY2_MASK (0xFFFFU)
16915#define PDB_PODLY_DLY2_SHIFT (0U)
16916#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
16917#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
16918#define PDB_PODLY_DLY1_SHIFT (16U)
16919#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
16920/*! @} */
16921
16922/* The count of PDB_PODLY */
16923#define PDB_PODLY_COUNT (4U)
16924
16925
16926/*!
16927 * @}
16928 */ /* end of group PDB_Register_Masks */
16929
16930
16931/* PDB - Peripheral instance base addresses */
16932/** Peripheral PDB0 base address */
16933#define PDB0_BASE (0x40036000u)
16934/** Peripheral PDB0 base pointer */
16935#define PDB0 ((PDB_Type *)PDB0_BASE)
16936/** Array initializer of PDB peripheral base addresses */
16937#define PDB_BASE_ADDRS { PDB0_BASE }
16938/** Array initializer of PDB peripheral base pointers */
16939#define PDB_BASE_PTRS { PDB0 }
16940/** Interrupt vectors for the PDB peripheral type */
16941#define PDB_IRQS { PDB0_IRQn }
16942
16943/*!
16944 * @}
16945 */ /* end of group PDB_Peripheral_Access_Layer */
16946
16947
16948/* ----------------------------------------------------------------------------
16949 -- PIT Peripheral Access Layer
16950 ---------------------------------------------------------------------------- */
16951
16952/*!
16953 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
16954 * @{
16955 */
16956
16957/** PIT - Register Layout Typedef */
16958typedef struct {
16959 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
16960 uint8_t RESERVED_0[220];
16961 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
16962 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
16963 uint8_t RESERVED_1[24];
16964 struct { /* offset: 0x100, array step: 0x10 */
16965 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
16966 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
16967 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
16968 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
16969 } CHANNEL[4];
16970} PIT_Type;
16971
16972/* ----------------------------------------------------------------------------
16973 -- PIT Register Masks
16974 ---------------------------------------------------------------------------- */
16975
16976/*!
16977 * @addtogroup PIT_Register_Masks PIT Register Masks
16978 * @{
16979 */
16980
16981/*! @name MCR - PIT Module Control Register */
16982/*! @{ */
16983#define PIT_MCR_FRZ_MASK (0x1U)
16984#define PIT_MCR_FRZ_SHIFT (0U)
16985/*! FRZ - Freeze
16986 * 0b0..Timers continue to run in Debug mode.
16987 * 0b1..Timers are stopped in Debug mode.
16988 */
16989#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
16990#define PIT_MCR_MDIS_MASK (0x2U)
16991#define PIT_MCR_MDIS_SHIFT (1U)
16992/*! MDIS - Module Disable - (PIT section)
16993 * 0b0..Clock for standard PIT timers is enabled.
16994 * 0b1..Clock for standard PIT timers is disabled.
16995 */
16996#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
16997/*! @} */
16998
16999/*! @name LTMR64H - PIT Upper Lifetime Timer Register */
17000/*! @{ */
17001#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
17002#define PIT_LTMR64H_LTH_SHIFT (0U)
17003#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
17004/*! @} */
17005
17006/*! @name LTMR64L - PIT Lower Lifetime Timer Register */
17007/*! @{ */
17008#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
17009#define PIT_LTMR64L_LTL_SHIFT (0U)
17010#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
17011/*! @} */
17012
17013/*! @name LDVAL - Timer Load Value Register */
17014/*! @{ */
17015#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
17016#define PIT_LDVAL_TSV_SHIFT (0U)
17017#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
17018/*! @} */
17019
17020/* The count of PIT_LDVAL */
17021#define PIT_LDVAL_COUNT (4U)
17022
17023/*! @name CVAL - Current Timer Value Register */
17024/*! @{ */
17025#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
17026#define PIT_CVAL_TVL_SHIFT (0U)
17027#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
17028/*! @} */
17029
17030/* The count of PIT_CVAL */
17031#define PIT_CVAL_COUNT (4U)
17032
17033/*! @name TCTRL - Timer Control Register */
17034/*! @{ */
17035#define PIT_TCTRL_TEN_MASK (0x1U)
17036#define PIT_TCTRL_TEN_SHIFT (0U)
17037/*! TEN - Timer Enable
17038 * 0b0..Timer n is disabled.
17039 * 0b1..Timer n is enabled.
17040 */
17041#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
17042#define PIT_TCTRL_TIE_MASK (0x2U)
17043#define PIT_TCTRL_TIE_SHIFT (1U)
17044/*! TIE - Timer Interrupt Enable
17045 * 0b0..Interrupt requests from Timer n are disabled.
17046 * 0b1..Interrupt will be requested whenever TIF is set.
17047 */
17048#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
17049#define PIT_TCTRL_CHN_MASK (0x4U)
17050#define PIT_TCTRL_CHN_SHIFT (2U)
17051/*! CHN - Chain Mode
17052 * 0b0..Timer is not chained.
17053 * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
17054 */
17055#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
17056/*! @} */
17057
17058/* The count of PIT_TCTRL */
17059#define PIT_TCTRL_COUNT (4U)
17060
17061/*! @name TFLG - Timer Flag Register */
17062/*! @{ */
17063#define PIT_TFLG_TIF_MASK (0x1U)
17064#define PIT_TFLG_TIF_SHIFT (0U)
17065/*! TIF - Timer Interrupt Flag
17066 * 0b0..Timeout has not yet occurred.
17067 * 0b1..Timeout has occurred.
17068 */
17069#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
17070/*! @} */
17071
17072/* The count of PIT_TFLG */
17073#define PIT_TFLG_COUNT (4U)
17074
17075
17076/*!
17077 * @}
17078 */ /* end of group PIT_Register_Masks */
17079
17080
17081/* PIT - Peripheral instance base addresses */
17082/** Peripheral PIT base address */
17083#define PIT_BASE (0x40037000u)
17084/** Peripheral PIT base pointer */
17085#define PIT ((PIT_Type *)PIT_BASE)
17086/** Array initializer of PIT peripheral base addresses */
17087#define PIT_BASE_ADDRS { PIT_BASE }
17088/** Array initializer of PIT peripheral base pointers */
17089#define PIT_BASE_PTRS { PIT }
17090/** Interrupt vectors for the PIT peripheral type */
17091#define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
17092
17093/*!
17094 * @}
17095 */ /* end of group PIT_Peripheral_Access_Layer */
17096
17097
17098/* ----------------------------------------------------------------------------
17099 -- PMC Peripheral Access Layer
17100 ---------------------------------------------------------------------------- */
17101
17102/*!
17103 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
17104 * @{
17105 */
17106
17107/** PMC - Register Layout Typedef */
17108typedef struct {
17109 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
17110 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
17111 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
17112} PMC_Type;
17113
17114/* ----------------------------------------------------------------------------
17115 -- PMC Register Masks
17116 ---------------------------------------------------------------------------- */
17117
17118/*!
17119 * @addtogroup PMC_Register_Masks PMC Register Masks
17120 * @{
17121 */
17122
17123/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
17124/*! @{ */
17125#define PMC_LVDSC1_LVDV_MASK (0x3U)
17126#define PMC_LVDSC1_LVDV_SHIFT (0U)
17127/*! LVDV - Low-Voltage Detect Voltage Select
17128 * 0b00..Low trip point selected (V LVD = V LVDL )
17129 * 0b01..High trip point selected (V LVD = V LVDH )
17130 * 0b10..Reserved
17131 * 0b11..Reserved
17132 */
17133#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
17134#define PMC_LVDSC1_LVDRE_MASK (0x10U)
17135#define PMC_LVDSC1_LVDRE_SHIFT (4U)
17136/*! LVDRE - Low-Voltage Detect Reset Enable
17137 * 0b0..LVDF does not generate hardware resets
17138 * 0b1..Force an MCU reset when LVDF = 1
17139 */
17140#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
17141#define PMC_LVDSC1_LVDIE_MASK (0x20U)
17142#define PMC_LVDSC1_LVDIE_SHIFT (5U)
17143/*! LVDIE - Low-Voltage Detect Interrupt Enable
17144 * 0b0..Hardware interrupt disabled (use polling)
17145 * 0b1..Request a hardware interrupt when LVDF = 1
17146 */
17147#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
17148#define PMC_LVDSC1_LVDACK_MASK (0x40U)
17149#define PMC_LVDSC1_LVDACK_SHIFT (6U)
17150#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
17151#define PMC_LVDSC1_LVDF_MASK (0x80U)
17152#define PMC_LVDSC1_LVDF_SHIFT (7U)
17153/*! LVDF - Low-Voltage Detect Flag
17154 * 0b0..Low-voltage event not detected
17155 * 0b1..Low-voltage event detected
17156 */
17157#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
17158/*! @} */
17159
17160/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
17161/*! @{ */
17162#define PMC_LVDSC2_LVWV_MASK (0x3U)
17163#define PMC_LVDSC2_LVWV_SHIFT (0U)
17164/*! LVWV - Low-Voltage Warning Voltage Select
17165 * 0b00..Low trip point selected (VLVW = VLVW1)
17166 * 0b01..Mid 1 trip point selected (VLVW = VLVW2)
17167 * 0b10..Mid 2 trip point selected (VLVW = VLVW3)
17168 * 0b11..High trip point selected (VLVW = VLVW4)
17169 */
17170#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
17171#define PMC_LVDSC2_LVWIE_MASK (0x20U)
17172#define PMC_LVDSC2_LVWIE_SHIFT (5U)
17173/*! LVWIE - Low-Voltage Warning Interrupt Enable
17174 * 0b0..Hardware interrupt disabled (use polling)
17175 * 0b1..Request a hardware interrupt when LVWF = 1
17176 */
17177#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
17178#define PMC_LVDSC2_LVWACK_MASK (0x40U)
17179#define PMC_LVDSC2_LVWACK_SHIFT (6U)
17180#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
17181#define PMC_LVDSC2_LVWF_MASK (0x80U)
17182#define PMC_LVDSC2_LVWF_SHIFT (7U)
17183/*! LVWF - Low-Voltage Warning Flag
17184 * 0b0..Low-voltage warning event not detected
17185 * 0b1..Low-voltage warning event detected
17186 */
17187#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
17188/*! @} */
17189
17190/*! @name REGSC - Regulator Status And Control register */
17191/*! @{ */
17192#define PMC_REGSC_BGBE_MASK (0x1U)
17193#define PMC_REGSC_BGBE_SHIFT (0U)
17194/*! BGBE - Bandgap Buffer Enable
17195 * 0b0..Bandgap buffer not enabled
17196 * 0b1..Bandgap buffer enabled
17197 */
17198#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
17199#define PMC_REGSC_REGONS_MASK (0x4U)
17200#define PMC_REGSC_REGONS_SHIFT (2U)
17201/*! REGONS - Regulator In Run Regulation Status
17202 * 0b0..Regulator is in stop regulation or in transition to/from it
17203 * 0b1..Regulator is in run regulation
17204 */
17205#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
17206#define PMC_REGSC_ACKISO_MASK (0x8U)
17207#define PMC_REGSC_ACKISO_SHIFT (3U)
17208/*! ACKISO - Acknowledge Isolation
17209 * 0b0..Peripherals and I/O pads are in normal run state.
17210 * 0b1..Certain peripherals and I/O pads are in an isolated and latched state.
17211 */
17212#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
17213#define PMC_REGSC_BGEN_MASK (0x10U)
17214#define PMC_REGSC_BGEN_SHIFT (4U)
17215/*! BGEN - Bandgap Enable In VLPx Operation
17216 * 0b0..Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
17217 * 0b1..Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
17218 */
17219#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
17220/*! @} */
17221
17222
17223/*!
17224 * @}
17225 */ /* end of group PMC_Register_Masks */
17226
17227
17228/* PMC - Peripheral instance base addresses */
17229/** Peripheral PMC base address */
17230#define PMC_BASE (0x4007D000u)
17231/** Peripheral PMC base pointer */
17232#define PMC ((PMC_Type *)PMC_BASE)
17233/** Array initializer of PMC peripheral base addresses */
17234#define PMC_BASE_ADDRS { PMC_BASE }
17235/** Array initializer of PMC peripheral base pointers */
17236#define PMC_BASE_PTRS { PMC }
17237/** Interrupt vectors for the PMC peripheral type */
17238#define PMC_IRQS { LVD_LVW_IRQn }
17239
17240/*!
17241 * @}
17242 */ /* end of group PMC_Peripheral_Access_Layer */
17243
17244
17245/* ----------------------------------------------------------------------------
17246 -- PORT Peripheral Access Layer
17247 ---------------------------------------------------------------------------- */
17248
17249/*!
17250 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
17251 * @{
17252 */
17253
17254/** PORT - Register Layout Typedef */
17255typedef struct {
17256 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
17257 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
17258 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
17259 uint8_t RESERVED_0[24];
17260 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
17261 uint8_t RESERVED_1[28];
17262 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
17263 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
17264 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
17265} PORT_Type;
17266
17267/* ----------------------------------------------------------------------------
17268 -- PORT Register Masks
17269 ---------------------------------------------------------------------------- */
17270
17271/*!
17272 * @addtogroup PORT_Register_Masks PORT Register Masks
17273 * @{
17274 */
17275
17276/*! @name PCR - Pin Control Register n */
17277/*! @{ */
17278#define PORT_PCR_PS_MASK (0x1U)
17279#define PORT_PCR_PS_SHIFT (0U)
17280/*! PS - Pull Select
17281 * 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
17282 * 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
17283 */
17284#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
17285#define PORT_PCR_PE_MASK (0x2U)
17286#define PORT_PCR_PE_SHIFT (1U)
17287/*! PE - Pull Enable
17288 * 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin.
17289 * 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
17290 */
17291#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
17292#define PORT_PCR_SRE_MASK (0x4U)
17293#define PORT_PCR_SRE_SHIFT (2U)
17294/*! SRE - Slew Rate Enable
17295 * 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
17296 * 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
17297 */
17298#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
17299#define PORT_PCR_PFE_MASK (0x10U)
17300#define PORT_PCR_PFE_SHIFT (4U)
17301/*! PFE - Passive Filter Enable
17302 * 0b0..Passive input filter is disabled on the corresponding pin.
17303 * 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
17304 */
17305#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
17306#define PORT_PCR_ODE_MASK (0x20U)
17307#define PORT_PCR_ODE_SHIFT (5U)
17308/*! ODE - Open Drain Enable
17309 * 0b0..Open drain output is disabled on the corresponding pin.
17310 * 0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
17311 */
17312#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
17313#define PORT_PCR_DSE_MASK (0x40U)
17314#define PORT_PCR_DSE_SHIFT (6U)
17315/*! DSE - Drive Strength Enable
17316 * 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
17317 * 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
17318 */
17319#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
17320#define PORT_PCR_MUX_MASK (0x700U)
17321#define PORT_PCR_MUX_SHIFT (8U)
17322/*! MUX - Pin Mux Control
17323 * 0b000..Pin disabled (analog).
17324 * 0b001..Alternative 1 (GPIO).
17325 * 0b010..Alternative 2 (chip-specific).
17326 * 0b011..Alternative 3 (chip-specific).
17327 * 0b100..Alternative 4 (chip-specific).
17328 * 0b101..Alternative 5 (chip-specific).
17329 * 0b110..Alternative 6 (chip-specific).
17330 * 0b111..Alternative 7 (chip-specific).
17331 */
17332#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
17333#define PORT_PCR_LK_MASK (0x8000U)
17334#define PORT_PCR_LK_SHIFT (15U)
17335/*! LK - Lock Register
17336 * 0b0..Pin Control Register fields [15:0] are not locked.
17337 * 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
17338 */
17339#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
17340#define PORT_PCR_IRQC_MASK (0xF0000U)
17341#define PORT_PCR_IRQC_SHIFT (16U)
17342/*! IRQC - Interrupt Configuration
17343 * 0b0000..Interrupt Status Flag (ISF) is disabled.
17344 * 0b0001..ISF flag and DMA request on rising edge.
17345 * 0b0010..ISF flag and DMA request on falling edge.
17346 * 0b0011..ISF flag and DMA request on either edge.
17347 * 0b0100..Reserved.
17348 * 0b0101..Reserved.
17349 * 0b0110..Reserved.
17350 * 0b0111..Reserved.
17351 * 0b1000..ISF flag and Interrupt when logic 0.
17352 * 0b1001..ISF flag and Interrupt on rising-edge.
17353 * 0b1010..ISF flag and Interrupt on falling-edge.
17354 * 0b1011..ISF flag and Interrupt on either edge.
17355 * 0b1100..ISF flag and Interrupt when logic 1.
17356 * 0b1101..Reserved.
17357 * 0b1110..Reserved.
17358 * 0b1111..Reserved.
17359 */
17360#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
17361#define PORT_PCR_ISF_MASK (0x1000000U)
17362#define PORT_PCR_ISF_SHIFT (24U)
17363/*! ISF - Interrupt Status Flag
17364 * 0b0..Configured interrupt is not detected.
17365 * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
17366 */
17367#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
17368/*! @} */
17369
17370/* The count of PORT_PCR */
17371#define PORT_PCR_COUNT (32U)
17372
17373/*! @name GPCLR - Global Pin Control Low Register */
17374/*! @{ */
17375#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
17376#define PORT_GPCLR_GPWD_SHIFT (0U)
17377#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
17378#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
17379#define PORT_GPCLR_GPWE_SHIFT (16U)
17380/*! GPWE - Global Pin Write Enable
17381 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
17382 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
17383 */
17384#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
17385/*! @} */
17386
17387/*! @name GPCHR - Global Pin Control High Register */
17388/*! @{ */
17389#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
17390#define PORT_GPCHR_GPWD_SHIFT (0U)
17391#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
17392#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
17393#define PORT_GPCHR_GPWE_SHIFT (16U)
17394/*! GPWE - Global Pin Write Enable
17395 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
17396 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
17397 */
17398#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
17399/*! @} */
17400
17401/*! @name ISFR - Interrupt Status Flag Register */
17402/*! @{ */
17403#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
17404#define PORT_ISFR_ISF_SHIFT (0U)
17405/*! ISF - Interrupt Status Flag
17406 * 0b00000000000000000000000000000000..Configured interrupt is not detected.
17407 * 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
17408 */
17409#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
17410/*! @} */
17411
17412/*! @name DFER - Digital Filter Enable Register */
17413/*! @{ */
17414#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
17415#define PORT_DFER_DFE_SHIFT (0U)
17416/*! DFE - Digital Filter Enable
17417 * 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
17418 * 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
17419 */
17420#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
17421/*! @} */
17422
17423/*! @name DFCR - Digital Filter Clock Register */
17424/*! @{ */
17425#define PORT_DFCR_CS_MASK (0x1U)
17426#define PORT_DFCR_CS_SHIFT (0U)
17427/*! CS - Clock Source
17428 * 0b0..Digital filters are clocked by the bus clock.
17429 * 0b1..Digital filters are clocked by the LPO clock.
17430 */
17431#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
17432/*! @} */
17433
17434/*! @name DFWR - Digital Filter Width Register */
17435/*! @{ */
17436#define PORT_DFWR_FILT_MASK (0x1FU)
17437#define PORT_DFWR_FILT_SHIFT (0U)
17438#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
17439/*! @} */
17440
17441
17442/*!
17443 * @}
17444 */ /* end of group PORT_Register_Masks */
17445
17446
17447/* PORT - Peripheral instance base addresses */
17448/** Peripheral PORTA base address */
17449#define PORTA_BASE (0x40049000u)
17450/** Peripheral PORTA base pointer */
17451#define PORTA ((PORT_Type *)PORTA_BASE)
17452/** Peripheral PORTB base address */
17453#define PORTB_BASE (0x4004A000u)
17454/** Peripheral PORTB base pointer */
17455#define PORTB ((PORT_Type *)PORTB_BASE)
17456/** Peripheral PORTC base address */
17457#define PORTC_BASE (0x4004B000u)
17458/** Peripheral PORTC base pointer */
17459#define PORTC ((PORT_Type *)PORTC_BASE)
17460/** Peripheral PORTD base address */
17461#define PORTD_BASE (0x4004C000u)
17462/** Peripheral PORTD base pointer */
17463#define PORTD ((PORT_Type *)PORTD_BASE)
17464/** Peripheral PORTE base address */
17465#define PORTE_BASE (0x4004D000u)
17466/** Peripheral PORTE base pointer */
17467#define PORTE ((PORT_Type *)PORTE_BASE)
17468/** Array initializer of PORT peripheral base addresses */
17469#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
17470/** Array initializer of PORT peripheral base pointers */
17471#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
17472/** Interrupt vectors for the PORT peripheral type */
17473#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
17474
17475/*!
17476 * @}
17477 */ /* end of group PORT_Peripheral_Access_Layer */
17478
17479
17480/* ----------------------------------------------------------------------------
17481 -- RCM Peripheral Access Layer
17482 ---------------------------------------------------------------------------- */
17483
17484/*!
17485 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
17486 * @{
17487 */
17488
17489/** RCM - Register Layout Typedef */
17490typedef struct {
17491 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
17492 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
17493 uint8_t RESERVED_0[2];
17494 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
17495 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
17496 uint8_t RESERVED_1[1];
17497 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
17498 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
17499 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
17500} RCM_Type;
17501
17502/* ----------------------------------------------------------------------------
17503 -- RCM Register Masks
17504 ---------------------------------------------------------------------------- */
17505
17506/*!
17507 * @addtogroup RCM_Register_Masks RCM Register Masks
17508 * @{
17509 */
17510
17511/*! @name SRS0 - System Reset Status Register 0 */
17512/*! @{ */
17513#define RCM_SRS0_WAKEUP_MASK (0x1U)
17514#define RCM_SRS0_WAKEUP_SHIFT (0U)
17515/*! WAKEUP - Low Leakage Wakeup Reset
17516 * 0b0..Reset not caused by LLWU module wakeup source
17517 * 0b1..Reset caused by LLWU module wakeup source
17518 */
17519#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
17520#define RCM_SRS0_LVD_MASK (0x2U)
17521#define RCM_SRS0_LVD_SHIFT (1U)
17522/*! LVD - Low-Voltage Detect Reset
17523 * 0b0..Reset not caused by LVD trip or POR
17524 * 0b1..Reset caused by LVD trip or POR
17525 */
17526#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
17527#define RCM_SRS0_LOC_MASK (0x4U)
17528#define RCM_SRS0_LOC_SHIFT (2U)
17529/*! LOC - Loss-of-Clock Reset
17530 * 0b0..Reset not caused by a loss of external clock.
17531 * 0b1..Reset caused by a loss of external clock.
17532 */
17533#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
17534#define RCM_SRS0_LOL_MASK (0x8U)
17535#define RCM_SRS0_LOL_SHIFT (3U)
17536/*! LOL - Loss-of-Lock Reset
17537 * 0b0..Reset not caused by a loss of lock in the PLL
17538 * 0b1..Reset caused by a loss of lock in the PLL
17539 */
17540#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
17541#define RCM_SRS0_WDOG_MASK (0x20U)
17542#define RCM_SRS0_WDOG_SHIFT (5U)
17543/*! WDOG - Watchdog
17544 * 0b0..Reset not caused by watchdog timeout
17545 * 0b1..Reset caused by watchdog timeout
17546 */
17547#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
17548#define RCM_SRS0_PIN_MASK (0x40U)
17549#define RCM_SRS0_PIN_SHIFT (6U)
17550/*! PIN - External Reset Pin
17551 * 0b0..Reset not caused by external reset pin
17552 * 0b1..Reset caused by external reset pin
17553 */
17554#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
17555#define RCM_SRS0_POR_MASK (0x80U)
17556#define RCM_SRS0_POR_SHIFT (7U)
17557/*! POR - Power-On Reset
17558 * 0b0..Reset not caused by POR
17559 * 0b1..Reset caused by POR
17560 */
17561#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
17562/*! @} */
17563
17564/*! @name SRS1 - System Reset Status Register 1 */
17565/*! @{ */
17566#define RCM_SRS1_JTAG_MASK (0x1U)
17567#define RCM_SRS1_JTAG_SHIFT (0U)
17568/*! JTAG - JTAG Generated Reset
17569 * 0b0..Reset not caused by JTAG
17570 * 0b1..Reset caused by JTAG
17571 */
17572#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
17573#define RCM_SRS1_LOCKUP_MASK (0x2U)
17574#define RCM_SRS1_LOCKUP_SHIFT (1U)
17575/*! LOCKUP - Core Lockup
17576 * 0b0..Reset not caused by core LOCKUP event
17577 * 0b1..Reset caused by core LOCKUP event
17578 */
17579#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
17580#define RCM_SRS1_SW_MASK (0x4U)
17581#define RCM_SRS1_SW_SHIFT (2U)
17582/*! SW - Software
17583 * 0b0..Reset not caused by software setting of SYSRESETREQ bit
17584 * 0b1..Reset caused by software setting of SYSRESETREQ bit
17585 */
17586#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
17587#define RCM_SRS1_MDM_AP_MASK (0x8U)
17588#define RCM_SRS1_MDM_AP_SHIFT (3U)
17589/*! MDM_AP - MDM-AP System Reset Request
17590 * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit
17591 * 0b1..Reset caused by host debugger system setting of the System Reset Request bit
17592 */
17593#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
17594#define RCM_SRS1_EZPT_MASK (0x10U)
17595#define RCM_SRS1_EZPT_SHIFT (4U)
17596/*! EZPT - EzPort Reset
17597 * 0b0..Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode
17598 * 0b1..Reset caused by EzPort receiving the RESET command while the device is in EzPort mode
17599 */
17600#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
17601#define RCM_SRS1_SACKERR_MASK (0x20U)
17602#define RCM_SRS1_SACKERR_SHIFT (5U)
17603/*! SACKERR - Stop Mode Acknowledge Error Reset
17604 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
17605 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
17606 */
17607#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
17608/*! @} */
17609
17610/*! @name RPFC - Reset Pin Filter Control register */
17611/*! @{ */
17612#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
17613#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
17614/*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes
17615 * 0b00..All filtering disabled
17616 * 0b01..Bus clock filter enabled for normal operation
17617 * 0b10..LPO clock filter enabled for normal operation
17618 * 0b11..Reserved
17619 */
17620#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
17621#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
17622#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
17623/*! RSTFLTSS - Reset Pin Filter Select in Stop Mode
17624 * 0b0..All filtering disabled
17625 * 0b1..LPO clock filter enabled
17626 */
17627#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
17628/*! @} */
17629
17630/*! @name RPFW - Reset Pin Filter Width register */
17631/*! @{ */
17632#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
17633#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
17634/*! RSTFLTSEL - Reset Pin Filter Bus Clock Select
17635 * 0b00000..Bus clock filter count is 1
17636 * 0b00001..Bus clock filter count is 2
17637 * 0b00010..Bus clock filter count is 3
17638 * 0b00011..Bus clock filter count is 4
17639 * 0b00100..Bus clock filter count is 5
17640 * 0b00101..Bus clock filter count is 6
17641 * 0b00110..Bus clock filter count is 7
17642 * 0b00111..Bus clock filter count is 8
17643 * 0b01000..Bus clock filter count is 9
17644 * 0b01001..Bus clock filter count is 10
17645 * 0b01010..Bus clock filter count is 11
17646 * 0b01011..Bus clock filter count is 12
17647 * 0b01100..Bus clock filter count is 13
17648 * 0b01101..Bus clock filter count is 14
17649 * 0b01110..Bus clock filter count is 15
17650 * 0b01111..Bus clock filter count is 16
17651 * 0b10000..Bus clock filter count is 17
17652 * 0b10001..Bus clock filter count is 18
17653 * 0b10010..Bus clock filter count is 19
17654 * 0b10011..Bus clock filter count is 20
17655 * 0b10100..Bus clock filter count is 21
17656 * 0b10101..Bus clock filter count is 22
17657 * 0b10110..Bus clock filter count is 23
17658 * 0b10111..Bus clock filter count is 24
17659 * 0b11000..Bus clock filter count is 25
17660 * 0b11001..Bus clock filter count is 26
17661 * 0b11010..Bus clock filter count is 27
17662 * 0b11011..Bus clock filter count is 28
17663 * 0b11100..Bus clock filter count is 29
17664 * 0b11101..Bus clock filter count is 30
17665 * 0b11110..Bus clock filter count is 31
17666 * 0b11111..Bus clock filter count is 32
17667 */
17668#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
17669/*! @} */
17670
17671/*! @name MR - Mode Register */
17672/*! @{ */
17673#define RCM_MR_EZP_MS_MASK (0x2U)
17674#define RCM_MR_EZP_MS_SHIFT (1U)
17675/*! EZP_MS - EZP_MS_B pin state
17676 * 0b0..Pin deasserted (logic 1)
17677 * 0b1..Pin asserted (logic 0)
17678 */
17679#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
17680/*! @} */
17681
17682/*! @name SSRS0 - Sticky System Reset Status Register 0 */
17683/*! @{ */
17684#define RCM_SSRS0_SWAKEUP_MASK (0x1U)
17685#define RCM_SSRS0_SWAKEUP_SHIFT (0U)
17686/*! SWAKEUP - Sticky Low Leakage Wakeup Reset
17687 * 0b0..Reset not caused by LLWU module wakeup source
17688 * 0b1..Reset caused by LLWU module wakeup source
17689 */
17690#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
17691#define RCM_SSRS0_SLVD_MASK (0x2U)
17692#define RCM_SSRS0_SLVD_SHIFT (1U)
17693/*! SLVD - Sticky Low-Voltage Detect Reset
17694 * 0b0..Reset not caused by LVD trip or POR
17695 * 0b1..Reset caused by LVD trip or POR
17696 */
17697#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
17698#define RCM_SSRS0_SLOC_MASK (0x4U)
17699#define RCM_SSRS0_SLOC_SHIFT (2U)
17700/*! SLOC - Sticky Loss-of-Clock Reset
17701 * 0b0..Reset not caused by a loss of external clock.
17702 * 0b1..Reset caused by a loss of external clock.
17703 */
17704#define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
17705#define RCM_SSRS0_SLOL_MASK (0x8U)
17706#define RCM_SSRS0_SLOL_SHIFT (3U)
17707/*! SLOL - Sticky Loss-of-Lock Reset
17708 * 0b0..Reset not caused by a loss of lock in the PLL
17709 * 0b1..Reset caused by a loss of lock in the PLL
17710 */
17711#define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
17712#define RCM_SSRS0_SWDOG_MASK (0x20U)
17713#define RCM_SSRS0_SWDOG_SHIFT (5U)
17714/*! SWDOG - Sticky Watchdog
17715 * 0b0..Reset not caused by watchdog timeout
17716 * 0b1..Reset caused by watchdog timeout
17717 */
17718#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
17719#define RCM_SSRS0_SPIN_MASK (0x40U)
17720#define RCM_SSRS0_SPIN_SHIFT (6U)
17721/*! SPIN - Sticky External Reset Pin
17722 * 0b0..Reset not caused by external reset pin
17723 * 0b1..Reset caused by external reset pin
17724 */
17725#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
17726#define RCM_SSRS0_SPOR_MASK (0x80U)
17727#define RCM_SSRS0_SPOR_SHIFT (7U)
17728/*! SPOR - Sticky Power-On Reset
17729 * 0b0..Reset not caused by POR
17730 * 0b1..Reset caused by POR
17731 */
17732#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
17733/*! @} */
17734
17735/*! @name SSRS1 - Sticky System Reset Status Register 1 */
17736/*! @{ */
17737#define RCM_SSRS1_SJTAG_MASK (0x1U)
17738#define RCM_SSRS1_SJTAG_SHIFT (0U)
17739/*! SJTAG - Sticky JTAG Generated Reset
17740 * 0b0..Reset not caused by JTAG
17741 * 0b1..Reset caused by JTAG
17742 */
17743#define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
17744#define RCM_SSRS1_SLOCKUP_MASK (0x2U)
17745#define RCM_SSRS1_SLOCKUP_SHIFT (1U)
17746/*! SLOCKUP - Sticky Core Lockup
17747 * 0b0..Reset not caused by core LOCKUP event
17748 * 0b1..Reset caused by core LOCKUP event
17749 */
17750#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
17751#define RCM_SSRS1_SSW_MASK (0x4U)
17752#define RCM_SSRS1_SSW_SHIFT (2U)
17753/*! SSW - Sticky Software
17754 * 0b0..Reset not caused by software setting of SYSRESETREQ bit
17755 * 0b1..Reset caused by software setting of SYSRESETREQ bit
17756 */
17757#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
17758#define RCM_SSRS1_SMDM_AP_MASK (0x8U)
17759#define RCM_SSRS1_SMDM_AP_SHIFT (3U)
17760/*! SMDM_AP - Sticky MDM-AP System Reset Request
17761 * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit
17762 * 0b1..Reset caused by host debugger system setting of the System Reset Request bit
17763 */
17764#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
17765#define RCM_SSRS1_SEZPT_MASK (0x10U)
17766#define RCM_SSRS1_SEZPT_SHIFT (4U)
17767/*! SEZPT - Sticky EzPort Reset
17768 * 0b0..Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode
17769 * 0b1..Reset caused by EzPort receiving the RESET command while the device is in EzPort mode
17770 */
17771#define RCM_SSRS1_SEZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK)
17772#define RCM_SSRS1_SSACKERR_MASK (0x20U)
17773#define RCM_SSRS1_SSACKERR_SHIFT (5U)
17774/*! SSACKERR - Sticky Stop Mode Acknowledge Error Reset
17775 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
17776 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
17777 */
17778#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
17779/*! @} */
17780
17781
17782/*!
17783 * @}
17784 */ /* end of group RCM_Register_Masks */
17785
17786
17787/* RCM - Peripheral instance base addresses */
17788/** Peripheral RCM base address */
17789#define RCM_BASE (0x4007F000u)
17790/** Peripheral RCM base pointer */
17791#define RCM ((RCM_Type *)RCM_BASE)
17792/** Array initializer of RCM peripheral base addresses */
17793#define RCM_BASE_ADDRS { RCM_BASE }
17794/** Array initializer of RCM peripheral base pointers */
17795#define RCM_BASE_PTRS { RCM }
17796
17797/*!
17798 * @}
17799 */ /* end of group RCM_Peripheral_Access_Layer */
17800
17801
17802/* ----------------------------------------------------------------------------
17803 -- RFSYS Peripheral Access Layer
17804 ---------------------------------------------------------------------------- */
17805
17806/*!
17807 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
17808 * @{
17809 */
17810
17811/** RFSYS - Register Layout Typedef */
17812typedef struct {
17813 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
17814} RFSYS_Type;
17815
17816/* ----------------------------------------------------------------------------
17817 -- RFSYS Register Masks
17818 ---------------------------------------------------------------------------- */
17819
17820/*!
17821 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
17822 * @{
17823 */
17824
17825/*! @name REG - Register file register */
17826/*! @{ */
17827#define RFSYS_REG_LL_MASK (0xFFU)
17828#define RFSYS_REG_LL_SHIFT (0U)
17829#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
17830#define RFSYS_REG_LH_MASK (0xFF00U)
17831#define RFSYS_REG_LH_SHIFT (8U)
17832#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
17833#define RFSYS_REG_HL_MASK (0xFF0000U)
17834#define RFSYS_REG_HL_SHIFT (16U)
17835#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
17836#define RFSYS_REG_HH_MASK (0xFF000000U)
17837#define RFSYS_REG_HH_SHIFT (24U)
17838#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
17839/*! @} */
17840
17841/* The count of RFSYS_REG */
17842#define RFSYS_REG_COUNT (8U)
17843
17844
17845/*!
17846 * @}
17847 */ /* end of group RFSYS_Register_Masks */
17848
17849
17850/* RFSYS - Peripheral instance base addresses */
17851/** Peripheral RFSYS base address */
17852#define RFSYS_BASE (0x40041000u)
17853/** Peripheral RFSYS base pointer */
17854#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
17855/** Array initializer of RFSYS peripheral base addresses */
17856#define RFSYS_BASE_ADDRS { RFSYS_BASE }
17857/** Array initializer of RFSYS peripheral base pointers */
17858#define RFSYS_BASE_PTRS { RFSYS }
17859
17860/*!
17861 * @}
17862 */ /* end of group RFSYS_Peripheral_Access_Layer */
17863
17864
17865/* ----------------------------------------------------------------------------
17866 -- RFVBAT Peripheral Access Layer
17867 ---------------------------------------------------------------------------- */
17868
17869/*!
17870 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
17871 * @{
17872 */
17873
17874/** RFVBAT - Register Layout Typedef */
17875typedef struct {
17876 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
17877} RFVBAT_Type;
17878
17879/* ----------------------------------------------------------------------------
17880 -- RFVBAT Register Masks
17881 ---------------------------------------------------------------------------- */
17882
17883/*!
17884 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
17885 * @{
17886 */
17887
17888/*! @name REG - VBAT register file register */
17889/*! @{ */
17890#define RFVBAT_REG_LL_MASK (0xFFU)
17891#define RFVBAT_REG_LL_SHIFT (0U)
17892#define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
17893#define RFVBAT_REG_LH_MASK (0xFF00U)
17894#define RFVBAT_REG_LH_SHIFT (8U)
17895#define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
17896#define RFVBAT_REG_HL_MASK (0xFF0000U)
17897#define RFVBAT_REG_HL_SHIFT (16U)
17898#define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
17899#define RFVBAT_REG_HH_MASK (0xFF000000U)
17900#define RFVBAT_REG_HH_SHIFT (24U)
17901#define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
17902/*! @} */
17903
17904/* The count of RFVBAT_REG */
17905#define RFVBAT_REG_COUNT (8U)
17906
17907
17908/*!
17909 * @}
17910 */ /* end of group RFVBAT_Register_Masks */
17911
17912
17913/* RFVBAT - Peripheral instance base addresses */
17914/** Peripheral RFVBAT base address */
17915#define RFVBAT_BASE (0x4003E000u)
17916/** Peripheral RFVBAT base pointer */
17917#define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
17918/** Array initializer of RFVBAT peripheral base addresses */
17919#define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
17920/** Array initializer of RFVBAT peripheral base pointers */
17921#define RFVBAT_BASE_PTRS { RFVBAT }
17922
17923/*!
17924 * @}
17925 */ /* end of group RFVBAT_Peripheral_Access_Layer */
17926
17927
17928/* ----------------------------------------------------------------------------
17929 -- RNG Peripheral Access Layer
17930 ---------------------------------------------------------------------------- */
17931
17932/*!
17933 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
17934 * @{
17935 */
17936
17937/** RNG - Register Layout Typedef */
17938typedef struct {
17939 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
17940 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
17941 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
17942 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
17943} RNG_Type;
17944
17945/* ----------------------------------------------------------------------------
17946 -- RNG Register Masks
17947 ---------------------------------------------------------------------------- */
17948
17949/*!
17950 * @addtogroup RNG_Register_Masks RNG Register Masks
17951 * @{
17952 */
17953
17954/*! @name CR - RNGA Control Register */
17955/*! @{ */
17956#define RNG_CR_GO_MASK (0x1U)
17957#define RNG_CR_GO_SHIFT (0U)
17958/*! GO - Go
17959 * 0b0..Disabled
17960 * 0b1..Enabled
17961 */
17962#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
17963#define RNG_CR_HA_MASK (0x2U)
17964#define RNG_CR_HA_SHIFT (1U)
17965/*! HA - High Assurance
17966 * 0b0..Disabled
17967 * 0b1..Enabled
17968 */
17969#define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
17970#define RNG_CR_INTM_MASK (0x4U)
17971#define RNG_CR_INTM_SHIFT (2U)
17972/*! INTM - Interrupt Mask
17973 * 0b0..Not masked
17974 * 0b1..Masked
17975 */
17976#define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
17977#define RNG_CR_CLRI_MASK (0x8U)
17978#define RNG_CR_CLRI_SHIFT (3U)
17979/*! CLRI - Clear Interrupt
17980 * 0b0..Do not clear the interrupt.
17981 * 0b1..Clear the interrupt. When you write 1 to this field, RNGA then resets the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
17982 */
17983#define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
17984#define RNG_CR_SLP_MASK (0x10U)
17985#define RNG_CR_SLP_SHIFT (4U)
17986/*! SLP - Sleep
17987 * 0b0..Normal mode
17988 * 0b1..Sleep (low-power) mode
17989 */
17990#define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
17991/*! @} */
17992
17993/*! @name SR - RNGA Status Register */
17994/*! @{ */
17995#define RNG_SR_SECV_MASK (0x1U)
17996#define RNG_SR_SECV_SHIFT (0U)
17997/*! SECV - Security Violation
17998 * 0b0..No security violation
17999 * 0b1..Security violation
18000 */
18001#define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
18002#define RNG_SR_LRS_MASK (0x2U)
18003#define RNG_SR_LRS_SHIFT (1U)
18004/*! LRS - Last Read Status
18005 * 0b0..No underflow
18006 * 0b1..Underflow
18007 */
18008#define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
18009#define RNG_SR_ORU_MASK (0x4U)
18010#define RNG_SR_ORU_SHIFT (2U)
18011/*! ORU - Output Register Underflow
18012 * 0b0..No underflow
18013 * 0b1..Underflow
18014 */
18015#define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
18016#define RNG_SR_ERRI_MASK (0x8U)
18017#define RNG_SR_ERRI_SHIFT (3U)
18018/*! ERRI - Error Interrupt
18019 * 0b0..No underflow
18020 * 0b1..Underflow
18021 */
18022#define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
18023#define RNG_SR_SLP_MASK (0x10U)
18024#define RNG_SR_SLP_SHIFT (4U)
18025/*! SLP - Sleep
18026 * 0b0..Normal mode
18027 * 0b1..Sleep (low-power) mode
18028 */
18029#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
18030#define RNG_SR_OREG_LVL_MASK (0xFF00U)
18031#define RNG_SR_OREG_LVL_SHIFT (8U)
18032/*! OREG_LVL - Output Register Level
18033 * 0b00000000..No words (empty)
18034 * 0b00000001..One word (valid)
18035 */
18036#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
18037#define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
18038#define RNG_SR_OREG_SIZE_SHIFT (16U)
18039/*! OREG_SIZE - Output Register Size
18040 * 0b00000001..One word (this value is fixed)
18041 */
18042#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
18043/*! @} */
18044
18045/*! @name ER - RNGA Entropy Register */
18046/*! @{ */
18047#define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU)
18048#define RNG_ER_EXT_ENT_SHIFT (0U)
18049#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
18050/*! @} */
18051
18052/*! @name OR - RNGA Output Register */
18053/*! @{ */
18054#define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU)
18055#define RNG_OR_RANDOUT_SHIFT (0U)
18056/*! RANDOUT - Random Output
18057 * 0b00000000000000000000000000000000..Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt request to the interrupt controller).
18058 */
18059#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
18060/*! @} */
18061
18062
18063/*!
18064 * @}
18065 */ /* end of group RNG_Register_Masks */
18066
18067
18068/* RNG - Peripheral instance base addresses */
18069/** Peripheral RNG base address */
18070#define RNG_BASE (0x400A0000u)
18071/** Peripheral RNG base pointer */
18072#define RNG ((RNG_Type *)RNG_BASE)
18073/** Array initializer of RNG peripheral base addresses */
18074#define RNG_BASE_ADDRS { RNG_BASE }
18075/** Array initializer of RNG peripheral base pointers */
18076#define RNG_BASE_PTRS { RNG }
18077/** Interrupt vectors for the RNG peripheral type */
18078#define RNG_IRQS { RNG_IRQn }
18079
18080/*!
18081 * @}
18082 */ /* end of group RNG_Peripheral_Access_Layer */
18083
18084
18085/* ----------------------------------------------------------------------------
18086 -- RTC Peripheral Access Layer
18087 ---------------------------------------------------------------------------- */
18088
18089/*!
18090 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
18091 * @{
18092 */
18093
18094/** RTC - Register Layout Typedef */
18095typedef struct {
18096 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
18097 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
18098 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
18099 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
18100 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
18101 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
18102 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
18103 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
18104 __I uint32_t TTSR; /**< RTC Tamper Time Seconds Register, offset: 0x20 */
18105 __IO uint32_t MER; /**< RTC Monotonic Enable Register, offset: 0x24 */
18106 __IO uint32_t MCLR; /**< RTC Monotonic Counter Low Register, offset: 0x28 */
18107 __IO uint32_t MCHR; /**< RTC Monotonic Counter High Register, offset: 0x2C */
18108 uint8_t RESERVED_0[2000];
18109 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
18110 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
18111} RTC_Type;
18112
18113/* ----------------------------------------------------------------------------
18114 -- RTC Register Masks
18115 ---------------------------------------------------------------------------- */
18116
18117/*!
18118 * @addtogroup RTC_Register_Masks RTC Register Masks
18119 * @{
18120 */
18121
18122/*! @name TSR - RTC Time Seconds Register */
18123/*! @{ */
18124#define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
18125#define RTC_TSR_TSR_SHIFT (0U)
18126#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
18127/*! @} */
18128
18129/*! @name TPR - RTC Time Prescaler Register */
18130/*! @{ */
18131#define RTC_TPR_TPR_MASK (0xFFFFU)
18132#define RTC_TPR_TPR_SHIFT (0U)
18133#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
18134/*! @} */
18135
18136/*! @name TAR - RTC Time Alarm Register */
18137/*! @{ */
18138#define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
18139#define RTC_TAR_TAR_SHIFT (0U)
18140#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
18141/*! @} */
18142
18143/*! @name TCR - RTC Time Compensation Register */
18144/*! @{ */
18145#define RTC_TCR_TCR_MASK (0xFFU)
18146#define RTC_TCR_TCR_SHIFT (0U)
18147/*! TCR - Time Compensation Register
18148 * 0b10000000..Time Prescaler Register overflows every 32896 clock cycles.
18149 * 0b11111111..Time Prescaler Register overflows every 32769 clock cycles.
18150 * 0b00000000..Time Prescaler Register overflows every 32768 clock cycles.
18151 * 0b00000001..Time Prescaler Register overflows every 32767 clock cycles.
18152 * 0b01111111..Time Prescaler Register overflows every 32641 clock cycles.
18153 */
18154#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
18155#define RTC_TCR_CIR_MASK (0xFF00U)
18156#define RTC_TCR_CIR_SHIFT (8U)
18157#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
18158#define RTC_TCR_TCV_MASK (0xFF0000U)
18159#define RTC_TCR_TCV_SHIFT (16U)
18160#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
18161#define RTC_TCR_CIC_MASK (0xFF000000U)
18162#define RTC_TCR_CIC_SHIFT (24U)
18163#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
18164/*! @} */
18165
18166/*! @name CR - RTC Control Register */
18167/*! @{ */
18168#define RTC_CR_SWR_MASK (0x1U)
18169#define RTC_CR_SWR_SHIFT (0U)
18170/*! SWR - Software Reset
18171 * 0b0..No effect.
18172 * 0b1..Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers . The SWR bit is cleared by VBAT POR and by software explicitly clearing it.
18173 */
18174#define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
18175#define RTC_CR_WPE_MASK (0x2U)
18176#define RTC_CR_WPE_SHIFT (1U)
18177/*! WPE - Wakeup Pin Enable
18178 * 0b0..Wakeup pin is disabled.
18179 * 0b1..Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts or the wakeup pin is turned on.
18180 */
18181#define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
18182#define RTC_CR_SUP_MASK (0x4U)
18183#define RTC_CR_SUP_SHIFT (2U)
18184/*! SUP - Supervisor Access
18185 * 0b0..Non-supervisor mode write accesses are not supported and generate a bus error.
18186 * 0b1..Non-supervisor mode write accesses are supported.
18187 */
18188#define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
18189#define RTC_CR_UM_MASK (0x8U)
18190#define RTC_CR_UM_SHIFT (3U)
18191/*! UM - Update Mode
18192 * 0b0..Registers cannot be written when locked.
18193 * 0b1..Registers can be written when locked under limited conditions.
18194 */
18195#define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
18196#define RTC_CR_WPS_MASK (0x10U)
18197#define RTC_CR_WPS_SHIFT (4U)
18198/*! WPS - Wakeup Pin Select
18199 * 0b0..Wakeup pin asserts (active low, open drain) if the RTC interrupt asserts or the wakeup pin is turned on.
18200 * 0b1..Wakeup pin instead outputs the RTC 32kHz clock, provided the wakeup pin is turned on and the 32kHz clock is output to other peripherals.
18201 */
18202#define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
18203#define RTC_CR_OSCE_MASK (0x100U)
18204#define RTC_CR_OSCE_SHIFT (8U)
18205/*! OSCE - Oscillator Enable
18206 * 0b0..32.768 kHz oscillator is disabled.
18207 * 0b1..32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize.
18208 */
18209#define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
18210#define RTC_CR_CLKO_MASK (0x200U)
18211#define RTC_CR_CLKO_SHIFT (9U)
18212/*! CLKO - Clock Output
18213 * 0b0..The 32 kHz clock is output to other peripherals.
18214 * 0b1..The 32 kHz clock is not output to other peripherals.
18215 */
18216#define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
18217#define RTC_CR_SC16P_MASK (0x400U)
18218#define RTC_CR_SC16P_SHIFT (10U)
18219/*! SC16P - Oscillator 16pF Load Configure
18220 * 0b0..Disable the load.
18221 * 0b1..Enable the additional load.
18222 */
18223#define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
18224#define RTC_CR_SC8P_MASK (0x800U)
18225#define RTC_CR_SC8P_SHIFT (11U)
18226/*! SC8P - Oscillator 8pF Load Configure
18227 * 0b0..Disable the load.
18228 * 0b1..Enable the additional load.
18229 */
18230#define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
18231#define RTC_CR_SC4P_MASK (0x1000U)
18232#define RTC_CR_SC4P_SHIFT (12U)
18233/*! SC4P - Oscillator 4pF Load Configure
18234 * 0b0..Disable the load.
18235 * 0b1..Enable the additional load.
18236 */
18237#define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
18238#define RTC_CR_SC2P_MASK (0x2000U)
18239#define RTC_CR_SC2P_SHIFT (13U)
18240/*! SC2P - Oscillator 2pF Load Configure
18241 * 0b0..Disable the load.
18242 * 0b1..Enable the additional load.
18243 */
18244#define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
18245/*! @} */
18246
18247/*! @name SR - RTC Status Register */
18248/*! @{ */
18249#define RTC_SR_TIF_MASK (0x1U)
18250#define RTC_SR_TIF_SHIFT (0U)
18251/*! TIF - Time Invalid Flag
18252 * 0b0..Time is valid.
18253 * 0b1..Time is invalid and time counter is read as zero.
18254 */
18255#define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
18256#define RTC_SR_TOF_MASK (0x2U)
18257#define RTC_SR_TOF_SHIFT (1U)
18258/*! TOF - Time Overflow Flag
18259 * 0b0..Time overflow has not occurred.
18260 * 0b1..Time overflow has occurred and time counter is read as zero.
18261 */
18262#define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
18263#define RTC_SR_TAF_MASK (0x4U)
18264#define RTC_SR_TAF_SHIFT (2U)
18265/*! TAF - Time Alarm Flag
18266 * 0b0..Time alarm has not occurred.
18267 * 0b1..Time alarm has occurred.
18268 */
18269#define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
18270#define RTC_SR_MOF_MASK (0x8U)
18271#define RTC_SR_MOF_SHIFT (3U)
18272/*! MOF - Monotonic Overflow Flag
18273 * 0b0..Monotonic counter overflow has not occurred.
18274 * 0b1..Monotonic counter overflow has occurred and monotonic counter is read as zero.
18275 */
18276#define RTC_SR_MOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
18277#define RTC_SR_TCE_MASK (0x10U)
18278#define RTC_SR_TCE_SHIFT (4U)
18279/*! TCE - Time Counter Enable
18280 * 0b0..Time counter is disabled.
18281 * 0b1..Time counter is enabled.
18282 */
18283#define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
18284/*! @} */
18285
18286/*! @name LR - RTC Lock Register */
18287/*! @{ */
18288#define RTC_LR_TCL_MASK (0x8U)
18289#define RTC_LR_TCL_SHIFT (3U)
18290/*! TCL - Time Compensation Lock
18291 * 0b0..Time Compensation Register is locked and writes are ignored.
18292 * 0b1..Time Compensation Register is not locked and writes complete as normal.
18293 */
18294#define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
18295#define RTC_LR_CRL_MASK (0x10U)
18296#define RTC_LR_CRL_SHIFT (4U)
18297/*! CRL - Control Register Lock
18298 * 0b0..Control Register is locked and writes are ignored.
18299 * 0b1..Control Register is not locked and writes complete as normal.
18300 */
18301#define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
18302#define RTC_LR_SRL_MASK (0x20U)
18303#define RTC_LR_SRL_SHIFT (5U)
18304/*! SRL - Status Register Lock
18305 * 0b0..Status Register is locked and writes are ignored.
18306 * 0b1..Status Register is not locked and writes complete as normal.
18307 */
18308#define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
18309#define RTC_LR_LRL_MASK (0x40U)
18310#define RTC_LR_LRL_SHIFT (6U)
18311/*! LRL - Lock Register Lock
18312 * 0b0..Lock Register is locked and writes are ignored.
18313 * 0b1..Lock Register is not locked and writes complete as normal.
18314 */
18315#define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
18316#define RTC_LR_TTSL_MASK (0x100U)
18317#define RTC_LR_TTSL_SHIFT (8U)
18318/*! TTSL - Tamper Time Seconds Lock
18319 * 0b0..Tamper Time Seconds Register is locked and writes are ignored.
18320 * 0b1..Tamper Time Seconds Register is not locked and writes complete as normal.
18321 */
18322#define RTC_LR_TTSL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
18323#define RTC_LR_MEL_MASK (0x200U)
18324#define RTC_LR_MEL_SHIFT (9U)
18325/*! MEL - Monotonic Enable Lock
18326 * 0b0..Monotonic Enable Register is locked and writes are ignored.
18327 * 0b1..Monotonic Enable Register is not locked and writes complete as normal.
18328 */
18329#define RTC_LR_MEL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
18330#define RTC_LR_MCLL_MASK (0x400U)
18331#define RTC_LR_MCLL_SHIFT (10U)
18332/*! MCLL - Monotonic Counter Low Lock
18333 * 0b0..Monotonic Counter Low Register is locked and writes are ignored.
18334 * 0b1..Monotonic Counter Low Register is not locked and writes complete as normal.
18335 */
18336#define RTC_LR_MCLL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
18337#define RTC_LR_MCHL_MASK (0x800U)
18338#define RTC_LR_MCHL_SHIFT (11U)
18339/*! MCHL - Monotonic Counter High Lock
18340 * 0b0..Monotonic Counter High Register is locked and writes are ignored.
18341 * 0b1..Monotonic Counter High Register is not locked and writes complete as normal.
18342 */
18343#define RTC_LR_MCHL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
18344/*! @} */
18345
18346/*! @name IER - RTC Interrupt Enable Register */
18347/*! @{ */
18348#define RTC_IER_TIIE_MASK (0x1U)
18349#define RTC_IER_TIIE_SHIFT (0U)
18350/*! TIIE - Time Invalid Interrupt Enable
18351 * 0b0..Time invalid flag does not generate an interrupt.
18352 * 0b1..Time invalid flag does generate an interrupt.
18353 */
18354#define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
18355#define RTC_IER_TOIE_MASK (0x2U)
18356#define RTC_IER_TOIE_SHIFT (1U)
18357/*! TOIE - Time Overflow Interrupt Enable
18358 * 0b0..Time overflow flag does not generate an interrupt.
18359 * 0b1..Time overflow flag does generate an interrupt.
18360 */
18361#define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
18362#define RTC_IER_TAIE_MASK (0x4U)
18363#define RTC_IER_TAIE_SHIFT (2U)
18364/*! TAIE - Time Alarm Interrupt Enable
18365 * 0b0..Time alarm flag does not generate an interrupt.
18366 * 0b1..Time alarm flag does generate an interrupt.
18367 */
18368#define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
18369#define RTC_IER_MOIE_MASK (0x8U)
18370#define RTC_IER_MOIE_SHIFT (3U)
18371/*! MOIE - Monotonic Overflow Interrupt Enable
18372 * 0b0..Monotonic overflow flag does not generate an interrupt.
18373 * 0b1..Monotonic overflow flag does generate an interrupt.
18374 */
18375#define RTC_IER_MOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
18376#define RTC_IER_TSIE_MASK (0x10U)
18377#define RTC_IER_TSIE_SHIFT (4U)
18378/*! TSIE - Time Seconds Interrupt Enable
18379 * 0b0..Seconds interrupt is disabled.
18380 * 0b1..Seconds interrupt is enabled.
18381 */
18382#define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
18383#define RTC_IER_WPON_MASK (0x80U)
18384#define RTC_IER_WPON_SHIFT (7U)
18385/*! WPON - Wakeup Pin On
18386 * 0b0..No effect.
18387 * 0b1..If the wakeup pin is enabled, then the wakeup pin will assert.
18388 */
18389#define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
18390/*! @} */
18391
18392/*! @name TTSR - RTC Tamper Time Seconds Register */
18393/*! @{ */
18394#define RTC_TTSR_TTS_MASK (0xFFFFFFFFU)
18395#define RTC_TTSR_TTS_SHIFT (0U)
18396#define RTC_TTSR_TTS(x) (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
18397/*! @} */
18398
18399/*! @name MER - RTC Monotonic Enable Register */
18400/*! @{ */
18401#define RTC_MER_MCE_MASK (0x10U)
18402#define RTC_MER_MCE_SHIFT (4U)
18403/*! MCE - Monotonic Counter Enable
18404 * 0b0..Writes to the monotonic counter load the counter with the value written.
18405 * 0b1..Writes to the monotonic counter increment the counter.
18406 */
18407#define RTC_MER_MCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
18408/*! @} */
18409
18410/*! @name MCLR - RTC Monotonic Counter Low Register */
18411/*! @{ */
18412#define RTC_MCLR_MCL_MASK (0xFFFFFFFFU)
18413#define RTC_MCLR_MCL_SHIFT (0U)
18414#define RTC_MCLR_MCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
18415/*! @} */
18416
18417/*! @name MCHR - RTC Monotonic Counter High Register */
18418/*! @{ */
18419#define RTC_MCHR_MCH_MASK (0xFFFFFFFFU)
18420#define RTC_MCHR_MCH_SHIFT (0U)
18421#define RTC_MCHR_MCH(x) (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
18422/*! @} */
18423
18424/*! @name WAR - RTC Write Access Register */
18425/*! @{ */
18426#define RTC_WAR_TSRW_MASK (0x1U)
18427#define RTC_WAR_TSRW_SHIFT (0U)
18428/*! TSRW - Time Seconds Register Write
18429 * 0b0..Writes to the Time Seconds Register are ignored.
18430 * 0b1..Writes to the Time Seconds Register complete as normal.
18431 */
18432#define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
18433#define RTC_WAR_TPRW_MASK (0x2U)
18434#define RTC_WAR_TPRW_SHIFT (1U)
18435/*! TPRW - Time Prescaler Register Write
18436 * 0b0..Writes to the Time Prescaler Register are ignored.
18437 * 0b1..Writes to the Time Prescaler Register complete as normal.
18438 */
18439#define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
18440#define RTC_WAR_TARW_MASK (0x4U)
18441#define RTC_WAR_TARW_SHIFT (2U)
18442/*! TARW - Time Alarm Register Write
18443 * 0b0..Writes to the Time Alarm Register are ignored.
18444 * 0b1..Writes to the Time Alarm Register complete as normal.
18445 */
18446#define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
18447#define RTC_WAR_TCRW_MASK (0x8U)
18448#define RTC_WAR_TCRW_SHIFT (3U)
18449/*! TCRW - Time Compensation Register Write
18450 * 0b0..Writes to the Time Compensation Register are ignored.
18451 * 0b1..Writes to the Time Compensation Register complete as normal.
18452 */
18453#define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
18454#define RTC_WAR_CRW_MASK (0x10U)
18455#define RTC_WAR_CRW_SHIFT (4U)
18456/*! CRW - Control Register Write
18457 * 0b0..Writes to the Control Register are ignored.
18458 * 0b1..Writes to the Control Register complete as normal.
18459 */
18460#define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
18461#define RTC_WAR_SRW_MASK (0x20U)
18462#define RTC_WAR_SRW_SHIFT (5U)
18463/*! SRW - Status Register Write
18464 * 0b0..Writes to the Status Register are ignored.
18465 * 0b1..Writes to the Status Register complete as normal.
18466 */
18467#define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
18468#define RTC_WAR_LRW_MASK (0x40U)
18469#define RTC_WAR_LRW_SHIFT (6U)
18470/*! LRW - Lock Register Write
18471 * 0b0..Writes to the Lock Register are ignored.
18472 * 0b1..Writes to the Lock Register complete as normal.
18473 */
18474#define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
18475#define RTC_WAR_IERW_MASK (0x80U)
18476#define RTC_WAR_IERW_SHIFT (7U)
18477/*! IERW - Interrupt Enable Register Write
18478 * 0b0..Writes to the Interupt Enable Register are ignored.
18479 * 0b1..Writes to the Interrupt Enable Register complete as normal.
18480 */
18481#define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
18482#define RTC_WAR_TTSW_MASK (0x100U)
18483#define RTC_WAR_TTSW_SHIFT (8U)
18484/*! TTSW - Tamper Time Seconds Write
18485 * 0b0..Writes to the Tamper Time Seconds Register are ignored.
18486 * 0b1..Writes to the Tamper Time Seconds Register complete as normal.
18487 */
18488#define RTC_WAR_TTSW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
18489#define RTC_WAR_MERW_MASK (0x200U)
18490#define RTC_WAR_MERW_SHIFT (9U)
18491/*! MERW - Monotonic Enable Register Write
18492 * 0b0..Writes to the Monotonic Enable Register are ignored.
18493 * 0b1..Writes to the Monotonic Enable Register complete as normal.
18494 */
18495#define RTC_WAR_MERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
18496#define RTC_WAR_MCLW_MASK (0x400U)
18497#define RTC_WAR_MCLW_SHIFT (10U)
18498/*! MCLW - Monotonic Counter Low Write
18499 * 0b0..Writes to the Monotonic Counter Low Register are ignored.
18500 * 0b1..Writes to the Monotonic Counter Low Register complete as normal.
18501 */
18502#define RTC_WAR_MCLW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
18503#define RTC_WAR_MCHW_MASK (0x800U)
18504#define RTC_WAR_MCHW_SHIFT (11U)
18505/*! MCHW - Monotonic Counter High Write
18506 * 0b0..Writes to the Monotonic Counter High Register are ignored.
18507 * 0b1..Writes to the Monotonic Counter High Register complete as normal.
18508 */
18509#define RTC_WAR_MCHW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
18510/*! @} */
18511
18512/*! @name RAR - RTC Read Access Register */
18513/*! @{ */
18514#define RTC_RAR_TSRR_MASK (0x1U)
18515#define RTC_RAR_TSRR_SHIFT (0U)
18516/*! TSRR - Time Seconds Register Read
18517 * 0b0..Reads to the Time Seconds Register are ignored.
18518 * 0b1..Reads to the Time Seconds Register complete as normal.
18519 */
18520#define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
18521#define RTC_RAR_TPRR_MASK (0x2U)
18522#define RTC_RAR_TPRR_SHIFT (1U)
18523/*! TPRR - Time Prescaler Register Read
18524 * 0b0..Reads to the Time Pprescaler Register are ignored.
18525 * 0b1..Reads to the Time Prescaler Register complete as normal.
18526 */
18527#define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
18528#define RTC_RAR_TARR_MASK (0x4U)
18529#define RTC_RAR_TARR_SHIFT (2U)
18530/*! TARR - Time Alarm Register Read
18531 * 0b0..Reads to the Time Alarm Register are ignored.
18532 * 0b1..Reads to the Time Alarm Register complete as normal.
18533 */
18534#define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
18535#define RTC_RAR_TCRR_MASK (0x8U)
18536#define RTC_RAR_TCRR_SHIFT (3U)
18537/*! TCRR - Time Compensation Register Read
18538 * 0b0..Reads to the Time Compensation Register are ignored.
18539 * 0b1..Reads to the Time Compensation Register complete as normal.
18540 */
18541#define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
18542#define RTC_RAR_CRR_MASK (0x10U)
18543#define RTC_RAR_CRR_SHIFT (4U)
18544/*! CRR - Control Register Read
18545 * 0b0..Reads to the Control Register are ignored.
18546 * 0b1..Reads to the Control Register complete as normal.
18547 */
18548#define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
18549#define RTC_RAR_SRR_MASK (0x20U)
18550#define RTC_RAR_SRR_SHIFT (5U)
18551/*! SRR - Status Register Read
18552 * 0b0..Reads to the Status Register are ignored.
18553 * 0b1..Reads to the Status Register complete as normal.
18554 */
18555#define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
18556#define RTC_RAR_LRR_MASK (0x40U)
18557#define RTC_RAR_LRR_SHIFT (6U)
18558/*! LRR - Lock Register Read
18559 * 0b0..Reads to the Lock Register are ignored.
18560 * 0b1..Reads to the Lock Register complete as normal.
18561 */
18562#define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
18563#define RTC_RAR_IERR_MASK (0x80U)
18564#define RTC_RAR_IERR_SHIFT (7U)
18565/*! IERR - Interrupt Enable Register Read
18566 * 0b0..Reads to the Interrupt Enable Register are ignored.
18567 * 0b1..Reads to the Interrupt Enable Register complete as normal.
18568 */
18569#define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
18570#define RTC_RAR_TTSR_MASK (0x100U)
18571#define RTC_RAR_TTSR_SHIFT (8U)
18572/*! TTSR - Tamper Time Seconds Read
18573 * 0b0..Reads to the Tamper Time Seconds Register are ignored.
18574 * 0b1..Reads to the Tamper Time Seconds Register complete as normal.
18575 */
18576#define RTC_RAR_TTSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
18577#define RTC_RAR_MERR_MASK (0x200U)
18578#define RTC_RAR_MERR_SHIFT (9U)
18579/*! MERR - Monotonic Enable Register Read
18580 * 0b0..Reads to the Monotonic Enable Register are ignored.
18581 * 0b1..Reads to the Monotonic Enable Register complete as normal.
18582 */
18583#define RTC_RAR_MERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
18584#define RTC_RAR_MCLR_MASK (0x400U)
18585#define RTC_RAR_MCLR_SHIFT (10U)
18586/*! MCLR - Monotonic Counter Low Read
18587 * 0b0..Reads to the Monotonic Counter Low Register are ignored.
18588 * 0b1..Reads to the Monotonic Counter Low Register complete as normal.
18589 */
18590#define RTC_RAR_MCLR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
18591#define RTC_RAR_MCHR_MASK (0x800U)
18592#define RTC_RAR_MCHR_SHIFT (11U)
18593/*! MCHR - Monotonic Counter High Read
18594 * 0b0..Reads to the Monotonic Counter High Register are ignored.
18595 * 0b1..Reads to the Monotonic Counter High Register complete as normal.
18596 */
18597#define RTC_RAR_MCHR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
18598/*! @} */
18599
18600
18601/*!
18602 * @}
18603 */ /* end of group RTC_Register_Masks */
18604
18605
18606/* RTC - Peripheral instance base addresses */
18607/** Peripheral RTC base address */
18608#define RTC_BASE (0x4003D000u)
18609/** Peripheral RTC base pointer */
18610#define RTC ((RTC_Type *)RTC_BASE)
18611/** Array initializer of RTC peripheral base addresses */
18612#define RTC_BASE_ADDRS { RTC_BASE }
18613/** Array initializer of RTC peripheral base pointers */
18614#define RTC_BASE_PTRS { RTC }
18615/** Interrupt vectors for the RTC peripheral type */
18616#define RTC_IRQS { RTC_IRQn }
18617#define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
18618
18619/*!
18620 * @}
18621 */ /* end of group RTC_Peripheral_Access_Layer */
18622
18623
18624/* ----------------------------------------------------------------------------
18625 -- SDHC Peripheral Access Layer
18626 ---------------------------------------------------------------------------- */
18627
18628/*!
18629 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
18630 * @{
18631 */
18632
18633/** SDHC - Register Layout Typedef */
18634typedef struct {
18635 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
18636 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
18637 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
18638 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
18639 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
18640 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
18641 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
18642 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
18643 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
18644 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
18645 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
18646 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
18647 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
18648 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
18649 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
18650 uint8_t RESERVED_0[8];
18651 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
18652 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
18653 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
18654 uint8_t RESERVED_1[100];
18655 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
18656 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
18657 uint8_t RESERVED_2[52];
18658 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
18659} SDHC_Type;
18660
18661/* ----------------------------------------------------------------------------
18662 -- SDHC Register Masks
18663 ---------------------------------------------------------------------------- */
18664
18665/*!
18666 * @addtogroup SDHC_Register_Masks SDHC Register Masks
18667 * @{
18668 */
18669
18670/*! @name DSADDR - DMA System Address register */
18671/*! @{ */
18672#define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU)
18673#define SDHC_DSADDR_DSADDR_SHIFT (2U)
18674#define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
18675/*! @} */
18676
18677/*! @name BLKATTR - Block Attributes register */
18678/*! @{ */
18679#define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
18680#define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
18681/*! BLKSIZE - Transfer Block Size
18682 * 0b0000000000000..No data transfer.
18683 * 0b0000000000001..1 Byte
18684 * 0b0000000000010..2 Bytes
18685 * 0b0000000000011..3 Bytes
18686 * 0b0000000000100..4 Bytes
18687 * 0b0000111111111..511 Bytes
18688 * 0b0001000000000..512 Bytes
18689 * 0b0100000000000..2048 Bytes
18690 * 0b1000000000000..4096 Bytes
18691 */
18692#define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
18693#define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
18694#define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
18695/*! BLKCNT - Blocks Count For Current Transfer
18696 * 0b0000000000000000..Stop count.
18697 * 0b0000000000000001..1 block
18698 * 0b0000000000000010..2 blocks
18699 * 0b1111111111111111..65535 blocks
18700 */
18701#define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
18702/*! @} */
18703
18704/*! @name CMDARG - Command Argument register */
18705/*! @{ */
18706#define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU)
18707#define SDHC_CMDARG_CMDARG_SHIFT (0U)
18708#define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
18709/*! @} */
18710
18711/*! @name XFERTYP - Transfer Type register */
18712/*! @{ */
18713#define SDHC_XFERTYP_DMAEN_MASK (0x1U)
18714#define SDHC_XFERTYP_DMAEN_SHIFT (0U)
18715/*! DMAEN - DMA Enable
18716 * 0b0..Disable
18717 * 0b1..Enable
18718 */
18719#define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
18720#define SDHC_XFERTYP_BCEN_MASK (0x2U)
18721#define SDHC_XFERTYP_BCEN_SHIFT (1U)
18722/*! BCEN - Block Count Enable
18723 * 0b0..Disable
18724 * 0b1..Enable
18725 */
18726#define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
18727#define SDHC_XFERTYP_AC12EN_MASK (0x4U)
18728#define SDHC_XFERTYP_AC12EN_SHIFT (2U)
18729/*! AC12EN - Auto CMD12 Enable
18730 * 0b0..Disable
18731 * 0b1..Enable
18732 */
18733#define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
18734#define SDHC_XFERTYP_DTDSEL_MASK (0x10U)
18735#define SDHC_XFERTYP_DTDSEL_SHIFT (4U)
18736/*! DTDSEL - Data Transfer Direction Select
18737 * 0b0..Write host to card.
18738 * 0b1..Read card to host.
18739 */
18740#define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
18741#define SDHC_XFERTYP_MSBSEL_MASK (0x20U)
18742#define SDHC_XFERTYP_MSBSEL_SHIFT (5U)
18743/*! MSBSEL - Multi/Single Block Select
18744 * 0b0..Single block.
18745 * 0b1..Multiple blocks.
18746 */
18747#define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
18748#define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
18749#define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
18750/*! RSPTYP - Response Type Select
18751 * 0b00..No response.
18752 * 0b01..Response length 136.
18753 * 0b10..Response length 48.
18754 * 0b11..Response length 48, check busy after response.
18755 */
18756#define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
18757#define SDHC_XFERTYP_CCCEN_MASK (0x80000U)
18758#define SDHC_XFERTYP_CCCEN_SHIFT (19U)
18759/*! CCCEN - Command CRC Check Enable
18760 * 0b0..Disable
18761 * 0b1..Enable
18762 */
18763#define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
18764#define SDHC_XFERTYP_CICEN_MASK (0x100000U)
18765#define SDHC_XFERTYP_CICEN_SHIFT (20U)
18766/*! CICEN - Command Index Check Enable
18767 * 0b0..Disable
18768 * 0b1..Enable
18769 */
18770#define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
18771#define SDHC_XFERTYP_DPSEL_MASK (0x200000U)
18772#define SDHC_XFERTYP_DPSEL_SHIFT (21U)
18773/*! DPSEL - Data Present Select
18774 * 0b0..No data present.
18775 * 0b1..Data present.
18776 */
18777#define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
18778#define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
18779#define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
18780/*! CMDTYP - Command Type
18781 * 0b00..Normal other commands.
18782 * 0b01..Suspend CMD52 for writing bus suspend in CCCR.
18783 * 0b10..Resume CMD52 for writing function select in CCCR.
18784 * 0b11..Abort CMD12, CMD52 for writing I/O abort in CCCR.
18785 */
18786#define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
18787#define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
18788#define SDHC_XFERTYP_CMDINX_SHIFT (24U)
18789#define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
18790/*! @} */
18791
18792/*! @name CMDRSP - Command Response 0..Command Response 3 */
18793/*! @{ */
18794#define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU)
18795#define SDHC_CMDRSP_CMDRSP0_SHIFT (0U)
18796#define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
18797#define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU)
18798#define SDHC_CMDRSP_CMDRSP1_SHIFT (0U)
18799#define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
18800#define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU)
18801#define SDHC_CMDRSP_CMDRSP2_SHIFT (0U)
18802#define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
18803#define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU)
18804#define SDHC_CMDRSP_CMDRSP3_SHIFT (0U)
18805#define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
18806/*! @} */
18807
18808/* The count of SDHC_CMDRSP */
18809#define SDHC_CMDRSP_COUNT (4U)
18810
18811/*! @name DATPORT - Buffer Data Port register */
18812/*! @{ */
18813#define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU)
18814#define SDHC_DATPORT_DATCONT_SHIFT (0U)
18815#define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
18816/*! @} */
18817
18818/*! @name PRSSTAT - Present State register */
18819/*! @{ */
18820#define SDHC_PRSSTAT_CIHB_MASK (0x1U)
18821#define SDHC_PRSSTAT_CIHB_SHIFT (0U)
18822/*! CIHB - Command Inhibit (CMD)
18823 * 0b0..Can issue command using only CMD line.
18824 * 0b1..Cannot issue command.
18825 */
18826#define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
18827#define SDHC_PRSSTAT_CDIHB_MASK (0x2U)
18828#define SDHC_PRSSTAT_CDIHB_SHIFT (1U)
18829/*! CDIHB - Command Inhibit (DAT)
18830 * 0b0..Can issue command which uses the DAT line.
18831 * 0b1..Cannot issue command which uses the DAT line.
18832 */
18833#define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
18834#define SDHC_PRSSTAT_DLA_MASK (0x4U)
18835#define SDHC_PRSSTAT_DLA_SHIFT (2U)
18836/*! DLA - Data Line Active
18837 * 0b0..DAT line inactive.
18838 * 0b1..DAT line active.
18839 */
18840#define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
18841#define SDHC_PRSSTAT_SDSTB_MASK (0x8U)
18842#define SDHC_PRSSTAT_SDSTB_SHIFT (3U)
18843/*! SDSTB - SD Clock Stable
18844 * 0b0..Clock is changing frequency and not stable.
18845 * 0b1..Clock is stable.
18846 */
18847#define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
18848#define SDHC_PRSSTAT_IPGOFF_MASK (0x10U)
18849#define SDHC_PRSSTAT_IPGOFF_SHIFT (4U)
18850/*! IPGOFF - Bus Clock Gated Off Internally
18851 * 0b0..Bus clock is active.
18852 * 0b1..Bus clock is gated off.
18853 */
18854#define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
18855#define SDHC_PRSSTAT_HCKOFF_MASK (0x20U)
18856#define SDHC_PRSSTAT_HCKOFF_SHIFT (5U)
18857/*! HCKOFF - System Clock Gated Off Internally
18858 * 0b0..System clock is active.
18859 * 0b1..System clock is gated off.
18860 */
18861#define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
18862#define SDHC_PRSSTAT_PEROFF_MASK (0x40U)
18863#define SDHC_PRSSTAT_PEROFF_SHIFT (6U)
18864/*! PEROFF - SDHC clock Gated Off Internally
18865 * 0b0..SDHC clock is active.
18866 * 0b1..SDHC clock is gated off.
18867 */
18868#define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
18869#define SDHC_PRSSTAT_SDOFF_MASK (0x80U)
18870#define SDHC_PRSSTAT_SDOFF_SHIFT (7U)
18871/*! SDOFF - SD Clock Gated Off Internally
18872 * 0b0..SD clock is active.
18873 * 0b1..SD clock is gated off.
18874 */
18875#define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
18876#define SDHC_PRSSTAT_WTA_MASK (0x100U)
18877#define SDHC_PRSSTAT_WTA_SHIFT (8U)
18878/*! WTA - Write Transfer Active
18879 * 0b0..No valid data.
18880 * 0b1..Transferring data.
18881 */
18882#define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
18883#define SDHC_PRSSTAT_RTA_MASK (0x200U)
18884#define SDHC_PRSSTAT_RTA_SHIFT (9U)
18885/*! RTA - Read Transfer Active
18886 * 0b0..No valid data.
18887 * 0b1..Transferring data.
18888 */
18889#define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
18890#define SDHC_PRSSTAT_BWEN_MASK (0x400U)
18891#define SDHC_PRSSTAT_BWEN_SHIFT (10U)
18892/*! BWEN - Buffer Write Enable
18893 * 0b0..Write disable, the buffer can hold valid data less than the write watermark level.
18894 * 0b1..Write enable, the buffer can hold valid data greater than the write watermark level.
18895 */
18896#define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
18897#define SDHC_PRSSTAT_BREN_MASK (0x800U)
18898#define SDHC_PRSSTAT_BREN_SHIFT (11U)
18899/*! BREN - Buffer Read Enable
18900 * 0b0..Read disable, valid data less than the watermark level exist in the buffer.
18901 * 0b1..Read enable, valid data greater than the watermark level exist in the buffer.
18902 */
18903#define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
18904#define SDHC_PRSSTAT_CINS_MASK (0x10000U)
18905#define SDHC_PRSSTAT_CINS_SHIFT (16U)
18906/*! CINS - Card Inserted
18907 * 0b0..Power on reset or no card.
18908 * 0b1..Card inserted.
18909 */
18910#define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
18911#define SDHC_PRSSTAT_CLSL_MASK (0x800000U)
18912#define SDHC_PRSSTAT_CLSL_SHIFT (23U)
18913#define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
18914#define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
18915#define SDHC_PRSSTAT_DLSL_SHIFT (24U)
18916#define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
18917/*! @} */
18918
18919/*! @name PROCTL - Protocol Control register */
18920/*! @{ */
18921#define SDHC_PROCTL_LCTL_MASK (0x1U)
18922#define SDHC_PROCTL_LCTL_SHIFT (0U)
18923/*! LCTL - LED Control
18924 * 0b0..LED off.
18925 * 0b1..LED on.
18926 */
18927#define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
18928#define SDHC_PROCTL_DTW_MASK (0x6U)
18929#define SDHC_PROCTL_DTW_SHIFT (1U)
18930/*! DTW - Data Transfer Width
18931 * 0b00..1-bit mode
18932 * 0b01..4-bit mode
18933 * 0b10..8-bit mode
18934 * 0b11..Reserved
18935 */
18936#define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
18937#define SDHC_PROCTL_D3CD_MASK (0x8U)
18938#define SDHC_PROCTL_D3CD_SHIFT (3U)
18939/*! D3CD - DAT3 As Card Detection Pin
18940 * 0b0..DAT3 does not monitor card Insertion.
18941 * 0b1..DAT3 as card detection pin.
18942 */
18943#define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
18944#define SDHC_PROCTL_EMODE_MASK (0x30U)
18945#define SDHC_PROCTL_EMODE_SHIFT (4U)
18946/*! EMODE - Endian Mode
18947 * 0b00..Big endian mode
18948 * 0b01..Half word big endian mode
18949 * 0b10..Little endian mode
18950 * 0b11..Reserved
18951 */
18952#define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
18953#define SDHC_PROCTL_CDTL_MASK (0x40U)
18954#define SDHC_PROCTL_CDTL_SHIFT (6U)
18955/*! CDTL - Card Detect Test Level
18956 * 0b0..Card detect test level is 0, no card inserted.
18957 * 0b1..Card detect test level is 1, card inserted.
18958 */
18959#define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
18960#define SDHC_PROCTL_CDSS_MASK (0x80U)
18961#define SDHC_PROCTL_CDSS_SHIFT (7U)
18962/*! CDSS - Card Detect Signal Selection
18963 * 0b0..Card detection level is selected for normal purpose.
18964 * 0b1..Card detection test level is selected for test purpose.
18965 */
18966#define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
18967#define SDHC_PROCTL_DMAS_MASK (0x300U)
18968#define SDHC_PROCTL_DMAS_SHIFT (8U)
18969/*! DMAS - DMA Select
18970 * 0b00..No DMA or simple DMA is selected.
18971 * 0b01..ADMA1 is selected.
18972 * 0b10..ADMA2 is selected.
18973 * 0b11..Reserved
18974 */
18975#define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
18976#define SDHC_PROCTL_SABGREQ_MASK (0x10000U)
18977#define SDHC_PROCTL_SABGREQ_SHIFT (16U)
18978/*! SABGREQ - Stop At Block Gap Request
18979 * 0b0..Transfer
18980 * 0b1..Stop
18981 */
18982#define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
18983#define SDHC_PROCTL_CREQ_MASK (0x20000U)
18984#define SDHC_PROCTL_CREQ_SHIFT (17U)
18985/*! CREQ - Continue Request
18986 * 0b0..No effect.
18987 * 0b1..Restart
18988 */
18989#define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
18990#define SDHC_PROCTL_RWCTL_MASK (0x40000U)
18991#define SDHC_PROCTL_RWCTL_SHIFT (18U)
18992/*! RWCTL - Read Wait Control
18993 * 0b0..Disable read wait control, and stop SD clock at block gap when SABGREQ is set.
18994 * 0b1..Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set.
18995 */
18996#define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
18997#define SDHC_PROCTL_IABG_MASK (0x80000U)
18998#define SDHC_PROCTL_IABG_SHIFT (19U)
18999/*! IABG - Interrupt At Block Gap
19000 * 0b0..Disabled
19001 * 0b1..Enabled
19002 */
19003#define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
19004#define SDHC_PROCTL_WECINT_MASK (0x1000000U)
19005#define SDHC_PROCTL_WECINT_SHIFT (24U)
19006/*! WECINT - Wakeup Event Enable On Card Interrupt
19007 * 0b0..Disabled
19008 * 0b1..Enabled
19009 */
19010#define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
19011#define SDHC_PROCTL_WECINS_MASK (0x2000000U)
19012#define SDHC_PROCTL_WECINS_SHIFT (25U)
19013/*! WECINS - Wakeup Event Enable On SD Card Insertion
19014 * 0b0..Disabled
19015 * 0b1..Enabled
19016 */
19017#define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
19018#define SDHC_PROCTL_WECRM_MASK (0x4000000U)
19019#define SDHC_PROCTL_WECRM_SHIFT (26U)
19020/*! WECRM - Wakeup Event Enable On SD Card Removal
19021 * 0b0..Disabled
19022 * 0b1..Enabled
19023 */
19024#define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
19025/*! @} */
19026
19027/*! @name SYSCTL - System Control register */
19028/*! @{ */
19029#define SDHC_SYSCTL_IPGEN_MASK (0x1U)
19030#define SDHC_SYSCTL_IPGEN_SHIFT (0U)
19031/*! IPGEN - IPG Clock Enable
19032 * 0b0..Bus clock will be internally gated off.
19033 * 0b1..Bus clock will not be automatically gated off.
19034 */
19035#define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
19036#define SDHC_SYSCTL_HCKEN_MASK (0x2U)
19037#define SDHC_SYSCTL_HCKEN_SHIFT (1U)
19038/*! HCKEN - System Clock Enable
19039 * 0b0..System clock will be internally gated off.
19040 * 0b1..System clock will not be automatically gated off.
19041 */
19042#define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
19043#define SDHC_SYSCTL_PEREN_MASK (0x4U)
19044#define SDHC_SYSCTL_PEREN_SHIFT (2U)
19045/*! PEREN - Peripheral Clock Enable
19046 * 0b0..SDHC clock will be internally gated off.
19047 * 0b1..SDHC clock will not be automatically gated off.
19048 */
19049#define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
19050#define SDHC_SYSCTL_SDCLKEN_MASK (0x8U)
19051#define SDHC_SYSCTL_SDCLKEN_SHIFT (3U)
19052#define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
19053#define SDHC_SYSCTL_DVS_MASK (0xF0U)
19054#define SDHC_SYSCTL_DVS_SHIFT (4U)
19055/*! DVS - Divisor
19056 * 0b0000..Divisor by 1.
19057 * 0b0001..Divisor by 2.
19058 * 0b1110..Divisor by 15.
19059 * 0b1111..Divisor by 16.
19060 */
19061#define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
19062#define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
19063#define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
19064/*! SDCLKFS - SDCLK Frequency Select
19065 * 0b00000001..Base clock divided by 2.
19066 * 0b00000010..Base clock divided by 4.
19067 * 0b00000100..Base clock divided by 8.
19068 * 0b00001000..Base clock divided by 16.
19069 * 0b00010000..Base clock divided by 32.
19070 * 0b00100000..Base clock divided by 64.
19071 * 0b01000000..Base clock divided by 128.
19072 * 0b10000000..Base clock divided by 256.
19073 */
19074#define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
19075#define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
19076#define SDHC_SYSCTL_DTOCV_SHIFT (16U)
19077/*! DTOCV - Data Timeout Counter Value
19078 * 0b0000..SDCLK x 2 13
19079 * 0b0001..SDCLK x 2 14
19080 * 0b1110..SDCLK x 2 27
19081 * 0b1111..Reserved
19082 */
19083#define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
19084#define SDHC_SYSCTL_RSTA_MASK (0x1000000U)
19085#define SDHC_SYSCTL_RSTA_SHIFT (24U)
19086/*! RSTA - Software Reset For ALL
19087 * 0b0..No reset.
19088 * 0b1..Reset.
19089 */
19090#define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
19091#define SDHC_SYSCTL_RSTC_MASK (0x2000000U)
19092#define SDHC_SYSCTL_RSTC_SHIFT (25U)
19093/*! RSTC - Software Reset For CMD Line
19094 * 0b0..No reset.
19095 * 0b1..Reset.
19096 */
19097#define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
19098#define SDHC_SYSCTL_RSTD_MASK (0x4000000U)
19099#define SDHC_SYSCTL_RSTD_SHIFT (26U)
19100/*! RSTD - Software Reset For DAT Line
19101 * 0b0..No reset.
19102 * 0b1..Reset.
19103 */
19104#define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
19105#define SDHC_SYSCTL_INITA_MASK (0x8000000U)
19106#define SDHC_SYSCTL_INITA_SHIFT (27U)
19107#define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
19108/*! @} */
19109
19110/*! @name IRQSTAT - Interrupt Status register */
19111/*! @{ */
19112#define SDHC_IRQSTAT_CC_MASK (0x1U)
19113#define SDHC_IRQSTAT_CC_SHIFT (0U)
19114/*! CC - Command Complete
19115 * 0b0..Command not complete.
19116 * 0b1..Command complete.
19117 */
19118#define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
19119#define SDHC_IRQSTAT_TC_MASK (0x2U)
19120#define SDHC_IRQSTAT_TC_SHIFT (1U)
19121/*! TC - Transfer Complete
19122 * 0b0..Transfer not complete.
19123 * 0b1..Transfer complete.
19124 */
19125#define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
19126#define SDHC_IRQSTAT_BGE_MASK (0x4U)
19127#define SDHC_IRQSTAT_BGE_SHIFT (2U)
19128/*! BGE - Block Gap Event
19129 * 0b0..No block gap event.
19130 * 0b1..Transaction stopped at block gap.
19131 */
19132#define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
19133#define SDHC_IRQSTAT_DINT_MASK (0x8U)
19134#define SDHC_IRQSTAT_DINT_SHIFT (3U)
19135/*! DINT - DMA Interrupt
19136 * 0b0..No DMA Interrupt.
19137 * 0b1..DMA Interrupt is generated.
19138 */
19139#define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
19140#define SDHC_IRQSTAT_BWR_MASK (0x10U)
19141#define SDHC_IRQSTAT_BWR_SHIFT (4U)
19142/*! BWR - Buffer Write Ready
19143 * 0b0..Not ready to write buffer.
19144 * 0b1..Ready to write buffer.
19145 */
19146#define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
19147#define SDHC_IRQSTAT_BRR_MASK (0x20U)
19148#define SDHC_IRQSTAT_BRR_SHIFT (5U)
19149/*! BRR - Buffer Read Ready
19150 * 0b0..Not ready to read buffer.
19151 * 0b1..Ready to read buffer.
19152 */
19153#define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
19154#define SDHC_IRQSTAT_CINS_MASK (0x40U)
19155#define SDHC_IRQSTAT_CINS_SHIFT (6U)
19156/*! CINS - Card Insertion
19157 * 0b0..Card state unstable or removed.
19158 * 0b1..Card inserted.
19159 */
19160#define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
19161#define SDHC_IRQSTAT_CRM_MASK (0x80U)
19162#define SDHC_IRQSTAT_CRM_SHIFT (7U)
19163/*! CRM - Card Removal
19164 * 0b0..Card state unstable or inserted.
19165 * 0b1..Card removed.
19166 */
19167#define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
19168#define SDHC_IRQSTAT_CINT_MASK (0x100U)
19169#define SDHC_IRQSTAT_CINT_SHIFT (8U)
19170/*! CINT - Card Interrupt
19171 * 0b0..No Card Interrupt.
19172 * 0b1..Generate Card Interrupt.
19173 */
19174#define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
19175#define SDHC_IRQSTAT_CTOE_MASK (0x10000U)
19176#define SDHC_IRQSTAT_CTOE_SHIFT (16U)
19177/*! CTOE - Command Timeout Error
19178 * 0b0..No error.
19179 * 0b1..Time out.
19180 */
19181#define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
19182#define SDHC_IRQSTAT_CCE_MASK (0x20000U)
19183#define SDHC_IRQSTAT_CCE_SHIFT (17U)
19184/*! CCE - Command CRC Error
19185 * 0b0..No error.
19186 * 0b1..CRC Error generated.
19187 */
19188#define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
19189#define SDHC_IRQSTAT_CEBE_MASK (0x40000U)
19190#define SDHC_IRQSTAT_CEBE_SHIFT (18U)
19191/*! CEBE - Command End Bit Error
19192 * 0b0..No error.
19193 * 0b1..End Bit Error generated.
19194 */
19195#define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
19196#define SDHC_IRQSTAT_CIE_MASK (0x80000U)
19197#define SDHC_IRQSTAT_CIE_SHIFT (19U)
19198/*! CIE - Command Index Error
19199 * 0b0..No error.
19200 * 0b1..Error.
19201 */
19202#define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
19203#define SDHC_IRQSTAT_DTOE_MASK (0x100000U)
19204#define SDHC_IRQSTAT_DTOE_SHIFT (20U)
19205/*! DTOE - Data Timeout Error
19206 * 0b0..No error.
19207 * 0b1..Time out.
19208 */
19209#define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
19210#define SDHC_IRQSTAT_DCE_MASK (0x200000U)
19211#define SDHC_IRQSTAT_DCE_SHIFT (21U)
19212/*! DCE - Data CRC Error
19213 * 0b0..No error.
19214 * 0b1..Error.
19215 */
19216#define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
19217#define SDHC_IRQSTAT_DEBE_MASK (0x400000U)
19218#define SDHC_IRQSTAT_DEBE_SHIFT (22U)
19219/*! DEBE - Data End Bit Error
19220 * 0b0..No error.
19221 * 0b1..Error.
19222 */
19223#define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
19224#define SDHC_IRQSTAT_AC12E_MASK (0x1000000U)
19225#define SDHC_IRQSTAT_AC12E_SHIFT (24U)
19226/*! AC12E - Auto CMD12 Error
19227 * 0b0..No error.
19228 * 0b1..Error.
19229 */
19230#define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
19231#define SDHC_IRQSTAT_DMAE_MASK (0x10000000U)
19232#define SDHC_IRQSTAT_DMAE_SHIFT (28U)
19233/*! DMAE - DMA Error
19234 * 0b0..No error.
19235 * 0b1..Error.
19236 */
19237#define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
19238/*! @} */
19239
19240/*! @name IRQSTATEN - Interrupt Status Enable register */
19241/*! @{ */
19242#define SDHC_IRQSTATEN_CCSEN_MASK (0x1U)
19243#define SDHC_IRQSTATEN_CCSEN_SHIFT (0U)
19244/*! CCSEN - Command Complete Status Enable
19245 * 0b0..Masked
19246 * 0b1..Enabled
19247 */
19248#define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
19249#define SDHC_IRQSTATEN_TCSEN_MASK (0x2U)
19250#define SDHC_IRQSTATEN_TCSEN_SHIFT (1U)
19251/*! TCSEN - Transfer Complete Status Enable
19252 * 0b0..Masked
19253 * 0b1..Enabled
19254 */
19255#define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
19256#define SDHC_IRQSTATEN_BGESEN_MASK (0x4U)
19257#define SDHC_IRQSTATEN_BGESEN_SHIFT (2U)
19258/*! BGESEN - Block Gap Event Status Enable
19259 * 0b0..Masked
19260 * 0b1..Enabled
19261 */
19262#define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
19263#define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U)
19264#define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U)
19265/*! DINTSEN - DMA Interrupt Status Enable
19266 * 0b0..Masked
19267 * 0b1..Enabled
19268 */
19269#define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
19270#define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U)
19271#define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U)
19272/*! BWRSEN - Buffer Write Ready Status Enable
19273 * 0b0..Masked
19274 * 0b1..Enabled
19275 */
19276#define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
19277#define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U)
19278#define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U)
19279/*! BRRSEN - Buffer Read Ready Status Enable
19280 * 0b0..Masked
19281 * 0b1..Enabled
19282 */
19283#define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
19284#define SDHC_IRQSTATEN_CINSEN_MASK (0x40U)
19285#define SDHC_IRQSTATEN_CINSEN_SHIFT (6U)
19286/*! CINSEN - Card Insertion Status Enable
19287 * 0b0..Masked
19288 * 0b1..Enabled
19289 */
19290#define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
19291#define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U)
19292#define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U)
19293/*! CRMSEN - Card Removal Status Enable
19294 * 0b0..Masked
19295 * 0b1..Enabled
19296 */
19297#define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
19298#define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U)
19299#define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U)
19300/*! CINTSEN - Card Interrupt Status Enable
19301 * 0b0..Masked
19302 * 0b1..Enabled
19303 */
19304#define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
19305#define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U)
19306#define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U)
19307/*! CTOESEN - Command Timeout Error Status Enable
19308 * 0b0..Masked
19309 * 0b1..Enabled
19310 */
19311#define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
19312#define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U)
19313#define SDHC_IRQSTATEN_CCESEN_SHIFT (17U)
19314/*! CCESEN - Command CRC Error Status Enable
19315 * 0b0..Masked
19316 * 0b1..Enabled
19317 */
19318#define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
19319#define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U)
19320#define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U)
19321/*! CEBESEN - Command End Bit Error Status Enable
19322 * 0b0..Masked
19323 * 0b1..Enabled
19324 */
19325#define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
19326#define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U)
19327#define SDHC_IRQSTATEN_CIESEN_SHIFT (19U)
19328/*! CIESEN - Command Index Error Status Enable
19329 * 0b0..Masked
19330 * 0b1..Enabled
19331 */
19332#define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
19333#define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U)
19334#define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U)
19335/*! DTOESEN - Data Timeout Error Status Enable
19336 * 0b0..Masked
19337 * 0b1..Enabled
19338 */
19339#define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
19340#define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U)
19341#define SDHC_IRQSTATEN_DCESEN_SHIFT (21U)
19342/*! DCESEN - Data CRC Error Status Enable
19343 * 0b0..Masked
19344 * 0b1..Enabled
19345 */
19346#define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
19347#define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U)
19348#define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U)
19349/*! DEBESEN - Data End Bit Error Status Enable
19350 * 0b0..Masked
19351 * 0b1..Enabled
19352 */
19353#define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
19354#define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U)
19355#define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U)
19356/*! AC12ESEN - Auto CMD12 Error Status Enable
19357 * 0b0..Masked
19358 * 0b1..Enabled
19359 */
19360#define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
19361#define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U)
19362#define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U)
19363/*! DMAESEN - DMA Error Status Enable
19364 * 0b0..Masked
19365 * 0b1..Enabled
19366 */
19367#define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
19368/*! @} */
19369
19370/*! @name IRQSIGEN - Interrupt Signal Enable register */
19371/*! @{ */
19372#define SDHC_IRQSIGEN_CCIEN_MASK (0x1U)
19373#define SDHC_IRQSIGEN_CCIEN_SHIFT (0U)
19374/*! CCIEN - Command Complete Interrupt Enable
19375 * 0b0..Masked
19376 * 0b1..Enabled
19377 */
19378#define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
19379#define SDHC_IRQSIGEN_TCIEN_MASK (0x2U)
19380#define SDHC_IRQSIGEN_TCIEN_SHIFT (1U)
19381/*! TCIEN - Transfer Complete Interrupt Enable
19382 * 0b0..Masked
19383 * 0b1..Enabled
19384 */
19385#define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
19386#define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U)
19387#define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U)
19388/*! BGEIEN - Block Gap Event Interrupt Enable
19389 * 0b0..Masked
19390 * 0b1..Enabled
19391 */
19392#define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
19393#define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U)
19394#define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U)
19395/*! DINTIEN - DMA Interrupt Enable
19396 * 0b0..Masked
19397 * 0b1..Enabled
19398 */
19399#define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
19400#define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U)
19401#define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U)
19402/*! BWRIEN - Buffer Write Ready Interrupt Enable
19403 * 0b0..Masked
19404 * 0b1..Enabled
19405 */
19406#define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
19407#define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U)
19408#define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U)
19409/*! BRRIEN - Buffer Read Ready Interrupt Enable
19410 * 0b0..Masked
19411 * 0b1..Enabled
19412 */
19413#define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
19414#define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U)
19415#define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U)
19416/*! CINSIEN - Card Insertion Interrupt Enable
19417 * 0b0..Masked
19418 * 0b1..Enabled
19419 */
19420#define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
19421#define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U)
19422#define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U)
19423/*! CRMIEN - Card Removal Interrupt Enable
19424 * 0b0..Masked
19425 * 0b1..Enabled
19426 */
19427#define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
19428#define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U)
19429#define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U)
19430/*! CINTIEN - Card Interrupt Enable
19431 * 0b0..Masked
19432 * 0b1..Enabled
19433 */
19434#define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
19435#define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U)
19436#define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U)
19437/*! CTOEIEN - Command Timeout Error Interrupt Enable
19438 * 0b0..Masked
19439 * 0b1..Enabled
19440 */
19441#define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
19442#define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U)
19443#define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U)
19444/*! CCEIEN - Command CRC Error Interrupt Enable
19445 * 0b0..Masked
19446 * 0b1..Enabled
19447 */
19448#define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
19449#define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U)
19450#define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U)
19451/*! CEBEIEN - Command End Bit Error Interrupt Enable
19452 * 0b0..Masked
19453 * 0b1..Enabled
19454 */
19455#define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
19456#define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U)
19457#define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U)
19458/*! CIEIEN - Command Index Error Interrupt Enable
19459 * 0b0..Masked
19460 * 0b1..Enabled
19461 */
19462#define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
19463#define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U)
19464#define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U)
19465/*! DTOEIEN - Data Timeout Error Interrupt Enable
19466 * 0b0..Masked
19467 * 0b1..Enabled
19468 */
19469#define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
19470#define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U)
19471#define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U)
19472/*! DCEIEN - Data CRC Error Interrupt Enable
19473 * 0b0..Masked
19474 * 0b1..Enabled
19475 */
19476#define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
19477#define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U)
19478#define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U)
19479/*! DEBEIEN - Data End Bit Error Interrupt Enable
19480 * 0b0..Masked
19481 * 0b1..Enabled
19482 */
19483#define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
19484#define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U)
19485#define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U)
19486/*! AC12EIEN - Auto CMD12 Error Interrupt Enable
19487 * 0b0..Masked
19488 * 0b1..Enabled
19489 */
19490#define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
19491#define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U)
19492#define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U)
19493/*! DMAEIEN - DMA Error Interrupt Enable
19494 * 0b0..Masked
19495 * 0b1..Enabled
19496 */
19497#define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
19498/*! @} */
19499
19500/*! @name AC12ERR - Auto CMD12 Error Status Register */
19501/*! @{ */
19502#define SDHC_AC12ERR_AC12NE_MASK (0x1U)
19503#define SDHC_AC12ERR_AC12NE_SHIFT (0U)
19504/*! AC12NE - Auto CMD12 Not Executed
19505 * 0b0..Executed.
19506 * 0b1..Not executed.
19507 */
19508#define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
19509#define SDHC_AC12ERR_AC12TOE_MASK (0x2U)
19510#define SDHC_AC12ERR_AC12TOE_SHIFT (1U)
19511/*! AC12TOE - Auto CMD12 Timeout Error
19512 * 0b0..No error.
19513 * 0b1..Time out.
19514 */
19515#define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
19516#define SDHC_AC12ERR_AC12EBE_MASK (0x4U)
19517#define SDHC_AC12ERR_AC12EBE_SHIFT (2U)
19518/*! AC12EBE - Auto CMD12 End Bit Error
19519 * 0b0..No error.
19520 * 0b1..End bit error generated.
19521 */
19522#define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
19523#define SDHC_AC12ERR_AC12CE_MASK (0x8U)
19524#define SDHC_AC12ERR_AC12CE_SHIFT (3U)
19525/*! AC12CE - Auto CMD12 CRC Error
19526 * 0b0..No CRC error.
19527 * 0b1..CRC error met in Auto CMD12 response.
19528 */
19529#define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
19530#define SDHC_AC12ERR_AC12IE_MASK (0x10U)
19531#define SDHC_AC12ERR_AC12IE_SHIFT (4U)
19532/*! AC12IE - Auto CMD12 Index Error
19533 * 0b0..No error.
19534 * 0b1..Error, the CMD index in response is not CMD12.
19535 */
19536#define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
19537#define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U)
19538#define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U)
19539/*! CNIBAC12E - Command Not Issued By Auto CMD12 Error
19540 * 0b0..No error.
19541 * 0b1..Not issued.
19542 */
19543#define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
19544/*! @} */
19545
19546/*! @name HTCAPBLT - Host Controller Capabilities */
19547/*! @{ */
19548#define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
19549#define SDHC_HTCAPBLT_MBL_SHIFT (16U)
19550/*! MBL - Max Block Length
19551 * 0b000..512 bytes
19552 * 0b001..1024 bytes
19553 * 0b010..2048 bytes
19554 * 0b011..4096 bytes
19555 */
19556#define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
19557#define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U)
19558#define SDHC_HTCAPBLT_ADMAS_SHIFT (20U)
19559/*! ADMAS - ADMA Support
19560 * 0b0..Advanced DMA not supported.
19561 * 0b1..Advanced DMA supported.
19562 */
19563#define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
19564#define SDHC_HTCAPBLT_HSS_MASK (0x200000U)
19565#define SDHC_HTCAPBLT_HSS_SHIFT (21U)
19566/*! HSS - High Speed Support
19567 * 0b0..High speed not supported.
19568 * 0b1..High speed supported.
19569 */
19570#define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
19571#define SDHC_HTCAPBLT_DMAS_MASK (0x400000U)
19572#define SDHC_HTCAPBLT_DMAS_SHIFT (22U)
19573/*! DMAS - DMA Support
19574 * 0b0..DMA not supported.
19575 * 0b1..DMA supported.
19576 */
19577#define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
19578#define SDHC_HTCAPBLT_SRS_MASK (0x800000U)
19579#define SDHC_HTCAPBLT_SRS_SHIFT (23U)
19580/*! SRS - Suspend/Resume Support
19581 * 0b0..Not supported.
19582 * 0b1..Supported.
19583 */
19584#define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
19585#define SDHC_HTCAPBLT_VS33_MASK (0x1000000U)
19586#define SDHC_HTCAPBLT_VS33_SHIFT (24U)
19587/*! VS33 - Voltage Support 3.3 V
19588 * 0b0..3.3 V not supported.
19589 * 0b1..3.3 V supported.
19590 */
19591#define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
19592/*! @} */
19593
19594/*! @name WML - Watermark Level Register */
19595/*! @{ */
19596#define SDHC_WML_RDWML_MASK (0xFFU)
19597#define SDHC_WML_RDWML_SHIFT (0U)
19598#define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
19599#define SDHC_WML_WRWML_MASK (0xFF0000U)
19600#define SDHC_WML_WRWML_SHIFT (16U)
19601#define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
19602/*! @} */
19603
19604/*! @name FEVT - Force Event register */
19605/*! @{ */
19606#define SDHC_FEVT_AC12NE_MASK (0x1U)
19607#define SDHC_FEVT_AC12NE_SHIFT (0U)
19608#define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
19609#define SDHC_FEVT_AC12TOE_MASK (0x2U)
19610#define SDHC_FEVT_AC12TOE_SHIFT (1U)
19611#define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
19612#define SDHC_FEVT_AC12CE_MASK (0x4U)
19613#define SDHC_FEVT_AC12CE_SHIFT (2U)
19614#define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
19615#define SDHC_FEVT_AC12EBE_MASK (0x8U)
19616#define SDHC_FEVT_AC12EBE_SHIFT (3U)
19617#define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
19618#define SDHC_FEVT_AC12IE_MASK (0x10U)
19619#define SDHC_FEVT_AC12IE_SHIFT (4U)
19620#define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
19621#define SDHC_FEVT_CNIBAC12E_MASK (0x80U)
19622#define SDHC_FEVT_CNIBAC12E_SHIFT (7U)
19623#define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
19624#define SDHC_FEVT_CTOE_MASK (0x10000U)
19625#define SDHC_FEVT_CTOE_SHIFT (16U)
19626#define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
19627#define SDHC_FEVT_CCE_MASK (0x20000U)
19628#define SDHC_FEVT_CCE_SHIFT (17U)
19629#define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
19630#define SDHC_FEVT_CEBE_MASK (0x40000U)
19631#define SDHC_FEVT_CEBE_SHIFT (18U)
19632#define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
19633#define SDHC_FEVT_CIE_MASK (0x80000U)
19634#define SDHC_FEVT_CIE_SHIFT (19U)
19635#define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
19636#define SDHC_FEVT_DTOE_MASK (0x100000U)
19637#define SDHC_FEVT_DTOE_SHIFT (20U)
19638#define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
19639#define SDHC_FEVT_DCE_MASK (0x200000U)
19640#define SDHC_FEVT_DCE_SHIFT (21U)
19641#define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
19642#define SDHC_FEVT_DEBE_MASK (0x400000U)
19643#define SDHC_FEVT_DEBE_SHIFT (22U)
19644#define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
19645#define SDHC_FEVT_AC12E_MASK (0x1000000U)
19646#define SDHC_FEVT_AC12E_SHIFT (24U)
19647#define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
19648#define SDHC_FEVT_DMAE_MASK (0x10000000U)
19649#define SDHC_FEVT_DMAE_SHIFT (28U)
19650#define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
19651#define SDHC_FEVT_CINT_MASK (0x80000000U)
19652#define SDHC_FEVT_CINT_SHIFT (31U)
19653#define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
19654/*! @} */
19655
19656/*! @name ADMAES - ADMA Error Status register */
19657/*! @{ */
19658#define SDHC_ADMAES_ADMAES_MASK (0x3U)
19659#define SDHC_ADMAES_ADMAES_SHIFT (0U)
19660#define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
19661#define SDHC_ADMAES_ADMALME_MASK (0x4U)
19662#define SDHC_ADMAES_ADMALME_SHIFT (2U)
19663/*! ADMALME - ADMA Length Mismatch Error
19664 * 0b0..No error.
19665 * 0b1..Error.
19666 */
19667#define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
19668#define SDHC_ADMAES_ADMADCE_MASK (0x8U)
19669#define SDHC_ADMAES_ADMADCE_SHIFT (3U)
19670/*! ADMADCE - ADMA Descriptor Error
19671 * 0b0..No error.
19672 * 0b1..Error.
19673 */
19674#define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
19675/*! @} */
19676
19677/*! @name ADSADDR - ADMA System Addressregister */
19678/*! @{ */
19679#define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU)
19680#define SDHC_ADSADDR_ADSADDR_SHIFT (2U)
19681#define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
19682/*! @} */
19683
19684/*! @name VENDOR - Vendor Specific register */
19685/*! @{ */
19686#define SDHC_VENDOR_EXBLKNU_MASK (0x2U)
19687#define SDHC_VENDOR_EXBLKNU_SHIFT (1U)
19688/*! EXBLKNU - Exact Block Number Block Read Enable For SDIO CMD53
19689 * 0b0..None exact block read.
19690 * 0b1..Exact block read for SDIO CMD53.
19691 */
19692#define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
19693#define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
19694#define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
19695#define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
19696/*! @} */
19697
19698/*! @name MMCBOOT - MMC Boot register */
19699/*! @{ */
19700#define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
19701#define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
19702/*! DTOCVACK - Boot ACK Time Out Counter Value
19703 * 0b0000..SDCLK x 2^8
19704 * 0b0001..SDCLK x 2^9
19705 * 0b0010..SDCLK x 2^10
19706 * 0b0011..SDCLK x 2^11
19707 * 0b0100..SDCLK x 2^12
19708 * 0b0101..SDCLK x 2^13
19709 * 0b0110..SDCLK x 2^14
19710 * 0b0111..SDCLK x 2^15
19711 * 0b1110..SDCLK x 2^22
19712 * 0b1111..Reserved
19713 */
19714#define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
19715#define SDHC_MMCBOOT_BOOTACK_MASK (0x10U)
19716#define SDHC_MMCBOOT_BOOTACK_SHIFT (4U)
19717/*! BOOTACK - Boot Ack Mode Select
19718 * 0b0..No ack.
19719 * 0b1..Ack.
19720 */
19721#define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
19722#define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U)
19723#define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U)
19724/*! BOOTMODE - Boot Mode Select
19725 * 0b0..Normal boot.
19726 * 0b1..Alternative boot.
19727 */
19728#define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
19729#define SDHC_MMCBOOT_BOOTEN_MASK (0x40U)
19730#define SDHC_MMCBOOT_BOOTEN_SHIFT (6U)
19731/*! BOOTEN - Boot Mode Enable
19732 * 0b0..Fast boot disable.
19733 * 0b1..Fast boot enable.
19734 */
19735#define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
19736#define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U)
19737#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U)
19738#define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
19739#define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
19740#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
19741#define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
19742/*! @} */
19743
19744/*! @name HOSTVER - Host Controller Version */
19745/*! @{ */
19746#define SDHC_HOSTVER_SVN_MASK (0xFFU)
19747#define SDHC_HOSTVER_SVN_SHIFT (0U)
19748/*! SVN - Specification Version Number
19749 * 0b00000001..SD host specification version 2.0, supports test event register and ADMA.
19750 */
19751#define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
19752#define SDHC_HOSTVER_VVN_MASK (0xFF00U)
19753#define SDHC_HOSTVER_VVN_SHIFT (8U)
19754/*! VVN - Vendor Version Number
19755 * 0b00000000..Freescale SDHC version 1.0
19756 * 0b00010000..Freescale SDHC version 2.0
19757 * 0b00010001..Freescale SDHC version 2.1
19758 * 0b00010010..Freescale SDHC version 2.2
19759 */
19760#define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
19761/*! @} */
19762
19763
19764/*!
19765 * @}
19766 */ /* end of group SDHC_Register_Masks */
19767
19768
19769/* SDHC - Peripheral instance base addresses */
19770/** Peripheral SDHC base address */
19771#define SDHC_BASE (0x400B1000u)
19772/** Peripheral SDHC base pointer */
19773#define SDHC ((SDHC_Type *)SDHC_BASE)
19774/** Array initializer of SDHC peripheral base addresses */
19775#define SDHC_BASE_ADDRS { SDHC_BASE }
19776/** Array initializer of SDHC peripheral base pointers */
19777#define SDHC_BASE_PTRS { SDHC }
19778/** Interrupt vectors for the SDHC peripheral type */
19779#define SDHC_IRQS { SDHC_IRQn }
19780
19781/*!
19782 * @}
19783 */ /* end of group SDHC_Peripheral_Access_Layer */
19784
19785
19786/* ----------------------------------------------------------------------------
19787 -- SDRAM Peripheral Access Layer
19788 ---------------------------------------------------------------------------- */
19789
19790/*!
19791 * @addtogroup SDRAM_Peripheral_Access_Layer SDRAM Peripheral Access Layer
19792 * @{
19793 */
19794
19795/** SDRAM - Register Layout Typedef */
19796typedef struct {
19797 uint8_t RESERVED_0[66];
19798 __IO uint16_t CTRL; /**< Control Register, offset: 0x42 */
19799 uint8_t RESERVED_1[4];
19800 struct { /* offset: 0x48, array step: 0x8 */
19801 __IO uint32_t AC; /**< Address and Control Register, array offset: 0x48, array step: 0x8 */
19802 __IO uint32_t CM; /**< Control Mask, array offset: 0x4C, array step: 0x8 */
19803 } BLOCK[2];
19804} SDRAM_Type;
19805
19806/* ----------------------------------------------------------------------------
19807 -- SDRAM Register Masks
19808 ---------------------------------------------------------------------------- */
19809
19810/*!
19811 * @addtogroup SDRAM_Register_Masks SDRAM Register Masks
19812 * @{
19813 */
19814
19815/*! @name CTRL - Control Register */
19816/*! @{ */
19817#define SDRAM_CTRL_RC_MASK (0x1FFU)
19818#define SDRAM_CTRL_RC_SHIFT (0U)
19819#define SDRAM_CTRL_RC(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RC_SHIFT)) & SDRAM_CTRL_RC_MASK)
19820#define SDRAM_CTRL_RTIM_MASK (0x600U)
19821#define SDRAM_CTRL_RTIM_SHIFT (9U)
19822/*! RTIM - Refresh timing
19823 * 0b00..3 clocks
19824 * 0b01..6 clocks
19825 * 0b10..9 clocks
19826 * 0b11..9 clocks
19827 */
19828#define SDRAM_CTRL_RTIM(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RTIM_SHIFT)) & SDRAM_CTRL_RTIM_MASK)
19829#define SDRAM_CTRL_IS_MASK (0x800U)
19830#define SDRAM_CTRL_IS_SHIFT (11U)
19831/*! IS
19832 * 0b0..Take no action or issue a selfx command to exit self refresh.
19833 * 0b1..SDRAM controller sends a self command to both SDRAM blocks to put them in low-power, self-refresh state where they remain until IS is cleared. When IS is cleared, the controller sends a selfx command for the SDRAMs to exit self-refresh. The refresh counter is suspended while the SDRAMs are in self-refresh; the SDRAM controls the refresh period.
19834 */
19835#define SDRAM_CTRL_IS(x) (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK)
19836/*! @} */
19837
19838/*! @name AC - Address and Control Register */
19839/*! @{ */
19840#define SDRAM_AC_IP_MASK (0x8U)
19841#define SDRAM_AC_IP_SHIFT (3U)
19842/*! IP - Initiate precharge all (pall) command.
19843 * 0b0..Take no action.
19844 * 0b1..A pall command is sent to the associated SDRAM block. During initialization, this command is executed after all DRAM controller registers are programmed. After IP is set, the next write to an appropriate SDRAM address generates the pall command to the SDRAM block.
19845 */
19846#define SDRAM_AC_IP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)
19847#define SDRAM_AC_PS_MASK (0x30U)
19848#define SDRAM_AC_PS_SHIFT (4U)
19849/*! PS - Port size.
19850 * 0b00..32-bit port
19851 * 0b01..8-bit port
19852 * 0b10..16-bit port
19853 * 0b11..16-bit port
19854 */
19855#define SDRAM_AC_PS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)
19856#define SDRAM_AC_IMRS_MASK (0x40U)
19857#define SDRAM_AC_IMRS_SHIFT (6U)
19858/*! IMRS - Initiate mode register set (mrs) command.
19859 * 0b0..Take no action
19860 * 0b1..Initiate mrs command
19861 */
19862#define SDRAM_AC_IMRS(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)
19863#define SDRAM_AC_CBM_MASK (0x700U)
19864#define SDRAM_AC_CBM_SHIFT (8U)
19865#define SDRAM_AC_CBM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CBM_SHIFT)) & SDRAM_AC_CBM_MASK)
19866#define SDRAM_AC_CASL_MASK (0x3000U)
19867#define SDRAM_AC_CASL_SHIFT (12U)
19868#define SDRAM_AC_CASL(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CASL_SHIFT)) & SDRAM_AC_CASL_MASK)
19869#define SDRAM_AC_RE_MASK (0x8000U)
19870#define SDRAM_AC_RE_SHIFT (15U)
19871/*! RE - Refresh enable
19872 * 0b0..Do not refresh associated DRAM block
19873 * 0b1..Refresh associated DRAM block
19874 */
19875#define SDRAM_AC_RE(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)
19876#define SDRAM_AC_BA_MASK (0xFFFC0000U)
19877#define SDRAM_AC_BA_SHIFT (18U)
19878#define SDRAM_AC_BA(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_BA_SHIFT)) & SDRAM_AC_BA_MASK)
19879/*! @} */
19880
19881/* The count of SDRAM_AC */
19882#define SDRAM_AC_COUNT (2U)
19883
19884/*! @name CM - Control Mask */
19885/*! @{ */
19886#define SDRAM_CM_V_MASK (0x1U)
19887#define SDRAM_CM_V_SHIFT (0U)
19888/*! V - Valid.
19889 * 0b0..Do not decode DRAM accesses.
19890 * 0b1..Registers controlling the DRAM block are initialized; DRAM accesses can be decoded
19891 */
19892#define SDRAM_CM_V(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)
19893#define SDRAM_CM_WP_MASK (0x100U)
19894#define SDRAM_CM_WP_SHIFT (8U)
19895/*! WP - Write protect.
19896 * 0b0..Allow write accesses
19897 * 0b1..Ignore write accesses. The DRAM controller ignores write accesses to the memory block and an address exception occurs. Write accesses to a write-protected DRAM region are compared in the chip select module for a hit. If no hit occurs, an external bus cycle is generated. If this external bus cycle is not acknowledged, an access exception occurs.
19898 */
19899#define SDRAM_CM_WP(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)
19900#define SDRAM_CM_BAM_MASK (0xFFFC0000U)
19901#define SDRAM_CM_BAM_SHIFT (18U)
19902/*! BAM - Base address mask.
19903 * 0b00000000000000..The associated address bit is used in decoding the DRAM hit to a memory block
19904 * 0b00000000000001..The associated address bit is not used in the DRAM hit decode
19905 */
19906#define SDRAM_CM_BAM(x) (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)
19907/*! @} */
19908
19909/* The count of SDRAM_CM */
19910#define SDRAM_CM_COUNT (2U)
19911
19912
19913/*!
19914 * @}
19915 */ /* end of group SDRAM_Register_Masks */
19916
19917
19918/* SDRAM - Peripheral instance base addresses */
19919/** Peripheral SDRAM base address */
19920#define SDRAM_BASE (0x4000F000u)
19921/** Peripheral SDRAM base pointer */
19922#define SDRAM ((SDRAM_Type *)SDRAM_BASE)
19923/** Array initializer of SDRAM peripheral base addresses */
19924#define SDRAM_BASE_ADDRS { SDRAM_BASE }
19925/** Array initializer of SDRAM peripheral base pointers */
19926#define SDRAM_BASE_PTRS { SDRAM }
19927
19928/*!
19929 * @}
19930 */ /* end of group SDRAM_Peripheral_Access_Layer */
19931
19932
19933/* ----------------------------------------------------------------------------
19934 -- SIM Peripheral Access Layer
19935 ---------------------------------------------------------------------------- */
19936
19937/*!
19938 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
19939 * @{
19940 */
19941
19942/** SIM - Register Layout Typedef */
19943typedef struct {
19944 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
19945 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
19946 __IO uint32_t USBPHYCTL; /**< USB PHY Control Register, offset: 0x8 */
19947 uint8_t RESERVED_0[4088];
19948 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
19949 uint8_t RESERVED_1[4];
19950 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
19951 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
19952 uint8_t RESERVED_2[4];
19953 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
19954 __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
19955 __IO uint32_t SOPT9; /**< System Options Register 9, offset: 0x1020 */
19956 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
19957 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
19958 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
19959 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
19960 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
19961 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
19962 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
19963 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
19964 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
19965 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
19966 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
19967 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
19968 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
19969 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
19970 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
19971 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
19972 __IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1064 */
19973 __IO uint32_t CLKDIV4; /**< System Clock Divider Register 4, offset: 0x1068 */
19974} SIM_Type;
19975
19976/* ----------------------------------------------------------------------------
19977 -- SIM Register Masks
19978 ---------------------------------------------------------------------------- */
19979
19980/*!
19981 * @addtogroup SIM_Register_Masks SIM Register Masks
19982 * @{
19983 */
19984
19985/*! @name SOPT1 - System Options Register 1 */
19986/*! @{ */
19987#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
19988#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
19989/*! RAMSIZE - RAM size
19990 * 0b0001..8 KB
19991 * 0b0011..16 KB
19992 * 0b0100..24 KB
19993 * 0b0101..32 KB
19994 * 0b0110..48 KB
19995 * 0b0111..64 KB
19996 * 0b1000..96 KB
19997 * 0b1001..128 KB
19998 * 0b1011..256 KB
19999 */
20000#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
20001#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
20002#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
20003/*! OSC32KSEL - 32K oscillator clock select
20004 * 0b00..System oscillator (OSC32KCLK)
20005 * 0b01..Reserved
20006 * 0b10..RTC 32.768kHz oscillator
20007 * 0b11..LPO 1 kHz
20008 */
20009#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
20010#define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
20011#define SIM_SOPT1_USBVSTBY_SHIFT (29U)
20012/*! USBVSTBY - USB voltage regulator in standby mode during VLPR and VLPW modes
20013 * 0b0..USB voltage regulator not in standby during VLPR and VLPW modes.
20014 * 0b1..USB voltage regulator in standby during VLPR and VLPW modes.
20015 */
20016#define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
20017#define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
20018#define SIM_SOPT1_USBSSTBY_SHIFT (30U)
20019/*! USBSSTBY - USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes.
20020 * 0b0..USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes.
20021 * 0b1..USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes.
20022 */
20023#define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
20024#define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
20025#define SIM_SOPT1_USBREGEN_SHIFT (31U)
20026/*! USBREGEN - USB voltage regulator enable
20027 * 0b0..USB voltage regulator is disabled.
20028 * 0b1..USB voltage regulator is enabled.
20029 */
20030#define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
20031/*! @} */
20032
20033/*! @name SOPT1CFG - SOPT1 Configuration Register */
20034/*! @{ */
20035#define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
20036#define SIM_SOPT1CFG_URWE_SHIFT (24U)
20037/*! URWE - USB voltage regulator enable write enable
20038 * 0b0..SOPT1 USBREGEN cannot be written.
20039 * 0b1..SOPT1 USBREGEN can be written.
20040 */
20041#define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
20042#define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
20043#define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
20044/*! UVSWE - USB voltage regulator VLP standby write enable
20045 * 0b0..SOPT1 USBVSTBY cannot be written.
20046 * 0b1..SOPT1 USBVSTBY can be written.
20047 */
20048#define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
20049#define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
20050#define SIM_SOPT1CFG_USSWE_SHIFT (26U)
20051/*! USSWE - USB voltage regulator stop standby write enable
20052 * 0b0..SOPT1 USBSSTBY cannot be written.
20053 * 0b1..SOPT1 USBSSTBY can be written.
20054 */
20055#define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
20056/*! @} */
20057
20058/*! @name USBPHYCTL - USB PHY Control Register */
20059/*! @{ */
20060#define SIM_USBPHYCTL_USBVREGSEL_MASK (0x100U)
20061#define SIM_USBPHYCTL_USBVREGSEL_SHIFT (8U)
20062/*! USBVREGSEL
20063 * 0b0..VREG_IN0 will be selected if both regulator inputs are powered
20064 * 0b1..VREG_IN1 will be selected if both regulator inputs are powered
20065 */
20066#define SIM_USBPHYCTL_USBVREGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGSEL_SHIFT)) & SIM_USBPHYCTL_USBVREGSEL_MASK)
20067#define SIM_USBPHYCTL_USBVREGPD_MASK (0x200U)
20068#define SIM_USBPHYCTL_USBVREGPD_SHIFT (9U)
20069/*! USBVREGPD
20070 * 0b0..Regulator output pulldown resistor is not enabled
20071 * 0b1..Regulator output pulldown resistor is enabled
20072 */
20073#define SIM_USBPHYCTL_USBVREGPD(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGPD_SHIFT)) & SIM_USBPHYCTL_USBVREGPD_MASK)
20074#define SIM_USBPHYCTL_USB3VOUTTRG_MASK (0x700000U)
20075#define SIM_USBPHYCTL_USB3VOUTTRG_SHIFT (20U)
20076/*! USB3VOUTTRG - USB 3.3V Output Target
20077 * 0b000..2.733V
20078 * 0b001..3.020V
20079 * 0b010..3.074V
20080 * 0b011..3.130V
20081 * 0b100..3.188V
20082 * 0b101..3.248V
20083 * 0b110..3.310V (default)
20084 * 0b111..3.662V (For Freescale use only, not for customer use)
20085 */
20086#define SIM_USBPHYCTL_USB3VOUTTRG(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT)) & SIM_USBPHYCTL_USB3VOUTTRG_MASK)
20087#define SIM_USBPHYCTL_USBDISILIM_MASK (0x800000U)
20088#define SIM_USBPHYCTL_USBDISILIM_SHIFT (23U)
20089/*! USBDISILIM - USB Disable Inrush Current Limit
20090 * 0b0..The current limiter for the USB Voltage Regulator is enabled
20091 * 0b1..The current limiter for the USB Voltage Regulator is disabled
20092 */
20093#define SIM_USBPHYCTL_USBDISILIM(x) (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBDISILIM_SHIFT)) & SIM_USBPHYCTL_USBDISILIM_MASK)
20094/*! @} */
20095
20096/*! @name SOPT2 - System Options Register 2 */
20097/*! @{ */
20098#define SIM_SOPT2_USBSLSRC_MASK (0x1U)
20099#define SIM_SOPT2_USBSLSRC_SHIFT (0U)
20100/*! USBSLSRC - USB Slow Clock Source
20101 * 0b0..MCGIRCLK
20102 * 0b1..RTC 32.768kHz clock
20103 */
20104#define SIM_SOPT2_USBSLSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSLSRC_SHIFT)) & SIM_SOPT2_USBSLSRC_MASK)
20105#define SIM_SOPT2_USBREGEN_MASK (0x2U)
20106#define SIM_SOPT2_USBREGEN_SHIFT (1U)
20107/*! USBREGEN - USB PHY PLL Regulator Enable
20108 * 0b0..USB PHY PLL Regulator disabled.
20109 * 0b1..USB PHY PLL Regulator enabled.
20110 */
20111#define SIM_SOPT2_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBREGEN_SHIFT)) & SIM_SOPT2_USBREGEN_MASK)
20112#define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
20113#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
20114/*! RTCCLKOUTSEL - RTC clock out select
20115 * 0b0..RTC 1 Hz clock is output on the RTC_CLKOUT pin.
20116 * 0b1..RTC 32.768kHz clock is output on the RTC_CLKOUT pin.
20117 */
20118#define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
20119#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
20120#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
20121/*! CLKOUTSEL - CLKOUT select
20122 * 0b000..FlexBus CLKOUT
20123 * 0b001..Reserved
20124 * 0b010..Flash clock
20125 * 0b011..LPO clock (1 kHz)
20126 * 0b100..MCGIRCLK
20127 * 0b101..RTC 32.768kHz clock
20128 * 0b110..OSCERCLK0
20129 * 0b111..IRC 48 MHz clock
20130 */
20131#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
20132#define SIM_SOPT2_FBSL_MASK (0x300U)
20133#define SIM_SOPT2_FBSL_SHIFT (8U)
20134/*! FBSL - FlexBus security level
20135 * 0b00..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed.
20136 * 0b01..All off-chip accesses (instruction and data) via the FlexBus or SDRAM are disallowed.
20137 * 0b10..Off-chip instruction accesses are disallowed. Data accesses are allowed.
20138 * 0b11..Off-chip instruction accesses and data accesses are allowed.
20139 */
20140#define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
20141#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
20142#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
20143/*! TRACECLKSEL - Debug trace clock select
20144 * 0b0..MCGOUTCLK, divided by the TRACECLK fractional divider as configured by SIM_CLKDIV4[TRACEFRAC, TRACEDIV]
20145 * 0b1..Core/system clock
20146 */
20147#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
20148#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
20149#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
20150/*! PLLFLLSEL - PLL/FLL clock select
20151 * 0b00..MCGFLLCLK clock
20152 * 0b01..MCGPLLCLK clock
20153 * 0b10..USB1 PFD clock
20154 * 0b11..IRC48 MHz clock
20155 */
20156#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
20157#define SIM_SOPT2_USBSRC_MASK (0x40000U)
20158#define SIM_SOPT2_USBSRC_SHIFT (18U)
20159/*! USBSRC - USB clock source select
20160 * 0b0..External bypass clock (USB_CLKIN).
20161 * 0b1..MCGFLLCLK, or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the USB fractional divider as configured by SIM_CLKDIV2[USBFRAC, USBDIV].
20162 */
20163#define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
20164#define SIM_SOPT2_TPMSRC_MASK (0x3000000U)
20165#define SIM_SOPT2_TPMSRC_SHIFT (24U)
20166/*! TPMSRC - TPM clock source select
20167 * 0b00..Clock disabled
20168 * 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
20169 * 0b10..OSCERCLK clock
20170 * 0b11..MCGIRCLK clock
20171 */
20172#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
20173#define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U)
20174#define SIM_SOPT2_LPUARTSRC_SHIFT (26U)
20175/*! LPUARTSRC - LPUART clock source select
20176 * 0b00..Clock disabled
20177 * 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL], and then divided by the PLLFLLCLK fractional divider as configured by SIM_CLKDIV3[PLLFLLFRAC, PLLFLLDIV].
20178 * 0b10..OSCERCLK clock
20179 * 0b11..MCGIRCLK clock
20180 */
20181#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
20182#define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
20183#define SIM_SOPT2_SDHCSRC_SHIFT (28U)
20184/*! SDHCSRC - SDHC clock source select
20185 * 0b00..Core/system clock.
20186 * 0b01..MCGFLLCLK, or MCGPLLCLK , or IRC48M , or USB1 PFD clock as selected by SOPT2[PLLFLLSEL].
20187 * 0b10..OSCERCLK clock
20188 * 0b11..External bypass clock (SDHC0_CLKIN)
20189 */
20190#define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
20191/*! @} */
20192
20193/*! @name SOPT4 - System Options Register 4 */
20194/*! @{ */
20195#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
20196#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
20197/*! FTM0FLT0 - FTM0 Fault 0 Select
20198 * 0b0..FTM0_FLT0 pin
20199 * 0b1..CMP0 out
20200 */
20201#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
20202#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
20203#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
20204/*! FTM0FLT1 - FTM0 Fault 1 Select
20205 * 0b0..FTM0_FLT1 pin
20206 * 0b1..CMP1 out
20207 */
20208#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
20209#define SIM_SOPT4_FTM0FLT2_MASK (0x4U)
20210#define SIM_SOPT4_FTM0FLT2_SHIFT (2U)
20211/*! FTM0FLT2 - FTM0 Fault 2 Select
20212 * 0b0..FTM0_FLT2 pin
20213 * 0b1..CMP2 out
20214 */
20215#define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
20216#define SIM_SOPT4_FTM0FLT3_MASK (0x8U)
20217#define SIM_SOPT4_FTM0FLT3_SHIFT (3U)
20218/*! FTM0FLT3 - FTM0 Fault 3 Select
20219 * 0b0..FTM0_FLT3 pin
20220 * 0b1..CMP3 out
20221 */
20222#define SIM_SOPT4_FTM0FLT3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)
20223#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
20224#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
20225/*! FTM1FLT0 - FTM1 Fault 0 Select
20226 * 0b0..FTM1_FLT0 pin
20227 * 0b1..CMP0 out
20228 */
20229#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
20230#define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
20231#define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
20232/*! FTM2FLT0 - FTM2 Fault 0 Select
20233 * 0b0..FTM2_FLT0 pin
20234 * 0b1..CMP0 out
20235 */
20236#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
20237#define SIM_SOPT4_FTM3FLT0_MASK (0x1000U)
20238#define SIM_SOPT4_FTM3FLT0_SHIFT (12U)
20239/*! FTM3FLT0 - FTM3 Fault 0 Select
20240 * 0b0..FTM3_FLT0 pin
20241 * 0b1..CMP0 out
20242 */
20243#define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
20244#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
20245#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
20246/*! FTM1CH0SRC - FTM1 channel 0 input capture source select
20247 * 0b00..FTM1_CH0 signal
20248 * 0b01..CMP0 output
20249 * 0b10..CMP1 output
20250 * 0b11..USB start of frame pulse
20251 */
20252#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
20253#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
20254#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
20255/*! FTM2CH0SRC - FTM2 channel 0 input capture source select
20256 * 0b00..FTM2_CH0 signal
20257 * 0b01..CMP0 output
20258 * 0b10..CMP1 output
20259 * 0b11..Reserved
20260 */
20261#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
20262#define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U)
20263#define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U)
20264/*! FTM2CH1SRC - FTM2 channel 1 input capture source select
20265 * 0b0..FTM2_CH1 signal
20266 * 0b1..Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1.
20267 */
20268#define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
20269#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
20270#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
20271/*! FTM0CLKSEL - FlexTimer 0 External Clock Pin Select
20272 * 0b0..FTM_CLK0 pin
20273 * 0b1..FTM_CLK1 pin
20274 */
20275#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
20276#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
20277#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
20278/*! FTM1CLKSEL - FTM1 External Clock Pin Select
20279 * 0b0..FTM_CLK0 pin
20280 * 0b1..FTM_CLK1 pin
20281 */
20282#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
20283#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
20284#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
20285/*! FTM2CLKSEL - FlexTimer 2 External Clock Pin Select
20286 * 0b0..FTM2 external clock driven by FTM_CLK0 pin.
20287 * 0b1..FTM2 external clock driven by FTM_CLK1 pin.
20288 */
20289#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
20290#define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U)
20291#define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U)
20292/*! FTM3CLKSEL - FlexTimer 3 External Clock Pin Select
20293 * 0b0..FTM3 external clock driven by FTM_CLK0 pin.
20294 * 0b1..FTM3 external clock driven by FTM_CLK1 pin.
20295 */
20296#define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
20297#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
20298#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
20299/*! FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select
20300 * 0b0..HSCMP0 output drives FTM0 hardware trigger 0
20301 * 0b1..FTM1 channel match drives FTM0 hardware trigger 0
20302 */
20303#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
20304#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
20305#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
20306/*! FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select
20307 * 0b0..PDB output trigger 1 drives FTM0 hardware trigger 1
20308 * 0b1..FTM2 channel match drives FTM0 hardware trigger 1
20309 */
20310#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
20311#define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U)
20312#define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U)
20313/*! FTM3TRG0SRC - FlexTimer 3 Hardware Trigger 0 Source Select
20314 * 0b0..Reserved
20315 * 0b1..FTM1 channel match drives FTM3 hardware trigger 0
20316 */
20317#define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
20318#define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U)
20319#define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U)
20320/*! FTM3TRG1SRC - FlexTimer 3 Hardware Trigger 1 Source Select
20321 * 0b0..Reserved
20322 * 0b1..FTM2 channel match drives FTM3 hardware trigger 1
20323 */
20324#define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
20325/*! @} */
20326
20327/*! @name SOPT5 - System Options Register 5 */
20328/*! @{ */
20329#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
20330#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
20331/*! UART0TXSRC - UART 0 transmit data source select
20332 * 0b00..UART0_TX pin
20333 * 0b01..UART0_TX pin modulated with FTM1 channel 0 output
20334 * 0b10..UART0_TX pin modulated with FTM2 channel 0 output
20335 * 0b11..Reserved
20336 */
20337#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
20338#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
20339#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
20340/*! UART0RXSRC - UART 0 receive data source select
20341 * 0b00..UART0_RX pin
20342 * 0b01..CMP0
20343 * 0b10..CMP1
20344 * 0b11..Reserved
20345 */
20346#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
20347#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
20348#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
20349/*! UART1TXSRC - UART 1 transmit data source select
20350 * 0b00..UART1_TX pin
20351 * 0b01..UART1_TX pin modulated with FTM1 channel 0 output
20352 * 0b10..UART1_TX pin modulated with FTM2 channel 0 output
20353 * 0b11..Reserved
20354 */
20355#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
20356#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
20357#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
20358/*! UART1RXSRC - UART 1 receive data source select
20359 * 0b00..UART1_RX pin
20360 * 0b01..CMP0
20361 * 0b10..CMP1
20362 * 0b11..Reserved
20363 */
20364#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
20365#define SIM_SOPT5_LPUART0TXSRC_MASK (0x30000U)
20366#define SIM_SOPT5_LPUART0TXSRC_SHIFT (16U)
20367/*! LPUART0TXSRC - LPUART0 transmit data source select
20368 * 0b00..LPUART0_TX pin
20369 * 0b01..LPUART0_TX pin modulated with TPM1 channel 0 output
20370 * 0b10..LPUART0_TX pin modulated with TPM2 channel 0 output
20371 * 0b11..Reserved
20372 */
20373#define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
20374#define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U)
20375#define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U)
20376/*! LPUART0RXSRC - LPUART0 receive data source select
20377 * 0b00..LPUART0_RX pin
20378 * 0b01..CMP0 output
20379 * 0b10..CMP1 output
20380 * 0b11..Reserved
20381 */
20382#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
20383/*! @} */
20384
20385/*! @name SOPT7 - System Options Register 7 */
20386/*! @{ */
20387#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
20388#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
20389/*! ADC0TRGSEL - ADC0 trigger select
20390 * 0b0000..PDB external trigger pin input (PDB0_EXTRG)
20391 * 0b0001..High speed comparator 0 output
20392 * 0b0010..High speed comparator 1 output
20393 * 0b0011..High speed comparator 2 output
20394 * 0b0100..PIT trigger 0
20395 * 0b0101..PIT trigger 1
20396 * 0b0110..PIT trigger 2
20397 * 0b0111..PIT trigger 3
20398 * 0b1000..FTM0 trigger
20399 * 0b1001..FTM1 trigger
20400 * 0b1010..FTM2 trigger
20401 * 0b1011..FTM3 trigger
20402 * 0b1100..RTC alarm
20403 * 0b1101..RTC seconds
20404 * 0b1110..Low-power timer (LPTMR) trigger
20405 * 0b1111..TPM1 channel 0 (A pretrigger) and channel 1 (B pretrigger)
20406 */
20407#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
20408#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
20409#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
20410/*! ADC0PRETRGSEL - ADC0 pretrigger select
20411 * 0b0..Pre-trigger A
20412 * 0b1..Pre-trigger B
20413 */
20414#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
20415#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
20416#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
20417/*! ADC0ALTTRGEN - ADC0 alternate trigger enable
20418 * 0b0..PDB trigger selected for ADC0.
20419 * 0b1..Alternate trigger selected for ADC0.
20420 */
20421#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
20422#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
20423#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
20424/*! ADC1TRGSEL - ADC1 trigger select
20425 * 0b0000..PDB external trigger pin input (PDB0_EXTRG)
20426 * 0b0001..High speed comparator 0 output
20427 * 0b0010..High speed comparator 1 output
20428 * 0b0011..High speed comparator 2 output
20429 * 0b0100..PIT trigger 0
20430 * 0b0101..PIT trigger 1
20431 * 0b0110..PIT trigger 2
20432 * 0b0111..PIT trigger 3
20433 * 0b1000..FTM0 trigger
20434 * 0b1001..FTM1 trigger
20435 * 0b1010..FTM2 trigger
20436 * 0b1011..FTM3 trigger
20437 * 0b1100..RTC alarm
20438 * 0b1101..RTC seconds
20439 * 0b1110..Low-power timer (LPTMR) trigger
20440 * 0b1111..TPM2 channel 0 (A pretrigger) and channel 1 (B pretrigger)
20441 */
20442#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
20443#define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
20444#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
20445/*! ADC1PRETRGSEL - ADC1 pre-trigger select
20446 * 0b0..Pre-trigger A selected for ADC1.
20447 * 0b1..Pre-trigger B selected for ADC1.
20448 */
20449#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
20450#define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
20451#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
20452/*! ADC1ALTTRGEN - ADC1 alternate trigger enable
20453 * 0b0..PDB trigger selected for ADC1
20454 * 0b1..Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
20455 */
20456#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
20457/*! @} */
20458
20459/*! @name SOPT8 - System Options Register 8 */
20460/*! @{ */
20461#define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U)
20462#define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U)
20463/*! FTM0SYNCBIT - FTM0 Hardware Trigger 0 Software Synchronization
20464 * 0b0..No effect
20465 * 0b1..Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert.
20466 */
20467#define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
20468#define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U)
20469#define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U)
20470/*! FTM1SYNCBIT - FTM1 Hardware Trigger 0 Software Synchronization
20471 * 0b0..No effect.
20472 * 0b1..Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert.
20473 */
20474#define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
20475#define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U)
20476#define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U)
20477/*! FTM2SYNCBIT - FTM2 Hardware Trigger 0 Software Synchronization
20478 * 0b0..No effect.
20479 * 0b1..Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert.
20480 */
20481#define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
20482#define SIM_SOPT8_FTM3SYNCBIT_MASK (0x8U)
20483#define SIM_SOPT8_FTM3SYNCBIT_SHIFT (3U)
20484/*! FTM3SYNCBIT - FTM3 Hardware Trigger 0 Software Synchronization
20485 * 0b0..No effect.
20486 * 0b1..Write 1 to assert the TRIG0 input to FTM3, software must clear this bit to allow other trigger sources to assert.
20487 */
20488#define SIM_SOPT8_FTM3SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
20489#define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U)
20490#define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U)
20491/*! FTM0OCH0SRC - FTM0 channel 0 output source
20492 * 0b0..FTM0_CH0 pin is output of FTM0 channel 0 output
20493 * 0b1..FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output
20494 */
20495#define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
20496#define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U)
20497#define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U)
20498/*! FTM0OCH1SRC - FTM0 channel 1 output source
20499 * 0b0..FTM0_CH1 pin is output of FTM0 channel 1 output
20500 * 0b1..FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output
20501 */
20502#define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
20503#define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U)
20504#define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U)
20505/*! FTM0OCH2SRC - FTM0 channel 2 output source
20506 * 0b0..FTM0_CH2 pin is output of FTM0 channel 2 output
20507 * 0b1..FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output
20508 */
20509#define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
20510#define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U)
20511#define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U)
20512/*! FTM0OCH3SRC - FTM0 channel 3 output source
20513 * 0b0..FTM0_CH3 pin is output of FTM0 channel 3 output
20514 * 0b1..FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output
20515 */
20516#define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
20517#define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U)
20518#define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U)
20519/*! FTM0OCH4SRC - FTM0 channel 4 output source
20520 * 0b0..FTM0_CH4 pin is output of FTM0 channel 4 output
20521 * 0b1..FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output
20522 */
20523#define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
20524#define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U)
20525#define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U)
20526/*! FTM0OCH5SRC - FTM0 channel 5 output source
20527 * 0b0..FTM0_CH5 pin is output of FTM0 channel 5 output
20528 * 0b1..FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output
20529 */
20530#define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
20531#define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U)
20532#define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U)
20533/*! FTM0OCH6SRC - FTM0 channel 6 output source
20534 * 0b0..FTM0_CH6 pin is output of FTM0 channel 6 output
20535 * 0b1..FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output
20536 */
20537#define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
20538#define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U)
20539#define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U)
20540/*! FTM0OCH7SRC - FTM0 channel 7 output source
20541 * 0b0..FTM0_CH7 pin is output of FTM0 channel 7 output
20542 * 0b1..FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output
20543 */
20544#define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
20545#define SIM_SOPT8_FTM3OCH0SRC_MASK (0x1000000U)
20546#define SIM_SOPT8_FTM3OCH0SRC_SHIFT (24U)
20547/*! FTM3OCH0SRC - FTM3 channel 0 output source
20548 * 0b0..FTM3_CH0 pin is output of FTM3 channel 0 output
20549 * 0b1..FTM3_CH0 pin is output of FTM3 channel 0 output modulated by FTM2 channel 1 output.
20550 */
20551#define SIM_SOPT8_FTM3OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
20552#define SIM_SOPT8_FTM3OCH1SRC_MASK (0x2000000U)
20553#define SIM_SOPT8_FTM3OCH1SRC_SHIFT (25U)
20554/*! FTM3OCH1SRC - FTM3 channel 1 output source
20555 * 0b0..FTM3_CH1 pin is output of FTM3 channel 1 output
20556 * 0b1..FTM3_CH1 pin is output of FTM3 channel 1 output modulated by FTM2 channel 1 output.
20557 */
20558#define SIM_SOPT8_FTM3OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
20559#define SIM_SOPT8_FTM3OCH2SRC_MASK (0x4000000U)
20560#define SIM_SOPT8_FTM3OCH2SRC_SHIFT (26U)
20561/*! FTM3OCH2SRC - FTM3 channel 2 output source
20562 * 0b0..FTM3_CH2 pin is output of FTM3 channel 2 output
20563 * 0b1..FTM3_CH2 pin is output of FTM3 channel 2 output modulated by FTM2 channel 1 output.
20564 */
20565#define SIM_SOPT8_FTM3OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
20566#define SIM_SOPT8_FTM3OCH3SRC_MASK (0x8000000U)
20567#define SIM_SOPT8_FTM3OCH3SRC_SHIFT (27U)
20568/*! FTM3OCH3SRC - FTM3 channel 3 output source
20569 * 0b0..FTM3_CH3 pin is output of FTM3 channel 3 output
20570 * 0b1..FTM3_CH3 pin is output of FTM3 channel 3 output modulated by FTM2 channel 1 output.
20571 */
20572#define SIM_SOPT8_FTM3OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
20573#define SIM_SOPT8_FTM3OCH4SRC_MASK (0x10000000U)
20574#define SIM_SOPT8_FTM3OCH4SRC_SHIFT (28U)
20575/*! FTM3OCH4SRC - FTM3 channel 4 output source
20576 * 0b0..FTM3_CH4 pin is output of FTM3 channel 4 output
20577 * 0b1..FTM3_CH4 pin is output of FTM3 channel 4 output modulated by FTM2 channel 1 output.
20578 */
20579#define SIM_SOPT8_FTM3OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
20580#define SIM_SOPT8_FTM3OCH5SRC_MASK (0x20000000U)
20581#define SIM_SOPT8_FTM3OCH5SRC_SHIFT (29U)
20582/*! FTM3OCH5SRC - FTM3 channel 5 output source
20583 * 0b0..FTM3_CH5 pin is output of FTM3 channel 5 output
20584 * 0b1..FTM3_CH5 pin is output of FTM3 channel 5 output modulated by FTM2 channel 1 output.
20585 */
20586#define SIM_SOPT8_FTM3OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
20587#define SIM_SOPT8_FTM3OCH6SRC_MASK (0x40000000U)
20588#define SIM_SOPT8_FTM3OCH6SRC_SHIFT (30U)
20589/*! FTM3OCH6SRC - FTM3 channel 6 output source
20590 * 0b0..FTM3_CH6 pin is output of FTM3 channel 6 output
20591 * 0b1..FTM3_CH6 pin is output of FTM3 channel 6 output modulated by FTM2 channel 1 output.
20592 */
20593#define SIM_SOPT8_FTM3OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
20594#define SIM_SOPT8_FTM3OCH7SRC_MASK (0x80000000U)
20595#define SIM_SOPT8_FTM3OCH7SRC_SHIFT (31U)
20596/*! FTM3OCH7SRC - FTM3 channel 7 output source
20597 * 0b0..FTM3_CH7 pin is output of FTM3 channel 7 output
20598 * 0b1..FTM3_CH7 pin is output of FTM3 channel 7 output modulated by FTM2 channel 1 output.
20599 */
20600#define SIM_SOPT8_FTM3OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
20601/*! @} */
20602
20603/*! @name SOPT9 - System Options Register 9 */
20604/*! @{ */
20605#define SIM_SOPT9_TPM1CH0SRC_MASK (0xC0000U)
20606#define SIM_SOPT9_TPM1CH0SRC_SHIFT (18U)
20607/*! TPM1CH0SRC - TPM1 channel 0 input capture source select
20608 * 0b00..TPM1_CH0 signal
20609 * 0b01..CMP0 output
20610 * 0b10..CMP1 output
20611 * 0b11..Reserved
20612 */
20613#define SIM_SOPT9_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)
20614#define SIM_SOPT9_TPM2CH0SRC_MASK (0x300000U)
20615#define SIM_SOPT9_TPM2CH0SRC_SHIFT (20U)
20616/*! TPM2CH0SRC - TPM2 channel 0 input capture source select
20617 * 0b00..TPM2_CH0 signal
20618 * 0b01..CMP0 output
20619 * 0b10..CMP1 output
20620 * 0b11..Reserved
20621 */
20622#define SIM_SOPT9_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)
20623#define SIM_SOPT9_TPM1CLKSEL_MASK (0x2000000U)
20624#define SIM_SOPT9_TPM1CLKSEL_SHIFT (25U)
20625/*! TPM1CLKSEL - TPM1 External Clock Pin Select
20626 * 0b0..TPM_CLKIN0 pin
20627 * 0b1..TPM_CLKIN1 pin
20628 */
20629#define SIM_SOPT9_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)
20630#define SIM_SOPT9_TPM2CLKSEL_MASK (0x4000000U)
20631#define SIM_SOPT9_TPM2CLKSEL_SHIFT (26U)
20632/*! TPM2CLKSEL - TPM2 External Clock Pin Select
20633 * 0b0..TPM_CLKIN0 pin
20634 * 0b1..TPM_CLKIN1 pin
20635 */
20636#define SIM_SOPT9_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)
20637/*! @} */
20638
20639/*! @name SDID - System Device Identification Register */
20640/*! @{ */
20641#define SIM_SDID_PINID_MASK (0xFU)
20642#define SIM_SDID_PINID_SHIFT (0U)
20643/*! PINID - Pincount identification
20644 * 0b0000..Reserved
20645 * 0b0001..Reserved
20646 * 0b0010..32-pin
20647 * 0b0011..Reserved
20648 * 0b0100..48-pin
20649 * 0b0101..64-pin
20650 * 0b0110..80-pin
20651 * 0b0111..81-pin or 121-pin
20652 * 0b1000..100-pin
20653 * 0b1001..121-pin
20654 * 0b1010..144-pin
20655 * 0b1011..Custom pinout (WLCSP)
20656 * 0b1100..169-pin
20657 * 0b1101..Reserved
20658 * 0b1110..256-pin
20659 * 0b1111..Reserved
20660 */
20661#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
20662#define SIM_SDID_FAMID_MASK (0x70U)
20663#define SIM_SDID_FAMID_SHIFT (4U)
20664/*! FAMID - Kinetis family identification
20665 * 0b000..K1x Family (without tamper)
20666 * 0b001..K2x Family (without tamper)
20667 * 0b010..K3x Family or K1x/K6x Family (with tamper)
20668 * 0b011..K4x Family or K2x Family (with tamper)
20669 * 0b100..K6x Family (without tamper)
20670 * 0b101..K7x Family
20671 * 0b110..Reserved
20672 * 0b111..Reserved
20673 */
20674#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
20675#define SIM_SDID_DIEID_MASK (0xF80U)
20676#define SIM_SDID_DIEID_SHIFT (7U)
20677#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
20678#define SIM_SDID_REVID_MASK (0xF000U)
20679#define SIM_SDID_REVID_SHIFT (12U)
20680#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
20681#define SIM_SDID_SERIESID_MASK (0xF00000U)
20682#define SIM_SDID_SERIESID_SHIFT (20U)
20683/*! SERIESID - Kinetis Series ID
20684 * 0b0000..Kinetis K series
20685 * 0b0001..Kinetis L series
20686 * 0b0101..Kinetis W series
20687 * 0b0110..Kinetis V series
20688 */
20689#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
20690#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
20691#define SIM_SDID_SUBFAMID_SHIFT (24U)
20692/*! SUBFAMID - Kinetis Sub-Family ID
20693 * 0b0000..Kx0 Subfamily
20694 * 0b0001..Kx1 Subfamily (tamper detect)
20695 * 0b0010..Kx2 Subfamily
20696 * 0b0011..Kx3 Subfamily (tamper detect)
20697 * 0b0100..Kx4 Subfamily
20698 * 0b0101..Kx5 Subfamily (tamper detect)
20699 * 0b0110..Kx6 Subfamily
20700 */
20701#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
20702#define SIM_SDID_FAMILYID_MASK (0xF0000000U)
20703#define SIM_SDID_FAMILYID_SHIFT (28U)
20704/*! FAMILYID - Kinetis Family ID
20705 * 0b0000..K0x Family
20706 * 0b0001..K1x Family
20707 * 0b0010..K2x Family
20708 * 0b0011..K3x Family
20709 * 0b0100..K4x Family
20710 * 0b0110..K6x Family
20711 * 0b0111..K7x Family
20712 * 0b1000..K8x Family
20713 */
20714#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
20715/*! @} */
20716
20717/*! @name SCGC1 - System Clock Gating Control Register 1 */
20718/*! @{ */
20719#define SIM_SCGC1_I2C2_MASK (0x40U)
20720#define SIM_SCGC1_I2C2_SHIFT (6U)
20721/*! I2C2 - I2C2 Clock Gate Control
20722 * 0b0..Clock disabled
20723 * 0b1..Clock enabled
20724 */
20725#define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
20726#define SIM_SCGC1_I2C3_MASK (0x80U)
20727#define SIM_SCGC1_I2C3_SHIFT (7U)
20728/*! I2C3 - I2C3 Clock Gate Control
20729 * 0b0..Clock disabled
20730 * 0b1..Clock enabled
20731 */
20732#define SIM_SCGC1_I2C3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)
20733#define SIM_SCGC1_UART4_MASK (0x400U)
20734#define SIM_SCGC1_UART4_SHIFT (10U)
20735/*! UART4 - UART4 Clock Gate Control
20736 * 0b0..Clock disabled
20737 * 0b1..Clock enabled
20738 */
20739#define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
20740/*! @} */
20741
20742/*! @name SCGC2 - System Clock Gating Control Register 2 */
20743/*! @{ */
20744#define SIM_SCGC2_LPUART0_MASK (0x10U)
20745#define SIM_SCGC2_LPUART0_SHIFT (4U)
20746/*! LPUART0 - LPUART0 Clock Gate Control
20747 * 0b0..Clock disabled
20748 * 0b1..Clock enabled
20749 */
20750#define SIM_SCGC2_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)
20751#define SIM_SCGC2_TPM1_MASK (0x200U)
20752#define SIM_SCGC2_TPM1_SHIFT (9U)
20753/*! TPM1 - TPM1 Clock Gate Control
20754 * 0b0..Clock disabled
20755 * 0b1..Clock enabled
20756 */
20757#define SIM_SCGC2_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)
20758#define SIM_SCGC2_TPM2_MASK (0x400U)
20759#define SIM_SCGC2_TPM2_SHIFT (10U)
20760/*! TPM2 - TPM2 Clock Gate Control
20761 * 0b0..Clock disabled
20762 * 0b1..Clock enabled
20763 */
20764#define SIM_SCGC2_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)
20765#define SIM_SCGC2_DAC0_MASK (0x1000U)
20766#define SIM_SCGC2_DAC0_SHIFT (12U)
20767/*! DAC0 - DAC0 Clock Gate Control
20768 * 0b0..Clock disabled
20769 * 0b1..Clock enabled
20770 */
20771#define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
20772#define SIM_SCGC2_DAC1_MASK (0x2000U)
20773#define SIM_SCGC2_DAC1_SHIFT (13U)
20774/*! DAC1 - DAC1 Clock Gate Control
20775 * 0b0..Clock disabled
20776 * 0b1..Clock enabled
20777 */
20778#define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
20779/*! @} */
20780
20781/*! @name SCGC3 - System Clock Gating Control Register 3 */
20782/*! @{ */
20783#define SIM_SCGC3_RNGA_MASK (0x1U)
20784#define SIM_SCGC3_RNGA_SHIFT (0U)
20785/*! RNGA - RNGA Clock Gate Control
20786 * 0b0..Clock disabled
20787 * 0b1..Clock enabled
20788 */
20789#define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
20790#define SIM_SCGC3_USBHS_MASK (0x2U)
20791#define SIM_SCGC3_USBHS_SHIFT (1U)
20792/*! USBHS - USBHS Clock Gate Control
20793 * 0b0..Clock disabled
20794 * 0b1..Clock enabled
20795 */
20796#define SIM_SCGC3_USBHS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHS_SHIFT)) & SIM_SCGC3_USBHS_MASK)
20797#define SIM_SCGC3_USBHSPHY_MASK (0x4U)
20798#define SIM_SCGC3_USBHSPHY_SHIFT (2U)
20799/*! USBHSPHY - USBHS PHY Clock Gate Control
20800 * 0b0..Clock disabled
20801 * 0b1..Clock enabled
20802 */
20803#define SIM_SCGC3_USBHSPHY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSPHY_SHIFT)) & SIM_SCGC3_USBHSPHY_MASK)
20804#define SIM_SCGC3_USBHSDCD_MASK (0x8U)
20805#define SIM_SCGC3_USBHSDCD_SHIFT (3U)
20806/*! USBHSDCD - USBHS DCD Clock Gate Control
20807 * 0b0..Clock disabled
20808 * 0b1..Clock enabled
20809 */
20810#define SIM_SCGC3_USBHSDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSDCD_SHIFT)) & SIM_SCGC3_USBHSDCD_MASK)
20811#define SIM_SCGC3_FLEXCAN1_MASK (0x10U)
20812#define SIM_SCGC3_FLEXCAN1_SHIFT (4U)
20813/*! FLEXCAN1 - FlexCAN1 Clock Gate Control
20814 * 0b0..Clock disabled
20815 * 0b1..Clock enabled
20816 */
20817#define SIM_SCGC3_FLEXCAN1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)
20818#define SIM_SCGC3_SPI2_MASK (0x1000U)
20819#define SIM_SCGC3_SPI2_SHIFT (12U)
20820/*! SPI2 - SPI2 Clock Gate Control
20821 * 0b0..Clock disabled
20822 * 0b1..Clock enabled
20823 */
20824#define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
20825#define SIM_SCGC3_SDHC_MASK (0x20000U)
20826#define SIM_SCGC3_SDHC_SHIFT (17U)
20827/*! SDHC - SDHC Clock Gate Control
20828 * 0b0..Clock disabled
20829 * 0b1..Clock enabled
20830 */
20831#define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
20832#define SIM_SCGC3_FTM2_MASK (0x1000000U)
20833#define SIM_SCGC3_FTM2_SHIFT (24U)
20834/*! FTM2 - FTM2 Clock Gate Control
20835 * 0b0..Clock disabled
20836 * 0b1..Clock enabled
20837 */
20838#define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
20839#define SIM_SCGC3_FTM3_MASK (0x2000000U)
20840#define SIM_SCGC3_FTM3_SHIFT (25U)
20841/*! FTM3 - FTM3 Clock Gate Control
20842 * 0b0..Clock disabled
20843 * 0b1..Clock enabled
20844 */
20845#define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
20846#define SIM_SCGC3_ADC1_MASK (0x8000000U)
20847#define SIM_SCGC3_ADC1_SHIFT (27U)
20848/*! ADC1 - ADC1 Clock Gate Control
20849 * 0b0..Clock disabled
20850 * 0b1..Clock enabled
20851 */
20852#define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
20853/*! @} */
20854
20855/*! @name SCGC4 - System Clock Gating Control Register 4 */
20856/*! @{ */
20857#define SIM_SCGC4_EWM_MASK (0x2U)
20858#define SIM_SCGC4_EWM_SHIFT (1U)
20859/*! EWM - EWM Clock Gate Control
20860 * 0b0..Clock disabled
20861 * 0b1..Clock enabled
20862 */
20863#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
20864#define SIM_SCGC4_CMT_MASK (0x4U)
20865#define SIM_SCGC4_CMT_SHIFT (2U)
20866/*! CMT - CMT Clock Gate Control
20867 * 0b0..Clock disabled
20868 * 0b1..Clock enabled
20869 */
20870#define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
20871#define SIM_SCGC4_I2C0_MASK (0x40U)
20872#define SIM_SCGC4_I2C0_SHIFT (6U)
20873/*! I2C0 - I2C0 Clock Gate Control
20874 * 0b0..Clock disabled
20875 * 0b1..Clock enabled
20876 */
20877#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
20878#define SIM_SCGC4_I2C1_MASK (0x80U)
20879#define SIM_SCGC4_I2C1_SHIFT (7U)
20880/*! I2C1 - I2C1 Clock Gate Control
20881 * 0b0..Clock disabled
20882 * 0b1..Clock enabled
20883 */
20884#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
20885#define SIM_SCGC4_UART0_MASK (0x400U)
20886#define SIM_SCGC4_UART0_SHIFT (10U)
20887/*! UART0 - UART0 Clock Gate Control
20888 * 0b0..Clock disabled
20889 * 0b1..Clock enabled
20890 */
20891#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
20892#define SIM_SCGC4_UART1_MASK (0x800U)
20893#define SIM_SCGC4_UART1_SHIFT (11U)
20894/*! UART1 - UART1 Clock Gate Control
20895 * 0b0..Clock disabled
20896 * 0b1..Clock enabled
20897 */
20898#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
20899#define SIM_SCGC4_UART2_MASK (0x1000U)
20900#define SIM_SCGC4_UART2_SHIFT (12U)
20901/*! UART2 - UART2 Clock Gate Control
20902 * 0b0..Clock disabled
20903 * 0b1..Clock enabled
20904 */
20905#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
20906#define SIM_SCGC4_UART3_MASK (0x2000U)
20907#define SIM_SCGC4_UART3_SHIFT (13U)
20908/*! UART3 - UART3 Clock Gate Control
20909 * 0b0..Clock disabled
20910 * 0b1..Clock enabled
20911 */
20912#define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
20913#define SIM_SCGC4_USBOTG_MASK (0x40000U)
20914#define SIM_SCGC4_USBOTG_SHIFT (18U)
20915/*! USBOTG - USB Clock Gate Control
20916 * 0b0..Clock disabled
20917 * 0b1..Clock enabled
20918 */
20919#define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
20920#define SIM_SCGC4_CMP_MASK (0x80000U)
20921#define SIM_SCGC4_CMP_SHIFT (19U)
20922/*! CMP - Comparator Clock Gate Control
20923 * 0b0..Clock disabled
20924 * 0b1..Clock enabled
20925 */
20926#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
20927#define SIM_SCGC4_VREF_MASK (0x100000U)
20928#define SIM_SCGC4_VREF_SHIFT (20U)
20929/*! VREF - VREF Clock Gate Control
20930 * 0b0..Clock disabled
20931 * 0b1..Clock enabled
20932 */
20933#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
20934/*! @} */
20935
20936/*! @name SCGC5 - System Clock Gating Control Register 5 */
20937/*! @{ */
20938#define SIM_SCGC5_LPTMR_MASK (0x1U)
20939#define SIM_SCGC5_LPTMR_SHIFT (0U)
20940/*! LPTMR - Low Power Timer Access Control
20941 * 0b0..Access disabled
20942 * 0b1..Access enabled
20943 */
20944#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
20945#define SIM_SCGC5_TSI_MASK (0x20U)
20946#define SIM_SCGC5_TSI_SHIFT (5U)
20947/*! TSI - TSI Clock Gate Control
20948 * 0b0..Clock disabled
20949 * 0b1..Clock enabled
20950 */
20951#define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
20952#define SIM_SCGC5_PORTA_MASK (0x200U)
20953#define SIM_SCGC5_PORTA_SHIFT (9U)
20954/*! PORTA - Port A Clock Gate Control
20955 * 0b0..Clock disabled
20956 * 0b1..Clock enabled
20957 */
20958#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
20959#define SIM_SCGC5_PORTB_MASK (0x400U)
20960#define SIM_SCGC5_PORTB_SHIFT (10U)
20961/*! PORTB - Port B Clock Gate Control
20962 * 0b0..Clock disabled
20963 * 0b1..Clock enabled
20964 */
20965#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
20966#define SIM_SCGC5_PORTC_MASK (0x800U)
20967#define SIM_SCGC5_PORTC_SHIFT (11U)
20968/*! PORTC - Port C Clock Gate Control
20969 * 0b0..Clock disabled
20970 * 0b1..Clock enabled
20971 */
20972#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
20973#define SIM_SCGC5_PORTD_MASK (0x1000U)
20974#define SIM_SCGC5_PORTD_SHIFT (12U)
20975/*! PORTD - Port D Clock Gate Control
20976 * 0b0..Clock disabled
20977 * 0b1..Clock enabled
20978 */
20979#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
20980#define SIM_SCGC5_PORTE_MASK (0x2000U)
20981#define SIM_SCGC5_PORTE_SHIFT (13U)
20982/*! PORTE - Port E Clock Gate Control
20983 * 0b0..Clock disabled
20984 * 0b1..Clock enabled
20985 */
20986#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
20987/*! @} */
20988
20989/*! @name SCGC6 - System Clock Gating Control Register 6 */
20990/*! @{ */
20991#define SIM_SCGC6_FTF_MASK (0x1U)
20992#define SIM_SCGC6_FTF_SHIFT (0U)
20993/*! FTF - Flash Memory Clock Gate Control
20994 * 0b0..Clock disabled
20995 * 0b1..Clock enabled
20996 */
20997#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
20998#define SIM_SCGC6_DMAMUX_MASK (0x2U)
20999#define SIM_SCGC6_DMAMUX_SHIFT (1U)
21000/*! DMAMUX - DMA Mux Clock Gate Control
21001 * 0b0..Clock disabled
21002 * 0b1..Clock enabled
21003 */
21004#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
21005#define SIM_SCGC6_FLEXCAN0_MASK (0x10U)
21006#define SIM_SCGC6_FLEXCAN0_SHIFT (4U)
21007/*! FLEXCAN0 - FlexCAN0 Clock Gate Control
21008 * 0b0..Clock disabled
21009 * 0b1..Clock enabled
21010 */
21011#define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
21012#define SIM_SCGC6_RNGA_MASK (0x200U)
21013#define SIM_SCGC6_RNGA_SHIFT (9U)
21014#define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
21015#define SIM_SCGC6_SPI0_MASK (0x1000U)
21016#define SIM_SCGC6_SPI0_SHIFT (12U)
21017/*! SPI0 - SPI0 Clock Gate Control
21018 * 0b0..Clock disabled
21019 * 0b1..Clock enabled
21020 */
21021#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
21022#define SIM_SCGC6_SPI1_MASK (0x2000U)
21023#define SIM_SCGC6_SPI1_SHIFT (13U)
21024/*! SPI1 - SPI1 Clock Gate Control
21025 * 0b0..Clock disabled
21026 * 0b1..Clock enabled
21027 */
21028#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
21029#define SIM_SCGC6_I2S_MASK (0x8000U)
21030#define SIM_SCGC6_I2S_SHIFT (15U)
21031/*! I2S - I2S Clock Gate Control
21032 * 0b0..Clock disabled
21033 * 0b1..Clock enabled
21034 */
21035#define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
21036#define SIM_SCGC6_CRC_MASK (0x40000U)
21037#define SIM_SCGC6_CRC_SHIFT (18U)
21038/*! CRC - CRC Clock Gate Control
21039 * 0b0..Clock disabled
21040 * 0b1..Clock enabled
21041 */
21042#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
21043#define SIM_SCGC6_USBDCD_MASK (0x200000U)
21044#define SIM_SCGC6_USBDCD_SHIFT (21U)
21045/*! USBDCD - USB DCD Clock Gate Control
21046 * 0b0..Clock disabled
21047 * 0b1..Clock enabled
21048 */
21049#define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
21050#define SIM_SCGC6_PDB_MASK (0x400000U)
21051#define SIM_SCGC6_PDB_SHIFT (22U)
21052/*! PDB - PDB Clock Gate Control
21053 * 0b0..Clock disabled
21054 * 0b1..Clock enabled
21055 */
21056#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
21057#define SIM_SCGC6_PIT_MASK (0x800000U)
21058#define SIM_SCGC6_PIT_SHIFT (23U)
21059/*! PIT - PIT Clock Gate Control
21060 * 0b0..Clock disabled
21061 * 0b1..Clock enabled
21062 */
21063#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
21064#define SIM_SCGC6_FTM0_MASK (0x1000000U)
21065#define SIM_SCGC6_FTM0_SHIFT (24U)
21066/*! FTM0 - FTM0 Clock Gate Control
21067 * 0b0..Clock disabled
21068 * 0b1..Clock enabled
21069 */
21070#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
21071#define SIM_SCGC6_FTM1_MASK (0x2000000U)
21072#define SIM_SCGC6_FTM1_SHIFT (25U)
21073/*! FTM1 - FTM1 Clock Gate Control
21074 * 0b0..Clock disabled
21075 * 0b1..Clock enabled
21076 */
21077#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
21078#define SIM_SCGC6_FTM2_MASK (0x4000000U)
21079#define SIM_SCGC6_FTM2_SHIFT (26U)
21080/*! FTM2 - FTM2 Clock Gate Control
21081 * 0b0..Clock disabled
21082 * 0b1..Clock enabled
21083 */
21084#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
21085#define SIM_SCGC6_ADC0_MASK (0x8000000U)
21086#define SIM_SCGC6_ADC0_SHIFT (27U)
21087/*! ADC0 - ADC0 Clock Gate Control
21088 * 0b0..Clock disabled
21089 * 0b1..Clock enabled
21090 */
21091#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
21092#define SIM_SCGC6_RTC_MASK (0x20000000U)
21093#define SIM_SCGC6_RTC_SHIFT (29U)
21094/*! RTC - RTC Access Control
21095 * 0b0..Access and interrupts disabled
21096 * 0b1..Access and interrupts enabled
21097 */
21098#define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
21099#define SIM_SCGC6_DAC0_MASK (0x80000000U)
21100#define SIM_SCGC6_DAC0_SHIFT (31U)
21101/*! DAC0 - DAC0 Clock Gate Control
21102 * 0b0..Clock disabled
21103 * 0b1..Clock enabled
21104 */
21105#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
21106/*! @} */
21107
21108/*! @name SCGC7 - System Clock Gating Control Register 7 */
21109/*! @{ */
21110#define SIM_SCGC7_FLEXBUS_MASK (0x1U)
21111#define SIM_SCGC7_FLEXBUS_SHIFT (0U)
21112/*! FLEXBUS - FlexBus Clock Gate Control
21113 * 0b0..Clock disabled
21114 * 0b1..Clock enabled
21115 */
21116#define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
21117#define SIM_SCGC7_DMA_MASK (0x2U)
21118#define SIM_SCGC7_DMA_SHIFT (1U)
21119/*! DMA - DMA Clock Gate Control
21120 * 0b0..Clock disabled
21121 * 0b1..Clock enabled
21122 */
21123#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
21124#define SIM_SCGC7_MPU_MASK (0x4U)
21125#define SIM_SCGC7_MPU_SHIFT (2U)
21126/*! MPU - MPU Clock Gate Control
21127 * 0b0..Clock disabled
21128 * 0b1..Clock enabled
21129 */
21130#define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
21131#define SIM_SCGC7_SDRAMC_MASK (0x8U)
21132#define SIM_SCGC7_SDRAMC_SHIFT (3U)
21133/*! SDRAMC - SDRAMC Clock Gate Control
21134 * 0b0..Clock disabled
21135 * 0b1..Clock enabled
21136 */
21137#define SIM_SCGC7_SDRAMC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)
21138/*! @} */
21139
21140/*! @name CLKDIV1 - System Clock Divider Register 1 */
21141/*! @{ */
21142#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
21143#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
21144/*! OUTDIV4 - Clock 4 output divider value
21145 * 0b0000..Divide-by-1.
21146 * 0b0001..Divide-by-2.
21147 * 0b0010..Divide-by-3.
21148 * 0b0011..Divide-by-4.
21149 * 0b0100..Divide-by-5.
21150 * 0b0101..Divide-by-6.
21151 * 0b0110..Divide-by-7.
21152 * 0b0111..Divide-by-8.
21153 * 0b1000..Divide-by-9.
21154 * 0b1001..Divide-by-10.
21155 * 0b1010..Divide-by-11.
21156 * 0b1011..Divide-by-12.
21157 * 0b1100..Divide-by-13.
21158 * 0b1101..Divide-by-14.
21159 * 0b1110..Divide-by-15.
21160 * 0b1111..Divide-by-16.
21161 */
21162#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
21163#define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
21164#define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
21165/*! OUTDIV3 - Clock 3 output divider value
21166 * 0b0000..Divide-by-1.
21167 * 0b0001..Divide-by-2.
21168 * 0b0010..Divide-by-3.
21169 * 0b0011..Divide-by-4.
21170 * 0b0100..Divide-by-5.
21171 * 0b0101..Divide-by-6.
21172 * 0b0110..Divide-by-7.
21173 * 0b0111..Divide-by-8.
21174 * 0b1000..Divide-by-9.
21175 * 0b1001..Divide-by-10.
21176 * 0b1010..Divide-by-11.
21177 * 0b1011..Divide-by-12.
21178 * 0b1100..Divide-by-13.
21179 * 0b1101..Divide-by-14.
21180 * 0b1110..Divide-by-15.
21181 * 0b1111..Divide-by-16.
21182 */
21183#define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
21184#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
21185#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
21186/*! OUTDIV2 - Clock 2 output divider value
21187 * 0b0000..Divide-by-1.
21188 * 0b0001..Divide-by-2.
21189 * 0b0010..Divide-by-3.
21190 * 0b0011..Divide-by-4.
21191 * 0b0100..Divide-by-5.
21192 * 0b0101..Divide-by-6.
21193 * 0b0110..Divide-by-7.
21194 * 0b0111..Divide-by-8.
21195 * 0b1000..Divide-by-9.
21196 * 0b1001..Divide-by-10.
21197 * 0b1010..Divide-by-11.
21198 * 0b1011..Divide-by-12.
21199 * 0b1100..Divide-by-13.
21200 * 0b1101..Divide-by-14.
21201 * 0b1110..Divide-by-15.
21202 * 0b1111..Divide-by-16.
21203 */
21204#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
21205#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
21206#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
21207/*! OUTDIV1 - Clock 1 output divider value
21208 * 0b0000..Divide-by-1.
21209 * 0b0001..Divide-by-2.
21210 * 0b0010..Divide-by-3.
21211 * 0b0011..Divide-by-4.
21212 * 0b0100..Divide-by-5.
21213 * 0b0101..Divide-by-6.
21214 * 0b0110..Divide-by-7.
21215 * 0b0111..Divide-by-8.
21216 * 0b1000..Divide-by-9.
21217 * 0b1001..Divide-by-10.
21218 * 0b1010..Divide-by-11.
21219 * 0b1011..Divide-by-12.
21220 * 0b1100..Divide-by-13.
21221 * 0b1101..Divide-by-14.
21222 * 0b1110..Divide-by-15.
21223 * 0b1111..Divide-by-16.
21224 */
21225#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
21226/*! @} */
21227
21228/*! @name CLKDIV2 - System Clock Divider Register 2 */
21229/*! @{ */
21230#define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
21231#define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
21232#define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
21233#define SIM_CLKDIV2_USBDIV_MASK (0xEU)
21234#define SIM_CLKDIV2_USBDIV_SHIFT (1U)
21235#define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
21236/*! @} */
21237
21238/*! @name FCFG1 - Flash Configuration Register 1 */
21239/*! @{ */
21240#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
21241#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
21242/*! FLASHDIS - Flash Disable
21243 * 0b0..Flash is enabled
21244 * 0b1..Flash is disabled
21245 */
21246#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
21247#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
21248#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
21249/*! FLASHDOZE - Flash Doze
21250 * 0b0..Flash remains enabled during Wait mode
21251 * 0b1..Flash is disabled for the duration of Wait mode
21252 */
21253#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
21254#define SIM_FCFG1_DEPART_MASK (0xF00U)
21255#define SIM_FCFG1_DEPART_SHIFT (8U)
21256#define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
21257#define SIM_FCFG1_EESIZE_MASK (0xF0000U)
21258#define SIM_FCFG1_EESIZE_SHIFT (16U)
21259/*! EESIZE - EEPROM size
21260 * 0b0000..16 KB
21261 * 0b0001..8 KB
21262 * 0b0010..4 KB
21263 * 0b0011..2 KB
21264 * 0b0100..1 KB
21265 * 0b0101..512 Bytes
21266 * 0b0110..256 Bytes
21267 * 0b0111..128 Bytes
21268 * 0b1000..64 Bytes
21269 * 0b1001..32 Bytes
21270 * 0b1111..0 Bytes
21271 */
21272#define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
21273#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
21274#define SIM_FCFG1_PFSIZE_SHIFT (24U)
21275/*! PFSIZE - Program flash size
21276 * 0b0011..32 KB of program flash memory
21277 * 0b0101..64 KB of program flash memory
21278 * 0b0111..128 KB of program flash memory
21279 * 0b1001..256 KB of program flash memory
21280 * 0b1011..512 KB of program flash memory
21281 * 0b1101..1024 KB of program flash memory
21282 * 0b1111..2048 KB of program flash memory
21283 */
21284#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
21285#define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
21286#define SIM_FCFG1_NVMSIZE_SHIFT (28U)
21287/*! NVMSIZE - FlexNVM size
21288 * 0b0000..0 KB of FlexNVM
21289 * 0b0011..32 KB of FlexNVM
21290 * 0b0101..64 KB of FlexNVM
21291 * 0b0111..128 KB of FlexNVM
21292 * 0b1001..256 KB of FlexNVM
21293 * 0b1011..512 KB of FlexNVM
21294 * 0b1111..256 KB of FlexNVM
21295 */
21296#define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
21297/*! @} */
21298
21299/*! @name FCFG2 - Flash Configuration Register 2 */
21300/*! @{ */
21301#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
21302#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
21303#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
21304#define SIM_FCFG2_PFLSH_MASK (0x800000U)
21305#define SIM_FCFG2_PFLSH_SHIFT (23U)
21306/*! PFLSH - Program flash only
21307 * 0b0..Device supports FlexNVM
21308 * 0b1..Program Flash only, device does not support FlexNVM
21309 */
21310#define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
21311#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
21312#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
21313#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
21314#define SIM_FCFG2_SWAPPFLSH_MASK (0x80000000U)
21315#define SIM_FCFG2_SWAPPFLSH_SHIFT (31U)
21316/*! SWAPPFLSH - Swap program flash
21317 * 0b0..Swap is not active.
21318 * 0b1..Swap is active.
21319 */
21320#define SIM_FCFG2_SWAPPFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
21321/*! @} */
21322
21323/*! @name UIDH - Unique Identification Register High */
21324/*! @{ */
21325#define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
21326#define SIM_UIDH_UID_SHIFT (0U)
21327#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
21328/*! @} */
21329
21330/*! @name UIDMH - Unique Identification Register Mid-High */
21331/*! @{ */
21332#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
21333#define SIM_UIDMH_UID_SHIFT (0U)
21334#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
21335/*! @} */
21336
21337/*! @name UIDML - Unique Identification Register Mid Low */
21338/*! @{ */
21339#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
21340#define SIM_UIDML_UID_SHIFT (0U)
21341#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
21342/*! @} */
21343
21344/*! @name UIDL - Unique Identification Register Low */
21345/*! @{ */
21346#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
21347#define SIM_UIDL_UID_SHIFT (0U)
21348#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
21349/*! @} */
21350
21351/*! @name CLKDIV3 - System Clock Divider Register 3 */
21352/*! @{ */
21353#define SIM_CLKDIV3_PLLFLLFRAC_MASK (0x1U)
21354#define SIM_CLKDIV3_PLLFLLFRAC_SHIFT (0U)
21355#define SIM_CLKDIV3_PLLFLLFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK)
21356#define SIM_CLKDIV3_PLLFLLDIV_MASK (0xEU)
21357#define SIM_CLKDIV3_PLLFLLDIV_SHIFT (1U)
21358#define SIM_CLKDIV3_PLLFLLDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK)
21359/*! @} */
21360
21361/*! @name CLKDIV4 - System Clock Divider Register 4 */
21362/*! @{ */
21363#define SIM_CLKDIV4_TRACEFRAC_MASK (0x1U)
21364#define SIM_CLKDIV4_TRACEFRAC_SHIFT (0U)
21365#define SIM_CLKDIV4_TRACEFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
21366#define SIM_CLKDIV4_TRACEDIV_MASK (0xEU)
21367#define SIM_CLKDIV4_TRACEDIV_SHIFT (1U)
21368#define SIM_CLKDIV4_TRACEDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
21369/*! @} */
21370
21371
21372/*!
21373 * @}
21374 */ /* end of group SIM_Register_Masks */
21375
21376
21377/* SIM - Peripheral instance base addresses */
21378/** Peripheral SIM base address */
21379#define SIM_BASE (0x40047000u)
21380/** Peripheral SIM base pointer */
21381#define SIM ((SIM_Type *)SIM_BASE)
21382/** Array initializer of SIM peripheral base addresses */
21383#define SIM_BASE_ADDRS { SIM_BASE }
21384/** Array initializer of SIM peripheral base pointers */
21385#define SIM_BASE_PTRS { SIM }
21386
21387/*!
21388 * @}
21389 */ /* end of group SIM_Peripheral_Access_Layer */
21390
21391
21392/* ----------------------------------------------------------------------------
21393 -- SMC Peripheral Access Layer
21394 ---------------------------------------------------------------------------- */
21395
21396/*!
21397 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
21398 * @{
21399 */
21400
21401/** SMC - Register Layout Typedef */
21402typedef struct {
21403 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
21404 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
21405 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
21406 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
21407} SMC_Type;
21408
21409/* ----------------------------------------------------------------------------
21410 -- SMC Register Masks
21411 ---------------------------------------------------------------------------- */
21412
21413/*!
21414 * @addtogroup SMC_Register_Masks SMC Register Masks
21415 * @{
21416 */
21417
21418/*! @name PMPROT - Power Mode Protection register */
21419/*! @{ */
21420#define SMC_PMPROT_AVLLS_MASK (0x2U)
21421#define SMC_PMPROT_AVLLS_SHIFT (1U)
21422/*! AVLLS - Allow Very-Low-Leakage Stop Mode
21423 * 0b0..Any VLLSx mode is not allowed
21424 * 0b1..Any VLLSx mode is allowed
21425 */
21426#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
21427#define SMC_PMPROT_ALLS_MASK (0x8U)
21428#define SMC_PMPROT_ALLS_SHIFT (3U)
21429/*! ALLS - Allow Low-Leakage Stop Mode
21430 * 0b0..Any LLSx mode is not allowed
21431 * 0b1..Any LLSx mode is allowed
21432 */
21433#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
21434#define SMC_PMPROT_AVLP_MASK (0x20U)
21435#define SMC_PMPROT_AVLP_SHIFT (5U)
21436/*! AVLP - Allow Very-Low-Power Modes
21437 * 0b0..VLPR, VLPW, and VLPS are not allowed.
21438 * 0b1..VLPR, VLPW, and VLPS are allowed.
21439 */
21440#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
21441#define SMC_PMPROT_AHSRUN_MASK (0x80U)
21442#define SMC_PMPROT_AHSRUN_SHIFT (7U)
21443/*! AHSRUN - Allow High Speed Run mode
21444 * 0b0..HSRUN is not allowed
21445 * 0b1..HSRUN is allowed
21446 */
21447#define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
21448/*! @} */
21449
21450/*! @name PMCTRL - Power Mode Control register */
21451/*! @{ */
21452#define SMC_PMCTRL_STOPM_MASK (0x7U)
21453#define SMC_PMCTRL_STOPM_SHIFT (0U)
21454/*! STOPM - Stop Mode Control
21455 * 0b000..Normal Stop (STOP)
21456 * 0b001..Reserved
21457 * 0b010..Very-Low-Power Stop (VLPS)
21458 * 0b011..Low-Leakage Stop (LLSx)
21459 * 0b100..Very-Low-Leakage Stop (VLLSx)
21460 * 0b101..Reserved
21461 * 0b110..Reseved
21462 * 0b111..Reserved
21463 */
21464#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
21465#define SMC_PMCTRL_STOPA_MASK (0x8U)
21466#define SMC_PMCTRL_STOPA_SHIFT (3U)
21467/*! STOPA - Stop Aborted
21468 * 0b0..The previous stop mode entry was successsful.
21469 * 0b1..The previous stop mode entry was aborted.
21470 */
21471#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
21472#define SMC_PMCTRL_RUNM_MASK (0x60U)
21473#define SMC_PMCTRL_RUNM_SHIFT (5U)
21474/*! RUNM - Run Mode Control
21475 * 0b00..Normal Run mode (RUN)
21476 * 0b01..Reserved
21477 * 0b10..Very-Low-Power Run mode (VLPR)
21478 * 0b11..High Speed Run mode (HSRUN)
21479 */
21480#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
21481/*! @} */
21482
21483/*! @name STOPCTRL - Stop Control Register */
21484/*! @{ */
21485#define SMC_STOPCTRL_LLSM_MASK (0x7U)
21486#define SMC_STOPCTRL_LLSM_SHIFT (0U)
21487/*! LLSM - LLS or VLLS Mode Control
21488 * 0b000..VLLS0 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
21489 * 0b001..VLLS1 if PMCTRL[STOPM]=VLLSx, reserved if PMCTRL[STOPM]=LLSx
21490 * 0b010..VLLS2 if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
21491 * 0b011..VLLS3 if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
21492 * 0b100..Reserved
21493 * 0b101..Reserved
21494 * 0b110..Reserved
21495 * 0b111..Reserved
21496 */
21497#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
21498#define SMC_STOPCTRL_RAM2PO_MASK (0x10U)
21499#define SMC_STOPCTRL_RAM2PO_SHIFT (4U)
21500/*! RAM2PO - RAM2 Power Option
21501 * 0b0..RAM2 not powered in LLS2/VLLS2
21502 * 0b1..RAM2 powered in LLS2/VLLS2
21503 */
21504#define SMC_STOPCTRL_RAM2PO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK)
21505#define SMC_STOPCTRL_PORPO_MASK (0x20U)
21506#define SMC_STOPCTRL_PORPO_SHIFT (5U)
21507/*! PORPO - POR Power Option
21508 * 0b0..POR detect circuit is enabled in VLLS0
21509 * 0b1..POR detect circuit is disabled in VLLS0
21510 */
21511#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
21512#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
21513#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
21514/*! PSTOPO - Partial Stop Option
21515 * 0b00..STOP - Normal Stop mode
21516 * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
21517 * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
21518 * 0b11..Reserved
21519 */
21520#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
21521/*! @} */
21522
21523/*! @name PMSTAT - Power Mode Status register */
21524/*! @{ */
21525#define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
21526#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
21527#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
21528/*! @} */
21529
21530
21531/*!
21532 * @}
21533 */ /* end of group SMC_Register_Masks */
21534
21535
21536/* SMC - Peripheral instance base addresses */
21537/** Peripheral SMC base address */
21538#define SMC_BASE (0x4007E000u)
21539/** Peripheral SMC base pointer */
21540#define SMC ((SMC_Type *)SMC_BASE)
21541/** Array initializer of SMC peripheral base addresses */
21542#define SMC_BASE_ADDRS { SMC_BASE }
21543/** Array initializer of SMC peripheral base pointers */
21544#define SMC_BASE_PTRS { SMC }
21545
21546/*!
21547 * @}
21548 */ /* end of group SMC_Peripheral_Access_Layer */
21549
21550
21551/* ----------------------------------------------------------------------------
21552 -- SPI Peripheral Access Layer
21553 ---------------------------------------------------------------------------- */
21554
21555/*!
21556 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
21557 * @{
21558 */
21559
21560/** SPI - Register Layout Typedef */
21561typedef struct {
21562 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
21563 uint8_t RESERVED_0[4];
21564 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
21565 union { /* offset: 0xC */
21566 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
21567 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
21568 };
21569 uint8_t RESERVED_1[24];
21570 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
21571 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
21572 union { /* offset: 0x34 */
21573 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
21574 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
21575 };
21576 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
21577 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
21578 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
21579 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
21580 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
21581 uint8_t RESERVED_2[48];
21582 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
21583 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
21584 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
21585 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
21586} SPI_Type;
21587
21588/* ----------------------------------------------------------------------------
21589 -- SPI Register Masks
21590 ---------------------------------------------------------------------------- */
21591
21592/*!
21593 * @addtogroup SPI_Register_Masks SPI Register Masks
21594 * @{
21595 */
21596
21597/*! @name MCR - Module Configuration Register */
21598/*! @{ */
21599#define SPI_MCR_HALT_MASK (0x1U)
21600#define SPI_MCR_HALT_SHIFT (0U)
21601/*! HALT - Halt
21602 * 0b0..Start transfers.
21603 * 0b1..Stop transfers.
21604 */
21605#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
21606#define SPI_MCR_SMPL_PT_MASK (0x300U)
21607#define SPI_MCR_SMPL_PT_SHIFT (8U)
21608/*! SMPL_PT - Sample Point
21609 * 0b00..0 protocol clock cycles between SCK edge and SIN sample
21610 * 0b01..1 protocol clock cycle between SCK edge and SIN sample
21611 * 0b10..2 protocol clock cycles between SCK edge and SIN sample
21612 * 0b11..Reserved
21613 */
21614#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
21615#define SPI_MCR_CLR_RXF_MASK (0x400U)
21616#define SPI_MCR_CLR_RXF_SHIFT (10U)
21617/*! CLR_RXF - CLR_RXF
21618 * 0b0..Do not clear the RX FIFO counter.
21619 * 0b1..Clear the RX FIFO counter.
21620 */
21621#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
21622#define SPI_MCR_CLR_TXF_MASK (0x800U)
21623#define SPI_MCR_CLR_TXF_SHIFT (11U)
21624/*! CLR_TXF - Clear TX FIFO
21625 * 0b0..Do not clear the TX FIFO counter.
21626 * 0b1..Clear the TX FIFO counter.
21627 */
21628#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
21629#define SPI_MCR_DIS_RXF_MASK (0x1000U)
21630#define SPI_MCR_DIS_RXF_SHIFT (12U)
21631/*! DIS_RXF - Disable Receive FIFO
21632 * 0b0..RX FIFO is enabled.
21633 * 0b1..RX FIFO is disabled.
21634 */
21635#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
21636#define SPI_MCR_DIS_TXF_MASK (0x2000U)
21637#define SPI_MCR_DIS_TXF_SHIFT (13U)
21638/*! DIS_TXF - Disable Transmit FIFO
21639 * 0b0..TX FIFO is enabled.
21640 * 0b1..TX FIFO is disabled.
21641 */
21642#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
21643#define SPI_MCR_MDIS_MASK (0x4000U)
21644#define SPI_MCR_MDIS_SHIFT (14U)
21645/*! MDIS - Module Disable
21646 * 0b0..Enables the module clocks.
21647 * 0b1..Allows external logic to disable the module clocks.
21648 */
21649#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
21650#define SPI_MCR_DOZE_MASK (0x8000U)
21651#define SPI_MCR_DOZE_SHIFT (15U)
21652/*! DOZE - Doze Enable
21653 * 0b0..Doze mode has no effect on the module.
21654 * 0b1..Doze mode disables the module.
21655 */
21656#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
21657#define SPI_MCR_PCSIS_MASK (0x3F0000U)
21658#define SPI_MCR_PCSIS_SHIFT (16U)
21659/*! PCSIS - Peripheral Chip Select x Inactive State
21660 * 0b000000..The inactive state of PCSx is low.
21661 * 0b000001..The inactive state of PCSx is high.
21662 */
21663#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
21664#define SPI_MCR_ROOE_MASK (0x1000000U)
21665#define SPI_MCR_ROOE_SHIFT (24U)
21666/*! ROOE - Receive FIFO Overflow Overwrite Enable
21667 * 0b0..Incoming data is ignored.
21668 * 0b1..Incoming data is shifted into the shift register.
21669 */
21670#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
21671#define SPI_MCR_PCSSE_MASK (0x2000000U)
21672#define SPI_MCR_PCSSE_SHIFT (25U)
21673/*! PCSSE - Peripheral Chip Select Strobe Enable
21674 * 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
21675 * 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.
21676 */
21677#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
21678#define SPI_MCR_MTFE_MASK (0x4000000U)
21679#define SPI_MCR_MTFE_SHIFT (26U)
21680/*! MTFE - Modified Transfer Format Enable
21681 * 0b0..Modified SPI transfer format disabled.
21682 * 0b1..Modified SPI transfer format enabled.
21683 */
21684#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
21685#define SPI_MCR_FRZ_MASK (0x8000000U)
21686#define SPI_MCR_FRZ_SHIFT (27U)
21687/*! FRZ - Freeze
21688 * 0b0..Do not halt serial transfers in Debug mode.
21689 * 0b1..Halt serial transfers in Debug mode.
21690 */
21691#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
21692#define SPI_MCR_DCONF_MASK (0x30000000U)
21693#define SPI_MCR_DCONF_SHIFT (28U)
21694/*! DCONF - SPI Configuration.
21695 * 0b00..SPI
21696 * 0b01..Reserved
21697 * 0b10..Reserved
21698 * 0b11..Reserved
21699 */
21700#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
21701#define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
21702#define SPI_MCR_CONT_SCKE_SHIFT (30U)
21703/*! CONT_SCKE - Continuous SCK Enable
21704 * 0b0..Continuous SCK disabled.
21705 * 0b1..Continuous SCK enabled.
21706 */
21707#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
21708#define SPI_MCR_MSTR_MASK (0x80000000U)
21709#define SPI_MCR_MSTR_SHIFT (31U)
21710/*! MSTR - Master/Slave Mode Select
21711 * 0b0..Enables Slave mode
21712 * 0b1..Enables Master mode
21713 */
21714#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
21715/*! @} */
21716
21717/*! @name TCR - Transfer Count Register */
21718/*! @{ */
21719#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
21720#define SPI_TCR_SPI_TCNT_SHIFT (16U)
21721#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
21722/*! @} */
21723
21724/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
21725/*! @{ */
21726#define SPI_CTAR_BR_MASK (0xFU)
21727#define SPI_CTAR_BR_SHIFT (0U)
21728#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
21729#define SPI_CTAR_DT_MASK (0xF0U)
21730#define SPI_CTAR_DT_SHIFT (4U)
21731#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
21732#define SPI_CTAR_ASC_MASK (0xF00U)
21733#define SPI_CTAR_ASC_SHIFT (8U)
21734#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
21735#define SPI_CTAR_CSSCK_MASK (0xF000U)
21736#define SPI_CTAR_CSSCK_SHIFT (12U)
21737#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
21738#define SPI_CTAR_PBR_MASK (0x30000U)
21739#define SPI_CTAR_PBR_SHIFT (16U)
21740/*! PBR - Baud Rate Prescaler
21741 * 0b00..Baud Rate Prescaler value is 2.
21742 * 0b01..Baud Rate Prescaler value is 3.
21743 * 0b10..Baud Rate Prescaler value is 5.
21744 * 0b11..Baud Rate Prescaler value is 7.
21745 */
21746#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
21747#define SPI_CTAR_PDT_MASK (0xC0000U)
21748#define SPI_CTAR_PDT_SHIFT (18U)
21749/*! PDT - Delay after Transfer Prescaler
21750 * 0b00..Delay after Transfer Prescaler value is 1.
21751 * 0b01..Delay after Transfer Prescaler value is 3.
21752 * 0b10..Delay after Transfer Prescaler value is 5.
21753 * 0b11..Delay after Transfer Prescaler value is 7.
21754 */
21755#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
21756#define SPI_CTAR_PASC_MASK (0x300000U)
21757#define SPI_CTAR_PASC_SHIFT (20U)
21758/*! PASC - After SCK Delay Prescaler
21759 * 0b00..Delay after Transfer Prescaler value is 1.
21760 * 0b01..Delay after Transfer Prescaler value is 3.
21761 * 0b10..Delay after Transfer Prescaler value is 5.
21762 * 0b11..Delay after Transfer Prescaler value is 7.
21763 */
21764#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
21765#define SPI_CTAR_PCSSCK_MASK (0xC00000U)
21766#define SPI_CTAR_PCSSCK_SHIFT (22U)
21767/*! PCSSCK - PCS to SCK Delay Prescaler
21768 * 0b00..PCS to SCK Prescaler value is 1.
21769 * 0b01..PCS to SCK Prescaler value is 3.
21770 * 0b10..PCS to SCK Prescaler value is 5.
21771 * 0b11..PCS to SCK Prescaler value is 7.
21772 */
21773#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
21774#define SPI_CTAR_LSBFE_MASK (0x1000000U)
21775#define SPI_CTAR_LSBFE_SHIFT (24U)
21776/*! LSBFE - LSB First
21777 * 0b0..Data is transferred MSB first.
21778 * 0b1..Data is transferred LSB first.
21779 */
21780#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
21781#define SPI_CTAR_CPHA_MASK (0x2000000U)
21782#define SPI_CTAR_CPHA_SHIFT (25U)
21783/*! CPHA - Clock Phase
21784 * 0b0..Data is captured on the leading edge of SCK and changed on the following edge.
21785 * 0b1..Data is changed on the leading edge of SCK and captured on the following edge.
21786 */
21787#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
21788#define SPI_CTAR_CPOL_MASK (0x4000000U)
21789#define SPI_CTAR_CPOL_SHIFT (26U)
21790/*! CPOL - Clock Polarity
21791 * 0b0..The inactive state value of SCK is low.
21792 * 0b1..The inactive state value of SCK is high.
21793 */
21794#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
21795#define SPI_CTAR_FMSZ_MASK (0x78000000U)
21796#define SPI_CTAR_FMSZ_SHIFT (27U)
21797#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
21798#define SPI_CTAR_DBR_MASK (0x80000000U)
21799#define SPI_CTAR_DBR_SHIFT (31U)
21800/*! DBR - Double Baud Rate
21801 * 0b0..The baud rate is computed normally with a 50/50 duty cycle.
21802 * 0b1..The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
21803 */
21804#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
21805/*! @} */
21806
21807/* The count of SPI_CTAR */
21808#define SPI_CTAR_COUNT (2U)
21809
21810/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
21811/*! @{ */
21812#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
21813#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
21814/*! CPHA - Clock Phase
21815 * 0b0..Data is captured on the leading edge of SCK and changed on the following edge.
21816 * 0b1..Data is changed on the leading edge of SCK and captured on the following edge.
21817 */
21818#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
21819#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
21820#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
21821/*! CPOL - Clock Polarity
21822 * 0b0..The inactive state value of SCK is low.
21823 * 0b1..The inactive state value of SCK is high.
21824 */
21825#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
21826#define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U)
21827#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
21828#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
21829/*! @} */
21830
21831/* The count of SPI_CTAR_SLAVE */
21832#define SPI_CTAR_SLAVE_COUNT (1U)
21833
21834/*! @name SR - Status Register */
21835/*! @{ */
21836#define SPI_SR_POPNXTPTR_MASK (0xFU)
21837#define SPI_SR_POPNXTPTR_SHIFT (0U)
21838#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
21839#define SPI_SR_RXCTR_MASK (0xF0U)
21840#define SPI_SR_RXCTR_SHIFT (4U)
21841#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
21842#define SPI_SR_TXNXTPTR_MASK (0xF00U)
21843#define SPI_SR_TXNXTPTR_SHIFT (8U)
21844#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
21845#define SPI_SR_TXCTR_MASK (0xF000U)
21846#define SPI_SR_TXCTR_SHIFT (12U)
21847#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
21848#define SPI_SR_RFDF_MASK (0x20000U)
21849#define SPI_SR_RFDF_SHIFT (17U)
21850/*! RFDF - Receive FIFO Drain Flag
21851 * 0b0..RX FIFO is empty.
21852 * 0b1..RX FIFO is not empty.
21853 */
21854#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
21855#define SPI_SR_RFOF_MASK (0x80000U)
21856#define SPI_SR_RFOF_SHIFT (19U)
21857/*! RFOF - Receive FIFO Overflow Flag
21858 * 0b0..No Rx FIFO overflow.
21859 * 0b1..Rx FIFO overflow has occurred.
21860 */
21861#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
21862#define SPI_SR_TFFF_MASK (0x2000000U)
21863#define SPI_SR_TFFF_SHIFT (25U)
21864/*! TFFF - Transmit FIFO Fill Flag
21865 * 0b0..TX FIFO is full.
21866 * 0b1..TX FIFO is not full.
21867 */
21868#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
21869#define SPI_SR_TFUF_MASK (0x8000000U)
21870#define SPI_SR_TFUF_SHIFT (27U)
21871/*! TFUF - Transmit FIFO Underflow Flag
21872 * 0b0..No TX FIFO underflow.
21873 * 0b1..TX FIFO underflow has occurred.
21874 */
21875#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
21876#define SPI_SR_EOQF_MASK (0x10000000U)
21877#define SPI_SR_EOQF_SHIFT (28U)
21878/*! EOQF - End of Queue Flag
21879 * 0b0..EOQ is not set in the executing command.
21880 * 0b1..EOQ is set in the executing SPI command.
21881 */
21882#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
21883#define SPI_SR_TXRXS_MASK (0x40000000U)
21884#define SPI_SR_TXRXS_SHIFT (30U)
21885/*! TXRXS - TX and RX Status
21886 * 0b0..Transmit and receive operations are disabled (The module is in Stopped state).
21887 * 0b1..Transmit and receive operations are enabled (The module is in Running state).
21888 */
21889#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
21890#define SPI_SR_TCF_MASK (0x80000000U)
21891#define SPI_SR_TCF_SHIFT (31U)
21892/*! TCF - Transfer Complete Flag
21893 * 0b0..Transfer not complete.
21894 * 0b1..Transfer complete.
21895 */
21896#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
21897/*! @} */
21898
21899/*! @name RSER - DMA/Interrupt Request Select and Enable Register */
21900/*! @{ */
21901#define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
21902#define SPI_RSER_RFDF_DIRS_SHIFT (16U)
21903/*! RFDF_DIRS - Receive FIFO Drain DMA or Interrupt Request Select
21904 * 0b0..Interrupt request.
21905 * 0b1..DMA request.
21906 */
21907#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
21908#define SPI_RSER_RFDF_RE_MASK (0x20000U)
21909#define SPI_RSER_RFDF_RE_SHIFT (17U)
21910/*! RFDF_RE - Receive FIFO Drain Request Enable
21911 * 0b0..RFDF interrupt or DMA requests are disabled.
21912 * 0b1..RFDF interrupt or DMA requests are enabled.
21913 */
21914#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
21915#define SPI_RSER_RFOF_RE_MASK (0x80000U)
21916#define SPI_RSER_RFOF_RE_SHIFT (19U)
21917/*! RFOF_RE - Receive FIFO Overflow Request Enable
21918 * 0b0..RFOF interrupt requests are disabled.
21919 * 0b1..RFOF interrupt requests are enabled.
21920 */
21921#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
21922#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
21923#define SPI_RSER_TFFF_DIRS_SHIFT (24U)
21924/*! TFFF_DIRS - Transmit FIFO Fill DMA or Interrupt Request Select
21925 * 0b0..TFFF flag generates interrupt requests.
21926 * 0b1..TFFF flag generates DMA requests.
21927 */
21928#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
21929#define SPI_RSER_TFFF_RE_MASK (0x2000000U)
21930#define SPI_RSER_TFFF_RE_SHIFT (25U)
21931/*! TFFF_RE - Transmit FIFO Fill Request Enable
21932 * 0b0..TFFF interrupts or DMA requests are disabled.
21933 * 0b1..TFFF interrupts or DMA requests are enabled.
21934 */
21935#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
21936#define SPI_RSER_TFUF_RE_MASK (0x8000000U)
21937#define SPI_RSER_TFUF_RE_SHIFT (27U)
21938/*! TFUF_RE - Transmit FIFO Underflow Request Enable
21939 * 0b0..TFUF interrupt requests are disabled.
21940 * 0b1..TFUF interrupt requests are enabled.
21941 */
21942#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
21943#define SPI_RSER_EOQF_RE_MASK (0x10000000U)
21944#define SPI_RSER_EOQF_RE_SHIFT (28U)
21945/*! EOQF_RE - Finished Request Enable
21946 * 0b0..EOQF interrupt requests are disabled.
21947 * 0b1..EOQF interrupt requests are enabled.
21948 */
21949#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
21950#define SPI_RSER_TCF_RE_MASK (0x80000000U)
21951#define SPI_RSER_TCF_RE_SHIFT (31U)
21952/*! TCF_RE - Transmission Complete Request Enable
21953 * 0b0..TCF interrupt requests are disabled.
21954 * 0b1..TCF interrupt requests are enabled.
21955 */
21956#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
21957/*! @} */
21958
21959/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
21960/*! @{ */
21961#define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
21962#define SPI_PUSHR_TXDATA_SHIFT (0U)
21963#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
21964#define SPI_PUSHR_PCS_MASK (0x3F0000U)
21965#define SPI_PUSHR_PCS_SHIFT (16U)
21966/*! PCS
21967 * 0b000000..Negate the PCS[x] signal.
21968 * 0b000001..Assert the PCS[x] signal.
21969 */
21970#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
21971#define SPI_PUSHR_CTCNT_MASK (0x4000000U)
21972#define SPI_PUSHR_CTCNT_SHIFT (26U)
21973/*! CTCNT - Clear Transfer Counter
21974 * 0b0..Do not clear the TCR[TCNT] field.
21975 * 0b1..Clear the TCR[TCNT] field.
21976 */
21977#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
21978#define SPI_PUSHR_EOQ_MASK (0x8000000U)
21979#define SPI_PUSHR_EOQ_SHIFT (27U)
21980/*! EOQ - End Of Queue
21981 * 0b0..The SPI data is not the last data to transfer.
21982 * 0b1..The SPI data is the last data to transfer.
21983 */
21984#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
21985#define SPI_PUSHR_CTAS_MASK (0x70000000U)
21986#define SPI_PUSHR_CTAS_SHIFT (28U)
21987/*! CTAS - Clock and Transfer Attributes Select
21988 * 0b000..CTAR0
21989 * 0b001..CTAR1
21990 * 0b010..Reserved
21991 * 0b011..Reserved
21992 * 0b100..Reserved
21993 * 0b101..Reserved
21994 * 0b110..Reserved
21995 * 0b111..Reserved
21996 */
21997#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
21998#define SPI_PUSHR_CONT_MASK (0x80000000U)
21999#define SPI_PUSHR_CONT_SHIFT (31U)
22000/*! CONT - Continuous Peripheral Chip Select Enable
22001 * 0b0..Return PCSn signals to their inactive state between transfers.
22002 * 0b1..Keep PCSn signals asserted between transfers.
22003 */
22004#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
22005/*! @} */
22006
22007/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
22008/*! @{ */
22009#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
22010#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
22011#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
22012/*! @} */
22013
22014/*! @name POPR - POP RX FIFO Register */
22015/*! @{ */
22016#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
22017#define SPI_POPR_RXDATA_SHIFT (0U)
22018#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
22019/*! @} */
22020
22021/*! @name TXFR0 - Transmit FIFO Registers */
22022/*! @{ */
22023#define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
22024#define SPI_TXFR0_TXDATA_SHIFT (0U)
22025#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
22026#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
22027#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
22028#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
22029/*! @} */
22030
22031/*! @name TXFR1 - Transmit FIFO Registers */
22032/*! @{ */
22033#define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
22034#define SPI_TXFR1_TXDATA_SHIFT (0U)
22035#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
22036#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
22037#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
22038#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
22039/*! @} */
22040
22041/*! @name TXFR2 - Transmit FIFO Registers */
22042/*! @{ */
22043#define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
22044#define SPI_TXFR2_TXDATA_SHIFT (0U)
22045#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
22046#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
22047#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
22048#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
22049/*! @} */
22050
22051/*! @name TXFR3 - Transmit FIFO Registers */
22052/*! @{ */
22053#define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
22054#define SPI_TXFR3_TXDATA_SHIFT (0U)
22055#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
22056#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
22057#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
22058#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
22059/*! @} */
22060
22061/*! @name RXFR0 - Receive FIFO Registers */
22062/*! @{ */
22063#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
22064#define SPI_RXFR0_RXDATA_SHIFT (0U)
22065#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
22066/*! @} */
22067
22068/*! @name RXFR1 - Receive FIFO Registers */
22069/*! @{ */
22070#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
22071#define SPI_RXFR1_RXDATA_SHIFT (0U)
22072#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
22073/*! @} */
22074
22075/*! @name RXFR2 - Receive FIFO Registers */
22076/*! @{ */
22077#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
22078#define SPI_RXFR2_RXDATA_SHIFT (0U)
22079#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
22080/*! @} */
22081
22082/*! @name RXFR3 - Receive FIFO Registers */
22083/*! @{ */
22084#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
22085#define SPI_RXFR3_RXDATA_SHIFT (0U)
22086#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
22087/*! @} */
22088
22089
22090/*!
22091 * @}
22092 */ /* end of group SPI_Register_Masks */
22093
22094
22095/* SPI - Peripheral instance base addresses */
22096/** Peripheral SPI0 base address */
22097#define SPI0_BASE (0x4002C000u)
22098/** Peripheral SPI0 base pointer */
22099#define SPI0 ((SPI_Type *)SPI0_BASE)
22100/** Peripheral SPI1 base address */
22101#define SPI1_BASE (0x4002D000u)
22102/** Peripheral SPI1 base pointer */
22103#define SPI1 ((SPI_Type *)SPI1_BASE)
22104/** Peripheral SPI2 base address */
22105#define SPI2_BASE (0x400AC000u)
22106/** Peripheral SPI2 base pointer */
22107#define SPI2 ((SPI_Type *)SPI2_BASE)
22108/** Array initializer of SPI peripheral base addresses */
22109#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
22110/** Array initializer of SPI peripheral base pointers */
22111#define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
22112/** Interrupt vectors for the SPI peripheral type */
22113#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
22114
22115/*!
22116 * @}
22117 */ /* end of group SPI_Peripheral_Access_Layer */
22118
22119
22120/* ----------------------------------------------------------------------------
22121 -- SYSMPU Peripheral Access Layer
22122 ---------------------------------------------------------------------------- */
22123
22124/*!
22125 * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer
22126 * @{
22127 */
22128
22129/** SYSMPU - Register Layout Typedef */
22130typedef struct {
22131 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
22132 uint8_t RESERVED_0[12];
22133 struct { /* offset: 0x10, array step: 0x8 */
22134 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
22135 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
22136 } SP[5];
22137 uint8_t RESERVED_1[968];
22138 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
22139 uint8_t RESERVED_2[832];
22140 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
22141} SYSMPU_Type;
22142
22143/* ----------------------------------------------------------------------------
22144 -- SYSMPU Register Masks
22145 ---------------------------------------------------------------------------- */
22146
22147/*!
22148 * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks
22149 * @{
22150 */
22151
22152/*! @name CESR - Control/Error Status Register */
22153/*! @{ */
22154#define SYSMPU_CESR_VLD_MASK (0x1U)
22155#define SYSMPU_CESR_VLD_SHIFT (0U)
22156/*! VLD - Valid
22157 * 0b0..MPU is disabled. All accesses from all bus masters are allowed.
22158 * 0b1..MPU is enabled
22159 */
22160#define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
22161#define SYSMPU_CESR_NRGD_MASK (0xF00U)
22162#define SYSMPU_CESR_NRGD_SHIFT (8U)
22163/*! NRGD - Number Of Region Descriptors
22164 * 0b0000..8 region descriptors
22165 * 0b0001..12 region descriptors
22166 * 0b0010..16 region descriptors
22167 */
22168#define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
22169#define SYSMPU_CESR_NSP_MASK (0xF000U)
22170#define SYSMPU_CESR_NSP_SHIFT (12U)
22171#define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
22172#define SYSMPU_CESR_HRL_MASK (0xF0000U)
22173#define SYSMPU_CESR_HRL_SHIFT (16U)
22174#define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
22175#define SYSMPU_CESR_SPERR_MASK (0xF8000000U)
22176#define SYSMPU_CESR_SPERR_SHIFT (27U)
22177/*! SPERR - Slave Port n Error
22178 * 0b00000..No error has occurred for slave port n.
22179 * 0b00001..An error has occurred for slave port n.
22180 */
22181#define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
22182/*! @} */
22183
22184/*! @name EAR - Error Address Register, slave port n */
22185/*! @{ */
22186#define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU)
22187#define SYSMPU_EAR_EADDR_SHIFT (0U)
22188#define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
22189/*! @} */
22190
22191/* The count of SYSMPU_EAR */
22192#define SYSMPU_EAR_COUNT (5U)
22193
22194/*! @name EDR - Error Detail Register, slave port n */
22195/*! @{ */
22196#define SYSMPU_EDR_ERW_MASK (0x1U)
22197#define SYSMPU_EDR_ERW_SHIFT (0U)
22198/*! ERW - Error Read/Write
22199 * 0b0..Read
22200 * 0b1..Write
22201 */
22202#define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
22203#define SYSMPU_EDR_EATTR_MASK (0xEU)
22204#define SYSMPU_EDR_EATTR_SHIFT (1U)
22205/*! EATTR - Error Attributes
22206 * 0b000..User mode, instruction access
22207 * 0b001..User mode, data access
22208 * 0b010..Supervisor mode, instruction access
22209 * 0b011..Supervisor mode, data access
22210 */
22211#define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
22212#define SYSMPU_EDR_EMN_MASK (0xF0U)
22213#define SYSMPU_EDR_EMN_SHIFT (4U)
22214#define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
22215#define SYSMPU_EDR_EPID_MASK (0xFF00U)
22216#define SYSMPU_EDR_EPID_SHIFT (8U)
22217#define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
22218#define SYSMPU_EDR_EACD_MASK (0xFFFF0000U)
22219#define SYSMPU_EDR_EACD_SHIFT (16U)
22220#define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
22221/*! @} */
22222
22223/* The count of SYSMPU_EDR */
22224#define SYSMPU_EDR_COUNT (5U)
22225
22226/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
22227/*! @{ */
22228#define SYSMPU_WORD_M0UM_MASK (0x7U)
22229#define SYSMPU_WORD_M0UM_SHIFT (0U)
22230#define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
22231#define SYSMPU_WORD_VLD_MASK (0x1U)
22232#define SYSMPU_WORD_VLD_SHIFT (0U)
22233/*! VLD - Valid
22234 * 0b0..Region descriptor is invalid
22235 * 0b1..Region descriptor is valid
22236 */
22237#define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
22238#define SYSMPU_WORD_M0SM_MASK (0x18U)
22239#define SYSMPU_WORD_M0SM_SHIFT (3U)
22240#define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
22241#define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
22242#define SYSMPU_WORD_ENDADDR_SHIFT (5U)
22243#define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
22244#define SYSMPU_WORD_M0PE_MASK (0x20U)
22245#define SYSMPU_WORD_M0PE_SHIFT (5U)
22246#define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
22247#define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
22248#define SYSMPU_WORD_SRTADDR_SHIFT (5U)
22249#define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
22250#define SYSMPU_WORD_M1UM_MASK (0x1C0U)
22251#define SYSMPU_WORD_M1UM_SHIFT (6U)
22252#define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
22253#define SYSMPU_WORD_M1SM_MASK (0x600U)
22254#define SYSMPU_WORD_M1SM_SHIFT (9U)
22255#define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
22256#define SYSMPU_WORD_M1PE_MASK (0x800U)
22257#define SYSMPU_WORD_M1PE_SHIFT (11U)
22258#define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
22259#define SYSMPU_WORD_M2UM_MASK (0x7000U)
22260#define SYSMPU_WORD_M2UM_SHIFT (12U)
22261#define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
22262#define SYSMPU_WORD_M2SM_MASK (0x18000U)
22263#define SYSMPU_WORD_M2SM_SHIFT (15U)
22264#define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
22265#define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U)
22266#define SYSMPU_WORD_PIDMASK_SHIFT (16U)
22267#define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
22268#define SYSMPU_WORD_M2PE_MASK (0x20000U)
22269#define SYSMPU_WORD_M2PE_SHIFT (17U)
22270#define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
22271#define SYSMPU_WORD_M3UM_MASK (0x1C0000U)
22272#define SYSMPU_WORD_M3UM_SHIFT (18U)
22273/*! M3UM - Bus Master 3 User Mode Access Control
22274 * 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
22275 * 0b001..Allows the given access type to occur
22276 */
22277#define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
22278#define SYSMPU_WORD_M3SM_MASK (0x600000U)
22279#define SYSMPU_WORD_M3SM_SHIFT (21U)
22280/*! M3SM - Bus Master 3 Supervisor Mode Access Control
22281 * 0b00..r/w/x; read, write and execute allowed
22282 * 0b01..r/x; read and execute allowed, but no write
22283 * 0b10..r/w; read and write allowed, but no execute
22284 * 0b11..Same as User mode defined in M3UM
22285 */
22286#define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
22287#define SYSMPU_WORD_M3PE_MASK (0x800000U)
22288#define SYSMPU_WORD_M3PE_SHIFT (23U)
22289/*! M3PE - Bus Master 3 Process Identifier Enable
22290 * 0b0..Do not include the process identifier in the evaluation
22291 * 0b1..Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation
22292 */
22293#define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
22294#define SYSMPU_WORD_M4WE_MASK (0x1000000U)
22295#define SYSMPU_WORD_M4WE_SHIFT (24U)
22296/*! M4WE - Bus Master 4 Write Enable
22297 * 0b0..Bus master 4 writes terminate with an access error and the write is not performed
22298 * 0b1..Bus master 4 writes allowed
22299 */
22300#define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
22301#define SYSMPU_WORD_PID_MASK (0xFF000000U)
22302#define SYSMPU_WORD_PID_SHIFT (24U)
22303#define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
22304#define SYSMPU_WORD_M4RE_MASK (0x2000000U)
22305#define SYSMPU_WORD_M4RE_SHIFT (25U)
22306/*! M4RE - Bus Master 4 Read Enable
22307 * 0b0..Bus master 4 reads terminate with an access error and the read is not performed
22308 * 0b1..Bus master 4 reads allowed
22309 */
22310#define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
22311#define SYSMPU_WORD_M5WE_MASK (0x4000000U)
22312#define SYSMPU_WORD_M5WE_SHIFT (26U)
22313/*! M5WE - Bus Master 5 Write Enable
22314 * 0b0..Bus master 5 writes terminate with an access error and the write is not performed
22315 * 0b1..Bus master 5 writes allowed
22316 */
22317#define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
22318#define SYSMPU_WORD_M5RE_MASK (0x8000000U)
22319#define SYSMPU_WORD_M5RE_SHIFT (27U)
22320/*! M5RE - Bus Master 5 Read Enable
22321 * 0b0..Bus master 5 reads terminate with an access error and the read is not performed
22322 * 0b1..Bus master 5 reads allowed
22323 */
22324#define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
22325#define SYSMPU_WORD_M6WE_MASK (0x10000000U)
22326#define SYSMPU_WORD_M6WE_SHIFT (28U)
22327/*! M6WE - Bus Master 6 Write Enable
22328 * 0b0..Bus master 6 writes terminate with an access error and the write is not performed
22329 * 0b1..Bus master 6 writes allowed
22330 */
22331#define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
22332#define SYSMPU_WORD_M6RE_MASK (0x20000000U)
22333#define SYSMPU_WORD_M6RE_SHIFT (29U)
22334/*! M6RE - Bus Master 6 Read Enable
22335 * 0b0..Bus master 6 reads terminate with an access error and the read is not performed
22336 * 0b1..Bus master 6 reads allowed
22337 */
22338#define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
22339#define SYSMPU_WORD_M7WE_MASK (0x40000000U)
22340#define SYSMPU_WORD_M7WE_SHIFT (30U)
22341/*! M7WE - Bus Master 7 Write Enable
22342 * 0b0..Bus master 7 writes terminate with an access error and the write is not performed
22343 * 0b1..Bus master 7 writes allowed
22344 */
22345#define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
22346#define SYSMPU_WORD_M7RE_MASK (0x80000000U)
22347#define SYSMPU_WORD_M7RE_SHIFT (31U)
22348/*! M7RE - Bus Master 7 Read Enable
22349 * 0b0..Bus master 7 reads terminate with an access error and the read is not performed
22350 * 0b1..Bus master 7 reads allowed
22351 */
22352#define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
22353/*! @} */
22354
22355/* The count of SYSMPU_WORD */
22356#define SYSMPU_WORD_COUNT (12U)
22357
22358/* The count of SYSMPU_WORD */
22359#define SYSMPU_WORD_COUNT2 (4U)
22360
22361/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
22362/*! @{ */
22363#define SYSMPU_RGDAAC_M0UM_MASK (0x7U)
22364#define SYSMPU_RGDAAC_M0UM_SHIFT (0U)
22365#define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
22366#define SYSMPU_RGDAAC_M0SM_MASK (0x18U)
22367#define SYSMPU_RGDAAC_M0SM_SHIFT (3U)
22368#define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
22369#define SYSMPU_RGDAAC_M0PE_MASK (0x20U)
22370#define SYSMPU_RGDAAC_M0PE_SHIFT (5U)
22371#define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
22372#define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U)
22373#define SYSMPU_RGDAAC_M1UM_SHIFT (6U)
22374#define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
22375#define SYSMPU_RGDAAC_M1SM_MASK (0x600U)
22376#define SYSMPU_RGDAAC_M1SM_SHIFT (9U)
22377#define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
22378#define SYSMPU_RGDAAC_M1PE_MASK (0x800U)
22379#define SYSMPU_RGDAAC_M1PE_SHIFT (11U)
22380#define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
22381#define SYSMPU_RGDAAC_M2UM_MASK (0x7000U)
22382#define SYSMPU_RGDAAC_M2UM_SHIFT (12U)
22383#define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
22384#define SYSMPU_RGDAAC_M2SM_MASK (0x18000U)
22385#define SYSMPU_RGDAAC_M2SM_SHIFT (15U)
22386#define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
22387#define SYSMPU_RGDAAC_M2PE_MASK (0x20000U)
22388#define SYSMPU_RGDAAC_M2PE_SHIFT (17U)
22389#define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
22390#define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U)
22391#define SYSMPU_RGDAAC_M3UM_SHIFT (18U)
22392/*! M3UM - Bus Master 3 User Mode Access Control
22393 * 0b000..An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
22394 * 0b001..Allows the given access type to occur
22395 */
22396#define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
22397#define SYSMPU_RGDAAC_M3SM_MASK (0x600000U)
22398#define SYSMPU_RGDAAC_M3SM_SHIFT (21U)
22399/*! M3SM - Bus Master 3 Supervisor Mode Access Control
22400 * 0b00..r/w/x; read, write and execute allowed
22401 * 0b01..r/x; read and execute allowed, but no write
22402 * 0b10..r/w; read and write allowed, but no execute
22403 * 0b11..Same as User mode defined in M3UM
22404 */
22405#define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
22406#define SYSMPU_RGDAAC_M3PE_MASK (0x800000U)
22407#define SYSMPU_RGDAAC_M3PE_SHIFT (23U)
22408/*! M3PE - Bus Master 3 Process Identifier Enable
22409 * 0b0..Do not include the process identifier in the evaluation
22410 * 0b1..Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
22411 */
22412#define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
22413#define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U)
22414#define SYSMPU_RGDAAC_M4WE_SHIFT (24U)
22415/*! M4WE - Bus Master 4 Write Enable
22416 * 0b0..Bus master 4 writes terminate with an access error and the write is not performed
22417 * 0b1..Bus master 4 writes allowed
22418 */
22419#define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
22420#define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U)
22421#define SYSMPU_RGDAAC_M4RE_SHIFT (25U)
22422/*! M4RE - Bus Master 4 Read Enable
22423 * 0b0..Bus master 4 reads terminate with an access error and the read is not performed
22424 * 0b1..Bus master 4 reads allowed
22425 */
22426#define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
22427#define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U)
22428#define SYSMPU_RGDAAC_M5WE_SHIFT (26U)
22429/*! M5WE - Bus Master 5 Write Enable
22430 * 0b0..Bus master 5 writes terminate with an access error and the write is not performed
22431 * 0b1..Bus master 5 writes allowed
22432 */
22433#define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
22434#define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U)
22435#define SYSMPU_RGDAAC_M5RE_SHIFT (27U)
22436/*! M5RE - Bus Master 5 Read Enable
22437 * 0b0..Bus master 5 reads terminate with an access error and the read is not performed
22438 * 0b1..Bus master 5 reads allowed
22439 */
22440#define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
22441#define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U)
22442#define SYSMPU_RGDAAC_M6WE_SHIFT (28U)
22443/*! M6WE - Bus Master 6 Write Enable
22444 * 0b0..Bus master 6 writes terminate with an access error and the write is not performed
22445 * 0b1..Bus master 6 writes allowed
22446 */
22447#define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
22448#define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U)
22449#define SYSMPU_RGDAAC_M6RE_SHIFT (29U)
22450/*! M6RE - Bus Master 6 Read Enable
22451 * 0b0..Bus master 6 reads terminate with an access error and the read is not performed
22452 * 0b1..Bus master 6 reads allowed
22453 */
22454#define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
22455#define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U)
22456#define SYSMPU_RGDAAC_M7WE_SHIFT (30U)
22457/*! M7WE - Bus Master 7 Write Enable
22458 * 0b0..Bus master 7 writes terminate with an access error and the write is not performed
22459 * 0b1..Bus master 7 writes allowed
22460 */
22461#define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
22462#define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U)
22463#define SYSMPU_RGDAAC_M7RE_SHIFT (31U)
22464/*! M7RE - Bus Master 7 Read Enable
22465 * 0b0..Bus master 7 reads terminate with an access error and the read is not performed
22466 * 0b1..Bus master 7 reads allowed
22467 */
22468#define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
22469/*! @} */
22470
22471/* The count of SYSMPU_RGDAAC */
22472#define SYSMPU_RGDAAC_COUNT (12U)
22473
22474
22475/*!
22476 * @}
22477 */ /* end of group SYSMPU_Register_Masks */
22478
22479
22480/* SYSMPU - Peripheral instance base addresses */
22481/** Peripheral SYSMPU base address */
22482#define SYSMPU_BASE (0x4000D000u)
22483/** Peripheral SYSMPU base pointer */
22484#define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE)
22485/** Array initializer of SYSMPU peripheral base addresses */
22486#define SYSMPU_BASE_ADDRS { SYSMPU_BASE }
22487/** Array initializer of SYSMPU peripheral base pointers */
22488#define SYSMPU_BASE_PTRS { SYSMPU }
22489
22490/*!
22491 * @}
22492 */ /* end of group SYSMPU_Peripheral_Access_Layer */
22493
22494
22495/* ----------------------------------------------------------------------------
22496 -- TPM Peripheral Access Layer
22497 ---------------------------------------------------------------------------- */
22498
22499/*!
22500 * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
22501 * @{
22502 */
22503
22504/** TPM - Register Layout Typedef */
22505typedef struct {
22506 __IO uint32_t SC; /**< Status and Control, offset: 0x0 */
22507 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
22508 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
22509 struct { /* offset: 0xC, array step: 0x8 */
22510 __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
22511 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
22512 } CONTROLS[2];
22513 uint8_t RESERVED_0[52];
22514 __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */
22515 uint8_t RESERVED_1[16];
22516 __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */
22517 uint8_t RESERVED_2[8];
22518 __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */
22519 uint8_t RESERVED_3[4];
22520 __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */
22521 uint8_t RESERVED_4[4];
22522 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control and Status, offset: 0x80 */
22523 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
22524} TPM_Type;
22525
22526/* ----------------------------------------------------------------------------
22527 -- TPM Register Masks
22528 ---------------------------------------------------------------------------- */
22529
22530/*!
22531 * @addtogroup TPM_Register_Masks TPM Register Masks
22532 * @{
22533 */
22534
22535/*! @name SC - Status and Control */
22536/*! @{ */
22537#define TPM_SC_PS_MASK (0x7U)
22538#define TPM_SC_PS_SHIFT (0U)
22539/*! PS - Prescale Factor Selection
22540 * 0b000..Divide by 1
22541 * 0b001..Divide by 2
22542 * 0b010..Divide by 4
22543 * 0b011..Divide by 8
22544 * 0b100..Divide by 16
22545 * 0b101..Divide by 32
22546 * 0b110..Divide by 64
22547 * 0b111..Divide by 128
22548 */
22549#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
22550#define TPM_SC_CMOD_MASK (0x18U)
22551#define TPM_SC_CMOD_SHIFT (3U)
22552/*! CMOD - Clock Mode Selection
22553 * 0b00..TPM counter is disabled
22554 * 0b01..TPM counter increments on every TPM counter clock
22555 * 0b10..TPM counter increments on rising edge of TPM_EXTCLK synchronized to the TPM counter clock
22556 * 0b11..Reserved.
22557 */
22558#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
22559#define TPM_SC_CPWMS_MASK (0x20U)
22560#define TPM_SC_CPWMS_SHIFT (5U)
22561/*! CPWMS - Center-Aligned PWM Select
22562 * 0b0..TPM counter operates in up counting mode.
22563 * 0b1..TPM counter operates in up-down counting mode.
22564 */
22565#define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
22566#define TPM_SC_TOIE_MASK (0x40U)
22567#define TPM_SC_TOIE_SHIFT (6U)
22568/*! TOIE - Timer Overflow Interrupt Enable
22569 * 0b0..Disable TOF interrupts. Use software polling or DMA request.
22570 * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
22571 */
22572#define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
22573#define TPM_SC_TOF_MASK (0x80U)
22574#define TPM_SC_TOF_SHIFT (7U)
22575/*! TOF - Timer Overflow Flag
22576 * 0b0..TPM counter has not overflowed.
22577 * 0b1..TPM counter has overflowed.
22578 */
22579#define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
22580#define TPM_SC_DMA_MASK (0x100U)
22581#define TPM_SC_DMA_SHIFT (8U)
22582/*! DMA - DMA Enable
22583 * 0b0..Disables DMA transfers.
22584 * 0b1..Enables DMA transfers.
22585 */
22586#define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
22587/*! @} */
22588
22589/*! @name CNT - Counter */
22590/*! @{ */
22591#define TPM_CNT_COUNT_MASK (0xFFFFU)
22592#define TPM_CNT_COUNT_SHIFT (0U)
22593#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
22594/*! @} */
22595
22596/*! @name MOD - Modulo */
22597/*! @{ */
22598#define TPM_MOD_MOD_MASK (0xFFFFU)
22599#define TPM_MOD_MOD_SHIFT (0U)
22600#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
22601/*! @} */
22602
22603/*! @name CnSC - Channel (n) Status and Control */
22604/*! @{ */
22605#define TPM_CnSC_DMA_MASK (0x1U)
22606#define TPM_CnSC_DMA_SHIFT (0U)
22607/*! DMA - DMA Enable
22608 * 0b0..Disable DMA transfers.
22609 * 0b1..Enable DMA transfers.
22610 */
22611#define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
22612#define TPM_CnSC_ELSA_MASK (0x4U)
22613#define TPM_CnSC_ELSA_SHIFT (2U)
22614#define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
22615#define TPM_CnSC_ELSB_MASK (0x8U)
22616#define TPM_CnSC_ELSB_SHIFT (3U)
22617#define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
22618#define TPM_CnSC_MSA_MASK (0x10U)
22619#define TPM_CnSC_MSA_SHIFT (4U)
22620#define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
22621#define TPM_CnSC_MSB_MASK (0x20U)
22622#define TPM_CnSC_MSB_SHIFT (5U)
22623#define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
22624#define TPM_CnSC_CHIE_MASK (0x40U)
22625#define TPM_CnSC_CHIE_SHIFT (6U)
22626/*! CHIE - Channel Interrupt Enable
22627 * 0b0..Disable channel interrupts.
22628 * 0b1..Enable channel interrupts.
22629 */
22630#define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
22631#define TPM_CnSC_CHF_MASK (0x80U)
22632#define TPM_CnSC_CHF_SHIFT (7U)
22633/*! CHF - Channel Flag
22634 * 0b0..No channel event has occurred.
22635 * 0b1..A channel event has occurred.
22636 */
22637#define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
22638/*! @} */
22639
22640/* The count of TPM_CnSC */
22641#define TPM_CnSC_COUNT (2U)
22642
22643/*! @name CnV - Channel (n) Value */
22644/*! @{ */
22645#define TPM_CnV_VAL_MASK (0xFFFFU)
22646#define TPM_CnV_VAL_SHIFT (0U)
22647#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
22648/*! @} */
22649
22650/* The count of TPM_CnV */
22651#define TPM_CnV_COUNT (2U)
22652
22653/*! @name STATUS - Capture and Compare Status */
22654/*! @{ */
22655#define TPM_STATUS_CH0F_MASK (0x1U)
22656#define TPM_STATUS_CH0F_SHIFT (0U)
22657/*! CH0F - Channel 0 Flag
22658 * 0b0..No channel event has occurred.
22659 * 0b1..A channel event has occurred.
22660 */
22661#define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
22662#define TPM_STATUS_CH1F_MASK (0x2U)
22663#define TPM_STATUS_CH1F_SHIFT (1U)
22664/*! CH1F - Channel 1 Flag
22665 * 0b0..No channel event has occurred.
22666 * 0b1..A channel event has occurred.
22667 */
22668#define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
22669#define TPM_STATUS_TOF_MASK (0x100U)
22670#define TPM_STATUS_TOF_SHIFT (8U)
22671/*! TOF - Timer Overflow Flag
22672 * 0b0..TPM counter has not overflowed.
22673 * 0b1..TPM counter has overflowed.
22674 */
22675#define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
22676/*! @} */
22677
22678/*! @name COMBINE - Combine Channel Register */
22679/*! @{ */
22680#define TPM_COMBINE_COMBINE0_MASK (0x1U)
22681#define TPM_COMBINE_COMBINE0_SHIFT (0U)
22682/*! COMBINE0 - Combine Channels 0 and 1
22683 * 0b0..Channels 0 and 1 are independent.
22684 * 0b1..Channels 0 and 1 are combined.
22685 */
22686#define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
22687#define TPM_COMBINE_COMSWAP0_MASK (0x2U)
22688#define TPM_COMBINE_COMSWAP0_SHIFT (1U)
22689/*! COMSWAP0 - Combine Channel 0 and 1 Swap
22690 * 0b0..Even channel is used for input capture and 1st compare.
22691 * 0b1..Odd channel is used for input capture and 1st compare.
22692 */
22693#define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
22694/*! @} */
22695
22696/*! @name POL - Channel Polarity */
22697/*! @{ */
22698#define TPM_POL_POL0_MASK (0x1U)
22699#define TPM_POL_POL0_SHIFT (0U)
22700/*! POL0 - Channel 0 Polarity
22701 * 0b0..The channel polarity is active high.
22702 * 0b1..The channel polarity is active low.
22703 */
22704#define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
22705#define TPM_POL_POL1_MASK (0x2U)
22706#define TPM_POL_POL1_SHIFT (1U)
22707/*! POL1 - Channel 1 Polarity
22708 * 0b0..The channel polarity is active high.
22709 * 0b1..The channel polarity is active low.
22710 */
22711#define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
22712/*! @} */
22713
22714/*! @name FILTER - Filter Control */
22715/*! @{ */
22716#define TPM_FILTER_CH0FVAL_MASK (0xFU)
22717#define TPM_FILTER_CH0FVAL_SHIFT (0U)
22718#define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
22719#define TPM_FILTER_CH1FVAL_MASK (0xF0U)
22720#define TPM_FILTER_CH1FVAL_SHIFT (4U)
22721#define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
22722/*! @} */
22723
22724/*! @name QDCTRL - Quadrature Decoder Control and Status */
22725/*! @{ */
22726#define TPM_QDCTRL_QUADEN_MASK (0x1U)
22727#define TPM_QDCTRL_QUADEN_SHIFT (0U)
22728/*! QUADEN
22729 * 0b0..Quadrature decoder mode is disabled.
22730 * 0b1..Quadrature decoder mode is enabled.
22731 */
22732#define TPM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
22733#define TPM_QDCTRL_TOFDIR_MASK (0x2U)
22734#define TPM_QDCTRL_TOFDIR_SHIFT (1U)
22735/*! TOFDIR
22736 * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (zero) to its maximum value (MOD register).
22737 * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (zero).
22738 */
22739#define TPM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
22740#define TPM_QDCTRL_QUADIR_MASK (0x4U)
22741#define TPM_QDCTRL_QUADIR_SHIFT (2U)
22742/*! QUADIR - Counter Direction in Quadrature Decode Mode
22743 * 0b0..Counter direction is decreasing (counter decrement).
22744 * 0b1..Counter direction is increasing (counter increment).
22745 */
22746#define TPM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
22747#define TPM_QDCTRL_QUADMODE_MASK (0x8U)
22748#define TPM_QDCTRL_QUADMODE_SHIFT (3U)
22749/*! QUADMODE - Quadrature Decoder Mode
22750 * 0b0..Phase encoding mode.
22751 * 0b1..Count and direction encoding mode.
22752 */
22753#define TPM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
22754/*! @} */
22755
22756/*! @name CONF - Configuration */
22757/*! @{ */
22758#define TPM_CONF_DOZEEN_MASK (0x20U)
22759#define TPM_CONF_DOZEEN_SHIFT (5U)
22760/*! DOZEEN - Doze Enable
22761 * 0b0..Internal TPM counter continues in Doze mode.
22762 * 0b1..Internal TPM counter is paused and does not increment during Doze mode. Trigger inputs and input capture events are also ignored.
22763 */
22764#define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
22765#define TPM_CONF_DBGMODE_MASK (0xC0U)
22766#define TPM_CONF_DBGMODE_SHIFT (6U)
22767/*! DBGMODE - Debug Mode
22768 * 0b00..TPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored.
22769 * 0b11..TPM counter continues in debug mode.
22770 */
22771#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
22772#define TPM_CONF_GTBSYNC_MASK (0x100U)
22773#define TPM_CONF_GTBSYNC_SHIFT (8U)
22774/*! GTBSYNC - Global Time Base Synchronization
22775 * 0b0..Global timebase synchronization disabled.
22776 * 0b1..Global timebase synchronization enabled.
22777 */
22778#define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
22779#define TPM_CONF_GTBEEN_MASK (0x200U)
22780#define TPM_CONF_GTBEEN_SHIFT (9U)
22781/*! GTBEEN - Global time base enable
22782 * 0b0..All channels use the internally generated TPM counter as their timebase
22783 * 0b1..All channels use an externally generated global timebase as their timebase
22784 */
22785#define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
22786#define TPM_CONF_CSOT_MASK (0x10000U)
22787#define TPM_CONF_CSOT_SHIFT (16U)
22788/*! CSOT - Counter Start on Trigger
22789 * 0b0..TPM counter starts to increment immediately, once it is enabled.
22790 * 0b1..TPM counter only starts to increment when it a rising edge on the selected input trigger is detected, after it has been enabled or after it has stopped due to overflow.
22791 */
22792#define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
22793#define TPM_CONF_CSOO_MASK (0x20000U)
22794#define TPM_CONF_CSOO_SHIFT (17U)
22795/*! CSOO - Counter Stop On Overflow
22796 * 0b0..TPM counter continues incrementing or decrementing after overflow
22797 * 0b1..TPM counter stops incrementing or decrementing after overflow.
22798 */
22799#define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
22800#define TPM_CONF_CROT_MASK (0x40000U)
22801#define TPM_CONF_CROT_SHIFT (18U)
22802/*! CROT - Counter Reload On Trigger
22803 * 0b0..Counter is not reloaded due to a rising edge on the selected input trigger
22804 * 0b1..Counter is reloaded when a rising edge is detected on the selected input trigger
22805 */
22806#define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
22807#define TPM_CONF_CPOT_MASK (0x80000U)
22808#define TPM_CONF_CPOT_SHIFT (19U)
22809#define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
22810#define TPM_CONF_TRGPOL_MASK (0x400000U)
22811#define TPM_CONF_TRGPOL_SHIFT (22U)
22812/*! TRGPOL - Trigger Polarity
22813 * 0b0..Trigger is active high.
22814 * 0b1..Trigger is active low.
22815 */
22816#define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
22817#define TPM_CONF_TRGSRC_MASK (0x800000U)
22818#define TPM_CONF_TRGSRC_SHIFT (23U)
22819/*! TRGSRC - Trigger Source
22820 * 0b0..Trigger source selected by TRGSEL is external.
22821 * 0b1..Trigger source selected by TRGSEL is internal (channel pin input capture).
22822 */
22823#define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
22824#define TPM_CONF_TRGSEL_MASK (0xF000000U)
22825#define TPM_CONF_TRGSEL_SHIFT (24U)
22826/*! TRGSEL - Trigger Select
22827 * 0b0001..Channel 0 pin input capture
22828 * 0b0010..Channel 1 pin input capture
22829 * 0b0011..Channel 0 or Channel 1 pin input capture
22830 */
22831#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
22832/*! @} */
22833
22834
22835/*!
22836 * @}
22837 */ /* end of group TPM_Register_Masks */
22838
22839
22840/* TPM - Peripheral instance base addresses */
22841/** Peripheral TPM1 base address */
22842#define TPM1_BASE (0x400C9000u)
22843/** Peripheral TPM1 base pointer */
22844#define TPM1 ((TPM_Type *)TPM1_BASE)
22845/** Peripheral TPM2 base address */
22846#define TPM2_BASE (0x400CA000u)
22847/** Peripheral TPM2 base pointer */
22848#define TPM2 ((TPM_Type *)TPM2_BASE)
22849/** Array initializer of TPM peripheral base addresses */
22850#define TPM_BASE_ADDRS { 0u, TPM1_BASE, TPM2_BASE }
22851/** Array initializer of TPM peripheral base pointers */
22852#define TPM_BASE_PTRS { (TPM_Type *)0u, TPM1, TPM2 }
22853/** Interrupt vectors for the TPM peripheral type */
22854#define TPM_IRQS { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn }
22855
22856/*!
22857 * @}
22858 */ /* end of group TPM_Peripheral_Access_Layer */
22859
22860
22861/* ----------------------------------------------------------------------------
22862 -- TSI Peripheral Access Layer
22863 ---------------------------------------------------------------------------- */
22864
22865/*!
22866 * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
22867 * @{
22868 */
22869
22870/** TSI - Register Layout Typedef */
22871typedef struct {
22872 __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */
22873 __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */
22874 __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */
22875} TSI_Type;
22876
22877/* ----------------------------------------------------------------------------
22878 -- TSI Register Masks
22879 ---------------------------------------------------------------------------- */
22880
22881/*!
22882 * @addtogroup TSI_Register_Masks TSI Register Masks
22883 * @{
22884 */
22885
22886/*! @name GENCS - TSI General Control and Status Register */
22887/*! @{ */
22888#define TSI_GENCS_EOSDMEO_MASK (0x1U)
22889#define TSI_GENCS_EOSDMEO_SHIFT (0U)
22890/*! EOSDMEO - End-of-Scan DMA Transfer Request Enable Only
22891 * 0b0..Do not enable the End-of-Scan DMA transfer request only. Depending on ESOR state, either Out-of-Range or End-of-Scan can trigger a DMA transfer request and interrupt.
22892 * 0b1..Only the End-of-Scan event can trigger a DMA transfer request. The Out-of-Range event only and always triggers an interrupt if TSIIE is set.
22893 */
22894#define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
22895#define TSI_GENCS_CURSW_MASK (0x2U)
22896#define TSI_GENCS_CURSW_SHIFT (1U)
22897/*! CURSW - CURSW
22898 * 0b0..The current source pair are not swapped.
22899 * 0b1..The current source pair are swapped.
22900 */
22901#define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
22902#define TSI_GENCS_EOSF_MASK (0x4U)
22903#define TSI_GENCS_EOSF_SHIFT (2U)
22904/*! EOSF - End of Scan Flag
22905 * 0b0..Scan not complete.
22906 * 0b1..Scan complete.
22907 */
22908#define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
22909#define TSI_GENCS_SCNIP_MASK (0x8U)
22910#define TSI_GENCS_SCNIP_SHIFT (3U)
22911/*! SCNIP - Scan In Progress Status
22912 * 0b0..No scan in progress.
22913 * 0b1..Scan in progress.
22914 */
22915#define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
22916#define TSI_GENCS_STM_MASK (0x10U)
22917#define TSI_GENCS_STM_SHIFT (4U)
22918/*! STM - Scan Trigger Mode
22919 * 0b0..Software trigger scan.
22920 * 0b1..Hardware trigger scan.
22921 */
22922#define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
22923#define TSI_GENCS_STPE_MASK (0x20U)
22924#define TSI_GENCS_STPE_SHIFT (5U)
22925/*! STPE - TSI STOP Enable
22926 * 0b0..TSI is disabled when MCU goes into low power mode.
22927 * 0b1..Allows TSI to continue running in all low power modes.
22928 */
22929#define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
22930#define TSI_GENCS_TSIIEN_MASK (0x40U)
22931#define TSI_GENCS_TSIIEN_SHIFT (6U)
22932/*! TSIIEN - Touch Sensing Input Interrupt Enable
22933 * 0b0..TSI interrupt is disabled.
22934 * 0b1..TSI interrupt is enabled.
22935 */
22936#define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
22937#define TSI_GENCS_TSIEN_MASK (0x80U)
22938#define TSI_GENCS_TSIEN_SHIFT (7U)
22939/*! TSIEN - Touch Sensing Input Module Enable
22940 * 0b0..TSI module disabled.
22941 * 0b1..TSI module enabled.
22942 */
22943#define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
22944#define TSI_GENCS_NSCN_MASK (0x1F00U)
22945#define TSI_GENCS_NSCN_SHIFT (8U)
22946/*! NSCN - NSCN
22947 * 0b00000..Once per electrode
22948 * 0b00001..Twice per electrode
22949 * 0b00010..3 times per electrode
22950 * 0b00011..4 times per electrode
22951 * 0b00100..5 times per electrode
22952 * 0b00101..6 times per electrode
22953 * 0b00110..7 times per electrode
22954 * 0b00111..8 times per electrode
22955 * 0b01000..9 times per electrode
22956 * 0b01001..10 times per electrode
22957 * 0b01010..11 times per electrode
22958 * 0b01011..12 times per electrode
22959 * 0b01100..13 times per electrode
22960 * 0b01101..14 times per electrode
22961 * 0b01110..15 times per electrode
22962 * 0b01111..16 times per electrode
22963 * 0b10000..17 times per electrode
22964 * 0b10001..18 times per electrode
22965 * 0b10010..19 times per electrode
22966 * 0b10011..20 times per electrode
22967 * 0b10100..21 times per electrode
22968 * 0b10101..22 times per electrode
22969 * 0b10110..23 times per electrode
22970 * 0b10111..24 times per electrode
22971 * 0b11000..25 times per electrode
22972 * 0b11001..26 times per electrode
22973 * 0b11010..27 times per electrode
22974 * 0b11011..28 times per electrode
22975 * 0b11100..29 times per electrode
22976 * 0b11101..30 times per electrode
22977 * 0b11110..31 times per electrode
22978 * 0b11111..32 times per electrode
22979 */
22980#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
22981#define TSI_GENCS_PS_MASK (0xE000U)
22982#define TSI_GENCS_PS_SHIFT (13U)
22983/*! PS - PS
22984 * 0b000..Electrode Oscillator Frequency divided by 1
22985 * 0b001..Electrode Oscillator Frequency divided by 2
22986 * 0b010..Electrode Oscillator Frequency divided by 4
22987 * 0b011..Electrode Oscillator Frequency divided by 8
22988 * 0b100..Electrode Oscillator Frequency divided by 16
22989 * 0b101..Electrode Oscillator Frequency divided by 32
22990 * 0b110..Electrode Oscillator Frequency divided by 64
22991 * 0b111..Electrode Oscillator Frequency divided by 128
22992 */
22993#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
22994#define TSI_GENCS_EXTCHRG_MASK (0x70000U)
22995#define TSI_GENCS_EXTCHRG_SHIFT (16U)
22996/*! EXTCHRG - EXTCHRG
22997 * 0b000..500 nA.
22998 * 0b001..1 uA.
22999 * 0b010..2 uA.
23000 * 0b011..4 uA.
23001 * 0b100..8 uA.
23002 * 0b101..16 uA.
23003 * 0b110..32 uA.
23004 * 0b111..64 uA.
23005 */
23006#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
23007#define TSI_GENCS_DVOLT_MASK (0x180000U)
23008#define TSI_GENCS_DVOLT_SHIFT (19U)
23009/*! DVOLT - DVOLT
23010 * 0b00..DV = 1.026 V; VP = 1.328 V; Vm = 0.302 V.
23011 * 0b01..DV = 0.592 V; VP = 1.111 V; Vm = 0.519 V.
23012 * 0b10..DV = 0.342 V; VP = 0.986 V; Vm = 0.644 V.
23013 * 0b11..DV = 0.197 V; VP = 0.914 V; Vm = 0.716 V.
23014 */
23015#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
23016#define TSI_GENCS_REFCHRG_MASK (0xE00000U)
23017#define TSI_GENCS_REFCHRG_SHIFT (21U)
23018/*! REFCHRG - REFCHRG
23019 * 0b000..500 nA.
23020 * 0b001..1 uA.
23021 * 0b010..2 uA.
23022 * 0b011..4 uA.
23023 * 0b100..8 uA.
23024 * 0b101..16 uA.
23025 * 0b110..32 uA.
23026 * 0b111..64 uA.
23027 */
23028#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
23029#define TSI_GENCS_MODE_MASK (0xF000000U)
23030#define TSI_GENCS_MODE_SHIFT (24U)
23031/*! MODE - TSI analog modes setup and status bits.
23032 * 0b0000..Set TSI in capacitive sensing(non-noise detection) mode.
23033 * 0b0100..Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is disabled.
23034 * 0b1000..Set TSI analog to work in single threshold noise detection mode and the frequency limitation circuit is enabled to work in higher frequencies operations.
23035 * 0b1100..Set TSI analog to work in automatic noise detection mode.
23036 */
23037#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
23038#define TSI_GENCS_ESOR_MASK (0x10000000U)
23039#define TSI_GENCS_ESOR_SHIFT (28U)
23040/*! ESOR - End-of-scan or Out-of-Range Interrupt Selection
23041 * 0b0..Out-of-range interrupt is allowed.
23042 * 0b1..End-of-scan interrupt is allowed.
23043 */
23044#define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
23045#define TSI_GENCS_OUTRGF_MASK (0x80000000U)
23046#define TSI_GENCS_OUTRGF_SHIFT (31U)
23047#define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
23048/*! @} */
23049
23050/*! @name DATA - TSI DATA Register */
23051/*! @{ */
23052#define TSI_DATA_TSICNT_MASK (0xFFFFU)
23053#define TSI_DATA_TSICNT_SHIFT (0U)
23054#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
23055#define TSI_DATA_SWTS_MASK (0x400000U)
23056#define TSI_DATA_SWTS_SHIFT (22U)
23057/*! SWTS - Software Trigger Start
23058 * 0b0..No effect.
23059 * 0b1..Start a scan to determine which channel is specified by TSI_DATA[TSICH].
23060 */
23061#define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
23062#define TSI_DATA_DMAEN_MASK (0x800000U)
23063#define TSI_DATA_DMAEN_SHIFT (23U)
23064/*! DMAEN - DMA Transfer Enabled
23065 * 0b0..Interrupt is selected when the interrupt enable bit is set and the corresponding TSI events assert.
23066 * 0b1..DMA transfer request is selected when the interrupt enable bit is set and the corresponding TSI events assert.
23067 */
23068#define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
23069#define TSI_DATA_TSICH_MASK (0xF0000000U)
23070#define TSI_DATA_TSICH_SHIFT (28U)
23071/*! TSICH - TSICH
23072 * 0b0000..Channel 0.
23073 * 0b0001..Channel 1.
23074 * 0b0010..Channel 2.
23075 * 0b0011..Channel 3.
23076 * 0b0100..Channel 4.
23077 * 0b0101..Channel 5.
23078 * 0b0110..Channel 6.
23079 * 0b0111..Channel 7.
23080 * 0b1000..Channel 8.
23081 * 0b1001..Channel 9.
23082 * 0b1010..Channel 10.
23083 * 0b1011..Channel 11.
23084 * 0b1100..Channel 12.
23085 * 0b1101..Channel 13.
23086 * 0b1110..Channel 14.
23087 * 0b1111..Channel 15.
23088 */
23089#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
23090/*! @} */
23091
23092/*! @name TSHD - TSI Threshold Register */
23093/*! @{ */
23094#define TSI_TSHD_THRESL_MASK (0xFFFFU)
23095#define TSI_TSHD_THRESL_SHIFT (0U)
23096#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
23097#define TSI_TSHD_THRESH_MASK (0xFFFF0000U)
23098#define TSI_TSHD_THRESH_SHIFT (16U)
23099#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
23100/*! @} */
23101
23102
23103/*!
23104 * @}
23105 */ /* end of group TSI_Register_Masks */
23106
23107
23108/* TSI - Peripheral instance base addresses */
23109/** Peripheral TSI0 base address */
23110#define TSI0_BASE (0x40045000u)
23111/** Peripheral TSI0 base pointer */
23112#define TSI0 ((TSI_Type *)TSI0_BASE)
23113/** Array initializer of TSI peripheral base addresses */
23114#define TSI_BASE_ADDRS { TSI0_BASE }
23115/** Array initializer of TSI peripheral base pointers */
23116#define TSI_BASE_PTRS { TSI0 }
23117/** Interrupt vectors for the TSI peripheral type */
23118#define TSI_IRQS { TSI0_IRQn }
23119
23120/*!
23121 * @}
23122 */ /* end of group TSI_Peripheral_Access_Layer */
23123
23124
23125/* ----------------------------------------------------------------------------
23126 -- UART Peripheral Access Layer
23127 ---------------------------------------------------------------------------- */
23128
23129/*!
23130 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
23131 * @{
23132 */
23133
23134/** UART - Register Layout Typedef */
23135typedef struct {
23136 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
23137 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
23138 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
23139 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
23140 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
23141 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
23142 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
23143 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
23144 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
23145 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
23146 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
23147 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
23148 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
23149 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
23150 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
23151 uint8_t RESERVED_0[1];
23152 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
23153 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
23154 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
23155 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
23156 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
23157 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
23158 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
23159 uint8_t RESERVED_1[1];
23160 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
23161 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
23162 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
23163 __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
23164 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
23165 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
23166 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
23167 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
23168 uint8_t RESERVED_2[26];
23169 __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
23170 __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
23171 union { /* offset: 0x3C */
23172 struct { /* offset: 0x3C */
23173 __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
23174 __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
23175 } TYPE0;
23176 struct { /* offset: 0x3C */
23177 __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
23178 __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
23179 } TYPE1;
23180 };
23181 __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
23182 __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
23183} UART_Type;
23184
23185/* ----------------------------------------------------------------------------
23186 -- UART Register Masks
23187 ---------------------------------------------------------------------------- */
23188
23189/*!
23190 * @addtogroup UART_Register_Masks UART Register Masks
23191 * @{
23192 */
23193
23194/*! @name BDH - UART Baud Rate Registers: High */
23195/*! @{ */
23196#define UART_BDH_SBR_MASK (0x1FU)
23197#define UART_BDH_SBR_SHIFT (0U)
23198#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
23199#define UART_BDH_SBNS_MASK (0x20U)
23200#define UART_BDH_SBNS_SHIFT (5U)
23201/*! SBNS - Stop Bit Number Select
23202 * 0b0..Data frame consists of a single stop bit.
23203 * 0b1..Data frame consists of two stop bits.
23204 */
23205#define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
23206#define UART_BDH_RXEDGIE_MASK (0x40U)
23207#define UART_BDH_RXEDGIE_SHIFT (6U)
23208/*! RXEDGIE - RxD Input Active Edge Interrupt Enable
23209 * 0b0..Hardware interrupts from RXEDGIF disabled using polling.
23210 * 0b1..RXEDGIF interrupt request enabled.
23211 */
23212#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
23213#define UART_BDH_LBKDIE_MASK (0x80U)
23214#define UART_BDH_LBKDIE_SHIFT (7U)
23215/*! LBKDIE - LIN Break Detect Interrupt Enable
23216 * 0b0..LBKDIF interrupt requests disabled.
23217 * 0b1..LBKDIF interrupt requests enabled.
23218 */
23219#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
23220/*! @} */
23221
23222/*! @name BDL - UART Baud Rate Registers: Low */
23223/*! @{ */
23224#define UART_BDL_SBR_MASK (0xFFU)
23225#define UART_BDL_SBR_SHIFT (0U)
23226#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
23227/*! @} */
23228
23229/*! @name C1 - UART Control Register 1 */
23230/*! @{ */
23231#define UART_C1_PT_MASK (0x1U)
23232#define UART_C1_PT_SHIFT (0U)
23233/*! PT - Parity Type
23234 * 0b0..Even parity.
23235 * 0b1..Odd parity.
23236 */
23237#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
23238#define UART_C1_PE_MASK (0x2U)
23239#define UART_C1_PE_SHIFT (1U)
23240/*! PE - Parity Enable
23241 * 0b0..Parity function disabled.
23242 * 0b1..Parity function enabled.
23243 */
23244#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
23245#define UART_C1_ILT_MASK (0x4U)
23246#define UART_C1_ILT_SHIFT (2U)
23247/*! ILT - Idle Line Type Select
23248 * 0b0..Idle character bit count starts after start bit.
23249 * 0b1..Idle character bit count starts after stop bit.
23250 */
23251#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
23252#define UART_C1_WAKE_MASK (0x8U)
23253#define UART_C1_WAKE_SHIFT (3U)
23254/*! WAKE - Receiver Wakeup Method Select
23255 * 0b0..Idle line wakeup.
23256 * 0b1..Address mark wakeup.
23257 */
23258#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
23259#define UART_C1_M_MASK (0x10U)
23260#define UART_C1_M_SHIFT (4U)
23261/*! M - 9-bit or 8-bit Mode Select
23262 * 0b0..Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
23263 * 0b1..Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
23264 */
23265#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
23266#define UART_C1_RSRC_MASK (0x20U)
23267#define UART_C1_RSRC_SHIFT (5U)
23268/*! RSRC - Receiver Source Select
23269 * 0b0..Selects internal loop back mode. The receiver input is internally connected to transmitter output.
23270 * 0b1..Single wire UART mode where the receiver input is connected to the transmit pin input signal.
23271 */
23272#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
23273#define UART_C1_UARTSWAI_MASK (0x40U)
23274#define UART_C1_UARTSWAI_SHIFT (6U)
23275/*! UARTSWAI - UART Stops in Wait Mode
23276 * 0b0..UART clock continues to run in Wait mode.
23277 * 0b1..UART clock freezes while CPU is in Wait mode.
23278 */
23279#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
23280#define UART_C1_LOOPS_MASK (0x80U)
23281#define UART_C1_LOOPS_SHIFT (7U)
23282/*! LOOPS - Loop Mode Select
23283 * 0b0..Normal operation.
23284 * 0b1..Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
23285 */
23286#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
23287/*! @} */
23288
23289/*! @name C2 - UART Control Register 2 */
23290/*! @{ */
23291#define UART_C2_SBK_MASK (0x1U)
23292#define UART_C2_SBK_SHIFT (0U)
23293/*! SBK - Send Break
23294 * 0b0..Normal transmitter operation.
23295 * 0b1..Queue break characters to be sent.
23296 */
23297#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
23298#define UART_C2_RWU_MASK (0x2U)
23299#define UART_C2_RWU_SHIFT (1U)
23300/*! RWU - Receiver Wakeup Control
23301 * 0b0..Normal operation.
23302 * 0b1..RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
23303 */
23304#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
23305#define UART_C2_RE_MASK (0x4U)
23306#define UART_C2_RE_SHIFT (2U)
23307/*! RE - Receiver Enable
23308 * 0b0..Receiver off.
23309 * 0b1..Receiver on.
23310 */
23311#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
23312#define UART_C2_TE_MASK (0x8U)
23313#define UART_C2_TE_SHIFT (3U)
23314/*! TE - Transmitter Enable
23315 * 0b0..Transmitter off.
23316 * 0b1..Transmitter on.
23317 */
23318#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
23319#define UART_C2_ILIE_MASK (0x10U)
23320#define UART_C2_ILIE_SHIFT (4U)
23321/*! ILIE - Idle Line Interrupt Enable
23322 * 0b0..IDLE interrupt requests disabled.
23323 * 0b1..IDLE interrupt requests enabled.
23324 */
23325#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
23326#define UART_C2_RIE_MASK (0x20U)
23327#define UART_C2_RIE_SHIFT (5U)
23328/*! RIE - Receiver Full Interrupt or DMA Transfer Enable
23329 * 0b0..RDRF interrupt and DMA transfer requests disabled.
23330 * 0b1..RDRF interrupt or DMA transfer requests enabled.
23331 */
23332#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
23333#define UART_C2_TCIE_MASK (0x40U)
23334#define UART_C2_TCIE_SHIFT (6U)
23335/*! TCIE - Transmission Complete Interrupt Enable
23336 * 0b0..TC interrupt requests disabled.
23337 * 0b1..TC interrupt requests enabled.
23338 */
23339#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
23340#define UART_C2_TIE_MASK (0x80U)
23341#define UART_C2_TIE_SHIFT (7U)
23342/*! TIE - Transmitter Interrupt or DMA Transfer Enable.
23343 * 0b0..TDRE interrupt and DMA transfer requests disabled.
23344 * 0b1..TDRE interrupt or DMA transfer requests enabled.
23345 */
23346#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
23347/*! @} */
23348
23349/*! @name S1 - UART Status Register 1 */
23350/*! @{ */
23351#define UART_S1_PF_MASK (0x1U)
23352#define UART_S1_PF_SHIFT (0U)
23353/*! PF - Parity Error Flag
23354 * 0b0..No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
23355 * 0b1..At least one dataword was received with a parity error since the last time this flag was cleared.
23356 */
23357#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
23358#define UART_S1_FE_MASK (0x2U)
23359#define UART_S1_FE_SHIFT (1U)
23360/*! FE - Framing Error Flag
23361 * 0b0..No framing error detected.
23362 * 0b1..Framing error.
23363 */
23364#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
23365#define UART_S1_NF_MASK (0x4U)
23366#define UART_S1_NF_SHIFT (2U)
23367/*! NF - Noise Flag
23368 * 0b0..No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
23369 * 0b1..At least one dataword was received with noise detected since the last time the flag was cleared.
23370 */
23371#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
23372#define UART_S1_OR_MASK (0x8U)
23373#define UART_S1_OR_SHIFT (3U)
23374/*! OR - Receiver Overrun Flag
23375 * 0b0..No overrun has occurred since the last time the flag was cleared.
23376 * 0b1..Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
23377 */
23378#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
23379#define UART_S1_IDLE_MASK (0x10U)
23380#define UART_S1_IDLE_SHIFT (4U)
23381/*! IDLE - Idle Line Flag
23382 * 0b0..Receiver input is either active now or has never become active since the IDLE flag was last cleared.
23383 * 0b1..Receiver input has become idle or the flag has not been cleared since it last asserted.
23384 */
23385#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
23386#define UART_S1_RDRF_MASK (0x20U)
23387#define UART_S1_RDRF_SHIFT (5U)
23388/*! RDRF - Receive Data Register Full Flag
23389 * 0b0..The number of datawords in the receive buffer is less than the number indicated by RXWATER.
23390 * 0b1..The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
23391 */
23392#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
23393#define UART_S1_TC_MASK (0x40U)
23394#define UART_S1_TC_SHIFT (6U)
23395/*! TC - Transmit Complete Flag
23396 * 0b0..Transmitter active (sending data, a preamble, or a break).
23397 * 0b1..Transmitter idle (transmission activity complete).
23398 */
23399#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
23400#define UART_S1_TDRE_MASK (0x80U)
23401#define UART_S1_TDRE_SHIFT (7U)
23402/*! TDRE - Transmit Data Register Empty Flag
23403 * 0b0..The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
23404 * 0b1..The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
23405 */
23406#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
23407/*! @} */
23408
23409/*! @name S2 - UART Status Register 2 */
23410/*! @{ */
23411#define UART_S2_RAF_MASK (0x1U)
23412#define UART_S2_RAF_SHIFT (0U)
23413/*! RAF - Receiver Active Flag
23414 * 0b0..UART receiver idle/inactive waiting for a start bit.
23415 * 0b1..UART receiver active, RxD input not idle.
23416 */
23417#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
23418#define UART_S2_LBKDE_MASK (0x2U)
23419#define UART_S2_LBKDE_SHIFT (1U)
23420/*! LBKDE - LIN Break Detection Enable
23421 * 0b0..Break character detection is disabled.
23422 * 0b1..Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.
23423 */
23424#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
23425#define UART_S2_BRK13_MASK (0x4U)
23426#define UART_S2_BRK13_SHIFT (2U)
23427/*! BRK13 - Break Transmit Character Length
23428 * 0b0..Break character is 10, 11, or 12 bits long.
23429 * 0b1..Break character is 13 or 14 bits long.
23430 */
23431#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
23432#define UART_S2_RWUID_MASK (0x8U)
23433#define UART_S2_RWUID_SHIFT (3U)
23434/*! RWUID - Receive Wakeup Idle Detect
23435 * 0b0..S1[IDLE] is not set upon detection of an idle character.
23436 * 0b1..S1[IDLE] is set upon detection of an idle character.
23437 */
23438#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
23439#define UART_S2_RXINV_MASK (0x10U)
23440#define UART_S2_RXINV_SHIFT (4U)
23441/*! RXINV - Receive Data Inversion
23442 * 0b0..Receive data is not inverted.
23443 * 0b1..Receive data is inverted.
23444 */
23445#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
23446#define UART_S2_MSBF_MASK (0x20U)
23447#define UART_S2_MSBF_SHIFT (5U)
23448/*! MSBF - Most Significant Bit First
23449 * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
23450 * 0b1..MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
23451 */
23452#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
23453#define UART_S2_RXEDGIF_MASK (0x40U)
23454#define UART_S2_RXEDGIF_SHIFT (6U)
23455/*! RXEDGIF - RxD Pin Active Edge Interrupt Flag
23456 * 0b0..No active edge on the receive pin has occurred.
23457 * 0b1..An active edge on the receive pin has occurred.
23458 */
23459#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
23460#define UART_S2_LBKDIF_MASK (0x80U)
23461#define UART_S2_LBKDIF_SHIFT (7U)
23462/*! LBKDIF - LIN Break Detect Interrupt Flag
23463 * 0b0..No LIN break character detected.
23464 * 0b1..LIN break character detected.
23465 */
23466#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
23467/*! @} */
23468
23469/*! @name C3 - UART Control Register 3 */
23470/*! @{ */
23471#define UART_C3_PEIE_MASK (0x1U)
23472#define UART_C3_PEIE_SHIFT (0U)
23473/*! PEIE - Parity Error Interrupt Enable
23474 * 0b0..PF interrupt requests are disabled.
23475 * 0b1..PF interrupt requests are enabled.
23476 */
23477#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
23478#define UART_C3_FEIE_MASK (0x2U)
23479#define UART_C3_FEIE_SHIFT (1U)
23480/*! FEIE - Framing Error Interrupt Enable
23481 * 0b0..FE interrupt requests are disabled.
23482 * 0b1..FE interrupt requests are enabled.
23483 */
23484#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
23485#define UART_C3_NEIE_MASK (0x4U)
23486#define UART_C3_NEIE_SHIFT (2U)
23487/*! NEIE - Noise Error Interrupt Enable
23488 * 0b0..NF interrupt requests are disabled.
23489 * 0b1..NF interrupt requests are enabled.
23490 */
23491#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
23492#define UART_C3_ORIE_MASK (0x8U)
23493#define UART_C3_ORIE_SHIFT (3U)
23494/*! ORIE - Overrun Error Interrupt Enable
23495 * 0b0..OR interrupts are disabled.
23496 * 0b1..OR interrupt requests are enabled.
23497 */
23498#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
23499#define UART_C3_TXINV_MASK (0x10U)
23500#define UART_C3_TXINV_SHIFT (4U)
23501/*! TXINV - Transmit Data Inversion.
23502 * 0b0..Transmit data is not inverted.
23503 * 0b1..Transmit data is inverted.
23504 */
23505#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
23506#define UART_C3_TXDIR_MASK (0x20U)
23507#define UART_C3_TXDIR_SHIFT (5U)
23508/*! TXDIR - Transmitter Pin Data Direction in Single-Wire mode
23509 * 0b0..TXD pin is an input in single wire mode.
23510 * 0b1..TXD pin is an output in single wire mode.
23511 */
23512#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
23513#define UART_C3_T8_MASK (0x40U)
23514#define UART_C3_T8_SHIFT (6U)
23515#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
23516#define UART_C3_R8_MASK (0x80U)
23517#define UART_C3_R8_SHIFT (7U)
23518#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
23519/*! @} */
23520
23521/*! @name D - UART Data Register */
23522/*! @{ */
23523#define UART_D_RT_MASK (0xFFU)
23524#define UART_D_RT_SHIFT (0U)
23525#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
23526/*! @} */
23527
23528/*! @name MA1 - UART Match Address Registers 1 */
23529/*! @{ */
23530#define UART_MA1_MA_MASK (0xFFU)
23531#define UART_MA1_MA_SHIFT (0U)
23532#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
23533/*! @} */
23534
23535/*! @name MA2 - UART Match Address Registers 2 */
23536/*! @{ */
23537#define UART_MA2_MA_MASK (0xFFU)
23538#define UART_MA2_MA_SHIFT (0U)
23539#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
23540/*! @} */
23541
23542/*! @name C4 - UART Control Register 4 */
23543/*! @{ */
23544#define UART_C4_BRFA_MASK (0x1FU)
23545#define UART_C4_BRFA_SHIFT (0U)
23546#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
23547#define UART_C4_M10_MASK (0x20U)
23548#define UART_C4_M10_SHIFT (5U)
23549/*! M10 - 10-bit Mode select
23550 * 0b0..The parity bit is the ninth bit in the serial transmission.
23551 * 0b1..The parity bit is the tenth bit in the serial transmission.
23552 */
23553#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
23554#define UART_C4_MAEN2_MASK (0x40U)
23555#define UART_C4_MAEN2_SHIFT (6U)
23556/*! MAEN2 - Match Address Mode Enable 2
23557 * 0b0..All data received is transferred to the data buffer if MAEN1 is cleared.
23558 * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
23559 */
23560#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
23561#define UART_C4_MAEN1_MASK (0x80U)
23562#define UART_C4_MAEN1_SHIFT (7U)
23563/*! MAEN1 - Match Address Mode Enable 1
23564 * 0b0..All data received is transferred to the data buffer if MAEN2 is cleared.
23565 * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
23566 */
23567#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
23568/*! @} */
23569
23570/*! @name C5 - UART Control Register 5 */
23571/*! @{ */
23572#define UART_C5_RDMAS_MASK (0x20U)
23573#define UART_C5_RDMAS_SHIFT (5U)
23574/*! RDMAS - Receiver Full DMA Select
23575 * 0b0..If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
23576 * 0b1..If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
23577 */
23578#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
23579#define UART_C5_TDMAS_MASK (0x80U)
23580#define UART_C5_TDMAS_SHIFT (7U)
23581/*! TDMAS - Transmitter DMA Select
23582 * 0b0..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
23583 * 0b1..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
23584 */
23585#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
23586/*! @} */
23587
23588/*! @name ED - UART Extended Data Register */
23589/*! @{ */
23590#define UART_ED_PARITYE_MASK (0x40U)
23591#define UART_ED_PARITYE_SHIFT (6U)
23592/*! PARITYE
23593 * 0b0..The dataword was received without a parity error.
23594 * 0b1..The dataword was received with a parity error.
23595 */
23596#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
23597#define UART_ED_NOISY_MASK (0x80U)
23598#define UART_ED_NOISY_SHIFT (7U)
23599/*! NOISY
23600 * 0b0..The dataword was received without noise.
23601 * 0b1..The data was received with noise.
23602 */
23603#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
23604/*! @} */
23605
23606/*! @name MODEM - UART Modem Register */
23607/*! @{ */
23608#define UART_MODEM_TXCTSE_MASK (0x1U)
23609#define UART_MODEM_TXCTSE_SHIFT (0U)
23610/*! TXCTSE - Transmitter clear-to-send enable
23611 * 0b0..CTS has no effect on the transmitter.
23612 * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
23613 */
23614#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
23615#define UART_MODEM_TXRTSE_MASK (0x2U)
23616#define UART_MODEM_TXRTSE_SHIFT (1U)
23617/*! TXRTSE - Transmitter request-to-send enable
23618 * 0b0..The transmitter has no effect on RTS.
23619 * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
23620 */
23621#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
23622#define UART_MODEM_TXRTSPOL_MASK (0x4U)
23623#define UART_MODEM_TXRTSPOL_SHIFT (2U)
23624/*! TXRTSPOL - Transmitter request-to-send polarity
23625 * 0b0..Transmitter RTS is active low.
23626 * 0b1..Transmitter RTS is active high.
23627 */
23628#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
23629#define UART_MODEM_RXRTSE_MASK (0x8U)
23630#define UART_MODEM_RXRTSE_SHIFT (3U)
23631/*! RXRTSE - Receiver request-to-send enable
23632 * 0b0..The receiver has no effect on RTS.
23633 * 0b1..RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. See Hardware flow control
23634 */
23635#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
23636/*! @} */
23637
23638/*! @name IR - UART Infrared Register */
23639/*! @{ */
23640#define UART_IR_TNP_MASK (0x3U)
23641#define UART_IR_TNP_SHIFT (0U)
23642/*! TNP - Transmitter narrow pulse
23643 * 0b00..3/16.
23644 * 0b01..1/16.
23645 * 0b10..1/32.
23646 * 0b11..1/4.
23647 */
23648#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
23649#define UART_IR_IREN_MASK (0x4U)
23650#define UART_IR_IREN_SHIFT (2U)
23651/*! IREN - Infrared enable
23652 * 0b0..IR disabled.
23653 * 0b1..IR enabled.
23654 */
23655#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
23656/*! @} */
23657
23658/*! @name PFIFO - UART FIFO Parameters */
23659/*! @{ */
23660#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
23661#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
23662/*! RXFIFOSIZE - Receive FIFO. Buffer Depth
23663 * 0b000..Receive FIFO/Buffer depth = 1 dataword.
23664 * 0b001..Receive FIFO/Buffer depth = 4 datawords.
23665 * 0b010..Receive FIFO/Buffer depth = 8 datawords.
23666 * 0b011..Receive FIFO/Buffer depth = 16 datawords.
23667 * 0b100..Receive FIFO/Buffer depth = 32 datawords.
23668 * 0b101..Receive FIFO/Buffer depth = 64 datawords.
23669 * 0b110..Receive FIFO/Buffer depth = 128 datawords.
23670 * 0b111..Reserved.
23671 */
23672#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
23673#define UART_PFIFO_RXFE_MASK (0x8U)
23674#define UART_PFIFO_RXFE_SHIFT (3U)
23675/*! RXFE - Receive FIFO Enable
23676 * 0b0..Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
23677 * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
23678 */
23679#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
23680#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
23681#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
23682/*! TXFIFOSIZE - Transmit FIFO. Buffer Depth
23683 * 0b000..Transmit FIFO/Buffer depth = 1 dataword.
23684 * 0b001..Transmit FIFO/Buffer depth = 4 datawords.
23685 * 0b010..Transmit FIFO/Buffer depth = 8 datawords.
23686 * 0b011..Transmit FIFO/Buffer depth = 16 datawords.
23687 * 0b100..Transmit FIFO/Buffer depth = 32 datawords.
23688 * 0b101..Transmit FIFO/Buffer depth = 64 datawords.
23689 * 0b110..Transmit FIFO/Buffer depth = 128 datawords.
23690 * 0b111..Reserved.
23691 */
23692#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
23693#define UART_PFIFO_TXFE_MASK (0x80U)
23694#define UART_PFIFO_TXFE_SHIFT (7U)
23695/*! TXFE - Transmit FIFO Enable
23696 * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
23697 * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
23698 */
23699#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
23700/*! @} */
23701
23702/*! @name CFIFO - UART FIFO Control Register */
23703/*! @{ */
23704#define UART_CFIFO_RXUFE_MASK (0x1U)
23705#define UART_CFIFO_RXUFE_SHIFT (0U)
23706/*! RXUFE - Receive FIFO Underflow Interrupt Enable
23707 * 0b0..RXUF flag does not generate an interrupt to the host.
23708 * 0b1..RXUF flag generates an interrupt to the host.
23709 */
23710#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
23711#define UART_CFIFO_TXOFE_MASK (0x2U)
23712#define UART_CFIFO_TXOFE_SHIFT (1U)
23713/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
23714 * 0b0..TXOF flag does not generate an interrupt to the host.
23715 * 0b1..TXOF flag generates an interrupt to the host.
23716 */
23717#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
23718#define UART_CFIFO_RXOFE_MASK (0x4U)
23719#define UART_CFIFO_RXOFE_SHIFT (2U)
23720/*! RXOFE - Receive FIFO Overflow Interrupt Enable
23721 * 0b0..RXOF flag does not generate an interrupt to the host.
23722 * 0b1..RXOF flag generates an interrupt to the host.
23723 */
23724#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
23725#define UART_CFIFO_RXFLUSH_MASK (0x40U)
23726#define UART_CFIFO_RXFLUSH_SHIFT (6U)
23727/*! RXFLUSH - Receive FIFO/Buffer Flush
23728 * 0b0..No flush operation occurs.
23729 * 0b1..All data in the receive FIFO/buffer is cleared out.
23730 */
23731#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
23732#define UART_CFIFO_TXFLUSH_MASK (0x80U)
23733#define UART_CFIFO_TXFLUSH_SHIFT (7U)
23734/*! TXFLUSH - Transmit FIFO/Buffer Flush
23735 * 0b0..No flush operation occurs.
23736 * 0b1..All data in the transmit FIFO/Buffer is cleared out.
23737 */
23738#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
23739/*! @} */
23740
23741/*! @name SFIFO - UART FIFO Status Register */
23742/*! @{ */
23743#define UART_SFIFO_RXUF_MASK (0x1U)
23744#define UART_SFIFO_RXUF_SHIFT (0U)
23745/*! RXUF - Receiver Buffer Underflow Flag
23746 * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared.
23747 * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.
23748 */
23749#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
23750#define UART_SFIFO_TXOF_MASK (0x2U)
23751#define UART_SFIFO_TXOF_SHIFT (1U)
23752/*! TXOF - Transmitter Buffer Overflow Flag
23753 * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared.
23754 * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.
23755 */
23756#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
23757#define UART_SFIFO_RXOF_MASK (0x4U)
23758#define UART_SFIFO_RXOF_SHIFT (2U)
23759/*! RXOF - Receiver Buffer Overflow Flag
23760 * 0b0..No receive buffer overflow has occurred since the last time the flag was cleared.
23761 * 0b1..At least one receive buffer overflow has occurred since the last time the flag was cleared.
23762 */
23763#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
23764#define UART_SFIFO_RXEMPT_MASK (0x40U)
23765#define UART_SFIFO_RXEMPT_SHIFT (6U)
23766/*! RXEMPT - Receive Buffer/FIFO Empty
23767 * 0b0..Receive buffer is not empty.
23768 * 0b1..Receive buffer is empty.
23769 */
23770#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
23771#define UART_SFIFO_TXEMPT_MASK (0x80U)
23772#define UART_SFIFO_TXEMPT_SHIFT (7U)
23773/*! TXEMPT - Transmit Buffer/FIFO Empty
23774 * 0b0..Transmit buffer is not empty.
23775 * 0b1..Transmit buffer is empty.
23776 */
23777#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
23778/*! @} */
23779
23780/*! @name TWFIFO - UART FIFO Transmit Watermark */
23781/*! @{ */
23782#define UART_TWFIFO_TXWATER_MASK (0xFFU)
23783#define UART_TWFIFO_TXWATER_SHIFT (0U)
23784#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
23785/*! @} */
23786
23787/*! @name TCFIFO - UART FIFO Transmit Count */
23788/*! @{ */
23789#define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
23790#define UART_TCFIFO_TXCOUNT_SHIFT (0U)
23791#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
23792/*! @} */
23793
23794/*! @name RWFIFO - UART FIFO Receive Watermark */
23795/*! @{ */
23796#define UART_RWFIFO_RXWATER_MASK (0xFFU)
23797#define UART_RWFIFO_RXWATER_SHIFT (0U)
23798#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
23799/*! @} */
23800
23801/*! @name RCFIFO - UART FIFO Receive Count */
23802/*! @{ */
23803#define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
23804#define UART_RCFIFO_RXCOUNT_SHIFT (0U)
23805#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
23806/*! @} */
23807
23808/*! @name C7816 - UART 7816 Control Register */
23809/*! @{ */
23810#define UART_C7816_ISO_7816E_MASK (0x1U)
23811#define UART_C7816_ISO_7816E_SHIFT (0U)
23812/*! ISO_7816E - ISO-7816 Functionality Enabled
23813 * 0b0..ISO-7816 functionality is turned off/not enabled.
23814 * 0b1..ISO-7816 functionality is turned on/enabled.
23815 */
23816#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
23817#define UART_C7816_TTYPE_MASK (0x2U)
23818#define UART_C7816_TTYPE_SHIFT (1U)
23819/*! TTYPE - Transfer Type
23820 * 0b0..T = 0 per the ISO-7816 specification.
23821 * 0b1..T = 1 per the ISO-7816 specification.
23822 */
23823#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
23824#define UART_C7816_INIT_MASK (0x4U)
23825#define UART_C7816_INIT_SHIFT (2U)
23826/*! INIT - Detect Initial Character
23827 * 0b0..Normal operating mode. Receiver does not seek to identify initial character.
23828 * 0b1..Receiver searches for initial character.
23829 */
23830#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
23831#define UART_C7816_ANACK_MASK (0x8U)
23832#define UART_C7816_ANACK_SHIFT (3U)
23833/*! ANACK - Generate NACK on Error
23834 * 0b0..No NACK is automatically generated.
23835 * 0b1..A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.
23836 */
23837#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
23838#define UART_C7816_ONACK_MASK (0x10U)
23839#define UART_C7816_ONACK_SHIFT (4U)
23840/*! ONACK - Generate NACK on Overflow
23841 * 0b0..The received data does not generate a NACK when the receipt of the data results in an overflow event.
23842 * 0b1..If the receiver buffer overflows, a NACK is automatically sent on a received character.
23843 */
23844#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
23845/*! @} */
23846
23847/*! @name IE7816 - UART 7816 Interrupt Enable Register */
23848/*! @{ */
23849#define UART_IE7816_RXTE_MASK (0x1U)
23850#define UART_IE7816_RXTE_SHIFT (0U)
23851/*! RXTE - Receive Threshold Exceeded Interrupt Enable
23852 * 0b0..The assertion of IS7816[RXT] does not result in the generation of an interrupt.
23853 * 0b1..The assertion of IS7816[RXT] results in the generation of an interrupt.
23854 */
23855#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
23856#define UART_IE7816_TXTE_MASK (0x2U)
23857#define UART_IE7816_TXTE_SHIFT (1U)
23858/*! TXTE - Transmit Threshold Exceeded Interrupt Enable
23859 * 0b0..The assertion of IS7816[TXT] does not result in the generation of an interrupt.
23860 * 0b1..The assertion of IS7816[TXT] results in the generation of an interrupt.
23861 */
23862#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
23863#define UART_IE7816_GTVE_MASK (0x4U)
23864#define UART_IE7816_GTVE_SHIFT (2U)
23865/*! GTVE - Guard Timer Violated Interrupt Enable
23866 * 0b0..The assertion of IS7816[GTV] does not result in the generation of an interrupt.
23867 * 0b1..The assertion of IS7816[GTV] results in the generation of an interrupt.
23868 */
23869#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
23870#define UART_IE7816_ADTE_MASK (0x8U)
23871#define UART_IE7816_ADTE_SHIFT (3U)
23872/*! ADTE - ATR Duration Timer Interrupt Enable
23873 * 0b0..The assertion of IS7816[ADT] does not result in the generation of an interrupt.
23874 * 0b1..The assertion of IS7816[ADT] results in the generation of an interrupt.
23875 */
23876#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
23877#define UART_IE7816_INITDE_MASK (0x10U)
23878#define UART_IE7816_INITDE_SHIFT (4U)
23879/*! INITDE - Initial Character Detected Interrupt Enable
23880 * 0b0..The assertion of IS7816[INITD] does not result in the generation of an interrupt.
23881 * 0b1..The assertion of IS7816[INITD] results in the generation of an interrupt.
23882 */
23883#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
23884#define UART_IE7816_BWTE_MASK (0x20U)
23885#define UART_IE7816_BWTE_SHIFT (5U)
23886/*! BWTE - Block Wait Timer Interrupt Enable
23887 * 0b0..The assertion of IS7816[BWT] does not result in the generation of an interrupt.
23888 * 0b1..The assertion of IS7816[BWT] results in the generation of an interrupt.
23889 */
23890#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
23891#define UART_IE7816_CWTE_MASK (0x40U)
23892#define UART_IE7816_CWTE_SHIFT (6U)
23893/*! CWTE - Character Wait Timer Interrupt Enable
23894 * 0b0..The assertion of IS7816[CWT] does not result in the generation of an interrupt.
23895 * 0b1..The assertion of IS7816[CWT] results in the generation of an interrupt.
23896 */
23897#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
23898#define UART_IE7816_WTE_MASK (0x80U)
23899#define UART_IE7816_WTE_SHIFT (7U)
23900/*! WTE - Wait Timer Interrupt Enable
23901 * 0b0..The assertion of IS7816[WT] does not result in the generation of an interrupt.
23902 * 0b1..The assertion of IS7816[WT] results in the generation of an interrupt.
23903 */
23904#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
23905/*! @} */
23906
23907/*! @name IS7816 - UART 7816 Interrupt Status Register */
23908/*! @{ */
23909#define UART_IS7816_RXT_MASK (0x1U)
23910#define UART_IS7816_RXT_SHIFT (0U)
23911/*! RXT - Receive Threshold Exceeded Interrupt
23912 * 0b0..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].
23913 * 0b1..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
23914 */
23915#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
23916#define UART_IS7816_TXT_MASK (0x2U)
23917#define UART_IS7816_TXT_SHIFT (1U)
23918/*! TXT - Transmit Threshold Exceeded Interrupt
23919 * 0b0..The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].
23920 * 0b1..The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].
23921 */
23922#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
23923#define UART_IS7816_GTV_MASK (0x4U)
23924#define UART_IS7816_GTV_SHIFT (2U)
23925/*! GTV - Guard Timer Violated Interrupt
23926 * 0b0..A guard time (GT, CGT, or BGT) has not been violated.
23927 * 0b1..A guard time (GT, CGT, or BGT) has been violated.
23928 */
23929#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
23930#define UART_IS7816_ADT_MASK (0x8U)
23931#define UART_IS7816_ADT_SHIFT (3U)
23932/*! ADT - ATR Duration Time Interrupt
23933 * 0b0..ATR Duration time (ADT) has not been violated.
23934 * 0b1..ATR Duration time (ADT) has been violated.
23935 */
23936#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
23937#define UART_IS7816_INITD_MASK (0x10U)
23938#define UART_IS7816_INITD_SHIFT (4U)
23939/*! INITD - Initial Character Detected Interrupt
23940 * 0b0..A valid initial character has not been received.
23941 * 0b1..A valid initial character has been received.
23942 */
23943#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
23944#define UART_IS7816_BWT_MASK (0x20U)
23945#define UART_IS7816_BWT_SHIFT (5U)
23946/*! BWT - Block Wait Timer Interrupt
23947 * 0b0..Block wait time (BWT) has not been violated.
23948 * 0b1..Block wait time (BWT) has been violated.
23949 */
23950#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
23951#define UART_IS7816_CWT_MASK (0x40U)
23952#define UART_IS7816_CWT_SHIFT (6U)
23953/*! CWT - Character Wait Timer Interrupt
23954 * 0b0..Character wait time (CWT) has not been violated.
23955 * 0b1..Character wait time (CWT) has been violated.
23956 */
23957#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
23958#define UART_IS7816_WT_MASK (0x80U)
23959#define UART_IS7816_WT_SHIFT (7U)
23960/*! WT - Wait Timer Interrupt
23961 * 0b0..Wait time (WT) has not been violated.
23962 * 0b1..Wait time (WT) has been violated.
23963 */
23964#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
23965/*! @} */
23966
23967/*! @name WP7816 - UART 7816 Wait Parameter Register */
23968/*! @{ */
23969#define UART_WP7816_WTX_MASK (0xFFU)
23970#define UART_WP7816_WTX_SHIFT (0U)
23971#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
23972/*! @} */
23973
23974/*! @name WN7816 - UART 7816 Wait N Register */
23975/*! @{ */
23976#define UART_WN7816_GTN_MASK (0xFFU)
23977#define UART_WN7816_GTN_SHIFT (0U)
23978#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
23979/*! @} */
23980
23981/*! @name WF7816 - UART 7816 Wait FD Register */
23982/*! @{ */
23983#define UART_WF7816_GTFD_MASK (0xFFU)
23984#define UART_WF7816_GTFD_SHIFT (0U)
23985#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
23986/*! @} */
23987
23988/*! @name ET7816 - UART 7816 Error Threshold Register */
23989/*! @{ */
23990#define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
23991#define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
23992#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
23993#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
23994#define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
23995/*! TXTHRESHOLD - Transmit NACK Threshold
23996 * 0b0000..TXT asserts on the first NACK that is received.
23997 * 0b0001..TXT asserts on the second NACK that is received.
23998 */
23999#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
24000/*! @} */
24001
24002/*! @name TL7816 - UART 7816 Transmit Length Register */
24003/*! @{ */
24004#define UART_TL7816_TLEN_MASK (0xFFU)
24005#define UART_TL7816_TLEN_SHIFT (0U)
24006#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
24007/*! @} */
24008
24009/*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
24010/*! @{ */
24011#define UART_AP7816A_T0_ADTI_H_MASK (0xFFU)
24012#define UART_AP7816A_T0_ADTI_H_SHIFT (0U)
24013#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
24014/*! @} */
24015
24016/*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
24017/*! @{ */
24018#define UART_AP7816B_T0_ADTI_L_MASK (0xFFU)
24019#define UART_AP7816B_T0_ADTI_L_SHIFT (0U)
24020#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
24021/*! @} */
24022
24023/*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
24024/*! @{ */
24025#define UART_WP7816A_T0_WI_H_MASK (0xFFU)
24026#define UART_WP7816A_T0_WI_H_SHIFT (0U)
24027#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
24028/*! @} */
24029
24030/*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
24031/*! @{ */
24032#define UART_WP7816B_T0_WI_L_MASK (0xFFU)
24033#define UART_WP7816B_T0_WI_L_SHIFT (0U)
24034#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
24035/*! @} */
24036
24037/*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
24038/*! @{ */
24039#define UART_WP7816A_T1_BWI_H_MASK (0xFFU)
24040#define UART_WP7816A_T1_BWI_H_SHIFT (0U)
24041#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
24042/*! @} */
24043
24044/*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
24045/*! @{ */
24046#define UART_WP7816B_T1_BWI_L_MASK (0xFFU)
24047#define UART_WP7816B_T1_BWI_L_SHIFT (0U)
24048#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
24049/*! @} */
24050
24051/*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
24052/*! @{ */
24053#define UART_WGP7816_T1_BGI_MASK (0xFU)
24054#define UART_WGP7816_T1_BGI_SHIFT (0U)
24055#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
24056#define UART_WGP7816_T1_CWI1_MASK (0xF0U)
24057#define UART_WGP7816_T1_CWI1_SHIFT (4U)
24058#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
24059/*! @} */
24060
24061/*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
24062/*! @{ */
24063#define UART_WP7816C_T1_CWI2_MASK (0x1FU)
24064#define UART_WP7816C_T1_CWI2_SHIFT (0U)
24065#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
24066/*! @} */
24067
24068
24069/*!
24070 * @}
24071 */ /* end of group UART_Register_Masks */
24072
24073
24074/* UART - Peripheral instance base addresses */
24075/** Peripheral UART0 base address */
24076#define UART0_BASE (0x4006A000u)
24077/** Peripheral UART0 base pointer */
24078#define UART0 ((UART_Type *)UART0_BASE)
24079/** Peripheral UART1 base address */
24080#define UART1_BASE (0x4006B000u)
24081/** Peripheral UART1 base pointer */
24082#define UART1 ((UART_Type *)UART1_BASE)
24083/** Peripheral UART2 base address */
24084#define UART2_BASE (0x4006C000u)
24085/** Peripheral UART2 base pointer */
24086#define UART2 ((UART_Type *)UART2_BASE)
24087/** Peripheral UART3 base address */
24088#define UART3_BASE (0x4006D000u)
24089/** Peripheral UART3 base pointer */
24090#define UART3 ((UART_Type *)UART3_BASE)
24091/** Peripheral UART4 base address */
24092#define UART4_BASE (0x400EA000u)
24093/** Peripheral UART4 base pointer */
24094#define UART4 ((UART_Type *)UART4_BASE)
24095/** Array initializer of UART peripheral base addresses */
24096#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE }
24097/** Array initializer of UART peripheral base pointers */
24098#define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4 }
24099/** Interrupt vectors for the UART peripheral type */
24100#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn }
24101#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn }
24102
24103/*!
24104 * @}
24105 */ /* end of group UART_Peripheral_Access_Layer */
24106
24107
24108/* ----------------------------------------------------------------------------
24109 -- USB Peripheral Access Layer
24110 ---------------------------------------------------------------------------- */
24111
24112/*!
24113 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
24114 * @{
24115 */
24116
24117/** USB - Register Layout Typedef */
24118typedef struct {
24119 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
24120 uint8_t RESERVED_0[3];
24121 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
24122 uint8_t RESERVED_1[3];
24123 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
24124 uint8_t RESERVED_2[3];
24125 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
24126 uint8_t RESERVED_3[3];
24127 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
24128 uint8_t RESERVED_4[3];
24129 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
24130 uint8_t RESERVED_5[3];
24131 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
24132 uint8_t RESERVED_6[3];
24133 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
24134 uint8_t RESERVED_7[99];
24135 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
24136 uint8_t RESERVED_8[3];
24137 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
24138 uint8_t RESERVED_9[3];
24139 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
24140 uint8_t RESERVED_10[3];
24141 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
24142 uint8_t RESERVED_11[3];
24143 __I uint8_t STAT; /**< Status register, offset: 0x90 */
24144 uint8_t RESERVED_12[3];
24145 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
24146 uint8_t RESERVED_13[3];
24147 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
24148 uint8_t RESERVED_14[3];
24149 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
24150 uint8_t RESERVED_15[3];
24151 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
24152 uint8_t RESERVED_16[3];
24153 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
24154 uint8_t RESERVED_17[3];
24155 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
24156 uint8_t RESERVED_18[3];
24157 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
24158 uint8_t RESERVED_19[3];
24159 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
24160 uint8_t RESERVED_20[3];
24161 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
24162 uint8_t RESERVED_21[11];
24163 struct { /* offset: 0xC0, array step: 0x4 */
24164 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
24165 uint8_t RESERVED_0[3];
24166 } ENDPOINT[16];
24167 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
24168 uint8_t RESERVED_22[3];
24169 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
24170 uint8_t RESERVED_23[3];
24171 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
24172 uint8_t RESERVED_24[3];
24173 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
24174 uint8_t RESERVED_25[7];
24175 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
24176 uint8_t RESERVED_26[43];
24177 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
24178 uint8_t RESERVED_27[3];
24179 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
24180 uint8_t RESERVED_28[15];
24181 __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */
24182 uint8_t RESERVED_29[7];
24183 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
24184} USB_Type;
24185
24186/* ----------------------------------------------------------------------------
24187 -- USB Register Masks
24188 ---------------------------------------------------------------------------- */
24189
24190/*!
24191 * @addtogroup USB_Register_Masks USB Register Masks
24192 * @{
24193 */
24194
24195/*! @name PERID - Peripheral ID register */
24196/*! @{ */
24197#define USB_PERID_ID_MASK (0x3FU)
24198#define USB_PERID_ID_SHIFT (0U)
24199#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
24200/*! @} */
24201
24202/*! @name IDCOMP - Peripheral ID Complement register */
24203/*! @{ */
24204#define USB_IDCOMP_NID_MASK (0x3FU)
24205#define USB_IDCOMP_NID_SHIFT (0U)
24206#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
24207/*! @} */
24208
24209/*! @name REV - Peripheral Revision register */
24210/*! @{ */
24211#define USB_REV_REV_MASK (0xFFU)
24212#define USB_REV_REV_SHIFT (0U)
24213#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
24214/*! @} */
24215
24216/*! @name ADDINFO - Peripheral Additional Info register */
24217/*! @{ */
24218#define USB_ADDINFO_IEHOST_MASK (0x1U)
24219#define USB_ADDINFO_IEHOST_SHIFT (0U)
24220#define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
24221/*! @} */
24222
24223/*! @name OTGISTAT - OTG Interrupt Status register */
24224/*! @{ */
24225#define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
24226#define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
24227#define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
24228#define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
24229#define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
24230#define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
24231#define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
24232#define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
24233#define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
24234#define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
24235#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
24236#define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
24237#define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
24238#define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
24239#define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
24240#define USB_OTGISTAT_IDCHG_MASK (0x80U)
24241#define USB_OTGISTAT_IDCHG_SHIFT (7U)
24242#define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
24243/*! @} */
24244
24245/*! @name OTGICR - OTG Interrupt Control register */
24246/*! @{ */
24247#define USB_OTGICR_AVBUSEN_MASK (0x1U)
24248#define USB_OTGICR_AVBUSEN_SHIFT (0U)
24249/*! AVBUSEN - A VBUS Valid Interrupt Enable
24250 * 0b0..Disables the AVBUSCHG interrupt.
24251 * 0b1..Enables the AVBUSCHG interrupt.
24252 */
24253#define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
24254#define USB_OTGICR_BSESSEN_MASK (0x4U)
24255#define USB_OTGICR_BSESSEN_SHIFT (2U)
24256/*! BSESSEN - B Session END Interrupt Enable
24257 * 0b0..Disables the B_SESS_CHG interrupt.
24258 * 0b1..Enables the B_SESS_CHG interrupt.
24259 */
24260#define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
24261#define USB_OTGICR_SESSVLDEN_MASK (0x8U)
24262#define USB_OTGICR_SESSVLDEN_SHIFT (3U)
24263/*! SESSVLDEN - Session Valid Interrupt Enable
24264 * 0b0..Disables the SESSVLDCHG interrupt.
24265 * 0b1..Enables the SESSVLDCHG interrupt.
24266 */
24267#define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
24268#define USB_OTGICR_LINESTATEEN_MASK (0x20U)
24269#define USB_OTGICR_LINESTATEEN_SHIFT (5U)
24270/*! LINESTATEEN - Line State Change Interrupt Enable
24271 * 0b0..Disables the LINE_STAT_CHG interrupt.
24272 * 0b1..Enables the LINE_STAT_CHG interrupt.
24273 */
24274#define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
24275#define USB_OTGICR_ONEMSECEN_MASK (0x40U)
24276#define USB_OTGICR_ONEMSECEN_SHIFT (6U)
24277/*! ONEMSECEN - One Millisecond Interrupt Enable
24278 * 0b0..Diables the 1ms timer interrupt.
24279 * 0b1..Enables the 1ms timer interrupt.
24280 */
24281#define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
24282#define USB_OTGICR_IDEN_MASK (0x80U)
24283#define USB_OTGICR_IDEN_SHIFT (7U)
24284/*! IDEN - ID Interrupt Enable
24285 * 0b0..The ID interrupt is disabled
24286 * 0b1..The ID interrupt is enabled
24287 */
24288#define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
24289/*! @} */
24290
24291/*! @name OTGSTAT - OTG Status register */
24292/*! @{ */
24293#define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
24294#define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
24295/*! AVBUSVLD - A VBUS Valid
24296 * 0b0..The VBUS voltage is below the A VBUS Valid threshold.
24297 * 0b1..The VBUS voltage is above the A VBUS Valid threshold.
24298 */
24299#define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
24300#define USB_OTGSTAT_BSESSEND_MASK (0x4U)
24301#define USB_OTGSTAT_BSESSEND_SHIFT (2U)
24302/*! BSESSEND - B Session End
24303 * 0b0..The VBUS voltage is above the B session end threshold.
24304 * 0b1..The VBUS voltage is below the B session end threshold.
24305 */
24306#define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
24307#define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
24308#define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
24309/*! SESS_VLD - Session Valid
24310 * 0b0..The VBUS voltage is below the B session valid threshold
24311 * 0b1..The VBUS voltage is above the B session valid threshold.
24312 */
24313#define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
24314#define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
24315#define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
24316/*! LINESTATESTABLE
24317 * 0b0..The LINE_STAT_CHG bit is not yet stable.
24318 * 0b1..The LINE_STAT_CHG bit has been debounced and is stable.
24319 */
24320#define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
24321#define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
24322#define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
24323#define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
24324#define USB_OTGSTAT_ID_MASK (0x80U)
24325#define USB_OTGSTAT_ID_SHIFT (7U)
24326/*! ID
24327 * 0b0..Indicates a Type A cable is plugged into the USB connector.
24328 * 0b1..Indicates no cable is attached or a Type B cable is plugged into the USB connector.
24329 */
24330#define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
24331/*! @} */
24332
24333/*! @name OTGCTL - OTG Control register */
24334/*! @{ */
24335#define USB_OTGCTL_OTGEN_MASK (0x4U)
24336#define USB_OTGCTL_OTGEN_SHIFT (2U)
24337/*! OTGEN - On-The-Go pullup/pulldown resistor enable
24338 * 0b0..If USB_EN is 1 and HOST_MODE is 0 in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is 1 the D+ and D- Data Line pull-down resistors are engaged.
24339 * 0b1..The pull-up and pull-down controls in this register are used.
24340 */
24341#define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
24342#define USB_OTGCTL_DMLOW_MASK (0x10U)
24343#define USB_OTGCTL_DMLOW_SHIFT (4U)
24344/*! DMLOW - D- Data Line pull-down resistor enable
24345 * 0b0..D- pulldown resistor is not enabled.
24346 * 0b1..D- pulldown resistor is enabled.
24347 */
24348#define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
24349#define USB_OTGCTL_DPLOW_MASK (0x20U)
24350#define USB_OTGCTL_DPLOW_SHIFT (5U)
24351/*! DPLOW - D+ Data Line pull-down resistor enable
24352 * 0b0..D+ pulldown resistor is not enabled.
24353 * 0b1..D+ pulldown resistor is enabled.
24354 */
24355#define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
24356#define USB_OTGCTL_DPHIGH_MASK (0x80U)
24357#define USB_OTGCTL_DPHIGH_SHIFT (7U)
24358/*! DPHIGH - D+ Data Line pullup resistor enable
24359 * 0b0..D+ pullup resistor is not enabled
24360 * 0b1..D+ pullup resistor is enabled
24361 */
24362#define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
24363/*! @} */
24364
24365/*! @name ISTAT - Interrupt Status register */
24366/*! @{ */
24367#define USB_ISTAT_USBRST_MASK (0x1U)
24368#define USB_ISTAT_USBRST_SHIFT (0U)
24369#define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
24370#define USB_ISTAT_ERROR_MASK (0x2U)
24371#define USB_ISTAT_ERROR_SHIFT (1U)
24372#define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
24373#define USB_ISTAT_SOFTOK_MASK (0x4U)
24374#define USB_ISTAT_SOFTOK_SHIFT (2U)
24375#define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
24376#define USB_ISTAT_TOKDNE_MASK (0x8U)
24377#define USB_ISTAT_TOKDNE_SHIFT (3U)
24378#define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
24379#define USB_ISTAT_SLEEP_MASK (0x10U)
24380#define USB_ISTAT_SLEEP_SHIFT (4U)
24381#define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
24382#define USB_ISTAT_RESUME_MASK (0x20U)
24383#define USB_ISTAT_RESUME_SHIFT (5U)
24384#define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
24385#define USB_ISTAT_ATTACH_MASK (0x40U)
24386#define USB_ISTAT_ATTACH_SHIFT (6U)
24387/*! ATTACH - Attach Interrupt
24388 * 0b0..No Attach is detected since the last time the ATTACH bit was cleared.
24389 * 0b1..A peripheral is now present and must be configured (a stable non-SE0 state is detected for more than 2.5 us).
24390 */
24391#define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
24392#define USB_ISTAT_STALL_MASK (0x80U)
24393#define USB_ISTAT_STALL_SHIFT (7U)
24394#define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
24395/*! @} */
24396
24397/*! @name INTEN - Interrupt Enable register */
24398/*! @{ */
24399#define USB_INTEN_USBRSTEN_MASK (0x1U)
24400#define USB_INTEN_USBRSTEN_SHIFT (0U)
24401/*! USBRSTEN - USBRST Interrupt Enable
24402 * 0b0..Disables the USBRST interrupt.
24403 * 0b1..Enables the USBRST interrupt.
24404 */
24405#define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
24406#define USB_INTEN_ERROREN_MASK (0x2U)
24407#define USB_INTEN_ERROREN_SHIFT (1U)
24408/*! ERROREN - ERROR Interrupt Enable
24409 * 0b0..Disables the ERROR interrupt.
24410 * 0b1..Enables the ERROR interrupt.
24411 */
24412#define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
24413#define USB_INTEN_SOFTOKEN_MASK (0x4U)
24414#define USB_INTEN_SOFTOKEN_SHIFT (2U)
24415/*! SOFTOKEN - SOFTOK Interrupt Enable
24416 * 0b0..Disbles the SOFTOK interrupt.
24417 * 0b1..Enables the SOFTOK interrupt.
24418 */
24419#define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
24420#define USB_INTEN_TOKDNEEN_MASK (0x8U)
24421#define USB_INTEN_TOKDNEEN_SHIFT (3U)
24422/*! TOKDNEEN - TOKDNE Interrupt Enable
24423 * 0b0..Disables the TOKDNE interrupt.
24424 * 0b1..Enables the TOKDNE interrupt.
24425 */
24426#define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
24427#define USB_INTEN_SLEEPEN_MASK (0x10U)
24428#define USB_INTEN_SLEEPEN_SHIFT (4U)
24429/*! SLEEPEN - SLEEP Interrupt Enable
24430 * 0b0..Disables the SLEEP interrupt.
24431 * 0b1..Enables the SLEEP interrupt.
24432 */
24433#define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
24434#define USB_INTEN_RESUMEEN_MASK (0x20U)
24435#define USB_INTEN_RESUMEEN_SHIFT (5U)
24436/*! RESUMEEN - RESUME Interrupt Enable
24437 * 0b0..Disables the RESUME interrupt.
24438 * 0b1..Enables the RESUME interrupt.
24439 */
24440#define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
24441#define USB_INTEN_ATTACHEN_MASK (0x40U)
24442#define USB_INTEN_ATTACHEN_SHIFT (6U)
24443/*! ATTACHEN - ATTACH Interrupt Enable
24444 * 0b0..Disables the ATTACH interrupt.
24445 * 0b1..Enables the ATTACH interrupt.
24446 */
24447#define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
24448#define USB_INTEN_STALLEN_MASK (0x80U)
24449#define USB_INTEN_STALLEN_SHIFT (7U)
24450/*! STALLEN - STALL Interrupt Enable
24451 * 0b0..Diasbles the STALL interrupt.
24452 * 0b1..Enables the STALL interrupt.
24453 */
24454#define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
24455/*! @} */
24456
24457/*! @name ERRSTAT - Error Interrupt Status register */
24458/*! @{ */
24459#define USB_ERRSTAT_PIDERR_MASK (0x1U)
24460#define USB_ERRSTAT_PIDERR_SHIFT (0U)
24461#define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
24462#define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
24463#define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
24464#define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
24465#define USB_ERRSTAT_CRC16_MASK (0x4U)
24466#define USB_ERRSTAT_CRC16_SHIFT (2U)
24467#define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
24468#define USB_ERRSTAT_DFN8_MASK (0x8U)
24469#define USB_ERRSTAT_DFN8_SHIFT (3U)
24470#define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
24471#define USB_ERRSTAT_BTOERR_MASK (0x10U)
24472#define USB_ERRSTAT_BTOERR_SHIFT (4U)
24473#define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
24474#define USB_ERRSTAT_DMAERR_MASK (0x20U)
24475#define USB_ERRSTAT_DMAERR_SHIFT (5U)
24476#define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
24477#define USB_ERRSTAT_BTSERR_MASK (0x80U)
24478#define USB_ERRSTAT_BTSERR_SHIFT (7U)
24479#define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
24480/*! @} */
24481
24482/*! @name ERREN - Error Interrupt Enable register */
24483/*! @{ */
24484#define USB_ERREN_PIDERREN_MASK (0x1U)
24485#define USB_ERREN_PIDERREN_SHIFT (0U)
24486/*! PIDERREN - PIDERR Interrupt Enable
24487 * 0b0..Disables the PIDERR interrupt.
24488 * 0b1..Enters the PIDERR interrupt.
24489 */
24490#define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
24491#define USB_ERREN_CRC5EOFEN_MASK (0x2U)
24492#define USB_ERREN_CRC5EOFEN_SHIFT (1U)
24493/*! CRC5EOFEN - CRC5/EOF Interrupt Enable
24494 * 0b0..Disables the CRC5/EOF interrupt.
24495 * 0b1..Enables the CRC5/EOF interrupt.
24496 */
24497#define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
24498#define USB_ERREN_CRC16EN_MASK (0x4U)
24499#define USB_ERREN_CRC16EN_SHIFT (2U)
24500/*! CRC16EN - CRC16 Interrupt Enable
24501 * 0b0..Disables the CRC16 interrupt.
24502 * 0b1..Enables the CRC16 interrupt.
24503 */
24504#define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
24505#define USB_ERREN_DFN8EN_MASK (0x8U)
24506#define USB_ERREN_DFN8EN_SHIFT (3U)
24507/*! DFN8EN - DFN8 Interrupt Enable
24508 * 0b0..Disables the DFN8 interrupt.
24509 * 0b1..Enables the DFN8 interrupt.
24510 */
24511#define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
24512#define USB_ERREN_BTOERREN_MASK (0x10U)
24513#define USB_ERREN_BTOERREN_SHIFT (4U)
24514/*! BTOERREN - BTOERR Interrupt Enable
24515 * 0b0..Disables the BTOERR interrupt.
24516 * 0b1..Enables the BTOERR interrupt.
24517 */
24518#define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
24519#define USB_ERREN_DMAERREN_MASK (0x20U)
24520#define USB_ERREN_DMAERREN_SHIFT (5U)
24521/*! DMAERREN - DMAERR Interrupt Enable
24522 * 0b0..Disables the DMAERR interrupt.
24523 * 0b1..Enables the DMAERR interrupt.
24524 */
24525#define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
24526#define USB_ERREN_BTSERREN_MASK (0x80U)
24527#define USB_ERREN_BTSERREN_SHIFT (7U)
24528/*! BTSERREN - BTSERR Interrupt Enable
24529 * 0b0..Disables the BTSERR interrupt.
24530 * 0b1..Enables the BTSERR interrupt.
24531 */
24532#define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
24533/*! @} */
24534
24535/*! @name STAT - Status register */
24536/*! @{ */
24537#define USB_STAT_ODD_MASK (0x4U)
24538#define USB_STAT_ODD_SHIFT (2U)
24539#define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
24540#define USB_STAT_TX_MASK (0x8U)
24541#define USB_STAT_TX_SHIFT (3U)
24542/*! TX - Transmit Indicator
24543 * 0b0..The most recent transaction was a receive operation.
24544 * 0b1..The most recent transaction was a transmit operation.
24545 */
24546#define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
24547#define USB_STAT_ENDP_MASK (0xF0U)
24548#define USB_STAT_ENDP_SHIFT (4U)
24549#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
24550/*! @} */
24551
24552/*! @name CTL - Control register */
24553/*! @{ */
24554#define USB_CTL_USBENSOFEN_MASK (0x1U)
24555#define USB_CTL_USBENSOFEN_SHIFT (0U)
24556/*! USBENSOFEN - USB Enable
24557 * 0b0..Disables the USB Module.
24558 * 0b1..Enables the USB Module.
24559 */
24560#define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
24561#define USB_CTL_ODDRST_MASK (0x2U)
24562#define USB_CTL_ODDRST_SHIFT (1U)
24563#define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
24564#define USB_CTL_RESUME_MASK (0x4U)
24565#define USB_CTL_RESUME_SHIFT (2U)
24566#define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
24567#define USB_CTL_HOSTMODEEN_MASK (0x8U)
24568#define USB_CTL_HOSTMODEEN_SHIFT (3U)
24569#define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
24570#define USB_CTL_RESET_MASK (0x10U)
24571#define USB_CTL_RESET_SHIFT (4U)
24572#define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
24573#define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
24574#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
24575#define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
24576#define USB_CTL_SE0_MASK (0x40U)
24577#define USB_CTL_SE0_SHIFT (6U)
24578#define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
24579#define USB_CTL_JSTATE_MASK (0x80U)
24580#define USB_CTL_JSTATE_SHIFT (7U)
24581#define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
24582/*! @} */
24583
24584/*! @name ADDR - Address register */
24585/*! @{ */
24586#define USB_ADDR_ADDR_MASK (0x7FU)
24587#define USB_ADDR_ADDR_SHIFT (0U)
24588#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
24589#define USB_ADDR_LSEN_MASK (0x80U)
24590#define USB_ADDR_LSEN_SHIFT (7U)
24591#define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
24592/*! @} */
24593
24594/*! @name BDTPAGE1 - BDT Page register 1 */
24595/*! @{ */
24596#define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
24597#define USB_BDTPAGE1_BDTBA_SHIFT (1U)
24598#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
24599/*! @} */
24600
24601/*! @name FRMNUML - Frame Number register Low */
24602/*! @{ */
24603#define USB_FRMNUML_FRM_MASK (0xFFU)
24604#define USB_FRMNUML_FRM_SHIFT (0U)
24605#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
24606/*! @} */
24607
24608/*! @name FRMNUMH - Frame Number register High */
24609/*! @{ */
24610#define USB_FRMNUMH_FRM_MASK (0x7U)
24611#define USB_FRMNUMH_FRM_SHIFT (0U)
24612#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
24613/*! @} */
24614
24615/*! @name TOKEN - Token register */
24616/*! @{ */
24617#define USB_TOKEN_TOKENENDPT_MASK (0xFU)
24618#define USB_TOKEN_TOKENENDPT_SHIFT (0U)
24619#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
24620#define USB_TOKEN_TOKENPID_MASK (0xF0U)
24621#define USB_TOKEN_TOKENPID_SHIFT (4U)
24622/*! TOKENPID
24623 * 0b0001..OUT Token. USB Module performs an OUT (TX) transaction.
24624 * 0b1001..IN Token. USB Module performs an In (RX) transaction.
24625 * 0b1101..SETUP Token. USB Module performs a SETUP (TX) transaction
24626 */
24627#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
24628/*! @} */
24629
24630/*! @name SOFTHLD - SOF Threshold register */
24631/*! @{ */
24632#define USB_SOFTHLD_CNT_MASK (0xFFU)
24633#define USB_SOFTHLD_CNT_SHIFT (0U)
24634#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
24635/*! @} */
24636
24637/*! @name BDTPAGE2 - BDT Page Register 2 */
24638/*! @{ */
24639#define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
24640#define USB_BDTPAGE2_BDTBA_SHIFT (0U)
24641#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
24642/*! @} */
24643
24644/*! @name BDTPAGE3 - BDT Page Register 3 */
24645/*! @{ */
24646#define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
24647#define USB_BDTPAGE3_BDTBA_SHIFT (0U)
24648#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
24649/*! @} */
24650
24651/*! @name ENDPT - Endpoint Control register */
24652/*! @{ */
24653#define USB_ENDPT_EPHSHK_MASK (0x1U)
24654#define USB_ENDPT_EPHSHK_SHIFT (0U)
24655#define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
24656#define USB_ENDPT_EPSTALL_MASK (0x2U)
24657#define USB_ENDPT_EPSTALL_SHIFT (1U)
24658#define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
24659#define USB_ENDPT_EPTXEN_MASK (0x4U)
24660#define USB_ENDPT_EPTXEN_SHIFT (2U)
24661#define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
24662#define USB_ENDPT_EPRXEN_MASK (0x8U)
24663#define USB_ENDPT_EPRXEN_SHIFT (3U)
24664#define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
24665#define USB_ENDPT_EPCTLDIS_MASK (0x10U)
24666#define USB_ENDPT_EPCTLDIS_SHIFT (4U)
24667#define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
24668#define USB_ENDPT_RETRYDIS_MASK (0x40U)
24669#define USB_ENDPT_RETRYDIS_SHIFT (6U)
24670#define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
24671#define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
24672#define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
24673/*! HOSTWOHUB
24674 * 0b0..Low-speed device connected to Host through a hub. PRE_PID will be generated as required.
24675 * 0b1..Low-speed device directly connected. No hub, or no low-speed device attached.
24676 */
24677#define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
24678/*! @} */
24679
24680/* The count of USB_ENDPT */
24681#define USB_ENDPT_COUNT (16U)
24682
24683/*! @name USBCTRL - USB Control register */
24684/*! @{ */
24685#define USB_USBCTRL_PDE_MASK (0x40U)
24686#define USB_USBCTRL_PDE_SHIFT (6U)
24687/*! PDE
24688 * 0b0..Weak pulldowns are disabled on D+ and D-.
24689 * 0b1..Weak pulldowns are enabled on D+ and D-.
24690 */
24691#define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
24692#define USB_USBCTRL_SUSP_MASK (0x80U)
24693#define USB_USBCTRL_SUSP_SHIFT (7U)
24694/*! SUSP
24695 * 0b0..USB transceiver is not in suspend state.
24696 * 0b1..USB transceiver is in suspend state.
24697 */
24698#define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
24699/*! @} */
24700
24701/*! @name OBSERVE - USB OTG Observe register */
24702/*! @{ */
24703#define USB_OBSERVE_DMPD_MASK (0x10U)
24704#define USB_OBSERVE_DMPD_SHIFT (4U)
24705/*! DMPD
24706 * 0b0..D- pulldown disabled.
24707 * 0b1..D- pulldown enabled.
24708 */
24709#define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
24710#define USB_OBSERVE_DPPD_MASK (0x40U)
24711#define USB_OBSERVE_DPPD_SHIFT (6U)
24712/*! DPPD
24713 * 0b0..D+ pulldown disabled.
24714 * 0b1..D+ pulldown enabled.
24715 */
24716#define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
24717#define USB_OBSERVE_DPPU_MASK (0x80U)
24718#define USB_OBSERVE_DPPU_SHIFT (7U)
24719/*! DPPU
24720 * 0b0..D+ pullup disabled.
24721 * 0b1..D+ pullup enabled.
24722 */
24723#define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
24724/*! @} */
24725
24726/*! @name CONTROL - USB OTG Control register */
24727/*! @{ */
24728#define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
24729#define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
24730/*! DPPULLUPNONOTG
24731 * 0b0..DP Pullup in non-OTG device mode is not enabled.
24732 * 0b1..DP Pullup in non-OTG device mode is enabled.
24733 */
24734#define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
24735/*! @} */
24736
24737/*! @name USBTRC0 - USB Transceiver Control register 0 */
24738/*! @{ */
24739#define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
24740#define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
24741/*! USB_RESUME_INT - USB Asynchronous Interrupt
24742 * 0b0..No interrupt was generated.
24743 * 0b1..Interrupt was generated because of the USB asynchronous interrupt.
24744 */
24745#define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
24746#define USB_USBTRC0_SYNC_DET_MASK (0x2U)
24747#define USB_USBTRC0_SYNC_DET_SHIFT (1U)
24748/*! SYNC_DET - Synchronous USB Interrupt Detect
24749 * 0b0..Synchronous interrupt has not been detected.
24750 * 0b1..Synchronous interrupt has been detected.
24751 */
24752#define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
24753#define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
24754#define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
24755#define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
24756#define USB_USBTRC0_USBRESMEN_MASK (0x20U)
24757#define USB_USBTRC0_USBRESMEN_SHIFT (5U)
24758/*! USBRESMEN - Asynchronous Resume Interrupt Enable
24759 * 0b0..USB asynchronous wakeup from suspend mode disabled.
24760 * 0b1..USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interrupt should only be enabled when the Transceiver is suspended.
24761 */
24762#define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
24763#define USB_USBTRC0_USBRESET_MASK (0x80U)
24764#define USB_USBTRC0_USBRESET_SHIFT (7U)
24765/*! USBRESET - USB Reset
24766 * 0b0..Normal USB module operation.
24767 * 0b1..Returns the USB module to its reset state.
24768 */
24769#define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
24770/*! @} */
24771
24772/*! @name USBFRMADJUST - Frame Adjust Register */
24773/*! @{ */
24774#define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
24775#define USB_USBFRMADJUST_ADJ_SHIFT (0U)
24776#define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
24777/*! @} */
24778
24779/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
24780/*! @{ */
24781#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
24782#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
24783/*! RESTART_IFRTRIM_EN - Restart from IFR trim value
24784 * 0b0..Trim fine adjustment always works based on the previous updated trim fine value (default)
24785 * 0b1..Trim fine restarts from the IFR trim value whenever bus_reset/bus_resume is detected or module enable is desasserted
24786 */
24787#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
24788#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
24789#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
24790/*! RESET_RESUME_ROUGH_EN - Reset/resume to rough phase enable
24791 * 0b0..Always works in tracking phase after the 1st time rough to track transition (default)
24792 * 0b1..Go back to rough stage whenever bus reset or bus resume occurs
24793 */
24794#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
24795#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
24796#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
24797/*! CLOCK_RECOVER_EN - Crystal-less USB enable
24798 * 0b0..Disable clock recovery block (default)
24799 * 0b1..Enable clock recovery block
24800 */
24801#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
24802/*! @} */
24803
24804/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
24805/*! @{ */
24806#define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
24807#define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
24808/*! REG_EN - IRC48M regulator enable
24809 * 0b0..IRC48M local regulator is disabled
24810 * 0b1..IRC48M local regulator is enabled (default)
24811 */
24812#define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
24813#define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
24814#define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
24815/*! IRC_EN - IRC48M enable
24816 * 0b0..Disable the IRC48M module (default)
24817 * 0b1..Enable the IRC48M module
24818 */
24819#define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
24820/*! @} */
24821
24822/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
24823/*! @{ */
24824#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
24825#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
24826/*! OVF_ERROR_EN
24827 * 0b0..The interrupt will be masked
24828 * 0b1..The interrupt will be enabled (default)
24829 */
24830#define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
24831/*! @} */
24832
24833/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
24834/*! @{ */
24835#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
24836#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
24837/*! OVF_ERROR
24838 * 0b0..No interrupt is reported
24839 * 0b1..Unmasked interrupt has been generated
24840 */
24841#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
24842/*! @} */
24843
24844
24845/*!
24846 * @}
24847 */ /* end of group USB_Register_Masks */
24848
24849
24850/* USB - Peripheral instance base addresses */
24851/** Peripheral USB0 base address */
24852#define USB0_BASE (0x40072000u)
24853/** Peripheral USB0 base pointer */
24854#define USB0 ((USB_Type *)USB0_BASE)
24855/** Array initializer of USB peripheral base addresses */
24856#define USB_BASE_ADDRS { USB0_BASE }
24857/** Array initializer of USB peripheral base pointers */
24858#define USB_BASE_PTRS { USB0 }
24859/** Interrupt vectors for the USB peripheral type */
24860#define USB_IRQS { USB0_IRQn }
24861
24862/*!
24863 * @}
24864 */ /* end of group USB_Peripheral_Access_Layer */
24865
24866
24867/* ----------------------------------------------------------------------------
24868 -- USBDCD Peripheral Access Layer
24869 ---------------------------------------------------------------------------- */
24870
24871/*!
24872 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
24873 * @{
24874 */
24875
24876/** USBDCD - Register Layout Typedef */
24877typedef struct {
24878 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
24879 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
24880 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
24881 __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */
24882 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
24883 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
24884 union { /* offset: 0x18 */
24885 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
24886 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
24887 };
24888} USBDCD_Type;
24889
24890/* ----------------------------------------------------------------------------
24891 -- USBDCD Register Masks
24892 ---------------------------------------------------------------------------- */
24893
24894/*!
24895 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
24896 * @{
24897 */
24898
24899/*! @name CONTROL - Control register */
24900/*! @{ */
24901#define USBDCD_CONTROL_IACK_MASK (0x1U)
24902#define USBDCD_CONTROL_IACK_SHIFT (0U)
24903/*! IACK - Interrupt Acknowledge
24904 * 0b0..Do not clear the interrupt.
24905 * 0b1..Clear the IF bit (interrupt flag).
24906 */
24907#define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
24908#define USBDCD_CONTROL_IF_MASK (0x100U)
24909#define USBDCD_CONTROL_IF_SHIFT (8U)
24910/*! IF - Interrupt Flag
24911 * 0b0..No interrupt is pending.
24912 * 0b1..An interrupt is pending.
24913 */
24914#define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
24915#define USBDCD_CONTROL_IE_MASK (0x10000U)
24916#define USBDCD_CONTROL_IE_SHIFT (16U)
24917/*! IE - Interrupt Enable
24918 * 0b0..Disable interrupts to the system.
24919 * 0b1..Enable interrupts to the system.
24920 */
24921#define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
24922#define USBDCD_CONTROL_BC12_MASK (0x20000U)
24923#define USBDCD_CONTROL_BC12_SHIFT (17U)
24924/*! BC12
24925 * 0b0..Compatible with BC1.1 (default)
24926 * 0b1..Compatible with BC1.2
24927 */
24928#define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
24929#define USBDCD_CONTROL_START_MASK (0x1000000U)
24930#define USBDCD_CONTROL_START_SHIFT (24U)
24931/*! START - Start Change Detection Sequence
24932 * 0b0..Do not start the sequence. Writes of this value have no effect.
24933 * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
24934 */
24935#define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
24936#define USBDCD_CONTROL_SR_MASK (0x2000000U)
24937#define USBDCD_CONTROL_SR_SHIFT (25U)
24938/*! SR - Software Reset
24939 * 0b0..Do not perform a software reset.
24940 * 0b1..Perform a software reset.
24941 */
24942#define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
24943/*! @} */
24944
24945/*! @name CLOCK - Clock register */
24946/*! @{ */
24947#define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
24948#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
24949/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
24950 * 0b0..kHz Speed (between 1 kHz and 1023 kHz)
24951 * 0b1..MHz Speed (between 1 MHz and 1023 MHz)
24952 */
24953#define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
24954#define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
24955#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
24956#define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
24957/*! @} */
24958
24959/*! @name STATUS - Status register */
24960/*! @{ */
24961#define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
24962#define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
24963/*! SEQ_RES - Charger Detection Sequence Results
24964 * 0b00..No results to report.
24965 * 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
24966 * 0b10..Attached to a charging port. The exact meaning depends on bit 18: 0: Attached to either a CDP or a DCP. The charger type detection has not completed. 1: Attached to a CDP. The charger type detection has completed.
24967 * 0b11..Attached to a DCP.
24968 */
24969#define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
24970#define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
24971#define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
24972/*! SEQ_STAT - Charger Detection Sequence Status
24973 * 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
24974 * 0b01..Data pin contact detection is complete.
24975 * 0b10..Charging port detection is complete.
24976 * 0b11..Charger type detection is complete.
24977 */
24978#define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
24979#define USBDCD_STATUS_ERR_MASK (0x100000U)
24980#define USBDCD_STATUS_ERR_SHIFT (20U)
24981/*! ERR - Error Flag
24982 * 0b0..No sequence errors.
24983 * 0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
24984 */
24985#define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
24986#define USBDCD_STATUS_TO_MASK (0x200000U)
24987#define USBDCD_STATUS_TO_SHIFT (21U)
24988/*! TO - Timeout Flag
24989 * 0b0..The detection sequence has not been running for over 1 s.
24990 * 0b1..It has been over 1 s since the data pin contact was detected and debounced.
24991 */
24992#define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
24993#define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
24994#define USBDCD_STATUS_ACTIVE_SHIFT (22U)
24995/*! ACTIVE - Active Status Indicator
24996 * 0b0..The sequence is not running.
24997 * 0b1..The sequence is running.
24998 */
24999#define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
25000/*! @} */
25001
25002/*! @name SIGNAL_OVERRIDE - Signal Override Register */
25003/*! @{ */
25004#define USBDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
25005#define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
25006/*! PS - Phase Selection
25007 * 0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent unexpected conditions on USB_DP and USB_DM pins. (Default)
25008 * 0b01..Reserved, not for customer use.
25009 * 0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
25010 * 0b11..Reserved, not for customer use.
25011 */
25012#define USBDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK)
25013/*! @} */
25014
25015/*! @name TIMER0 - TIMER0 register */
25016/*! @{ */
25017#define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
25018#define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
25019#define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
25020#define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
25021#define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
25022#define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
25023/*! @} */
25024
25025/*! @name TIMER1 - TIMER1 register */
25026/*! @{ */
25027#define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
25028#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
25029#define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
25030#define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
25031#define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
25032#define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
25033/*! @} */
25034
25035/*! @name TIMER2_BC11 - TIMER2_BC11 register */
25036/*! @{ */
25037#define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
25038#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
25039#define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
25040#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
25041#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
25042#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
25043/*! @} */
25044
25045/*! @name TIMER2_BC12 - TIMER2_BC12 register */
25046/*! @{ */
25047#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
25048#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
25049#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
25050#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
25051#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
25052#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
25053/*! @} */
25054
25055
25056/*!
25057 * @}
25058 */ /* end of group USBDCD_Register_Masks */
25059
25060
25061/* USBDCD - Peripheral instance base addresses */
25062/** Peripheral USBDCD base address */
25063#define USBDCD_BASE (0x40035000u)
25064/** Peripheral USBDCD base pointer */
25065#define USBDCD ((USBDCD_Type *)USBDCD_BASE)
25066/** Array initializer of USBDCD peripheral base addresses */
25067#define USBDCD_BASE_ADDRS { USBDCD_BASE }
25068/** Array initializer of USBDCD peripheral base pointers */
25069#define USBDCD_BASE_PTRS { USBDCD }
25070/** Interrupt vectors for the USBDCD peripheral type */
25071#define USBDCD_IRQS { USBDCD_IRQn }
25072
25073/*!
25074 * @}
25075 */ /* end of group USBDCD_Peripheral_Access_Layer */
25076
25077
25078/* ----------------------------------------------------------------------------
25079 -- USBHS Peripheral Access Layer
25080 ---------------------------------------------------------------------------- */
25081
25082/*!
25083 * @addtogroup USBHS_Peripheral_Access_Layer USBHS Peripheral Access Layer
25084 * @{
25085 */
25086
25087/** USBHS - Register Layout Typedef */
25088typedef struct {
25089 __I uint32_t ID; /**< Identification Register, offset: 0x0 */
25090 __I uint32_t HWGENERAL; /**< General Hardware Parameters Register, offset: 0x4 */
25091 __I uint32_t HWHOST; /**< Host Hardware Parameters Register, offset: 0x8 */
25092 __I uint32_t HWDEVICE; /**< Device Hardware Parameters Register, offset: 0xC */
25093 __I uint32_t HWTXBUF; /**< Transmit Buffer Hardware Parameters Register, offset: 0x10 */
25094 __I uint32_t HWRXBUF; /**< Receive Buffer Hardware Parameters Register, offset: 0x14 */
25095 uint8_t RESERVED_0[104];
25096 __IO uint32_t GPTIMER0LD; /**< General Purpose Timer n Load Register, offset: 0x80 */
25097 __IO uint32_t GPTIMER0CTL; /**< General Purpose Timer n Control Register, offset: 0x84 */
25098 __IO uint32_t GPTIMER1LD; /**< General Purpose Timer n Load Register, offset: 0x88 */
25099 __IO uint32_t GPTIMER1CTL; /**< General Purpose Timer n Control Register, offset: 0x8C */
25100 __IO uint32_t USB_SBUSCFG; /**< System Bus Interface Configuration Register, offset: 0x90 */
25101 uint8_t RESERVED_1[108];
25102 __I uint32_t HCIVERSION; /**< Host Controller Interface Version and Capability Registers Length Register, offset: 0x100 */
25103 __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters Register, offset: 0x104 */
25104 __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters Register, offset: 0x108 */
25105 uint8_t RESERVED_2[22];
25106 __I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x122 */
25107 __I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */
25108 uint8_t RESERVED_3[24];
25109 __IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */
25110 __IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */
25111 __IO uint32_t USBINTR; /**< USB Interrupt Enable Register, offset: 0x148 */
25112 __IO uint32_t FRINDEX; /**< Frame Index Register, offset: 0x14C */
25113 uint8_t RESERVED_4[4];
25114 union { /* offset: 0x154 */
25115 __IO uint32_t DEVICEADDR; /**< Device Address Register, offset: 0x154 */
25116 __IO uint32_t PERIODICLISTBASE; /**< Periodic Frame List Base Address Register, offset: 0x154 */
25117 };
25118 union { /* offset: 0x158 */
25119 __IO uint32_t ASYNCLISTADDR; /**< Current Asynchronous List Address Register, offset: 0x158 */
25120 __IO uint32_t EPLISTADDR; /**< Endpoint List Address Register, offset: 0x158 */
25121 };
25122 __I uint32_t TTCTRL; /**< Host TT Asynchronous Buffer Control, offset: 0x15C */
25123 __IO uint32_t BURSTSIZE; /**< Master Interface Data Burst Size Register, offset: 0x160 */
25124 __IO uint32_t TXFILLTUNING; /**< Transmit FIFO Tuning Control Register, offset: 0x164 */
25125 uint8_t RESERVED_5[16];
25126 __IO uint32_t ENDPTNAK; /**< Endpoint NAK Register, offset: 0x178 */
25127 __IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable Register, offset: 0x17C */
25128 uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */
25129 __IO uint32_t PORTSC1; /**< Port Status and Control Registers, offset: 0x184 */
25130 uint8_t RESERVED_6[28];
25131 __IO uint32_t OTGSC; /**< On-the-Go Status and Control Register, offset: 0x1A4 */
25132 __IO uint32_t USBMODE; /**< USB Mode Register, offset: 0x1A8 */
25133 __IO uint32_t EPSETUPSR; /**< Endpoint Setup Status Register, offset: 0x1AC */
25134 __IO uint32_t EPPRIME; /**< Endpoint Initialization Register, offset: 0x1B0 */
25135 __IO uint32_t EPFLUSH; /**< Endpoint Flush Register, offset: 0x1B4 */
25136 __I uint32_t EPSR; /**< Endpoint Status Register, offset: 0x1B8 */
25137 __IO uint32_t EPCOMPLETE; /**< Endpoint Complete Register, offset: 0x1BC */
25138 __IO uint32_t EPCR0; /**< Endpoint Control Register 0, offset: 0x1C0 */
25139 __IO uint32_t EPCR[7]; /**< Endpoint Control Register n, array offset: 0x1C4, array step: 0x4 */
25140 uint8_t RESERVED_7[32];
25141 __IO uint32_t USBGENCTRL; /**< USB General Control Register, offset: 0x200 */
25142} USBHS_Type;
25143
25144/* ----------------------------------------------------------------------------
25145 -- USBHS Register Masks
25146 ---------------------------------------------------------------------------- */
25147
25148/*!
25149 * @addtogroup USBHS_Register_Masks USBHS Register Masks
25150 * @{
25151 */
25152
25153/*! @name ID - Identification Register */
25154/*! @{ */
25155#define USBHS_ID_ID_MASK (0x3FU)
25156#define USBHS_ID_ID_SHIFT (0U)
25157#define USBHS_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK)
25158#define USBHS_ID_NID_MASK (0x3F00U)
25159#define USBHS_ID_NID_SHIFT (8U)
25160#define USBHS_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK)
25161#define USBHS_ID_TAG_MASK (0x1F0000U)
25162#define USBHS_ID_TAG_SHIFT (16U)
25163#define USBHS_ID_TAG(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_TAG_SHIFT)) & USBHS_ID_TAG_MASK)
25164#define USBHS_ID_REVISION_MASK (0x1E00000U)
25165#define USBHS_ID_REVISION_SHIFT (21U)
25166#define USBHS_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK)
25167#define USBHS_ID_VERSION_MASK (0x1E000000U)
25168#define USBHS_ID_VERSION_SHIFT (25U)
25169#define USBHS_ID_VERSION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSION_SHIFT)) & USBHS_ID_VERSION_MASK)
25170#define USBHS_ID_VERSIONID_MASK (0xE0000000U)
25171#define USBHS_ID_VERSIONID_SHIFT (29U)
25172#define USBHS_ID_VERSIONID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSIONID_SHIFT)) & USBHS_ID_VERSIONID_MASK)
25173/*! @} */
25174
25175/*! @name HWGENERAL - General Hardware Parameters Register */
25176/*! @{ */
25177#define USBHS_HWGENERAL_PHYW_MASK (0x30U)
25178#define USBHS_HWGENERAL_PHYW_SHIFT (4U)
25179/*! PHYW - PHY Width
25180 * 0b01..16 bit wide data bus
25181 */
25182#define USBHS_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK)
25183#define USBHS_HWGENERAL_PHYM_MASK (0x1C0U)
25184#define USBHS_HWGENERAL_PHYM_SHIFT (6U)
25185/*! PHYM - PHY Mode
25186 * 0b000..Controller configured for UTMI/UTMI+ interface.
25187 */
25188#define USBHS_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK)
25189#define USBHS_HWGENERAL_SM_MASK (0x600U)
25190#define USBHS_HWGENERAL_SM_SHIFT (9U)
25191/*! SM - Serial mode
25192 * 0b00..No Serial Engine, always use parallel signaling.
25193 */
25194#define USBHS_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK)
25195/*! @} */
25196
25197/*! @name HWHOST - Host Hardware Parameters Register */
25198/*! @{ */
25199#define USBHS_HWHOST_HC_MASK (0x1U)
25200#define USBHS_HWHOST_HC_SHIFT (0U)
25201#define USBHS_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK)
25202#define USBHS_HWHOST_NPORT_MASK (0xEU)
25203#define USBHS_HWHOST_NPORT_SHIFT (1U)
25204#define USBHS_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK)
25205#define USBHS_HWHOST_TTASY_MASK (0xFF0000U)
25206#define USBHS_HWHOST_TTASY_SHIFT (16U)
25207#define USBHS_HWHOST_TTASY(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTASY_SHIFT)) & USBHS_HWHOST_TTASY_MASK)
25208#define USBHS_HWHOST_TTPER_MASK (0xFF000000U)
25209#define USBHS_HWHOST_TTPER_SHIFT (24U)
25210#define USBHS_HWHOST_TTPER(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTPER_SHIFT)) & USBHS_HWHOST_TTPER_MASK)
25211/*! @} */
25212
25213/*! @name HWDEVICE - Device Hardware Parameters Register */
25214/*! @{ */
25215#define USBHS_HWDEVICE_DC_MASK (0x1U)
25216#define USBHS_HWDEVICE_DC_SHIFT (0U)
25217#define USBHS_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK)
25218#define USBHS_HWDEVICE_DEVEP_MASK (0x3EU)
25219#define USBHS_HWDEVICE_DEVEP_SHIFT (1U)
25220#define USBHS_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK)
25221/*! @} */
25222
25223/*! @name HWTXBUF - Transmit Buffer Hardware Parameters Register */
25224/*! @{ */
25225#define USBHS_HWTXBUF_TXBURST_MASK (0xFFU)
25226#define USBHS_HWTXBUF_TXBURST_SHIFT (0U)
25227#define USBHS_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK)
25228#define USBHS_HWTXBUF_TXADD_MASK (0xFF00U)
25229#define USBHS_HWTXBUF_TXADD_SHIFT (8U)
25230#define USBHS_HWTXBUF_TXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXADD_SHIFT)) & USBHS_HWTXBUF_TXADD_MASK)
25231#define USBHS_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
25232#define USBHS_HWTXBUF_TXCHANADD_SHIFT (16U)
25233#define USBHS_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK)
25234#define USBHS_HWTXBUF_TXLC_MASK (0x80000000U)
25235#define USBHS_HWTXBUF_TXLC_SHIFT (31U)
25236/*! TXLC - Transmit local Context Registers
25237 * 0b0..Store device transmit contexts in the TX FIFO
25238 * 0b1..Store device transmit contexts in a register file
25239 */
25240#define USBHS_HWTXBUF_TXLC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXLC_SHIFT)) & USBHS_HWTXBUF_TXLC_MASK)
25241/*! @} */
25242
25243/*! @name HWRXBUF - Receive Buffer Hardware Parameters Register */
25244/*! @{ */
25245#define USBHS_HWRXBUF_RXBURST_MASK (0xFFU)
25246#define USBHS_HWRXBUF_RXBURST_SHIFT (0U)
25247#define USBHS_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK)
25248#define USBHS_HWRXBUF_RXADD_MASK (0xFF00U)
25249#define USBHS_HWRXBUF_RXADD_SHIFT (8U)
25250#define USBHS_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK)
25251/*! @} */
25252
25253/*! @name GPTIMER0LD - General Purpose Timer n Load Register */
25254/*! @{ */
25255#define USBHS_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
25256#define USBHS_GPTIMER0LD_GPTLD_SHIFT (0U)
25257#define USBHS_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK)
25258/*! @} */
25259
25260/*! @name GPTIMER0CTL - General Purpose Timer n Control Register */
25261/*! @{ */
25262#define USBHS_GPTIMER0CTL_GPTCNT_MASK (0xFFFFFFU)
25263#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT (0U)
25264#define USBHS_GPTIMER0CTL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTL_GPTCNT_MASK)
25265#define USBHS_GPTIMER0CTL_MODE_MASK (0x1000000U)
25266#define USBHS_GPTIMER0CTL_MODE_SHIFT (24U)
25267/*! MODE - Timer Mode
25268 * 0b0..One shot
25269 * 0b1..Repeat
25270 */
25271#define USBHS_GPTIMER0CTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_MODE_SHIFT)) & USBHS_GPTIMER0CTL_MODE_MASK)
25272#define USBHS_GPTIMER0CTL_RST_MASK (0x40000000U)
25273#define USBHS_GPTIMER0CTL_RST_SHIFT (30U)
25274/*! RST - Timer Reset
25275 * 0b0..No action
25276 * 0b1..Load counter value
25277 */
25278#define USBHS_GPTIMER0CTL_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RST_SHIFT)) & USBHS_GPTIMER0CTL_RST_MASK)
25279#define USBHS_GPTIMER0CTL_RUN_MASK (0x80000000U)
25280#define USBHS_GPTIMER0CTL_RUN_SHIFT (31U)
25281/*! RUN - Timer Run
25282 * 0b0..Timer stop
25283 * 0b1..Timer run
25284 */
25285#define USBHS_GPTIMER0CTL_RUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RUN_SHIFT)) & USBHS_GPTIMER0CTL_RUN_MASK)
25286/*! @} */
25287
25288/*! @name GPTIMER1LD - General Purpose Timer n Load Register */
25289/*! @{ */
25290#define USBHS_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
25291#define USBHS_GPTIMER1LD_GPTLD_SHIFT (0U)
25292#define USBHS_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK)
25293/*! @} */
25294
25295/*! @name GPTIMER1CTL - General Purpose Timer n Control Register */
25296/*! @{ */
25297#define USBHS_GPTIMER1CTL_GPTCNT_MASK (0xFFFFFFU)
25298#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT (0U)
25299#define USBHS_GPTIMER1CTL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTL_GPTCNT_MASK)
25300#define USBHS_GPTIMER1CTL_MODE_MASK (0x1000000U)
25301#define USBHS_GPTIMER1CTL_MODE_SHIFT (24U)
25302/*! MODE - Timer Mode
25303 * 0b0..One shot
25304 * 0b1..Repeat
25305 */
25306#define USBHS_GPTIMER1CTL_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_MODE_SHIFT)) & USBHS_GPTIMER1CTL_MODE_MASK)
25307#define USBHS_GPTIMER1CTL_RST_MASK (0x40000000U)
25308#define USBHS_GPTIMER1CTL_RST_SHIFT (30U)
25309/*! RST - Timer Reset
25310 * 0b0..No action
25311 * 0b1..Load counter value
25312 */
25313#define USBHS_GPTIMER1CTL_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RST_SHIFT)) & USBHS_GPTIMER1CTL_RST_MASK)
25314#define USBHS_GPTIMER1CTL_RUN_MASK (0x80000000U)
25315#define USBHS_GPTIMER1CTL_RUN_SHIFT (31U)
25316/*! RUN - Timer Run
25317 * 0b0..Timer stop
25318 * 0b1..Timer run
25319 */
25320#define USBHS_GPTIMER1CTL_RUN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RUN_SHIFT)) & USBHS_GPTIMER1CTL_RUN_MASK)
25321/*! @} */
25322
25323/*! @name USB_SBUSCFG - System Bus Interface Configuration Register */
25324/*! @{ */
25325#define USBHS_USB_SBUSCFG_BURSTMODE_MASK (0x7U)
25326#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT (0U)
25327/*! BURSTMODE - Burst mode
25328 * 0b000..INCR burst of unspecified length
25329 * 0b001..INCR4, non-multiple transfers of INCR4 is decomposed into singles.
25330 * 0b010..INCR8, non-multiple transfers of INCR8, is decomposed into INCR4 or singles.
25331 * 0b011..INCR16, non-multiple transfers of INCR16, is decomposed into INCR8, INCR4 or singles.
25332 * 0b100..Reserved, do not use.
25333 * 0b101..INCR4, non-multiple transfers of INCR4 is decomposed into smaller unspecified length bursts.
25334 * 0b110..INCR8, non-multiple transfers of INCR8 is decomposed into smaller unspecified length bursts.
25335 * 0b111..INCR16, non-multiple transfers of INCR16 is decomposed into smaller unspecified length bursts.
25336 */
25337#define USBHS_USB_SBUSCFG_BURSTMODE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USB_SBUSCFG_BURSTMODE_SHIFT)) & USBHS_USB_SBUSCFG_BURSTMODE_MASK)
25338/*! @} */
25339
25340/*! @name HCIVERSION - Host Controller Interface Version and Capability Registers Length Register */
25341/*! @{ */
25342#define USBHS_HCIVERSION_CAPLENGTH_MASK (0xFFU)
25343#define USBHS_HCIVERSION_CAPLENGTH_SHIFT (0U)
25344#define USBHS_HCIVERSION_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_CAPLENGTH_SHIFT)) & USBHS_HCIVERSION_CAPLENGTH_MASK)
25345#define USBHS_HCIVERSION_HCIVERSION_MASK (0xFFFF0000U)
25346#define USBHS_HCIVERSION_HCIVERSION_SHIFT (16U)
25347#define USBHS_HCIVERSION_HCIVERSION(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK)
25348/*! @} */
25349
25350/*! @name HCSPARAMS - Host Controller Structural Parameters Register */
25351/*! @{ */
25352#define USBHS_HCSPARAMS_N_PORTS_MASK (0xFU)
25353#define USBHS_HCSPARAMS_N_PORTS_SHIFT (0U)
25354#define USBHS_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK)
25355#define USBHS_HCSPARAMS_PPC_MASK (0x10U)
25356#define USBHS_HCSPARAMS_PPC_SHIFT (4U)
25357/*! PPC - Power Port Control
25358 * 0b1..Ports have power port switches
25359 */
25360#define USBHS_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK)
25361#define USBHS_HCSPARAMS_N_PCC_MASK (0xF00U)
25362#define USBHS_HCSPARAMS_N_PCC_SHIFT (8U)
25363#define USBHS_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK)
25364#define USBHS_HCSPARAMS_N_CC_MASK (0xF000U)
25365#define USBHS_HCSPARAMS_N_CC_SHIFT (12U)
25366#define USBHS_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK)
25367#define USBHS_HCSPARAMS_PI_MASK (0x10000U)
25368#define USBHS_HCSPARAMS_PI_SHIFT (16U)
25369/*! PI - Port Indicators
25370 * 0b0..No port indicator fields
25371 * 0b1..The port status and control registers include a R/W field for controlling the state of the port indicator
25372 */
25373#define USBHS_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK)
25374#define USBHS_HCSPARAMS_N_PTT_MASK (0xF00000U)
25375#define USBHS_HCSPARAMS_N_PTT_SHIFT (20U)
25376#define USBHS_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK)
25377#define USBHS_HCSPARAMS_N_TT_MASK (0xF000000U)
25378#define USBHS_HCSPARAMS_N_TT_SHIFT (24U)
25379#define USBHS_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK)
25380/*! @} */
25381
25382/*! @name HCCPARAMS - Host Controller Capability Parameters Register */
25383/*! @{ */
25384#define USBHS_HCCPARAMS_ADC_MASK (0x1U)
25385#define USBHS_HCCPARAMS_ADC_SHIFT (0U)
25386#define USBHS_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK)
25387#define USBHS_HCCPARAMS_PFL_MASK (0x2U)
25388#define USBHS_HCCPARAMS_PFL_SHIFT (1U)
25389#define USBHS_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK)
25390#define USBHS_HCCPARAMS_ASP_MASK (0x4U)
25391#define USBHS_HCCPARAMS_ASP_SHIFT (2U)
25392/*! ASP - Asynchronous Schedule Park capability
25393 * 0b0..Park not supported.
25394 * 0b1..Park supported.
25395 */
25396#define USBHS_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK)
25397#define USBHS_HCCPARAMS_IST_MASK (0xF0U)
25398#define USBHS_HCCPARAMS_IST_SHIFT (4U)
25399/*! IST - Isochronous Scheduling Threshold
25400 * 0b0000..The value of the least significant 3 bits indicates the number of microframes a host controller can hold a set of isochronous data structures (one or more) before flushing the state
25401 */
25402#define USBHS_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK)
25403#define USBHS_HCCPARAMS_EECP_MASK (0xFF00U)
25404#define USBHS_HCCPARAMS_EECP_SHIFT (8U)
25405/*! EECP - EHCI Extended Capabilities Pointer
25406 * 0b00000000..No extended capabilities are implemented
25407 */
25408#define USBHS_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK)
25409/*! @} */
25410
25411/*! @name DCIVERSION - Device Controller Interface Version */
25412/*! @{ */
25413#define USBHS_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
25414#define USBHS_DCIVERSION_DCIVERSION_SHIFT (0U)
25415#define USBHS_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK)
25416/*! @} */
25417
25418/*! @name DCCPARAMS - Device Controller Capability Parameters */
25419/*! @{ */
25420#define USBHS_DCCPARAMS_DEN_MASK (0x1FU)
25421#define USBHS_DCCPARAMS_DEN_SHIFT (0U)
25422#define USBHS_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK)
25423#define USBHS_DCCPARAMS_DC_MASK (0x80U)
25424#define USBHS_DCCPARAMS_DC_SHIFT (7U)
25425#define USBHS_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK)
25426#define USBHS_DCCPARAMS_HC_MASK (0x100U)
25427#define USBHS_DCCPARAMS_HC_SHIFT (8U)
25428#define USBHS_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK)
25429/*! @} */
25430
25431/*! @name USBCMD - USB Command Register */
25432/*! @{ */
25433#define USBHS_USBCMD_RS_MASK (0x1U)
25434#define USBHS_USBCMD_RS_SHIFT (0U)
25435#define USBHS_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK)
25436#define USBHS_USBCMD_RST_MASK (0x2U)
25437#define USBHS_USBCMD_RST_SHIFT (1U)
25438#define USBHS_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK)
25439#define USBHS_USBCMD_FS_MASK (0xCU)
25440#define USBHS_USBCMD_FS_SHIFT (2U)
25441/*! FS - Frame list Size
25442 * 0b00..When FS2 = 0, the size is 1024 elements (4096 bytes). When FS2 = 1, the size is 64 elements (256 bytes).
25443 * 0b01..When FS2 = 0, the size is 512 elements (2048 bytes). When FS2 = 1, the size is 32 elements (128 bytes).
25444 * 0b10..When FS2 = 0, the size is 256 elements (1024 bytes). When FS2 = 1, the size is 16 elements (64 bytes).
25445 * 0b11..When FS2 = 0, the size is 128 elements (512 bytes). When FS2 = 1, the size is 8 elements (32 bytes).
25446 */
25447#define USBHS_USBCMD_FS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_SHIFT)) & USBHS_USBCMD_FS_MASK)
25448#define USBHS_USBCMD_PSE_MASK (0x10U)
25449#define USBHS_USBCMD_PSE_SHIFT (4U)
25450/*! PSE - Periodic Schedule Enable
25451 * 0b0..Do not process periodic schedule.
25452 * 0b1..Use the PERIODICLISTBASE register to access the periodic schedule.
25453 */
25454#define USBHS_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK)
25455#define USBHS_USBCMD_ASE_MASK (0x20U)
25456#define USBHS_USBCMD_ASE_SHIFT (5U)
25457/*! ASE - Asynchronous Schedule Enable
25458 * 0b0..Do not process asynchronous schedule.
25459 * 0b1..Use the ASYNCLISTADDR register to access asynchronous schedule.
25460 */
25461#define USBHS_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK)
25462#define USBHS_USBCMD_IAA_MASK (0x40U)
25463#define USBHS_USBCMD_IAA_SHIFT (6U)
25464#define USBHS_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK)
25465#define USBHS_USBCMD_ASP_MASK (0x300U)
25466#define USBHS_USBCMD_ASP_SHIFT (8U)
25467#define USBHS_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK)
25468#define USBHS_USBCMD_ASPE_MASK (0x800U)
25469#define USBHS_USBCMD_ASPE_SHIFT (11U)
25470/*! ASPE - Asynchronous Schedule Park mode Enable
25471 * 0b0..Park mode disabled
25472 * 0b1..Park mode enabled
25473 */
25474#define USBHS_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK)
25475#define USBHS_USBCMD_SUTW_MASK (0x2000U)
25476#define USBHS_USBCMD_SUTW_SHIFT (13U)
25477#define USBHS_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK)
25478#define USBHS_USBCMD_ATDTW_MASK (0x4000U)
25479#define USBHS_USBCMD_ATDTW_SHIFT (14U)
25480#define USBHS_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK)
25481#define USBHS_USBCMD_FS2_MASK (0x8000U)
25482#define USBHS_USBCMD_FS2_SHIFT (15U)
25483#define USBHS_USBCMD_FS2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS2_SHIFT)) & USBHS_USBCMD_FS2_MASK)
25484#define USBHS_USBCMD_ITC_MASK (0xFF0000U)
25485#define USBHS_USBCMD_ITC_SHIFT (16U)
25486/*! ITC - Interrupt Threshold Control
25487 * 0b00000000..Immediate (no threshold)
25488 * 0b00000001..1 microframe
25489 * 0b00000010..2 microframes
25490 * 0b00000100..4 microframes
25491 * 0b00001000..8 microframes
25492 * 0b00010000..16 microframes
25493 * 0b00100000..32 microframes
25494 * 0b01000000..64 microframes
25495 */
25496#define USBHS_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK)
25497/*! @} */
25498
25499/*! @name USBSTS - USB Status Register */
25500/*! @{ */
25501#define USBHS_USBSTS_UI_MASK (0x1U)
25502#define USBHS_USBSTS_UI_SHIFT (0U)
25503#define USBHS_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK)
25504#define USBHS_USBSTS_UEI_MASK (0x2U)
25505#define USBHS_USBSTS_UEI_SHIFT (1U)
25506/*! UEI - USB Error Interrupt
25507 * 0b0..No error
25508 * 0b1..Error detected
25509 */
25510#define USBHS_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK)
25511#define USBHS_USBSTS_PCI_MASK (0x4U)
25512#define USBHS_USBSTS_PCI_SHIFT (2U)
25513#define USBHS_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK)
25514#define USBHS_USBSTS_FRI_MASK (0x8U)
25515#define USBHS_USBSTS_FRI_SHIFT (3U)
25516#define USBHS_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK)
25517#define USBHS_USBSTS_SEI_MASK (0x10U)
25518#define USBHS_USBSTS_SEI_SHIFT (4U)
25519/*! SEI - System Error
25520 * 0b0..Normal operation
25521 * 0b1..Error
25522 */
25523#define USBHS_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK)
25524#define USBHS_USBSTS_AAI_MASK (0x20U)
25525#define USBHS_USBSTS_AAI_SHIFT (5U)
25526/*! AAI - Interrupt on Async Advance
25527 * 0b0..No async advance interrupt
25528 * 0b1..Async advance interrupt
25529 */
25530#define USBHS_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK)
25531#define USBHS_USBSTS_URI_MASK (0x40U)
25532#define USBHS_USBSTS_URI_SHIFT (6U)
25533/*! URI - USB Reset received
25534 * 0b0..No reset received
25535 * 0b1..Reset received
25536 */
25537#define USBHS_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK)
25538#define USBHS_USBSTS_SRI_MASK (0x80U)
25539#define USBHS_USBSTS_SRI_SHIFT (7U)
25540#define USBHS_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK)
25541#define USBHS_USBSTS_SLI_MASK (0x100U)
25542#define USBHS_USBSTS_SLI_SHIFT (8U)
25543/*! SLI - Device-controller suspend
25544 * 0b0..Active
25545 * 0b1..Suspended
25546 */
25547#define USBHS_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK)
25548#define USBHS_USBSTS_HCH_MASK (0x1000U)
25549#define USBHS_USBSTS_HCH_SHIFT (12U)
25550/*! HCH - Host Controller Halted
25551 * 0b0..Running
25552 * 0b1..Halted
25553 */
25554#define USBHS_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK)
25555#define USBHS_USBSTS_RCL_MASK (0x2000U)
25556#define USBHS_USBSTS_RCL_SHIFT (13U)
25557/*! RCL - Reclamation
25558 * 0b0..Non-empty asynchronous schedule
25559 * 0b1..Empty asynchronous schedule
25560 */
25561#define USBHS_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK)
25562#define USBHS_USBSTS_PS_MASK (0x4000U)
25563#define USBHS_USBSTS_PS_SHIFT (14U)
25564/*! PS - Periodic schedule Status
25565 * 0b0..Disabled
25566 * 0b1..Enabled
25567 */
25568#define USBHS_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK)
25569#define USBHS_USBSTS_AS_MASK (0x8000U)
25570#define USBHS_USBSTS_AS_SHIFT (15U)
25571/*! AS - Asynchronous schedule Status
25572 * 0b0..Disabled
25573 * 0b1..Enabled
25574 */
25575#define USBHS_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK)
25576#define USBHS_USBSTS_NAKI_MASK (0x10000U)
25577#define USBHS_USBSTS_NAKI_SHIFT (16U)
25578#define USBHS_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK)
25579#define USBHS_USBSTS_UAI_MASK (0x40000U)
25580#define USBHS_USBSTS_UAI_SHIFT (18U)
25581#define USBHS_USBSTS_UAI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UAI_SHIFT)) & USBHS_USBSTS_UAI_MASK)
25582#define USBHS_USBSTS_UPI_MASK (0x80000U)
25583#define USBHS_USBSTS_UPI_SHIFT (19U)
25584#define USBHS_USBSTS_UPI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UPI_SHIFT)) & USBHS_USBSTS_UPI_MASK)
25585#define USBHS_USBSTS_TI0_MASK (0x1000000U)
25586#define USBHS_USBSTS_TI0_SHIFT (24U)
25587/*! TI0 - General purpose Timer 0 Interrupt
25588 * 0b0..No interrupt
25589 * 0b1..Interrupt occurred
25590 */
25591#define USBHS_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK)
25592#define USBHS_USBSTS_TI1_MASK (0x2000000U)
25593#define USBHS_USBSTS_TI1_SHIFT (25U)
25594/*! TI1 - General purpose Timer 1 Interrupt
25595 * 0b0..No interrupt
25596 * 0b1..Interrupt occurred
25597 */
25598#define USBHS_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK)
25599/*! @} */
25600
25601/*! @name USBINTR - USB Interrupt Enable Register */
25602/*! @{ */
25603#define USBHS_USBINTR_UE_MASK (0x1U)
25604#define USBHS_USBINTR_UE_SHIFT (0U)
25605/*! UE - USB interrupt Enable
25606 * 0b0..Disabled
25607 * 0b1..Enabled
25608 */
25609#define USBHS_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK)
25610#define USBHS_USBINTR_UEE_MASK (0x2U)
25611#define USBHS_USBINTR_UEE_SHIFT (1U)
25612/*! UEE - USB Error interrupt Enable
25613 * 0b0..Disabled
25614 * 0b1..Enabled
25615 */
25616#define USBHS_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK)
25617#define USBHS_USBINTR_PCE_MASK (0x4U)
25618#define USBHS_USBINTR_PCE_SHIFT (2U)
25619/*! PCE - Port Change detect Enable
25620 * 0b0..Disabled
25621 * 0b1..Enabled
25622 */
25623#define USBHS_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK)
25624#define USBHS_USBINTR_FRE_MASK (0x8U)
25625#define USBHS_USBINTR_FRE_SHIFT (3U)
25626/*! FRE - Frame list Rollover Enable
25627 * 0b0..Disabled
25628 * 0b1..Enabled
25629 */
25630#define USBHS_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK)
25631#define USBHS_USBINTR_SEE_MASK (0x10U)
25632#define USBHS_USBINTR_SEE_SHIFT (4U)
25633/*! SEE - System Error Enable
25634 * 0b0..Disabled
25635 * 0b1..Enabled
25636 */
25637#define USBHS_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK)
25638#define USBHS_USBINTR_AAE_MASK (0x20U)
25639#define USBHS_USBINTR_AAE_SHIFT (5U)
25640/*! AAE - Interrupt on Async advance Enable
25641 * 0b0..Disabled
25642 * 0b1..Enabled
25643 */
25644#define USBHS_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK)
25645#define USBHS_USBINTR_URE_MASK (0x40U)
25646#define USBHS_USBINTR_URE_SHIFT (6U)
25647/*! URE - USB-Reset Enable
25648 * 0b0..Disabled
25649 * 0b1..Enabled
25650 */
25651#define USBHS_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK)
25652#define USBHS_USBINTR_SRE_MASK (0x80U)
25653#define USBHS_USBINTR_SRE_SHIFT (7U)
25654/*! SRE - SOF-Received Enable
25655 * 0b0..Disabled
25656 * 0b1..Enabled
25657 */
25658#define USBHS_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK)
25659#define USBHS_USBINTR_SLE_MASK (0x100U)
25660#define USBHS_USBINTR_SLE_SHIFT (8U)
25661/*! SLE - Sleep (DC suspend) Enable
25662 * 0b0..Disabled
25663 * 0b1..Enabled
25664 */
25665#define USBHS_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK)
25666#define USBHS_USBINTR_NAKE_MASK (0x10000U)
25667#define USBHS_USBINTR_NAKE_SHIFT (16U)
25668/*! NAKE - NAK Interrupt Enable
25669 * 0b0..Disabled
25670 * 0b1..Enabled
25671 */
25672#define USBHS_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK)
25673#define USBHS_USBINTR_UAIE_MASK (0x40000U)
25674#define USBHS_USBINTR_UAIE_SHIFT (18U)
25675#define USBHS_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK)
25676#define USBHS_USBINTR_UPIE_MASK (0x80000U)
25677#define USBHS_USBINTR_UPIE_SHIFT (19U)
25678#define USBHS_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK)
25679#define USBHS_USBINTR_TIE0_MASK (0x1000000U)
25680#define USBHS_USBINTR_TIE0_SHIFT (24U)
25681/*! TIE0 - General purpose Timer 0 Interrupt Enable
25682 * 0b0..Disabled
25683 * 0b1..Enabled
25684 */
25685#define USBHS_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK)
25686#define USBHS_USBINTR_TIE1_MASK (0x2000000U)
25687#define USBHS_USBINTR_TIE1_SHIFT (25U)
25688/*! TIE1 - General purpose Timer 1 Interrupt Enable
25689 * 0b0..Disabled
25690 * 0b1..Enabled
25691 */
25692#define USBHS_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK)
25693/*! @} */
25694
25695/*! @name FRINDEX - Frame Index Register */
25696/*! @{ */
25697#define USBHS_FRINDEX_FRINDEX_MASK (0x3FFFU)
25698#define USBHS_FRINDEX_FRINDEX_SHIFT (0U)
25699#define USBHS_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK)
25700#define USBHS_FRINDEX_Reerved_MASK (0xFFFFC000U)
25701#define USBHS_FRINDEX_Reerved_SHIFT (14U)
25702#define USBHS_FRINDEX_Reerved(x) (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_Reerved_SHIFT)) & USBHS_FRINDEX_Reerved_MASK)
25703/*! @} */
25704
25705/*! @name DEVICEADDR - Device Address Register */
25706/*! @{ */
25707#define USBHS_DEVICEADDR_USBADRA_MASK (0x1000000U)
25708#define USBHS_DEVICEADDR_USBADRA_SHIFT (24U)
25709/*! USBADRA - Device Address Advance
25710 * 0b0..Writes to USBADR are instantaneous.
25711 * 0b1..When this bit is written to a 1 at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR is loaded from the holding register.
25712 */
25713#define USBHS_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK)
25714#define USBHS_DEVICEADDR_USBADR_MASK (0xFE000000U)
25715#define USBHS_DEVICEADDR_USBADR_SHIFT (25U)
25716#define USBHS_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK)
25717/*! @} */
25718
25719/*! @name PERIODICLISTBASE - Periodic Frame List Base Address Register */
25720/*! @{ */
25721#define USBHS_PERIODICLISTBASE_PERBASE_MASK (0xFFFFF000U)
25722#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT (12U)
25723#define USBHS_PERIODICLISTBASE_PERBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_PERBASE_SHIFT)) & USBHS_PERIODICLISTBASE_PERBASE_MASK)
25724/*! @} */
25725
25726/*! @name ASYNCLISTADDR - Current Asynchronous List Address Register */
25727/*! @{ */
25728#define USBHS_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
25729#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
25730#define USBHS_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK)
25731/*! @} */
25732
25733/*! @name EPLISTADDR - Endpoint List Address Register */
25734/*! @{ */
25735#define USBHS_EPLISTADDR_EPBASE_MASK (0xFFFFF800U)
25736#define USBHS_EPLISTADDR_EPBASE_SHIFT (11U)
25737#define USBHS_EPLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPLISTADDR_EPBASE_SHIFT)) & USBHS_EPLISTADDR_EPBASE_MASK)
25738/*! @} */
25739
25740/*! @name TTCTRL - Host TT Asynchronous Buffer Control */
25741/*! @{ */
25742#define USBHS_TTCTRL_TTHA_MASK (0x7F000000U)
25743#define USBHS_TTCTRL_TTHA_SHIFT (24U)
25744#define USBHS_TTCTRL_TTHA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_TTHA_SHIFT)) & USBHS_TTCTRL_TTHA_MASK)
25745#define USBHS_TTCTRL_Reerved_MASK (0x80000000U)
25746#define USBHS_TTCTRL_Reerved_SHIFT (31U)
25747#define USBHS_TTCTRL_Reerved(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_Reerved_SHIFT)) & USBHS_TTCTRL_Reerved_MASK)
25748/*! @} */
25749
25750/*! @name BURSTSIZE - Master Interface Data Burst Size Register */
25751/*! @{ */
25752#define USBHS_BURSTSIZE_RXPBURST_MASK (0xFFU)
25753#define USBHS_BURSTSIZE_RXPBURST_SHIFT (0U)
25754#define USBHS_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK)
25755#define USBHS_BURSTSIZE_TXPBURST_MASK (0xFF00U)
25756#define USBHS_BURSTSIZE_TXPBURST_SHIFT (8U)
25757#define USBHS_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK)
25758/*! @} */
25759
25760/*! @name TXFILLTUNING - Transmit FIFO Tuning Control Register */
25761/*! @{ */
25762#define USBHS_TXFILLTUNING_TXSCHOH_MASK (0x7FU)
25763#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT (0U)
25764#define USBHS_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK)
25765#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
25766#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
25767#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK)
25768#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
25769#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
25770#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK)
25771/*! @} */
25772
25773/*! @name ENDPTNAK - Endpoint NAK Register */
25774/*! @{ */
25775#define USBHS_ENDPTNAK_EPRN_MASK (0xFU)
25776#define USBHS_ENDPTNAK_EPRN_SHIFT (0U)
25777#define USBHS_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK)
25778#define USBHS_ENDPTNAK_EPTN_MASK (0xF0000U)
25779#define USBHS_ENDPTNAK_EPTN_SHIFT (16U)
25780#define USBHS_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK)
25781/*! @} */
25782
25783/*! @name ENDPTNAKEN - Endpoint NAK Enable Register */
25784/*! @{ */
25785#define USBHS_ENDPTNAKEN_EPRNE_MASK (0xFU)
25786#define USBHS_ENDPTNAKEN_EPRNE_SHIFT (0U)
25787#define USBHS_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK)
25788#define USBHS_ENDPTNAKEN_EPTNE_MASK (0xF0000U)
25789#define USBHS_ENDPTNAKEN_EPTNE_SHIFT (16U)
25790#define USBHS_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK)
25791/*! @} */
25792
25793/*! @name PORTSC1 - Port Status and Control Registers */
25794/*! @{ */
25795#define USBHS_PORTSC1_CCS_MASK (0x1U)
25796#define USBHS_PORTSC1_CCS_SHIFT (0U)
25797/*! CCS - Current Connect Status
25798 * 0b0..No device present (host mode) or attached (device mode)
25799 * 0b1..Device is present (host mode) or attached (device mode)
25800 */
25801#define USBHS_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK)
25802#define USBHS_PORTSC1_CSC_MASK (0x2U)
25803#define USBHS_PORTSC1_CSC_SHIFT (1U)
25804/*! CSC - Connect Change Status
25805 * 0b0..No change
25806 * 0b1..Connect status has changed
25807 */
25808#define USBHS_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK)
25809#define USBHS_PORTSC1_PE_MASK (0x4U)
25810#define USBHS_PORTSC1_PE_SHIFT (2U)
25811#define USBHS_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK)
25812#define USBHS_PORTSC1_PEC_MASK (0x8U)
25813#define USBHS_PORTSC1_PEC_SHIFT (3U)
25814/*! PEC - Port Enable/disable Change
25815 * 0b0..No change
25816 * 0b1..Port disabled
25817 */
25818#define USBHS_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK)
25819#define USBHS_PORTSC1_OCA_MASK (0x10U)
25820#define USBHS_PORTSC1_OCA_SHIFT (4U)
25821/*! OCA - Over-current active
25822 * 0b0..Port not in over-current condition
25823 * 0b1..Port currently in over-current condition
25824 */
25825#define USBHS_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK)
25826#define USBHS_PORTSC1_OCC_MASK (0x20U)
25827#define USBHS_PORTSC1_OCC_SHIFT (5U)
25828/*! OCC - Over-Current Change
25829 * 0b0..No over-current
25830 * 0b1..Over-current detect
25831 */
25832#define USBHS_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK)
25833#define USBHS_PORTSC1_FPR_MASK (0x40U)
25834#define USBHS_PORTSC1_FPR_SHIFT (6U)
25835/*! FPR - Force Port Resume
25836 * 0b0..No resume (K-state) detected/driven on port
25837 * 0b1..Resume detected/driven on port
25838 */
25839#define USBHS_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK)
25840#define USBHS_PORTSC1_SUSP_MASK (0x80U)
25841#define USBHS_PORTSC1_SUSP_SHIFT (7U)
25842/*! SUSP - Suspend
25843 * 0b0..Port not in suspend state
25844 * 0b1..Port in suspend state
25845 */
25846#define USBHS_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK)
25847#define USBHS_PORTSC1_PR_MASK (0x100U)
25848#define USBHS_PORTSC1_PR_SHIFT (8U)
25849/*! PR - Port Reset
25850 * 0b0..Port is not in reset
25851 * 0b1..Port is in reset
25852 */
25853#define USBHS_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK)
25854#define USBHS_PORTSC1_HSP_MASK (0x200U)
25855#define USBHS_PORTSC1_HSP_SHIFT (9U)
25856/*! HSP - High Speed Port.
25857 * 0b0..FS or LS
25858 * 0b1..HS
25859 */
25860#define USBHS_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK)
25861#define USBHS_PORTSC1_LS_MASK (0xC00U)
25862#define USBHS_PORTSC1_LS_SHIFT (10U)
25863/*! LS - Line Status
25864 * 0b00..SE0
25865 * 0b01..J-state
25866 * 0b10..K-state
25867 * 0b11..Undefined
25868 */
25869#define USBHS_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK)
25870#define USBHS_PORTSC1_PP_MASK (0x1000U)
25871#define USBHS_PORTSC1_PP_SHIFT (12U)
25872#define USBHS_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK)
25873#define USBHS_PORTSC1_PO_MASK (0x2000U)
25874#define USBHS_PORTSC1_PO_SHIFT (13U)
25875#define USBHS_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK)
25876#define USBHS_PORTSC1_PIC_MASK (0xC000U)
25877#define USBHS_PORTSC1_PIC_SHIFT (14U)
25878#define USBHS_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK)
25879#define USBHS_PORTSC1_PTC_MASK (0xF0000U)
25880#define USBHS_PORTSC1_PTC_SHIFT (16U)
25881/*! PTC - Port Test Control
25882 * 0b0000..Not enabled
25883 * 0b0001..J_STATE
25884 * 0b0010..K_STATE
25885 * 0b0011..SE0_NAK
25886 * 0b0100..Packet
25887 * 0b0101..FORCE_ENABLE_HS
25888 * 0b0110..FORCE_ENABLE_FS
25889 * 0b0111..FORCE_ENABLE_LS
25890 */
25891#define USBHS_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK)
25892#define USBHS_PORTSC1_WKCN_MASK (0x100000U)
25893#define USBHS_PORTSC1_WKCN_SHIFT (20U)
25894#define USBHS_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK)
25895#define USBHS_PORTSC1_WKDS_MASK (0x200000U)
25896#define USBHS_PORTSC1_WKDS_SHIFT (21U)
25897#define USBHS_PORTSC1_WKDS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDS_SHIFT)) & USBHS_PORTSC1_WKDS_MASK)
25898#define USBHS_PORTSC1_WKOC_MASK (0x400000U)
25899#define USBHS_PORTSC1_WKOC_SHIFT (22U)
25900#define USBHS_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK)
25901#define USBHS_PORTSC1_PHCD_MASK (0x800000U)
25902#define USBHS_PORTSC1_PHCD_SHIFT (23U)
25903#define USBHS_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK)
25904#define USBHS_PORTSC1_PFSC_MASK (0x1000000U)
25905#define USBHS_PORTSC1_PFSC_SHIFT (24U)
25906/*! PFSC - Port force Full-Speed Connect
25907 * 0b0..Allow the port to identify itself as high speed
25908 * 0b1..Force the port to only connect at full speed
25909 */
25910#define USBHS_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK)
25911#define USBHS_PORTSC1_PTS2_MASK (0x2000000U)
25912#define USBHS_PORTSC1_PTS2_SHIFT (25U)
25913#define USBHS_PORTSC1_PTS2(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS2_SHIFT)) & USBHS_PORTSC1_PTS2_MASK)
25914#define USBHS_PORTSC1_PSPD_MASK (0xC000000U)
25915#define USBHS_PORTSC1_PSPD_SHIFT (26U)
25916/*! PSPD - Port Speed
25917 * 0b00..Full speed
25918 * 0b01..Low speed
25919 * 0b10..High speed
25920 * 0b11..Undefined
25921 */
25922#define USBHS_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK)
25923#define USBHS_PORTSC1_PTS_MASK (0xC0000000U)
25924#define USBHS_PORTSC1_PTS_SHIFT (30U)
25925/*! PTS - Port Transceiver Select [1:0]
25926 * 0b00..Use UTMI transceiver interface.
25927 */
25928#define USBHS_PORTSC1_PTS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_SHIFT)) & USBHS_PORTSC1_PTS_MASK)
25929/*! @} */
25930
25931/*! @name OTGSC - On-the-Go Status and Control Register */
25932/*! @{ */
25933#define USBHS_OTGSC_VD_MASK (0x1U)
25934#define USBHS_OTGSC_VD_SHIFT (0U)
25935#define USBHS_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK)
25936#define USBHS_OTGSC_VC_MASK (0x2U)
25937#define USBHS_OTGSC_VC_SHIFT (1U)
25938#define USBHS_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK)
25939#define USBHS_OTGSC_HAAR_MASK (0x4U)
25940#define USBHS_OTGSC_HAAR_SHIFT (2U)
25941/*! HAAR - Hardware Assist Auto-Reset
25942 * 0b0..Disabled.
25943 * 0b1..Enable automatic reset after connect on host port.
25944 */
25945#define USBHS_OTGSC_HAAR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HAAR_SHIFT)) & USBHS_OTGSC_HAAR_MASK)
25946#define USBHS_OTGSC_OT_MASK (0x8U)
25947#define USBHS_OTGSC_OT_SHIFT (3U)
25948/*! OT - OTG Termination
25949 * 0b0..Disable pull-down on DM
25950 * 0b1..Enable pull-down on DM
25951 */
25952#define USBHS_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK)
25953#define USBHS_OTGSC_DP_MASK (0x10U)
25954#define USBHS_OTGSC_DP_SHIFT (4U)
25955/*! DP - Data Pulsing
25956 * 0b0..The pull-up on DP is not asserted
25957 * 0b1..The pull-up on DP is asserted for data pulsing during SRP
25958 */
25959#define USBHS_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK)
25960#define USBHS_OTGSC_IDPU_MASK (0x20U)
25961#define USBHS_OTGSC_IDPU_SHIFT (5U)
25962/*! IDPU - ID Pull-Up
25963 * 0b0..Disable pull-up. ID input not sampled.
25964 * 0b1..Enable pull-up
25965 */
25966#define USBHS_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK)
25967#define USBHS_OTGSC_HABA_MASK (0x80U)
25968#define USBHS_OTGSC_HABA_SHIFT (7U)
25969/*! HABA - Hardware Assist B-Disconnect to A-connect
25970 * 0b0..Disabled.
25971 * 0b1..Enable automatic B-disconnect to A-connect sequence.
25972 */
25973#define USBHS_OTGSC_HABA(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HABA_SHIFT)) & USBHS_OTGSC_HABA_MASK)
25974#define USBHS_OTGSC_ID_MASK (0x100U)
25975#define USBHS_OTGSC_ID_SHIFT (8U)
25976/*! ID - USB ID
25977 * 0b0..A device
25978 * 0b1..B device
25979 */
25980#define USBHS_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK)
25981#define USBHS_OTGSC_AVV_MASK (0x200U)
25982#define USBHS_OTGSC_AVV_SHIFT (9U)
25983/*! AVV - A VBus Valid
25984 * 0b0..VBus is below A VBus valid threshold
25985 * 0b1..VBus is above A VBus valid threshold
25986 */
25987#define USBHS_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK)
25988#define USBHS_OTGSC_ASV_MASK (0x400U)
25989#define USBHS_OTGSC_ASV_SHIFT (10U)
25990/*! ASV - A Session Valid
25991 * 0b0..VBus is below A session valid threshold
25992 * 0b1..VBus is above A session valid threshold
25993 */
25994#define USBHS_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK)
25995#define USBHS_OTGSC_BSV_MASK (0x800U)
25996#define USBHS_OTGSC_BSV_SHIFT (11U)
25997/*! BSV - B Session Valid
25998 * 0b0..VBus is below B session valid threshold
25999 * 0b1..VBus is above B session valid threshold
26000 */
26001#define USBHS_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK)
26002#define USBHS_OTGSC_BSE_MASK (0x1000U)
26003#define USBHS_OTGSC_BSE_SHIFT (12U)
26004/*! BSE - B Session End
26005 * 0b0..VBus is above B session end threshold
26006 * 0b1..VBus is below B session end threshold
26007 */
26008#define USBHS_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK)
26009#define USBHS_OTGSC_MST_MASK (0x2000U)
26010#define USBHS_OTGSC_MST_SHIFT (13U)
26011#define USBHS_OTGSC_MST(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MST_SHIFT)) & USBHS_OTGSC_MST_MASK)
26012#define USBHS_OTGSC_DPS_MASK (0x4000U)
26013#define USBHS_OTGSC_DPS_SHIFT (14U)
26014/*! DPS - Data bus Pulsing Status
26015 * 0b0..No pulsing on port
26016 * 0b1..Pulsing detected on port
26017 */
26018#define USBHS_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK)
26019#define USBHS_OTGSC_IDIS_MASK (0x10000U)
26020#define USBHS_OTGSC_IDIS_SHIFT (16U)
26021#define USBHS_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK)
26022#define USBHS_OTGSC_AVVIS_MASK (0x20000U)
26023#define USBHS_OTGSC_AVVIS_SHIFT (17U)
26024#define USBHS_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK)
26025#define USBHS_OTGSC_ASVIS_MASK (0x40000U)
26026#define USBHS_OTGSC_ASVIS_SHIFT (18U)
26027#define USBHS_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK)
26028#define USBHS_OTGSC_BSVIS_MASK (0x80000U)
26029#define USBHS_OTGSC_BSVIS_SHIFT (19U)
26030#define USBHS_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK)
26031#define USBHS_OTGSC_BSEIS_MASK (0x100000U)
26032#define USBHS_OTGSC_BSEIS_SHIFT (20U)
26033#define USBHS_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK)
26034#define USBHS_OTGSC_MSS_MASK (0x200000U)
26035#define USBHS_OTGSC_MSS_SHIFT (21U)
26036#define USBHS_OTGSC_MSS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSS_SHIFT)) & USBHS_OTGSC_MSS_MASK)
26037#define USBHS_OTGSC_DPIS_MASK (0x400000U)
26038#define USBHS_OTGSC_DPIS_SHIFT (22U)
26039#define USBHS_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK)
26040#define USBHS_OTGSC_IDIE_MASK (0x1000000U)
26041#define USBHS_OTGSC_IDIE_SHIFT (24U)
26042/*! IDIE - USB ID Interrupt Enable
26043 * 0b0..Disable
26044 * 0b1..Enable
26045 */
26046#define USBHS_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK)
26047#define USBHS_OTGSC_AVVIE_MASK (0x2000000U)
26048#define USBHS_OTGSC_AVVIE_SHIFT (25U)
26049/*! AVVIE - A VBUS Valid Interrupt Enable
26050 * 0b0..Disable
26051 * 0b1..Enable
26052 */
26053#define USBHS_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK)
26054#define USBHS_OTGSC_ASVIE_MASK (0x4000000U)
26055#define USBHS_OTGSC_ASVIE_SHIFT (26U)
26056/*! ASVIE - A Session Valid Interrupt Enable
26057 * 0b0..Disable
26058 * 0b1..Enable
26059 */
26060#define USBHS_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK)
26061#define USBHS_OTGSC_BSVIE_MASK (0x8000000U)
26062#define USBHS_OTGSC_BSVIE_SHIFT (27U)
26063/*! BSVIE - B Session Valid Interrupt Enable
26064 * 0b0..Disable
26065 * 0b1..Enable
26066 */
26067#define USBHS_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK)
26068#define USBHS_OTGSC_BSEIE_MASK (0x10000000U)
26069#define USBHS_OTGSC_BSEIE_SHIFT (28U)
26070/*! BSEIE - B Session End Interrupt Enable
26071 * 0b0..Disable
26072 * 0b1..Enable
26073 */
26074#define USBHS_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK)
26075#define USBHS_OTGSC_MSE_MASK (0x20000000U)
26076#define USBHS_OTGSC_MSE_SHIFT (29U)
26077/*! MSE - 1 Milli-Second timer interrupt Enable
26078 * 0b0..Disable
26079 * 0b1..Enable
26080 */
26081#define USBHS_OTGSC_MSE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSE_SHIFT)) & USBHS_OTGSC_MSE_MASK)
26082#define USBHS_OTGSC_DPIE_MASK (0x40000000U)
26083#define USBHS_OTGSC_DPIE_SHIFT (30U)
26084/*! DPIE - Data Pulse Interrupt Enable
26085 * 0b0..Disable
26086 * 0b1..Enable
26087 */
26088#define USBHS_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK)
26089/*! @} */
26090
26091/*! @name USBMODE - USB Mode Register */
26092/*! @{ */
26093#define USBHS_USBMODE_CM_MASK (0x3U)
26094#define USBHS_USBMODE_CM_SHIFT (0U)
26095/*! CM - Controller Mode
26096 * 0b00..Idle (default for the USBHS module)
26097 * 0b01..Reserved
26098 * 0b10..Device controller
26099 * 0b11..Host controller
26100 */
26101#define USBHS_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK)
26102#define USBHS_USBMODE_ES_MASK (0x4U)
26103#define USBHS_USBMODE_ES_SHIFT (2U)
26104/*! ES - Endian Select
26105 * 0b0..Little endian. First byte referenced in least significant byte of 32-bit word.
26106 * 0b1..Big endian. First byte referenced in most significant byte of 32-bit word.
26107 */
26108#define USBHS_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK)
26109#define USBHS_USBMODE_SLOM_MASK (0x8U)
26110#define USBHS_USBMODE_SLOM_SHIFT (3U)
26111#define USBHS_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK)
26112#define USBHS_USBMODE_SDIS_MASK (0x10U)
26113#define USBHS_USBMODE_SDIS_SHIFT (4U)
26114/*! SDIS - Stream DISable
26115 * 0b0..Inactive
26116 * 0b1..Active
26117 */
26118#define USBHS_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK)
26119#define USBHS_USBMODE_TXHSD_MASK (0x7000U)
26120#define USBHS_USBMODE_TXHSD_SHIFT (12U)
26121/*! TXHSD - Tx to Tx HS Delay
26122 * 0b000..10
26123 * 0b001..11
26124 * 0b010..12
26125 * 0b011..13
26126 * 0b100..14
26127 * 0b101..15
26128 * 0b110..16
26129 * 0b111..17
26130 */
26131#define USBHS_USBMODE_TXHSD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_TXHSD_SHIFT)) & USBHS_USBMODE_TXHSD_MASK)
26132/*! @} */
26133
26134/*! @name EPSETUPSR - Endpoint Setup Status Register */
26135/*! @{ */
26136#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK (0xFU)
26137#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT (0U)
26138#define USBHS_EPSETUPSR_EPSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT)) & USBHS_EPSETUPSR_EPSETUPSTAT_MASK)
26139/*! @} */
26140
26141/*! @name EPPRIME - Endpoint Initialization Register */
26142/*! @{ */
26143#define USBHS_EPPRIME_PERB_MASK (0xFU)
26144#define USBHS_EPPRIME_PERB_SHIFT (0U)
26145#define USBHS_EPPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PERB_SHIFT)) & USBHS_EPPRIME_PERB_MASK)
26146#define USBHS_EPPRIME_PETB_MASK (0xF0000U)
26147#define USBHS_EPPRIME_PETB_SHIFT (16U)
26148#define USBHS_EPPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PETB_SHIFT)) & USBHS_EPPRIME_PETB_MASK)
26149/*! @} */
26150
26151/*! @name EPFLUSH - Endpoint Flush Register */
26152/*! @{ */
26153#define USBHS_EPFLUSH_FERB_MASK (0xFU)
26154#define USBHS_EPFLUSH_FERB_SHIFT (0U)
26155#define USBHS_EPFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FERB_SHIFT)) & USBHS_EPFLUSH_FERB_MASK)
26156#define USBHS_EPFLUSH_FETB_MASK (0xF0000U)
26157#define USBHS_EPFLUSH_FETB_SHIFT (16U)
26158#define USBHS_EPFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FETB_SHIFT)) & USBHS_EPFLUSH_FETB_MASK)
26159/*! @} */
26160
26161/*! @name EPSR - Endpoint Status Register */
26162/*! @{ */
26163#define USBHS_EPSR_ERBR_MASK (0xFU)
26164#define USBHS_EPSR_ERBR_SHIFT (0U)
26165#define USBHS_EPSR_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ERBR_SHIFT)) & USBHS_EPSR_ERBR_MASK)
26166#define USBHS_EPSR_ETBR_MASK (0xF0000U)
26167#define USBHS_EPSR_ETBR_SHIFT (16U)
26168#define USBHS_EPSR_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ETBR_SHIFT)) & USBHS_EPSR_ETBR_MASK)
26169/*! @} */
26170
26171/*! @name EPCOMPLETE - Endpoint Complete Register */
26172/*! @{ */
26173#define USBHS_EPCOMPLETE_ERCE_MASK (0xFU)
26174#define USBHS_EPCOMPLETE_ERCE_SHIFT (0U)
26175#define USBHS_EPCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ERCE_SHIFT)) & USBHS_EPCOMPLETE_ERCE_MASK)
26176#define USBHS_EPCOMPLETE_ETCE_MASK (0xF0000U)
26177#define USBHS_EPCOMPLETE_ETCE_SHIFT (16U)
26178#define USBHS_EPCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ETCE_SHIFT)) & USBHS_EPCOMPLETE_ETCE_MASK)
26179/*! @} */
26180
26181/*! @name EPCR0 - Endpoint Control Register 0 */
26182/*! @{ */
26183#define USBHS_EPCR0_RXS_MASK (0x1U)
26184#define USBHS_EPCR0_RXS_SHIFT (0U)
26185/*! RXS - RX endpoint Stall
26186 * 0b0..Endpoint OK
26187 * 0b1..Endpoint stalled
26188 */
26189#define USBHS_EPCR0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXS_SHIFT)) & USBHS_EPCR0_RXS_MASK)
26190#define USBHS_EPCR0_RXT_MASK (0xCU)
26191#define USBHS_EPCR0_RXT_SHIFT (2U)
26192/*! RXT - RX endpoint Type
26193 * 0b00..Control
26194 */
26195#define USBHS_EPCR0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXT_SHIFT)) & USBHS_EPCR0_RXT_MASK)
26196#define USBHS_EPCR0_RXE_MASK (0x80U)
26197#define USBHS_EPCR0_RXE_SHIFT (7U)
26198/*! RXE - RX endpoint Enable
26199 * 0b1..Enabled
26200 */
26201#define USBHS_EPCR0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXE_SHIFT)) & USBHS_EPCR0_RXE_MASK)
26202#define USBHS_EPCR0_TXS_MASK (0x10000U)
26203#define USBHS_EPCR0_TXS_SHIFT (16U)
26204/*! TXS - TX Endpoint Stall
26205 * 0b0..Endpoint OK
26206 * 0b1..Endpoint stalled
26207 */
26208#define USBHS_EPCR0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXS_SHIFT)) & USBHS_EPCR0_TXS_MASK)
26209#define USBHS_EPCR0_TXT_MASK (0xC0000U)
26210#define USBHS_EPCR0_TXT_SHIFT (18U)
26211/*! TXT - TX Endpoint Type
26212 * 0b00..Control
26213 */
26214#define USBHS_EPCR0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXT_SHIFT)) & USBHS_EPCR0_TXT_MASK)
26215#define USBHS_EPCR0_TXE_MASK (0x800000U)
26216#define USBHS_EPCR0_TXE_SHIFT (23U)
26217/*! TXE - TX Endpoint Enable
26218 * 0b1..Enable
26219 */
26220#define USBHS_EPCR0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXE_SHIFT)) & USBHS_EPCR0_TXE_MASK)
26221/*! @} */
26222
26223/*! @name EPCR - Endpoint Control Register n */
26224/*! @{ */
26225#define USBHS_EPCR_RXS_MASK (0x1U)
26226#define USBHS_EPCR_RXS_SHIFT (0U)
26227/*! RXS - RX endpoint Stall
26228 * 0b0..Endpoint OK
26229 * 0b1..Endpoint stalled
26230 */
26231#define USBHS_EPCR_RXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXS_SHIFT)) & USBHS_EPCR_RXS_MASK)
26232#define USBHS_EPCR_RXD_MASK (0x2U)
26233#define USBHS_EPCR_RXD_SHIFT (1U)
26234#define USBHS_EPCR_RXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXD_SHIFT)) & USBHS_EPCR_RXD_MASK)
26235#define USBHS_EPCR_RXT_MASK (0xCU)
26236#define USBHS_EPCR_RXT_SHIFT (2U)
26237/*! RXT - RX endpoint Type
26238 * 0b00..Control
26239 * 0b01..Isochronous
26240 * 0b10..Bulk
26241 * 0b11..Interrupt
26242 */
26243#define USBHS_EPCR_RXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXT_SHIFT)) & USBHS_EPCR_RXT_MASK)
26244#define USBHS_EPCR_RXI_MASK (0x20U)
26245#define USBHS_EPCR_RXI_SHIFT (5U)
26246/*! RXI - RX data toggle Inhibit
26247 * 0b0..PID sequencing enabled
26248 * 0b1..PID sequencing disabled
26249 */
26250#define USBHS_EPCR_RXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXI_SHIFT)) & USBHS_EPCR_RXI_MASK)
26251#define USBHS_EPCR_RXR_MASK (0x40U)
26252#define USBHS_EPCR_RXR_SHIFT (6U)
26253#define USBHS_EPCR_RXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXR_SHIFT)) & USBHS_EPCR_RXR_MASK)
26254#define USBHS_EPCR_RXE_MASK (0x80U)
26255#define USBHS_EPCR_RXE_SHIFT (7U)
26256/*! RXE - RX endpoint Enable
26257 * 0b0..Disabled
26258 * 0b1..Enabled
26259 */
26260#define USBHS_EPCR_RXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXE_SHIFT)) & USBHS_EPCR_RXE_MASK)
26261#define USBHS_EPCR_TXS_MASK (0x10000U)
26262#define USBHS_EPCR_TXS_SHIFT (16U)
26263/*! TXS - TX endpoint Stall
26264 * 0b0..Endpoint OK
26265 * 0b1..Endpoint stalled
26266 */
26267#define USBHS_EPCR_TXS(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXS_SHIFT)) & USBHS_EPCR_TXS_MASK)
26268#define USBHS_EPCR_TXD_MASK (0x20000U)
26269#define USBHS_EPCR_TXD_SHIFT (17U)
26270#define USBHS_EPCR_TXD(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXD_SHIFT)) & USBHS_EPCR_TXD_MASK)
26271#define USBHS_EPCR_TXT_MASK (0xC0000U)
26272#define USBHS_EPCR_TXT_SHIFT (18U)
26273/*! TXT - TX endpoint Type
26274 * 0b00..Control
26275 * 0b01..Isochronous
26276 * 0b10..Bulk
26277 * 0b11..Interrupt
26278 */
26279#define USBHS_EPCR_TXT(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXT_SHIFT)) & USBHS_EPCR_TXT_MASK)
26280#define USBHS_EPCR_TXI_MASK (0x200000U)
26281#define USBHS_EPCR_TXI_SHIFT (21U)
26282/*! TXI - TX data toggle Inhibit
26283 * 0b0..PID sequencing enabled
26284 * 0b1..PID sequencing disabled
26285 */
26286#define USBHS_EPCR_TXI(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXI_SHIFT)) & USBHS_EPCR_TXI_MASK)
26287#define USBHS_EPCR_TXR_MASK (0x400000U)
26288#define USBHS_EPCR_TXR_SHIFT (22U)
26289#define USBHS_EPCR_TXR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXR_SHIFT)) & USBHS_EPCR_TXR_MASK)
26290#define USBHS_EPCR_TXE_MASK (0x800000U)
26291#define USBHS_EPCR_TXE_SHIFT (23U)
26292/*! TXE - TX endpoint Enable
26293 * 0b0..Disabled
26294 * 0b1..Enabled
26295 */
26296#define USBHS_EPCR_TXE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXE_SHIFT)) & USBHS_EPCR_TXE_MASK)
26297/*! @} */
26298
26299/* The count of USBHS_EPCR */
26300#define USBHS_EPCR_COUNT (7U)
26301
26302/*! @name USBGENCTRL - USB General Control Register */
26303/*! @{ */
26304#define USBHS_USBGENCTRL_WU_IE_MASK (0x1U)
26305#define USBHS_USBGENCTRL_WU_IE_SHIFT (0U)
26306/*! WU_IE - Wakeup Interrupt Enable
26307 * 0b0..Disabled
26308 * 0b1..Enabled
26309 */
26310#define USBHS_USBGENCTRL_WU_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_IE_SHIFT)) & USBHS_USBGENCTRL_WU_IE_MASK)
26311#define USBHS_USBGENCTRL_WU_INT_CLR_MASK (0x20U)
26312#define USBHS_USBGENCTRL_WU_INT_CLR_SHIFT (5U)
26313/*! WU_INT_CLR - Wakeup Interrupt Clear
26314 * 0b0..Default, no action.
26315 * 0b1..Clear the wake-up interrupt.
26316 */
26317#define USBHS_USBGENCTRL_WU_INT_CLR(x) (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_INT_CLR_SHIFT)) & USBHS_USBGENCTRL_WU_INT_CLR_MASK)
26318/*! @} */
26319
26320
26321/*!
26322 * @}
26323 */ /* end of group USBHS_Register_Masks */
26324
26325
26326/* USBHS - Peripheral instance base addresses */
26327/** Peripheral USBHS base address */
26328#define USBHS_BASE (0x400A1000u)
26329/** Peripheral USBHS base pointer */
26330#define USBHS ((USBHS_Type *)USBHS_BASE)
26331/** Array initializer of USBHS peripheral base addresses */
26332#define USBHS_BASE_ADDRS { USBHS_BASE }
26333/** Array initializer of USBHS peripheral base pointers */
26334#define USBHS_BASE_PTRS { USBHS }
26335/** Interrupt vectors for the USBHS peripheral type */
26336#define USBHS_IRQS { USBHS_IRQn }
26337
26338/*!
26339 * @}
26340 */ /* end of group USBHS_Peripheral_Access_Layer */
26341
26342
26343/* ----------------------------------------------------------------------------
26344 -- USBHSDCD Peripheral Access Layer
26345 ---------------------------------------------------------------------------- */
26346
26347/*!
26348 * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
26349 * @{
26350 */
26351
26352/** USBHSDCD - Register Layout Typedef */
26353typedef struct {
26354 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
26355 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
26356 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
26357 __IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */
26358 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
26359 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
26360 union { /* offset: 0x18 */
26361 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
26362 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
26363 };
26364} USBHSDCD_Type;
26365
26366/* ----------------------------------------------------------------------------
26367 -- USBHSDCD Register Masks
26368 ---------------------------------------------------------------------------- */
26369
26370/*!
26371 * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
26372 * @{
26373 */
26374
26375/*! @name CONTROL - Control register */
26376/*! @{ */
26377#define USBHSDCD_CONTROL_IACK_MASK (0x1U)
26378#define USBHSDCD_CONTROL_IACK_SHIFT (0U)
26379/*! IACK - Interrupt Acknowledge
26380 * 0b0..Do not clear the interrupt.
26381 * 0b1..Clear the IF bit (interrupt flag).
26382 */
26383#define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
26384#define USBHSDCD_CONTROL_IF_MASK (0x100U)
26385#define USBHSDCD_CONTROL_IF_SHIFT (8U)
26386/*! IF - Interrupt Flag
26387 * 0b0..No interrupt is pending.
26388 * 0b1..An interrupt is pending.
26389 */
26390#define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
26391#define USBHSDCD_CONTROL_IE_MASK (0x10000U)
26392#define USBHSDCD_CONTROL_IE_SHIFT (16U)
26393/*! IE - Interrupt Enable
26394 * 0b0..Disable interrupts to the system.
26395 * 0b1..Enable interrupts to the system.
26396 */
26397#define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
26398#define USBHSDCD_CONTROL_BC12_MASK (0x20000U)
26399#define USBHSDCD_CONTROL_BC12_SHIFT (17U)
26400/*! BC12
26401 * 0b0..Compatible with BC1.1 (default)
26402 * 0b1..Compatible with BC1.2
26403 */
26404#define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
26405#define USBHSDCD_CONTROL_START_MASK (0x1000000U)
26406#define USBHSDCD_CONTROL_START_SHIFT (24U)
26407/*! START - Start Change Detection Sequence
26408 * 0b0..Do not start the sequence. Writes of this value have no effect.
26409 * 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
26410 */
26411#define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
26412#define USBHSDCD_CONTROL_SR_MASK (0x2000000U)
26413#define USBHSDCD_CONTROL_SR_SHIFT (25U)
26414/*! SR - Software Reset
26415 * 0b0..Do not perform a software reset.
26416 * 0b1..Perform a software reset.
26417 */
26418#define USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
26419/*! @} */
26420
26421/*! @name CLOCK - Clock register */
26422/*! @{ */
26423#define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
26424#define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
26425/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
26426 * 0b0..kHz Speed (between 1 kHz and 1023 kHz)
26427 * 0b1..MHz Speed (between 1 MHz and 1023 MHz)
26428 */
26429#define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
26430#define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
26431#define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
26432#define USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
26433/*! @} */
26434
26435/*! @name STATUS - Status register */
26436/*! @{ */
26437#define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U)
26438#define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U)
26439/*! SEQ_RES - Charger Detection Sequence Results
26440 * 0b00..No results to report.
26441 * 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
26442 * 0b10..Attached to a charging port. The exact meaning depends on bit 18: 0: Attached to either a CDP or a DCP. The charger type detection has not completed. 1: Attached to a CDP. The charger type detection has completed.
26443 * 0b11..Attached to a DCP.
26444 */
26445#define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
26446#define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
26447#define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U)
26448/*! SEQ_STAT - Charger Detection Sequence Status
26449 * 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
26450 * 0b01..Data pin contact detection is complete.
26451 * 0b10..Charging port detection is complete.
26452 * 0b11..Charger type detection is complete.
26453 */
26454#define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
26455#define USBHSDCD_STATUS_ERR_MASK (0x100000U)
26456#define USBHSDCD_STATUS_ERR_SHIFT (20U)
26457/*! ERR - Error Flag
26458 * 0b0..No sequence errors.
26459 * 0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
26460 */
26461#define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
26462#define USBHSDCD_STATUS_TO_MASK (0x200000U)
26463#define USBHSDCD_STATUS_TO_SHIFT (21U)
26464/*! TO - Timeout Flag
26465 * 0b0..The detection sequence has not been running for over 1 s.
26466 * 0b1..It has been over 1 s since the data pin contact was detected and debounced.
26467 */
26468#define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
26469#define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U)
26470#define USBHSDCD_STATUS_ACTIVE_SHIFT (22U)
26471/*! ACTIVE - Active Status Indicator
26472 * 0b0..The sequence is not running.
26473 * 0b1..The sequence is running.
26474 */
26475#define USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
26476/*! @} */
26477
26478/*! @name SIGNAL_OVERRIDE - Signal Override Register */
26479/*! @{ */
26480#define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
26481#define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
26482/*! PS - Phase Selection
26483 * 0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent unexpected conditions on USB_DP and USB_DM pins. (Default)
26484 * 0b01..Reserved, not for customer use.
26485 * 0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
26486 * 0b11..Reserved, not for customer use.
26487 */
26488#define USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
26489/*! @} */
26490
26491/*! @name TIMER0 - TIMER0 register */
26492/*! @{ */
26493#define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU)
26494#define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U)
26495#define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
26496#define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
26497#define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
26498#define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
26499/*! @} */
26500
26501/*! @name TIMER1 - TIMER1 register */
26502/*! @{ */
26503#define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
26504#define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
26505#define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
26506#define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
26507#define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
26508#define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
26509/*! @} */
26510
26511/*! @name TIMER2_BC11 - TIMER2_BC11 register */
26512/*! @{ */
26513#define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
26514#define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
26515#define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
26516#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
26517#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
26518#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
26519/*! @} */
26520
26521/*! @name TIMER2_BC12 - TIMER2_BC12 register */
26522/*! @{ */
26523#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
26524#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
26525#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
26526#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
26527#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
26528#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
26529/*! @} */
26530
26531
26532/*!
26533 * @}
26534 */ /* end of group USBHSDCD_Register_Masks */
26535
26536
26537/* USBHSDCD - Peripheral instance base addresses */
26538/** Peripheral USBHSDCD base address */
26539#define USBHSDCD_BASE (0x400A3000u)
26540/** Peripheral USBHSDCD base pointer */
26541#define USBHSDCD ((USBHSDCD_Type *)USBHSDCD_BASE)
26542/** Array initializer of USBHSDCD peripheral base addresses */
26543#define USBHSDCD_BASE_ADDRS { USBHSDCD_BASE }
26544/** Array initializer of USBHSDCD peripheral base pointers */
26545#define USBHSDCD_BASE_PTRS { USBHSDCD }
26546/** Interrupt vectors for the USBHSDCD peripheral type */
26547#define USBHSDCD_IRQS { USBHSDCD_IRQn }
26548
26549/*!
26550 * @}
26551 */ /* end of group USBHSDCD_Peripheral_Access_Layer */
26552
26553
26554/* ----------------------------------------------------------------------------
26555 -- USBPHY Peripheral Access Layer
26556 ---------------------------------------------------------------------------- */
26557
26558/*!
26559 * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
26560 * @{
26561 */
26562
26563/** USBPHY - Register Layout Typedef */
26564typedef struct {
26565 __IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */
26566 __IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */
26567 __IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */
26568 __IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */
26569 __IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */
26570 __IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */
26571 __IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */
26572 __IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */
26573 __IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */
26574 __IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */
26575 __IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */
26576 __IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */
26577 __IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */
26578 __IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */
26579 __IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */
26580 __IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */
26581 __IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */
26582 uint8_t RESERVED_0[12];
26583 __IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */
26584 __IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */
26585 __IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */
26586 __IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */
26587 __I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */
26588 uint8_t RESERVED_1[12];
26589 __IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */
26590 __IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */
26591 __IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */
26592 __IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */
26593 __I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */
26594 uint8_t RESERVED_2[28];
26595 __IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
26596 __IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
26597 __IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
26598 __IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */
26599 uint8_t RESERVED_3[16];
26600 __IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
26601 __IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
26602 __IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
26603 __IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
26604 __I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */
26605 uint8_t RESERVED_4[28];
26606 __I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */
26607 uint8_t RESERVED_5[12];
26608 __IO uint32_t ANACTRL; /**< USB PHY Analog Control Register, offset: 0x100 */
26609 __IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */
26610 __IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */
26611 __IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */
26612 __IO uint32_t USB1_LOOPBACK; /**< USB PHY Loopback Control/Status Register, offset: 0x110 */
26613 __IO uint32_t USB1_LOOPBACK_SET; /**< USB PHY Loopback Control/Status Register, offset: 0x114 */
26614 __IO uint32_t USB1_LOOPBACK_CLR; /**< USB PHY Loopback Control/Status Register, offset: 0x118 */
26615 __IO uint32_t USB1_LOOPBACK_TOG; /**< USB PHY Loopback Control/Status Register, offset: 0x11C */
26616 __IO uint32_t USB1_LOOPBACK_HSFSCNT; /**< USB PHY Loopback Packet Number Select Register, offset: 0x120 */
26617 __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET; /**< USB PHY Loopback Packet Number Select Register, offset: 0x124 */
26618 __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR; /**< USB PHY Loopback Packet Number Select Register, offset: 0x128 */
26619 __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG; /**< USB PHY Loopback Packet Number Select Register, offset: 0x12C */
26620 __IO uint32_t TRIM_OVERRIDE_EN; /**< USB PHY Trim Override Enable Register, offset: 0x130 */
26621 __IO uint32_t TRIM_OVERRIDE_EN_SET; /**< USB PHY Trim Override Enable Register, offset: 0x134 */
26622 __IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< USB PHY Trim Override Enable Register, offset: 0x138 */
26623 __IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< USB PHY Trim Override Enable Register, offset: 0x13C */
26624} USBPHY_Type;
26625
26626/* ----------------------------------------------------------------------------
26627 -- USBPHY Register Masks
26628 ---------------------------------------------------------------------------- */
26629
26630/*!
26631 * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
26632 * @{
26633 */
26634
26635/*! @name PWD - USB PHY Power-Down Register */
26636/*! @{ */
26637#define USBPHY_PWD_TXPWDFS_MASK (0x400U)
26638#define USBPHY_PWD_TXPWDFS_SHIFT (10U)
26639/*! TXPWDFS
26640 * 0b0..Normal operation.
26641 * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
26642 */
26643#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
26644#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
26645#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
26646/*! TXPWDIBIAS
26647 * 0b0..Normal operation
26648 * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path
26649 */
26650#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
26651#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
26652#define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
26653/*! TXPWDV2I
26654 * 0b0..Normal operation.
26655 * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
26656 */
26657#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
26658#define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
26659#define USBPHY_PWD_RXPWDENV_SHIFT (17U)
26660/*! RXPWDENV
26661 * 0b0..Normal operation.
26662 * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
26663 */
26664#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
26665#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
26666#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
26667/*! RXPWD1PT1
26668 * 0b0..Normal operation
26669 * 0b1..Power-down the USB full-speed differential receiver.
26670 */
26671#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
26672#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
26673#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
26674/*! RXPWDDIFF
26675 * 0b0..Normal operation.
26676 * 0b1..Power-down the USB high-speed differential receiver
26677 */
26678#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
26679#define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
26680#define USBPHY_PWD_RXPWDRX_SHIFT (20U)
26681/*! RXPWDRX
26682 * 0b0..Normal operation
26683 * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
26684 */
26685#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
26686/*! @} */
26687
26688/*! @name PWD_SET - USB PHY Power-Down Register */
26689/*! @{ */
26690#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
26691#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
26692/*! TXPWDFS
26693 * 0b0..Normal operation.
26694 * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
26695 */
26696#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
26697#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
26698#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
26699/*! TXPWDIBIAS
26700 * 0b0..Normal operation
26701 * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path
26702 */
26703#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
26704#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
26705#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
26706/*! TXPWDV2I
26707 * 0b0..Normal operation.
26708 * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
26709 */
26710#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
26711#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
26712#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
26713/*! RXPWDENV
26714 * 0b0..Normal operation.
26715 * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
26716 */
26717#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
26718#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
26719#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
26720/*! RXPWD1PT1
26721 * 0b0..Normal operation
26722 * 0b1..Power-down the USB full-speed differential receiver.
26723 */
26724#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
26725#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
26726#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
26727/*! RXPWDDIFF
26728 * 0b0..Normal operation.
26729 * 0b1..Power-down the USB high-speed differential receiver
26730 */
26731#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
26732#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
26733#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
26734/*! RXPWDRX
26735 * 0b0..Normal operation
26736 * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
26737 */
26738#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
26739/*! @} */
26740
26741/*! @name PWD_CLR - USB PHY Power-Down Register */
26742/*! @{ */
26743#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
26744#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
26745/*! TXPWDFS
26746 * 0b0..Normal operation.
26747 * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
26748 */
26749#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
26750#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
26751#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
26752/*! TXPWDIBIAS
26753 * 0b0..Normal operation
26754 * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path
26755 */
26756#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
26757#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
26758#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
26759/*! TXPWDV2I
26760 * 0b0..Normal operation.
26761 * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
26762 */
26763#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
26764#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
26765#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
26766/*! RXPWDENV
26767 * 0b0..Normal operation.
26768 * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
26769 */
26770#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
26771#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
26772#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
26773/*! RXPWD1PT1
26774 * 0b0..Normal operation
26775 * 0b1..Power-down the USB full-speed differential receiver.
26776 */
26777#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
26778#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
26779#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
26780/*! RXPWDDIFF
26781 * 0b0..Normal operation.
26782 * 0b1..Power-down the USB high-speed differential receiver
26783 */
26784#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
26785#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
26786#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
26787/*! RXPWDRX
26788 * 0b0..Normal operation
26789 * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
26790 */
26791#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
26792/*! @} */
26793
26794/*! @name PWD_TOG - USB PHY Power-Down Register */
26795/*! @{ */
26796#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
26797#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
26798/*! TXPWDFS
26799 * 0b0..Normal operation.
26800 * 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
26801 */
26802#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
26803#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
26804#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
26805/*! TXPWDIBIAS
26806 * 0b0..Normal operation
26807 * 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB is in suspend mode. This effectively powers down the entire USB transmit path
26808 */
26809#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
26810#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
26811#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
26812/*! TXPWDV2I
26813 * 0b0..Normal operation.
26814 * 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
26815 */
26816#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
26817#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
26818#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
26819/*! RXPWDENV
26820 * 0b0..Normal operation.
26821 * 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
26822 */
26823#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
26824#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
26825#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
26826/*! RXPWD1PT1
26827 * 0b0..Normal operation
26828 * 0b1..Power-down the USB full-speed differential receiver.
26829 */
26830#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
26831#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
26832#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
26833/*! RXPWDDIFF
26834 * 0b0..Normal operation.
26835 * 0b1..Power-down the USB high-speed differential receiver
26836 */
26837#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
26838#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
26839#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
26840/*! RXPWDRX
26841 * 0b0..Normal operation
26842 * 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
26843 */
26844#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
26845/*! @} */
26846
26847/*! @name TX - USB PHY Transmitter Control Register */
26848/*! @{ */
26849#define USBPHY_TX_D_CAL_MASK (0xFU)
26850#define USBPHY_TX_D_CAL_SHIFT (0U)
26851/*! D_CAL
26852 * 0b0000..Maximum current, approximately 19% above nominal.
26853 * 0b0111..Nominal
26854 * 0b1111..Minimum current, approximately 19% below nominal.
26855 */
26856#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
26857#define USBPHY_TX_TXCAL45DM_MASK (0xF00U)
26858#define USBPHY_TX_TXCAL45DM_SHIFT (8U)
26859#define USBPHY_TX_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)
26860#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
26861#define USBPHY_TX_TXCAL45DP_SHIFT (16U)
26862#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
26863#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
26864#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT (26U)
26865#define USBPHY_TX_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
26866/*! @} */
26867
26868/*! @name TX_SET - USB PHY Transmitter Control Register */
26869/*! @{ */
26870#define USBPHY_TX_SET_D_CAL_MASK (0xFU)
26871#define USBPHY_TX_SET_D_CAL_SHIFT (0U)
26872/*! D_CAL
26873 * 0b0000..Maximum current, approximately 19% above nominal.
26874 * 0b0111..Nominal
26875 * 0b1111..Minimum current, approximately 19% below nominal.
26876 */
26877#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
26878#define USBPHY_TX_SET_TXCAL45DM_MASK (0xF00U)
26879#define USBPHY_TX_SET_TXCAL45DM_SHIFT (8U)
26880#define USBPHY_TX_SET_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK)
26881#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
26882#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
26883#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
26884#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
26885#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT (26U)
26886#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
26887/*! @} */
26888
26889/*! @name TX_CLR - USB PHY Transmitter Control Register */
26890/*! @{ */
26891#define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
26892#define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
26893/*! D_CAL
26894 * 0b0000..Maximum current, approximately 19% above nominal.
26895 * 0b0111..Nominal
26896 * 0b1111..Minimum current, approximately 19% below nominal.
26897 */
26898#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
26899#define USBPHY_TX_CLR_TXCAL45DM_MASK (0xF00U)
26900#define USBPHY_TX_CLR_TXCAL45DM_SHIFT (8U)
26901#define USBPHY_TX_CLR_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK)
26902#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
26903#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
26904#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
26905#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
26906#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT (26U)
26907#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
26908/*! @} */
26909
26910/*! @name TX_TOG - USB PHY Transmitter Control Register */
26911/*! @{ */
26912#define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
26913#define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
26914/*! D_CAL
26915 * 0b0000..Maximum current, approximately 19% above nominal.
26916 * 0b0111..Nominal
26917 * 0b1111..Minimum current, approximately 19% below nominal.
26918 */
26919#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
26920#define USBPHY_TX_TOG_TXCAL45DM_MASK (0xF00U)
26921#define USBPHY_TX_TOG_TXCAL45DM_SHIFT (8U)
26922#define USBPHY_TX_TOG_TXCAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK)
26923#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
26924#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
26925#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
26926#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK (0x1C000000U)
26927#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT (26U)
26928#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
26929/*! @} */
26930
26931/*! @name RX - USB PHY Receiver Control Register */
26932/*! @{ */
26933#define USBPHY_RX_ENVADJ_MASK (0x7U)
26934#define USBPHY_RX_ENVADJ_SHIFT (0U)
26935/*! ENVADJ
26936 * 0b000..Trip-Level Voltage is 0.1000 V
26937 * 0b001..Trip-Level Voltage is 0.1125 V
26938 * 0b010..Trip-Level Voltage is 0.1250 V
26939 * 0b011..Trip-Level Voltage is 0.0875 V
26940 * 0b1xx..Reserved
26941 */
26942#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
26943#define USBPHY_RX_DISCONADJ_MASK (0x70U)
26944#define USBPHY_RX_DISCONADJ_SHIFT (4U)
26945/*! DISCONADJ
26946 * 0b000..Trip-Level Voltage is 0.56875 V
26947 * 0b001..Trip-Level Voltage is 0.55000 V
26948 * 0b010..Trip-Level Voltage is 0.58125 V
26949 * 0b011..Trip-Level Voltage is 0.60000 V
26950 * 0b1xx..Reserved
26951 */
26952#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
26953#define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
26954#define USBPHY_RX_RXDBYPASS_SHIFT (22U)
26955/*! RXDBYPASS
26956 * 0b0..Normal operation.
26957 * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
26958 */
26959#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
26960/*! @} */
26961
26962/*! @name RX_SET - USB PHY Receiver Control Register */
26963/*! @{ */
26964#define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
26965#define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
26966/*! ENVADJ
26967 * 0b000..Trip-Level Voltage is 0.1000 V
26968 * 0b001..Trip-Level Voltage is 0.1125 V
26969 * 0b010..Trip-Level Voltage is 0.1250 V
26970 * 0b011..Trip-Level Voltage is 0.0875 V
26971 * 0b1xx..Reserved
26972 */
26973#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
26974#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
26975#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
26976/*! DISCONADJ
26977 * 0b000..Trip-Level Voltage is 0.56875 V
26978 * 0b001..Trip-Level Voltage is 0.55000 V
26979 * 0b010..Trip-Level Voltage is 0.58125 V
26980 * 0b011..Trip-Level Voltage is 0.60000 V
26981 * 0b1xx..Reserved
26982 */
26983#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
26984#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
26985#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
26986/*! RXDBYPASS
26987 * 0b0..Normal operation.
26988 * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
26989 */
26990#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
26991/*! @} */
26992
26993/*! @name RX_CLR - USB PHY Receiver Control Register */
26994/*! @{ */
26995#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
26996#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
26997/*! ENVADJ
26998 * 0b000..Trip-Level Voltage is 0.1000 V
26999 * 0b001..Trip-Level Voltage is 0.1125 V
27000 * 0b010..Trip-Level Voltage is 0.1250 V
27001 * 0b011..Trip-Level Voltage is 0.0875 V
27002 * 0b1xx..Reserved
27003 */
27004#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
27005#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
27006#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
27007/*! DISCONADJ
27008 * 0b000..Trip-Level Voltage is 0.56875 V
27009 * 0b001..Trip-Level Voltage is 0.55000 V
27010 * 0b010..Trip-Level Voltage is 0.58125 V
27011 * 0b011..Trip-Level Voltage is 0.60000 V
27012 * 0b1xx..Reserved
27013 */
27014#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
27015#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
27016#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
27017/*! RXDBYPASS
27018 * 0b0..Normal operation.
27019 * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
27020 */
27021#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
27022/*! @} */
27023
27024/*! @name RX_TOG - USB PHY Receiver Control Register */
27025/*! @{ */
27026#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
27027#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
27028/*! ENVADJ
27029 * 0b000..Trip-Level Voltage is 0.1000 V
27030 * 0b001..Trip-Level Voltage is 0.1125 V
27031 * 0b010..Trip-Level Voltage is 0.1250 V
27032 * 0b011..Trip-Level Voltage is 0.0875 V
27033 * 0b1xx..Reserved
27034 */
27035#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
27036#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
27037#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
27038/*! DISCONADJ
27039 * 0b000..Trip-Level Voltage is 0.56875 V
27040 * 0b001..Trip-Level Voltage is 0.55000 V
27041 * 0b010..Trip-Level Voltage is 0.58125 V
27042 * 0b011..Trip-Level Voltage is 0.60000 V
27043 * 0b1xx..Reserved
27044 */
27045#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
27046#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
27047#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
27048/*! RXDBYPASS
27049 * 0b0..Normal operation.
27050 * 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
27051 */
27052#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
27053/*! @} */
27054
27055/*! @name CTRL - USB PHY General Control Register */
27056/*! @{ */
27057#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
27058#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
27059#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
27060#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
27061#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
27062#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
27063#define USBPHY_CTRL_ENDEVPLUGINDET_MASK (0x10U)
27064#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT (4U)
27065/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection
27066 * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
27067 * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
27068 */
27069#define USBPHY_CTRL_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)
27070#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
27071#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
27072#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
27073#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
27074#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
27075#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
27076#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
27077#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
27078#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
27079#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U)
27080#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U)
27081#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
27082#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
27083#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
27084#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
27085#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
27086#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
27087#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
27088#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
27089#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
27090#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
27091#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
27092#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
27093#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
27094#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
27095#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
27096#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
27097#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
27098#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
27099#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
27100#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
27101#define USBPHY_CTRL_CLKGATE_SHIFT (30U)
27102#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
27103#define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
27104#define USBPHY_CTRL_SFTRST_SHIFT (31U)
27105#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
27106/*! @} */
27107
27108/*! @name CTRL_SET - USB PHY General Control Register */
27109/*! @{ */
27110#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
27111#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
27112#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
27113#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
27114#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
27115#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
27116#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK (0x10U)
27117#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT (4U)
27118/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection
27119 * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
27120 * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
27121 */
27122#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)
27123#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
27124#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
27125#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
27126#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
27127#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
27128#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
27129#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
27130#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
27131#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
27132#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U)
27133#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U)
27134#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
27135#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
27136#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
27137#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
27138#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
27139#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
27140#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
27141#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
27142#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
27143#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
27144#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
27145#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
27146#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
27147#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
27148#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
27149#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
27150#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
27151#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
27152#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
27153#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
27154#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
27155#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
27156#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
27157#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
27158#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
27159/*! @} */
27160
27161/*! @name CTRL_CLR - USB PHY General Control Register */
27162/*! @{ */
27163#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
27164#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
27165#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
27166#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
27167#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
27168#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
27169#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK (0x10U)
27170#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT (4U)
27171/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection
27172 * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
27173 * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
27174 */
27175#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)
27176#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
27177#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
27178#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
27179#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
27180#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
27181#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
27182#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
27183#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
27184#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
27185#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U)
27186#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U)
27187#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
27188#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
27189#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
27190#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
27191#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
27192#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
27193#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
27194#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
27195#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
27196#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
27197#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
27198#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
27199#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
27200#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
27201#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
27202#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
27203#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
27204#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
27205#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
27206#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
27207#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
27208#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
27209#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
27210#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
27211#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
27212/*! @} */
27213
27214/*! @name CTRL_TOG - USB PHY General Control Register */
27215/*! @{ */
27216#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
27217#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
27218#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
27219#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
27220#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
27221#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
27222#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK (0x10U)
27223#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT (4U)
27224/*! ENDEVPLUGINDET - Enables non-standard resistive plugged-in detection
27225 * 0b0..Disables 200kohm pullup resistors on USB_DP and USB_DM pins (Default)
27226 * 0b1..Enables 200kohm pullup resistors on USB_DP and USB_DM pins
27227 */
27228#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)
27229#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
27230#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
27231#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
27232#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
27233#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
27234#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
27235#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
27236#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
27237#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
27238#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U)
27239#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U)
27240#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
27241#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
27242#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
27243#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
27244#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
27245#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
27246#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
27247#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
27248#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
27249#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
27250#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
27251#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
27252#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
27253#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
27254#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
27255#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
27256#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
27257#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
27258#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
27259#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
27260#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
27261#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
27262#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
27263#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
27264#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
27265/*! @} */
27266
27267/*! @name STATUS - USB PHY Status Register */
27268/*! @{ */
27269#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
27270#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
27271/*! HOSTDISCONDETECT_STATUS
27272 * 0b0..USB cable disconnect has not been detected at the local host
27273 * 0b1..USB cable disconnect has been detected at the local host
27274 */
27275#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
27276#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
27277#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
27278/*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection
27279 * 0b0..No attachment to a USB host is detected
27280 * 0b1..Cable attachment to a USB host is detected
27281 */
27282#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
27283#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
27284#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
27285#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
27286#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
27287#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
27288#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
27289/*! @} */
27290
27291/*! @name DEBUG - USB PHY Debug Register */
27292/*! @{ */
27293#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
27294#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
27295#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
27296#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
27297#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
27298#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
27299#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
27300#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
27301#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
27302#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
27303#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
27304#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
27305#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
27306#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
27307#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
27308#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
27309#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
27310#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
27311#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
27312#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
27313#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
27314#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
27315#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
27316#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
27317#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
27318#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
27319#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
27320#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
27321#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
27322#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
27323#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
27324#define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
27325#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
27326/*! @} */
27327
27328/*! @name DEBUG_SET - USB PHY Debug Register */
27329/*! @{ */
27330#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
27331#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
27332#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
27333#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
27334#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
27335#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
27336#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
27337#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
27338#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
27339#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
27340#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
27341#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
27342#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
27343#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
27344#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
27345#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
27346#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
27347#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
27348#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
27349#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
27350#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
27351#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
27352#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
27353#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
27354#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
27355#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
27356#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
27357#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
27358#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
27359#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
27360#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
27361#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
27362#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
27363/*! @} */
27364
27365/*! @name DEBUG_CLR - USB PHY Debug Register */
27366/*! @{ */
27367#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
27368#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
27369#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
27370#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
27371#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
27372#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
27373#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
27374#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
27375#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
27376#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
27377#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
27378#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
27379#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
27380#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
27381#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
27382#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
27383#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
27384#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
27385#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
27386#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
27387#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
27388#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
27389#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
27390#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
27391#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
27392#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
27393#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
27394#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
27395#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
27396#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
27397#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
27398#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
27399#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
27400/*! @} */
27401
27402/*! @name DEBUG_TOG - USB PHY Debug Register */
27403/*! @{ */
27404#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
27405#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
27406#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
27407#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
27408#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
27409#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
27410#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
27411#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
27412#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
27413#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
27414#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
27415#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
27416#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
27417#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
27418#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
27419#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
27420#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
27421#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
27422#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
27423#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
27424#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
27425#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
27426#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
27427#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
27428#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
27429#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
27430#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
27431#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
27432#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
27433#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
27434#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
27435#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
27436#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
27437/*! @} */
27438
27439/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
27440/*! @{ */
27441#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
27442#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
27443#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
27444#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
27445#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
27446#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
27447#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
27448#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
27449#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
27450/*! @} */
27451
27452/*! @name DEBUG1 - UTMI Debug Status Register 1 */
27453/*! @{ */
27454#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
27455#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
27456/*! ENTAILADJVD
27457 * 0b00..Delay is nominal
27458 * 0b01..Delay is +20%
27459 * 0b10..Delay is -20%
27460 * 0b11..Delay is -40%
27461 */
27462#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
27463/*! @} */
27464
27465/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
27466/*! @{ */
27467#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
27468#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
27469/*! ENTAILADJVD
27470 * 0b00..Delay is nominal
27471 * 0b01..Delay is +20%
27472 * 0b10..Delay is -20%
27473 * 0b11..Delay is -40%
27474 */
27475#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
27476/*! @} */
27477
27478/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
27479/*! @{ */
27480#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
27481#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
27482/*! ENTAILADJVD
27483 * 0b00..Delay is nominal
27484 * 0b01..Delay is +20%
27485 * 0b10..Delay is -20%
27486 * 0b11..Delay is -40%
27487 */
27488#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
27489/*! @} */
27490
27491/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
27492/*! @{ */
27493#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
27494#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
27495/*! ENTAILADJVD
27496 * 0b00..Delay is nominal
27497 * 0b01..Delay is +20%
27498 * 0b10..Delay is -20%
27499 * 0b11..Delay is -40%
27500 */
27501#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
27502/*! @} */
27503
27504/*! @name VERSION - UTMI RTL Version */
27505/*! @{ */
27506#define USBPHY_VERSION_STEP_MASK (0xFFFFU)
27507#define USBPHY_VERSION_STEP_SHIFT (0U)
27508#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
27509#define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
27510#define USBPHY_VERSION_MINOR_SHIFT (16U)
27511#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
27512#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
27513#define USBPHY_VERSION_MAJOR_SHIFT (24U)
27514#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
27515/*! @} */
27516
27517/*! @name PLL_SIC - USB PHY PLL Control/Status Register */
27518/*! @{ */
27519#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x3U)
27520#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (0U)
27521/*! PLL_DIV_SEL
27522 * 0b00..PLL reference frequency = 24MHz
27523 * 0b01..PLL reference frequency = 16MHz
27524 * 0b1x..PLL reference frequency = 12MHz
27525 */
27526#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
27527#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U)
27528#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U)
27529#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
27530#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK (0x800U)
27531#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT (11U)
27532#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK)
27533#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U)
27534#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U)
27535#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
27536#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U)
27537#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U)
27538#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
27539#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U)
27540#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U)
27541#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
27542#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U)
27543#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U)
27544/*! PLL_LOCK
27545 * 0b0..PLL is not currently locked
27546 * 0b1..PLL is currently locked
27547 */
27548#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
27549/*! @} */
27550
27551/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
27552/*! @{ */
27553#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x3U)
27554#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (0U)
27555/*! PLL_DIV_SEL
27556 * 0b00..PLL reference frequency = 24MHz
27557 * 0b01..PLL reference frequency = 16MHz
27558 * 0b1x..PLL reference frequency = 12MHz
27559 */
27560#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
27561#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U)
27562#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
27563#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
27564#define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK (0x800U)
27565#define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT (11U)
27566#define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK)
27567#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U)
27568#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U)
27569#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
27570#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U)
27571#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U)
27572#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
27573#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U)
27574#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U)
27575#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
27576#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U)
27577#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U)
27578/*! PLL_LOCK
27579 * 0b0..PLL is not currently locked
27580 * 0b1..PLL is currently locked
27581 */
27582#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
27583/*! @} */
27584
27585/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
27586/*! @{ */
27587#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x3U)
27588#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (0U)
27589/*! PLL_DIV_SEL
27590 * 0b00..PLL reference frequency = 24MHz
27591 * 0b01..PLL reference frequency = 16MHz
27592 * 0b1x..PLL reference frequency = 12MHz
27593 */
27594#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
27595#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U)
27596#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
27597#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
27598#define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK (0x800U)
27599#define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT (11U)
27600#define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK)
27601#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U)
27602#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U)
27603#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
27604#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U)
27605#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U)
27606#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
27607#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U)
27608#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U)
27609#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
27610#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U)
27611#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U)
27612/*! PLL_LOCK
27613 * 0b0..PLL is not currently locked
27614 * 0b1..PLL is currently locked
27615 */
27616#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
27617/*! @} */
27618
27619/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
27620/*! @{ */
27621#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x3U)
27622#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (0U)
27623/*! PLL_DIV_SEL
27624 * 0b00..PLL reference frequency = 24MHz
27625 * 0b01..PLL reference frequency = 16MHz
27626 * 0b1x..PLL reference frequency = 12MHz
27627 */
27628#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
27629#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U)
27630#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
27631#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
27632#define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK (0x800U)
27633#define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT (11U)
27634#define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK)
27635#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U)
27636#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U)
27637#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
27638#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U)
27639#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U)
27640#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
27641#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U)
27642#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U)
27643#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
27644#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U)
27645#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U)
27646/*! PLL_LOCK
27647 * 0b0..PLL is not currently locked
27648 * 0b1..PLL is currently locked
27649 */
27650#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
27651/*! @} */
27652
27653/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
27654/*! @{ */
27655#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
27656#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
27657/*! VBUSVALID_THRESH
27658 * 0b000..4.0 V
27659 * 0b001..4.1 V
27660 * 0b010..4.2 V
27661 * 0b011..4.3 V
27662 * 0b100..4.4 V (Default)
27663 * 0b101..4.5 V
27664 * 0b110..4.6 V
27665 * 0b111..4.7 V
27666 */
27667#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
27668#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
27669#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
27670/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
27671 * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
27672 * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
27673 */
27674#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
27675#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
27676#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
27677#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
27678#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
27679#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
27680#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
27681#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
27682#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
27683#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
27684#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
27685#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
27686#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
27687#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
27688#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
27689/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
27690 * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
27691 * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
27692 */
27693#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
27694#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
27695#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
27696/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
27697 * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
27698 * 0b01..Use the Session Valid comparator results for signal reported to the USB controller
27699 * 0b10..Use the Session Valid comparator results for signal reported to the USB controller
27700 * 0b11..Reserved, do not use
27701 */
27702#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
27703#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
27704#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
27705/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
27706 * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
27707 * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
27708 */
27709#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
27710#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x100000U)
27711#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
27712/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
27713 * 0b0..Powers down the VBUS_VALID comparator
27714 * 0b1..Enables the VBUS_VALID comparator (default)
27715 */
27716#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
27717#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
27718#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
27719/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
27720 * 0b0..VBUS discharge resistor is disabled (Default)
27721 * 0b1..VBUS discharge resistor is enabled
27722 */
27723#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
27724#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
27725#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
27726/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
27727 * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP
27728 * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP
27729 */
27730#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
27731/*! @} */
27732
27733/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */
27734/*! @{ */
27735#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
27736#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
27737/*! VBUSVALID_THRESH
27738 * 0b000..4.0 V
27739 * 0b001..4.1 V
27740 * 0b010..4.2 V
27741 * 0b011..4.3 V
27742 * 0b100..4.4 V (Default)
27743 * 0b101..4.5 V
27744 * 0b110..4.6 V
27745 * 0b111..4.7 V
27746 */
27747#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
27748#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
27749#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
27750/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
27751 * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
27752 * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
27753 */
27754#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
27755#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
27756#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
27757#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
27758#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
27759#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
27760#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
27761#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
27762#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
27763#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
27764#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
27765#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
27766#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
27767#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
27768#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
27769/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
27770 * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
27771 * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
27772 */
27773#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
27774#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
27775#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
27776/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
27777 * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
27778 * 0b01..Use the Session Valid comparator results for signal reported to the USB controller
27779 * 0b10..Use the Session Valid comparator results for signal reported to the USB controller
27780 * 0b11..Reserved, do not use
27781 */
27782#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
27783#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
27784#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
27785/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
27786 * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
27787 * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
27788 */
27789#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
27790#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U)
27791#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
27792/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
27793 * 0b0..Powers down the VBUS_VALID comparator
27794 * 0b1..Enables the VBUS_VALID comparator (default)
27795 */
27796#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
27797#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
27798#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
27799/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
27800 * 0b0..VBUS discharge resistor is disabled (Default)
27801 * 0b1..VBUS discharge resistor is enabled
27802 */
27803#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
27804#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
27805#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
27806/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
27807 * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP
27808 * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP
27809 */
27810#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
27811/*! @} */
27812
27813/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */
27814/*! @{ */
27815#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
27816#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
27817/*! VBUSVALID_THRESH
27818 * 0b000..4.0 V
27819 * 0b001..4.1 V
27820 * 0b010..4.2 V
27821 * 0b011..4.3 V
27822 * 0b100..4.4 V (Default)
27823 * 0b101..4.5 V
27824 * 0b110..4.6 V
27825 * 0b111..4.7 V
27826 */
27827#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
27828#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
27829#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
27830/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
27831 * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
27832 * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
27833 */
27834#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
27835#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
27836#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
27837#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
27838#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
27839#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
27840#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
27841#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
27842#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
27843#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
27844#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
27845#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
27846#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
27847#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
27848#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
27849/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
27850 * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
27851 * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
27852 */
27853#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
27854#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
27855#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
27856/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
27857 * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
27858 * 0b01..Use the Session Valid comparator results for signal reported to the USB controller
27859 * 0b10..Use the Session Valid comparator results for signal reported to the USB controller
27860 * 0b11..Reserved, do not use
27861 */
27862#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
27863#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
27864#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
27865/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
27866 * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
27867 * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
27868 */
27869#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
27870#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U)
27871#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
27872/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
27873 * 0b0..Powers down the VBUS_VALID comparator
27874 * 0b1..Enables the VBUS_VALID comparator (default)
27875 */
27876#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
27877#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
27878#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
27879/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
27880 * 0b0..VBUS discharge resistor is disabled (Default)
27881 * 0b1..VBUS discharge resistor is enabled
27882 */
27883#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
27884#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
27885#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
27886/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
27887 * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP
27888 * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP
27889 */
27890#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
27891/*! @} */
27892
27893/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */
27894/*! @{ */
27895#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
27896#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
27897/*! VBUSVALID_THRESH
27898 * 0b000..4.0 V
27899 * 0b001..4.1 V
27900 * 0b010..4.2 V
27901 * 0b011..4.3 V
27902 * 0b100..4.4 V (Default)
27903 * 0b101..4.5 V
27904 * 0b110..4.6 V
27905 * 0b111..4.7 V
27906 */
27907#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
27908#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
27909#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
27910/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
27911 * 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
27912 * 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
27913 */
27914#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
27915#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
27916#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
27917#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
27918#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
27919#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
27920#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
27921#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
27922#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
27923#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
27924#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
27925#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
27926#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
27927#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
27928#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
27929/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
27930 * 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
27931 * 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
27932 */
27933#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
27934#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
27935#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
27936/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
27937 * 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
27938 * 0b01..Use the Session Valid comparator results for signal reported to the USB controller
27939 * 0b10..Use the Session Valid comparator results for signal reported to the USB controller
27940 * 0b11..Reserved, do not use
27941 */
27942#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
27943#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
27944#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
27945/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
27946 * 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
27947 * 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
27948 */
27949#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
27950#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U)
27951#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
27952/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
27953 * 0b0..Powers down the VBUS_VALID comparator
27954 * 0b1..Enables the VBUS_VALID comparator (default)
27955 */
27956#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
27957#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
27958#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
27959/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
27960 * 0b0..VBUS discharge resistor is disabled (Default)
27961 * 0b1..VBUS discharge resistor is enabled
27962 */
27963#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
27964#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
27965#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
27966/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
27967 * 0b0..Disable resistive charger detection resistors on USB_DP and USB_DP
27968 * 0b1..Enable resistive charger detection resistors on USB_DP and USB_DP
27969 */
27970#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
27971/*! @} */
27972
27973/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */
27974/*! @{ */
27975#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U)
27976#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U)
27977/*! SESSEND - Session End indicator
27978 * 0b0..The VBUS voltage is above the Session Valid threshold
27979 * 0b1..The VBUS voltage is below the Session Valid threshold
27980 */
27981#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
27982#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U)
27983#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U)
27984/*! BVALID - B-Device Session Valid status
27985 * 0b0..The VBUS voltage is below the Session Valid threshold
27986 * 0b1..The VBUS voltage is above the Session Valid threshold
27987 */
27988#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
27989#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U)
27990#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U)
27991/*! AVALID - A-Device Session Valid status
27992 * 0b0..The VBUS voltage is below the Session Valid threshold
27993 * 0b1..The VBUS voltage is above the Session Valid threshold
27994 */
27995#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
27996#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
27997#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
27998/*! VBUS_VALID - VBUS voltage status
27999 * 0b0..VBUS is below the comparator threshold
28000 * 0b1..VBUS is above the comparator threshold
28001 */
28002#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
28003#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
28004#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
28005/*! VBUS_VALID_3V - VBUS_VALID_3V detector status
28006 * 0b0..VBUS voltage is below VBUS_VALID_3V threshold
28007 * 0b1..VBUS voltage is above VBUS_VALID_3V threshold
28008 */
28009#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
28010/*! @} */
28011
28012/*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */
28013/*! @{ */
28014#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
28015#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
28016/*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output
28017 * 0b0..No USB cable attachment has been detected
28018 * 0b1..A USB cable attachment between the device and host has been detected
28019 */
28020#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
28021#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
28022#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
28023/*! CHRG_DETECTED - Battery Charging Primary Detection phase output
28024 * 0b0..Standard Downstream Port (SDP) has been detected
28025 * 0b1..Charging Port has been detected
28026 */
28027#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
28028#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK (0x4U)
28029#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U)
28030/*! DM_STATE
28031 * 0b0..USB_DM pin voltage is < 0.8V
28032 * 0b1..USB_DM pin voltage is > 2.0V
28033 */
28034#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK)
28035#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U)
28036#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
28037/*! DP_STATE
28038 * 0b0..USB_DP pin voltage is < 0.8V
28039 * 0b1..USB_DP pin voltage is > 2.0V
28040 */
28041#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
28042#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
28043#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
28044/*! SECDET_DCP - Battery Charging Secondary Detection phase output
28045 * 0b0..Charging Downstream Port (CDP) has been detected
28046 * 0b1..Downstream Charging Port (DCP) has been detected
28047 */
28048#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
28049/*! @} */
28050
28051/*! @name ANACTRL - USB PHY Analog Control Register */
28052/*! @{ */
28053#define USBPHY_ANACTRL_TESTCLK_SEL_MASK (0x1U)
28054#define USBPHY_ANACTRL_TESTCLK_SEL_SHIFT (0U)
28055#define USBPHY_ANACTRL_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TESTCLK_SEL_MASK)
28056#define USBPHY_ANACTRL_PFD_CLKGATE_MASK (0x2U)
28057#define USBPHY_ANACTRL_PFD_CLKGATE_SHIFT (1U)
28058/*! PFD_CLKGATE
28059 * 0b0..PFD clock output is enabled
28060 * 0b1..PFD clock output is gated (Default)
28061 */
28062#define USBPHY_ANACTRL_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_PFD_CLKGATE_MASK)
28063#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK (0xCU)
28064#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT (2U)
28065/*! PFD_CLK_SEL
28066 * 0b00..USB1PFDCLK is the same frequency as the xtal clock (Default)
28067 * 0b01..USB1PFDCLK frequency is pfd_clk divided by 4
28068 * 0b10..USB1PFDCLK frequency is pfd_clk divided by 2
28069 * 0b11..USB1PFDCLK frequency is the same as pfd_clk frequency
28070 */
28071#define USBPHY_ANACTRL_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK)
28072#define USBPHY_ANACTRL_PFD_FRAC_MASK (0x3F0U)
28073#define USBPHY_ANACTRL_PFD_FRAC_SHIFT (4U)
28074#define USBPHY_ANACTRL_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_PFD_FRAC_MASK)
28075#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U)
28076#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U)
28077/*! DEV_PULLDOWN
28078 * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
28079 * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
28080 */
28081#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
28082#define USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK (0x1800U)
28083#define USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT (11U)
28084/*! EMPH_PULSE_CTRL
28085 * 0b00..Minimum duration of pre-emphasis current after each data transition
28086 * 0b11..Maximum duration of pre-emphasis current after each data transition
28087 */
28088#define USBPHY_ANACTRL_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK)
28089#define USBPHY_ANACTRL_EMPH_EN_MASK (0x2000U)
28090#define USBPHY_ANACTRL_EMPH_EN_SHIFT (13U)
28091/*! EMPH_EN
28092 * 0b0..No pre-emphasis is used on HS TX output drivers
28093 * 0b1..Enables pre-emphasis for HS TX output drivers
28094 */
28095#define USBPHY_ANACTRL_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_EMPH_EN_MASK)
28096#define USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK (0xC000U)
28097#define USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT (14U)
28098/*! EMPH_CUR_CTRL
28099 * 0b00..No pre-emphasis current is enabled for the HS TX drivers
28100 * 0b01..One unit of pre-emphasis current is enabled for the HS TX drivers
28101 * 0b10..Two units of pre-emphasis current are enabled for the HS TX drivers
28102 * 0b11..Three units of pre-emphasis current are enabled for the HS TX drivers
28103 */
28104#define USBPHY_ANACTRL_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK)
28105#define USBPHY_ANACTRL_PFD_STABLE_MASK (0x80000000U)
28106#define USBPHY_ANACTRL_PFD_STABLE_SHIFT (31U)
28107#define USBPHY_ANACTRL_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_PFD_STABLE_MASK)
28108/*! @} */
28109
28110/*! @name ANACTRL_SET - USB PHY Analog Control Register */
28111/*! @{ */
28112#define USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK (0x1U)
28113#define USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT (0U)
28114#define USBPHY_ANACTRL_SET_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK)
28115#define USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK (0x2U)
28116#define USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT (1U)
28117/*! PFD_CLKGATE
28118 * 0b0..PFD clock output is enabled
28119 * 0b1..PFD clock output is gated (Default)
28120 */
28121#define USBPHY_ANACTRL_SET_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK)
28122#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK (0xCU)
28123#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT (2U)
28124/*! PFD_CLK_SEL
28125 * 0b00..USB1PFDCLK is the same frequency as the xtal clock (Default)
28126 * 0b01..USB1PFDCLK frequency is pfd_clk divided by 4
28127 * 0b10..USB1PFDCLK frequency is pfd_clk divided by 2
28128 * 0b11..USB1PFDCLK frequency is the same as pfd_clk frequency
28129 */
28130#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK)
28131#define USBPHY_ANACTRL_SET_PFD_FRAC_MASK (0x3F0U)
28132#define USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT (4U)
28133#define USBPHY_ANACTRL_SET_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_SET_PFD_FRAC_MASK)
28134#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U)
28135#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U)
28136/*! DEV_PULLDOWN
28137 * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
28138 * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
28139 */
28140#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
28141#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK (0x1800U)
28142#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT (11U)
28143/*! EMPH_PULSE_CTRL
28144 * 0b00..Minimum duration of pre-emphasis current after each data transition
28145 * 0b11..Maximum duration of pre-emphasis current after each data transition
28146 */
28147#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK)
28148#define USBPHY_ANACTRL_SET_EMPH_EN_MASK (0x2000U)
28149#define USBPHY_ANACTRL_SET_EMPH_EN_SHIFT (13U)
28150/*! EMPH_EN
28151 * 0b0..No pre-emphasis is used on HS TX output drivers
28152 * 0b1..Enables pre-emphasis for HS TX output drivers
28153 */
28154#define USBPHY_ANACTRL_SET_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_EN_MASK)
28155#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK (0xC000U)
28156#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT (14U)
28157/*! EMPH_CUR_CTRL
28158 * 0b00..No pre-emphasis current is enabled for the HS TX drivers
28159 * 0b01..One unit of pre-emphasis current is enabled for the HS TX drivers
28160 * 0b10..Two units of pre-emphasis current are enabled for the HS TX drivers
28161 * 0b11..Three units of pre-emphasis current are enabled for the HS TX drivers
28162 */
28163#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK)
28164#define USBPHY_ANACTRL_SET_PFD_STABLE_MASK (0x80000000U)
28165#define USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT (31U)
28166#define USBPHY_ANACTRL_SET_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_STABLE_MASK)
28167/*! @} */
28168
28169/*! @name ANACTRL_CLR - USB PHY Analog Control Register */
28170/*! @{ */
28171#define USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK (0x1U)
28172#define USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT (0U)
28173#define USBPHY_ANACTRL_CLR_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK)
28174#define USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK (0x2U)
28175#define USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT (1U)
28176/*! PFD_CLKGATE
28177 * 0b0..PFD clock output is enabled
28178 * 0b1..PFD clock output is gated (Default)
28179 */
28180#define USBPHY_ANACTRL_CLR_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK)
28181#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK (0xCU)
28182#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT (2U)
28183/*! PFD_CLK_SEL
28184 * 0b00..USB1PFDCLK is the same frequency as the xtal clock (Default)
28185 * 0b01..USB1PFDCLK frequency is pfd_clk divided by 4
28186 * 0b10..USB1PFDCLK frequency is pfd_clk divided by 2
28187 * 0b11..USB1PFDCLK frequency is the same as pfd_clk frequency
28188 */
28189#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK)
28190#define USBPHY_ANACTRL_CLR_PFD_FRAC_MASK (0x3F0U)
28191#define USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT (4U)
28192#define USBPHY_ANACTRL_CLR_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_FRAC_MASK)
28193#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U)
28194#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U)
28195/*! DEV_PULLDOWN
28196 * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
28197 * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
28198 */
28199#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
28200#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK (0x1800U)
28201#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT (11U)
28202/*! EMPH_PULSE_CTRL
28203 * 0b00..Minimum duration of pre-emphasis current after each data transition
28204 * 0b11..Maximum duration of pre-emphasis current after each data transition
28205 */
28206#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK)
28207#define USBPHY_ANACTRL_CLR_EMPH_EN_MASK (0x2000U)
28208#define USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT (13U)
28209/*! EMPH_EN
28210 * 0b0..No pre-emphasis is used on HS TX output drivers
28211 * 0b1..Enables pre-emphasis for HS TX output drivers
28212 */
28213#define USBPHY_ANACTRL_CLR_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_EN_MASK)
28214#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK (0xC000U)
28215#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT (14U)
28216/*! EMPH_CUR_CTRL
28217 * 0b00..No pre-emphasis current is enabled for the HS TX drivers
28218 * 0b01..One unit of pre-emphasis current is enabled for the HS TX drivers
28219 * 0b10..Two units of pre-emphasis current are enabled for the HS TX drivers
28220 * 0b11..Three units of pre-emphasis current are enabled for the HS TX drivers
28221 */
28222#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK)
28223#define USBPHY_ANACTRL_CLR_PFD_STABLE_MASK (0x80000000U)
28224#define USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT (31U)
28225#define USBPHY_ANACTRL_CLR_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_STABLE_MASK)
28226/*! @} */
28227
28228/*! @name ANACTRL_TOG - USB PHY Analog Control Register */
28229/*! @{ */
28230#define USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK (0x1U)
28231#define USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT (0U)
28232#define USBPHY_ANACTRL_TOG_TESTCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK)
28233#define USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK (0x2U)
28234#define USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT (1U)
28235/*! PFD_CLKGATE
28236 * 0b0..PFD clock output is enabled
28237 * 0b1..PFD clock output is gated (Default)
28238 */
28239#define USBPHY_ANACTRL_TOG_PFD_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK)
28240#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK (0xCU)
28241#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT (2U)
28242/*! PFD_CLK_SEL
28243 * 0b00..USB1PFDCLK is the same frequency as the xtal clock (Default)
28244 * 0b01..USB1PFDCLK frequency is pfd_clk divided by 4
28245 * 0b10..USB1PFDCLK frequency is pfd_clk divided by 2
28246 * 0b11..USB1PFDCLK frequency is the same as pfd_clk frequency
28247 */
28248#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK)
28249#define USBPHY_ANACTRL_TOG_PFD_FRAC_MASK (0x3F0U)
28250#define USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT (4U)
28251#define USBPHY_ANACTRL_TOG_PFD_FRAC(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_FRAC_MASK)
28252#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U)
28253#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U)
28254/*! DEV_PULLDOWN
28255 * 0b0..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare disabled in device mode.
28256 * 0b1..The 15kohm nominal pulldowns on the USB_DP and USB_DM pinsare enabled in device mode.
28257 */
28258#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
28259#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK (0x1800U)
28260#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT (11U)
28261/*! EMPH_PULSE_CTRL
28262 * 0b00..Minimum duration of pre-emphasis current after each data transition
28263 * 0b11..Maximum duration of pre-emphasis current after each data transition
28264 */
28265#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK)
28266#define USBPHY_ANACTRL_TOG_EMPH_EN_MASK (0x2000U)
28267#define USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT (13U)
28268/*! EMPH_EN
28269 * 0b0..No pre-emphasis is used on HS TX output drivers
28270 * 0b1..Enables pre-emphasis for HS TX output drivers
28271 */
28272#define USBPHY_ANACTRL_TOG_EMPH_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_EN_MASK)
28273#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK (0xC000U)
28274#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT (14U)
28275/*! EMPH_CUR_CTRL
28276 * 0b00..No pre-emphasis current is enabled for the HS TX drivers
28277 * 0b01..One unit of pre-emphasis current is enabled for the HS TX drivers
28278 * 0b10..Two units of pre-emphasis current are enabled for the HS TX drivers
28279 * 0b11..Three units of pre-emphasis current are enabled for the HS TX drivers
28280 */
28281#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK)
28282#define USBPHY_ANACTRL_TOG_PFD_STABLE_MASK (0x80000000U)
28283#define USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT (31U)
28284#define USBPHY_ANACTRL_TOG_PFD_STABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_STABLE_MASK)
28285/*! @} */
28286
28287/*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */
28288/*! @{ */
28289#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
28290#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
28291#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
28292#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK (0x2U)
28293#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
28294#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
28295#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK (0x4U)
28296#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
28297#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
28298#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
28299#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
28300#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
28301#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
28302#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
28303#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
28304#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK (0x20U)
28305#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT (5U)
28306#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
28307#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK (0x40U)
28308#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT (6U)
28309#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
28310#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK (0x80U)
28311#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
28312#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
28313#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK (0x100U)
28314#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
28315#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
28316#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
28317#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
28318#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
28319#define USBPHY_USB1_LOOPBACK_TSTPKT_MASK (0xFF0000U)
28320#define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT (16U)
28321#define USBPHY_USB1_LOOPBACK_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
28322/*! @} */
28323
28324/*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */
28325/*! @{ */
28326#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
28327#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
28328#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)
28329#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
28330#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
28331#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)
28332#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
28333#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
28334#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)
28335#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
28336#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
28337#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)
28338#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
28339#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
28340#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)
28341#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
28342#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
28343#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)
28344#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
28345#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
28346#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)
28347#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
28348#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
28349#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)
28350#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
28351#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
28352#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)
28353#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
28354#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
28355#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
28356#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK (0xFF0000U)
28357#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT (16U)
28358#define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
28359/*! @} */
28360
28361/*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */
28362/*! @{ */
28363#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
28364#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
28365#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
28366#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
28367#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
28368#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)
28369#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
28370#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
28371#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)
28372#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
28373#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
28374#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)
28375#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
28376#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
28377#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)
28378#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
28379#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
28380#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)
28381#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
28382#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
28383#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)
28384#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
28385#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
28386#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)
28387#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
28388#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
28389#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)
28390#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
28391#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
28392#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
28393#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK (0xFF0000U)
28394#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT (16U)
28395#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
28396/*! @} */
28397
28398/*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */
28399/*! @{ */
28400#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
28401#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
28402#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
28403#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
28404#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
28405#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)
28406#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
28407#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
28408#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)
28409#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
28410#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
28411#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)
28412#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
28413#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
28414#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)
28415#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
28416#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
28417#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)
28418#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
28419#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
28420#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)
28421#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
28422#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
28423#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)
28424#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
28425#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
28426#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)
28427#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
28428#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
28429#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
28430#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK (0xFF0000U)
28431#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT (16U)
28432#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
28433/*! @} */
28434
28435/*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */
28436/*! @{ */
28437#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
28438#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
28439#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)
28440#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
28441#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
28442#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
28443/*! @} */
28444
28445/*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */
28446/*! @{ */
28447#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
28448#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
28449#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)
28450#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
28451#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
28452#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
28453/*! @} */
28454
28455/*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */
28456/*! @{ */
28457#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
28458#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
28459#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)
28460#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
28461#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
28462#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
28463/*! @} */
28464
28465/*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */
28466/*! @{ */
28467#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
28468#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
28469#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)
28470#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
28471#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
28472#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
28473/*! @} */
28474
28475/*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */
28476/*! @{ */
28477#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
28478#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
28479#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)
28480#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
28481#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
28482#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
28483#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
28484#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
28485#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)
28486#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
28487#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
28488#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)
28489#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
28490#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
28491#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK)
28492#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
28493#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
28494#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)
28495#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
28496#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
28497#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
28498#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
28499#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
28500#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)
28501#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
28502#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
28503#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)
28504#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
28505#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
28506#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK)
28507/*! @} */
28508
28509/*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */
28510/*! @{ */
28511#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
28512#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
28513#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)
28514#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
28515#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
28516#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
28517#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
28518#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
28519#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)
28520#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
28521#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
28522#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)
28523#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
28524#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
28525#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK)
28526#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
28527#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
28528#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)
28529#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
28530#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
28531#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
28532#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
28533#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
28534#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)
28535#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
28536#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
28537#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)
28538#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
28539#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
28540#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK)
28541/*! @} */
28542
28543/*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */
28544/*! @{ */
28545#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
28546#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
28547#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)
28548#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
28549#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
28550#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
28551#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
28552#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
28553#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)
28554#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
28555#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
28556#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)
28557#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
28558#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
28559#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK)
28560#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
28561#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
28562#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)
28563#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
28564#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
28565#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
28566#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
28567#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
28568#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)
28569#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
28570#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
28571#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)
28572#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
28573#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
28574#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK)
28575/*! @} */
28576
28577/*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */
28578/*! @{ */
28579#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
28580#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
28581#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)
28582#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
28583#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
28584#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
28585#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
28586#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
28587#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)
28588#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
28589#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
28590#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)
28591#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
28592#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
28593#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK)
28594#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
28595#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
28596#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)
28597#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
28598#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
28599#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
28600#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
28601#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
28602#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)
28603#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
28604#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
28605#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)
28606#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
28607#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
28608#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK)
28609/*! @} */
28610
28611
28612/*!
28613 * @}
28614 */ /* end of group USBPHY_Register_Masks */
28615
28616
28617/* USBPHY - Peripheral instance base addresses */
28618/** Peripheral USBPHY base address */
28619#define USBPHY_BASE (0x400A2000u)
28620/** Peripheral USBPHY base pointer */
28621#define USBPHY ((USBPHY_Type *)USBPHY_BASE)
28622/** Array initializer of USBPHY peripheral base addresses */
28623#define USBPHY_BASE_ADDRS { USBPHY_BASE }
28624/** Array initializer of USBPHY peripheral base pointers */
28625#define USBPHY_BASE_PTRS { USBPHY }
28626
28627/*!
28628 * @}
28629 */ /* end of group USBPHY_Peripheral_Access_Layer */
28630
28631
28632/* ----------------------------------------------------------------------------
28633 -- VREF Peripheral Access Layer
28634 ---------------------------------------------------------------------------- */
28635
28636/*!
28637 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
28638 * @{
28639 */
28640
28641/** VREF - Register Layout Typedef */
28642typedef struct {
28643 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
28644 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
28645} VREF_Type;
28646
28647/* ----------------------------------------------------------------------------
28648 -- VREF Register Masks
28649 ---------------------------------------------------------------------------- */
28650
28651/*!
28652 * @addtogroup VREF_Register_Masks VREF Register Masks
28653 * @{
28654 */
28655
28656/*! @name TRM - VREF Trim Register */
28657/*! @{ */
28658#define VREF_TRM_TRIM_MASK (0x3FU)
28659#define VREF_TRM_TRIM_SHIFT (0U)
28660/*! TRIM - Trim bits
28661 * 0b000000..Min
28662 * 0b111111..Max
28663 */
28664#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
28665#define VREF_TRM_CHOPEN_MASK (0x40U)
28666#define VREF_TRM_CHOPEN_SHIFT (6U)
28667/*! CHOPEN - Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized.
28668 * 0b0..Chop oscillator is disabled.
28669 * 0b1..Chop oscillator is enabled.
28670 */
28671#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
28672/*! @} */
28673
28674/*! @name SC - VREF Status and Control Register */
28675/*! @{ */
28676#define VREF_SC_MODE_LV_MASK (0x3U)
28677#define VREF_SC_MODE_LV_SHIFT (0U)
28678/*! MODE_LV - Buffer Mode selection
28679 * 0b00..Bandgap on only, for stabilization and startup
28680 * 0b01..High power buffer mode enabled
28681 * 0b10..Low-power buffer mode enabled
28682 * 0b11..Reserved
28683 */
28684#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
28685#define VREF_SC_VREFST_MASK (0x4U)
28686#define VREF_SC_VREFST_SHIFT (2U)
28687/*! VREFST - Internal Voltage Reference stable
28688 * 0b0..The module is disabled or not stable.
28689 * 0b1..The module is stable.
28690 */
28691#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
28692#define VREF_SC_ICOMPEN_MASK (0x20U)
28693#define VREF_SC_ICOMPEN_SHIFT (5U)
28694/*! ICOMPEN - Second order curvature compensation enable
28695 * 0b0..Disabled
28696 * 0b1..Enabled
28697 */
28698#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
28699#define VREF_SC_REGEN_MASK (0x40U)
28700#define VREF_SC_REGEN_SHIFT (6U)
28701/*! REGEN - Regulator enable
28702 * 0b0..Internal 1.75 V regulator is disabled.
28703 * 0b1..Internal 1.75 V regulator is enabled.
28704 */
28705#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
28706#define VREF_SC_VREFEN_MASK (0x80U)
28707#define VREF_SC_VREFEN_SHIFT (7U)
28708/*! VREFEN - Internal Voltage Reference enable
28709 * 0b0..The module is disabled.
28710 * 0b1..The module is enabled.
28711 */
28712#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
28713/*! @} */
28714
28715
28716/*!
28717 * @}
28718 */ /* end of group VREF_Register_Masks */
28719
28720
28721/* VREF - Peripheral instance base addresses */
28722/** Peripheral VREF base address */
28723#define VREF_BASE (0x40074000u)
28724/** Peripheral VREF base pointer */
28725#define VREF ((VREF_Type *)VREF_BASE)
28726/** Array initializer of VREF peripheral base addresses */
28727#define VREF_BASE_ADDRS { VREF_BASE }
28728/** Array initializer of VREF peripheral base pointers */
28729#define VREF_BASE_PTRS { VREF }
28730
28731/*!
28732 * @}
28733 */ /* end of group VREF_Peripheral_Access_Layer */
28734
28735
28736/* ----------------------------------------------------------------------------
28737 -- WDOG Peripheral Access Layer
28738 ---------------------------------------------------------------------------- */
28739
28740/*!
28741 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
28742 * @{
28743 */
28744
28745/** WDOG - Register Layout Typedef */
28746typedef struct {
28747 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
28748 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
28749 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
28750 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
28751 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
28752 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
28753 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
28754 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
28755 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
28756 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
28757 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
28758 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
28759} WDOG_Type;
28760
28761/* ----------------------------------------------------------------------------
28762 -- WDOG Register Masks
28763 ---------------------------------------------------------------------------- */
28764
28765/*!
28766 * @addtogroup WDOG_Register_Masks WDOG Register Masks
28767 * @{
28768 */
28769
28770/*! @name STCTRLH - Watchdog Status and Control Register High */
28771/*! @{ */
28772#define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
28773#define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
28774/*! WDOGEN
28775 * 0b0..WDOG is disabled.
28776 * 0b1..WDOG is enabled.
28777 */
28778#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
28779#define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
28780#define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
28781/*! CLKSRC
28782 * 0b0..WDOG clock sourced from LPO .
28783 * 0b1..WDOG clock sourced from alternate clock source.
28784 */
28785#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
28786#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
28787#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
28788/*! IRQRSTEN
28789 * 0b0..WDOG time-out generates reset only.
28790 * 0b1..WDOG time-out initially generates an interrupt. After WCT, it generates a reset.
28791 */
28792#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
28793#define WDOG_STCTRLH_WINEN_MASK (0x8U)
28794#define WDOG_STCTRLH_WINEN_SHIFT (3U)
28795/*! WINEN
28796 * 0b0..Windowing mode is disabled.
28797 * 0b1..Windowing mode is enabled.
28798 */
28799#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
28800#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
28801#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
28802/*! ALLOWUPDATE
28803 * 0b0..No further updates allowed to WDOG write-once registers.
28804 * 0b1..WDOG write-once registers can be unlocked for updating.
28805 */
28806#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
28807#define WDOG_STCTRLH_DBGEN_MASK (0x20U)
28808#define WDOG_STCTRLH_DBGEN_SHIFT (5U)
28809/*! DBGEN
28810 * 0b0..WDOG is disabled in CPU Debug mode.
28811 * 0b1..WDOG is enabled in CPU Debug mode.
28812 */
28813#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
28814#define WDOG_STCTRLH_STOPEN_MASK (0x40U)
28815#define WDOG_STCTRLH_STOPEN_SHIFT (6U)
28816/*! STOPEN
28817 * 0b0..WDOG is disabled in CPU Stop mode.
28818 * 0b1..WDOG is enabled in CPU Stop mode.
28819 */
28820#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
28821#define WDOG_STCTRLH_WAITEN_MASK (0x80U)
28822#define WDOG_STCTRLH_WAITEN_SHIFT (7U)
28823/*! WAITEN
28824 * 0b0..WDOG is disabled in CPU Wait mode.
28825 * 0b1..WDOG is enabled in CPU Wait mode.
28826 */
28827#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
28828#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
28829#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
28830#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
28831#define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
28832#define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
28833/*! TESTSEL
28834 * 0b0..Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test.
28835 * 0b1..Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing.
28836 */
28837#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
28838#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
28839#define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
28840/*! BYTESEL
28841 * 0b00..Byte 0 selected
28842 * 0b01..Byte 1 selected
28843 * 0b10..Byte 2 selected
28844 * 0b11..Byte 3 selected
28845 */
28846#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
28847#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
28848#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
28849/*! DISTESTWDOG
28850 * 0b0..WDOG functional test mode is not disabled.
28851 * 0b1..WDOG functional test mode is disabled permanently until reset.
28852 */
28853#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
28854/*! @} */
28855
28856/*! @name STCTRLL - Watchdog Status and Control Register Low */
28857/*! @{ */
28858#define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
28859#define WDOG_STCTRLL_INTFLG_SHIFT (15U)
28860#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
28861/*! @} */
28862
28863/*! @name TOVALH - Watchdog Time-out Value Register High */
28864/*! @{ */
28865#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
28866#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
28867#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
28868/*! @} */
28869
28870/*! @name TOVALL - Watchdog Time-out Value Register Low */
28871/*! @{ */
28872#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
28873#define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
28874#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
28875/*! @} */
28876
28877/*! @name WINH - Watchdog Window Register High */
28878/*! @{ */
28879#define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
28880#define WDOG_WINH_WINHIGH_SHIFT (0U)
28881#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
28882/*! @} */
28883
28884/*! @name WINL - Watchdog Window Register Low */
28885/*! @{ */
28886#define WDOG_WINL_WINLOW_MASK (0xFFFFU)
28887#define WDOG_WINL_WINLOW_SHIFT (0U)
28888#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
28889/*! @} */
28890
28891/*! @name REFRESH - Watchdog Refresh register */
28892/*! @{ */
28893#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
28894#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
28895#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
28896/*! @} */
28897
28898/*! @name UNLOCK - Watchdog Unlock register */
28899/*! @{ */
28900#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
28901#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
28902#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
28903/*! @} */
28904
28905/*! @name TMROUTH - Watchdog Timer Output Register High */
28906/*! @{ */
28907#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
28908#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
28909#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
28910/*! @} */
28911
28912/*! @name TMROUTL - Watchdog Timer Output Register Low */
28913/*! @{ */
28914#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
28915#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
28916#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
28917/*! @} */
28918
28919/*! @name RSTCNT - Watchdog Reset Count register */
28920/*! @{ */
28921#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
28922#define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
28923#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
28924/*! @} */
28925
28926/*! @name PRESC - Watchdog Prescaler register */
28927/*! @{ */
28928#define WDOG_PRESC_PRESCVAL_MASK (0x700U)
28929#define WDOG_PRESC_PRESCVAL_SHIFT (8U)
28930#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
28931/*! @} */
28932
28933
28934/*!
28935 * @}
28936 */ /* end of group WDOG_Register_Masks */
28937
28938
28939/* WDOG - Peripheral instance base addresses */
28940/** Peripheral WDOG base address */
28941#define WDOG_BASE (0x40052000u)
28942/** Peripheral WDOG base pointer */
28943#define WDOG ((WDOG_Type *)WDOG_BASE)
28944/** Array initializer of WDOG peripheral base addresses */
28945#define WDOG_BASE_ADDRS { WDOG_BASE }
28946/** Array initializer of WDOG peripheral base pointers */
28947#define WDOG_BASE_PTRS { WDOG }
28948/** Interrupt vectors for the WDOG peripheral type */
28949#define WDOG_IRQS { WDOG_EWM_IRQn }
28950
28951/*!
28952 * @}
28953 */ /* end of group WDOG_Peripheral_Access_Layer */
28954
28955
28956/*
28957** End of section using anonymous unions
28958*/
28959
28960#if defined(__ARMCC_VERSION)
28961 #if (__ARMCC_VERSION >= 6010050)
28962 #pragma clang diagnostic pop
28963 #else
28964 #pragma pop
28965 #endif
28966#elif defined(__CWCC__)
28967 #pragma pop
28968#elif defined(__GNUC__)
28969 /* leave anonymous unions enabled */
28970#elif defined(__IAR_SYSTEMS_ICC__)
28971 #pragma language=default
28972#else
28973 #error Not supported compiler type
28974#endif
28975
28976/*!
28977 * @}
28978 */ /* end of group Peripheral_access_layer */
28979
28980
28981/* ----------------------------------------------------------------------------
28982 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
28983 ---------------------------------------------------------------------------- */
28984
28985/*!
28986 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
28987 * @{
28988 */
28989
28990#if defined(__ARMCC_VERSION)
28991 #if (__ARMCC_VERSION >= 6010050)
28992 #pragma clang system_header
28993 #endif
28994#elif defined(__IAR_SYSTEMS_ICC__)
28995 #pragma system_include
28996#endif
28997
28998/**
28999 * @brief Mask and left-shift a bit field value for use in a register bit range.
29000 * @param field Name of the register bit field.
29001 * @param value Value of the bit field.
29002 * @return Masked and shifted value.
29003 */
29004#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
29005/**
29006 * @brief Mask and right-shift a register value to extract a bit field value.
29007 * @param field Name of the register bit field.
29008 * @param value Value of the register.
29009 * @return Masked and shifted bit field value.
29010 */
29011#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
29012
29013/*!
29014 * @}
29015 */ /* end of group Bit_Field_Generic_Macros */
29016
29017
29018/* ----------------------------------------------------------------------------
29019 -- SDK Compatibility
29020 ---------------------------------------------------------------------------- */
29021
29022/*!
29023 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
29024 * @{
29025 */
29026
29027#define FMC_PFB0CR_RFU_MASK FMC_PFB01CR_RFU_MASK
29028#define FMC_PFB0CR_RFU_SHIFT FMC_PFB01CR_RFU_SHIFT
29029#define FMC_PFB0CR_B0IPE_MASK FMC_PFB01CR_B0IPE_MASK
29030#define FMC_PFB0CR_B0IPE_SHIFT FMC_PFB01CR_B0IPE_SHIFT
29031#define FMC_PFB0CR_B0DPE_MASK FMC_PFB01CR_B0DPE_MASK
29032#define FMC_PFB0CR_B0DPE_SHIFT FMC_PFB01CR_B0DPE_SHIFT
29033#define FMC_PFB0CR_B0ICE_MASK FMC_PFB01CR_B0ICE_MASK
29034#define FMC_PFB0CR_B0ICE_SHIFT FMC_PFB01CR_B0ICE_SHIFT
29035#define FMC_PFB0CR_B0DCE_MASK FMC_PFB01CR_B0DCE_MASK
29036#define FMC_PFB0CR_B0DCE_SHIFT FMC_PFB01CR_B0DCE_SHIFT
29037#define FMC_PFB0CR_CRC_MASK FMC_PFB01CR_CRC_MASK
29038#define FMC_PFB0CR_CRC_SHIFT FMC_PFB01CR_CRC_SHIFT
29039#define FMC_PFB0CR_CRC(x) FMC_PFB01CR_CRC(x)
29040#define FMC_PFB0CR_B0MW_MASK FMC_PFB01CR_B0MW_MASK
29041#define FMC_PFB0CR_B0MW_SHIFT FMC_PFB01CR_B0MW_SHIFT
29042#define FMC_PFB0CR_B0MW(x) FMC_PFB01CR_B0MW(x)
29043#define FMC_PFB0CR_S_B_INV_MASK FMC_PFB01CR_S_B_INV_MASK
29044#define FMC_PFB0CR_S_B_INV_SHIFT FMC_PFB01CR_S_B_INV_SHIFT
29045#define FMC_PFB0CR_CINV_WAY_MASK FMC_PFB01CR_CINV_WAY_MASK
29046#define FMC_PFB0CR_CINV_WAY_SHIFT FMC_PFB01CR_CINV_WAY_SHIFT
29047#define FMC_PFB0CR_CINV_WAY(x) FMC_PFB01CR_CINV_WAY(x)
29048#define FMC_PFB0CR_CLCK_WAY_MASK FMC_PFB01CR_CLCK_WAY_MASK
29049#define FMC_PFB0CR_CLCK_WAY_SHIFT FMC_PFB01CR_CLCK_WAY_SHIFT
29050#define FMC_PFB0CR_CLCK_WAY(x) FMC_PFB01CR_CLCK_WAY(x)
29051#define FMC_PFB0CR_B0RWSC_MASK FMC_PFB01CR_B0RWSC_MASK
29052#define FMC_PFB0CR_B0RWSC_SHIFT FMC_PFB01CR_B0RWSC_SHIFT
29053#define FMC_PFB0CR_B0RWSC(x) FMC_PFB01CR_B0RWSC(x)
29054#define FMC_PFB1CR_RFU_MASK FMC_PFB23CR_RFU_MASK
29055#define FMC_PFB1CR_RFU_SHIFT FMC_PFB23CR_RFU_SHIFT
29056#define FMC_PFB1CR_B1IPE_MASK FMC_PFB23CR_B1IPE_MASK
29057#define FMC_PFB1CR_B1IPE_SHIFT FMC_PFB23CR_B1IPE_SHIFT
29058#define FMC_PFB1CR_B1DPE_MASK FMC_PFB23CR_B1DPE_MASK
29059#define FMC_PFB1CR_B1DPE_SHIFT FMC_PFB23CR_B1DPE_SHIFT
29060#define FMC_PFB1CR_B1ICE_MASK FMC_PFB23CR_B1ICE_MASK
29061#define FMC_PFB1CR_B1ICE_SHIFT FMC_PFB23CR_B1ICE_SHIFT
29062#define FMC_PFB1CR_B1DCE_MASK FMC_PFB23CR_B1DCE_MASK
29063#define FMC_PFB1CR_B1DCE_SHIFT FMC_PFB23CR_B1DCE_SHIFT
29064#define FMC_PFB1CR_B1MW_MASK FMC_PFB23CR_B1MW_MASK
29065#define FMC_PFB1CR_B1MW_SHIFT FMC_PFB23CR_B1MW_SHIFT
29066#define FMC_PFB1CR_B1MW(x) FMC_PFB23CR_B1MW(x)
29067#define FMC_PFB1CR_B1RWSC_MASK FMC_PFB23CR_B1RWSC_MASK
29068#define FMC_PFB1CR_B1RWSC_SHIFT FMC_PFB23CR_B1RWSC_SHIFT
29069#define FMC_PFB1CR_B1RWSC(x) FMC_PFB23CR_B1RWSC(x)
29070#define LLWU_PE8_WUPE130_MASK LLWU_PE8_WUPE30_MASK
29071#define LLWU_PE8_WUPE130_SHIFT LLWU_PE8_WUPE30_SHIFT
29072#define LLWU_PE8_WUPE130(x) LLWU_PE8_WUPE30(x)
29073#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
29074#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
29075#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
29076#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
29077#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
29078#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
29079#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
29080#define PMC_REGSC_BGBDS_MASK This_symbol_has_been_deprecated
29081#define PMC_REGSC_BGBDS_SHIFT This_symbol_has_been_deprecated
29082#define SDHC_VENDOR_EXTDMAEN_MASK This_symbol_has_been_deprecated
29083#define SDHC_VENDOR_EXTDMAEN_SHIFT This_symbol_has_been_deprecated
29084#define SDRAM_CTRL_COC_MASK This_symbol_has_been_deprecated
29085#define SDRAM_CTRL_COC_SHIFT This_symbol_has_been_deprecated
29086#define SDRAM_CTRL_NAM_MASK This_symbol_has_been_deprecated
29087#define SDRAM_CTRL_NAM_SHIFT This_symbol_has_been_deprecated
29088#define SMC_STOPCTRL_LPOPO_MASK This_symbol_has_been_deprecated
29089#define SMC_STOPCTRL_LPOPO_SHIFT This_symbol_has_been_deprecated
29090#define UART_C6_CP_MASK This_symbol_has_been_deprecated
29091#define UART_C6_CP_SHIFT This_symbol_has_been_deprecated
29092#define UART_C6_CE_MASK This_symbol_has_been_deprecated
29093#define UART_C6_CE_SHIFT This_symbol_has_been_deprecated
29094#define UART_C6_TX709_MASK This_symbol_has_been_deprecated
29095#define UART_C6_TX709_SHIFT This_symbol_has_been_deprecated
29096#define UART_C6_EN709_MASK This_symbol_has_been_deprecated
29097#define UART_C6_EN709_SHIFT This_symbol_has_been_deprecated
29098#define UART_PCTH_PCTH_MASK This_symbol_has_been_deprecated
29099#define UART_PCTH_PCTH_SHIFT This_symbol_has_been_deprecated
29100#define UART_PCTH_PCTH(x) This_symbol_has_been_deprecated
29101#define UART_PCTL_PCTL_MASK This_symbol_has_been_deprecated
29102#define UART_PCTL_PCTL_SHIFT This_symbol_has_been_deprecated
29103#define UART_PCTL_PCTL(x) This_symbol_has_been_deprecated
29104#define UART_IE0_CPTXIE_MASK This_symbol_has_been_deprecated
29105#define UART_IE0_CPTXIE_SHIFT This_symbol_has_been_deprecated
29106#define UART_IE0_CTXDIE_MASK This_symbol_has_been_deprecated
29107#define UART_IE0_CTXDIE_SHIFT This_symbol_has_been_deprecated
29108#define UART_IE0_RPLOFIE_MASK This_symbol_has_been_deprecated
29109#define UART_IE0_RPLOFIE_SHIFT This_symbol_has_been_deprecated
29110#define UART_SDTH_SDTH_MASK This_symbol_has_been_deprecated
29111#define UART_SDTH_SDTH_SHIFT This_symbol_has_been_deprecated
29112#define UART_SDTH_SDTH(x) This_symbol_has_been_deprecated
29113#define UART_SDTL_SDTL_MASK This_symbol_has_been_deprecated
29114#define UART_SDTL_SDTL_SHIFT This_symbol_has_been_deprecated
29115#define UART_SDTL_SDTL(x) This_symbol_has_been_deprecated
29116#define UART_PRE_PREAMBLE_MASK This_symbol_has_been_deprecated
29117#define UART_PRE_PREAMBLE_SHIFT This_symbol_has_been_deprecated
29118#define UART_PRE_PREAMBLE(x) This_symbol_has_been_deprecated
29119#define UART_TPL_TPL_MASK This_symbol_has_been_deprecated
29120#define UART_TPL_TPL_SHIFT This_symbol_has_been_deprecated
29121#define UART_TPL_TPL(x) This_symbol_has_been_deprecated
29122#define UART_IE_TXDIE_MASK This_symbol_has_been_deprecated
29123#define UART_IE_TXDIE_SHIFT This_symbol_has_been_deprecated
29124#define UART_IE_PSIE_MASK This_symbol_has_been_deprecated
29125#define UART_IE_PSIE_SHIFT This_symbol_has_been_deprecated
29126#define UART_IE_PCTEIE_MASK This_symbol_has_been_deprecated
29127#define UART_IE_PCTEIE_SHIFT This_symbol_has_been_deprecated
29128#define UART_IE_PTXIE_MASK This_symbol_has_been_deprecated
29129#define UART_IE_PTXIE_SHIFT This_symbol_has_been_deprecated
29130#define UART_IE_PRXIE_MASK This_symbol_has_been_deprecated
29131#define UART_IE_PRXIE_SHIFT This_symbol_has_been_deprecated
29132#define UART_IE_ISDIE_MASK This_symbol_has_been_deprecated
29133#define UART_IE_ISDIE_SHIFT This_symbol_has_been_deprecated
29134#define UART_IE_WBEIE_MASK This_symbol_has_been_deprecated
29135#define UART_IE_WBEIE_SHIFT This_symbol_has_been_deprecated
29136#define UART_IE_PEIE_MASK This_symbol_has_been_deprecated
29137#define UART_IE_PEIE_SHIFT This_symbol_has_been_deprecated
29138#define UART_WB_WBASE_MASK This_symbol_has_been_deprecated
29139#define UART_WB_WBASE_SHIFT This_symbol_has_been_deprecated
29140#define UART_WB_WBASE(x) This_symbol_has_been_deprecated
29141#define UART_S3_TXFF_MASK This_symbol_has_been_deprecated
29142#define UART_S3_TXFF_SHIFT This_symbol_has_been_deprecated
29143#define UART_S3_PSF_MASK This_symbol_has_been_deprecated
29144#define UART_S3_PSF_SHIFT This_symbol_has_been_deprecated
29145#define UART_S3_PCTEF_MASK This_symbol_has_been_deprecated
29146#define UART_S3_PCTEF_SHIFT This_symbol_has_been_deprecated
29147#define UART_S3_PTXF_MASK This_symbol_has_been_deprecated
29148#define UART_S3_PTXF_SHIFT This_symbol_has_been_deprecated
29149#define UART_S3_PRXF_MASK This_symbol_has_been_deprecated
29150#define UART_S3_PRXF_SHIFT This_symbol_has_been_deprecated
29151#define UART_S3_ISD_MASK This_symbol_has_been_deprecated
29152#define UART_S3_ISD_SHIFT This_symbol_has_been_deprecated
29153#define UART_S3_WBEF_MASK This_symbol_has_been_deprecated
29154#define UART_S3_WBEF_SHIFT This_symbol_has_been_deprecated
29155#define UART_S3_PEF_MASK This_symbol_has_been_deprecated
29156#define UART_S3_PEF_SHIFT This_symbol_has_been_deprecated
29157#define UART_S4_FE_MASK This_symbol_has_been_deprecated
29158#define UART_S4_FE_SHIFT This_symbol_has_been_deprecated
29159#define UART_S4_TXDF_MASK This_symbol_has_been_deprecated
29160#define UART_S4_TXDF_SHIFT This_symbol_has_been_deprecated
29161#define UART_S4_CDET_MASK This_symbol_has_been_deprecated
29162#define UART_S4_CDET_SHIFT This_symbol_has_been_deprecated
29163#define UART_S4_CDET(x) This_symbol_has_been_deprecated
29164#define UART_S4_RPLOF_MASK This_symbol_has_been_deprecated
29165#define UART_S4_RPLOF_SHIFT This_symbol_has_been_deprecated
29166#define UART_S4_LNF_MASK This_symbol_has_been_deprecated
29167#define UART_S4_LNF_SHIFT This_symbol_has_been_deprecated
29168#define UART_RPL_RPL_MASK This_symbol_has_been_deprecated
29169#define UART_RPL_RPL_SHIFT This_symbol_has_been_deprecated
29170#define UART_RPL_RPL(x) This_symbol_has_been_deprecated
29171#define UART_RPREL_RPREL_MASK This_symbol_has_been_deprecated
29172#define UART_RPREL_RPREL_SHIFT This_symbol_has_been_deprecated
29173#define UART_RPREL_RPREL(x) This_symbol_has_been_deprecated
29174#define UART_CPW_CPW_MASK This_symbol_has_been_deprecated
29175#define UART_CPW_CPW_SHIFT This_symbol_has_been_deprecated
29176#define UART_CPW_CPW(x) This_symbol_has_been_deprecated
29177#define UART_RIDTH_RIDTH_MASK This_symbol_has_been_deprecated
29178#define UART_RIDTH_RIDTH_SHIFT This_symbol_has_been_deprecated
29179#define UART_RIDTH_RIDTH(x) This_symbol_has_been_deprecated
29180#define UART_RIDTL_RIDTL_MASK This_symbol_has_been_deprecated
29181#define UART_RIDTL_RIDTL_SHIFT This_symbol_has_been_deprecated
29182#define UART_RIDTL_RIDTL(x) This_symbol_has_been_deprecated
29183#define UART_TIDTH_TIDTH_MASK This_symbol_has_been_deprecated
29184#define UART_TIDTH_TIDTH_SHIFT This_symbol_has_been_deprecated
29185#define UART_TIDTH_TIDTH(x) This_symbol_has_been_deprecated
29186#define UART_TIDTL_TIDTL_MASK This_symbol_has_been_deprecated
29187#define UART_TIDTL_TIDTL_SHIFT This_symbol_has_been_deprecated
29188#define UART_TIDTL_TIDTL(x) This_symbol_has_been_deprecated
29189#define UART_RB1TH_RB1TH_MASK This_symbol_has_been_deprecated
29190#define UART_RB1TH_RB1TH_SHIFT This_symbol_has_been_deprecated
29191#define UART_RB1TH_RB1TH(x) This_symbol_has_been_deprecated
29192#define UART_RB1TL_RB1TL_MASK This_symbol_has_been_deprecated
29193#define UART_RB1TL_RB1TL_SHIFT This_symbol_has_been_deprecated
29194#define UART_RB1TL_RB1TL(x) This_symbol_has_been_deprecated
29195#define UART_TB1TH_TB1TH_MASK This_symbol_has_been_deprecated
29196#define UART_TB1TH_TB1TH_SHIFT This_symbol_has_been_deprecated
29197#define UART_TB1TH_TB1TH(x) This_symbol_has_been_deprecated
29198#define UART_TB1TL_TB1TL_MASK This_symbol_has_been_deprecated
29199#define UART_TB1TL_TB1TL_SHIFT This_symbol_has_been_deprecated
29200#define UART_TB1TL_TB1TL(x) This_symbol_has_been_deprecated
29201#define UART_PROG_REG_MIN_DMC1_MASK This_symbol_has_been_deprecated
29202#define UART_PROG_REG_MIN_DMC1_SHIFT This_symbol_has_been_deprecated
29203#define UART_PROG_REG_MIN_DMC1(x) This_symbol_has_been_deprecated
29204#define UART_PROG_REG_LCV_LEN_MASK This_symbol_has_been_deprecated
29205#define UART_PROG_REG_LCV_LEN_SHIFT This_symbol_has_been_deprecated
29206#define UART_PROG_REG_LCV_LEN(x) This_symbol_has_been_deprecated
29207#define UART_STATE_REG_SM_STATE_MASK This_symbol_has_been_deprecated
29208#define UART_STATE_REG_SM_STATE_SHIFT This_symbol_has_been_deprecated
29209#define UART_STATE_REG_SM_STATE(x) This_symbol_has_been_deprecated
29210#define UART_STATE_REG_TX_STATE_MASK This_symbol_has_been_deprecated
29211#define UART_STATE_REG_TX_STATE_SHIFT This_symbol_has_been_deprecated
29212#define UART_STATE_REG_TX_STATE(x) This_symbol_has_been_deprecated
29213#define USB_ADDINFO_IRQNUM_MASK This_symbol_has_been_deprecated
29214#define USB_ADDINFO_IRQNUM_SHIFT This_symbol_has_been_deprecated
29215#define USB_ADDINFO_IRQNUM(x) This_symbol_has_been_deprecated
29216#define USBHS_USBSTS_ULPII_MASK This_symbol_has_been_deprecated
29217#define USBHS_USBSTS_ULPII_SHIFT This_symbol_has_been_deprecated
29218#define USBHS_USBINTR_ULPIE_MASK This_symbol_has_been_deprecated
29219#define USBHS_USBINTR_ULPIE_SHIFT This_symbol_has_been_deprecated
29220#define USBPHY_CTRL_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
29221#define USBPHY_CTRL_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
29222#define USBPHY_CTRL_SET_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
29223#define USBPHY_CTRL_SET_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
29224#define USBPHY_CTRL_CLR_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
29225#define USBPHY_CTRL_CLR_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
29226#define USBPHY_CTRL_TOG_CLK_SWITCH_ENJ_MASK This_symbol_has_been_deprecated
29227#define USBPHY_CTRL_TOG_CLK_SWITCH_ENJ_SHIFT This_symbol_has_been_deprecated
29228#define MCM_ISR_REG(base) MCM_ISCR_REG(base)
29229#define MCM_ISR_IRQ_MASK MCM_ISCR_IRQ_MASK
29230#define MCM_ISR_IRQ_SHIFT MCM_ISCR_IRQ_SHIFT
29231#define MCM_ISR_NMI_MASK MCM_ISCR_NMI_MASK
29232#define MCM_ISR_NMI_SHIFT MCM_ISCR_NMI_SHIFT
29233#define MCM_ISR_DHREQ_MASK MCM_ISCR_DHREQ_MASK
29234#define MCM_ISR_DHREQ_SHIFT MCM_ISCR_DHREQ_SHIFT
29235#define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
29236#define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
29237#define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
29238#define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
29239#define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
29240#define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
29241#define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
29242#define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
29243#define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
29244#define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
29245#define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
29246#define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
29247#define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
29248#define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
29249#define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
29250#define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
29251#define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
29252#define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
29253#define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
29254#define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
29255#define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
29256#define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
29257#define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
29258#define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
29259#define DMAMUX0 DMAMUX
29260#define DSPI0 SPI0
29261#define DSPI1 SPI1
29262#define DSPI2 SPI2
29263#define FLEXCAN0 CAN0
29264#define FLEXCAN1 CAN1
29265#define PTA_BASE GPIOA_BASE
29266#define PTA GPIOA
29267#define PTB_BASE GPIOB_BASE
29268#define PTB GPIOB
29269#define PTC_BASE GPIOC_BASE
29270#define PTC GPIOC
29271#define PTD_BASE GPIOD_BASE
29272#define PTD GPIOD
29273#define PTE_BASE GPIOE_BASE
29274#define PTE GPIOE
29275#define Watchdog_IRQn WDOG_EWM_IRQn
29276#define Watchdog_IRQHandler WDOG_EWM_IRQHandler
29277#define LPTimer_IRQn LPTMR0_IRQn
29278#define LPTimer_IRQHandler LPTMR0_IRQHandler
29279#define UART0_LON_IRQn This_symbol_has_been_deprecated
29280#define UART0_LON_IRQHandler This_symbol_has_been_deprecated
29281#define LLW_IRQn LLWU_IRQn
29282#define LLW_IRQHandler LLWU_IRQHandler
29283
29284/*!
29285 * @}
29286 */ /* end of group SDK_Compatibility_Symbols */
29287
29288
29289#endif /* _MK26F18_H_ */
29290
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 21:53:35 +0100