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1/*
2** ###################################################################
3** Version: rev. 1.6, 2015-06-08
4** Build: b200921
5**
6** Abstract:
7** Chip specific module features.
8**
9** Copyright 2016 Freescale Semiconductor, Inc.
10** Copyright 2016-2020 NXP
11** All rights reserved.
12**
13** SPDX-License-Identifier: BSD-3-Clause
14**
15** http: www.nxp.com
16** mail: [email protected]
17**
18** Revisions:
19** - rev. 1.0 (2014-12-04)
20** Initial version.
21** - rev. 1.1 (2015-01-21)
22** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances
23** - rev. 1.2 (2015-02-19)
24** Renamed interrupt vector LLW to LLWU.
25** - rev. 1.3 (2015-05-19)
26** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT.
27** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC.
28** Added features for PDB and PORT.
29** - rev. 1.4 (2015-05-25)
30** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS
31** - rev. 1.5 (2015-05-27)
32** Several USB features added.
33** - rev. 1.6 (2015-06-08)
34** FTM features BUS_CLOCK and FAST_CLOCK removed.
35**
36** ###################################################################
37*/
38
39#ifndef _MK26F18_FEATURES_H_
40#define _MK26F18_FEATURES_H_
41
42/* SOC module features */
43
44/* @brief ADC16 availability on the SoC. */
45#define FSL_FEATURE_SOC_ADC16_COUNT (2)
46/* @brief AIPS availability on the SoC. */
47#define FSL_FEATURE_SOC_AIPS_COUNT (2)
48/* @brief AXBS availability on the SoC. */
49#define FSL_FEATURE_SOC_AXBS_COUNT (1)
50/* @brief FLEXCAN availability on the SoC. */
51#define FSL_FEATURE_SOC_FLEXCAN_COUNT (2)
52/* @brief MMCAU availability on the SoC. */
53#define FSL_FEATURE_SOC_MMCAU_COUNT (1)
54/* @brief CMP availability on the SoC. */
55#define FSL_FEATURE_SOC_CMP_COUNT (4)
56/* @brief CMT availability on the SoC. */
57#define FSL_FEATURE_SOC_CMT_COUNT (1)
58/* @brief CRC availability on the SoC. */
59#define FSL_FEATURE_SOC_CRC_COUNT (1)
60/* @brief DAC availability on the SoC. */
61#define FSL_FEATURE_SOC_DAC_COUNT (2)
62/* @brief EDMA availability on the SoC. */
63#define FSL_FEATURE_SOC_EDMA_COUNT (1)
64/* @brief DMAMUX availability on the SoC. */
65#define FSL_FEATURE_SOC_DMAMUX_COUNT (1)
66/* @brief DSPI availability on the SoC. */
67#define FSL_FEATURE_SOC_DSPI_COUNT (3)
68/* @brief EWM availability on the SoC. */
69#define FSL_FEATURE_SOC_EWM_COUNT (1)
70/* @brief FB availability on the SoC. */
71#define FSL_FEATURE_SOC_FB_COUNT (1)
72/* @brief FMC availability on the SoC. */
73#define FSL_FEATURE_SOC_FMC_COUNT (1)
74/* @brief FTFE availability on the SoC. */
75#define FSL_FEATURE_SOC_FTFE_COUNT (1)
76/* @brief FTM availability on the SoC. */
77#define FSL_FEATURE_SOC_FTM_COUNT (4)
78/* @brief GPIO availability on the SoC. */
79#define FSL_FEATURE_SOC_GPIO_COUNT (5)
80/* @brief I2C availability on the SoC. */
81#define FSL_FEATURE_SOC_I2C_COUNT (4)
82/* @brief I2S availability on the SoC. */
83#define FSL_FEATURE_SOC_I2S_COUNT (1)
84/* @brief LLWU availability on the SoC. */
85#define FSL_FEATURE_SOC_LLWU_COUNT (1)
86/* @brief LMEM availability on the SoC. */
87#define FSL_FEATURE_SOC_LMEM_COUNT (1)
88/* @brief LPTMR availability on the SoC. */
89#define FSL_FEATURE_SOC_LPTMR_COUNT (1)
90/* @brief LPUART availability on the SoC. */
91#define FSL_FEATURE_SOC_LPUART_COUNT (1)
92/* @brief MCG availability on the SoC. */
93#define FSL_FEATURE_SOC_MCG_COUNT (1)
94/* @brief MCM availability on the SoC. */
95#define FSL_FEATURE_SOC_MCM_COUNT (1)
96/* @brief SYSMPU availability on the SoC. */
97#define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
98/* @brief OSC availability on the SoC. */
99#define FSL_FEATURE_SOC_OSC_COUNT (1)
100/* @brief PDB availability on the SoC. */
101#define FSL_FEATURE_SOC_PDB_COUNT (1)
102/* @brief PIT availability on the SoC. */
103#define FSL_FEATURE_SOC_PIT_COUNT (1)
104/* @brief PMC availability on the SoC. */
105#define FSL_FEATURE_SOC_PMC_COUNT (1)
106/* @brief PORT availability on the SoC. */
107#define FSL_FEATURE_SOC_PORT_COUNT (5)
108/* @brief RCM availability on the SoC. */
109#define FSL_FEATURE_SOC_RCM_COUNT (1)
110/* @brief RFSYS availability on the SoC. */
111#define FSL_FEATURE_SOC_RFSYS_COUNT (1)
112/* @brief RFVBAT availability on the SoC. */
113#define FSL_FEATURE_SOC_RFVBAT_COUNT (1)
114/* @brief RNG availability on the SoC. */
115#define FSL_FEATURE_SOC_RNG_COUNT (1)
116/* @brief RTC availability on the SoC. */
117#define FSL_FEATURE_SOC_RTC_COUNT (1)
118/* @brief SDHC availability on the SoC. */
119#define FSL_FEATURE_SOC_SDHC_COUNT (1)
120/* @brief SDRAM availability on the SoC. */
121#define FSL_FEATURE_SOC_SDRAM_COUNT (1)
122/* @brief SIM availability on the SoC. */
123#define FSL_FEATURE_SOC_SIM_COUNT (1)
124/* @brief SMC availability on the SoC. */
125#define FSL_FEATURE_SOC_SMC_COUNT (1)
126/* @brief TPM availability on the SoC. */
127#define FSL_FEATURE_SOC_TPM_COUNT (2)
128/* @brief TSI availability on the SoC. */
129#define FSL_FEATURE_SOC_TSI_COUNT (1)
130/* @brief UART availability on the SoC. */
131#define FSL_FEATURE_SOC_UART_COUNT (5)
132/* @brief USB availability on the SoC. */
133#define FSL_FEATURE_SOC_USB_COUNT (1)
134/* @brief USBDCD availability on the SoC. */
135#define FSL_FEATURE_SOC_USBDCD_COUNT (1)
136/* @brief USBHS availability on the SoC. */
137#define FSL_FEATURE_SOC_USBHS_COUNT (1)
138/* @brief USBHSDCD availability on the SoC. */
139#define FSL_FEATURE_SOC_USBHSDCD_COUNT (1)
140/* @brief USBPHY availability on the SoC. */
141#define FSL_FEATURE_SOC_USBPHY_COUNT (1)
142/* @brief VREF availability on the SoC. */
143#define FSL_FEATURE_SOC_VREF_COUNT (1)
144/* @brief WDOG availability on the SoC. */
145#define FSL_FEATURE_SOC_WDOG_COUNT (1)
146
147/* ADC16 module features */
148
149/* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */
150#define FSL_FEATURE_ADC16_HAS_PGA (0)
151/* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */
152#define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0)
153/* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */
154#define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0)
155/* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */
156#define FSL_FEATURE_ADC16_HAS_DMA (1)
157/* @brief Has differential mode (bitfield SC1x[DIFF]). */
158#define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1)
159/* @brief Has FIFO (bit SC4[AFDEP]). */
160#define FSL_FEATURE_ADC16_HAS_FIFO (0)
161/* @brief FIFO size if available (bitfield SC4[AFDEP]). */
162#define FSL_FEATURE_ADC16_FIFO_SIZE (0)
163/* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */
164#define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1)
165/* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */
166#define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0)
167/* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */
168#define FSL_FEATURE_ADC16_HAS_CALIBRATION (1)
169/* @brief Has HW averaging (bit SC3[AVGE]). */
170#define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1)
171/* @brief Has offset correction (register OFS). */
172#define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1)
173/* @brief Maximum ADC resolution. */
174#define FSL_FEATURE_ADC16_MAX_RESOLUTION (16)
175/* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */
176#define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2)
177
178/* FLEXCAN module features */
179
180/* @brief Message buffer size */
181#define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16)
182/* @brief Has doze mode support (register bit field MCR[DOZE]). */
183#define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0)
184/* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */
185#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0)
186/* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */
187#define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1)
188/* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */
189#define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0)
190/* @brief Instance has extended bit timing register (register CBT). */
191#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0)
192/* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */
193#define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0)
194/* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */
195#define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0)
196/* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */
197#define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1)
198/* @brief Has bitfield name BUF31TO0M. */
199#define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0)
200/* @brief Number of interrupt vectors. */
201#define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6)
202/* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */
203#define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0)
204
205/* CMP module features */
206
207/* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */
208#define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1)
209/* @brief Has Window mode in CMP (register bit field CR1[WE]). */
210#define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1)
211/* @brief Has External sample supported in CMP (register bit field CR1[SE]). */
212#define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1)
213/* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */
214#define FSL_FEATURE_CMP_HAS_DMA (1)
215/* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */
216#define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1)
217/* @brief Has DAC Test function in CMP (register DACTEST). */
218#define FSL_FEATURE_CMP_HAS_DAC_TEST (0)
219
220/* CRC module features */
221
222/* @brief Has data register with name CRC */
223#define FSL_FEATURE_CRC_HAS_CRC_REG (0)
224
225/* DAC module features */
226
227/* @brief Define the size of hardware buffer */
228#define FSL_FEATURE_DAC_BUFFER_SIZE (16)
229/* @brief Define whether the buffer supports watermark event detection or not. */
230#define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1)
231/* @brief Define whether the buffer supports watermark selection detection or not. */
232#define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1)
233/* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */
234#define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1)
235/* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */
236#define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1)
237/* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */
238#define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1)
239/* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */
240#define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1)
241/* @brief Define whether FIFO buffer mode is available or not. */
242#define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0)
243/* @brief Define whether swing buffer mode is available or not.. */
244#define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1)
245
246/* EDMA module features */
247
248/* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
249#define FSL_FEATURE_EDMA_MODULE_CHANNEL (32)
250/* @brief Total number of DMA channels on all modules. */
251#define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32)
252/* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */
253#define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2)
254/* @brief Has DMA_Error interrupt vector. */
255#define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1)
256/* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */
257#define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32)
258/* @brief Channel IRQ entry shared offset. */
259#define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16)
260/* @brief If 8 bytes transfer supported. */
261#define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0)
262/* @brief If 16 bytes transfer supported. */
263#define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1)
264
265/* DMAMUX module features */
266
267/* @brief Number of DMA channels (related to number of register CHCFGn). */
268#define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32)
269/* @brief Total number of DMA channels on all modules. */
270#define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (32)
271/* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */
272#define FSL_FEATURE_DMAMUX_HAS_TRIG (1)
273/* @brief Register CHCFGn width. */
274#define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8)
275
276/* EWM module features */
277
278/* @brief Has clock select (register CLKCTRL). */
279#define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0)
280/* @brief Has clock prescaler (register CLKPRESCALER). */
281#define FSL_FEATURE_EWM_HAS_PRESCALER (0)
282
283/* FLEXBUS module features */
284
285/* No feature definitions */
286
287/* FLASH module features */
288
289/* @brief Is of type FTFA. */
290#define FSL_FEATURE_FLASH_IS_FTFA (0)
291/* @brief Is of type FTFE. */
292#define FSL_FEATURE_FLASH_IS_FTFE (1)
293/* @brief Is of type FTFL. */
294#define FSL_FEATURE_FLASH_IS_FTFL (0)
295/* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */
296#define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1)
297/* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */
298#define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1)
299/* @brief Has EEPROM region protection (register FEPROT). */
300#define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1)
301/* @brief Has data flash region protection (register FDPROT). */
302#define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1)
303/* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */
304#define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1)
305/* @brief Has flash cache control in FMC module. */
306#define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1)
307/* @brief Has flash cache control in MCM module. */
308#define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0)
309/* @brief Has flash cache control in MSCM module. */
310#define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0)
311/* @brief Has prefetch speculation control in flash, such as kv5x. */
312#define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0)
313/* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */
314#define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0)
315/* @brief P-Flash start address. */
316#define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000)
317/* @brief P-Flash block count. */
318#define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (4)
319/* @brief P-Flash block size. */
320#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288)
321/* @brief P-Flash sector size. */
322#define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096)
323/* @brief P-Flash write unit size. */
324#define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8)
325/* @brief P-Flash data path width. */
326#define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16)
327/* @brief P-Flash block swap feature. */
328#define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1)
329/* @brief P-Flash protection region count. */
330#define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32)
331/* @brief Has FlexNVM memory. */
332#define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0)
333/* @brief Has FlexNVM alias. */
334#define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0)
335/* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */
336#define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000)
337/* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */
338#define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000)
339/* @brief FlexNVM block count. */
340#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0)
341/* @brief FlexNVM block size. */
342#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0)
343/* @brief FlexNVM sector size. */
344#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0)
345/* @brief FlexNVM write unit size. */
346#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0)
347/* @brief FlexNVM data path width. */
348#define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0)
349/* @brief Has FlexRAM memory. */
350#define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1)
351/* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */
352#define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000)
353/* @brief FlexRAM size. */
354#define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096)
355/* @brief Has 0x00 Read 1s Block command. */
356#define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1)
357/* @brief Has 0x01 Read 1s Section command. */
358#define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1)
359/* @brief Has 0x02 Program Check command. */
360#define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1)
361/* @brief Has 0x03 Read Resource command. */
362#define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1)
363/* @brief Has 0x06 Program Longword command. */
364#define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0)
365/* @brief Has 0x07 Program Phrase command. */
366#define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1)
367/* @brief Has 0x08 Erase Flash Block command. */
368#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1)
369/* @brief Has 0x09 Erase Flash Sector command. */
370#define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1)
371/* @brief Has 0x0B Program Section command. */
372#define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1)
373/* @brief Has 0x40 Read 1s All Blocks command. */
374#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1)
375/* @brief Has 0x41 Read Once command. */
376#define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1)
377/* @brief Has 0x43 Program Once command. */
378#define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1)
379/* @brief Has 0x44 Erase All Blocks command. */
380#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1)
381/* @brief Has 0x45 Verify Backdoor Access Key command. */
382#define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1)
383/* @brief Has 0x46 Swap Control command. */
384#define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1)
385/* @brief Has 0x49 Erase All Blocks Unsecure command. */
386#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0)
387/* @brief Has 0x4A Read 1s All Execute-only Segments command. */
388#define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
389/* @brief Has 0x4B Erase All Execute-only Segments command. */
390#define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0)
391/* @brief Has 0x80 Program Partition command. */
392#define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0)
393/* @brief Has 0x81 Set FlexRAM Function command. */
394#define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0)
395/* @brief P-Flash Erase/Read 1st all block command address alignment. */
396#define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16)
397/* @brief P-Flash Erase sector command address alignment. */
398#define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16)
399/* @brief P-Flash Rrogram/Verify section command address alignment. */
400#define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16)
401/* @brief P-Flash Read resource command address alignment. */
402#define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8)
403/* @brief P-Flash Program check command address alignment. */
404#define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4)
405/* @brief P-Flash Program check command address alignment. */
406#define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16)
407/* @brief FlexNVM Erase/Read 1st all block command address alignment. */
408#define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0)
409/* @brief FlexNVM Erase sector command address alignment. */
410#define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0)
411/* @brief FlexNVM Rrogram/Verify section command address alignment. */
412#define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0)
413/* @brief FlexNVM Read resource command address alignment. */
414#define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0)
415/* @brief FlexNVM Program check command address alignment. */
416#define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0)
417/* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
418#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU)
419/* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
420#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU)
421/* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
422#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU)
423/* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
424#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU)
425/* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
426#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU)
427/* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
428#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU)
429/* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
430#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU)
431/* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
432#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU)
433/* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
434#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU)
435/* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
436#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU)
437/* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
438#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU)
439/* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
440#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU)
441/* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
442#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU)
443/* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
444#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU)
445/* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
446#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU)
447/* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */
448#define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU)
449/* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
450#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF)
451/* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
452#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF)
453/* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
454#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000)
455/* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
456#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800)
457/* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
458#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400)
459/* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
460#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200)
461/* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
462#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100)
463/* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
464#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080)
465/* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
466#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040)
467/* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
468#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020)
469/* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
470#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF)
471/* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
472#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF)
473/* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
474#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF)
475/* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
476#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF)
477/* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
478#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF)
479/* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */
480#define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000)
481
482/* FTM module features */
483
484/* @brief Number of channels. */
485#define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \
486 (((x) == FTM0) ? (8) : \
487 (((x) == FTM1) ? (2) : \
488 (((x) == FTM2) ? (2) : \
489 (((x) == FTM3) ? (8) : (-1)))))
490/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
491#define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
492/* @brief Has extended deadtime value. */
493#define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0)
494/* @brief Enable pwm output for the module. */
495#define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0)
496/* @brief Has half-cycle reload for the module. */
497#define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0)
498/* @brief Has reload interrupt. */
499#define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0)
500/* @brief Has reload initialization trigger. */
501#define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0)
502/* @brief Has DMA support, bitfield CnSC[DMA]. */
503#define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1)
504/* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */
505#define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0)
506/* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */
507#define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0)
508/* @brief Has no QDCTRL. */
509#define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0)
510/* @brief If instance has only TPM function. */
511#define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0)
512
513/* GPIO module features */
514
515/* @brief Has GPIO attribute checker register (GACR). */
516#define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0)
517
518/* I2C module features */
519
520/* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */
521#define FSL_FEATURE_I2C_HAS_SMBUS (1)
522/* @brief Maximum supported baud rate in kilobit per second. */
523#define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400)
524/* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */
525#define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0)
526/* @brief Has DMA support (register bit C1[DMAEN]). */
527#define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1)
528/* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */
529#define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1)
530/* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */
531#define FSL_FEATURE_I2C_HAS_STOP_DETECT (0)
532/* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */
533#define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1)
534/* @brief Maximum width of the glitch filter in number of bus clocks. */
535#define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15)
536/* @brief Has control of the drive capability of the I2C pins. */
537#define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1)
538/* @brief Has double buffering support (register S2). */
539#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0)
540/* @brief Has double buffer enable. */
541#define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0)
542
543/* SAI module features */
544
545/* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */
546#define FSL_FEATURE_SAI_FIFO_COUNT (8)
547/* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */
548#define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2)
549/* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */
550#define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32)
551/* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */
552#define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1)
553/* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */
554#define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1)
555/* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */
556#define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1)
557/* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */
558#define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1)
559/* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */
560#define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0)
561/* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */
562#define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1)
563/* @brief Ihe interrupt source number */
564#define FSL_FEATURE_SAI_INT_SOURCE_NUM (2)
565/* @brief Has register of MCR. */
566#define FSL_FEATURE_SAI_HAS_MCR (1)
567/* @brief Has register of MDR */
568#define FSL_FEATURE_SAI_HAS_MDR (1)
569/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
570#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
571/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
572#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0)
573
574/* LLWU module features */
575
576#if defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VMI18)
577 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
578 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32)
579 /* @brief Has pins 8-15 connected to LLWU device. */
580 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
581 /* @brief Maximum number of internal modules connected to LLWU device. */
582 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
583 /* @brief Number of digital filters. */
584 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4)
585 /* @brief Has MF register. */
586 #define FSL_FEATURE_LLWU_HAS_MF (1)
587 /* @brief Has PF register. */
588 #define FSL_FEATURE_LLWU_HAS_PF (1)
589 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
590 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
591 /* @brief Has no internal module wakeup flag register. */
592 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
593 /* @brief Has external pin 0 connected to LLWU device. */
594 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
595 /* @brief Index of port of external pin. */
596 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
597 /* @brief Number of external pin port on specified port. */
598 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
599 /* @brief Has external pin 1 connected to LLWU device. */
600 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
601 /* @brief Index of port of external pin. */
602 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
603 /* @brief Number of external pin port on specified port. */
604 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
605 /* @brief Has external pin 2 connected to LLWU device. */
606 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
607 /* @brief Index of port of external pin. */
608 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
609 /* @brief Number of external pin port on specified port. */
610 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
611 /* @brief Has external pin 3 connected to LLWU device. */
612 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
613 /* @brief Index of port of external pin. */
614 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
615 /* @brief Number of external pin port on specified port. */
616 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
617 /* @brief Has external pin 4 connected to LLWU device. */
618 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
619 /* @brief Index of port of external pin. */
620 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
621 /* @brief Number of external pin port on specified port. */
622 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
623 /* @brief Has external pin 5 connected to LLWU device. */
624 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
625 /* @brief Index of port of external pin. */
626 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
627 /* @brief Number of external pin port on specified port. */
628 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
629 /* @brief Has external pin 6 connected to LLWU device. */
630 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
631 /* @brief Index of port of external pin. */
632 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
633 /* @brief Number of external pin port on specified port. */
634 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
635 /* @brief Has external pin 7 connected to LLWU device. */
636 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
637 /* @brief Index of port of external pin. */
638 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
639 /* @brief Number of external pin port on specified port. */
640 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
641 /* @brief Has external pin 8 connected to LLWU device. */
642 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
643 /* @brief Index of port of external pin. */
644 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
645 /* @brief Number of external pin port on specified port. */
646 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
647 /* @brief Has external pin 9 connected to LLWU device. */
648 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
649 /* @brief Index of port of external pin. */
650 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
651 /* @brief Number of external pin port on specified port. */
652 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
653 /* @brief Has external pin 10 connected to LLWU device. */
654 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
655 /* @brief Index of port of external pin. */
656 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
657 /* @brief Number of external pin port on specified port. */
658 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
659 /* @brief Has external pin 11 connected to LLWU device. */
660 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
661 /* @brief Index of port of external pin. */
662 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
663 /* @brief Number of external pin port on specified port. */
664 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
665 /* @brief Has external pin 12 connected to LLWU device. */
666 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
667 /* @brief Index of port of external pin. */
668 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
669 /* @brief Number of external pin port on specified port. */
670 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
671 /* @brief Has external pin 13 connected to LLWU device. */
672 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
673 /* @brief Index of port of external pin. */
674 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
675 /* @brief Number of external pin port on specified port. */
676 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
677 /* @brief Has external pin 14 connected to LLWU device. */
678 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
679 /* @brief Index of port of external pin. */
680 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
681 /* @brief Number of external pin port on specified port. */
682 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
683 /* @brief Has external pin 15 connected to LLWU device. */
684 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
685 /* @brief Index of port of external pin. */
686 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
687 /* @brief Number of external pin port on specified port. */
688 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
689 /* @brief Has external pin 16 connected to LLWU device. */
690 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
691 /* @brief Index of port of external pin. */
692 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX)
693 /* @brief Number of external pin port on specified port. */
694 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6)
695 /* @brief Has external pin 17 connected to LLWU device. */
696 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
697 /* @brief Index of port of external pin. */
698 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX)
699 /* @brief Number of external pin port on specified port. */
700 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9)
701 /* @brief Has external pin 18 connected to LLWU device. */
702 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
703 /* @brief Index of port of external pin. */
704 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX)
705 /* @brief Number of external pin port on specified port. */
706 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10)
707 /* @brief Has external pin 19 connected to LLWU device. */
708 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1)
709 /* @brief Index of port of external pin. */
710 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX)
711 /* @brief Number of external pin port on specified port. */
712 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17)
713 /* @brief Has external pin 20 connected to LLWU device. */
714 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1)
715 /* @brief Index of port of external pin. */
716 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX)
717 /* @brief Number of external pin port on specified port. */
718 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18)
719 /* @brief Has external pin 21 connected to LLWU device. */
720 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1)
721 /* @brief Index of port of external pin. */
722 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX)
723 /* @brief Number of external pin port on specified port. */
724 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25)
725 /* @brief Has external pin 22 connected to LLWU device. */
726 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1)
727 /* @brief Index of port of external pin. */
728 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX)
729 /* @brief Number of external pin port on specified port. */
730 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10)
731 /* @brief Has external pin 23 connected to LLWU device. */
732 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1)
733 /* @brief Index of port of external pin. */
734 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX)
735 /* @brief Number of external pin port on specified port. */
736 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11)
737 /* @brief Has external pin 24 connected to LLWU device. */
738 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1)
739 /* @brief Index of port of external pin. */
740 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX)
741 /* @brief Number of external pin port on specified port. */
742 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8)
743 /* @brief Has external pin 25 connected to LLWU device. */
744 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1)
745 /* @brief Index of port of external pin. */
746 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX)
747 /* @brief Number of external pin port on specified port. */
748 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11)
749 /* @brief Has external pin 26 connected to LLWU device. */
750 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
751 /* @brief Index of port of external pin. */
752 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
753 /* @brief Number of external pin port on specified port. */
754 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
755 /* @brief Has external pin 27 connected to LLWU device. */
756 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
757 /* @brief Index of port of external pin. */
758 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
759 /* @brief Number of external pin port on specified port. */
760 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
761 /* @brief Has external pin 28 connected to LLWU device. */
762 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
763 /* @brief Index of port of external pin. */
764 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
765 /* @brief Number of external pin port on specified port. */
766 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
767 /* @brief Has external pin 29 connected to LLWU device. */
768 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (1)
769 /* @brief Index of port of external pin. */
770 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
771 /* @brief Number of external pin port on specified port. */
772 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
773 /* @brief Has external pin 30 connected to LLWU device. */
774 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (1)
775 /* @brief Index of port of external pin. */
776 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
777 /* @brief Number of external pin port on specified port. */
778 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
779 /* @brief Has external pin 31 connected to LLWU device. */
780 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (1)
781 /* @brief Index of port of external pin. */
782 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
783 /* @brief Number of external pin port on specified port. */
784 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
785 /* @brief Has internal module 0 connected to LLWU device. */
786 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
787 /* @brief Has internal module 1 connected to LLWU device. */
788 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
789 /* @brief Has internal module 2 connected to LLWU device. */
790 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
791 /* @brief Has internal module 3 connected to LLWU device. */
792 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
793 /* @brief Has internal module 4 connected to LLWU device. */
794 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
795 /* @brief Has internal module 5 connected to LLWU device. */
796 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
797 /* @brief Has internal module 6 connected to LLWU device. */
798 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
799 /* @brief Has internal module 7 connected to LLWU device. */
800 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
801 /* @brief Has Version ID Register (LLWU_VERID). */
802 #define FSL_FEATURE_LLWU_HAS_VERID (0)
803 /* @brief Has Parameter Register (LLWU_PARAM). */
804 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
805 /* @brief Width of registers of the LLWU. */
806 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
807 /* @brief Has DMA Enable register (LLWU_DE). */
808 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
809#elif defined(CPU_MK26FN2M0VLQ18) || defined(CPU_MK26FN2M0VMD18)
810 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */
811 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32)
812 /* @brief Has pins 8-15 connected to LLWU device. */
813 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1)
814 /* @brief Maximum number of internal modules connected to LLWU device. */
815 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8)
816 /* @brief Number of digital filters. */
817 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4)
818 /* @brief Has MF register. */
819 #define FSL_FEATURE_LLWU_HAS_MF (1)
820 /* @brief Has PF register. */
821 #define FSL_FEATURE_LLWU_HAS_PF (1)
822 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */
823 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0)
824 /* @brief Has no internal module wakeup flag register. */
825 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0)
826 /* @brief Has external pin 0 connected to LLWU device. */
827 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1)
828 /* @brief Index of port of external pin. */
829 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX)
830 /* @brief Number of external pin port on specified port. */
831 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1)
832 /* @brief Has external pin 1 connected to LLWU device. */
833 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1)
834 /* @brief Index of port of external pin. */
835 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX)
836 /* @brief Number of external pin port on specified port. */
837 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2)
838 /* @brief Has external pin 2 connected to LLWU device. */
839 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1)
840 /* @brief Index of port of external pin. */
841 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX)
842 /* @brief Number of external pin port on specified port. */
843 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4)
844 /* @brief Has external pin 3 connected to LLWU device. */
845 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1)
846 /* @brief Index of port of external pin. */
847 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX)
848 /* @brief Number of external pin port on specified port. */
849 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4)
850 /* @brief Has external pin 4 connected to LLWU device. */
851 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1)
852 /* @brief Index of port of external pin. */
853 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX)
854 /* @brief Number of external pin port on specified port. */
855 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13)
856 /* @brief Has external pin 5 connected to LLWU device. */
857 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1)
858 /* @brief Index of port of external pin. */
859 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX)
860 /* @brief Number of external pin port on specified port. */
861 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0)
862 /* @brief Has external pin 6 connected to LLWU device. */
863 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1)
864 /* @brief Index of port of external pin. */
865 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX)
866 /* @brief Number of external pin port on specified port. */
867 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1)
868 /* @brief Has external pin 7 connected to LLWU device. */
869 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1)
870 /* @brief Index of port of external pin. */
871 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX)
872 /* @brief Number of external pin port on specified port. */
873 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3)
874 /* @brief Has external pin 8 connected to LLWU device. */
875 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1)
876 /* @brief Index of port of external pin. */
877 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX)
878 /* @brief Number of external pin port on specified port. */
879 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4)
880 /* @brief Has external pin 9 connected to LLWU device. */
881 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1)
882 /* @brief Index of port of external pin. */
883 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX)
884 /* @brief Number of external pin port on specified port. */
885 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5)
886 /* @brief Has external pin 10 connected to LLWU device. */
887 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1)
888 /* @brief Index of port of external pin. */
889 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX)
890 /* @brief Number of external pin port on specified port. */
891 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6)
892 /* @brief Has external pin 11 connected to LLWU device. */
893 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1)
894 /* @brief Index of port of external pin. */
895 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX)
896 /* @brief Number of external pin port on specified port. */
897 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11)
898 /* @brief Has external pin 12 connected to LLWU device. */
899 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1)
900 /* @brief Index of port of external pin. */
901 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX)
902 /* @brief Number of external pin port on specified port. */
903 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0)
904 /* @brief Has external pin 13 connected to LLWU device. */
905 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1)
906 /* @brief Index of port of external pin. */
907 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX)
908 /* @brief Number of external pin port on specified port. */
909 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2)
910 /* @brief Has external pin 14 connected to LLWU device. */
911 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1)
912 /* @brief Index of port of external pin. */
913 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX)
914 /* @brief Number of external pin port on specified port. */
915 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4)
916 /* @brief Has external pin 15 connected to LLWU device. */
917 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1)
918 /* @brief Index of port of external pin. */
919 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX)
920 /* @brief Number of external pin port on specified port. */
921 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6)
922 /* @brief Has external pin 16 connected to LLWU device. */
923 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1)
924 /* @brief Index of port of external pin. */
925 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX)
926 /* @brief Number of external pin port on specified port. */
927 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6)
928 /* @brief Has external pin 17 connected to LLWU device. */
929 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1)
930 /* @brief Index of port of external pin. */
931 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX)
932 /* @brief Number of external pin port on specified port. */
933 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9)
934 /* @brief Has external pin 18 connected to LLWU device. */
935 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1)
936 /* @brief Index of port of external pin. */
937 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX)
938 /* @brief Number of external pin port on specified port. */
939 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10)
940 /* @brief Has external pin 19 connected to LLWU device. */
941 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0)
942 /* @brief Index of port of external pin. */
943 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0)
944 /* @brief Number of external pin port on specified port. */
945 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0)
946 /* @brief Has external pin 20 connected to LLWU device. */
947 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0)
948 /* @brief Index of port of external pin. */
949 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0)
950 /* @brief Number of external pin port on specified port. */
951 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0)
952 /* @brief Has external pin 21 connected to LLWU device. */
953 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1)
954 /* @brief Index of port of external pin. */
955 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX)
956 /* @brief Number of external pin port on specified port. */
957 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25)
958 /* @brief Has external pin 22 connected to LLWU device. */
959 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1)
960 /* @brief Index of port of external pin. */
961 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX)
962 /* @brief Number of external pin port on specified port. */
963 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10)
964 /* @brief Has external pin 23 connected to LLWU device. */
965 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1)
966 /* @brief Index of port of external pin. */
967 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX)
968 /* @brief Number of external pin port on specified port. */
969 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11)
970 /* @brief Has external pin 24 connected to LLWU device. */
971 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1)
972 /* @brief Index of port of external pin. */
973 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX)
974 /* @brief Number of external pin port on specified port. */
975 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8)
976 /* @brief Has external pin 25 connected to LLWU device. */
977 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1)
978 /* @brief Index of port of external pin. */
979 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX)
980 /* @brief Number of external pin port on specified port. */
981 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11)
982 /* @brief Has external pin 26 connected to LLWU device. */
983 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0)
984 /* @brief Index of port of external pin. */
985 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0)
986 /* @brief Number of external pin port on specified port. */
987 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0)
988 /* @brief Has external pin 27 connected to LLWU device. */
989 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0)
990 /* @brief Index of port of external pin. */
991 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0)
992 /* @brief Number of external pin port on specified port. */
993 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0)
994 /* @brief Has external pin 28 connected to LLWU device. */
995 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0)
996 /* @brief Index of port of external pin. */
997 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0)
998 /* @brief Number of external pin port on specified port. */
999 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0)
1000 /* @brief Has external pin 29 connected to LLWU device. */
1001 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (1)
1002 /* @brief Index of port of external pin. */
1003 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0)
1004 /* @brief Number of external pin port on specified port. */
1005 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0)
1006 /* @brief Has external pin 30 connected to LLWU device. */
1007 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (1)
1008 /* @brief Index of port of external pin. */
1009 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0)
1010 /* @brief Number of external pin port on specified port. */
1011 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0)
1012 /* @brief Has external pin 31 connected to LLWU device. */
1013 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (1)
1014 /* @brief Index of port of external pin. */
1015 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0)
1016 /* @brief Number of external pin port on specified port. */
1017 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0)
1018 /* @brief Has internal module 0 connected to LLWU device. */
1019 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1)
1020 /* @brief Has internal module 1 connected to LLWU device. */
1021 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1)
1022 /* @brief Has internal module 2 connected to LLWU device. */
1023 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1)
1024 /* @brief Has internal module 3 connected to LLWU device. */
1025 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1)
1026 /* @brief Has internal module 4 connected to LLWU device. */
1027 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1)
1028 /* @brief Has internal module 5 connected to LLWU device. */
1029 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1)
1030 /* @brief Has internal module 6 connected to LLWU device. */
1031 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0)
1032 /* @brief Has internal module 7 connected to LLWU device. */
1033 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1)
1034 /* @brief Has Version ID Register (LLWU_VERID). */
1035 #define FSL_FEATURE_LLWU_HAS_VERID (0)
1036 /* @brief Has Parameter Register (LLWU_PARAM). */
1037 #define FSL_FEATURE_LLWU_HAS_PARAM (0)
1038 /* @brief Width of registers of the LLWU. */
1039 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8)
1040 /* @brief Has DMA Enable register (LLWU_DE). */
1041 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0)
1042#endif /* defined(CPU_MK26FN2M0CAC18) || defined(CPU_MK26FN2M0VMI18) */
1043
1044/* LMEM module features */
1045
1046/* @brief Has process identifier support. */
1047#define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (0)
1048/* @brief Has L1 cache. */
1049#define FSL_FEATURE_HAS_L1CACHE (1)
1050/* @brief L1 ICACHE line size in byte. */
1051#define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (16)
1052/* @brief L1 DCACHE line size in byte. */
1053#define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (16)
1054
1055/* LPTMR module features */
1056
1057/* @brief Has shared interrupt handler with another LPTMR module. */
1058#define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0)
1059/* @brief Whether LPTMR counter is 32 bits width. */
1060#define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0)
1061/* @brief Has timer DMA request enable (register bit CSR[TDRE]). */
1062#define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0)
1063
1064/* LPUART module features */
1065
1066/* @brief LPUART0 and LPUART1 has shared interrupt vector. */
1067#define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0)
1068/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
1069#define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0)
1070/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
1071#define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1)
1072/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
1073#define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
1074/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1075#define FSL_FEATURE_LPUART_HAS_FIFO (0)
1076/* @brief Has 32-bit register MODIR */
1077#define FSL_FEATURE_LPUART_HAS_MODIR (1)
1078/* @brief Hardware flow control (RTS, CTS) is supported. */
1079#define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1)
1080/* @brief Infrared (modulation) is supported. */
1081#define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1)
1082/* @brief 2 bits long stop bit is available. */
1083#define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
1084/* @brief If 10-bit mode is supported. */
1085#define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1)
1086/* @brief If 7-bit mode is supported. */
1087#define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0)
1088/* @brief Baud rate fine adjustment is available. */
1089#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0)
1090/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
1091#define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1)
1092/* @brief Baud rate oversampling is available. */
1093#define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1)
1094/* @brief Baud rate oversampling is available. */
1095#define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1)
1096/* @brief Peripheral type. */
1097#define FSL_FEATURE_LPUART_IS_SCI (1)
1098/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1099#define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0)
1100/* @brief Supports two match addresses to filter incoming frames. */
1101#define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1)
1102/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
1103#define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1)
1104/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
1105#define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0)
1106/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
1107#define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1)
1108/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
1109#define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0)
1110/* @brief Has improved smart card (ISO7816 protocol) support. */
1111#define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0)
1112/* @brief Has local operation network (CEA709.1-B protocol) support. */
1113#define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
1114/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
1115#define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1)
1116/* @brief Lin break detect available (has bit BAUD[LBKDIE]). */
1117#define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1)
1118/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
1119#define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0)
1120/* @brief Has separate DMA RX and TX requests. */
1121#define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
1122/* @brief Has separate RX and TX interrupts. */
1123#define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0)
1124/* @brief Has LPAURT_PARAM. */
1125#define FSL_FEATURE_LPUART_HAS_PARAM (0)
1126/* @brief Has LPUART_VERID. */
1127#define FSL_FEATURE_LPUART_HAS_VERID (0)
1128/* @brief Has LPUART_GLOBAL. */
1129#define FSL_FEATURE_LPUART_HAS_GLOBAL (0)
1130/* @brief Has LPUART_PINCFG. */
1131#define FSL_FEATURE_LPUART_HAS_PINCFG (0)
1132
1133/* MCG module features */
1134
1135/* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */
1136#define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1)
1137/* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */
1138#define FSL_FEATURE_MCG_PLL_PRDIV_MAX (7)
1139/* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */
1140#define FSL_FEATURE_MCG_PLL_VDIV_BASE (16)
1141/* @brief PLL reference clock low range. OSCCLK/PLL_R. */
1142#define FSL_FEATURE_MCG_PLL_REF_MIN (8000000)
1143/* @brief PLL reference clock high range. OSCCLK/PLL_R. */
1144#define FSL_FEATURE_MCG_PLL_REF_MAX (16000000)
1145/* @brief The PLL clock is divided by 2 before VCO divider. */
1146#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (1)
1147/* @brief FRDIV supports 1280. */
1148#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1)
1149/* @brief FRDIV supports 1536. */
1150#define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1)
1151/* @brief MCGFFCLK divider. */
1152#define FSL_FEATURE_MCG_FFCLK_DIV (1)
1153/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */
1154#define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0)
1155/* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */
1156#define FSL_FEATURE_MCG_HAS_RTC_32K (1)
1157/* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */
1158#define FSL_FEATURE_MCG_HAS_PLL1 (0)
1159/* @brief Has 48MHz internal oscillator. */
1160#define FSL_FEATURE_MCG_HAS_IRC_48M (1)
1161/* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */
1162#define FSL_FEATURE_MCG_HAS_OSC1 (0)
1163/* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */
1164#define FSL_FEATURE_MCG_HAS_FCFTRIM (1)
1165/* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */
1166#define FSL_FEATURE_MCG_HAS_LOLRE (1)
1167/* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */
1168#define FSL_FEATURE_MCG_USE_OSCSEL (1)
1169/* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */
1170#define FSL_FEATURE_MCG_USE_PLLREFSEL (0)
1171/* @brief TBD */
1172#define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0)
1173/* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */
1174#define FSL_FEATURE_MCG_HAS_PLL (1)
1175/* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */
1176#define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1)
1177/* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */
1178#define FSL_FEATURE_MCG_HAS_PLL_VDIV (1)
1179/* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */
1180#define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0)
1181/* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */
1182#define FSL_FEATURE_MCG_HAS_FLL (1)
1183/* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */
1184#define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1)
1185/* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */
1186#define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1)
1187/* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */
1188#define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1)
1189/* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */
1190#define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (1)
1191/* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */
1192#define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1)
1193/* @brief Has external clock monitor (register bit C6[CME]). */
1194#define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1)
1195/* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */
1196#define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0)
1197/* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */
1198#define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0)
1199/* @brief Has PEI mode or PBI mode. */
1200#define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0)
1201/* @brief Reset clock mode is BLPI. */
1202#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
1203
1204/* interrupt module features */
1205
1206/* @brief Lowest interrupt request number. */
1207#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
1208/* @brief Highest interrupt request number. */
1209#define FSL_FEATURE_INTERRUPT_IRQ_MAX (99)
1210
1211/* OSC module features */
1212
1213/* @brief Has OSC1 external oscillator. */
1214#define FSL_FEATURE_OSC_HAS_OSC1 (0)
1215/* @brief Has OSC0 external oscillator. */
1216#define FSL_FEATURE_OSC_HAS_OSC0 (0)
1217/* @brief Has OSC external oscillator (without index). */
1218#define FSL_FEATURE_OSC_HAS_OSC (1)
1219/* @brief Number of OSC external oscillators. */
1220#define FSL_FEATURE_OSC_OSC_COUNT (1)
1221/* @brief Has external reference clock divider (register bit field DIV[ERPS]). */
1222#define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1)
1223
1224/* PDB module features */
1225
1226/* @brief Has DAC support. */
1227#define FSL_FEATURE_PDB_HAS_DAC (1)
1228/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
1229#define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0)
1230/* @brief PDB channel number). */
1231#define FSL_FEATURE_PDB_CHANNEL_COUNT (2)
1232/* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */
1233#define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2)
1234/* @brief DAC interval trigger number). */
1235#define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (2)
1236/* @brief Pulse out number). */
1237#define FSL_FEATURE_PDB_PULSE_OUT_COUNT (4)
1238
1239/* PIT module features */
1240
1241/* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */
1242#define FSL_FEATURE_PIT_TIMER_COUNT (4)
1243/* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */
1244#define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1)
1245/* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */
1246#define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1)
1247/* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */
1248#define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0)
1249/* @brief Has timer enable control. */
1250#define FSL_FEATURE_PIT_HAS_MDIS (1)
1251
1252/* PMC module features */
1253
1254/* @brief Has Bandgap Enable In VLPx Operation support. */
1255#define FSL_FEATURE_PMC_HAS_BGEN (1)
1256/* @brief Has Bandgap Buffer Enable. */
1257#define FSL_FEATURE_PMC_HAS_BGBE (1)
1258/* @brief Has Bandgap Buffer Drive Select. */
1259#define FSL_FEATURE_PMC_HAS_BGBDS (0)
1260/* @brief Has Low-Voltage Detect Voltage Select support. */
1261#define FSL_FEATURE_PMC_HAS_LVDV (1)
1262/* @brief Has Low-Voltage Warning Voltage Select support. */
1263#define FSL_FEATURE_PMC_HAS_LVWV (1)
1264/* @brief Has LPO. */
1265#define FSL_FEATURE_PMC_HAS_LPO (0)
1266/* @brief Has VLPx option PMC_REGSC[VLPO]. */
1267#define FSL_FEATURE_PMC_HAS_VLPO (0)
1268/* @brief Has acknowledge isolation support. */
1269#define FSL_FEATURE_PMC_HAS_ACKISO (1)
1270/* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */
1271#define FSL_FEATURE_PMC_HAS_REGFPM (0)
1272/* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */
1273#define FSL_FEATURE_PMC_HAS_REGONS (1)
1274/* @brief Has PMC_HVDSC1. */
1275#define FSL_FEATURE_PMC_HAS_HVDSC1 (0)
1276/* @brief Has PMC_PARAM. */
1277#define FSL_FEATURE_PMC_HAS_PARAM (0)
1278/* @brief Has PMC_VERID. */
1279#define FSL_FEATURE_PMC_HAS_VERID (0)
1280
1281/* PORT module features */
1282
1283/* @brief Has control lock (register bit PCR[LK]). */
1284#define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1)
1285/* @brief Has open drain control (register bit PCR[ODE]). */
1286#define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1)
1287/* @brief Has digital filter (registers DFER, DFCR and DFWR). */
1288#define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1)
1289/* @brief Has DMA request (register bit field PCR[IRQC] values). */
1290#define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1)
1291/* @brief Has pull resistor selection available. */
1292#define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1)
1293/* @brief Has pull resistor enable (register bit PCR[PE]). */
1294#define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1)
1295/* @brief Has slew rate control (register bit PCR[SRE]). */
1296#define FSL_FEATURE_PORT_HAS_SLEW_RATE (1)
1297/* @brief Has passive filter (register bit field PCR[PFE]). */
1298#define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1)
1299/* @brief Has drive strength control (register bit PCR[DSE]). */
1300#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1)
1301/* @brief Has separate drive strength register (HDRVE). */
1302#define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0)
1303/* @brief Has glitch filter (register IOFLT). */
1304#define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0)
1305/* @brief Defines width of PCR[MUX] field. */
1306#define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3)
1307/* @brief Has dedicated interrupt vector. */
1308#define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1)
1309/* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */
1310#define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0)
1311/* @brief Defines whether PCR[IRQC] bit-field has flag states. */
1312#define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0)
1313/* @brief Defines whether PCR[IRQC] bit-field has trigger states. */
1314#define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0)
1315
1316/* RCM module features */
1317
1318/* @brief Has Loss-of-Lock Reset support. */
1319#define FSL_FEATURE_RCM_HAS_LOL (1)
1320/* @brief Has Loss-of-Clock Reset support. */
1321#define FSL_FEATURE_RCM_HAS_LOC (1)
1322/* @brief Has JTAG generated Reset support. */
1323#define FSL_FEATURE_RCM_HAS_JTAG (1)
1324/* @brief Has EzPort generated Reset support. */
1325#define FSL_FEATURE_RCM_HAS_EZPORT (1)
1326/* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */
1327#define FSL_FEATURE_RCM_HAS_EZPMS (1)
1328/* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */
1329#define FSL_FEATURE_RCM_HAS_BOOTROM (0)
1330/* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */
1331#define FSL_FEATURE_RCM_HAS_SSRS (1)
1332/* @brief Has Version ID Register (RCM_VERID). */
1333#define FSL_FEATURE_RCM_HAS_VERID (0)
1334/* @brief Has Parameter Register (RCM_PARAM). */
1335#define FSL_FEATURE_RCM_HAS_PARAM (0)
1336/* @brief Has Reset Interrupt Enable Register RCM_SRIE. */
1337#define FSL_FEATURE_RCM_HAS_SRIE (0)
1338/* @brief Width of registers of the RCM. */
1339#define FSL_FEATURE_RCM_REG_WIDTH (8)
1340/* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */
1341#define FSL_FEATURE_RCM_HAS_CORE1 (0)
1342/* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */
1343#define FSL_FEATURE_RCM_HAS_MDM_AP (1)
1344/* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */
1345#define FSL_FEATURE_RCM_HAS_WAKEUP (1)
1346
1347/* RTC module features */
1348
1349/* @brief Has wakeup pin. */
1350#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1)
1351/* @brief Has wakeup pin selection (bit field CR[WPS]). */
1352#define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1)
1353/* @brief Has low power features (registers MER, MCLR and MCHR). */
1354#define FSL_FEATURE_RTC_HAS_MONOTONIC (1)
1355/* @brief Has read/write access control (registers WAR and RAR). */
1356#define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1)
1357/* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */
1358#define FSL_FEATURE_RTC_HAS_SECURITY (1)
1359/* @brief Has RTC_CLKIN available. */
1360#define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0)
1361/* @brief Has prescaler adjust for LPO. */
1362#define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0)
1363/* @brief Has Clock Pin Enable field. */
1364#define FSL_FEATURE_RTC_HAS_CPE (0)
1365/* @brief Has Timer Seconds Interrupt Configuration field. */
1366#define FSL_FEATURE_RTC_HAS_TSIC (0)
1367/* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */
1368#define FSL_FEATURE_RTC_HAS_OSC_SCXP (1)
1369/* @brief Has Tamper Interrupt Register (register TIR). */
1370#define FSL_FEATURE_RTC_HAS_TIR (0)
1371/* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */
1372#define FSL_FEATURE_RTC_HAS_TIR_TPIE (0)
1373/* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */
1374#define FSL_FEATURE_RTC_HAS_TIR_SIE (0)
1375/* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */
1376#define FSL_FEATURE_RTC_HAS_TIR_LCIE (0)
1377/* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */
1378#define FSL_FEATURE_RTC_HAS_SR_TIDF (0)
1379/* @brief Has Tamper Detect Register (register TDR). */
1380#define FSL_FEATURE_RTC_HAS_TDR (0)
1381/* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */
1382#define FSL_FEATURE_RTC_HAS_TDR_TPF (0)
1383/* @brief Has Security Tamper Flag (bitfield TDR[STF]). */
1384#define FSL_FEATURE_RTC_HAS_TDR_STF (0)
1385/* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */
1386#define FSL_FEATURE_RTC_HAS_TDR_LCTF (0)
1387/* @brief Has Tamper Time Seconds Register (register TTSR). */
1388#define FSL_FEATURE_RTC_HAS_TTSR (1)
1389/* @brief Has Pin Configuration Register (register PCR). */
1390#define FSL_FEATURE_RTC_HAS_PCR (0)
1391
1392/* SDHC module features */
1393
1394/* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */
1395#define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (0)
1396/* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */
1397#define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0)
1398/* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */
1399#define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0)
1400
1401/* SIM module features */
1402
1403/* @brief Has USB FS divider. */
1404#define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0)
1405/* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */
1406#define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0)
1407/* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */
1408#define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1)
1409/* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */
1410#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0)
1411/* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */
1412#define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1)
1413/* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */
1414#define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2)
1415/* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */
1416#define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1)
1417/* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */
1418#define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1)
1419/* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */
1420#define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (1)
1421/* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */
1422#define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0)
1423/* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */
1424#define FSL_FEATURE_SIM_OPT_HAS_FBSL (1)
1425/* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */
1426#define FSL_FEATURE_SIM_OPT_HAS_PCR (0)
1427/* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */
1428#define FSL_FEATURE_SIM_OPT_HAS_MCC (0)
1429/* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */
1430#define FSL_FEATURE_SIM_OPT_HAS_ODE (0)
1431/* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */
1432#define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1)
1433/* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */
1434#define FSL_FEATURE_SIM_OPT_UART_COUNT (4)
1435/* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */
1436#define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0)
1437/* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */
1438#define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0)
1439/* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */
1440#define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0)
1441/* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */
1442#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0)
1443/* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */
1444#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0)
1445/* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */
1446#define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0)
1447/* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */
1448#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1)
1449/* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */
1450#define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1)
1451/* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */
1452#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0)
1453/* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */
1454#define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0)
1455/* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */
1456#define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1)
1457/* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */
1458#define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2)
1459/* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */
1460#define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1)
1461/* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */
1462#define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2)
1463/* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */
1464#define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1)
1465/* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */
1466#define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1)
1467/* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */
1468#define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2)
1469/* @brief Has FTM module(s) configuration. */
1470#define FSL_FEATURE_SIM_OPT_HAS_FTM (1)
1471/* @brief Number of FTM modules. */
1472#define FSL_FEATURE_SIM_OPT_FTM_COUNT (4)
1473/* @brief Number of FTM triggers with selectable source. */
1474#define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2)
1475/* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */
1476#define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1)
1477/* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */
1478#define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1)
1479/* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */
1480#define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1)
1481/* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */
1482#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1)
1483/* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */
1484#define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0)
1485/* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */
1486#define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1)
1487/* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */
1488#define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4)
1489/* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */
1490#define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1)
1491/* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */
1492#define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1)
1493/* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */
1494#define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1)
1495/* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */
1496#define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1)
1497/* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */
1498#define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1)
1499/* @brief Has TPM module(s) configuration. */
1500#define FSL_FEATURE_SIM_OPT_HAS_TPM (1)
1501/* @brief The highest TPM module index. */
1502#define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2)
1503/* @brief Has TPM module with index 0. */
1504#define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0)
1505/* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */
1506#define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0)
1507/* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */
1508#define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0)
1509/* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1510#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1)
1511/* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */
1512#define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0)
1513/* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */
1514#define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1)
1515/* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */
1516#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0)
1517/* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */
1518#define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0)
1519/* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */
1520#define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1)
1521/* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */
1522#define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1)
1523/* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */
1524#define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0)
1525/* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */
1526#define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0)
1527/* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */
1528#define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1)
1529/* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */
1530#define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0)
1531/* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */
1532#define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0)
1533/* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */
1534#define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0)
1535/* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */
1536#define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1)
1537/* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */
1538#define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0)
1539/* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */
1540#define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0)
1541/* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */
1542#define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1)
1543/* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */
1544#define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0)
1545/* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */
1546#define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0)
1547/* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */
1548#define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0)
1549/* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */
1550#define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0)
1551/* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */
1552#define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1)
1553/* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */
1554#define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1)
1555/* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */
1556#define FSL_FEATURE_SIM_OPT_ADC_COUNT (2)
1557/* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */
1558#define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1)
1559/* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */
1560#define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1)
1561/* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */
1562#define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0)
1563/* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */
1564#define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0)
1565/* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */
1566#define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0)
1567/* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */
1568#define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0)
1569/* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */
1570#define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0)
1571/* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */
1572#define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0)
1573/* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */
1574#define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0)
1575/* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */
1576#define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0)
1577/* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */
1578#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1)
1579/* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */
1580#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1)
1581/* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */
1582#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1)
1583/* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */
1584#define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4)
1585/* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */
1586#define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0)
1587/* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */
1588#define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1)
1589/* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */
1590#define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0)
1591/* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */
1592#define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0)
1593/* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */
1594#define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (1)
1595/* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */
1596#define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0)
1597/* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */
1598#define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1)
1599/* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */
1600#define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0)
1601/* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */
1602#define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1)
1603/* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */
1604#define FSL_FEATURE_SIM_SDID_HAS_FAMID (1)
1605/* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */
1606#define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1)
1607/* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */
1608#define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1)
1609/* @brief Has device die ID (register bit field SDID[DIEID]). */
1610#define FSL_FEATURE_SIM_SDID_HAS_DIEID (1)
1611/* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */
1612#define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0)
1613/* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */
1614#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1)
1615/* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */
1616#define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1)
1617/* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */
1618#define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0)
1619/* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */
1620#define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1)
1621/* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */
1622#define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1)
1623/* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */
1624#define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1)
1625/* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */
1626#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1)
1627/* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */
1628#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1)
1629/* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */
1630#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0)
1631/* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */
1632#define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0)
1633/* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */
1634#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1)
1635/* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */
1636#define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1)
1637/* @brief Has miscellanious control register (register MCR). */
1638#define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0)
1639/* @brief Has COP watchdog (registers COPC and SRVCOP). */
1640#define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0)
1641/* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */
1642#define FSL_FEATURE_SIM_HAS_COP_STOP (0)
1643/* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */
1644#define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0)
1645
1646/* SMC module features */
1647
1648/* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */
1649#define FSL_FEATURE_SMC_HAS_PSTOPO (1)
1650/* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */
1651#define FSL_FEATURE_SMC_HAS_LPOPO (0)
1652/* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */
1653#define FSL_FEATURE_SMC_HAS_PORPO (1)
1654/* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */
1655#define FSL_FEATURE_SMC_HAS_LPWUI (0)
1656/* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */
1657#define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1)
1658/* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */
1659#define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0)
1660/* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */
1661#define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0)
1662/* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */
1663#define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1)
1664/* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */
1665#define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1)
1666/* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */
1667#define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1)
1668/* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */
1669#define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1)
1670/* @brief Has stop submode. */
1671#define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1)
1672/* @brief Has stop submode 0(VLLS0). */
1673#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1)
1674/* @brief Has stop submode 1(VLLS1). */
1675#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1)
1676/* @brief Has stop submode 2(VLLS2). */
1677#define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1)
1678/* @brief Has SMC_PARAM. */
1679#define FSL_FEATURE_SMC_HAS_PARAM (0)
1680/* @brief Has SMC_VERID. */
1681#define FSL_FEATURE_SMC_HAS_VERID (0)
1682/* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */
1683#define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1)
1684/* @brief Has tamper reset (register bit SRS[TAMPER]). */
1685#define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0)
1686/* @brief Has security violation reset (register bit SRS[SECVIO]). */
1687#define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0)
1688/* @brief Width of SMC registers. */
1689#define FSL_FEATURE_SMC_REG_WIDTH (8)
1690
1691/* DSPI module features */
1692
1693/* @brief Receive/transmit FIFO size in number of items. */
1694#define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \
1695 (((x) == SPI0) ? (4) : \
1696 (((x) == SPI1) ? (1) : \
1697 (((x) == SPI2) ? (1) : (-1))))
1698/* @brief Maximum transfer data width in bits. */
1699#define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16)
1700/* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */
1701#define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6)
1702/* @brief Number of chip select pins. */
1703#define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6)
1704/* @brief Number of CTAR registers. */
1705#define FSL_FEATURE_DSPI_CTAR_COUNT (2)
1706/* @brief Has chip select strobe capability on the PCS5 pin. */
1707#define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1)
1708/* @brief Has separated TXDATA and CMD FIFOs (register SREX). */
1709#define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0)
1710/* @brief Has 16-bit data transfer support. */
1711#define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1)
1712/* @brief Has separate DMA RX and TX requests. */
1713#define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1)
1714
1715/* SYSMPU module features */
1716
1717/* @brief Specifies number of descriptors available. */
1718#define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12)
1719/* @brief Has process identifier support. */
1720#define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1)
1721/* @brief Total number of MPU slave. */
1722#define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5)
1723/* @brief Total number of MPU master. */
1724#define FSL_FEATURE_SYSMPU_MASTER_COUNT (7)
1725
1726/* SysTick module features */
1727
1728/* @brief Systick has external reference clock. */
1729#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
1730/* @brief Systick external reference clock is core clock divided by this value. */
1731#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
1732
1733/* TPM module features */
1734
1735/* @brief Bus clock is the source clock for the module. */
1736#define FSL_FEATURE_TPM_BUS_CLOCK (0)
1737/* @brief Number of channels. */
1738#define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) (2)
1739/* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */
1740#define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0)
1741/* @brief Has TPM_PARAM. */
1742#define FSL_FEATURE_TPM_HAS_PARAM (0)
1743/* @brief Has TPM_VERID. */
1744#define FSL_FEATURE_TPM_HAS_VERID (0)
1745/* @brief Has TPM_GLOBAL. */
1746#define FSL_FEATURE_TPM_HAS_GLOBAL (0)
1747/* @brief Has TPM_TRIG. */
1748#define FSL_FEATURE_TPM_HAS_TRIG (0)
1749/* @brief Has counter pause on trigger. */
1750#define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1)
1751/* @brief Has external trigger selection. */
1752#define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1)
1753/* @brief Has TPM_COMBINE register. */
1754#define FSL_FEATURE_TPM_HAS_COMBINE (1)
1755/* @brief Whether COMBINE register has effect. */
1756#define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1)
1757/* @brief Has TPM_POL. */
1758#define FSL_FEATURE_TPM_HAS_POL (1)
1759/* @brief Has TPM_FILTER register. */
1760#define FSL_FEATURE_TPM_HAS_FILTER (1)
1761/* @brief Whether FILTER register has effect. */
1762#define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1)
1763/* @brief Has TPM_QDCTRL register. */
1764#define FSL_FEATURE_TPM_HAS_QDCTRL (1)
1765/* @brief Whether QDCTRL register has effect. */
1766#define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1)
1767/* @brief Is affected by errata with ID 050050 (Incorrect duty output when EPWM mode is set to PS=0 during write 1 to CnV register). */
1768#define FSL_FEATURE_TPM_HAS_ERRATA_050050 (0)
1769
1770/* TSI module features */
1771
1772/* @brief TSI module version. */
1773#define FSL_FEATURE_TSI_VERSION (4)
1774/* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */
1775#define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (1)
1776/* @brief Number of TSI channels. */
1777#define FSL_FEATURE_TSI_CHANNEL_COUNT (16)
1778
1779/* UART module features */
1780
1781/* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */
1782#define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1)
1783/* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */
1784#define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0)
1785/* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */
1786#define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1)
1787/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1788#define FSL_FEATURE_UART_HAS_FIFO (1)
1789/* @brief Hardware flow control (RTS, CTS) is supported. */
1790#define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1)
1791/* @brief Infrared (modulation) is supported. */
1792#define FSL_FEATURE_UART_HAS_IR_SUPPORT (1)
1793/* @brief 2 bits long stop bit is available. */
1794#define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1)
1795/* @brief If 10-bit mode is supported. */
1796#define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1)
1797/* @brief Baud rate fine adjustment is available. */
1798#define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1)
1799/* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */
1800#define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0)
1801/* @brief Baud rate oversampling is available. */
1802#define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0)
1803/* @brief Baud rate oversampling is available. */
1804#define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0)
1805/* @brief Peripheral type. */
1806#define FSL_FEATURE_UART_IS_SCI (0)
1807/* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */
1808#define FSL_FEATURE_UART_FIFO_SIZEn(x) \
1809 (((x) == UART0) ? (8) : \
1810 (((x) == UART1) ? (8) : \
1811 (((x) == UART2) ? (1) : \
1812 (((x) == UART3) ? (1) : \
1813 (((x) == UART4) ? (1) : (-1))))))
1814/* @brief Supports two match addresses to filter incoming frames. */
1815#define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1)
1816/* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */
1817#define FSL_FEATURE_UART_HAS_DMA_ENABLE (0)
1818/* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */
1819#define FSL_FEATURE_UART_HAS_DMA_SELECT (1)
1820/* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */
1821#define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1)
1822/* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */
1823#define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1)
1824/* @brief Has improved smart card (ISO7816 protocol) support. */
1825#define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1)
1826/* @brief Has local operation network (CEA709.1-B protocol) support. */
1827#define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0)
1828/* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */
1829#define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0)
1830/* @brief Lin break detect available (has bit BDH[LBKDIE]). */
1831#define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1)
1832/* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */
1833#define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1)
1834/* @brief Has separate DMA RX and TX requests. */
1835#define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \
1836 (((x) == UART0) ? (1) : \
1837 (((x) == UART1) ? (1) : \
1838 (((x) == UART2) ? (1) : \
1839 (((x) == UART3) ? (1) : \
1840 (((x) == UART4) ? (0) : (-1))))))
1841
1842/* USB module features */
1843
1844/* @brief KHCI module instance count */
1845#define FSL_FEATURE_USB_KHCI_COUNT (1)
1846/* @brief HOST mode enabled */
1847#define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1)
1848/* @brief OTG mode enabled */
1849#define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1)
1850/* @brief Size of the USB dedicated RAM */
1851#define FSL_FEATURE_USB_KHCI_USB_RAM (0)
1852/* @brief Has KEEP_ALIVE_CTRL register */
1853#define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0)
1854/* @brief Has the Dynamic SOF threshold compare support */
1855#define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0)
1856/* @brief Has the VBUS detect support */
1857#define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0)
1858/* @brief Has the IRC48M module clock support */
1859#define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1)
1860/* @brief Number of endpoints supported */
1861#define FSL_FEATURE_USB_ENDPT_COUNT (16)
1862/* @brief Has STALL_IL/OL_DIS registers */
1863#define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0)
1864/* @brief Has STALL_IH/OH_DIS registers */
1865#define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0)
1866
1867/* USBHS module features */
1868
1869/* @brief EHCI module instance count */
1870#define FSL_FEATURE_USBHS_EHCI_COUNT (1)
1871/* @brief Number of endpoints supported */
1872#define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
1873
1874/* VREF module features */
1875
1876/* @brief Has chop oscillator (bit TRM[CHOPEN]) */
1877#define FSL_FEATURE_VREF_HAS_CHOP_OSC (1)
1878/* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */
1879#define FSL_FEATURE_VREF_HAS_COMPENSATION (1)
1880/* @brief If high/low buffer mode supported */
1881#define FSL_FEATURE_VREF_MODE_LV_TYPE (1)
1882/* @brief Module has also low reference (registers VREFL/VREFH) */
1883#define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0)
1884/* @brief Has VREF_TRM4. */
1885#define FSL_FEATURE_VREF_HAS_TRM4 (0)
1886
1887/* WDOG module features */
1888
1889/* @brief Watchdog is available. */
1890#define FSL_FEATURE_WDOG_HAS_WATCHDOG (1)
1891/* @brief Has Wait mode support. */
1892#define FSL_FEATURE_WDOG_HAS_WAITEN (1)
1893
1894#endif /* _MK26F18_FEATURES_H_ */
1895
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