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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/drivers/fsl_clock.h
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1/*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_CLOCK_H_
10#define _FSL_CLOCK_H_
11
12#include "fsl_common.h"
13
14/*! @addtogroup clock */
15/*! @{ */
16
17/*! @file */
18
19/*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23/*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37#ifndef MCG_CONFIG_CHECK_PARAM
38#define MCG_CONFIG_CHECK_PARAM 0U
39#endif
40
41/*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53#endif
54
55/*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59/*! @name Driver version */
60/*@{*/
61/*! @brief CLOCK driver version 2.5.2. */
62#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 2))
63/*@}*/
64
65/*! @brief External XTAL0 (OSC0) clock frequency.
66 *
67 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
68 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
69 * if XTAL0 is 8 MHz:
70 * @code
71 * Set up the OSC0
72 * CLOCK_InitOsc0(...);
73 * Set the XTAL0 value to the clock driver.
74 * CLOCK_SetXtal0Freq(80000000);
75 * @endcode
76 *
77 * This is important for the multicore platforms where only one core needs to set up the
78 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
79 * to get a valid clock frequency.
80 */
81extern volatile uint32_t g_xtal0Freq;
82
83/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
84 *
85 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
86 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
87 *
88 * This is important for the multicore platforms where only one core needs to set up
89 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
90 * to get a valid clock frequency.
91 */
92extern volatile uint32_t g_xtal32Freq;
93
94/*! @brief IRC48M clock frequency in Hz. */
95#define MCG_INTERNAL_IRC_48M 48000000U
96
97#if (defined(OSC) && !(defined(OSC0)))
98#define OSC0 OSC
99#endif
100
101/* Definition for delay API in clock driver, users can redefine it to the real application. */
102#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
103#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (120000000UL)
104#endif
105
106/*! @brief Clock ip name array for DMAMUX. */
107#define DMAMUX_CLOCKS \
108 { \
109 kCLOCK_Dmamux0 \
110 }
111
112/*! @brief Clock ip name array for RTC. */
113#define RTC_CLOCKS \
114 { \
115 kCLOCK_Rtc0 \
116 }
117
118/*! @brief Clock ip name array for PORT. */
119#define PORT_CLOCKS \
120 { \
121 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
122 }
123
124/*! @brief Clock ip name array for SAI. */
125#define SAI_CLOCKS \
126 { \
127 kCLOCK_Sai0 \
128 }
129
130/*! @brief Clock ip name array for FLEXBUS. */
131#define FLEXBUS_CLOCKS \
132 { \
133 kCLOCK_Flexbus0 \
134 }
135
136/*! @brief Clock ip name array for TSI. */
137#define TSI_CLOCKS \
138 { \
139 kCLOCK_Tsi0 \
140 }
141
142/*! @brief Clock ip name array for LPUART. */
143#define LPUART_CLOCKS \
144 { \
145 kCLOCK_Lpuart0 \
146 }
147
148/*! @brief Clock ip name array for EWM. */
149#define EWM_CLOCKS \
150 { \
151 kCLOCK_Ewm0 \
152 }
153
154/*! @brief Clock ip name array for PIT. */
155#define PIT_CLOCKS \
156 { \
157 kCLOCK_Pit0 \
158 }
159
160/*! @brief Clock ip name array for DSPI. */
161#define DSPI_CLOCKS \
162 { \
163 kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2 \
164 }
165
166/*! @brief Clock ip name array for LPTMR. */
167#define LPTMR_CLOCKS \
168 { \
169 kCLOCK_Lptmr0 \
170 }
171
172/*! @brief Clock ip name array for SDHC. */
173#define SDHC_CLOCKS \
174 { \
175 kCLOCK_Sdhc0 \
176 }
177
178/*! @brief Clock ip name array for FTM. */
179#define FTM_CLOCKS \
180 { \
181 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
182 }
183
184/*! @brief Clock ip name array for EDMA. */
185#define EDMA_CLOCKS \
186 { \
187 kCLOCK_Dma0 \
188 }
189
190/*! @brief Clock ip name array for FLEXCAN. */
191#define FLEXCAN_CLOCKS \
192 { \
193 kCLOCK_Flexcan0, kCLOCK_Flexcan1 \
194 }
195
196/*! @brief Clock ip name array for DAC. */
197#define DAC_CLOCKS \
198 { \
199 kCLOCK_Dac0, kCLOCK_Dac1 \
200 }
201
202/*! @brief Clock ip name array for ADC16. */
203#define ADC16_CLOCKS \
204 { \
205 kCLOCK_Adc0, kCLOCK_Adc1 \
206 }
207
208/*! @brief Clock ip name array for SDRAM. */
209#define SDRAM_CLOCKS \
210 { \
211 kCLOCK_Sdramc0 \
212 }
213
214/*! @brief Clock ip name array for MPU. */
215#define SYSMPU_CLOCKS \
216 { \
217 kCLOCK_Sysmpu0 \
218 }
219
220/*! @brief Clock ip name array for VREF. */
221#define VREF_CLOCKS \
222 { \
223 kCLOCK_Vref0 \
224 }
225
226/*! @brief Clock ip name array for CMT. */
227#define CMT_CLOCKS \
228 { \
229 kCLOCK_Cmt0 \
230 }
231
232/*! @brief Clock ip name array for UART. */
233#define UART_CLOCKS \
234 { \
235 kCLOCK_Uart0, kCLOCK_Uart1, kCLOCK_Uart2, kCLOCK_Uart3, kCLOCK_Uart4 \
236 }
237
238/*! @brief Clock ip name array for TPM. */
239#define TPM_CLOCKS \
240 { \
241 kCLOCK_IpInvalid, kCLOCK_Tpm1, kCLOCK_Tpm2 \
242 }
243
244/*! @brief Clock ip name array for RNGA. */
245#define RNGA_CLOCKS \
246 { \
247 kCLOCK_Rnga0 \
248 }
249
250/*! @brief Clock ip name array for CRC. */
251#define CRC_CLOCKS \
252 { \
253 kCLOCK_Crc0 \
254 }
255
256/*! @brief Clock ip name array for I2C. */
257#define I2C_CLOCKS \
258 { \
259 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3 \
260 }
261
262/*! @brief Clock ip name array for FTF. */
263#define FTF_CLOCKS \
264 { \
265 kCLOCK_Ftf0 \
266 }
267
268/*! @brief Clock ip name array for PDB. */
269#define PDB_CLOCKS \
270 { \
271 kCLOCK_Pdb0 \
272 }
273
274/*! @brief Clock ip name array for CMP. */
275#define CMP_CLOCKS \
276 { \
277 kCLOCK_Cmp0, kCLOCK_Cmp1, kCLOCK_Cmp2, kCLOCK_Cmp3 \
278 }
279
280/*!
281 * @brief LPO clock frequency.
282 */
283#define LPO_CLK_FREQ 1000U
284
285/*! @brief Peripherals clock source definition. */
286#define SYS_CLK kCLOCK_CoreSysClk
287#define BUS_CLK kCLOCK_BusClk
288
289#define I2C0_CLK_SRC BUS_CLK
290#define I2C1_CLK_SRC BUS_CLK
291#define I2C2_CLK_SRC BUS_CLK
292#define I2C3_CLK_SRC BUS_CLK
293#define DSPI0_CLK_SRC BUS_CLK
294#define DSPI1_CLK_SRC BUS_CLK
295#define DSPI2_CLK_SRC BUS_CLK
296#define UART0_CLK_SRC SYS_CLK
297#define UART1_CLK_SRC SYS_CLK
298#define UART2_CLK_SRC BUS_CLK
299#define UART3_CLK_SRC BUS_CLK
300#define UART4_CLK_SRC BUS_CLK
301
302/*! @brief Clock name used to get clock frequency. */
303typedef enum _clock_name
304{
305
306 /* ----------------------------- System layer clock -------------------------------*/
307 kCLOCK_CoreSysClk, /*!< Core/system clock */
308 kCLOCK_PlatClk, /*!< Platform clock */
309 kCLOCK_BusClk, /*!< Bus clock */
310 kCLOCK_FlexBusClk, /*!< FlexBus clock */
311 kCLOCK_FlashClk, /*!< Flash clock */
312 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
313 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
314
315 /* ---------------------------------- OSC clock -----------------------------------*/
316 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
317 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
318 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
319 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
320
321 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
322 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
323 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
324 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
325 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
326 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
327 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
328 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
329 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
330
331 /* --------------------------------- Other clock ----------------------------------*/
332 kCLOCK_LpoClk, /*!< LPO clock */
333
334} clock_name_t;
335
336/*! @brief USB clock source definition. */
337typedef enum _clock_usb_src
338{
339 kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */
340 kCLOCK_UsbSrcUsbPfd = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(2U), /*!< Use USBPFDCLK. */
341 kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */
342 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U), /*!< Use USB_CLKIN. */
343 kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not
344 care the clock source. */
345} clock_usb_src_t;
346
347/*! @brief Source of the USB HS PHY. */
348typedef enum _clock_usb_phy_src
349{
350 kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */
351} clock_usb_phy_src_t;
352
353/*! @brief Source of the USB HS PFD clock (USB1PFDCLK) */
354typedef enum _clock_usb_pfd_src
355{
356 kCLOCK_UsbPfdSrcExt = 0U, /*!< Use external crystal. */
357 kCLOCK_UsbPfdSrcFracDivBy4 = 1U, /*!< Use PFD_FRAC output divided by 4. */
358 kCLOCK_UsbPfdSrcFracDivBy2 = 2U, /*!< Use PFD_FRAC output divided by 2. */
359 kCLOCK_UsbPfdSrcFrac = 3U, /*!< Use PFD_FRAC output. */
360} clock_usb_pfd_src_t;
361
362/*------------------------------------------------------------------------------
363
364 clock_gate_t definition:
365
366 31 16 0
367 -----------------------------------------------------------------
368 | SIM_SCGC register offset | control bit offset in SCGC |
369 -----------------------------------------------------------------
370
371 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
372 SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
373
374 kClockGateSdhc0 = (0x1030 << 16) | 17;
375
376------------------------------------------------------------------------------*/
377
378#define CLK_GATE_REG_OFFSET_SHIFT 16U
379#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
380#define CLK_GATE_BIT_SHIFT_SHIFT 0U
381#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
382
383#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
384 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
385 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
386
387#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
388#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
389
390/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
391typedef enum _clock_ip_name
392{
393 kCLOCK_IpInvalid = 0U,
394 kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U),
395 kCLOCK_I2c3 = CLK_GATE_DEFINE(0x1028U, 7U),
396 kCLOCK_Uart4 = CLK_GATE_DEFINE(0x1028U, 10U),
397
398 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x102CU, 4U),
399 kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x102CU, 9U),
400 kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x102CU, 10U),
401 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U),
402 kCLOCK_Dac1 = CLK_GATE_DEFINE(0x102CU, 13U),
403
404 kCLOCK_Rnga0 = CLK_GATE_DEFINE(0x1030U, 0U),
405 kCLOCK_Usbhs0 = CLK_GATE_DEFINE(0x1030U, 1U),
406 kCLOCK_UsbhsPhy0 = CLK_GATE_DEFINE(0x1030U, 2U),
407 kCLOCK_UsbhsDcd0 = CLK_GATE_DEFINE(0x1030U, 3U),
408 kCLOCK_Flexcan1 = CLK_GATE_DEFINE(0x1030U, 4U),
409 kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U),
410 kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U),
411 kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U),
412 kCLOCK_Adc1 = CLK_GATE_DEFINE(0x1030U, 27U),
413
414 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
415 kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
416 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
417 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
418 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
419 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
420 kCLOCK_Uart2 = CLK_GATE_DEFINE(0x1034U, 12U),
421 kCLOCK_Uart3 = CLK_GATE_DEFINE(0x1034U, 13U),
422 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
423 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
424 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
425 kCLOCK_Cmp2 = CLK_GATE_DEFINE(0x1034U, 19U),
426 kCLOCK_Cmp3 = CLK_GATE_DEFINE(0x1034U, 19U),
427 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
428
429 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
430 kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U),
431 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
432 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
433 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
434 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
435 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
436
437 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
438 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
439 kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U),
440 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
441 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
442 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
443 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
444 kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U),
445 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
446 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
447 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
448 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
449 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
450 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
451 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
452
453 kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
454 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
455 kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
456 kCLOCK_Sdramc0 = CLK_GATE_DEFINE(0x1040U, 3U),
457} clock_ip_name_t;
458
459/*!@brief SIM configuration structure for clock setting. */
460typedef struct _sim_clock_config
461{
462 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
463 uint8_t pllFllDiv; /*!< PLLFLLSEL clock divider divisor. */
464 uint8_t pllFllFrac; /*!< PLLFLLSEL clock divider fraction. */
465 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
466 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
467} sim_clock_config_t;
468
469/*! @brief OSC work mode. */
470typedef enum _osc_mode
471{
472 kOSC_ModeExt = 0U, /*!< Use an external clock. */
473#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
474 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
475#else
476 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
477#endif
478 kOSC_ModeOscHighGain = 0U
479#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
480 | MCG_C2_EREFS_MASK
481#else
482 | MCG_C2_EREFS0_MASK
483#endif
484#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
485 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
486#else
487 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
488#endif
489} osc_mode_t;
490
491/*! @brief Oscillator capacitor load setting.*/
492enum _osc_cap_load
493{
494 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
495 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
496 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
497 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
498};
499
500/*! @brief OSCERCLK enable mode. */
501enum _oscer_enable_mode
502{
503 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
504 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
505};
506
507/*! @brief OSC configuration for OSCERCLK. */
508typedef struct _oscer_config
509{
510 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
511
512 uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/
513} oscer_config_t;
514
515/*!
516 * @brief OSC Initialization Configuration Structure
517 *
518 * Defines the configuration data structure to initialize the OSC.
519 * When porting to a new board, set the following members
520 * according to the board setting:
521 * 1. freq: The external frequency.
522 * 2. workMode: The OSC module mode.
523 */
524typedef struct _osc_config
525{
526 uint32_t freq; /*!< External clock frequency. */
527 uint8_t capLoad; /*!< Capacitor load setting. */
528 osc_mode_t workMode; /*!< OSC work mode setting. */
529 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
530} osc_config_t;
531
532/*! @brief MCG FLL reference clock source select. */
533typedef enum _mcg_fll_src
534{
535 kMCG_FllSrcExternal, /*!< External reference clock is selected */
536 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
537} mcg_fll_src_t;
538
539/*! @brief MCG internal reference clock select */
540typedef enum _mcg_irc_mode
541{
542 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
543 kMCG_IrcFast /*!< Fast internal reference clock selected */
544} mcg_irc_mode_t;
545
546/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
547typedef enum _mcg_dmx32
548{
549 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
550 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
551} mcg_dmx32_t;
552
553/*! @brief MCG DCO range select */
554typedef enum _mcg_drs
555{
556 kMCG_DrsLow, /*!< Low frequency range */
557 kMCG_DrsMid, /*!< Mid frequency range */
558 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
559 kMCG_DrsHigh /*!< High frequency range */
560} mcg_drs_t;
561
562/*! @brief MCG PLL reference clock select */
563typedef enum _mcg_pll_ref_src
564{
565 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
566 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
567} mcg_pll_ref_src_t;
568
569/*! @brief MCGOUT clock source. */
570typedef enum _mcg_clkout_src
571{
572 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
573 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
574 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
575} mcg_clkout_src_t;
576
577/*! @brief MCG Automatic Trim Machine Select */
578typedef enum _mcg_atm_select
579{
580 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
581 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
582} mcg_atm_select_t;
583
584/*! @brief MCG OSC Clock Select */
585typedef enum _mcg_oscsel
586{
587 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
588 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
589 kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */
590} mcg_oscsel_t;
591
592/*! @brief MCG PLLCS select */
593typedef enum _mcg_pll_clk_select
594{
595 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
596 kMCG_PllClkSelExtPll /* The external PLL clock is selected */
597} mcg_pll_clk_select_t;
598
599/*! @brief MCG clock monitor mode. */
600typedef enum _mcg_monitor_mode
601{
602 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
603 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
604 kMCG_MonitorReset /*!< System reset when clock lost. */
605} mcg_monitor_mode_t;
606
607/*! @brief MCG status. */
608enum
609{
610 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), /*!< Can't switch to target mode. */
611 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), /*!< Current mode invalid for the specific
612 function. */
613 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), /*!< Invalid bus clock for ATM. */
614 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), /*!< Invalid desired frequency for ATM. */
615 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), /*!< IRC is used when using ATM. */
616 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), /*!< Hardware fail occurs during ATM. */
617 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) /*!< Can't change the clock source because
618 it is in use. */
619};
620
621/*! @brief MCG status flags. */
622enum
623{
624 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
625 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
626 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
627 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
628 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
629 kMCG_ExtPllLostFlag = (1U << 9U), /*!< External PLL lost. */
630};
631
632/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
633enum
634{
635 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
636 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
637};
638
639/*! @brief MCG PLL clock enable mode definition. */
640enum
641{
642 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
643 MCG clock mode. Generally, the PLL
644 is disabled in FLL modes
645 (FEI/FBI/FEE/FBE). Setting the PLL clock
646 enable independent, enables the
647 PLL in the FLL modes. */
648 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
649};
650
651/*! @brief MCG mode definitions */
652typedef enum _mcg_mode
653{
654 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
655 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
656 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
657 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
658 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
659 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
660 kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
661 kMCG_ModePEE, /*!< PEE - PLL Engaged External */
662 kMCG_ModeError /*!< Unknown mode */
663} mcg_mode_t;
664
665/*! @brief MCG PLL configuration. */
666typedef struct _mcg_pll_config
667{
668 uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */
669 uint8_t prdiv; /*!< Reference divider PRDIV. */
670 uint8_t vdiv; /*!< VCO divider VDIV. */
671} mcg_pll_config_t;
672
673/*! @brief MCG mode change configuration structure
674 *
675 * When porting to a new board, set the following members
676 * according to the board setting:
677 * 1. frdiv: If the FLL uses the external reference clock, set this
678 * value to ensure that the external reference clock divided by frdiv is
679 * in the 31.25 kHz to 39.0625 kHz range.
680 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
681 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
682 * FSL_FEATURE_MCG_PLL_REF_MAX range.
683 */
684typedef struct _mcg_config
685{
686 mcg_mode_t mcgMode; /*!< MCG mode. */
687
688 /* ----------------------- MCGIRCCLK settings ------------------------ */
689 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
690 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
691 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
692
693 /* ------------------------ MCG FLL settings ------------------------- */
694 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
695 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
696 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
697 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
698
699 /* ------------------------ MCG PLL settings ------------------------- */
700 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
701
702 mcg_pll_clk_select_t pllcs; /*!< PLL select as output, PLLCS.*/
703
704} mcg_config_t;
705
706/*******************************************************************************
707 * API
708 ******************************************************************************/
709
710#if defined(__cplusplus)
711extern "C" {
712#endif /* __cplusplus */
713
714/*!
715 * @brief Enable the clock for specific IP.
716 *
717 * @param name Which clock to enable, see \ref clock_ip_name_t.
718 */
719static inline void CLOCK_EnableClock(clock_ip_name_t name)
720{
721 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
722 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
723}
724
725/*!
726 * @brief Disable the clock for specific IP.
727 *
728 * @param name Which clock to disable, see \ref clock_ip_name_t.
729 */
730static inline void CLOCK_DisableClock(clock_ip_name_t name)
731{
732 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
733 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
734}
735
736/*!
737 * @brief Set ERCLK32K source.
738 *
739 * @param src The value to set ERCLK32K clock source.
740 */
741static inline void CLOCK_SetEr32kClock(uint32_t src)
742{
743 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
744}
745
746/*!
747 * @brief Set SDHC0 clock source.
748 *
749 * @param src The value to set SDHC0 clock source.
750 */
751static inline void CLOCK_SetSdhc0Clock(uint32_t src)
752{
753 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src));
754}
755
756/*!
757 * @brief Set LPUART clock source.
758 *
759 * @param src The value to set LPUART clock source.
760 */
761static inline void CLOCK_SetLpuartClock(uint32_t src)
762{
763 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) | SIM_SOPT2_LPUARTSRC(src));
764}
765
766/*!
767 * @brief Set TPM clock source.
768 *
769 * @param src The value to set TPM clock source.
770 */
771static inline void CLOCK_SetTpmClock(uint32_t src)
772{
773 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src));
774}
775
776/*!
777 * @brief Set debug trace clock source.
778 *
779 * @param src The value to set debug trace clock source.
780 */
781static inline void CLOCK_SetTraceClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
782{
783 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
784 SIM->CLKDIV4 = SIM_CLKDIV4_TRACEDIV(divValue) | SIM_CLKDIV4_TRACEFRAC(fracValue);
785}
786
787/*!
788 * @brief Set PLLFLLSEL clock source.
789 *
790 * @param src The value to set PLLFLLSEL clock source.
791 * @param divValue PLLFLL clock divider divisor.
792 * @param fracValue PLLFLL clock divider fraction.
793 */
794static inline void CLOCK_SetPllFllSelClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
795{
796 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
797 SIM->CLKDIV3 = SIM_CLKDIV3_PLLFLLDIV(divValue) | SIM_CLKDIV3_PLLFLLFRAC(fracValue);
798}
799
800/*!
801 * @brief Set CLKOUT source.
802 *
803 * @param src The value to set CLKOUT source.
804 */
805static inline void CLOCK_SetClkOutClock(uint32_t src)
806{
807 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
808}
809
810/*!
811 * @brief Set RTC_CLKOUT source.
812 *
813 * @param src The value to set RTC_CLKOUT source.
814 */
815static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
816{
817 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
818}
819
820/*! @brief Enable USB HS clock.
821 *
822 * This function only enables the access to USB HS prepheral, upper layer
823 * should first call the @ref CLOCK_EnableUsbhs0PhyPllClock to enable the PHY
824 * clock to use USB HS.
825 *
826 * @param src USB HS does not care about the clock source, here must be @ref kCLOCK_UsbSrcUnused.
827 * @param freq USB HS does not care about the clock source, so this parameter is ignored.
828 * @retval true The clock is set successfully.
829 * @retval false The clock source is invalid to get proper USB HS clock.
830 */
831bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
832
833/*! @brief Disable USB HS clock.
834 *
835 * Disable USB HS clock, this function should not be called after
836 * @ref CLOCK_DisableUsbhs0PhyPllClock.
837 */
838void CLOCK_DisableUsbhs0Clock(void);
839
840/*! @brief Enable USB HS PHY PLL clock.
841 *
842 * This function enables the internal 480MHz USB PHY PLL clock.
843 *
844 * @param src USB HS PHY PLL clock source.
845 * @param freq The frequency specified by src.
846 * @retval true The clock is set successfully.
847 * @retval false The clock source is invalid to get proper USB HS clock.
848 */
849bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
850
851/*! @brief Disable USB HS PHY PLL clock.
852 *
853 * This function disables USB HS PHY PLL clock.
854 */
855void CLOCK_DisableUsbhs0PhyPllClock(void);
856
857/*! @brief Enable USB HS PFD clock.
858 *
859 * This function enables USB HS PFD clock. It should be called after function
860 * @ref CLOCK_EnableUsbhs0PhyPllClock.
861 * The PFD output clock is selected by the parameter @p src. When the @p src is
862 * @ref kCLOCK_UsbPfdSrcExt, then the PFD outout is from external crystal
863 * directly, in this case, the @p frac is not used. In other cases, the PFD_FRAC
864 * output clock frequency is 480MHz*18/frac, the PFD output frequency is based
865 * on the PFD_FRAC output.
866 *
867 * @param frac The value set to PFD_FRAC, it must be in the range of 18 to 35.
868 * @param src Source of the USB HS PFD clock (USB1PFDCLK).
869 */
870void CLOCK_EnableUsbhs0PfdClock(uint8_t frac, clock_usb_pfd_src_t src);
871
872/*! @brief Disable USB HS PFD clock.
873 *
874 * This function disables USB HS PFD clock. It should be called before function
875 * @ref CLOCK_DisableUsbhs0PhyPllClock.
876 */
877void CLOCK_DisableUsbhs0PfdClock(void);
878
879/*! @brief Enable USB FS clock.
880 *
881 * @param src USB FS clock source.
882 * @param freq The frequency specified by src.
883 * @retval true The clock is set successfully.
884 * @retval false The clock source is invalid to get proper USB FS clock.
885 */
886bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
887
888/*! @brief Disable USB FS clock.
889 *
890 * Disable USB FS clock.
891 */
892static inline void CLOCK_DisableUsbfs0Clock(void)
893{
894 CLOCK_DisableClock(kCLOCK_Usbfs0);
895}
896
897/*!
898 * @brief System clock divider
899 *
900 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
901 *
902 * @param outdiv1 Clock 1 output divider value.
903 *
904 * @param outdiv2 Clock 2 output divider value.
905 *
906 * @param outdiv3 Clock 3 output divider value.
907 *
908 * @param outdiv4 Clock 4 output divider value.
909 */
910static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
911{
912 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) |
913 SIM_CLKDIV1_OUTDIV4(outdiv4);
914}
915
916/*!
917 * @brief Gets the clock frequency for a specific clock name.
918 *
919 * This function checks the current clock configurations and then calculates
920 * the clock frequency for a specific clock name defined in clock_name_t.
921 * The MCG must be properly configured before using this function.
922 *
923 * @param clockName Clock names defined in clock_name_t
924 * @return Clock frequency value in Hertz
925 */
926uint32_t CLOCK_GetFreq(clock_name_t clockName);
927
928/*!
929 * @brief Get the core clock or system clock frequency.
930 *
931 * @return Clock frequency in Hz.
932 */
933uint32_t CLOCK_GetCoreSysClkFreq(void);
934
935/*!
936 * @brief Get the platform clock frequency.
937 *
938 * @return Clock frequency in Hz.
939 */
940uint32_t CLOCK_GetPlatClkFreq(void);
941
942/*!
943 * @brief Get the bus clock frequency.
944 *
945 * @return Clock frequency in Hz.
946 */
947uint32_t CLOCK_GetBusClkFreq(void);
948
949/*!
950 * @brief Get the flexbus clock frequency.
951 *
952 * @return Clock frequency in Hz.
953 */
954uint32_t CLOCK_GetFlexBusClkFreq(void);
955
956/*!
957 * @brief Get the flash clock frequency.
958 *
959 * @return Clock frequency in Hz.
960 */
961uint32_t CLOCK_GetFlashClkFreq(void);
962
963/*!
964 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
965 *
966 * @return Clock frequency in Hz.
967 */
968uint32_t CLOCK_GetPllFllSelClkFreq(void);
969
970/*!
971 * @brief Get the external reference 32K clock frequency (ERCLK32K).
972 *
973 * @return Clock frequency in Hz.
974 */
975uint32_t CLOCK_GetEr32kClkFreq(void);
976
977/*!
978 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
979 *
980 * @return Clock frequency in Hz.
981 */
982uint32_t CLOCK_GetOsc0ErClkFreq(void);
983
984/*!
985 * @brief Get the OSC0 external reference divided clock frequency.
986 *
987 * @return Clock frequency in Hz.
988 */
989uint32_t CLOCK_GetOsc0ErClkDivFreq(void);
990
991/*!
992 * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV).
993 *
994 * @return Clock frequency in Hz.
995 */
996uint32_t CLOCK_GetOsc0ErClkUndivFreq(void);
997
998/*!
999 * @brief Set the clock configure in SIM module.
1000 *
1001 * This function sets system layer clock settings in SIM module.
1002 *
1003 * @param config Pointer to the configure structure.
1004 */
1005void CLOCK_SetSimConfig(sim_clock_config_t const *config);
1006
1007/*!
1008 * @brief Set the system clock dividers in SIM to safe value.
1009 *
1010 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
1011 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
1012 * changes then the system level clocks may be out of range. This function could
1013 * be used before MCG mode change, to make sure system level clocks are in allowed
1014 * range.
1015 *
1016 * @param config Pointer to the configure structure.
1017 */
1018static inline void CLOCK_SetSimSafeDivs(void)
1019{
1020 SIM->CLKDIV1 = 0x03770000U;
1021}
1022
1023/*! @name MCG frequency functions. */
1024/*@{*/
1025
1026/*!
1027 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
1028 *
1029 * This function gets the MCG output clock frequency in Hz based on the current MCG
1030 * register value.
1031 *
1032 * @return The frequency of MCGOUTCLK.
1033 */
1034uint32_t CLOCK_GetOutClkFreq(void);
1035
1036/*!
1037 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
1038 *
1039 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
1040 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
1041 * disabled in low power state in other modes.
1042 *
1043 * @return The frequency of MCGFLLCLK.
1044 */
1045uint32_t CLOCK_GetFllFreq(void);
1046
1047/*!
1048 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
1049 *
1050 * This function gets the MCG internal reference clock frequency in Hz based
1051 * on the current MCG register value.
1052 *
1053 * @return The frequency of MCGIRCLK.
1054 */
1055uint32_t CLOCK_GetInternalRefClkFreq(void);
1056
1057/*!
1058 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
1059 *
1060 * This function gets the MCG fixed frequency clock frequency in Hz based
1061 * on the current MCG register value.
1062 *
1063 * @return The frequency of MCGFFCLK.
1064 */
1065uint32_t CLOCK_GetFixedFreqClkFreq(void);
1066
1067/*!
1068 * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
1069 *
1070 * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
1071 * register value.
1072 *
1073 * @return The frequency of MCGPLL0CLK.
1074 */
1075uint32_t CLOCK_GetPll0Freq(void);
1076
1077/*!
1078 * @brief Gets the MCG external PLL frequency.
1079 *
1080 * This function gets the MCG external PLL frequency in Hz.
1081 *
1082 * @return The frequency of the MCG external PLL.
1083 */
1084uint32_t CLOCK_GetExtPllFreq(void);
1085
1086/*!
1087 * @brief Sets the MCG external PLL frequency.
1088 *
1089 * This function sets the MCG external PLL frequency in Hz. The MCG external PLL
1090 * frequency is passed to the MCG driver using this function. Call this
1091 * function after the external PLL frequency is changed. Otherwise, the APIs, which are used to get
1092 * the frequency, may return an incorrect value.
1093 *
1094 * @param The frequency of MCG external PLL.
1095 */
1096void CLOCK_SetExtPllFreq(uint32_t freq);
1097
1098/*@}*/
1099
1100/*! @name MCG clock configuration. */
1101/*@{*/
1102
1103/*!
1104 * @brief Enables or disables the MCG low power.
1105 *
1106 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
1107 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
1108 * PBI modes, enabling low power sets the MCG to BLPI mode.
1109 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
1110 *
1111 * @param enable True to enable MCG low power, false to disable MCG low power.
1112 */
1113static inline void CLOCK_SetLowPowerEnable(bool enable)
1114{
1115 if (enable)
1116 {
1117 MCG->C2 |= MCG_C2_LP_MASK;
1118 }
1119 else
1120 {
1121 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
1122 }
1123}
1124
1125/*!
1126 * @brief Configures the Internal Reference clock (MCGIRCLK).
1127 *
1128 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
1129 * source. If the fast IRC is used, this function sets the fast IRC divider.
1130 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
1131 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
1132 * using the function in these modes it is not allowed.
1133 *
1134 * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
1135 * @param ircs MCGIRCLK clock source, choose fast or slow.
1136 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
1137 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
1138 * the configuration should not be changed. Otherwise, a glitch occurs.
1139 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
1140 */
1141status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
1142
1143/*!
1144 * @brief Selects the MCG external reference clock.
1145 *
1146 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
1147 * and waits for the clock source to be stable. Because the external reference
1148 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
1149 *
1150 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
1151 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
1152 * the configuration should not be changed. Otherwise, a glitch occurs.
1153 * @retval kStatus_Success External reference clock set successfully.
1154 */
1155status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
1156
1157/*!
1158 * @brief Set the FLL external reference clock divider value.
1159 *
1160 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
1161 *
1162 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
1163 */
1164static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
1165{
1166 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
1167}
1168
1169/*!
1170 * @brief Enables the PLL0 in FLL mode.
1171 *
1172 * This function sets us the PLL0 in FLL mode and reconfigures
1173 * the PLL0. Ensure that the PLL reference
1174 * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
1175 * The function CLOCK_CalcPllDiv gets the correct PLL
1176 * divider values.
1177 *
1178 * @param config Pointer to the configuration structure.
1179 */
1180void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1181
1182/*!
1183 * @brief Disables the PLL0 in FLL mode.
1184 *
1185 * This function disables the PLL0 in FLL mode. It should be used together with the
1186 * @ref CLOCK_EnablePll0.
1187 */
1188static inline void CLOCK_DisablePll0(void)
1189{
1190 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK));
1191}
1192
1193/*!
1194 * @brief Calculates the PLL divider setting for a desired output frequency.
1195 *
1196 * This function calculates the correct reference clock divider (\c PRDIV) and
1197 * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
1198 * closest frequency match with the corresponding \c PRDIV/VDIV
1199 * returned from parameters. If a desired frequency is not valid, this function
1200 * returns 0.
1201 *
1202 * @param refFreq PLL reference clock frequency.
1203 * @param desireFreq Desired PLL output frequency.
1204 * @param prdiv PRDIV value to generate desired PLL frequency.
1205 * @param vdiv VDIV value to generate desired PLL frequency.
1206 * @return Closest frequency match that the PLL was able generate.
1207 */
1208uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
1209
1210/*!
1211 * @brief Set the PLL selection.
1212 *
1213 * This function sets the PLL selection between PLL0/PLL1/EXTPLL, and waits for
1214 * change finished.
1215 *
1216 * @param pllcs The PLL to select.
1217 */
1218void CLOCK_SetPllClkSel(mcg_pll_clk_select_t pllcs);
1219
1220/*@}*/
1221
1222/*! @name MCG clock lock monitor functions. */
1223/*@{*/
1224
1225/*!
1226 * @brief Sets the OSC0 clock monitor mode.
1227 *
1228 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1229 *
1230 * @param mode Monitor mode to set.
1231 */
1232void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
1233
1234/*!
1235 * @brief Sets the RTC OSC clock monitor mode.
1236 *
1237 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
1238 *
1239 * @param mode Monitor mode to set.
1240 */
1241void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
1242
1243/*!
1244 * @brief Sets the PLL0 clock monitor mode.
1245 *
1246 * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1247 *
1248 * @param mode Monitor mode to set.
1249 */
1250void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
1251
1252/*!
1253 * @brief Sets the external PLL clock monitor mode.
1254 *
1255 * This function ets the external PLL clock monitor mode. See @ref mcg_monitor_mode_t
1256 * for details.
1257 *
1258 * @param mode Monitor mode to set.
1259 */
1260void CLOCK_SetExtPllMonitorMode(mcg_monitor_mode_t mode);
1261
1262/*!
1263 * @brief Gets the MCG status flags.
1264 *
1265 * This function gets the MCG clock status flags. All status flags are
1266 * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
1267 * check a specific flag, compare the return value with the flag.
1268 *
1269 * Example:
1270 * @code
1271 * To check the clock lost lock status of OSC0 and PLL0.
1272 * uint32_t mcgFlags;
1273 *
1274 * mcgFlags = CLOCK_GetStatusFlags();
1275 *
1276 * if (mcgFlags & kMCG_Osc0LostFlag)
1277 * {
1278 * OSC0 clock lock lost. Do something.
1279 * }
1280 * if (mcgFlags & kMCG_Pll0LostFlag)
1281 * {
1282 * PLL0 clock lock lost. Do something.
1283 * }
1284 * @endcode
1285 *
1286 * @return Logical OR value of the @ref _mcg_status_flags_t.
1287 */
1288uint32_t CLOCK_GetStatusFlags(void);
1289
1290/*!
1291 * @brief Clears the MCG status flags.
1292 *
1293 * This function clears the MCG clock lock lost status. The parameter is a logical
1294 * OR value of the flags to clear. See @ref _mcg_status_flags_t.
1295 *
1296 * Example:
1297 * @code
1298 * To clear the clock lost lock status flags of OSC0 and PLL0.
1299 *
1300 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
1301 * @endcode
1302 *
1303 * @param mask The status flags to clear. This is a logical OR of members of the
1304 * enumeration @ref _mcg_status_flags_t.
1305 */
1306void CLOCK_ClearStatusFlags(uint32_t mask);
1307
1308/*@}*/
1309
1310/*!
1311 * @name OSC configuration
1312 * @{
1313 */
1314
1315/*!
1316 * @brief Configures the OSC external reference clock (OSCERCLK).
1317 *
1318 * This function configures the OSC external reference clock (OSCERCLK).
1319 * This is an example to enable the OSCERCLK in normal and stop modes and also set
1320 * the output divider to 1:
1321 *
1322 @code
1323 oscer_config_t config =
1324 {
1325 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
1326 .erclkDiv = 1U,
1327 };
1328
1329 OSC_SetExtRefClkConfig(OSC, &config);
1330 @endcode
1331 *
1332 * @param base OSC peripheral address.
1333 * @param config Pointer to the configuration structure.
1334 */
1335static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
1336{
1337 uint8_t reg = base->CR;
1338
1339 reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
1340 reg |= config->enableMode;
1341
1342 base->CR = reg;
1343
1344 base->DIV = OSC_DIV_ERPS(config->erclkDiv);
1345}
1346
1347/*!
1348 * @brief Sets the capacitor load configuration for the oscillator.
1349 *
1350 * This function sets the specified capacitors configuration for the oscillator.
1351 * This should be done in the early system level initialization function call
1352 * based on the system configuration.
1353 *
1354 * @param base OSC peripheral address.
1355 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
1356 *
1357 * Example:
1358 @code
1359 To enable only 2 pF and 8 pF capacitor load, please use like this.
1360 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
1361 @endcode
1362 */
1363static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
1364{
1365 uint8_t reg = base->CR;
1366
1367 reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
1368 reg |= capLoad;
1369
1370 base->CR = reg;
1371}
1372
1373/*!
1374 * @brief Initializes the OSC0.
1375 *
1376 * This function initializes the OSC0 according to the board configuration.
1377 *
1378 * @param config Pointer to the OSC0 configuration structure.
1379 */
1380void CLOCK_InitOsc0(osc_config_t const *config);
1381
1382/*!
1383 * @brief Deinitializes the OSC0.
1384 *
1385 * This function deinitializes the OSC0.
1386 */
1387void CLOCK_DeinitOsc0(void);
1388
1389/* @} */
1390
1391/*!
1392 * @name External clock frequency
1393 * @{
1394 */
1395
1396/*!
1397 * @brief Sets the XTAL0 frequency based on board settings.
1398 *
1399 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
1400 */
1401static inline void CLOCK_SetXtal0Freq(uint32_t freq)
1402{
1403 g_xtal0Freq = freq;
1404}
1405
1406/*!
1407 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
1408 *
1409 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
1410 */
1411static inline void CLOCK_SetXtal32Freq(uint32_t freq)
1412{
1413 g_xtal32Freq = freq;
1414}
1415/* @} */
1416
1417/*!
1418 * @name IRCs frequency
1419 * @{
1420 */
1421
1422/*!
1423 * @brief Set the Slow IRC frequency based on the trimmed value
1424 *
1425 * @param freq The Slow IRC frequency input clock frequency in Hz.
1426 */
1427void CLOCK_SetSlowIrcFreq(uint32_t freq);
1428
1429/*!
1430 * @brief Set the Fast IRC frequency based on the trimmed value
1431 *
1432 * @param freq The Fast IRC frequency input clock frequency in Hz.
1433 */
1434void CLOCK_SetFastIrcFreq(uint32_t freq);
1435/* @} */
1436
1437/*!
1438 * @name MCG auto-trim machine.
1439 * @{
1440 */
1441
1442/*!
1443 * @brief Auto trims the internal reference clock.
1444 *
1445 * This function trims the internal reference clock by using the external clock. If
1446 * successful, it returns the kStatus_Success and the frequency after
1447 * trimming is received in the parameter @p actualFreq. If an error occurs,
1448 * the error code is returned.
1449 *
1450 * @param extFreq External clock frequency, which should be a bus clock.
1451 * @param desireFreq Frequency to trim to.
1452 * @param actualFreq Actual frequency after trimming.
1453 * @param atms Trim fast or slow internal reference clock.
1454 * @retval kStatus_Success ATM success.
1455 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
1456 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
1457 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
1458 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
1459 */
1460status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
1461/* @} */
1462
1463/*! @name MCG mode functions. */
1464/*@{*/
1465
1466/*!
1467 * @brief Gets the current MCG mode.
1468 *
1469 * This function checks the MCG registers and determines the current MCG mode.
1470 *
1471 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1472 */
1473mcg_mode_t CLOCK_GetMode(void);
1474
1475/*!
1476 * @brief Sets the MCG to FEI mode.
1477 *
1478 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1479 * from the current mode, this function returns an error.
1480 *
1481 * @param dmx32 DMX32 in FEI mode.
1482 * @param drs The DCO range selection.
1483 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1484 * NULL does not cause a delay.
1485 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1486 * @retval kStatus_Success Switched to the target mode successfully.
1487 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1488 * to a frequency above 32768 Hz.
1489 */
1490status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1491
1492/*!
1493 * @brief Sets the MCG to FEE mode.
1494 *
1495 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1496 * from the current mode, this function returns an error.
1497 *
1498 * @param frdiv FLL reference clock divider setting, FRDIV.
1499 * @param dmx32 DMX32 in FEE mode.
1500 * @param drs The DCO range selection.
1501 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1502 * NULL does not cause a delay.
1503 *
1504 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1505 * @retval kStatus_Success Switched to the target mode successfully.
1506 */
1507status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1508
1509/*!
1510 * @brief Sets the MCG to FBI mode.
1511 *
1512 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1513 * from the current mode, this function returns an error.
1514 *
1515 * @param dmx32 DMX32 in FBI mode.
1516 * @param drs The DCO range selection.
1517 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1518 * is not used in FBI mode, this parameter can be NULL. Passing
1519 * NULL does not cause a delay.
1520 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1521 * @retval kStatus_Success Switched to the target mode successfully.
1522 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1523 * to frequency above 32768 Hz.
1524 */
1525status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1526
1527/*!
1528 * @brief Sets the MCG to FBE mode.
1529 *
1530 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1531 * from the current mode, this function returns an error.
1532 *
1533 * @param frdiv FLL reference clock divider setting, FRDIV.
1534 * @param dmx32 DMX32 in FBE mode.
1535 * @param drs The DCO range selection.
1536 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1537 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1538 * does not cause a delay.
1539 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1540 * @retval kStatus_Success Switched to the target mode successfully.
1541 */
1542status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1543
1544/*!
1545 * @brief Sets the MCG to BLPI mode.
1546 *
1547 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1548 * from the current mode, this function returns an error.
1549 *
1550 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1551 * @retval kStatus_Success Switched to the target mode successfully.
1552 */
1553status_t CLOCK_SetBlpiMode(void);
1554
1555/*!
1556 * @brief Sets the MCG to BLPE mode.
1557 *
1558 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1559 * from the current mode, this function returns an error.
1560 *
1561 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1562 * @retval kStatus_Success Switched to the target mode successfully.
1563 */
1564status_t CLOCK_SetBlpeMode(void);
1565
1566/*!
1567 * @brief Sets the MCG to PBE mode.
1568 *
1569 * This function sets the MCG to PBE mode. If setting to PBE mode fails
1570 * from the current mode, this function returns an error.
1571 *
1572 * @param pllcs The PLL selection, PLLCS.
1573 * @param config Pointer to the PLL configuration.
1574 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1575 * @retval kStatus_Success Switched to the target mode successfully.
1576 *
1577 * @note
1578 * 1. The parameter \c pllcs selects the PLL. For platforms with
1579 * only one PLL, the parameter pllcs is kept for interface compatibility.
1580 * 2. The parameter \c config is the PLL configuration structure. On some
1581 * platforms, it is possible to choose the external PLL directly, which renders the
1582 * configuration structure not necessary. In this case, pass in NULL.
1583 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
1584 */
1585status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1586
1587/*!
1588 * @brief Sets the MCG to PEE mode.
1589 *
1590 * This function sets the MCG to PEE mode.
1591 *
1592 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1593 * @retval kStatus_Success Switched to the target mode successfully.
1594 *
1595 * @note This function only changes the CLKS to use the PLL/FLL output. If the
1596 * PRDIV/VDIV are different than in the PBE mode, set them up
1597 * in PBE mode and wait. When the clock is stable, switch to PEE mode.
1598 */
1599status_t CLOCK_SetPeeMode(void);
1600
1601/*!
1602 * @brief Switches the MCG to FBE mode from the external mode.
1603 *
1604 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1605 * The external clock is used as the system clock source and PLL is disabled. However,
1606 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1607 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1608 *
1609 * @code
1610 * CLOCK_ExternalModeToFbeModeQuick();
1611 * CLOCK_SetFeiMode(...);
1612 * @endcode
1613 *
1614 * @retval kStatus_Success Switched successfully.
1615 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1616 */
1617status_t CLOCK_ExternalModeToFbeModeQuick(void);
1618
1619/*!
1620 * @brief Switches the MCG to FBI mode from internal modes.
1621 *
1622 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1623 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1624 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1625 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1626 *
1627 * @code
1628 * CLOCK_InternalModeToFbiModeQuick();
1629 * CLOCK_SetFeeMode(...);
1630 * @endcode
1631 *
1632 * @retval kStatus_Success Switched successfully.
1633 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1634 */
1635status_t CLOCK_InternalModeToFbiModeQuick(void);
1636
1637/*!
1638 * @brief Sets the MCG to FEI mode during system boot up.
1639 *
1640 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1641 * set up MCG during system boot up.
1642 *
1643 * @param dmx32 DMX32 in FEI mode.
1644 * @param drs The DCO range selection.
1645 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1646 *
1647 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1648 * @retval kStatus_Success Switched to the target mode successfully.
1649 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1650 * to frequency above 32768 Hz.
1651 */
1652status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1653
1654/*!
1655 * @brief Sets the MCG to FEE mode during system bootup.
1656 *
1657 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1658 * set up the MCG during system boot up.
1659 *
1660 * @param oscsel OSC clock select, OSCSEL.
1661 * @param frdiv FLL reference clock divider setting, FRDIV.
1662 * @param dmx32 DMX32 in FEE mode.
1663 * @param drs The DCO range selection.
1664 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1665 *
1666 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1667 * @retval kStatus_Success Switched to the target mode successfully.
1668 */
1669status_t CLOCK_BootToFeeMode(
1670 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1671
1672/*!
1673 * @brief Sets the MCG to BLPI mode during system boot up.
1674 *
1675 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1676 * set up the MCG during system boot up.
1677 *
1678 * @param fcrdiv Fast IRC divider, FCRDIV.
1679 * @param ircs The internal reference clock to select, IRCS.
1680 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
1681 *
1682 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1683 * @retval kStatus_Success Switched to the target mode successfully.
1684 */
1685status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1686
1687/*!
1688 * @brief Sets the MCG to BLPE mode during system boot up.
1689 *
1690 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1691 * set up the MCG during system boot up.
1692 *
1693 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1694 *
1695 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1696 * @retval kStatus_Success Switched to the target mode successfully.
1697 */
1698status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1699
1700/*!
1701 * @brief Sets the MCG to PEE mode during system boot up.
1702 *
1703 * This function sets the MCG to PEE mode from reset mode. It can also be used to
1704 * set up the MCG during system boot up.
1705 *
1706 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1707 * @param pllcs The PLL selection, PLLCS.
1708 * @param config Pointer to the PLL configuration.
1709 *
1710 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1711 * @retval kStatus_Success Switched to the target mode successfully.
1712 */
1713status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1714
1715/*!
1716 * @brief Sets the MCG to a target mode.
1717 *
1718 * This function sets MCG to a target mode defined by the configuration
1719 * structure. If switching to the target mode fails, this function
1720 * chooses the correct path.
1721 *
1722 * @param config Pointer to the target MCG mode configuration structure.
1723 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
1724 *
1725 * @note If the external clock is used in the target mode, ensure that it is
1726 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1727 * function.
1728 */
1729status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1730
1731/*@}*/
1732
1733#if defined(__cplusplus)
1734}
1735#endif /* __cplusplus */
1736
1737/*! @} */
1738
1739#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 20:17:15 +0100