aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc')
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc/MK26FN2M0xxx18_flash.ld225
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc/MK26FN2M0xxx18_ram.ld216
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc/startup_MK26F18.S1024
3 files changed, 1465 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc/MK26FN2M0xxx18_flash.ld b/lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc/MK26FN2M0xxx18_flash.ld
new file mode 100644
index 000000000..2512fe54f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc/MK26FN2M0xxx18_flash.ld
@@ -0,0 +1,225 @@
1/*
2** ###################################################################
3** Processors: MK26FN2M0CAC18
4** MK26FN2M0VLQ18
5** MK26FN2M0VMD18
6** MK26FN2M0VMI18
7**
8** Compiler: GNU C Compiler
9** Reference manual: MK26P169M180SF5RM, Rev. 1, Mar 2015
10** Version: rev. 2.0, 2015-03-25
11** Build: b190916
12**
13** Abstract:
14** Linker file for the GNU C Compiler
15**
16** Copyright 2016 Freescale Semiconductor, Inc.
17** Copyright 2016-2019 NXP
18** All rights reserved.
19**
20** SPDX-License-Identifier: BSD-3-Clause
21**
22** http: www.nxp.com
23** mail: [email protected]
24**
25** ###################################################################
26*/
27
28/* Entry Point */
29ENTRY(Reset_Handler)
30
31HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
32STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
33
34/* Specify the memory areas */
35MEMORY
36{
37 m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
38 m_flash_config (RX) : ORIGIN = 0x00000400, LENGTH = 0x00000010
39 m_text (RX) : ORIGIN = 0x00000410, LENGTH = 0x001FFBF0
40 m_data (RW) : ORIGIN = 0x1FFF0000, LENGTH = 0x00010000
41 m_data_2 (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000
42}
43
44/* Define output sections */
45SECTIONS
46{
47 /* The startup code goes first into internal flash */
48 .interrupts :
49 {
50 . = ALIGN(4);
51 KEEP(*(.isr_vector)) /* Startup code */
52 . = ALIGN(4);
53 } > m_interrupts
54
55 .flash_config :
56 {
57 . = ALIGN(4);
58 KEEP(*(.FlashConfig)) /* Flash Configuration Field (FCF) */
59 . = ALIGN(4);
60 } > m_flash_config
61
62 /* The program code and other data goes into internal flash */
63 .text :
64 {
65 . = ALIGN(4);
66 *(.text) /* .text sections (code) */
67 *(.text*) /* .text* sections (code) */
68 *(.rodata) /* .rodata sections (constants, strings, etc.) */
69 *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
70 *(.glue_7) /* glue arm to thumb code */
71 *(.glue_7t) /* glue thumb to arm code */
72 *(.eh_frame)
73 KEEP (*(.init))
74 KEEP (*(.fini))
75 . = ALIGN(4);
76 } > m_text
77
78 .ARM.extab :
79 {
80 *(.ARM.extab* .gnu.linkonce.armextab.*)
81 } > m_text
82
83 .ARM :
84 {
85 __exidx_start = .;
86 *(.ARM.exidx*)
87 __exidx_end = .;
88 } > m_text
89
90 .ctors :
91 {
92 __CTOR_LIST__ = .;
93 /* gcc uses crtbegin.o to find the start of
94 the constructors, so we make sure it is
95 first. Because this is a wildcard, it
96 doesn't matter if the user does not
97 actually link against crtbegin.o; the
98 linker won't look for a file to match a
99 wildcard. The wildcard also means that it
100 doesn't matter which directory crtbegin.o
101 is in. */
102 KEEP (*crtbegin.o(.ctors))
103 KEEP (*crtbegin?.o(.ctors))
104 /* We don't want to include the .ctor section from
105 from the crtend.o file until after the sorted ctors.
106 The .ctor section from the crtend file contains the
107 end of ctors marker and it must be last */
108 KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
109 KEEP (*(SORT(.ctors.*)))
110 KEEP (*(.ctors))
111 __CTOR_END__ = .;
112 } > m_text
113
114 .dtors :
115 {
116 __DTOR_LIST__ = .;
117 KEEP (*crtbegin.o(.dtors))
118 KEEP (*crtbegin?.o(.dtors))
119 KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
120 KEEP (*(SORT(.dtors.*)))
121 KEEP (*(.dtors))
122 __DTOR_END__ = .;
123 } > m_text
124
125 .preinit_array :
126 {
127 PROVIDE_HIDDEN (__preinit_array_start = .);
128 KEEP (*(.preinit_array*))
129 PROVIDE_HIDDEN (__preinit_array_end = .);
130 } > m_text
131
132 .init_array :
133 {
134 PROVIDE_HIDDEN (__init_array_start = .);
135 KEEP (*(SORT(.init_array.*)))
136 KEEP (*(.init_array*))
137 PROVIDE_HIDDEN (__init_array_end = .);
138 } > m_text
139
140 .fini_array :
141 {
142 PROVIDE_HIDDEN (__fini_array_start = .);
143 KEEP (*(SORT(.fini_array.*)))
144 KEEP (*(.fini_array*))
145 PROVIDE_HIDDEN (__fini_array_end = .);
146 } > m_text
147
148 __etext = .; /* define a global symbol at end of code */
149 __DATA_ROM = .; /* Symbol is used by startup for data initialization */
150
151 .data : AT(__DATA_ROM)
152 {
153 . = ALIGN(4);
154 __DATA_RAM = .;
155 __data_start__ = .; /* create a global symbol at data start */
156 *(.data) /* .data sections */
157 *(.data*) /* .data* sections */
158 KEEP(*(.jcr*))
159 . = ALIGN(4);
160 __data_end__ = .; /* define a global symbol at data end */
161 } > m_data
162
163 __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
164 .ncache.init : AT(__NDATA_ROM)
165 {
166 __noncachedata_start__ = .; /* create a global symbol at ncache data start */
167 *(NonCacheable.init)
168 . = ALIGN(4);
169 __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
170 } > m_data
171
172 . = __noncachedata_init_end__;
173 .ncache :
174 {
175 *(NonCacheable)
176 . = ALIGN(4);
177 __noncachedata_end__ = .; /* define a global symbol at ncache data end */
178 } > m_data
179
180 __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
181 text_end = ORIGIN(m_text) + LENGTH(m_text);
182 ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
183
184 /* Uninitialized data section */
185 .bss :
186 {
187 /* This is used by the startup in order to initialize the .bss section */
188 . = ALIGN(4);
189 __START_BSS = .;
190 __bss_start__ = .;
191 *(.bss)
192 *(.bss*)
193 *(COMMON)
194 . = ALIGN(4);
195 __bss_end__ = .;
196 __END_BSS = .;
197 } > m_data
198
199 .heap :
200 {
201 . = ALIGN(8);
202 __end__ = .;
203 PROVIDE(end = .);
204 __HeapBase = .;
205 . += HEAP_SIZE;
206 __HeapLimit = .;
207 __heap_limit = .; /* Add for _sbrk */
208 } > m_data_2
209
210 .stack :
211 {
212 . = ALIGN(8);
213 . += STACK_SIZE;
214 } > m_data_2
215
216 /* Initializes stack on the end of block */
217 __StackTop = ORIGIN(m_data_2) + LENGTH(m_data_2);
218 __StackLimit = __StackTop - STACK_SIZE;
219 PROVIDE(__stack = __StackTop);
220
221 .ARM.attributes 0 : { *(.ARM.attributes) }
222
223 ASSERT(__StackLimit >= __HeapLimit, "region m_data_2 overflowed with stack and heap")
224}
225
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc/MK26FN2M0xxx18_ram.ld b/lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc/MK26FN2M0xxx18_ram.ld
new file mode 100644
index 000000000..90a2b1bf2
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc/MK26FN2M0xxx18_ram.ld
@@ -0,0 +1,216 @@
1/*
2** ###################################################################
3** Processors: MK26FN2M0CAC18
4** MK26FN2M0VLQ18
5** MK26FN2M0VMD18
6** MK26FN2M0VMI18
7**
8** Compiler: GNU C Compiler
9** Reference manual: MK26P169M180SF5RM, Rev. 1, Mar 2015
10** Version: rev. 2.0, 2015-03-25
11** Build: b190916
12**
13** Abstract:
14** Linker file for the GNU C Compiler
15**
16** Copyright 2016 Freescale Semiconductor, Inc.
17** Copyright 2016-2019 NXP
18** All rights reserved.
19**
20** SPDX-License-Identifier: BSD-3-Clause
21**
22** http: www.nxp.com
23** mail: [email protected]
24**
25** ###################################################################
26*/
27
28/* Entry Point */
29ENTRY(Reset_Handler)
30
31HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
32STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0400;
33
34/* Specify the memory areas */
35MEMORY
36{
37 m_interrupts (RX) : ORIGIN = 0x1FFF0000, LENGTH = 0x00000400
38 m_text (RX) : ORIGIN = 0x1FFF0400, LENGTH = 0x0000FC00
39 m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00030000
40}
41
42/* Define output sections */
43SECTIONS
44{
45 /* The startup code goes first into internal RAM */
46 .interrupts :
47 {
48 . = ALIGN(4);
49 KEEP(*(.isr_vector)) /* Startup code */
50 . = ALIGN(4);
51 } > m_interrupts
52
53 /* The program code and other data goes into internal RAM */
54 .text :
55 {
56 . = ALIGN(4);
57 *(.text) /* .text sections (code) */
58 *(.text*) /* .text* sections (code) */
59 *(.rodata) /* .rodata sections (constants, strings, etc.) */
60 *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
61 *(.glue_7) /* glue arm to thumb code */
62 *(.glue_7t) /* glue thumb to arm code */
63 *(.eh_frame)
64 KEEP (*(.init))
65 KEEP (*(.fini))
66 . = ALIGN(4);
67 } > m_text
68
69 .ARM.extab :
70 {
71 *(.ARM.extab* .gnu.linkonce.armextab.*)
72 } > m_text
73
74 .ARM :
75 {
76 __exidx_start = .;
77 *(.ARM.exidx*)
78 __exidx_end = .;
79 } > m_text
80
81 .ctors :
82 {
83 __CTOR_LIST__ = .;
84 /* gcc uses crtbegin.o to find the start of
85 the constructors, so we make sure it is
86 first. Because this is a wildcard, it
87 doesn't matter if the user does not
88 actually link against crtbegin.o; the
89 linker won't look for a file to match a
90 wildcard. The wildcard also means that it
91 doesn't matter which directory crtbegin.o
92 is in. */
93 KEEP (*crtbegin.o(.ctors))
94 KEEP (*crtbegin?.o(.ctors))
95 /* We don't want to include the .ctor section from
96 from the crtend.o file until after the sorted ctors.
97 The .ctor section from the crtend file contains the
98 end of ctors marker and it must be last */
99 KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
100 KEEP (*(SORT(.ctors.*)))
101 KEEP (*(.ctors))
102 __CTOR_END__ = .;
103 } > m_text
104
105 .dtors :
106 {
107 __DTOR_LIST__ = .;
108 KEEP (*crtbegin.o(.dtors))
109 KEEP (*crtbegin?.o(.dtors))
110 KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
111 KEEP (*(SORT(.dtors.*)))
112 KEEP (*(.dtors))
113 __DTOR_END__ = .;
114 } > m_text
115
116 .preinit_array :
117 {
118 PROVIDE_HIDDEN (__preinit_array_start = .);
119 KEEP (*(.preinit_array*))
120 PROVIDE_HIDDEN (__preinit_array_end = .);
121 } > m_text
122
123 .init_array :
124 {
125 PROVIDE_HIDDEN (__init_array_start = .);
126 KEEP (*(SORT(.init_array.*)))
127 KEEP (*(.init_array*))
128 PROVIDE_HIDDEN (__init_array_end = .);
129 } > m_text
130
131 .fini_array :
132 {
133 PROVIDE_HIDDEN (__fini_array_start = .);
134 KEEP (*(SORT(.fini_array.*)))
135 KEEP (*(.fini_array*))
136 PROVIDE_HIDDEN (__fini_array_end = .);
137 } > m_text
138
139 __etext = .; /* define a global symbol at end of code */
140 __DATA_ROM = .; /* Symbol is used by startup for data initialization */
141
142 .data : AT(__DATA_ROM)
143 {
144 . = ALIGN(4);
145 __DATA_RAM = .;
146 __data_start__ = .; /* create a global symbol at data start */
147 *(.data) /* .data sections */
148 *(.data*) /* .data* sections */
149 KEEP(*(.jcr*))
150 . = ALIGN(4);
151 __data_end__ = .; /* define a global symbol at data end */
152 } > m_data
153
154 __NDATA_ROM = __DATA_ROM + (__data_end__ - __data_start__);
155 .ncache.init : AT(__NDATA_ROM)
156 {
157 __noncachedata_start__ = .; /* create a global symbol at ncache data start */
158 *(NonCacheable.init)
159 . = ALIGN(4);
160 __noncachedata_init_end__ = .; /* create a global symbol at initialized ncache data end */
161 } > m_data
162
163 . = __noncachedata_init_end__;
164 .ncache :
165 {
166 *(NonCacheable)
167 . = ALIGN(4);
168 __noncachedata_end__ = .; /* define a global symbol at ncache data end */
169 } > m_data
170
171 __DATA_END = __NDATA_ROM + (__noncachedata_init_end__ - __noncachedata_start__);
172 text_end = ORIGIN(m_text) + LENGTH(m_text);
173 ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
174
175 /* Uninitialized data section */
176 .bss :
177 {
178 /* This is used by the startup in order to initialize the .bss section */
179 . = ALIGN(4);
180 __START_BSS = .;
181 __bss_start__ = .;
182 *(.bss)
183 *(.bss*)
184 *(COMMON)
185 . = ALIGN(4);
186 __bss_end__ = .;
187 __END_BSS = .;
188 } > m_data
189
190 .heap :
191 {
192 . = ALIGN(8);
193 __end__ = .;
194 PROVIDE(end = .);
195 __HeapBase = .;
196 . += HEAP_SIZE;
197 __HeapLimit = .;
198 __heap_limit = .; /* Add for _sbrk */
199 } > m_data
200
201 .stack :
202 {
203 . = ALIGN(8);
204 . += STACK_SIZE;
205 } > m_data
206
207 /* Initializes stack on the end of block */
208 __StackTop = ORIGIN(m_data) + LENGTH(m_data);
209 __StackLimit = __StackTop - STACK_SIZE;
210 PROVIDE(__stack = __StackTop);
211
212 .ARM.attributes 0 : { *(.ARM.attributes) }
213
214 ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
215}
216
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc/startup_MK26F18.S b/lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc/startup_MK26F18.S
new file mode 100644
index 000000000..b3dea1748
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MK26F18/gcc/startup_MK26F18.S
@@ -0,0 +1,1024 @@
1/* ------------------------------------------------------------------------- */
2/* @file: startup_MK26F18.s */
3/* @purpose: CMSIS Cortex-M4 Core Device Startup File */
4/* MK26F18 */
5/* @version: 2.0 */
6/* @date: 2015-3-25 */
7/* @build: b190918 */
8/* ------------------------------------------------------------------------- */
9/* */
10/* Copyright 1997-2016 Freescale Semiconductor, Inc. */
11/* Copyright 2016-2019 NXP */
12/* All rights reserved. */
13/* */
14/* SPDX-License-Identifier: BSD-3-Clause */
15/*****************************************************************************/
16/* Version: GCC for ARM Embedded Processors */
17/*****************************************************************************/
18 .syntax unified
19 .arch armv7-m
20
21 .section .isr_vector, "a"
22 .align 2
23 .globl __isr_vector
24__isr_vector:
25 .long __StackTop /* Top of Stack */
26 .long Reset_Handler /* Reset Handler */
27 .long NMI_Handler /* NMI Handler*/
28 .long HardFault_Handler /* Hard Fault Handler*/
29 .long MemManage_Handler /* MPU Fault Handler*/
30 .long BusFault_Handler /* Bus Fault Handler*/
31 .long UsageFault_Handler /* Usage Fault Handler*/
32 .long 0 /* Reserved*/
33 .long 0 /* Reserved*/
34 .long 0 /* Reserved*/
35 .long 0 /* Reserved*/
36 .long SVC_Handler /* SVCall Handler*/
37 .long DebugMon_Handler /* Debug Monitor Handler*/
38 .long 0 /* Reserved*/
39 .long PendSV_Handler /* PendSV Handler*/
40 .long SysTick_Handler /* SysTick Handler*/
41
42 /* External Interrupts*/
43 .long DMA0_DMA16_IRQHandler /* DMA Channel 0, 16 Transfer Complete*/
44 .long DMA1_DMA17_IRQHandler /* DMA Channel 1, 17 Transfer Complete*/
45 .long DMA2_DMA18_IRQHandler /* DMA Channel 2, 18 Transfer Complete*/
46 .long DMA3_DMA19_IRQHandler /* DMA Channel 3, 19 Transfer Complete*/
47 .long DMA4_DMA20_IRQHandler /* DMA Channel 4, 20 Transfer Complete*/
48 .long DMA5_DMA21_IRQHandler /* DMA Channel 5, 21 Transfer Complete*/
49 .long DMA6_DMA22_IRQHandler /* DMA Channel 6, 22 Transfer Complete*/
50 .long DMA7_DMA23_IRQHandler /* DMA Channel 7, 23 Transfer Complete*/
51 .long DMA8_DMA24_IRQHandler /* DMA Channel 8, 24 Transfer Complete*/
52 .long DMA9_DMA25_IRQHandler /* DMA Channel 9, 25 Transfer Complete*/
53 .long DMA10_DMA26_IRQHandler /* DMA Channel 10, 26 Transfer Complete*/
54 .long DMA11_DMA27_IRQHandler /* DMA Channel 11, 27 Transfer Complete*/
55 .long DMA12_DMA28_IRQHandler /* DMA Channel 12, 28 Transfer Complete*/
56 .long DMA13_DMA29_IRQHandler /* DMA Channel 13, 29 Transfer Complete*/
57 .long DMA14_DMA30_IRQHandler /* DMA Channel 14, 30 Transfer Complete*/
58 .long DMA15_DMA31_IRQHandler /* DMA Channel 15, 31 Transfer Complete*/
59 .long DMA_Error_IRQHandler /* DMA Error Interrupt*/
60 .long MCM_IRQHandler /* Normal Interrupt*/
61 .long FTFE_IRQHandler /* FTFE Command complete interrupt*/
62 .long Read_Collision_IRQHandler /* Read Collision Interrupt*/
63 .long LVD_LVW_IRQHandler /* Low Voltage Detect, Low Voltage Warning*/
64 .long LLWU_IRQHandler /* Low Leakage Wakeup Unit*/
65 .long WDOG_EWM_IRQHandler /* WDOG Interrupt*/
66 .long RNG_IRQHandler /* RNG Interrupt*/
67 .long I2C0_IRQHandler /* I2C0 interrupt*/
68 .long I2C1_IRQHandler /* I2C1 interrupt*/
69 .long SPI0_IRQHandler /* SPI0 Interrupt*/
70 .long SPI1_IRQHandler /* SPI1 Interrupt*/
71 .long I2S0_Tx_IRQHandler /* I2S0 transmit interrupt*/
72 .long I2S0_Rx_IRQHandler /* I2S0 receive interrupt*/
73 .long Reserved46_IRQHandler /* Reserved interrupt 46*/
74 .long UART0_RX_TX_IRQHandler /* UART0 Receive/Transmit interrupt*/
75 .long UART0_ERR_IRQHandler /* UART0 Error interrupt*/
76 .long UART1_RX_TX_IRQHandler /* UART1 Receive/Transmit interrupt*/
77 .long UART1_ERR_IRQHandler /* UART1 Error interrupt*/
78 .long UART2_RX_TX_IRQHandler /* UART2 Receive/Transmit interrupt*/
79 .long UART2_ERR_IRQHandler /* UART2 Error interrupt*/
80 .long UART3_RX_TX_IRQHandler /* UART3 Receive/Transmit interrupt*/
81 .long UART3_ERR_IRQHandler /* UART3 Error interrupt*/
82 .long ADC0_IRQHandler /* ADC0 interrupt*/
83 .long CMP0_IRQHandler /* CMP0 interrupt*/
84 .long CMP1_IRQHandler /* CMP1 interrupt*/
85 .long FTM0_IRQHandler /* FTM0 fault, overflow and channels interrupt*/
86 .long FTM1_IRQHandler /* FTM1 fault, overflow and channels interrupt*/
87 .long FTM2_IRQHandler /* FTM2 fault, overflow and channels interrupt*/
88 .long CMT_IRQHandler /* CMT interrupt*/
89 .long RTC_IRQHandler /* RTC interrupt*/
90 .long RTC_Seconds_IRQHandler /* RTC seconds interrupt*/
91 .long PIT0_IRQHandler /* PIT timer channel 0 interrupt*/
92 .long PIT1_IRQHandler /* PIT timer channel 1 interrupt*/
93 .long PIT2_IRQHandler /* PIT timer channel 2 interrupt*/
94 .long PIT3_IRQHandler /* PIT timer channel 3 interrupt*/
95 .long PDB0_IRQHandler /* PDB0 Interrupt*/
96 .long USB0_IRQHandler /* USB0 interrupt*/
97 .long USBDCD_IRQHandler /* USBDCD Interrupt*/
98 .long Reserved71_IRQHandler /* Reserved interrupt 71*/
99 .long DAC0_IRQHandler /* DAC0 interrupt*/
100 .long MCG_IRQHandler /* MCG Interrupt*/
101 .long LPTMR0_IRQHandler /* LPTimer interrupt*/
102 .long PORTA_IRQHandler /* Port A interrupt*/
103 .long PORTB_IRQHandler /* Port B interrupt*/
104 .long PORTC_IRQHandler /* Port C interrupt*/
105 .long PORTD_IRQHandler /* Port D interrupt*/
106 .long PORTE_IRQHandler /* Port E interrupt*/
107 .long SWI_IRQHandler /* Software interrupt*/
108 .long SPI2_IRQHandler /* SPI2 Interrupt*/
109 .long UART4_RX_TX_IRQHandler /* UART4 Receive/Transmit interrupt*/
110 .long UART4_ERR_IRQHandler /* UART4 Error interrupt*/
111 .long Reserved84_IRQHandler /* Reserved interrupt 84*/
112 .long Reserved85_IRQHandler /* Reserved interrupt 85*/
113 .long CMP2_IRQHandler /* CMP2 interrupt*/
114 .long FTM3_IRQHandler /* FTM3 fault, overflow and channels interrupt*/
115 .long DAC1_IRQHandler /* DAC1 interrupt*/
116 .long ADC1_IRQHandler /* ADC1 interrupt*/
117 .long I2C2_IRQHandler /* I2C2 interrupt*/
118 .long CAN0_ORed_Message_buffer_IRQHandler /* CAN0 OR'd message buffers interrupt*/
119 .long CAN0_Bus_Off_IRQHandler /* CAN0 bus off interrupt*/
120 .long CAN0_Error_IRQHandler /* CAN0 error interrupt*/
121 .long CAN0_Tx_Warning_IRQHandler /* CAN0 Tx warning interrupt*/
122 .long CAN0_Rx_Warning_IRQHandler /* CAN0 Rx warning interrupt*/
123 .long CAN0_Wake_Up_IRQHandler /* CAN0 wake up interrupt*/
124 .long SDHC_IRQHandler /* SDHC interrupt*/
125 .long Reserved98_IRQHandler /* Reserved Interrupt 98*/
126 .long Reserved99_IRQHandler /* Reserved Interrupt 99*/
127 .long Reserved100_IRQHandler /* Reserved Interrupt 100*/
128 .long Reserved101_IRQHandler /* Reserved Interrupt 101*/
129 .long LPUART0_IRQHandler /* LPUART0 status/error interrupt*/
130 .long TSI0_IRQHandler /* TSI0 interrupt*/
131 .long TPM1_IRQHandler /* TPM1 fault, overflow and channels interrupt*/
132 .long TPM2_IRQHandler /* TPM2 fault, overflow and channels interrupt*/
133 .long USBHSDCD_IRQHandler /* USBHSDCD, USBHS Phy Interrupt*/
134 .long I2C3_IRQHandler /* I2C3 interrupt*/
135 .long CMP3_IRQHandler /* CMP3 interrupt*/
136 .long USBHS_IRQHandler /* USB high speed OTG interrupt*/
137 .long CAN1_ORed_Message_buffer_IRQHandler /* CAN1 OR'd message buffers interrupt*/
138 .long CAN1_Bus_Off_IRQHandler /* CAN1 bus off interrupt*/
139 .long CAN1_Error_IRQHandler /* CAN1 error interrupt*/
140 .long CAN1_Tx_Warning_IRQHandler /* CAN1 Tx warning interrupt*/
141 .long CAN1_Rx_Warning_IRQHandler /* CAN1 Rx warning interrupt*/
142 .long CAN1_Wake_Up_IRQHandler /* CAN1 wake up interrupt*/
143 .long DefaultISR /* 116*/
144 .long DefaultISR /* 117*/
145 .long DefaultISR /* 118*/
146 .long DefaultISR /* 119*/
147 .long DefaultISR /* 120*/
148 .long DefaultISR /* 121*/
149 .long DefaultISR /* 122*/
150 .long DefaultISR /* 123*/
151 .long DefaultISR /* 124*/
152 .long DefaultISR /* 125*/
153 .long DefaultISR /* 126*/
154 .long DefaultISR /* 127*/
155 .long DefaultISR /* 128*/
156 .long DefaultISR /* 129*/
157 .long DefaultISR /* 130*/
158 .long DefaultISR /* 131*/
159 .long DefaultISR /* 132*/
160 .long DefaultISR /* 133*/
161 .long DefaultISR /* 134*/
162 .long DefaultISR /* 135*/
163 .long DefaultISR /* 136*/
164 .long DefaultISR /* 137*/
165 .long DefaultISR /* 138*/
166 .long DefaultISR /* 139*/
167 .long DefaultISR /* 140*/
168 .long DefaultISR /* 141*/
169 .long DefaultISR /* 142*/
170 .long DefaultISR /* 143*/
171 .long DefaultISR /* 144*/
172 .long DefaultISR /* 145*/
173 .long DefaultISR /* 146*/
174 .long DefaultISR /* 147*/
175 .long DefaultISR /* 148*/
176 .long DefaultISR /* 149*/
177 .long DefaultISR /* 150*/
178 .long DefaultISR /* 151*/
179 .long DefaultISR /* 152*/
180 .long DefaultISR /* 153*/
181 .long DefaultISR /* 154*/
182 .long DefaultISR /* 155*/
183 .long DefaultISR /* 156*/
184 .long DefaultISR /* 157*/
185 .long DefaultISR /* 158*/
186 .long DefaultISR /* 159*/
187 .long DefaultISR /* 160*/
188 .long DefaultISR /* 161*/
189 .long DefaultISR /* 162*/
190 .long DefaultISR /* 163*/
191 .long DefaultISR /* 164*/
192 .long DefaultISR /* 165*/
193 .long DefaultISR /* 166*/
194 .long DefaultISR /* 167*/
195 .long DefaultISR /* 168*/
196 .long DefaultISR /* 169*/
197 .long DefaultISR /* 170*/
198 .long DefaultISR /* 171*/
199 .long DefaultISR /* 172*/
200 .long DefaultISR /* 173*/
201 .long DefaultISR /* 174*/
202 .long DefaultISR /* 175*/
203 .long DefaultISR /* 176*/
204 .long DefaultISR /* 177*/
205 .long DefaultISR /* 178*/
206 .long DefaultISR /* 179*/
207 .long DefaultISR /* 180*/
208 .long DefaultISR /* 181*/
209 .long DefaultISR /* 182*/
210 .long DefaultISR /* 183*/
211 .long DefaultISR /* 184*/
212 .long DefaultISR /* 185*/
213 .long DefaultISR /* 186*/
214 .long DefaultISR /* 187*/
215 .long DefaultISR /* 188*/
216 .long DefaultISR /* 189*/
217 .long DefaultISR /* 190*/
218 .long DefaultISR /* 191*/
219 .long DefaultISR /* 192*/
220 .long DefaultISR /* 193*/
221 .long DefaultISR /* 194*/
222 .long DefaultISR /* 195*/
223 .long DefaultISR /* 196*/
224 .long DefaultISR /* 197*/
225 .long DefaultISR /* 198*/
226 .long DefaultISR /* 199*/
227 .long DefaultISR /* 200*/
228 .long DefaultISR /* 201*/
229 .long DefaultISR /* 202*/
230 .long DefaultISR /* 203*/
231 .long DefaultISR /* 204*/
232 .long DefaultISR /* 205*/
233 .long DefaultISR /* 206*/
234 .long DefaultISR /* 207*/
235 .long DefaultISR /* 208*/
236 .long DefaultISR /* 209*/
237 .long DefaultISR /* 210*/
238 .long DefaultISR /* 211*/
239 .long DefaultISR /* 212*/
240 .long DefaultISR /* 213*/
241 .long DefaultISR /* 214*/
242 .long DefaultISR /* 215*/
243 .long DefaultISR /* 216*/
244 .long DefaultISR /* 217*/
245 .long DefaultISR /* 218*/
246 .long DefaultISR /* 219*/
247 .long DefaultISR /* 220*/
248 .long DefaultISR /* 221*/
249 .long DefaultISR /* 222*/
250 .long DefaultISR /* 223*/
251 .long DefaultISR /* 224*/
252 .long DefaultISR /* 225*/
253 .long DefaultISR /* 226*/
254 .long DefaultISR /* 227*/
255 .long DefaultISR /* 228*/
256 .long DefaultISR /* 229*/
257 .long DefaultISR /* 230*/
258 .long DefaultISR /* 231*/
259 .long DefaultISR /* 232*/
260 .long DefaultISR /* 233*/
261 .long DefaultISR /* 234*/
262 .long DefaultISR /* 235*/
263 .long DefaultISR /* 236*/
264 .long DefaultISR /* 237*/
265 .long DefaultISR /* 238*/
266 .long DefaultISR /* 239*/
267 .long DefaultISR /* 240*/
268 .long DefaultISR /* 241*/
269 .long DefaultISR /* 242*/
270 .long DefaultISR /* 243*/
271 .long DefaultISR /* 244*/
272 .long DefaultISR /* 245*/
273 .long DefaultISR /* 246*/
274 .long DefaultISR /* 247*/
275 .long DefaultISR /* 248*/
276 .long DefaultISR /* 249*/
277 .long DefaultISR /* 250*/
278 .long DefaultISR /* 251*/
279 .long DefaultISR /* 252*/
280 .long DefaultISR /* 253*/
281 .long DefaultISR /* 254*/
282 .long 0xFFFFFFFF /* Reserved for user TRIM value*/
283
284 .size __isr_vector, . - __isr_vector
285
286/* Flash Configuration */
287 .section .FlashConfig, "a"
288 .long 0xFFFFFFFF
289 .long 0xFFFFFFFF
290 .long 0xFFFFFFFF
291 .long 0xFFFFFFFE
292
293 .text
294 .thumb
295
296/* Reset Handler */
297
298 .thumb_func
299 .align 2
300 .globl Reset_Handler
301 .weak Reset_Handler
302 .type Reset_Handler, %function
303Reset_Handler:
304 cpsid i /* Mask interrupts */
305 .equ VTOR, 0xE000ED08
306 ldr r0, =VTOR
307 ldr r1, =__isr_vector
308 str r1, [r0]
309 ldr r2, [r1]
310 msr msp, r2
311#ifndef __NO_SYSTEM_INIT
312 ldr r0,=SystemInit
313 blx r0
314#endif
315/* Loop to copy data from read only memory to RAM. The ranges
316 * of copy from/to are specified by following symbols evaluated in
317 * linker script.
318 * __etext: End of code section, i.e., begin of data sections to copy from.
319 * __data_start__/__data_end__: RAM address range that data should be
320 * __noncachedata_start__/__noncachedata_end__ : none cachable region
321 * copied to. Both must be aligned to 4 bytes boundary. */
322
323 ldr r1, =__etext
324 ldr r2, =__data_start__
325 ldr r3, =__data_end__
326
327#ifdef __PERFORMANCE_IMPLEMENTATION
328/* Here are two copies of loop implementations. First one favors performance
329 * and the second one favors code size. Default uses the second one.
330 * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
331 subs r3, r2
332 ble .LC1
333.LC0:
334 subs r3, #4
335 ldr r0, [r1, r3]
336 str r0, [r2, r3]
337 bgt .LC0
338.LC1:
339#else /* code size implemenation */
340.LC0:
341 cmp r2, r3
342 ittt lt
343 ldrlt r0, [r1], #4
344 strlt r0, [r2], #4
345 blt .LC0
346#endif
347#ifdef __STARTUP_INITIALIZE_NONCACHEDATA
348 ldr r2, =__noncachedata_start__
349 ldr r3, =__noncachedata_init_end__
350#ifdef __PERFORMANCE_IMPLEMENTATION
351/* Here are two copies of loop implementations. First one favors performance
352 * and the second one favors code size. Default uses the second one.
353 * Define macro "__PERFORMANCE_IMPLEMENTATION" in project to use the first one */
354 subs r3, r2
355 ble .LC3
356.LC2:
357 subs r3, #4
358 ldr r0, [r1, r3]
359 str r0, [r2, r3]
360 bgt .LC2
361.LC3:
362#else /* code size implemenation */
363.LC2:
364 cmp r2, r3
365 ittt lt
366 ldrlt r0, [r1], #4
367 strlt r0, [r2], #4
368 blt .LC2
369#endif
370/* zero inited ncache section initialization */
371 ldr r3, =__noncachedata_end__
372 movs r0,0
373.LC4:
374 cmp r2,r3
375 itt lt
376 strlt r0,[r2],#4
377 blt .LC4
378#endif /* __STARTUP_INITIALIZE_NONCACHEDATA */
379
380#ifdef __STARTUP_CLEAR_BSS
381/* This part of work usually is done in C library startup code. Otherwise,
382 * define this macro to enable it in this startup.
383 *
384 * Loop to zero out BSS section, which uses following symbols
385 * in linker script:
386 * __bss_start__: start of BSS section. Must align to 4
387 * __bss_end__: end of BSS section. Must align to 4
388 */
389 ldr r1, =__bss_start__
390 ldr r2, =__bss_end__
391
392 movs r0, 0
393.LC5:
394 cmp r1, r2
395 itt lt
396 strlt r0, [r1], #4
397 blt .LC5
398#endif /* __STARTUP_CLEAR_BSS */
399
400 cpsie i /* Unmask interrupts */
401#ifndef __START
402#define __START _start
403#endif
404#ifndef __ATOLLIC__
405 ldr r0,=__START
406 blx r0
407#else
408 ldr r0,=__libc_init_array
409 blx r0
410 ldr r0,=main
411 bx r0
412#endif
413 .pool
414 .size Reset_Handler, . - Reset_Handler
415
416 .align 1
417 .thumb_func
418 .weak DefaultISR
419 .type DefaultISR, %function
420DefaultISR:
421 b DefaultISR
422 .size DefaultISR, . - DefaultISR
423
424 .align 1
425 .thumb_func
426 .weak NMI_Handler
427 .type NMI_Handler, %function
428NMI_Handler:
429 ldr r0,=NMI_Handler
430 bx r0
431 .size NMI_Handler, . - NMI_Handler
432
433 .align 1
434 .thumb_func
435 .weak HardFault_Handler
436 .type HardFault_Handler, %function
437HardFault_Handler:
438 ldr r0,=HardFault_Handler
439 bx r0
440 .size HardFault_Handler, . - HardFault_Handler
441
442 .align 1
443 .thumb_func
444 .weak SVC_Handler
445 .type SVC_Handler, %function
446SVC_Handler:
447 ldr r0,=SVC_Handler
448 bx r0
449 .size SVC_Handler, . - SVC_Handler
450
451 .align 1
452 .thumb_func
453 .weak PendSV_Handler
454 .type PendSV_Handler, %function
455PendSV_Handler:
456 ldr r0,=PendSV_Handler
457 bx r0
458 .size PendSV_Handler, . - PendSV_Handler
459
460 .align 1
461 .thumb_func
462 .weak SysTick_Handler
463 .type SysTick_Handler, %function
464SysTick_Handler:
465 ldr r0,=SysTick_Handler
466 bx r0
467 .size SysTick_Handler, . - SysTick_Handler
468
469 .align 1
470 .thumb_func
471 .weak DMA0_DMA16_IRQHandler
472 .type DMA0_DMA16_IRQHandler, %function
473DMA0_DMA16_IRQHandler:
474 ldr r0,=DMA0_DMA16_DriverIRQHandler
475 bx r0
476 .size DMA0_DMA16_IRQHandler, . - DMA0_DMA16_IRQHandler
477
478 .align 1
479 .thumb_func
480 .weak DMA1_DMA17_IRQHandler
481 .type DMA1_DMA17_IRQHandler, %function
482DMA1_DMA17_IRQHandler:
483 ldr r0,=DMA1_DMA17_DriverIRQHandler
484 bx r0
485 .size DMA1_DMA17_IRQHandler, . - DMA1_DMA17_IRQHandler
486
487 .align 1
488 .thumb_func
489 .weak DMA2_DMA18_IRQHandler
490 .type DMA2_DMA18_IRQHandler, %function
491DMA2_DMA18_IRQHandler:
492 ldr r0,=DMA2_DMA18_DriverIRQHandler
493 bx r0
494 .size DMA2_DMA18_IRQHandler, . - DMA2_DMA18_IRQHandler
495
496 .align 1
497 .thumb_func
498 .weak DMA3_DMA19_IRQHandler
499 .type DMA3_DMA19_IRQHandler, %function
500DMA3_DMA19_IRQHandler:
501 ldr r0,=DMA3_DMA19_DriverIRQHandler
502 bx r0
503 .size DMA3_DMA19_IRQHandler, . - DMA3_DMA19_IRQHandler
504
505 .align 1
506 .thumb_func
507 .weak DMA4_DMA20_IRQHandler
508 .type DMA4_DMA20_IRQHandler, %function
509DMA4_DMA20_IRQHandler:
510 ldr r0,=DMA4_DMA20_DriverIRQHandler
511 bx r0
512 .size DMA4_DMA20_IRQHandler, . - DMA4_DMA20_IRQHandler
513
514 .align 1
515 .thumb_func
516 .weak DMA5_DMA21_IRQHandler
517 .type DMA5_DMA21_IRQHandler, %function
518DMA5_DMA21_IRQHandler:
519 ldr r0,=DMA5_DMA21_DriverIRQHandler
520 bx r0
521 .size DMA5_DMA21_IRQHandler, . - DMA5_DMA21_IRQHandler
522
523 .align 1
524 .thumb_func
525 .weak DMA6_DMA22_IRQHandler
526 .type DMA6_DMA22_IRQHandler, %function
527DMA6_DMA22_IRQHandler:
528 ldr r0,=DMA6_DMA22_DriverIRQHandler
529 bx r0
530 .size DMA6_DMA22_IRQHandler, . - DMA6_DMA22_IRQHandler
531
532 .align 1
533 .thumb_func
534 .weak DMA7_DMA23_IRQHandler
535 .type DMA7_DMA23_IRQHandler, %function
536DMA7_DMA23_IRQHandler:
537 ldr r0,=DMA7_DMA23_DriverIRQHandler
538 bx r0
539 .size DMA7_DMA23_IRQHandler, . - DMA7_DMA23_IRQHandler
540
541 .align 1
542 .thumb_func
543 .weak DMA8_DMA24_IRQHandler
544 .type DMA8_DMA24_IRQHandler, %function
545DMA8_DMA24_IRQHandler:
546 ldr r0,=DMA8_DMA24_DriverIRQHandler
547 bx r0
548 .size DMA8_DMA24_IRQHandler, . - DMA8_DMA24_IRQHandler
549
550 .align 1
551 .thumb_func
552 .weak DMA9_DMA25_IRQHandler
553 .type DMA9_DMA25_IRQHandler, %function
554DMA9_DMA25_IRQHandler:
555 ldr r0,=DMA9_DMA25_DriverIRQHandler
556 bx r0
557 .size DMA9_DMA25_IRQHandler, . - DMA9_DMA25_IRQHandler
558
559 .align 1
560 .thumb_func
561 .weak DMA10_DMA26_IRQHandler
562 .type DMA10_DMA26_IRQHandler, %function
563DMA10_DMA26_IRQHandler:
564 ldr r0,=DMA10_DMA26_DriverIRQHandler
565 bx r0
566 .size DMA10_DMA26_IRQHandler, . - DMA10_DMA26_IRQHandler
567
568 .align 1
569 .thumb_func
570 .weak DMA11_DMA27_IRQHandler
571 .type DMA11_DMA27_IRQHandler, %function
572DMA11_DMA27_IRQHandler:
573 ldr r0,=DMA11_DMA27_DriverIRQHandler
574 bx r0
575 .size DMA11_DMA27_IRQHandler, . - DMA11_DMA27_IRQHandler
576
577 .align 1
578 .thumb_func
579 .weak DMA12_DMA28_IRQHandler
580 .type DMA12_DMA28_IRQHandler, %function
581DMA12_DMA28_IRQHandler:
582 ldr r0,=DMA12_DMA28_DriverIRQHandler
583 bx r0
584 .size DMA12_DMA28_IRQHandler, . - DMA12_DMA28_IRQHandler
585
586 .align 1
587 .thumb_func
588 .weak DMA13_DMA29_IRQHandler
589 .type DMA13_DMA29_IRQHandler, %function
590DMA13_DMA29_IRQHandler:
591 ldr r0,=DMA13_DMA29_DriverIRQHandler
592 bx r0
593 .size DMA13_DMA29_IRQHandler, . - DMA13_DMA29_IRQHandler
594
595 .align 1
596 .thumb_func
597 .weak DMA14_DMA30_IRQHandler
598 .type DMA14_DMA30_IRQHandler, %function
599DMA14_DMA30_IRQHandler:
600 ldr r0,=DMA14_DMA30_DriverIRQHandler
601 bx r0
602 .size DMA14_DMA30_IRQHandler, . - DMA14_DMA30_IRQHandler
603
604 .align 1
605 .thumb_func
606 .weak DMA15_DMA31_IRQHandler
607 .type DMA15_DMA31_IRQHandler, %function
608DMA15_DMA31_IRQHandler:
609 ldr r0,=DMA15_DMA31_DriverIRQHandler
610 bx r0
611 .size DMA15_DMA31_IRQHandler, . - DMA15_DMA31_IRQHandler
612
613 .align 1
614 .thumb_func
615 .weak DMA_Error_IRQHandler
616 .type DMA_Error_IRQHandler, %function
617DMA_Error_IRQHandler:
618 ldr r0,=DMA_Error_DriverIRQHandler
619 bx r0
620 .size DMA_Error_IRQHandler, . - DMA_Error_IRQHandler
621
622 .align 1
623 .thumb_func
624 .weak I2C0_IRQHandler
625 .type I2C0_IRQHandler, %function
626I2C0_IRQHandler:
627 ldr r0,=I2C0_DriverIRQHandler
628 bx r0
629 .size I2C0_IRQHandler, . - I2C0_IRQHandler
630
631 .align 1
632 .thumb_func
633 .weak I2C1_IRQHandler
634 .type I2C1_IRQHandler, %function
635I2C1_IRQHandler:
636 ldr r0,=I2C1_DriverIRQHandler
637 bx r0
638 .size I2C1_IRQHandler, . - I2C1_IRQHandler
639
640 .align 1
641 .thumb_func
642 .weak SPI0_IRQHandler
643 .type SPI0_IRQHandler, %function
644SPI0_IRQHandler:
645 ldr r0,=SPI0_DriverIRQHandler
646 bx r0
647 .size SPI0_IRQHandler, . - SPI0_IRQHandler
648
649 .align 1
650 .thumb_func
651 .weak SPI1_IRQHandler
652 .type SPI1_IRQHandler, %function
653SPI1_IRQHandler:
654 ldr r0,=SPI1_DriverIRQHandler
655 bx r0
656 .size SPI1_IRQHandler, . - SPI1_IRQHandler
657
658 .align 1
659 .thumb_func
660 .weak I2S0_Tx_IRQHandler
661 .type I2S0_Tx_IRQHandler, %function
662I2S0_Tx_IRQHandler:
663 ldr r0,=I2S0_Tx_DriverIRQHandler
664 bx r0
665 .size I2S0_Tx_IRQHandler, . - I2S0_Tx_IRQHandler
666
667 .align 1
668 .thumb_func
669 .weak I2S0_Rx_IRQHandler
670 .type I2S0_Rx_IRQHandler, %function
671I2S0_Rx_IRQHandler:
672 ldr r0,=I2S0_Rx_DriverIRQHandler
673 bx r0
674 .size I2S0_Rx_IRQHandler, . - I2S0_Rx_IRQHandler
675
676 .align 1
677 .thumb_func
678 .weak UART0_RX_TX_IRQHandler
679 .type UART0_RX_TX_IRQHandler, %function
680UART0_RX_TX_IRQHandler:
681 ldr r0,=UART0_RX_TX_DriverIRQHandler
682 bx r0
683 .size UART0_RX_TX_IRQHandler, . - UART0_RX_TX_IRQHandler
684
685 .align 1
686 .thumb_func
687 .weak UART0_ERR_IRQHandler
688 .type UART0_ERR_IRQHandler, %function
689UART0_ERR_IRQHandler:
690 ldr r0,=UART0_ERR_DriverIRQHandler
691 bx r0
692 .size UART0_ERR_IRQHandler, . - UART0_ERR_IRQHandler
693
694 .align 1
695 .thumb_func
696 .weak UART1_RX_TX_IRQHandler
697 .type UART1_RX_TX_IRQHandler, %function
698UART1_RX_TX_IRQHandler:
699 ldr r0,=UART1_RX_TX_DriverIRQHandler
700 bx r0
701 .size UART1_RX_TX_IRQHandler, . - UART1_RX_TX_IRQHandler
702
703 .align 1
704 .thumb_func
705 .weak UART1_ERR_IRQHandler
706 .type UART1_ERR_IRQHandler, %function
707UART1_ERR_IRQHandler:
708 ldr r0,=UART1_ERR_DriverIRQHandler
709 bx r0
710 .size UART1_ERR_IRQHandler, . - UART1_ERR_IRQHandler
711
712 .align 1
713 .thumb_func
714 .weak UART2_RX_TX_IRQHandler
715 .type UART2_RX_TX_IRQHandler, %function
716UART2_RX_TX_IRQHandler:
717 ldr r0,=UART2_RX_TX_DriverIRQHandler
718 bx r0
719 .size UART2_RX_TX_IRQHandler, . - UART2_RX_TX_IRQHandler
720
721 .align 1
722 .thumb_func
723 .weak UART2_ERR_IRQHandler
724 .type UART2_ERR_IRQHandler, %function
725UART2_ERR_IRQHandler:
726 ldr r0,=UART2_ERR_DriverIRQHandler
727 bx r0
728 .size UART2_ERR_IRQHandler, . - UART2_ERR_IRQHandler
729
730 .align 1
731 .thumb_func
732 .weak UART3_RX_TX_IRQHandler
733 .type UART3_RX_TX_IRQHandler, %function
734UART3_RX_TX_IRQHandler:
735 ldr r0,=UART3_RX_TX_DriverIRQHandler
736 bx r0
737 .size UART3_RX_TX_IRQHandler, . - UART3_RX_TX_IRQHandler
738
739 .align 1
740 .thumb_func
741 .weak UART3_ERR_IRQHandler
742 .type UART3_ERR_IRQHandler, %function
743UART3_ERR_IRQHandler:
744 ldr r0,=UART3_ERR_DriverIRQHandler
745 bx r0
746 .size UART3_ERR_IRQHandler, . - UART3_ERR_IRQHandler
747
748 .align 1
749 .thumb_func
750 .weak SPI2_IRQHandler
751 .type SPI2_IRQHandler, %function
752SPI2_IRQHandler:
753 ldr r0,=SPI2_DriverIRQHandler
754 bx r0
755 .size SPI2_IRQHandler, . - SPI2_IRQHandler
756
757 .align 1
758 .thumb_func
759 .weak UART4_RX_TX_IRQHandler
760 .type UART4_RX_TX_IRQHandler, %function
761UART4_RX_TX_IRQHandler:
762 ldr r0,=UART4_RX_TX_DriverIRQHandler
763 bx r0
764 .size UART4_RX_TX_IRQHandler, . - UART4_RX_TX_IRQHandler
765
766 .align 1
767 .thumb_func
768 .weak UART4_ERR_IRQHandler
769 .type UART4_ERR_IRQHandler, %function
770UART4_ERR_IRQHandler:
771 ldr r0,=UART4_ERR_DriverIRQHandler
772 bx r0
773 .size UART4_ERR_IRQHandler, . - UART4_ERR_IRQHandler
774
775 .align 1
776 .thumb_func
777 .weak I2C2_IRQHandler
778 .type I2C2_IRQHandler, %function
779I2C2_IRQHandler:
780 ldr r0,=I2C2_DriverIRQHandler
781 bx r0
782 .size I2C2_IRQHandler, . - I2C2_IRQHandler
783
784 .align 1
785 .thumb_func
786 .weak CAN0_ORed_Message_buffer_IRQHandler
787 .type CAN0_ORed_Message_buffer_IRQHandler, %function
788CAN0_ORed_Message_buffer_IRQHandler:
789 ldr r0,=CAN0_DriverIRQHandler
790 bx r0
791 .size CAN0_ORed_Message_buffer_IRQHandler, . - CAN0_ORed_Message_buffer_IRQHandler
792
793 .align 1
794 .thumb_func
795 .weak CAN0_Bus_Off_IRQHandler
796 .type CAN0_Bus_Off_IRQHandler, %function
797CAN0_Bus_Off_IRQHandler:
798 ldr r0,=CAN0_DriverIRQHandler
799 bx r0
800 .size CAN0_Bus_Off_IRQHandler, . - CAN0_Bus_Off_IRQHandler
801
802 .align 1
803 .thumb_func
804 .weak CAN0_Error_IRQHandler
805 .type CAN0_Error_IRQHandler, %function
806CAN0_Error_IRQHandler:
807 ldr r0,=CAN0_DriverIRQHandler
808 bx r0
809 .size CAN0_Error_IRQHandler, . - CAN0_Error_IRQHandler
810
811 .align 1
812 .thumb_func
813 .weak CAN0_Tx_Warning_IRQHandler
814 .type CAN0_Tx_Warning_IRQHandler, %function
815CAN0_Tx_Warning_IRQHandler:
816 ldr r0,=CAN0_DriverIRQHandler
817 bx r0
818 .size CAN0_Tx_Warning_IRQHandler, . - CAN0_Tx_Warning_IRQHandler
819
820 .align 1
821 .thumb_func
822 .weak CAN0_Rx_Warning_IRQHandler
823 .type CAN0_Rx_Warning_IRQHandler, %function
824CAN0_Rx_Warning_IRQHandler:
825 ldr r0,=CAN0_DriverIRQHandler
826 bx r0
827 .size CAN0_Rx_Warning_IRQHandler, . - CAN0_Rx_Warning_IRQHandler
828
829 .align 1
830 .thumb_func
831 .weak CAN0_Wake_Up_IRQHandler
832 .type CAN0_Wake_Up_IRQHandler, %function
833CAN0_Wake_Up_IRQHandler:
834 ldr r0,=CAN0_DriverIRQHandler
835 bx r0
836 .size CAN0_Wake_Up_IRQHandler, . - CAN0_Wake_Up_IRQHandler
837
838 .align 1
839 .thumb_func
840 .weak SDHC_IRQHandler
841 .type SDHC_IRQHandler, %function
842SDHC_IRQHandler:
843 ldr r0,=SDHC_DriverIRQHandler
844 bx r0
845 .size SDHC_IRQHandler, . - SDHC_IRQHandler
846
847 .align 1
848 .thumb_func
849 .weak LPUART0_IRQHandler
850 .type LPUART0_IRQHandler, %function
851LPUART0_IRQHandler:
852 ldr r0,=LPUART0_DriverIRQHandler
853 bx r0
854 .size LPUART0_IRQHandler, . - LPUART0_IRQHandler
855
856 .align 1
857 .thumb_func
858 .weak I2C3_IRQHandler
859 .type I2C3_IRQHandler, %function
860I2C3_IRQHandler:
861 ldr r0,=I2C3_DriverIRQHandler
862 bx r0
863 .size I2C3_IRQHandler, . - I2C3_IRQHandler
864
865 .align 1
866 .thumb_func
867 .weak CAN1_ORed_Message_buffer_IRQHandler
868 .type CAN1_ORed_Message_buffer_IRQHandler, %function
869CAN1_ORed_Message_buffer_IRQHandler:
870 ldr r0,=CAN1_DriverIRQHandler
871 bx r0
872 .size CAN1_ORed_Message_buffer_IRQHandler, . - CAN1_ORed_Message_buffer_IRQHandler
873
874 .align 1
875 .thumb_func
876 .weak CAN1_Bus_Off_IRQHandler
877 .type CAN1_Bus_Off_IRQHandler, %function
878CAN1_Bus_Off_IRQHandler:
879 ldr r0,=CAN1_DriverIRQHandler
880 bx r0
881 .size CAN1_Bus_Off_IRQHandler, . - CAN1_Bus_Off_IRQHandler
882
883 .align 1
884 .thumb_func
885 .weak CAN1_Error_IRQHandler
886 .type CAN1_Error_IRQHandler, %function
887CAN1_Error_IRQHandler:
888 ldr r0,=CAN1_DriverIRQHandler
889 bx r0
890 .size CAN1_Error_IRQHandler, . - CAN1_Error_IRQHandler
891
892 .align 1
893 .thumb_func
894 .weak CAN1_Tx_Warning_IRQHandler
895 .type CAN1_Tx_Warning_IRQHandler, %function
896CAN1_Tx_Warning_IRQHandler:
897 ldr r0,=CAN1_DriverIRQHandler
898 bx r0
899 .size CAN1_Tx_Warning_IRQHandler, . - CAN1_Tx_Warning_IRQHandler
900
901 .align 1
902 .thumb_func
903 .weak CAN1_Rx_Warning_IRQHandler
904 .type CAN1_Rx_Warning_IRQHandler, %function
905CAN1_Rx_Warning_IRQHandler:
906 ldr r0,=CAN1_DriverIRQHandler
907 bx r0
908 .size CAN1_Rx_Warning_IRQHandler, . - CAN1_Rx_Warning_IRQHandler
909
910 .align 1
911 .thumb_func
912 .weak CAN1_Wake_Up_IRQHandler
913 .type CAN1_Wake_Up_IRQHandler, %function
914CAN1_Wake_Up_IRQHandler:
915 ldr r0,=CAN1_DriverIRQHandler
916 bx r0
917 .size CAN1_Wake_Up_IRQHandler, . - CAN1_Wake_Up_IRQHandler
918
919
920/* Macro to define default handlers. Default handler
921 * will be weak symbol and just dead loops. They can be
922 * overwritten by other handlers */
923 .macro def_irq_handler handler_name
924 .weak \handler_name
925 .set \handler_name, DefaultISR
926 .endm
927
928/* Exception Handlers */
929 def_irq_handler MemManage_Handler
930 def_irq_handler BusFault_Handler
931 def_irq_handler UsageFault_Handler
932 def_irq_handler DebugMon_Handler
933 def_irq_handler DMA0_DMA16_DriverIRQHandler
934 def_irq_handler DMA1_DMA17_DriverIRQHandler
935 def_irq_handler DMA2_DMA18_DriverIRQHandler
936 def_irq_handler DMA3_DMA19_DriverIRQHandler
937 def_irq_handler DMA4_DMA20_DriverIRQHandler
938 def_irq_handler DMA5_DMA21_DriverIRQHandler
939 def_irq_handler DMA6_DMA22_DriverIRQHandler
940 def_irq_handler DMA7_DMA23_DriverIRQHandler
941 def_irq_handler DMA8_DMA24_DriverIRQHandler
942 def_irq_handler DMA9_DMA25_DriverIRQHandler
943 def_irq_handler DMA10_DMA26_DriverIRQHandler
944 def_irq_handler DMA11_DMA27_DriverIRQHandler
945 def_irq_handler DMA12_DMA28_DriverIRQHandler
946 def_irq_handler DMA13_DMA29_DriverIRQHandler
947 def_irq_handler DMA14_DMA30_DriverIRQHandler
948 def_irq_handler DMA15_DMA31_DriverIRQHandler
949 def_irq_handler DMA_Error_DriverIRQHandler
950 def_irq_handler MCM_IRQHandler
951 def_irq_handler FTFE_IRQHandler
952 def_irq_handler Read_Collision_IRQHandler
953 def_irq_handler LVD_LVW_IRQHandler
954 def_irq_handler LLWU_IRQHandler
955 def_irq_handler WDOG_EWM_IRQHandler
956 def_irq_handler RNG_IRQHandler
957 def_irq_handler I2C0_DriverIRQHandler
958 def_irq_handler I2C1_DriverIRQHandler
959 def_irq_handler SPI0_DriverIRQHandler
960 def_irq_handler SPI1_DriverIRQHandler
961 def_irq_handler I2S0_Tx_DriverIRQHandler
962 def_irq_handler I2S0_Rx_DriverIRQHandler
963 def_irq_handler Reserved46_IRQHandler
964 def_irq_handler UART0_RX_TX_DriverIRQHandler
965 def_irq_handler UART0_ERR_DriverIRQHandler
966 def_irq_handler UART1_RX_TX_DriverIRQHandler
967 def_irq_handler UART1_ERR_DriverIRQHandler
968 def_irq_handler UART2_RX_TX_DriverIRQHandler
969 def_irq_handler UART2_ERR_DriverIRQHandler
970 def_irq_handler UART3_RX_TX_DriverIRQHandler
971 def_irq_handler UART3_ERR_DriverIRQHandler
972 def_irq_handler ADC0_IRQHandler
973 def_irq_handler CMP0_IRQHandler
974 def_irq_handler CMP1_IRQHandler
975 def_irq_handler FTM0_IRQHandler
976 def_irq_handler FTM1_IRQHandler
977 def_irq_handler FTM2_IRQHandler
978 def_irq_handler CMT_IRQHandler
979 def_irq_handler RTC_IRQHandler
980 def_irq_handler RTC_Seconds_IRQHandler
981 def_irq_handler PIT0_IRQHandler
982 def_irq_handler PIT1_IRQHandler
983 def_irq_handler PIT2_IRQHandler
984 def_irq_handler PIT3_IRQHandler
985 def_irq_handler PDB0_IRQHandler
986 def_irq_handler USB0_IRQHandler
987 def_irq_handler USBDCD_IRQHandler
988 def_irq_handler Reserved71_IRQHandler
989 def_irq_handler DAC0_IRQHandler
990 def_irq_handler MCG_IRQHandler
991 def_irq_handler LPTMR0_IRQHandler
992 def_irq_handler PORTA_IRQHandler
993 def_irq_handler PORTB_IRQHandler
994 def_irq_handler PORTC_IRQHandler
995 def_irq_handler PORTD_IRQHandler
996 def_irq_handler PORTE_IRQHandler
997 def_irq_handler SWI_IRQHandler
998 def_irq_handler SPI2_DriverIRQHandler
999 def_irq_handler UART4_RX_TX_DriverIRQHandler
1000 def_irq_handler UART4_ERR_DriverIRQHandler
1001 def_irq_handler Reserved84_IRQHandler
1002 def_irq_handler Reserved85_IRQHandler
1003 def_irq_handler CMP2_IRQHandler
1004 def_irq_handler FTM3_IRQHandler
1005 def_irq_handler DAC1_IRQHandler
1006 def_irq_handler ADC1_IRQHandler
1007 def_irq_handler I2C2_DriverIRQHandler
1008 def_irq_handler CAN0_DriverIRQHandler
1009 def_irq_handler SDHC_DriverIRQHandler
1010 def_irq_handler Reserved98_IRQHandler
1011 def_irq_handler Reserved99_IRQHandler
1012 def_irq_handler Reserved100_IRQHandler
1013 def_irq_handler Reserved101_IRQHandler
1014 def_irq_handler LPUART0_DriverIRQHandler
1015 def_irq_handler TSI0_IRQHandler
1016 def_irq_handler TPM1_IRQHandler
1017 def_irq_handler TPM2_IRQHandler
1018 def_irq_handler USBHSDCD_IRQHandler
1019 def_irq_handler I2C3_DriverIRQHandler
1020 def_irq_handler CMP3_IRQHandler
1021 def_irq_handler USBHS_IRQHandler
1022 def_irq_handler CAN1_DriverIRQHandler
1023
1024 .end
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 18:55:11 +0100