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1/*
2** ###################################################################
3** Processor: MK27FN2M0AVMI15
4** Compilers: Keil ARM C/C++ Compiler
5** Freescale C/C++ for Embedded ARM
6** GNU C Compiler
7** IAR ANSI C/C++ Compiler for ARM
8** MCUXpresso Compiler
9**
10** Reference manual: K27P169M150SF5RM, Rev. 2, Aug 2017
11** Version: rev. 1.3, 2018-01-09
12** Build: b180801
13**
14** Abstract:
15** CMSIS Peripheral Access Layer for MK27FA15
16**
17** Copyright 1997-2016 Freescale Semiconductor, Inc.
18** Copyright 2016-2018 NXP
19**
20** SPDX-License-Identifier: BSD-3-Clause
21**
22** http: www.nxp.com
23** mail: [email protected]
24**
25** Revisions:
26** - rev. 1.0 (2016-05-10)
27** Initial version
28** - rev. 1.1 (2016-10-20)
29** Update based on Rev1 RM.
30** - rev. 1.2 (2017-04-06)
31** Remove TSI.
32** Add ISD2FA, ISD3FA, ISD2FB and ISD3FB bits in QuadSPI0_MCR.
33** - rev. 1.3 (2018-01-09)
34** Add K28FA support.
35**
36** ###################################################################
37*/
38
39/*!
40 * @file MK27FA15.h
41 * @version 1.3
42 * @date 2018-01-09
43 * @brief CMSIS Peripheral Access Layer for MK27FA15
44 *
45 * CMSIS Peripheral Access Layer for MK27FA15
46 */
47
48#ifndef _MK27FA15_H_
49#define _MK27FA15_H_ /**< Symbol preventing repeated inclusion */
50
51/** Memory map major version (memory maps with equal major version number are
52 * compatible) */
53#define MCU_MEM_MAP_VERSION 0x0100U
54/** Memory map minor version */
55#define MCU_MEM_MAP_VERSION_MINOR 0x0003U
56
57/**
58 * @brief Macro to calculate address of an aliased word in the peripheral
59 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
60 * 0x400FFFFF).
61 * @param Reg Register to access.
62 * @param Bit Bit number to access.
63 * @return Address of the aliased word in the peripheral bitband area.
64 */
65#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
66/**
67 * @brief Macro to access a single bit of a peripheral register (bit band region
68 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
69 * be used for peripherals with 32bit access allowed.
70 * @param Reg Register to access.
71 * @param Bit Bit number to access.
72 * @return Value of the targeted bit in the bit band region.
73 */
74#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
75#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
76/**
77 * @brief Macro to access a single bit of a peripheral register (bit band region
78 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
79 * be used for peripherals with 16bit access allowed.
80 * @param Reg Register to access.
81 * @param Bit Bit number to access.
82 * @return Value of the targeted bit in the bit band region.
83 */
84#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
85/**
86 * @brief Macro to access a single bit of a peripheral register (bit band region
87 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
88 * be used for peripherals with 8bit access allowed.
89 * @param Reg Register to access.
90 * @param Bit Bit number to access.
91 * @return Value of the targeted bit in the bit band region.
92 */
93#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
94
95/* ----------------------------------------------------------------------------
96 -- Interrupt vector numbers
97 ---------------------------------------------------------------------------- */
98
99/*!
100 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
101 * @{
102 */
103
104/** Interrupt Number Definitions */
105#define NUMBER_OF_INT_VECTORS 123 /**< Number of interrupts in the Vector table */
106
107typedef enum IRQn {
108 /* Auxiliary constants */
109 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
110
111 /* Core interrupts */
112 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
113 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
114 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
115 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
116 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
117 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
118 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
119 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
120 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
121
122 /* Device specific interrupts */
123 DMA0_DMA16_IRQn = 0, /**< DMA channel 0,16 transfer complete */
124 DMA1_DMA17_IRQn = 1, /**< DMA channel 1,17 transfer complete */
125 DMA2_DMA18_IRQn = 2, /**< DMA channel 2,18 transfer complete */
126 DMA3_DMA19_IRQn = 3, /**< DMA channel 3,19 transfer complete */
127 DMA4_DMA20_IRQn = 4, /**< DMA channel 4,20 transfer complete */
128 DMA5_DMA21_IRQn = 5, /**< DMA channel 5,21 transfer complete */
129 DMA6_DMA22_IRQn = 6, /**< DMA channel 6,22 transfer complete */
130 DMA7_DMA23_IRQn = 7, /**< DMA channel 7,23 transfer complete */
131 DMA8_DMA24_IRQn = 8, /**< DMA channel 8,24 transfer complete */
132 DMA9_DMA25_IRQn = 9, /**< DMA channel 9,25 transfer complete */
133 DMA10_DMA26_IRQn = 10, /**< DMA channel 10,26 transfer complete */
134 DMA11_DMA27_IRQn = 11, /**< DMA channel 11,27 transfer complete */
135 DMA12_DMA28_IRQn = 12, /**< DMA channel 12,28 transfer complete */
136 DMA13_DMA29_IRQn = 13, /**< DMA channel 13,29 transfer complete */
137 DMA14_DMA30_IRQn = 14, /**< DMA channel 14,30 transfer complete */
138 DMA15_DMA31_IRQn = 15, /**< DMA channel 15,31 transfer complete */
139 DMA_Error_IRQn = 16, /**< DMA channel 0 - 31 error */
140 MCM_IRQn = 17, /**< MCM normal interrupt */
141 FTFE_IRQn = 18, /**< FTFE command complete */
142 Read_Collision_IRQn = 19, /**< FTFE read collision */
143 LVD_LVW_IRQn = 20, /**< PMC controller low-voltage detect, low-voltage warning */
144 LLWU_IRQn = 21, /**< Low leakage wakeup unit */
145 WDOG_EWM_IRQn = 22, /**< Single interrupt vector for WDOG and EWM */
146 TRNG0_IRQn = 23, /**< True randon number generator */
147 I2C0_IRQn = 24, /**< Inter-integrated circuit 0 */
148 I2C1_IRQn = 25, /**< Inter-integrated circuit 1 */
149 SPI0_IRQn = 26, /**< Serial peripheral Interface 0 */
150 SPI1_IRQn = 27, /**< Serial peripheral Interface 1 */
151 I2S0_Tx_IRQn = 28, /**< Integrated interchip sound 0 transmit interrupt */
152 I2S0_Rx_IRQn = 29, /**< Integrated interchip sound 0 receive interrupt */
153 LPUART0_IRQn = 30, /**< LPUART0 receive/transmit/error interrupt */
154 LPUART1_IRQn = 31, /**< LPUART1 receive/transmit/error interrupt */
155 LPUART2_IRQn = 32, /**< LPUART2 receive/transmit/error interrupt */
156 LPUART3_IRQn = 33, /**< LPUART3 receive/transmit/error interrupt */
157 LPUART4_IRQn = 34, /**< LPUART4 receive/transmit/error interrupt */
158 Reserved51_IRQn = 35, /**< Reserved interrupt */
159 Reserved52_IRQn = 36, /**< Reserved interrupt */
160 Reserved53_IRQn = 37, /**< Reserved interrupt */
161 Reserved54_IRQn = 38, /**< Reserved interrupt */
162 ADC0_IRQn = 39, /**< Analog-to-digital converter 0 */
163 CMP0_IRQn = 40, /**< Comparator 0 */
164 CMP1_IRQn = 41, /**< Comparator 1 */
165 FTM0_IRQn = 42, /**< FlexTimer module 0 fault, overflow and channels interrupt */
166 FTM1_IRQn = 43, /**< FlexTimer module 1 fault, overflow and channels interrupt */
167 FTM2_IRQn = 44, /**< FlexTimer module 2 fault, overflow and channels interrupt */
168 CMT_IRQn = 45, /**< Carrier modulator transmitter */
169 RTC_IRQn = 46, /**< Real time clock */
170 RTC_Seconds_IRQn = 47, /**< Real time clock seconds */
171 PIT0CH0_IRQn = 48, /**< Periodic interrupt timer 0 channel 0 */
172 PIT0CH1_IRQn = 49, /**< Periodic interrupt timer 0 channel 1 */
173 PIT0CH2_IRQn = 50, /**< Periodic interrupt timer 0 channel 2 */
174 PIT0CH3_IRQn = 51, /**< Periodic interrupt timer 0 channel 3 */
175 PDB0_IRQn = 52, /**< Programmable delay block */
176 USB0_IRQn = 53, /**< USB OTG interrupt */
177 USBDCD_IRQn = 54, /**< USB charger detect */
178 Reserved71_IRQn = 55, /**< Reserved interrupt */
179 DAC0_IRQn = 56, /**< Digital-to-analog converter 0 */
180 MCG_IRQn = 57, /**< Multipurpose clock generator */
181 LPTMR0_LPTMR1_IRQn = 58, /**< Single interrupt vector for Low Power Timer 0 and 1 */
182 PORTA_IRQn = 59, /**< Port A pin detect interrupt */
183 PORTB_IRQn = 60, /**< Port B pin detect interrupt */
184 PORTC_IRQn = 61, /**< Port C pin detect interrupt */
185 PORTD_IRQn = 62, /**< Port D pin detect interrupt */
186 PORTE_IRQn = 63, /**< Port E pin detect interrupt */
187 SWI_IRQn = 64, /**< Software interrupt */
188 SPI2_IRQn = 65, /**< Serial peripheral Interface 2 */
189 SPI3_IRQn = 66, /**< Serial peripheral Interface 3 */
190 Reserved83_IRQn = 67, /**< Reserved interrupt */
191 I2S1_Tx_IRQn = 68, /**< Integrated interchip sound 1 transmit interrupt */
192 I2S1_Rx_IRQn = 69, /**< Integrated interchip sound 1 receive interrupt */
193 FLEXIO0_IRQn = 70, /**< FLEXIO0 */
194 FTM3_IRQn = 71, /**< FlexTimer module 3 fault, overflow and channels interrupt */
195 Reserved88_IRQn = 72, /**< Reserved interrupt */
196 Reserved89_IRQn = 73, /**< Reserved interrupt */
197 I2C2_IRQn = 74, /**< Inter-integrated circuit 2 */
198 Reserved91_IRQn = 75, /**< Reserved interrupt */
199 Reserved92_IRQn = 76, /**< Reserved interrupt */
200 Reserved93_IRQn = 77, /**< Reserved interrupt */
201 Reserved94_IRQn = 78, /**< Reserved interrupt */
202 Reserved95_IRQn = 79, /**< Reserved interrupt */
203 Reserved96_IRQn = 80, /**< Reserved interrupt */
204 SDHC_IRQn = 81, /**< Secured digital host controller */
205 Reserved98_IRQn = 82, /**< Reserved interrupt */
206 Reserved99_IRQn = 83, /**< Reserved interrupt */
207 Reserved100_IRQn = 84, /**< Reserved interrupt */
208 Reserved101_IRQn = 85, /**< Reserved interrupt */
209 Reserved102_IRQn = 86, /**< Reserved interrupt */
210 Reserved103_IRQn = 87, /**< Reserved interrupt */
211 TPM1_IRQn = 88, /**< TPM1 single interrupt vector for all sources */
212 TPM2_IRQn = 89, /**< TPM2 single interrupt vector for all sources */
213 USBHSDCD_IRQn = 90, /**< HS USB charger detect */
214 I2C3_IRQn = 91, /**< Inter-integrated circuit 3 */
215 Reserved108_IRQn = 92, /**< Reserved interrupt */
216 USBHS_IRQn = 93, /**< USB HS interrupt */
217 Reserved110_IRQn = 94, /**< Reserved interrupt */
218 Reserved111_IRQn = 95, /**< Reserved interrupt */
219 Reserved112_IRQn = 96, /**< Reserved interrupt */
220 Reserved113_IRQn = 97, /**< Reserved interrupt */
221 Reserved114_IRQn = 98, /**< Reserved interrupt */
222 Reserved115_IRQn = 99, /**< Reserved interrupt */
223 QuadSPI0_IRQn = 100, /**< qspi */
224 Reserved117_IRQn = 101, /**< Reserved interrupt */
225 Reserved118_IRQn = 102, /**< Reserved interrupt */
226 Reserved119_IRQn = 103, /**< Reserved interrupt */
227 Reserved120_IRQn = 104, /**< Reserved interrupt */
228 Reserved121_IRQn = 105, /**< Reserved interrupt */
229 Reserved122_IRQn = 106 /**< Reserved interrupt */
230} IRQn_Type;
231
232/*!
233 * @}
234 */ /* end of group Interrupt_vector_numbers */
235
236
237/* ----------------------------------------------------------------------------
238 -- Cortex M4 Core Configuration
239 ---------------------------------------------------------------------------- */
240
241/*!
242 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
243 * @{
244 */
245
246#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
247#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
248#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
249#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
250
251#include "core_cm4.h" /* Core Peripheral Access Layer */
252#include "system_MK27FA15.h" /* Device specific configuration file */
253
254/*!
255 * @}
256 */ /* end of group Cortex_Core_Configuration */
257
258
259/* ----------------------------------------------------------------------------
260 -- Mapping Information
261 ---------------------------------------------------------------------------- */
262
263/*!
264 * @addtogroup Mapping_Information Mapping Information
265 * @{
266 */
267
268/** Mapping Information */
269/*!
270 * @addtogroup edma_request
271 * @{
272 */
273
274/*******************************************************************************
275 * Definitions
276 ******************************************************************************/
277
278/*!
279 * @brief Structure for the DMA hardware request
280 *
281 * Defines the structure for the DMA hardware request collections. The user can configure the
282 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
283 * of the hardware request varies according to the to SoC.
284 */
285typedef enum _dma_request_source
286{
287 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
288 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
289 kDmaRequestMux0LPUART0Rx = 2|0x100U, /**< LPUART0 Receive. */
290 kDmaRequestMux0LPUART0Tx = 3|0x100U, /**< LPUART0 Transmit. */
291 kDmaRequestMux0LPUART1Rx = 4|0x100U, /**< LPUART1 Receive. */
292 kDmaRequestMux0LPUART1Tx = 5|0x100U, /**< LPUART1 Transmit. */
293 kDmaRequestMux0LPUART2Rx = 6|0x100U, /**< LPUART2 Receive. */
294 kDmaRequestMux0LPUART2Tx = 7|0x100U, /**< LPUART2 Transmit. */
295 kDmaRequestMux0LPUART3Rx = 8|0x100U, /**< LPUART3 Receive. */
296 kDmaRequestMux0LPUART3Tx = 9|0x100U, /**< LPUART3 Transmit. */
297 kDmaRequestMux0LPUART4Rx = 10|0x100U, /**< LPUART4 Receive. */
298 kDmaRequestMux0LPUART4Tx = 11|0x100U, /**< LPUART4 Transmit. */
299 kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
300 kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
301 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
302 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
303 kDmaRequestMux0SPI1Rx = 16|0x100U, /**< SPI1 Receive. */
304 kDmaRequestMux0SPI1Tx = 17|0x100U, /**< SPI1 Transmit. */
305 kDmaRequestMux0I2C0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
306 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0 and I2C3. */
307 kDmaRequestMux0I2C3 = 18|0x100U, /**< I2C0 and I2C3. */
308 kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
309 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
310 kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
311 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
312 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
313 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
314 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
315 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
316 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
317 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
318 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
319 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
320 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
321 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
322 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
323 kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
324 kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
325 kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
326 kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
327 kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
328 kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
329 kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */
330 kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */
331 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
332 kDmaRequestMux0Reserved41 = 41|0x100U, /**< Reserved41 */
333 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
334 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
335 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
336 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
337 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
338 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
339 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
340 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
341 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
342 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
343 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
344 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
345 kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */
346 kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */
347 kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */
348 kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
349 kDmaRequestMux0SPI2Rx = 58|0x100U, /**< SPI2 Receive. */
350 kDmaRequestMux0SPI2Tx = 59|0x100U, /**< SPI2 Transmit. */
351 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
352 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
353 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
354 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
355 kDmaRequestMux0Group1Disable = 0|0x200U, /**< DMAMUX TriggerDisabled. */
356 kDmaRequestMux0Group1FlexIO0Channel0 = 1|0x200U, /**< FLEXIO0. */
357 kDmaRequestMux0Group1FlexIO0Channel1 = 2|0x200U, /**< FLEXIO0. */
358 kDmaRequestMux0Group1FlexIO0Channel2 = 3|0x200U, /**< FLEXIO0. */
359 kDmaRequestMux0Group1FlexIO0Channel3 = 4|0x200U, /**< FLEXIO0. */
360 kDmaRequestMux0Group1FlexIO0Channel4 = 5|0x200U, /**< FLEXIO0. */
361 kDmaRequestMux0Group1FlexIO0Channel5 = 6|0x200U, /**< FLEXIO0. */
362 kDmaRequestMux0Group1FlexIO0Channel6 = 7|0x200U, /**< FLEXIO0. */
363 kDmaRequestMux0Group1FlexIO0Channel7 = 8|0x200U, /**< FLEXIO0. */
364 kDmaRequestMux0Group1Reserved9 = 9|0x200U, /**< Reserved9 */
365 kDmaRequestMux0Group1Reserved10 = 10|0x200U, /**< Reserved10 */
366 kDmaRequestMux0Group1Reserved11 = 11|0x200U, /**< Reserved11 */
367 kDmaRequestMux0Group1I2S1Tx = 12|0x200U, /**< I2S1 Transmit. */
368 kDmaRequestMux0Group1I2S1Rx = 13|0x200U, /**< I2S1 Receive. */
369 kDmaRequestMux0Group1Reserved14 = 14|0x200U, /**< Reserved14 */
370 kDmaRequestMux0Group1Reserved15 = 15|0x200U, /**< Reserved15 */
371 kDmaRequestMux0Group1Reserved16 = 16|0x200U, /**< Reserved16 */
372 kDmaRequestMux0Group1Reserved17 = 17|0x200U, /**< Reserved17 */
373 kDmaRequestMux0Group1Reserved18 = 18|0x200U, /**< Reserved18 */
374 kDmaRequestMux0Group1Reserved19 = 19|0x200U, /**< Reserved19 */
375 kDmaRequestMux0Group1Reserved20 = 20|0x200U, /**< Reserved20 */
376 kDmaRequestMux0Group1Reserved21 = 21|0x200U, /**< Reserved21 */
377 kDmaRequestMux0Group1Reserved22 = 22|0x200U, /**< Reserved22 */
378 kDmaRequestMux0Group1Reserved23 = 23|0x200U, /**< Reserved23 */
379 kDmaRequestMux0Group1QSPI0Rx = 24|0x200U, /**< QuadSPI0 Receive. */
380 kDmaRequestMux0Group1QSPI0Tx = 25|0x200U, /**< QuadSPI0 Transmit. */
381 kDmaRequestMux0Group1Reserved26 = 26|0x200U, /**< Reserved26 */
382 kDmaRequestMux0Group1Reserved27 = 27|0x200U, /**< Reserved27 */
383 kDmaRequestMux0Group1SPI0Rx = 28|0x200U, /**< SPI0 Receive. */
384 kDmaRequestMux0Group1SPI0Tx = 29|0x200U, /**< SPI0 Transmit. */
385 kDmaRequestMux0Group1SPI1Rx = 30|0x200U, /**< SPI1 Receive. */
386 kDmaRequestMux0Group1SPI1Tx = 31|0x200U, /**< SPI1 Transmit. */
387 kDmaRequestMux0Group1Reserved32 = 32|0x200U, /**< Reserved32 */
388 kDmaRequestMux0Group1Reserved33 = 33|0x200U, /**< Reserved33 */
389 kDmaRequestMux0Group1Reserved34 = 34|0x200U, /**< Reserved34 */
390 kDmaRequestMux0Group1Reserved35 = 35|0x200U, /**< Reserved35 */
391 kDmaRequestMux0Group1Reserved36 = 36|0x200U, /**< Reserved36 */
392 kDmaRequestMux0Group1Reserved37 = 37|0x200U, /**< Reserved37 */
393 kDmaRequestMux0Group1Reserved38 = 38|0x200U, /**< Reserved38 */
394 kDmaRequestMux0Group1Reserved39 = 39|0x200U, /**< Reserved39 */
395 kDmaRequestMux0Group1Reserved40 = 40|0x200U, /**< Reserved40 */
396 kDmaRequestMux0Group1Reserved41 = 41|0x200U, /**< Reserved41 */
397 kDmaRequestMux0Group1TPM1Channel0 = 42|0x200U, /**< TPM1 C0V. */
398 kDmaRequestMux0Group1TPM1Channel1 = 43|0x200U, /**< TPM1 C1V. */
399 kDmaRequestMux0Group1TPM2Channel0 = 44|0x200U, /**< TPM2 C0V. */
400 kDmaRequestMux0Group1TPM2Channel1 = 45|0x200U, /**< TPM2 C1V. */
401 kDmaRequestMux0Group1Reserved46 = 46|0x200U, /**< Reserved46 */
402 kDmaRequestMux0Group1Reserved47 = 47|0x200U, /**< Reserved47 */
403 kDmaRequestMux0Group1Reserved48 = 48|0x200U, /**< Reserved48 */
404 kDmaRequestMux0Group1Reserved49 = 49|0x200U, /**< Reserved49 */
405 kDmaRequestMux0Group1Reserved50 = 50|0x200U, /**< Reserved50 */
406 kDmaRequestMux0Group1Reserved51 = 51|0x200U, /**< Reserved51 */
407 kDmaRequestMux0Group1Reserved52 = 52|0x200U, /**< Reserved52 */
408 kDmaRequestMux0Group1Reserved53 = 53|0x200U, /**< Reserved53 */
409 kDmaRequestMux0Group1Reserved54 = 54|0x200U, /**< Reserved54 */
410 kDmaRequestMux0Group1TPM1Overflow = 55|0x200U, /**< TPM1. */
411 kDmaRequestMux0Group1TPM2Overflow = 56|0x200U, /**< TPM2. */
412 kDmaRequestMux0Group1Reserved57 = 57|0x200U, /**< Reserved57 */
413 kDmaRequestMux0Group1SPI3Rx = 58|0x200U, /**< SPI3 Receive. */
414 kDmaRequestMux0Group1SPI3Tx = 59|0x200U, /**< SPI3 Transmit. */
415 kDmaRequestMux0Group1AlwaysOn60 = 60|0x200U, /**< DMAMUX Always Enabled slot. */
416 kDmaRequestMux0Group1AlwaysOn61 = 61|0x200U, /**< DMAMUX Always Enabled slot. */
417 kDmaRequestMux0Group1AlwaysOn62 = 62|0x200U, /**< DMAMUX Always Enabled slot. */
418 kDmaRequestMux0Group1AlwaysOn63 = 63|0x200U, /**< DMAMUX Always Enabled slot. */
419} dma_request_source_t;
420
421/* @} */
422
423
424/*!
425 * @}
426 */ /* end of group Mapping_Information */
427
428
429/* ----------------------------------------------------------------------------
430 -- Device Peripheral Access Layer
431 ---------------------------------------------------------------------------- */
432
433/*!
434 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
435 * @{
436 */
437
438
439/*
440** Start of section using anonymous unions
441*/
442
443#if defined(__ARMCC_VERSION)
444 #if (__ARMCC_VERSION >= 6010050)
445 #pragma clang diagnostic push
446 #else
447 #pragma push
448 #pragma anon_unions
449 #endif
450#elif defined(__CWCC__)
451 #pragma push
452 #pragma cpp_extensions on
453#elif defined(__GNUC__)
454 /* anonymous unions are enabled by default */
455#elif defined(__IAR_SYSTEMS_ICC__)
456 #pragma language=extended
457#else
458 #error Not supported compiler type
459#endif
460
461/* ----------------------------------------------------------------------------
462 -- ADC Peripheral Access Layer
463 ---------------------------------------------------------------------------- */
464
465/*!
466 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
467 * @{
468 */
469
470/** ADC - Register Layout Typedef */
471typedef struct {
472 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
473 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
474 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
475 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
476 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
477 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
478 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
479 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
480 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
481 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
482 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
483 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
484 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
485 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
486 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
487 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
488 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
489 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
490 uint8_t RESERVED_0[4];
491 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
492 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
493 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
494 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
495 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
496 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
497 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
498} ADC_Type;
499
500/* ----------------------------------------------------------------------------
501 -- ADC Register Masks
502 ---------------------------------------------------------------------------- */
503
504/*!
505 * @addtogroup ADC_Register_Masks ADC Register Masks
506 * @{
507 */
508
509/*! @name SC1 - ADC Status and Control Registers 1 */
510/*! @{ */
511#define ADC_SC1_ADCH_MASK (0x1FU)
512#define ADC_SC1_ADCH_SHIFT (0U)
513/*! ADCH - Input channel select
514 * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
515 * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
516 * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
517 * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
518 * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
519 * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
520 * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
521 * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
522 * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
523 * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
524 * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
525 * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
526 * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
527 * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
528 * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
529 * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
530 * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
531 * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
532 * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
533 * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
534 * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
535 * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
536 * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
537 * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
538 * 0b11000..Reserved.
539 * 0b11001..Reserved.
540 * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
541 * 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
542 * 0b11100..Reserved.
543 * 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
544 * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
545 * 0b11111..Module is disabled.
546 */
547#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
548#define ADC_SC1_DIFF_MASK (0x20U)
549#define ADC_SC1_DIFF_SHIFT (5U)
550/*! DIFF - Differential Mode Enable
551 * 0b0..Single-ended conversions and input channels are selected.
552 * 0b1..Differential conversions and input channels are selected.
553 */
554#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
555#define ADC_SC1_AIEN_MASK (0x40U)
556#define ADC_SC1_AIEN_SHIFT (6U)
557/*! AIEN - Interrupt Enable
558 * 0b0..Conversion complete interrupt is disabled.
559 * 0b1..Conversion complete interrupt is enabled.
560 */
561#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
562#define ADC_SC1_COCO_MASK (0x80U)
563#define ADC_SC1_COCO_SHIFT (7U)
564/*! COCO - Conversion Complete Flag
565 * 0b0..Conversion is not completed.
566 * 0b1..Conversion is completed.
567 */
568#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
569/*! @} */
570
571/* The count of ADC_SC1 */
572#define ADC_SC1_COUNT (2U)
573
574/*! @name CFG1 - ADC Configuration Register 1 */
575/*! @{ */
576#define ADC_CFG1_ADICLK_MASK (0x3U)
577#define ADC_CFG1_ADICLK_SHIFT (0U)
578/*! ADICLK - Input Clock Select
579 * 0b00..Bus clock
580 * 0b01..Alternate clock 2 (ALTCLK2)
581 * 0b10..Alternate clock (ALTCLK)
582 * 0b11..Asynchronous clock (ADACK)
583 */
584#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
585#define ADC_CFG1_MODE_MASK (0xCU)
586#define ADC_CFG1_MODE_SHIFT (2U)
587/*! MODE - Conversion mode selection
588 * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
589 * 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
590 * 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
591 * 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
592 */
593#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
594#define ADC_CFG1_ADLSMP_MASK (0x10U)
595#define ADC_CFG1_ADLSMP_SHIFT (4U)
596/*! ADLSMP - Sample Time Configuration
597 * 0b0..Short sample time.
598 * 0b1..Long sample time.
599 */
600#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
601#define ADC_CFG1_ADIV_MASK (0x60U)
602#define ADC_CFG1_ADIV_SHIFT (5U)
603/*! ADIV - Clock Divide Select
604 * 0b00..The divide ratio is 1 and the clock rate is input clock.
605 * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2.
606 * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4.
607 * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.
608 */
609#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
610#define ADC_CFG1_ADLPC_MASK (0x80U)
611#define ADC_CFG1_ADLPC_SHIFT (7U)
612/*! ADLPC - Low-Power Configuration
613 * 0b0..Normal power configuration.
614 * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.
615 */
616#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
617/*! @} */
618
619/*! @name CFG2 - ADC Configuration Register 2 */
620/*! @{ */
621#define ADC_CFG2_ADLSTS_MASK (0x3U)
622#define ADC_CFG2_ADLSTS_SHIFT (0U)
623/*! ADLSTS - Long Sample Time Select
624 * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
625 * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time.
626 * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time.
627 * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.
628 */
629#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
630#define ADC_CFG2_ADHSC_MASK (0x4U)
631#define ADC_CFG2_ADHSC_SHIFT (2U)
632/*! ADHSC - High-Speed Configuration
633 * 0b0..Normal conversion sequence selected.
634 * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
635 */
636#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
637#define ADC_CFG2_ADACKEN_MASK (0x8U)
638#define ADC_CFG2_ADACKEN_SHIFT (3U)
639/*! ADACKEN - Asynchronous Clock Output Enable
640 * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
641 * 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.
642 */
643#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
644#define ADC_CFG2_MUXSEL_MASK (0x10U)
645#define ADC_CFG2_MUXSEL_SHIFT (4U)
646/*! MUXSEL - ADC Mux Select
647 * 0b0..ADxxa channels are selected.
648 * 0b1..ADxxb channels are selected.
649 */
650#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
651/*! @} */
652
653/*! @name R - ADC Data Result Register */
654/*! @{ */
655#define ADC_R_D_MASK (0xFFFFU)
656#define ADC_R_D_SHIFT (0U)
657#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
658/*! @} */
659
660/* The count of ADC_R */
661#define ADC_R_COUNT (2U)
662
663/*! @name CV1 - Compare Value Registers */
664/*! @{ */
665#define ADC_CV1_CV_MASK (0xFFFFU)
666#define ADC_CV1_CV_SHIFT (0U)
667#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
668/*! @} */
669
670/*! @name CV2 - Compare Value Registers */
671/*! @{ */
672#define ADC_CV2_CV_MASK (0xFFFFU)
673#define ADC_CV2_CV_SHIFT (0U)
674#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
675/*! @} */
676
677/*! @name SC2 - Status and Control Register 2 */
678/*! @{ */
679#define ADC_SC2_REFSEL_MASK (0x3U)
680#define ADC_SC2_REFSEL_SHIFT (0U)
681/*! REFSEL - Voltage Reference Selection
682 * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL
683 * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
684 * 0b10..Reserved
685 * 0b11..Reserved
686 */
687#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
688#define ADC_SC2_DMAEN_MASK (0x4U)
689#define ADC_SC2_DMAEN_SHIFT (2U)
690/*! DMAEN - DMA Enable
691 * 0b0..DMA is disabled.
692 * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
693 */
694#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
695#define ADC_SC2_ACREN_MASK (0x8U)
696#define ADC_SC2_ACREN_SHIFT (3U)
697/*! ACREN - Compare Function Range Enable
698 * 0b0..Range function disabled. Only CV1 is compared.
699 * 0b1..Range function enabled. Both CV1 and CV2 are compared.
700 */
701#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
702#define ADC_SC2_ACFGT_MASK (0x10U)
703#define ADC_SC2_ACFGT_SHIFT (4U)
704/*! ACFGT - Compare Function Greater Than Enable
705 * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
706 * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
707 */
708#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
709#define ADC_SC2_ACFE_MASK (0x20U)
710#define ADC_SC2_ACFE_SHIFT (5U)
711/*! ACFE - Compare Function Enable
712 * 0b0..Compare function disabled.
713 * 0b1..Compare function enabled.
714 */
715#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
716#define ADC_SC2_ADTRG_MASK (0x40U)
717#define ADC_SC2_ADTRG_SHIFT (6U)
718/*! ADTRG - Conversion Trigger Select
719 * 0b0..Software trigger selected.
720 * 0b1..Hardware trigger selected.
721 */
722#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
723#define ADC_SC2_ADACT_MASK (0x80U)
724#define ADC_SC2_ADACT_SHIFT (7U)
725/*! ADACT - Conversion Active
726 * 0b0..Conversion not in progress.
727 * 0b1..Conversion in progress.
728 */
729#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
730/*! @} */
731
732/*! @name SC3 - Status and Control Register 3 */
733/*! @{ */
734#define ADC_SC3_AVGS_MASK (0x3U)
735#define ADC_SC3_AVGS_SHIFT (0U)
736/*! AVGS - Hardware Average Select
737 * 0b00..4 samples averaged.
738 * 0b01..8 samples averaged.
739 * 0b10..16 samples averaged.
740 * 0b11..32 samples averaged.
741 */
742#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
743#define ADC_SC3_AVGE_MASK (0x4U)
744#define ADC_SC3_AVGE_SHIFT (2U)
745/*! AVGE - Hardware Average Enable
746 * 0b0..Hardware average function disabled.
747 * 0b1..Hardware average function enabled.
748 */
749#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
750#define ADC_SC3_ADCO_MASK (0x8U)
751#define ADC_SC3_ADCO_SHIFT (3U)
752/*! ADCO - Continuous Conversion Enable
753 * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
754 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
755 */
756#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
757#define ADC_SC3_CALF_MASK (0x40U)
758#define ADC_SC3_CALF_SHIFT (6U)
759/*! CALF - Calibration Failed Flag
760 * 0b0..Calibration completed normally.
761 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
762 */
763#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
764#define ADC_SC3_CAL_MASK (0x80U)
765#define ADC_SC3_CAL_SHIFT (7U)
766#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
767/*! @} */
768
769/*! @name OFS - ADC Offset Correction Register */
770/*! @{ */
771#define ADC_OFS_OFS_MASK (0xFFFFU)
772#define ADC_OFS_OFS_SHIFT (0U)
773#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
774/*! @} */
775
776/*! @name PG - ADC Plus-Side Gain Register */
777/*! @{ */
778#define ADC_PG_PG_MASK (0xFFFFU)
779#define ADC_PG_PG_SHIFT (0U)
780#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
781/*! @} */
782
783/*! @name MG - ADC Minus-Side Gain Register */
784/*! @{ */
785#define ADC_MG_MG_MASK (0xFFFFU)
786#define ADC_MG_MG_SHIFT (0U)
787#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
788/*! @} */
789
790/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
791/*! @{ */
792#define ADC_CLPD_CLPD_MASK (0x3FU)
793#define ADC_CLPD_CLPD_SHIFT (0U)
794#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
795/*! @} */
796
797/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
798/*! @{ */
799#define ADC_CLPS_CLPS_MASK (0x3FU)
800#define ADC_CLPS_CLPS_SHIFT (0U)
801#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
802/*! @} */
803
804/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
805/*! @{ */
806#define ADC_CLP4_CLP4_MASK (0x3FFU)
807#define ADC_CLP4_CLP4_SHIFT (0U)
808#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
809/*! @} */
810
811/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
812/*! @{ */
813#define ADC_CLP3_CLP3_MASK (0x1FFU)
814#define ADC_CLP3_CLP3_SHIFT (0U)
815#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
816/*! @} */
817
818/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
819/*! @{ */
820#define ADC_CLP2_CLP2_MASK (0xFFU)
821#define ADC_CLP2_CLP2_SHIFT (0U)
822#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
823/*! @} */
824
825/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
826/*! @{ */
827#define ADC_CLP1_CLP1_MASK (0x7FU)
828#define ADC_CLP1_CLP1_SHIFT (0U)
829#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
830/*! @} */
831
832/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
833/*! @{ */
834#define ADC_CLP0_CLP0_MASK (0x3FU)
835#define ADC_CLP0_CLP0_SHIFT (0U)
836#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
837/*! @} */
838
839/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
840/*! @{ */
841#define ADC_CLMD_CLMD_MASK (0x3FU)
842#define ADC_CLMD_CLMD_SHIFT (0U)
843#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
844/*! @} */
845
846/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
847/*! @{ */
848#define ADC_CLMS_CLMS_MASK (0x3FU)
849#define ADC_CLMS_CLMS_SHIFT (0U)
850#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
851/*! @} */
852
853/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
854/*! @{ */
855#define ADC_CLM4_CLM4_MASK (0x3FFU)
856#define ADC_CLM4_CLM4_SHIFT (0U)
857#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
858/*! @} */
859
860/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
861/*! @{ */
862#define ADC_CLM3_CLM3_MASK (0x1FFU)
863#define ADC_CLM3_CLM3_SHIFT (0U)
864#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
865/*! @} */
866
867/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
868/*! @{ */
869#define ADC_CLM2_CLM2_MASK (0xFFU)
870#define ADC_CLM2_CLM2_SHIFT (0U)
871#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
872/*! @} */
873
874/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
875/*! @{ */
876#define ADC_CLM1_CLM1_MASK (0x7FU)
877#define ADC_CLM1_CLM1_SHIFT (0U)
878#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
879/*! @} */
880
881/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
882/*! @{ */
883#define ADC_CLM0_CLM0_MASK (0x3FU)
884#define ADC_CLM0_CLM0_SHIFT (0U)
885#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
886/*! @} */
887
888
889/*!
890 * @}
891 */ /* end of group ADC_Register_Masks */
892
893
894/* ADC - Peripheral instance base addresses */
895/** Peripheral ADC0 base address */
896#define ADC0_BASE (0x4003B000u)
897/** Peripheral ADC0 base pointer */
898#define ADC0 ((ADC_Type *)ADC0_BASE)
899/** Array initializer of ADC peripheral base addresses */
900#define ADC_BASE_ADDRS { ADC0_BASE }
901/** Array initializer of ADC peripheral base pointers */
902#define ADC_BASE_PTRS { ADC0 }
903/** Interrupt vectors for the ADC peripheral type */
904#define ADC_IRQS { ADC0_IRQn }
905
906/*!
907 * @}
908 */ /* end of group ADC_Peripheral_Access_Layer */
909
910
911/* ----------------------------------------------------------------------------
912 -- AIPS Peripheral Access Layer
913 ---------------------------------------------------------------------------- */
914
915/*!
916 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
917 * @{
918 */
919
920/** AIPS - Register Layout Typedef */
921typedef struct {
922 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
923 uint8_t RESERVED_0[28];
924 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
925 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
926 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
927 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
928 uint8_t RESERVED_1[16];
929 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
930 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
931 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
932 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
933 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
934 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
935 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
936 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
937 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
938 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
939 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
940 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
941} AIPS_Type;
942
943/* ----------------------------------------------------------------------------
944 -- AIPS Register Masks
945 ---------------------------------------------------------------------------- */
946
947/*!
948 * @addtogroup AIPS_Register_Masks AIPS Register Masks
949 * @{
950 */
951
952/*! @name MPRA - Master Privilege Register A */
953/*! @{ */
954#define AIPS_MPRA_MPL4_MASK (0x1000U)
955#define AIPS_MPRA_MPL4_SHIFT (12U)
956/*! MPL4 - Master 4 Privilege Level
957 * 0b0..Accesses from this master are forced to user-mode.
958 * 0b1..Accesses from this master are not forced to user-mode.
959 */
960#define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
961#define AIPS_MPRA_MTW4_MASK (0x2000U)
962#define AIPS_MPRA_MTW4_SHIFT (13U)
963/*! MTW4 - Master 4 Trusted For Writes
964 * 0b0..This master is not trusted for write accesses.
965 * 0b1..This master is trusted for write accesses.
966 */
967#define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
968#define AIPS_MPRA_MTR4_MASK (0x4000U)
969#define AIPS_MPRA_MTR4_SHIFT (14U)
970/*! MTR4 - Master 4 Trusted For Read
971 * 0b0..This master is not trusted for read accesses.
972 * 0b1..This master is trusted for read accesses.
973 */
974#define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
975#define AIPS_MPRA_MPL3_MASK (0x10000U)
976#define AIPS_MPRA_MPL3_SHIFT (16U)
977/*! MPL3 - Master 3 Privilege Level
978 * 0b0..Accesses from this master are forced to user-mode.
979 * 0b1..Accesses from this master are not forced to user-mode.
980 */
981#define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
982#define AIPS_MPRA_MTW3_MASK (0x20000U)
983#define AIPS_MPRA_MTW3_SHIFT (17U)
984/*! MTW3 - Master 3 Trusted For Writes
985 * 0b0..This master is not trusted for write accesses.
986 * 0b1..This master is trusted for write accesses.
987 */
988#define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
989#define AIPS_MPRA_MTR3_MASK (0x40000U)
990#define AIPS_MPRA_MTR3_SHIFT (18U)
991/*! MTR3 - Master 3 Trusted For Read
992 * 0b0..This master is not trusted for read accesses.
993 * 0b1..This master is trusted for read accesses.
994 */
995#define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
996#define AIPS_MPRA_MPL2_MASK (0x100000U)
997#define AIPS_MPRA_MPL2_SHIFT (20U)
998/*! MPL2 - Master 2 Privilege Level
999 * 0b0..Accesses from this master are forced to user-mode.
1000 * 0b1..Accesses from this master are not forced to user-mode.
1001 */
1002#define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
1003#define AIPS_MPRA_MTW2_MASK (0x200000U)
1004#define AIPS_MPRA_MTW2_SHIFT (21U)
1005/*! MTW2 - Master 2 Trusted For Writes
1006 * 0b0..This master is not trusted for write accesses.
1007 * 0b1..This master is trusted for write accesses.
1008 */
1009#define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
1010#define AIPS_MPRA_MTR2_MASK (0x400000U)
1011#define AIPS_MPRA_MTR2_SHIFT (22U)
1012/*! MTR2 - Master 2 Trusted For Read
1013 * 0b0..This master is not trusted for read accesses.
1014 * 0b1..This master is trusted for read accesses.
1015 */
1016#define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
1017#define AIPS_MPRA_MPL1_MASK (0x1000000U)
1018#define AIPS_MPRA_MPL1_SHIFT (24U)
1019/*! MPL1 - Master 1 Privilege Level
1020 * 0b0..Accesses from this master are forced to user-mode.
1021 * 0b1..Accesses from this master are not forced to user-mode.
1022 */
1023#define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
1024#define AIPS_MPRA_MTW1_MASK (0x2000000U)
1025#define AIPS_MPRA_MTW1_SHIFT (25U)
1026/*! MTW1 - Master 1 Trusted for Writes
1027 * 0b0..This master is not trusted for write accesses.
1028 * 0b1..This master is trusted for write accesses.
1029 */
1030#define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
1031#define AIPS_MPRA_MTR1_MASK (0x4000000U)
1032#define AIPS_MPRA_MTR1_SHIFT (26U)
1033/*! MTR1 - Master 1 Trusted for Read
1034 * 0b0..This master is not trusted for read accesses.
1035 * 0b1..This master is trusted for read accesses.
1036 */
1037#define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
1038#define AIPS_MPRA_MPL0_MASK (0x10000000U)
1039#define AIPS_MPRA_MPL0_SHIFT (28U)
1040/*! MPL0 - Master 0 Privilege Level
1041 * 0b0..Accesses from this master are forced to user-mode.
1042 * 0b1..Accesses from this master are not forced to user-mode.
1043 */
1044#define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
1045#define AIPS_MPRA_MTW0_MASK (0x20000000U)
1046#define AIPS_MPRA_MTW0_SHIFT (29U)
1047/*! MTW0 - Master 0 Trusted For Writes
1048 * 0b0..This master is not trusted for write accesses.
1049 * 0b1..This master is trusted for write accesses.
1050 */
1051#define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
1052#define AIPS_MPRA_MTR0_MASK (0x40000000U)
1053#define AIPS_MPRA_MTR0_SHIFT (30U)
1054/*! MTR0 - Master 0 Trusted For Read
1055 * 0b0..This master is not trusted for read accesses.
1056 * 0b1..This master is trusted for read accesses.
1057 */
1058#define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
1059/*! @} */
1060
1061/*! @name PACRA - Peripheral Access Control Register */
1062/*! @{ */
1063#define AIPS_PACRA_TP7_MASK (0x1U)
1064#define AIPS_PACRA_TP7_SHIFT (0U)
1065/*! TP7 - Trusted Protect
1066 * 0b0..Accesses from an untrusted master are allowed.
1067 * 0b1..Accesses from an untrusted master are not allowed.
1068 */
1069#define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
1070#define AIPS_PACRA_WP7_MASK (0x2U)
1071#define AIPS_PACRA_WP7_SHIFT (1U)
1072/*! WP7 - Write Protect
1073 * 0b0..This peripheral allows write accesses.
1074 * 0b1..This peripheral is write protected.
1075 */
1076#define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
1077#define AIPS_PACRA_SP7_MASK (0x4U)
1078#define AIPS_PACRA_SP7_SHIFT (2U)
1079/*! SP7 - Supervisor Protect
1080 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1081 * 0b1..This peripheral requires supervisor privilege level for accesses.
1082 */
1083#define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
1084#define AIPS_PACRA_TP6_MASK (0x10U)
1085#define AIPS_PACRA_TP6_SHIFT (4U)
1086/*! TP6 - Trusted Protect
1087 * 0b0..Accesses from an untrusted master are allowed.
1088 * 0b1..Accesses from an untrusted master are not allowed.
1089 */
1090#define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
1091#define AIPS_PACRA_WP6_MASK (0x20U)
1092#define AIPS_PACRA_WP6_SHIFT (5U)
1093/*! WP6 - Write Protect
1094 * 0b0..This peripheral allows write accesses.
1095 * 0b1..This peripheral is write protected.
1096 */
1097#define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
1098#define AIPS_PACRA_SP6_MASK (0x40U)
1099#define AIPS_PACRA_SP6_SHIFT (6U)
1100/*! SP6 - Supervisor Protect
1101 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1102 * 0b1..This peripheral requires supervisor privilege level for accesses.
1103 */
1104#define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
1105#define AIPS_PACRA_TP5_MASK (0x100U)
1106#define AIPS_PACRA_TP5_SHIFT (8U)
1107/*! TP5 - Trusted Protect
1108 * 0b0..Accesses from an untrusted master are allowed.
1109 * 0b1..Accesses from an untrusted master are not allowed.
1110 */
1111#define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
1112#define AIPS_PACRA_WP5_MASK (0x200U)
1113#define AIPS_PACRA_WP5_SHIFT (9U)
1114/*! WP5 - Write Protect
1115 * 0b0..This peripheral allows write accesses.
1116 * 0b1..This peripheral is write protected.
1117 */
1118#define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
1119#define AIPS_PACRA_SP5_MASK (0x400U)
1120#define AIPS_PACRA_SP5_SHIFT (10U)
1121/*! SP5 - Supervisor Protect
1122 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1123 * 0b1..This peripheral requires supervisor privilege level for accesses.
1124 */
1125#define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
1126#define AIPS_PACRA_TP4_MASK (0x1000U)
1127#define AIPS_PACRA_TP4_SHIFT (12U)
1128/*! TP4 - Trusted Protect
1129 * 0b0..Accesses from an untrusted master are allowed.
1130 * 0b1..Accesses from an untrusted master are not allowed.
1131 */
1132#define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
1133#define AIPS_PACRA_WP4_MASK (0x2000U)
1134#define AIPS_PACRA_WP4_SHIFT (13U)
1135/*! WP4 - Write Protect
1136 * 0b0..This peripheral allows write accesses.
1137 * 0b1..This peripheral is write protected.
1138 */
1139#define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
1140#define AIPS_PACRA_SP4_MASK (0x4000U)
1141#define AIPS_PACRA_SP4_SHIFT (14U)
1142/*! SP4 - Supervisor Protect
1143 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1144 * 0b1..This peripheral requires supervisor privilege level for accesses.
1145 */
1146#define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
1147#define AIPS_PACRA_TP3_MASK (0x10000U)
1148#define AIPS_PACRA_TP3_SHIFT (16U)
1149/*! TP3 - Trusted Protect
1150 * 0b0..Accesses from an untrusted master are allowed.
1151 * 0b1..Accesses from an untrusted master are not allowed.
1152 */
1153#define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
1154#define AIPS_PACRA_WP3_MASK (0x20000U)
1155#define AIPS_PACRA_WP3_SHIFT (17U)
1156/*! WP3 - Write Protect
1157 * 0b0..This peripheral allows write accesses.
1158 * 0b1..This peripheral is write protected.
1159 */
1160#define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
1161#define AIPS_PACRA_SP3_MASK (0x40000U)
1162#define AIPS_PACRA_SP3_SHIFT (18U)
1163/*! SP3 - Supervisor Protect
1164 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1165 * 0b1..This peripheral requires supervisor privilege level for accesses.
1166 */
1167#define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
1168#define AIPS_PACRA_TP2_MASK (0x100000U)
1169#define AIPS_PACRA_TP2_SHIFT (20U)
1170/*! TP2 - Trusted Protect
1171 * 0b0..Accesses from an untrusted master are allowed.
1172 * 0b1..Accesses from an untrusted master are not allowed.
1173 */
1174#define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
1175#define AIPS_PACRA_WP2_MASK (0x200000U)
1176#define AIPS_PACRA_WP2_SHIFT (21U)
1177/*! WP2 - Write Protect
1178 * 0b0..This peripheral allows write accesses.
1179 * 0b1..This peripheral is write protected.
1180 */
1181#define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
1182#define AIPS_PACRA_SP2_MASK (0x400000U)
1183#define AIPS_PACRA_SP2_SHIFT (22U)
1184/*! SP2 - Supervisor Protect
1185 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1186 * 0b1..This peripheral requires supervisor privilege level for accesses.
1187 */
1188#define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
1189#define AIPS_PACRA_TP1_MASK (0x1000000U)
1190#define AIPS_PACRA_TP1_SHIFT (24U)
1191/*! TP1 - Trusted Protect
1192 * 0b0..Accesses from an untrusted master are allowed.
1193 * 0b1..Accesses from an untrusted master are not allowed.
1194 */
1195#define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
1196#define AIPS_PACRA_WP1_MASK (0x2000000U)
1197#define AIPS_PACRA_WP1_SHIFT (25U)
1198/*! WP1 - Write Protect
1199 * 0b0..This peripheral allows write accesses.
1200 * 0b1..This peripheral is write protected.
1201 */
1202#define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
1203#define AIPS_PACRA_SP1_MASK (0x4000000U)
1204#define AIPS_PACRA_SP1_SHIFT (26U)
1205/*! SP1 - Supervisor Protect
1206 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1207 * 0b1..This peripheral requires supervisor privilege level for accesses.
1208 */
1209#define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
1210#define AIPS_PACRA_TP0_MASK (0x10000000U)
1211#define AIPS_PACRA_TP0_SHIFT (28U)
1212/*! TP0 - Trusted Protect
1213 * 0b0..Accesses from an untrusted master are allowed.
1214 * 0b1..Accesses from an untrusted master are not allowed.
1215 */
1216#define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
1217#define AIPS_PACRA_WP0_MASK (0x20000000U)
1218#define AIPS_PACRA_WP0_SHIFT (29U)
1219/*! WP0 - Write Protect
1220 * 0b0..This peripheral allows write accesses.
1221 * 0b1..This peripheral is write protected.
1222 */
1223#define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
1224#define AIPS_PACRA_SP0_MASK (0x40000000U)
1225#define AIPS_PACRA_SP0_SHIFT (30U)
1226/*! SP0 - Supervisor Protect
1227 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1228 * 0b1..This peripheral requires supervisor privilege level for accesses.
1229 */
1230#define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
1231/*! @} */
1232
1233/*! @name PACRB - Peripheral Access Control Register */
1234/*! @{ */
1235#define AIPS_PACRB_TP7_MASK (0x1U)
1236#define AIPS_PACRB_TP7_SHIFT (0U)
1237/*! TP7 - Trusted Protect
1238 * 0b0..Accesses from an untrusted master are allowed.
1239 * 0b1..Accesses from an untrusted master are not allowed.
1240 */
1241#define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
1242#define AIPS_PACRB_WP7_MASK (0x2U)
1243#define AIPS_PACRB_WP7_SHIFT (1U)
1244/*! WP7 - Write Protect
1245 * 0b0..This peripheral allows write accesses.
1246 * 0b1..This peripheral is write protected.
1247 */
1248#define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
1249#define AIPS_PACRB_SP7_MASK (0x4U)
1250#define AIPS_PACRB_SP7_SHIFT (2U)
1251/*! SP7 - Supervisor Protect
1252 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1253 * 0b1..This peripheral requires supervisor privilege level for accesses.
1254 */
1255#define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
1256#define AIPS_PACRB_TP6_MASK (0x10U)
1257#define AIPS_PACRB_TP6_SHIFT (4U)
1258/*! TP6 - Trusted Protect
1259 * 0b0..Accesses from an untrusted master are allowed.
1260 * 0b1..Accesses from an untrusted master are not allowed.
1261 */
1262#define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
1263#define AIPS_PACRB_WP6_MASK (0x20U)
1264#define AIPS_PACRB_WP6_SHIFT (5U)
1265/*! WP6 - Write Protect
1266 * 0b0..This peripheral allows write accesses.
1267 * 0b1..This peripheral is write protected.
1268 */
1269#define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
1270#define AIPS_PACRB_SP6_MASK (0x40U)
1271#define AIPS_PACRB_SP6_SHIFT (6U)
1272/*! SP6 - Supervisor Protect
1273 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1274 * 0b1..This peripheral requires supervisor privilege level for accesses.
1275 */
1276#define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
1277#define AIPS_PACRB_TP5_MASK (0x100U)
1278#define AIPS_PACRB_TP5_SHIFT (8U)
1279/*! TP5 - Trusted Protect
1280 * 0b0..Accesses from an untrusted master are allowed.
1281 * 0b1..Accesses from an untrusted master are not allowed.
1282 */
1283#define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
1284#define AIPS_PACRB_WP5_MASK (0x200U)
1285#define AIPS_PACRB_WP5_SHIFT (9U)
1286/*! WP5 - Write Protect
1287 * 0b0..This peripheral allows write accesses.
1288 * 0b1..This peripheral is write protected.
1289 */
1290#define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
1291#define AIPS_PACRB_SP5_MASK (0x400U)
1292#define AIPS_PACRB_SP5_SHIFT (10U)
1293/*! SP5 - Supervisor Protect
1294 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1295 * 0b1..This peripheral requires supervisor privilege level for accesses.
1296 */
1297#define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
1298#define AIPS_PACRB_TP4_MASK (0x1000U)
1299#define AIPS_PACRB_TP4_SHIFT (12U)
1300/*! TP4 - Trusted Protect
1301 * 0b0..Accesses from an untrusted master are allowed.
1302 * 0b1..Accesses from an untrusted master are not allowed.
1303 */
1304#define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
1305#define AIPS_PACRB_WP4_MASK (0x2000U)
1306#define AIPS_PACRB_WP4_SHIFT (13U)
1307/*! WP4 - Write Protect
1308 * 0b0..This peripheral allows write accesses.
1309 * 0b1..This peripheral is write protected.
1310 */
1311#define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
1312#define AIPS_PACRB_SP4_MASK (0x4000U)
1313#define AIPS_PACRB_SP4_SHIFT (14U)
1314/*! SP4 - Supervisor Protect
1315 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1316 * 0b1..This peripheral requires supervisor privilege level for accesses.
1317 */
1318#define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
1319#define AIPS_PACRB_TP3_MASK (0x10000U)
1320#define AIPS_PACRB_TP3_SHIFT (16U)
1321/*! TP3 - Trusted Protect
1322 * 0b0..Accesses from an untrusted master are allowed.
1323 * 0b1..Accesses from an untrusted master are not allowed.
1324 */
1325#define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
1326#define AIPS_PACRB_WP3_MASK (0x20000U)
1327#define AIPS_PACRB_WP3_SHIFT (17U)
1328/*! WP3 - Write Protect
1329 * 0b0..This peripheral allows write accesses.
1330 * 0b1..This peripheral is write protected.
1331 */
1332#define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
1333#define AIPS_PACRB_SP3_MASK (0x40000U)
1334#define AIPS_PACRB_SP3_SHIFT (18U)
1335/*! SP3 - Supervisor Protect
1336 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1337 * 0b1..This peripheral requires supervisor privilege level for accesses.
1338 */
1339#define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
1340#define AIPS_PACRB_TP2_MASK (0x100000U)
1341#define AIPS_PACRB_TP2_SHIFT (20U)
1342/*! TP2 - Trusted Protect
1343 * 0b0..Accesses from an untrusted master are allowed.
1344 * 0b1..Accesses from an untrusted master are not allowed.
1345 */
1346#define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
1347#define AIPS_PACRB_WP2_MASK (0x200000U)
1348#define AIPS_PACRB_WP2_SHIFT (21U)
1349/*! WP2 - Write Protect
1350 * 0b0..This peripheral allows write accesses.
1351 * 0b1..This peripheral is write protected.
1352 */
1353#define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
1354#define AIPS_PACRB_SP2_MASK (0x400000U)
1355#define AIPS_PACRB_SP2_SHIFT (22U)
1356/*! SP2 - Supervisor Protect
1357 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1358 * 0b1..This peripheral requires supervisor privilege level for accesses.
1359 */
1360#define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
1361#define AIPS_PACRB_TP1_MASK (0x1000000U)
1362#define AIPS_PACRB_TP1_SHIFT (24U)
1363/*! TP1 - Trusted Protect
1364 * 0b0..Accesses from an untrusted master are allowed.
1365 * 0b1..Accesses from an untrusted master are not allowed.
1366 */
1367#define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
1368#define AIPS_PACRB_WP1_MASK (0x2000000U)
1369#define AIPS_PACRB_WP1_SHIFT (25U)
1370/*! WP1 - Write Protect
1371 * 0b0..This peripheral allows write accesses.
1372 * 0b1..This peripheral is write protected.
1373 */
1374#define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
1375#define AIPS_PACRB_SP1_MASK (0x4000000U)
1376#define AIPS_PACRB_SP1_SHIFT (26U)
1377/*! SP1 - Supervisor Protect
1378 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1379 * 0b1..This peripheral requires supervisor privilege level for accesses.
1380 */
1381#define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
1382#define AIPS_PACRB_TP0_MASK (0x10000000U)
1383#define AIPS_PACRB_TP0_SHIFT (28U)
1384/*! TP0 - Trusted Protect
1385 * 0b0..Accesses from an untrusted master are allowed.
1386 * 0b1..Accesses from an untrusted master are not allowed.
1387 */
1388#define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
1389#define AIPS_PACRB_WP0_MASK (0x20000000U)
1390#define AIPS_PACRB_WP0_SHIFT (29U)
1391/*! WP0 - Write Protect
1392 * 0b0..This peripheral allows write accesses.
1393 * 0b1..This peripheral is write protected.
1394 */
1395#define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
1396#define AIPS_PACRB_SP0_MASK (0x40000000U)
1397#define AIPS_PACRB_SP0_SHIFT (30U)
1398/*! SP0 - Supervisor Protect
1399 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1400 * 0b1..This peripheral requires supervisor privilege level for accesses.
1401 */
1402#define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
1403/*! @} */
1404
1405/*! @name PACRC - Peripheral Access Control Register */
1406/*! @{ */
1407#define AIPS_PACRC_TP7_MASK (0x1U)
1408#define AIPS_PACRC_TP7_SHIFT (0U)
1409/*! TP7 - Trusted Protect
1410 * 0b0..Accesses from an untrusted master are allowed.
1411 * 0b1..Accesses from an untrusted master are not allowed.
1412 */
1413#define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
1414#define AIPS_PACRC_WP7_MASK (0x2U)
1415#define AIPS_PACRC_WP7_SHIFT (1U)
1416/*! WP7 - Write Protect
1417 * 0b0..This peripheral allows write accesses.
1418 * 0b1..This peripheral is write protected.
1419 */
1420#define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
1421#define AIPS_PACRC_SP7_MASK (0x4U)
1422#define AIPS_PACRC_SP7_SHIFT (2U)
1423/*! SP7 - Supervisor Protect
1424 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1425 * 0b1..This peripheral requires supervisor privilege level for accesses.
1426 */
1427#define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
1428#define AIPS_PACRC_TP6_MASK (0x10U)
1429#define AIPS_PACRC_TP6_SHIFT (4U)
1430/*! TP6 - Trusted Protect
1431 * 0b0..Accesses from an untrusted master are allowed.
1432 * 0b1..Accesses from an untrusted master are not allowed.
1433 */
1434#define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
1435#define AIPS_PACRC_WP6_MASK (0x20U)
1436#define AIPS_PACRC_WP6_SHIFT (5U)
1437/*! WP6 - Write Protect
1438 * 0b0..This peripheral allows write accesses.
1439 * 0b1..This peripheral is write protected.
1440 */
1441#define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
1442#define AIPS_PACRC_SP6_MASK (0x40U)
1443#define AIPS_PACRC_SP6_SHIFT (6U)
1444/*! SP6 - Supervisor Protect
1445 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1446 * 0b1..This peripheral requires supervisor privilege level for accesses.
1447 */
1448#define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
1449#define AIPS_PACRC_TP5_MASK (0x100U)
1450#define AIPS_PACRC_TP5_SHIFT (8U)
1451/*! TP5 - Trusted Protect
1452 * 0b0..Accesses from an untrusted master are allowed.
1453 * 0b1..Accesses from an untrusted master are not allowed.
1454 */
1455#define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
1456#define AIPS_PACRC_WP5_MASK (0x200U)
1457#define AIPS_PACRC_WP5_SHIFT (9U)
1458/*! WP5 - Write Protect
1459 * 0b0..This peripheral allows write accesses.
1460 * 0b1..This peripheral is write protected.
1461 */
1462#define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
1463#define AIPS_PACRC_SP5_MASK (0x400U)
1464#define AIPS_PACRC_SP5_SHIFT (10U)
1465/*! SP5 - Supervisor Protect
1466 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1467 * 0b1..This peripheral requires supervisor privilege level for accesses.
1468 */
1469#define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
1470#define AIPS_PACRC_TP4_MASK (0x1000U)
1471#define AIPS_PACRC_TP4_SHIFT (12U)
1472/*! TP4 - Trusted Protect
1473 * 0b0..Accesses from an untrusted master are allowed.
1474 * 0b1..Accesses from an untrusted master are not allowed.
1475 */
1476#define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
1477#define AIPS_PACRC_WP4_MASK (0x2000U)
1478#define AIPS_PACRC_WP4_SHIFT (13U)
1479/*! WP4 - Write Protect
1480 * 0b0..This peripheral allows write accesses.
1481 * 0b1..This peripheral is write protected.
1482 */
1483#define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
1484#define AIPS_PACRC_SP4_MASK (0x4000U)
1485#define AIPS_PACRC_SP4_SHIFT (14U)
1486/*! SP4 - Supervisor Protect
1487 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1488 * 0b1..This peripheral requires supervisor privilege level for accesses.
1489 */
1490#define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
1491#define AIPS_PACRC_TP3_MASK (0x10000U)
1492#define AIPS_PACRC_TP3_SHIFT (16U)
1493/*! TP3 - Trusted Protect
1494 * 0b0..Accesses from an untrusted master are allowed.
1495 * 0b1..Accesses from an untrusted master are not allowed.
1496 */
1497#define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
1498#define AIPS_PACRC_WP3_MASK (0x20000U)
1499#define AIPS_PACRC_WP3_SHIFT (17U)
1500/*! WP3 - Write Protect
1501 * 0b0..This peripheral allows write accesses.
1502 * 0b1..This peripheral is write protected.
1503 */
1504#define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
1505#define AIPS_PACRC_SP3_MASK (0x40000U)
1506#define AIPS_PACRC_SP3_SHIFT (18U)
1507/*! SP3 - Supervisor Protect
1508 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1509 * 0b1..This peripheral requires supervisor privilege level for accesses.
1510 */
1511#define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
1512#define AIPS_PACRC_TP2_MASK (0x100000U)
1513#define AIPS_PACRC_TP2_SHIFT (20U)
1514/*! TP2 - Trusted Protect
1515 * 0b0..Accesses from an untrusted master are allowed.
1516 * 0b1..Accesses from an untrusted master are not allowed.
1517 */
1518#define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
1519#define AIPS_PACRC_WP2_MASK (0x200000U)
1520#define AIPS_PACRC_WP2_SHIFT (21U)
1521/*! WP2 - Write Protect
1522 * 0b0..This peripheral allows write accesses.
1523 * 0b1..This peripheral is write protected.
1524 */
1525#define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
1526#define AIPS_PACRC_SP2_MASK (0x400000U)
1527#define AIPS_PACRC_SP2_SHIFT (22U)
1528/*! SP2 - Supervisor Protect
1529 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1530 * 0b1..This peripheral requires supervisor privilege level for accesses.
1531 */
1532#define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
1533#define AIPS_PACRC_TP1_MASK (0x1000000U)
1534#define AIPS_PACRC_TP1_SHIFT (24U)
1535/*! TP1 - Trusted Protect
1536 * 0b0..Accesses from an untrusted master are allowed.
1537 * 0b1..Accesses from an untrusted master are not allowed.
1538 */
1539#define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
1540#define AIPS_PACRC_WP1_MASK (0x2000000U)
1541#define AIPS_PACRC_WP1_SHIFT (25U)
1542/*! WP1 - Write Protect
1543 * 0b0..This peripheral allows write accesses.
1544 * 0b1..This peripheral is write protected.
1545 */
1546#define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
1547#define AIPS_PACRC_SP1_MASK (0x4000000U)
1548#define AIPS_PACRC_SP1_SHIFT (26U)
1549/*! SP1 - Supervisor Protect
1550 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1551 * 0b1..This peripheral requires supervisor privilege level for accesses.
1552 */
1553#define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
1554#define AIPS_PACRC_TP0_MASK (0x10000000U)
1555#define AIPS_PACRC_TP0_SHIFT (28U)
1556/*! TP0 - Trusted Protect
1557 * 0b0..Accesses from an untrusted master are allowed.
1558 * 0b1..Accesses from an untrusted master are not allowed.
1559 */
1560#define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
1561#define AIPS_PACRC_WP0_MASK (0x20000000U)
1562#define AIPS_PACRC_WP0_SHIFT (29U)
1563/*! WP0 - Write Protect
1564 * 0b0..This peripheral allows write accesses.
1565 * 0b1..This peripheral is write protected.
1566 */
1567#define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
1568#define AIPS_PACRC_SP0_MASK (0x40000000U)
1569#define AIPS_PACRC_SP0_SHIFT (30U)
1570/*! SP0 - Supervisor Protect
1571 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1572 * 0b1..This peripheral requires supervisor privilege level for accesses.
1573 */
1574#define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
1575/*! @} */
1576
1577/*! @name PACRD - Peripheral Access Control Register */
1578/*! @{ */
1579#define AIPS_PACRD_TP7_MASK (0x1U)
1580#define AIPS_PACRD_TP7_SHIFT (0U)
1581/*! TP7 - Trusted Protect
1582 * 0b0..Accesses from an untrusted master are allowed.
1583 * 0b1..Accesses from an untrusted master are not allowed.
1584 */
1585#define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
1586#define AIPS_PACRD_WP7_MASK (0x2U)
1587#define AIPS_PACRD_WP7_SHIFT (1U)
1588/*! WP7 - Write Protect
1589 * 0b0..This peripheral allows write accesses.
1590 * 0b1..This peripheral is write protected.
1591 */
1592#define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
1593#define AIPS_PACRD_SP7_MASK (0x4U)
1594#define AIPS_PACRD_SP7_SHIFT (2U)
1595/*! SP7 - Supervisor Protect
1596 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1597 * 0b1..This peripheral requires supervisor privilege level for accesses.
1598 */
1599#define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
1600#define AIPS_PACRD_TP6_MASK (0x10U)
1601#define AIPS_PACRD_TP6_SHIFT (4U)
1602/*! TP6 - Trusted Protect
1603 * 0b0..Accesses from an untrusted master are allowed.
1604 * 0b1..Accesses from an untrusted master are not allowed.
1605 */
1606#define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
1607#define AIPS_PACRD_WP6_MASK (0x20U)
1608#define AIPS_PACRD_WP6_SHIFT (5U)
1609/*! WP6 - Write Protect
1610 * 0b0..This peripheral allows write accesses.
1611 * 0b1..This peripheral is write protected.
1612 */
1613#define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
1614#define AIPS_PACRD_SP6_MASK (0x40U)
1615#define AIPS_PACRD_SP6_SHIFT (6U)
1616/*! SP6 - Supervisor Protect
1617 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1618 * 0b1..This peripheral requires supervisor privilege level for accesses.
1619 */
1620#define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
1621#define AIPS_PACRD_TP5_MASK (0x100U)
1622#define AIPS_PACRD_TP5_SHIFT (8U)
1623/*! TP5 - Trusted Protect
1624 * 0b0..Accesses from an untrusted master are allowed.
1625 * 0b1..Accesses from an untrusted master are not allowed.
1626 */
1627#define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
1628#define AIPS_PACRD_WP5_MASK (0x200U)
1629#define AIPS_PACRD_WP5_SHIFT (9U)
1630/*! WP5 - Write Protect
1631 * 0b0..This peripheral allows write accesses.
1632 * 0b1..This peripheral is write protected.
1633 */
1634#define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
1635#define AIPS_PACRD_SP5_MASK (0x400U)
1636#define AIPS_PACRD_SP5_SHIFT (10U)
1637/*! SP5 - Supervisor Protect
1638 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1639 * 0b1..This peripheral requires supervisor privilege level for accesses.
1640 */
1641#define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
1642#define AIPS_PACRD_TP4_MASK (0x1000U)
1643#define AIPS_PACRD_TP4_SHIFT (12U)
1644/*! TP4 - Trusted Protect
1645 * 0b0..Accesses from an untrusted master are allowed.
1646 * 0b1..Accesses from an untrusted master are not allowed.
1647 */
1648#define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
1649#define AIPS_PACRD_WP4_MASK (0x2000U)
1650#define AIPS_PACRD_WP4_SHIFT (13U)
1651/*! WP4 - Write Protect
1652 * 0b0..This peripheral allows write accesses.
1653 * 0b1..This peripheral is write protected.
1654 */
1655#define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
1656#define AIPS_PACRD_SP4_MASK (0x4000U)
1657#define AIPS_PACRD_SP4_SHIFT (14U)
1658/*! SP4 - Supervisor Protect
1659 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1660 * 0b1..This peripheral requires supervisor privilege level for accesses.
1661 */
1662#define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
1663#define AIPS_PACRD_TP3_MASK (0x10000U)
1664#define AIPS_PACRD_TP3_SHIFT (16U)
1665/*! TP3 - Trusted Protect
1666 * 0b0..Accesses from an untrusted master are allowed.
1667 * 0b1..Accesses from an untrusted master are not allowed.
1668 */
1669#define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
1670#define AIPS_PACRD_WP3_MASK (0x20000U)
1671#define AIPS_PACRD_WP3_SHIFT (17U)
1672/*! WP3 - Write Protect
1673 * 0b0..This peripheral allows write accesses.
1674 * 0b1..This peripheral is write protected.
1675 */
1676#define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
1677#define AIPS_PACRD_SP3_MASK (0x40000U)
1678#define AIPS_PACRD_SP3_SHIFT (18U)
1679/*! SP3 - Supervisor Protect
1680 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1681 * 0b1..This peripheral requires supervisor privilege level for accesses.
1682 */
1683#define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
1684#define AIPS_PACRD_TP2_MASK (0x100000U)
1685#define AIPS_PACRD_TP2_SHIFT (20U)
1686/*! TP2 - Trusted Protect
1687 * 0b0..Accesses from an untrusted master are allowed.
1688 * 0b1..Accesses from an untrusted master are not allowed.
1689 */
1690#define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
1691#define AIPS_PACRD_WP2_MASK (0x200000U)
1692#define AIPS_PACRD_WP2_SHIFT (21U)
1693/*! WP2 - Write Protect
1694 * 0b0..This peripheral allows write accesses.
1695 * 0b1..This peripheral is write protected.
1696 */
1697#define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
1698#define AIPS_PACRD_SP2_MASK (0x400000U)
1699#define AIPS_PACRD_SP2_SHIFT (22U)
1700/*! SP2 - Supervisor Protect
1701 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1702 * 0b1..This peripheral requires supervisor privilege level for accesses.
1703 */
1704#define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
1705#define AIPS_PACRD_TP1_MASK (0x1000000U)
1706#define AIPS_PACRD_TP1_SHIFT (24U)
1707/*! TP1 - Trusted Protect
1708 * 0b0..Accesses from an untrusted master are allowed.
1709 * 0b1..Accesses from an untrusted master are not allowed.
1710 */
1711#define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
1712#define AIPS_PACRD_WP1_MASK (0x2000000U)
1713#define AIPS_PACRD_WP1_SHIFT (25U)
1714/*! WP1 - Write Protect
1715 * 0b0..This peripheral allows write accesses.
1716 * 0b1..This peripheral is write protected.
1717 */
1718#define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
1719#define AIPS_PACRD_SP1_MASK (0x4000000U)
1720#define AIPS_PACRD_SP1_SHIFT (26U)
1721/*! SP1 - Supervisor Protect
1722 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1723 * 0b1..This peripheral requires supervisor privilege level for accesses.
1724 */
1725#define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
1726#define AIPS_PACRD_TP0_MASK (0x10000000U)
1727#define AIPS_PACRD_TP0_SHIFT (28U)
1728/*! TP0 - Trusted Protect
1729 * 0b0..Accesses from an untrusted master are allowed.
1730 * 0b1..Accesses from an untrusted master are not allowed.
1731 */
1732#define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
1733#define AIPS_PACRD_WP0_MASK (0x20000000U)
1734#define AIPS_PACRD_WP0_SHIFT (29U)
1735/*! WP0 - Write Protect
1736 * 0b0..This peripheral allows write accesses.
1737 * 0b1..This peripheral is write protected.
1738 */
1739#define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
1740#define AIPS_PACRD_SP0_MASK (0x40000000U)
1741#define AIPS_PACRD_SP0_SHIFT (30U)
1742/*! SP0 - Supervisor Protect
1743 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1744 * 0b1..This peripheral requires supervisor privilege level for accesses.
1745 */
1746#define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
1747/*! @} */
1748
1749/*! @name PACRE - Peripheral Access Control Register */
1750/*! @{ */
1751#define AIPS_PACRE_TP7_MASK (0x1U)
1752#define AIPS_PACRE_TP7_SHIFT (0U)
1753/*! TP7 - Trusted Protect
1754 * 0b0..Accesses from an untrusted master are allowed.
1755 * 0b1..Accesses from an untrusted master are not allowed.
1756 */
1757#define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
1758#define AIPS_PACRE_WP7_MASK (0x2U)
1759#define AIPS_PACRE_WP7_SHIFT (1U)
1760/*! WP7 - Write Protect
1761 * 0b0..This peripheral allows write accesses.
1762 * 0b1..This peripheral is write protected.
1763 */
1764#define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
1765#define AIPS_PACRE_SP7_MASK (0x4U)
1766#define AIPS_PACRE_SP7_SHIFT (2U)
1767/*! SP7 - Supervisor Protect
1768 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1769 * 0b1..This peripheral requires supervisor privilege level for accesses.
1770 */
1771#define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
1772#define AIPS_PACRE_TP6_MASK (0x10U)
1773#define AIPS_PACRE_TP6_SHIFT (4U)
1774/*! TP6 - Trusted Protect
1775 * 0b0..Accesses from an untrusted master are allowed.
1776 * 0b1..Accesses from an untrusted master are not allowed.
1777 */
1778#define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
1779#define AIPS_PACRE_WP6_MASK (0x20U)
1780#define AIPS_PACRE_WP6_SHIFT (5U)
1781/*! WP6 - Write Protect
1782 * 0b0..This peripheral allows write accesses.
1783 * 0b1..This peripheral is write protected.
1784 */
1785#define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
1786#define AIPS_PACRE_SP6_MASK (0x40U)
1787#define AIPS_PACRE_SP6_SHIFT (6U)
1788/*! SP6 - Supervisor Protect
1789 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1790 * 0b1..This peripheral requires supervisor privilege level for accesses.
1791 */
1792#define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
1793#define AIPS_PACRE_TP5_MASK (0x100U)
1794#define AIPS_PACRE_TP5_SHIFT (8U)
1795/*! TP5 - Trusted Protect
1796 * 0b0..Accesses from an untrusted master are allowed.
1797 * 0b1..Accesses from an untrusted master are not allowed.
1798 */
1799#define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
1800#define AIPS_PACRE_WP5_MASK (0x200U)
1801#define AIPS_PACRE_WP5_SHIFT (9U)
1802/*! WP5 - Write Protect
1803 * 0b0..This peripheral allows write accesses.
1804 * 0b1..This peripheral is write protected.
1805 */
1806#define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
1807#define AIPS_PACRE_SP5_MASK (0x400U)
1808#define AIPS_PACRE_SP5_SHIFT (10U)
1809/*! SP5 - Supervisor Protect
1810 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1811 * 0b1..This peripheral requires supervisor privilege level for accesses.
1812 */
1813#define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
1814#define AIPS_PACRE_TP4_MASK (0x1000U)
1815#define AIPS_PACRE_TP4_SHIFT (12U)
1816/*! TP4 - Trusted Protect
1817 * 0b0..Accesses from an untrusted master are allowed.
1818 * 0b1..Accesses from an untrusted master are not allowed.
1819 */
1820#define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
1821#define AIPS_PACRE_WP4_MASK (0x2000U)
1822#define AIPS_PACRE_WP4_SHIFT (13U)
1823/*! WP4 - Write Protect
1824 * 0b0..This peripheral allows write accesses.
1825 * 0b1..This peripheral is write protected.
1826 */
1827#define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
1828#define AIPS_PACRE_SP4_MASK (0x4000U)
1829#define AIPS_PACRE_SP4_SHIFT (14U)
1830/*! SP4 - Supervisor Protect
1831 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1832 * 0b1..This peripheral requires supervisor privilege level for accesses.
1833 */
1834#define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
1835#define AIPS_PACRE_TP3_MASK (0x10000U)
1836#define AIPS_PACRE_TP3_SHIFT (16U)
1837/*! TP3 - Trusted Protect
1838 * 0b0..Accesses from an untrusted master are allowed.
1839 * 0b1..Accesses from an untrusted master are not allowed.
1840 */
1841#define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
1842#define AIPS_PACRE_WP3_MASK (0x20000U)
1843#define AIPS_PACRE_WP3_SHIFT (17U)
1844/*! WP3 - Write Protect
1845 * 0b0..This peripheral allows write accesses.
1846 * 0b1..This peripheral is write protected.
1847 */
1848#define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
1849#define AIPS_PACRE_SP3_MASK (0x40000U)
1850#define AIPS_PACRE_SP3_SHIFT (18U)
1851/*! SP3 - Supervisor Protect
1852 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1853 * 0b1..This peripheral requires supervisor privilege level for accesses.
1854 */
1855#define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
1856#define AIPS_PACRE_TP2_MASK (0x100000U)
1857#define AIPS_PACRE_TP2_SHIFT (20U)
1858/*! TP2 - Trusted Protect
1859 * 0b0..Accesses from an untrusted master are allowed.
1860 * 0b1..Accesses from an untrusted master are not allowed.
1861 */
1862#define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
1863#define AIPS_PACRE_WP2_MASK (0x200000U)
1864#define AIPS_PACRE_WP2_SHIFT (21U)
1865/*! WP2 - Write Protect
1866 * 0b0..This peripheral allows write accesses.
1867 * 0b1..This peripheral is write protected.
1868 */
1869#define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
1870#define AIPS_PACRE_SP2_MASK (0x400000U)
1871#define AIPS_PACRE_SP2_SHIFT (22U)
1872/*! SP2 - Supervisor Protect
1873 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1874 * 0b1..This peripheral requires supervisor privilege level for accesses.
1875 */
1876#define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
1877#define AIPS_PACRE_TP1_MASK (0x1000000U)
1878#define AIPS_PACRE_TP1_SHIFT (24U)
1879/*! TP1 - Trusted Protect
1880 * 0b0..Accesses from an untrusted master are allowed.
1881 * 0b1..Accesses from an untrusted master are not allowed.
1882 */
1883#define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
1884#define AIPS_PACRE_WP1_MASK (0x2000000U)
1885#define AIPS_PACRE_WP1_SHIFT (25U)
1886/*! WP1 - Write Protect
1887 * 0b0..This peripheral allows write accesses.
1888 * 0b1..This peripheral is write protected.
1889 */
1890#define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
1891#define AIPS_PACRE_SP1_MASK (0x4000000U)
1892#define AIPS_PACRE_SP1_SHIFT (26U)
1893/*! SP1 - Supervisor Protect
1894 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1895 * 0b1..This peripheral requires supervisor privilege level for accesses.
1896 */
1897#define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
1898#define AIPS_PACRE_TP0_MASK (0x10000000U)
1899#define AIPS_PACRE_TP0_SHIFT (28U)
1900/*! TP0 - Trusted Protect
1901 * 0b0..Accesses from an untrusted master are allowed.
1902 * 0b1..Accesses from an untrusted master are not allowed.
1903 */
1904#define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
1905#define AIPS_PACRE_WP0_MASK (0x20000000U)
1906#define AIPS_PACRE_WP0_SHIFT (29U)
1907/*! WP0 - Write Protect
1908 * 0b0..This peripheral allows write accesses.
1909 * 0b1..This peripheral is write protected.
1910 */
1911#define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
1912#define AIPS_PACRE_SP0_MASK (0x40000000U)
1913#define AIPS_PACRE_SP0_SHIFT (30U)
1914/*! SP0 - Supervisor Protect
1915 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1916 * 0b1..This peripheral requires supervisor privilege level for accesses.
1917 */
1918#define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
1919/*! @} */
1920
1921/*! @name PACRF - Peripheral Access Control Register */
1922/*! @{ */
1923#define AIPS_PACRF_TP7_MASK (0x1U)
1924#define AIPS_PACRF_TP7_SHIFT (0U)
1925/*! TP7 - Trusted Protect
1926 * 0b0..Accesses from an untrusted master are allowed.
1927 * 0b1..Accesses from an untrusted master are not allowed.
1928 */
1929#define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
1930#define AIPS_PACRF_WP7_MASK (0x2U)
1931#define AIPS_PACRF_WP7_SHIFT (1U)
1932/*! WP7 - Write Protect
1933 * 0b0..This peripheral allows write accesses.
1934 * 0b1..This peripheral is write protected.
1935 */
1936#define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
1937#define AIPS_PACRF_SP7_MASK (0x4U)
1938#define AIPS_PACRF_SP7_SHIFT (2U)
1939/*! SP7 - Supervisor Protect
1940 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1941 * 0b1..This peripheral requires supervisor privilege level for accesses.
1942 */
1943#define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
1944#define AIPS_PACRF_TP6_MASK (0x10U)
1945#define AIPS_PACRF_TP6_SHIFT (4U)
1946/*! TP6 - Trusted Protect
1947 * 0b0..Accesses from an untrusted master are allowed.
1948 * 0b1..Accesses from an untrusted master are not allowed.
1949 */
1950#define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
1951#define AIPS_PACRF_WP6_MASK (0x20U)
1952#define AIPS_PACRF_WP6_SHIFT (5U)
1953/*! WP6 - Write Protect
1954 * 0b0..This peripheral allows write accesses.
1955 * 0b1..This peripheral is write protected.
1956 */
1957#define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
1958#define AIPS_PACRF_SP6_MASK (0x40U)
1959#define AIPS_PACRF_SP6_SHIFT (6U)
1960/*! SP6 - Supervisor Protect
1961 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1962 * 0b1..This peripheral requires supervisor privilege level for accesses.
1963 */
1964#define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
1965#define AIPS_PACRF_TP5_MASK (0x100U)
1966#define AIPS_PACRF_TP5_SHIFT (8U)
1967/*! TP5 - Trusted Protect
1968 * 0b0..Accesses from an untrusted master are allowed.
1969 * 0b1..Accesses from an untrusted master are not allowed.
1970 */
1971#define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
1972#define AIPS_PACRF_WP5_MASK (0x200U)
1973#define AIPS_PACRF_WP5_SHIFT (9U)
1974/*! WP5 - Write Protect
1975 * 0b0..This peripheral allows write accesses.
1976 * 0b1..This peripheral is write protected.
1977 */
1978#define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
1979#define AIPS_PACRF_SP5_MASK (0x400U)
1980#define AIPS_PACRF_SP5_SHIFT (10U)
1981/*! SP5 - Supervisor Protect
1982 * 0b0..This peripheral does not require supervisor privilege level for accesses.
1983 * 0b1..This peripheral requires supervisor privilege level for accesses.
1984 */
1985#define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
1986#define AIPS_PACRF_TP4_MASK (0x1000U)
1987#define AIPS_PACRF_TP4_SHIFT (12U)
1988/*! TP4 - Trusted Protect
1989 * 0b0..Accesses from an untrusted master are allowed.
1990 * 0b1..Accesses from an untrusted master are not allowed.
1991 */
1992#define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
1993#define AIPS_PACRF_WP4_MASK (0x2000U)
1994#define AIPS_PACRF_WP4_SHIFT (13U)
1995/*! WP4 - Write Protect
1996 * 0b0..This peripheral allows write accesses.
1997 * 0b1..This peripheral is write protected.
1998 */
1999#define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
2000#define AIPS_PACRF_SP4_MASK (0x4000U)
2001#define AIPS_PACRF_SP4_SHIFT (14U)
2002/*! SP4 - Supervisor Protect
2003 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2004 * 0b1..This peripheral requires supervisor privilege level for accesses.
2005 */
2006#define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
2007#define AIPS_PACRF_TP3_MASK (0x10000U)
2008#define AIPS_PACRF_TP3_SHIFT (16U)
2009/*! TP3 - Trusted Protect
2010 * 0b0..Accesses from an untrusted master are allowed.
2011 * 0b1..Accesses from an untrusted master are not allowed.
2012 */
2013#define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
2014#define AIPS_PACRF_WP3_MASK (0x20000U)
2015#define AIPS_PACRF_WP3_SHIFT (17U)
2016/*! WP3 - Write Protect
2017 * 0b0..This peripheral allows write accesses.
2018 * 0b1..This peripheral is write protected.
2019 */
2020#define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
2021#define AIPS_PACRF_SP3_MASK (0x40000U)
2022#define AIPS_PACRF_SP3_SHIFT (18U)
2023/*! SP3 - Supervisor Protect
2024 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2025 * 0b1..This peripheral requires supervisor privilege level for accesses.
2026 */
2027#define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
2028#define AIPS_PACRF_TP2_MASK (0x100000U)
2029#define AIPS_PACRF_TP2_SHIFT (20U)
2030/*! TP2 - Trusted Protect
2031 * 0b0..Accesses from an untrusted master are allowed.
2032 * 0b1..Accesses from an untrusted master are not allowed.
2033 */
2034#define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
2035#define AIPS_PACRF_WP2_MASK (0x200000U)
2036#define AIPS_PACRF_WP2_SHIFT (21U)
2037/*! WP2 - Write Protect
2038 * 0b0..This peripheral allows write accesses.
2039 * 0b1..This peripheral is write protected.
2040 */
2041#define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
2042#define AIPS_PACRF_SP2_MASK (0x400000U)
2043#define AIPS_PACRF_SP2_SHIFT (22U)
2044/*! SP2 - Supervisor Protect
2045 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2046 * 0b1..This peripheral requires supervisor privilege level for accesses.
2047 */
2048#define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
2049#define AIPS_PACRF_TP1_MASK (0x1000000U)
2050#define AIPS_PACRF_TP1_SHIFT (24U)
2051/*! TP1 - Trusted Protect
2052 * 0b0..Accesses from an untrusted master are allowed.
2053 * 0b1..Accesses from an untrusted master are not allowed.
2054 */
2055#define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
2056#define AIPS_PACRF_WP1_MASK (0x2000000U)
2057#define AIPS_PACRF_WP1_SHIFT (25U)
2058/*! WP1 - Write Protect
2059 * 0b0..This peripheral allows write accesses.
2060 * 0b1..This peripheral is write protected.
2061 */
2062#define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
2063#define AIPS_PACRF_SP1_MASK (0x4000000U)
2064#define AIPS_PACRF_SP1_SHIFT (26U)
2065/*! SP1 - Supervisor Protect
2066 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2067 * 0b1..This peripheral requires supervisor privilege level for accesses.
2068 */
2069#define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
2070#define AIPS_PACRF_TP0_MASK (0x10000000U)
2071#define AIPS_PACRF_TP0_SHIFT (28U)
2072/*! TP0 - Trusted Protect
2073 * 0b0..Accesses from an untrusted master are allowed.
2074 * 0b1..Accesses from an untrusted master are not allowed.
2075 */
2076#define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
2077#define AIPS_PACRF_WP0_MASK (0x20000000U)
2078#define AIPS_PACRF_WP0_SHIFT (29U)
2079/*! WP0 - Write Protect
2080 * 0b0..This peripheral allows write accesses.
2081 * 0b1..This peripheral is write protected.
2082 */
2083#define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
2084#define AIPS_PACRF_SP0_MASK (0x40000000U)
2085#define AIPS_PACRF_SP0_SHIFT (30U)
2086/*! SP0 - Supervisor Protect
2087 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2088 * 0b1..This peripheral requires supervisor privilege level for accesses.
2089 */
2090#define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
2091/*! @} */
2092
2093/*! @name PACRG - Peripheral Access Control Register */
2094/*! @{ */
2095#define AIPS_PACRG_TP7_MASK (0x1U)
2096#define AIPS_PACRG_TP7_SHIFT (0U)
2097/*! TP7 - Trusted Protect
2098 * 0b0..Accesses from an untrusted master are allowed.
2099 * 0b1..Accesses from an untrusted master are not allowed.
2100 */
2101#define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
2102#define AIPS_PACRG_WP7_MASK (0x2U)
2103#define AIPS_PACRG_WP7_SHIFT (1U)
2104/*! WP7 - Write Protect
2105 * 0b0..This peripheral allows write accesses.
2106 * 0b1..This peripheral is write protected.
2107 */
2108#define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
2109#define AIPS_PACRG_SP7_MASK (0x4U)
2110#define AIPS_PACRG_SP7_SHIFT (2U)
2111/*! SP7 - Supervisor Protect
2112 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2113 * 0b1..This peripheral requires supervisor privilege level for accesses.
2114 */
2115#define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
2116#define AIPS_PACRG_TP6_MASK (0x10U)
2117#define AIPS_PACRG_TP6_SHIFT (4U)
2118/*! TP6 - Trusted Protect
2119 * 0b0..Accesses from an untrusted master are allowed.
2120 * 0b1..Accesses from an untrusted master are not allowed.
2121 */
2122#define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
2123#define AIPS_PACRG_WP6_MASK (0x20U)
2124#define AIPS_PACRG_WP6_SHIFT (5U)
2125/*! WP6 - Write Protect
2126 * 0b0..This peripheral allows write accesses.
2127 * 0b1..This peripheral is write protected.
2128 */
2129#define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
2130#define AIPS_PACRG_SP6_MASK (0x40U)
2131#define AIPS_PACRG_SP6_SHIFT (6U)
2132/*! SP6 - Supervisor Protect
2133 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2134 * 0b1..This peripheral requires supervisor privilege level for accesses.
2135 */
2136#define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
2137#define AIPS_PACRG_TP5_MASK (0x100U)
2138#define AIPS_PACRG_TP5_SHIFT (8U)
2139/*! TP5 - Trusted Protect
2140 * 0b0..Accesses from an untrusted master are allowed.
2141 * 0b1..Accesses from an untrusted master are not allowed.
2142 */
2143#define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
2144#define AIPS_PACRG_WP5_MASK (0x200U)
2145#define AIPS_PACRG_WP5_SHIFT (9U)
2146/*! WP5 - Write Protect
2147 * 0b0..This peripheral allows write accesses.
2148 * 0b1..This peripheral is write protected.
2149 */
2150#define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
2151#define AIPS_PACRG_SP5_MASK (0x400U)
2152#define AIPS_PACRG_SP5_SHIFT (10U)
2153/*! SP5 - Supervisor Protect
2154 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2155 * 0b1..This peripheral requires supervisor privilege level for accesses.
2156 */
2157#define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
2158#define AIPS_PACRG_TP4_MASK (0x1000U)
2159#define AIPS_PACRG_TP4_SHIFT (12U)
2160/*! TP4 - Trusted Protect
2161 * 0b0..Accesses from an untrusted master are allowed.
2162 * 0b1..Accesses from an untrusted master are not allowed.
2163 */
2164#define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
2165#define AIPS_PACRG_WP4_MASK (0x2000U)
2166#define AIPS_PACRG_WP4_SHIFT (13U)
2167/*! WP4 - Write Protect
2168 * 0b0..This peripheral allows write accesses.
2169 * 0b1..This peripheral is write protected.
2170 */
2171#define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
2172#define AIPS_PACRG_SP4_MASK (0x4000U)
2173#define AIPS_PACRG_SP4_SHIFT (14U)
2174/*! SP4 - Supervisor Protect
2175 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2176 * 0b1..This peripheral requires supervisor privilege level for accesses.
2177 */
2178#define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
2179#define AIPS_PACRG_TP3_MASK (0x10000U)
2180#define AIPS_PACRG_TP3_SHIFT (16U)
2181/*! TP3 - Trusted Protect
2182 * 0b0..Accesses from an untrusted master are allowed.
2183 * 0b1..Accesses from an untrusted master are not allowed.
2184 */
2185#define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
2186#define AIPS_PACRG_WP3_MASK (0x20000U)
2187#define AIPS_PACRG_WP3_SHIFT (17U)
2188/*! WP3 - Write Protect
2189 * 0b0..This peripheral allows write accesses.
2190 * 0b1..This peripheral is write protected.
2191 */
2192#define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
2193#define AIPS_PACRG_SP3_MASK (0x40000U)
2194#define AIPS_PACRG_SP3_SHIFT (18U)
2195/*! SP3 - Supervisor Protect
2196 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2197 * 0b1..This peripheral requires supervisor privilege level for accesses.
2198 */
2199#define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
2200#define AIPS_PACRG_TP2_MASK (0x100000U)
2201#define AIPS_PACRG_TP2_SHIFT (20U)
2202/*! TP2 - Trusted Protect
2203 * 0b0..Accesses from an untrusted master are allowed.
2204 * 0b1..Accesses from an untrusted master are not allowed.
2205 */
2206#define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
2207#define AIPS_PACRG_WP2_MASK (0x200000U)
2208#define AIPS_PACRG_WP2_SHIFT (21U)
2209/*! WP2 - Write Protect
2210 * 0b0..This peripheral allows write accesses.
2211 * 0b1..This peripheral is write protected.
2212 */
2213#define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
2214#define AIPS_PACRG_SP2_MASK (0x400000U)
2215#define AIPS_PACRG_SP2_SHIFT (22U)
2216/*! SP2 - Supervisor Protect
2217 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2218 * 0b1..This peripheral requires supervisor privilege level for accesses.
2219 */
2220#define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
2221#define AIPS_PACRG_TP1_MASK (0x1000000U)
2222#define AIPS_PACRG_TP1_SHIFT (24U)
2223/*! TP1 - Trusted Protect
2224 * 0b0..Accesses from an untrusted master are allowed.
2225 * 0b1..Accesses from an untrusted master are not allowed.
2226 */
2227#define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
2228#define AIPS_PACRG_WP1_MASK (0x2000000U)
2229#define AIPS_PACRG_WP1_SHIFT (25U)
2230/*! WP1 - Write Protect
2231 * 0b0..This peripheral allows write accesses.
2232 * 0b1..This peripheral is write protected.
2233 */
2234#define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
2235#define AIPS_PACRG_SP1_MASK (0x4000000U)
2236#define AIPS_PACRG_SP1_SHIFT (26U)
2237/*! SP1 - Supervisor Protect
2238 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2239 * 0b1..This peripheral requires supervisor privilege level for accesses.
2240 */
2241#define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
2242#define AIPS_PACRG_TP0_MASK (0x10000000U)
2243#define AIPS_PACRG_TP0_SHIFT (28U)
2244/*! TP0 - Trusted Protect
2245 * 0b0..Accesses from an untrusted master are allowed.
2246 * 0b1..Accesses from an untrusted master are not allowed.
2247 */
2248#define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
2249#define AIPS_PACRG_WP0_MASK (0x20000000U)
2250#define AIPS_PACRG_WP0_SHIFT (29U)
2251/*! WP0 - Write Protect
2252 * 0b0..This peripheral allows write accesses.
2253 * 0b1..This peripheral is write protected.
2254 */
2255#define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
2256#define AIPS_PACRG_SP0_MASK (0x40000000U)
2257#define AIPS_PACRG_SP0_SHIFT (30U)
2258/*! SP0 - Supervisor Protect
2259 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2260 * 0b1..This peripheral requires supervisor privilege level for accesses.
2261 */
2262#define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
2263/*! @} */
2264
2265/*! @name PACRH - Peripheral Access Control Register */
2266/*! @{ */
2267#define AIPS_PACRH_TP7_MASK (0x1U)
2268#define AIPS_PACRH_TP7_SHIFT (0U)
2269/*! TP7 - Trusted Protect
2270 * 0b0..Accesses from an untrusted master are allowed.
2271 * 0b1..Accesses from an untrusted master are not allowed.
2272 */
2273#define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
2274#define AIPS_PACRH_WP7_MASK (0x2U)
2275#define AIPS_PACRH_WP7_SHIFT (1U)
2276/*! WP7 - Write Protect
2277 * 0b0..This peripheral allows write accesses.
2278 * 0b1..This peripheral is write protected.
2279 */
2280#define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
2281#define AIPS_PACRH_SP7_MASK (0x4U)
2282#define AIPS_PACRH_SP7_SHIFT (2U)
2283/*! SP7 - Supervisor Protect
2284 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2285 * 0b1..This peripheral requires supervisor privilege level for accesses.
2286 */
2287#define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
2288#define AIPS_PACRH_TP6_MASK (0x10U)
2289#define AIPS_PACRH_TP6_SHIFT (4U)
2290/*! TP6 - Trusted Protect
2291 * 0b0..Accesses from an untrusted master are allowed.
2292 * 0b1..Accesses from an untrusted master are not allowed.
2293 */
2294#define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
2295#define AIPS_PACRH_WP6_MASK (0x20U)
2296#define AIPS_PACRH_WP6_SHIFT (5U)
2297/*! WP6 - Write Protect
2298 * 0b0..This peripheral allows write accesses.
2299 * 0b1..This peripheral is write protected.
2300 */
2301#define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
2302#define AIPS_PACRH_SP6_MASK (0x40U)
2303#define AIPS_PACRH_SP6_SHIFT (6U)
2304/*! SP6 - Supervisor Protect
2305 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2306 * 0b1..This peripheral requires supervisor privilege level for accesses.
2307 */
2308#define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
2309#define AIPS_PACRH_TP5_MASK (0x100U)
2310#define AIPS_PACRH_TP5_SHIFT (8U)
2311/*! TP5 - Trusted Protect
2312 * 0b0..Accesses from an untrusted master are allowed.
2313 * 0b1..Accesses from an untrusted master are not allowed.
2314 */
2315#define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
2316#define AIPS_PACRH_WP5_MASK (0x200U)
2317#define AIPS_PACRH_WP5_SHIFT (9U)
2318/*! WP5 - Write Protect
2319 * 0b0..This peripheral allows write accesses.
2320 * 0b1..This peripheral is write protected.
2321 */
2322#define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
2323#define AIPS_PACRH_SP5_MASK (0x400U)
2324#define AIPS_PACRH_SP5_SHIFT (10U)
2325/*! SP5 - Supervisor Protect
2326 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2327 * 0b1..This peripheral requires supervisor privilege level for accesses.
2328 */
2329#define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
2330#define AIPS_PACRH_TP4_MASK (0x1000U)
2331#define AIPS_PACRH_TP4_SHIFT (12U)
2332/*! TP4 - Trusted Protect
2333 * 0b0..Accesses from an untrusted master are allowed.
2334 * 0b1..Accesses from an untrusted master are not allowed.
2335 */
2336#define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
2337#define AIPS_PACRH_WP4_MASK (0x2000U)
2338#define AIPS_PACRH_WP4_SHIFT (13U)
2339/*! WP4 - Write Protect
2340 * 0b0..This peripheral allows write accesses.
2341 * 0b1..This peripheral is write protected.
2342 */
2343#define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
2344#define AIPS_PACRH_SP4_MASK (0x4000U)
2345#define AIPS_PACRH_SP4_SHIFT (14U)
2346/*! SP4 - Supervisor Protect
2347 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2348 * 0b1..This peripheral requires supervisor privilege level for accesses.
2349 */
2350#define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
2351#define AIPS_PACRH_TP3_MASK (0x10000U)
2352#define AIPS_PACRH_TP3_SHIFT (16U)
2353/*! TP3 - Trusted Protect
2354 * 0b0..Accesses from an untrusted master are allowed.
2355 * 0b1..Accesses from an untrusted master are not allowed.
2356 */
2357#define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
2358#define AIPS_PACRH_WP3_MASK (0x20000U)
2359#define AIPS_PACRH_WP3_SHIFT (17U)
2360/*! WP3 - Write Protect
2361 * 0b0..This peripheral allows write accesses.
2362 * 0b1..This peripheral is write protected.
2363 */
2364#define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
2365#define AIPS_PACRH_SP3_MASK (0x40000U)
2366#define AIPS_PACRH_SP3_SHIFT (18U)
2367/*! SP3 - Supervisor Protect
2368 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2369 * 0b1..This peripheral requires supervisor privilege level for accesses.
2370 */
2371#define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
2372#define AIPS_PACRH_TP2_MASK (0x100000U)
2373#define AIPS_PACRH_TP2_SHIFT (20U)
2374/*! TP2 - Trusted Protect
2375 * 0b0..Accesses from an untrusted master are allowed.
2376 * 0b1..Accesses from an untrusted master are not allowed.
2377 */
2378#define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
2379#define AIPS_PACRH_WP2_MASK (0x200000U)
2380#define AIPS_PACRH_WP2_SHIFT (21U)
2381/*! WP2 - Write Protect
2382 * 0b0..This peripheral allows write accesses.
2383 * 0b1..This peripheral is write protected.
2384 */
2385#define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
2386#define AIPS_PACRH_SP2_MASK (0x400000U)
2387#define AIPS_PACRH_SP2_SHIFT (22U)
2388/*! SP2 - Supervisor Protect
2389 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2390 * 0b1..This peripheral requires supervisor privilege level for accesses.
2391 */
2392#define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
2393#define AIPS_PACRH_TP1_MASK (0x1000000U)
2394#define AIPS_PACRH_TP1_SHIFT (24U)
2395/*! TP1 - Trusted Protect
2396 * 0b0..Accesses from an untrusted master are allowed.
2397 * 0b1..Accesses from an untrusted master are not allowed.
2398 */
2399#define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
2400#define AIPS_PACRH_WP1_MASK (0x2000000U)
2401#define AIPS_PACRH_WP1_SHIFT (25U)
2402/*! WP1 - Write Protect
2403 * 0b0..This peripheral allows write accesses.
2404 * 0b1..This peripheral is write protected.
2405 */
2406#define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
2407#define AIPS_PACRH_SP1_MASK (0x4000000U)
2408#define AIPS_PACRH_SP1_SHIFT (26U)
2409/*! SP1 - Supervisor Protect
2410 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2411 * 0b1..This peripheral requires supervisor privilege level for accesses.
2412 */
2413#define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
2414#define AIPS_PACRH_TP0_MASK (0x10000000U)
2415#define AIPS_PACRH_TP0_SHIFT (28U)
2416/*! TP0 - Trusted Protect
2417 * 0b0..Accesses from an untrusted master are allowed.
2418 * 0b1..Accesses from an untrusted master are not allowed.
2419 */
2420#define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
2421#define AIPS_PACRH_WP0_MASK (0x20000000U)
2422#define AIPS_PACRH_WP0_SHIFT (29U)
2423/*! WP0 - Write Protect
2424 * 0b0..This peripheral allows write accesses.
2425 * 0b1..This peripheral is write protected.
2426 */
2427#define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
2428#define AIPS_PACRH_SP0_MASK (0x40000000U)
2429#define AIPS_PACRH_SP0_SHIFT (30U)
2430/*! SP0 - Supervisor Protect
2431 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2432 * 0b1..This peripheral requires supervisor privilege level for accesses.
2433 */
2434#define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
2435/*! @} */
2436
2437/*! @name PACRI - Peripheral Access Control Register */
2438/*! @{ */
2439#define AIPS_PACRI_TP7_MASK (0x1U)
2440#define AIPS_PACRI_TP7_SHIFT (0U)
2441/*! TP7 - Trusted Protect
2442 * 0b0..Accesses from an untrusted master are allowed.
2443 * 0b1..Accesses from an untrusted master are not allowed.
2444 */
2445#define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
2446#define AIPS_PACRI_WP7_MASK (0x2U)
2447#define AIPS_PACRI_WP7_SHIFT (1U)
2448/*! WP7 - Write Protect
2449 * 0b0..This peripheral allows write accesses.
2450 * 0b1..This peripheral is write protected.
2451 */
2452#define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
2453#define AIPS_PACRI_SP7_MASK (0x4U)
2454#define AIPS_PACRI_SP7_SHIFT (2U)
2455/*! SP7 - Supervisor Protect
2456 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2457 * 0b1..This peripheral requires supervisor privilege level for accesses.
2458 */
2459#define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
2460#define AIPS_PACRI_TP6_MASK (0x10U)
2461#define AIPS_PACRI_TP6_SHIFT (4U)
2462/*! TP6 - Trusted Protect
2463 * 0b0..Accesses from an untrusted master are allowed.
2464 * 0b1..Accesses from an untrusted master are not allowed.
2465 */
2466#define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
2467#define AIPS_PACRI_WP6_MASK (0x20U)
2468#define AIPS_PACRI_WP6_SHIFT (5U)
2469/*! WP6 - Write Protect
2470 * 0b0..This peripheral allows write accesses.
2471 * 0b1..This peripheral is write protected.
2472 */
2473#define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
2474#define AIPS_PACRI_SP6_MASK (0x40U)
2475#define AIPS_PACRI_SP6_SHIFT (6U)
2476/*! SP6 - Supervisor Protect
2477 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2478 * 0b1..This peripheral requires supervisor privilege level for accesses.
2479 */
2480#define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
2481#define AIPS_PACRI_TP5_MASK (0x100U)
2482#define AIPS_PACRI_TP5_SHIFT (8U)
2483/*! TP5 - Trusted Protect
2484 * 0b0..Accesses from an untrusted master are allowed.
2485 * 0b1..Accesses from an untrusted master are not allowed.
2486 */
2487#define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
2488#define AIPS_PACRI_WP5_MASK (0x200U)
2489#define AIPS_PACRI_WP5_SHIFT (9U)
2490/*! WP5 - Write Protect
2491 * 0b0..This peripheral allows write accesses.
2492 * 0b1..This peripheral is write protected.
2493 */
2494#define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
2495#define AIPS_PACRI_SP5_MASK (0x400U)
2496#define AIPS_PACRI_SP5_SHIFT (10U)
2497/*! SP5 - Supervisor Protect
2498 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2499 * 0b1..This peripheral requires supervisor privilege level for accesses.
2500 */
2501#define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
2502#define AIPS_PACRI_TP4_MASK (0x1000U)
2503#define AIPS_PACRI_TP4_SHIFT (12U)
2504/*! TP4 - Trusted Protect
2505 * 0b0..Accesses from an untrusted master are allowed.
2506 * 0b1..Accesses from an untrusted master are not allowed.
2507 */
2508#define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
2509#define AIPS_PACRI_WP4_MASK (0x2000U)
2510#define AIPS_PACRI_WP4_SHIFT (13U)
2511/*! WP4 - Write Protect
2512 * 0b0..This peripheral allows write accesses.
2513 * 0b1..This peripheral is write protected.
2514 */
2515#define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
2516#define AIPS_PACRI_SP4_MASK (0x4000U)
2517#define AIPS_PACRI_SP4_SHIFT (14U)
2518/*! SP4 - Supervisor Protect
2519 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2520 * 0b1..This peripheral requires supervisor privilege level for accesses.
2521 */
2522#define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
2523#define AIPS_PACRI_TP3_MASK (0x10000U)
2524#define AIPS_PACRI_TP3_SHIFT (16U)
2525/*! TP3 - Trusted Protect
2526 * 0b0..Accesses from an untrusted master are allowed.
2527 * 0b1..Accesses from an untrusted master are not allowed.
2528 */
2529#define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
2530#define AIPS_PACRI_WP3_MASK (0x20000U)
2531#define AIPS_PACRI_WP3_SHIFT (17U)
2532/*! WP3 - Write Protect
2533 * 0b0..This peripheral allows write accesses.
2534 * 0b1..This peripheral is write protected.
2535 */
2536#define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
2537#define AIPS_PACRI_SP3_MASK (0x40000U)
2538#define AIPS_PACRI_SP3_SHIFT (18U)
2539/*! SP3 - Supervisor Protect
2540 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2541 * 0b1..This peripheral requires supervisor privilege level for accesses.
2542 */
2543#define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
2544#define AIPS_PACRI_TP2_MASK (0x100000U)
2545#define AIPS_PACRI_TP2_SHIFT (20U)
2546/*! TP2 - Trusted Protect
2547 * 0b0..Accesses from an untrusted master are allowed.
2548 * 0b1..Accesses from an untrusted master are not allowed.
2549 */
2550#define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
2551#define AIPS_PACRI_WP2_MASK (0x200000U)
2552#define AIPS_PACRI_WP2_SHIFT (21U)
2553/*! WP2 - Write Protect
2554 * 0b0..This peripheral allows write accesses.
2555 * 0b1..This peripheral is write protected.
2556 */
2557#define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
2558#define AIPS_PACRI_SP2_MASK (0x400000U)
2559#define AIPS_PACRI_SP2_SHIFT (22U)
2560/*! SP2 - Supervisor Protect
2561 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2562 * 0b1..This peripheral requires supervisor privilege level for accesses.
2563 */
2564#define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
2565#define AIPS_PACRI_TP1_MASK (0x1000000U)
2566#define AIPS_PACRI_TP1_SHIFT (24U)
2567/*! TP1 - Trusted Protect
2568 * 0b0..Accesses from an untrusted master are allowed.
2569 * 0b1..Accesses from an untrusted master are not allowed.
2570 */
2571#define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
2572#define AIPS_PACRI_WP1_MASK (0x2000000U)
2573#define AIPS_PACRI_WP1_SHIFT (25U)
2574/*! WP1 - Write Protect
2575 * 0b0..This peripheral allows write accesses.
2576 * 0b1..This peripheral is write protected.
2577 */
2578#define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
2579#define AIPS_PACRI_SP1_MASK (0x4000000U)
2580#define AIPS_PACRI_SP1_SHIFT (26U)
2581/*! SP1 - Supervisor Protect
2582 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2583 * 0b1..This peripheral requires supervisor privilege level for accesses.
2584 */
2585#define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
2586#define AIPS_PACRI_TP0_MASK (0x10000000U)
2587#define AIPS_PACRI_TP0_SHIFT (28U)
2588/*! TP0 - Trusted Protect
2589 * 0b0..Accesses from an untrusted master are allowed.
2590 * 0b1..Accesses from an untrusted master are not allowed.
2591 */
2592#define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
2593#define AIPS_PACRI_WP0_MASK (0x20000000U)
2594#define AIPS_PACRI_WP0_SHIFT (29U)
2595/*! WP0 - Write Protect
2596 * 0b0..This peripheral allows write accesses.
2597 * 0b1..This peripheral is write protected.
2598 */
2599#define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
2600#define AIPS_PACRI_SP0_MASK (0x40000000U)
2601#define AIPS_PACRI_SP0_SHIFT (30U)
2602/*! SP0 - Supervisor Protect
2603 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2604 * 0b1..This peripheral requires supervisor privilege level for accesses.
2605 */
2606#define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
2607/*! @} */
2608
2609/*! @name PACRJ - Peripheral Access Control Register */
2610/*! @{ */
2611#define AIPS_PACRJ_TP7_MASK (0x1U)
2612#define AIPS_PACRJ_TP7_SHIFT (0U)
2613/*! TP7 - Trusted Protect
2614 * 0b0..Accesses from an untrusted master are allowed.
2615 * 0b1..Accesses from an untrusted master are not allowed.
2616 */
2617#define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
2618#define AIPS_PACRJ_WP7_MASK (0x2U)
2619#define AIPS_PACRJ_WP7_SHIFT (1U)
2620/*! WP7 - Write Protect
2621 * 0b0..This peripheral allows write accesses.
2622 * 0b1..This peripheral is write protected.
2623 */
2624#define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
2625#define AIPS_PACRJ_SP7_MASK (0x4U)
2626#define AIPS_PACRJ_SP7_SHIFT (2U)
2627/*! SP7 - Supervisor Protect
2628 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2629 * 0b1..This peripheral requires supervisor privilege level for accesses.
2630 */
2631#define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
2632#define AIPS_PACRJ_TP6_MASK (0x10U)
2633#define AIPS_PACRJ_TP6_SHIFT (4U)
2634/*! TP6 - Trusted Protect
2635 * 0b0..Accesses from an untrusted master are allowed.
2636 * 0b1..Accesses from an untrusted master are not allowed.
2637 */
2638#define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
2639#define AIPS_PACRJ_WP6_MASK (0x20U)
2640#define AIPS_PACRJ_WP6_SHIFT (5U)
2641/*! WP6 - Write Protect
2642 * 0b0..This peripheral allows write accesses.
2643 * 0b1..This peripheral is write protected.
2644 */
2645#define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
2646#define AIPS_PACRJ_SP6_MASK (0x40U)
2647#define AIPS_PACRJ_SP6_SHIFT (6U)
2648/*! SP6 - Supervisor Protect
2649 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2650 * 0b1..This peripheral requires supervisor privilege level for accesses.
2651 */
2652#define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
2653#define AIPS_PACRJ_TP5_MASK (0x100U)
2654#define AIPS_PACRJ_TP5_SHIFT (8U)
2655/*! TP5 - Trusted Protect
2656 * 0b0..Accesses from an untrusted master are allowed.
2657 * 0b1..Accesses from an untrusted master are not allowed.
2658 */
2659#define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
2660#define AIPS_PACRJ_WP5_MASK (0x200U)
2661#define AIPS_PACRJ_WP5_SHIFT (9U)
2662/*! WP5 - Write Protect
2663 * 0b0..This peripheral allows write accesses.
2664 * 0b1..This peripheral is write protected.
2665 */
2666#define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
2667#define AIPS_PACRJ_SP5_MASK (0x400U)
2668#define AIPS_PACRJ_SP5_SHIFT (10U)
2669/*! SP5 - Supervisor Protect
2670 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2671 * 0b1..This peripheral requires supervisor privilege level for accesses.
2672 */
2673#define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
2674#define AIPS_PACRJ_TP4_MASK (0x1000U)
2675#define AIPS_PACRJ_TP4_SHIFT (12U)
2676/*! TP4 - Trusted Protect
2677 * 0b0..Accesses from an untrusted master are allowed.
2678 * 0b1..Accesses from an untrusted master are not allowed.
2679 */
2680#define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
2681#define AIPS_PACRJ_WP4_MASK (0x2000U)
2682#define AIPS_PACRJ_WP4_SHIFT (13U)
2683/*! WP4 - Write Protect
2684 * 0b0..This peripheral allows write accesses.
2685 * 0b1..This peripheral is write protected.
2686 */
2687#define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
2688#define AIPS_PACRJ_SP4_MASK (0x4000U)
2689#define AIPS_PACRJ_SP4_SHIFT (14U)
2690/*! SP4 - Supervisor Protect
2691 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2692 * 0b1..This peripheral requires supervisor privilege level for accesses.
2693 */
2694#define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
2695#define AIPS_PACRJ_TP3_MASK (0x10000U)
2696#define AIPS_PACRJ_TP3_SHIFT (16U)
2697/*! TP3 - Trusted Protect
2698 * 0b0..Accesses from an untrusted master are allowed.
2699 * 0b1..Accesses from an untrusted master are not allowed.
2700 */
2701#define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
2702#define AIPS_PACRJ_WP3_MASK (0x20000U)
2703#define AIPS_PACRJ_WP3_SHIFT (17U)
2704/*! WP3 - Write Protect
2705 * 0b0..This peripheral allows write accesses.
2706 * 0b1..This peripheral is write protected.
2707 */
2708#define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
2709#define AIPS_PACRJ_SP3_MASK (0x40000U)
2710#define AIPS_PACRJ_SP3_SHIFT (18U)
2711/*! SP3 - Supervisor Protect
2712 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2713 * 0b1..This peripheral requires supervisor privilege level for accesses.
2714 */
2715#define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
2716#define AIPS_PACRJ_TP2_MASK (0x100000U)
2717#define AIPS_PACRJ_TP2_SHIFT (20U)
2718/*! TP2 - Trusted Protect
2719 * 0b0..Accesses from an untrusted master are allowed.
2720 * 0b1..Accesses from an untrusted master are not allowed.
2721 */
2722#define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
2723#define AIPS_PACRJ_WP2_MASK (0x200000U)
2724#define AIPS_PACRJ_WP2_SHIFT (21U)
2725/*! WP2 - Write Protect
2726 * 0b0..This peripheral allows write accesses.
2727 * 0b1..This peripheral is write protected.
2728 */
2729#define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
2730#define AIPS_PACRJ_SP2_MASK (0x400000U)
2731#define AIPS_PACRJ_SP2_SHIFT (22U)
2732/*! SP2 - Supervisor Protect
2733 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2734 * 0b1..This peripheral requires supervisor privilege level for accesses.
2735 */
2736#define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
2737#define AIPS_PACRJ_TP1_MASK (0x1000000U)
2738#define AIPS_PACRJ_TP1_SHIFT (24U)
2739/*! TP1 - Trusted Protect
2740 * 0b0..Accesses from an untrusted master are allowed.
2741 * 0b1..Accesses from an untrusted master are not allowed.
2742 */
2743#define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
2744#define AIPS_PACRJ_WP1_MASK (0x2000000U)
2745#define AIPS_PACRJ_WP1_SHIFT (25U)
2746/*! WP1 - Write Protect
2747 * 0b0..This peripheral allows write accesses.
2748 * 0b1..This peripheral is write protected.
2749 */
2750#define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
2751#define AIPS_PACRJ_SP1_MASK (0x4000000U)
2752#define AIPS_PACRJ_SP1_SHIFT (26U)
2753/*! SP1 - Supervisor Protect
2754 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2755 * 0b1..This peripheral requires supervisor privilege level for accesses.
2756 */
2757#define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
2758#define AIPS_PACRJ_TP0_MASK (0x10000000U)
2759#define AIPS_PACRJ_TP0_SHIFT (28U)
2760/*! TP0 - Trusted Protect
2761 * 0b0..Accesses from an untrusted master are allowed.
2762 * 0b1..Accesses from an untrusted master are not allowed.
2763 */
2764#define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
2765#define AIPS_PACRJ_WP0_MASK (0x20000000U)
2766#define AIPS_PACRJ_WP0_SHIFT (29U)
2767/*! WP0 - Write Protect
2768 * 0b0..This peripheral allows write accesses.
2769 * 0b1..This peripheral is write protected.
2770 */
2771#define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
2772#define AIPS_PACRJ_SP0_MASK (0x40000000U)
2773#define AIPS_PACRJ_SP0_SHIFT (30U)
2774/*! SP0 - Supervisor Protect
2775 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2776 * 0b1..This peripheral requires supervisor privilege level for accesses.
2777 */
2778#define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
2779/*! @} */
2780
2781/*! @name PACRK - Peripheral Access Control Register */
2782/*! @{ */
2783#define AIPS_PACRK_TP7_MASK (0x1U)
2784#define AIPS_PACRK_TP7_SHIFT (0U)
2785/*! TP7 - Trusted Protect
2786 * 0b0..Accesses from an untrusted master are allowed.
2787 * 0b1..Accesses from an untrusted master are not allowed.
2788 */
2789#define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
2790#define AIPS_PACRK_WP7_MASK (0x2U)
2791#define AIPS_PACRK_WP7_SHIFT (1U)
2792/*! WP7 - Write Protect
2793 * 0b0..This peripheral allows write accesses.
2794 * 0b1..This peripheral is write protected.
2795 */
2796#define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
2797#define AIPS_PACRK_SP7_MASK (0x4U)
2798#define AIPS_PACRK_SP7_SHIFT (2U)
2799/*! SP7 - Supervisor Protect
2800 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2801 * 0b1..This peripheral requires supervisor privilege level for accesses.
2802 */
2803#define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
2804#define AIPS_PACRK_TP6_MASK (0x10U)
2805#define AIPS_PACRK_TP6_SHIFT (4U)
2806/*! TP6 - Trusted Protect
2807 * 0b0..Accesses from an untrusted master are allowed.
2808 * 0b1..Accesses from an untrusted master are not allowed.
2809 */
2810#define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
2811#define AIPS_PACRK_WP6_MASK (0x20U)
2812#define AIPS_PACRK_WP6_SHIFT (5U)
2813/*! WP6 - Write Protect
2814 * 0b0..This peripheral allows write accesses.
2815 * 0b1..This peripheral is write protected.
2816 */
2817#define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
2818#define AIPS_PACRK_SP6_MASK (0x40U)
2819#define AIPS_PACRK_SP6_SHIFT (6U)
2820/*! SP6 - Supervisor Protect
2821 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2822 * 0b1..This peripheral requires supervisor privilege level for accesses.
2823 */
2824#define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
2825#define AIPS_PACRK_TP5_MASK (0x100U)
2826#define AIPS_PACRK_TP5_SHIFT (8U)
2827/*! TP5 - Trusted Protect
2828 * 0b0..Accesses from an untrusted master are allowed.
2829 * 0b1..Accesses from an untrusted master are not allowed.
2830 */
2831#define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
2832#define AIPS_PACRK_WP5_MASK (0x200U)
2833#define AIPS_PACRK_WP5_SHIFT (9U)
2834/*! WP5 - Write Protect
2835 * 0b0..This peripheral allows write accesses.
2836 * 0b1..This peripheral is write protected.
2837 */
2838#define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
2839#define AIPS_PACRK_SP5_MASK (0x400U)
2840#define AIPS_PACRK_SP5_SHIFT (10U)
2841/*! SP5 - Supervisor Protect
2842 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2843 * 0b1..This peripheral requires supervisor privilege level for accesses.
2844 */
2845#define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
2846#define AIPS_PACRK_TP4_MASK (0x1000U)
2847#define AIPS_PACRK_TP4_SHIFT (12U)
2848/*! TP4 - Trusted Protect
2849 * 0b0..Accesses from an untrusted master are allowed.
2850 * 0b1..Accesses from an untrusted master are not allowed.
2851 */
2852#define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
2853#define AIPS_PACRK_WP4_MASK (0x2000U)
2854#define AIPS_PACRK_WP4_SHIFT (13U)
2855/*! WP4 - Write Protect
2856 * 0b0..This peripheral allows write accesses.
2857 * 0b1..This peripheral is write protected.
2858 */
2859#define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
2860#define AIPS_PACRK_SP4_MASK (0x4000U)
2861#define AIPS_PACRK_SP4_SHIFT (14U)
2862/*! SP4 - Supervisor Protect
2863 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2864 * 0b1..This peripheral requires supervisor privilege level for accesses.
2865 */
2866#define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
2867#define AIPS_PACRK_TP3_MASK (0x10000U)
2868#define AIPS_PACRK_TP3_SHIFT (16U)
2869/*! TP3 - Trusted Protect
2870 * 0b0..Accesses from an untrusted master are allowed.
2871 * 0b1..Accesses from an untrusted master are not allowed.
2872 */
2873#define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
2874#define AIPS_PACRK_WP3_MASK (0x20000U)
2875#define AIPS_PACRK_WP3_SHIFT (17U)
2876/*! WP3 - Write Protect
2877 * 0b0..This peripheral allows write accesses.
2878 * 0b1..This peripheral is write protected.
2879 */
2880#define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
2881#define AIPS_PACRK_SP3_MASK (0x40000U)
2882#define AIPS_PACRK_SP3_SHIFT (18U)
2883/*! SP3 - Supervisor Protect
2884 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2885 * 0b1..This peripheral requires supervisor privilege level for accesses.
2886 */
2887#define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
2888#define AIPS_PACRK_TP2_MASK (0x100000U)
2889#define AIPS_PACRK_TP2_SHIFT (20U)
2890/*! TP2 - Trusted Protect
2891 * 0b0..Accesses from an untrusted master are allowed.
2892 * 0b1..Accesses from an untrusted master are not allowed.
2893 */
2894#define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
2895#define AIPS_PACRK_WP2_MASK (0x200000U)
2896#define AIPS_PACRK_WP2_SHIFT (21U)
2897/*! WP2 - Write Protect
2898 * 0b0..This peripheral allows write accesses.
2899 * 0b1..This peripheral is write protected.
2900 */
2901#define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
2902#define AIPS_PACRK_SP2_MASK (0x400000U)
2903#define AIPS_PACRK_SP2_SHIFT (22U)
2904/*! SP2 - Supervisor Protect
2905 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2906 * 0b1..This peripheral requires supervisor privilege level for accesses.
2907 */
2908#define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
2909#define AIPS_PACRK_TP1_MASK (0x1000000U)
2910#define AIPS_PACRK_TP1_SHIFT (24U)
2911/*! TP1 - Trusted Protect
2912 * 0b0..Accesses from an untrusted master are allowed.
2913 * 0b1..Accesses from an untrusted master are not allowed.
2914 */
2915#define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
2916#define AIPS_PACRK_WP1_MASK (0x2000000U)
2917#define AIPS_PACRK_WP1_SHIFT (25U)
2918/*! WP1 - Write Protect
2919 * 0b0..This peripheral allows write accesses.
2920 * 0b1..This peripheral is write protected.
2921 */
2922#define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
2923#define AIPS_PACRK_SP1_MASK (0x4000000U)
2924#define AIPS_PACRK_SP1_SHIFT (26U)
2925/*! SP1 - Supervisor Protect
2926 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2927 * 0b1..This peripheral requires supervisor privilege level for accesses.
2928 */
2929#define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
2930#define AIPS_PACRK_TP0_MASK (0x10000000U)
2931#define AIPS_PACRK_TP0_SHIFT (28U)
2932/*! TP0 - Trusted Protect
2933 * 0b0..Accesses from an untrusted master are allowed.
2934 * 0b1..Accesses from an untrusted master are not allowed.
2935 */
2936#define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
2937#define AIPS_PACRK_WP0_MASK (0x20000000U)
2938#define AIPS_PACRK_WP0_SHIFT (29U)
2939/*! WP0 - Write Protect
2940 * 0b0..This peripheral allows write accesses.
2941 * 0b1..This peripheral is write protected.
2942 */
2943#define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
2944#define AIPS_PACRK_SP0_MASK (0x40000000U)
2945#define AIPS_PACRK_SP0_SHIFT (30U)
2946/*! SP0 - Supervisor Protect
2947 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2948 * 0b1..This peripheral requires supervisor privilege level for accesses.
2949 */
2950#define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
2951/*! @} */
2952
2953/*! @name PACRL - Peripheral Access Control Register */
2954/*! @{ */
2955#define AIPS_PACRL_TP7_MASK (0x1U)
2956#define AIPS_PACRL_TP7_SHIFT (0U)
2957/*! TP7 - Trusted Protect
2958 * 0b0..Accesses from an untrusted master are allowed.
2959 * 0b1..Accesses from an untrusted master are not allowed.
2960 */
2961#define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
2962#define AIPS_PACRL_WP7_MASK (0x2U)
2963#define AIPS_PACRL_WP7_SHIFT (1U)
2964/*! WP7 - Write Protect
2965 * 0b0..This peripheral allows write accesses.
2966 * 0b1..This peripheral is write protected.
2967 */
2968#define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
2969#define AIPS_PACRL_SP7_MASK (0x4U)
2970#define AIPS_PACRL_SP7_SHIFT (2U)
2971/*! SP7 - Supervisor Protect
2972 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2973 * 0b1..This peripheral requires supervisor privilege level for accesses.
2974 */
2975#define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
2976#define AIPS_PACRL_TP6_MASK (0x10U)
2977#define AIPS_PACRL_TP6_SHIFT (4U)
2978/*! TP6 - Trusted Protect
2979 * 0b0..Accesses from an untrusted master are allowed.
2980 * 0b1..Accesses from an untrusted master are not allowed.
2981 */
2982#define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
2983#define AIPS_PACRL_WP6_MASK (0x20U)
2984#define AIPS_PACRL_WP6_SHIFT (5U)
2985/*! WP6 - Write Protect
2986 * 0b0..This peripheral allows write accesses.
2987 * 0b1..This peripheral is write protected.
2988 */
2989#define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
2990#define AIPS_PACRL_SP6_MASK (0x40U)
2991#define AIPS_PACRL_SP6_SHIFT (6U)
2992/*! SP6 - Supervisor Protect
2993 * 0b0..This peripheral does not require supervisor privilege level for accesses.
2994 * 0b1..This peripheral requires supervisor privilege level for accesses.
2995 */
2996#define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
2997#define AIPS_PACRL_TP5_MASK (0x100U)
2998#define AIPS_PACRL_TP5_SHIFT (8U)
2999/*! TP5 - Trusted Protect
3000 * 0b0..Accesses from an untrusted master are allowed.
3001 * 0b1..Accesses from an untrusted master are not allowed.
3002 */
3003#define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
3004#define AIPS_PACRL_WP5_MASK (0x200U)
3005#define AIPS_PACRL_WP5_SHIFT (9U)
3006/*! WP5 - Write Protect
3007 * 0b0..This peripheral allows write accesses.
3008 * 0b1..This peripheral is write protected.
3009 */
3010#define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
3011#define AIPS_PACRL_SP5_MASK (0x400U)
3012#define AIPS_PACRL_SP5_SHIFT (10U)
3013/*! SP5 - Supervisor Protect
3014 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3015 * 0b1..This peripheral requires supervisor privilege level for accesses.
3016 */
3017#define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
3018#define AIPS_PACRL_TP4_MASK (0x1000U)
3019#define AIPS_PACRL_TP4_SHIFT (12U)
3020/*! TP4 - Trusted Protect
3021 * 0b0..Accesses from an untrusted master are allowed.
3022 * 0b1..Accesses from an untrusted master are not allowed.
3023 */
3024#define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
3025#define AIPS_PACRL_WP4_MASK (0x2000U)
3026#define AIPS_PACRL_WP4_SHIFT (13U)
3027/*! WP4 - Write Protect
3028 * 0b0..This peripheral allows write accesses.
3029 * 0b1..This peripheral is write protected.
3030 */
3031#define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
3032#define AIPS_PACRL_SP4_MASK (0x4000U)
3033#define AIPS_PACRL_SP4_SHIFT (14U)
3034/*! SP4 - Supervisor Protect
3035 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3036 * 0b1..This peripheral requires supervisor privilege level for accesses.
3037 */
3038#define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
3039#define AIPS_PACRL_TP3_MASK (0x10000U)
3040#define AIPS_PACRL_TP3_SHIFT (16U)
3041/*! TP3 - Trusted Protect
3042 * 0b0..Accesses from an untrusted master are allowed.
3043 * 0b1..Accesses from an untrusted master are not allowed.
3044 */
3045#define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
3046#define AIPS_PACRL_WP3_MASK (0x20000U)
3047#define AIPS_PACRL_WP3_SHIFT (17U)
3048/*! WP3 - Write Protect
3049 * 0b0..This peripheral allows write accesses.
3050 * 0b1..This peripheral is write protected.
3051 */
3052#define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
3053#define AIPS_PACRL_SP3_MASK (0x40000U)
3054#define AIPS_PACRL_SP3_SHIFT (18U)
3055/*! SP3 - Supervisor Protect
3056 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3057 * 0b1..This peripheral requires supervisor privilege level for accesses.
3058 */
3059#define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
3060#define AIPS_PACRL_TP2_MASK (0x100000U)
3061#define AIPS_PACRL_TP2_SHIFT (20U)
3062/*! TP2 - Trusted Protect
3063 * 0b0..Accesses from an untrusted master are allowed.
3064 * 0b1..Accesses from an untrusted master are not allowed.
3065 */
3066#define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
3067#define AIPS_PACRL_WP2_MASK (0x200000U)
3068#define AIPS_PACRL_WP2_SHIFT (21U)
3069/*! WP2 - Write Protect
3070 * 0b0..This peripheral allows write accesses.
3071 * 0b1..This peripheral is write protected.
3072 */
3073#define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
3074#define AIPS_PACRL_SP2_MASK (0x400000U)
3075#define AIPS_PACRL_SP2_SHIFT (22U)
3076/*! SP2 - Supervisor Protect
3077 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3078 * 0b1..This peripheral requires supervisor privilege level for accesses.
3079 */
3080#define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
3081#define AIPS_PACRL_TP1_MASK (0x1000000U)
3082#define AIPS_PACRL_TP1_SHIFT (24U)
3083/*! TP1 - Trusted Protect
3084 * 0b0..Accesses from an untrusted master are allowed.
3085 * 0b1..Accesses from an untrusted master are not allowed.
3086 */
3087#define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
3088#define AIPS_PACRL_WP1_MASK (0x2000000U)
3089#define AIPS_PACRL_WP1_SHIFT (25U)
3090/*! WP1 - Write Protect
3091 * 0b0..This peripheral allows write accesses.
3092 * 0b1..This peripheral is write protected.
3093 */
3094#define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
3095#define AIPS_PACRL_SP1_MASK (0x4000000U)
3096#define AIPS_PACRL_SP1_SHIFT (26U)
3097/*! SP1 - Supervisor Protect
3098 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3099 * 0b1..This peripheral requires supervisor privilege level for accesses.
3100 */
3101#define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
3102#define AIPS_PACRL_TP0_MASK (0x10000000U)
3103#define AIPS_PACRL_TP0_SHIFT (28U)
3104/*! TP0 - Trusted Protect
3105 * 0b0..Accesses from an untrusted master are allowed.
3106 * 0b1..Accesses from an untrusted master are not allowed.
3107 */
3108#define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
3109#define AIPS_PACRL_WP0_MASK (0x20000000U)
3110#define AIPS_PACRL_WP0_SHIFT (29U)
3111/*! WP0 - Write Protect
3112 * 0b0..This peripheral allows write accesses.
3113 * 0b1..This peripheral is write protected.
3114 */
3115#define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
3116#define AIPS_PACRL_SP0_MASK (0x40000000U)
3117#define AIPS_PACRL_SP0_SHIFT (30U)
3118/*! SP0 - Supervisor Protect
3119 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3120 * 0b1..This peripheral requires supervisor privilege level for accesses.
3121 */
3122#define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
3123/*! @} */
3124
3125/*! @name PACRM - Peripheral Access Control Register */
3126/*! @{ */
3127#define AIPS_PACRM_TP7_MASK (0x1U)
3128#define AIPS_PACRM_TP7_SHIFT (0U)
3129/*! TP7 - Trusted Protect
3130 * 0b0..Accesses from an untrusted master are allowed.
3131 * 0b1..Accesses from an untrusted master are not allowed.
3132 */
3133#define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
3134#define AIPS_PACRM_WP7_MASK (0x2U)
3135#define AIPS_PACRM_WP7_SHIFT (1U)
3136/*! WP7 - Write Protect
3137 * 0b0..This peripheral allows write accesses.
3138 * 0b1..This peripheral is write protected.
3139 */
3140#define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
3141#define AIPS_PACRM_SP7_MASK (0x4U)
3142#define AIPS_PACRM_SP7_SHIFT (2U)
3143/*! SP7 - Supervisor Protect
3144 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3145 * 0b1..This peripheral requires supervisor privilege level for accesses.
3146 */
3147#define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
3148#define AIPS_PACRM_TP6_MASK (0x10U)
3149#define AIPS_PACRM_TP6_SHIFT (4U)
3150/*! TP6 - Trusted Protect
3151 * 0b0..Accesses from an untrusted master are allowed.
3152 * 0b1..Accesses from an untrusted master are not allowed.
3153 */
3154#define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
3155#define AIPS_PACRM_WP6_MASK (0x20U)
3156#define AIPS_PACRM_WP6_SHIFT (5U)
3157/*! WP6 - Write Protect
3158 * 0b0..This peripheral allows write accesses.
3159 * 0b1..This peripheral is write protected.
3160 */
3161#define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
3162#define AIPS_PACRM_SP6_MASK (0x40U)
3163#define AIPS_PACRM_SP6_SHIFT (6U)
3164/*! SP6 - Supervisor Protect
3165 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3166 * 0b1..This peripheral requires supervisor privilege level for accesses.
3167 */
3168#define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
3169#define AIPS_PACRM_TP5_MASK (0x100U)
3170#define AIPS_PACRM_TP5_SHIFT (8U)
3171/*! TP5 - Trusted Protect
3172 * 0b0..Accesses from an untrusted master are allowed.
3173 * 0b1..Accesses from an untrusted master are not allowed.
3174 */
3175#define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
3176#define AIPS_PACRM_WP5_MASK (0x200U)
3177#define AIPS_PACRM_WP5_SHIFT (9U)
3178/*! WP5 - Write Protect
3179 * 0b0..This peripheral allows write accesses.
3180 * 0b1..This peripheral is write protected.
3181 */
3182#define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
3183#define AIPS_PACRM_SP5_MASK (0x400U)
3184#define AIPS_PACRM_SP5_SHIFT (10U)
3185/*! SP5 - Supervisor Protect
3186 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3187 * 0b1..This peripheral requires supervisor privilege level for accesses.
3188 */
3189#define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
3190#define AIPS_PACRM_TP4_MASK (0x1000U)
3191#define AIPS_PACRM_TP4_SHIFT (12U)
3192/*! TP4 - Trusted Protect
3193 * 0b0..Accesses from an untrusted master are allowed.
3194 * 0b1..Accesses from an untrusted master are not allowed.
3195 */
3196#define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
3197#define AIPS_PACRM_WP4_MASK (0x2000U)
3198#define AIPS_PACRM_WP4_SHIFT (13U)
3199/*! WP4 - Write Protect
3200 * 0b0..This peripheral allows write accesses.
3201 * 0b1..This peripheral is write protected.
3202 */
3203#define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
3204#define AIPS_PACRM_SP4_MASK (0x4000U)
3205#define AIPS_PACRM_SP4_SHIFT (14U)
3206/*! SP4 - Supervisor Protect
3207 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3208 * 0b1..This peripheral requires supervisor privilege level for accesses.
3209 */
3210#define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
3211#define AIPS_PACRM_TP3_MASK (0x10000U)
3212#define AIPS_PACRM_TP3_SHIFT (16U)
3213/*! TP3 - Trusted Protect
3214 * 0b0..Accesses from an untrusted master are allowed.
3215 * 0b1..Accesses from an untrusted master are not allowed.
3216 */
3217#define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
3218#define AIPS_PACRM_WP3_MASK (0x20000U)
3219#define AIPS_PACRM_WP3_SHIFT (17U)
3220/*! WP3 - Write Protect
3221 * 0b0..This peripheral allows write accesses.
3222 * 0b1..This peripheral is write protected.
3223 */
3224#define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
3225#define AIPS_PACRM_SP3_MASK (0x40000U)
3226#define AIPS_PACRM_SP3_SHIFT (18U)
3227/*! SP3 - Supervisor Protect
3228 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3229 * 0b1..This peripheral requires supervisor privilege level for accesses.
3230 */
3231#define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
3232#define AIPS_PACRM_TP2_MASK (0x100000U)
3233#define AIPS_PACRM_TP2_SHIFT (20U)
3234/*! TP2 - Trusted Protect
3235 * 0b0..Accesses from an untrusted master are allowed.
3236 * 0b1..Accesses from an untrusted master are not allowed.
3237 */
3238#define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
3239#define AIPS_PACRM_WP2_MASK (0x200000U)
3240#define AIPS_PACRM_WP2_SHIFT (21U)
3241/*! WP2 - Write Protect
3242 * 0b0..This peripheral allows write accesses.
3243 * 0b1..This peripheral is write protected.
3244 */
3245#define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
3246#define AIPS_PACRM_SP2_MASK (0x400000U)
3247#define AIPS_PACRM_SP2_SHIFT (22U)
3248/*! SP2 - Supervisor Protect
3249 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3250 * 0b1..This peripheral requires supervisor privilege level for accesses.
3251 */
3252#define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
3253#define AIPS_PACRM_TP1_MASK (0x1000000U)
3254#define AIPS_PACRM_TP1_SHIFT (24U)
3255/*! TP1 - Trusted Protect
3256 * 0b0..Accesses from an untrusted master are allowed.
3257 * 0b1..Accesses from an untrusted master are not allowed.
3258 */
3259#define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
3260#define AIPS_PACRM_WP1_MASK (0x2000000U)
3261#define AIPS_PACRM_WP1_SHIFT (25U)
3262/*! WP1 - Write Protect
3263 * 0b0..This peripheral allows write accesses.
3264 * 0b1..This peripheral is write protected.
3265 */
3266#define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
3267#define AIPS_PACRM_SP1_MASK (0x4000000U)
3268#define AIPS_PACRM_SP1_SHIFT (26U)
3269/*! SP1 - Supervisor Protect
3270 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3271 * 0b1..This peripheral requires supervisor privilege level for accesses.
3272 */
3273#define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
3274#define AIPS_PACRM_TP0_MASK (0x10000000U)
3275#define AIPS_PACRM_TP0_SHIFT (28U)
3276/*! TP0 - Trusted Protect
3277 * 0b0..Accesses from an untrusted master are allowed.
3278 * 0b1..Accesses from an untrusted master are not allowed.
3279 */
3280#define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
3281#define AIPS_PACRM_WP0_MASK (0x20000000U)
3282#define AIPS_PACRM_WP0_SHIFT (29U)
3283/*! WP0 - Write Protect
3284 * 0b0..This peripheral allows write accesses.
3285 * 0b1..This peripheral is write protected.
3286 */
3287#define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
3288#define AIPS_PACRM_SP0_MASK (0x40000000U)
3289#define AIPS_PACRM_SP0_SHIFT (30U)
3290/*! SP0 - Supervisor Protect
3291 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3292 * 0b1..This peripheral requires supervisor privilege level for accesses.
3293 */
3294#define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
3295/*! @} */
3296
3297/*! @name PACRN - Peripheral Access Control Register */
3298/*! @{ */
3299#define AIPS_PACRN_TP7_MASK (0x1U)
3300#define AIPS_PACRN_TP7_SHIFT (0U)
3301/*! TP7 - Trusted Protect
3302 * 0b0..Accesses from an untrusted master are allowed.
3303 * 0b1..Accesses from an untrusted master are not allowed.
3304 */
3305#define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
3306#define AIPS_PACRN_WP7_MASK (0x2U)
3307#define AIPS_PACRN_WP7_SHIFT (1U)
3308/*! WP7 - Write Protect
3309 * 0b0..This peripheral allows write accesses.
3310 * 0b1..This peripheral is write protected.
3311 */
3312#define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
3313#define AIPS_PACRN_SP7_MASK (0x4U)
3314#define AIPS_PACRN_SP7_SHIFT (2U)
3315/*! SP7 - Supervisor Protect
3316 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3317 * 0b1..This peripheral requires supervisor privilege level for accesses.
3318 */
3319#define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
3320#define AIPS_PACRN_TP6_MASK (0x10U)
3321#define AIPS_PACRN_TP6_SHIFT (4U)
3322/*! TP6 - Trusted Protect
3323 * 0b0..Accesses from an untrusted master are allowed.
3324 * 0b1..Accesses from an untrusted master are not allowed.
3325 */
3326#define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
3327#define AIPS_PACRN_WP6_MASK (0x20U)
3328#define AIPS_PACRN_WP6_SHIFT (5U)
3329/*! WP6 - Write Protect
3330 * 0b0..This peripheral allows write accesses.
3331 * 0b1..This peripheral is write protected.
3332 */
3333#define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
3334#define AIPS_PACRN_SP6_MASK (0x40U)
3335#define AIPS_PACRN_SP6_SHIFT (6U)
3336/*! SP6 - Supervisor Protect
3337 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3338 * 0b1..This peripheral requires supervisor privilege level for accesses.
3339 */
3340#define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
3341#define AIPS_PACRN_TP5_MASK (0x100U)
3342#define AIPS_PACRN_TP5_SHIFT (8U)
3343/*! TP5 - Trusted Protect
3344 * 0b0..Accesses from an untrusted master are allowed.
3345 * 0b1..Accesses from an untrusted master are not allowed.
3346 */
3347#define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
3348#define AIPS_PACRN_WP5_MASK (0x200U)
3349#define AIPS_PACRN_WP5_SHIFT (9U)
3350/*! WP5 - Write Protect
3351 * 0b0..This peripheral allows write accesses.
3352 * 0b1..This peripheral is write protected.
3353 */
3354#define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
3355#define AIPS_PACRN_SP5_MASK (0x400U)
3356#define AIPS_PACRN_SP5_SHIFT (10U)
3357/*! SP5 - Supervisor Protect
3358 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3359 * 0b1..This peripheral requires supervisor privilege level for accesses.
3360 */
3361#define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
3362#define AIPS_PACRN_TP4_MASK (0x1000U)
3363#define AIPS_PACRN_TP4_SHIFT (12U)
3364/*! TP4 - Trusted Protect
3365 * 0b0..Accesses from an untrusted master are allowed.
3366 * 0b1..Accesses from an untrusted master are not allowed.
3367 */
3368#define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
3369#define AIPS_PACRN_WP4_MASK (0x2000U)
3370#define AIPS_PACRN_WP4_SHIFT (13U)
3371/*! WP4 - Write Protect
3372 * 0b0..This peripheral allows write accesses.
3373 * 0b1..This peripheral is write protected.
3374 */
3375#define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
3376#define AIPS_PACRN_SP4_MASK (0x4000U)
3377#define AIPS_PACRN_SP4_SHIFT (14U)
3378/*! SP4 - Supervisor Protect
3379 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3380 * 0b1..This peripheral requires supervisor privilege level for accesses.
3381 */
3382#define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
3383#define AIPS_PACRN_TP3_MASK (0x10000U)
3384#define AIPS_PACRN_TP3_SHIFT (16U)
3385/*! TP3 - Trusted Protect
3386 * 0b0..Accesses from an untrusted master are allowed.
3387 * 0b1..Accesses from an untrusted master are not allowed.
3388 */
3389#define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
3390#define AIPS_PACRN_WP3_MASK (0x20000U)
3391#define AIPS_PACRN_WP3_SHIFT (17U)
3392/*! WP3 - Write Protect
3393 * 0b0..This peripheral allows write accesses.
3394 * 0b1..This peripheral is write protected.
3395 */
3396#define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
3397#define AIPS_PACRN_SP3_MASK (0x40000U)
3398#define AIPS_PACRN_SP3_SHIFT (18U)
3399/*! SP3 - Supervisor Protect
3400 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3401 * 0b1..This peripheral requires supervisor privilege level for accesses.
3402 */
3403#define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
3404#define AIPS_PACRN_TP2_MASK (0x100000U)
3405#define AIPS_PACRN_TP2_SHIFT (20U)
3406/*! TP2 - Trusted Protect
3407 * 0b0..Accesses from an untrusted master are allowed.
3408 * 0b1..Accesses from an untrusted master are not allowed.
3409 */
3410#define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
3411#define AIPS_PACRN_WP2_MASK (0x200000U)
3412#define AIPS_PACRN_WP2_SHIFT (21U)
3413/*! WP2 - Write Protect
3414 * 0b0..This peripheral allows write accesses.
3415 * 0b1..This peripheral is write protected.
3416 */
3417#define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
3418#define AIPS_PACRN_SP2_MASK (0x400000U)
3419#define AIPS_PACRN_SP2_SHIFT (22U)
3420/*! SP2 - Supervisor Protect
3421 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3422 * 0b1..This peripheral requires supervisor privilege level for accesses.
3423 */
3424#define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
3425#define AIPS_PACRN_TP1_MASK (0x1000000U)
3426#define AIPS_PACRN_TP1_SHIFT (24U)
3427/*! TP1 - Trusted Protect
3428 * 0b0..Accesses from an untrusted master are allowed.
3429 * 0b1..Accesses from an untrusted master are not allowed.
3430 */
3431#define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
3432#define AIPS_PACRN_WP1_MASK (0x2000000U)
3433#define AIPS_PACRN_WP1_SHIFT (25U)
3434/*! WP1 - Write Protect
3435 * 0b0..This peripheral allows write accesses.
3436 * 0b1..This peripheral is write protected.
3437 */
3438#define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
3439#define AIPS_PACRN_SP1_MASK (0x4000000U)
3440#define AIPS_PACRN_SP1_SHIFT (26U)
3441/*! SP1 - Supervisor Protect
3442 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3443 * 0b1..This peripheral requires supervisor privilege level for accesses.
3444 */
3445#define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
3446#define AIPS_PACRN_TP0_MASK (0x10000000U)
3447#define AIPS_PACRN_TP0_SHIFT (28U)
3448/*! TP0 - Trusted Protect
3449 * 0b0..Accesses from an untrusted master are allowed.
3450 * 0b1..Accesses from an untrusted master are not allowed.
3451 */
3452#define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
3453#define AIPS_PACRN_WP0_MASK (0x20000000U)
3454#define AIPS_PACRN_WP0_SHIFT (29U)
3455/*! WP0 - Write Protect
3456 * 0b0..This peripheral allows write accesses.
3457 * 0b1..This peripheral is write protected.
3458 */
3459#define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
3460#define AIPS_PACRN_SP0_MASK (0x40000000U)
3461#define AIPS_PACRN_SP0_SHIFT (30U)
3462/*! SP0 - Supervisor Protect
3463 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3464 * 0b1..This peripheral requires supervisor privilege level for accesses.
3465 */
3466#define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
3467/*! @} */
3468
3469/*! @name PACRO - Peripheral Access Control Register */
3470/*! @{ */
3471#define AIPS_PACRO_TP7_MASK (0x1U)
3472#define AIPS_PACRO_TP7_SHIFT (0U)
3473/*! TP7 - Trusted Protect
3474 * 0b0..Accesses from an untrusted master are allowed.
3475 * 0b1..Accesses from an untrusted master are not allowed.
3476 */
3477#define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
3478#define AIPS_PACRO_WP7_MASK (0x2U)
3479#define AIPS_PACRO_WP7_SHIFT (1U)
3480/*! WP7 - Write Protect
3481 * 0b0..This peripheral allows write accesses.
3482 * 0b1..This peripheral is write protected.
3483 */
3484#define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
3485#define AIPS_PACRO_SP7_MASK (0x4U)
3486#define AIPS_PACRO_SP7_SHIFT (2U)
3487/*! SP7 - Supervisor Protect
3488 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3489 * 0b1..This peripheral requires supervisor privilege level for accesses.
3490 */
3491#define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
3492#define AIPS_PACRO_TP6_MASK (0x10U)
3493#define AIPS_PACRO_TP6_SHIFT (4U)
3494/*! TP6 - Trusted Protect
3495 * 0b0..Accesses from an untrusted master are allowed.
3496 * 0b1..Accesses from an untrusted master are not allowed.
3497 */
3498#define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
3499#define AIPS_PACRO_WP6_MASK (0x20U)
3500#define AIPS_PACRO_WP6_SHIFT (5U)
3501/*! WP6 - Write Protect
3502 * 0b0..This peripheral allows write accesses.
3503 * 0b1..This peripheral is write protected.
3504 */
3505#define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
3506#define AIPS_PACRO_SP6_MASK (0x40U)
3507#define AIPS_PACRO_SP6_SHIFT (6U)
3508/*! SP6 - Supervisor Protect
3509 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3510 * 0b1..This peripheral requires supervisor privilege level for accesses.
3511 */
3512#define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
3513#define AIPS_PACRO_TP5_MASK (0x100U)
3514#define AIPS_PACRO_TP5_SHIFT (8U)
3515/*! TP5 - Trusted Protect
3516 * 0b0..Accesses from an untrusted master are allowed.
3517 * 0b1..Accesses from an untrusted master are not allowed.
3518 */
3519#define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
3520#define AIPS_PACRO_WP5_MASK (0x200U)
3521#define AIPS_PACRO_WP5_SHIFT (9U)
3522/*! WP5 - Write Protect
3523 * 0b0..This peripheral allows write accesses.
3524 * 0b1..This peripheral is write protected.
3525 */
3526#define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
3527#define AIPS_PACRO_SP5_MASK (0x400U)
3528#define AIPS_PACRO_SP5_SHIFT (10U)
3529/*! SP5 - Supervisor Protect
3530 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3531 * 0b1..This peripheral requires supervisor privilege level for accesses.
3532 */
3533#define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
3534#define AIPS_PACRO_TP4_MASK (0x1000U)
3535#define AIPS_PACRO_TP4_SHIFT (12U)
3536/*! TP4 - Trusted Protect
3537 * 0b0..Accesses from an untrusted master are allowed.
3538 * 0b1..Accesses from an untrusted master are not allowed.
3539 */
3540#define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
3541#define AIPS_PACRO_WP4_MASK (0x2000U)
3542#define AIPS_PACRO_WP4_SHIFT (13U)
3543/*! WP4 - Write Protect
3544 * 0b0..This peripheral allows write accesses.
3545 * 0b1..This peripheral is write protected.
3546 */
3547#define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
3548#define AIPS_PACRO_SP4_MASK (0x4000U)
3549#define AIPS_PACRO_SP4_SHIFT (14U)
3550/*! SP4 - Supervisor Protect
3551 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3552 * 0b1..This peripheral requires supervisor privilege level for accesses.
3553 */
3554#define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
3555#define AIPS_PACRO_TP3_MASK (0x10000U)
3556#define AIPS_PACRO_TP3_SHIFT (16U)
3557/*! TP3 - Trusted Protect
3558 * 0b0..Accesses from an untrusted master are allowed.
3559 * 0b1..Accesses from an untrusted master are not allowed.
3560 */
3561#define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
3562#define AIPS_PACRO_WP3_MASK (0x20000U)
3563#define AIPS_PACRO_WP3_SHIFT (17U)
3564/*! WP3 - Write Protect
3565 * 0b0..This peripheral allows write accesses.
3566 * 0b1..This peripheral is write protected.
3567 */
3568#define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
3569#define AIPS_PACRO_SP3_MASK (0x40000U)
3570#define AIPS_PACRO_SP3_SHIFT (18U)
3571/*! SP3 - Supervisor Protect
3572 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3573 * 0b1..This peripheral requires supervisor privilege level for accesses.
3574 */
3575#define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
3576#define AIPS_PACRO_TP2_MASK (0x100000U)
3577#define AIPS_PACRO_TP2_SHIFT (20U)
3578/*! TP2 - Trusted Protect
3579 * 0b0..Accesses from an untrusted master are allowed.
3580 * 0b1..Accesses from an untrusted master are not allowed.
3581 */
3582#define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
3583#define AIPS_PACRO_WP2_MASK (0x200000U)
3584#define AIPS_PACRO_WP2_SHIFT (21U)
3585/*! WP2 - Write Protect
3586 * 0b0..This peripheral allows write accesses.
3587 * 0b1..This peripheral is write protected.
3588 */
3589#define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
3590#define AIPS_PACRO_SP2_MASK (0x400000U)
3591#define AIPS_PACRO_SP2_SHIFT (22U)
3592/*! SP2 - Supervisor Protect
3593 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3594 * 0b1..This peripheral requires supervisor privilege level for accesses.
3595 */
3596#define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
3597#define AIPS_PACRO_TP1_MASK (0x1000000U)
3598#define AIPS_PACRO_TP1_SHIFT (24U)
3599/*! TP1 - Trusted Protect
3600 * 0b0..Accesses from an untrusted master are allowed.
3601 * 0b1..Accesses from an untrusted master are not allowed.
3602 */
3603#define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
3604#define AIPS_PACRO_WP1_MASK (0x2000000U)
3605#define AIPS_PACRO_WP1_SHIFT (25U)
3606/*! WP1 - Write Protect
3607 * 0b0..This peripheral allows write accesses.
3608 * 0b1..This peripheral is write protected.
3609 */
3610#define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
3611#define AIPS_PACRO_SP1_MASK (0x4000000U)
3612#define AIPS_PACRO_SP1_SHIFT (26U)
3613/*! SP1 - Supervisor Protect
3614 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3615 * 0b1..This peripheral requires supervisor privilege level for accesses.
3616 */
3617#define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
3618#define AIPS_PACRO_TP0_MASK (0x10000000U)
3619#define AIPS_PACRO_TP0_SHIFT (28U)
3620/*! TP0 - Trusted Protect
3621 * 0b0..Accesses from an untrusted master are allowed.
3622 * 0b1..Accesses from an untrusted master are not allowed.
3623 */
3624#define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
3625#define AIPS_PACRO_WP0_MASK (0x20000000U)
3626#define AIPS_PACRO_WP0_SHIFT (29U)
3627/*! WP0 - Write Protect
3628 * 0b0..This peripheral allows write accesses.
3629 * 0b1..This peripheral is write protected.
3630 */
3631#define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
3632#define AIPS_PACRO_SP0_MASK (0x40000000U)
3633#define AIPS_PACRO_SP0_SHIFT (30U)
3634/*! SP0 - Supervisor Protect
3635 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3636 * 0b1..This peripheral requires supervisor privilege level for accesses.
3637 */
3638#define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
3639/*! @} */
3640
3641/*! @name PACRP - Peripheral Access Control Register */
3642/*! @{ */
3643#define AIPS_PACRP_TP7_MASK (0x1U)
3644#define AIPS_PACRP_TP7_SHIFT (0U)
3645/*! TP7 - Trusted Protect
3646 * 0b0..Accesses from an untrusted master are allowed.
3647 * 0b1..Accesses from an untrusted master are not allowed.
3648 */
3649#define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
3650#define AIPS_PACRP_WP7_MASK (0x2U)
3651#define AIPS_PACRP_WP7_SHIFT (1U)
3652/*! WP7 - Write Protect
3653 * 0b0..This peripheral allows write accesses.
3654 * 0b1..This peripheral is write protected.
3655 */
3656#define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
3657#define AIPS_PACRP_SP7_MASK (0x4U)
3658#define AIPS_PACRP_SP7_SHIFT (2U)
3659/*! SP7 - Supervisor Protect
3660 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3661 * 0b1..This peripheral requires supervisor privilege level for accesses.
3662 */
3663#define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
3664#define AIPS_PACRP_TP6_MASK (0x10U)
3665#define AIPS_PACRP_TP6_SHIFT (4U)
3666/*! TP6 - Trusted Protect
3667 * 0b0..Accesses from an untrusted master are allowed.
3668 * 0b1..Accesses from an untrusted master are not allowed.
3669 */
3670#define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
3671#define AIPS_PACRP_WP6_MASK (0x20U)
3672#define AIPS_PACRP_WP6_SHIFT (5U)
3673/*! WP6 - Write Protect
3674 * 0b0..This peripheral allows write accesses.
3675 * 0b1..This peripheral is write protected.
3676 */
3677#define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
3678#define AIPS_PACRP_SP6_MASK (0x40U)
3679#define AIPS_PACRP_SP6_SHIFT (6U)
3680/*! SP6 - Supervisor Protect
3681 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3682 * 0b1..This peripheral requires supervisor privilege level for accesses.
3683 */
3684#define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
3685#define AIPS_PACRP_TP5_MASK (0x100U)
3686#define AIPS_PACRP_TP5_SHIFT (8U)
3687/*! TP5 - Trusted Protect
3688 * 0b0..Accesses from an untrusted master are allowed.
3689 * 0b1..Accesses from an untrusted master are not allowed.
3690 */
3691#define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
3692#define AIPS_PACRP_WP5_MASK (0x200U)
3693#define AIPS_PACRP_WP5_SHIFT (9U)
3694/*! WP5 - Write Protect
3695 * 0b0..This peripheral allows write accesses.
3696 * 0b1..This peripheral is write protected.
3697 */
3698#define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
3699#define AIPS_PACRP_SP5_MASK (0x400U)
3700#define AIPS_PACRP_SP5_SHIFT (10U)
3701/*! SP5 - Supervisor Protect
3702 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3703 * 0b1..This peripheral requires supervisor privilege level for accesses.
3704 */
3705#define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
3706#define AIPS_PACRP_TP4_MASK (0x1000U)
3707#define AIPS_PACRP_TP4_SHIFT (12U)
3708/*! TP4 - Trusted Protect
3709 * 0b0..Accesses from an untrusted master are allowed.
3710 * 0b1..Accesses from an untrusted master are not allowed.
3711 */
3712#define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
3713#define AIPS_PACRP_WP4_MASK (0x2000U)
3714#define AIPS_PACRP_WP4_SHIFT (13U)
3715/*! WP4 - Write Protect
3716 * 0b0..This peripheral allows write accesses.
3717 * 0b1..This peripheral is write protected.
3718 */
3719#define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
3720#define AIPS_PACRP_SP4_MASK (0x4000U)
3721#define AIPS_PACRP_SP4_SHIFT (14U)
3722/*! SP4 - Supervisor Protect
3723 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3724 * 0b1..This peripheral requires supervisor privilege level for accesses.
3725 */
3726#define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
3727#define AIPS_PACRP_TP3_MASK (0x10000U)
3728#define AIPS_PACRP_TP3_SHIFT (16U)
3729/*! TP3 - Trusted Protect
3730 * 0b0..Accesses from an untrusted master are allowed.
3731 * 0b1..Accesses from an untrusted master are not allowed.
3732 */
3733#define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
3734#define AIPS_PACRP_WP3_MASK (0x20000U)
3735#define AIPS_PACRP_WP3_SHIFT (17U)
3736/*! WP3 - Write Protect
3737 * 0b0..This peripheral allows write accesses.
3738 * 0b1..This peripheral is write protected.
3739 */
3740#define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
3741#define AIPS_PACRP_SP3_MASK (0x40000U)
3742#define AIPS_PACRP_SP3_SHIFT (18U)
3743/*! SP3 - Supervisor Protect
3744 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3745 * 0b1..This peripheral requires supervisor privilege level for accesses.
3746 */
3747#define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
3748#define AIPS_PACRP_TP2_MASK (0x100000U)
3749#define AIPS_PACRP_TP2_SHIFT (20U)
3750/*! TP2 - Trusted Protect
3751 * 0b0..Accesses from an untrusted master are allowed.
3752 * 0b1..Accesses from an untrusted master are not allowed.
3753 */
3754#define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
3755#define AIPS_PACRP_WP2_MASK (0x200000U)
3756#define AIPS_PACRP_WP2_SHIFT (21U)
3757/*! WP2 - Write Protect
3758 * 0b0..This peripheral allows write accesses.
3759 * 0b1..This peripheral is write protected.
3760 */
3761#define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
3762#define AIPS_PACRP_SP2_MASK (0x400000U)
3763#define AIPS_PACRP_SP2_SHIFT (22U)
3764/*! SP2 - Supervisor Protect
3765 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3766 * 0b1..This peripheral requires supervisor privilege level for accesses.
3767 */
3768#define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
3769#define AIPS_PACRP_TP1_MASK (0x1000000U)
3770#define AIPS_PACRP_TP1_SHIFT (24U)
3771/*! TP1 - Trusted Protect
3772 * 0b0..Accesses from an untrusted master are allowed.
3773 * 0b1..Accesses from an untrusted master are not allowed.
3774 */
3775#define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
3776#define AIPS_PACRP_WP1_MASK (0x2000000U)
3777#define AIPS_PACRP_WP1_SHIFT (25U)
3778/*! WP1 - Write Protect
3779 * 0b0..This peripheral allows write accesses.
3780 * 0b1..This peripheral is write protected.
3781 */
3782#define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
3783#define AIPS_PACRP_SP1_MASK (0x4000000U)
3784#define AIPS_PACRP_SP1_SHIFT (26U)
3785/*! SP1 - Supervisor Protect
3786 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3787 * 0b1..This peripheral requires supervisor privilege level for accesses.
3788 */
3789#define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
3790#define AIPS_PACRP_TP0_MASK (0x10000000U)
3791#define AIPS_PACRP_TP0_SHIFT (28U)
3792/*! TP0 - Trusted Protect
3793 * 0b0..Accesses from an untrusted master are allowed.
3794 * 0b1..Accesses from an untrusted master are not allowed.
3795 */
3796#define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
3797#define AIPS_PACRP_WP0_MASK (0x20000000U)
3798#define AIPS_PACRP_WP0_SHIFT (29U)
3799/*! WP0 - Write Protect
3800 * 0b0..This peripheral allows write accesses.
3801 * 0b1..This peripheral is write protected.
3802 */
3803#define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
3804#define AIPS_PACRP_SP0_MASK (0x40000000U)
3805#define AIPS_PACRP_SP0_SHIFT (30U)
3806/*! SP0 - Supervisor Protect
3807 * 0b0..This peripheral does not require supervisor privilege level for accesses.
3808 * 0b1..This peripheral requires supervisor privilege level for accesses.
3809 */
3810#define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
3811/*! @} */
3812
3813
3814/*!
3815 * @}
3816 */ /* end of group AIPS_Register_Masks */
3817
3818
3819/* AIPS - Peripheral instance base addresses */
3820/** Peripheral AIPS0 base address */
3821#define AIPS0_BASE (0x40000000u)
3822/** Peripheral AIPS0 base pointer */
3823#define AIPS0 ((AIPS_Type *)AIPS0_BASE)
3824/** Peripheral AIPS1 base address */
3825#define AIPS1_BASE (0x40080000u)
3826/** Peripheral AIPS1 base pointer */
3827#define AIPS1 ((AIPS_Type *)AIPS1_BASE)
3828/** Array initializer of AIPS peripheral base addresses */
3829#define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
3830/** Array initializer of AIPS peripheral base pointers */
3831#define AIPS_BASE_PTRS { AIPS0, AIPS1 }
3832
3833/*!
3834 * @}
3835 */ /* end of group AIPS_Peripheral_Access_Layer */
3836
3837
3838/* ----------------------------------------------------------------------------
3839 -- AXBS Peripheral Access Layer
3840 ---------------------------------------------------------------------------- */
3841
3842/*!
3843 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
3844 * @{
3845 */
3846
3847/** AXBS - Register Layout Typedef */
3848typedef struct {
3849 struct { /* offset: 0x0, array step: 0x100 */
3850 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
3851 uint8_t RESERVED_0[12];
3852 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
3853 uint8_t RESERVED_1[236];
3854 } SLAVE[8];
3855 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
3856 uint8_t RESERVED_0[252];
3857 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
3858 uint8_t RESERVED_1[252];
3859 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
3860 uint8_t RESERVED_2[252];
3861 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
3862 uint8_t RESERVED_3[252];
3863 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
3864 uint8_t RESERVED_4[252];
3865 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
3866 uint8_t RESERVED_5[252];
3867 __IO uint32_t MGPCR6; /**< Master General Purpose Control Register, offset: 0xE00 */
3868 uint8_t RESERVED_6[252];
3869 __IO uint32_t MGPCR7; /**< Master General Purpose Control Register, offset: 0xF00 */
3870} AXBS_Type;
3871
3872/* ----------------------------------------------------------------------------
3873 -- AXBS Register Masks
3874 ---------------------------------------------------------------------------- */
3875
3876/*!
3877 * @addtogroup AXBS_Register_Masks AXBS Register Masks
3878 * @{
3879 */
3880
3881/*! @name PRS - Priority Registers Slave */
3882/*! @{ */
3883#define AXBS_PRS_M0_MASK (0x7U)
3884#define AXBS_PRS_M0_SHIFT (0U)
3885/*! M0 - Master 0 Priority. Sets the arbitration priority for this port on the associated slave port.
3886 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3887 * 0b001..This master has level 2 priority when accessing the slave port.
3888 * 0b010..This master has level 3 priority when accessing the slave port.
3889 * 0b011..This master has level 4 priority when accessing the slave port.
3890 * 0b100..This master has level 5 priority when accessing the slave port.
3891 * 0b101..This master has level 6 priority when accessing the slave port.
3892 * 0b110..This master has level 7 priority when accessing the slave port.
3893 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3894 */
3895#define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
3896#define AXBS_PRS_M1_MASK (0x70U)
3897#define AXBS_PRS_M1_SHIFT (4U)
3898/*! M1 - Master 1 Priority. Sets the arbitration priority for this port on the associated slave port.
3899 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3900 * 0b001..This master has level 2 priority when accessing the slave port.
3901 * 0b010..This master has level 3 priority when accessing the slave port.
3902 * 0b011..This master has level 4 priority when accessing the slave port.
3903 * 0b100..This master has level 5 priority when accessing the slave port.
3904 * 0b101..This master has level 6 priority when accessing the slave port.
3905 * 0b110..This master has level 7 priority when accessing the slave port.
3906 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3907 */
3908#define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
3909#define AXBS_PRS_M2_MASK (0x700U)
3910#define AXBS_PRS_M2_SHIFT (8U)
3911/*! M2 - Master 2 Priority. Sets the arbitration priority for this port on the associated slave port.
3912 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3913 * 0b001..This master has level 2 priority when accessing the slave port.
3914 * 0b010..This master has level 3 priority when accessing the slave port.
3915 * 0b011..This master has level 4 priority when accessing the slave port.
3916 * 0b100..This master has level 5 priority when accessing the slave port.
3917 * 0b101..This master has level 6 priority when accessing the slave port.
3918 * 0b110..This master has level 7 priority when accessing the slave port.
3919 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3920 */
3921#define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
3922#define AXBS_PRS_M3_MASK (0x7000U)
3923#define AXBS_PRS_M3_SHIFT (12U)
3924/*! M3 - Master 3 Priority. Sets the arbitration priority for this port on the associated slave port.
3925 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3926 * 0b001..This master has level 2 priority when accessing the slave port.
3927 * 0b010..This master has level 3 priority when accessing the slave port.
3928 * 0b011..This master has level 4 priority when accessing the slave port.
3929 * 0b100..This master has level 5 priority when accessing the slave port.
3930 * 0b101..This master has level 6 priority when accessing the slave port.
3931 * 0b110..This master has level 7 priority when accessing the slave port.
3932 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3933 */
3934#define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
3935#define AXBS_PRS_M4_MASK (0x70000U)
3936#define AXBS_PRS_M4_SHIFT (16U)
3937/*! M4 - Master 4 Priority. Sets the arbitration priority for this port on the associated slave port.
3938 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3939 * 0b001..This master has level 2 priority when accessing the slave port.
3940 * 0b010..This master has level 3 priority when accessing the slave port.
3941 * 0b011..This master has level 4 priority when accessing the slave port.
3942 * 0b100..This master has level 5 priority when accessing the slave port.
3943 * 0b101..This master has level 6 priority when accessing the slave port.
3944 * 0b110..This master has level 7 priority when accessing the slave port.
3945 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3946 */
3947#define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
3948#define AXBS_PRS_M5_MASK (0x700000U)
3949#define AXBS_PRS_M5_SHIFT (20U)
3950/*! M5 - Master 5 Priority. Sets the arbitration priority for this port on the associated slave port.
3951 * 0b000..This master has level 1, or highest, priority when accessing the slave port.
3952 * 0b001..This master has level 2 priority when accessing the slave port.
3953 * 0b010..This master has level 3 priority when accessing the slave port.
3954 * 0b011..This master has level 4 priority when accessing the slave port.
3955 * 0b100..This master has level 5 priority when accessing the slave port.
3956 * 0b101..This master has level 6 priority when accessing the slave port.
3957 * 0b110..This master has level 7 priority when accessing the slave port.
3958 * 0b111..This master has level 8, or lowest, priority when accessing the slave port.
3959 */
3960#define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
3961/*! @} */
3962
3963/* The count of AXBS_PRS */
3964#define AXBS_PRS_COUNT (8U)
3965
3966/*! @name CRS - Control Register */
3967/*! @{ */
3968#define AXBS_CRS_PARK_MASK (0x7U)
3969#define AXBS_CRS_PARK_SHIFT (0U)
3970/*! PARK - Park
3971 * 0b000..Park on master port M0
3972 * 0b001..Park on master port M1
3973 * 0b010..Park on master port M2
3974 * 0b011..Park on master port M3
3975 * 0b100..Park on master port M4
3976 * 0b101..Park on master port M5
3977 * 0b110..Park on master port M6
3978 * 0b111..Park on master port M7
3979 */
3980#define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
3981#define AXBS_CRS_PCTL_MASK (0x30U)
3982#define AXBS_CRS_PCTL_SHIFT (4U)
3983/*! PCTL - Parking Control
3984 * 0b00..When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field
3985 * 0b01..When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port
3986 * 0b10..When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state
3987 * 0b11..Reserved
3988 */
3989#define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
3990#define AXBS_CRS_ARB_MASK (0x300U)
3991#define AXBS_CRS_ARB_SHIFT (8U)
3992/*! ARB - Arbitration Mode
3993 * 0b00..Fixed priority
3994 * 0b01..Round-robin, or rotating, priority
3995 * 0b10..Reserved
3996 * 0b11..Reserved
3997 */
3998#define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
3999#define AXBS_CRS_HLP_MASK (0x40000000U)
4000#define AXBS_CRS_HLP_SHIFT (30U)
4001/*! HLP - Halt Low Priority
4002 * 0b0..The low power mode request has the highest priority for arbitration on this slave port
4003 * 0b1..The low power mode request has the lowest initial priority for arbitration on this slave port
4004 */
4005#define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
4006#define AXBS_CRS_RO_MASK (0x80000000U)
4007#define AXBS_CRS_RO_SHIFT (31U)
4008/*! RO - Read Only
4009 * 0b0..The slave port's registers are writeable
4010 * 0b1..The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response.
4011 */
4012#define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
4013/*! @} */
4014
4015/* The count of AXBS_CRS */
4016#define AXBS_CRS_COUNT (8U)
4017
4018/*! @name MGPCR0 - Master General Purpose Control Register */
4019/*! @{ */
4020#define AXBS_MGPCR0_AULB_MASK (0x7U)
4021#define AXBS_MGPCR0_AULB_SHIFT (0U)
4022/*! AULB - Arbitrates On Undefined Length Bursts
4023 * 0b000..No arbitration is allowed during an undefined length burst
4024 * 0b001..Arbitration is allowed at any time during an undefined length burst
4025 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4026 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4027 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4028 * 0b101..Reserved
4029 * 0b110..Reserved
4030 * 0b111..Reserved
4031 */
4032#define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
4033/*! @} */
4034
4035/*! @name MGPCR1 - Master General Purpose Control Register */
4036/*! @{ */
4037#define AXBS_MGPCR1_AULB_MASK (0x7U)
4038#define AXBS_MGPCR1_AULB_SHIFT (0U)
4039/*! AULB - Arbitrates On Undefined Length Bursts
4040 * 0b000..No arbitration is allowed during an undefined length burst
4041 * 0b001..Arbitration is allowed at any time during an undefined length burst
4042 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4043 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4044 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4045 * 0b101..Reserved
4046 * 0b110..Reserved
4047 * 0b111..Reserved
4048 */
4049#define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
4050/*! @} */
4051
4052/*! @name MGPCR2 - Master General Purpose Control Register */
4053/*! @{ */
4054#define AXBS_MGPCR2_AULB_MASK (0x7U)
4055#define AXBS_MGPCR2_AULB_SHIFT (0U)
4056/*! AULB - Arbitrates On Undefined Length Bursts
4057 * 0b000..No arbitration is allowed during an undefined length burst
4058 * 0b001..Arbitration is allowed at any time during an undefined length burst
4059 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4060 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4061 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4062 * 0b101..Reserved
4063 * 0b110..Reserved
4064 * 0b111..Reserved
4065 */
4066#define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
4067/*! @} */
4068
4069/*! @name MGPCR3 - Master General Purpose Control Register */
4070/*! @{ */
4071#define AXBS_MGPCR3_AULB_MASK (0x7U)
4072#define AXBS_MGPCR3_AULB_SHIFT (0U)
4073/*! AULB - Arbitrates On Undefined Length Bursts
4074 * 0b000..No arbitration is allowed during an undefined length burst
4075 * 0b001..Arbitration is allowed at any time during an undefined length burst
4076 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4077 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4078 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4079 * 0b101..Reserved
4080 * 0b110..Reserved
4081 * 0b111..Reserved
4082 */
4083#define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
4084/*! @} */
4085
4086/*! @name MGPCR4 - Master General Purpose Control Register */
4087/*! @{ */
4088#define AXBS_MGPCR4_AULB_MASK (0x7U)
4089#define AXBS_MGPCR4_AULB_SHIFT (0U)
4090/*! AULB - Arbitrates On Undefined Length Bursts
4091 * 0b000..No arbitration is allowed during an undefined length burst
4092 * 0b001..Arbitration is allowed at any time during an undefined length burst
4093 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4094 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4095 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4096 * 0b101..Reserved
4097 * 0b110..Reserved
4098 * 0b111..Reserved
4099 */
4100#define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
4101/*! @} */
4102
4103/*! @name MGPCR5 - Master General Purpose Control Register */
4104/*! @{ */
4105#define AXBS_MGPCR5_AULB_MASK (0x7U)
4106#define AXBS_MGPCR5_AULB_SHIFT (0U)
4107/*! AULB - Arbitrates On Undefined Length Bursts
4108 * 0b000..No arbitration is allowed during an undefined length burst
4109 * 0b001..Arbitration is allowed at any time during an undefined length burst
4110 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4111 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4112 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4113 * 0b101..Reserved
4114 * 0b110..Reserved
4115 * 0b111..Reserved
4116 */
4117#define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
4118/*! @} */
4119
4120/*! @name MGPCR6 - Master General Purpose Control Register */
4121/*! @{ */
4122#define AXBS_MGPCR6_AULB_MASK (0x7U)
4123#define AXBS_MGPCR6_AULB_SHIFT (0U)
4124/*! AULB - Arbitrates On Undefined Length Bursts
4125 * 0b000..No arbitration is allowed during an undefined length burst
4126 * 0b001..Arbitration is allowed at any time during an undefined length burst
4127 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4128 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4129 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4130 * 0b101..Reserved
4131 * 0b110..Reserved
4132 * 0b111..Reserved
4133 */
4134#define AXBS_MGPCR6_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)
4135/*! @} */
4136
4137/*! @name MGPCR7 - Master General Purpose Control Register */
4138/*! @{ */
4139#define AXBS_MGPCR7_AULB_MASK (0x7U)
4140#define AXBS_MGPCR7_AULB_SHIFT (0U)
4141/*! AULB - Arbitrates On Undefined Length Bursts
4142 * 0b000..No arbitration is allowed during an undefined length burst
4143 * 0b001..Arbitration is allowed at any time during an undefined length burst
4144 * 0b010..Arbitration is allowed after four beats of an undefined length burst
4145 * 0b011..Arbitration is allowed after eight beats of an undefined length burst
4146 * 0b100..Arbitration is allowed after 16 beats of an undefined length burst
4147 * 0b101..Reserved
4148 * 0b110..Reserved
4149 * 0b111..Reserved
4150 */
4151#define AXBS_MGPCR7_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR7_AULB_SHIFT)) & AXBS_MGPCR7_AULB_MASK)
4152/*! @} */
4153
4154
4155/*!
4156 * @}
4157 */ /* end of group AXBS_Register_Masks */
4158
4159
4160/* AXBS - Peripheral instance base addresses */
4161/** Peripheral AXBS base address */
4162#define AXBS_BASE (0x40004000u)
4163/** Peripheral AXBS base pointer */
4164#define AXBS ((AXBS_Type *)AXBS_BASE)
4165/** Array initializer of AXBS peripheral base addresses */
4166#define AXBS_BASE_ADDRS { AXBS_BASE }
4167/** Array initializer of AXBS peripheral base pointers */
4168#define AXBS_BASE_PTRS { AXBS }
4169
4170/*!
4171 * @}
4172 */ /* end of group AXBS_Peripheral_Access_Layer */
4173
4174
4175/* ----------------------------------------------------------------------------
4176 -- CAU Peripheral Access Layer
4177 ---------------------------------------------------------------------------- */
4178
4179/*!
4180 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
4181 * @{
4182 */
4183
4184/** CAU - Register Layout Typedef */
4185typedef struct {
4186 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
4187 uint8_t RESERVED_0[2048];
4188 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
4189 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
4190 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
4191 uint8_t RESERVED_1[20];
4192 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
4193 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
4194 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
4195 uint8_t RESERVED_2[20];
4196 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
4197 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
4198 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
4199 uint8_t RESERVED_3[20];
4200 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
4201 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
4202 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
4203 uint8_t RESERVED_4[84];
4204 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
4205 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
4206 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
4207 uint8_t RESERVED_5[20];
4208 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
4209 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
4210 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
4211 uint8_t RESERVED_6[276];
4212 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
4213 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
4214 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
4215 uint8_t RESERVED_7[20];
4216 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
4217 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
4218 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
4219} CAU_Type;
4220
4221/* ----------------------------------------------------------------------------
4222 -- CAU Register Masks
4223 ---------------------------------------------------------------------------- */
4224
4225/*!
4226 * @addtogroup CAU_Register_Masks CAU Register Masks
4227 * @{
4228 */
4229
4230/*! @name DIRECT - Direct access register 0..Direct access register 15 */
4231/*! @{ */
4232#define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
4233#define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
4234#define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
4235#define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
4236#define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
4237#define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
4238#define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
4239#define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
4240#define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
4241#define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
4242#define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
4243#define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
4244#define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
4245#define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
4246#define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
4247#define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
4248#define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
4249#define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
4250#define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
4251#define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
4252#define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
4253#define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
4254#define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
4255#define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
4256#define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
4257#define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
4258#define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
4259#define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
4260#define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
4261#define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
4262#define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
4263#define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
4264#define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
4265#define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
4266#define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
4267#define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
4268#define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
4269#define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
4270#define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
4271#define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
4272#define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
4273#define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
4274#define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
4275#define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
4276#define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
4277#define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
4278#define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
4279#define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
4280/*! @} */
4281
4282/* The count of CAU_DIRECT */
4283#define CAU_DIRECT_COUNT (16U)
4284
4285/*! @name LDR_CASR - Status register - Load Register command */
4286/*! @{ */
4287#define CAU_LDR_CASR_IC_MASK (0x1U)
4288#define CAU_LDR_CASR_IC_SHIFT (0U)
4289/*! IC
4290 * 0b0..No illegal commands issued
4291 * 0b1..Illegal command issued
4292 */
4293#define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
4294#define CAU_LDR_CASR_DPE_MASK (0x2U)
4295#define CAU_LDR_CASR_DPE_SHIFT (1U)
4296/*! DPE
4297 * 0b0..No error detected
4298 * 0b1..DES key parity error detected
4299 */
4300#define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
4301#define CAU_LDR_CASR_VER_MASK (0xF0000000U)
4302#define CAU_LDR_CASR_VER_SHIFT (28U)
4303/*! VER - CAU version
4304 * 0b0001..Initial CAU version
4305 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4306 */
4307#define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
4308/*! @} */
4309
4310/*! @name LDR_CAA - Accumulator register - Load Register command */
4311/*! @{ */
4312#define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
4313#define CAU_LDR_CAA_ACC_SHIFT (0U)
4314#define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
4315/*! @} */
4316
4317/*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
4318/*! @{ */
4319#define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
4320#define CAU_LDR_CA_CA0_SHIFT (0U)
4321#define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
4322#define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
4323#define CAU_LDR_CA_CA1_SHIFT (0U)
4324#define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
4325#define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
4326#define CAU_LDR_CA_CA2_SHIFT (0U)
4327#define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
4328#define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
4329#define CAU_LDR_CA_CA3_SHIFT (0U)
4330#define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
4331#define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
4332#define CAU_LDR_CA_CA4_SHIFT (0U)
4333#define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
4334#define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
4335#define CAU_LDR_CA_CA5_SHIFT (0U)
4336#define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
4337#define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
4338#define CAU_LDR_CA_CA6_SHIFT (0U)
4339#define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
4340#define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
4341#define CAU_LDR_CA_CA7_SHIFT (0U)
4342#define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
4343#define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
4344#define CAU_LDR_CA_CA8_SHIFT (0U)
4345#define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
4346/*! @} */
4347
4348/* The count of CAU_LDR_CA */
4349#define CAU_LDR_CA_COUNT (9U)
4350
4351/*! @name STR_CASR - Status register - Store Register command */
4352/*! @{ */
4353#define CAU_STR_CASR_IC_MASK (0x1U)
4354#define CAU_STR_CASR_IC_SHIFT (0U)
4355/*! IC
4356 * 0b0..No illegal commands issued
4357 * 0b1..Illegal command issued
4358 */
4359#define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
4360#define CAU_STR_CASR_DPE_MASK (0x2U)
4361#define CAU_STR_CASR_DPE_SHIFT (1U)
4362/*! DPE
4363 * 0b0..No error detected
4364 * 0b1..DES key parity error detected
4365 */
4366#define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
4367#define CAU_STR_CASR_VER_MASK (0xF0000000U)
4368#define CAU_STR_CASR_VER_SHIFT (28U)
4369/*! VER - CAU version
4370 * 0b0001..Initial CAU version
4371 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4372 */
4373#define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
4374/*! @} */
4375
4376/*! @name STR_CAA - Accumulator register - Store Register command */
4377/*! @{ */
4378#define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
4379#define CAU_STR_CAA_ACC_SHIFT (0U)
4380#define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
4381/*! @} */
4382
4383/*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
4384/*! @{ */
4385#define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
4386#define CAU_STR_CA_CA0_SHIFT (0U)
4387#define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
4388#define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
4389#define CAU_STR_CA_CA1_SHIFT (0U)
4390#define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
4391#define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
4392#define CAU_STR_CA_CA2_SHIFT (0U)
4393#define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
4394#define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
4395#define CAU_STR_CA_CA3_SHIFT (0U)
4396#define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
4397#define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
4398#define CAU_STR_CA_CA4_SHIFT (0U)
4399#define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
4400#define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
4401#define CAU_STR_CA_CA5_SHIFT (0U)
4402#define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
4403#define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
4404#define CAU_STR_CA_CA6_SHIFT (0U)
4405#define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
4406#define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
4407#define CAU_STR_CA_CA7_SHIFT (0U)
4408#define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
4409#define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
4410#define CAU_STR_CA_CA8_SHIFT (0U)
4411#define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
4412/*! @} */
4413
4414/* The count of CAU_STR_CA */
4415#define CAU_STR_CA_COUNT (9U)
4416
4417/*! @name ADR_CASR - Status register - Add Register command */
4418/*! @{ */
4419#define CAU_ADR_CASR_IC_MASK (0x1U)
4420#define CAU_ADR_CASR_IC_SHIFT (0U)
4421/*! IC
4422 * 0b0..No illegal commands issued
4423 * 0b1..Illegal command issued
4424 */
4425#define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
4426#define CAU_ADR_CASR_DPE_MASK (0x2U)
4427#define CAU_ADR_CASR_DPE_SHIFT (1U)
4428/*! DPE
4429 * 0b0..No error detected
4430 * 0b1..DES key parity error detected
4431 */
4432#define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
4433#define CAU_ADR_CASR_VER_MASK (0xF0000000U)
4434#define CAU_ADR_CASR_VER_SHIFT (28U)
4435/*! VER - CAU version
4436 * 0b0001..Initial CAU version
4437 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4438 */
4439#define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
4440/*! @} */
4441
4442/*! @name ADR_CAA - Accumulator register - Add to register command */
4443/*! @{ */
4444#define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
4445#define CAU_ADR_CAA_ACC_SHIFT (0U)
4446#define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
4447/*! @} */
4448
4449/*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
4450/*! @{ */
4451#define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
4452#define CAU_ADR_CA_CA0_SHIFT (0U)
4453#define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
4454#define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
4455#define CAU_ADR_CA_CA1_SHIFT (0U)
4456#define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
4457#define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
4458#define CAU_ADR_CA_CA2_SHIFT (0U)
4459#define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
4460#define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
4461#define CAU_ADR_CA_CA3_SHIFT (0U)
4462#define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
4463#define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
4464#define CAU_ADR_CA_CA4_SHIFT (0U)
4465#define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
4466#define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
4467#define CAU_ADR_CA_CA5_SHIFT (0U)
4468#define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
4469#define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
4470#define CAU_ADR_CA_CA6_SHIFT (0U)
4471#define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
4472#define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
4473#define CAU_ADR_CA_CA7_SHIFT (0U)
4474#define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
4475#define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
4476#define CAU_ADR_CA_CA8_SHIFT (0U)
4477#define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
4478/*! @} */
4479
4480/* The count of CAU_ADR_CA */
4481#define CAU_ADR_CA_COUNT (9U)
4482
4483/*! @name RADR_CASR - Status register - Reverse and Add to Register command */
4484/*! @{ */
4485#define CAU_RADR_CASR_IC_MASK (0x1U)
4486#define CAU_RADR_CASR_IC_SHIFT (0U)
4487/*! IC
4488 * 0b0..No illegal commands issued
4489 * 0b1..Illegal command issued
4490 */
4491#define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
4492#define CAU_RADR_CASR_DPE_MASK (0x2U)
4493#define CAU_RADR_CASR_DPE_SHIFT (1U)
4494/*! DPE
4495 * 0b0..No error detected
4496 * 0b1..DES key parity error detected
4497 */
4498#define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
4499#define CAU_RADR_CASR_VER_MASK (0xF0000000U)
4500#define CAU_RADR_CASR_VER_SHIFT (28U)
4501/*! VER - CAU version
4502 * 0b0001..Initial CAU version
4503 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4504 */
4505#define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
4506/*! @} */
4507
4508/*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
4509/*! @{ */
4510#define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
4511#define CAU_RADR_CAA_ACC_SHIFT (0U)
4512#define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
4513/*! @} */
4514
4515/*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
4516/*! @{ */
4517#define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
4518#define CAU_RADR_CA_CA0_SHIFT (0U)
4519#define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
4520#define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
4521#define CAU_RADR_CA_CA1_SHIFT (0U)
4522#define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
4523#define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
4524#define CAU_RADR_CA_CA2_SHIFT (0U)
4525#define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
4526#define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
4527#define CAU_RADR_CA_CA3_SHIFT (0U)
4528#define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
4529#define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
4530#define CAU_RADR_CA_CA4_SHIFT (0U)
4531#define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
4532#define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
4533#define CAU_RADR_CA_CA5_SHIFT (0U)
4534#define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
4535#define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
4536#define CAU_RADR_CA_CA6_SHIFT (0U)
4537#define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
4538#define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
4539#define CAU_RADR_CA_CA7_SHIFT (0U)
4540#define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
4541#define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
4542#define CAU_RADR_CA_CA8_SHIFT (0U)
4543#define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
4544/*! @} */
4545
4546/* The count of CAU_RADR_CA */
4547#define CAU_RADR_CA_COUNT (9U)
4548
4549/*! @name XOR_CASR - Status register - Exclusive Or command */
4550/*! @{ */
4551#define CAU_XOR_CASR_IC_MASK (0x1U)
4552#define CAU_XOR_CASR_IC_SHIFT (0U)
4553/*! IC
4554 * 0b0..No illegal commands issued
4555 * 0b1..Illegal command issued
4556 */
4557#define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
4558#define CAU_XOR_CASR_DPE_MASK (0x2U)
4559#define CAU_XOR_CASR_DPE_SHIFT (1U)
4560/*! DPE
4561 * 0b0..No error detected
4562 * 0b1..DES key parity error detected
4563 */
4564#define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
4565#define CAU_XOR_CASR_VER_MASK (0xF0000000U)
4566#define CAU_XOR_CASR_VER_SHIFT (28U)
4567/*! VER - CAU version
4568 * 0b0001..Initial CAU version
4569 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4570 */
4571#define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
4572/*! @} */
4573
4574/*! @name XOR_CAA - Accumulator register - Exclusive Or command */
4575/*! @{ */
4576#define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
4577#define CAU_XOR_CAA_ACC_SHIFT (0U)
4578#define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
4579/*! @} */
4580
4581/*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
4582/*! @{ */
4583#define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
4584#define CAU_XOR_CA_CA0_SHIFT (0U)
4585#define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
4586#define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
4587#define CAU_XOR_CA_CA1_SHIFT (0U)
4588#define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
4589#define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
4590#define CAU_XOR_CA_CA2_SHIFT (0U)
4591#define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
4592#define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
4593#define CAU_XOR_CA_CA3_SHIFT (0U)
4594#define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
4595#define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
4596#define CAU_XOR_CA_CA4_SHIFT (0U)
4597#define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
4598#define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
4599#define CAU_XOR_CA_CA5_SHIFT (0U)
4600#define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
4601#define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
4602#define CAU_XOR_CA_CA6_SHIFT (0U)
4603#define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
4604#define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
4605#define CAU_XOR_CA_CA7_SHIFT (0U)
4606#define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
4607#define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
4608#define CAU_XOR_CA_CA8_SHIFT (0U)
4609#define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
4610/*! @} */
4611
4612/* The count of CAU_XOR_CA */
4613#define CAU_XOR_CA_COUNT (9U)
4614
4615/*! @name ROTL_CASR - Status register - Rotate Left command */
4616/*! @{ */
4617#define CAU_ROTL_CASR_IC_MASK (0x1U)
4618#define CAU_ROTL_CASR_IC_SHIFT (0U)
4619/*! IC
4620 * 0b0..No illegal commands issued
4621 * 0b1..Illegal command issued
4622 */
4623#define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
4624#define CAU_ROTL_CASR_DPE_MASK (0x2U)
4625#define CAU_ROTL_CASR_DPE_SHIFT (1U)
4626/*! DPE
4627 * 0b0..No error detected
4628 * 0b1..DES key parity error detected
4629 */
4630#define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
4631#define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
4632#define CAU_ROTL_CASR_VER_SHIFT (28U)
4633/*! VER - CAU version
4634 * 0b0001..Initial CAU version
4635 * 0b0010..Second version, added support for SHA-256 algorithm.(This is the value on this device)
4636 */
4637#define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
4638/*! @} */
4639
4640/*! @name ROTL_CAA - Accumulator register - Rotate Left command */
4641/*! @{ */
4642#define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
4643#define CAU_ROTL_CAA_ACC_SHIFT (0U)
4644#define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
4645/*! @} */
4646
4647/*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
4648/*! @{ */
4649#define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
4650#define CAU_ROTL_CA_CA0_SHIFT (0U)
4651#define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
4652#define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
4653#define CAU_ROTL_CA_CA1_SHIFT (0U)
4654#define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
4655#define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
4656#define CAU_ROTL_CA_CA2_SHIFT (0U)
4657#define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
4658#define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
4659#define CAU_ROTL_CA_CA3_SHIFT (0U)
4660#define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
4661#define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
4662#define CAU_ROTL_CA_CA4_SHIFT (0U)
4663#define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
4664#define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
4665#define CAU_ROTL_CA_CA5_SHIFT (0U)
4666#define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
4667#define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
4668#define CAU_ROTL_CA_CA6_SHIFT (0U)
4669#define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
4670#define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
4671#define CAU_ROTL_CA_CA7_SHIFT (0U)
4672#define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
4673#define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)