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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK27FA15/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MK27FA15/drivers/fsl_clock.h
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1/*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2020, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_CLOCK_H_
10#define _FSL_CLOCK_H_
11
12#include "fsl_common.h"
13
14/*! @addtogroup clock */
15/*! @{ */
16
17/*! @file */
18
19/*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23/*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37#ifndef MCG_CONFIG_CHECK_PARAM
38#define MCG_CONFIG_CHECK_PARAM 0U
39#endif
40
41/*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53#endif
54
55/*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59/*! @name Driver version */
60/*@{*/
61/*! @brief CLOCK driver version 2.5.2. */
62#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 2))
63/*@}*/
64
65/*! @brief External XTAL0 (OSC0) clock frequency.
66 *
67 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
68 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
69 * if XTAL0 is 8 MHz:
70 * @code
71 * Set up the OSC0
72 * CLOCK_InitOsc0(...);
73 * Set the XTAL0 value to the clock driver.
74 * CLOCK_SetXtal0Freq(80000000);
75 * @endcode
76 *
77 * This is important for the multicore platforms where only one core needs to set up the
78 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
79 * to get a valid clock frequency.
80 */
81extern volatile uint32_t g_xtal0Freq;
82
83/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
84 *
85 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
86 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
87 *
88 * This is important for the multicore platforms where only one core needs to set up
89 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
90 * to get a valid clock frequency.
91 */
92extern volatile uint32_t g_xtal32Freq;
93
94/*! @brief IRC48M clock frequency in Hz. */
95#define MCG_INTERNAL_IRC_48M 48000000U
96
97#if (defined(OSC) && !(defined(OSC0)))
98#define OSC0 OSC
99#endif
100
101/* Definition for delay API in clock driver, users can redefine it to the real application. */
102#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
103#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY (120000000UL)
104#endif
105/*! @brief Clock ip name array for DMAMUX. */
106#define DMAMUX_CLOCKS \
107 { \
108 kCLOCK_Dmamux0 \
109 }
110
111/*! @brief Clock ip name array for RTC. */
112#define RTC_CLOCKS \
113 { \
114 kCLOCK_Rtc0 \
115 }
116
117/*! @brief Clock ip name array for SAI. */
118#define SAI_CLOCKS \
119 { \
120 kCLOCK_Sai0, kCLOCK_Sai1 \
121 }
122
123/*! @brief Clock ip name array for PORT. */
124#define PORT_CLOCKS \
125 { \
126 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
127 }
128
129/*! @brief Clock ip name array for FLEXBUS. */
130#define FLEXBUS_CLOCKS \
131 { \
132 kCLOCK_Flexbus0 \
133 }
134
135/*! @brief Clock ip name array for EWM. */
136#define EWM_CLOCKS \
137 { \
138 kCLOCK_Ewm0 \
139 }
140
141/*! @brief Clock ip name array for PIT. */
142#define PIT_CLOCKS \
143 { \
144 kCLOCK_Pit0 \
145 }
146
147/*! @brief Clock ip name array for DSPI. */
148#define DSPI_CLOCKS \
149 { \
150 kCLOCK_Spi0, kCLOCK_Spi1, kCLOCK_Spi2, kCLOCK_Spi3 \
151 }
152
153/*! @brief Clock ip name array for QSPI. */
154#define QSPI_CLOCKS \
155 { \
156 kCLOCK_Qspi0 \
157 }
158
159/*! @brief Clock ip name array for LPTMR. */
160#define LPTMR_CLOCKS \
161 { \
162 kCLOCK_Lptmr0, kCLOCK_Lptmr1 \
163 }
164
165/*! @brief Clock ip name array for SDHC. */
166#define SDHC_CLOCKS \
167 { \
168 kCLOCK_Sdhc0 \
169 }
170
171/*! @brief Clock ip name array for FTM. */
172#define FTM_CLOCKS \
173 { \
174 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3 \
175 }
176
177/*! @brief Clock ip name array for EDMA. */
178#define EDMA_CLOCKS \
179 { \
180 kCLOCK_Dma0 \
181 }
182
183/*! @brief Clock ip name array for LPUART. */
184#define LPUART_CLOCKS \
185 { \
186 kCLOCK_Lpuart0, kCLOCK_Lpuart1, kCLOCK_Lpuart2, kCLOCK_Lpuart3, kCLOCK_Lpuart4 \
187 }
188
189/*! @brief Clock ip name array for DAC. */
190#define DAC_CLOCKS \
191 { \
192 kCLOCK_Dac0 \
193 }
194
195/*! @brief Clock ip name array for ADC16. */
196#define ADC16_CLOCKS \
197 { \
198 kCLOCK_Adc0 \
199 }
200
201/*! @brief Clock ip name array for SDRAM. */
202#define SDRAM_CLOCKS \
203 { \
204 kCLOCK_Sdramc0 \
205 }
206
207/*! @brief Clock ip name array for TRNG. */
208#define TRNG_CLOCKS \
209 { \
210 kCLOCK_Trng0 \
211 }
212
213/*! @brief Clock ip name array for USBHS. */
214#define USBHS_CLOCKS \
215 { \
216 kCLOCK_Usbhs \
217 }
218
219/*! @brief Clock ip name array for USBHSPHY. */
220#define USBHSPHY_CLOCKS \
221 { \
222 kCLOCK_Usbhsphy \
223 }
224
225/*! @brief Clock ip name array for USBHSDCD. */
226#define USBHSDCD_CLOCKS \
227 { \
228 kCLOCK_Usbhsdcd \
229 }
230
231/*! @brief Clock ip name array for MPU. */
232#define SYSMPU_CLOCKS \
233 { \
234 kCLOCK_Sysmpu0 \
235 }
236
237/*! @brief Clock ip name array for FLEXIO. */
238#define FLEXIO_CLOCKS \
239 { \
240 kCLOCK_Flexio0 \
241 }
242
243/*! @brief Clock ip name array for VREF. */
244#define VREF_CLOCKS \
245 { \
246 kCLOCK_Vref0 \
247 }
248
249/*! @brief Clock ip name array for CMT. */
250#define CMT_CLOCKS \
251 { \
252 kCLOCK_Cmt0 \
253 }
254
255/*! @brief Clock ip name array for TPM. */
256#define TPM_CLOCKS \
257 { \
258 kCLOCK_IpInvalid, kCLOCK_Tpm1, kCLOCK_Tpm2 \
259 }
260
261/*! @brief Clock ip name array for TSI. */
262#define TSI_CLOCKS \
263 { \
264 kCLOCK_Tsi0 \
265 }
266
267/*! @brief Clock ip name array for CRC. */
268#define CRC_CLOCKS \
269 { \
270 kCLOCK_Crc0 \
271 }
272
273/*! @brief Clock ip name array for I2C. */
274#define I2C_CLOCKS \
275 { \
276 kCLOCK_I2c0, kCLOCK_I2c1, kCLOCK_I2c2, kCLOCK_I2c3 \
277 }
278
279/*! @brief Clock ip name array for PDB. */
280#define PDB_CLOCKS \
281 { \
282 kCLOCK_Pdb0 \
283 }
284
285/*! @brief Clock ip name array for FTF. */
286#define FTF_CLOCKS \
287 { \
288 kCLOCK_Ftf0 \
289 }
290
291/*! @brief Clock ip name array for CMP. */
292#define CMP_CLOCKS \
293 { \
294 kCLOCK_Cmp0, kCLOCK_Cmp1 \
295 }
296
297/*!
298 * @brief LPO clock frequency.
299 */
300#define LPO_CLK_FREQ 1000U
301
302/*! @brief Peripherals clock source definition. */
303#define SYS_CLK kCLOCK_CoreSysClk
304#define BUS_CLK kCLOCK_BusClk
305
306#define I2C0_CLK_SRC BUS_CLK
307#define I2C1_CLK_SRC BUS_CLK
308#define I2C2_CLK_SRC BUS_CLK
309#define I2C3_CLK_SRC BUS_CLK
310#define DSPI0_CLK_SRC BUS_CLK
311#define DSPI1_CLK_SRC BUS_CLK
312#define DSPI2_CLK_SRC BUS_CLK
313#define DSPI3_CLK_SRC BUS_CLK
314
315/*! @brief Clock name used to get clock frequency. */
316typedef enum _clock_name
317{
318
319 /* ----------------------------- System layer clock -------------------------------*/
320 kCLOCK_CoreSysClk, /*!< Core/system clock */
321 kCLOCK_PlatClk, /*!< Platform clock */
322 kCLOCK_BusClk, /*!< Bus clock */
323 kCLOCK_FlexBusClk, /*!< FlexBus clock */
324 kCLOCK_FlashClk, /*!< Flash clock */
325 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
326 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
327
328 /* ---------------------------------- OSC clock -----------------------------------*/
329 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
330 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
331 kCLOCK_Osc1ErClk, /*!< OSC1 external reference clock (OSC1ERCLK) */
332 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
333
334 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
335 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
336 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
337 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
338 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
339 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
340 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
341 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
342 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
343
344 /* --------------------------------- Other clock ----------------------------------*/
345 kCLOCK_LpoClk, /*!< LPO clock */
346
347} clock_name_t;
348
349/*! @brief USB clock source definition. */
350typedef enum _clock_usb_src
351{
352 kCLOCK_UsbSrcPll0 = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(1U), /*!< Use PLL0. */
353 kCLOCK_UsbSrcUsbPfd = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(2U), /*!< Use USBPFDCLK. */
354 kCLOCK_UsbSrcIrc48M = SIM_SOPT2_USBSRC(1U) | SIM_SOPT2_PLLFLLSEL(3U), /*!< Use IRC48M. */
355 kCLOCK_UsbSrcExt = SIM_SOPT2_USBSRC(0U), /*!< Use USB_CLKIN. */
356 kCLOCK_UsbSrcUnused = 0xFFFFFFFFU, /*!< Used when the function does not
357 care the clock source. */
358} clock_usb_src_t;
359/*------------------------------------------------------------------------------
360
361 clock_gate_t definition:
362
363 31 16 0
364 -----------------------------------------------------------------
365 | SIM_SCGC register offset | control bit offset in SCGC |
366 -----------------------------------------------------------------
367
368 For example, the SDHC clock gate is controlled by SIM_SCGC3[17], the
369 SIM_SCGC3 offset in SIM is 0x1030, then kClockGateSdhc0 is defined as
370
371 kClockGateSdhc0 = (0x1030 << 16) | 17;
372
373------------------------------------------------------------------------------*/
374
375#define CLK_GATE_REG_OFFSET_SHIFT 16U
376#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
377#define CLK_GATE_BIT_SHIFT_SHIFT 0U
378#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
379
380#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
381 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
382 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
383
384#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
385#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
386
387/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
388typedef enum _clock_ip_name
389{
390 kCLOCK_IpInvalid = 0U,
391 kCLOCK_I2c2 = CLK_GATE_DEFINE(0x1028U, 6U),
392 kCLOCK_I2c3 = CLK_GATE_DEFINE(0x1028U, 7U),
393
394 kCLOCK_Lpuart0 = CLK_GATE_DEFINE(0x102CU, 4U),
395 kCLOCK_Lpuart1 = CLK_GATE_DEFINE(0x102CU, 5U),
396 kCLOCK_Lpuart2 = CLK_GATE_DEFINE(0x102CU, 6U),
397 kCLOCK_Lpuart3 = CLK_GATE_DEFINE(0x102CU, 7U),
398 kCLOCK_Tpm1 = CLK_GATE_DEFINE(0x102CU, 9U),
399 kCLOCK_Tpm2 = CLK_GATE_DEFINE(0x102CU, 10U),
400 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x102CU, 12U),
401 kCLOCK_Lpuart4 = CLK_GATE_DEFINE(0x102CU, 22U),
402 kCLOCK_Qspi0 = CLK_GATE_DEFINE(0x102CU, 26U),
403 kCLOCK_Flexio0 = CLK_GATE_DEFINE(0x102CU, 31U),
404
405 kCLOCK_Trng0 = CLK_GATE_DEFINE(0x1030U, 0U),
406 kCLOCK_Usbhs = CLK_GATE_DEFINE(0x1030U, 1U),
407 kCLOCK_Usbhsphy = CLK_GATE_DEFINE(0x1030U, 2U),
408 kCLOCK_Usbhsdcd = CLK_GATE_DEFINE(0x1030U, 3U),
409 kCLOCK_Spi2 = CLK_GATE_DEFINE(0x1030U, 12U),
410 kCLOCK_Spi3 = CLK_GATE_DEFINE(0x1030U, 13U),
411 kCLOCK_Sai1 = CLK_GATE_DEFINE(0x1030U, 15U),
412 kCLOCK_Sdhc0 = CLK_GATE_DEFINE(0x1030U, 17U),
413 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x1030U, 24U),
414 kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x1030U, 25U),
415
416 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
417 kCLOCK_Cmt0 = CLK_GATE_DEFINE(0x1034U, 2U),
418 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
419 kCLOCK_I2c1 = CLK_GATE_DEFINE(0x1034U, 7U),
420 kCLOCK_Usbfs0 = CLK_GATE_DEFINE(0x1034U, 18U),
421 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
422 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
423 kCLOCK_Vref0 = CLK_GATE_DEFINE(0x1034U, 20U),
424
425 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
426 kCLOCK_Lptmr1 = CLK_GATE_DEFINE(0x1038U, 4U),
427 kCLOCK_Tsi0 = CLK_GATE_DEFINE(0x1038U, 5U),
428 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
429 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
430 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
431 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
432 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
433
434 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
435 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
436 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
437 kCLOCK_Spi1 = CLK_GATE_DEFINE(0x103CU, 13U),
438 kCLOCK_Sai0 = CLK_GATE_DEFINE(0x103CU, 15U),
439 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
440 kCLOCK_Usbdcd0 = CLK_GATE_DEFINE(0x103CU, 21U),
441 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
442 kCLOCK_Pit0 = CLK_GATE_DEFINE(0x103CU, 23U),
443 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
444 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
445 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
446 kCLOCK_Rtc0 = CLK_GATE_DEFINE(0x103CU, 29U),
447
448 kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
449 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
450 kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
451 kCLOCK_Sdramc0 = CLK_GATE_DEFINE(0x1040U, 3U),
452} clock_ip_name_t;
453
454/*! @brief Source of the USB HS PHY. */
455typedef enum _clock_usb_phy_src
456{
457 kCLOCK_UsbPhySrcExt = 0U, /*!< Use external crystal. */
458} clock_usb_phy_src_t;
459
460/*! @brief Source of the USB HS PFD clock (USB1PFDCLK) */
461typedef enum _clock_usb_pfd_src
462{
463 kCLOCK_UsbPfdSrcExt = 0U, /*!< Use external crystal. */
464 kCLOCK_UsbPfdSrcFracDivBy4 = 1U, /*!< Use PFD_FRAC output divided by 4. */
465 kCLOCK_UsbPfdSrcFracDivBy2 = 2U, /*!< Use PFD_FRAC output divided by 2. */
466 kCLOCK_UsbPfdSrcFrac = 3U, /*!< Use PFD_FRAC output. */
467} clock_usb_pfd_src_t;
468
469/*!@brief SIM configuration structure for clock setting. */
470typedef struct _sim_clock_config
471{
472 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
473 uint8_t pllFllDiv; /*!< PLLFLLSEL clock divider divisor. */
474 uint8_t pllFllFrac; /*!< PLLFLLSEL clock divider fraction. */
475 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
476 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
477} sim_clock_config_t;
478
479/*! @brief OSC work mode. */
480typedef enum _osc_mode
481{
482 kOSC_ModeExt = 0U, /*!< Use an external clock. */
483#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
484 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
485#else
486 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
487#endif
488 kOSC_ModeOscHighGain = 0U
489#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
490 | MCG_C2_EREFS_MASK
491#else
492 | MCG_C2_EREFS0_MASK
493#endif
494#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
495 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
496#else
497 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
498#endif
499} osc_mode_t;
500
501/*! @brief Oscillator capacitor load setting.*/
502enum _osc_cap_load
503{
504 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
505 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
506 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
507 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
508};
509
510/*! @brief OSCERCLK enable mode. */
511enum _oscer_enable_mode
512{
513 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
514 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
515};
516
517/*! @brief OSC configuration for OSCERCLK. */
518typedef struct _oscer_config
519{
520 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
521
522 uint8_t erclkDiv; /*!< Divider for OSCERCLK.*/
523} oscer_config_t;
524
525/*!
526 * @brief OSC Initialization Configuration Structure
527 *
528 * Defines the configuration data structure to initialize the OSC.
529 * When porting to a new board, set the following members
530 * according to the board setting:
531 * 1. freq: The external frequency.
532 * 2. workMode: The OSC module mode.
533 */
534typedef struct _osc_config
535{
536 uint32_t freq; /*!< External clock frequency. */
537 uint8_t capLoad; /*!< Capacitor load setting. */
538 osc_mode_t workMode; /*!< OSC work mode setting. */
539 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
540} osc_config_t;
541
542/*! @brief MCG FLL reference clock source select. */
543typedef enum _mcg_fll_src
544{
545 kMCG_FllSrcExternal, /*!< External reference clock is selected */
546 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
547} mcg_fll_src_t;
548
549/*! @brief MCG internal reference clock select */
550typedef enum _mcg_irc_mode
551{
552 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
553 kMCG_IrcFast /*!< Fast internal reference clock selected */
554} mcg_irc_mode_t;
555
556/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
557typedef enum _mcg_dmx32
558{
559 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
560 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
561} mcg_dmx32_t;
562
563/*! @brief MCG DCO range select */
564typedef enum _mcg_drs
565{
566 kMCG_DrsLow, /*!< Low frequency range */
567 kMCG_DrsMid, /*!< Mid frequency range */
568 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
569 kMCG_DrsHigh /*!< High frequency range */
570} mcg_drs_t;
571
572/*! @brief MCG PLL reference clock select */
573typedef enum _mcg_pll_ref_src
574{
575 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
576 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
577} mcg_pll_ref_src_t;
578
579/*! @brief MCGOUT clock source. */
580typedef enum _mcg_clkout_src
581{
582 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
583 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
584 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
585} mcg_clkout_src_t;
586
587/*! @brief MCG Automatic Trim Machine Select */
588typedef enum _mcg_atm_select
589{
590 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
591 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
592} mcg_atm_select_t;
593
594/*! @brief MCG OSC Clock Select */
595typedef enum _mcg_oscsel
596{
597 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
598 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
599 kMCG_OscselIrc /*!< Selects 48 MHz IRC Oscillator */
600} mcg_oscsel_t;
601
602/*! @brief MCG PLLCS select */
603typedef enum _mcg_pll_clk_select
604{
605 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
606 kMCG_PllClkSelExtPll /* The external PLL clock is selected */
607} mcg_pll_clk_select_t;
608
609/*! @brief MCG clock monitor mode. */
610typedef enum _mcg_monitor_mode
611{
612 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
613 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
614 kMCG_MonitorReset /*!< System reset when clock lost. */
615} mcg_monitor_mode_t;
616
617/*! @brief MCG status. */
618enum
619{
620 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), /*!< Can't switch to target mode. */
621 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), /*!< Current mode invalid for the specific
622 function. */
623 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), /*!< Invalid bus clock for ATM. */
624 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), /*!< Invalid desired frequency for ATM. */
625 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), /*!< IRC is used when using ATM. */
626 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), /*!< Hardware fail occurs during ATM. */
627 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) /*!< Can't change the clock source because
628 it is in use. */
629};
630
631/*! @brief MCG status flags. */
632enum
633{
634 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
635 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
636 kMCG_RtcOscLostFlag = (1U << 4U), /*!< RTC OSC lost. */
637 kMCG_Pll0LostFlag = (1U << 5U), /*!< PLL0 lost. */
638 kMCG_Pll0LockFlag = (1U << 6U), /*!< PLL0 locked. */
639 kMCG_ExtPllLostFlag = (1U << 9U), /*!< External PLL lost. */
640};
641
642/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
643enum
644{
645 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
646 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
647};
648
649/*! @brief MCG PLL clock enable mode definition. */
650enum
651{
652 kMCG_PllEnableIndependent = MCG_C5_PLLCLKEN0_MASK, /*!< MCGPLLCLK enable independent of the
653 MCG clock mode. Generally, the PLL
654 is disabled in FLL modes
655 (FEI/FBI/FEE/FBE). Setting the PLL clock
656 enable independent, enables the
657 PLL in the FLL modes. */
658 kMCG_PllEnableInStop = MCG_C5_PLLSTEN0_MASK /*!< MCGPLLCLK enable in STOP mode. */
659};
660
661/*! @brief MCG mode definitions */
662typedef enum _mcg_mode
663{
664 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
665 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
666 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
667 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
668 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
669 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
670 kMCG_ModePBE, /*!< PBE - PLL Bypassed External */
671 kMCG_ModePEE, /*!< PEE - PLL Engaged External */
672 kMCG_ModeError /*!< Unknown mode */
673} mcg_mode_t;
674
675/*! @brief MCG PLL configuration. */
676typedef struct _mcg_pll_config
677{
678 uint8_t enableMode; /*!< Enable mode. OR'ed value of @ref _mcg_pll_enable_mode. */
679 uint8_t prdiv; /*!< Reference divider PRDIV. */
680 uint8_t vdiv; /*!< VCO divider VDIV. */
681} mcg_pll_config_t;
682
683/*! @brief MCG mode change configuration structure
684 *
685 * When porting to a new board, set the following members
686 * according to the board setting:
687 * 1. frdiv: If the FLL uses the external reference clock, set this
688 * value to ensure that the external reference clock divided by frdiv is
689 * in the 31.25 kHz to 39.0625 kHz range.
690 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
691 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
692 * FSL_FEATURE_MCG_PLL_REF_MAX range.
693 */
694typedef struct _mcg_config
695{
696 mcg_mode_t mcgMode; /*!< MCG mode. */
697
698 /* ----------------------- MCGIRCCLK settings ------------------------ */
699 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
700 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
701 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
702
703 /* ------------------------ MCG FLL settings ------------------------- */
704 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
705 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
706 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
707 mcg_oscsel_t oscsel; /*!< OSC select MCG_C7[OSCSEL]. */
708
709 /* ------------------------ MCG PLL settings ------------------------- */
710 mcg_pll_config_t pll0Config; /*!< MCGPLL0CLK configuration. */
711
712 mcg_pll_clk_select_t pllcs; /*!< PLL select as output, PLLCS.*/
713
714} mcg_config_t;
715
716/*******************************************************************************
717 * API
718 ******************************************************************************/
719
720#if defined(__cplusplus)
721extern "C" {
722#endif /* __cplusplus */
723
724/*!
725 * @brief Enable the clock for specific IP.
726 *
727 * @param name Which clock to enable, see \ref clock_ip_name_t.
728 */
729static inline void CLOCK_EnableClock(clock_ip_name_t name)
730{
731 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
732 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
733}
734
735/*!
736 * @brief Disable the clock for specific IP.
737 *
738 * @param name Which clock to disable, see \ref clock_ip_name_t.
739 */
740static inline void CLOCK_DisableClock(clock_ip_name_t name)
741{
742 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
743 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
744}
745
746/*!
747 * @brief Set ERCLK32K source.
748 *
749 * @param src The value to set ERCLK32K clock source.
750 */
751static inline void CLOCK_SetEr32kClock(uint32_t src)
752{
753 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
754}
755
756/*!
757 * @brief Set SDHC0 clock source.
758 *
759 * @param src The value to set SDHC0 clock source.
760 */
761static inline void CLOCK_SetSdhc0Clock(uint32_t src)
762{
763 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) | SIM_SOPT2_SDHCSRC(src));
764}
765
766/*!
767 * @brief Set LPUART clock source.
768 *
769 * @param src The value to set LPUART clock source.
770 */
771static inline void CLOCK_SetLpuartClock(uint32_t src)
772{
773 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_LPUARTSRC_MASK) | SIM_SOPT2_LPUARTSRC(src));
774}
775
776/*!
777 * @brief Set TPM clock source.
778 *
779 * @param src The value to set TPM clock source.
780 */
781static inline void CLOCK_SetTpmClock(uint32_t src)
782{
783 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TPMSRC_MASK) | SIM_SOPT2_TPMSRC(src));
784}
785
786/*!
787 * @brief Set FLEXIO clock source.
788 *
789 * @param src The value to set FLEXIO clock source.
790 */
791static inline void CLOCK_SetFlexio0Clock(uint32_t src)
792{
793 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_FLEXIOSRC_MASK) | SIM_SOPT2_FLEXIOSRC(src));
794}
795
796/*!
797 * @brief Set USB clock source.
798 *
799 * @param src The value to set USB clock source.
800 */
801static inline void CLOCK_SetUsbClock(uint32_t src)
802{
803 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_USBSRC_MASK) | SIM_SOPT2_USBSRC(src));
804}
805
806/*!
807 * @brief Set debug trace clock source.
808 *
809 * @param src The value to set debug trace clock source.
810 */
811static inline void CLOCK_SetTraceClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
812{
813 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_TRACECLKSEL_MASK) | SIM_SOPT2_TRACECLKSEL(src));
814 SIM->CLKDIV4 = SIM_CLKDIV4_TRACEDIV(divValue) | SIM_CLKDIV4_TRACEFRAC(fracValue);
815}
816
817/*!
818 * @brief Set PLLFLLSEL clock source.
819 *
820 * @param src The value to set PLLFLLSEL clock source.
821 */
822static inline void CLOCK_SetPllFllSelClock(uint32_t src, uint32_t divValue, uint32_t fracValue)
823{
824 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_PLLFLLSEL_MASK) | SIM_SOPT2_PLLFLLSEL(src));
825 SIM->CLKDIV3 = SIM_CLKDIV3_PLLFLLDIV(divValue) | SIM_CLKDIV3_PLLFLLFRAC(fracValue);
826}
827
828/*!
829 * @brief Set CLKOUT source.
830 *
831 * @param src The value to set CLKOUT source.
832 */
833static inline void CLOCK_SetClkOutClock(uint32_t src)
834{
835 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
836}
837
838/*!
839 * @brief Set RTC_CLKOUT source.
840 *
841 * @param src The value to set RTC_CLKOUT source.
842 */
843static inline void CLOCK_SetRtcClkOutClock(uint32_t src)
844{
845 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_RTCCLKOUTSEL_MASK) | SIM_SOPT2_RTCCLKOUTSEL(src));
846}
847
848/*! @brief Enable USB HS clock.
849 *
850 * @param src USB HS clock source.
851 * @param freq The frequency specified by src.
852 * @retval true The clock is set successfully.
853 * @retval false The clock source is invalid to get proper USB HS clock.
854 */
855bool CLOCK_EnableUsbhs0Clock(clock_usb_src_t src, uint32_t freq);
856
857/*! @brief Disable USB HS clock.
858 *
859 * Disable USB HS clock.
860 *
861 */
862void CLOCK_DisableUsbhs0Clock(void);
863
864/*! @ brief Disable USB hs0 Phy Pll Clock
865 *
866 * Disable USB hs0 Phy Pll Clock
867 */
868void CLOCK_DisableUsbhs0PhyPllClock(void);
869
870/*! Enable USB hs0 Pfd clock
871 *
872 * @param src USB hs0 clock source.
873 *
874 */
875void CLOCK_EnableUsbhs0PfdClock(uint8_t frac, clock_usb_pfd_src_t src);
876
877/*! @ brief Disable USB hs0 Pfd Pll Clock
878 *
879 * Disable USB hs0 Pfd Pll Clock
880 */
881void CLOCK_DisableUsbhs0PfdClock(void);
882
883/*! @brief Enable USB FS clock.
884 *
885 * @param src USB FS clock source.
886 * @param freq The frequency specified by src.
887 * @retval true The clock is set successfully.
888 * @retval false The clock source is invalid to get proper USB FS clock.
889 */
890bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
891
892/*! @brief Enable USB hs0PhyPll clock.
893 *
894 * @param src USB HS clock source.
895 * @param freq The frequency specified by src.
896 * @retval true The clock is set successfully.
897 * @retval false The clock source is invalid to get proper USB HS clock.
898 */
899bool CLOCK_EnableUsbhs0PhyPllClock(clock_usb_phy_src_t src, uint32_t freq);
900
901/*! @brief Disable USB FS clock.
902 *
903 * Disable USB FS clock.
904 */
905static inline void CLOCK_DisableUsbfs0Clock(void)
906{
907 CLOCK_DisableClock(kCLOCK_Usbfs0);
908}
909
910/*!
911 * @brief System clock divider
912 *
913 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV2], SIM_CLKDIV1[OUTDIV3], SIM_CLKDIV1[OUTDIV4].
914 *
915 * @param outdiv1 Clock 1 output divider value.
916 *
917 * @param outdiv2 Clock 2 output divider value.
918 *
919 * @param outdiv3 Clock 3 output divider value.
920 *
921 * @param outdiv4 Clock 4 output divider value.
922 */
923static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv2, uint32_t outdiv3, uint32_t outdiv4)
924{
925 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV2(outdiv2) | SIM_CLKDIV1_OUTDIV3(outdiv3) |
926 SIM_CLKDIV1_OUTDIV4(outdiv4);
927}
928
929/*!
930 * @brief Gets the clock frequency for a specific clock name.
931 *
932 * This function checks the current clock configurations and then calculates
933 * the clock frequency for a specific clock name defined in clock_name_t.
934 * The MCG must be properly configured before using this function.
935 *
936 * @param clockName Clock names defined in clock_name_t
937 * @return Clock frequency value in Hertz
938 */
939uint32_t CLOCK_GetFreq(clock_name_t clockName);
940
941/*!
942 * @brief Get the core clock or system clock frequency.
943 *
944 * @return Clock frequency in Hz.
945 */
946uint32_t CLOCK_GetCoreSysClkFreq(void);
947
948/*!
949 * @brief Get the platform clock frequency.
950 *
951 * @return Clock frequency in Hz.
952 */
953uint32_t CLOCK_GetPlatClkFreq(void);
954
955/*!
956 * @brief Get the bus clock frequency.
957 *
958 * @return Clock frequency in Hz.
959 */
960uint32_t CLOCK_GetBusClkFreq(void);
961
962/*!
963 * @brief Get the flexbus clock frequency.
964 *
965 * @return Clock frequency in Hz.
966 */
967uint32_t CLOCK_GetFlexBusClkFreq(void);
968
969/*!
970 * @brief Get the flash clock frequency.
971 *
972 * @return Clock frequency in Hz.
973 */
974uint32_t CLOCK_GetFlashClkFreq(void);
975
976/*!
977 * @brief Get the output clock frequency selected by SIM[PLLFLLSEL].
978 *
979 * @return Clock frequency in Hz.
980 */
981uint32_t CLOCK_GetPllFllSelClkFreq(void);
982
983/*!
984 * @brief Get the external reference 32K clock frequency (ERCLK32K).
985 *
986 * @return Clock frequency in Hz.
987 */
988uint32_t CLOCK_GetEr32kClkFreq(void);
989
990/*!
991 * @brief Get the OSC0 external reference undivided clock frequency (OSC0ERCLK_UNDIV).
992 *
993 * @return Clock frequency in Hz.
994 */
995uint32_t CLOCK_GetOsc0ErClkUndivFreq(void);
996
997/*!
998 * @brief Get the OSC0 external reference divided clock frequency (OSC0ERCLK_UNDIV).
999 *
1000 * @return Clock frequency
1001 */
1002uint32_t CLOCK_GetOsc0ErClkDivFreq(void);
1003
1004/*!
1005 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
1006 *
1007 * @return Clock frequency in Hz.
1008 */
1009uint32_t CLOCK_GetOsc0ErClkFreq(void);
1010
1011/*!
1012 * @brief Set the clock configure in SIM module.
1013 *
1014 * This function sets system layer clock settings in SIM module.
1015 *
1016 * @param config Pointer to the configure structure.
1017 */
1018void CLOCK_SetSimConfig(sim_clock_config_t const *config);
1019
1020/*!
1021 * @brief Set the system clock dividers in SIM to safe value.
1022 *
1023 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
1024 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
1025 * changes then the system level clocks may be out of range. This function could
1026 * be used before MCG mode change, to make sure system level clocks are in allowed
1027 * range.
1028 *
1029 * @param config Pointer to the configure structure.
1030 */
1031static inline void CLOCK_SetSimSafeDivs(void)
1032{
1033 SIM->CLKDIV1 = 0x02260000U;
1034}
1035
1036/*! @name MCG frequency functions. */
1037/*@{*/
1038
1039/*!
1040 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
1041 *
1042 * This function gets the MCG output clock frequency in Hz based on the current MCG
1043 * register value.
1044 *
1045 * @return The frequency of MCGOUTCLK.
1046 */
1047uint32_t CLOCK_GetOutClkFreq(void);
1048
1049/*!
1050 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
1051 *
1052 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
1053 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
1054 * disabled in low power state in other modes.
1055 *
1056 * @return The frequency of MCGFLLCLK.
1057 */
1058uint32_t CLOCK_GetFllFreq(void);
1059
1060/*!
1061 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
1062 *
1063 * This function gets the MCG internal reference clock frequency in Hz based
1064 * on the current MCG register value.
1065 *
1066 * @return The frequency of MCGIRCLK.
1067 */
1068uint32_t CLOCK_GetInternalRefClkFreq(void);
1069
1070/*!
1071 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
1072 *
1073 * This function gets the MCG fixed frequency clock frequency in Hz based
1074 * on the current MCG register value.
1075 *
1076 * @return The frequency of MCGFFCLK.
1077 */
1078uint32_t CLOCK_GetFixedFreqClkFreq(void);
1079
1080/*!
1081 * @brief Gets the MCG PLL0 clock (MCGPLL0CLK) frequency.
1082 *
1083 * This function gets the MCG PLL0 clock frequency in Hz based on the current MCG
1084 * register value.
1085 *
1086 * @return The frequency of MCGPLL0CLK.
1087 */
1088uint32_t CLOCK_GetPll0Freq(void);
1089
1090/*!
1091 * @brief Gets the MCG external PLL frequency.
1092 *
1093 * This function gets the MCG external PLL frequency in Hz.
1094 *
1095 * @return The frequency of the MCG external PLL.
1096 */
1097uint32_t CLOCK_GetExtPllFreq(void);
1098
1099/*!
1100 * @brief Sets the MCG external PLL frequency.
1101 *
1102 * This function sets the MCG external PLL frequency in Hz. The MCG external PLL
1103 * frequency is passed to the MCG driver using this function. Call this
1104 * function after the external PLL frequency is changed. Otherwise, the APIs, which are used to get
1105 * the frequency, may return an incorrect value.
1106 *
1107 * @param The frequency of MCG external PLL.
1108 */
1109void CLOCK_SetExtPllFreq(uint32_t freq);
1110
1111/*@}*/
1112
1113/*! @name MCG clock configuration. */
1114/*@{*/
1115
1116/*!
1117 * @brief Enables or disables the MCG low power.
1118 *
1119 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
1120 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
1121 * PBI modes, enabling low power sets the MCG to BLPI mode.
1122 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
1123 *
1124 * @param enable True to enable MCG low power, false to disable MCG low power.
1125 */
1126static inline void CLOCK_SetLowPowerEnable(bool enable)
1127{
1128 if (enable)
1129 {
1130 MCG->C2 |= MCG_C2_LP_MASK;
1131 }
1132 else
1133 {
1134 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
1135 }
1136}
1137
1138/*!
1139 * @brief Configures the Internal Reference clock (MCGIRCLK).
1140 *
1141 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
1142 * source. If the fast IRC is used, this function sets the fast IRC divider.
1143 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
1144 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
1145 * using the function in these modes it is not allowed.
1146 *
1147 * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
1148 * @param ircs MCGIRCLK clock source, choose fast or slow.
1149 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
1150 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
1151 * the configuration should not be changed. Otherwise, a glitch occurs.
1152 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
1153 */
1154status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
1155
1156/*!
1157 * @brief Selects the MCG external reference clock.
1158 *
1159 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
1160 * and waits for the clock source to be stable. Because the external reference
1161 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
1162 *
1163 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
1164 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
1165 * the configuration should not be changed. Otherwise, a glitch occurs.
1166 * @retval kStatus_Success External reference clock set successfully.
1167 */
1168status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
1169
1170/*!
1171 * @brief Set the FLL external reference clock divider value.
1172 *
1173 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
1174 *
1175 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
1176 */
1177static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
1178{
1179 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
1180}
1181
1182/*!
1183 * @brief Enables the PLL0 in FLL mode.
1184 *
1185 * This function sets us the PLL0 in FLL mode and reconfigures
1186 * the PLL0. Ensure that the PLL reference
1187 * clock is enabled before calling this function and that the PLL0 is not used as a clock source.
1188 * The function CLOCK_CalcPllDiv gets the correct PLL
1189 * divider values.
1190 *
1191 * @param config Pointer to the configuration structure.
1192 */
1193void CLOCK_EnablePll0(mcg_pll_config_t const *config);
1194
1195/*!
1196 * @brief Disables the PLL0 in FLL mode.
1197 *
1198 * This function disables the PLL0 in FLL mode. It should be used together with the
1199 * @ref CLOCK_EnablePll0.
1200 */
1201static inline void CLOCK_DisablePll0(void)
1202{
1203 MCG->C5 &= (uint8_t)(~(MCG_C5_PLLCLKEN0_MASK | MCG_C5_PLLSTEN0_MASK));
1204}
1205
1206/*!
1207 * @brief Calculates the PLL divider setting for a desired output frequency.
1208 *
1209 * This function calculates the correct reference clock divider (\c PRDIV) and
1210 * VCO divider (\c VDIV) to generate a desired PLL output frequency. It returns the
1211 * closest frequency match with the corresponding \c PRDIV/VDIV
1212 * returned from parameters. If a desired frequency is not valid, this function
1213 * returns 0.
1214 *
1215 * @param refFreq PLL reference clock frequency.
1216 * @param desireFreq Desired PLL output frequency.
1217 * @param prdiv PRDIV value to generate desired PLL frequency.
1218 * @param vdiv VDIV value to generate desired PLL frequency.
1219 * @return Closest frequency match that the PLL was able generate.
1220 */
1221uint32_t CLOCK_CalcPllDiv(uint32_t refFreq, uint32_t desireFreq, uint8_t *prdiv, uint8_t *vdiv);
1222
1223/*!
1224 * @brief Set the PLL selection.
1225 *
1226 * This function sets the PLL selection between PLL0/PLL1/EXTPLL, and waits for
1227 * change finished.
1228 *
1229 * @param pllcs The PLL to select.
1230 */
1231void CLOCK_SetPllClkSel(mcg_pll_clk_select_t pllcs);
1232
1233/*@}*/
1234
1235/*! @name MCG clock lock monitor functions. */
1236/*@{*/
1237
1238/*!
1239 * @brief Sets the OSC0 clock monitor mode.
1240 *
1241 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1242 *
1243 * @param mode Monitor mode to set.
1244 */
1245void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
1246
1247/*!
1248 * @brief Sets the RTC OSC clock monitor mode.
1249 *
1250 * This function sets the RTC OSC clock monitor mode. See @ref mcg_monitor_mode_t for details.
1251 *
1252 * @param mode Monitor mode to set.
1253 */
1254void CLOCK_SetRtcOscMonitorMode(mcg_monitor_mode_t mode);
1255
1256/*!
1257 * @brief Sets the PLL0 clock monitor mode.
1258 *
1259 * This function sets the PLL0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
1260 *
1261 * @param mode Monitor mode to set.
1262 */
1263void CLOCK_SetPll0MonitorMode(mcg_monitor_mode_t mode);
1264
1265/*!
1266 * @brief Sets the external PLL clock monitor mode.
1267 *
1268 * This function ets the external PLL clock monitor mode. See @ref mcg_monitor_mode_t
1269 * for details.
1270 *
1271 * @param mode Monitor mode to set.
1272 */
1273void CLOCK_SetExtPllMonitorMode(mcg_monitor_mode_t mode);
1274
1275/*!
1276 * @brief Gets the MCG status flags.
1277 *
1278 * This function gets the MCG clock status flags. All status flags are
1279 * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
1280 * check a specific flag, compare the return value with the flag.
1281 *
1282 * Example:
1283 * @code
1284 * To check the clock lost lock status of OSC0 and PLL0.
1285 * uint32_t mcgFlags;
1286 *
1287 * mcgFlags = CLOCK_GetStatusFlags();
1288 *
1289 * if (mcgFlags & kMCG_Osc0LostFlag)
1290 * {
1291 * OSC0 clock lock lost. Do something.
1292 * }
1293 * if (mcgFlags & kMCG_Pll0LostFlag)
1294 * {
1295 * PLL0 clock lock lost. Do something.
1296 * }
1297 * @endcode
1298 *
1299 * @return Logical OR value of the @ref _mcg_status_flags_t.
1300 */
1301uint32_t CLOCK_GetStatusFlags(void);
1302
1303/*!
1304 * @brief Clears the MCG status flags.
1305 *
1306 * This function clears the MCG clock lock lost status. The parameter is a logical
1307 * OR value of the flags to clear. See @ref _mcg_status_flags_t.
1308 *
1309 * Example:
1310 * @code
1311 * To clear the clock lost lock status flags of OSC0 and PLL0.
1312 *
1313 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
1314 * @endcode
1315 *
1316 * @param mask The status flags to clear. This is a logical OR of members of the
1317 * enumeration @ref _mcg_status_flags_t.
1318 */
1319void CLOCK_ClearStatusFlags(uint32_t mask);
1320
1321/*@}*/
1322
1323/*!
1324 * @name OSC configuration
1325 * @{
1326 */
1327
1328/*!
1329 * @brief Configures the OSC external reference clock (OSCERCLK).
1330 *
1331 * This function configures the OSC external reference clock (OSCERCLK).
1332 * This is an example to enable the OSCERCLK in normal and stop modes and also set
1333 * the output divider to 1:
1334 *
1335 @code
1336 oscer_config_t config =
1337 {
1338 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
1339 .erclkDiv = 1U,
1340 };
1341
1342 OSC_SetExtRefClkConfig(OSC, &config);
1343 @endcode
1344 *
1345 * @param base OSC peripheral address.
1346 * @param config Pointer to the configuration structure.
1347 */
1348static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
1349{
1350 uint8_t reg = base->CR;
1351
1352 reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
1353 reg |= config->enableMode;
1354
1355 base->CR = reg;
1356
1357 base->DIV = OSC_DIV_ERPS(config->erclkDiv);
1358}
1359
1360/*!
1361 * @brief Sets the capacitor load configuration for the oscillator.
1362 *
1363 * This function sets the specified capacitors configuration for the oscillator.
1364 * This should be done in the early system level initialization function call
1365 * based on the system configuration.
1366 *
1367 * @param base OSC peripheral address.
1368 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
1369 *
1370 * Example:
1371 @code
1372 To enable only 2 pF and 8 pF capacitor load, please use like this.
1373 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
1374 @endcode
1375 */
1376static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
1377{
1378 uint8_t reg = base->CR;
1379
1380 reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
1381 reg |= capLoad;
1382
1383 base->CR = reg;
1384}
1385
1386/*!
1387 * @brief Initializes the OSC0.
1388 *
1389 * This function initializes the OSC0 according to the board configuration.
1390 *
1391 * @param config Pointer to the OSC0 configuration structure.
1392 */
1393void CLOCK_InitOsc0(osc_config_t const *config);
1394
1395/*!
1396 * @brief Deinitializes the OSC0.
1397 *
1398 * This function deinitializes the OSC0.
1399 */
1400void CLOCK_DeinitOsc0(void);
1401
1402/* @} */
1403
1404/*!
1405 * @name External clock frequency
1406 * @{
1407 */
1408
1409/*!
1410 * @brief Sets the XTAL0 frequency based on board settings.
1411 *
1412 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
1413 */
1414static inline void CLOCK_SetXtal0Freq(uint32_t freq)
1415{
1416 g_xtal0Freq = freq;
1417}
1418
1419/*!
1420 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
1421 *
1422 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
1423 */
1424static inline void CLOCK_SetXtal32Freq(uint32_t freq)
1425{
1426 g_xtal32Freq = freq;
1427}
1428/* @} */
1429
1430/*!
1431 * @name IRCs frequency
1432 * @{
1433 */
1434
1435/*!
1436 * @brief Set the Slow IRC frequency based on the trimmed value
1437 *
1438 * @param freq The Slow IRC frequency input clock frequency in Hz.
1439 */
1440void CLOCK_SetSlowIrcFreq(uint32_t freq);
1441
1442/*!
1443 * @brief Set the Fast IRC frequency based on the trimmed value
1444 *
1445 * @param freq The Fast IRC frequency input clock frequency in Hz.
1446 */
1447void CLOCK_SetFastIrcFreq(uint32_t freq);
1448/* @} */
1449
1450/*!
1451 * @name MCG auto-trim machine.
1452 * @{
1453 */
1454
1455/*!
1456 * @brief Auto trims the internal reference clock.
1457 *
1458 * This function trims the internal reference clock by using the external clock. If
1459 * successful, it returns the kStatus_Success and the frequency after
1460 * trimming is received in the parameter @p actualFreq. If an error occurs,
1461 * the error code is returned.
1462 *
1463 * @param extFreq External clock frequency, which should be a bus clock.
1464 * @param desireFreq Frequency to trim to.
1465 * @param actualFreq Actual frequency after trimming.
1466 * @param atms Trim fast or slow internal reference clock.
1467 * @retval kStatus_Success ATM success.
1468 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
1469 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
1470 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
1471 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
1472 */
1473status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
1474/* @} */
1475
1476/*! @name MCG mode functions. */
1477/*@{*/
1478
1479/*!
1480 * @brief Gets the current MCG mode.
1481 *
1482 * This function checks the MCG registers and determines the current MCG mode.
1483 *
1484 * @return Current MCG mode or error code; See @ref mcg_mode_t.
1485 */
1486mcg_mode_t CLOCK_GetMode(void);
1487
1488/*!
1489 * @brief Sets the MCG to FEI mode.
1490 *
1491 * This function sets the MCG to FEI mode. If setting to FEI mode fails
1492 * from the current mode, this function returns an error.
1493 *
1494 * @param dmx32 DMX32 in FEI mode.
1495 * @param drs The DCO range selection.
1496 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1497 * NULL does not cause a delay.
1498 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1499 * @retval kStatus_Success Switched to the target mode successfully.
1500 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1501 * to a frequency above 32768 Hz.
1502 */
1503status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1504
1505/*!
1506 * @brief Sets the MCG to FEE mode.
1507 *
1508 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1509 * from the current mode, this function returns an error.
1510 *
1511 * @param frdiv FLL reference clock divider setting, FRDIV.
1512 * @param dmx32 DMX32 in FEE mode.
1513 * @param drs The DCO range selection.
1514 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1515 * NULL does not cause a delay.
1516 *
1517 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1518 * @retval kStatus_Success Switched to the target mode successfully.
1519 */
1520status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1521
1522/*!
1523 * @brief Sets the MCG to FBI mode.
1524 *
1525 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1526 * from the current mode, this function returns an error.
1527 *
1528 * @param dmx32 DMX32 in FBI mode.
1529 * @param drs The DCO range selection.
1530 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1531 * is not used in FBI mode, this parameter can be NULL. Passing
1532 * NULL does not cause a delay.
1533 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1534 * @retval kStatus_Success Switched to the target mode successfully.
1535 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1536 * to frequency above 32768 Hz.
1537 */
1538status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1539
1540/*!
1541 * @brief Sets the MCG to FBE mode.
1542 *
1543 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1544 * from the current mode, this function returns an error.
1545 *
1546 * @param frdiv FLL reference clock divider setting, FRDIV.
1547 * @param dmx32 DMX32 in FBE mode.
1548 * @param drs The DCO range selection.
1549 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1550 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1551 * does not cause a delay.
1552 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1553 * @retval kStatus_Success Switched to the target mode successfully.
1554 */
1555status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1556
1557/*!
1558 * @brief Sets the MCG to BLPI mode.
1559 *
1560 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1561 * from the current mode, this function returns an error.
1562 *
1563 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1564 * @retval kStatus_Success Switched to the target mode successfully.
1565 */
1566status_t CLOCK_SetBlpiMode(void);
1567
1568/*!
1569 * @brief Sets the MCG to BLPE mode.
1570 *
1571 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1572 * from the current mode, this function returns an error.
1573 *
1574 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1575 * @retval kStatus_Success Switched to the target mode successfully.
1576 */
1577status_t CLOCK_SetBlpeMode(void);
1578
1579/*!
1580 * @brief Sets the MCG to PBE mode.
1581 *
1582 * This function sets the MCG to PBE mode. If setting to PBE mode fails
1583 * from the current mode, this function returns an error.
1584 *
1585 * @param pllcs The PLL selection, PLLCS.
1586 * @param config Pointer to the PLL configuration.
1587 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1588 * @retval kStatus_Success Switched to the target mode successfully.
1589 *
1590 * @note
1591 * 1. The parameter \c pllcs selects the PLL. For platforms with
1592 * only one PLL, the parameter pllcs is kept for interface compatibility.
1593 * 2. The parameter \c config is the PLL configuration structure. On some
1594 * platforms, it is possible to choose the external PLL directly, which renders the
1595 * configuration structure not necessary. In this case, pass in NULL.
1596 * For example: CLOCK_SetPbeMode(kMCG_OscselOsc, kMCG_PllClkSelExtPll, NULL);
1597 */
1598status_t CLOCK_SetPbeMode(mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1599
1600/*!
1601 * @brief Sets the MCG to PEE mode.
1602 *
1603 * This function sets the MCG to PEE mode.
1604 *
1605 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1606 * @retval kStatus_Success Switched to the target mode successfully.
1607 *
1608 * @note This function only changes the CLKS to use the PLL/FLL output. If the
1609 * PRDIV/VDIV are different than in the PBE mode, set them up
1610 * in PBE mode and wait. When the clock is stable, switch to PEE mode.
1611 */
1612status_t CLOCK_SetPeeMode(void);
1613
1614/*!
1615 * @brief Switches the MCG to FBE mode from the external mode.
1616 *
1617 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1618 * The external clock is used as the system clock source and PLL is disabled. However,
1619 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1620 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1621 *
1622 * @code
1623 * CLOCK_ExternalModeToFbeModeQuick();
1624 * CLOCK_SetFeiMode(...);
1625 * @endcode
1626 *
1627 * @retval kStatus_Success Switched successfully.
1628 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1629 */
1630status_t CLOCK_ExternalModeToFbeModeQuick(void);
1631
1632/*!
1633 * @brief Switches the MCG to FBI mode from internal modes.
1634 *
1635 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1636 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1637 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1638 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1639 *
1640 * @code
1641 * CLOCK_InternalModeToFbiModeQuick();
1642 * CLOCK_SetFeeMode(...);
1643 * @endcode
1644 *
1645 * @retval kStatus_Success Switched successfully.
1646 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1647 */
1648status_t CLOCK_InternalModeToFbiModeQuick(void);
1649
1650/*!
1651 * @brief Sets the MCG to FEI mode during system boot up.
1652 *
1653 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1654 * set up MCG during system boot up.
1655 *
1656 * @param dmx32 DMX32 in FEI mode.
1657 * @param drs The DCO range selection.
1658 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1659 *
1660 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1661 * @retval kStatus_Success Switched to the target mode successfully.
1662 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1663 * to frequency above 32768 Hz.
1664 */
1665status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1666
1667/*!
1668 * @brief Sets the MCG to FEE mode during system bootup.
1669 *
1670 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1671 * set up the MCG during system boot up.
1672 *
1673 * @param oscsel OSC clock select, OSCSEL.
1674 * @param frdiv FLL reference clock divider setting, FRDIV.
1675 * @param dmx32 DMX32 in FEE mode.
1676 * @param drs The DCO range selection.
1677 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1678 *
1679 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1680 * @retval kStatus_Success Switched to the target mode successfully.
1681 */
1682status_t CLOCK_BootToFeeMode(
1683 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1684
1685/*!
1686 * @brief Sets the MCG to BLPI mode during system boot up.
1687 *
1688 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1689 * set up the MCG during system boot up.
1690 *
1691 * @param fcrdiv Fast IRC divider, FCRDIV.
1692 * @param ircs The internal reference clock to select, IRCS.
1693 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
1694 *
1695 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1696 * @retval kStatus_Success Switched to the target mode successfully.
1697 */
1698status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1699
1700/*!
1701 * @brief Sets the MCG to BLPE mode during system boot up.
1702 *
1703 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1704 * set up the MCG during system boot up.
1705 *
1706 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1707 *
1708 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1709 * @retval kStatus_Success Switched to the target mode successfully.
1710 */
1711status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1712
1713/*!
1714 * @brief Sets the MCG to PEE mode during system boot up.
1715 *
1716 * This function sets the MCG to PEE mode from reset mode. It can also be used to
1717 * set up the MCG during system boot up.
1718 *
1719 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1720 * @param pllcs The PLL selection, PLLCS.
1721 * @param config Pointer to the PLL configuration.
1722 *
1723 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1724 * @retval kStatus_Success Switched to the target mode successfully.
1725 */
1726status_t CLOCK_BootToPeeMode(mcg_oscsel_t oscsel, mcg_pll_clk_select_t pllcs, mcg_pll_config_t const *config);
1727
1728/*!
1729 * @brief Sets the MCG to a target mode.
1730 *
1731 * This function sets MCG to a target mode defined by the configuration
1732 * structure. If switching to the target mode fails, this function
1733 * chooses the correct path.
1734 *
1735 * @param config Pointer to the target MCG mode configuration structure.
1736 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
1737 *
1738 * @note If the external clock is used in the target mode, ensure that it is
1739 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1740 * function.
1741 */
1742status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1743
1744/*@}*/
1745
1746#if defined(__cplusplus)
1747}
1748#endif /* __cplusplus */
1749
1750/*! @} */
1751
1752#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 05:23:48 +0100