aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios-contrib/ext/mcux-sdk/devices/MK63F12/system_MK63F12.c
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios-contrib/ext/mcux-sdk/devices/MK63F12/system_MK63F12.c')
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/devices/MK63F12/system_MK63F12.c229
1 files changed, 229 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MK63F12/system_MK63F12.c b/lib/chibios-contrib/ext/mcux-sdk/devices/MK63F12/system_MK63F12.c
new file mode 100644
index 000000000..cbed619ac
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/devices/MK63F12/system_MK63F12.c
@@ -0,0 +1,229 @@
1/*
2** ###################################################################
3** Processors: MK63FN1M0VLQ12
4** MK63FN1M0VMD12
5**
6** Compilers: Freescale C/C++ for Embedded ARM
7** GNU C Compiler
8** IAR ANSI C/C++ Compiler for ARM
9** Keil ARM C/C++ Compiler
10** MCUXpresso Compiler
11**
12** Reference manual: K63P144M120SF5RM, Rev.2, January 2014
13** Version: rev. 2.7, 2015-02-19
14** Build: b181105
15**
16** Abstract:
17** Provides a system configuration function and a global variable that
18** contains the system frequency. It configures the device and initializes
19** the oscillator (PLL) that is part of the microcontroller device.
20**
21** Copyright 2016 Freescale Semiconductor, Inc.
22** Copyright 2016-2018 NXP
23** All rights reserved.
24**
25** SPDX-License-Identifier: BSD-3-Clause
26**
27** http: www.nxp.com
28** mail: [email protected]
29**
30** Revisions:
31** - rev. 1.0 (2013-05-03)
32** Initial version.
33** - rev. 2.0 (2013-10-29)
34** Register accessor macros added to the memory map.
35** Symbols for Processor Expert memory map compatibility added to the memory map.
36** Startup file for gcc has been updated according to CMSIS 3.2.
37** System initialization updated.
38** MCG - registers updated.
39** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
40** - rev. 2.1 (2013-10-30)
41** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
42** - rev. 2.2 (2013-12-09)
43** DMA - EARS register removed.
44** AIPS0, AIPS1 - MPRA register updated.
45** - rev. 2.3 (2014-01-24)
46** Update according to reference manual rev. 2
47** ENET, MCG, MCM, SIM, USB - registers updated
48** - rev. 2.4 (2014-02-10)
49** The declaration of clock configurations has been moved to separate header file system_MK63F12.h
50** Update of SystemInit() and SystemCoreClockUpdate() functions.
51** Module access macro module_BASES replaced by module_BASE_PTRS.
52** - rev. 2.5 (2014-08-28)
53** Update of system files - default clock configuration changed.
54** Update of startup files - possibility to override DefaultISR added.
55** - rev. 2.6 (2014-10-14)
56** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
57** - rev. 2.7 (2015-02-19)
58** Renamed interrupt vector LLW to LLWU.
59**
60** ###################################################################
61*/
62
63/*!
64 * @file MK63F12
65 * @version 2.7
66 * @date 2015-02-19
67 * @brief Device specific configuration file for MK63F12 (implementation file)
68 *
69 * Provides a system configuration function and a global variable that contains
70 * the system frequency. It configures the device and initializes the oscillator
71 * (PLL) that is part of the microcontroller device.
72 */
73
74#include <stdint.h>
75#include "fsl_device_registers.h"
76
77
78
79/* ----------------------------------------------------------------------------
80 -- Core clock
81 ---------------------------------------------------------------------------- */
82
83uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
84
85/* ----------------------------------------------------------------------------
86 -- SystemInit()
87 ---------------------------------------------------------------------------- */
88
89void SystemInit (void) {
90#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
91 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
92#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
93#if (DISABLE_WDOG)
94 /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
95 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
96 /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
97 WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
98 /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
99 WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
100 WDOG_STCTRLH_WAITEN_MASK |
101 WDOG_STCTRLH_STOPEN_MASK |
102 WDOG_STCTRLH_ALLOWUPDATE_MASK |
103 WDOG_STCTRLH_CLKSRC_MASK |
104 0x0100U;
105#endif /* (DISABLE_WDOG) */
106
107 SystemInitHook();
108}
109
110/* ----------------------------------------------------------------------------
111 -- SystemCoreClockUpdate()
112 ---------------------------------------------------------------------------- */
113
114void SystemCoreClockUpdate (void) {
115 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
116 uint16_t Divider;
117 uint8_t tmpC7 = 0;
118
119 if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
120 /* Output of FLL or PLL is selected */
121 if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
122 /* FLL is selected */
123 if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
124 /* External reference clock is selected */
125 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
126 case 0x00U:
127 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
128 break;
129 case 0x01U:
130 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
131 break;
132 case 0x02U:
133 default:
134 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
135 break;
136 }
137 tmpC7 = MCG->C7;
138 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
139 switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
140 case 0x38U:
141 Divider = 1536U;
142 break;
143 case 0x30U:
144 Divider = 1280U;
145 break;
146 default:
147 Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
148 break;
149 }
150 } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
151 Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
152 }
153 MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
154 } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
155 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
156 } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
157 /* Select correct multiplier to calculate the MCG output clock */
158 switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
159 case 0x00U:
160 MCGOUTClock *= 640U;
161 break;
162 case 0x20U:
163 MCGOUTClock *= 1280U;
164 break;
165 case 0x40U:
166 MCGOUTClock *= 1920U;
167 break;
168 case 0x60U:
169 MCGOUTClock *= 2560U;
170 break;
171 case 0x80U:
172 MCGOUTClock *= 732U;
173 break;
174 case 0xA0U:
175 MCGOUTClock *= 1464U;
176 break;
177 case 0xC0U:
178 MCGOUTClock *= 2197U;
179 break;
180 case 0xE0U:
181 MCGOUTClock *= 2929U;
182 break;
183 default:
184 MCGOUTClock *= 640U;
185 break;
186 }
187 } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
188 /* PLL is selected */
189 Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
190 MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
191 Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
192 MCGOUTClock *= Divider; /* Calculate the MCG output clock */
193 } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
194 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
195 /* Internal reference clock is selected */
196 if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
197 MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
198 } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
199 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
200 MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
201 } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
202 } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
203 /* External reference clock is selected */
204 switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
205 case 0x00U:
206 MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
207 break;
208 case 0x01U:
209 MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
210 break;
211 case 0x02U:
212 default:
213 MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
214 break;
215 }
216 } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
217 /* Reserved value */
218 return;
219 } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
220 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
221}
222
223/* ----------------------------------------------------------------------------
224 -- SystemInitHook()
225 ---------------------------------------------------------------------------- */
226
227__attribute__ ((weak)) void SystemInitHook (void) {
228 /* Void implementation of the weak function. */
229}
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 18:29:39 +0100