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diff --git a/lib/chibios-contrib/ext/mcux-sdk/devices/MKV10Z1287/drivers/fsl_clock.h b/lib/chibios-contrib/ext/mcux-sdk/devices/MKV10Z1287/drivers/fsl_clock.h
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1/*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016 - 2019, NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_CLOCK_H_
10#define _FSL_CLOCK_H_
11
12#include "fsl_common.h"
13
14/*! @addtogroup clock */
15/*! @{ */
16
17/*! @file */
18
19/*******************************************************************************
20 * Configurations
21 ******************************************************************************/
22
23/*! @brief Configures whether to check a parameter in a function.
24 *
25 * Some MCG settings must be changed with conditions, for example:
26 * 1. MCGIRCLK settings, such as the source, divider, and the trim value should not change when
27 * MCGIRCLK is used as a system clock source.
28 * 2. MCG_C7[OSCSEL] should not be changed when the external reference clock is used
29 * as a system clock source. For example, in FBE/BLPE/PBE modes.
30 * 3. The users should only switch between the supported clock modes.
31 *
32 * MCG functions check the parameter and MCG status before setting, if not allowed
33 * to change, the functions return error. The parameter checking increases code size,
34 * if code size is a critical requirement, change #MCG_CONFIG_CHECK_PARAM to 0 to
35 * disable parameter checking.
36 */
37#ifndef MCG_CONFIG_CHECK_PARAM
38#define MCG_CONFIG_CHECK_PARAM 0U
39#endif
40
41/*! @brief Configure whether driver controls clock
42 *
43 * When set to 0, peripheral drivers will enable clock in initialize function
44 * and disable clock in de-initialize function. When set to 1, peripheral
45 * driver will not control the clock, application could control the clock out of
46 * the driver.
47 *
48 * @note All drivers share this feature switcher. If it is set to 1, application
49 * should handle clock enable and disable for all drivers.
50 */
51#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL))
52#define FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL 0
53#endif
54
55/*******************************************************************************
56 * Definitions
57 ******************************************************************************/
58
59/*! @name Driver version */
60/*@{*/
61/*! @brief CLOCK driver version 2.5.1. */
62#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 5, 1))
63/*@}*/
64
65/*! @brief External XTAL0 (OSC0) clock frequency.
66 *
67 * The XTAL0/EXTAL0 (OSC0) clock frequency in Hz. When the clock is set up, use the
68 * function CLOCK_SetXtal0Freq to set the value in the clock driver. For example,
69 * if XTAL0 is 8 MHz:
70 * @code
71 * Set up the OSC0
72 * CLOCK_InitOsc0(...);
73 * Set the XTAL0 value to the clock driver.
74 * CLOCK_SetXtal0Freq(80000000);
75 * @endcode
76 *
77 * This is important for the multicore platforms where only one core needs to set up the
78 * OSC0 using the CLOCK_InitOsc0. All other cores need to call the CLOCK_SetXtal0Freq
79 * to get a valid clock frequency.
80 */
81extern volatile uint32_t g_xtal0Freq;
82
83/*! @brief External XTAL32/EXTAL32/RTC_CLKIN clock frequency.
84 *
85 * The XTAL32/EXTAL32/RTC_CLKIN clock frequency in Hz. When the clock is set up, use the
86 * function CLOCK_SetXtal32Freq to set the value in the clock driver.
87 *
88 * This is important for the multicore platforms where only one core needs to set up
89 * the clock. All other cores need to call the CLOCK_SetXtal32Freq
90 * to get a valid clock frequency.
91 */
92extern volatile uint32_t g_xtal32Freq;
93
94#if (defined(OSC) && !(defined(OSC0)))
95#define OSC0 OSC
96#endif
97
98/* Definition for delay API in clock driver, users can redefine it to the real application. */
99#ifndef SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY
100#define SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY 75000000
101#endif
102/*! @brief Clock ip name array for DMAMUX. */
103#define DMAMUX_CLOCKS \
104 { \
105 kCLOCK_Dmamux0 \
106 }
107
108/*! @brief Clock ip name array for PORT. */
109#define PORT_CLOCKS \
110 { \
111 kCLOCK_PortA, kCLOCK_PortB, kCLOCK_PortC, kCLOCK_PortD, kCLOCK_PortE \
112 }
113
114/*! @brief Clock ip name array for EWM. */
115#define EWM_CLOCKS \
116 { \
117 kCLOCK_Ewm0 \
118 }
119
120/*! @brief Clock ip name array for DSPI. */
121#define DSPI_CLOCKS \
122 { \
123 kCLOCK_Spi0 \
124 }
125
126/*! @brief Clock ip name array for FTM. */
127#define FTM_CLOCKS \
128 { \
129 kCLOCK_Ftm0, kCLOCK_Ftm1, kCLOCK_Ftm2, kCLOCK_Ftm3, kCLOCK_Ftm4, kCLOCK_Ftm5 \
130 }
131
132/*! @brief Clock ip name array for EDMA. */
133#define EDMA_CLOCKS \
134 { \
135 kCLOCK_Dma0 \
136 }
137
138/*! @brief Clock ip name array for FLEXCAN. */
139#define FLEXCAN_CLOCKS \
140 { \
141 kCLOCK_Flexcan0 \
142 }
143
144/*! @brief Clock ip name array for DAC. */
145#define DAC_CLOCKS \
146 { \
147 kCLOCK_Dac0 \
148 }
149
150/*! @brief Clock ip name array for ADC16. */
151#define ADC16_CLOCKS \
152 { \
153 kCLOCK_Adc0, kCLOCK_Adc1 \
154 }
155
156/*! @brief Clock ip name array for UART. */
157#define UART_CLOCKS \
158 { \
159 kCLOCK_Uart0, kCLOCK_Uart1 \
160 }
161
162/*! @brief Clock ip name array for CRC. */
163#define CRC_CLOCKS \
164 { \
165 kCLOCK_Crc0 \
166 }
167
168/*! @brief Clock ip name array for I2C. */
169#define I2C_CLOCKS \
170 { \
171 kCLOCK_I2c0 \
172 }
173
174/*! @brief Clock ip name array for LPTMR. */
175#define LPTMR_CLOCKS \
176 { \
177 kCLOCK_Lptmr0 \
178 }
179
180/*! @brief Clock ip name array for PDB. */
181#define PDB_CLOCKS \
182 { \
183 kCLOCK_Pdb0, kCLOCK_Pdb1 \
184 }
185
186/*! @brief Clock ip name array for CMP. */
187#define CMP_CLOCKS \
188 { \
189 kCLOCK_Cmp0, kCLOCK_Cmp1 \
190 }
191
192/*! @brief Clock ip name array for FTF. */
193#define FTF_CLOCKS \
194 { \
195 kCLOCK_Ftf0 \
196 }
197
198/*!
199 * @brief LPO clock frequency.
200 */
201#define LPO_CLK_FREQ 1000U
202
203/*! @brief Peripherals clock source definition. */
204#define SYS_CLK kCLOCK_CoreSysClk
205#define BUS_CLK kCLOCK_BusClk
206
207#define I2C0_CLK_SRC BUS_CLK
208#define DSPI0_CLK_SRC SYS_CLK
209#define UART0_CLK_SRC SYS_CLK
210#define UART1_CLK_SRC BUS_CLK
211
212/*! @brief Clock name used to get clock frequency. */
213typedef enum _clock_name
214{
215
216 /* ----------------------------- System layer clock -------------------------------*/
217 kCLOCK_CoreSysClk, /*!< Core/system clock */
218 kCLOCK_PlatClk, /*!< Platform clock */
219 kCLOCK_BusClk, /*!< Bus clock */
220 kCLOCK_FlexBusClk, /*!< FlexBus clock */
221 kCLOCK_FlashClk, /*!< Flash clock */
222 kCLOCK_FastPeriphClk, /*!< Fast peripheral clock */
223 kCLOCK_PllFllSelClk, /*!< The clock after SIM[PLLFLLSEL]. */
224
225 /* ---------------------------------- OSC clock -----------------------------------*/
226 kCLOCK_Er32kClk, /*!< External reference 32K clock (ERCLK32K) */
227 kCLOCK_Osc0ErClk, /*!< OSC0 external reference clock (OSC0ERCLK) */
228 kCLOCK_Osc0ErClkUndiv, /*!< OSC0 external reference undivided clock(OSC0ERCLK_UNDIV). */
229
230 /* ----------------------------- MCG and MCG-Lite clock ---------------------------*/
231 kCLOCK_McgFixedFreqClk, /*!< MCG fixed frequency clock (MCGFFCLK) */
232 kCLOCK_McgInternalRefClk, /*!< MCG internal reference clock (MCGIRCLK) */
233 kCLOCK_McgFllClk, /*!< MCGFLLCLK */
234 kCLOCK_McgPll0Clk, /*!< MCGPLL0CLK */
235 kCLOCK_McgPll1Clk, /*!< MCGPLL1CLK */
236 kCLOCK_McgExtPllClk, /*!< EXT_PLLCLK */
237 kCLOCK_McgPeriphClk, /*!< MCG peripheral clock (MCGPCLK) */
238 kCLOCK_McgIrc48MClk, /*!< MCG IRC48M clock */
239
240 /* --------------------------------- Other clock ----------------------------------*/
241 kCLOCK_LpoClk, /*!< LPO clock */
242
243} clock_name_t;
244
245#define CLK_GATE_REG_OFFSET_SHIFT 16U
246#define CLK_GATE_REG_OFFSET_MASK 0xFFFF0000U
247#define CLK_GATE_BIT_SHIFT_SHIFT 0U
248#define CLK_GATE_BIT_SHIFT_MASK 0x0000FFFFU
249
250#define CLK_GATE_DEFINE(reg_offset, bit_shift) \
251 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
252 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
253
254#define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
255#define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
256
257/*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
258typedef enum _clock_ip_name
259{
260 kCLOCK_IpInvalid = 0U,
261 kCLOCK_Ewm0 = CLK_GATE_DEFINE(0x1034U, 1U),
262 kCLOCK_I2c0 = CLK_GATE_DEFINE(0x1034U, 6U),
263 kCLOCK_Uart0 = CLK_GATE_DEFINE(0x1034U, 10U),
264 kCLOCK_Uart1 = CLK_GATE_DEFINE(0x1034U, 11U),
265 kCLOCK_Cmp0 = CLK_GATE_DEFINE(0x1034U, 19U),
266 kCLOCK_Cmp1 = CLK_GATE_DEFINE(0x1034U, 19U),
267
268 kCLOCK_Lptmr0 = CLK_GATE_DEFINE(0x1038U, 0U),
269 kCLOCK_PortA = CLK_GATE_DEFINE(0x1038U, 9U),
270 kCLOCK_PortB = CLK_GATE_DEFINE(0x1038U, 10U),
271 kCLOCK_PortC = CLK_GATE_DEFINE(0x1038U, 11U),
272 kCLOCK_PortD = CLK_GATE_DEFINE(0x1038U, 12U),
273 kCLOCK_PortE = CLK_GATE_DEFINE(0x1038U, 13U),
274
275 kCLOCK_Ftf0 = CLK_GATE_DEFINE(0x103CU, 0U),
276 kCLOCK_Dmamux0 = CLK_GATE_DEFINE(0x103CU, 1U),
277 kCLOCK_Flexcan0 = CLK_GATE_DEFINE(0x103CU, 4U),
278 kCLOCK_Ftm3 = CLK_GATE_DEFINE(0x103CU, 6U),
279 kCLOCK_Ftm4 = CLK_GATE_DEFINE(0x103CU, 7U),
280 kCLOCK_Ftm5 = CLK_GATE_DEFINE(0x103CU, 8U),
281 kCLOCK_Spi0 = CLK_GATE_DEFINE(0x103CU, 12U),
282 kCLOCK_Pdb1 = CLK_GATE_DEFINE(0x103CU, 17U),
283 kCLOCK_Crc0 = CLK_GATE_DEFINE(0x103CU, 18U),
284 kCLOCK_Pdb0 = CLK_GATE_DEFINE(0x103CU, 22U),
285 kCLOCK_Ftm0 = CLK_GATE_DEFINE(0x103CU, 24U),
286 kCLOCK_Ftm1 = CLK_GATE_DEFINE(0x103CU, 25U),
287 kCLOCK_Ftm2 = CLK_GATE_DEFINE(0x103CU, 26U),
288 kCLOCK_Adc0 = CLK_GATE_DEFINE(0x103CU, 27U),
289 kCLOCK_Adc1 = CLK_GATE_DEFINE(0x103CU, 28U),
290 kCLOCK_Dac0 = CLK_GATE_DEFINE(0x103CU, 31U),
291
292 kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 8U),
293
294} clock_ip_name_t;
295
296/*!@brief SIM configuration structure for clock setting. */
297typedef struct _sim_clock_config
298{
299 uint8_t pllFllSel; /*!< PLL/FLL/IRC48M selection. */
300 uint8_t er32kSrc; /*!< ERCLK32K source selection. */
301 uint32_t clkdiv1; /*!< SIM_CLKDIV1. */
302} sim_clock_config_t;
303
304/*! @brief OSC work mode. */
305typedef enum _osc_mode
306{
307 kOSC_ModeExt = 0U, /*!< Use an external clock. */
308#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
309 kOSC_ModeOscLowPower = MCG_C2_EREFS_MASK, /*!< Oscillator low power. */
310#else
311 kOSC_ModeOscLowPower = MCG_C2_EREFS0_MASK, /*!< Oscillator low power. */
312#endif
313 kOSC_ModeOscHighGain = 0U
314#if (defined(MCG_C2_EREFS_MASK) && !(defined(MCG_C2_EREFS0_MASK)))
315 | MCG_C2_EREFS_MASK
316#else
317 | MCG_C2_EREFS0_MASK
318#endif
319#if (defined(MCG_C2_HGO_MASK) && !(defined(MCG_C2_HGO0_MASK)))
320 | MCG_C2_HGO_MASK, /*!< Oscillator high gain. */
321#else
322 | MCG_C2_HGO0_MASK, /*!< Oscillator high gain. */
323#endif
324} osc_mode_t;
325
326/*! @brief Oscillator capacitor load setting.*/
327enum _osc_cap_load
328{
329 kOSC_Cap2P = OSC_CR_SC2P_MASK, /*!< 2 pF capacitor load */
330 kOSC_Cap4P = OSC_CR_SC4P_MASK, /*!< 4 pF capacitor load */
331 kOSC_Cap8P = OSC_CR_SC8P_MASK, /*!< 8 pF capacitor load */
332 kOSC_Cap16P = OSC_CR_SC16P_MASK /*!< 16 pF capacitor load */
333};
334
335/*! @brief OSCERCLK enable mode. */
336enum _oscer_enable_mode
337{
338 kOSC_ErClkEnable = OSC_CR_ERCLKEN_MASK, /*!< Enable. */
339 kOSC_ErClkEnableInStop = OSC_CR_EREFSTEN_MASK /*!< Enable in stop mode. */
340};
341
342/*! @brief OSC configuration for OSCERCLK. */
343typedef struct _oscer_config
344{
345 uint8_t enableMode; /*!< OSCERCLK enable mode. OR'ed value of @ref _oscer_enable_mode. */
346
347} oscer_config_t;
348
349/*!
350 * @brief OSC Initialization Configuration Structure
351 *
352 * Defines the configuration data structure to initialize the OSC.
353 * When porting to a new board, set the following members
354 * according to the board setting:
355 * 1. freq: The external frequency.
356 * 2. workMode: The OSC module mode.
357 */
358typedef struct _osc_config
359{
360 uint32_t freq; /*!< External clock frequency. */
361 uint8_t capLoad; /*!< Capacitor load setting. */
362 osc_mode_t workMode; /*!< OSC work mode setting. */
363 oscer_config_t oscerConfig; /*!< Configuration for OSCERCLK. */
364} osc_config_t;
365
366/*! @brief MCG FLL reference clock source select. */
367typedef enum _mcg_fll_src
368{
369 kMCG_FllSrcExternal, /*!< External reference clock is selected */
370 kMCG_FllSrcInternal /*!< The slow internal reference clock is selected */
371} mcg_fll_src_t;
372
373/*! @brief MCG internal reference clock select */
374typedef enum _mcg_irc_mode
375{
376 kMCG_IrcSlow, /*!< Slow internal reference clock selected */
377 kMCG_IrcFast /*!< Fast internal reference clock selected */
378} mcg_irc_mode_t;
379
380/*! @brief MCG DCO Maximum Frequency with 32.768 kHz Reference */
381typedef enum _mcg_dmx32
382{
383 kMCG_Dmx32Default, /*!< DCO has a default range of 25% */
384 kMCG_Dmx32Fine /*!< DCO is fine-tuned for maximum frequency with 32.768 kHz reference */
385} mcg_dmx32_t;
386
387/*! @brief MCG DCO range select */
388typedef enum _mcg_drs
389{
390 kMCG_DrsLow, /*!< Low frequency range */
391 kMCG_DrsMid, /*!< Mid frequency range */
392 kMCG_DrsMidHigh, /*!< Mid-High frequency range */
393 kMCG_DrsHigh /*!< High frequency range */
394} mcg_drs_t;
395
396/*! @brief MCG PLL reference clock select */
397typedef enum _mcg_pll_ref_src
398{
399 kMCG_PllRefOsc0, /*!< Selects OSC0 as PLL reference clock */
400 kMCG_PllRefOsc1 /*!< Selects OSC1 as PLL reference clock */
401} mcg_pll_ref_src_t;
402
403/*! @brief MCGOUT clock source. */
404typedef enum _mcg_clkout_src
405{
406 kMCG_ClkOutSrcOut, /*!< Output of the FLL is selected (reset default) */
407 kMCG_ClkOutSrcInternal, /*!< Internal reference clock is selected */
408 kMCG_ClkOutSrcExternal, /*!< External reference clock is selected */
409} mcg_clkout_src_t;
410
411/*! @brief MCG Automatic Trim Machine Select */
412typedef enum _mcg_atm_select
413{
414 kMCG_AtmSel32k, /*!< 32 kHz Internal Reference Clock selected */
415 kMCG_AtmSel4m /*!< 4 MHz Internal Reference Clock selected */
416} mcg_atm_select_t;
417
418/*! @brief MCG OSC Clock Select */
419typedef enum _mcg_oscsel
420{
421 kMCG_OscselOsc, /*!< Selects System Oscillator (OSCCLK) */
422 kMCG_OscselRtc, /*!< Selects 32 kHz RTC Oscillator */
423} mcg_oscsel_t;
424
425/*! @brief MCG PLLCS select */
426typedef enum _mcg_pll_clk_select
427{
428 kMCG_PllClkSelPll0, /*!< PLL0 output clock is selected */
429 kMCG_PllClkSelPll1 /* PLL1 output clock is selected */
430} mcg_pll_clk_select_t;
431
432/*! @brief MCG clock monitor mode. */
433typedef enum _mcg_monitor_mode
434{
435 kMCG_MonitorNone, /*!< Clock monitor is disabled. */
436 kMCG_MonitorInt, /*!< Trigger interrupt when clock lost. */
437 kMCG_MonitorReset /*!< System reset when clock lost. */
438} mcg_monitor_mode_t;
439
440/*! @brief MCG status. */
441enum
442{
443 kStatus_MCG_ModeUnreachable = MAKE_STATUS(kStatusGroup_MCG, 0U), /*!< Can't switch to target mode. */
444 kStatus_MCG_ModeInvalid = MAKE_STATUS(kStatusGroup_MCG, 1U), /*!< Current mode invalid for the specific
445 function. */
446 kStatus_MCG_AtmBusClockInvalid = MAKE_STATUS(kStatusGroup_MCG, 2U), /*!< Invalid bus clock for ATM. */
447 kStatus_MCG_AtmDesiredFreqInvalid = MAKE_STATUS(kStatusGroup_MCG, 3U), /*!< Invalid desired frequency for ATM. */
448 kStatus_MCG_AtmIrcUsed = MAKE_STATUS(kStatusGroup_MCG, 4U), /*!< IRC is used when using ATM. */
449 kStatus_MCG_AtmHardwareFail = MAKE_STATUS(kStatusGroup_MCG, 5U), /*!< Hardware fail occurs during ATM. */
450 kStatus_MCG_SourceUsed = MAKE_STATUS(kStatusGroup_MCG, 6U) /*!< Can't change the clock source because
451 it is in use. */
452};
453
454/*! @brief MCG status flags. */
455enum
456{
457 kMCG_Osc0LostFlag = (1U << 0U), /*!< OSC0 lost. */
458 kMCG_Osc0InitFlag = (1U << 1U), /*!< OSC0 crystal initialized. */
459};
460
461/*! @brief MCG internal reference clock (MCGIRCLK) enable mode definition. */
462enum
463{
464 kMCG_IrclkEnable = MCG_C1_IRCLKEN_MASK, /*!< MCGIRCLK enable. */
465 kMCG_IrclkEnableInStop = MCG_C1_IREFSTEN_MASK /*!< MCGIRCLK enable in stop mode. */
466};
467
468/*! @brief MCG mode definitions */
469typedef enum _mcg_mode
470{
471 kMCG_ModeFEI = 0U, /*!< FEI - FLL Engaged Internal */
472 kMCG_ModeFBI, /*!< FBI - FLL Bypassed Internal */
473 kMCG_ModeBLPI, /*!< BLPI - Bypassed Low Power Internal */
474 kMCG_ModeFEE, /*!< FEE - FLL Engaged External */
475 kMCG_ModeFBE, /*!< FBE - FLL Bypassed External */
476 kMCG_ModeBLPE, /*!< BLPE - Bypassed Low Power External */
477 kMCG_ModeError /*!< Unknown mode */
478} mcg_mode_t;
479
480/*! @brief MCG mode change configuration structure
481 *
482 * When porting to a new board, set the following members
483 * according to the board setting:
484 * 1. frdiv: If the FLL uses the external reference clock, set this
485 * value to ensure that the external reference clock divided by frdiv is
486 * in the 31.25 kHz to 39.0625 kHz range.
487 * 2. The PLL reference clock divider PRDIV: PLL reference clock frequency after
488 * PRDIV should be in the FSL_FEATURE_MCG_PLL_REF_MIN to
489 * FSL_FEATURE_MCG_PLL_REF_MAX range.
490 */
491typedef struct _mcg_config
492{
493 mcg_mode_t mcgMode; /*!< MCG mode. */
494
495 /* ----------------------- MCGIRCCLK settings ------------------------ */
496 uint8_t irclkEnableMode; /*!< MCGIRCLK enable mode. */
497 mcg_irc_mode_t ircs; /*!< Source, MCG_C2[IRCS]. */
498 uint8_t fcrdiv; /*!< Divider, MCG_SC[FCRDIV]. */
499
500 /* ------------------------ MCG FLL settings ------------------------- */
501 uint8_t frdiv; /*!< Divider MCG_C1[FRDIV]. */
502 mcg_drs_t drs; /*!< DCO range MCG_C4[DRST_DRS]. */
503 mcg_dmx32_t dmx32; /*!< MCG_C4[DMX32]. */
504
505 /* ------------------------ MCG PLL settings ------------------------- */
506} mcg_config_t;
507
508/*******************************************************************************
509 * API
510 ******************************************************************************/
511
512#if defined(__cplusplus)
513extern "C" {
514#endif /* __cplusplus */
515
516/*!
517 * @brief Enable the clock for specific IP.
518 *
519 * @param name Which clock to enable, see \ref clock_ip_name_t.
520 */
521static inline void CLOCK_EnableClock(clock_ip_name_t name)
522{
523 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
524 (*(volatile uint32_t *)regAddr) |= (1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
525}
526
527/*!
528 * @brief Disable the clock for specific IP.
529 *
530 * @param name Which clock to disable, see \ref clock_ip_name_t.
531 */
532static inline void CLOCK_DisableClock(clock_ip_name_t name)
533{
534 uint32_t regAddr = SIM_BASE + CLK_GATE_ABSTRACT_REG_OFFSET((uint32_t)name);
535 (*(volatile uint32_t *)regAddr) &= ~(1UL << CLK_GATE_ABSTRACT_BITS_SHIFT((uint32_t)name));
536}
537
538/*!
539 * @brief Set ERCLK32K source.
540 *
541 * @param src The value to set ERCLK32K clock source.
542 */
543static inline void CLOCK_SetEr32kClock(uint32_t src)
544{
545 SIM->SOPT1 = ((SIM->SOPT1 & ~SIM_SOPT1_OSC32KSEL_MASK) | SIM_SOPT1_OSC32KSEL(src));
546}
547
548/*!
549 * @brief Set CLKOUT source.
550 *
551 * @param src The value to set CLKOUT source.
552 */
553static inline void CLOCK_SetClkOutClock(uint32_t src)
554{
555 SIM->SOPT2 = ((SIM->SOPT2 & ~SIM_SOPT2_CLKOUTSEL_MASK) | SIM_SOPT2_CLKOUTSEL(src));
556}
557
558/*!
559 * @brief System clock divider
560 *
561 * Set the SIM_CLKDIV1[OUTDIV1], SIM_CLKDIV1[OUTDIV4], SIM_CLKDIV1[OUTDIV5].
562 *
563 * @param outdiv1 Clock 1 output divider value.
564 *
565 * @param outdiv4 Clock 4 output divider value.
566 *
567 * @param outdiv1 Clock 5 output divider value.
568 */
569static inline void CLOCK_SetOutDiv(uint32_t outdiv1, uint32_t outdiv4, uint32_t outdiv5)
570{
571 SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(outdiv1) | SIM_CLKDIV1_OUTDIV4(outdiv4) | SIM_CLKDIV1_OUTDIV5(outdiv5);
572}
573
574/*!
575 * @brief Gets the clock frequency for a specific clock name.
576 *
577 * This function checks the current clock configurations and then calculates
578 * the clock frequency for a specific clock name defined in clock_name_t.
579 * The MCG must be properly configured before using this function.
580 *
581 * @param clockName Clock names defined in clock_name_t
582 * @return Clock frequency value in Hertz
583 */
584uint32_t CLOCK_GetFreq(clock_name_t clockName);
585
586/*!
587 * @brief Get the core clock or system clock frequency.
588 *
589 * @return Clock frequency in Hz.
590 */
591uint32_t CLOCK_GetCoreSysClkFreq(void);
592
593/*!
594 * @brief Get the platform clock frequency.
595 *
596 * @return Clock frequency in Hz.
597 */
598uint32_t CLOCK_GetPlatClkFreq(void);
599
600/*!
601 * @brief Get the bus clock frequency.
602 *
603 * @return Clock frequency in Hz.
604 */
605uint32_t CLOCK_GetBusClkFreq(void);
606
607/*!
608 * @brief Get the flash clock frequency.
609 *
610 * @return Clock frequency in Hz.
611 */
612uint32_t CLOCK_GetFlashClkFreq(void);
613
614/*!
615 * @brief Get the external reference 32K clock frequency (ERCLK32K).
616 *
617 * @return Clock frequency in Hz.
618 */
619uint32_t CLOCK_GetEr32kClkFreq(void);
620
621/*!
622 * @brief Get the OSC0 external reference clock frequency (OSC0ERCLK).
623 *
624 * @return Clock frequency in Hz.
625 */
626uint32_t CLOCK_GetOsc0ErClkFreq(void);
627
628/*!
629 * @brief Set the clock configure in SIM module.
630 *
631 * This function sets system layer clock settings in SIM module.
632 *
633 * @param config Pointer to the configure structure.
634 */
635void CLOCK_SetSimConfig(sim_clock_config_t const *config);
636
637/*!
638 * @brief Set the system clock dividers in SIM to safe value.
639 *
640 * The system level clocks (core clock, bus clock, flexbus clock and flash clock)
641 * must be in allowed ranges. During MCG clock mode switch, the MCG output clock
642 * changes then the system level clocks may be out of range. This function could
643 * be used before MCG mode change, to make sure system level clocks are in allowed
644 * range.
645 *
646 * @param config Pointer to the configure structure.
647 */
648static inline void CLOCK_SetSimSafeDivs(void)
649{
650 /* Sys_clock 4MHZ, Bus_clock 1MHZ */
651 SIM->CLKDIV1 = 0x00030000U;
652}
653
654/*! @name MCG frequency functions. */
655/*@{*/
656
657/*!
658 * @brief Gets the MCG output clock (MCGOUTCLK) frequency.
659 *
660 * This function gets the MCG output clock frequency in Hz based on the current MCG
661 * register value.
662 *
663 * @return The frequency of MCGOUTCLK.
664 */
665uint32_t CLOCK_GetOutClkFreq(void);
666
667/*!
668 * @brief Gets the MCG FLL clock (MCGFLLCLK) frequency.
669 *
670 * This function gets the MCG FLL clock frequency in Hz based on the current MCG
671 * register value. The FLL is enabled in FEI/FBI/FEE/FBE mode and
672 * disabled in low power state in other modes.
673 *
674 * @return The frequency of MCGFLLCLK.
675 */
676uint32_t CLOCK_GetFllFreq(void);
677
678/*!
679 * @brief Gets the MCG internal reference clock (MCGIRCLK) frequency.
680 *
681 * This function gets the MCG internal reference clock frequency in Hz based
682 * on the current MCG register value.
683 *
684 * @return The frequency of MCGIRCLK.
685 */
686uint32_t CLOCK_GetInternalRefClkFreq(void);
687
688/*!
689 * @brief Gets the MCG fixed frequency clock (MCGFFCLK) frequency.
690 *
691 * This function gets the MCG fixed frequency clock frequency in Hz based
692 * on the current MCG register value.
693 *
694 * @return The frequency of MCGFFCLK.
695 */
696uint32_t CLOCK_GetFixedFreqClkFreq(void);
697
698/*@}*/
699
700/*! @name MCG clock configuration. */
701/*@{*/
702
703/*!
704 * @brief Enables or disables the MCG low power.
705 *
706 * Enabling the MCG low power disables the PLL and FLL in bypass modes. In other words,
707 * in FBE and PBE modes, enabling low power sets the MCG to BLPE mode. In FBI and
708 * PBI modes, enabling low power sets the MCG to BLPI mode.
709 * When disabling the MCG low power, the PLL or FLL are enabled based on MCG settings.
710 *
711 * @param enable True to enable MCG low power, false to disable MCG low power.
712 */
713static inline void CLOCK_SetLowPowerEnable(bool enable)
714{
715 if (enable)
716 {
717 MCG->C2 |= MCG_C2_LP_MASK;
718 }
719 else
720 {
721 MCG->C2 &= ~(uint8_t)MCG_C2_LP_MASK;
722 }
723}
724
725/*!
726 * @brief Configures the Internal Reference clock (MCGIRCLK).
727 *
728 * This function sets the \c MCGIRCLK base on parameters. It also selects the IRC
729 * source. If the fast IRC is used, this function sets the fast IRC divider.
730 * This function also sets whether the \c MCGIRCLK is enabled in stop mode.
731 * Calling this function in FBI/PBI/BLPI modes may change the system clock. As a result,
732 * using the function in these modes it is not allowed.
733 *
734 * @param enableMode MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
735 * @param ircs MCGIRCLK clock source, choose fast or slow.
736 * @param fcrdiv Fast IRC divider setting (\c FCRDIV).
737 * @retval kStatus_MCG_SourceUsed Because the internal reference clock is used as a clock source,
738 * the configuration should not be changed. Otherwise, a glitch occurs.
739 * @retval kStatus_Success MCGIRCLK configuration finished successfully.
740 */
741status_t CLOCK_SetInternalRefClkConfig(uint8_t enableMode, mcg_irc_mode_t ircs, uint8_t fcrdiv);
742
743/*!
744 * @brief Selects the MCG external reference clock.
745 *
746 * Selects the MCG external reference clock source, changes the MCG_C7[OSCSEL],
747 * and waits for the clock source to be stable. Because the external reference
748 * clock should not be changed in FEE/FBE/BLPE/PBE/PEE modes, do not call this function in these modes.
749 *
750 * @param oscsel MCG external reference clock source, MCG_C7[OSCSEL].
751 * @retval kStatus_MCG_SourceUsed Because the external reference clock is used as a clock source,
752 * the configuration should not be changed. Otherwise, a glitch occurs.
753 * @retval kStatus_Success External reference clock set successfully.
754 */
755status_t CLOCK_SetExternalRefClkConfig(mcg_oscsel_t oscsel);
756
757/*!
758 * @brief Set the FLL external reference clock divider value.
759 *
760 * Sets the FLL external reference clock divider value, the register MCG_C1[FRDIV].
761 *
762 * @param frdiv The FLL external reference clock divider value, MCG_C1[FRDIV].
763 */
764static inline void CLOCK_SetFllExtRefDiv(uint8_t frdiv)
765{
766 MCG->C1 = (uint8_t)((MCG->C1 & ~MCG_C1_FRDIV_MASK) | MCG_C1_FRDIV(frdiv));
767}
768
769/*@}*/
770
771/*! @name MCG clock lock monitor functions. */
772/*@{*/
773
774/*!
775 * @brief Sets the OSC0 clock monitor mode.
776 *
777 * This function sets the OSC0 clock monitor mode. See @ref mcg_monitor_mode_t for details.
778 *
779 * @param mode Monitor mode to set.
780 */
781void CLOCK_SetOsc0MonitorMode(mcg_monitor_mode_t mode);
782
783/*!
784 * @brief Gets the MCG status flags.
785 *
786 * This function gets the MCG clock status flags. All status flags are
787 * returned as a logical OR of the enumeration @ref _mcg_status_flags_t. To
788 * check a specific flag, compare the return value with the flag.
789 *
790 * Example:
791 * @code
792 * To check the clock lost lock status of OSC0 and PLL0.
793 * uint32_t mcgFlags;
794 *
795 * mcgFlags = CLOCK_GetStatusFlags();
796 *
797 * if (mcgFlags & kMCG_Osc0LostFlag)
798 * {
799 * OSC0 clock lock lost. Do something.
800 * }
801 * if (mcgFlags & kMCG_Pll0LostFlag)
802 * {
803 * PLL0 clock lock lost. Do something.
804 * }
805 * @endcode
806 *
807 * @return Logical OR value of the @ref _mcg_status_flags_t.
808 */
809uint32_t CLOCK_GetStatusFlags(void);
810
811/*!
812 * @brief Clears the MCG status flags.
813 *
814 * This function clears the MCG clock lock lost status. The parameter is a logical
815 * OR value of the flags to clear. See @ref _mcg_status_flags_t.
816 *
817 * Example:
818 * @code
819 * To clear the clock lost lock status flags of OSC0 and PLL0.
820 *
821 * CLOCK_ClearStatusFlags(kMCG_Osc0LostFlag | kMCG_Pll0LostFlag);
822 * @endcode
823 *
824 * @param mask The status flags to clear. This is a logical OR of members of the
825 * enumeration @ref _mcg_status_flags_t.
826 */
827void CLOCK_ClearStatusFlags(uint32_t mask);
828
829/*@}*/
830
831/*!
832 * @name OSC configuration
833 * @{
834 */
835
836/*!
837 * @brief Configures the OSC external reference clock (OSCERCLK).
838 *
839 * This function configures the OSC external reference clock (OSCERCLK).
840 * This is an example to enable the OSCERCLK in normal and stop modes and also set
841 * the output divider to 1:
842 *
843 @code
844 oscer_config_t config =
845 {
846 .enableMode = kOSC_ErClkEnable | kOSC_ErClkEnableInStop,
847 .erclkDiv = 1U,
848 };
849
850 OSC_SetExtRefClkConfig(OSC, &config);
851 @endcode
852 *
853 * @param base OSC peripheral address.
854 * @param config Pointer to the configuration structure.
855 */
856static inline void OSC_SetExtRefClkConfig(OSC_Type *base, oscer_config_t const *config)
857{
858 uint8_t reg = base->CR;
859
860 reg &= (uint8_t)(~(OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK));
861 reg |= config->enableMode;
862
863 base->CR = reg;
864}
865
866/*!
867 * @brief Sets the capacitor load configuration for the oscillator.
868 *
869 * This function sets the specified capacitors configuration for the oscillator.
870 * This should be done in the early system level initialization function call
871 * based on the system configuration.
872 *
873 * @param base OSC peripheral address.
874 * @param capLoad OR'ed value for the capacitor load option, see \ref _osc_cap_load.
875 *
876 * Example:
877 @code
878 To enable only 2 pF and 8 pF capacitor load, please use like this.
879 OSC_SetCapLoad(OSC, kOSC_Cap2P | kOSC_Cap8P);
880 @endcode
881 */
882static inline void OSC_SetCapLoad(OSC_Type *base, uint8_t capLoad)
883{
884 uint8_t reg = base->CR;
885
886 reg &= (uint8_t)(~(OSC_CR_SC2P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC8P_MASK | OSC_CR_SC16P_MASK));
887 reg |= capLoad;
888
889 base->CR = reg;
890}
891
892/*!
893 * @brief Initializes the OSC0.
894 *
895 * This function initializes the OSC0 according to the board configuration.
896 *
897 * @param config Pointer to the OSC0 configuration structure.
898 */
899void CLOCK_InitOsc0(osc_config_t const *config);
900
901/*!
902 * @brief Deinitializes the OSC0.
903 *
904 * This function deinitializes the OSC0.
905 */
906void CLOCK_DeinitOsc0(void);
907
908/* @} */
909
910/*!
911 * @name External clock frequency
912 * @{
913 */
914
915/*!
916 * @brief Sets the XTAL0 frequency based on board settings.
917 *
918 * @param freq The XTAL0/EXTAL0 input clock frequency in Hz.
919 */
920static inline void CLOCK_SetXtal0Freq(uint32_t freq)
921{
922 g_xtal0Freq = freq;
923}
924
925/*!
926 * @brief Sets the XTAL32/RTC_CLKIN frequency based on board settings.
927 *
928 * @param freq The XTAL32/EXTAL32/RTC_CLKIN input clock frequency in Hz.
929 */
930static inline void CLOCK_SetXtal32Freq(uint32_t freq)
931{
932 g_xtal32Freq = freq;
933}
934/* @} */
935
936/*!
937 * @name IRCs frequency
938 * @{
939 */
940
941/*!
942 * @brief Set the Slow IRC frequency based on the trimmed value
943 *
944 * @param freq The Slow IRC frequency input clock frequency in Hz.
945 */
946void CLOCK_SetSlowIrcFreq(uint32_t freq);
947
948/*!
949 * @brief Set the Fast IRC frequency based on the trimmed value
950 *
951 * @param freq The Fast IRC frequency input clock frequency in Hz.
952 */
953void CLOCK_SetFastIrcFreq(uint32_t freq);
954/* @} */
955
956/*!
957 * @name MCG auto-trim machine.
958 * @{
959 */
960
961/*!
962 * @brief Auto trims the internal reference clock.
963 *
964 * This function trims the internal reference clock by using the external clock. If
965 * successful, it returns the kStatus_Success and the frequency after
966 * trimming is received in the parameter @p actualFreq. If an error occurs,
967 * the error code is returned.
968 *
969 * @param extFreq External clock frequency, which should be a bus clock.
970 * @param desireFreq Frequency to trim to.
971 * @param actualFreq Actual frequency after trimming.
972 * @param atms Trim fast or slow internal reference clock.
973 * @retval kStatus_Success ATM success.
974 * @retval kStatus_MCG_AtmBusClockInvalid The bus clock is not in allowed range for the ATM.
975 * @retval kStatus_MCG_AtmDesiredFreqInvalid MCGIRCLK could not be trimmed to the desired frequency.
976 * @retval kStatus_MCG_AtmIrcUsed Could not trim because MCGIRCLK is used as a bus clock source.
977 * @retval kStatus_MCG_AtmHardwareFail Hardware fails while trimming.
978 */
979status_t CLOCK_TrimInternalRefClk(uint32_t extFreq, uint32_t desireFreq, uint32_t *actualFreq, mcg_atm_select_t atms);
980/* @} */
981
982/*! @name MCG mode functions. */
983/*@{*/
984
985/*!
986 * @brief Gets the current MCG mode.
987 *
988 * This function checks the MCG registers and determines the current MCG mode.
989 *
990 * @return Current MCG mode or error code; See @ref mcg_mode_t.
991 */
992mcg_mode_t CLOCK_GetMode(void);
993
994/*!
995 * @brief Sets the MCG to FEI mode.
996 *
997 * This function sets the MCG to FEI mode. If setting to FEI mode fails
998 * from the current mode, this function returns an error.
999 *
1000 * @param dmx32 DMX32 in FEI mode.
1001 * @param drs The DCO range selection.
1002 * @param fllStableDelay Delay function to ensure that the FLL is stable. Passing
1003 * NULL does not cause a delay.
1004 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1005 * @retval kStatus_Success Switched to the target mode successfully.
1006 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1007 * to a frequency above 32768 Hz.
1008 */
1009status_t CLOCK_SetFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1010
1011/*!
1012 * @brief Sets the MCG to FEE mode.
1013 *
1014 * This function sets the MCG to FEE mode. If setting to FEE mode fails
1015 * from the current mode, this function returns an error.
1016 *
1017 * @param frdiv FLL reference clock divider setting, FRDIV.
1018 * @param dmx32 DMX32 in FEE mode.
1019 * @param drs The DCO range selection.
1020 * @param fllStableDelay Delay function to make sure FLL is stable. Passing
1021 * NULL does not cause a delay.
1022 *
1023 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1024 * @retval kStatus_Success Switched to the target mode successfully.
1025 */
1026status_t CLOCK_SetFeeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1027
1028/*!
1029 * @brief Sets the MCG to FBI mode.
1030 *
1031 * This function sets the MCG to FBI mode. If setting to FBI mode fails
1032 * from the current mode, this function returns an error.
1033 *
1034 * @param dmx32 DMX32 in FBI mode.
1035 * @param drs The DCO range selection.
1036 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1037 * is not used in FBI mode, this parameter can be NULL. Passing
1038 * NULL does not cause a delay.
1039 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1040 * @retval kStatus_Success Switched to the target mode successfully.
1041 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1042 * to frequency above 32768 Hz.
1043 */
1044status_t CLOCK_SetFbiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1045
1046/*!
1047 * @brief Sets the MCG to FBE mode.
1048 *
1049 * This function sets the MCG to FBE mode. If setting to FBE mode fails
1050 * from the current mode, this function returns an error.
1051 *
1052 * @param frdiv FLL reference clock divider setting, FRDIV.
1053 * @param dmx32 DMX32 in FBE mode.
1054 * @param drs The DCO range selection.
1055 * @param fllStableDelay Delay function to make sure FLL is stable. If the FLL
1056 * is not used in FBE mode, this parameter can be NULL. Passing NULL
1057 * does not cause a delay.
1058 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1059 * @retval kStatus_Success Switched to the target mode successfully.
1060 */
1061status_t CLOCK_SetFbeMode(uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1062
1063/*!
1064 * @brief Sets the MCG to BLPI mode.
1065 *
1066 * This function sets the MCG to BLPI mode. If setting to BLPI mode fails
1067 * from the current mode, this function returns an error.
1068 *
1069 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1070 * @retval kStatus_Success Switched to the target mode successfully.
1071 */
1072status_t CLOCK_SetBlpiMode(void);
1073
1074/*!
1075 * @brief Sets the MCG to BLPE mode.
1076 *
1077 * This function sets the MCG to BLPE mode. If setting to BLPE mode fails
1078 * from the current mode, this function returns an error.
1079 *
1080 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1081 * @retval kStatus_Success Switched to the target mode successfully.
1082 */
1083status_t CLOCK_SetBlpeMode(void);
1084
1085/*!
1086 * @brief Switches the MCG to FBE mode from the external mode.
1087 *
1088 * This function switches the MCG from external modes (PEE/PBE/BLPE/FEE) to the FBE mode quickly.
1089 * The external clock is used as the system clock source and PLL is disabled. However,
1090 * the FLL settings are not configured. This is a lite function with a small code size, which is useful
1091 * during the mode switch. For example, to switch from PEE mode to FEI mode:
1092 *
1093 * @code
1094 * CLOCK_ExternalModeToFbeModeQuick();
1095 * CLOCK_SetFeiMode(...);
1096 * @endcode
1097 *
1098 * @retval kStatus_Success Switched successfully.
1099 * @retval kStatus_MCG_ModeInvalid If the current mode is not an external mode, do not call this function.
1100 */
1101status_t CLOCK_ExternalModeToFbeModeQuick(void);
1102
1103/*!
1104 * @brief Switches the MCG to FBI mode from internal modes.
1105 *
1106 * This function switches the MCG from internal modes (PEI/PBI/BLPI/FEI) to the FBI mode quickly.
1107 * The MCGIRCLK is used as the system clock source and PLL is disabled. However,
1108 * FLL settings are not configured. This is a lite function with a small code size, which is useful
1109 * during the mode switch. For example, to switch from PEI mode to FEE mode:
1110 *
1111 * @code
1112 * CLOCK_InternalModeToFbiModeQuick();
1113 * CLOCK_SetFeeMode(...);
1114 * @endcode
1115 *
1116 * @retval kStatus_Success Switched successfully.
1117 * @retval kStatus_MCG_ModeInvalid If the current mode is not an internal mode, do not call this function.
1118 */
1119status_t CLOCK_InternalModeToFbiModeQuick(void);
1120
1121/*!
1122 * @brief Sets the MCG to FEI mode during system boot up.
1123 *
1124 * This function sets the MCG to FEI mode from the reset mode. It can also be used to
1125 * set up MCG during system boot up.
1126 *
1127 * @param dmx32 DMX32 in FEI mode.
1128 * @param drs The DCO range selection.
1129 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1130 *
1131 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1132 * @retval kStatus_Success Switched to the target mode successfully.
1133 * @note If @p dmx32 is set to kMCG_Dmx32Fine, the slow IRC must not be trimmed
1134 * to frequency above 32768 Hz.
1135 */
1136status_t CLOCK_BootToFeiMode(mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1137
1138/*!
1139 * @brief Sets the MCG to FEE mode during system bootup.
1140 *
1141 * This function sets MCG to FEE mode from the reset mode. It can also be used to
1142 * set up the MCG during system boot up.
1143 *
1144 * @param oscsel OSC clock select, OSCSEL.
1145 * @param frdiv FLL reference clock divider setting, FRDIV.
1146 * @param dmx32 DMX32 in FEE mode.
1147 * @param drs The DCO range selection.
1148 * @param fllStableDelay Delay function to ensure that the FLL is stable.
1149 *
1150 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1151 * @retval kStatus_Success Switched to the target mode successfully.
1152 */
1153status_t CLOCK_BootToFeeMode(
1154 mcg_oscsel_t oscsel, uint8_t frdiv, mcg_dmx32_t dmx32, mcg_drs_t drs, void (*fllStableDelay)(void));
1155
1156/*!
1157 * @brief Sets the MCG to BLPI mode during system boot up.
1158 *
1159 * This function sets the MCG to BLPI mode from the reset mode. It can also be used to
1160 * set up the MCG during system boot up.
1161 *
1162 * @param fcrdiv Fast IRC divider, FCRDIV.
1163 * @param ircs The internal reference clock to select, IRCS.
1164 * @param ircEnableMode The MCGIRCLK enable mode, OR'ed value of @ref _mcg_irclk_enable_mode.
1165 *
1166 * @retval kStatus_MCG_SourceUsed Could not change MCGIRCLK setting.
1167 * @retval kStatus_Success Switched to the target mode successfully.
1168 */
1169status_t CLOCK_BootToBlpiMode(uint8_t fcrdiv, mcg_irc_mode_t ircs, uint8_t ircEnableMode);
1170
1171/*!
1172 * @brief Sets the MCG to BLPE mode during system boot up.
1173 *
1174 * This function sets the MCG to BLPE mode from the reset mode. It can also be used to
1175 * set up the MCG during system boot up.
1176 *
1177 * @param oscsel OSC clock select, MCG_C7[OSCSEL].
1178 *
1179 * @retval kStatus_MCG_ModeUnreachable Could not switch to the target mode.
1180 * @retval kStatus_Success Switched to the target mode successfully.
1181 */
1182status_t CLOCK_BootToBlpeMode(mcg_oscsel_t oscsel);
1183
1184/*!
1185 * @brief Sets the MCG to a target mode.
1186 *
1187 * This function sets MCG to a target mode defined by the configuration
1188 * structure. If switching to the target mode fails, this function
1189 * chooses the correct path.
1190 *
1191 * @param config Pointer to the target MCG mode configuration structure.
1192 * @return Return kStatus_Success if switched successfully; Otherwise, it returns an error code #_mcg_status.
1193 *
1194 * @note If the external clock is used in the target mode, ensure that it is
1195 * enabled. For example, if the OSC0 is used, set up OSC0 correctly before calling this
1196 * function.
1197 */
1198status_t CLOCK_SetMcgConfig(mcg_config_t const *config);
1199
1200/*@}*/
1201
1202#if defined(__cplusplus)
1203}
1204#endif /* __cplusplus */
1205
1206/*! @} */
1207
1208#endif /* _FSL_CLOCK_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 20:49:20 +0100