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1/*
2** ###################################################################
3** Processors: MKV31F256VLH12
4** MKV31F256VLL12
5**
6** Compilers: Keil ARM C/C++ Compiler
7** Freescale C/C++ for Embedded ARM
8** GNU C Compiler
9** IAR ANSI C/C++ Compiler for ARM
10** MCUXpresso Compiler
11**
12** Reference manual: KV31P100M120SF8RM, Rev. 1, March 24, 2014
13** Version: rev. 1.7, 2015-02-19
14** Build: b180801
15**
16** Abstract:
17** CMSIS Peripheral Access Layer for MKV31F25612
18**
19** Copyright 1997-2016 Freescale Semiconductor, Inc.
20** Copyright 2016-2018 NXP
21**
22** SPDX-License-Identifier: BSD-3-Clause
23**
24** http: www.nxp.com
25** mail: [email protected]
26**
27** Revisions:
28** - rev. 1.0 (2013-11-01)
29** Initial version.
30** - rev. 1.1 (2013-12-20)
31** Update according to reference manual rev. 0.6,
32** - rev. 1.2 (2014-02-06)
33** Update according to reference manual rev. 0.61,
34** - rev. 1.3 (2014-02-10)
35** The declaration of clock configurations has been moved to separate header file system_MKV31F25612.h
36** - rev. 1.4 (2014-04-30)
37** Update of MCM module according to the RM rev. 1.
38** Update of system and startup files.
39** Module access macro module_BASES replaced by module_BASE_PTRS.
40** - rev. 1.5 (2014-08-28)
41** Update of system files - default clock configuration changed.
42** Update of startup files - possibility to override DefaultISR added.
43** - rev. 1.6 (2014-10-14)
44** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
45** - rev. 1.7 (2015-02-19)
46** Renamed interrupt vector LLW to LLWU.
47**
48** ###################################################################
49*/
50
51/*!
52 * @file MKV31F25612.h
53 * @version 1.7
54 * @date 2015-02-19
55 * @brief CMSIS Peripheral Access Layer for MKV31F25612
56 *
57 * CMSIS Peripheral Access Layer for MKV31F25612
58 */
59
60#ifndef _MKV31F25612_H_
61#define _MKV31F25612_H_ /**< Symbol preventing repeated inclusion */
62
63/** Memory map major version (memory maps with equal major version number are
64 * compatible) */
65#define MCU_MEM_MAP_VERSION 0x0100U
66/** Memory map minor version */
67#define MCU_MEM_MAP_VERSION_MINOR 0x0007U
68
69/**
70 * @brief Macro to calculate address of an aliased word in the peripheral
71 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
72 * 0x400FFFFF).
73 * @param Reg Register to access.
74 * @param Bit Bit number to access.
75 * @return Address of the aliased word in the peripheral bitband area.
76 */
77#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
78/**
79 * @brief Macro to access a single bit of a peripheral register (bit band region
80 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
81 * be used for peripherals with 32bit access allowed.
82 * @param Reg Register to access.
83 * @param Bit Bit number to access.
84 * @return Value of the targeted bit in the bit band region.
85 */
86#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
87#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
88/**
89 * @brief Macro to access a single bit of a peripheral register (bit band region
90 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
91 * be used for peripherals with 16bit access allowed.
92 * @param Reg Register to access.
93 * @param Bit Bit number to access.
94 * @return Value of the targeted bit in the bit band region.
95 */
96#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
97/**
98 * @brief Macro to access a single bit of a peripheral register (bit band region
99 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
100 * be used for peripherals with 8bit access allowed.
101 * @param Reg Register to access.
102 * @param Bit Bit number to access.
103 * @return Value of the targeted bit in the bit band region.
104 */
105#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
106
107/* ----------------------------------------------------------------------------
108 -- Interrupt vector numbers
109 ---------------------------------------------------------------------------- */
110
111/*!
112 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
113 * @{
114 */
115
116/** Interrupt Number Definitions */
117#define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
118
119typedef enum IRQn {
120 /* Auxiliary constants */
121 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
122
123 /* Core interrupts */
124 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
125 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
126 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
127 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
128 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
129 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
130 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
131 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
132 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
133
134 /* Device specific interrupts */
135 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
136 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
137 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
138 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
139 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
140 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
141 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
142 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
143 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
144 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
145 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
146 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
147 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
148 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
149 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
150 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
151 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
152 MCM_IRQn = 17, /**< Normal Interrupt */
153 FTF_IRQn = 18, /**< FTFA Command complete interrupt */
154 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
155 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
156 LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */
157 WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */
158 RNG_IRQn = 23, /**< RNG Interrupt */
159 I2C0_IRQn = 24, /**< I2C0 interrupt */
160 I2C1_IRQn = 25, /**< I2C1 interrupt */
161 SPI0_IRQn = 26, /**< SPI0 Interrupt */
162 SPI1_IRQn = 27, /**< SPI1 Interrupt */
163 Reserved44_IRQn = 28, /**< Reserved Interrupt 44 */
164 Reserved45_IRQn = 29, /**< Reserved interrupt 45 */
165 LPUART0_IRQn = 30, /**< LPUART0 status/error interrupt */
166 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
167 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
168 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
169 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
170 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
171 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
172 Reserved53_IRQn = 37, /**< Reserved interrupt 53 */
173 Reserved54_IRQn = 38, /**< Reserved interrupt 54 */
174 ADC0_IRQn = 39, /**< ADC0 interrupt */
175 CMP0_IRQn = 40, /**< CMP0 interrupt */
176 CMP1_IRQn = 41, /**< CMP1 interrupt */
177 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
178 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
179 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
180 Reserved61_IRQn = 45, /**< Reserved interrupt 61 */
181 Reserved62_IRQn = 46, /**< Reserved interrupt 62 */
182 Reserved63_IRQn = 47, /**< Reserved interrupt 63 */
183 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
184 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
185 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
186 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
187 PDB0_IRQn = 52, /**< PDB0 Interrupt */
188 Reserved69_IRQn = 53, /**< Reserved interrupt 69 */
189 Reserved70_IRQn = 54, /**< Reserved interrupt 70 */
190 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
191 DAC0_IRQn = 56, /**< DAC0 interrupt */
192 MCG_IRQn = 57, /**< MCG Interrupt */
193 LPTMR0_IRQn = 58, /**< LPTimer interrupt */
194 PORTA_IRQn = 59, /**< Port A interrupt */
195 PORTB_IRQn = 60, /**< Port B interrupt */
196 PORTC_IRQn = 61, /**< Port C interrupt */
197 PORTD_IRQn = 62, /**< Port D interrupt */
198 PORTE_IRQn = 63, /**< Port E interrupt */
199 SWI_IRQn = 64, /**< Software interrupt */
200 Reserved81_IRQn = 65, /**< Reserved interrupt 81 */
201 Reserved82_IRQn = 66, /**< Reserved interrupt 82 */
202 Reserved83_IRQn = 67, /**< Reserved interrupt 83 */
203 Reserved84_IRQn = 68, /**< Reserved interrupt 84 */
204 Reserved85_IRQn = 69, /**< Reserved interrupt 85 */
205 Reserved86_IRQn = 70, /**< Reserved interrupt 86 */
206 Reserved87_IRQn = 71, /**< Reserved interrupt 87 */
207 Reserved88_IRQn = 72, /**< Reserved interrupt 88 */
208 ADC1_IRQn = 73, /**< ADC1 interrupt */
209 Reserved90_IRQn = 74, /**< Reserved Interrupt 90 */
210 Reserved91_IRQn = 75, /**< Reserved Interrupt 91 */
211 Reserved92_IRQn = 76, /**< Reserved Interrupt 92 */
212 Reserved93_IRQn = 77, /**< Reserved Interrupt 93 */
213 Reserved94_IRQn = 78, /**< Reserved Interrupt 94 */
214 Reserved95_IRQn = 79, /**< Reserved Interrupt 95 */
215 Reserved96_IRQn = 80, /**< Reserved Interrupt 96 */
216 Reserved97_IRQn = 81, /**< Reserved Interrupt 97 */
217 Reserved98_IRQn = 82, /**< Reserved Interrupt 98 */
218 Reserved99_IRQn = 83, /**< Reserved Interrupt 99 */
219 Reserved100_IRQn = 84, /**< Reserved Interrupt 100 */
220 Reserved101_IRQn = 85 /**< Reserved Interrupt 101 */
221} IRQn_Type;
222
223/*!
224 * @}
225 */ /* end of group Interrupt_vector_numbers */
226
227
228/* ----------------------------------------------------------------------------
229 -- Cortex M4 Core Configuration
230 ---------------------------------------------------------------------------- */
231
232/*!
233 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
234 * @{
235 */
236
237#define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
238#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
239#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
240#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
241
242#include "core_cm4.h" /* Core Peripheral Access Layer */
243#include "system_MKV31F25612.h" /* Device specific configuration file */
244
245/*!
246 * @}
247 */ /* end of group Cortex_Core_Configuration */
248
249
250/* ----------------------------------------------------------------------------
251 -- Mapping Information
252 ---------------------------------------------------------------------------- */
253
254/*!
255 * @addtogroup Mapping_Information Mapping Information
256 * @{
257 */
258
259/** Mapping Information */
260/*!
261 * @addtogroup edma_request
262 * @{
263 */
264
265/*******************************************************************************
266 * Definitions
267 ******************************************************************************/
268
269/*!
270 * @brief Structure for the DMA hardware request
271 *
272 * Defines the structure for the DMA hardware request collections. The user can configure the
273 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
274 * of the hardware request varies according to the to SoC.
275 */
276typedef enum _dma_request_source
277{
278 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
279 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
280 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
281 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
282 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
283 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
284 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
285 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
286 kDmaRequestMux0Reserved8 = 8|0x100U, /**< Reserved8 */
287 kDmaRequestMux0Reserved9 = 9|0x100U, /**< Reserved9 */
288 kDmaRequestMux0Reserved10 = 10|0x100U, /**< Reserved10 */
289 kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */
290 kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */
291 kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */
292 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
293 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
294 kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */
295 kDmaRequestMux0Reserved17 = 17|0x100U, /**< Reserved17 */
296 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */
297 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1. */
298 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
299 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
300 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
301 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
302 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
303 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
304 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
305 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
306 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
307 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
308 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
309 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
310 kDmaRequestMux0Reserved32 = 32|0x100U, /**< Reserved32 */
311 kDmaRequestMux0Reserved33 = 33|0x100U, /**< Reserved33 */
312 kDmaRequestMux0Reserved34 = 34|0x100U, /**< Reserved34 */
313 kDmaRequestMux0Reserved35 = 35|0x100U, /**< Reserved35 */
314 kDmaRequestMux0Reserved36 = 36|0x100U, /**< Reserved36 */
315 kDmaRequestMux0Reserved37 = 37|0x100U, /**< Reserved37 */
316 kDmaRequestMux0Reserved38 = 38|0x100U, /**< Reserved38 */
317 kDmaRequestMux0Reserved39 = 39|0x100U, /**< Reserved39 */
318 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
319 kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
320 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
321 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
322 kDmaRequestMux0Reserved44 = 44|0x100U, /**< Reserved44 */
323 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
324 kDmaRequestMux0Reserved46 = 46|0x100U, /**< Reserved46 */
325 kDmaRequestMux0Reserved47 = 47|0x100U, /**< Reserved47 */
326 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
327 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
328 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
329 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
330 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
331 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
332 kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */
333 kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */
334 kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */
335 kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
336 kDmaRequestMux0LPUART0Rx = 58|0x100U, /**< LPUART0 Receive. */
337 kDmaRequestMux0LPUART0Tx = 59|0x100U, /**< LPUART0 Transmit. */
338 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
339 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
340 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
341 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
342} dma_request_source_t;
343
344/* @} */
345
346
347/*!
348 * @}
349 */ /* end of group Mapping_Information */
350
351
352/* ----------------------------------------------------------------------------
353 -- Device Peripheral Access Layer
354 ---------------------------------------------------------------------------- */
355
356/*!
357 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
358 * @{
359 */
360
361
362/*
363** Start of section using anonymous unions
364*/
365
366#if defined(__ARMCC_VERSION)
367 #if (__ARMCC_VERSION >= 6010050)
368 #pragma clang diagnostic push
369 #else
370 #pragma push
371 #pragma anon_unions
372 #endif
373#elif defined(__CWCC__)
374 #pragma push
375 #pragma cpp_extensions on
376#elif defined(__GNUC__)
377 /* anonymous unions are enabled by default */
378#elif defined(__IAR_SYSTEMS_ICC__)
379 #pragma language=extended
380#else
381 #error Not supported compiler type
382#endif
383
384/* ----------------------------------------------------------------------------
385 -- ADC Peripheral Access Layer
386 ---------------------------------------------------------------------------- */
387
388/*!
389 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
390 * @{
391 */
392
393/** ADC - Register Layout Typedef */
394typedef struct {
395 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
396 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
397 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
398 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
399 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
400 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
401 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
402 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
403 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
404 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
405 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
406 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
407 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
408 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
409 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
410 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
411 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
412 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
413 uint8_t RESERVED_0[4];
414 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
415 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
416 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
417 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
418 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
419 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
420 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
421} ADC_Type;
422
423/* ----------------------------------------------------------------------------
424 -- ADC Register Masks
425 ---------------------------------------------------------------------------- */
426
427/*!
428 * @addtogroup ADC_Register_Masks ADC Register Masks
429 * @{
430 */
431
432/*! @name SC1 - ADC Status and Control Registers 1 */
433/*! @{ */
434#define ADC_SC1_ADCH_MASK (0x1FU)
435#define ADC_SC1_ADCH_SHIFT (0U)
436/*! ADCH - Input channel select
437 * 0b00000..When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input.
438 * 0b00001..When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input.
439 * 0b00010..When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input.
440 * 0b00011..When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input.
441 * 0b00100..When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved.
442 * 0b00101..When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved.
443 * 0b00110..When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved.
444 * 0b00111..When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved.
445 * 0b01000..When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved.
446 * 0b01001..When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved.
447 * 0b01010..When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved.
448 * 0b01011..When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved.
449 * 0b01100..When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved.
450 * 0b01101..When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved.
451 * 0b01110..When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved.
452 * 0b01111..When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved.
453 * 0b10000..When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved.
454 * 0b10001..When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved.
455 * 0b10010..When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved.
456 * 0b10011..When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved.
457 * 0b10100..When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved.
458 * 0b10101..When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved.
459 * 0b10110..When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved.
460 * 0b10111..When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
461 * 0b11000..Reserved.
462 * 0b11001..Reserved.
463 * 0b11010..When DIFF=0, Temp Sensor (single-ended) is selected as input; when DIFF=1, Temp Sensor (differential) is selected as input.
464 * 0b11011..When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input.
465 * 0b11100..Reserved.
466 * 0b11101..When DIFF=0,VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by SC2[REFSEL].
467 * 0b11110..When DIFF=0,VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by SC2[REFSEL].
468 * 0b11111..Module is disabled.
469 */
470#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
471#define ADC_SC1_DIFF_MASK (0x20U)
472#define ADC_SC1_DIFF_SHIFT (5U)
473/*! DIFF - Differential Mode Enable
474 * 0b0..Single-ended conversions and input channels are selected.
475 * 0b1..Differential conversions and input channels are selected.
476 */
477#define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
478#define ADC_SC1_AIEN_MASK (0x40U)
479#define ADC_SC1_AIEN_SHIFT (6U)
480/*! AIEN - Interrupt Enable
481 * 0b0..Conversion complete interrupt is disabled.
482 * 0b1..Conversion complete interrupt is enabled.
483 */
484#define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
485#define ADC_SC1_COCO_MASK (0x80U)
486#define ADC_SC1_COCO_SHIFT (7U)
487/*! COCO - Conversion Complete Flag
488 * 0b0..Conversion is not completed.
489 * 0b1..Conversion is completed.
490 */
491#define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
492/*! @} */
493
494/* The count of ADC_SC1 */
495#define ADC_SC1_COUNT (2U)
496
497/*! @name CFG1 - ADC Configuration Register 1 */
498/*! @{ */
499#define ADC_CFG1_ADICLK_MASK (0x3U)
500#define ADC_CFG1_ADICLK_SHIFT (0U)
501/*! ADICLK - Input Clock Select
502 * 0b00..Bus clock
503 * 0b01..Alternate clock 2 (ALTCLK2)
504 * 0b10..Alternate clock (ALTCLK)
505 * 0b11..Asynchronous clock (ADACK)
506 */
507#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
508#define ADC_CFG1_MODE_MASK (0xCU)
509#define ADC_CFG1_MODE_SHIFT (2U)
510/*! MODE - Conversion mode selection
511 * 0b00..When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output.
512 * 0b01..When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion with 2's complement output.
513 * 0b10..When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion with 2's complement output
514 * 0b11..When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion with 2's complement output
515 */
516#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
517#define ADC_CFG1_ADLSMP_MASK (0x10U)
518#define ADC_CFG1_ADLSMP_SHIFT (4U)
519/*! ADLSMP - Sample Time Configuration
520 * 0b0..Short sample time.
521 * 0b1..Long sample time.
522 */
523#define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
524#define ADC_CFG1_ADIV_MASK (0x60U)
525#define ADC_CFG1_ADIV_SHIFT (5U)
526/*! ADIV - Clock Divide Select
527 * 0b00..The divide ratio is 1 and the clock rate is input clock.
528 * 0b01..The divide ratio is 2 and the clock rate is (input clock)/2.
529 * 0b10..The divide ratio is 4 and the clock rate is (input clock)/4.
530 * 0b11..The divide ratio is 8 and the clock rate is (input clock)/8.
531 */
532#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
533#define ADC_CFG1_ADLPC_MASK (0x80U)
534#define ADC_CFG1_ADLPC_SHIFT (7U)
535/*! ADLPC - Low-Power Configuration
536 * 0b0..Normal power configuration.
537 * 0b1..Low-power configuration. The power is reduced at the expense of maximum clock speed.
538 */
539#define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
540/*! @} */
541
542/*! @name CFG2 - ADC Configuration Register 2 */
543/*! @{ */
544#define ADC_CFG2_ADLSTS_MASK (0x3U)
545#define ADC_CFG2_ADLSTS_SHIFT (0U)
546/*! ADLSTS - Long Sample Time Select
547 * 0b00..Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
548 * 0b01..12 extra ADCK cycles; 16 ADCK cycles total sample time.
549 * 0b10..6 extra ADCK cycles; 10 ADCK cycles total sample time.
550 * 0b11..2 extra ADCK cycles; 6 ADCK cycles total sample time.
551 */
552#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
553#define ADC_CFG2_ADHSC_MASK (0x4U)
554#define ADC_CFG2_ADHSC_SHIFT (2U)
555/*! ADHSC - High-Speed Configuration
556 * 0b0..Normal conversion sequence selected.
557 * 0b1..High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
558 */
559#define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
560#define ADC_CFG2_ADACKEN_MASK (0x8U)
561#define ADC_CFG2_ADACKEN_SHIFT (3U)
562/*! ADACKEN - Asynchronous Clock Output Enable
563 * 0b0..Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
564 * 0b1..Asynchronous clock and clock output is enabled regardless of the state of the ADC.
565 */
566#define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
567#define ADC_CFG2_MUXSEL_MASK (0x10U)
568#define ADC_CFG2_MUXSEL_SHIFT (4U)
569/*! MUXSEL - ADC Mux Select
570 * 0b0..ADxxa channels are selected.
571 * 0b1..ADxxb channels are selected.
572 */
573#define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
574/*! @} */
575
576/*! @name R - ADC Data Result Register */
577/*! @{ */
578#define ADC_R_D_MASK (0xFFFFU)
579#define ADC_R_D_SHIFT (0U)
580#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
581/*! @} */
582
583/* The count of ADC_R */
584#define ADC_R_COUNT (2U)
585
586/*! @name CV1 - Compare Value Registers */
587/*! @{ */
588#define ADC_CV1_CV_MASK (0xFFFFU)
589#define ADC_CV1_CV_SHIFT (0U)
590#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
591/*! @} */
592
593/*! @name CV2 - Compare Value Registers */
594/*! @{ */
595#define ADC_CV2_CV_MASK (0xFFFFU)
596#define ADC_CV2_CV_SHIFT (0U)
597#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
598/*! @} */
599
600/*! @name SC2 - Status and Control Register 2 */
601/*! @{ */
602#define ADC_SC2_REFSEL_MASK (0x3U)
603#define ADC_SC2_REFSEL_SHIFT (0U)
604/*! REFSEL - Voltage Reference Selection
605 * 0b00..Default voltage reference pin pair, that is, external pins VREFH and VREFL
606 * 0b01..Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
607 * 0b10..Reserved
608 * 0b11..Reserved
609 */
610#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
611#define ADC_SC2_DMAEN_MASK (0x4U)
612#define ADC_SC2_DMAEN_SHIFT (2U)
613/*! DMAEN - DMA Enable
614 * 0b0..DMA is disabled.
615 * 0b1..DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
616 */
617#define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
618#define ADC_SC2_ACREN_MASK (0x8U)
619#define ADC_SC2_ACREN_SHIFT (3U)
620/*! ACREN - Compare Function Range Enable
621 * 0b0..Range function disabled. Only CV1 is compared.
622 * 0b1..Range function enabled. Both CV1 and CV2 are compared.
623 */
624#define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
625#define ADC_SC2_ACFGT_MASK (0x10U)
626#define ADC_SC2_ACFGT_SHIFT (4U)
627/*! ACFGT - Compare Function Greater Than Enable
628 * 0b0..Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
629 * 0b1..Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
630 */
631#define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
632#define ADC_SC2_ACFE_MASK (0x20U)
633#define ADC_SC2_ACFE_SHIFT (5U)
634/*! ACFE - Compare Function Enable
635 * 0b0..Compare function disabled.
636 * 0b1..Compare function enabled.
637 */
638#define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
639#define ADC_SC2_ADTRG_MASK (0x40U)
640#define ADC_SC2_ADTRG_SHIFT (6U)
641/*! ADTRG - Conversion Trigger Select
642 * 0b0..Software trigger selected.
643 * 0b1..Hardware trigger selected.
644 */
645#define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
646#define ADC_SC2_ADACT_MASK (0x80U)
647#define ADC_SC2_ADACT_SHIFT (7U)
648/*! ADACT - Conversion Active
649 * 0b0..Conversion not in progress.
650 * 0b1..Conversion in progress.
651 */
652#define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
653/*! @} */
654
655/*! @name SC3 - Status and Control Register 3 */
656/*! @{ */
657#define ADC_SC3_AVGS_MASK (0x3U)
658#define ADC_SC3_AVGS_SHIFT (0U)
659/*! AVGS - Hardware Average Select
660 * 0b00..4 samples averaged.
661 * 0b01..8 samples averaged.
662 * 0b10..16 samples averaged.
663 * 0b11..32 samples averaged.
664 */
665#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
666#define ADC_SC3_AVGE_MASK (0x4U)
667#define ADC_SC3_AVGE_SHIFT (2U)
668/*! AVGE - Hardware Average Enable
669 * 0b0..Hardware average function disabled.
670 * 0b1..Hardware average function enabled.
671 */
672#define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
673#define ADC_SC3_ADCO_MASK (0x8U)
674#define ADC_SC3_ADCO_SHIFT (3U)
675/*! ADCO - Continuous Conversion Enable
676 * 0b0..One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
677 * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
678 */
679#define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
680#define ADC_SC3_CALF_MASK (0x40U)
681#define ADC_SC3_CALF_SHIFT (6U)
682/*! CALF - Calibration Failed Flag
683 * 0b0..Calibration completed normally.
684 * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
685 */
686#define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
687#define ADC_SC3_CAL_MASK (0x80U)
688#define ADC_SC3_CAL_SHIFT (7U)
689#define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
690/*! @} */
691
692/*! @name OFS - ADC Offset Correction Register */
693/*! @{ */
694#define ADC_OFS_OFS_MASK (0xFFFFU)
695#define ADC_OFS_OFS_SHIFT (0U)
696#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
697/*! @} */
698
699/*! @name PG - ADC Plus-Side Gain Register */
700/*! @{ */
701#define ADC_PG_PG_MASK (0xFFFFU)
702#define ADC_PG_PG_SHIFT (0U)
703#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
704/*! @} */
705
706/*! @name MG - ADC Minus-Side Gain Register */
707/*! @{ */
708#define ADC_MG_MG_MASK (0xFFFFU)
709#define ADC_MG_MG_SHIFT (0U)
710#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
711/*! @} */
712
713/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
714/*! @{ */
715#define ADC_CLPD_CLPD_MASK (0x3FU)
716#define ADC_CLPD_CLPD_SHIFT (0U)
717#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
718/*! @} */
719
720/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
721/*! @{ */
722#define ADC_CLPS_CLPS_MASK (0x3FU)
723#define ADC_CLPS_CLPS_SHIFT (0U)
724#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
725/*! @} */
726
727/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
728/*! @{ */
729#define ADC_CLP4_CLP4_MASK (0x3FFU)
730#define ADC_CLP4_CLP4_SHIFT (0U)
731#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
732/*! @} */
733
734/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
735/*! @{ */
736#define ADC_CLP3_CLP3_MASK (0x1FFU)
737#define ADC_CLP3_CLP3_SHIFT (0U)
738#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
739/*! @} */
740
741/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
742/*! @{ */
743#define ADC_CLP2_CLP2_MASK (0xFFU)
744#define ADC_CLP2_CLP2_SHIFT (0U)
745#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
746/*! @} */
747
748/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
749/*! @{ */
750#define ADC_CLP1_CLP1_MASK (0x7FU)
751#define ADC_CLP1_CLP1_SHIFT (0U)
752#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
753/*! @} */
754
755/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
756/*! @{ */
757#define ADC_CLP0_CLP0_MASK (0x3FU)
758#define ADC_CLP0_CLP0_SHIFT (0U)
759#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
760/*! @} */
761
762/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
763/*! @{ */
764#define ADC_CLMD_CLMD_MASK (0x3FU)
765#define ADC_CLMD_CLMD_SHIFT (0U)
766#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
767/*! @} */
768
769/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
770/*! @{ */
771#define ADC_CLMS_CLMS_MASK (0x3FU)
772#define ADC_CLMS_CLMS_SHIFT (0U)
773#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
774/*! @} */
775
776/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
777/*! @{ */
778#define ADC_CLM4_CLM4_MASK (0x3FFU)
779#define ADC_CLM4_CLM4_SHIFT (0U)
780#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
781/*! @} */
782
783/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
784/*! @{ */
785#define ADC_CLM3_CLM3_MASK (0x1FFU)
786#define ADC_CLM3_CLM3_SHIFT (0U)
787#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
788/*! @} */
789
790/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
791/*! @{ */
792#define ADC_CLM2_CLM2_MASK (0xFFU)
793#define ADC_CLM2_CLM2_SHIFT (0U)
794#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
795/*! @} */
796
797/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
798/*! @{ */
799#define ADC_CLM1_CLM1_MASK (0x7FU)
800#define ADC_CLM1_CLM1_SHIFT (0U)
801#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
802/*! @} */
803
804/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
805/*! @{ */
806#define ADC_CLM0_CLM0_MASK (0x3FU)
807#define ADC_CLM0_CLM0_SHIFT (0U)
808#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
809/*! @} */
810
811
812/*!
813 * @}
814 */ /* end of group ADC_Register_Masks */
815
816
817/* ADC - Peripheral instance base addresses */
818/** Peripheral ADC0 base address */
819#define ADC0_BASE (0x4003B000u)
820/** Peripheral ADC0 base pointer */
821#define ADC0 ((ADC_Type *)ADC0_BASE)
822/** Peripheral ADC1 base address */
823#define ADC1_BASE (0x40027000u)
824/** Peripheral ADC1 base pointer */
825#define ADC1 ((ADC_Type *)ADC1_BASE)
826/** Array initializer of ADC peripheral base addresses */
827#define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
828/** Array initializer of ADC peripheral base pointers */
829#define ADC_BASE_PTRS { ADC0, ADC1 }
830/** Interrupt vectors for the ADC peripheral type */
831#define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
832
833/*!
834 * @}
835 */ /* end of group ADC_Peripheral_Access_Layer */
836
837
838/* ----------------------------------------------------------------------------
839 -- CMP Peripheral Access Layer
840 ---------------------------------------------------------------------------- */
841
842/*!
843 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
844 * @{
845 */
846
847/** CMP - Register Layout Typedef */
848typedef struct {
849 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
850 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
851 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
852 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
853 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
854 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
855} CMP_Type;
856
857/* ----------------------------------------------------------------------------
858 -- CMP Register Masks
859 ---------------------------------------------------------------------------- */
860
861/*!
862 * @addtogroup CMP_Register_Masks CMP Register Masks
863 * @{
864 */
865
866/*! @name CR0 - CMP Control Register 0 */
867/*! @{ */
868#define CMP_CR0_HYSTCTR_MASK (0x3U)
869#define CMP_CR0_HYSTCTR_SHIFT (0U)
870/*! HYSTCTR - Comparator hard block hysteresis control
871 * 0b00..Level 0
872 * 0b01..Level 1
873 * 0b10..Level 2
874 * 0b11..Level 3
875 */
876#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
877#define CMP_CR0_FILTER_CNT_MASK (0x70U)
878#define CMP_CR0_FILTER_CNT_SHIFT (4U)
879/*! FILTER_CNT - Filter Sample Count
880 * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
881 * 0b001..One sample must agree. The comparator output is simply sampled.
882 * 0b010..2 consecutive samples must agree.
883 * 0b011..3 consecutive samples must agree.
884 * 0b100..4 consecutive samples must agree.
885 * 0b101..5 consecutive samples must agree.
886 * 0b110..6 consecutive samples must agree.
887 * 0b111..7 consecutive samples must agree.
888 */
889#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
890/*! @} */
891
892/*! @name CR1 - CMP Control Register 1 */
893/*! @{ */
894#define CMP_CR1_EN_MASK (0x1U)
895#define CMP_CR1_EN_SHIFT (0U)
896/*! EN - Comparator Module Enable
897 * 0b0..Analog Comparator is disabled.
898 * 0b1..Analog Comparator is enabled.
899 */
900#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
901#define CMP_CR1_OPE_MASK (0x2U)
902#define CMP_CR1_OPE_SHIFT (1U)
903/*! OPE - Comparator Output Pin Enable
904 * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
905 * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect.
906 */
907#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
908#define CMP_CR1_COS_MASK (0x4U)
909#define CMP_CR1_COS_SHIFT (2U)
910/*! COS - Comparator Output Select
911 * 0b0..Set the filtered comparator output (CMPO) to equal COUT.
912 * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
913 */
914#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
915#define CMP_CR1_INV_MASK (0x8U)
916#define CMP_CR1_INV_SHIFT (3U)
917/*! INV - Comparator INVERT
918 * 0b0..Does not invert the comparator output.
919 * 0b1..Inverts the comparator output.
920 */
921#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
922#define CMP_CR1_PMODE_MASK (0x10U)
923#define CMP_CR1_PMODE_SHIFT (4U)
924/*! PMODE - Power Mode Select
925 * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
926 * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
927 */
928#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
929#define CMP_CR1_TRIGM_MASK (0x20U)
930#define CMP_CR1_TRIGM_SHIFT (5U)
931/*! TRIGM - Trigger Mode Enable
932 * 0b0..Trigger mode is disabled.
933 * 0b1..Trigger mode is enabled.
934 */
935#define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
936#define CMP_CR1_WE_MASK (0x40U)
937#define CMP_CR1_WE_SHIFT (6U)
938/*! WE - Windowing Enable
939 * 0b0..Windowing mode is not selected.
940 * 0b1..Windowing mode is selected.
941 */
942#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
943#define CMP_CR1_SE_MASK (0x80U)
944#define CMP_CR1_SE_SHIFT (7U)
945/*! SE - Sample Enable
946 * 0b0..Sampling mode is not selected.
947 * 0b1..Sampling mode is selected.
948 */
949#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
950/*! @} */
951
952/*! @name FPR - CMP Filter Period Register */
953/*! @{ */
954#define CMP_FPR_FILT_PER_MASK (0xFFU)
955#define CMP_FPR_FILT_PER_SHIFT (0U)
956#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
957/*! @} */
958
959/*! @name SCR - CMP Status and Control Register */
960/*! @{ */
961#define CMP_SCR_COUT_MASK (0x1U)
962#define CMP_SCR_COUT_SHIFT (0U)
963#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
964#define CMP_SCR_CFF_MASK (0x2U)
965#define CMP_SCR_CFF_SHIFT (1U)
966/*! CFF - Analog Comparator Flag Falling
967 * 0b0..Falling-edge on COUT has not been detected.
968 * 0b1..Falling-edge on COUT has occurred.
969 */
970#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
971#define CMP_SCR_CFR_MASK (0x4U)
972#define CMP_SCR_CFR_SHIFT (2U)
973/*! CFR - Analog Comparator Flag Rising
974 * 0b0..Rising-edge on COUT has not been detected.
975 * 0b1..Rising-edge on COUT has occurred.
976 */
977#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
978#define CMP_SCR_IEF_MASK (0x8U)
979#define CMP_SCR_IEF_SHIFT (3U)
980/*! IEF - Comparator Interrupt Enable Falling
981 * 0b0..Interrupt is disabled.
982 * 0b1..Interrupt is enabled.
983 */
984#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
985#define CMP_SCR_IER_MASK (0x10U)
986#define CMP_SCR_IER_SHIFT (4U)
987/*! IER - Comparator Interrupt Enable Rising
988 * 0b0..Interrupt is disabled.
989 * 0b1..Interrupt is enabled.
990 */
991#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
992#define CMP_SCR_DMAEN_MASK (0x40U)
993#define CMP_SCR_DMAEN_SHIFT (6U)
994/*! DMAEN - DMA Enable Control
995 * 0b0..DMA is disabled.
996 * 0b1..DMA is enabled.
997 */
998#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
999/*! @} */
1000
1001/*! @name DACCR - DAC Control Register */
1002/*! @{ */
1003#define CMP_DACCR_VOSEL_MASK (0x3FU)
1004#define CMP_DACCR_VOSEL_SHIFT (0U)
1005#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
1006#define CMP_DACCR_VRSEL_MASK (0x40U)
1007#define CMP_DACCR_VRSEL_SHIFT (6U)
1008/*! VRSEL - Supply Voltage Reference Source Select
1009 * 0b0..V is selected as resistor ladder network supply reference V. in1 in
1010 * 0b1..V is selected as resistor ladder network supply reference V. in2 in
1011 */
1012#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
1013#define CMP_DACCR_DACEN_MASK (0x80U)
1014#define CMP_DACCR_DACEN_SHIFT (7U)
1015/*! DACEN - DAC Enable
1016 * 0b0..DAC is disabled.
1017 * 0b1..DAC is enabled.
1018 */
1019#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
1020/*! @} */
1021
1022/*! @name MUXCR - MUX Control Register */
1023/*! @{ */
1024#define CMP_MUXCR_MSEL_MASK (0x7U)
1025#define CMP_MUXCR_MSEL_SHIFT (0U)
1026/*! MSEL - Minus Input Mux Control
1027 * 0b000..IN0
1028 * 0b001..IN1
1029 * 0b010..IN2
1030 * 0b011..IN3
1031 * 0b100..IN4
1032 * 0b101..IN5
1033 * 0b110..IN6
1034 * 0b111..IN7
1035 */
1036#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
1037#define CMP_MUXCR_PSEL_MASK (0x38U)
1038#define CMP_MUXCR_PSEL_SHIFT (3U)
1039/*! PSEL - Plus Input Mux Control
1040 * 0b000..IN0
1041 * 0b001..IN1
1042 * 0b010..IN2
1043 * 0b011..IN3
1044 * 0b100..IN4
1045 * 0b101..IN5
1046 * 0b110..IN6
1047 * 0b111..IN7
1048 */
1049#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
1050/*! @} */
1051
1052
1053/*!
1054 * @}
1055 */ /* end of group CMP_Register_Masks */
1056
1057
1058/* CMP - Peripheral instance base addresses */
1059/** Peripheral CMP0 base address */
1060#define CMP0_BASE (0x40073000u)
1061/** Peripheral CMP0 base pointer */
1062#define CMP0 ((CMP_Type *)CMP0_BASE)
1063/** Peripheral CMP1 base address */
1064#define CMP1_BASE (0x40073008u)
1065/** Peripheral CMP1 base pointer */
1066#define CMP1 ((CMP_Type *)CMP1_BASE)
1067/** Array initializer of CMP peripheral base addresses */
1068#define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE }
1069/** Array initializer of CMP peripheral base pointers */
1070#define CMP_BASE_PTRS { CMP0, CMP1 }
1071/** Interrupt vectors for the CMP peripheral type */
1072#define CMP_IRQS { CMP0_IRQn, CMP1_IRQn }
1073
1074/*!
1075 * @}
1076 */ /* end of group CMP_Peripheral_Access_Layer */
1077
1078
1079/* ----------------------------------------------------------------------------
1080 -- CRC Peripheral Access Layer
1081 ---------------------------------------------------------------------------- */
1082
1083/*!
1084 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
1085 * @{
1086 */
1087
1088/** CRC - Register Layout Typedef */
1089typedef struct {
1090 union { /* offset: 0x0 */
1091 struct { /* offset: 0x0 */
1092 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
1093 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
1094 } ACCESS16BIT;
1095 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
1096 struct { /* offset: 0x0 */
1097 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
1098 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
1099 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
1100 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
1101 } ACCESS8BIT;
1102 };
1103 union { /* offset: 0x4 */
1104 struct { /* offset: 0x4 */
1105 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
1106 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
1107 } GPOLY_ACCESS16BIT;
1108 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
1109 struct { /* offset: 0x4 */
1110 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
1111 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
1112 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
1113 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
1114 } GPOLY_ACCESS8BIT;
1115 };
1116 union { /* offset: 0x8 */
1117 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
1118 struct { /* offset: 0x8 */
1119 uint8_t RESERVED_0[3];
1120 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
1121 } CTRL_ACCESS8BIT;
1122 };
1123} CRC_Type;
1124
1125/* ----------------------------------------------------------------------------
1126 -- CRC Register Masks
1127 ---------------------------------------------------------------------------- */
1128
1129/*!
1130 * @addtogroup CRC_Register_Masks CRC Register Masks
1131 * @{
1132 */
1133
1134/*! @name DATAL - CRC_DATAL register. */
1135/*! @{ */
1136#define CRC_DATAL_DATAL_MASK (0xFFFFU)
1137#define CRC_DATAL_DATAL_SHIFT (0U)
1138#define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
1139/*! @} */
1140
1141/*! @name DATAH - CRC_DATAH register. */
1142/*! @{ */
1143#define CRC_DATAH_DATAH_MASK (0xFFFFU)
1144#define CRC_DATAH_DATAH_SHIFT (0U)
1145#define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
1146/*! @} */
1147
1148/*! @name DATA - CRC Data register */
1149/*! @{ */
1150#define CRC_DATA_LL_MASK (0xFFU)
1151#define CRC_DATA_LL_SHIFT (0U)
1152#define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
1153#define CRC_DATA_LU_MASK (0xFF00U)
1154#define CRC_DATA_LU_SHIFT (8U)
1155#define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
1156#define CRC_DATA_HL_MASK (0xFF0000U)
1157#define CRC_DATA_HL_SHIFT (16U)
1158#define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
1159#define CRC_DATA_HU_MASK (0xFF000000U)
1160#define CRC_DATA_HU_SHIFT (24U)
1161#define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
1162/*! @} */
1163
1164/*! @name DATALL - CRC_DATALL register. */
1165/*! @{ */
1166#define CRC_DATALL_DATALL_MASK (0xFFU)
1167#define CRC_DATALL_DATALL_SHIFT (0U)
1168#define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
1169/*! @} */
1170
1171/*! @name DATALU - CRC_DATALU register. */
1172/*! @{ */
1173#define CRC_DATALU_DATALU_MASK (0xFFU)
1174#define CRC_DATALU_DATALU_SHIFT (0U)
1175#define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
1176/*! @} */
1177
1178/*! @name DATAHL - CRC_DATAHL register. */
1179/*! @{ */
1180#define CRC_DATAHL_DATAHL_MASK (0xFFU)
1181#define CRC_DATAHL_DATAHL_SHIFT (0U)
1182#define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
1183/*! @} */
1184
1185/*! @name DATAHU - CRC_DATAHU register. */
1186/*! @{ */
1187#define CRC_DATAHU_DATAHU_MASK (0xFFU)
1188#define CRC_DATAHU_DATAHU_SHIFT (0U)
1189#define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
1190/*! @} */
1191
1192/*! @name GPOLYL - CRC_GPOLYL register. */
1193/*! @{ */
1194#define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
1195#define CRC_GPOLYL_GPOLYL_SHIFT (0U)
1196#define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
1197/*! @} */
1198
1199/*! @name GPOLYH - CRC_GPOLYH register. */
1200/*! @{ */
1201#define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
1202#define CRC_GPOLYH_GPOLYH_SHIFT (0U)
1203#define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
1204/*! @} */
1205
1206/*! @name GPOLY - CRC Polynomial register */
1207/*! @{ */
1208#define CRC_GPOLY_LOW_MASK (0xFFFFU)
1209#define CRC_GPOLY_LOW_SHIFT (0U)
1210#define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
1211#define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
1212#define CRC_GPOLY_HIGH_SHIFT (16U)
1213#define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
1214/*! @} */
1215
1216/*! @name GPOLYLL - CRC_GPOLYLL register. */
1217/*! @{ */
1218#define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
1219#define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
1220#define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
1221/*! @} */
1222
1223/*! @name GPOLYLU - CRC_GPOLYLU register. */
1224/*! @{ */
1225#define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
1226#define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
1227#define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
1228/*! @} */
1229
1230/*! @name GPOLYHL - CRC_GPOLYHL register. */
1231/*! @{ */
1232#define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
1233#define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
1234#define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
1235/*! @} */
1236
1237/*! @name GPOLYHU - CRC_GPOLYHU register. */
1238/*! @{ */
1239#define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
1240#define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
1241#define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
1242/*! @} */
1243
1244/*! @name CTRL - CRC Control register */
1245/*! @{ */
1246#define CRC_CTRL_TCRC_MASK (0x1000000U)
1247#define CRC_CTRL_TCRC_SHIFT (24U)
1248/*! TCRC
1249 * 0b0..16-bit CRC protocol.
1250 * 0b1..32-bit CRC protocol.
1251 */
1252#define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
1253#define CRC_CTRL_WAS_MASK (0x2000000U)
1254#define CRC_CTRL_WAS_SHIFT (25U)
1255/*! WAS - Write CRC Data Register As Seed
1256 * 0b0..Writes to the CRC data register are data values.
1257 * 0b1..Writes to the CRC data register are seed values.
1258 */
1259#define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
1260#define CRC_CTRL_FXOR_MASK (0x4000000U)
1261#define CRC_CTRL_FXOR_SHIFT (26U)
1262/*! FXOR - Complement Read Of CRC Data Register
1263 * 0b0..No XOR on reading.
1264 * 0b1..Invert or complement the read value of the CRC Data register.
1265 */
1266#define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
1267#define CRC_CTRL_TOTR_MASK (0x30000000U)
1268#define CRC_CTRL_TOTR_SHIFT (28U)
1269/*! TOTR - Type Of Transpose For Read
1270 * 0b00..No transposition.
1271 * 0b01..Bits in bytes are transposed; bytes are not transposed.
1272 * 0b10..Both bits in bytes and bytes are transposed.
1273 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
1274 */
1275#define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
1276#define CRC_CTRL_TOT_MASK (0xC0000000U)
1277#define CRC_CTRL_TOT_SHIFT (30U)
1278/*! TOT - Type Of Transpose For Writes
1279 * 0b00..No transposition.
1280 * 0b01..Bits in bytes are transposed; bytes are not transposed.
1281 * 0b10..Both bits in bytes and bytes are transposed.
1282 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
1283 */
1284#define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
1285/*! @} */
1286
1287/*! @name CTRLHU - CRC_CTRLHU register. */
1288/*! @{ */
1289#define CRC_CTRLHU_TCRC_MASK (0x1U)
1290#define CRC_CTRLHU_TCRC_SHIFT (0U)
1291/*! TCRC
1292 * 0b0..16-bit CRC protocol.
1293 * 0b1..32-bit CRC protocol.
1294 */
1295#define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
1296#define CRC_CTRLHU_WAS_MASK (0x2U)
1297#define CRC_CTRLHU_WAS_SHIFT (1U)
1298/*! WAS
1299 * 0b0..Writes to CRC data register are data values.
1300 * 0b1..Writes to CRC data reguster are seed values.
1301 */
1302#define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
1303#define CRC_CTRLHU_FXOR_MASK (0x4U)
1304#define CRC_CTRLHU_FXOR_SHIFT (2U)
1305/*! FXOR
1306 * 0b0..No XOR on reading.
1307 * 0b1..Invert or complement the read value of CRC data register.
1308 */
1309#define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
1310#define CRC_CTRLHU_TOTR_MASK (0x30U)
1311#define CRC_CTRLHU_TOTR_SHIFT (4U)
1312/*! TOTR
1313 * 0b00..No Transposition.
1314 * 0b01..Bits in bytes are transposed, bytes are not transposed.
1315 * 0b10..Both bits in bytes and bytes are transposed.
1316 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
1317 */
1318#define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
1319#define CRC_CTRLHU_TOT_MASK (0xC0U)
1320#define CRC_CTRLHU_TOT_SHIFT (6U)
1321/*! TOT
1322 * 0b00..No Transposition.
1323 * 0b01..Bits in bytes are transposed, bytes are not transposed.
1324 * 0b10..Both bits in bytes and bytes are transposed.
1325 * 0b11..Only bytes are transposed; no bits in a byte are transposed.
1326 */
1327#define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
1328/*! @} */
1329
1330
1331/*!
1332 * @}
1333 */ /* end of group CRC_Register_Masks */
1334
1335
1336/* CRC - Peripheral instance base addresses */
1337/** Peripheral CRC base address */
1338#define CRC_BASE (0x40032000u)
1339/** Peripheral CRC base pointer */
1340#define CRC0 ((CRC_Type *)CRC_BASE)
1341/** Array initializer of CRC peripheral base addresses */
1342#define CRC_BASE_ADDRS { CRC_BASE }
1343/** Array initializer of CRC peripheral base pointers */
1344#define CRC_BASE_PTRS { CRC0 }
1345
1346/*!
1347 * @}
1348 */ /* end of group CRC_Peripheral_Access_Layer */
1349
1350
1351/* ----------------------------------------------------------------------------
1352 -- DAC Peripheral Access Layer
1353 ---------------------------------------------------------------------------- */
1354
1355/*!
1356 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
1357 * @{
1358 */
1359
1360/** DAC - Register Layout Typedef */
1361typedef struct {
1362 struct { /* offset: 0x0, array step: 0x2 */
1363 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
1364 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
1365 } DAT[16];
1366 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
1367 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
1368 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
1369 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
1370} DAC_Type;
1371
1372/* ----------------------------------------------------------------------------
1373 -- DAC Register Masks
1374 ---------------------------------------------------------------------------- */
1375
1376/*!
1377 * @addtogroup DAC_Register_Masks DAC Register Masks
1378 * @{
1379 */
1380
1381/*! @name DATL - DAC Data Low Register */
1382/*! @{ */
1383#define DAC_DATL_DATA0_MASK (0xFFU)
1384#define DAC_DATL_DATA0_SHIFT (0U)
1385#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
1386/*! @} */
1387
1388/* The count of DAC_DATL */
1389#define DAC_DATL_COUNT (16U)
1390
1391/*! @name DATH - DAC Data High Register */
1392/*! @{ */
1393#define DAC_DATH_DATA1_MASK (0xFU)
1394#define DAC_DATH_DATA1_SHIFT (0U)
1395#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
1396/*! @} */
1397
1398/* The count of DAC_DATH */
1399#define DAC_DATH_COUNT (16U)
1400
1401/*! @name SR - DAC Status Register */
1402/*! @{ */
1403#define DAC_SR_DACBFRPBF_MASK (0x1U)
1404#define DAC_SR_DACBFRPBF_SHIFT (0U)
1405/*! DACBFRPBF - DAC Buffer Read Pointer Bottom Position Flag
1406 * 0b0..The DAC buffer read pointer is not equal to C2[DACBFUP].
1407 * 0b1..The DAC buffer read pointer is equal to C2[DACBFUP].
1408 */
1409#define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
1410#define DAC_SR_DACBFRPTF_MASK (0x2U)
1411#define DAC_SR_DACBFRPTF_SHIFT (1U)
1412/*! DACBFRPTF - DAC Buffer Read Pointer Top Position Flag
1413 * 0b0..The DAC buffer read pointer is not zero.
1414 * 0b1..The DAC buffer read pointer is zero.
1415 */
1416#define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
1417#define DAC_SR_DACBFWMF_MASK (0x4U)
1418#define DAC_SR_DACBFWMF_SHIFT (2U)
1419/*! DACBFWMF - DAC Buffer Watermark Flag
1420 * 0b0..The DAC buffer read pointer has not reached the watermark level.
1421 * 0b1..The DAC buffer read pointer has reached the watermark level.
1422 */
1423#define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
1424/*! @} */
1425
1426/*! @name C0 - DAC Control Register */
1427/*! @{ */
1428#define DAC_C0_DACBBIEN_MASK (0x1U)
1429#define DAC_C0_DACBBIEN_SHIFT (0U)
1430/*! DACBBIEN - DAC Buffer Read Pointer Bottom Flag Interrupt Enable
1431 * 0b0..The DAC buffer read pointer bottom flag interrupt is disabled.
1432 * 0b1..The DAC buffer read pointer bottom flag interrupt is enabled.
1433 */
1434#define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
1435#define DAC_C0_DACBTIEN_MASK (0x2U)
1436#define DAC_C0_DACBTIEN_SHIFT (1U)
1437/*! DACBTIEN - DAC Buffer Read Pointer Top Flag Interrupt Enable
1438 * 0b0..The DAC buffer read pointer top flag interrupt is disabled.
1439 * 0b1..The DAC buffer read pointer top flag interrupt is enabled.
1440 */
1441#define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
1442#define DAC_C0_DACBWIEN_MASK (0x4U)
1443#define DAC_C0_DACBWIEN_SHIFT (2U)
1444/*! DACBWIEN - DAC Buffer Watermark Interrupt Enable
1445 * 0b0..The DAC buffer watermark interrupt is disabled.
1446 * 0b1..The DAC buffer watermark interrupt is enabled.
1447 */
1448#define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
1449#define DAC_C0_LPEN_MASK (0x8U)
1450#define DAC_C0_LPEN_SHIFT (3U)
1451/*! LPEN - DAC Low Power Control
1452 * 0b0..High-Power mode
1453 * 0b1..Low-Power mode
1454 */
1455#define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
1456#define DAC_C0_DACSWTRG_MASK (0x10U)
1457#define DAC_C0_DACSWTRG_SHIFT (4U)
1458/*! DACSWTRG - DAC Software Trigger
1459 * 0b0..The DAC soft trigger is not valid.
1460 * 0b1..The DAC soft trigger is valid.
1461 */
1462#define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
1463#define DAC_C0_DACTRGSEL_MASK (0x20U)
1464#define DAC_C0_DACTRGSEL_SHIFT (5U)
1465/*! DACTRGSEL - DAC Trigger Select
1466 * 0b0..The DAC hardware trigger is selected.
1467 * 0b1..The DAC software trigger is selected.
1468 */
1469#define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
1470#define DAC_C0_DACRFS_MASK (0x40U)
1471#define DAC_C0_DACRFS_SHIFT (6U)
1472/*! DACRFS - DAC Reference Select
1473 * 0b0..The DAC selects DACREF_1 as the reference voltage.
1474 * 0b1..The DAC selects DACREF_2 as the reference voltage.
1475 */
1476#define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
1477#define DAC_C0_DACEN_MASK (0x80U)
1478#define DAC_C0_DACEN_SHIFT (7U)
1479/*! DACEN - DAC Enable
1480 * 0b0..The DAC system is disabled.
1481 * 0b1..The DAC system is enabled.
1482 */
1483#define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
1484/*! @} */
1485
1486/*! @name C1 - DAC Control Register 1 */
1487/*! @{ */
1488#define DAC_C1_DACBFEN_MASK (0x1U)
1489#define DAC_C1_DACBFEN_SHIFT (0U)
1490/*! DACBFEN - DAC Buffer Enable
1491 * 0b0..Buffer read pointer is disabled. The converted data is always the first word of the buffer.
1492 * 0b1..Buffer read pointer is enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer.
1493 */
1494#define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
1495#define DAC_C1_DACBFMD_MASK (0x6U)
1496#define DAC_C1_DACBFMD_SHIFT (1U)
1497/*! DACBFMD - DAC Buffer Work Mode Select
1498 * 0b00..Normal mode
1499 * 0b01..Swing mode
1500 * 0b10..One-Time Scan mode
1501 * 0b11..FIFO mode
1502 */
1503#define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
1504#define DAC_C1_DACBFWM_MASK (0x18U)
1505#define DAC_C1_DACBFWM_SHIFT (3U)
1506/*! DACBFWM - DAC Buffer Watermark Select
1507 * 0b00..In normal mode, 1 word . In FIFO mode, 2 or less than 2 data remaining in FIFO will set watermark status bit.
1508 * 0b01..In normal mode, 2 words . In FIFO mode, Max/4 or less than Max/4 data remaining in FIFO will set watermark status bit.
1509 * 0b10..In normal mode, 3 words . In FIFO mode, Max/2 or less than Max/2 data remaining in FIFO will set watermark status bit.
1510 * 0b11..In normal mode, 4 words . In FIFO mode, Max-2 or less than Max-2 data remaining in FIFO will set watermark status bit.
1511 */
1512#define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
1513#define DAC_C1_DMAEN_MASK (0x80U)
1514#define DAC_C1_DMAEN_SHIFT (7U)
1515/*! DMAEN - DMA Enable Select
1516 * 0b0..DMA is disabled.
1517 * 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The interrupts will not be presented on this module at the same time.
1518 */
1519#define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
1520/*! @} */
1521
1522/*! @name C2 - DAC Control Register 2 */
1523/*! @{ */
1524#define DAC_C2_DACBFUP_MASK (0xFU)
1525#define DAC_C2_DACBFUP_SHIFT (0U)
1526#define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
1527#define DAC_C2_DACBFRP_MASK (0xF0U)
1528#define DAC_C2_DACBFRP_SHIFT (4U)
1529#define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
1530/*! @} */
1531
1532
1533/*!
1534 * @}
1535 */ /* end of group DAC_Register_Masks */
1536
1537
1538/* DAC - Peripheral instance base addresses */
1539/** Peripheral DAC0 base address */
1540#define DAC0_BASE (0x4003F000u)
1541/** Peripheral DAC0 base pointer */
1542#define DAC0 ((DAC_Type *)DAC0_BASE)
1543/** Array initializer of DAC peripheral base addresses */
1544#define DAC_BASE_ADDRS { DAC0_BASE }
1545/** Array initializer of DAC peripheral base pointers */
1546#define DAC_BASE_PTRS { DAC0 }
1547/** Interrupt vectors for the DAC peripheral type */
1548#define DAC_IRQS { DAC0_IRQn }
1549
1550/*!
1551 * @}
1552 */ /* end of group DAC_Peripheral_Access_Layer */
1553
1554
1555/* ----------------------------------------------------------------------------
1556 -- DMA Peripheral Access Layer
1557 ---------------------------------------------------------------------------- */
1558
1559/*!
1560 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
1561 * @{
1562 */
1563
1564/** DMA - Register Layout Typedef */
1565typedef struct {
1566 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
1567 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
1568 uint8_t RESERVED_0[4];
1569 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
1570 uint8_t RESERVED_1[4];
1571 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
1572 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
1573 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
1574 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
1575 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
1576 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
1577 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
1578 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
1579 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
1580 uint8_t RESERVED_2[4];
1581 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
1582 uint8_t RESERVED_3[4];
1583 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
1584 uint8_t RESERVED_4[4];
1585 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
1586 uint8_t RESERVED_5[12];
1587 __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
1588 uint8_t RESERVED_6[184];
1589 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
1590 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
1591 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
1592 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
1593 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
1594 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
1595 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
1596 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
1597 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
1598 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
1599 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
1600 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
1601 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
1602 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
1603 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
1604 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
1605 uint8_t RESERVED_7[3824];
1606 struct { /* offset: 0x1000, array step: 0x20 */
1607 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
1608 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
1609 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
1610 union { /* offset: 0x1008, array step: 0x20 */
1611 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
1612 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
1613 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
1614 };
1615 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
1616 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
1617 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
1618 union { /* offset: 0x1016, array step: 0x20 */
1619 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
1620 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
1621 };
1622 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
1623 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
1624 union { /* offset: 0x101E, array step: 0x20 */
1625 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
1626 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
1627 };
1628 } TCD[16];
1629} DMA_Type;
1630
1631/* ----------------------------------------------------------------------------
1632 -- DMA Register Masks
1633 ---------------------------------------------------------------------------- */
1634
1635/*!
1636 * @addtogroup DMA_Register_Masks DMA Register Masks
1637 * @{
1638 */
1639
1640/*! @name CR - Control Register */
1641/*! @{ */
1642#define DMA_CR_EDBG_MASK (0x2U)
1643#define DMA_CR_EDBG_SHIFT (1U)
1644/*! EDBG - Enable Debug
1645 * 0b0..When in debug mode, the DMA continues to operate.
1646 * 0b1..When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared.
1647 */
1648#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
1649#define DMA_CR_ERCA_MASK (0x4U)
1650#define DMA_CR_ERCA_SHIFT (2U)
1651/*! ERCA - Enable Round Robin Channel Arbitration
1652 * 0b0..Fixed priority arbitration is used for channel selection .
1653 * 0b1..Round robin arbitration is used for channel selection .
1654 */
1655#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
1656#define DMA_CR_HOE_MASK (0x10U)
1657#define DMA_CR_HOE_SHIFT (4U)
1658/*! HOE - Halt On Error
1659 * 0b0..Normal operation
1660 * 0b1..Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared.
1661 */
1662#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
1663#define DMA_CR_HALT_MASK (0x20U)
1664#define DMA_CR_HALT_SHIFT (5U)
1665/*! HALT - Halt DMA Operations
1666 * 0b0..Normal operation
1667 * 0b1..Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared.
1668 */
1669#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
1670#define DMA_CR_CLM_MASK (0x40U)
1671#define DMA_CR_CLM_SHIFT (6U)
1672/*! CLM - Continuous Link Mode
1673 * 0b0..A minor loop channel link made to itself goes through channel arbitration before being activated again.
1674 * 0b1..A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop.
1675 */
1676#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
1677#define DMA_CR_EMLM_MASK (0x80U)
1678#define DMA_CR_EMLM_SHIFT (7U)
1679/*! EMLM - Enable Minor Loop Mapping
1680 * 0b0..Disabled. TCDn.word2 is defined as a 32-bit NBYTES field.
1681 * 0b1..Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled.
1682 */
1683#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
1684#define DMA_CR_ECX_MASK (0x10000U)
1685#define DMA_CR_ECX_SHIFT (16U)
1686/*! ECX - Error Cancel Transfer
1687 * 0b0..Normal operation
1688 * 0b1..Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the Error Status register (DMAx_ES) and generating an optional error interrupt.
1689 */
1690#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
1691#define DMA_CR_CX_MASK (0x20000U)
1692#define DMA_CR_CX_SHIFT (17U)
1693/*! CX - Cancel Transfer
1694 * 0b0..Normal operation
1695 * 0b1..Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed.
1696 */
1697#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
1698/*! @} */
1699
1700/*! @name ES - Error Status Register */
1701/*! @{ */
1702#define DMA_ES_DBE_MASK (0x1U)
1703#define DMA_ES_DBE_SHIFT (0U)
1704/*! DBE - Destination Bus Error
1705 * 0b0..No destination bus error
1706 * 0b1..The last recorded error was a bus error on a destination write
1707 */
1708#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
1709#define DMA_ES_SBE_MASK (0x2U)
1710#define DMA_ES_SBE_SHIFT (1U)
1711/*! SBE - Source Bus Error
1712 * 0b0..No source bus error
1713 * 0b1..The last recorded error was a bus error on a source read
1714 */
1715#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
1716#define DMA_ES_SGE_MASK (0x4U)
1717#define DMA_ES_SGE_SHIFT (2U)
1718/*! SGE - Scatter/Gather Configuration Error
1719 * 0b0..No scatter/gather configuration error
1720 * 0b1..The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary.
1721 */
1722#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
1723#define DMA_ES_NCE_MASK (0x8U)
1724#define DMA_ES_NCE_SHIFT (3U)
1725/*! NCE - NBYTES/CITER Configuration Error
1726 * 0b0..No NBYTES/CITER configuration error
1727 * 0b1..The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK]
1728 */
1729#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
1730#define DMA_ES_DOE_MASK (0x10U)
1731#define DMA_ES_DOE_SHIFT (4U)
1732/*! DOE - Destination Offset Error
1733 * 0b0..No destination offset configuration error
1734 * 0b1..The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
1735 */
1736#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
1737#define DMA_ES_DAE_MASK (0x20U)
1738#define DMA_ES_DAE_SHIFT (5U)
1739/*! DAE - Destination Address Error
1740 * 0b0..No destination address configuration error
1741 * 0b1..The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE].
1742 */
1743#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
1744#define DMA_ES_SOE_MASK (0x40U)
1745#define DMA_ES_SOE_SHIFT (6U)
1746/*! SOE - Source Offset Error
1747 * 0b0..No source offset configuration error
1748 * 0b1..The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
1749 */
1750#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
1751#define DMA_ES_SAE_MASK (0x80U)
1752#define DMA_ES_SAE_SHIFT (7U)
1753/*! SAE - Source Address Error
1754 * 0b0..No source address configuration error.
1755 * 0b1..The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE].
1756 */
1757#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
1758#define DMA_ES_ERRCHN_MASK (0xF00U)
1759#define DMA_ES_ERRCHN_SHIFT (8U)
1760#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
1761#define DMA_ES_CPE_MASK (0x4000U)
1762#define DMA_ES_CPE_SHIFT (14U)
1763/*! CPE - Channel Priority Error
1764 * 0b0..No channel priority error
1765 * 0b1..The last recorded error was a configuration error in the channel priorities . Channel priorities are not unique.
1766 */
1767#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
1768#define DMA_ES_ECX_MASK (0x10000U)
1769#define DMA_ES_ECX_SHIFT (16U)
1770/*! ECX - Transfer Canceled
1771 * 0b0..No canceled transfers
1772 * 0b1..The last recorded entry was a canceled transfer by the error cancel transfer input
1773 */
1774#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
1775#define DMA_ES_VLD_MASK (0x80000000U)
1776#define DMA_ES_VLD_SHIFT (31U)
1777/*! VLD
1778 * 0b0..No ERR bits are set
1779 * 0b1..At least one ERR bit is set indicating a valid error exists that has not been cleared
1780 */
1781#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
1782/*! @} */
1783
1784/*! @name ERQ - Enable Request Register */
1785/*! @{ */
1786#define DMA_ERQ_ERQ0_MASK (0x1U)
1787#define DMA_ERQ_ERQ0_SHIFT (0U)
1788/*! ERQ0 - Enable DMA Request 0
1789 * 0b0..The DMA request signal for the corresponding channel is disabled
1790 * 0b1..The DMA request signal for the corresponding channel is enabled
1791 */
1792#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
1793#define DMA_ERQ_ERQ1_MASK (0x2U)
1794#define DMA_ERQ_ERQ1_SHIFT (1U)
1795/*! ERQ1 - Enable DMA Request 1
1796 * 0b0..The DMA request signal for the corresponding channel is disabled
1797 * 0b1..The DMA request signal for the corresponding channel is enabled
1798 */
1799#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
1800#define DMA_ERQ_ERQ2_MASK (0x4U)
1801#define DMA_ERQ_ERQ2_SHIFT (2U)
1802/*! ERQ2 - Enable DMA Request 2
1803 * 0b0..The DMA request signal for the corresponding channel is disabled
1804 * 0b1..The DMA request signal for the corresponding channel is enabled
1805 */
1806#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
1807#define DMA_ERQ_ERQ3_MASK (0x8U)
1808#define DMA_ERQ_ERQ3_SHIFT (3U)
1809/*! ERQ3 - Enable DMA Request 3
1810 * 0b0..The DMA request signal for the corresponding channel is disabled
1811 * 0b1..The DMA request signal for the corresponding channel is enabled
1812 */
1813#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
1814#define DMA_ERQ_ERQ4_MASK (0x10U)
1815#define DMA_ERQ_ERQ4_SHIFT (4U)
1816/*! ERQ4 - Enable DMA Request 4
1817 * 0b0..The DMA request signal for the corresponding channel is disabled
1818 * 0b1..The DMA request signal for the corresponding channel is enabled
1819 */
1820#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
1821#define DMA_ERQ_ERQ5_MASK (0x20U)
1822#define DMA_ERQ_ERQ5_SHIFT (5U)
1823/*! ERQ5 - Enable DMA Request 5
1824 * 0b0..The DMA request signal for the corresponding channel is disabled
1825 * 0b1..The DMA request signal for the corresponding channel is enabled
1826 */
1827#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
1828#define DMA_ERQ_ERQ6_MASK (0x40U)
1829#define DMA_ERQ_ERQ6_SHIFT (6U)
1830/*! ERQ6 - Enable DMA Request 6
1831 * 0b0..The DMA request signal for the corresponding channel is disabled
1832 * 0b1..The DMA request signal for the corresponding channel is enabled
1833 */
1834#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
1835#define DMA_ERQ_ERQ7_MASK (0x80U)
1836#define DMA_ERQ_ERQ7_SHIFT (7U)
1837/*! ERQ7 - Enable DMA Request 7
1838 * 0b0..The DMA request signal for the corresponding channel is disabled
1839 * 0b1..The DMA request signal for the corresponding channel is enabled
1840 */
1841#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
1842#define DMA_ERQ_ERQ8_MASK (0x100U)
1843#define DMA_ERQ_ERQ8_SHIFT (8U)
1844/*! ERQ8 - Enable DMA Request 8
1845 * 0b0..The DMA request signal for the corresponding channel is disabled
1846 * 0b1..The DMA request signal for the corresponding channel is enabled
1847 */
1848#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
1849#define DMA_ERQ_ERQ9_MASK (0x200U)
1850#define DMA_ERQ_ERQ9_SHIFT (9U)
1851/*! ERQ9 - Enable DMA Request 9
1852 * 0b0..The DMA request signal for the corresponding channel is disabled
1853 * 0b1..The DMA request signal for the corresponding channel is enabled
1854 */
1855#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
1856#define DMA_ERQ_ERQ10_MASK (0x400U)
1857#define DMA_ERQ_ERQ10_SHIFT (10U)
1858/*! ERQ10 - Enable DMA Request 10
1859 * 0b0..The DMA request signal for the corresponding channel is disabled
1860 * 0b1..The DMA request signal for the corresponding channel is enabled
1861 */
1862#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
1863#define DMA_ERQ_ERQ11_MASK (0x800U)
1864#define DMA_ERQ_ERQ11_SHIFT (11U)
1865/*! ERQ11 - Enable DMA Request 11
1866 * 0b0..The DMA request signal for the corresponding channel is disabled
1867 * 0b1..The DMA request signal for the corresponding channel is enabled
1868 */
1869#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
1870#define DMA_ERQ_ERQ12_MASK (0x1000U)
1871#define DMA_ERQ_ERQ12_SHIFT (12U)
1872/*! ERQ12 - Enable DMA Request 12
1873 * 0b0..The DMA request signal for the corresponding channel is disabled
1874 * 0b1..The DMA request signal for the corresponding channel is enabled
1875 */
1876#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
1877#define DMA_ERQ_ERQ13_MASK (0x2000U)
1878#define DMA_ERQ_ERQ13_SHIFT (13U)
1879/*! ERQ13 - Enable DMA Request 13
1880 * 0b0..The DMA request signal for the corresponding channel is disabled
1881 * 0b1..The DMA request signal for the corresponding channel is enabled
1882 */
1883#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
1884#define DMA_ERQ_ERQ14_MASK (0x4000U)
1885#define DMA_ERQ_ERQ14_SHIFT (14U)
1886/*! ERQ14 - Enable DMA Request 14
1887 * 0b0..The DMA request signal for the corresponding channel is disabled
1888 * 0b1..The DMA request signal for the corresponding channel is enabled
1889 */
1890#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
1891#define DMA_ERQ_ERQ15_MASK (0x8000U)
1892#define DMA_ERQ_ERQ15_SHIFT (15U)
1893/*! ERQ15 - Enable DMA Request 15
1894 * 0b0..The DMA request signal for the corresponding channel is disabled
1895 * 0b1..The DMA request signal for the corresponding channel is enabled
1896 */
1897#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
1898/*! @} */
1899
1900/*! @name EEI - Enable Error Interrupt Register */
1901/*! @{ */
1902#define DMA_EEI_EEI0_MASK (0x1U)
1903#define DMA_EEI_EEI0_SHIFT (0U)
1904/*! EEI0 - Enable Error Interrupt 0
1905 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1906 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1907 */
1908#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
1909#define DMA_EEI_EEI1_MASK (0x2U)
1910#define DMA_EEI_EEI1_SHIFT (1U)
1911/*! EEI1 - Enable Error Interrupt 1
1912 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1913 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1914 */
1915#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
1916#define DMA_EEI_EEI2_MASK (0x4U)
1917#define DMA_EEI_EEI2_SHIFT (2U)
1918/*! EEI2 - Enable Error Interrupt 2
1919 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1920 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1921 */
1922#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
1923#define DMA_EEI_EEI3_MASK (0x8U)
1924#define DMA_EEI_EEI3_SHIFT (3U)
1925/*! EEI3 - Enable Error Interrupt 3
1926 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1927 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1928 */
1929#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
1930#define DMA_EEI_EEI4_MASK (0x10U)
1931#define DMA_EEI_EEI4_SHIFT (4U)
1932/*! EEI4 - Enable Error Interrupt 4
1933 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1934 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1935 */
1936#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
1937#define DMA_EEI_EEI5_MASK (0x20U)
1938#define DMA_EEI_EEI5_SHIFT (5U)
1939/*! EEI5 - Enable Error Interrupt 5
1940 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1941 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1942 */
1943#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
1944#define DMA_EEI_EEI6_MASK (0x40U)
1945#define DMA_EEI_EEI6_SHIFT (6U)
1946/*! EEI6 - Enable Error Interrupt 6
1947 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1948 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1949 */
1950#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
1951#define DMA_EEI_EEI7_MASK (0x80U)
1952#define DMA_EEI_EEI7_SHIFT (7U)
1953/*! EEI7 - Enable Error Interrupt 7
1954 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1955 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1956 */
1957#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
1958#define DMA_EEI_EEI8_MASK (0x100U)
1959#define DMA_EEI_EEI8_SHIFT (8U)
1960/*! EEI8 - Enable Error Interrupt 8
1961 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1962 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1963 */
1964#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
1965#define DMA_EEI_EEI9_MASK (0x200U)
1966#define DMA_EEI_EEI9_SHIFT (9U)
1967/*! EEI9 - Enable Error Interrupt 9
1968 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1969 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1970 */
1971#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
1972#define DMA_EEI_EEI10_MASK (0x400U)
1973#define DMA_EEI_EEI10_SHIFT (10U)
1974/*! EEI10 - Enable Error Interrupt 10
1975 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1976 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1977 */
1978#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
1979#define DMA_EEI_EEI11_MASK (0x800U)
1980#define DMA_EEI_EEI11_SHIFT (11U)
1981/*! EEI11 - Enable Error Interrupt 11
1982 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1983 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1984 */
1985#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
1986#define DMA_EEI_EEI12_MASK (0x1000U)
1987#define DMA_EEI_EEI12_SHIFT (12U)
1988/*! EEI12 - Enable Error Interrupt 12
1989 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1990 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1991 */
1992#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
1993#define DMA_EEI_EEI13_MASK (0x2000U)
1994#define DMA_EEI_EEI13_SHIFT (13U)
1995/*! EEI13 - Enable Error Interrupt 13
1996 * 0b0..The error signal for corresponding channel does not generate an error interrupt
1997 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
1998 */
1999#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
2000#define DMA_EEI_EEI14_MASK (0x4000U)
2001#define DMA_EEI_EEI14_SHIFT (14U)
2002/*! EEI14 - Enable Error Interrupt 14
2003 * 0b0..The error signal for corresponding channel does not generate an error interrupt
2004 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2005 */
2006#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
2007#define DMA_EEI_EEI15_MASK (0x8000U)
2008#define DMA_EEI_EEI15_SHIFT (15U)
2009/*! EEI15 - Enable Error Interrupt 15
2010 * 0b0..The error signal for corresponding channel does not generate an error interrupt
2011 * 0b1..The assertion of the error signal for corresponding channel generates an error interrupt request
2012 */
2013#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
2014/*! @} */
2015
2016/*! @name CEEI - Clear Enable Error Interrupt Register */
2017/*! @{ */
2018#define DMA_CEEI_CEEI_MASK (0xFU)
2019#define DMA_CEEI_CEEI_SHIFT (0U)
2020#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
2021#define DMA_CEEI_CAEE_MASK (0x40U)
2022#define DMA_CEEI_CAEE_SHIFT (6U)
2023/*! CAEE - Clear All Enable Error Interrupts
2024 * 0b0..Clear only the EEI bit specified in the CEEI field
2025 * 0b1..Clear all bits in EEI
2026 */
2027#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
2028#define DMA_CEEI_NOP_MASK (0x80U)
2029#define DMA_CEEI_NOP_SHIFT (7U)
2030/*! NOP - No Op enable
2031 * 0b0..Normal operation
2032 * 0b1..No operation, ignore the other bits in this register
2033 */
2034#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
2035/*! @} */
2036
2037/*! @name SEEI - Set Enable Error Interrupt Register */
2038/*! @{ */
2039#define DMA_SEEI_SEEI_MASK (0xFU)
2040#define DMA_SEEI_SEEI_SHIFT (0U)
2041#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
2042#define DMA_SEEI_SAEE_MASK (0x40U)
2043#define DMA_SEEI_SAEE_SHIFT (6U)
2044/*! SAEE - Sets All Enable Error Interrupts
2045 * 0b0..Set only the EEI bit specified in the SEEI field.
2046 * 0b1..Sets all bits in EEI
2047 */
2048#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
2049#define DMA_SEEI_NOP_MASK (0x80U)
2050#define DMA_SEEI_NOP_SHIFT (7U)
2051/*! NOP - No Op enable
2052 * 0b0..Normal operation
2053 * 0b1..No operation, ignore the other bits in this register
2054 */
2055#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
2056/*! @} */
2057
2058/*! @name CERQ - Clear Enable Request Register */
2059/*! @{ */
2060#define DMA_CERQ_CERQ_MASK (0xFU)
2061#define DMA_CERQ_CERQ_SHIFT (0U)
2062#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
2063#define DMA_CERQ_CAER_MASK (0x40U)
2064#define DMA_CERQ_CAER_SHIFT (6U)
2065/*! CAER - Clear All Enable Requests
2066 * 0b0..Clear only the ERQ bit specified in the CERQ field
2067 * 0b1..Clear all bits in ERQ
2068 */
2069#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
2070#define DMA_CERQ_NOP_MASK (0x80U)
2071#define DMA_CERQ_NOP_SHIFT (7U)
2072/*! NOP - No Op enable
2073 * 0b0..Normal operation
2074 * 0b1..No operation, ignore the other bits in this register
2075 */
2076#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
2077/*! @} */
2078
2079/*! @name SERQ - Set Enable Request Register */
2080/*! @{ */
2081#define DMA_SERQ_SERQ_MASK (0xFU)
2082#define DMA_SERQ_SERQ_SHIFT (0U)
2083#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
2084#define DMA_SERQ_SAER_MASK (0x40U)
2085#define DMA_SERQ_SAER_SHIFT (6U)
2086/*! SAER - Set All Enable Requests
2087 * 0b0..Set only the ERQ bit specified in the SERQ field
2088 * 0b1..Set all bits in ERQ
2089 */
2090#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
2091#define DMA_SERQ_NOP_MASK (0x80U)
2092#define DMA_SERQ_NOP_SHIFT (7U)
2093/*! NOP - No Op enable
2094 * 0b0..Normal operation
2095 * 0b1..No operation, ignore the other bits in this register
2096 */
2097#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
2098/*! @} */
2099
2100/*! @name CDNE - Clear DONE Status Bit Register */
2101/*! @{ */
2102#define DMA_CDNE_CDNE_MASK (0xFU)
2103#define DMA_CDNE_CDNE_SHIFT (0U)
2104#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
2105#define DMA_CDNE_CADN_MASK (0x40U)
2106#define DMA_CDNE_CADN_SHIFT (6U)
2107/*! CADN - Clears All DONE Bits
2108 * 0b0..Clears only the TCDn_CSR[DONE] bit specified in the CDNE field
2109 * 0b1..Clears all bits in TCDn_CSR[DONE]
2110 */
2111#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
2112#define DMA_CDNE_NOP_MASK (0x80U)
2113#define DMA_CDNE_NOP_SHIFT (7U)
2114/*! NOP - No Op enable
2115 * 0b0..Normal operation
2116 * 0b1..No operation, ignore the other bits in this register
2117 */
2118#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
2119/*! @} */
2120
2121/*! @name SSRT - Set START Bit Register */
2122/*! @{ */
2123#define DMA_SSRT_SSRT_MASK (0xFU)
2124#define DMA_SSRT_SSRT_SHIFT (0U)
2125#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
2126#define DMA_SSRT_SAST_MASK (0x40U)
2127#define DMA_SSRT_SAST_SHIFT (6U)
2128/*! SAST - Set All START Bits (activates all channels)
2129 * 0b0..Set only the TCDn_CSR[START] bit specified in the SSRT field
2130 * 0b1..Set all bits in TCDn_CSR[START]
2131 */
2132#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
2133#define DMA_SSRT_NOP_MASK (0x80U)
2134#define DMA_SSRT_NOP_SHIFT (7U)
2135/*! NOP - No Op enable
2136 * 0b0..Normal operation
2137 * 0b1..No operation, ignore the other bits in this register
2138 */
2139#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
2140/*! @} */
2141
2142/*! @name CERR - Clear Error Register */
2143/*! @{ */
2144#define DMA_CERR_CERR_MASK (0xFU)
2145#define DMA_CERR_CERR_SHIFT (0U)
2146#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
2147#define DMA_CERR_CAEI_MASK (0x40U)
2148#define DMA_CERR_CAEI_SHIFT (6U)
2149/*! CAEI - Clear All Error Indicators
2150 * 0b0..Clear only the ERR bit specified in the CERR field
2151 * 0b1..Clear all bits in ERR
2152 */
2153#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
2154#define DMA_CERR_NOP_MASK (0x80U)
2155#define DMA_CERR_NOP_SHIFT (7U)
2156/*! NOP - No Op enable
2157 * 0b0..Normal operation
2158 * 0b1..No operation, ignore the other bits in this register
2159 */
2160#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
2161/*! @} */
2162
2163/*! @name CINT - Clear Interrupt Request Register */
2164/*! @{ */
2165#define DMA_CINT_CINT_MASK (0xFU)
2166#define DMA_CINT_CINT_SHIFT (0U)
2167#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
2168#define DMA_CINT_CAIR_MASK (0x40U)
2169#define DMA_CINT_CAIR_SHIFT (6U)
2170/*! CAIR - Clear All Interrupt Requests
2171 * 0b0..Clear only the INT bit specified in the CINT field
2172 * 0b1..Clear all bits in INT
2173 */
2174#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
2175#define DMA_CINT_NOP_MASK (0x80U)
2176#define DMA_CINT_NOP_SHIFT (7U)
2177/*! NOP - No Op enable
2178 * 0b0..Normal operation
2179 * 0b1..No operation, ignore the other bits in this register
2180 */
2181#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
2182/*! @} */
2183
2184/*! @name INT - Interrupt Request Register */
2185/*! @{ */
2186#define DMA_INT_INT0_MASK (0x1U)
2187#define DMA_INT_INT0_SHIFT (0U)
2188/*! INT0 - Interrupt Request 0
2189 * 0b0..The interrupt request for corresponding channel is cleared
2190 * 0b1..The interrupt request for corresponding channel is active
2191 */
2192#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
2193#define DMA_INT_INT1_MASK (0x2U)
2194#define DMA_INT_INT1_SHIFT (1U)
2195/*! INT1 - Interrupt Request 1
2196 * 0b0..The interrupt request for corresponding channel is cleared
2197 * 0b1..The interrupt request for corresponding channel is active
2198 */
2199#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
2200#define DMA_INT_INT2_MASK (0x4U)
2201#define DMA_INT_INT2_SHIFT (2U)
2202/*! INT2 - Interrupt Request 2
2203 * 0b0..The interrupt request for corresponding channel is cleared
2204 * 0b1..The interrupt request for corresponding channel is active
2205 */
2206#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
2207#define DMA_INT_INT3_MASK (0x8U)
2208#define DMA_INT_INT3_SHIFT (3U)
2209/*! INT3 - Interrupt Request 3
2210 * 0b0..The interrupt request for corresponding channel is cleared
2211 * 0b1..The interrupt request for corresponding channel is active
2212 */
2213#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
2214#define DMA_INT_INT4_MASK (0x10U)
2215#define DMA_INT_INT4_SHIFT (4U)
2216/*! INT4 - Interrupt Request 4
2217 * 0b0..The interrupt request for corresponding channel is cleared
2218 * 0b1..The interrupt request for corresponding channel is active
2219 */
2220#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
2221#define DMA_INT_INT5_MASK (0x20U)
2222#define DMA_INT_INT5_SHIFT (5U)
2223/*! INT5 - Interrupt Request 5
2224 * 0b0..The interrupt request for corresponding channel is cleared
2225 * 0b1..The interrupt request for corresponding channel is active
2226 */
2227#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
2228#define DMA_INT_INT6_MASK (0x40U)
2229#define DMA_INT_INT6_SHIFT (6U)
2230/*! INT6 - Interrupt Request 6
2231 * 0b0..The interrupt request for corresponding channel is cleared
2232 * 0b1..The interrupt request for corresponding channel is active
2233 */
2234#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
2235#define DMA_INT_INT7_MASK (0x80U)
2236#define DMA_INT_INT7_SHIFT (7U)
2237/*! INT7 - Interrupt Request 7
2238 * 0b0..The interrupt request for corresponding channel is cleared
2239 * 0b1..The interrupt request for corresponding channel is active
2240 */
2241#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
2242#define DMA_INT_INT8_MASK (0x100U)
2243#define DMA_INT_INT8_SHIFT (8U)
2244/*! INT8 - Interrupt Request 8
2245 * 0b0..The interrupt request for corresponding channel is cleared
2246 * 0b1..The interrupt request for corresponding channel is active
2247 */
2248#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
2249#define DMA_INT_INT9_MASK (0x200U)
2250#define DMA_INT_INT9_SHIFT (9U)
2251/*! INT9 - Interrupt Request 9
2252 * 0b0..The interrupt request for corresponding channel is cleared
2253 * 0b1..The interrupt request for corresponding channel is active
2254 */
2255#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
2256#define DMA_INT_INT10_MASK (0x400U)
2257#define DMA_INT_INT10_SHIFT (10U)
2258/*! INT10 - Interrupt Request 10
2259 * 0b0..The interrupt request for corresponding channel is cleared
2260 * 0b1..The interrupt request for corresponding channel is active
2261 */
2262#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
2263#define DMA_INT_INT11_MASK (0x800U)
2264#define DMA_INT_INT11_SHIFT (11U)
2265/*! INT11 - Interrupt Request 11
2266 * 0b0..The interrupt request for corresponding channel is cleared
2267 * 0b1..The interrupt request for corresponding channel is active
2268 */
2269#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
2270#define DMA_INT_INT12_MASK (0x1000U)
2271#define DMA_INT_INT12_SHIFT (12U)
2272/*! INT12 - Interrupt Request 12
2273 * 0b0..The interrupt request for corresponding channel is cleared
2274 * 0b1..The interrupt request for corresponding channel is active
2275 */
2276#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
2277#define DMA_INT_INT13_MASK (0x2000U)
2278#define DMA_INT_INT13_SHIFT (13U)
2279/*! INT13 - Interrupt Request 13
2280 * 0b0..The interrupt request for corresponding channel is cleared
2281 * 0b1..The interrupt request for corresponding channel is active
2282 */
2283#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
2284#define DMA_INT_INT14_MASK (0x4000U)
2285#define DMA_INT_INT14_SHIFT (14U)
2286/*! INT14 - Interrupt Request 14
2287 * 0b0..The interrupt request for corresponding channel is cleared
2288 * 0b1..The interrupt request for corresponding channel is active
2289 */
2290#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
2291#define DMA_INT_INT15_MASK (0x8000U)
2292#define DMA_INT_INT15_SHIFT (15U)
2293/*! INT15 - Interrupt Request 15
2294 * 0b0..The interrupt request for corresponding channel is cleared
2295 * 0b1..The interrupt request for corresponding channel is active
2296 */
2297#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
2298/*! @} */
2299
2300/*! @name ERR - Error Register */
2301/*! @{ */
2302#define DMA_ERR_ERR0_MASK (0x1U)
2303#define DMA_ERR_ERR0_SHIFT (0U)
2304/*! ERR0 - Error In Channel 0
2305 * 0b0..An error in the corresponding channel has not occurred
2306 * 0b1..An error in the corresponding channel has occurred
2307 */
2308#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
2309#define DMA_ERR_ERR1_MASK (0x2U)
2310#define DMA_ERR_ERR1_SHIFT (1U)
2311/*! ERR1 - Error In Channel 1
2312 * 0b0..An error in the corresponding channel has not occurred
2313 * 0b1..An error in the corresponding channel has occurred
2314 */
2315#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
2316#define DMA_ERR_ERR2_MASK (0x4U)
2317#define DMA_ERR_ERR2_SHIFT (2U)
2318/*! ERR2 - Error In Channel 2
2319 * 0b0..An error in the corresponding channel has not occurred
2320 * 0b1..An error in the corresponding channel has occurred
2321 */
2322#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
2323#define DMA_ERR_ERR3_MASK (0x8U)
2324#define DMA_ERR_ERR3_SHIFT (3U)
2325/*! ERR3 - Error In Channel 3
2326 * 0b0..An error in the corresponding channel has not occurred
2327 * 0b1..An error in the corresponding channel has occurred
2328 */
2329#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
2330#define DMA_ERR_ERR4_MASK (0x10U)
2331#define DMA_ERR_ERR4_SHIFT (4U)
2332/*! ERR4 - Error In Channel 4
2333 * 0b0..An error in the corresponding channel has not occurred
2334 * 0b1..An error in the corresponding channel has occurred
2335 */
2336#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
2337#define DMA_ERR_ERR5_MASK (0x20U)
2338#define DMA_ERR_ERR5_SHIFT (5U)
2339/*! ERR5 - Error In Channel 5
2340 * 0b0..An error in the corresponding channel has not occurred
2341 * 0b1..An error in the corresponding channel has occurred
2342 */
2343#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
2344#define DMA_ERR_ERR6_MASK (0x40U)
2345#define DMA_ERR_ERR6_SHIFT (6U)
2346/*! ERR6 - Error In Channel 6
2347 * 0b0..An error in the corresponding channel has not occurred
2348 * 0b1..An error in the corresponding channel has occurred
2349 */
2350#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
2351#define DMA_ERR_ERR7_MASK (0x80U)
2352#define DMA_ERR_ERR7_SHIFT (7U)
2353/*! ERR7 - Error In Channel 7
2354 * 0b0..An error in the corresponding channel has not occurred
2355 * 0b1..An error in the corresponding channel has occurred
2356 */
2357#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
2358#define DMA_ERR_ERR8_MASK (0x100U)
2359#define DMA_ERR_ERR8_SHIFT (8U)
2360/*! ERR8 - Error In Channel 8
2361 * 0b0..An error in the corresponding channel has not occurred
2362 * 0b1..An error in the corresponding channel has occurred
2363 */
2364#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
2365#define DMA_ERR_ERR9_MASK (0x200U)
2366#define DMA_ERR_ERR9_SHIFT (9U)
2367/*! ERR9 - Error In Channel 9
2368 * 0b0..An error in the corresponding channel has not occurred
2369 * 0b1..An error in the corresponding channel has occurred
2370 */
2371#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
2372#define DMA_ERR_ERR10_MASK (0x400U)
2373#define DMA_ERR_ERR10_SHIFT (10U)
2374/*! ERR10 - Error In Channel 10
2375 * 0b0..An error in the corresponding channel has not occurred
2376 * 0b1..An error in the corresponding channel has occurred
2377 */
2378#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
2379#define DMA_ERR_ERR11_MASK (0x800U)
2380#define DMA_ERR_ERR11_SHIFT (11U)
2381/*! ERR11 - Error In Channel 11
2382 * 0b0..An error in the corresponding channel has not occurred
2383 * 0b1..An error in the corresponding channel has occurred
2384 */
2385#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
2386#define DMA_ERR_ERR12_MASK (0x1000U)
2387#define DMA_ERR_ERR12_SHIFT (12U)
2388/*! ERR12 - Error In Channel 12
2389 * 0b0..An error in the corresponding channel has not occurred
2390 * 0b1..An error in the corresponding channel has occurred
2391 */
2392#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
2393#define DMA_ERR_ERR13_MASK (0x2000U)
2394#define DMA_ERR_ERR13_SHIFT (13U)
2395/*! ERR13 - Error In Channel 13
2396 * 0b0..An error in the corresponding channel has not occurred
2397 * 0b1..An error in the corresponding channel has occurred
2398 */
2399#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
2400#define DMA_ERR_ERR14_MASK (0x4000U)
2401#define DMA_ERR_ERR14_SHIFT (14U)
2402/*! ERR14 - Error In Channel 14
2403 * 0b0..An error in the corresponding channel has not occurred
2404 * 0b1..An error in the corresponding channel has occurred
2405 */
2406#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
2407#define DMA_ERR_ERR15_MASK (0x8000U)
2408#define DMA_ERR_ERR15_SHIFT (15U)
2409/*! ERR15 - Error In Channel 15
2410 * 0b0..An error in the corresponding channel has not occurred
2411 * 0b1..An error in the corresponding channel has occurred
2412 */
2413#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
2414/*! @} */
2415
2416/*! @name HRS - Hardware Request Status Register */
2417/*! @{ */
2418#define DMA_HRS_HRS0_MASK (0x1U)
2419#define DMA_HRS_HRS0_SHIFT (0U)
2420/*! HRS0 - Hardware Request Status Channel 0
2421 * 0b0..A hardware service request for channel 0 is not present
2422 * 0b1..A hardware service request for channel 0 is present
2423 */
2424#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
2425#define DMA_HRS_HRS1_MASK (0x2U)
2426#define DMA_HRS_HRS1_SHIFT (1U)
2427/*! HRS1 - Hardware Request Status Channel 1
2428 * 0b0..A hardware service request for channel 1 is not present
2429 * 0b1..A hardware service request for channel 1 is present
2430 */
2431#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
2432#define DMA_HRS_HRS2_MASK (0x4U)
2433#define DMA_HRS_HRS2_SHIFT (2U)
2434/*! HRS2 - Hardware Request Status Channel 2
2435 * 0b0..A hardware service request for channel 2 is not present
2436 * 0b1..A hardware service request for channel 2 is present
2437 */
2438#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
2439#define DMA_HRS_HRS3_MASK (0x8U)
2440#define DMA_HRS_HRS3_SHIFT (3U)
2441/*! HRS3 - Hardware Request Status Channel 3
2442 * 0b0..A hardware service request for channel 3 is not present
2443 * 0b1..A hardware service request for channel 3 is present
2444 */
2445#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
2446#define DMA_HRS_HRS4_MASK (0x10U)
2447#define DMA_HRS_HRS4_SHIFT (4U)
2448/*! HRS4 - Hardware Request Status Channel 4
2449 * 0b0..A hardware service request for channel 4 is not present
2450 * 0b1..A hardware service request for channel 4 is present
2451 */
2452#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
2453#define DMA_HRS_HRS5_MASK (0x20U)
2454#define DMA_HRS_HRS5_SHIFT (5U)
2455/*! HRS5 - Hardware Request Status Channel 5
2456 * 0b0..A hardware service request for channel 5 is not present
2457 * 0b1..A hardware service request for channel 5 is present
2458 */
2459#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
2460#define DMA_HRS_HRS6_MASK (0x40U)
2461#define DMA_HRS_HRS6_SHIFT (6U)
2462/*! HRS6 - Hardware Request Status Channel 6
2463 * 0b0..A hardware service request for channel 6 is not present
2464 * 0b1..A hardware service request for channel 6 is present
2465 */
2466#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
2467#define DMA_HRS_HRS7_MASK (0x80U)
2468#define DMA_HRS_HRS7_SHIFT (7U)
2469/*! HRS7 - Hardware Request Status Channel 7
2470 * 0b0..A hardware service request for channel 7 is not present
2471 * 0b1..A hardware service request for channel 7 is present
2472 */
2473#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
2474#define DMA_HRS_HRS8_MASK (0x100U)
2475#define DMA_HRS_HRS8_SHIFT (8U)
2476/*! HRS8 - Hardware Request Status Channel 8
2477 * 0b0..A hardware service request for channel 8 is not present
2478 * 0b1..A hardware service request for channel 8 is present
2479 */
2480#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
2481#define DMA_HRS_HRS9_MASK (0x200U)
2482#define DMA_HRS_HRS9_SHIFT (9U)
2483/*! HRS9 - Hardware Request Status Channel 9
2484 * 0b0..A hardware service request for channel 9 is not present
2485 * 0b1..A hardware service request for channel 9 is present
2486 */
2487#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
2488#define DMA_HRS_HRS10_MASK (0x400U)
2489#define DMA_HRS_HRS10_SHIFT (10U)
2490/*! HRS10 - Hardware Request Status Channel 10
2491 * 0b0..A hardware service request for channel 10 is not present
2492 * 0b1..A hardware service request for channel 10 is present
2493 */
2494#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
2495#define DMA_HRS_HRS11_MASK (0x800U)
2496#define DMA_HRS_HRS11_SHIFT (11U)
2497/*! HRS11 - Hardware Request Status Channel 11
2498 * 0b0..A hardware service request for channel 11 is not present
2499 * 0b1..A hardware service request for channel 11 is present
2500 */
2501#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
2502#define DMA_HRS_HRS12_MASK (0x1000U)
2503#define DMA_HRS_HRS12_SHIFT (12U)
2504/*! HRS12 - Hardware Request Status Channel 12
2505 * 0b0..A hardware service request for channel 12 is not present
2506 * 0b1..A hardware service request for channel 12 is present
2507 */
2508#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
2509#define DMA_HRS_HRS13_MASK (0x2000U)
2510#define DMA_HRS_HRS13_SHIFT (13U)
2511/*! HRS13 - Hardware Request Status Channel 13
2512 * 0b0..A hardware service request for channel 13 is not present
2513 * 0b1..A hardware service request for channel 13 is present
2514 */
2515#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
2516#define DMA_HRS_HRS14_MASK (0x4000U)
2517#define DMA_HRS_HRS14_SHIFT (14U)
2518/*! HRS14 - Hardware Request Status Channel 14
2519 * 0b0..A hardware service request for channel 14 is not present
2520 * 0b1..A hardware service request for channel 14 is present
2521 */
2522#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
2523#define DMA_HRS_HRS15_MASK (0x8000U)
2524#define DMA_HRS_HRS15_SHIFT (15U)
2525/*! HRS15 - Hardware Request Status Channel 15
2526 * 0b0..A hardware service request for channel 15 is not present
2527 * 0b1..A hardware service request for channel 15 is present
2528 */
2529#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
2530/*! @} */
2531
2532/*! @name EARS - Enable Asynchronous Request in Stop Register */
2533/*! @{ */
2534#define DMA_EARS_EDREQ_0_MASK (0x1U)
2535#define DMA_EARS_EDREQ_0_SHIFT (0U)
2536/*! EDREQ_0 - Enable asynchronous DMA request in stop for channel 0.
2537 * 0b0..Disable asynchronous DMA request for channel 0.
2538 * 0b1..Enable asynchronous DMA request for channel 0.
2539 */
2540#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
2541#define DMA_EARS_EDREQ_1_MASK (0x2U)
2542#define DMA_EARS_EDREQ_1_SHIFT (1U)
2543/*! EDREQ_1 - Enable asynchronous DMA request in stop for channel 1.
2544 * 0b0..Disable asynchronous DMA request for channel 1
2545 * 0b1..Enable asynchronous DMA request for channel 1.
2546 */
2547#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
2548#define DMA_EARS_EDREQ_2_MASK (0x4U)
2549#define DMA_EARS_EDREQ_2_SHIFT (2U)
2550/*! EDREQ_2 - Enable asynchronous DMA request in stop for channel 2.
2551 * 0b0..Disable asynchronous DMA request for channel 2.
2552 * 0b1..Enable asynchronous DMA request for channel 2.
2553 */
2554#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
2555#define DMA_EARS_EDREQ_3_MASK (0x8U)
2556#define DMA_EARS_EDREQ_3_SHIFT (3U)
2557/*! EDREQ_3 - Enable asynchronous DMA request in stop for channel 3.
2558 * 0b0..Disable asynchronous DMA request for channel 3.
2559 * 0b1..Enable asynchronous DMA request for channel 3.
2560 */
2561#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
2562#define DMA_EARS_EDREQ_4_MASK (0x10U)
2563#define DMA_EARS_EDREQ_4_SHIFT (4U)
2564/*! EDREQ_4 - Enable asynchronous DMA request in stop for channel 4
2565 * 0b0..Disable asynchronous DMA request for channel 4.
2566 * 0b1..Enable asynchronous DMA request for channel 4.
2567 */
2568#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
2569#define DMA_EARS_EDREQ_5_MASK (0x20U)
2570#define DMA_EARS_EDREQ_5_SHIFT (5U)
2571/*! EDREQ_5 - Enable asynchronous DMA request in stop for channel 5
2572 * 0b0..Disable asynchronous DMA request for channel 5.
2573 * 0b1..Enable asynchronous DMA request for channel 5.
2574 */
2575#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
2576#define DMA_EARS_EDREQ_6_MASK (0x40U)
2577#define DMA_EARS_EDREQ_6_SHIFT (6U)
2578/*! EDREQ_6 - Enable asynchronous DMA request in stop for channel 6
2579 * 0b0..Disable asynchronous DMA request for channel 6.
2580 * 0b1..Enable asynchronous DMA request for channel 6.
2581 */
2582#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
2583#define DMA_EARS_EDREQ_7_MASK (0x80U)
2584#define DMA_EARS_EDREQ_7_SHIFT (7U)
2585/*! EDREQ_7 - Enable asynchronous DMA request in stop for channel 7
2586 * 0b0..Disable asynchronous DMA request for channel 7.
2587 * 0b1..Enable asynchronous DMA request for channel 7.
2588 */
2589#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
2590#define DMA_EARS_EDREQ_8_MASK (0x100U)
2591#define DMA_EARS_EDREQ_8_SHIFT (8U)
2592/*! EDREQ_8 - Enable asynchronous DMA request in stop for channel 8
2593 * 0b0..Disable asynchronous DMA request for channel 8.
2594 * 0b1..Enable asynchronous DMA request for channel 8.
2595 */
2596#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
2597#define DMA_EARS_EDREQ_9_MASK (0x200U)
2598#define DMA_EARS_EDREQ_9_SHIFT (9U)
2599/*! EDREQ_9 - Enable asynchronous DMA request in stop for channel 9
2600 * 0b0..Disable asynchronous DMA request for channel 9.
2601 * 0b1..Enable asynchronous DMA request for channel 9.
2602 */
2603#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
2604#define DMA_EARS_EDREQ_10_MASK (0x400U)
2605#define DMA_EARS_EDREQ_10_SHIFT (10U)
2606/*! EDREQ_10 - Enable asynchronous DMA request in stop for channel 10
2607 * 0b0..Disable asynchronous DMA request for channel 10.
2608 * 0b1..Enable asynchronous DMA request for channel 10.
2609 */
2610#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
2611#define DMA_EARS_EDREQ_11_MASK (0x800U)
2612#define DMA_EARS_EDREQ_11_SHIFT (11U)
2613/*! EDREQ_11 - Enable asynchronous DMA request in stop for channel 11
2614 * 0b0..Disable asynchronous DMA request for channel 11.
2615 * 0b1..Enable asynchronous DMA request for channel 11.
2616 */
2617#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
2618#define DMA_EARS_EDREQ_12_MASK (0x1000U)
2619#define DMA_EARS_EDREQ_12_SHIFT (12U)
2620/*! EDREQ_12 - Enable asynchronous DMA request in stop for channel 12
2621 * 0b0..Disable asynchronous DMA request for channel 12.
2622 * 0b1..Enable asynchronous DMA request for channel 12.
2623 */
2624#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
2625#define DMA_EARS_EDREQ_13_MASK (0x2000U)
2626#define DMA_EARS_EDREQ_13_SHIFT (13U)
2627/*! EDREQ_13 - Enable asynchronous DMA request in stop for channel 13
2628 * 0b0..Disable asynchronous DMA request for channel 13.
2629 * 0b1..Enable asynchronous DMA request for channel 13.
2630 */
2631#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
2632#define DMA_EARS_EDREQ_14_MASK (0x4000U)
2633#define DMA_EARS_EDREQ_14_SHIFT (14U)
2634/*! EDREQ_14 - Enable asynchronous DMA request in stop for channel 14
2635 * 0b0..Disable asynchronous DMA request for channel 14.
2636 * 0b1..Enable asynchronous DMA request for channel 14.
2637 */
2638#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
2639#define DMA_EARS_EDREQ_15_MASK (0x8000U)
2640#define DMA_EARS_EDREQ_15_SHIFT (15U)
2641/*! EDREQ_15 - Enable asynchronous DMA request in stop for channel 15
2642 * 0b0..Disable asynchronous DMA request for channel 15.
2643 * 0b1..Enable asynchronous DMA request for channel 15.
2644 */
2645#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
2646/*! @} */
2647
2648/*! @name DCHPRI3 - Channel n Priority Register */
2649/*! @{ */
2650#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
2651#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
2652#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
2653#define DMA_DCHPRI3_DPA_MASK (0x40U)
2654#define DMA_DCHPRI3_DPA_SHIFT (6U)
2655/*! DPA - Disable Preempt Ability
2656 * 0b0..Channel n can suspend a lower priority channel
2657 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2658 */
2659#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
2660#define DMA_DCHPRI3_ECP_MASK (0x80U)
2661#define DMA_DCHPRI3_ECP_SHIFT (7U)
2662/*! ECP - Enable Channel Preemption
2663 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2664 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2665 */
2666#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
2667/*! @} */
2668
2669/*! @name DCHPRI2 - Channel n Priority Register */
2670/*! @{ */
2671#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
2672#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
2673#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
2674#define DMA_DCHPRI2_DPA_MASK (0x40U)
2675#define DMA_DCHPRI2_DPA_SHIFT (6U)
2676/*! DPA - Disable Preempt Ability
2677 * 0b0..Channel n can suspend a lower priority channel
2678 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2679 */
2680#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
2681#define DMA_DCHPRI2_ECP_MASK (0x80U)
2682#define DMA_DCHPRI2_ECP_SHIFT (7U)
2683/*! ECP - Enable Channel Preemption
2684 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2685 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2686 */
2687#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
2688/*! @} */
2689
2690/*! @name DCHPRI1 - Channel n Priority Register */
2691/*! @{ */
2692#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
2693#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
2694#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
2695#define DMA_DCHPRI1_DPA_MASK (0x40U)
2696#define DMA_DCHPRI1_DPA_SHIFT (6U)
2697/*! DPA - Disable Preempt Ability
2698 * 0b0..Channel n can suspend a lower priority channel
2699 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2700 */
2701#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
2702#define DMA_DCHPRI1_ECP_MASK (0x80U)
2703#define DMA_DCHPRI1_ECP_SHIFT (7U)
2704/*! ECP - Enable Channel Preemption
2705 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2706 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2707 */
2708#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
2709/*! @} */
2710
2711/*! @name DCHPRI0 - Channel n Priority Register */
2712/*! @{ */
2713#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
2714#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
2715#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
2716#define DMA_DCHPRI0_DPA_MASK (0x40U)
2717#define DMA_DCHPRI0_DPA_SHIFT (6U)
2718/*! DPA - Disable Preempt Ability
2719 * 0b0..Channel n can suspend a lower priority channel
2720 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2721 */
2722#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
2723#define DMA_DCHPRI0_ECP_MASK (0x80U)
2724#define DMA_DCHPRI0_ECP_SHIFT (7U)
2725/*! ECP - Enable Channel Preemption
2726 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2727 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2728 */
2729#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
2730/*! @} */
2731
2732/*! @name DCHPRI7 - Channel n Priority Register */
2733/*! @{ */
2734#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
2735#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
2736#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
2737#define DMA_DCHPRI7_DPA_MASK (0x40U)
2738#define DMA_DCHPRI7_DPA_SHIFT (6U)
2739/*! DPA - Disable Preempt Ability
2740 * 0b0..Channel n can suspend a lower priority channel
2741 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2742 */
2743#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
2744#define DMA_DCHPRI7_ECP_MASK (0x80U)
2745#define DMA_DCHPRI7_ECP_SHIFT (7U)
2746/*! ECP - Enable Channel Preemption
2747 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2748 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2749 */
2750#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
2751/*! @} */
2752
2753/*! @name DCHPRI6 - Channel n Priority Register */
2754/*! @{ */
2755#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
2756#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
2757#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
2758#define DMA_DCHPRI6_DPA_MASK (0x40U)
2759#define DMA_DCHPRI6_DPA_SHIFT (6U)
2760/*! DPA - Disable Preempt Ability
2761 * 0b0..Channel n can suspend a lower priority channel
2762 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2763 */
2764#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
2765#define DMA_DCHPRI6_ECP_MASK (0x80U)
2766#define DMA_DCHPRI6_ECP_SHIFT (7U)
2767/*! ECP - Enable Channel Preemption
2768 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2769 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2770 */
2771#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
2772/*! @} */
2773
2774/*! @name DCHPRI5 - Channel n Priority Register */
2775/*! @{ */
2776#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
2777#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
2778#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
2779#define DMA_DCHPRI5_DPA_MASK (0x40U)
2780#define DMA_DCHPRI5_DPA_SHIFT (6U)
2781/*! DPA - Disable Preempt Ability
2782 * 0b0..Channel n can suspend a lower priority channel
2783 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2784 */
2785#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
2786#define DMA_DCHPRI5_ECP_MASK (0x80U)
2787#define DMA_DCHPRI5_ECP_SHIFT (7U)
2788/*! ECP - Enable Channel Preemption
2789 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2790 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2791 */
2792#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
2793/*! @} */
2794
2795/*! @name DCHPRI4 - Channel n Priority Register */
2796/*! @{ */
2797#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
2798#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
2799#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
2800#define DMA_DCHPRI4_DPA_MASK (0x40U)
2801#define DMA_DCHPRI4_DPA_SHIFT (6U)
2802/*! DPA - Disable Preempt Ability
2803 * 0b0..Channel n can suspend a lower priority channel
2804 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2805 */
2806#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
2807#define DMA_DCHPRI4_ECP_MASK (0x80U)
2808#define DMA_DCHPRI4_ECP_SHIFT (7U)
2809/*! ECP - Enable Channel Preemption
2810 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2811 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2812 */
2813#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
2814/*! @} */
2815
2816/*! @name DCHPRI11 - Channel n Priority Register */
2817/*! @{ */
2818#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
2819#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
2820#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
2821#define DMA_DCHPRI11_DPA_MASK (0x40U)
2822#define DMA_DCHPRI11_DPA_SHIFT (6U)
2823/*! DPA - Disable Preempt Ability
2824 * 0b0..Channel n can suspend a lower priority channel
2825 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2826 */
2827#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
2828#define DMA_DCHPRI11_ECP_MASK (0x80U)
2829#define DMA_DCHPRI11_ECP_SHIFT (7U)
2830/*! ECP - Enable Channel Preemption
2831 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2832 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2833 */
2834#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
2835/*! @} */
2836
2837/*! @name DCHPRI10 - Channel n Priority Register */
2838/*! @{ */
2839#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
2840#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
2841#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
2842#define DMA_DCHPRI10_DPA_MASK (0x40U)
2843#define DMA_DCHPRI10_DPA_SHIFT (6U)
2844/*! DPA - Disable Preempt Ability
2845 * 0b0..Channel n can suspend a lower priority channel
2846 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2847 */
2848#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
2849#define DMA_DCHPRI10_ECP_MASK (0x80U)
2850#define DMA_DCHPRI10_ECP_SHIFT (7U)
2851/*! ECP - Enable Channel Preemption
2852 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2853 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2854 */
2855#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
2856/*! @} */
2857
2858/*! @name DCHPRI9 - Channel n Priority Register */
2859/*! @{ */
2860#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
2861#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
2862#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
2863#define DMA_DCHPRI9_DPA_MASK (0x40U)
2864#define DMA_DCHPRI9_DPA_SHIFT (6U)
2865/*! DPA - Disable Preempt Ability
2866 * 0b0..Channel n can suspend a lower priority channel
2867 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2868 */
2869#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
2870#define DMA_DCHPRI9_ECP_MASK (0x80U)
2871#define DMA_DCHPRI9_ECP_SHIFT (7U)
2872/*! ECP - Enable Channel Preemption
2873 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2874 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2875 */
2876#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
2877/*! @} */
2878
2879/*! @name DCHPRI8 - Channel n Priority Register */
2880/*! @{ */
2881#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
2882#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
2883#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
2884#define DMA_DCHPRI8_DPA_MASK (0x40U)
2885#define DMA_DCHPRI8_DPA_SHIFT (6U)
2886/*! DPA - Disable Preempt Ability
2887 * 0b0..Channel n can suspend a lower priority channel
2888 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2889 */
2890#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
2891#define DMA_DCHPRI8_ECP_MASK (0x80U)
2892#define DMA_DCHPRI8_ECP_SHIFT (7U)
2893/*! ECP - Enable Channel Preemption
2894 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2895 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2896 */
2897#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
2898/*! @} */
2899
2900/*! @name DCHPRI15 - Channel n Priority Register */
2901/*! @{ */
2902#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
2903#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
2904#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
2905#define DMA_DCHPRI15_DPA_MASK (0x40U)
2906#define DMA_DCHPRI15_DPA_SHIFT (6U)
2907/*! DPA - Disable Preempt Ability
2908 * 0b0..Channel n can suspend a lower priority channel
2909 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2910 */
2911#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
2912#define DMA_DCHPRI15_ECP_MASK (0x80U)
2913#define DMA_DCHPRI15_ECP_SHIFT (7U)
2914/*! ECP - Enable Channel Preemption
2915 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2916 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2917 */
2918#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
2919/*! @} */
2920
2921/*! @name DCHPRI14 - Channel n Priority Register */
2922/*! @{ */
2923#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
2924#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
2925#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
2926#define DMA_DCHPRI14_DPA_MASK (0x40U)
2927#define DMA_DCHPRI14_DPA_SHIFT (6U)
2928/*! DPA - Disable Preempt Ability
2929 * 0b0..Channel n can suspend a lower priority channel
2930 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2931 */
2932#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
2933#define DMA_DCHPRI14_ECP_MASK (0x80U)
2934#define DMA_DCHPRI14_ECP_SHIFT (7U)
2935/*! ECP - Enable Channel Preemption
2936 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2937 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2938 */
2939#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
2940/*! @} */
2941
2942/*! @name DCHPRI13 - Channel n Priority Register */
2943/*! @{ */
2944#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
2945#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
2946#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
2947#define DMA_DCHPRI13_DPA_MASK (0x40U)
2948#define DMA_DCHPRI13_DPA_SHIFT (6U)
2949/*! DPA - Disable Preempt Ability
2950 * 0b0..Channel n can suspend a lower priority channel
2951 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2952 */
2953#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
2954#define DMA_DCHPRI13_ECP_MASK (0x80U)
2955#define DMA_DCHPRI13_ECP_SHIFT (7U)
2956/*! ECP - Enable Channel Preemption
2957 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2958 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2959 */
2960#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
2961/*! @} */
2962
2963/*! @name DCHPRI12 - Channel n Priority Register */
2964/*! @{ */
2965#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
2966#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
2967#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
2968#define DMA_DCHPRI12_DPA_MASK (0x40U)
2969#define DMA_DCHPRI12_DPA_SHIFT (6U)
2970/*! DPA - Disable Preempt Ability
2971 * 0b0..Channel n can suspend a lower priority channel
2972 * 0b1..Channel n cannot suspend any channel, regardless of channel priority
2973 */
2974#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
2975#define DMA_DCHPRI12_ECP_MASK (0x80U)
2976#define DMA_DCHPRI12_ECP_SHIFT (7U)
2977/*! ECP - Enable Channel Preemption
2978 * 0b0..Channel n cannot be suspended by a higher priority channel's service request
2979 * 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
2980 */
2981#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
2982/*! @} */
2983
2984/*! @name SADDR - TCD Source Address */
2985/*! @{ */
2986#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
2987#define DMA_SADDR_SADDR_SHIFT (0U)
2988#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
2989/*! @} */
2990
2991/* The count of DMA_SADDR */
2992#define DMA_SADDR_COUNT (16U)
2993
2994/*! @name SOFF - TCD Signed Source Address Offset */
2995/*! @{ */
2996#define DMA_SOFF_SOFF_MASK (0xFFFFU)
2997#define DMA_SOFF_SOFF_SHIFT (0U)
2998#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
2999/*! @} */
3000
3001/* The count of DMA_SOFF */
3002#define DMA_SOFF_COUNT (16U)
3003
3004/*! @name ATTR - TCD Transfer Attributes */
3005/*! @{ */
3006#define DMA_ATTR_DSIZE_MASK (0x7U)
3007#define DMA_ATTR_DSIZE_SHIFT (0U)
3008#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
3009#define DMA_ATTR_DMOD_MASK (0xF8U)
3010#define DMA_ATTR_DMOD_SHIFT (3U)
3011#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
3012#define DMA_ATTR_SSIZE_MASK (0x700U)
3013#define DMA_ATTR_SSIZE_SHIFT (8U)
3014/*! SSIZE - Source data transfer size
3015 * 0b000..8-bit
3016 * 0b001..16-bit
3017 * 0b010..32-bit
3018 * 0b011..Reserved
3019 * 0b100..16-byte
3020 * 0b101..32-byte
3021 * 0b110..Reserved
3022 * 0b111..Reserved
3023 */
3024#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
3025#define DMA_ATTR_SMOD_MASK (0xF800U)
3026#define DMA_ATTR_SMOD_SHIFT (11U)
3027/*! SMOD - Source Address Modulo.
3028 * 0b00000..Source address modulo feature is disabled
3029 */
3030#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
3031/*! @} */
3032
3033/* The count of DMA_ATTR */
3034#define DMA_ATTR_COUNT (16U)
3035
3036/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */
3037/*! @{ */
3038#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
3039#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
3040#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
3041/*! @} */
3042
3043/* The count of DMA_NBYTES_MLNO */
3044#define DMA_NBYTES_MLNO_COUNT (16U)
3045
3046/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
3047/*! @{ */
3048#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
3049#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
3050#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
3051#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
3052#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
3053/*! DMLOE - Destination Minor Loop Offset enable
3054 * 0b0..The minor loop offset is not applied to the DADDR
3055 * 0b1..The minor loop offset is applied to the DADDR
3056 */
3057#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
3058#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
3059#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
3060/*! SMLOE - Source Minor Loop Offset Enable
3061 * 0b0..The minor loop offset is not applied to the SADDR
3062 * 0b1..The minor loop offset is applied to the SADDR
3063 */
3064#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
3065/*! @} */
3066
3067/* The count of DMA_NBYTES_MLOFFNO */
3068#define DMA_NBYTES_MLOFFNO_COUNT (16U)
3069
3070/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
3071/*! @{ */
3072#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
3073#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
3074#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
3075#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
3076#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
3077#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
3078#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
3079#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
3080/*! DMLOE - Destination Minor Loop Offset enable
3081 * 0b0..The minor loop offset is not applied to the DADDR
3082 * 0b1..The minor loop offset is applied to the DADDR
3083 */
3084#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
3085#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
3086#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
3087/*! SMLOE - Source Minor Loop Offset Enable
3088 * 0b0..The minor loop offset is not applied to the SADDR
3089 * 0b1..The minor loop offset is applied to the SADDR
3090 */
3091#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
3092/*! @} */
3093
3094/* The count of DMA_NBYTES_MLOFFYES */
3095#define DMA_NBYTES_MLOFFYES_COUNT (16U)
3096
3097/*! @name SLAST - TCD Last Source Address Adjustment */
3098/*! @{ */
3099#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
3100#define DMA_SLAST_SLAST_SHIFT (0U)
3101#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
3102/*! @} */
3103
3104/* The count of DMA_SLAST */
3105#define DMA_SLAST_COUNT (16U)
3106
3107/*! @name DADDR - TCD Destination Address */
3108/*! @{ */
3109#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
3110#define DMA_DADDR_DADDR_SHIFT (0U)
3111#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
3112/*! @} */
3113
3114/* The count of DMA_DADDR */
3115#define DMA_DADDR_COUNT (16U)
3116
3117/*! @name DOFF - TCD Signed Destination Address Offset */
3118/*! @{ */
3119#define DMA_DOFF_DOFF_MASK (0xFFFFU)
3120#define DMA_DOFF_DOFF_SHIFT (0U)
3121#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
3122/*! @} */
3123
3124/* The count of DMA_DOFF */
3125#define DMA_DOFF_COUNT (16U)
3126
3127/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
3128/*! @{ */
3129#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
3130#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
3131#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
3132#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
3133#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
3134/*! ELINK - Enable channel-to-channel linking on minor-loop complete
3135 * 0b0..The channel-to-channel linking is disabled
3136 * 0b1..The channel-to-channel linking is enabled
3137 */
3138#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
3139/*! @} */
3140
3141/* The count of DMA_CITER_ELINKNO */
3142#define DMA_CITER_ELINKNO_COUNT (16U)
3143
3144/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
3145/*! @{ */
3146#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
3147#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
3148#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
3149#define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)
3150#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
3151#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
3152#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
3153#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
3154/*! ELINK - Enable channel-to-channel linking on minor-loop complete
3155 * 0b0..The channel-to-channel linking is disabled
3156 * 0b1..The channel-to-channel linking is enabled
3157 */
3158#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
3159/*! @} */
3160
3161/* The count of DMA_CITER_ELINKYES */
3162#define DMA_CITER_ELINKYES_COUNT (16U)
3163
3164/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
3165/*! @{ */
3166#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
3167#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
3168#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
3169/*! @} */
3170
3171/* The count of DMA_DLAST_SGA */
3172#define DMA_DLAST_SGA_COUNT (16U)
3173
3174/*! @name CSR - TCD Control and Status */
3175/*! @{ */
3176#define DMA_CSR_START_MASK (0x1U)
3177#define DMA_CSR_START_SHIFT (0U)
3178/*! START - Channel Start
3179 * 0b0..The channel is not explicitly started
3180 * 0b1..The channel is explicitly started via a software initiated service request
3181 */
3182#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
3183#define DMA_CSR_INTMAJOR_MASK (0x2U)
3184#define DMA_CSR_INTMAJOR_SHIFT (1U)
3185/*! INTMAJOR - Enable an interrupt when major iteration count completes
3186 * 0b0..The end-of-major loop interrupt is disabled
3187 * 0b1..The end-of-major loop interrupt is enabled
3188 */
3189#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
3190#define DMA_CSR_INTHALF_MASK (0x4U)
3191#define DMA_CSR_INTHALF_SHIFT (2U)
3192/*! INTHALF - Enable an interrupt when major counter is half complete.
3193 * 0b0..The half-point interrupt is disabled
3194 * 0b1..The half-point interrupt is enabled
3195 */
3196#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
3197#define DMA_CSR_DREQ_MASK (0x8U)
3198#define DMA_CSR_DREQ_SHIFT (3U)
3199/*! DREQ - Disable Request
3200 * 0b0..The channel's ERQ bit is not affected
3201 * 0b1..The channel's ERQ bit is cleared when the major loop is complete
3202 */
3203#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
3204#define DMA_CSR_ESG_MASK (0x10U)
3205#define DMA_CSR_ESG_SHIFT (4U)
3206/*! ESG - Enable Scatter/Gather Processing
3207 * 0b0..The current channel's TCD is normal format.
3208 * 0b1..The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
3209 */
3210#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
3211#define DMA_CSR_MAJORELINK_MASK (0x20U)
3212#define DMA_CSR_MAJORELINK_SHIFT (5U)
3213/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
3214 * 0b0..The channel-to-channel linking is disabled
3215 * 0b1..The channel-to-channel linking is enabled
3216 */
3217#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
3218#define DMA_CSR_ACTIVE_MASK (0x40U)
3219#define DMA_CSR_ACTIVE_SHIFT (6U)
3220#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
3221#define DMA_CSR_DONE_MASK (0x80U)
3222#define DMA_CSR_DONE_SHIFT (7U)
3223#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
3224#define DMA_CSR_MAJORLINKCH_MASK (0xF00U)
3225#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
3226#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
3227#define DMA_CSR_BWC_MASK (0xC000U)
3228#define DMA_CSR_BWC_SHIFT (14U)
3229/*! BWC - Bandwidth Control
3230 * 0b00..No eDMA engine stalls
3231 * 0b01..Reserved
3232 * 0b10..eDMA engine stalls for 4 cycles after each r/w
3233 * 0b11..eDMA engine stalls for 8 cycles after each r/w
3234 */
3235#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
3236/*! @} */
3237
3238/* The count of DMA_CSR */
3239#define DMA_CSR_COUNT (16U)
3240
3241/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
3242/*! @{ */
3243#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
3244#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
3245#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
3246#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
3247#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
3248/*! ELINK - Enables channel-to-channel linking on minor loop complete
3249 * 0b0..The channel-to-channel linking is disabled
3250 * 0b1..The channel-to-channel linking is enabled
3251 */
3252#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
3253/*! @} */
3254
3255/* The count of DMA_BITER_ELINKNO */
3256#define DMA_BITER_ELINKNO_COUNT (16U)
3257
3258/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
3259/*! @{ */
3260#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
3261#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
3262#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
3263#define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)
3264#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
3265#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
3266#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
3267#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
3268/*! ELINK - Enables channel-to-channel linking on minor loop complete
3269 * 0b0..The channel-to-channel linking is disabled
3270 * 0b1..The channel-to-channel linking is enabled
3271 */
3272#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
3273/*! @} */
3274
3275/* The count of DMA_BITER_ELINKYES */
3276#define DMA_BITER_ELINKYES_COUNT (16U)
3277
3278
3279/*!
3280 * @}
3281 */ /* end of group DMA_Register_Masks */
3282
3283
3284/* DMA - Peripheral instance base addresses */
3285/** Peripheral DMA base address */
3286#define DMA_BASE (0x40008000u)
3287/** Peripheral DMA base pointer */
3288#define DMA0 ((DMA_Type *)DMA_BASE)
3289/** Array initializer of DMA peripheral base addresses */
3290#define DMA_BASE_ADDRS { DMA_BASE }
3291/** Array initializer of DMA peripheral base pointers */
3292#define DMA_BASE_PTRS { DMA0 }
3293/** Interrupt vectors for the DMA peripheral type */
3294#define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } }
3295#define DMA_ERROR_IRQS { DMA_Error_IRQn }
3296
3297/*!
3298 * @}
3299 */ /* end of group DMA_Peripheral_Access_Layer */
3300
3301
3302/* ----------------------------------------------------------------------------
3303 -- DMAMUX Peripheral Access Layer
3304 ---------------------------------------------------------------------------- */
3305
3306/*!
3307 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
3308 * @{
3309 */
3310
3311/** DMAMUX - Register Layout Typedef */
3312typedef struct {
3313 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
3314} DMAMUX_Type;
3315
3316/* ----------------------------------------------------------------------------
3317 -- DMAMUX Register Masks
3318 ---------------------------------------------------------------------------- */
3319
3320/*!
3321 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
3322 * @{
3323 */
3324
3325/*! @name CHCFG - Channel Configuration register */
3326/*! @{ */
3327#define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
3328#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
3329/*! SOURCE - DMA Channel Source (Slot)
3330 * 0b000000..Disable_Signal
3331 * 0b000010..UART0_Rx_Signal
3332 * 0b000011..UART0_Tx_Signal
3333 * 0b000100..UART1_Rx_Signal
3334 * 0b000101..UART1_Tx_Signal
3335 * 0b000110..UART2_Rx_Signal
3336 * 0b000111..UART2_Tx_Signal
3337 * 0b001110..SPI0_Rx_Signal
3338 * 0b001111..SPI0_Tx_Signal
3339 * 0b010000..SPI1_Signal
3340 * 0b010010..I2C0_Signal
3341 * 0b010011..I2C1_Signal
3342 * 0b010100..FTM0_Channel0_Signal
3343 * 0b010101..FTM0_Channel1_Signal
3344 * 0b010110..FTM0_Channel2_Signal
3345 * 0b010111..FTM0_Channel3_Signal
3346 * 0b011000..FTM0_Channel4_Signal
3347 * 0b011001..FTM0_Channel5_Signal
3348 * 0b011010..FTM0_Channel6_Signal
3349 * 0b011011..FTM0_Channel7_Signal
3350 * 0b011100..FTM1_Channel0_Signal
3351 * 0b011101..FTM1_Channel1_Signal
3352 * 0b011110..FTM2_Channel0_Signal
3353 * 0b011111..FTM2_Channel1_Signal
3354 * 0b101000..ADC0_Signal
3355 * 0b101001..ADC1_Signal
3356 * 0b101010..CMP0_Signal
3357 * 0b101011..CMP1_Signal
3358 * 0b101101..DAC0_Signal
3359 * 0b110000..PDB_Signal
3360 * 0b110001..PortA_Signal
3361 * 0b110010..PortB_Signal
3362 * 0b110011..PortC_Signal
3363 * 0b110100..PortD_Signal
3364 * 0b110101..PortE_Signal
3365 * 0b111010..LPUART0_Rx_Signal
3366 * 0b111011..LPUART0_Tx_Signal
3367 * 0b111100..AlwaysOn60_Signal
3368 * 0b111101..AlwaysOn61_Signal
3369 * 0b111110..AlwaysOn62_Signal
3370 * 0b111111..AlwaysOn63_Signal
3371 */
3372#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
3373#define DMAMUX_CHCFG_TRIG_MASK (0x40U)
3374#define DMAMUX_CHCFG_TRIG_SHIFT (6U)
3375/*! TRIG - DMA Channel Trigger Enable
3376 * 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
3377 * 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
3378 */
3379#define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
3380#define DMAMUX_CHCFG_ENBL_MASK (0x80U)
3381#define DMAMUX_CHCFG_ENBL_SHIFT (7U)
3382/*! ENBL - DMA Channel Enable
3383 * 0b0..DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
3384 * 0b1..DMA channel is enabled
3385 */
3386#define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
3387/*! @} */
3388
3389/* The count of DMAMUX_CHCFG */
3390#define DMAMUX_CHCFG_COUNT (16U)
3391
3392
3393/*!
3394 * @}
3395 */ /* end of group DMAMUX_Register_Masks */
3396
3397
3398/* DMAMUX - Peripheral instance base addresses */
3399/** Peripheral DMAMUX base address */
3400#define DMAMUX_BASE (0x40021000u)
3401/** Peripheral DMAMUX base pointer */
3402#define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
3403/** Array initializer of DMAMUX peripheral base addresses */
3404#define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
3405/** Array initializer of DMAMUX peripheral base pointers */
3406#define DMAMUX_BASE_PTRS { DMAMUX }
3407
3408/*!
3409 * @}
3410 */ /* end of group DMAMUX_Peripheral_Access_Layer */
3411
3412
3413/* ----------------------------------------------------------------------------
3414 -- EWM Peripheral Access Layer
3415 ---------------------------------------------------------------------------- */
3416
3417/*!
3418 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
3419 * @{
3420 */
3421
3422/** EWM - Register Layout Typedef */
3423typedef struct {
3424 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
3425 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
3426 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
3427 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
3428 uint8_t RESERVED_0[1];
3429 __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
3430} EWM_Type;
3431
3432/* ----------------------------------------------------------------------------
3433 -- EWM Register Masks
3434 ---------------------------------------------------------------------------- */
3435
3436/*!
3437 * @addtogroup EWM_Register_Masks EWM Register Masks
3438 * @{
3439 */
3440
3441/*! @name CTRL - Control Register */
3442/*! @{ */
3443#define EWM_CTRL_EWMEN_MASK (0x1U)
3444#define EWM_CTRL_EWMEN_SHIFT (0U)
3445#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
3446#define EWM_CTRL_ASSIN_MASK (0x2U)
3447#define EWM_CTRL_ASSIN_SHIFT (1U)
3448#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
3449#define EWM_CTRL_INEN_MASK (0x4U)
3450#define EWM_CTRL_INEN_SHIFT (2U)
3451#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
3452#define EWM_CTRL_INTEN_MASK (0x8U)
3453#define EWM_CTRL_INTEN_SHIFT (3U)
3454#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
3455/*! @} */
3456
3457/*! @name SERV - Service Register */
3458/*! @{ */
3459#define EWM_SERV_SERVICE_MASK (0xFFU)
3460#define EWM_SERV_SERVICE_SHIFT (0U)
3461#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
3462/*! @} */
3463
3464/*! @name CMPL - Compare Low Register */
3465/*! @{ */
3466#define EWM_CMPL_COMPAREL_MASK (0xFFU)
3467#define EWM_CMPL_COMPAREL_SHIFT (0U)
3468#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
3469/*! @} */
3470
3471/*! @name CMPH - Compare High Register */
3472/*! @{ */
3473#define EWM_CMPH_COMPAREH_MASK (0xFFU)
3474#define EWM_CMPH_COMPAREH_SHIFT (0U)
3475#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
3476/*! @} */
3477
3478/*! @name CLKPRESCALER - Clock Prescaler Register */
3479/*! @{ */
3480#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
3481#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
3482#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
3483/*! @} */
3484
3485
3486/*!
3487 * @}
3488 */ /* end of group EWM_Register_Masks */
3489
3490
3491/* EWM - Peripheral instance base addresses */
3492/** Peripheral EWM base address */
3493#define EWM_BASE (0x40061000u)
3494/** Peripheral EWM base pointer */
3495#define EWM ((EWM_Type *)EWM_BASE)
3496/** Array initializer of EWM peripheral base addresses */
3497#define EWM_BASE_ADDRS { EWM_BASE }
3498/** Array initializer of EWM peripheral base pointers */
3499#define EWM_BASE_PTRS { EWM }
3500/** Interrupt vectors for the EWM peripheral type */
3501#define EWM_IRQS { WDOG_EWM_IRQn }
3502
3503/*!
3504 * @}
3505 */ /* end of group EWM_Peripheral_Access_Layer */
3506
3507
3508/* ----------------------------------------------------------------------------
3509 -- FMC Peripheral Access Layer
3510 ---------------------------------------------------------------------------- */
3511
3512/*!
3513 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
3514 * @{
3515 */
3516
3517/** FMC - Register Layout Typedef */
3518typedef struct {
3519 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
3520 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
3521 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
3522 uint8_t RESERVED_0[244];
3523 __IO uint32_t TAGVDW0S[8]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
3524 __IO uint32_t TAGVDW1S[8]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
3525 __IO uint32_t TAGVDW2S[8]; /**< Cache Tag Storage, array offset: 0x140, array step: 0x4 */
3526 __IO uint32_t TAGVDW3S[8]; /**< Cache Tag Storage, array offset: 0x160, array step: 0x4 */
3527 uint8_t RESERVED_1[128];
3528 struct { /* offset: 0x200, array step: index*0x40, index2*0x8 */
3529 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8 */
3530 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8 */
3531 } SET[4][8];
3532} FMC_Type;
3533
3534/* ----------------------------------------------------------------------------
3535 -- FMC Register Masks
3536 ---------------------------------------------------------------------------- */
3537
3538/*!
3539 * @addtogroup FMC_Register_Masks FMC Register Masks
3540 * @{
3541 */
3542
3543/*! @name PFAPR - Flash Access Protection Register */
3544/*! @{ */
3545#define FMC_PFAPR_M0AP_MASK (0x3U)
3546#define FMC_PFAPR_M0AP_SHIFT (0U)
3547/*! M0AP - Master 0 Access Protection
3548 * 0b00..No access may be performed by this master
3549 * 0b01..Only read accesses may be performed by this master
3550 * 0b10..Only write accesses may be performed by this master
3551 * 0b11..Both read and write accesses may be performed by this master
3552 */
3553#define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
3554#define FMC_PFAPR_M1AP_MASK (0xCU)
3555#define FMC_PFAPR_M1AP_SHIFT (2U)
3556/*! M1AP - Master 1 Access Protection
3557 * 0b00..No access may be performed by this master
3558 * 0b01..Only read accesses may be performed by this master
3559 * 0b10..Only write accesses may be performed by this master
3560 * 0b11..Both read and write accesses may be performed by this master
3561 */
3562#define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
3563#define FMC_PFAPR_M2AP_MASK (0x30U)
3564#define FMC_PFAPR_M2AP_SHIFT (4U)
3565/*! M2AP - Master 2 Access Protection
3566 * 0b00..No access may be performed by this master
3567 * 0b01..Only read accesses may be performed by this master
3568 * 0b10..Only write accesses may be performed by this master
3569 * 0b11..Both read and write accesses may be performed by this master
3570 */
3571#define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
3572#define FMC_PFAPR_M3AP_MASK (0xC0U)
3573#define FMC_PFAPR_M3AP_SHIFT (6U)
3574/*! M3AP - Master 3 Access Protection
3575 * 0b00..No access may be performed by this master
3576 * 0b01..Only read accesses may be performed by this master
3577 * 0b10..Only write accesses may be performed by this master
3578 * 0b11..Both read and write accesses may be performed by this master
3579 */
3580#define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
3581#define FMC_PFAPR_M4AP_MASK (0x300U)
3582#define FMC_PFAPR_M4AP_SHIFT (8U)
3583/*! M4AP - Master 4 Access Protection
3584 * 0b00..No access may be performed by this master
3585 * 0b01..Only read accesses may be performed by this master
3586 * 0b10..Only write accesses may be performed by this master
3587 * 0b11..Both read and write accesses may be performed by this master
3588 */
3589#define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
3590#define FMC_PFAPR_M5AP_MASK (0xC00U)
3591#define FMC_PFAPR_M5AP_SHIFT (10U)
3592/*! M5AP - Master 5 Access Protection
3593 * 0b00..No access may be performed by this master
3594 * 0b01..Only read accesses may be performed by this master
3595 * 0b10..Only write accesses may be performed by this master
3596 * 0b11..Both read and write accesses may be performed by this master
3597 */
3598#define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
3599#define FMC_PFAPR_M6AP_MASK (0x3000U)
3600#define FMC_PFAPR_M6AP_SHIFT (12U)
3601/*! M6AP - Master 6 Access Protection
3602 * 0b00..No access may be performed by this master
3603 * 0b01..Only read accesses may be performed by this master
3604 * 0b10..Only write accesses may be performed by this master
3605 * 0b11..Both read and write accesses may be performed by this master
3606 */
3607#define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
3608#define FMC_PFAPR_M7AP_MASK (0xC000U)
3609#define FMC_PFAPR_M7AP_SHIFT (14U)
3610/*! M7AP - Master 7 Access Protection
3611 * 0b00..No access may be performed by this master.
3612 * 0b01..Only read accesses may be performed by this master.
3613 * 0b10..Only write accesses may be performed by this master.
3614 * 0b11..Both read and write accesses may be performed by this master.
3615 */
3616#define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
3617#define FMC_PFAPR_M0PFD_MASK (0x10000U)
3618#define FMC_PFAPR_M0PFD_SHIFT (16U)
3619/*! M0PFD - Master 0 Prefetch Disable
3620 * 0b0..Prefetching for this master is enabled.
3621 * 0b1..Prefetching for this master is disabled.
3622 */
3623#define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
3624#define FMC_PFAPR_M1PFD_MASK (0x20000U)
3625#define FMC_PFAPR_M1PFD_SHIFT (17U)
3626/*! M1PFD - Master 1 Prefetch Disable
3627 * 0b0..Prefetching for this master is enabled.
3628 * 0b1..Prefetching for this master is disabled.
3629 */
3630#define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
3631#define FMC_PFAPR_M2PFD_MASK (0x40000U)
3632#define FMC_PFAPR_M2PFD_SHIFT (18U)
3633/*! M2PFD - Master 2 Prefetch Disable
3634 * 0b0..Prefetching for this master is enabled.
3635 * 0b1..Prefetching for this master is disabled.
3636 */
3637#define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
3638#define FMC_PFAPR_M3PFD_MASK (0x80000U)
3639#define FMC_PFAPR_M3PFD_SHIFT (19U)
3640/*! M3PFD - Master 3 Prefetch Disable
3641 * 0b0..Prefetching for this master is enabled.
3642 * 0b1..Prefetching for this master is disabled.
3643 */
3644#define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
3645#define FMC_PFAPR_M4PFD_MASK (0x100000U)
3646#define FMC_PFAPR_M4PFD_SHIFT (20U)
3647/*! M4PFD - Master 4 Prefetch Disable
3648 * 0b0..Prefetching for this master is enabled.
3649 * 0b1..Prefetching for this master is disabled.
3650 */
3651#define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
3652#define FMC_PFAPR_M5PFD_MASK (0x200000U)
3653#define FMC_PFAPR_M5PFD_SHIFT (21U)
3654/*! M5PFD - Master 5 Prefetch Disable
3655 * 0b0..Prefetching for this master is enabled.
3656 * 0b1..Prefetching for this master is disabled.
3657 */
3658#define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
3659#define FMC_PFAPR_M6PFD_MASK (0x400000U)
3660#define FMC_PFAPR_M6PFD_SHIFT (22U)
3661/*! M6PFD - Master 6 Prefetch Disable
3662 * 0b0..Prefetching for this master is enabled.
3663 * 0b1..Prefetching for this master is disabled.
3664 */
3665#define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
3666#define FMC_PFAPR_M7PFD_MASK (0x800000U)
3667#define FMC_PFAPR_M7PFD_SHIFT (23U)
3668/*! M7PFD - Master 7 Prefetch Disable
3669 * 0b0..Prefetching for this master is enabled.
3670 * 0b1..Prefetching for this master is disabled.
3671 */
3672#define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
3673/*! @} */
3674
3675/*! @name PFB0CR - Flash Bank 0 Control Register */
3676/*! @{ */
3677#define FMC_PFB0CR_B0SEBE_MASK (0x1U)
3678#define FMC_PFB0CR_B0SEBE_SHIFT (0U)
3679/*! B0SEBE - Bank 0 Single Entry Buffer Enable
3680 * 0b0..Single entry buffer is disabled.
3681 * 0b1..Single entry buffer is enabled.
3682 */
3683#define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
3684#define FMC_PFB0CR_B0IPE_MASK (0x2U)
3685#define FMC_PFB0CR_B0IPE_SHIFT (1U)
3686/*! B0IPE - Bank 0 Instruction Prefetch Enable
3687 * 0b0..Do not prefetch in response to instruction fetches.
3688 * 0b1..Enable prefetches in response to instruction fetches.
3689 */
3690#define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
3691#define FMC_PFB0CR_B0DPE_MASK (0x4U)
3692#define FMC_PFB0CR_B0DPE_SHIFT (2U)
3693/*! B0DPE - Bank 0 Data Prefetch Enable
3694 * 0b0..Do not prefetch in response to data references.
3695 * 0b1..Enable prefetches in response to data references.
3696 */
3697#define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
3698#define FMC_PFB0CR_B0ICE_MASK (0x8U)
3699#define FMC_PFB0CR_B0ICE_SHIFT (3U)
3700/*! B0ICE - Bank 0 Instruction Cache Enable
3701 * 0b0..Do not cache instruction fetches.
3702 * 0b1..Cache instruction fetches.
3703 */
3704#define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
3705#define FMC_PFB0CR_B0DCE_MASK (0x10U)
3706#define FMC_PFB0CR_B0DCE_SHIFT (4U)
3707/*! B0DCE - Bank 0 Data Cache Enable
3708 * 0b0..Do not cache data references.
3709 * 0b1..Cache data references.
3710 */
3711#define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
3712#define FMC_PFB0CR_CRC_MASK (0xE0U)
3713#define FMC_PFB0CR_CRC_SHIFT (5U)
3714/*! CRC - Cache Replacement Control
3715 * 0b000..LRU replacement algorithm per set across all four ways
3716 * 0b001..Reserved
3717 * 0b010..Independent LRU with ways [0-1] for ifetches, [2-3] for data
3718 * 0b011..Independent LRU with ways [0-2] for ifetches, [3] for data
3719 * 0b1xx..Reserved
3720 */
3721#define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
3722#define FMC_PFB0CR_B0MW_MASK (0x60000U)
3723#define FMC_PFB0CR_B0MW_SHIFT (17U)
3724/*! B0MW - Bank 0 Memory Width
3725 * 0b00..32 bits
3726 * 0b01..64 bits
3727 * 0b10..Reserved
3728 * 0b11..Reserved
3729 */
3730#define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
3731#define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
3732#define FMC_PFB0CR_S_B_INV_SHIFT (19U)
3733/*! S_B_INV - Invalidate Prefetch Speculation Buffer
3734 * 0b0..Speculation buffer and single entry buffer are not affected.
3735 * 0b1..Invalidate (clear) speculation buffer and single entry buffer.
3736 */
3737#define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
3738#define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
3739#define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
3740/*! CINV_WAY - Cache Invalidate Way x
3741 * 0b0000..No cache way invalidation for the corresponding cache
3742 * 0b0001..Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected
3743 */
3744#define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
3745#define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
3746#define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
3747/*! CLCK_WAY - Cache Lock Way x
3748 * 0b0000..Cache way is unlocked and may be displaced
3749 * 0b0001..Cache way is locked and its contents are not displaced
3750 */
3751#define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
3752#define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
3753#define FMC_PFB0CR_B0RWSC_SHIFT (28U)
3754#define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
3755/*! @} */
3756
3757/*! @name PFB1CR - Flash Bank 1 Control Register */
3758/*! @{ */
3759#define FMC_PFB1CR_B1SEBE_MASK (0x1U)
3760#define FMC_PFB1CR_B1SEBE_SHIFT (0U)
3761/*! B1SEBE - Bank 1 Single Entry Buffer Enable
3762 * 0b0..Single entry buffer is disabled.
3763 * 0b1..Single entry buffer is enabled.
3764 */
3765#define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
3766#define FMC_PFB1CR_B1IPE_MASK (0x2U)
3767#define FMC_PFB1CR_B1IPE_SHIFT (1U)
3768/*! B1IPE - Bank 1 Instruction Prefetch Enable
3769 * 0b0..Do not prefetch in response to instruction fetches.
3770 * 0b1..Enable prefetches in response to instruction fetches.
3771 */
3772#define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
3773#define FMC_PFB1CR_B1DPE_MASK (0x4U)
3774#define FMC_PFB1CR_B1DPE_SHIFT (2U)
3775/*! B1DPE - Bank 1 Data Prefetch Enable
3776 * 0b0..Do not prefetch in response to data references.
3777 * 0b1..Enable prefetches in response to data references.
3778 */
3779#define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
3780#define FMC_PFB1CR_B1ICE_MASK (0x8U)
3781#define FMC_PFB1CR_B1ICE_SHIFT (3U)
3782/*! B1ICE - Bank 1 Instruction Cache Enable
3783 * 0b0..Do not cache instruction fetches.
3784 * 0b1..Cache instruction fetches.
3785 */
3786#define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
3787#define FMC_PFB1CR_B1DCE_MASK (0x10U)
3788#define FMC_PFB1CR_B1DCE_SHIFT (4U)
3789/*! B1DCE - Bank 1 Data Cache Enable
3790 * 0b0..Do not cache data references.
3791 * 0b1..Cache data references.
3792 */
3793#define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
3794#define FMC_PFB1CR_B1MW_MASK (0x60000U)
3795#define FMC_PFB1CR_B1MW_SHIFT (17U)
3796/*! B1MW - Bank 1 Memory Width
3797 * 0b00..32 bits
3798 * 0b01..64 bits
3799 * 0b10..Reserved
3800 * 0b11..Reserved
3801 */
3802#define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
3803#define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U)
3804#define FMC_PFB1CR_B1RWSC_SHIFT (28U)
3805#define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
3806/*! @} */
3807
3808/*! @name TAGVDW0S - Cache Tag Storage */
3809/*! @{ */
3810#define FMC_TAGVDW0S_valid_MASK (0x1U)
3811#define FMC_TAGVDW0S_valid_SHIFT (0U)
3812#define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
3813#define FMC_TAGVDW0S_tag_MASK (0x7FFE0U)
3814#define FMC_TAGVDW0S_tag_SHIFT (5U)
3815#define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
3816/*! @} */
3817
3818/* The count of FMC_TAGVDW0S */
3819#define FMC_TAGVDW0S_COUNT (8U)
3820
3821/*! @name TAGVDW1S - Cache Tag Storage */
3822/*! @{ */
3823#define FMC_TAGVDW1S_valid_MASK (0x1U)
3824#define FMC_TAGVDW1S_valid_SHIFT (0U)
3825#define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
3826#define FMC_TAGVDW1S_tag_MASK (0x7FFE0U)
3827#define FMC_TAGVDW1S_tag_SHIFT (5U)
3828#define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
3829/*! @} */
3830
3831/* The count of FMC_TAGVDW1S */
3832#define FMC_TAGVDW1S_COUNT (8U)
3833
3834/*! @name TAGVDW2S - Cache Tag Storage */
3835/*! @{ */
3836#define FMC_TAGVDW2S_valid_MASK (0x1U)
3837#define FMC_TAGVDW2S_valid_SHIFT (0U)
3838#define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
3839#define FMC_TAGVDW2S_tag_MASK (0x7FFE0U)
3840#define FMC_TAGVDW2S_tag_SHIFT (5U)
3841#define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
3842/*! @} */
3843
3844/* The count of FMC_TAGVDW2S */
3845#define FMC_TAGVDW2S_COUNT (8U)
3846
3847/*! @name TAGVDW3S - Cache Tag Storage */
3848/*! @{ */
3849#define FMC_TAGVDW3S_valid_MASK (0x1U)
3850#define FMC_TAGVDW3S_valid_SHIFT (0U)
3851#define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
3852#define FMC_TAGVDW3S_tag_MASK (0x7FFE0U)
3853#define FMC_TAGVDW3S_tag_SHIFT (5U)
3854#define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
3855/*! @} */
3856
3857/* The count of FMC_TAGVDW3S */
3858#define FMC_TAGVDW3S_COUNT (8U)
3859
3860/*! @name DATA_U - Cache Data Storage (upper word) */
3861/*! @{ */
3862#define FMC_DATA_U_data_MASK (0xFFFFFFFFU)
3863#define FMC_DATA_U_data_SHIFT (0U)
3864#define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
3865/*! @} */
3866
3867/* The count of FMC_DATA_U */
3868#define FMC_DATA_U_COUNT (4U)
3869
3870/* The count of FMC_DATA_U */
3871#define FMC_DATA_U_COUNT2 (8U)
3872
3873/*! @name DATA_L - Cache Data Storage (lower word) */
3874/*! @{ */
3875#define FMC_DATA_L_data_MASK (0xFFFFFFFFU)
3876#define FMC_DATA_L_data_SHIFT (0U)
3877#define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
3878/*! @} */
3879
3880/* The count of FMC_DATA_L */
3881#define FMC_DATA_L_COUNT (4U)
3882
3883/* The count of FMC_DATA_L */
3884#define FMC_DATA_L_COUNT2 (8U)
3885
3886
3887/*!
3888 * @}
3889 */ /* end of group FMC_Register_Masks */
3890
3891
3892/* FMC - Peripheral instance base addresses */
3893/** Peripheral FMC base address */
3894#define FMC_BASE (0x4001F000u)
3895/** Peripheral FMC base pointer */
3896#define FMC ((FMC_Type *)FMC_BASE)
3897/** Array initializer of FMC peripheral base addresses */
3898#define FMC_BASE_ADDRS { FMC_BASE }
3899/** Array initializer of FMC peripheral base pointers */
3900#define FMC_BASE_PTRS { FMC }
3901
3902/*!
3903 * @}
3904 */ /* end of group FMC_Peripheral_Access_Layer */
3905
3906
3907/* ----------------------------------------------------------------------------
3908 -- FTFA Peripheral Access Layer
3909 ---------------------------------------------------------------------------- */
3910
3911/*!
3912 * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
3913 * @{
3914 */
3915
3916/** FTFA - Register Layout Typedef */
3917typedef struct {
3918 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
3919 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
3920 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
3921 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
3922 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
3923 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
3924 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
3925 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
3926 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
3927 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
3928 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
3929 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
3930 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
3931 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
3932 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
3933 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
3934 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
3935 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
3936 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
3937 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
3938 uint8_t RESERVED_0[4];
3939 __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */
3940 __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */
3941 __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */
3942 __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */
3943 __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */
3944 __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */
3945 __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */
3946 __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */
3947 __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */
3948 __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */
3949 __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */
3950 __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */
3951 __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */
3952 __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */
3953 __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */
3954 __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */
3955 __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */
3956 uint8_t RESERVED_1[2];
3957 __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */
3958} FTFA_Type;
3959
3960/* ----------------------------------------------------------------------------
3961 -- FTFA Register Masks
3962 ---------------------------------------------------------------------------- */
3963
3964/*!
3965 * @addtogroup FTFA_Register_Masks FTFA Register Masks
3966 * @{
3967 */
3968
3969/*! @name FSTAT - Flash Status Register */
3970/*! @{ */
3971#define FTFA_FSTAT_MGSTAT0_MASK (0x1U)
3972#define FTFA_FSTAT_MGSTAT0_SHIFT (0U)
3973#define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK)
3974#define FTFA_FSTAT_FPVIOL_MASK (0x10U)
3975#define FTFA_FSTAT_FPVIOL_SHIFT (4U)
3976/*! FPVIOL - Flash Protection Violation Flag
3977 * 0b0..No protection violation detected
3978 * 0b1..Protection violation detected
3979 */
3980#define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK)
3981#define FTFA_FSTAT_ACCERR_MASK (0x20U)
3982#define FTFA_FSTAT_ACCERR_SHIFT (5U)
3983/*! ACCERR - Flash Access Error Flag
3984 * 0b0..No access error detected
3985 * 0b1..Access error detected
3986 */
3987#define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK)
3988#define FTFA_FSTAT_RDCOLERR_MASK (0x40U)
3989#define FTFA_FSTAT_RDCOLERR_SHIFT (6U)
3990/*! RDCOLERR - Flash Read Collision Error Flag
3991 * 0b0..No collision error detected
3992 * 0b1..Collision error detected
3993 */
3994#define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK)
3995#define FTFA_FSTAT_CCIF_MASK (0x80U)
3996#define FTFA_FSTAT_CCIF_SHIFT (7U)
3997/*! CCIF - Command Complete Interrupt Flag
3998 * 0b0..Flash command in progress
3999 * 0b1..Flash command has completed
4000 */
4001#define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK)
4002/*! @} */
4003
4004/*! @name FCNFG - Flash Configuration Register */
4005/*! @{ */
4006#define FTFA_FCNFG_ERSSUSP_MASK (0x10U)
4007#define FTFA_FCNFG_ERSSUSP_SHIFT (4U)
4008/*! ERSSUSP - Erase Suspend
4009 * 0b0..No suspend requested
4010 * 0b1..Suspend the current Erase Flash Sector command execution.
4011 */
4012#define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK)
4013#define FTFA_FCNFG_ERSAREQ_MASK (0x20U)
4014#define FTFA_FCNFG_ERSAREQ_SHIFT (5U)
4015/*! ERSAREQ - Erase All Request
4016 * 0b0..No request or request complete
4017 * 0b1..Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.
4018 */
4019#define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK)
4020#define FTFA_FCNFG_RDCOLLIE_MASK (0x40U)
4021#define FTFA_FCNFG_RDCOLLIE_SHIFT (6U)
4022/*! RDCOLLIE - Read Collision Error Interrupt Enable
4023 * 0b0..Read collision error interrupt disabled
4024 * 0b1..Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).
4025 */
4026#define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK)
4027#define FTFA_FCNFG_CCIE_MASK (0x80U)
4028#define FTFA_FCNFG_CCIE_SHIFT (7U)
4029/*! CCIE - Command Complete Interrupt Enable
4030 * 0b0..Command complete interrupt disabled
4031 * 0b1..Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
4032 */
4033#define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK)
4034/*! @} */
4035
4036/*! @name FSEC - Flash Security Register */
4037/*! @{ */
4038#define FTFA_FSEC_SEC_MASK (0x3U)
4039#define FTFA_FSEC_SEC_SHIFT (0U)
4040/*! SEC - Flash Security
4041 * 0b00..MCU security status is secure.
4042 * 0b01..MCU security status is secure.
4043 * 0b10..MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
4044 * 0b11..MCU security status is secure.
4045 */
4046#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK)
4047#define FTFA_FSEC_FSLACC_MASK (0xCU)
4048#define FTFA_FSEC_FSLACC_SHIFT (2U)
4049/*! FSLACC - Freescale Failure Analysis Access Code
4050 * 0b00..Freescale factory access granted
4051 * 0b01..Freescale factory access denied
4052 * 0b10..Freescale factory access denied
4053 * 0b11..Freescale factory access granted
4054 */
4055#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK)
4056#define FTFA_FSEC_MEEN_MASK (0x30U)
4057#define FTFA_FSEC_MEEN_SHIFT (4U)
4058/*! MEEN - Mass Erase Enable Bits
4059 * 0b00..Mass erase is enabled
4060 * 0b01..Mass erase is enabled
4061 * 0b10..Mass erase is disabled
4062 * 0b11..Mass erase is enabled
4063 */
4064#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK)
4065#define FTFA_FSEC_KEYEN_MASK (0xC0U)
4066#define FTFA_FSEC_KEYEN_SHIFT (6U)
4067/*! KEYEN - Backdoor Key Security Enable
4068 * 0b00..Backdoor key access disabled
4069 * 0b01..Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
4070 * 0b10..Backdoor key access enabled
4071 * 0b11..Backdoor key access disabled
4072 */
4073#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK)
4074/*! @} */
4075
4076/*! @name FOPT - Flash Option Register */
4077/*! @{ */
4078#define FTFA_FOPT_OPT_MASK (0xFFU)
4079#define FTFA_FOPT_OPT_SHIFT (0U)
4080#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK)
4081/*! @} */
4082
4083/*! @name FCCOB3 - Flash Common Command Object Registers */
4084/*! @{ */
4085#define FTFA_FCCOB3_CCOBn_MASK (0xFFU)
4086#define FTFA_FCCOB3_CCOBn_SHIFT (0U)
4087#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK)
4088/*! @} */
4089
4090/*! @name FCCOB2 - Flash Common Command Object Registers */
4091/*! @{ */
4092#define FTFA_FCCOB2_CCOBn_MASK (0xFFU)
4093#define FTFA_FCCOB2_CCOBn_SHIFT (0U)
4094#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK)
4095/*! @} */
4096
4097/*! @name FCCOB1 - Flash Common Command Object Registers */
4098/*! @{ */
4099#define FTFA_FCCOB1_CCOBn_MASK (0xFFU)
4100#define FTFA_FCCOB1_CCOBn_SHIFT (0U)
4101#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK)
4102/*! @} */
4103
4104/*! @name FCCOB0 - Flash Common Command Object Registers */
4105/*! @{ */
4106#define FTFA_FCCOB0_CCOBn_MASK (0xFFU)
4107#define FTFA_FCCOB0_CCOBn_SHIFT (0U)
4108#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK)
4109/*! @} */
4110
4111/*! @name FCCOB7 - Flash Common Command Object Registers */
4112/*! @{ */
4113#define FTFA_FCCOB7_CCOBn_MASK (0xFFU)
4114#define FTFA_FCCOB7_CCOBn_SHIFT (0U)
4115#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK)
4116/*! @} */
4117
4118/*! @name FCCOB6 - Flash Common Command Object Registers */
4119/*! @{ */
4120#define FTFA_FCCOB6_CCOBn_MASK (0xFFU)
4121#define FTFA_FCCOB6_CCOBn_SHIFT (0U)
4122#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK)
4123/*! @} */
4124
4125/*! @name FCCOB5 - Flash Common Command Object Registers */
4126/*! @{ */
4127#define FTFA_FCCOB5_CCOBn_MASK (0xFFU)
4128#define FTFA_FCCOB5_CCOBn_SHIFT (0U)
4129#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK)
4130/*! @} */
4131
4132/*! @name FCCOB4 - Flash Common Command Object Registers */
4133/*! @{ */
4134#define FTFA_FCCOB4_CCOBn_MASK (0xFFU)
4135#define FTFA_FCCOB4_CCOBn_SHIFT (0U)
4136#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK)
4137/*! @} */
4138
4139/*! @name FCCOBB - Flash Common Command Object Registers */
4140/*! @{ */
4141#define FTFA_FCCOBB_CCOBn_MASK (0xFFU)
4142#define FTFA_FCCOBB_CCOBn_SHIFT (0U)
4143#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK)
4144/*! @} */
4145
4146/*! @name FCCOBA - Flash Common Command Object Registers */
4147/*! @{ */
4148#define FTFA_FCCOBA_CCOBn_MASK (0xFFU)
4149#define FTFA_FCCOBA_CCOBn_SHIFT (0U)
4150#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK)
4151/*! @} */
4152
4153/*! @name FCCOB9 - Flash Common Command Object Registers */
4154/*! @{ */
4155#define FTFA_FCCOB9_CCOBn_MASK (0xFFU)
4156#define FTFA_FCCOB9_CCOBn_SHIFT (0U)
4157#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK)
4158/*! @} */
4159
4160/*! @name FCCOB8 - Flash Common Command Object Registers */
4161/*! @{ */
4162#define FTFA_FCCOB8_CCOBn_MASK (0xFFU)
4163#define FTFA_FCCOB8_CCOBn_SHIFT (0U)
4164#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK)
4165/*! @} */
4166
4167/*! @name FPROT3 - Program Flash Protection Registers */
4168/*! @{ */
4169#define FTFA_FPROT3_PROT_MASK (0xFFU)
4170#define FTFA_FPROT3_PROT_SHIFT (0U)
4171/*! PROT - Program Flash Region Protect
4172 * 0b00000000..Program flash region is protected.
4173 * 0b00000001..Program flash region is not protected
4174 */
4175#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK)
4176/*! @} */
4177
4178/*! @name FPROT2 - Program Flash Protection Registers */
4179/*! @{ */
4180#define FTFA_FPROT2_PROT_MASK (0xFFU)
4181#define FTFA_FPROT2_PROT_SHIFT (0U)
4182/*! PROT - Program Flash Region Protect
4183 * 0b00000000..Program flash region is protected.
4184 * 0b00000001..Program flash region is not protected
4185 */
4186#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK)
4187/*! @} */
4188
4189/*! @name FPROT1 - Program Flash Protection Registers */
4190/*! @{ */
4191#define FTFA_FPROT1_PROT_MASK (0xFFU)
4192#define FTFA_FPROT1_PROT_SHIFT (0U)
4193/*! PROT - Program Flash Region Protect
4194 * 0b00000000..Program flash region is protected.
4195 * 0b00000001..Program flash region is not protected
4196 */
4197#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK)
4198/*! @} */
4199
4200/*! @name FPROT0 - Program Flash Protection Registers */
4201/*! @{ */
4202#define FTFA_FPROT0_PROT_MASK (0xFFU)
4203#define FTFA_FPROT0_PROT_SHIFT (0U)
4204/*! PROT - Program Flash Region Protect
4205 * 0b00000000..Program flash region is protected.
4206 * 0b00000001..Program flash region is not protected
4207 */
4208#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK)
4209/*! @} */
4210
4211/*! @name XACCH3 - Execute-only Access Registers */
4212/*! @{ */
4213#define FTFA_XACCH3_XA_MASK (0xFFU)
4214#define FTFA_XACCH3_XA_SHIFT (0U)
4215/*! XA - Execute-only access control
4216 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
4217 * 0b00000001..Associated segment is accessible as data or in execute mode
4218 */
4219#define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK)
4220/*! @} */
4221
4222/*! @name XACCH2 - Execute-only Access Registers */
4223/*! @{ */
4224#define FTFA_XACCH2_XA_MASK (0xFFU)
4225#define FTFA_XACCH2_XA_SHIFT (0U)
4226/*! XA - Execute-only access control
4227 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
4228 * 0b00000001..Associated segment is accessible as data or in execute mode
4229 */
4230#define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK)
4231/*! @} */
4232
4233/*! @name XACCH1 - Execute-only Access Registers */
4234/*! @{ */
4235#define FTFA_XACCH1_XA_MASK (0xFFU)
4236#define FTFA_XACCH1_XA_SHIFT (0U)
4237/*! XA - Execute-only access control
4238 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
4239 * 0b00000001..Associated segment is accessible as data or in execute mode
4240 */
4241#define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK)
4242/*! @} */
4243
4244/*! @name XACCH0 - Execute-only Access Registers */
4245/*! @{ */
4246#define FTFA_XACCH0_XA_MASK (0xFFU)
4247#define FTFA_XACCH0_XA_SHIFT (0U)
4248/*! XA - Execute-only access control
4249 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
4250 * 0b00000001..Associated segment is accessible as data or in execute mode
4251 */
4252#define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK)
4253/*! @} */
4254
4255/*! @name XACCL3 - Execute-only Access Registers */
4256/*! @{ */
4257#define FTFA_XACCL3_XA_MASK (0xFFU)
4258#define FTFA_XACCL3_XA_SHIFT (0U)
4259/*! XA - Execute-only access control
4260 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
4261 * 0b00000001..Associated segment is accessible as data or in execute mode
4262 */
4263#define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK)
4264/*! @} */
4265
4266/*! @name XACCL2 - Execute-only Access Registers */
4267/*! @{ */
4268#define FTFA_XACCL2_XA_MASK (0xFFU)
4269#define FTFA_XACCL2_XA_SHIFT (0U)
4270/*! XA - Execute-only access control
4271 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
4272 * 0b00000001..Associated segment is accessible as data or in execute mode
4273 */
4274#define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK)
4275/*! @} */
4276
4277/*! @name XACCL1 - Execute-only Access Registers */
4278/*! @{ */
4279#define FTFA_XACCL1_XA_MASK (0xFFU)
4280#define FTFA_XACCL1_XA_SHIFT (0U)
4281/*! XA - Execute-only access control
4282 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
4283 * 0b00000001..Associated segment is accessible as data or in execute mode
4284 */
4285#define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK)
4286/*! @} */
4287
4288/*! @name XACCL0 - Execute-only Access Registers */
4289/*! @{ */
4290#define FTFA_XACCL0_XA_MASK (0xFFU)
4291#define FTFA_XACCL0_XA_SHIFT (0U)
4292/*! XA - Execute-only access control
4293 * 0b00000000..Associated segment is accessible in execute mode only (as an instruction fetch)
4294 * 0b00000001..Associated segment is accessible as data or in execute mode
4295 */
4296#define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK)
4297/*! @} */
4298
4299/*! @name SACCH3 - Supervisor-only Access Registers */
4300/*! @{ */
4301#define FTFA_SACCH3_SA_MASK (0xFFU)
4302#define FTFA_SACCH3_SA_SHIFT (0U)
4303/*! SA - Supervisor-only access control
4304 * 0b00000000..Associated segment is accessible in supervisor mode only
4305 * 0b00000001..Associated segment is accessible in user or supervisor mode
4306 */
4307#define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK)
4308/*! @} */
4309
4310/*! @name SACCH2 - Supervisor-only Access Registers */
4311/*! @{ */
4312#define FTFA_SACCH2_SA_MASK (0xFFU)
4313#define FTFA_SACCH2_SA_SHIFT (0U)
4314/*! SA - Supervisor-only access control
4315 * 0b00000000..Associated segment is accessible in supervisor mode only
4316 * 0b00000001..Associated segment is accessible in user or supervisor mode
4317 */
4318#define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK)
4319/*! @} */
4320
4321/*! @name SACCH1 - Supervisor-only Access Registers */
4322/*! @{ */
4323#define FTFA_SACCH1_SA_MASK (0xFFU)
4324#define FTFA_SACCH1_SA_SHIFT (0U)
4325/*! SA - Supervisor-only access control
4326 * 0b00000000..Associated segment is accessible in supervisor mode only
4327 * 0b00000001..Associated segment is accessible in user or supervisor mode
4328 */
4329#define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK)
4330/*! @} */
4331
4332/*! @name SACCH0 - Supervisor-only Access Registers */
4333/*! @{ */
4334#define FTFA_SACCH0_SA_MASK (0xFFU)
4335#define FTFA_SACCH0_SA_SHIFT (0U)
4336/*! SA - Supervisor-only access control
4337 * 0b00000000..Associated segment is accessible in supervisor mode only
4338 * 0b00000001..Associated segment is accessible in user or supervisor mode
4339 */
4340#define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK)
4341/*! @} */
4342
4343/*! @name SACCL3 - Supervisor-only Access Registers */
4344/*! @{ */
4345#define FTFA_SACCL3_SA_MASK (0xFFU)
4346#define FTFA_SACCL3_SA_SHIFT (0U)
4347/*! SA - Supervisor-only access control
4348 * 0b00000000..Associated segment is accessible in supervisor mode only
4349 * 0b00000001..Associated segment is accessible in user or supervisor mode
4350 */
4351#define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK)
4352/*! @} */
4353
4354/*! @name SACCL2 - Supervisor-only Access Registers */
4355/*! @{ */
4356#define FTFA_SACCL2_SA_MASK (0xFFU)
4357#define FTFA_SACCL2_SA_SHIFT (0U)
4358/*! SA - Supervisor-only access control
4359 * 0b00000000..Associated segment is accessible in supervisor mode only
4360 * 0b00000001..Associated segment is accessible in user or supervisor mode
4361 */
4362#define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK)
4363/*! @} */
4364
4365/*! @name SACCL1 - Supervisor-only Access Registers */
4366/*! @{ */
4367#define FTFA_SACCL1_SA_MASK (0xFFU)
4368#define FTFA_SACCL1_SA_SHIFT (0U)
4369/*! SA - Supervisor-only access control
4370 * 0b00000000..Associated segment is accessible in supervisor mode only
4371 * 0b00000001..Associated segment is accessible in user or supervisor mode
4372 */
4373#define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK)
4374/*! @} */
4375
4376/*! @name SACCL0 - Supervisor-only Access Registers */
4377/*! @{ */
4378#define FTFA_SACCL0_SA_MASK (0xFFU)
4379#define FTFA_SACCL0_SA_SHIFT (0U)
4380/*! SA - Supervisor-only access control
4381 * 0b00000000..Associated segment is accessible in supervisor mode only
4382 * 0b00000001..Associated segment is accessible in user or supervisor mode
4383 */
4384#define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK)
4385/*! @} */
4386
4387/*! @name FACSS - Flash Access Segment Size Register */
4388/*! @{ */
4389#define FTFA_FACSS_SGSIZE_MASK (0xFFU)
4390#define FTFA_FACSS_SGSIZE_SHIFT (0U)
4391#define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK)
4392/*! @} */
4393
4394/*! @name FACSN - Flash Access Segment Number Register */
4395/*! @{ */
4396#define FTFA_FACSN_NUMSG_MASK (0xFFU)
4397#define FTFA_FACSN_NUMSG_SHIFT (0U)
4398/*! NUMSG - Number of Segments Indicator
4399 * 0b00100000..Program flash memory is divided into 32 segments (64 Kbytes, 128 Kbytes)
4400 * 0b00101000..Program flash memory is divided into 40 segments (160 Kbytes)
4401 * 0b01000000..Program flash memory is divided into 64 segments (256 Kbytes, 512 Kbytes)
4402 */
4403#define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK)
4404/*! @} */
4405
4406
4407/*!
4408 * @}
4409 */ /* end of group FTFA_Register_Masks */
4410
4411
4412/* FTFA - Peripheral instance base addresses */
4413/** Peripheral FTFA base address */
4414#define FTFA_BASE (0x40020000u)
4415/** Peripheral FTFA base pointer */
4416#define FTFA ((FTFA_Type *)FTFA_BASE)
4417/** Array initializer of FTFA peripheral base addresses */
4418#define FTFA_BASE_ADDRS { FTFA_BASE }
4419/** Array initializer of FTFA peripheral base pointers */
4420#define FTFA_BASE_PTRS { FTFA }
4421/** Interrupt vectors for the FTFA peripheral type */
4422#define FTFA_COMMAND_COMPLETE_IRQS { FTF_IRQn }
4423#define FTFA_READ_COLLISION_IRQS { Read_Collision_IRQn }
4424
4425/*!
4426 * @}
4427 */ /* end of group FTFA_Peripheral_Access_Layer */
4428
4429
4430/* ----------------------------------------------------------------------------
4431 -- FTM Peripheral Access Layer
4432 ---------------------------------------------------------------------------- */
4433
4434/*!
4435 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
4436 * @{
4437 */
4438
4439/** FTM - Register Layout Typedef */
4440typedef struct {
4441 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
4442 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
4443 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
4444 struct { /* offset: 0xC, array step: 0x8 */
4445 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
4446 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
4447 } CONTROLS[8];
4448 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
4449 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
4450 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
4451 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
4452 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
4453 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
4454 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
4455 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
4456 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
4457 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
4458 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
4459 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
4460 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
4461 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
4462 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
4463 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
4464 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
4465 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
4466 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
4467 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
4468} FTM_Type;
4469
4470/* ----------------------------------------------------------------------------
4471 -- FTM Register Masks
4472 ---------------------------------------------------------------------------- */
4473
4474/*!
4475 * @addtogroup FTM_Register_Masks FTM Register Masks
4476 * @{
4477 */
4478
4479/*! @name SC - Status And Control */
4480/*! @{ */
4481#define FTM_SC_PS_MASK (0x7U)
4482#define FTM_SC_PS_SHIFT (0U)
4483/*! PS - Prescale Factor Selection
4484 * 0b000..Divide by 1
4485 * 0b001..Divide by 2
4486 * 0b010..Divide by 4
4487 * 0b011..Divide by 8
4488 * 0b100..Divide by 16
4489 * 0b101..Divide by 32
4490 * 0b110..Divide by 64
4491 * 0b111..Divide by 128
4492 */
4493#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
4494#define FTM_SC_CLKS_MASK (0x18U)
4495#define FTM_SC_CLKS_SHIFT (3U)
4496/*! CLKS - Clock Source Selection
4497 * 0b00..No clock selected. This in effect disables the FTM counter.
4498 * 0b01..System clock
4499 * 0b10..Fixed frequency clock
4500 * 0b11..External clock
4501 */
4502#define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
4503#define FTM_SC_CPWMS_MASK (0x20U)
4504#define FTM_SC_CPWMS_SHIFT (5U)
4505/*! CPWMS - Center-Aligned PWM Select
4506 * 0b0..FTM counter operates in Up Counting mode.
4507 * 0b1..FTM counter operates in Up-Down Counting mode.
4508 */
4509#define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
4510#define FTM_SC_TOIE_MASK (0x40U)
4511#define FTM_SC_TOIE_SHIFT (6U)
4512/*! TOIE - Timer Overflow Interrupt Enable
4513 * 0b0..Disable TOF interrupts. Use software polling.
4514 * 0b1..Enable TOF interrupts. An interrupt is generated when TOF equals one.
4515 */
4516#define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
4517#define FTM_SC_TOF_MASK (0x80U)
4518#define FTM_SC_TOF_SHIFT (7U)
4519/*! TOF - Timer Overflow Flag
4520 * 0b0..FTM counter has not overflowed.
4521 * 0b1..FTM counter has overflowed.
4522 */
4523#define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
4524/*! @} */
4525
4526/*! @name CNT - Counter */
4527/*! @{ */
4528#define FTM_CNT_COUNT_MASK (0xFFFFU)
4529#define FTM_CNT_COUNT_SHIFT (0U)
4530#define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
4531/*! @} */
4532
4533/*! @name MOD - Modulo */
4534/*! @{ */
4535#define FTM_MOD_MOD_MASK (0xFFFFU)
4536#define FTM_MOD_MOD_SHIFT (0U)
4537#define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
4538/*! @} */
4539
4540/*! @name CnSC - Channel (n) Status And Control */
4541/*! @{ */
4542#define FTM_CnSC_DMA_MASK (0x1U)
4543#define FTM_CnSC_DMA_SHIFT (0U)
4544/*! DMA - DMA Enable
4545 * 0b0..Disable DMA transfers.
4546 * 0b1..Enable DMA transfers.
4547 */
4548#define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
4549#define FTM_CnSC_ICRST_MASK (0x2U)
4550#define FTM_CnSC_ICRST_SHIFT (1U)
4551/*! ICRST - FTM counter reset by the selected input capture event.
4552 * 0b0..FTM counter is not reset when the selected channel (n) input event is detected.
4553 * 0b1..FTM counter is reset when the selected channel (n) input event is detected.
4554 */
4555#define FTM_CnSC_ICRST(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ICRST_SHIFT)) & FTM_CnSC_ICRST_MASK)
4556#define FTM_CnSC_ELSA_MASK (0x4U)
4557#define FTM_CnSC_ELSA_SHIFT (2U)
4558#define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
4559#define FTM_CnSC_ELSB_MASK (0x8U)
4560#define FTM_CnSC_ELSB_SHIFT (3U)
4561#define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
4562#define FTM_CnSC_MSA_MASK (0x10U)
4563#define FTM_CnSC_MSA_SHIFT (4U)
4564#define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
4565#define FTM_CnSC_MSB_MASK (0x20U)
4566#define FTM_CnSC_MSB_SHIFT (5U)
4567#define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
4568#define FTM_CnSC_CHIE_MASK (0x40U)
4569#define FTM_CnSC_CHIE_SHIFT (6U)
4570/*! CHIE - Channel Interrupt Enable
4571 * 0b0..Disable channel interrupts. Use software polling.
4572 * 0b1..Enable channel interrupts.
4573 */
4574#define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
4575#define FTM_CnSC_CHF_MASK (0x80U)
4576#define FTM_CnSC_CHF_SHIFT (7U)
4577/*! CHF - Channel Flag
4578 * 0b0..No channel event has occurred.
4579 * 0b1..A channel event has occurred.
4580 */
4581#define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
4582/*! @} */
4583
4584/* The count of FTM_CnSC */
4585#define FTM_CnSC_COUNT (8U)
4586
4587/*! @name CnV - Channel (n) Value */
4588/*! @{ */
4589#define FTM_CnV_VAL_MASK (0xFFFFU)
4590#define FTM_CnV_VAL_SHIFT (0U)
4591#define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
4592/*! @} */
4593
4594/* The count of FTM_CnV */
4595#define FTM_CnV_COUNT (8U)
4596
4597/*! @name CNTIN - Counter Initial Value */
4598/*! @{ */
4599#define FTM_CNTIN_INIT_MASK (0xFFFFU)
4600#define FTM_CNTIN_INIT_SHIFT (0U)
4601#define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
4602/*! @} */
4603
4604/*! @name STATUS - Capture And Compare Status */
4605/*! @{ */
4606#define FTM_STATUS_CH0F_MASK (0x1U)
4607#define FTM_STATUS_CH0F_SHIFT (0U)
4608/*! CH0F - Channel 0 Flag
4609 * 0b0..No channel event has occurred.
4610 * 0b1..A channel event has occurred.
4611 */
4612#define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
4613#define FTM_STATUS_CH1F_MASK (0x2U)
4614#define FTM_STATUS_CH1F_SHIFT (1U)
4615/*! CH1F - Channel 1 Flag
4616 * 0b0..No channel event has occurred.
4617 * 0b1..A channel event has occurred.
4618 */
4619#define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
4620#define FTM_STATUS_CH2F_MASK (0x4U)
4621#define FTM_STATUS_CH2F_SHIFT (2U)
4622/*! CH2F - Channel 2 Flag
4623 * 0b0..No channel event has occurred.
4624 * 0b1..A channel event has occurred.
4625 */
4626#define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
4627#define FTM_STATUS_CH3F_MASK (0x8U)
4628#define FTM_STATUS_CH3F_SHIFT (3U)
4629/*! CH3F - Channel 3 Flag
4630 * 0b0..No channel event has occurred.
4631 * 0b1..A channel event has occurred.
4632 */
4633#define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
4634#define FTM_STATUS_CH4F_MASK (0x10U)
4635#define FTM_STATUS_CH4F_SHIFT (4U)
4636/*! CH4F - Channel 4 Flag
4637 * 0b0..No channel event has occurred.
4638 * 0b1..A channel event has occurred.
4639 */
4640#define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
4641#define FTM_STATUS_CH5F_MASK (0x20U)
4642#define FTM_STATUS_CH5F_SHIFT (5U)
4643/*! CH5F - Channel 5 Flag
4644 * 0b0..No channel event has occurred.
4645 * 0b1..A channel event has occurred.
4646 */
4647#define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
4648#define FTM_STATUS_CH6F_MASK (0x40U)
4649#define FTM_STATUS_CH6F_SHIFT (6U)
4650/*! CH6F - Channel 6 Flag
4651 * 0b0..No channel event has occurred.
4652 * 0b1..A channel event has occurred.
4653 */
4654#define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
4655#define FTM_STATUS_CH7F_MASK (0x80U)
4656#define FTM_STATUS_CH7F_SHIFT (7U)
4657/*! CH7F - Channel 7 Flag
4658 * 0b0..No channel event has occurred.
4659 * 0b1..A channel event has occurred.
4660 */
4661#define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
4662/*! @} */
4663
4664/*! @name MODE - Features Mode Selection */
4665/*! @{ */
4666#define FTM_MODE_FTMEN_MASK (0x1U)
4667#define FTM_MODE_FTMEN_SHIFT (0U)
4668/*! FTMEN - FTM Enable
4669 * 0b0..Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.
4670 * 0b1..All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.
4671 */
4672#define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
4673#define FTM_MODE_INIT_MASK (0x2U)
4674#define FTM_MODE_INIT_SHIFT (1U)
4675#define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
4676#define FTM_MODE_WPDIS_MASK (0x4U)
4677#define FTM_MODE_WPDIS_SHIFT (2U)
4678/*! WPDIS - Write Protection Disable
4679 * 0b0..Write protection is enabled.
4680 * 0b1..Write protection is disabled.
4681 */
4682#define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
4683#define FTM_MODE_PWMSYNC_MASK (0x8U)
4684#define FTM_MODE_PWMSYNC_SHIFT (3U)
4685/*! PWMSYNC - PWM Synchronization Mode
4686 * 0b0..No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization.
4687 * 0b1..Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization.
4688 */
4689#define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
4690#define FTM_MODE_CAPTEST_MASK (0x10U)
4691#define FTM_MODE_CAPTEST_SHIFT (4U)
4692/*! CAPTEST - Capture Test Mode Enable
4693 * 0b0..Capture test mode is disabled.
4694 * 0b1..Capture test mode is enabled.
4695 */
4696#define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
4697#define FTM_MODE_FAULTM_MASK (0x60U)
4698#define FTM_MODE_FAULTM_SHIFT (5U)
4699/*! FAULTM - Fault Control Mode
4700 * 0b00..Fault control is disabled for all channels.
4701 * 0b01..Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing.
4702 * 0b10..Fault control is enabled for all channels, and the selected mode is the manual fault clearing.
4703 * 0b11..Fault control is enabled for all channels, and the selected mode is the automatic fault clearing.
4704 */
4705#define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
4706#define FTM_MODE_FAULTIE_MASK (0x80U)
4707#define FTM_MODE_FAULTIE_SHIFT (7U)
4708/*! FAULTIE - Fault Interrupt Enable
4709 * 0b0..Fault control interrupt is disabled.
4710 * 0b1..Fault control interrupt is enabled.
4711 */
4712#define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
4713/*! @} */
4714
4715/*! @name SYNC - Synchronization */
4716/*! @{ */
4717#define FTM_SYNC_CNTMIN_MASK (0x1U)
4718#define FTM_SYNC_CNTMIN_SHIFT (0U)
4719/*! CNTMIN - Minimum Loading Point Enable
4720 * 0b0..The minimum loading point is disabled.
4721 * 0b1..The minimum loading point is enabled.
4722 */
4723#define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
4724#define FTM_SYNC_CNTMAX_MASK (0x2U)
4725#define FTM_SYNC_CNTMAX_SHIFT (1U)
4726/*! CNTMAX - Maximum Loading Point Enable
4727 * 0b0..The maximum loading point is disabled.
4728 * 0b1..The maximum loading point is enabled.
4729 */
4730#define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
4731#define FTM_SYNC_REINIT_MASK (0x4U)
4732#define FTM_SYNC_REINIT_SHIFT (2U)
4733/*! REINIT - FTM Counter Reinitialization By Synchronization (FTM counter synchronization)
4734 * 0b0..FTM counter continues to count normally.
4735 * 0b1..FTM counter is updated with its initial value when the selected trigger is detected.
4736 */
4737#define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
4738#define FTM_SYNC_SYNCHOM_MASK (0x8U)
4739#define FTM_SYNC_SYNCHOM_SHIFT (3U)
4740/*! SYNCHOM - Output Mask Synchronization
4741 * 0b0..OUTMASK register is updated with the value of its buffer in all rising edges of the system clock.
4742 * 0b1..OUTMASK register is updated with the value of its buffer only by the PWM synchronization.
4743 */
4744#define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
4745#define FTM_SYNC_TRIG0_MASK (0x10U)
4746#define FTM_SYNC_TRIG0_SHIFT (4U)
4747/*! TRIG0 - PWM Synchronization Hardware Trigger 0
4748 * 0b0..Trigger is disabled.
4749 * 0b1..Trigger is enabled.
4750 */
4751#define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
4752#define FTM_SYNC_TRIG1_MASK (0x20U)
4753#define FTM_SYNC_TRIG1_SHIFT (5U)
4754/*! TRIG1 - PWM Synchronization Hardware Trigger 1
4755 * 0b0..Trigger is disabled.
4756 * 0b1..Trigger is enabled.
4757 */
4758#define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
4759#define FTM_SYNC_TRIG2_MASK (0x40U)
4760#define FTM_SYNC_TRIG2_SHIFT (6U)
4761/*! TRIG2 - PWM Synchronization Hardware Trigger 2
4762 * 0b0..Trigger is disabled.
4763 * 0b1..Trigger is enabled.
4764 */
4765#define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
4766#define FTM_SYNC_SWSYNC_MASK (0x80U)
4767#define FTM_SYNC_SWSYNC_SHIFT (7U)
4768/*! SWSYNC - PWM Synchronization Software Trigger
4769 * 0b0..Software trigger is not selected.
4770 * 0b1..Software trigger is selected.
4771 */
4772#define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
4773/*! @} */
4774
4775/*! @name OUTINIT - Initial State For Channels Output */
4776/*! @{ */
4777#define FTM_OUTINIT_CH0OI_MASK (0x1U)
4778#define FTM_OUTINIT_CH0OI_SHIFT (0U)
4779/*! CH0OI - Channel 0 Output Initialization Value
4780 * 0b0..The initialization value is 0.
4781 * 0b1..The initialization value is 1.
4782 */
4783#define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
4784#define FTM_OUTINIT_CH1OI_MASK (0x2U)
4785#define FTM_OUTINIT_CH1OI_SHIFT (1U)
4786/*! CH1OI - Channel 1 Output Initialization Value
4787 * 0b0..The initialization value is 0.
4788 * 0b1..The initialization value is 1.
4789 */
4790#define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
4791#define FTM_OUTINIT_CH2OI_MASK (0x4U)
4792#define FTM_OUTINIT_CH2OI_SHIFT (2U)
4793/*! CH2OI - Channel 2 Output Initialization Value
4794 * 0b0..The initialization value is 0.
4795 * 0b1..The initialization value is 1.
4796 */
4797#define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
4798#define FTM_OUTINIT_CH3OI_MASK (0x8U)
4799#define FTM_OUTINIT_CH3OI_SHIFT (3U)
4800/*! CH3OI - Channel 3 Output Initialization Value
4801 * 0b0..The initialization value is 0.
4802 * 0b1..The initialization value is 1.
4803 */
4804#define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
4805#define FTM_OUTINIT_CH4OI_MASK (0x10U)
4806#define FTM_OUTINIT_CH4OI_SHIFT (4U)
4807/*! CH4OI - Channel 4 Output Initialization Value
4808 * 0b0..The initialization value is 0.
4809 * 0b1..The initialization value is 1.
4810 */
4811#define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
4812#define FTM_OUTINIT_CH5OI_MASK (0x20U)
4813#define FTM_OUTINIT_CH5OI_SHIFT (5U)
4814/*! CH5OI - Channel 5 Output Initialization Value
4815 * 0b0..The initialization value is 0.
4816 * 0b1..The initialization value is 1.
4817 */
4818#define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
4819#define FTM_OUTINIT_CH6OI_MASK (0x40U)
4820#define FTM_OUTINIT_CH6OI_SHIFT (6U)
4821/*! CH6OI - Channel 6 Output Initialization Value
4822 * 0b0..The initialization value is 0.
4823 * 0b1..The initialization value is 1.
4824 */
4825#define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
4826#define FTM_OUTINIT_CH7OI_MASK (0x80U)
4827#define FTM_OUTINIT_CH7OI_SHIFT (7U)
4828/*! CH7OI - Channel 7 Output Initialization Value
4829 * 0b0..The initialization value is 0.
4830 * 0b1..The initialization value is 1.
4831 */
4832#define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
4833/*! @} */
4834
4835/*! @name OUTMASK - Output Mask */
4836/*! @{ */
4837#define FTM_OUTMASK_CH0OM_MASK (0x1U)
4838#define FTM_OUTMASK_CH0OM_SHIFT (0U)
4839/*! CH0OM - Channel 0 Output Mask
4840 * 0b0..Channel output is not masked. It continues to operate normally.
4841 * 0b1..Channel output is masked. It is forced to its inactive state.
4842 */
4843#define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
4844#define FTM_OUTMASK_CH1OM_MASK (0x2U)
4845#define FTM_OUTMASK_CH1OM_SHIFT (1U)
4846/*! CH1OM - Channel 1 Output Mask
4847 * 0b0..Channel output is not masked. It continues to operate normally.
4848 * 0b1..Channel output is masked. It is forced to its inactive state.
4849 */
4850#define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
4851#define FTM_OUTMASK_CH2OM_MASK (0x4U)
4852#define FTM_OUTMASK_CH2OM_SHIFT (2U)
4853/*! CH2OM - Channel 2 Output Mask
4854 * 0b0..Channel output is not masked. It continues to operate normally.
4855 * 0b1..Channel output is masked. It is forced to its inactive state.
4856 */
4857#define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
4858#define FTM_OUTMASK_CH3OM_MASK (0x8U)
4859#define FTM_OUTMASK_CH3OM_SHIFT (3U)
4860/*! CH3OM - Channel 3 Output Mask
4861 * 0b0..Channel output is not masked. It continues to operate normally.
4862 * 0b1..Channel output is masked. It is forced to its inactive state.
4863 */
4864#define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
4865#define FTM_OUTMASK_CH4OM_MASK (0x10U)
4866#define FTM_OUTMASK_CH4OM_SHIFT (4U)
4867/*! CH4OM - Channel 4 Output Mask
4868 * 0b0..Channel output is not masked. It continues to operate normally.
4869 * 0b1..Channel output is masked. It is forced to its inactive state.
4870 */
4871#define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
4872#define FTM_OUTMASK_CH5OM_MASK (0x20U)
4873#define FTM_OUTMASK_CH5OM_SHIFT (5U)
4874/*! CH5OM - Channel 5 Output Mask
4875 * 0b0..Channel output is not masked. It continues to operate normally.
4876 * 0b1..Channel output is masked. It is forced to its inactive state.
4877 */
4878#define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
4879#define FTM_OUTMASK_CH6OM_MASK (0x40U)
4880#define FTM_OUTMASK_CH6OM_SHIFT (6U)
4881/*! CH6OM - Channel 6 Output Mask
4882 * 0b0..Channel output is not masked. It continues to operate normally.
4883 * 0b1..Channel output is masked. It is forced to its inactive state.
4884 */
4885#define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
4886#define FTM_OUTMASK_CH7OM_MASK (0x80U)
4887#define FTM_OUTMASK_CH7OM_SHIFT (7U)
4888/*! CH7OM - Channel 7 Output Mask
4889 * 0b0..Channel output is not masked. It continues to operate normally.
4890 * 0b1..Channel output is masked. It is forced to its inactive state.
4891 */
4892#define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
4893/*! @} */
4894
4895/*! @name COMBINE - Function For Linked Channels */
4896/*! @{ */
4897#define FTM_COMBINE_COMBINE0_MASK (0x1U)
4898#define FTM_COMBINE_COMBINE0_SHIFT (0U)
4899/*! COMBINE0 - Combine Channels For n = 0
4900 * 0b0..Channels (n) and (n+1) are independent.
4901 * 0b1..Channels (n) and (n+1) are combined.
4902 */
4903#define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
4904#define FTM_COMBINE_COMP0_MASK (0x2U)
4905#define FTM_COMBINE_COMP0_SHIFT (1U)
4906/*! COMP0 - Complement Of Channel (n) For n = 0
4907 * 0b0..The channel (n+1) output is the same as the channel (n) output.
4908 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
4909 */
4910#define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
4911#define FTM_COMBINE_DECAPEN0_MASK (0x4U)
4912#define FTM_COMBINE_DECAPEN0_SHIFT (2U)
4913/*! DECAPEN0 - Dual Edge Capture Mode Enable For n = 0
4914 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
4915 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
4916 */
4917#define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
4918#define FTM_COMBINE_DECAP0_MASK (0x8U)
4919#define FTM_COMBINE_DECAP0_SHIFT (3U)
4920/*! DECAP0 - Dual Edge Capture Mode Captures For n = 0
4921 * 0b0..The dual edge captures are inactive.
4922 * 0b1..The dual edge captures are active.
4923 */
4924#define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
4925#define FTM_COMBINE_DTEN0_MASK (0x10U)
4926#define FTM_COMBINE_DTEN0_SHIFT (4U)
4927/*! DTEN0 - Deadtime Enable For n = 0
4928 * 0b0..The deadtime insertion in this pair of channels is disabled.
4929 * 0b1..The deadtime insertion in this pair of channels is enabled.
4930 */
4931#define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
4932#define FTM_COMBINE_SYNCEN0_MASK (0x20U)
4933#define FTM_COMBINE_SYNCEN0_SHIFT (5U)
4934/*! SYNCEN0 - Synchronization Enable For n = 0
4935 * 0b0..The PWM synchronization in this pair of channels is disabled.
4936 * 0b1..The PWM synchronization in this pair of channels is enabled.
4937 */
4938#define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
4939#define FTM_COMBINE_FAULTEN0_MASK (0x40U)
4940#define FTM_COMBINE_FAULTEN0_SHIFT (6U)
4941/*! FAULTEN0 - Fault Control Enable For n = 0
4942 * 0b0..The fault control in this pair of channels is disabled.
4943 * 0b1..The fault control in this pair of channels is enabled.
4944 */
4945#define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
4946#define FTM_COMBINE_COMBINE1_MASK (0x100U)
4947#define FTM_COMBINE_COMBINE1_SHIFT (8U)
4948/*! COMBINE1 - Combine Channels For n = 2
4949 * 0b0..Channels (n) and (n+1) are independent.
4950 * 0b1..Channels (n) and (n+1) are combined.
4951 */
4952#define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
4953#define FTM_COMBINE_COMP1_MASK (0x200U)
4954#define FTM_COMBINE_COMP1_SHIFT (9U)
4955/*! COMP1 - Complement Of Channel (n) For n = 2
4956 * 0b0..The channel (n+1) output is the same as the channel (n) output.
4957 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
4958 */
4959#define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
4960#define FTM_COMBINE_DECAPEN1_MASK (0x400U)
4961#define FTM_COMBINE_DECAPEN1_SHIFT (10U)
4962/*! DECAPEN1 - Dual Edge Capture Mode Enable For n = 2
4963 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
4964 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
4965 */
4966#define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
4967#define FTM_COMBINE_DECAP1_MASK (0x800U)
4968#define FTM_COMBINE_DECAP1_SHIFT (11U)
4969/*! DECAP1 - Dual Edge Capture Mode Captures For n = 2
4970 * 0b0..The dual edge captures are inactive.
4971 * 0b1..The dual edge captures are active.
4972 */
4973#define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
4974#define FTM_COMBINE_DTEN1_MASK (0x1000U)
4975#define FTM_COMBINE_DTEN1_SHIFT (12U)
4976/*! DTEN1 - Deadtime Enable For n = 2
4977 * 0b0..The deadtime insertion in this pair of channels is disabled.
4978 * 0b1..The deadtime insertion in this pair of channels is enabled.
4979 */
4980#define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
4981#define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
4982#define FTM_COMBINE_SYNCEN1_SHIFT (13U)
4983/*! SYNCEN1 - Synchronization Enable For n = 2
4984 * 0b0..The PWM synchronization in this pair of channels is disabled.
4985 * 0b1..The PWM synchronization in this pair of channels is enabled.
4986 */
4987#define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
4988#define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
4989#define FTM_COMBINE_FAULTEN1_SHIFT (14U)
4990/*! FAULTEN1 - Fault Control Enable For n = 2
4991 * 0b0..The fault control in this pair of channels is disabled.
4992 * 0b1..The fault control in this pair of channels is enabled.
4993 */
4994#define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
4995#define FTM_COMBINE_COMBINE2_MASK (0x10000U)
4996#define FTM_COMBINE_COMBINE2_SHIFT (16U)
4997/*! COMBINE2 - Combine Channels For n = 4
4998 * 0b0..Channels (n) and (n+1) are independent.
4999 * 0b1..Channels (n) and (n+1) are combined.
5000 */
5001#define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
5002#define FTM_COMBINE_COMP2_MASK (0x20000U)
5003#define FTM_COMBINE_COMP2_SHIFT (17U)
5004/*! COMP2 - Complement Of Channel (n) For n = 4
5005 * 0b0..The channel (n+1) output is the same as the channel (n) output.
5006 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
5007 */
5008#define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
5009#define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
5010#define FTM_COMBINE_DECAPEN2_SHIFT (18U)
5011/*! DECAPEN2 - Dual Edge Capture Mode Enable For n = 4
5012 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
5013 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
5014 */
5015#define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
5016#define FTM_COMBINE_DECAP2_MASK (0x80000U)
5017#define FTM_COMBINE_DECAP2_SHIFT (19U)
5018/*! DECAP2 - Dual Edge Capture Mode Captures For n = 4
5019 * 0b0..The dual edge captures are inactive.
5020 * 0b1..The dual edge captures are active.
5021 */
5022#define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
5023#define FTM_COMBINE_DTEN2_MASK (0x100000U)
5024#define FTM_COMBINE_DTEN2_SHIFT (20U)
5025/*! DTEN2 - Deadtime Enable For n = 4
5026 * 0b0..The deadtime insertion in this pair of channels is disabled.
5027 * 0b1..The deadtime insertion in this pair of channels is enabled.
5028 */
5029#define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
5030#define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
5031#define FTM_COMBINE_SYNCEN2_SHIFT (21U)
5032/*! SYNCEN2 - Synchronization Enable For n = 4
5033 * 0b0..The PWM synchronization in this pair of channels is disabled.
5034 * 0b1..The PWM synchronization in this pair of channels is enabled.
5035 */
5036#define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
5037#define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
5038#define FTM_COMBINE_FAULTEN2_SHIFT (22U)
5039/*! FAULTEN2 - Fault Control Enable For n = 4
5040 * 0b0..The fault control in this pair of channels is disabled.
5041 * 0b1..The fault control in this pair of channels is enabled.
5042 */
5043#define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
5044#define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
5045#define FTM_COMBINE_COMBINE3_SHIFT (24U)
5046/*! COMBINE3 - Combine Channels For n = 6
5047 * 0b0..Channels (n) and (n+1) are independent.
5048 * 0b1..Channels (n) and (n+1) are combined.
5049 */
5050#define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
5051#define FTM_COMBINE_COMP3_MASK (0x2000000U)
5052#define FTM_COMBINE_COMP3_SHIFT (25U)
5053/*! COMP3 - Complement Of Channel (n) for n = 6
5054 * 0b0..The channel (n+1) output is the same as the channel (n) output.
5055 * 0b1..The channel (n+1) output is the complement of the channel (n) output.
5056 */
5057#define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
5058#define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
5059#define FTM_COMBINE_DECAPEN3_SHIFT (26U)
5060/*! DECAPEN3 - Dual Edge Capture Mode Enable For n = 6
5061 * 0b0..The Dual Edge Capture mode in this pair of channels is disabled.
5062 * 0b1..The Dual Edge Capture mode in this pair of channels is enabled.
5063 */
5064#define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
5065#define FTM_COMBINE_DECAP3_MASK (0x8000000U)
5066#define FTM_COMBINE_DECAP3_SHIFT (27U)
5067/*! DECAP3 - Dual Edge Capture Mode Captures For n = 6
5068 * 0b0..The dual edge captures are inactive.
5069 * 0b1..The dual edge captures are active.
5070 */
5071#define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
5072#define FTM_COMBINE_DTEN3_MASK (0x10000000U)
5073#define FTM_COMBINE_DTEN3_SHIFT (28U)
5074/*! DTEN3 - Deadtime Enable For n = 6
5075 * 0b0..The deadtime insertion in this pair of channels is disabled.
5076 * 0b1..The deadtime insertion in this pair of channels is enabled.
5077 */
5078#define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
5079#define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
5080#define FTM_COMBINE_SYNCEN3_SHIFT (29U)
5081/*! SYNCEN3 - Synchronization Enable For n = 6
5082 * 0b0..The PWM synchronization in this pair of channels is disabled.
5083 * 0b1..The PWM synchronization in this pair of channels is enabled.
5084 */
5085#define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
5086#define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
5087#define FTM_COMBINE_FAULTEN3_SHIFT (30U)
5088/*! FAULTEN3 - Fault Control Enable For n = 6
5089 * 0b0..The fault control in this pair of channels is disabled.
5090 * 0b1..The fault control in this pair of channels is enabled.
5091 */
5092#define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
5093/*! @} */
5094
5095/*! @name DEADTIME - Deadtime Insertion Control */
5096/*! @{ */
5097#define FTM_DEADTIME_DTVAL_MASK (0x3FU)
5098#define FTM_DEADTIME_DTVAL_SHIFT (0U)
5099#define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
5100#define FTM_DEADTIME_DTPS_MASK (0xC0U)
5101#define FTM_DEADTIME_DTPS_SHIFT (6U)
5102/*! DTPS - Deadtime Prescaler Value
5103 * 0b0x..Divide the system clock by 1.
5104 * 0b10..Divide the system clock by 4.
5105 * 0b11..Divide the system clock by 16.
5106 */
5107#define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
5108/*! @} */
5109
5110/*! @name EXTTRIG - FTM External Trigger */
5111/*! @{ */
5112#define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
5113#define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
5114/*! CH2TRIG - Channel 2 Trigger Enable
5115 * 0b0..The generation of the channel trigger is disabled.
5116 * 0b1..The generation of the channel trigger is enabled.
5117 */
5118#define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
5119#define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
5120#define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
5121/*! CH3TRIG - Channel 3 Trigger Enable
5122 * 0b0..The generation of the channel trigger is disabled.
5123 * 0b1..The generation of the channel trigger is enabled.
5124 */
5125#define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
5126#define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
5127#define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
5128/*! CH4TRIG - Channel 4 Trigger Enable
5129 * 0b0..The generation of the channel trigger is disabled.
5130 * 0b1..The generation of the channel trigger is enabled.
5131 */
5132#define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
5133#define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
5134#define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
5135/*! CH5TRIG - Channel 5 Trigger Enable
5136 * 0b0..The generation of the channel trigger is disabled.
5137 * 0b1..The generation of the channel trigger is enabled.
5138 */
5139#define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
5140#define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
5141#define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
5142/*! CH0TRIG - Channel 0 Trigger Enable
5143 * 0b0..The generation of the channel trigger is disabled.
5144 * 0b1..The generation of the channel trigger is enabled.
5145 */
5146#define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
5147#define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
5148#define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
5149/*! CH1TRIG - Channel 1 Trigger Enable
5150 * 0b0..The generation of the channel trigger is disabled.
5151 * 0b1..The generation of the channel trigger is enabled.
5152 */
5153#define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
5154#define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
5155#define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
5156/*! INITTRIGEN - Initialization Trigger Enable
5157 * 0b0..The generation of initialization trigger is disabled.
5158 * 0b1..The generation of initialization trigger is enabled.
5159 */
5160#define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
5161#define FTM_EXTTRIG_TRIGF_MASK (0x80U)
5162#define FTM_EXTTRIG_TRIGF_SHIFT (7U)
5163/*! TRIGF - Channel Trigger Flag
5164 * 0b0..No channel trigger was generated.
5165 * 0b1..A channel trigger was generated.
5166 */
5167#define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
5168/*! @} */
5169
5170/*! @name POL - Channels Polarity */
5171/*! @{ */
5172#define FTM_POL_POL0_MASK (0x1U)
5173#define FTM_POL_POL0_SHIFT (0U)
5174/*! POL0 - Channel 0 Polarity
5175 * 0b0..The channel polarity is active high.
5176 * 0b1..The channel polarity is active low.
5177 */
5178#define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
5179#define FTM_POL_POL1_MASK (0x2U)
5180#define FTM_POL_POL1_SHIFT (1U)
5181/*! POL1 - Channel 1 Polarity
5182 * 0b0..The channel polarity is active high.
5183 * 0b1..The channel polarity is active low.
5184 */
5185#define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
5186#define FTM_POL_POL2_MASK (0x4U)
5187#define FTM_POL_POL2_SHIFT (2U)
5188/*! POL2 - Channel 2 Polarity
5189 * 0b0..The channel polarity is active high.
5190 * 0b1..The channel polarity is active low.
5191 */
5192#define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
5193#define FTM_POL_POL3_MASK (0x8U)
5194#define FTM_POL_POL3_SHIFT (3U)
5195/*! POL3 - Channel 3 Polarity
5196 * 0b0..The channel polarity is active high.
5197 * 0b1..The channel polarity is active low.
5198 */
5199#define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
5200#define FTM_POL_POL4_MASK (0x10U)
5201#define FTM_POL_POL4_SHIFT (4U)
5202/*! POL4 - Channel 4 Polarity
5203 * 0b0..The channel polarity is active high.
5204 * 0b1..The channel polarity is active low.
5205 */
5206#define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
5207#define FTM_POL_POL5_MASK (0x20U)
5208#define FTM_POL_POL5_SHIFT (5U)
5209/*! POL5 - Channel 5 Polarity
5210 * 0b0..The channel polarity is active high.
5211 * 0b1..The channel polarity is active low.
5212 */
5213#define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
5214#define FTM_POL_POL6_MASK (0x40U)
5215#define FTM_POL_POL6_SHIFT (6U)
5216/*! POL6 - Channel 6 Polarity
5217 * 0b0..The channel polarity is active high.
5218 * 0b1..The channel polarity is active low.
5219 */
5220#define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
5221#define FTM_POL_POL7_MASK (0x80U)
5222#define FTM_POL_POL7_SHIFT (7U)
5223/*! POL7 - Channel 7 Polarity
5224 * 0b0..The channel polarity is active high.
5225 * 0b1..The channel polarity is active low.
5226 */
5227#define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
5228/*! @} */
5229
5230/*! @name FMS - Fault Mode Status */
5231/*! @{ */
5232#define FTM_FMS_FAULTF0_MASK (0x1U)
5233#define FTM_FMS_FAULTF0_SHIFT (0U)
5234/*! FAULTF0 - Fault Detection Flag 0
5235 * 0b0..No fault condition was detected at the fault input.
5236 * 0b1..A fault condition was detected at the fault input.
5237 */
5238#define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
5239#define FTM_FMS_FAULTF1_MASK (0x2U)
5240#define FTM_FMS_FAULTF1_SHIFT (1U)
5241/*! FAULTF1 - Fault Detection Flag 1
5242 * 0b0..No fault condition was detected at the fault input.
5243 * 0b1..A fault condition was detected at the fault input.
5244 */
5245#define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
5246#define FTM_FMS_FAULTF2_MASK (0x4U)
5247#define FTM_FMS_FAULTF2_SHIFT (2U)
5248/*! FAULTF2 - Fault Detection Flag 2
5249 * 0b0..No fault condition was detected at the fault input.
5250 * 0b1..A fault condition was detected at the fault input.
5251 */
5252#define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
5253#define FTM_FMS_FAULTF3_MASK (0x8U)
5254#define FTM_FMS_FAULTF3_SHIFT (3U)
5255/*! FAULTF3 - Fault Detection Flag 3
5256 * 0b0..No fault condition was detected at the fault input.
5257 * 0b1..A fault condition was detected at the fault input.
5258 */
5259#define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
5260#define FTM_FMS_FAULTIN_MASK (0x20U)
5261#define FTM_FMS_FAULTIN_SHIFT (5U)
5262/*! FAULTIN - Fault Inputs
5263 * 0b0..The logic OR of the enabled fault inputs is 0.
5264 * 0b1..The logic OR of the enabled fault inputs is 1.
5265 */
5266#define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
5267#define FTM_FMS_WPEN_MASK (0x40U)
5268#define FTM_FMS_WPEN_SHIFT (6U)
5269/*! WPEN - Write Protection Enable
5270 * 0b0..Write protection is disabled. Write protected bits can be written.
5271 * 0b1..Write protection is enabled. Write protected bits cannot be written.
5272 */
5273#define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
5274#define FTM_FMS_FAULTF_MASK (0x80U)
5275#define FTM_FMS_FAULTF_SHIFT (7U)
5276/*! FAULTF - Fault Detection Flag
5277 * 0b0..No fault condition was detected.
5278 * 0b1..A fault condition was detected.
5279 */
5280#define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
5281/*! @} */
5282
5283/*! @name FILTER - Input Capture Filter Control */
5284/*! @{ */
5285#define FTM_FILTER_CH0FVAL_MASK (0xFU)
5286#define FTM_FILTER_CH0FVAL_SHIFT (0U)
5287#define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
5288#define FTM_FILTER_CH1FVAL_MASK (0xF0U)
5289#define FTM_FILTER_CH1FVAL_SHIFT (4U)
5290#define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
5291#define FTM_FILTER_CH2FVAL_MASK (0xF00U)
5292#define FTM_FILTER_CH2FVAL_SHIFT (8U)
5293#define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
5294#define FTM_FILTER_CH3FVAL_MASK (0xF000U)
5295#define FTM_FILTER_CH3FVAL_SHIFT (12U)
5296#define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
5297/*! @} */
5298
5299/*! @name FLTCTRL - Fault Control */
5300/*! @{ */
5301#define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
5302#define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
5303/*! FAULT0EN - Fault Input 0 Enable
5304 * 0b0..Fault input is disabled.
5305 * 0b1..Fault input is enabled.
5306 */
5307#define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
5308#define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
5309#define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
5310/*! FAULT1EN - Fault Input 1 Enable
5311 * 0b0..Fault input is disabled.
5312 * 0b1..Fault input is enabled.
5313 */
5314#define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
5315#define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
5316#define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
5317/*! FAULT2EN - Fault Input 2 Enable
5318 * 0b0..Fault input is disabled.
5319 * 0b1..Fault input is enabled.
5320 */
5321#define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
5322#define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
5323#define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
5324/*! FAULT3EN - Fault Input 3 Enable
5325 * 0b0..Fault input is disabled.
5326 * 0b1..Fault input is enabled.
5327 */
5328#define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
5329#define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
5330#define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
5331/*! FFLTR0EN - Fault Input 0 Filter Enable
5332 * 0b0..Fault input filter is disabled.
5333 * 0b1..Fault input filter is enabled.
5334 */
5335#define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
5336#define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
5337#define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
5338/*! FFLTR1EN - Fault Input 1 Filter Enable
5339 * 0b0..Fault input filter is disabled.
5340 * 0b1..Fault input filter is enabled.
5341 */
5342#define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
5343#define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
5344#define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
5345/*! FFLTR2EN - Fault Input 2 Filter Enable
5346 * 0b0..Fault input filter is disabled.
5347 * 0b1..Fault input filter is enabled.
5348 */
5349#define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
5350#define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
5351#define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
5352/*! FFLTR3EN - Fault Input 3 Filter Enable
5353 * 0b0..Fault input filter is disabled.
5354 * 0b1..Fault input filter is enabled.
5355 */
5356#define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
5357#define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
5358#define FTM_FLTCTRL_FFVAL_SHIFT (8U)
5359#define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
5360/*! @} */
5361
5362/*! @name QDCTRL - Quadrature Decoder Control And Status */
5363/*! @{ */
5364#define FTM_QDCTRL_QUADEN_MASK (0x1U)
5365#define FTM_QDCTRL_QUADEN_SHIFT (0U)
5366/*! QUADEN - Quadrature Decoder Mode Enable
5367 * 0b0..Quadrature Decoder mode is disabled.
5368 * 0b1..Quadrature Decoder mode is enabled.
5369 */
5370#define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
5371#define FTM_QDCTRL_TOFDIR_MASK (0x2U)
5372#define FTM_QDCTRL_TOFDIR_SHIFT (1U)
5373/*! TOFDIR - Timer Overflow Direction In Quadrature Decoder Mode
5374 * 0b0..TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register).
5375 * 0b1..TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register).
5376 */
5377#define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
5378#define FTM_QDCTRL_QUADIR_MASK (0x4U)
5379#define FTM_QDCTRL_QUADIR_SHIFT (2U)
5380/*! QUADIR - FTM Counter Direction In Quadrature Decoder Mode
5381 * 0b0..Counting direction is decreasing (FTM counter decrement).
5382 * 0b1..Counting direction is increasing (FTM counter increment).
5383 */
5384#define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
5385#define FTM_QDCTRL_QUADMODE_MASK (0x8U)
5386#define FTM_QDCTRL_QUADMODE_SHIFT (3U)
5387/*! QUADMODE - Quadrature Decoder Mode
5388 * 0b0..Phase A and phase B encoding mode.
5389 * 0b1..Count and direction encoding mode.
5390 */
5391#define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
5392#define FTM_QDCTRL_PHBPOL_MASK (0x10U)
5393#define FTM_QDCTRL_PHBPOL_SHIFT (4U)
5394/*! PHBPOL - Phase B Input Polarity
5395 * 0b0..Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal.
5396 * 0b1..Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal.
5397 */
5398#define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
5399#define FTM_QDCTRL_PHAPOL_MASK (0x20U)
5400#define FTM_QDCTRL_PHAPOL_SHIFT (5U)
5401/*! PHAPOL - Phase A Input Polarity
5402 * 0b0..Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal.
5403 * 0b1..Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal.
5404 */
5405#define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
5406#define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
5407#define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
5408/*! PHBFLTREN - Phase B Input Filter Enable
5409 * 0b0..Phase B input filter is disabled.
5410 * 0b1..Phase B input filter is enabled.
5411 */
5412#define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
5413#define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
5414#define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
5415/*! PHAFLTREN - Phase A Input Filter Enable
5416 * 0b0..Phase A input filter is disabled.
5417 * 0b1..Phase A input filter is enabled.
5418 */
5419#define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
5420/*! @} */
5421
5422/*! @name CONF - Configuration */
5423/*! @{ */
5424#define FTM_CONF_NUMTOF_MASK (0x1FU)
5425#define FTM_CONF_NUMTOF_SHIFT (0U)
5426#define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
5427#define FTM_CONF_BDMMODE_MASK (0xC0U)
5428#define FTM_CONF_BDMMODE_SHIFT (6U)
5429#define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
5430#define FTM_CONF_GTBEEN_MASK (0x200U)
5431#define FTM_CONF_GTBEEN_SHIFT (9U)
5432/*! GTBEEN - Global Time Base Enable
5433 * 0b0..Use of an external global time base is disabled.
5434 * 0b1..Use of an external global time base is enabled.
5435 */
5436#define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
5437#define FTM_CONF_GTBEOUT_MASK (0x400U)
5438#define FTM_CONF_GTBEOUT_SHIFT (10U)
5439/*! GTBEOUT - Global Time Base Output
5440 * 0b0..A global time base signal generation is disabled.
5441 * 0b1..A global time base signal generation is enabled.
5442 */
5443#define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
5444/*! @} */
5445
5446/*! @name FLTPOL - FTM Fault Input Polarity */
5447/*! @{ */
5448#define FTM_FLTPOL_FLT0POL_MASK (0x1U)
5449#define FTM_FLTPOL_FLT0POL_SHIFT (0U)
5450/*! FLT0POL - Fault Input 0 Polarity
5451 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
5452 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
5453 */
5454#define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
5455#define FTM_FLTPOL_FLT1POL_MASK (0x2U)
5456#define FTM_FLTPOL_FLT1POL_SHIFT (1U)
5457/*! FLT1POL - Fault Input 1 Polarity
5458 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
5459 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
5460 */
5461#define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
5462#define FTM_FLTPOL_FLT2POL_MASK (0x4U)
5463#define FTM_FLTPOL_FLT2POL_SHIFT (2U)
5464/*! FLT2POL - Fault Input 2 Polarity
5465 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
5466 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
5467 */
5468#define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
5469#define FTM_FLTPOL_FLT3POL_MASK (0x8U)
5470#define FTM_FLTPOL_FLT3POL_SHIFT (3U)
5471/*! FLT3POL - Fault Input 3 Polarity
5472 * 0b0..The fault input polarity is active high. A 1 at the fault input indicates a fault.
5473 * 0b1..The fault input polarity is active low. A 0 at the fault input indicates a fault.
5474 */
5475#define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
5476/*! @} */
5477
5478/*! @name SYNCONF - Synchronization Configuration */
5479/*! @{ */
5480#define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
5481#define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
5482/*! HWTRIGMODE - Hardware Trigger Mode
5483 * 0b0..FTM clears the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
5484 * 0b1..FTM does not clear the TRIGj bit when the hardware trigger j is detected, where j = 0, 1,2.
5485 */
5486#define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
5487#define FTM_SYNCONF_CNTINC_MASK (0x4U)
5488#define FTM_SYNCONF_CNTINC_SHIFT (2U)
5489/*! CNTINC - CNTIN Register Synchronization
5490 * 0b0..CNTIN register is updated with its buffer value at all rising edges of system clock.
5491 * 0b1..CNTIN register is updated with its buffer value by the PWM synchronization.
5492 */
5493#define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
5494#define FTM_SYNCONF_INVC_MASK (0x10U)
5495#define FTM_SYNCONF_INVC_SHIFT (4U)
5496/*! INVC - INVCTRL Register Synchronization
5497 * 0b0..INVCTRL register is updated with its buffer value at all rising edges of system clock.
5498 * 0b1..INVCTRL register is updated with its buffer value by the PWM synchronization.
5499 */
5500#define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
5501#define FTM_SYNCONF_SWOC_MASK (0x20U)
5502#define FTM_SYNCONF_SWOC_SHIFT (5U)
5503/*! SWOC - SWOCTRL Register Synchronization
5504 * 0b0..SWOCTRL register is updated with its buffer value at all rising edges of system clock.
5505 * 0b1..SWOCTRL register is updated with its buffer value by the PWM synchronization.
5506 */
5507#define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
5508#define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
5509#define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
5510/*! SYNCMODE - Synchronization Mode
5511 * 0b0..Legacy PWM synchronization is selected.
5512 * 0b1..Enhanced PWM synchronization is selected.
5513 */
5514#define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
5515#define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
5516#define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
5517/*! SWRSTCNT
5518 * 0b0..The software trigger does not activate the FTM counter synchronization.
5519 * 0b1..The software trigger activates the FTM counter synchronization.
5520 */
5521#define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
5522#define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
5523#define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
5524/*! SWWRBUF
5525 * 0b0..The software trigger does not activate MOD, CNTIN, and CV registers synchronization.
5526 * 0b1..The software trigger activates MOD, CNTIN, and CV registers synchronization.
5527 */
5528#define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
5529#define FTM_SYNCONF_SWOM_MASK (0x400U)
5530#define FTM_SYNCONF_SWOM_SHIFT (10U)
5531/*! SWOM
5532 * 0b0..The software trigger does not activate the OUTMASK register synchronization.
5533 * 0b1..The software trigger activates the OUTMASK register synchronization.
5534 */
5535#define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
5536#define FTM_SYNCONF_SWINVC_MASK (0x800U)
5537#define FTM_SYNCONF_SWINVC_SHIFT (11U)
5538/*! SWINVC
5539 * 0b0..The software trigger does not activate the INVCTRL register synchronization.
5540 * 0b1..The software trigger activates the INVCTRL register synchronization.
5541 */
5542#define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
5543#define FTM_SYNCONF_SWSOC_MASK (0x1000U)
5544#define FTM_SYNCONF_SWSOC_SHIFT (12U)
5545/*! SWSOC
5546 * 0b0..The software trigger does not activate the SWOCTRL register synchronization.
5547 * 0b1..The software trigger activates the SWOCTRL register synchronization.
5548 */
5549#define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
5550#define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
5551#define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
5552/*! HWRSTCNT
5553 * 0b0..A hardware trigger does not activate the FTM counter synchronization.
5554 * 0b1..A hardware trigger activates the FTM counter synchronization.
5555 */
5556#define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
5557#define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
5558#define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
5559/*! HWWRBUF
5560 * 0b0..A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization.
5561 * 0b1..A hardware trigger activates MOD, CNTIN, and CV registers synchronization.
5562 */
5563#define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
5564#define FTM_SYNCONF_HWOM_MASK (0x40000U)
5565#define FTM_SYNCONF_HWOM_SHIFT (18U)
5566/*! HWOM
5567 * 0b0..A hardware trigger does not activate the OUTMASK register synchronization.
5568 * 0b1..A hardware trigger activates the OUTMASK register synchronization.
5569 */
5570#define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
5571#define FTM_SYNCONF_HWINVC_MASK (0x80000U)
5572#define FTM_SYNCONF_HWINVC_SHIFT (19U)
5573/*! HWINVC
5574 * 0b0..A hardware trigger does not activate the INVCTRL register synchronization.
5575 * 0b1..A hardware trigger activates the INVCTRL register synchronization.
5576 */
5577#define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
5578#define FTM_SYNCONF_HWSOC_MASK (0x100000U)
5579#define FTM_SYNCONF_HWSOC_SHIFT (20U)
5580/*! HWSOC
5581 * 0b0..A hardware trigger does not activate the SWOCTRL register synchronization.
5582 * 0b1..A hardware trigger activates the SWOCTRL register synchronization.
5583 */
5584#define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
5585/*! @} */
5586
5587/*! @name INVCTRL - FTM Inverting Control */
5588/*! @{ */
5589#define FTM_INVCTRL_INV0EN_MASK (0x1U)
5590#define FTM_INVCTRL_INV0EN_SHIFT (0U)
5591/*! INV0EN - Pair Channels 0 Inverting Enable
5592 * 0b0..Inverting is disabled.
5593 * 0b1..Inverting is enabled.
5594 */
5595#define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
5596#define FTM_INVCTRL_INV1EN_MASK (0x2U)
5597#define FTM_INVCTRL_INV1EN_SHIFT (1U)
5598/*! INV1EN - Pair Channels 1 Inverting Enable
5599 * 0b0..Inverting is disabled.
5600 * 0b1..Inverting is enabled.
5601 */
5602#define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
5603#define FTM_INVCTRL_INV2EN_MASK (0x4U)
5604#define FTM_INVCTRL_INV2EN_SHIFT (2U)
5605/*! INV2EN - Pair Channels 2 Inverting Enable
5606 * 0b0..Inverting is disabled.
5607 * 0b1..Inverting is enabled.
5608 */
5609#define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
5610#define FTM_INVCTRL_INV3EN_MASK (0x8U)
5611#define FTM_INVCTRL_INV3EN_SHIFT (3U)
5612/*! INV3EN - Pair Channels 3 Inverting Enable
5613 * 0b0..Inverting is disabled.
5614 * 0b1..Inverting is enabled.
5615 */
5616#define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
5617/*! @} */
5618
5619/*! @name SWOCTRL - FTM Software Output Control */
5620/*! @{ */
5621#define FTM_SWOCTRL_CH0OC_MASK (0x1U)
5622#define FTM_SWOCTRL_CH0OC_SHIFT (0U)
5623/*! CH0OC - Channel 0 Software Output Control Enable
5624 * 0b0..The channel output is not affected by software output control.
5625 * 0b1..The channel output is affected by software output control.
5626 */
5627#define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
5628#define FTM_SWOCTRL_CH1OC_MASK (0x2U)
5629#define FTM_SWOCTRL_CH1OC_SHIFT (1U)
5630/*! CH1OC - Channel 1 Software Output Control Enable
5631 * 0b0..The channel output is not affected by software output control.
5632 * 0b1..The channel output is affected by software output control.
5633 */
5634#define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
5635#define FTM_SWOCTRL_CH2OC_MASK (0x4U)
5636#define FTM_SWOCTRL_CH2OC_SHIFT (2U)
5637/*! CH2OC - Channel 2 Software Output Control Enable
5638 * 0b0..The channel output is not affected by software output control.
5639 * 0b1..The channel output is affected by software output control.
5640 */
5641#define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
5642#define FTM_SWOCTRL_CH3OC_MASK (0x8U)
5643#define FTM_SWOCTRL_CH3OC_SHIFT (3U)
5644/*! CH3OC - Channel 3 Software Output Control Enable
5645 * 0b0..The channel output is not affected by software output control.
5646 * 0b1..The channel output is affected by software output control.
5647 */
5648#define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
5649#define FTM_SWOCTRL_CH4OC_MASK (0x10U)
5650#define FTM_SWOCTRL_CH4OC_SHIFT (4U)
5651/*! CH4OC - Channel 4 Software Output Control Enable
5652 * 0b0..The channel output is not affected by software output control.
5653 * 0b1..The channel output is affected by software output control.
5654 */
5655#define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
5656#define FTM_SWOCTRL_CH5OC_MASK (0x20U)
5657#define FTM_SWOCTRL_CH5OC_SHIFT (5U)
5658/*! CH5OC - Channel 5 Software Output Control Enable
5659 * 0b0..The channel output is not affected by software output control.
5660 * 0b1..The channel output is affected by software output control.
5661 */
5662#define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
5663#define FTM_SWOCTRL_CH6OC_MASK (0x40U)
5664#define FTM_SWOCTRL_CH6OC_SHIFT (6U)
5665/*! CH6OC - Channel 6 Software Output Control Enable
5666 * 0b0..The channel output is not affected by software output control.
5667 * 0b1..The channel output is affected by software output control.
5668 */
5669#define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
5670#define FTM_SWOCTRL_CH7OC_MASK (0x80U)
5671#define FTM_SWOCTRL_CH7OC_SHIFT (7U)
5672/*! CH7OC - Channel 7 Software Output Control Enable
5673 * 0b0..The channel output is not affected by software output control.
5674 * 0b1..The channel output is affected by software output control.
5675 */
5676#define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
5677#define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
5678#define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
5679/*! CH0OCV - Channel 0 Software Output Control Value
5680 * 0b0..The software output control forces 0 to the channel output.
5681 * 0b1..The software output control forces 1 to the channel output.
5682 */
5683#define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
5684#define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
5685#define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
5686/*! CH1OCV - Channel 1 Software Output Control Value
5687 * 0b0..The software output control forces 0 to the channel output.
5688 * 0b1..The software output control forces 1 to the channel output.
5689 */
5690#define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
5691#define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
5692#define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
5693/*! CH2OCV - Channel 2 Software Output Control Value
5694 * 0b0..The software output control forces 0 to the channel output.
5695 * 0b1..The software output control forces 1 to the channel output.
5696 */
5697#define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
5698#define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
5699#define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
5700/*! CH3OCV - Channel 3 Software Output Control Value
5701 * 0b0..The software output control forces 0 to the channel output.
5702 * 0b1..The software output control forces 1 to the channel output.
5703 */
5704#define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
5705#define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
5706#define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
5707/*! CH4OCV - Channel 4 Software Output Control Value
5708 * 0b0..The software output control forces 0 to the channel output.
5709 * 0b1..The software output control forces 1 to the channel output.
5710 */
5711#define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
5712#define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
5713#define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
5714/*! CH5OCV - Channel 5 Software Output Control Value
5715 * 0b0..The software output control forces 0 to the channel output.
5716 * 0b1..The software output control forces 1 to the channel output.
5717 */
5718#define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
5719#define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
5720#define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
5721/*! CH6OCV - Channel 6 Software Output Control Value
5722 * 0b0..The software output control forces 0 to the channel output.
5723 * 0b1..The software output control forces 1 to the channel output.
5724 */
5725#define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
5726#define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
5727#define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
5728/*! CH7OCV - Channel 7 Software Output Control Value
5729 * 0b0..The software output control forces 0 to the channel output.
5730 * 0b1..The software output control forces 1 to the channel output.
5731 */
5732#define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
5733/*! @} */
5734
5735/*! @name PWMLOAD - FTM PWM Load */
5736/*! @{ */
5737#define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
5738#define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
5739/*! CH0SEL - Channel 0 Select
5740 * 0b0..Do not include the channel in the matching process.
5741 * 0b1..Include the channel in the matching process.
5742 */
5743#define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
5744#define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
5745#define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
5746/*! CH1SEL - Channel 1 Select
5747 * 0b0..Do not include the channel in the matching process.
5748 * 0b1..Include the channel in the matching process.
5749 */
5750#define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
5751#define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
5752#define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
5753/*! CH2SEL - Channel 2 Select
5754 * 0b0..Do not include the channel in the matching process.
5755 * 0b1..Include the channel in the matching process.
5756 */
5757#define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
5758#define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
5759#define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
5760/*! CH3SEL - Channel 3 Select
5761 * 0b0..Do not include the channel in the matching process.
5762 * 0b1..Include the channel in the matching process.
5763 */
5764#define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
5765#define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
5766#define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
5767/*! CH4SEL - Channel 4 Select
5768 * 0b0..Do not include the channel in the matching process.
5769 * 0b1..Include the channel in the matching process.
5770 */
5771#define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
5772#define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
5773#define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
5774/*! CH5SEL - Channel 5 Select
5775 * 0b0..Do not include the channel in the matching process.
5776 * 0b1..Include the channel in the matching process.
5777 */
5778#define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
5779#define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
5780#define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
5781/*! CH6SEL - Channel 6 Select
5782 * 0b0..Do not include the channel in the matching process.
5783 * 0b1..Include the channel in the matching process.
5784 */
5785#define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
5786#define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
5787#define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
5788/*! CH7SEL - Channel 7 Select
5789 * 0b0..Do not include the channel in the matching process.
5790 * 0b1..Include the channel in the matching process.
5791 */
5792#define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
5793#define FTM_PWMLOAD_LDOK_MASK (0x200U)
5794#define FTM_PWMLOAD_LDOK_SHIFT (9U)
5795/*! LDOK - Load Enable
5796 * 0b0..Loading updated values is disabled.
5797 * 0b1..Loading updated values is enabled.
5798 */
5799#define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
5800/*! @} */
5801
5802
5803/*!
5804 * @}
5805 */ /* end of group FTM_Register_Masks */
5806
5807
5808/* FTM - Peripheral instance base addresses */
5809/** Peripheral FTM0 base address */
5810#define FTM0_BASE (0x40038000u)
5811/** Peripheral FTM0 base pointer */
5812#define FTM0 ((FTM_Type *)FTM0_BASE)
5813/** Peripheral FTM1 base address */
5814#define FTM1_BASE (0x40039000u)
5815/** Peripheral FTM1 base pointer */
5816#define FTM1 ((FTM_Type *)FTM1_BASE)
5817/** Peripheral FTM2 base address */
5818#define FTM2_BASE (0x4003A000u)
5819/** Peripheral FTM2 base pointer */
5820#define FTM2 ((FTM_Type *)FTM2_BASE)
5821/** Array initializer of FTM peripheral base addresses */
5822#define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE }
5823/** Array initializer of FTM peripheral base pointers */
5824#define FTM_BASE_PTRS { FTM0, FTM1, FTM2 }
5825/** Interrupt vectors for the FTM peripheral type */
5826#define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn }
5827
5828/*!
5829 * @}
5830 */ /* end of group FTM_Peripheral_Access_Layer */
5831
5832
5833/* ----------------------------------------------------------------------------
5834 -- GPIO Peripheral Access Layer
5835 ---------------------------------------------------------------------------- */
5836
5837/*!
5838 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
5839 * @{
5840 */
5841
5842/** GPIO - Register Layout Typedef */
5843typedef struct {
5844 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
5845 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
5846 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
5847 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
5848 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
5849 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
5850} GPIO_Type;
5851
5852/* ----------------------------------------------------------------------------
5853 -- GPIO Register Masks
5854 ---------------------------------------------------------------------------- */
5855
5856/*!
5857 * @addtogroup GPIO_Register_Masks GPIO Register Masks
5858 * @{
5859 */
5860
5861/*! @name PDOR - Port Data Output Register */
5862/*! @{ */
5863#define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
5864#define GPIO_PDOR_PDO_SHIFT (0U)
5865/*! PDO - Port Data Output
5866 * 0b00000000000000000000000000000000..Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
5867 * 0b00000000000000000000000000000001..Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
5868 */
5869#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
5870/*! @} */
5871
5872/*! @name PSOR - Port Set Output Register */
5873/*! @{ */
5874#define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
5875#define GPIO_PSOR_PTSO_SHIFT (0U)
5876/*! PTSO - Port Set Output
5877 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
5878 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to logic 1.
5879 */
5880#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
5881/*! @} */
5882
5883/*! @name PCOR - Port Clear Output Register */
5884/*! @{ */
5885#define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
5886#define GPIO_PCOR_PTCO_SHIFT (0U)
5887/*! PTCO - Port Clear Output
5888 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
5889 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is cleared to logic 0.
5890 */
5891#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
5892/*! @} */
5893
5894/*! @name PTOR - Port Toggle Output Register */
5895/*! @{ */
5896#define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
5897#define GPIO_PTOR_PTTO_SHIFT (0U)
5898/*! PTTO - Port Toggle Output
5899 * 0b00000000000000000000000000000000..Corresponding bit in PDORn does not change.
5900 * 0b00000000000000000000000000000001..Corresponding bit in PDORn is set to the inverse of its existing logic state.
5901 */
5902#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
5903/*! @} */
5904
5905/*! @name PDIR - Port Data Input Register */
5906/*! @{ */
5907#define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
5908#define GPIO_PDIR_PDI_SHIFT (0U)
5909/*! PDI - Port Data Input
5910 * 0b00000000000000000000000000000000..Pin logic level is logic 0, or is not configured for use by digital function.
5911 * 0b00000000000000000000000000000001..Pin logic level is logic 1.
5912 */
5913#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
5914/*! @} */
5915
5916/*! @name PDDR - Port Data Direction Register */
5917/*! @{ */
5918#define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
5919#define GPIO_PDDR_PDD_SHIFT (0U)
5920/*! PDD - Port Data Direction
5921 * 0b00000000000000000000000000000000..Pin is configured as general-purpose input, for the GPIO function.
5922 * 0b00000000000000000000000000000001..Pin is configured as general-purpose output, for the GPIO function.
5923 */
5924#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
5925/*! @} */
5926
5927
5928/*!
5929 * @}
5930 */ /* end of group GPIO_Register_Masks */
5931
5932
5933/* GPIO - Peripheral instance base addresses */
5934/** Peripheral GPIOA base address */
5935#define GPIOA_BASE (0x400FF000u)
5936/** Peripheral GPIOA base pointer */
5937#define GPIOA ((GPIO_Type *)GPIOA_BASE)
5938/** Peripheral GPIOB base address */
5939#define GPIOB_BASE (0x400FF040u)
5940/** Peripheral GPIOB base pointer */
5941#define GPIOB ((GPIO_Type *)GPIOB_BASE)
5942/** Peripheral GPIOC base address */
5943#define GPIOC_BASE (0x400FF080u)
5944/** Peripheral GPIOC base pointer */
5945#define GPIOC ((GPIO_Type *)GPIOC_BASE)
5946/** Peripheral GPIOD base address */
5947#define GPIOD_BASE (0x400FF0C0u)
5948/** Peripheral GPIOD base pointer */
5949#define GPIOD ((GPIO_Type *)GPIOD_BASE)
5950/** Peripheral GPIOE base address */
5951#define GPIOE_BASE (0x400FF100u)
5952/** Peripheral GPIOE base pointer */
5953#define GPIOE ((GPIO_Type *)GPIOE_BASE)
5954/** Array initializer of GPIO peripheral base addresses */
5955#define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
5956/** Array initializer of GPIO peripheral base pointers */
5957#define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
5958
5959/*!
5960 * @}
5961 */ /* end of group GPIO_Peripheral_Access_Layer */
5962
5963
5964/* ----------------------------------------------------------------------------
5965 -- I2C Peripheral Access Layer
5966 ---------------------------------------------------------------------------- */
5967
5968/*!
5969 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
5970 * @{
5971 */
5972
5973/** I2C - Register Layout Typedef */
5974typedef struct {
5975 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
5976 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
5977 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
5978 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
5979 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
5980 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
5981 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
5982 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
5983 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
5984 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
5985 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
5986 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
5987} I2C_Type;
5988
5989/* ----------------------------------------------------------------------------
5990 -- I2C Register Masks
5991 ---------------------------------------------------------------------------- */
5992
5993/*!
5994 * @addtogroup I2C_Register_Masks I2C Register Masks
5995 * @{
5996 */
5997
5998/*! @name A1 - I2C Address Register 1 */
5999/*! @{ */
6000#define I2C_A1_AD_MASK (0xFEU)
6001#define I2C_A1_AD_SHIFT (1U)
6002#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
6003/*! @} */
6004
6005/*! @name F - I2C Frequency Divider register */
6006/*! @{ */
6007#define I2C_F_ICR_MASK (0x3FU)
6008#define I2C_F_ICR_SHIFT (0U)
6009#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
6010#define I2C_F_MULT_MASK (0xC0U)
6011#define I2C_F_MULT_SHIFT (6U)
6012/*! MULT - Multiplier Factor
6013 * 0b00..mul = 1
6014 * 0b01..mul = 2
6015 * 0b10..mul = 4
6016 * 0b11..Reserved
6017 */
6018#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
6019/*! @} */
6020
6021/*! @name C1 - I2C Control Register 1 */
6022/*! @{ */
6023#define I2C_C1_DMAEN_MASK (0x1U)
6024#define I2C_C1_DMAEN_SHIFT (0U)
6025/*! DMAEN - DMA Enable
6026 * 0b0..All DMA signalling disabled.
6027 * 0b1..DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
6028 */
6029#define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
6030#define I2C_C1_WUEN_MASK (0x2U)
6031#define I2C_C1_WUEN_SHIFT (1U)
6032/*! WUEN - Wakeup Enable
6033 * 0b0..Normal operation. No interrupt generated when address matching in low power mode.
6034 * 0b1..Enables the wakeup function in low power mode.
6035 */
6036#define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
6037#define I2C_C1_RSTA_MASK (0x4U)
6038#define I2C_C1_RSTA_SHIFT (2U)
6039#define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
6040#define I2C_C1_TXAK_MASK (0x8U)
6041#define I2C_C1_TXAK_SHIFT (3U)
6042/*! TXAK - Transmit Acknowledge Enable
6043 * 0b0..An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
6044 * 0b1..No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
6045 */
6046#define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
6047#define I2C_C1_TX_MASK (0x10U)
6048#define I2C_C1_TX_SHIFT (4U)
6049/*! TX - Transmit Mode Select
6050 * 0b0..Receive
6051 * 0b1..Transmit
6052 */
6053#define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
6054#define I2C_C1_MST_MASK (0x20U)
6055#define I2C_C1_MST_SHIFT (5U)
6056/*! MST - Master Mode Select
6057 * 0b0..Slave mode
6058 * 0b1..Master mode
6059 */
6060#define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
6061#define I2C_C1_IICIE_MASK (0x40U)
6062#define I2C_C1_IICIE_SHIFT (6U)
6063/*! IICIE - I2C Interrupt Enable
6064 * 0b0..Disabled
6065 * 0b1..Enabled
6066 */
6067#define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
6068#define I2C_C1_IICEN_MASK (0x80U)
6069#define I2C_C1_IICEN_SHIFT (7U)
6070/*! IICEN - I2C Enable
6071 * 0b0..Disabled
6072 * 0b1..Enabled
6073 */
6074#define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
6075/*! @} */
6076
6077/*! @name S - I2C Status register */
6078/*! @{ */
6079#define I2C_S_RXAK_MASK (0x1U)
6080#define I2C_S_RXAK_SHIFT (0U)
6081/*! RXAK - Receive Acknowledge
6082 * 0b0..Acknowledge signal was received after the completion of one byte of data transmission on the bus
6083 * 0b1..No acknowledge signal detected
6084 */
6085#define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
6086#define I2C_S_IICIF_MASK (0x2U)
6087#define I2C_S_IICIF_SHIFT (1U)
6088/*! IICIF - Interrupt Flag
6089 * 0b0..No interrupt pending
6090 * 0b1..Interrupt pending
6091 */
6092#define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
6093#define I2C_S_SRW_MASK (0x4U)
6094#define I2C_S_SRW_SHIFT (2U)
6095/*! SRW - Slave Read/Write
6096 * 0b0..Slave receive, master writing to slave
6097 * 0b1..Slave transmit, master reading from slave
6098 */
6099#define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
6100#define I2C_S_RAM_MASK (0x8U)
6101#define I2C_S_RAM_SHIFT (3U)
6102/*! RAM - Range Address Match
6103 * 0b0..Not addressed
6104 * 0b1..Addressed as a slave
6105 */
6106#define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
6107#define I2C_S_ARBL_MASK (0x10U)
6108#define I2C_S_ARBL_SHIFT (4U)
6109/*! ARBL - Arbitration Lost
6110 * 0b0..Standard bus operation.
6111 * 0b1..Loss of arbitration.
6112 */
6113#define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
6114#define I2C_S_BUSY_MASK (0x20U)
6115#define I2C_S_BUSY_SHIFT (5U)
6116/*! BUSY - Bus Busy
6117 * 0b0..Bus is idle
6118 * 0b1..Bus is busy
6119 */
6120#define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
6121#define I2C_S_IAAS_MASK (0x40U)
6122#define I2C_S_IAAS_SHIFT (6U)
6123/*! IAAS - Addressed As A Slave
6124 * 0b0..Not addressed
6125 * 0b1..Addressed as a slave
6126 */
6127#define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
6128#define I2C_S_TCF_MASK (0x80U)
6129#define I2C_S_TCF_SHIFT (7U)
6130/*! TCF - Transfer Complete Flag
6131 * 0b0..Transfer in progress
6132 * 0b1..Transfer complete
6133 */
6134#define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
6135/*! @} */
6136
6137/*! @name D - I2C Data I/O register */
6138/*! @{ */
6139#define I2C_D_DATA_MASK (0xFFU)
6140#define I2C_D_DATA_SHIFT (0U)
6141#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
6142/*! @} */
6143
6144/*! @name C2 - I2C Control Register 2 */
6145/*! @{ */
6146#define I2C_C2_AD_MASK (0x7U)
6147#define I2C_C2_AD_SHIFT (0U)
6148#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
6149#define I2C_C2_RMEN_MASK (0x8U)
6150#define I2C_C2_RMEN_SHIFT (3U)
6151/*! RMEN - Range Address Matching Enable
6152 * 0b0..Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
6153 * 0b1..Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
6154 */
6155#define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
6156#define I2C_C2_SBRC_MASK (0x10U)
6157#define I2C_C2_SBRC_SHIFT (4U)
6158/*! SBRC - Slave Baud Rate Control
6159 * 0b0..The slave baud rate follows the master baud rate and clock stretching may occur
6160 * 0b1..Slave baud rate is independent of the master baud rate
6161 */
6162#define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
6163#define I2C_C2_HDRS_MASK (0x20U)
6164#define I2C_C2_HDRS_SHIFT (5U)
6165/*! HDRS - High Drive Select
6166 * 0b0..Normal drive mode
6167 * 0b1..High drive mode
6168 */
6169#define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
6170#define I2C_C2_ADEXT_MASK (0x40U)
6171#define I2C_C2_ADEXT_SHIFT (6U)
6172/*! ADEXT - Address Extension
6173 * 0b0..7-bit address scheme
6174 * 0b1..10-bit address scheme
6175 */
6176#define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
6177#define I2C_C2_GCAEN_MASK (0x80U)
6178#define I2C_C2_GCAEN_SHIFT (7U)
6179/*! GCAEN - General Call Address Enable
6180 * 0b0..Disabled
6181 * 0b1..Enabled
6182 */
6183#define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
6184/*! @} */
6185
6186/*! @name FLT - I2C Programmable Input Glitch Filter register */
6187/*! @{ */
6188#define I2C_FLT_FLT_MASK (0xFU)
6189#define I2C_FLT_FLT_SHIFT (0U)
6190/*! FLT - I2C Programmable Filter Factor
6191 * 0b0000..No filter/bypass
6192 */
6193#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
6194#define I2C_FLT_STARTF_MASK (0x10U)
6195#define I2C_FLT_STARTF_SHIFT (4U)
6196/*! STARTF - I2C Bus Start Detect Flag
6197 * 0b0..No start happens on I2C bus
6198 * 0b1..Start detected on I2C bus
6199 */
6200#define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
6201#define I2C_FLT_SSIE_MASK (0x20U)
6202#define I2C_FLT_SSIE_SHIFT (5U)
6203/*! SSIE - I2C Bus Stop or Start Interrupt Enable
6204 * 0b0..Stop or start detection interrupt is disabled
6205 * 0b1..Stop or start detection interrupt is enabled
6206 */
6207#define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
6208#define I2C_FLT_STOPF_MASK (0x40U)
6209#define I2C_FLT_STOPF_SHIFT (6U)
6210/*! STOPF - I2C Bus Stop Detect Flag
6211 * 0b0..No stop happens on I2C bus
6212 * 0b1..Stop detected on I2C bus
6213 */
6214#define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
6215#define I2C_FLT_SHEN_MASK (0x80U)
6216#define I2C_FLT_SHEN_SHIFT (7U)
6217/*! SHEN - Stop Hold Enable
6218 * 0b0..Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
6219 * 0b1..Stop holdoff is enabled.
6220 */
6221#define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
6222/*! @} */
6223
6224/*! @name RA - I2C Range Address register */
6225/*! @{ */
6226#define I2C_RA_RAD_MASK (0xFEU)
6227#define I2C_RA_RAD_SHIFT (1U)
6228#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
6229/*! @} */
6230
6231/*! @name SMB - I2C SMBus Control and Status register */
6232/*! @{ */
6233#define I2C_SMB_SHTF2IE_MASK (0x1U)
6234#define I2C_SMB_SHTF2IE_SHIFT (0U)
6235/*! SHTF2IE - SHTF2 Interrupt Enable
6236 * 0b0..SHTF2 interrupt is disabled
6237 * 0b1..SHTF2 interrupt is enabled
6238 */
6239#define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
6240#define I2C_SMB_SHTF2_MASK (0x2U)
6241#define I2C_SMB_SHTF2_SHIFT (1U)
6242/*! SHTF2 - SCL High Timeout Flag 2
6243 * 0b0..No SCL high and SDA low timeout occurs
6244 * 0b1..SCL high and SDA low timeout occurs
6245 */
6246#define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
6247#define I2C_SMB_SHTF1_MASK (0x4U)
6248#define I2C_SMB_SHTF1_SHIFT (2U)
6249/*! SHTF1 - SCL High Timeout Flag 1
6250 * 0b0..No SCL high and SDA high timeout occurs
6251 * 0b1..SCL high and SDA high timeout occurs
6252 */
6253#define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
6254#define I2C_SMB_SLTF_MASK (0x8U)
6255#define I2C_SMB_SLTF_SHIFT (3U)
6256/*! SLTF - SCL Low Timeout Flag
6257 * 0b0..No low timeout occurs
6258 * 0b1..Low timeout occurs
6259 */
6260#define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
6261#define I2C_SMB_TCKSEL_MASK (0x10U)
6262#define I2C_SMB_TCKSEL_SHIFT (4U)
6263/*! TCKSEL - Timeout Counter Clock Select
6264 * 0b0..Timeout counter counts at the frequency of the I2C module clock / 64
6265 * 0b1..Timeout counter counts at the frequency of the I2C module clock
6266 */
6267#define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
6268#define I2C_SMB_SIICAEN_MASK (0x20U)
6269#define I2C_SMB_SIICAEN_SHIFT (5U)
6270/*! SIICAEN - Second I2C Address Enable
6271 * 0b0..I2C address register 2 matching is disabled
6272 * 0b1..I2C address register 2 matching is enabled
6273 */
6274#define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
6275#define I2C_SMB_ALERTEN_MASK (0x40U)
6276#define I2C_SMB_ALERTEN_SHIFT (6U)
6277/*! ALERTEN - SMBus Alert Response Address Enable
6278 * 0b0..SMBus alert response address matching is disabled
6279 * 0b1..SMBus alert response address matching is enabled
6280 */
6281#define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
6282#define I2C_SMB_FACK_MASK (0x80U)
6283#define I2C_SMB_FACK_SHIFT (7U)
6284/*! FACK - Fast NACK/ACK Enable
6285 * 0b0..An ACK or NACK is sent on the following receiving data byte
6286 * 0b1..Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
6287 */
6288#define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
6289/*! @} */
6290
6291/*! @name A2 - I2C Address Register 2 */
6292/*! @{ */
6293#define I2C_A2_SAD_MASK (0xFEU)
6294#define I2C_A2_SAD_SHIFT (1U)
6295#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
6296/*! @} */
6297
6298/*! @name SLTH - I2C SCL Low Timeout Register High */
6299/*! @{ */
6300#define I2C_SLTH_SSLT_MASK (0xFFU)
6301#define I2C_SLTH_SSLT_SHIFT (0U)
6302#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
6303/*! @} */
6304
6305/*! @name SLTL - I2C SCL Low Timeout Register Low */
6306/*! @{ */
6307#define I2C_SLTL_SSLT_MASK (0xFFU)
6308#define I2C_SLTL_SSLT_SHIFT (0U)
6309#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
6310/*! @} */
6311
6312
6313/*!
6314 * @}
6315 */ /* end of group I2C_Register_Masks */
6316
6317
6318/* I2C - Peripheral instance base addresses */
6319/** Peripheral I2C0 base address */
6320#define I2C0_BASE (0x40066000u)
6321/** Peripheral I2C0 base pointer */
6322#define I2C0 ((I2C_Type *)I2C0_BASE)
6323/** Peripheral I2C1 base address */
6324#define I2C1_BASE (0x40067000u)
6325/** Peripheral I2C1 base pointer */
6326#define I2C1 ((I2C_Type *)I2C1_BASE)
6327/** Array initializer of I2C peripheral base addresses */
6328#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE }
6329/** Array initializer of I2C peripheral base pointers */
6330#define I2C_BASE_PTRS { I2C0, I2C1 }
6331/** Interrupt vectors for the I2C peripheral type */
6332#define I2C_IRQS { I2C0_IRQn, I2C1_IRQn }
6333
6334/*!
6335 * @}
6336 */ /* end of group I2C_Peripheral_Access_Layer */
6337
6338
6339/* ----------------------------------------------------------------------------
6340 -- LLWU Peripheral Access Layer
6341 ---------------------------------------------------------------------------- */
6342
6343/*!
6344 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
6345 * @{
6346 */
6347
6348/** LLWU - Register Layout Typedef */
6349typedef struct {
6350 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
6351 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
6352 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
6353 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
6354 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
6355 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
6356 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
6357 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
6358 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
6359 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
6360} LLWU_Type;
6361
6362/* ----------------------------------------------------------------------------
6363 -- LLWU Register Masks
6364 ---------------------------------------------------------------------------- */
6365
6366/*!
6367 * @addtogroup LLWU_Register_Masks LLWU Register Masks
6368 * @{
6369 */
6370
6371/*! @name PE1 - LLWU Pin Enable 1 register */
6372/*! @{ */
6373#define LLWU_PE1_WUPE0_MASK (0x3U)
6374#define LLWU_PE1_WUPE0_SHIFT (0U)
6375/*! WUPE0 - Wakeup Pin Enable For LLWU_P0
6376 * 0b00..External input pin disabled as wakeup input
6377 * 0b01..External input pin enabled with rising edge detection
6378 * 0b10..External input pin enabled with falling edge detection
6379 * 0b11..External input pin enabled with any change detection
6380 */
6381#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
6382#define LLWU_PE1_WUPE1_MASK (0xCU)
6383#define LLWU_PE1_WUPE1_SHIFT (2U)
6384/*! WUPE1 - Wakeup Pin Enable For LLWU_P1
6385 * 0b00..External input pin disabled as wakeup input
6386 * 0b01..External input pin enabled with rising edge detection
6387 * 0b10..External input pin enabled with falling edge detection
6388 * 0b11..External input pin enabled with any change detection
6389 */
6390#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
6391#define LLWU_PE1_WUPE2_MASK (0x30U)
6392#define LLWU_PE1_WUPE2_SHIFT (4U)
6393/*! WUPE2 - Wakeup Pin Enable For LLWU_P2
6394 * 0b00..External input pin disabled as wakeup input
6395 * 0b01..External input pin enabled with rising edge detection
6396 * 0b10..External input pin enabled with falling edge detection
6397 * 0b11..External input pin enabled with any change detection
6398 */
6399#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
6400#define LLWU_PE1_WUPE3_MASK (0xC0U)
6401#define LLWU_PE1_WUPE3_SHIFT (6U)
6402/*! WUPE3 - Wakeup Pin Enable For LLWU_P3
6403 * 0b00..External input pin disabled as wakeup input
6404 * 0b01..External input pin enabled with rising edge detection
6405 * 0b10..External input pin enabled with falling edge detection
6406 * 0b11..External input pin enabled with any change detection
6407 */
6408#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
6409/*! @} */
6410
6411/*! @name PE2 - LLWU Pin Enable 2 register */
6412/*! @{ */
6413#define LLWU_PE2_WUPE4_MASK (0x3U)
6414#define LLWU_PE2_WUPE4_SHIFT (0U)
6415/*! WUPE4 - Wakeup Pin Enable For LLWU_P4
6416 * 0b00..External input pin disabled as wakeup input
6417 * 0b01..External input pin enabled with rising edge detection
6418 * 0b10..External input pin enabled with falling edge detection
6419 * 0b11..External input pin enabled with any change detection
6420 */
6421#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
6422#define LLWU_PE2_WUPE5_MASK (0xCU)
6423#define LLWU_PE2_WUPE5_SHIFT (2U)
6424/*! WUPE5 - Wakeup Pin Enable For LLWU_P5
6425 * 0b00..External input pin disabled as wakeup input
6426 * 0b01..External input pin enabled with rising edge detection
6427 * 0b10..External input pin enabled with falling edge detection
6428 * 0b11..External input pin enabled with any change detection
6429 */
6430#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
6431#define LLWU_PE2_WUPE6_MASK (0x30U)
6432#define LLWU_PE2_WUPE6_SHIFT (4U)
6433/*! WUPE6 - Wakeup Pin Enable For LLWU_P6
6434 * 0b00..External input pin disabled as wakeup input
6435 * 0b01..External input pin enabled with rising edge detection
6436 * 0b10..External input pin enabled with falling edge detection
6437 * 0b11..External input pin enabled with any change detection
6438 */
6439#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
6440#define LLWU_PE2_WUPE7_MASK (0xC0U)
6441#define LLWU_PE2_WUPE7_SHIFT (6U)
6442/*! WUPE7 - Wakeup Pin Enable For LLWU_P7
6443 * 0b00..External input pin disabled as wakeup input
6444 * 0b01..External input pin enabled with rising edge detection
6445 * 0b10..External input pin enabled with falling edge detection
6446 * 0b11..External input pin enabled with any change detection
6447 */
6448#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
6449/*! @} */
6450
6451/*! @name PE3 - LLWU Pin Enable 3 register */
6452/*! @{ */
6453#define LLWU_PE3_WUPE8_MASK (0x3U)
6454#define LLWU_PE3_WUPE8_SHIFT (0U)
6455/*! WUPE8 - Wakeup Pin Enable For LLWU_P8
6456 * 0b00..External input pin disabled as wakeup input
6457 * 0b01..External input pin enabled with rising edge detection
6458 * 0b10..External input pin enabled with falling edge detection
6459 * 0b11..External input pin enabled with any change detection
6460 */
6461#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
6462#define LLWU_PE3_WUPE9_MASK (0xCU)
6463#define LLWU_PE3_WUPE9_SHIFT (2U)
6464/*! WUPE9 - Wakeup Pin Enable For LLWU_P9
6465 * 0b00..External input pin disabled as wakeup input
6466 * 0b01..External input pin enabled with rising edge detection
6467 * 0b10..External input pin enabled with falling edge detection
6468 * 0b11..External input pin enabled with any change detection
6469 */
6470#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
6471#define LLWU_PE3_WUPE10_MASK (0x30U)
6472#define LLWU_PE3_WUPE10_SHIFT (4U)
6473/*! WUPE10 - Wakeup Pin Enable For LLWU_P10
6474 * 0b00..External input pin disabled as wakeup input
6475 * 0b01..External input pin enabled with rising edge detection
6476 * 0b10..External input pin enabled with falling edge detection
6477 * 0b11..External input pin enabled with any change detection
6478 */
6479#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
6480#define LLWU_PE3_WUPE11_MASK (0xC0U)
6481#define LLWU_PE3_WUPE11_SHIFT (6U)
6482/*! WUPE11 - Wakeup Pin Enable For LLWU_P11
6483 * 0b00..External input pin disabled as wakeup input
6484 * 0b01..External input pin enabled with rising edge detection
6485 * 0b10..External input pin enabled with falling edge detection
6486 * 0b11..External input pin enabled with any change detection
6487 */
6488#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
6489/*! @} */
6490
6491/*! @name PE4 - LLWU Pin Enable 4 register */
6492/*! @{ */
6493#define LLWU_PE4_WUPE12_MASK (0x3U)
6494#define LLWU_PE4_WUPE12_SHIFT (0U)
6495/*! WUPE12 - Wakeup Pin Enable For LLWU_P12
6496 * 0b00..External input pin disabled as wakeup input
6497 * 0b01..External input pin enabled with rising edge detection
6498 * 0b10..External input pin enabled with falling edge detection
6499 * 0b11..External input pin enabled with any change detection
6500 */
6501#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
6502#define LLWU_PE4_WUPE13_MASK (0xCU)
6503#define LLWU_PE4_WUPE13_SHIFT (2U)
6504/*! WUPE13 - Wakeup Pin Enable For LLWU_P13
6505 * 0b00..External input pin disabled as wakeup input
6506 * 0b01..External input pin enabled with rising edge detection
6507 * 0b10..External input pin enabled with falling edge detection
6508 * 0b11..External input pin enabled with any change detection
6509 */
6510#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
6511#define LLWU_PE4_WUPE14_MASK (0x30U)
6512#define LLWU_PE4_WUPE14_SHIFT (4U)
6513/*! WUPE14 - Wakeup Pin Enable For LLWU_P14
6514 * 0b00..External input pin disabled as wakeup input
6515 * 0b01..External input pin enabled with rising edge detection
6516 * 0b10..External input pin enabled with falling edge detection
6517 * 0b11..External input pin enabled with any change detection
6518 */
6519#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
6520#define LLWU_PE4_WUPE15_MASK (0xC0U)
6521#define LLWU_PE4_WUPE15_SHIFT (6U)
6522/*! WUPE15 - Wakeup Pin Enable For LLWU_P15
6523 * 0b00..External input pin disabled as wakeup input
6524 * 0b01..External input pin enabled with rising edge detection
6525 * 0b10..External input pin enabled with falling edge detection
6526 * 0b11..External input pin enabled with any change detection
6527 */
6528#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
6529/*! @} */
6530
6531/*! @name ME - LLWU Module Enable register */
6532/*! @{ */
6533#define LLWU_ME_WUME0_MASK (0x1U)
6534#define LLWU_ME_WUME0_SHIFT (0U)
6535/*! WUME0 - Wakeup Module Enable For Module 0
6536 * 0b0..Internal module flag not used as wakeup source
6537 * 0b1..Internal module flag used as wakeup source
6538 */
6539#define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
6540#define LLWU_ME_WUME1_MASK (0x2U)
6541#define LLWU_ME_WUME1_SHIFT (1U)
6542/*! WUME1 - Wakeup Module Enable for Module 1
6543 * 0b0..Internal module flag not used as wakeup source
6544 * 0b1..Internal module flag used as wakeup source
6545 */
6546#define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
6547#define LLWU_ME_WUME2_MASK (0x4U)
6548#define LLWU_ME_WUME2_SHIFT (2U)
6549/*! WUME2 - Wakeup Module Enable For Module 2
6550 * 0b0..Internal module flag not used as wakeup source
6551 * 0b1..Internal module flag used as wakeup source
6552 */
6553#define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
6554#define LLWU_ME_WUME3_MASK (0x8U)
6555#define LLWU_ME_WUME3_SHIFT (3U)
6556/*! WUME3 - Wakeup Module Enable For Module 3
6557 * 0b0..Internal module flag not used as wakeup source
6558 * 0b1..Internal module flag used as wakeup source
6559 */
6560#define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
6561#define LLWU_ME_WUME4_MASK (0x10U)
6562#define LLWU_ME_WUME4_SHIFT (4U)
6563/*! WUME4 - Wakeup Module Enable For Module 4
6564 * 0b0..Internal module flag not used as wakeup source
6565 * 0b1..Internal module flag used as wakeup source
6566 */
6567#define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
6568#define LLWU_ME_WUME5_MASK (0x20U)
6569#define LLWU_ME_WUME5_SHIFT (5U)
6570/*! WUME5 - Wakeup Module Enable For Module 5
6571 * 0b0..Internal module flag not used as wakeup source
6572 * 0b1..Internal module flag used as wakeup source
6573 */
6574#define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
6575#define LLWU_ME_WUME6_MASK (0x40U)
6576#define LLWU_ME_WUME6_SHIFT (6U)
6577/*! WUME6 - Wakeup Module Enable For Module 6
6578 * 0b0..Internal module flag not used as wakeup source
6579 * 0b1..Internal module flag used as wakeup source
6580 */
6581#define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
6582#define LLWU_ME_WUME7_MASK (0x80U)
6583#define LLWU_ME_WUME7_SHIFT (7U)
6584/*! WUME7 - Wakeup Module Enable For Module 7
6585 * 0b0..Internal module flag not used as wakeup source
6586 * 0b1..Internal module flag used as wakeup source
6587 */
6588#define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
6589/*! @} */
6590
6591/*! @name F1 - LLWU Flag 1 register */
6592/*! @{ */
6593#define LLWU_F1_WUF0_MASK (0x1U)
6594#define LLWU_F1_WUF0_SHIFT (0U)
6595/*! WUF0 - Wakeup Flag For LLWU_P0
6596 * 0b0..LLWU_P0 input was not a wakeup source
6597 * 0b1..LLWU_P0 input was a wakeup source
6598 */
6599#define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
6600#define LLWU_F1_WUF1_MASK (0x2U)
6601#define LLWU_F1_WUF1_SHIFT (1U)
6602/*! WUF1 - Wakeup Flag For LLWU_P1
6603 * 0b0..LLWU_P1 input was not a wakeup source
6604 * 0b1..LLWU_P1 input was a wakeup source
6605 */
6606#define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
6607#define LLWU_F1_WUF2_MASK (0x4U)
6608#define LLWU_F1_WUF2_SHIFT (2U)
6609/*! WUF2 - Wakeup Flag For LLWU_P2
6610 * 0b0..LLWU_P2 input was not a wakeup source
6611 * 0b1..LLWU_P2 input was a wakeup source
6612 */
6613#define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
6614#define LLWU_F1_WUF3_MASK (0x8U)
6615#define LLWU_F1_WUF3_SHIFT (3U)
6616/*! WUF3 - Wakeup Flag For LLWU_P3
6617 * 0b0..LLWU_P3 input was not a wake-up source
6618 * 0b1..LLWU_P3 input was a wake-up source
6619 */
6620#define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
6621#define LLWU_F1_WUF4_MASK (0x10U)
6622#define LLWU_F1_WUF4_SHIFT (4U)
6623/*! WUF4 - Wakeup Flag For LLWU_P4
6624 * 0b0..LLWU_P4 input was not a wakeup source
6625 * 0b1..LLWU_P4 input was a wakeup source
6626 */
6627#define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
6628#define LLWU_F1_WUF5_MASK (0x20U)
6629#define LLWU_F1_WUF5_SHIFT (5U)
6630/*! WUF5 - Wakeup Flag For LLWU_P5
6631 * 0b0..LLWU_P5 input was not a wakeup source
6632 * 0b1..LLWU_P5 input was a wakeup source
6633 */
6634#define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
6635#define LLWU_F1_WUF6_MASK (0x40U)
6636#define LLWU_F1_WUF6_SHIFT (6U)
6637/*! WUF6 - Wakeup Flag For LLWU_P6
6638 * 0b0..LLWU_P6 input was not a wakeup source
6639 * 0b1..LLWU_P6 input was a wakeup source
6640 */
6641#define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
6642#define LLWU_F1_WUF7_MASK (0x80U)
6643#define LLWU_F1_WUF7_SHIFT (7U)
6644/*! WUF7 - Wakeup Flag For LLWU_P7
6645 * 0b0..LLWU_P7 input was not a wakeup source
6646 * 0b1..LLWU_P7 input was a wakeup source
6647 */
6648#define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
6649/*! @} */
6650
6651/*! @name F2 - LLWU Flag 2 register */
6652/*! @{ */
6653#define LLWU_F2_WUF8_MASK (0x1U)
6654#define LLWU_F2_WUF8_SHIFT (0U)
6655/*! WUF8 - Wakeup Flag For LLWU_P8
6656 * 0b0..LLWU_P8 input was not a wakeup source
6657 * 0b1..LLWU_P8 input was a wakeup source
6658 */
6659#define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
6660#define LLWU_F2_WUF9_MASK (0x2U)
6661#define LLWU_F2_WUF9_SHIFT (1U)
6662/*! WUF9 - Wakeup Flag For LLWU_P9
6663 * 0b0..LLWU_P9 input was not a wakeup source
6664 * 0b1..LLWU_P9 input was a wakeup source
6665 */
6666#define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
6667#define LLWU_F2_WUF10_MASK (0x4U)
6668#define LLWU_F2_WUF10_SHIFT (2U)
6669/*! WUF10 - Wakeup Flag For LLWU_P10
6670 * 0b0..LLWU_P10 input was not a wakeup source
6671 * 0b1..LLWU_P10 input was a wakeup source
6672 */
6673#define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
6674#define LLWU_F2_WUF11_MASK (0x8U)
6675#define LLWU_F2_WUF11_SHIFT (3U)
6676/*! WUF11 - Wakeup Flag For LLWU_P11
6677 * 0b0..LLWU_P11 input was not a wakeup source
6678 * 0b1..LLWU_P11 input was a wakeup source
6679 */
6680#define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
6681#define LLWU_F2_WUF12_MASK (0x10U)
6682#define LLWU_F2_WUF12_SHIFT (4U)
6683/*! WUF12 - Wakeup Flag For LLWU_P12
6684 * 0b0..LLWU_P12 input was not a wakeup source
6685 * 0b1..LLWU_P12 input was a wakeup source
6686 */
6687#define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
6688#define LLWU_F2_WUF13_MASK (0x20U)
6689#define LLWU_F2_WUF13_SHIFT (5U)
6690/*! WUF13 - Wakeup Flag For LLWU_P13
6691 * 0b0..LLWU_P13 input was not a wakeup source
6692 * 0b1..LLWU_P13 input was a wakeup source
6693 */
6694#define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
6695#define LLWU_F2_WUF14_MASK (0x40U)
6696#define LLWU_F2_WUF14_SHIFT (6U)
6697/*! WUF14 - Wakeup Flag For LLWU_P14
6698 * 0b0..LLWU_P14 input was not a wakeup source
6699 * 0b1..LLWU_P14 input was a wakeup source
6700 */
6701#define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
6702#define LLWU_F2_WUF15_MASK (0x80U)
6703#define LLWU_F2_WUF15_SHIFT (7U)
6704/*! WUF15 - Wakeup Flag For LLWU_P15
6705 * 0b0..LLWU_P15 input was not a wakeup source
6706 * 0b1..LLWU_P15 input was a wakeup source
6707 */
6708#define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
6709/*! @} */
6710
6711/*! @name F3 - LLWU Flag 3 register */
6712/*! @{ */
6713#define LLWU_F3_MWUF0_MASK (0x1U)
6714#define LLWU_F3_MWUF0_SHIFT (0U)
6715/*! MWUF0 - Wakeup flag For module 0
6716 * 0b0..Module 0 input was not a wakeup source
6717 * 0b1..Module 0 input was a wakeup source
6718 */
6719#define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
6720#define LLWU_F3_MWUF1_MASK (0x2U)
6721#define LLWU_F3_MWUF1_SHIFT (1U)
6722/*! MWUF1 - Wakeup flag For module 1
6723 * 0b0..Module 1 input was not a wakeup source
6724 * 0b1..Module 1 input was a wakeup source
6725 */
6726#define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
6727#define LLWU_F3_MWUF2_MASK (0x4U)
6728#define LLWU_F3_MWUF2_SHIFT (2U)
6729/*! MWUF2 - Wakeup flag For module 2
6730 * 0b0..Module 2 input was not a wakeup source
6731 * 0b1..Module 2 input was a wakeup source
6732 */
6733#define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
6734#define LLWU_F3_MWUF3_MASK (0x8U)
6735#define LLWU_F3_MWUF3_SHIFT (3U)
6736/*! MWUF3 - Wakeup flag For module 3
6737 * 0b0..Module 3 input was not a wakeup source
6738 * 0b1..Module 3 input was a wakeup source
6739 */
6740#define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
6741#define LLWU_F3_MWUF4_MASK (0x10U)
6742#define LLWU_F3_MWUF4_SHIFT (4U)
6743/*! MWUF4 - Wakeup flag For module 4
6744 * 0b0..Module 4 input was not a wakeup source
6745 * 0b1..Module 4 input was a wakeup source
6746 */
6747#define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
6748#define LLWU_F3_MWUF5_MASK (0x20U)
6749#define LLWU_F3_MWUF5_SHIFT (5U)
6750/*! MWUF5 - Wakeup flag For module 5
6751 * 0b0..Module 5 input was not a wakeup source
6752 * 0b1..Module 5 input was a wakeup source
6753 */
6754#define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
6755#define LLWU_F3_MWUF6_MASK (0x40U)
6756#define LLWU_F3_MWUF6_SHIFT (6U)
6757/*! MWUF6 - Wakeup flag For module 6
6758 * 0b0..Module 6 input was not a wakeup source
6759 * 0b1..Module 6 input was a wakeup source
6760 */
6761#define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
6762#define LLWU_F3_MWUF7_MASK (0x80U)
6763#define LLWU_F3_MWUF7_SHIFT (7U)
6764/*! MWUF7 - Wakeup flag For module 7
6765 * 0b0..Module 7 input was not a wakeup source
6766 * 0b1..Module 7 input was a wakeup source
6767 */
6768#define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
6769/*! @} */
6770
6771/*! @name FILT1 - LLWU Pin Filter 1 register */
6772/*! @{ */
6773#define LLWU_FILT1_FILTSEL_MASK (0xFU)
6774#define LLWU_FILT1_FILTSEL_SHIFT (0U)
6775/*! FILTSEL - Filter Pin Select
6776 * 0b0000..Select LLWU_P0 for filter
6777 * 0b1111..Select LLWU_P15 for filter
6778 */
6779#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
6780#define LLWU_FILT1_FILTE_MASK (0x60U)
6781#define LLWU_FILT1_FILTE_SHIFT (5U)
6782/*! FILTE - Digital Filter On External Pin
6783 * 0b00..Filter disabled
6784 * 0b01..Filter posedge detect enabled
6785 * 0b10..Filter negedge detect enabled
6786 * 0b11..Filter any edge detect enabled
6787 */
6788#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
6789#define LLWU_FILT1_FILTF_MASK (0x80U)
6790#define LLWU_FILT1_FILTF_SHIFT (7U)
6791/*! FILTF - Filter Detect Flag
6792 * 0b0..Pin Filter 1 was not a wakeup source
6793 * 0b1..Pin Filter 1 was a wakeup source
6794 */
6795#define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
6796/*! @} */
6797
6798/*! @name FILT2 - LLWU Pin Filter 2 register */
6799/*! @{ */
6800#define LLWU_FILT2_FILTSEL_MASK (0xFU)
6801#define LLWU_FILT2_FILTSEL_SHIFT (0U)
6802/*! FILTSEL - Filter Pin Select
6803 * 0b0000..Select LLWU_P0 for filter
6804 * 0b1111..Select LLWU_P15 for filter
6805 */
6806#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
6807#define LLWU_FILT2_FILTE_MASK (0x60U)
6808#define LLWU_FILT2_FILTE_SHIFT (5U)
6809/*! FILTE - Digital Filter On External Pin
6810 * 0b00..Filter disabled
6811 * 0b01..Filter posedge detect enabled
6812 * 0b10..Filter negedge detect enabled
6813 * 0b11..Filter any edge detect enabled
6814 */
6815#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
6816#define LLWU_FILT2_FILTF_MASK (0x80U)
6817#define LLWU_FILT2_FILTF_SHIFT (7U)
6818/*! FILTF - Filter Detect Flag
6819 * 0b0..Pin Filter 2 was not a wakeup source
6820 * 0b1..Pin Filter 2 was a wakeup source
6821 */
6822#define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
6823/*! @} */
6824
6825
6826/*!
6827 * @}
6828 */ /* end of group LLWU_Register_Masks */
6829
6830
6831/* LLWU - Peripheral instance base addresses */
6832/** Peripheral LLWU base address */
6833#define LLWU_BASE (0x4007C000u)
6834/** Peripheral LLWU base pointer */
6835#define LLWU ((LLWU_Type *)LLWU_BASE)
6836/** Array initializer of LLWU peripheral base addresses */
6837#define LLWU_BASE_ADDRS { LLWU_BASE }
6838/** Array initializer of LLWU peripheral base pointers */
6839#define LLWU_BASE_PTRS { LLWU }
6840/** Interrupt vectors for the LLWU peripheral type */
6841#define LLWU_IRQS { LLWU_IRQn }
6842
6843/*!
6844 * @}
6845 */ /* end of group LLWU_Peripheral_Access_Layer */
6846
6847
6848/* ----------------------------------------------------------------------------
6849 -- LPTMR Peripheral Access Layer
6850 ---------------------------------------------------------------------------- */
6851
6852/*!
6853 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
6854 * @{
6855 */
6856
6857/** LPTMR - Register Layout Typedef */
6858typedef struct {
6859 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
6860 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
6861 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
6862 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
6863} LPTMR_Type;
6864
6865/* ----------------------------------------------------------------------------
6866 -- LPTMR Register Masks
6867 ---------------------------------------------------------------------------- */
6868
6869/*!
6870 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
6871 * @{
6872 */
6873
6874/*! @name CSR - Low Power Timer Control Status Register */
6875/*! @{ */
6876#define LPTMR_CSR_TEN_MASK (0x1U)
6877#define LPTMR_CSR_TEN_SHIFT (0U)
6878/*! TEN - Timer Enable
6879 * 0b0..LPTMR is disabled and internal logic is reset.
6880 * 0b1..LPTMR is enabled.
6881 */
6882#define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
6883#define LPTMR_CSR_TMS_MASK (0x2U)
6884#define LPTMR_CSR_TMS_SHIFT (1U)
6885/*! TMS - Timer Mode Select
6886 * 0b0..Time Counter mode.
6887 * 0b1..Pulse Counter mode.
6888 */
6889#define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
6890#define LPTMR_CSR_TFC_MASK (0x4U)
6891#define LPTMR_CSR_TFC_SHIFT (2U)
6892/*! TFC - Timer Free-Running Counter
6893 * 0b0..CNR is reset whenever TCF is set.
6894 * 0b1..CNR is reset on overflow.
6895 */
6896#define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
6897#define LPTMR_CSR_TPP_MASK (0x8U)
6898#define LPTMR_CSR_TPP_SHIFT (3U)
6899/*! TPP - Timer Pin Polarity
6900 * 0b0..Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
6901 * 0b1..Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
6902 */
6903#define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
6904#define LPTMR_CSR_TPS_MASK (0x30U)
6905#define LPTMR_CSR_TPS_SHIFT (4U)
6906/*! TPS - Timer Pin Select
6907 * 0b00..Pulse counter input 0 is selected.
6908 * 0b01..Pulse counter input 1 is selected.
6909 * 0b10..Pulse counter input 2 is selected.
6910 * 0b11..Pulse counter input 3 is selected.
6911 */
6912#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
6913#define LPTMR_CSR_TIE_MASK (0x40U)
6914#define LPTMR_CSR_TIE_SHIFT (6U)
6915/*! TIE - Timer Interrupt Enable
6916 * 0b0..Timer interrupt disabled.
6917 * 0b1..Timer interrupt enabled.
6918 */
6919#define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
6920#define LPTMR_CSR_TCF_MASK (0x80U)
6921#define LPTMR_CSR_TCF_SHIFT (7U)
6922/*! TCF - Timer Compare Flag
6923 * 0b0..The value of CNR is not equal to CMR and increments.
6924 * 0b1..The value of CNR is equal to CMR and increments.
6925 */
6926#define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
6927/*! @} */
6928
6929/*! @name PSR - Low Power Timer Prescale Register */
6930/*! @{ */
6931#define LPTMR_PSR_PCS_MASK (0x3U)
6932#define LPTMR_PSR_PCS_SHIFT (0U)
6933/*! PCS - Prescaler Clock Select
6934 * 0b00..Prescaler/glitch filter clock 0 selected.
6935 * 0b01..Prescaler/glitch filter clock 1 selected.
6936 * 0b10..Prescaler/glitch filter clock 2 selected.
6937 * 0b11..Prescaler/glitch filter clock 3 selected.
6938 */
6939#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
6940#define LPTMR_PSR_PBYP_MASK (0x4U)
6941#define LPTMR_PSR_PBYP_SHIFT (2U)
6942/*! PBYP - Prescaler Bypass
6943 * 0b0..Prescaler/glitch filter is enabled.
6944 * 0b1..Prescaler/glitch filter is bypassed.
6945 */
6946#define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
6947#define LPTMR_PSR_PRESCALE_MASK (0x78U)
6948#define LPTMR_PSR_PRESCALE_SHIFT (3U)
6949/*! PRESCALE - Prescale Value
6950 * 0b0000..Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
6951 * 0b0001..Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
6952 * 0b0010..Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
6953 * 0b0011..Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
6954 * 0b0100..Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
6955 * 0b0101..Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
6956 * 0b0110..Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
6957 * 0b0111..Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
6958 * 0b1000..Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
6959 * 0b1001..Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
6960 * 0b1010..Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
6961 * 0b1011..Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
6962 * 0b1100..Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
6963 * 0b1101..Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
6964 * 0b1110..Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
6965 * 0b1111..Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
6966 */
6967#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
6968/*! @} */
6969
6970/*! @name CMR - Low Power Timer Compare Register */
6971/*! @{ */
6972#define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
6973#define LPTMR_CMR_COMPARE_SHIFT (0U)
6974#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
6975/*! @} */
6976
6977/*! @name CNR - Low Power Timer Counter Register */
6978/*! @{ */
6979#define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
6980#define LPTMR_CNR_COUNTER_SHIFT (0U)
6981#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
6982/*! @} */
6983
6984
6985/*!
6986 * @}
6987 */ /* end of group LPTMR_Register_Masks */
6988
6989
6990/* LPTMR - Peripheral instance base addresses */
6991/** Peripheral LPTMR0 base address */
6992#define LPTMR0_BASE (0x40040000u)
6993/** Peripheral LPTMR0 base pointer */
6994#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
6995/** Array initializer of LPTMR peripheral base addresses */
6996#define LPTMR_BASE_ADDRS { LPTMR0_BASE }
6997/** Array initializer of LPTMR peripheral base pointers */
6998#define LPTMR_BASE_PTRS { LPTMR0 }
6999/** Interrupt vectors for the LPTMR peripheral type */
7000#define LPTMR_IRQS { LPTMR0_IRQn }
7001
7002/*!
7003 * @}
7004 */ /* end of group LPTMR_Peripheral_Access_Layer */
7005
7006
7007/* ----------------------------------------------------------------------------
7008 -- LPUART Peripheral Access Layer
7009 ---------------------------------------------------------------------------- */
7010
7011/*!
7012 * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
7013 * @{
7014 */
7015
7016/** LPUART - Register Layout Typedef */
7017typedef struct {
7018 __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */
7019 __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */
7020 __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */
7021 __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */
7022 __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */
7023 __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */
7024} LPUART_Type;
7025
7026/* ----------------------------------------------------------------------------
7027 -- LPUART Register Masks
7028 ---------------------------------------------------------------------------- */
7029
7030/*!
7031 * @addtogroup LPUART_Register_Masks LPUART Register Masks
7032 * @{
7033 */
7034
7035/*! @name BAUD - LPUART Baud Rate Register */
7036/*! @{ */
7037#define LPUART_BAUD_SBR_MASK (0x1FFFU)
7038#define LPUART_BAUD_SBR_SHIFT (0U)
7039#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
7040#define LPUART_BAUD_SBNS_MASK (0x2000U)
7041#define LPUART_BAUD_SBNS_SHIFT (13U)
7042/*! SBNS - Stop Bit Number Select
7043 * 0b0..One stop bit.
7044 * 0b1..Two stop bits.
7045 */
7046#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
7047#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
7048#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
7049/*! RXEDGIE - RX Input Active Edge Interrupt Enable
7050 * 0b0..Hardware interrupts from LPUART_STAT[RXEDGIF] disabled (use polling).
7051 * 0b1..Hardware interrupt requested when LPUART_STAT[RXEDGIF] flag is 1.
7052 */
7053#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
7054#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
7055#define LPUART_BAUD_LBKDIE_SHIFT (15U)
7056/*! LBKDIE - LIN Break Detect Interrupt Enable
7057 * 0b0..Hardware interrupts from LPUART_STAT[LBKDIF] disabled (use polling).
7058 * 0b1..Hardware interrupt requested when LPUART_STAT[LBKDIF] flag is 1.
7059 */
7060#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
7061#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
7062#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
7063/*! RESYNCDIS - Resynchronization Disable
7064 * 0b0..Resynchronization during received data word is supported
7065 * 0b1..Resynchronization during received data word is disabled
7066 */
7067#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
7068#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
7069#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
7070/*! BOTHEDGE - Both Edge Sampling
7071 * 0b0..Receiver samples input data using the rising edge of the baud rate clock.
7072 * 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
7073 */
7074#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
7075#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
7076#define LPUART_BAUD_MATCFG_SHIFT (18U)
7077/*! MATCFG - Match Configuration
7078 * 0b00..Address Match Wakeup
7079 * 0b01..Idle Match Wakeup
7080 * 0b10..Match On and Match Off
7081 * 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
7082 */
7083#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
7084#define LPUART_BAUD_RDMAE_MASK (0x200000U)
7085#define LPUART_BAUD_RDMAE_SHIFT (21U)
7086/*! RDMAE - Receiver Full DMA Enable
7087 * 0b0..DMA request disabled.
7088 * 0b1..DMA request enabled.
7089 */
7090#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
7091#define LPUART_BAUD_TDMAE_MASK (0x800000U)
7092#define LPUART_BAUD_TDMAE_SHIFT (23U)
7093/*! TDMAE - Transmitter DMA Enable
7094 * 0b0..DMA request disabled.
7095 * 0b1..DMA request enabled.
7096 */
7097#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
7098#define LPUART_BAUD_OSR_MASK (0x1F000000U)
7099#define LPUART_BAUD_OSR_SHIFT (24U)
7100#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
7101#define LPUART_BAUD_M10_MASK (0x20000000U)
7102#define LPUART_BAUD_M10_SHIFT (29U)
7103/*! M10 - 10-bit Mode select
7104 * 0b0..Receiver and transmitter use 8-bit or 9-bit data characters.
7105 * 0b1..Receiver and transmitter use 10-bit data characters.
7106 */
7107#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
7108#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
7109#define LPUART_BAUD_MAEN2_SHIFT (30U)
7110/*! MAEN2 - Match Address Mode Enable 2
7111 * 0b0..Normal operation.
7112 * 0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
7113 */
7114#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
7115#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
7116#define LPUART_BAUD_MAEN1_SHIFT (31U)
7117/*! MAEN1 - Match Address Mode Enable 1
7118 * 0b0..Normal operation.
7119 * 0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
7120 */
7121#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
7122/*! @} */
7123
7124/*! @name STAT - LPUART Status Register */
7125/*! @{ */
7126#define LPUART_STAT_MA2F_MASK (0x4000U)
7127#define LPUART_STAT_MA2F_SHIFT (14U)
7128/*! MA2F - Match 2 Flag
7129 * 0b0..Received data is not equal to MA2
7130 * 0b1..Received data is equal to MA2
7131 */
7132#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
7133#define LPUART_STAT_MA1F_MASK (0x8000U)
7134#define LPUART_STAT_MA1F_SHIFT (15U)
7135/*! MA1F - Match 1 Flag
7136 * 0b0..Received data is not equal to MA1
7137 * 0b1..Received data is equal to MA1
7138 */
7139#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
7140#define LPUART_STAT_PF_MASK (0x10000U)
7141#define LPUART_STAT_PF_SHIFT (16U)
7142/*! PF - Parity Error Flag
7143 * 0b0..No parity error.
7144 * 0b1..Parity error.
7145 */
7146#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
7147#define LPUART_STAT_FE_MASK (0x20000U)
7148#define LPUART_STAT_FE_SHIFT (17U)
7149/*! FE - Framing Error Flag
7150 * 0b0..No framing error detected. This does not guarantee the framing is correct.
7151 * 0b1..Framing error.
7152 */
7153#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
7154#define LPUART_STAT_NF_MASK (0x40000U)
7155#define LPUART_STAT_NF_SHIFT (18U)
7156/*! NF - Noise Flag
7157 * 0b0..No noise detected.
7158 * 0b1..Noise detected in the received character in LPUART_DATA.
7159 */
7160#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
7161#define LPUART_STAT_OR_MASK (0x80000U)
7162#define LPUART_STAT_OR_SHIFT (19U)
7163/*! OR - Receiver Overrun Flag
7164 * 0b0..No overrun.
7165 * 0b1..Receive overrun (new LPUART data lost).
7166 */
7167#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
7168#define LPUART_STAT_IDLE_MASK (0x100000U)
7169#define LPUART_STAT_IDLE_SHIFT (20U)
7170/*! IDLE - Idle Line Flag
7171 * 0b0..No idle line detected.
7172 * 0b1..Idle line was detected.
7173 */
7174#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
7175#define LPUART_STAT_RDRF_MASK (0x200000U)
7176#define LPUART_STAT_RDRF_SHIFT (21U)
7177/*! RDRF - Receive Data Register Full Flag
7178 * 0b0..Receive data buffer empty.
7179 * 0b1..Receive data buffer full.
7180 */
7181#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
7182#define LPUART_STAT_TC_MASK (0x400000U)
7183#define LPUART_STAT_TC_SHIFT (22U)
7184/*! TC - Transmission Complete Flag
7185 * 0b0..Transmitter active (sending data, a preamble, or a break).
7186 * 0b1..Transmitter idle (transmission activity complete).
7187 */
7188#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
7189#define LPUART_STAT_TDRE_MASK (0x800000U)
7190#define LPUART_STAT_TDRE_SHIFT (23U)
7191/*! TDRE - Transmit Data Register Empty Flag
7192 * 0b0..Transmit data buffer full.
7193 * 0b1..Transmit data buffer empty.
7194 */
7195#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
7196#define LPUART_STAT_RAF_MASK (0x1000000U)
7197#define LPUART_STAT_RAF_SHIFT (24U)
7198/*! RAF - Receiver Active Flag
7199 * 0b0..LPUART receiver idle waiting for a start bit.
7200 * 0b1..LPUART receiver active (LPUART_RX input not idle).
7201 */
7202#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
7203#define LPUART_STAT_LBKDE_MASK (0x2000000U)
7204#define LPUART_STAT_LBKDE_SHIFT (25U)
7205/*! LBKDE - LIN Break Detection Enable
7206 * 0b0..Break character is detected at length 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
7207 * 0b1..Break character is detected at length of 11 bit times (if M = 0, SBNS = 0) or 12 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 14 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 15 (if M10 = 1, SNBS = 1).
7208 */
7209#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
7210#define LPUART_STAT_BRK13_MASK (0x4000000U)
7211#define LPUART_STAT_BRK13_SHIFT (26U)
7212/*! BRK13 - Break Character Generation Length
7213 * 0b0..Break character is transmitted with length of 10 bit times (if M = 0, SBNS = 0) or 11 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 12 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 13 (if M10 = 1, SNBS = 1).
7214 * 0b1..Break character is transmitted with length of 13 bit times (if M = 0, SBNS = 0) or 14 (if M = 1, SBNS = 0 or M = 0, SBNS = 1) or 15 (if M = 1, SBNS = 1 or M10 = 1, SNBS = 0) or 16 (if M10 = 1, SNBS = 1).
7215 */
7216#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
7217#define LPUART_STAT_RWUID_MASK (0x8000000U)
7218#define LPUART_STAT_RWUID_SHIFT (27U)
7219/*! RWUID - Receive Wake Up Idle Detect
7220 * 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not get set when an address does not match.
7221 * 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does get set when an address does not match.
7222 */
7223#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
7224#define LPUART_STAT_RXINV_MASK (0x10000000U)
7225#define LPUART_STAT_RXINV_SHIFT (28U)
7226/*! RXINV - Receive Data Inversion
7227 * 0b0..Receive data not inverted.
7228 * 0b1..Receive data inverted.
7229 */
7230#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
7231#define LPUART_STAT_MSBF_MASK (0x20000000U)
7232#define LPUART_STAT_MSBF_SHIFT (29U)
7233/*! MSBF - MSB First
7234 * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
7235 * 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].
7236 */
7237#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
7238#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
7239#define LPUART_STAT_RXEDGIF_SHIFT (30U)
7240/*! RXEDGIF - LPUART_RX Pin Active Edge Interrupt Flag
7241 * 0b0..No active edge on the receive pin has occurred.
7242 * 0b1..An active edge on the receive pin has occurred.
7243 */
7244#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
7245#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
7246#define LPUART_STAT_LBKDIF_SHIFT (31U)
7247/*! LBKDIF - LIN Break Detect Interrupt Flag
7248 * 0b0..No LIN break character has been detected.
7249 * 0b1..LIN break character has been detected.
7250 */
7251#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
7252/*! @} */
7253
7254/*! @name CTRL - LPUART Control Register */
7255/*! @{ */
7256#define LPUART_CTRL_PT_MASK (0x1U)
7257#define LPUART_CTRL_PT_SHIFT (0U)
7258/*! PT - Parity Type
7259 * 0b0..Even parity.
7260 * 0b1..Odd parity.
7261 */
7262#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
7263#define LPUART_CTRL_PE_MASK (0x2U)
7264#define LPUART_CTRL_PE_SHIFT (1U)
7265/*! PE - Parity Enable
7266 * 0b0..No hardware parity generation or checking.
7267 * 0b1..Parity enabled.
7268 */
7269#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
7270#define LPUART_CTRL_ILT_MASK (0x4U)
7271#define LPUART_CTRL_ILT_SHIFT (2U)
7272/*! ILT - Idle Line Type Select
7273 * 0b0..Idle character bit count starts after start bit.
7274 * 0b1..Idle character bit count starts after stop bit.
7275 */
7276#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
7277#define LPUART_CTRL_WAKE_MASK (0x8U)
7278#define LPUART_CTRL_WAKE_SHIFT (3U)
7279/*! WAKE - Receiver Wakeup Method Select
7280 * 0b0..Configures RWU for idle-line wakeup.
7281 * 0b1..Configures RWU with address-mark wakeup.
7282 */
7283#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
7284#define LPUART_CTRL_M_MASK (0x10U)
7285#define LPUART_CTRL_M_SHIFT (4U)
7286/*! M - 9-Bit or 8-Bit Mode Select
7287 * 0b0..Receiver and transmitter use 8-bit data characters.
7288 * 0b1..Receiver and transmitter use 9-bit data characters.
7289 */
7290#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
7291#define LPUART_CTRL_RSRC_MASK (0x20U)
7292#define LPUART_CTRL_RSRC_SHIFT (5U)
7293/*! RSRC - Receiver Source Select
7294 * 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the LPUART_RX pin.
7295 * 0b1..Single-wire LPUART mode where the LPUART_TX pin is connected to the transmitter output and receiver input.
7296 */
7297#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
7298#define LPUART_CTRL_DOZEEN_MASK (0x40U)
7299#define LPUART_CTRL_DOZEEN_SHIFT (6U)
7300/*! DOZEEN - Doze Enable
7301 * 0b0..LPUART is enabled in Doze mode.
7302 * 0b1..LPUART is disabled in Doze mode.
7303 */
7304#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
7305#define LPUART_CTRL_LOOPS_MASK (0x80U)
7306#define LPUART_CTRL_LOOPS_SHIFT (7U)
7307/*! LOOPS - Loop Mode Select
7308 * 0b0..Normal operation - LPUART_RX and LPUART_TX use separate pins.
7309 * 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
7310 */
7311#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
7312#define LPUART_CTRL_IDLECFG_MASK (0x700U)
7313#define LPUART_CTRL_IDLECFG_SHIFT (8U)
7314/*! IDLECFG - Idle Configuration
7315 * 0b000..1 idle character
7316 * 0b001..2 idle characters
7317 * 0b010..4 idle characters
7318 * 0b011..8 idle characters
7319 * 0b100..16 idle characters
7320 * 0b101..32 idle characters
7321 * 0b110..64 idle characters
7322 * 0b111..128 idle characters
7323 */
7324#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
7325#define LPUART_CTRL_MA2IE_MASK (0x4000U)
7326#define LPUART_CTRL_MA2IE_SHIFT (14U)
7327/*! MA2IE - Match 2 Interrupt Enable
7328 * 0b0..MA2F interrupt disabled
7329 * 0b1..MA2F interrupt enabled
7330 */
7331#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
7332#define LPUART_CTRL_MA1IE_MASK (0x8000U)
7333#define LPUART_CTRL_MA1IE_SHIFT (15U)
7334/*! MA1IE - Match 1 Interrupt Enable
7335 * 0b0..MA1F interrupt disabled
7336 * 0b1..MA1F interrupt enabled
7337 */
7338#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
7339#define LPUART_CTRL_SBK_MASK (0x10000U)
7340#define LPUART_CTRL_SBK_SHIFT (16U)
7341/*! SBK - Send Break
7342 * 0b0..Normal transmitter operation.
7343 * 0b1..Queue break character(s) to be sent.
7344 */
7345#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
7346#define LPUART_CTRL_RWU_MASK (0x20000U)
7347#define LPUART_CTRL_RWU_SHIFT (17U)
7348/*! RWU - Receiver Wakeup Control
7349 * 0b0..Normal receiver operation.
7350 * 0b1..LPUART receiver in standby waiting for wakeup condition.
7351 */
7352#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
7353#define LPUART_CTRL_RE_MASK (0x40000U)
7354#define LPUART_CTRL_RE_SHIFT (18U)
7355/*! RE - Receiver Enable
7356 * 0b0..Receiver disabled.
7357 * 0b1..Receiver enabled.
7358 */
7359#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
7360#define LPUART_CTRL_TE_MASK (0x80000U)
7361#define LPUART_CTRL_TE_SHIFT (19U)
7362/*! TE - Transmitter Enable
7363 * 0b0..Transmitter disabled.
7364 * 0b1..Transmitter enabled.
7365 */
7366#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
7367#define LPUART_CTRL_ILIE_MASK (0x100000U)
7368#define LPUART_CTRL_ILIE_SHIFT (20U)
7369/*! ILIE - Idle Line Interrupt Enable
7370 * 0b0..Hardware interrupts from IDLE disabled; use polling.
7371 * 0b1..Hardware interrupt requested when IDLE flag is 1.
7372 */
7373#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
7374#define LPUART_CTRL_RIE_MASK (0x200000U)
7375#define LPUART_CTRL_RIE_SHIFT (21U)
7376/*! RIE - Receiver Interrupt Enable
7377 * 0b0..Hardware interrupts from RDRF disabled; use polling.
7378 * 0b1..Hardware interrupt requested when RDRF flag is 1.
7379 */
7380#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
7381#define LPUART_CTRL_TCIE_MASK (0x400000U)
7382#define LPUART_CTRL_TCIE_SHIFT (22U)
7383/*! TCIE - Transmission Complete Interrupt Enable for
7384 * 0b0..Hardware interrupts from TC disabled; use polling.
7385 * 0b1..Hardware interrupt requested when TC flag is 1.
7386 */
7387#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
7388#define LPUART_CTRL_TIE_MASK (0x800000U)
7389#define LPUART_CTRL_TIE_SHIFT (23U)
7390/*! TIE - Transmit Interrupt Enable
7391 * 0b0..Hardware interrupts from TDRE disabled; use polling.
7392 * 0b1..Hardware interrupt requested when TDRE flag is 1.
7393 */
7394#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
7395#define LPUART_CTRL_PEIE_MASK (0x1000000U)
7396#define LPUART_CTRL_PEIE_SHIFT (24U)
7397/*! PEIE - Parity Error Interrupt Enable
7398 * 0b0..PF interrupts disabled; use polling).
7399 * 0b1..Hardware interrupt requested when PF is set.
7400 */
7401#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
7402#define LPUART_CTRL_FEIE_MASK (0x2000000U)
7403#define LPUART_CTRL_FEIE_SHIFT (25U)
7404/*! FEIE - Framing Error Interrupt Enable
7405 * 0b0..FE interrupts disabled; use polling.
7406 * 0b1..Hardware interrupt requested when FE is set.
7407 */
7408#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
7409#define LPUART_CTRL_NEIE_MASK (0x4000000U)
7410#define LPUART_CTRL_NEIE_SHIFT (26U)
7411/*! NEIE - Noise Error Interrupt Enable
7412 * 0b0..NF interrupts disabled; use polling.
7413 * 0b1..Hardware interrupt requested when NF is set.
7414 */
7415#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
7416#define LPUART_CTRL_ORIE_MASK (0x8000000U)
7417#define LPUART_CTRL_ORIE_SHIFT (27U)
7418/*! ORIE - Overrun Interrupt Enable
7419 * 0b0..OR interrupts disabled; use polling.
7420 * 0b1..Hardware interrupt requested when OR is set.
7421 */
7422#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
7423#define LPUART_CTRL_TXINV_MASK (0x10000000U)
7424#define LPUART_CTRL_TXINV_SHIFT (28U)
7425/*! TXINV - Transmit Data Inversion
7426 * 0b0..Transmit data not inverted.
7427 * 0b1..Transmit data inverted.
7428 */
7429#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
7430#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
7431#define LPUART_CTRL_TXDIR_SHIFT (29U)
7432/*! TXDIR - LPUART_TX Pin Direction in Single-Wire Mode
7433 * 0b0..LPUART_TX pin is an input in single-wire mode.
7434 * 0b1..LPUART_TX pin is an output in single-wire mode.
7435 */
7436#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
7437#define LPUART_CTRL_R9T8_MASK (0x40000000U)
7438#define LPUART_CTRL_R9T8_SHIFT (30U)
7439#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
7440#define LPUART_CTRL_R8T9_MASK (0x80000000U)
7441#define LPUART_CTRL_R8T9_SHIFT (31U)
7442#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
7443/*! @} */
7444
7445/*! @name DATA - LPUART Data Register */
7446/*! @{ */
7447#define LPUART_DATA_R0T0_MASK (0x1U)
7448#define LPUART_DATA_R0T0_SHIFT (0U)
7449#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
7450#define LPUART_DATA_R1T1_MASK (0x2U)
7451#define LPUART_DATA_R1T1_SHIFT (1U)
7452#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
7453#define LPUART_DATA_R2T2_MASK (0x4U)
7454#define LPUART_DATA_R2T2_SHIFT (2U)
7455#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
7456#define LPUART_DATA_R3T3_MASK (0x8U)
7457#define LPUART_DATA_R3T3_SHIFT (3U)
7458#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
7459#define LPUART_DATA_R4T4_MASK (0x10U)
7460#define LPUART_DATA_R4T4_SHIFT (4U)
7461#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
7462#define LPUART_DATA_R5T5_MASK (0x20U)
7463#define LPUART_DATA_R5T5_SHIFT (5U)
7464#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
7465#define LPUART_DATA_R6T6_MASK (0x40U)
7466#define LPUART_DATA_R6T6_SHIFT (6U)
7467#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
7468#define LPUART_DATA_R7T7_MASK (0x80U)
7469#define LPUART_DATA_R7T7_SHIFT (7U)
7470#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
7471#define LPUART_DATA_R8T8_MASK (0x100U)
7472#define LPUART_DATA_R8T8_SHIFT (8U)
7473#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
7474#define LPUART_DATA_R9T9_MASK (0x200U)
7475#define LPUART_DATA_R9T9_SHIFT (9U)
7476#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
7477#define LPUART_DATA_IDLINE_MASK (0x800U)
7478#define LPUART_DATA_IDLINE_SHIFT (11U)
7479/*! IDLINE - Idle Line
7480 * 0b0..Receiver was not idle before receiving this character.
7481 * 0b1..Receiver was idle before receiving this character.
7482 */
7483#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
7484#define LPUART_DATA_RXEMPT_MASK (0x1000U)
7485#define LPUART_DATA_RXEMPT_SHIFT (12U)
7486/*! RXEMPT - Receive Buffer Empty
7487 * 0b0..Receive buffer contains valid data.
7488 * 0b1..Receive buffer is empty, data returned on read is not valid.
7489 */
7490#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
7491#define LPUART_DATA_FRETSC_MASK (0x2000U)
7492#define LPUART_DATA_FRETSC_SHIFT (13U)
7493/*! FRETSC - Frame Error / Transmit Special Character
7494 * 0b0..The dataword was received without a frame error on read, transmit a normal character on write.
7495 * 0b1..The dataword was received with a frame error, transmit an idle or break character on transmit.
7496 */
7497#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
7498#define LPUART_DATA_PARITYE_MASK (0x4000U)
7499#define LPUART_DATA_PARITYE_SHIFT (14U)
7500/*! PARITYE
7501 * 0b0..The dataword was received without a parity error.
7502 * 0b1..The dataword was received with a parity error.
7503 */
7504#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
7505#define LPUART_DATA_NOISY_MASK (0x8000U)
7506#define LPUART_DATA_NOISY_SHIFT (15U)
7507/*! NOISY
7508 * 0b0..The dataword was received without noise.
7509 * 0b1..The data was received with noise.
7510 */
7511#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
7512/*! @} */
7513
7514/*! @name MATCH - LPUART Match Address Register */
7515/*! @{ */
7516#define LPUART_MATCH_MA1_MASK (0x3FFU)
7517#define LPUART_MATCH_MA1_SHIFT (0U)
7518#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
7519#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
7520#define LPUART_MATCH_MA2_SHIFT (16U)
7521#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
7522/*! @} */
7523
7524/*! @name MODIR - LPUART Modem IrDA Register */
7525/*! @{ */
7526#define LPUART_MODIR_TXCTSE_MASK (0x1U)
7527#define LPUART_MODIR_TXCTSE_SHIFT (0U)
7528/*! TXCTSE - Transmitter clear-to-send enable
7529 * 0b0..CTS has no effect on the transmitter.
7530 * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
7531 */
7532#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
7533#define LPUART_MODIR_TXRTSE_MASK (0x2U)
7534#define LPUART_MODIR_TXRTSE_SHIFT (1U)
7535/*! TXRTSE - Transmitter request-to-send enable
7536 * 0b0..The transmitter has no effect on RTS.
7537 * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.
7538 */
7539#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
7540#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
7541#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
7542/*! TXRTSPOL - Transmitter request-to-send polarity
7543 * 0b0..Transmitter RTS is active low.
7544 * 0b1..Transmitter RTS is active high.
7545 */
7546#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
7547#define LPUART_MODIR_RXRTSE_MASK (0x8U)
7548#define LPUART_MODIR_RXRTSE_SHIFT (3U)
7549/*! RXRTSE - Receiver request-to-send enable
7550 * 0b0..The receiver has no effect on RTS.
7551 * 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.
7552 */
7553#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
7554#define LPUART_MODIR_TXCTSC_MASK (0x10U)
7555#define LPUART_MODIR_TXCTSC_SHIFT (4U)
7556/*! TXCTSC - Transmit CTS Configuration
7557 * 0b0..CTS input is sampled at the start of each character.
7558 * 0b1..CTS input is sampled when the transmitter is idle.
7559 */
7560#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
7561#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
7562#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
7563/*! TXCTSSRC - Transmit CTS Source
7564 * 0b0..CTS input is the LPUART_CTS pin.
7565 * 0b1..CTS input is the inverted Receiver Match result.
7566 */
7567#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
7568#define LPUART_MODIR_TNP_MASK (0x30000U)
7569#define LPUART_MODIR_TNP_SHIFT (16U)
7570/*! TNP - Transmitter narrow pulse
7571 * 0b00..1/OSR.
7572 * 0b01..2/OSR.
7573 * 0b10..3/OSR.
7574 * 0b11..4/OSR.
7575 */
7576#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
7577#define LPUART_MODIR_IREN_MASK (0x40000U)
7578#define LPUART_MODIR_IREN_SHIFT (18U)
7579/*! IREN - Infrared enable
7580 * 0b0..IR disabled.
7581 * 0b1..IR enabled.
7582 */
7583#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
7584/*! @} */
7585
7586
7587/*!
7588 * @}
7589 */ /* end of group LPUART_Register_Masks */
7590
7591
7592/* LPUART - Peripheral instance base addresses */
7593/** Peripheral LPUART0 base address */
7594#define LPUART0_BASE (0x4002A000u)
7595/** Peripheral LPUART0 base pointer */
7596#define LPUART0 ((LPUART_Type *)LPUART0_BASE)
7597/** Array initializer of LPUART peripheral base addresses */
7598#define LPUART_BASE_ADDRS { LPUART0_BASE }
7599/** Array initializer of LPUART peripheral base pointers */
7600#define LPUART_BASE_PTRS { LPUART0 }
7601/** Interrupt vectors for the LPUART peripheral type */
7602#define LPUART_RX_TX_IRQS { LPUART0_IRQn }
7603#define LPUART_ERR_IRQS { LPUART0_IRQn }
7604
7605/*!
7606 * @}
7607 */ /* end of group LPUART_Peripheral_Access_Layer */
7608
7609
7610/* ----------------------------------------------------------------------------
7611 -- MCG Peripheral Access Layer
7612 ---------------------------------------------------------------------------- */
7613
7614/*!
7615 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
7616 * @{
7617 */
7618
7619/** MCG - Register Layout Typedef */
7620typedef struct {
7621 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
7622 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
7623 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
7624 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
7625 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
7626 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
7627 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
7628 uint8_t RESERVED_0[1];
7629 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
7630 uint8_t RESERVED_1[1];
7631 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
7632 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
7633 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
7634 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
7635} MCG_Type;
7636
7637/* ----------------------------------------------------------------------------
7638 -- MCG Register Masks
7639 ---------------------------------------------------------------------------- */
7640
7641/*!
7642 * @addtogroup MCG_Register_Masks MCG Register Masks
7643 * @{
7644 */
7645
7646/*! @name C1 - MCG Control 1 Register */
7647/*! @{ */
7648#define MCG_C1_IREFSTEN_MASK (0x1U)
7649#define MCG_C1_IREFSTEN_SHIFT (0U)
7650/*! IREFSTEN - Internal Reference Stop Enable
7651 * 0b0..Internal reference clock is disabled in Stop mode.
7652 * 0b1..Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
7653 */
7654#define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
7655#define MCG_C1_IRCLKEN_MASK (0x2U)
7656#define MCG_C1_IRCLKEN_SHIFT (1U)
7657/*! IRCLKEN - Internal Reference Clock Enable
7658 * 0b0..MCGIRCLK inactive.
7659 * 0b1..MCGIRCLK active.
7660 */
7661#define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
7662#define MCG_C1_IREFS_MASK (0x4U)
7663#define MCG_C1_IREFS_SHIFT (2U)
7664/*! IREFS - Internal Reference Select
7665 * 0b0..External reference clock is selected.
7666 * 0b1..The slow internal reference clock is selected.
7667 */
7668#define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
7669#define MCG_C1_FRDIV_MASK (0x38U)
7670#define MCG_C1_FRDIV_SHIFT (3U)
7671/*! FRDIV - FLL External Reference Divider
7672 * 0b000..If RANGE = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.
7673 * 0b001..If RANGE = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.
7674 * 0b010..If RANGE = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.
7675 * 0b011..If RANGE = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
7676 * 0b100..If RANGE = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.
7677 * 0b101..If RANGE = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.
7678 * 0b110..If RANGE = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 .
7679 * 0b111..If RANGE = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .
7680 */
7681#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
7682#define MCG_C1_CLKS_MASK (0xC0U)
7683#define MCG_C1_CLKS_SHIFT (6U)
7684/*! CLKS - Clock Source Select
7685 * 0b00..Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit).
7686 * 0b01..Encoding 1 - Internal reference clock is selected.
7687 * 0b10..Encoding 2 - External reference clock is selected.
7688 * 0b11..Encoding 3 - Reserved.
7689 */
7690#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
7691/*! @} */
7692
7693/*! @name C2 - MCG Control 2 Register */
7694/*! @{ */
7695#define MCG_C2_IRCS_MASK (0x1U)
7696#define MCG_C2_IRCS_SHIFT (0U)
7697/*! IRCS - Internal Reference Clock Select
7698 * 0b0..Slow internal reference clock selected.
7699 * 0b1..Fast internal reference clock selected.
7700 */
7701#define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
7702#define MCG_C2_LP_MASK (0x2U)
7703#define MCG_C2_LP_SHIFT (1U)
7704/*! LP - Low Power Select
7705 * 0b0..FLL or PLL is not disabled in bypass modes.
7706 * 0b1..FLL or PLL is disabled in bypass modes (lower power)
7707 */
7708#define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
7709#define MCG_C2_EREFS_MASK (0x4U)
7710#define MCG_C2_EREFS_SHIFT (2U)
7711/*! EREFS - External Reference Select
7712 * 0b0..External reference clock requested.
7713 * 0b1..Oscillator requested.
7714 */
7715#define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
7716#define MCG_C2_HGO_MASK (0x8U)
7717#define MCG_C2_HGO_SHIFT (3U)
7718/*! HGO - High Gain Oscillator Select
7719 * 0b0..Configure crystal oscillator for low-power operation.
7720 * 0b1..Configure crystal oscillator for high-gain operation.
7721 */
7722#define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
7723#define MCG_C2_RANGE_MASK (0x30U)
7724#define MCG_C2_RANGE_SHIFT (4U)
7725/*! RANGE - Frequency Range Select
7726 * 0b00..Encoding 0 - Low frequency range selected for the crystal oscillator .
7727 * 0b01..Encoding 1 - High frequency range selected for the crystal oscillator .
7728 * 0b1x..Encoding 2 - Very high frequency range selected for the crystal oscillator .
7729 */
7730#define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
7731#define MCG_C2_FCFTRIM_MASK (0x40U)
7732#define MCG_C2_FCFTRIM_SHIFT (6U)
7733#define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
7734#define MCG_C2_LOCRE0_MASK (0x80U)
7735#define MCG_C2_LOCRE0_SHIFT (7U)
7736/*! LOCRE0 - Loss of Clock Reset Enable
7737 * 0b0..Interrupt request is generated on a loss of OSC0 external reference clock.
7738 * 0b1..Generate a reset request on a loss of OSC0 external reference clock.
7739 */
7740#define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
7741/*! @} */
7742
7743/*! @name C3 - MCG Control 3 Register */
7744/*! @{ */
7745#define MCG_C3_SCTRIM_MASK (0xFFU)
7746#define MCG_C3_SCTRIM_SHIFT (0U)
7747#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
7748/*! @} */
7749
7750/*! @name C4 - MCG Control 4 Register */
7751/*! @{ */
7752#define MCG_C4_SCFTRIM_MASK (0x1U)
7753#define MCG_C4_SCFTRIM_SHIFT (0U)
7754#define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
7755#define MCG_C4_FCTRIM_MASK (0x1EU)
7756#define MCG_C4_FCTRIM_SHIFT (1U)
7757#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
7758#define MCG_C4_DRST_DRS_MASK (0x60U)
7759#define MCG_C4_DRST_DRS_SHIFT (5U)
7760/*! DRST_DRS - DCO Range Select
7761 * 0b00..Encoding 0 - Low range (reset default).
7762 * 0b01..Encoding 1 - Mid range.
7763 * 0b10..Encoding 2 - Mid-high range.
7764 * 0b11..Encoding 3 - High range.
7765 */
7766#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
7767#define MCG_C4_DMX32_MASK (0x80U)
7768#define MCG_C4_DMX32_SHIFT (7U)
7769/*! DMX32 - DCO Maximum Frequency with 32.768 kHz Reference
7770 * 0b0..DCO has a default range of 25%.
7771 * 0b1..DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
7772 */
7773#define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
7774/*! @} */
7775
7776/*! @name C5 - MCG Control 5 Register */
7777/*! @{ */
7778#define MCG_C5_PRDIV0_MASK (0x1FU)
7779#define MCG_C5_PRDIV0_SHIFT (0U)
7780/*! PRDIV0 - PLL External Reference Divider
7781 * 0b00000..Divide Factor is 1
7782 * 0b00001..Divide Factor is 2
7783 * 0b00010..Divide Factor is 3
7784 * 0b00011..Divide Factor is 4
7785 * 0b00100..Divide Factor is 5
7786 * 0b00101..Divide Factor is 6
7787 * 0b00110..Divide Factor is 7
7788 * 0b00111..Divide Factor is 8
7789 * 0b01000..Divide Factor is 9
7790 * 0b01001..Divide Factor is 10
7791 * 0b01010..Divide Factor is 11
7792 * 0b01011..Divide Factor is 12
7793 * 0b01100..Divide Factor is 13
7794 * 0b01101..Divide Factor is 14
7795 * 0b01110..Divide Factor is 15
7796 * 0b01111..Divide Factor is 16
7797 * 0b10000..Divide Factor is 17
7798 * 0b10001..Divide Factor is 18
7799 * 0b10010..Divide Factor is 19
7800 * 0b10011..Divide Factor is 20
7801 * 0b10100..Divide Factor is 21
7802 * 0b10101..Divide Factor is 22
7803 * 0b10110..Divide Factor is 23
7804 * 0b10111..Divide Factor is 24
7805 * 0b11000..Divide Factor is 25
7806 * 0b11001..Divide Factor is 26
7807 * 0b11010..Divide Factor is 27
7808 * 0b11011..Divide Factor is 28
7809 * 0b11100..Divide Factor is 29
7810 * 0b11101..Divide Factor is 30
7811 * 0b11110..Divide Factor is 31
7812 * 0b11111..Divide Factor is 32
7813 */
7814#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
7815#define MCG_C5_PLLSTEN0_MASK (0x20U)
7816#define MCG_C5_PLLSTEN0_SHIFT (5U)
7817/*! PLLSTEN0 - PLL Stop Enable
7818 * 0b0..MCGPLLCLK is disabled in any of the Stop modes.
7819 * 0b1..MCGPLLCLK is enabled if system is in Normal Stop mode.
7820 */
7821#define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
7822#define MCG_C5_PLLCLKEN0_MASK (0x40U)
7823#define MCG_C5_PLLCLKEN0_SHIFT (6U)
7824/*! PLLCLKEN0 - PLL Clock Enable
7825 * 0b0..MCGPLLCLK is inactive.
7826 * 0b1..MCGPLLCLK is active.
7827 */
7828#define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
7829/*! @} */
7830
7831/*! @name C6 - MCG Control 6 Register */
7832/*! @{ */
7833#define MCG_C6_VDIV0_MASK (0x1FU)
7834#define MCG_C6_VDIV0_SHIFT (0U)
7835/*! VDIV0 - VCO 0 Divider
7836 * 0b00000..Multiply Factor is 24
7837 * 0b00001..Multiply Factor is 25
7838 * 0b00010..Multiply Factor is 26
7839 * 0b00011..Multiply Factor is 27
7840 * 0b00100..Multiply Factor is 28
7841 * 0b00101..Multiply Factor is 29
7842 * 0b00110..Multiply Factor is 30
7843 * 0b00111..Multiply Factor is 31
7844 * 0b01000..Multiply Factor is 32
7845 * 0b01001..Multiply Factor is 33
7846 * 0b01010..Multiply Factor is 34
7847 * 0b01011..Multiply Factor is 35
7848 * 0b01100..Multiply Factor is 36
7849 * 0b01101..Multiply Factor is 37
7850 * 0b01110..Multiply Factor is 38
7851 * 0b01111..Multiply Factor is 39
7852 * 0b10000..Multiply Factor is 40
7853 * 0b10001..Multiply Factor is 41
7854 * 0b10010..Multiply Factor is 42
7855 * 0b10011..Multiply Factor is 43
7856 * 0b10100..Multiply Factor is 44
7857 * 0b10101..Multiply Factor is 45
7858 * 0b10110..Multiply Factor is 46
7859 * 0b10111..Multiply Factor is 47
7860 * 0b11000..Multiply Factor is 48
7861 * 0b11001..Multiply Factor is 49
7862 * 0b11010..Multiply Factor is 50
7863 * 0b11011..Multiply Factor is 51
7864 * 0b11100..Multiply Factor is 52
7865 * 0b11101..Multiply Factor is 53
7866 * 0b11110..Multiply Factor is 54
7867 * 0b11111..Multiply Factor is 55
7868 */
7869#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
7870#define MCG_C6_CME0_MASK (0x20U)
7871#define MCG_C6_CME0_SHIFT (5U)
7872/*! CME0 - Clock Monitor Enable
7873 * 0b0..External clock monitor is disabled for OSC0.
7874 * 0b1..External clock monitor is enabled for OSC0.
7875 */
7876#define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
7877#define MCG_C6_PLLS_MASK (0x40U)
7878#define MCG_C6_PLLS_SHIFT (6U)
7879/*! PLLS - PLL Select
7880 * 0b0..FLL is selected.
7881 * 0b1..PLL is selected (PRDIV 0 need to be programmed to the correct divider to generate a PLL reference clock in the range of 2-4 MHz prior to setting the PLLS bit).
7882 */
7883#define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
7884#define MCG_C6_LOLIE0_MASK (0x80U)
7885#define MCG_C6_LOLIE0_SHIFT (7U)
7886/*! LOLIE0 - Loss of Lock Interrrupt Enable
7887 * 0b0..No interrupt request is generated on loss of lock.
7888 * 0b1..Generate an interrupt request on loss of lock.
7889 */
7890#define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
7891/*! @} */
7892
7893/*! @name S - MCG Status Register */
7894/*! @{ */
7895#define MCG_S_IRCST_MASK (0x1U)
7896#define MCG_S_IRCST_SHIFT (0U)
7897/*! IRCST - Internal Reference Clock Status
7898 * 0b0..Source of internal reference clock is the slow clock (32 kHz IRC).
7899 * 0b1..Source of internal reference clock is the fast clock (4 MHz IRC).
7900 */
7901#define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
7902#define MCG_S_OSCINIT0_MASK (0x2U)
7903#define MCG_S_OSCINIT0_SHIFT (1U)
7904#define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
7905#define MCG_S_CLKST_MASK (0xCU)
7906#define MCG_S_CLKST_SHIFT (2U)
7907/*! CLKST - Clock Mode Status
7908 * 0b00..Encoding 0 - Output of the FLL is selected (reset default).
7909 * 0b01..Encoding 1 - Internal reference clock is selected.
7910 * 0b10..Encoding 2 - External reference clock is selected.
7911 * 0b11..Encoding 3 - Output of the PLL is selected.
7912 */
7913#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
7914#define MCG_S_IREFST_MASK (0x10U)
7915#define MCG_S_IREFST_SHIFT (4U)
7916/*! IREFST - Internal Reference Status
7917 * 0b0..Source of FLL reference clock is the external reference clock.
7918 * 0b1..Source of FLL reference clock is the internal reference clock.
7919 */
7920#define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
7921#define MCG_S_PLLST_MASK (0x20U)
7922#define MCG_S_PLLST_SHIFT (5U)
7923/*! PLLST - PLL Select Status
7924 * 0b0..Source of PLLS clock is FLL clock.
7925 * 0b1..Source of PLLS clock is PLL output clock.
7926 */
7927#define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
7928#define MCG_S_LOCK0_MASK (0x40U)
7929#define MCG_S_LOCK0_SHIFT (6U)
7930/*! LOCK0 - Lock Status
7931 * 0b0..PLL is currently unlocked.
7932 * 0b1..PLL is currently locked.
7933 */
7934#define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
7935#define MCG_S_LOLS0_MASK (0x80U)
7936#define MCG_S_LOLS0_SHIFT (7U)
7937/*! LOLS0 - Loss of Lock Status
7938 * 0b0..PLL has not lost lock since LOLS 0 was last cleared.
7939 * 0b1..PLL has lost lock since LOLS 0 was last cleared.
7940 */
7941#define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
7942/*! @} */
7943
7944/*! @name SC - MCG Status and Control Register */
7945/*! @{ */
7946#define MCG_SC_LOCS0_MASK (0x1U)
7947#define MCG_SC_LOCS0_SHIFT (0U)
7948/*! LOCS0 - OSC0 Loss of Clock Status
7949 * 0b0..Loss of OSC0 has not occurred.
7950 * 0b1..Loss of OSC0 has occurred.
7951 */
7952#define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
7953#define MCG_SC_FCRDIV_MASK (0xEU)
7954#define MCG_SC_FCRDIV_SHIFT (1U)
7955/*! FCRDIV - Fast Clock Internal Reference Divider
7956 * 0b000..Divide Factor is 1
7957 * 0b001..Divide Factor is 2.
7958 * 0b010..Divide Factor is 4.
7959 * 0b011..Divide Factor is 8.
7960 * 0b100..Divide Factor is 16
7961 * 0b101..Divide Factor is 32
7962 * 0b110..Divide Factor is 64
7963 * 0b111..Divide Factor is 128.
7964 */
7965#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
7966#define MCG_SC_FLTPRSRV_MASK (0x10U)
7967#define MCG_SC_FLTPRSRV_SHIFT (4U)
7968/*! FLTPRSRV - FLL Filter Preserve Enable
7969 * 0b0..FLL filter and FLL frequency will reset on changes to currect clock mode.
7970 * 0b1..Fll filter and FLL frequency retain their previous values during new clock mode change.
7971 */
7972#define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
7973#define MCG_SC_ATMF_MASK (0x20U)
7974#define MCG_SC_ATMF_SHIFT (5U)
7975/*! ATMF - Automatic Trim Machine Fail Flag
7976 * 0b0..Automatic Trim Machine completed normally.
7977 * 0b1..Automatic Trim Machine failed.
7978 */
7979#define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
7980#define MCG_SC_ATMS_MASK (0x40U)
7981#define MCG_SC_ATMS_SHIFT (6U)
7982/*! ATMS - Automatic Trim Machine Select
7983 * 0b0..32 kHz Internal Reference Clock selected.
7984 * 0b1..4 MHz Internal Reference Clock selected.
7985 */
7986#define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
7987#define MCG_SC_ATME_MASK (0x80U)
7988#define MCG_SC_ATME_SHIFT (7U)
7989/*! ATME - Automatic Trim Machine Enable
7990 * 0b0..Auto Trim Machine disabled.
7991 * 0b1..Auto Trim Machine enabled.
7992 */
7993#define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
7994/*! @} */
7995
7996/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
7997/*! @{ */
7998#define MCG_ATCVH_ATCVH_MASK (0xFFU)
7999#define MCG_ATCVH_ATCVH_SHIFT (0U)
8000#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
8001/*! @} */
8002
8003/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
8004/*! @{ */
8005#define MCG_ATCVL_ATCVL_MASK (0xFFU)
8006#define MCG_ATCVL_ATCVL_SHIFT (0U)
8007#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
8008/*! @} */
8009
8010/*! @name C7 - MCG Control 7 Register */
8011/*! @{ */
8012#define MCG_C7_OSCSEL_MASK (0x3U)
8013#define MCG_C7_OSCSEL_SHIFT (0U)
8014/*! OSCSEL - MCG OSC Clock Select
8015 * 0b00..Selects Oscillator (OSCCLK0).
8016 * 0b01..Selects 32 kHz RTC Oscillator.
8017 * 0b10..Selects Oscillator (OSCCLK1).
8018 * 0b11..RESERVED
8019 */
8020#define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
8021/*! @} */
8022
8023/*! @name C8 - MCG Control 8 Register */
8024/*! @{ */
8025#define MCG_C8_LOCS1_MASK (0x1U)
8026#define MCG_C8_LOCS1_SHIFT (0U)
8027/*! LOCS1 - RTC Loss of Clock Status
8028 * 0b0..Loss of RTC has not occur.
8029 * 0b1..Loss of RTC has occur
8030 */
8031#define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
8032#define MCG_C8_CME1_MASK (0x20U)
8033#define MCG_C8_CME1_SHIFT (5U)
8034/*! CME1 - Clock Monitor Enable1
8035 * 0b0..External clock monitor is disabled for RTC clock.
8036 * 0b1..External clock monitor is enabled for RTC clock.
8037 */
8038#define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
8039#define MCG_C8_LOLRE_MASK (0x40U)
8040#define MCG_C8_LOLRE_SHIFT (6U)
8041/*! LOLRE - PLL Loss of Lock Reset Enable
8042 * 0b0..Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request.
8043 * 0b1..Generate a reset request on a PLL loss of lock indication.
8044 */
8045#define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
8046#define MCG_C8_LOCRE1_MASK (0x80U)
8047#define MCG_C8_LOCRE1_SHIFT (7U)
8048/*! LOCRE1 - Loss of Clock Reset Enable
8049 * 0b0..Interrupt request is generated on a loss of RTC external reference clock.
8050 * 0b1..Generate a reset request on a loss of RTC external reference clock
8051 */
8052#define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
8053/*! @} */
8054
8055
8056/*!
8057 * @}
8058 */ /* end of group MCG_Register_Masks */
8059
8060
8061/* MCG - Peripheral instance base addresses */
8062/** Peripheral MCG base address */
8063#define MCG_BASE (0x40064000u)
8064/** Peripheral MCG base pointer */
8065#define MCG ((MCG_Type *)MCG_BASE)
8066/** Array initializer of MCG peripheral base addresses */
8067#define MCG_BASE_ADDRS { MCG_BASE }
8068/** Array initializer of MCG peripheral base pointers */
8069#define MCG_BASE_PTRS { MCG }
8070
8071/*!
8072 * @}
8073 */ /* end of group MCG_Peripheral_Access_Layer */
8074
8075
8076/* ----------------------------------------------------------------------------
8077 -- MCM Peripheral Access Layer
8078 ---------------------------------------------------------------------------- */
8079
8080/*!
8081 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
8082 * @{
8083 */
8084
8085/** MCM - Register Layout Typedef */
8086typedef struct {
8087 uint8_t RESERVED_0[8];
8088 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
8089 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
8090 __IO uint32_t PLACR; /**< Crossbar Switch (AXBS) Control Register, offset: 0xC */
8091 __IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
8092 uint8_t RESERVED_1[44];
8093 __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */
8094} MCM_Type;
8095
8096/* ----------------------------------------------------------------------------
8097 -- MCM Register Masks
8098 ---------------------------------------------------------------------------- */
8099
8100/*!
8101 * @addtogroup MCM_Register_Masks MCM Register Masks
8102 * @{
8103 */
8104
8105/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
8106/*! @{ */
8107#define MCM_PLASC_ASC_MASK (0xFFU)
8108#define MCM_PLASC_ASC_SHIFT (0U)
8109/*! ASC - Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
8110 * 0b00000000..A bus slave connection to AXBS input port n is absent
8111 * 0b00000001..A bus slave connection to AXBS input port n is present
8112 */
8113#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
8114/*! @} */
8115
8116/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
8117/*! @{ */
8118#define MCM_PLAMC_AMC_MASK (0xFFU)
8119#define MCM_PLAMC_AMC_SHIFT (0U)
8120/*! AMC - Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
8121 * 0b00000000..A bus master connection to AXBS input port n is absent
8122 * 0b00000001..A bus master connection to AXBS input port n is present
8123 */
8124#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
8125/*! @} */
8126
8127/*! @name PLACR - Crossbar Switch (AXBS) Control Register */
8128/*! @{ */
8129#define MCM_PLACR_ARB_MASK (0x200U)
8130#define MCM_PLACR_ARB_SHIFT (9U)
8131/*! ARB - Arbitration select
8132 * 0b0..Fixed-priority arbitration for the crossbar masters
8133 * 0b1..Round-robin arbitration for the crossbar masters
8134 */
8135#define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK)
8136/*! @} */
8137
8138/*! @name ISCR - Interrupt Status and Control Register */
8139/*! @{ */
8140#define MCM_ISCR_FIOC_MASK (0x100U)
8141#define MCM_ISCR_FIOC_SHIFT (8U)
8142/*! FIOC - FPU invalid operation interrupt status
8143 * 0b0..No interrupt
8144 * 0b1..Interrupt occurred
8145 */
8146#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
8147#define MCM_ISCR_FDZC_MASK (0x200U)
8148#define MCM_ISCR_FDZC_SHIFT (9U)
8149/*! FDZC - FPU divide-by-zero interrupt status
8150 * 0b0..No interrupt
8151 * 0b1..Interrupt occurred
8152 */
8153#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
8154#define MCM_ISCR_FOFC_MASK (0x400U)
8155#define MCM_ISCR_FOFC_SHIFT (10U)
8156/*! FOFC - FPU overflow interrupt status
8157 * 0b0..No interrupt
8158 * 0b1..Interrupt occurred
8159 */
8160#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
8161#define MCM_ISCR_FUFC_MASK (0x800U)
8162#define MCM_ISCR_FUFC_SHIFT (11U)
8163/*! FUFC - FPU underflow interrupt status
8164 * 0b0..No interrupt
8165 * 0b1..Interrupt occurred
8166 */
8167#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
8168#define MCM_ISCR_FIXC_MASK (0x1000U)
8169#define MCM_ISCR_FIXC_SHIFT (12U)
8170/*! FIXC - FPU inexact interrupt status
8171 * 0b0..No interrupt
8172 * 0b1..Interrupt occurred
8173 */
8174#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
8175#define MCM_ISCR_FIDC_MASK (0x8000U)
8176#define MCM_ISCR_FIDC_SHIFT (15U)
8177/*! FIDC - FPU input denormal interrupt status
8178 * 0b0..No interrupt
8179 * 0b1..Interrupt occurred
8180 */
8181#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
8182#define MCM_ISCR_FIOCE_MASK (0x1000000U)
8183#define MCM_ISCR_FIOCE_SHIFT (24U)
8184/*! FIOCE - FPU invalid operation interrupt enable
8185 * 0b0..Disable interrupt
8186 * 0b1..Enable interrupt
8187 */
8188#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
8189#define MCM_ISCR_FDZCE_MASK (0x2000000U)
8190#define MCM_ISCR_FDZCE_SHIFT (25U)
8191/*! FDZCE - FPU divide-by-zero interrupt enable
8192 * 0b0..Disable interrupt
8193 * 0b1..Enable interrupt
8194 */
8195#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
8196#define MCM_ISCR_FOFCE_MASK (0x4000000U)
8197#define MCM_ISCR_FOFCE_SHIFT (26U)
8198/*! FOFCE - FPU overflow interrupt enable
8199 * 0b0..Disable interrupt
8200 * 0b1..Enable interrupt
8201 */
8202#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
8203#define MCM_ISCR_FUFCE_MASK (0x8000000U)
8204#define MCM_ISCR_FUFCE_SHIFT (27U)
8205/*! FUFCE - FPU underflow interrupt enable
8206 * 0b0..Disable interrupt
8207 * 0b1..Enable interrupt
8208 */
8209#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
8210#define MCM_ISCR_FIXCE_MASK (0x10000000U)
8211#define MCM_ISCR_FIXCE_SHIFT (28U)
8212/*! FIXCE - FPU inexact interrupt enable
8213 * 0b0..Disable interrupt
8214 * 0b1..Enable interrupt
8215 */
8216#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
8217#define MCM_ISCR_FIDCE_MASK (0x80000000U)
8218#define MCM_ISCR_FIDCE_SHIFT (31U)
8219/*! FIDCE - FPU input denormal interrupt enable
8220 * 0b0..Disable interrupt
8221 * 0b1..Enable interrupt
8222 */
8223#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
8224/*! @} */
8225
8226/*! @name CPO - Compute Operation Control Register */
8227/*! @{ */
8228#define MCM_CPO_CPOREQ_MASK (0x1U)
8229#define MCM_CPO_CPOREQ_SHIFT (0U)
8230/*! CPOREQ - Compute Operation request
8231 * 0b0..Request is cleared.
8232 * 0b1..Request Compute Operation.
8233 */
8234#define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
8235#define MCM_CPO_CPOACK_MASK (0x2U)
8236#define MCM_CPO_CPOACK_SHIFT (1U)
8237/*! CPOACK - Compute Operation acknowledge
8238 * 0b0..Compute operation entry has not completed or compute operation exit has completed.
8239 * 0b1..Compute operation entry has completed or compute operation exit has not completed.
8240 */
8241#define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
8242#define MCM_CPO_CPOWOI_MASK (0x4U)
8243#define MCM_CPO_CPOWOI_SHIFT (2U)
8244/*! CPOWOI - Compute Operation wakeup on interrupt
8245 * 0b0..No effect.
8246 * 0b1..When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
8247 */
8248#define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
8249/*! @} */
8250
8251
8252/*!
8253 * @}
8254 */ /* end of group MCM_Register_Masks */
8255
8256
8257/* MCM - Peripheral instance base addresses */
8258/** Peripheral MCM base address */
8259#define MCM_BASE (0xE0080000u)
8260/** Peripheral MCM base pointer */
8261#define MCM ((MCM_Type *)MCM_BASE)
8262/** Array initializer of MCM peripheral base addresses */
8263#define MCM_BASE_ADDRS { MCM_BASE }
8264/** Array initializer of MCM peripheral base pointers */
8265#define MCM_BASE_PTRS { MCM }
8266/** Interrupt vectors for the MCM peripheral type */
8267#define MCM_IRQS { MCM_IRQn }
8268
8269/*!
8270 * @}
8271 */ /* end of group MCM_Peripheral_Access_Layer */
8272
8273
8274/* ----------------------------------------------------------------------------
8275 -- NV Peripheral Access Layer
8276 ---------------------------------------------------------------------------- */
8277
8278/*!
8279 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
8280 * @{
8281 */
8282
8283/** NV - Register Layout Typedef */
8284typedef struct {
8285 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
8286 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
8287 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
8288 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
8289 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
8290 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
8291 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
8292 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
8293 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
8294 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
8295 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
8296 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
8297 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
8298 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
8299} NV_Type;
8300
8301/* ----------------------------------------------------------------------------
8302 -- NV Register Masks
8303 ---------------------------------------------------------------------------- */
8304
8305/*!
8306 * @addtogroup NV_Register_Masks NV Register Masks
8307 * @{
8308 */
8309
8310/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
8311/*! @{ */
8312#define NV_BACKKEY3_KEY_MASK (0xFFU)
8313#define NV_BACKKEY3_KEY_SHIFT (0U)
8314#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
8315/*! @} */
8316
8317/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
8318/*! @{ */
8319#define NV_BACKKEY2_KEY_MASK (0xFFU)
8320#define NV_BACKKEY2_KEY_SHIFT (0U)
8321#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
8322/*! @} */
8323
8324/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
8325/*! @{ */
8326#define NV_BACKKEY1_KEY_MASK (0xFFU)
8327#define NV_BACKKEY1_KEY_SHIFT (0U)
8328#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
8329/*! @} */
8330
8331/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
8332/*! @{ */
8333#define NV_BACKKEY0_KEY_MASK (0xFFU)
8334#define NV_BACKKEY0_KEY_SHIFT (0U)
8335#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
8336/*! @} */
8337
8338/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
8339/*! @{ */
8340#define NV_BACKKEY7_KEY_MASK (0xFFU)
8341#define NV_BACKKEY7_KEY_SHIFT (0U)
8342#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
8343/*! @} */
8344
8345/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
8346/*! @{ */
8347#define NV_BACKKEY6_KEY_MASK (0xFFU)
8348#define NV_BACKKEY6_KEY_SHIFT (0U)
8349#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
8350/*! @} */
8351
8352/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
8353/*! @{ */
8354#define NV_BACKKEY5_KEY_MASK (0xFFU)
8355#define NV_BACKKEY5_KEY_SHIFT (0U)
8356#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
8357/*! @} */
8358
8359/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
8360/*! @{ */
8361#define NV_BACKKEY4_KEY_MASK (0xFFU)
8362#define NV_BACKKEY4_KEY_SHIFT (0U)
8363#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
8364/*! @} */
8365
8366/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
8367/*! @{ */
8368#define NV_FPROT3_PROT_MASK (0xFFU)
8369#define NV_FPROT3_PROT_SHIFT (0U)
8370#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
8371/*! @} */
8372
8373/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
8374/*! @{ */
8375#define NV_FPROT2_PROT_MASK (0xFFU)
8376#define NV_FPROT2_PROT_SHIFT (0U)
8377#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
8378/*! @} */
8379
8380/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
8381/*! @{ */
8382#define NV_FPROT1_PROT_MASK (0xFFU)
8383#define NV_FPROT1_PROT_SHIFT (0U)
8384#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
8385/*! @} */
8386
8387/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
8388/*! @{ */
8389#define NV_FPROT0_PROT_MASK (0xFFU)
8390#define NV_FPROT0_PROT_SHIFT (0U)
8391#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
8392/*! @} */
8393
8394/*! @name FSEC - Non-volatile Flash Security Register */
8395/*! @{ */
8396#define NV_FSEC_SEC_MASK (0x3U)
8397#define NV_FSEC_SEC_SHIFT (0U)
8398/*! SEC - Flash Security
8399 * 0b10..MCU security status is unsecure
8400 * 0b11..MCU security status is secure
8401 */
8402#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
8403#define NV_FSEC_FSLACC_MASK (0xCU)
8404#define NV_FSEC_FSLACC_SHIFT (2U)
8405/*! FSLACC - Freescale Failure Analysis Access Code
8406 * 0b10..Freescale factory access denied
8407 * 0b11..Freescale factory access granted
8408 */
8409#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
8410#define NV_FSEC_MEEN_MASK (0x30U)
8411#define NV_FSEC_MEEN_SHIFT (4U)
8412/*! MEEN
8413 * 0b10..Mass erase is disabled
8414 * 0b11..Mass erase is enabled
8415 */
8416#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
8417#define NV_FSEC_KEYEN_MASK (0xC0U)
8418#define NV_FSEC_KEYEN_SHIFT (6U)
8419/*! KEYEN - Backdoor Key Security Enable
8420 * 0b10..Backdoor key access enabled
8421 * 0b11..Backdoor key access disabled
8422 */
8423#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
8424/*! @} */
8425
8426/*! @name FOPT - Non-volatile Flash Option Register */
8427/*! @{ */
8428#define NV_FOPT_LPBOOT_MASK (0x1U)
8429#define NV_FOPT_LPBOOT_SHIFT (0U)
8430/*! LPBOOT
8431 * 0b0..Low-power boot
8432 * 0b1..Normal boot
8433 */
8434#define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
8435#define NV_FOPT_EZPORT_DIS_MASK (0x2U)
8436#define NV_FOPT_EZPORT_DIS_SHIFT (1U)
8437/*! EZPORT_DIS
8438 * 0b0..EzPort operation is disabled
8439 * 0b1..EzPort operation is enabled
8440 */
8441#define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
8442#define NV_FOPT_NMI_DIS_MASK (0x4U)
8443#define NV_FOPT_NMI_DIS_SHIFT (2U)
8444/*! NMI_DIS
8445 * 0b0..NMI interrupts are always blocked
8446 * 0b1..NMI_b pin/interrupts reset default to enabled
8447 */
8448#define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
8449#define NV_FOPT_FAST_INIT_MASK (0x20U)
8450#define NV_FOPT_FAST_INIT_SHIFT (5U)
8451/*! FAST_INIT
8452 * 0b0..Slower initialization
8453 * 0b1..Fast Initialization
8454 */
8455#define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK)
8456/*! @} */
8457
8458
8459/*!
8460 * @}
8461 */ /* end of group NV_Register_Masks */
8462
8463
8464/* NV - Peripheral instance base addresses */
8465/** Peripheral FTFA_FlashConfig base address */
8466#define FTFA_FlashConfig_BASE (0x400u)
8467/** Peripheral FTFA_FlashConfig base pointer */
8468#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
8469/** Array initializer of NV peripheral base addresses */
8470#define NV_BASE_ADDRS { FTFA_FlashConfig_BASE }
8471/** Array initializer of NV peripheral base pointers */
8472#define NV_BASE_PTRS { FTFA_FlashConfig }
8473
8474/*!
8475 * @}
8476 */ /* end of group NV_Peripheral_Access_Layer */
8477
8478
8479/* ----------------------------------------------------------------------------
8480 -- OSC Peripheral Access Layer
8481 ---------------------------------------------------------------------------- */
8482
8483/*!
8484 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
8485 * @{
8486 */
8487
8488/** OSC - Register Layout Typedef */
8489typedef struct {
8490 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
8491 uint8_t RESERVED_0[1];
8492 __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */
8493} OSC_Type;
8494
8495/* ----------------------------------------------------------------------------
8496 -- OSC Register Masks
8497 ---------------------------------------------------------------------------- */
8498
8499/*!
8500 * @addtogroup OSC_Register_Masks OSC Register Masks
8501 * @{
8502 */
8503
8504/*! @name CR - OSC Control Register */
8505/*! @{ */
8506#define OSC_CR_SC16P_MASK (0x1U)
8507#define OSC_CR_SC16P_SHIFT (0U)
8508/*! SC16P - Oscillator 16 pF Capacitor Load Configure
8509 * 0b0..Disable the selection.
8510 * 0b1..Add 16 pF capacitor to the oscillator load.
8511 */
8512#define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
8513#define OSC_CR_SC8P_MASK (0x2U)
8514#define OSC_CR_SC8P_SHIFT (1U)
8515/*! SC8P - Oscillator 8 pF Capacitor Load Configure
8516 * 0b0..Disable the selection.
8517 * 0b1..Add 8 pF capacitor to the oscillator load.
8518 */
8519#define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
8520#define OSC_CR_SC4P_MASK (0x4U)
8521#define OSC_CR_SC4P_SHIFT (2U)
8522/*! SC4P - Oscillator 4 pF Capacitor Load Configure
8523 * 0b0..Disable the selection.
8524 * 0b1..Add 4 pF capacitor to the oscillator load.
8525 */
8526#define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
8527#define OSC_CR_SC2P_MASK (0x8U)
8528#define OSC_CR_SC2P_SHIFT (3U)
8529/*! SC2P - Oscillator 2 pF Capacitor Load Configure
8530 * 0b0..Disable the selection.
8531 * 0b1..Add 2 pF capacitor to the oscillator load.
8532 */
8533#define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
8534#define OSC_CR_EREFSTEN_MASK (0x20U)
8535#define OSC_CR_EREFSTEN_SHIFT (5U)
8536/*! EREFSTEN - External Reference Stop Enable
8537 * 0b0..External reference clock is disabled in Stop mode.
8538 * 0b1..External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
8539 */
8540#define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
8541#define OSC_CR_ERCLKEN_MASK (0x80U)
8542#define OSC_CR_ERCLKEN_SHIFT (7U)
8543/*! ERCLKEN - External Reference Enable
8544 * 0b0..External reference clock is inactive.
8545 * 0b1..External reference clock is enabled.
8546 */
8547#define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
8548/*! @} */
8549
8550/*! @name DIV - OSC_DIV */
8551/*! @{ */
8552#define OSC_DIV_ERPS_MASK (0xC0U)
8553#define OSC_DIV_ERPS_SHIFT (6U)
8554/*! ERPS
8555 * 0b00..The divisor ratio is 1.
8556 * 0b01..The divisor ratio is 2.
8557 * 0b10..The divisor ratio is 4.
8558 * 0b11..The divisor ratio is 8.
8559 */
8560#define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK)
8561/*! @} */
8562
8563
8564/*!
8565 * @}
8566 */ /* end of group OSC_Register_Masks */
8567
8568
8569/* OSC - Peripheral instance base addresses */
8570/** Peripheral OSC base address */
8571#define OSC_BASE (0x40065000u)
8572/** Peripheral OSC base pointer */
8573#define OSC ((OSC_Type *)OSC_BASE)
8574/** Array initializer of OSC peripheral base addresses */
8575#define OSC_BASE_ADDRS { OSC_BASE }
8576/** Array initializer of OSC peripheral base pointers */
8577#define OSC_BASE_PTRS { OSC }
8578
8579/*!
8580 * @}
8581 */ /* end of group OSC_Peripheral_Access_Layer */
8582
8583
8584/* ----------------------------------------------------------------------------
8585 -- PDB Peripheral Access Layer
8586 ---------------------------------------------------------------------------- */
8587
8588/*!
8589 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
8590 * @{
8591 */
8592
8593/** PDB - Register Layout Typedef */
8594typedef struct {
8595 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
8596 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
8597 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
8598 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
8599 struct { /* offset: 0x10, array step: 0x28 */
8600 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
8601 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
8602 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
8603 uint8_t RESERVED_0[24];
8604 } CH[2];
8605 uint8_t RESERVED_0[240];
8606 struct { /* offset: 0x150, array step: 0x8 */
8607 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
8608 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
8609 } DAC[1];
8610 uint8_t RESERVED_1[56];
8611 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
8612 __IO uint32_t PODLY[2]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
8613} PDB_Type;
8614
8615/* ----------------------------------------------------------------------------
8616 -- PDB Register Masks
8617 ---------------------------------------------------------------------------- */
8618
8619/*!
8620 * @addtogroup PDB_Register_Masks PDB Register Masks
8621 * @{
8622 */
8623
8624/*! @name SC - Status and Control register */
8625/*! @{ */
8626#define PDB_SC_LDOK_MASK (0x1U)
8627#define PDB_SC_LDOK_SHIFT (0U)
8628#define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
8629#define PDB_SC_CONT_MASK (0x2U)
8630#define PDB_SC_CONT_SHIFT (1U)
8631/*! CONT - Continuous Mode Enable
8632 * 0b0..PDB operation in One-Shot mode
8633 * 0b1..PDB operation in Continuous mode
8634 */
8635#define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
8636#define PDB_SC_MULT_MASK (0xCU)
8637#define PDB_SC_MULT_SHIFT (2U)
8638/*! MULT - Multiplication Factor Select for Prescaler
8639 * 0b00..Multiplication factor is 1.
8640 * 0b01..Multiplication factor is 10.
8641 * 0b10..Multiplication factor is 20.
8642 * 0b11..Multiplication factor is 40.
8643 */
8644#define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
8645#define PDB_SC_PDBIE_MASK (0x20U)
8646#define PDB_SC_PDBIE_SHIFT (5U)
8647/*! PDBIE - PDB Interrupt Enable
8648 * 0b0..PDB interrupt disabled.
8649 * 0b1..PDB interrupt enabled.
8650 */
8651#define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
8652#define PDB_SC_PDBIF_MASK (0x40U)
8653#define PDB_SC_PDBIF_SHIFT (6U)
8654#define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
8655#define PDB_SC_PDBEN_MASK (0x80U)
8656#define PDB_SC_PDBEN_SHIFT (7U)
8657/*! PDBEN - PDB Enable
8658 * 0b0..PDB disabled. Counter is off.
8659 * 0b1..PDB enabled.
8660 */
8661#define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
8662#define PDB_SC_TRGSEL_MASK (0xF00U)
8663#define PDB_SC_TRGSEL_SHIFT (8U)
8664/*! TRGSEL - Trigger Input Source Select
8665 * 0b0000..Trigger-In 0 is selected.
8666 * 0b0001..Trigger-In 1 is selected.
8667 * 0b0010..Trigger-In 2 is selected.
8668 * 0b0011..Trigger-In 3 is selected.
8669 * 0b0100..Trigger-In 4 is selected.
8670 * 0b0101..Trigger-In 5 is selected.
8671 * 0b0110..Trigger-In 6 is selected.
8672 * 0b0111..Trigger-In 7 is selected.
8673 * 0b1000..Trigger-In 8 is selected.
8674 * 0b1001..Trigger-In 9 is selected.
8675 * 0b1010..Trigger-In 10 is selected.
8676 * 0b1011..Trigger-In 11 is selected.
8677 * 0b1100..Trigger-In 12 is selected.
8678 * 0b1101..Trigger-In 13 is selected.
8679 * 0b1110..Trigger-In 14 is selected.
8680 * 0b1111..Software trigger is selected.
8681 */
8682#define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
8683#define PDB_SC_PRESCALER_MASK (0x7000U)
8684#define PDB_SC_PRESCALER_SHIFT (12U)
8685/*! PRESCALER - Prescaler Divider Select
8686 * 0b000..Counting uses the peripheral clock divided by multiplication factor selected by MULT.
8687 * 0b001..Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT.
8688 * 0b010..Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT.
8689 * 0b011..Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT.
8690 * 0b100..Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT.
8691 * 0b101..Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT.
8692 * 0b110..Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT.
8693 * 0b111..Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT.
8694 */
8695#define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
8696#define PDB_SC_DMAEN_MASK (0x8000U)
8697#define PDB_SC_DMAEN_SHIFT (15U)
8698/*! DMAEN - DMA Enable
8699 * 0b0..DMA disabled.
8700 * 0b1..DMA enabled.
8701 */
8702#define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
8703#define PDB_SC_SWTRIG_MASK (0x10000U)
8704#define PDB_SC_SWTRIG_SHIFT (16U)
8705#define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
8706#define PDB_SC_PDBEIE_MASK (0x20000U)
8707#define PDB_SC_PDBEIE_SHIFT (17U)
8708/*! PDBEIE - PDB Sequence Error Interrupt Enable
8709 * 0b0..PDB sequence error interrupt disabled.
8710 * 0b1..PDB sequence error interrupt enabled.
8711 */
8712#define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
8713#define PDB_SC_LDMOD_MASK (0xC0000U)
8714#define PDB_SC_LDMOD_SHIFT (18U)
8715/*! LDMOD - Load Mode Select
8716 * 0b00..The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.
8717 * 0b01..The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK.
8718 * 0b10..The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK.
8719 * 0b11..The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK.
8720 */
8721#define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
8722/*! @} */
8723
8724/*! @name MOD - Modulus register */
8725/*! @{ */
8726#define PDB_MOD_MOD_MASK (0xFFFFU)
8727#define PDB_MOD_MOD_SHIFT (0U)
8728#define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
8729/*! @} */
8730
8731/*! @name CNT - Counter register */
8732/*! @{ */
8733#define PDB_CNT_CNT_MASK (0xFFFFU)
8734#define PDB_CNT_CNT_SHIFT (0U)
8735#define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
8736/*! @} */
8737
8738/*! @name IDLY - Interrupt Delay register */
8739/*! @{ */
8740#define PDB_IDLY_IDLY_MASK (0xFFFFU)
8741#define PDB_IDLY_IDLY_SHIFT (0U)
8742#define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
8743/*! @} */
8744
8745/*! @name C1 - Channel n Control register 1 */
8746/*! @{ */
8747#define PDB_C1_EN_MASK (0xFFU)
8748#define PDB_C1_EN_SHIFT (0U)
8749/*! EN - PDB Channel Pre-Trigger Enable
8750 * 0b00000000..PDB channel's corresponding pre-trigger disabled.
8751 * 0b00000001..PDB channel's corresponding pre-trigger enabled.
8752 */
8753#define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
8754#define PDB_C1_TOS_MASK (0xFF00U)
8755#define PDB_C1_TOS_SHIFT (8U)
8756/*! TOS - PDB Channel Pre-Trigger Output Select
8757 * 0b00000000..PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
8758 * 0b00000001..PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register and one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1.
8759 */
8760#define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
8761#define PDB_C1_BB_MASK (0xFF0000U)
8762#define PDB_C1_BB_SHIFT (16U)
8763/*! BB - PDB Channel Pre-Trigger Back-to-Back Operation Enable
8764 * 0b00000000..PDB channel's corresponding pre-trigger back-to-back operation disabled.
8765 * 0b00000001..PDB channel's corresponding pre-trigger back-to-back operation enabled.
8766 */
8767#define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
8768/*! @} */
8769
8770/* The count of PDB_C1 */
8771#define PDB_C1_COUNT (2U)
8772
8773/*! @name S - Channel n Status register */
8774/*! @{ */
8775#define PDB_S_ERR_MASK (0xFFU)
8776#define PDB_S_ERR_SHIFT (0U)
8777/*! ERR - PDB Channel Sequence Error Flags
8778 * 0b00000000..Sequence error not detected on PDB channel's corresponding pre-trigger.
8779 * 0b00000001..Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0's to clear the sequence error flags.
8780 */
8781#define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
8782#define PDB_S_CF_MASK (0xFF0000U)
8783#define PDB_S_CF_SHIFT (16U)
8784#define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
8785/*! @} */
8786
8787/* The count of PDB_S */
8788#define PDB_S_COUNT (2U)
8789
8790/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
8791/*! @{ */
8792#define PDB_DLY_DLY_MASK (0xFFFFU)
8793#define PDB_DLY_DLY_SHIFT (0U)
8794#define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
8795/*! @} */
8796
8797/* The count of PDB_DLY */
8798#define PDB_DLY_COUNT (2U)
8799
8800/* The count of PDB_DLY */
8801#define PDB_DLY_COUNT2 (2U)
8802
8803/*! @name INTC - DAC Interval Trigger n Control register */
8804/*! @{ */
8805#define PDB_INTC_TOE_MASK (0x1U)
8806#define PDB_INTC_TOE_SHIFT (0U)
8807/*! TOE - DAC Interval Trigger Enable
8808 * 0b0..DAC interval trigger disabled.
8809 * 0b1..DAC interval trigger enabled.
8810 */
8811#define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
8812#define PDB_INTC_EXT_MASK (0x2U)
8813#define PDB_INTC_EXT_SHIFT (1U)
8814/*! EXT - DAC External Trigger Input Enable
8815 * 0b0..DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1.
8816 * 0b1..DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger.
8817 */
8818#define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
8819/*! @} */
8820
8821/* The count of PDB_INTC */
8822#define PDB_INTC_COUNT (1U)
8823
8824/*! @name INT - DAC Interval n register */
8825/*! @{ */
8826#define PDB_INT_INT_MASK (0xFFFFU)
8827#define PDB_INT_INT_SHIFT (0U)
8828#define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
8829/*! @} */
8830
8831/* The count of PDB_INT */
8832#define PDB_INT_COUNT (1U)
8833
8834/*! @name POEN - Pulse-Out n Enable register */
8835/*! @{ */
8836#define PDB_POEN_POEN_MASK (0xFFU)
8837#define PDB_POEN_POEN_SHIFT (0U)
8838/*! POEN - PDB Pulse-Out Enable
8839 * 0b00000000..PDB Pulse-Out disabled
8840 * 0b00000001..PDB Pulse-Out enabled
8841 */
8842#define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
8843/*! @} */
8844
8845/*! @name PODLY - Pulse-Out n Delay register */
8846/*! @{ */
8847#define PDB_PODLY_DLY2_MASK (0xFFFFU)
8848#define PDB_PODLY_DLY2_SHIFT (0U)
8849#define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
8850#define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
8851#define PDB_PODLY_DLY1_SHIFT (16U)
8852#define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
8853/*! @} */
8854
8855/* The count of PDB_PODLY */
8856#define PDB_PODLY_COUNT (2U)
8857
8858
8859/*!
8860 * @}
8861 */ /* end of group PDB_Register_Masks */
8862
8863
8864/* PDB - Peripheral instance base addresses */
8865/** Peripheral PDB0 base address */
8866#define PDB0_BASE (0x40036000u)
8867/** Peripheral PDB0 base pointer */
8868#define PDB0 ((PDB_Type *)PDB0_BASE)
8869/** Array initializer of PDB peripheral base addresses */
8870#define PDB_BASE_ADDRS { PDB0_BASE }
8871/** Array initializer of PDB peripheral base pointers */
8872#define PDB_BASE_PTRS { PDB0 }
8873/** Interrupt vectors for the PDB peripheral type */
8874#define PDB_IRQS { PDB0_IRQn }
8875
8876/*!
8877 * @}
8878 */ /* end of group PDB_Peripheral_Access_Layer */
8879
8880
8881/* ----------------------------------------------------------------------------
8882 -- PIT Peripheral Access Layer
8883 ---------------------------------------------------------------------------- */
8884
8885/*!
8886 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
8887 * @{
8888 */
8889
8890/** PIT - Register Layout Typedef */
8891typedef struct {
8892 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
8893 uint8_t RESERVED_0[252];
8894 struct { /* offset: 0x100, array step: 0x10 */
8895 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
8896 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
8897 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
8898 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
8899 } CHANNEL[4];
8900} PIT_Type;
8901
8902/* ----------------------------------------------------------------------------
8903 -- PIT Register Masks
8904 ---------------------------------------------------------------------------- */
8905
8906/*!
8907 * @addtogroup PIT_Register_Masks PIT Register Masks
8908 * @{
8909 */
8910
8911/*! @name MCR - PIT Module Control Register */
8912/*! @{ */
8913#define PIT_MCR_FRZ_MASK (0x1U)
8914#define PIT_MCR_FRZ_SHIFT (0U)
8915/*! FRZ - Freeze
8916 * 0b0..Timers continue to run in Debug mode.
8917 * 0b1..Timers are stopped in Debug mode.
8918 */
8919#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
8920#define PIT_MCR_MDIS_MASK (0x2U)
8921#define PIT_MCR_MDIS_SHIFT (1U)
8922/*! MDIS - Module Disable - (PIT section)
8923 * 0b0..Clock for standard PIT timers is enabled.
8924 * 0b1..Clock for standard PIT timers is disabled.
8925 */
8926#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
8927/*! @} */
8928
8929/*! @name LDVAL - Timer Load Value Register */
8930/*! @{ */
8931#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
8932#define PIT_LDVAL_TSV_SHIFT (0U)
8933#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
8934/*! @} */
8935
8936/* The count of PIT_LDVAL */
8937#define PIT_LDVAL_COUNT (4U)
8938
8939/*! @name CVAL - Current Timer Value Register */
8940/*! @{ */
8941#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
8942#define PIT_CVAL_TVL_SHIFT (0U)
8943#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
8944/*! @} */
8945
8946/* The count of PIT_CVAL */
8947#define PIT_CVAL_COUNT (4U)
8948
8949/*! @name TCTRL - Timer Control Register */
8950/*! @{ */
8951#define PIT_TCTRL_TEN_MASK (0x1U)
8952#define PIT_TCTRL_TEN_SHIFT (0U)
8953/*! TEN - Timer Enable
8954 * 0b0..Timer n is disabled.
8955 * 0b1..Timer n is enabled.
8956 */
8957#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
8958#define PIT_TCTRL_TIE_MASK (0x2U)
8959#define PIT_TCTRL_TIE_SHIFT (1U)
8960/*! TIE - Timer Interrupt Enable
8961 * 0b0..Interrupt requests from Timer n are disabled.
8962 * 0b1..Interrupt will be requested whenever TIF is set.
8963 */
8964#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
8965#define PIT_TCTRL_CHN_MASK (0x4U)
8966#define PIT_TCTRL_CHN_SHIFT (2U)
8967/*! CHN - Chain Mode
8968 * 0b0..Timer is not chained.
8969 * 0b1..Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
8970 */
8971#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
8972/*! @} */
8973
8974/* The count of PIT_TCTRL */
8975#define PIT_TCTRL_COUNT (4U)
8976
8977/*! @name TFLG - Timer Flag Register */
8978/*! @{ */
8979#define PIT_TFLG_TIF_MASK (0x1U)
8980#define PIT_TFLG_TIF_SHIFT (0U)
8981/*! TIF - Timer Interrupt Flag
8982 * 0b0..Timeout has not yet occurred.
8983 * 0b1..Timeout has occurred.
8984 */
8985#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
8986/*! @} */
8987
8988/* The count of PIT_TFLG */
8989#define PIT_TFLG_COUNT (4U)
8990
8991
8992/*!
8993 * @}
8994 */ /* end of group PIT_Register_Masks */
8995
8996
8997/* PIT - Peripheral instance base addresses */
8998/** Peripheral PIT base address */
8999#define PIT_BASE (0x40037000u)
9000/** Peripheral PIT base pointer */
9001#define PIT ((PIT_Type *)PIT_BASE)
9002/** Array initializer of PIT peripheral base addresses */
9003#define PIT_BASE_ADDRS { PIT_BASE }
9004/** Array initializer of PIT peripheral base pointers */
9005#define PIT_BASE_PTRS { PIT }
9006/** Interrupt vectors for the PIT peripheral type */
9007#define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
9008
9009/*!
9010 * @}
9011 */ /* end of group PIT_Peripheral_Access_Layer */
9012
9013
9014/* ----------------------------------------------------------------------------
9015 -- PMC Peripheral Access Layer
9016 ---------------------------------------------------------------------------- */
9017
9018/*!
9019 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
9020 * @{
9021 */
9022
9023/** PMC - Register Layout Typedef */
9024typedef struct {
9025 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
9026 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
9027 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
9028} PMC_Type;
9029
9030/* ----------------------------------------------------------------------------
9031 -- PMC Register Masks
9032 ---------------------------------------------------------------------------- */
9033
9034/*!
9035 * @addtogroup PMC_Register_Masks PMC Register Masks
9036 * @{
9037 */
9038
9039/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
9040/*! @{ */
9041#define PMC_LVDSC1_LVDV_MASK (0x3U)
9042#define PMC_LVDSC1_LVDV_SHIFT (0U)
9043/*! LVDV - Low-Voltage Detect Voltage Select
9044 * 0b00..Low trip point selected (V LVD = V LVDL )
9045 * 0b01..High trip point selected (V LVD = V LVDH )
9046 * 0b10..Reserved
9047 * 0b11..Reserved
9048 */
9049#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
9050#define PMC_LVDSC1_LVDRE_MASK (0x10U)
9051#define PMC_LVDSC1_LVDRE_SHIFT (4U)
9052/*! LVDRE - Low-Voltage Detect Reset Enable
9053 * 0b0..LVDF does not generate hardware resets
9054 * 0b1..Force an MCU reset when LVDF = 1
9055 */
9056#define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
9057#define PMC_LVDSC1_LVDIE_MASK (0x20U)
9058#define PMC_LVDSC1_LVDIE_SHIFT (5U)
9059/*! LVDIE - Low-Voltage Detect Interrupt Enable
9060 * 0b0..Hardware interrupt disabled (use polling)
9061 * 0b1..Request a hardware interrupt when LVDF = 1
9062 */
9063#define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
9064#define PMC_LVDSC1_LVDACK_MASK (0x40U)
9065#define PMC_LVDSC1_LVDACK_SHIFT (6U)
9066#define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
9067#define PMC_LVDSC1_LVDF_MASK (0x80U)
9068#define PMC_LVDSC1_LVDF_SHIFT (7U)
9069/*! LVDF - Low-Voltage Detect Flag
9070 * 0b0..Low-voltage event not detected
9071 * 0b1..Low-voltage event detected
9072 */
9073#define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
9074/*! @} */
9075
9076/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
9077/*! @{ */
9078#define PMC_LVDSC2_LVWV_MASK (0x3U)
9079#define PMC_LVDSC2_LVWV_SHIFT (0U)
9080/*! LVWV - Low-Voltage Warning Voltage Select
9081 * 0b00..Low trip point selected (VLVW = VLVW1)
9082 * 0b01..Mid 1 trip point selected (VLVW = VLVW2)
9083 * 0b10..Mid 2 trip point selected (VLVW = VLVW3)
9084 * 0b11..High trip point selected (VLVW = VLVW4)
9085 */
9086#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
9087#define PMC_LVDSC2_LVWIE_MASK (0x20U)
9088#define PMC_LVDSC2_LVWIE_SHIFT (5U)
9089/*! LVWIE - Low-Voltage Warning Interrupt Enable
9090 * 0b0..Hardware interrupt disabled (use polling)
9091 * 0b1..Request a hardware interrupt when LVWF = 1
9092 */
9093#define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
9094#define PMC_LVDSC2_LVWACK_MASK (0x40U)
9095#define PMC_LVDSC2_LVWACK_SHIFT (6U)
9096#define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
9097#define PMC_LVDSC2_LVWF_MASK (0x80U)
9098#define PMC_LVDSC2_LVWF_SHIFT (7U)
9099/*! LVWF - Low-Voltage Warning Flag
9100 * 0b0..Low-voltage warning event not detected
9101 * 0b1..Low-voltage warning event detected
9102 */
9103#define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
9104/*! @} */
9105
9106/*! @name REGSC - Regulator Status And Control register */
9107/*! @{ */
9108#define PMC_REGSC_BGBE_MASK (0x1U)
9109#define PMC_REGSC_BGBE_SHIFT (0U)
9110/*! BGBE - Bandgap Buffer Enable
9111 * 0b0..Bandgap buffer not enabled
9112 * 0b1..Bandgap buffer enabled
9113 */
9114#define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
9115#define PMC_REGSC_REGONS_MASK (0x4U)
9116#define PMC_REGSC_REGONS_SHIFT (2U)
9117/*! REGONS - Regulator In Run Regulation Status
9118 * 0b0..Regulator is in stop regulation or in transition to/from it
9119 * 0b1..Regulator is in run regulation
9120 */
9121#define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
9122#define PMC_REGSC_ACKISO_MASK (0x8U)
9123#define PMC_REGSC_ACKISO_SHIFT (3U)
9124/*! ACKISO - Acknowledge Isolation
9125 * 0b0..Peripherals and I/O pads are in normal run state.
9126 * 0b1..Certain peripherals and I/O pads are in an isolated and latched state.
9127 */
9128#define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
9129#define PMC_REGSC_BGEN_MASK (0x10U)
9130#define PMC_REGSC_BGEN_SHIFT (4U)
9131/*! BGEN - Bandgap Enable In VLPx Operation
9132 * 0b0..Bandgap voltage reference is disabled in VLPx , LLS , and VLLSx modes.
9133 * 0b1..Bandgap voltage reference is enabled in VLPx , LLS , and VLLSx modes.
9134 */
9135#define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
9136/*! @} */
9137
9138
9139/*!
9140 * @}
9141 */ /* end of group PMC_Register_Masks */
9142
9143
9144/* PMC - Peripheral instance base addresses */
9145/** Peripheral PMC base address */
9146#define PMC_BASE (0x4007D000u)
9147/** Peripheral PMC base pointer */
9148#define PMC ((PMC_Type *)PMC_BASE)
9149/** Array initializer of PMC peripheral base addresses */
9150#define PMC_BASE_ADDRS { PMC_BASE }
9151/** Array initializer of PMC peripheral base pointers */
9152#define PMC_BASE_PTRS { PMC }
9153/** Interrupt vectors for the PMC peripheral type */
9154#define PMC_IRQS { LVD_LVW_IRQn }
9155
9156/*!
9157 * @}
9158 */ /* end of group PMC_Peripheral_Access_Layer */
9159
9160
9161/* ----------------------------------------------------------------------------
9162 -- PORT Peripheral Access Layer
9163 ---------------------------------------------------------------------------- */
9164
9165/*!
9166 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
9167 * @{
9168 */
9169
9170/** PORT - Register Layout Typedef */
9171typedef struct {
9172 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
9173 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
9174 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
9175 uint8_t RESERVED_0[24];
9176 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
9177 uint8_t RESERVED_1[28];
9178 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
9179 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
9180 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
9181} PORT_Type;
9182
9183/* ----------------------------------------------------------------------------
9184 -- PORT Register Masks
9185 ---------------------------------------------------------------------------- */
9186
9187/*!
9188 * @addtogroup PORT_Register_Masks PORT Register Masks
9189 * @{
9190 */
9191
9192/*! @name PCR - Pin Control Register n */
9193/*! @{ */
9194#define PORT_PCR_PS_MASK (0x1U)
9195#define PORT_PCR_PS_SHIFT (0U)
9196/*! PS - Pull Select
9197 * 0b0..Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set.
9198 * 0b1..Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set.
9199 */
9200#define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
9201#define PORT_PCR_PE_MASK (0x2U)
9202#define PORT_PCR_PE_SHIFT (1U)
9203/*! PE - Pull Enable
9204 * 0b0..Internal pullup or pulldown resistor is not enabled on the corresponding pin.
9205 * 0b1..Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
9206 */
9207#define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
9208#define PORT_PCR_SRE_MASK (0x4U)
9209#define PORT_PCR_SRE_SHIFT (2U)
9210/*! SRE - Slew Rate Enable
9211 * 0b0..Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
9212 * 0b1..Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
9213 */
9214#define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
9215#define PORT_PCR_PFE_MASK (0x10U)
9216#define PORT_PCR_PFE_SHIFT (4U)
9217/*! PFE - Passive Filter Enable
9218 * 0b0..Passive input filter is disabled on the corresponding pin.
9219 * 0b1..Passive input filter is enabled on the corresponding pin, if the pin is configured as a digital input. Refer to the device data sheet for filter characteristics.
9220 */
9221#define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
9222#define PORT_PCR_ODE_MASK (0x20U)
9223#define PORT_PCR_ODE_SHIFT (5U)
9224/*! ODE - Open Drain Enable
9225 * 0b0..Open drain output is disabled on the corresponding pin.
9226 * 0b1..Open drain output is enabled on the corresponding pin, if the pin is configured as a digital output.
9227 */
9228#define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
9229#define PORT_PCR_DSE_MASK (0x40U)
9230#define PORT_PCR_DSE_SHIFT (6U)
9231/*! DSE - Drive Strength Enable
9232 * 0b0..Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
9233 * 0b1..High drive strength is configured on the corresponding pin, if pin is configured as a digital output.
9234 */
9235#define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
9236#define PORT_PCR_MUX_MASK (0x700U)
9237#define PORT_PCR_MUX_SHIFT (8U)
9238/*! MUX - Pin Mux Control
9239 * 0b000..Pin disabled (analog).
9240 * 0b001..Alternative 1 (GPIO).
9241 * 0b010..Alternative 2 (chip-specific).
9242 * 0b011..Alternative 3 (chip-specific).
9243 * 0b100..Alternative 4 (chip-specific).
9244 * 0b101..Alternative 5 (chip-specific).
9245 * 0b110..Alternative 6 (chip-specific).
9246 * 0b111..Alternative 7 (chip-specific).
9247 */
9248#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
9249#define PORT_PCR_LK_MASK (0x8000U)
9250#define PORT_PCR_LK_SHIFT (15U)
9251/*! LK - Lock Register
9252 * 0b0..Pin Control Register fields [15:0] are not locked.
9253 * 0b1..Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
9254 */
9255#define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
9256#define PORT_PCR_IRQC_MASK (0xF0000U)
9257#define PORT_PCR_IRQC_SHIFT (16U)
9258/*! IRQC - Interrupt Configuration
9259 * 0b0000..Interrupt/DMA request disabled.
9260 * 0b0001..DMA request on rising edge.
9261 * 0b0010..DMA request on falling edge.
9262 * 0b0011..DMA request on either edge.
9263 * 0b1000..Interrupt when logic 0.
9264 * 0b1001..Interrupt on rising-edge.
9265 * 0b1010..Interrupt on falling-edge.
9266 * 0b1011..Interrupt on either edge.
9267 * 0b1100..Interrupt when logic 1.
9268 */
9269#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
9270#define PORT_PCR_ISF_MASK (0x1000000U)
9271#define PORT_PCR_ISF_SHIFT (24U)
9272/*! ISF - Interrupt Status Flag
9273 * 0b0..Configured interrupt is not detected.
9274 * 0b1..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
9275 */
9276#define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
9277/*! @} */
9278
9279/* The count of PORT_PCR */
9280#define PORT_PCR_COUNT (32U)
9281
9282/*! @name GPCLR - Global Pin Control Low Register */
9283/*! @{ */
9284#define PORT_GPCLR_GPWD_MASK (0xFFFFU)
9285#define PORT_GPCLR_GPWD_SHIFT (0U)
9286#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
9287#define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
9288#define PORT_GPCLR_GPWE_SHIFT (16U)
9289/*! GPWE - Global Pin Write Enable
9290 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
9291 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
9292 */
9293#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
9294/*! @} */
9295
9296/*! @name GPCHR - Global Pin Control High Register */
9297/*! @{ */
9298#define PORT_GPCHR_GPWD_MASK (0xFFFFU)
9299#define PORT_GPCHR_GPWD_SHIFT (0U)
9300#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
9301#define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
9302#define PORT_GPCHR_GPWE_SHIFT (16U)
9303/*! GPWE - Global Pin Write Enable
9304 * 0b0000000000000000..Corresponding Pin Control Register is not updated with the value in GPWD.
9305 * 0b0000000000000001..Corresponding Pin Control Register is updated with the value in GPWD.
9306 */
9307#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
9308/*! @} */
9309
9310/*! @name ISFR - Interrupt Status Flag Register */
9311/*! @{ */
9312#define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
9313#define PORT_ISFR_ISF_SHIFT (0U)
9314/*! ISF - Interrupt Status Flag
9315 * 0b00000000000000000000000000000000..Configured interrupt is not detected.
9316 * 0b00000000000000000000000000000001..Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
9317 */
9318#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
9319/*! @} */
9320
9321/*! @name DFER - Digital Filter Enable Register */
9322/*! @{ */
9323#define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
9324#define PORT_DFER_DFE_SHIFT (0U)
9325/*! DFE - Digital Filter Enable
9326 * 0b00000000000000000000000000000000..Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
9327 * 0b00000000000000000000000000000001..Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
9328 */
9329#define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
9330/*! @} */
9331
9332/*! @name DFCR - Digital Filter Clock Register */
9333/*! @{ */
9334#define PORT_DFCR_CS_MASK (0x1U)
9335#define PORT_DFCR_CS_SHIFT (0U)
9336/*! CS - Clock Source
9337 * 0b0..Digital filters are clocked by the bus clock.
9338 * 0b1..Digital filters are clocked by the 1 kHz LPO clock.
9339 */
9340#define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
9341/*! @} */
9342
9343/*! @name DFWR - Digital Filter Width Register */
9344/*! @{ */
9345#define PORT_DFWR_FILT_MASK (0x1FU)
9346#define PORT_DFWR_FILT_SHIFT (0U)
9347#define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
9348/*! @} */
9349
9350
9351/*!
9352 * @}
9353 */ /* end of group PORT_Register_Masks */
9354
9355
9356/* PORT - Peripheral instance base addresses */
9357/** Peripheral PORTA base address */
9358#define PORTA_BASE (0x40049000u)
9359/** Peripheral PORTA base pointer */
9360#define PORTA ((PORT_Type *)PORTA_BASE)
9361/** Peripheral PORTB base address */
9362#define PORTB_BASE (0x4004A000u)
9363/** Peripheral PORTB base pointer */
9364#define PORTB ((PORT_Type *)PORTB_BASE)
9365/** Peripheral PORTC base address */
9366#define PORTC_BASE (0x4004B000u)
9367/** Peripheral PORTC base pointer */
9368#define PORTC ((PORT_Type *)PORTC_BASE)
9369/** Peripheral PORTD base address */
9370#define PORTD_BASE (0x4004C000u)
9371/** Peripheral PORTD base pointer */
9372#define PORTD ((PORT_Type *)PORTD_BASE)
9373/** Peripheral PORTE base address */
9374#define PORTE_BASE (0x4004D000u)
9375/** Peripheral PORTE base pointer */
9376#define PORTE ((PORT_Type *)PORTE_BASE)
9377/** Array initializer of PORT peripheral base addresses */
9378#define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
9379/** Array initializer of PORT peripheral base pointers */
9380#define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
9381/** Interrupt vectors for the PORT peripheral type */
9382#define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
9383
9384/*!
9385 * @}
9386 */ /* end of group PORT_Peripheral_Access_Layer */
9387
9388
9389/* ----------------------------------------------------------------------------
9390 -- RCM Peripheral Access Layer
9391 ---------------------------------------------------------------------------- */
9392
9393/*!
9394 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
9395 * @{
9396 */
9397
9398/** RCM - Register Layout Typedef */
9399typedef struct {
9400 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
9401 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
9402 uint8_t RESERVED_0[2];
9403 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
9404 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
9405 uint8_t RESERVED_1[1];
9406 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
9407 __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */
9408 __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */
9409} RCM_Type;
9410
9411/* ----------------------------------------------------------------------------
9412 -- RCM Register Masks
9413 ---------------------------------------------------------------------------- */
9414
9415/*!
9416 * @addtogroup RCM_Register_Masks RCM Register Masks
9417 * @{
9418 */
9419
9420/*! @name SRS0 - System Reset Status Register 0 */
9421/*! @{ */
9422#define RCM_SRS0_WAKEUP_MASK (0x1U)
9423#define RCM_SRS0_WAKEUP_SHIFT (0U)
9424/*! WAKEUP - Low Leakage Wakeup Reset
9425 * 0b0..Reset not caused by LLWU module wakeup source
9426 * 0b1..Reset caused by LLWU module wakeup source
9427 */
9428#define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
9429#define RCM_SRS0_LVD_MASK (0x2U)
9430#define RCM_SRS0_LVD_SHIFT (1U)
9431/*! LVD - Low-Voltage Detect Reset
9432 * 0b0..Reset not caused by LVD trip or POR
9433 * 0b1..Reset caused by LVD trip or POR
9434 */
9435#define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
9436#define RCM_SRS0_LOC_MASK (0x4U)
9437#define RCM_SRS0_LOC_SHIFT (2U)
9438/*! LOC - Loss-of-Clock Reset
9439 * 0b0..Reset not caused by a loss of external clock.
9440 * 0b1..Reset caused by a loss of external clock.
9441 */
9442#define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
9443#define RCM_SRS0_LOL_MASK (0x8U)
9444#define RCM_SRS0_LOL_SHIFT (3U)
9445/*! LOL - Loss-of-Lock Reset
9446 * 0b0..Reset not caused by a loss of lock in the PLL
9447 * 0b1..Reset caused by a loss of lock in the PLL
9448 */
9449#define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
9450#define RCM_SRS0_WDOG_MASK (0x20U)
9451#define RCM_SRS0_WDOG_SHIFT (5U)
9452/*! WDOG - Watchdog
9453 * 0b0..Reset not caused by watchdog timeout
9454 * 0b1..Reset caused by watchdog timeout
9455 */
9456#define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
9457#define RCM_SRS0_PIN_MASK (0x40U)
9458#define RCM_SRS0_PIN_SHIFT (6U)
9459/*! PIN - External Reset Pin
9460 * 0b0..Reset not caused by external reset pin
9461 * 0b1..Reset caused by external reset pin
9462 */
9463#define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
9464#define RCM_SRS0_POR_MASK (0x80U)
9465#define RCM_SRS0_POR_SHIFT (7U)
9466/*! POR - Power-On Reset
9467 * 0b0..Reset not caused by POR
9468 * 0b1..Reset caused by POR
9469 */
9470#define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
9471/*! @} */
9472
9473/*! @name SRS1 - System Reset Status Register 1 */
9474/*! @{ */
9475#define RCM_SRS1_JTAG_MASK (0x1U)
9476#define RCM_SRS1_JTAG_SHIFT (0U)
9477/*! JTAG - JTAG Generated Reset
9478 * 0b0..Reset not caused by JTAG
9479 * 0b1..Reset caused by JTAG
9480 */
9481#define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
9482#define RCM_SRS1_LOCKUP_MASK (0x2U)
9483#define RCM_SRS1_LOCKUP_SHIFT (1U)
9484/*! LOCKUP - Core Lockup
9485 * 0b0..Reset not caused by core LOCKUP event
9486 * 0b1..Reset caused by core LOCKUP event
9487 */
9488#define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
9489#define RCM_SRS1_SW_MASK (0x4U)
9490#define RCM_SRS1_SW_SHIFT (2U)
9491/*! SW - Software
9492 * 0b0..Reset not caused by software setting of SYSRESETREQ bit
9493 * 0b1..Reset caused by software setting of SYSRESETREQ bit
9494 */
9495#define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
9496#define RCM_SRS1_MDM_AP_MASK (0x8U)
9497#define RCM_SRS1_MDM_AP_SHIFT (3U)
9498/*! MDM_AP - MDM-AP System Reset Request
9499 * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit
9500 * 0b1..Reset caused by host debugger system setting of the System Reset Request bit
9501 */
9502#define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
9503#define RCM_SRS1_EZPT_MASK (0x10U)
9504#define RCM_SRS1_EZPT_SHIFT (4U)
9505/*! EZPT - EzPort Reset
9506 * 0b0..Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode
9507 * 0b1..Reset caused by EzPort receiving the RESET command while the device is in EzPort mode
9508 */
9509#define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
9510#define RCM_SRS1_SACKERR_MASK (0x20U)
9511#define RCM_SRS1_SACKERR_SHIFT (5U)
9512/*! SACKERR - Stop Mode Acknowledge Error Reset
9513 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
9514 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
9515 */
9516#define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
9517/*! @} */
9518
9519/*! @name RPFC - Reset Pin Filter Control register */
9520/*! @{ */
9521#define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
9522#define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
9523/*! RSTFLTSRW - Reset Pin Filter Select in Run and Wait Modes
9524 * 0b00..All filtering disabled
9525 * 0b01..Bus clock filter enabled for normal operation
9526 * 0b10..LPO clock filter enabled for normal operation
9527 * 0b11..Reserved
9528 */
9529#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
9530#define RCM_RPFC_RSTFLTSS_MASK (0x4U)
9531#define RCM_RPFC_RSTFLTSS_SHIFT (2U)
9532/*! RSTFLTSS - Reset Pin Filter Select in Stop Mode
9533 * 0b0..All filtering disabled
9534 * 0b1..LPO clock filter enabled
9535 */
9536#define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
9537/*! @} */
9538
9539/*! @name RPFW - Reset Pin Filter Width register */
9540/*! @{ */
9541#define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
9542#define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
9543/*! RSTFLTSEL - Reset Pin Filter Bus Clock Select
9544 * 0b00000..Bus clock filter count is 1
9545 * 0b00001..Bus clock filter count is 2
9546 * 0b00010..Bus clock filter count is 3
9547 * 0b00011..Bus clock filter count is 4
9548 * 0b00100..Bus clock filter count is 5
9549 * 0b00101..Bus clock filter count is 6
9550 * 0b00110..Bus clock filter count is 7
9551 * 0b00111..Bus clock filter count is 8
9552 * 0b01000..Bus clock filter count is 9
9553 * 0b01001..Bus clock filter count is 10
9554 * 0b01010..Bus clock filter count is 11
9555 * 0b01011..Bus clock filter count is 12
9556 * 0b01100..Bus clock filter count is 13
9557 * 0b01101..Bus clock filter count is 14
9558 * 0b01110..Bus clock filter count is 15
9559 * 0b01111..Bus clock filter count is 16
9560 * 0b10000..Bus clock filter count is 17
9561 * 0b10001..Bus clock filter count is 18
9562 * 0b10010..Bus clock filter count is 19
9563 * 0b10011..Bus clock filter count is 20
9564 * 0b10100..Bus clock filter count is 21
9565 * 0b10101..Bus clock filter count is 22
9566 * 0b10110..Bus clock filter count is 23
9567 * 0b10111..Bus clock filter count is 24
9568 * 0b11000..Bus clock filter count is 25
9569 * 0b11001..Bus clock filter count is 26
9570 * 0b11010..Bus clock filter count is 27
9571 * 0b11011..Bus clock filter count is 28
9572 * 0b11100..Bus clock filter count is 29
9573 * 0b11101..Bus clock filter count is 30
9574 * 0b11110..Bus clock filter count is 31
9575 * 0b11111..Bus clock filter count is 32
9576 */
9577#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
9578/*! @} */
9579
9580/*! @name MR - Mode Register */
9581/*! @{ */
9582#define RCM_MR_EZP_MS_MASK (0x2U)
9583#define RCM_MR_EZP_MS_SHIFT (1U)
9584/*! EZP_MS - EZP_MS_B pin state
9585 * 0b0..Pin deasserted (logic 1)
9586 * 0b1..Pin asserted (logic 0)
9587 */
9588#define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
9589/*! @} */
9590
9591/*! @name SSRS0 - Sticky System Reset Status Register 0 */
9592/*! @{ */
9593#define RCM_SSRS0_SWAKEUP_MASK (0x1U)
9594#define RCM_SSRS0_SWAKEUP_SHIFT (0U)
9595/*! SWAKEUP - Sticky Low Leakage Wakeup Reset
9596 * 0b0..Reset not caused by LLWU module wakeup source
9597 * 0b1..Reset caused by LLWU module wakeup source
9598 */
9599#define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
9600#define RCM_SSRS0_SLVD_MASK (0x2U)
9601#define RCM_SSRS0_SLVD_SHIFT (1U)
9602/*! SLVD - Sticky Low-Voltage Detect Reset
9603 * 0b0..Reset not caused by LVD trip or POR
9604 * 0b1..Reset caused by LVD trip or POR
9605 */
9606#define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
9607#define RCM_SSRS0_SLOC_MASK (0x4U)
9608#define RCM_SSRS0_SLOC_SHIFT (2U)
9609/*! SLOC - Sticky Loss-of-Clock Reset
9610 * 0b0..Reset not caused by a loss of external clock.
9611 * 0b1..Reset caused by a loss of external clock.
9612 */
9613#define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
9614#define RCM_SSRS0_SLOL_MASK (0x8U)
9615#define RCM_SSRS0_SLOL_SHIFT (3U)
9616/*! SLOL - Sticky Loss-of-Lock Reset
9617 * 0b0..Reset not caused by a loss of lock in the PLL
9618 * 0b1..Reset caused by a loss of lock in the PLL
9619 */
9620#define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
9621#define RCM_SSRS0_SWDOG_MASK (0x20U)
9622#define RCM_SSRS0_SWDOG_SHIFT (5U)
9623/*! SWDOG - Sticky Watchdog
9624 * 0b0..Reset not caused by watchdog timeout
9625 * 0b1..Reset caused by watchdog timeout
9626 */
9627#define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
9628#define RCM_SSRS0_SPIN_MASK (0x40U)
9629#define RCM_SSRS0_SPIN_SHIFT (6U)
9630/*! SPIN - Sticky External Reset Pin
9631 * 0b0..Reset not caused by external reset pin
9632 * 0b1..Reset caused by external reset pin
9633 */
9634#define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
9635#define RCM_SSRS0_SPOR_MASK (0x80U)
9636#define RCM_SSRS0_SPOR_SHIFT (7U)
9637/*! SPOR - Sticky Power-On Reset
9638 * 0b0..Reset not caused by POR
9639 * 0b1..Reset caused by POR
9640 */
9641#define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
9642/*! @} */
9643
9644/*! @name SSRS1 - Sticky System Reset Status Register 1 */
9645/*! @{ */
9646#define RCM_SSRS1_SJTAG_MASK (0x1U)
9647#define RCM_SSRS1_SJTAG_SHIFT (0U)
9648/*! SJTAG - Sticky JTAG Generated Reset
9649 * 0b0..Reset not caused by JTAG
9650 * 0b1..Reset caused by JTAG
9651 */
9652#define RCM_SSRS1_SJTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
9653#define RCM_SSRS1_SLOCKUP_MASK (0x2U)
9654#define RCM_SSRS1_SLOCKUP_SHIFT (1U)
9655/*! SLOCKUP - Sticky Core Lockup
9656 * 0b0..Reset not caused by core LOCKUP event
9657 * 0b1..Reset caused by core LOCKUP event
9658 */
9659#define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
9660#define RCM_SSRS1_SSW_MASK (0x4U)
9661#define RCM_SSRS1_SSW_SHIFT (2U)
9662/*! SSW - Sticky Software
9663 * 0b0..Reset not caused by software setting of SYSRESETREQ bit
9664 * 0b1..Reset caused by software setting of SYSRESETREQ bit
9665 */
9666#define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
9667#define RCM_SSRS1_SMDM_AP_MASK (0x8U)
9668#define RCM_SSRS1_SMDM_AP_SHIFT (3U)
9669/*! SMDM_AP - Sticky MDM-AP System Reset Request
9670 * 0b0..Reset not caused by host debugger system setting of the System Reset Request bit
9671 * 0b1..Reset caused by host debugger system setting of the System Reset Request bit
9672 */
9673#define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
9674#define RCM_SSRS1_SEZPT_MASK (0x10U)
9675#define RCM_SSRS1_SEZPT_SHIFT (4U)
9676/*! SEZPT - Sticky EzPort Reset
9677 * 0b0..Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode
9678 * 0b1..Reset caused by EzPort receiving the RESET command while the device is in EzPort mode
9679 */
9680#define RCM_SSRS1_SEZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK)
9681#define RCM_SSRS1_SSACKERR_MASK (0x20U)
9682#define RCM_SSRS1_SSACKERR_SHIFT (5U)
9683/*! SSACKERR - Sticky Stop Mode Acknowledge Error Reset
9684 * 0b0..Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
9685 * 0b1..Reset caused by peripheral failure to acknowledge attempt to enter stop mode
9686 */
9687#define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
9688/*! @} */
9689
9690
9691/*!
9692 * @}
9693 */ /* end of group RCM_Register_Masks */
9694
9695
9696/* RCM - Peripheral instance base addresses */
9697/** Peripheral RCM base address */
9698#define RCM_BASE (0x4007F000u)
9699/** Peripheral RCM base pointer */
9700#define RCM ((RCM_Type *)RCM_BASE)
9701/** Array initializer of RCM peripheral base addresses */
9702#define RCM_BASE_ADDRS { RCM_BASE }
9703/** Array initializer of RCM peripheral base pointers */
9704#define RCM_BASE_PTRS { RCM }
9705
9706/*!
9707 * @}
9708 */ /* end of group RCM_Peripheral_Access_Layer */
9709
9710
9711/* ----------------------------------------------------------------------------
9712 -- RFSYS Peripheral Access Layer
9713 ---------------------------------------------------------------------------- */
9714
9715/*!
9716 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
9717 * @{
9718 */
9719
9720/** RFSYS - Register Layout Typedef */
9721typedef struct {
9722 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
9723} RFSYS_Type;
9724
9725/* ----------------------------------------------------------------------------
9726 -- RFSYS Register Masks
9727 ---------------------------------------------------------------------------- */
9728
9729/*!
9730 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
9731 * @{
9732 */
9733
9734/*! @name REG - Register file register */
9735/*! @{ */
9736#define RFSYS_REG_LL_MASK (0xFFU)
9737#define RFSYS_REG_LL_SHIFT (0U)
9738#define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
9739#define RFSYS_REG_LH_MASK (0xFF00U)
9740#define RFSYS_REG_LH_SHIFT (8U)
9741#define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
9742#define RFSYS_REG_HL_MASK (0xFF0000U)
9743#define RFSYS_REG_HL_SHIFT (16U)
9744#define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
9745#define RFSYS_REG_HH_MASK (0xFF000000U)
9746#define RFSYS_REG_HH_SHIFT (24U)
9747#define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
9748/*! @} */
9749
9750/* The count of RFSYS_REG */
9751#define RFSYS_REG_COUNT (8U)
9752
9753
9754/*!
9755 * @}
9756 */ /* end of group RFSYS_Register_Masks */
9757
9758
9759/* RFSYS - Peripheral instance base addresses */
9760/** Peripheral RFSYS base address */
9761#define RFSYS_BASE (0x40041000u)
9762/** Peripheral RFSYS base pointer */
9763#define RFSYS ((RFSYS_Type *)RFSYS_BASE)
9764/** Array initializer of RFSYS peripheral base addresses */
9765#define RFSYS_BASE_ADDRS { RFSYS_BASE }
9766/** Array initializer of RFSYS peripheral base pointers */
9767#define RFSYS_BASE_PTRS { RFSYS }
9768
9769/*!
9770 * @}
9771 */ /* end of group RFSYS_Peripheral_Access_Layer */
9772
9773
9774/* ----------------------------------------------------------------------------
9775 -- RNG Peripheral Access Layer
9776 ---------------------------------------------------------------------------- */
9777
9778/*!
9779 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
9780 * @{
9781 */
9782
9783/** RNG - Register Layout Typedef */
9784typedef struct {
9785 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
9786 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
9787 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
9788 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
9789} RNG_Type;
9790
9791/* ----------------------------------------------------------------------------
9792 -- RNG Register Masks
9793 ---------------------------------------------------------------------------- */
9794
9795/*!
9796 * @addtogroup RNG_Register_Masks RNG Register Masks
9797 * @{
9798 */
9799
9800/*! @name CR - RNGA Control Register */
9801/*! @{ */
9802#define RNG_CR_GO_MASK (0x1U)
9803#define RNG_CR_GO_SHIFT (0U)
9804/*! GO - Go
9805 * 0b0..Disabled
9806 * 0b1..Enabled
9807 */
9808#define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
9809#define RNG_CR_HA_MASK (0x2U)
9810#define RNG_CR_HA_SHIFT (1U)
9811/*! HA - High Assurance
9812 * 0b0..Disabled
9813 * 0b1..Enabled
9814 */
9815#define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
9816#define RNG_CR_INTM_MASK (0x4U)
9817#define RNG_CR_INTM_SHIFT (2U)
9818/*! INTM - Interrupt Mask
9819 * 0b0..Not masked
9820 * 0b1..Masked
9821 */
9822#define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
9823#define RNG_CR_CLRI_MASK (0x8U)
9824#define RNG_CR_CLRI_SHIFT (3U)
9825/*! CLRI - Clear Interrupt
9826 * 0b0..Do not clear the interrupt.
9827 * 0b1..Clear the interrupt. When you write 1 to this field, RNGA then resets the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
9828 */
9829#define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
9830#define RNG_CR_SLP_MASK (0x10U)
9831#define RNG_CR_SLP_SHIFT (4U)
9832/*! SLP - Sleep
9833 * 0b0..Normal mode
9834 * 0b1..Sleep (low-power) mode
9835 */
9836#define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
9837/*! @} */
9838
9839/*! @name SR - RNGA Status Register */
9840/*! @{ */
9841#define RNG_SR_SECV_MASK (0x1U)
9842#define RNG_SR_SECV_SHIFT (0U)
9843/*! SECV - Security Violation
9844 * 0b0..No security violation
9845 * 0b1..Security violation
9846 */
9847#define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
9848#define RNG_SR_LRS_MASK (0x2U)
9849#define RNG_SR_LRS_SHIFT (1U)
9850/*! LRS - Last Read Status
9851 * 0b0..No underflow
9852 * 0b1..Underflow
9853 */
9854#define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
9855#define RNG_SR_ORU_MASK (0x4U)
9856#define RNG_SR_ORU_SHIFT (2U)
9857/*! ORU - Output Register Underflow
9858 * 0b0..No underflow
9859 * 0b1..Underflow
9860 */
9861#define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
9862#define RNG_SR_ERRI_MASK (0x8U)
9863#define RNG_SR_ERRI_SHIFT (3U)
9864/*! ERRI - Error Interrupt
9865 * 0b0..No underflow
9866 * 0b1..Underflow
9867 */
9868#define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
9869#define RNG_SR_SLP_MASK (0x10U)
9870#define RNG_SR_SLP_SHIFT (4U)
9871/*! SLP - Sleep
9872 * 0b0..Normal mode
9873 * 0b1..Sleep (low-power) mode
9874 */
9875#define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
9876#define RNG_SR_OREG_LVL_MASK (0xFF00U)
9877#define RNG_SR_OREG_LVL_SHIFT (8U)
9878/*! OREG_LVL - Output Register Level
9879 * 0b00000000..No words (empty)
9880 * 0b00000001..One word (valid)
9881 */
9882#define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
9883#define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
9884#define RNG_SR_OREG_SIZE_SHIFT (16U)
9885/*! OREG_SIZE - Output Register Size
9886 * 0b00000001..One word (this value is fixed)
9887 */
9888#define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
9889/*! @} */
9890
9891/*! @name ER - RNGA Entropy Register */
9892/*! @{ */
9893#define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU)
9894#define RNG_ER_EXT_ENT_SHIFT (0U)
9895#define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
9896/*! @} */
9897
9898/*! @name OR - RNGA Output Register */
9899/*! @{ */
9900#define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU)
9901#define RNG_OR_RANDOUT_SHIFT (0U)
9902/*! RANDOUT - Random Output
9903 * 0b00000000000000000000000000000000..Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt request to the interrupt controller).
9904 */
9905#define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
9906/*! @} */
9907
9908
9909/*!
9910 * @}
9911 */ /* end of group RNG_Register_Masks */
9912
9913
9914/* RNG - Peripheral instance base addresses */
9915/** Peripheral RNG base address */
9916#define RNG_BASE (0x40029000u)
9917/** Peripheral RNG base pointer */
9918#define RNG ((RNG_Type *)RNG_BASE)
9919/** Array initializer of RNG peripheral base addresses */
9920#define RNG_BASE_ADDRS { RNG_BASE }
9921/** Array initializer of RNG peripheral base pointers */
9922#define RNG_BASE_PTRS { RNG }
9923/** Interrupt vectors for the RNG peripheral type */
9924#define RNG_IRQS { RNG_IRQn }
9925
9926/*!
9927 * @}
9928 */ /* end of group RNG_Peripheral_Access_Layer */
9929
9930
9931/* ----------------------------------------------------------------------------
9932 -- SIM Peripheral Access Layer
9933 ---------------------------------------------------------------------------- */
9934
9935/*!
9936 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
9937 * @{
9938 */
9939
9940/** SIM - Register Layout Typedef */
9941typedef struct {
9942 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
9943 uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
9944 uint8_t RESERVED_0[4092];
9945 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
9946 uint8_t RESERVED_1[4];
9947 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
9948 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
9949 uint8_t RESERVED_2[4];
9950 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
9951 __IO uint32_t SOPT8; /**< System Options Register 8, offset: 0x101C */
9952 uint8_t RESERVED_3[4];
9953 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
9954 uint8_t RESERVED_4[12];
9955 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
9956 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
9957 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
9958 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
9959 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
9960 uint8_t RESERVED_5[4];
9961 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
9962 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
9963 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
9964 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
9965 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
9966 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
9967} SIM_Type;
9968
9969/* ----------------------------------------------------------------------------
9970 -- SIM Register Masks
9971 ---------------------------------------------------------------------------- */
9972
9973/*!
9974 * @addtogroup SIM_Register_Masks SIM Register Masks
9975 * @{
9976 */
9977
9978/*! @name SOPT1 - System Options Register 1 */
9979/*! @{ */
9980#define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
9981#define SIM_SOPT1_RAMSIZE_SHIFT (12U)
9982/*! RAMSIZE - RAM size
9983 * 0b0001..8 KB
9984 * 0b0011..16 KB
9985 * 0b0100..24 KB
9986 * 0b0101..32 KB
9987 * 0b0110..48 KB
9988 * 0b0111..64 KB
9989 * 0b1000..96 KB
9990 * 0b1001..128 KB
9991 * 0b1011..256 KB
9992 */
9993#define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
9994#define SIM_SOPT1_OSC32KOUT_MASK (0x30000U)
9995#define SIM_SOPT1_OSC32KOUT_SHIFT (16U)
9996/*! OSC32KOUT - 32K Oscillator Clock Output
9997 * 0b00..ERCLK32K is not output.
9998 * 0b01..ERCLK32K is output on PTE0.
9999 * 0b10..ERCLK32K is output on PTE26.
10000 * 0b11..Reserved.
10001 */
10002#define SIM_SOPT1_OSC32KOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KOUT_SHIFT)) & SIM_SOPT1_OSC32KOUT_MASK)
10003#define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
10004#define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
10005/*! OSC32KSEL - 32K oscillator clock select
10006 * 0b00..System oscillator (OSC32KCLK)
10007 * 0b01..Reserved
10008 * 0b10..Reserved
10009 * 0b11..LPO 1 kHz
10010 */
10011#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
10012/*! @} */
10013
10014/*! @name SOPT2 - System Options Register 2 */
10015/*! @{ */
10016#define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
10017#define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
10018/*! CLKOUTSEL - CLKOUT select
10019 * 0b000..Reserved
10020 * 0b001..Reserved
10021 * 0b010..Flash clock
10022 * 0b011..LPO clock (1 kHz)
10023 * 0b100..MCGIRCLK
10024 * 0b101..Reserved
10025 * 0b110..OSCERCLK0
10026 * 0b111..IRC 48 MHz clock
10027 */
10028#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
10029#define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
10030#define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
10031/*! TRACECLKSEL - Debug trace clock select
10032 * 0b0..MCGOUTCLK
10033 * 0b1..Core/system clock
10034 */
10035#define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
10036#define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
10037#define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
10038/*! PLLFLLSEL - PLL/FLL clock select
10039 * 0b00..MCGFLLCLK clock
10040 * 0b01..MCGPLLCLK clock
10041 * 0b10..Reserved
10042 * 0b11..IRC48 MHz clock
10043 */
10044#define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
10045#define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U)
10046#define SIM_SOPT2_LPUARTSRC_SHIFT (26U)
10047/*! LPUARTSRC - LPUART clock source select
10048 * 0b00..Clock disabled
10049 * 0b01..MCGFLLCLK , or MCGPLLCLK , or IRC48M clock as selected by SOPT2[PLLFLLSEL].
10050 * 0b10..OSCERCLK clock
10051 * 0b11..MCGIRCLK clock
10052 */
10053#define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
10054/*! @} */
10055
10056/*! @name SOPT4 - System Options Register 4 */
10057/*! @{ */
10058#define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
10059#define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
10060/*! FTM0FLT0 - FTM0 Fault 0 Select
10061 * 0b0..FTM0_FLT0 pin
10062 * 0b1..CMP0 out
10063 */
10064#define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
10065#define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
10066#define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
10067/*! FTM0FLT1 - FTM0 Fault 1 Select
10068 * 0b0..FTM0_FLT1 pin
10069 * 0b1..CMP1 out
10070 */
10071#define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
10072#define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
10073#define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
10074/*! FTM1FLT0 - FTM1 Fault 0 Select
10075 * 0b0..FTM1_FLT0 pin
10076 * 0b1..CMP0 out
10077 */
10078#define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
10079#define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
10080#define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
10081/*! FTM2FLT0 - FTM2 Fault 0 Select
10082 * 0b0..FTM2_FLT0 pin
10083 * 0b1..CMP0 out
10084 */
10085#define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
10086#define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
10087#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
10088/*! FTM1CH0SRC - FTM1 channel 0 input capture source select
10089 * 0b00..FTM1_CH0 signal
10090 * 0b01..CMP0 output
10091 * 0b10..CMP1 output
10092 * 0b11..Reserved
10093 */
10094#define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
10095#define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
10096#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
10097/*! FTM2CH0SRC - FTM2 channel 0 input capture source select
10098 * 0b00..FTM2_CH0 signal
10099 * 0b01..CMP0 output
10100 * 0b10..CMP1 output
10101 * 0b11..Reserved
10102 */
10103#define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
10104#define SIM_SOPT4_FTM2CH1SRC_MASK (0x400000U)
10105#define SIM_SOPT4_FTM2CH1SRC_SHIFT (22U)
10106/*! FTM2CH1SRC - FTM2 channel 1 input capture source select
10107 * 0b0..FTM2_CH1 signal
10108 * 0b1..Exclusive OR of FTM2_CH1, FTM2_CH0 and FTM1_CH1.
10109 */
10110#define SIM_SOPT4_FTM2CH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
10111#define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
10112#define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
10113/*! FTM0CLKSEL - FlexTimer 0 External Clock Pin Select
10114 * 0b0..FTM_CLK0 pin
10115 * 0b1..FTM_CLK1 pin
10116 */
10117#define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
10118#define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
10119#define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
10120/*! FTM1CLKSEL - FTM1 External Clock Pin Select
10121 * 0b0..FTM_CLK0 pin
10122 * 0b1..FTM_CLK1 pin
10123 */
10124#define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
10125#define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
10126#define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
10127/*! FTM2CLKSEL - FlexTimer 2 External Clock Pin Select
10128 * 0b0..FTM2 external clock driven by FTM_CLK0 pin.
10129 * 0b1..FTM2 external clock driven by FTM_CLK1 pin.
10130 */
10131#define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
10132#define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
10133#define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
10134/*! FTM0TRG0SRC - FlexTimer 0 Hardware Trigger 0 Source Select
10135 * 0b0..HSCMP0 output drives FTM0 hardware trigger 0
10136 * 0b1..FTM1 channel match drives FTM0 hardware trigger 0
10137 */
10138#define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
10139#define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
10140#define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
10141/*! FTM0TRG1SRC - FlexTimer 0 Hardware Trigger 1 Source Select
10142 * 0b0..PDB output trigger 1 drives FTM0 hardware trigger 1
10143 * 0b1..FTM2 channel match drives FTM0 hardware trigger 1
10144 */
10145#define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
10146/*! @} */
10147
10148/*! @name SOPT5 - System Options Register 5 */
10149/*! @{ */
10150#define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
10151#define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
10152/*! UART0TXSRC - UART 0 transmit data source select
10153 * 0b00..UART0_TX pin
10154 * 0b01..UART0_TX pin modulated with FTM1 channel 0 output
10155 * 0b10..UART0_TX pin modulated with FTM2 channel 0 output
10156 * 0b11..Reserved
10157 */
10158#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
10159#define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
10160#define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
10161/*! UART0RXSRC - UART 0 receive data source select
10162 * 0b00..UART0_RX pin
10163 * 0b01..CMP0
10164 * 0b10..CMP1
10165 * 0b11..Reserved
10166 */
10167#define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
10168#define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
10169#define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
10170/*! UART1TXSRC - UART 1 transmit data source select
10171 * 0b00..UART1_TX pin
10172 * 0b01..UART1_TX pin modulated with FTM1 channel 0 output
10173 * 0b10..UART1_TX pin modulated with FTM2 channel 0 output
10174 * 0b11..Reserved
10175 */
10176#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
10177#define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
10178#define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
10179/*! UART1RXSRC - UART 1 receive data source select
10180 * 0b00..UART1_RX pin
10181 * 0b01..CMP0
10182 * 0b10..CMP1
10183 * 0b11..Reserved
10184 */
10185#define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
10186#define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U)
10187#define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U)
10188/*! LPUART0RXSRC - LPUART0 receive data source select
10189 * 0b00..LPUART0_RX pin
10190 * 0b01..CMP0 output
10191 * 0b10..CMP1 output
10192 * 0b11..Reserved
10193 */
10194#define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
10195/*! @} */
10196
10197/*! @name SOPT7 - System Options Register 7 */
10198/*! @{ */
10199#define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
10200#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
10201/*! ADC0TRGSEL - ADC0 trigger select
10202 * 0b0000..PDB external trigger pin input (PDB0_EXTRG)
10203 * 0b0001..High speed comparator 0 output
10204 * 0b0010..High speed comparator 1 output
10205 * 0b0011..Reserved
10206 * 0b0100..PIT trigger 0
10207 * 0b0101..PIT trigger 1
10208 * 0b0110..PIT trigger 2
10209 * 0b0111..PIT trigger 3
10210 * 0b1000..FTM0 trigger
10211 * 0b1001..FTM1 trigger
10212 * 0b1010..FTM2 trigger
10213 * 0b1011..Reserved
10214 * 0b1100..Reserved
10215 * 0b1101..Reserved
10216 * 0b1110..Low-power timer (LPTMR) trigger
10217 * 0b1111..Reserved
10218 */
10219#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
10220#define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
10221#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
10222/*! ADC0PRETRGSEL - ADC0 pretrigger select
10223 * 0b0..Pre-trigger A
10224 * 0b1..Pre-trigger B
10225 */
10226#define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
10227#define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
10228#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
10229/*! ADC0ALTTRGEN - ADC0 alternate trigger enable
10230 * 0b0..PDB trigger selected for ADC0.
10231 * 0b1..Alternate trigger selected for ADC0.
10232 */
10233#define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
10234#define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
10235#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
10236/*! ADC1TRGSEL - ADC1 trigger select
10237 * 0b0000..PDB external trigger pin input (PDB0_EXTRG)
10238 * 0b0001..High speed comparator 0 output
10239 * 0b0010..High speed comparator 1 output
10240 * 0b0011..Reserved
10241 * 0b0100..PIT trigger 0
10242 * 0b0101..PIT trigger 1
10243 * 0b0110..PIT trigger 2
10244 * 0b0111..PIT trigger 3
10245 * 0b1000..FTM0 trigger
10246 * 0b1001..FTM1 trigger
10247 * 0b1010..FTM2 trigger
10248 * 0b1011..Reserved
10249 * 0b1100..Reserved
10250 * 0b1101..Reserved
10251 * 0b1110..Low-power timer (LPTMR) trigger
10252 * 0b1111..Reserved
10253 */
10254#define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
10255#define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
10256#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
10257/*! ADC1PRETRGSEL - ADC1 pre-trigger select
10258 * 0b0..Pre-trigger A selected for ADC1.
10259 * 0b1..Pre-trigger B selected for ADC1.
10260 */
10261#define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
10262#define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
10263#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
10264/*! ADC1ALTTRGEN - ADC1 alternate trigger enable
10265 * 0b0..PDB trigger selected for ADC1
10266 * 0b1..Alternate trigger selected for ADC1 as defined by ADC1TRGSEL.
10267 */
10268#define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
10269/*! @} */
10270
10271/*! @name SOPT8 - System Options Register 8 */
10272/*! @{ */
10273#define SIM_SOPT8_FTM0SYNCBIT_MASK (0x1U)
10274#define SIM_SOPT8_FTM0SYNCBIT_SHIFT (0U)
10275/*! FTM0SYNCBIT - FTM0 Hardware Trigger 0 Software Synchronization
10276 * 0b0..No effect
10277 * 0b1..Write 1 to assert the TRIG0 input to FTM0, software must clear this bit to allow other trigger sources to assert.
10278 */
10279#define SIM_SOPT8_FTM0SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
10280#define SIM_SOPT8_FTM1SYNCBIT_MASK (0x2U)
10281#define SIM_SOPT8_FTM1SYNCBIT_SHIFT (1U)
10282/*! FTM1SYNCBIT - FTM1 Hardware Trigger 0 Software Synchronization
10283 * 0b0..No effect.
10284 * 0b1..Write 1 to assert the TRIG0 input to FTM1, software must clear this bit to allow other trigger sources to assert.
10285 */
10286#define SIM_SOPT8_FTM1SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
10287#define SIM_SOPT8_FTM2SYNCBIT_MASK (0x4U)
10288#define SIM_SOPT8_FTM2SYNCBIT_SHIFT (2U)
10289/*! FTM2SYNCBIT - FTM2 Hardware Trigger 0 Software Synchronization
10290 * 0b0..No effect.
10291 * 0b1..Write 1 to assert the TRIG0 input to FTM2, software must clear this bit to allow other trigger sources to assert.
10292 */
10293#define SIM_SOPT8_FTM2SYNCBIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
10294#define SIM_SOPT8_FTM0OCH0SRC_MASK (0x10000U)
10295#define SIM_SOPT8_FTM0OCH0SRC_SHIFT (16U)
10296/*! FTM0OCH0SRC - FTM0 channel 0 output source
10297 * 0b0..FTM0_CH0 pin is output of FTM0 channel 0 output
10298 * 0b1..FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by FTM1 channel 1 output
10299 */
10300#define SIM_SOPT8_FTM0OCH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
10301#define SIM_SOPT8_FTM0OCH1SRC_MASK (0x20000U)
10302#define SIM_SOPT8_FTM0OCH1SRC_SHIFT (17U)
10303/*! FTM0OCH1SRC - FTM0 channel 1 output source
10304 * 0b0..FTM0_CH1 pin is output of FTM0 channel 1 output
10305 * 0b1..FTM0_CH1 pin is output of FTM0 channel 1 output, modulated by FTM1 channel 1 output
10306 */
10307#define SIM_SOPT8_FTM0OCH1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
10308#define SIM_SOPT8_FTM0OCH2SRC_MASK (0x40000U)
10309#define SIM_SOPT8_FTM0OCH2SRC_SHIFT (18U)
10310/*! FTM0OCH2SRC - FTM0 channel 2 output source
10311 * 0b0..FTM0_CH2 pin is output of FTM0 channel 2 output
10312 * 0b1..FTM0_CH2 pin is output of FTM0 channel 2 output, modulated by FTM1 channel 1 output
10313 */
10314#define SIM_SOPT8_FTM0OCH2SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
10315#define SIM_SOPT8_FTM0OCH3SRC_MASK (0x80000U)
10316#define SIM_SOPT8_FTM0OCH3SRC_SHIFT (19U)
10317/*! FTM0OCH3SRC - FTM0 channel 3 output source
10318 * 0b0..FTM0_CH3 pin is output of FTM0 channel 3 output
10319 * 0b1..FTM0_CH3 pin is output of FTM0 channel 3 output, modulated by FTM1 channel 1 output
10320 */
10321#define SIM_SOPT8_FTM0OCH3SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
10322#define SIM_SOPT8_FTM0OCH4SRC_MASK (0x100000U)
10323#define SIM_SOPT8_FTM0OCH4SRC_SHIFT (20U)
10324/*! FTM0OCH4SRC - FTM0 channel 4 output source
10325 * 0b0..FTM0_CH4 pin is output of FTM0 channel 4 output
10326 * 0b1..FTM0_CH4 pin is output of FTM0 channel 4 output, modulated by FTM1 channel 1 output
10327 */
10328#define SIM_SOPT8_FTM0OCH4SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
10329#define SIM_SOPT8_FTM0OCH5SRC_MASK (0x200000U)
10330#define SIM_SOPT8_FTM0OCH5SRC_SHIFT (21U)
10331/*! FTM0OCH5SRC - FTM0 channel 5 output source
10332 * 0b0..FTM0_CH5 pin is output of FTM0 channel 5 output
10333 * 0b1..FTM0_CH5 pin is output of FTM0 channel 5 output, modulated by FTM1 channel 1 output
10334 */
10335#define SIM_SOPT8_FTM0OCH5SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
10336#define SIM_SOPT8_FTM0OCH6SRC_MASK (0x400000U)
10337#define SIM_SOPT8_FTM0OCH6SRC_SHIFT (22U)
10338/*! FTM0OCH6SRC - FTM0 channel 6 output source
10339 * 0b0..FTM0_CH6 pin is output of FTM0 channel 6 output
10340 * 0b1..FTM0_CH6 pin is output of FTM0 channel 6 output, modulated by FTM1 channel 1 output
10341 */
10342#define SIM_SOPT8_FTM0OCH6SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
10343#define SIM_SOPT8_FTM0OCH7SRC_MASK (0x800000U)
10344#define SIM_SOPT8_FTM0OCH7SRC_SHIFT (23U)
10345/*! FTM0OCH7SRC - FTM0 channel 7 output source
10346 * 0b0..FTM0_CH7 pin is output of FTM0 channel 7 output
10347 * 0b1..FTM0_CH7 pin is output of FTM0 channel 7 output, modulated by FTM1 channel 1 output
10348 */
10349#define SIM_SOPT8_FTM0OCH7SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
10350/*! @} */
10351
10352/*! @name SDID - System Device Identification Register */
10353/*! @{ */
10354#define SIM_SDID_PINID_MASK (0xFU)
10355#define SIM_SDID_PINID_SHIFT (0U)
10356/*! PINID - Pincount identification
10357 * 0b0000..Reserved
10358 * 0b0001..Reserved
10359 * 0b0010..32-pin
10360 * 0b0011..Reserved
10361 * 0b0100..48-pin
10362 * 0b0101..64-pin
10363 * 0b0110..80-pin
10364 * 0b0111..81-pin or 121-pin
10365 * 0b1000..100-pin
10366 * 0b1001..121-pin
10367 * 0b1010..144-pin
10368 * 0b1011..Custom pinout (WLCSP)
10369 * 0b1100..169-pin
10370 * 0b1101..Reserved
10371 * 0b1110..256-pin
10372 * 0b1111..Reserved
10373 */
10374#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
10375#define SIM_SDID_DIEID_MASK (0xF80U)
10376#define SIM_SDID_DIEID_SHIFT (7U)
10377#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
10378#define SIM_SDID_REVID_MASK (0xF000U)
10379#define SIM_SDID_REVID_SHIFT (12U)
10380#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
10381#define SIM_SDID_SERIESID_MASK (0xF00000U)
10382#define SIM_SDID_SERIESID_SHIFT (20U)
10383/*! SERIESID - Kinetis Series ID
10384 * 0b0000..Kinetis K series
10385 * 0b0001..Kinetis L series
10386 * 0b0101..Kinetis W series
10387 * 0b0110..Kinetis V series
10388 */
10389#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
10390#define SIM_SDID_SUBFAMID_MASK (0xF000000U)
10391#define SIM_SDID_SUBFAMID_SHIFT (24U)
10392/*! SUBFAMID - Kinetis Sub-Family ID
10393 * 0b0000..KVx0 Subfamily
10394 * 0b0001..KVx1 Subfamily
10395 * 0b0010..KVx2 Subfamily
10396 * 0b0011..KVx3 Subfamily
10397 * 0b0100..KVx4 Subfamily
10398 * 0b0101..KVx5 Subfamily
10399 * 0b0110..KVx6 Subfamily
10400 */
10401#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
10402#define SIM_SDID_FAMILYID_MASK (0xF0000000U)
10403#define SIM_SDID_FAMILYID_SHIFT (28U)
10404/*! FAMILYID - Kinetis Family ID
10405 * 0b0001..KV1x Family
10406 * 0b0010..KV2x Family
10407 * 0b0011..KV3x Family
10408 * 0b0100..KV4x Family
10409 * 0b0110..KV6x Family
10410 * 0b0111..KV7x Family
10411 */
10412#define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
10413/*! @} */
10414
10415/*! @name SCGC4 - System Clock Gating Control Register 4 */
10416/*! @{ */
10417#define SIM_SCGC4_EWM_MASK (0x2U)
10418#define SIM_SCGC4_EWM_SHIFT (1U)
10419/*! EWM - EWM Clock Gate Control
10420 * 0b0..Clock disabled
10421 * 0b1..Clock enabled
10422 */
10423#define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
10424#define SIM_SCGC4_I2C0_MASK (0x40U)
10425#define SIM_SCGC4_I2C0_SHIFT (6U)
10426/*! I2C0 - I2C0 Clock Gate Control
10427 * 0b0..Clock disabled
10428 * 0b1..Clock enabled
10429 */
10430#define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
10431#define SIM_SCGC4_I2C1_MASK (0x80U)
10432#define SIM_SCGC4_I2C1_SHIFT (7U)
10433/*! I2C1 - I2C1 Clock Gate Control
10434 * 0b0..Clock disabled
10435 * 0b1..Clock enabled
10436 */
10437#define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
10438#define SIM_SCGC4_UART0_MASK (0x400U)
10439#define SIM_SCGC4_UART0_SHIFT (10U)
10440/*! UART0 - UART0 Clock Gate Control
10441 * 0b0..Clock disabled
10442 * 0b1..Clock enabled
10443 */
10444#define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
10445#define SIM_SCGC4_UART1_MASK (0x800U)
10446#define SIM_SCGC4_UART1_SHIFT (11U)
10447/*! UART1 - UART1 Clock Gate Control
10448 * 0b0..Clock disabled
10449 * 0b1..Clock enabled
10450 */
10451#define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
10452#define SIM_SCGC4_UART2_MASK (0x1000U)
10453#define SIM_SCGC4_UART2_SHIFT (12U)
10454/*! UART2 - UART2 Clock Gate Control
10455 * 0b0..Clock disabled
10456 * 0b1..Clock enabled
10457 */
10458#define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
10459#define SIM_SCGC4_CMP_MASK (0x80000U)
10460#define SIM_SCGC4_CMP_SHIFT (19U)
10461/*! CMP - Comparator Clock Gate Control
10462 * 0b0..Clock disabled
10463 * 0b1..Clock enabled
10464 */
10465#define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
10466#define SIM_SCGC4_VREF_MASK (0x100000U)
10467#define SIM_SCGC4_VREF_SHIFT (20U)
10468/*! VREF - VREF Clock Gate Control
10469 * 0b0..Clock disabled
10470 * 0b1..Clock enabled
10471 */
10472#define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
10473/*! @} */
10474
10475/*! @name SCGC5 - System Clock Gating Control Register 5 */
10476/*! @{ */
10477#define SIM_SCGC5_LPTMR_MASK (0x1U)
10478#define SIM_SCGC5_LPTMR_SHIFT (0U)
10479/*! LPTMR - Low Power Timer Access Control
10480 * 0b0..Access disabled
10481 * 0b1..Access enabled
10482 */
10483#define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
10484#define SIM_SCGC5_PORTA_MASK (0x200U)
10485#define SIM_SCGC5_PORTA_SHIFT (9U)
10486/*! PORTA - Port A Clock Gate Control
10487 * 0b0..Clock disabled
10488 * 0b1..Clock enabled
10489 */
10490#define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
10491#define SIM_SCGC5_PORTB_MASK (0x400U)
10492#define SIM_SCGC5_PORTB_SHIFT (10U)
10493/*! PORTB - Port B Clock Gate Control
10494 * 0b0..Clock disabled
10495 * 0b1..Clock enabled
10496 */
10497#define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
10498#define SIM_SCGC5_PORTC_MASK (0x800U)
10499#define SIM_SCGC5_PORTC_SHIFT (11U)
10500/*! PORTC - Port C Clock Gate Control
10501 * 0b0..Clock disabled
10502 * 0b1..Clock enabled
10503 */
10504#define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
10505#define SIM_SCGC5_PORTD_MASK (0x1000U)
10506#define SIM_SCGC5_PORTD_SHIFT (12U)
10507/*! PORTD - Port D Clock Gate Control
10508 * 0b0..Clock disabled
10509 * 0b1..Clock enabled
10510 */
10511#define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
10512#define SIM_SCGC5_PORTE_MASK (0x2000U)
10513#define SIM_SCGC5_PORTE_SHIFT (13U)
10514/*! PORTE - Port E Clock Gate Control
10515 * 0b0..Clock disabled
10516 * 0b1..Clock enabled
10517 */
10518#define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
10519/*! @} */
10520
10521/*! @name SCGC6 - System Clock Gating Control Register 6 */
10522/*! @{ */
10523#define SIM_SCGC6_FTF_MASK (0x1U)
10524#define SIM_SCGC6_FTF_SHIFT (0U)
10525/*! FTF - Flash Memory Clock Gate Control
10526 * 0b0..Clock disabled
10527 * 0b1..Clock enabled
10528 */
10529#define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
10530#define SIM_SCGC6_DMAMUX_MASK (0x2U)
10531#define SIM_SCGC6_DMAMUX_SHIFT (1U)
10532/*! DMAMUX - DMA Mux Clock Gate Control
10533 * 0b0..Clock disabled
10534 * 0b1..Clock enabled
10535 */
10536#define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
10537#define SIM_SCGC6_ADC1_MASK (0x80U)
10538#define SIM_SCGC6_ADC1_SHIFT (7U)
10539/*! ADC1 - ADC1 Clock Gate Control
10540 * 0b0..Clock disabled
10541 * 0b1..Clock enabled
10542 */
10543#define SIM_SCGC6_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC1_SHIFT)) & SIM_SCGC6_ADC1_MASK)
10544#define SIM_SCGC6_RNGA_MASK (0x200U)
10545#define SIM_SCGC6_RNGA_SHIFT (9U)
10546#define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
10547#define SIM_SCGC6_LPUART0_MASK (0x400U)
10548#define SIM_SCGC6_LPUART0_SHIFT (10U)
10549/*! LPUART0 - LPUART0 Clock Gate Control
10550 * 0b0..Clock disabled
10551 * 0b1..Clock enabled
10552 */
10553#define SIM_SCGC6_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_LPUART0_SHIFT)) & SIM_SCGC6_LPUART0_MASK)
10554#define SIM_SCGC6_SPI0_MASK (0x1000U)
10555#define SIM_SCGC6_SPI0_SHIFT (12U)
10556/*! SPI0 - SPI0 Clock Gate Control
10557 * 0b0..Clock disabled
10558 * 0b1..Clock enabled
10559 */
10560#define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
10561#define SIM_SCGC6_SPI1_MASK (0x2000U)
10562#define SIM_SCGC6_SPI1_SHIFT (13U)
10563/*! SPI1 - SPI1 Clock Gate Control
10564 * 0b0..Clock disabled
10565 * 0b1..Clock enabled
10566 */
10567#define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
10568#define SIM_SCGC6_CRC_MASK (0x40000U)
10569#define SIM_SCGC6_CRC_SHIFT (18U)
10570/*! CRC - CRC Clock Gate Control
10571 * 0b0..Clock disabled
10572 * 0b1..Clock enabled
10573 */
10574#define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
10575#define SIM_SCGC6_PDB_MASK (0x400000U)
10576#define SIM_SCGC6_PDB_SHIFT (22U)
10577/*! PDB - PDB Clock Gate Control
10578 * 0b0..Clock disabled
10579 * 0b1..Clock enabled
10580 */
10581#define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
10582#define SIM_SCGC6_PIT_MASK (0x800000U)
10583#define SIM_SCGC6_PIT_SHIFT (23U)
10584/*! PIT - PIT Clock Gate Control
10585 * 0b0..Clock disabled
10586 * 0b1..Clock enabled
10587 */
10588#define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
10589#define SIM_SCGC6_FTM0_MASK (0x1000000U)
10590#define SIM_SCGC6_FTM0_SHIFT (24U)
10591/*! FTM0 - FTM0 Clock Gate Control
10592 * 0b0..Clock disabled
10593 * 0b1..Clock enabled
10594 */
10595#define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
10596#define SIM_SCGC6_FTM1_MASK (0x2000000U)
10597#define SIM_SCGC6_FTM1_SHIFT (25U)
10598/*! FTM1 - FTM1 Clock Gate Control
10599 * 0b0..Clock disabled
10600 * 0b1..Clock enabled
10601 */
10602#define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
10603#define SIM_SCGC6_FTM2_MASK (0x4000000U)
10604#define SIM_SCGC6_FTM2_SHIFT (26U)
10605/*! FTM2 - FTM2 Clock Gate Control
10606 * 0b0..Clock disabled
10607 * 0b1..Clock enabled
10608 */
10609#define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
10610#define SIM_SCGC6_ADC0_MASK (0x8000000U)
10611#define SIM_SCGC6_ADC0_SHIFT (27U)
10612/*! ADC0 - ADC0 Clock Gate Control
10613 * 0b0..Clock disabled
10614 * 0b1..Clock enabled
10615 */
10616#define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
10617#define SIM_SCGC6_DAC0_MASK (0x80000000U)
10618#define SIM_SCGC6_DAC0_SHIFT (31U)
10619/*! DAC0 - DAC0 Clock Gate Control
10620 * 0b0..Clock disabled
10621 * 0b1..Clock enabled
10622 */
10623#define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
10624/*! @} */
10625
10626/*! @name SCGC7 - System Clock Gating Control Register 7 */
10627/*! @{ */
10628#define SIM_SCGC7_DMA_MASK (0x2U)
10629#define SIM_SCGC7_DMA_SHIFT (1U)
10630/*! DMA - DMA Clock Gate Control
10631 * 0b0..Clock disabled
10632 * 0b1..Clock enabled
10633 */
10634#define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
10635/*! @} */
10636
10637/*! @name CLKDIV1 - System Clock Divider Register 1 */
10638/*! @{ */
10639#define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
10640#define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
10641/*! OUTDIV4 - Clock 4 output divider value
10642 * 0b0000..Divide-by-1.
10643 * 0b0001..Divide-by-2.
10644 * 0b0010..Divide-by-3.
10645 * 0b0011..Divide-by-4.
10646 * 0b0100..Divide-by-5.
10647 * 0b0101..Divide-by-6.
10648 * 0b0110..Divide-by-7.
10649 * 0b0111..Divide-by-8.
10650 * 0b1000..Divide-by-9.
10651 * 0b1001..Divide-by-10.
10652 * 0b1010..Divide-by-11.
10653 * 0b1011..Divide-by-12.
10654 * 0b1100..Divide-by-13.
10655 * 0b1101..Divide-by-14.
10656 * 0b1110..Divide-by-15.
10657 * 0b1111..Divide-by-16.
10658 */
10659#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
10660#define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
10661#define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
10662/*! OUTDIV2 - Clock 2 output divider value
10663 * 0b0000..Divide-by-1.
10664 * 0b0001..Divide-by-2.
10665 * 0b0010..Divide-by-3.
10666 * 0b0011..Divide-by-4.
10667 * 0b0100..Divide-by-5.
10668 * 0b0101..Divide-by-6.
10669 * 0b0110..Divide-by-7.
10670 * 0b0111..Divide-by-8.
10671 * 0b1000..Divide-by-9.
10672 * 0b1001..Divide-by-10.
10673 * 0b1010..Divide-by-11.
10674 * 0b1011..Divide-by-12.
10675 * 0b1100..Divide-by-13.
10676 * 0b1101..Divide-by-14.
10677 * 0b1110..Divide-by-15.
10678 * 0b1111..Divide-by-16.
10679 */
10680#define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
10681#define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
10682#define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
10683/*! OUTDIV1 - Clock 1 output divider value
10684 * 0b0000..Divide-by-1.
10685 * 0b0001..Divide-by-2.
10686 * 0b0010..Divide-by-3.
10687 * 0b0011..Divide-by-4.
10688 * 0b0100..Divide-by-5.
10689 * 0b0101..Divide-by-6.
10690 * 0b0110..Divide-by-7.
10691 * 0b0111..Divide-by-8.
10692 * 0b1000..Divide-by-9.
10693 * 0b1001..Divide-by-10.
10694 * 0b1010..Divide-by-11.
10695 * 0b1011..Divide-by-12.
10696 * 0b1100..Divide-by-13.
10697 * 0b1101..Divide-by-14.
10698 * 0b1110..Divide-by-15.
10699 * 0b1111..Divide-by-16.
10700 */
10701#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
10702/*! @} */
10703
10704/*! @name FCFG1 - Flash Configuration Register 1 */
10705/*! @{ */
10706#define SIM_FCFG1_FLASHDIS_MASK (0x1U)
10707#define SIM_FCFG1_FLASHDIS_SHIFT (0U)
10708/*! FLASHDIS - Flash Disable
10709 * 0b0..Flash is enabled
10710 * 0b1..Flash is disabled
10711 */
10712#define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
10713#define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
10714#define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
10715/*! FLASHDOZE - Flash Doze
10716 * 0b0..Flash remains enabled during Wait mode
10717 * 0b1..Flash is disabled for the duration of Wait mode
10718 */
10719#define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
10720#define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
10721#define SIM_FCFG1_PFSIZE_SHIFT (24U)
10722/*! PFSIZE - Program flash size
10723 * 0b0011..32 KB of program flash memory
10724 * 0b0101..64 KB of program flash memory
10725 * 0b0111..128 KB of program flash memory
10726 * 0b1001..256 KB of program flash memory
10727 * 0b1011..512 KB of program flash memory
10728 * 0b1101..1024 KB of program flash memory
10729 * 0b1111..256 KB of program flash memory
10730 */
10731#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
10732/*! @} */
10733
10734/*! @name FCFG2 - Flash Configuration Register 2 */
10735/*! @{ */
10736#define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
10737#define SIM_FCFG2_MAXADDR1_SHIFT (16U)
10738#define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
10739#define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
10740#define SIM_FCFG2_MAXADDR0_SHIFT (24U)
10741#define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
10742/*! @} */
10743
10744/*! @name UIDH - Unique Identification Register High */
10745/*! @{ */
10746#define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
10747#define SIM_UIDH_UID_SHIFT (0U)
10748#define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
10749/*! @} */
10750
10751/*! @name UIDMH - Unique Identification Register Mid-High */
10752/*! @{ */
10753#define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
10754#define SIM_UIDMH_UID_SHIFT (0U)
10755#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
10756/*! @} */
10757
10758/*! @name UIDML - Unique Identification Register Mid Low */
10759/*! @{ */
10760#define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
10761#define SIM_UIDML_UID_SHIFT (0U)
10762#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
10763/*! @} */
10764
10765/*! @name UIDL - Unique Identification Register Low */
10766/*! @{ */
10767#define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
10768#define SIM_UIDL_UID_SHIFT (0U)
10769#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
10770/*! @} */
10771
10772
10773/*!
10774 * @}
10775 */ /* end of group SIM_Register_Masks */
10776
10777
10778/* SIM - Peripheral instance base addresses */
10779/** Peripheral SIM base address */
10780#define SIM_BASE (0x40047000u)
10781/** Peripheral SIM base pointer */
10782#define SIM ((SIM_Type *)SIM_BASE)
10783/** Array initializer of SIM peripheral base addresses */
10784#define SIM_BASE_ADDRS { SIM_BASE }
10785/** Array initializer of SIM peripheral base pointers */
10786#define SIM_BASE_PTRS { SIM }
10787
10788/*!
10789 * @}
10790 */ /* end of group SIM_Peripheral_Access_Layer */
10791
10792
10793/* ----------------------------------------------------------------------------
10794 -- SMC Peripheral Access Layer
10795 ---------------------------------------------------------------------------- */
10796
10797/*!
10798 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
10799 * @{
10800 */
10801
10802/** SMC - Register Layout Typedef */
10803typedef struct {
10804 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
10805 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
10806 __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */
10807 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
10808} SMC_Type;
10809
10810/* ----------------------------------------------------------------------------
10811 -- SMC Register Masks
10812 ---------------------------------------------------------------------------- */
10813
10814/*!
10815 * @addtogroup SMC_Register_Masks SMC Register Masks
10816 * @{
10817 */
10818
10819/*! @name PMPROT - Power Mode Protection register */
10820/*! @{ */
10821#define SMC_PMPROT_AVLLS_MASK (0x2U)
10822#define SMC_PMPROT_AVLLS_SHIFT (1U)
10823/*! AVLLS - Allow Very-Low-Leakage Stop Mode
10824 * 0b0..Any VLLSx mode is not allowed
10825 * 0b1..Any VLLSx mode is allowed
10826 */
10827#define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
10828#define SMC_PMPROT_ALLS_MASK (0x8U)
10829#define SMC_PMPROT_ALLS_SHIFT (3U)
10830/*! ALLS - Allow Low-Leakage Stop Mode
10831 * 0b0..Any LLSx mode is not allowed
10832 * 0b1..Any LLSx mode is allowed
10833 */
10834#define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
10835#define SMC_PMPROT_AVLP_MASK (0x20U)
10836#define SMC_PMPROT_AVLP_SHIFT (5U)
10837/*! AVLP - Allow Very-Low-Power Modes
10838 * 0b0..VLPR, VLPW, and VLPS are not allowed.
10839 * 0b1..VLPR, VLPW, and VLPS are allowed.
10840 */
10841#define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
10842#define SMC_PMPROT_AHSRUN_MASK (0x80U)
10843#define SMC_PMPROT_AHSRUN_SHIFT (7U)
10844/*! AHSRUN - Allow High Speed Run mode
10845 * 0b0..HSRUN is not allowed
10846 * 0b1..HSRUN is allowed
10847 */
10848#define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
10849/*! @} */
10850
10851/*! @name PMCTRL - Power Mode Control register */
10852/*! @{ */
10853#define SMC_PMCTRL_STOPM_MASK (0x7U)
10854#define SMC_PMCTRL_STOPM_SHIFT (0U)
10855/*! STOPM - Stop Mode Control
10856 * 0b000..Normal Stop (STOP)
10857 * 0b001..Reserved
10858 * 0b010..Very-Low-Power Stop (VLPS)
10859 * 0b011..Low-Leakage Stop (LLSx)
10860 * 0b100..Very-Low-Leakage Stop (VLLSx)
10861 * 0b101..Reserved
10862 * 0b110..Reseved
10863 * 0b111..Reserved
10864 */
10865#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
10866#define SMC_PMCTRL_STOPA_MASK (0x8U)
10867#define SMC_PMCTRL_STOPA_SHIFT (3U)
10868/*! STOPA - Stop Aborted
10869 * 0b0..The previous stop mode entry was successsful.
10870 * 0b1..The previous stop mode entry was aborted.
10871 */
10872#define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
10873#define SMC_PMCTRL_RUNM_MASK (0x60U)
10874#define SMC_PMCTRL_RUNM_SHIFT (5U)
10875/*! RUNM - Run Mode Control
10876 * 0b00..Normal Run mode (RUN)
10877 * 0b01..Reserved
10878 * 0b10..Very-Low-Power Run mode (VLPR)
10879 * 0b11..High Speed Run mode (HSRUN)
10880 */
10881#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
10882/*! @} */
10883
10884/*! @name STOPCTRL - Stop Control Register */
10885/*! @{ */
10886#define SMC_STOPCTRL_LLSM_MASK (0x7U)
10887#define SMC_STOPCTRL_LLSM_SHIFT (0U)
10888/*! LLSM - LLS or VLLS Mode Control
10889 * 0b000..VLLS0if PMCTRL[STOPM]=VLLSx, Reserved if PMCTRL[STOPM]=LLSx
10890 * 0b001..VLLS1if PMCTRL[STOPM]=VLLSx, Reserved if PMCTRL[STOPM]=LLSx
10891 * 0b010..VLLS2if PMCTRL[STOPM]=VLLSx, LLS2 if PMCTRL[STOPM]=LLSx
10892 * 0b011..VLLS3if PMCTRL[STOPM]=VLLSx, LLS3 if PMCTRL[STOPM]=LLSx
10893 * 0b100..Reserved
10894 * 0b101..Reserved
10895 * 0b110..Reserved
10896 * 0b111..Reserved
10897 */
10898#define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
10899#define SMC_STOPCTRL_PORPO_MASK (0x20U)
10900#define SMC_STOPCTRL_PORPO_SHIFT (5U)
10901/*! PORPO - POR Power Option
10902 * 0b0..POR detect circuit is enabled in VLLS0
10903 * 0b1..POR detect circuit is disabled in VLLS0
10904 */
10905#define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
10906#define SMC_STOPCTRL_PSTOPO_MASK (0xC0U)
10907#define SMC_STOPCTRL_PSTOPO_SHIFT (6U)
10908/*! PSTOPO - Partial Stop Option
10909 * 0b00..STOP - Normal Stop mode
10910 * 0b01..PSTOP1 - Partial Stop with both system and bus clocks disabled
10911 * 0b10..PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
10912 * 0b11..Reserved
10913 */
10914#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
10915/*! @} */
10916
10917/*! @name PMSTAT - Power Mode Status register */
10918/*! @{ */
10919#define SMC_PMSTAT_PMSTAT_MASK (0xFFU)
10920#define SMC_PMSTAT_PMSTAT_SHIFT (0U)
10921#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
10922/*! @} */
10923
10924
10925/*!
10926 * @}
10927 */ /* end of group SMC_Register_Masks */
10928
10929
10930/* SMC - Peripheral instance base addresses */
10931/** Peripheral SMC base address */
10932#define SMC_BASE (0x4007E000u)
10933/** Peripheral SMC base pointer */
10934#define SMC ((SMC_Type *)SMC_BASE)
10935/** Array initializer of SMC peripheral base addresses */
10936#define SMC_BASE_ADDRS { SMC_BASE }
10937/** Array initializer of SMC peripheral base pointers */
10938#define SMC_BASE_PTRS { SMC }
10939
10940/*!
10941 * @}
10942 */ /* end of group SMC_Peripheral_Access_Layer */
10943
10944
10945/* ----------------------------------------------------------------------------
10946 -- SPI Peripheral Access Layer
10947 ---------------------------------------------------------------------------- */
10948
10949/*!
10950 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
10951 * @{
10952 */
10953
10954/** SPI - Register Layout Typedef */
10955typedef struct {
10956 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
10957 uint8_t RESERVED_0[4];
10958 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
10959 union { /* offset: 0xC */
10960 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
10961 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
10962 };
10963 uint8_t RESERVED_1[24];
10964 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
10965 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
10966 union { /* offset: 0x34 */
10967 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
10968 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
10969 };
10970 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
10971 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
10972 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
10973 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
10974 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
10975 uint8_t RESERVED_2[48];
10976 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
10977 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
10978 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
10979 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
10980} SPI_Type;
10981
10982/* ----------------------------------------------------------------------------
10983 -- SPI Register Masks
10984 ---------------------------------------------------------------------------- */
10985
10986/*!
10987 * @addtogroup SPI_Register_Masks SPI Register Masks
10988 * @{
10989 */
10990
10991/*! @name MCR - Module Configuration Register */
10992/*! @{ */
10993#define SPI_MCR_HALT_MASK (0x1U)
10994#define SPI_MCR_HALT_SHIFT (0U)
10995/*! HALT - Halt
10996 * 0b0..Start transfers.
10997 * 0b1..Stop transfers.
10998 */
10999#define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
11000#define SPI_MCR_SMPL_PT_MASK (0x300U)
11001#define SPI_MCR_SMPL_PT_SHIFT (8U)
11002/*! SMPL_PT - Sample Point
11003 * 0b00..0 protocol clock cycles between SCK edge and SIN sample
11004 * 0b01..1 protocol clock cycle between SCK edge and SIN sample
11005 * 0b10..2 protocol clock cycles between SCK edge and SIN sample
11006 * 0b11..Reserved
11007 */
11008#define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
11009#define SPI_MCR_CLR_RXF_MASK (0x400U)
11010#define SPI_MCR_CLR_RXF_SHIFT (10U)
11011/*! CLR_RXF
11012 * 0b0..Do not clear the RX FIFO counter.
11013 * 0b1..Clear the RX FIFO counter.
11014 */
11015#define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
11016#define SPI_MCR_CLR_TXF_MASK (0x800U)
11017#define SPI_MCR_CLR_TXF_SHIFT (11U)
11018/*! CLR_TXF - Clear TX FIFO
11019 * 0b0..Do not clear the TX FIFO counter.
11020 * 0b1..Clear the TX FIFO counter.
11021 */
11022#define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
11023#define SPI_MCR_DIS_RXF_MASK (0x1000U)
11024#define SPI_MCR_DIS_RXF_SHIFT (12U)
11025/*! DIS_RXF - Disable Receive FIFO
11026 * 0b0..RX FIFO is enabled.
11027 * 0b1..RX FIFO is disabled.
11028 */
11029#define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
11030#define SPI_MCR_DIS_TXF_MASK (0x2000U)
11031#define SPI_MCR_DIS_TXF_SHIFT (13U)
11032/*! DIS_TXF - Disable Transmit FIFO
11033 * 0b0..TX FIFO is enabled.
11034 * 0b1..TX FIFO is disabled.
11035 */
11036#define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
11037#define SPI_MCR_MDIS_MASK (0x4000U)
11038#define SPI_MCR_MDIS_SHIFT (14U)
11039/*! MDIS - Module Disable
11040 * 0b0..Enables the module clocks.
11041 * 0b1..Allows external logic to disable the module clocks.
11042 */
11043#define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
11044#define SPI_MCR_DOZE_MASK (0x8000U)
11045#define SPI_MCR_DOZE_SHIFT (15U)
11046/*! DOZE - Doze Enable
11047 * 0b0..Doze mode has no effect on the module.
11048 * 0b1..Doze mode disables the module.
11049 */
11050#define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
11051#define SPI_MCR_PCSIS_MASK (0x3F0000U)
11052#define SPI_MCR_PCSIS_SHIFT (16U)
11053/*! PCSIS - Peripheral Chip Select x Inactive State
11054 * 0b000000..The inactive state of PCSx is low.
11055 * 0b000001..The inactive state of PCSx is high.
11056 */
11057#define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
11058#define SPI_MCR_ROOE_MASK (0x1000000U)
11059#define SPI_MCR_ROOE_SHIFT (24U)
11060/*! ROOE - Receive FIFO Overflow Overwrite Enable
11061 * 0b0..Incoming data is ignored.
11062 * 0b1..Incoming data is shifted into the shift register.
11063 */
11064#define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
11065#define SPI_MCR_PCSSE_MASK (0x2000000U)
11066#define SPI_MCR_PCSSE_SHIFT (25U)
11067/*! PCSSE - Peripheral Chip Select Strobe Enable
11068 * 0b0..PCS5/ PCSS is used as the Peripheral Chip Select[5] signal.
11069 * 0b1..PCS5/ PCSS is used as an active-low PCS Strobe signal.
11070 */
11071#define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
11072#define SPI_MCR_MTFE_MASK (0x4000000U)
11073#define SPI_MCR_MTFE_SHIFT (26U)
11074/*! MTFE - Modified Timing Format Enable
11075 * 0b0..Modified SPI transfer format disabled.
11076 * 0b1..Modified SPI transfer format enabled.
11077 */
11078#define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
11079#define SPI_MCR_FRZ_MASK (0x8000000U)
11080#define SPI_MCR_FRZ_SHIFT (27U)
11081/*! FRZ - Freeze
11082 * 0b0..Do not halt serial transfers in Debug mode.
11083 * 0b1..Halt serial transfers in Debug mode.
11084 */
11085#define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
11086#define SPI_MCR_DCONF_MASK (0x30000000U)
11087#define SPI_MCR_DCONF_SHIFT (28U)
11088/*! DCONF - SPI Configuration.
11089 * 0b00..SPI
11090 * 0b01..Reserved
11091 * 0b10..Reserved
11092 * 0b11..Reserved
11093 */
11094#define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
11095#define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
11096#define SPI_MCR_CONT_SCKE_SHIFT (30U)
11097/*! CONT_SCKE - Continuous SCK Enable
11098 * 0b0..Continuous SCK disabled.
11099 * 0b1..Continuous SCK enabled.
11100 */
11101#define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
11102#define SPI_MCR_MSTR_MASK (0x80000000U)
11103#define SPI_MCR_MSTR_SHIFT (31U)
11104/*! MSTR - Master/Slave Mode Select
11105 * 0b0..Enables Slave mode
11106 * 0b1..Enables Master mode
11107 */
11108#define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
11109/*! @} */
11110
11111/*! @name TCR - Transfer Count Register */
11112/*! @{ */
11113#define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
11114#define SPI_TCR_SPI_TCNT_SHIFT (16U)
11115#define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
11116/*! @} */
11117
11118/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
11119/*! @{ */
11120#define SPI_CTAR_BR_MASK (0xFU)
11121#define SPI_CTAR_BR_SHIFT (0U)
11122#define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
11123#define SPI_CTAR_DT_MASK (0xF0U)
11124#define SPI_CTAR_DT_SHIFT (4U)
11125#define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
11126#define SPI_CTAR_ASC_MASK (0xF00U)
11127#define SPI_CTAR_ASC_SHIFT (8U)
11128#define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
11129#define SPI_CTAR_CSSCK_MASK (0xF000U)
11130#define SPI_CTAR_CSSCK_SHIFT (12U)
11131#define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
11132#define SPI_CTAR_PBR_MASK (0x30000U)
11133#define SPI_CTAR_PBR_SHIFT (16U)
11134/*! PBR - Baud Rate Prescaler
11135 * 0b00..Baud Rate Prescaler value is 2.
11136 * 0b01..Baud Rate Prescaler value is 3.
11137 * 0b10..Baud Rate Prescaler value is 5.
11138 * 0b11..Baud Rate Prescaler value is 7.
11139 */
11140#define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
11141#define SPI_CTAR_PDT_MASK (0xC0000U)
11142#define SPI_CTAR_PDT_SHIFT (18U)
11143/*! PDT - Delay after Transfer Prescaler
11144 * 0b00..Delay after Transfer Prescaler value is 1.
11145 * 0b01..Delay after Transfer Prescaler value is 3.
11146 * 0b10..Delay after Transfer Prescaler value is 5.
11147 * 0b11..Delay after Transfer Prescaler value is 7.
11148 */
11149#define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
11150#define SPI_CTAR_PASC_MASK (0x300000U)
11151#define SPI_CTAR_PASC_SHIFT (20U)
11152/*! PASC - After SCK Delay Prescaler
11153 * 0b00..Delay after Transfer Prescaler value is 1.
11154 * 0b01..Delay after Transfer Prescaler value is 3.
11155 * 0b10..Delay after Transfer Prescaler value is 5.
11156 * 0b11..Delay after Transfer Prescaler value is 7.
11157 */
11158#define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
11159#define SPI_CTAR_PCSSCK_MASK (0xC00000U)
11160#define SPI_CTAR_PCSSCK_SHIFT (22U)
11161/*! PCSSCK - PCS to SCK Delay Prescaler
11162 * 0b00..PCS to SCK Prescaler value is 1.
11163 * 0b01..PCS to SCK Prescaler value is 3.
11164 * 0b10..PCS to SCK Prescaler value is 5.
11165 * 0b11..PCS to SCK Prescaler value is 7.
11166 */
11167#define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
11168#define SPI_CTAR_LSBFE_MASK (0x1000000U)
11169#define SPI_CTAR_LSBFE_SHIFT (24U)
11170/*! LSBFE - LSB First
11171 * 0b0..Data is transferred MSB first.
11172 * 0b1..Data is transferred LSB first.
11173 */
11174#define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
11175#define SPI_CTAR_CPHA_MASK (0x2000000U)
11176#define SPI_CTAR_CPHA_SHIFT (25U)
11177/*! CPHA - Clock Phase
11178 * 0b0..Data is captured on the leading edge of SCK and changed on the following edge.
11179 * 0b1..Data is changed on the leading edge of SCK and captured on the following edge.
11180 */
11181#define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
11182#define SPI_CTAR_CPOL_MASK (0x4000000U)
11183#define SPI_CTAR_CPOL_SHIFT (26U)
11184/*! CPOL - Clock Polarity
11185 * 0b0..The inactive state value of SCK is low.
11186 * 0b1..The inactive state value of SCK is high.
11187 */
11188#define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
11189#define SPI_CTAR_FMSZ_MASK (0x78000000U)
11190#define SPI_CTAR_FMSZ_SHIFT (27U)
11191#define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
11192#define SPI_CTAR_DBR_MASK (0x80000000U)
11193#define SPI_CTAR_DBR_SHIFT (31U)
11194/*! DBR - Double Baud Rate
11195 * 0b0..The baud rate is computed normally with a 50/50 duty cycle.
11196 * 0b1..The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler.
11197 */
11198#define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
11199/*! @} */
11200
11201/* The count of SPI_CTAR */
11202#define SPI_CTAR_COUNT (2U)
11203
11204/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
11205/*! @{ */
11206#define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
11207#define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
11208/*! CPHA - Clock Phase
11209 * 0b0..Data is captured on the leading edge of SCK and changed on the following edge.
11210 * 0b1..Data is changed on the leading edge of SCK and captured on the following edge.
11211 */
11212#define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
11213#define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
11214#define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
11215/*! CPOL - Clock Polarity
11216 * 0b0..The inactive state value of SCK is low.
11217 * 0b1..The inactive state value of SCK is high.
11218 */
11219#define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
11220#define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U)
11221#define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
11222#define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
11223/*! @} */
11224
11225/* The count of SPI_CTAR_SLAVE */
11226#define SPI_CTAR_SLAVE_COUNT (1U)
11227
11228/*! @name SR - Status Register */
11229/*! @{ */
11230#define SPI_SR_POPNXTPTR_MASK (0xFU)
11231#define SPI_SR_POPNXTPTR_SHIFT (0U)
11232#define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
11233#define SPI_SR_RXCTR_MASK (0xF0U)
11234#define SPI_SR_RXCTR_SHIFT (4U)
11235#define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
11236#define SPI_SR_TXNXTPTR_MASK (0xF00U)
11237#define SPI_SR_TXNXTPTR_SHIFT (8U)
11238#define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
11239#define SPI_SR_TXCTR_MASK (0xF000U)
11240#define SPI_SR_TXCTR_SHIFT (12U)
11241#define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
11242#define SPI_SR_RFDF_MASK (0x20000U)
11243#define SPI_SR_RFDF_SHIFT (17U)
11244/*! RFDF - Receive FIFO Drain Flag
11245 * 0b0..RX FIFO is empty.
11246 * 0b1..RX FIFO is not empty.
11247 */
11248#define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
11249#define SPI_SR_RFOF_MASK (0x80000U)
11250#define SPI_SR_RFOF_SHIFT (19U)
11251/*! RFOF - Receive FIFO Overflow Flag
11252 * 0b0..No Rx FIFO overflow.
11253 * 0b1..Rx FIFO overflow has occurred.
11254 */
11255#define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
11256#define SPI_SR_TFFF_MASK (0x2000000U)
11257#define SPI_SR_TFFF_SHIFT (25U)
11258/*! TFFF - Transmit FIFO Fill Flag
11259 * 0b0..TX FIFO is full.
11260 * 0b1..TX FIFO is not full.
11261 */
11262#define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
11263#define SPI_SR_TFUF_MASK (0x8000000U)
11264#define SPI_SR_TFUF_SHIFT (27U)
11265/*! TFUF - Transmit FIFO Underflow Flag
11266 * 0b0..No TX FIFO underflow.
11267 * 0b1..TX FIFO underflow has occurred.
11268 */
11269#define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
11270#define SPI_SR_EOQF_MASK (0x10000000U)
11271#define SPI_SR_EOQF_SHIFT (28U)
11272/*! EOQF - End of Queue Flag
11273 * 0b0..EOQ is not set in the executing command.
11274 * 0b1..EOQ is set in the executing SPI command.
11275 */
11276#define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
11277#define SPI_SR_TXRXS_MASK (0x40000000U)
11278#define SPI_SR_TXRXS_SHIFT (30U)
11279/*! TXRXS - TX and RX Status
11280 * 0b0..Transmit and receive operations are disabled (The module is in Stopped state).
11281 * 0b1..Transmit and receive operations are enabled (The module is in Running state).
11282 */
11283#define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
11284#define SPI_SR_TCF_MASK (0x80000000U)
11285#define SPI_SR_TCF_SHIFT (31U)
11286/*! TCF - Transfer Complete Flag
11287 * 0b0..Transfer not complete.
11288 * 0b1..Transfer complete.
11289 */
11290#define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
11291/*! @} */
11292
11293/*! @name RSER - DMA/Interrupt Request Select and Enable Register */
11294/*! @{ */
11295#define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
11296#define SPI_RSER_RFDF_DIRS_SHIFT (16U)
11297/*! RFDF_DIRS - Receive FIFO Drain DMA or Interrupt Request Select
11298 * 0b0..Interrupt request.
11299 * 0b1..DMA request.
11300 */
11301#define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
11302#define SPI_RSER_RFDF_RE_MASK (0x20000U)
11303#define SPI_RSER_RFDF_RE_SHIFT (17U)
11304/*! RFDF_RE - Receive FIFO Drain Request Enable
11305 * 0b0..RFDF interrupt or DMA requests are disabled.
11306 * 0b1..RFDF interrupt or DMA requests are enabled.
11307 */
11308#define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
11309#define SPI_RSER_RFOF_RE_MASK (0x80000U)
11310#define SPI_RSER_RFOF_RE_SHIFT (19U)
11311/*! RFOF_RE - Receive FIFO Overflow Request Enable
11312 * 0b0..RFOF interrupt requests are disabled.
11313 * 0b1..RFOF interrupt requests are enabled.
11314 */
11315#define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
11316#define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
11317#define SPI_RSER_TFFF_DIRS_SHIFT (24U)
11318/*! TFFF_DIRS - Transmit FIFO Fill DMA or Interrupt Request Select
11319 * 0b0..TFFF flag generates interrupt requests.
11320 * 0b1..TFFF flag generates DMA requests.
11321 */
11322#define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
11323#define SPI_RSER_TFFF_RE_MASK (0x2000000U)
11324#define SPI_RSER_TFFF_RE_SHIFT (25U)
11325/*! TFFF_RE - Transmit FIFO Fill Request Enable
11326 * 0b0..TFFF interrupts or DMA requests are disabled.
11327 * 0b1..TFFF interrupts or DMA requests are enabled.
11328 */
11329#define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
11330#define SPI_RSER_TFUF_RE_MASK (0x8000000U)
11331#define SPI_RSER_TFUF_RE_SHIFT (27U)
11332/*! TFUF_RE - Transmit FIFO Underflow Request Enable
11333 * 0b0..TFUF interrupt requests are disabled.
11334 * 0b1..TFUF interrupt requests are enabled.
11335 */
11336#define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
11337#define SPI_RSER_EOQF_RE_MASK (0x10000000U)
11338#define SPI_RSER_EOQF_RE_SHIFT (28U)
11339/*! EOQF_RE - Finished Request Enable
11340 * 0b0..EOQF interrupt requests are disabled.
11341 * 0b1..EOQF interrupt requests are enabled.
11342 */
11343#define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
11344#define SPI_RSER_TCF_RE_MASK (0x80000000U)
11345#define SPI_RSER_TCF_RE_SHIFT (31U)
11346/*! TCF_RE - Transmission Complete Request Enable
11347 * 0b0..TCF interrupt requests are disabled.
11348 * 0b1..TCF interrupt requests are enabled.
11349 */
11350#define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
11351/*! @} */
11352
11353/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
11354/*! @{ */
11355#define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
11356#define SPI_PUSHR_TXDATA_SHIFT (0U)
11357#define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
11358#define SPI_PUSHR_PCS_MASK (0x3F0000U)
11359#define SPI_PUSHR_PCS_SHIFT (16U)
11360/*! PCS
11361 * 0b000000..Negate the PCS[x] signal.
11362 * 0b000001..Assert the PCS[x] signal.
11363 */
11364#define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
11365#define SPI_PUSHR_CTCNT_MASK (0x4000000U)
11366#define SPI_PUSHR_CTCNT_SHIFT (26U)
11367/*! CTCNT - Clear Transfer Counter
11368 * 0b0..Do not clear the TCR[TCNT] field.
11369 * 0b1..Clear the TCR[TCNT] field.
11370 */
11371#define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
11372#define SPI_PUSHR_EOQ_MASK (0x8000000U)
11373#define SPI_PUSHR_EOQ_SHIFT (27U)
11374/*! EOQ - End Of Queue
11375 * 0b0..The SPI data is not the last data to transfer.
11376 * 0b1..The SPI data is the last data to transfer.
11377 */
11378#define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
11379#define SPI_PUSHR_CTAS_MASK (0x70000000U)
11380#define SPI_PUSHR_CTAS_SHIFT (28U)
11381/*! CTAS - Clock and Transfer Attributes Select
11382 * 0b000..CTAR0
11383 * 0b001..CTAR1
11384 * 0b010..Reserved
11385 * 0b011..Reserved
11386 * 0b100..Reserved
11387 * 0b101..Reserved
11388 * 0b110..Reserved
11389 * 0b111..Reserved
11390 */
11391#define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
11392#define SPI_PUSHR_CONT_MASK (0x80000000U)
11393#define SPI_PUSHR_CONT_SHIFT (31U)
11394/*! CONT - Continuous Peripheral Chip Select Enable
11395 * 0b0..Return PCSn signals to their inactive state between transfers.
11396 * 0b1..Keep PCSn signals asserted between transfers.
11397 */
11398#define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
11399/*! @} */
11400
11401/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
11402/*! @{ */
11403#define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
11404#define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
11405#define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
11406/*! @} */
11407
11408/*! @name POPR - POP RX FIFO Register */
11409/*! @{ */
11410#define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
11411#define SPI_POPR_RXDATA_SHIFT (0U)
11412#define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
11413/*! @} */
11414
11415/*! @name TXFR0 - Transmit FIFO Registers */
11416/*! @{ */
11417#define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
11418#define SPI_TXFR0_TXDATA_SHIFT (0U)
11419#define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
11420#define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
11421#define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
11422#define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
11423/*! @} */
11424
11425/*! @name TXFR1 - Transmit FIFO Registers */
11426/*! @{ */
11427#define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
11428#define SPI_TXFR1_TXDATA_SHIFT (0U)
11429#define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
11430#define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
11431#define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
11432#define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
11433/*! @} */
11434
11435/*! @name TXFR2 - Transmit FIFO Registers */
11436/*! @{ */
11437#define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
11438#define SPI_TXFR2_TXDATA_SHIFT (0U)
11439#define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
11440#define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
11441#define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
11442#define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
11443/*! @} */
11444
11445/*! @name TXFR3 - Transmit FIFO Registers */
11446/*! @{ */
11447#define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
11448#define SPI_TXFR3_TXDATA_SHIFT (0U)
11449#define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
11450#define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
11451#define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
11452#define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
11453/*! @} */
11454
11455/*! @name RXFR0 - Receive FIFO Registers */
11456/*! @{ */
11457#define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
11458#define SPI_RXFR0_RXDATA_SHIFT (0U)
11459#define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
11460/*! @} */
11461
11462/*! @name RXFR1 - Receive FIFO Registers */
11463/*! @{ */
11464#define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
11465#define SPI_RXFR1_RXDATA_SHIFT (0U)
11466#define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
11467/*! @} */
11468
11469/*! @name RXFR2 - Receive FIFO Registers */
11470/*! @{ */
11471#define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
11472#define SPI_RXFR2_RXDATA_SHIFT (0U)
11473#define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
11474/*! @} */
11475
11476/*! @name RXFR3 - Receive FIFO Registers */
11477/*! @{ */
11478#define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
11479#define SPI_RXFR3_RXDATA_SHIFT (0U)
11480#define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
11481/*! @} */
11482
11483
11484/*!
11485 * @}
11486 */ /* end of group SPI_Register_Masks */
11487
11488
11489/* SPI - Peripheral instance base addresses */
11490/** Peripheral SPI0 base address */
11491#define SPI0_BASE (0x4002C000u)
11492/** Peripheral SPI0 base pointer */
11493#define SPI0 ((SPI_Type *)SPI0_BASE)
11494/** Peripheral SPI1 base address */
11495#define SPI1_BASE (0x4002D000u)
11496/** Peripheral SPI1 base pointer */
11497#define SPI1 ((SPI_Type *)SPI1_BASE)
11498/** Array initializer of SPI peripheral base addresses */
11499#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE }
11500/** Array initializer of SPI peripheral base pointers */
11501#define SPI_BASE_PTRS { SPI0, SPI1 }
11502/** Interrupt vectors for the SPI peripheral type */
11503#define SPI_IRQS { SPI0_IRQn, SPI1_IRQn }
11504
11505/*!
11506 * @}
11507 */ /* end of group SPI_Peripheral_Access_Layer */
11508
11509
11510/* ----------------------------------------------------------------------------
11511 -- UART Peripheral Access Layer
11512 ---------------------------------------------------------------------------- */
11513
11514/*!
11515 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
11516 * @{
11517 */
11518
11519/** UART - Register Layout Typedef */
11520typedef struct {
11521 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
11522 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
11523 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
11524 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
11525 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
11526 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
11527 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
11528 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
11529 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
11530 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
11531 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
11532 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
11533 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
11534 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
11535 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
11536 uint8_t RESERVED_0[1];
11537 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
11538 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
11539 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
11540 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
11541 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
11542 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
11543 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
11544 uint8_t RESERVED_1[1];
11545 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
11546 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
11547 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
11548 __IO uint8_t WP7816; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
11549 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
11550 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
11551 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
11552 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
11553 uint8_t RESERVED_2[26];
11554 __IO uint8_t AP7816A_T0; /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
11555 __IO uint8_t AP7816B_T0; /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
11556 union { /* offset: 0x3C */
11557 struct { /* offset: 0x3C */
11558 __IO uint8_t WP7816A_T0; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
11559 __IO uint8_t WP7816B_T0; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
11560 } TYPE0;
11561 struct { /* offset: 0x3C */
11562 __IO uint8_t WP7816A_T1; /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
11563 __IO uint8_t WP7816B_T1; /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
11564 } TYPE1;
11565 };
11566 __IO uint8_t WGP7816_T1; /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
11567 __IO uint8_t WP7816C_T1; /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
11568} UART_Type;
11569
11570/* ----------------------------------------------------------------------------
11571 -- UART Register Masks
11572 ---------------------------------------------------------------------------- */
11573
11574/*!
11575 * @addtogroup UART_Register_Masks UART Register Masks
11576 * @{
11577 */
11578
11579/*! @name BDH - UART Baud Rate Registers: High */
11580/*! @{ */
11581#define UART_BDH_SBR_MASK (0x1FU)
11582#define UART_BDH_SBR_SHIFT (0U)
11583#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
11584#define UART_BDH_RXEDGIE_MASK (0x40U)
11585#define UART_BDH_RXEDGIE_SHIFT (6U)
11586/*! RXEDGIE - RxD Input Active Edge Interrupt Enable
11587 * 0b0..Hardware interrupts from RXEDGIF disabled using polling.
11588 * 0b1..RXEDGIF interrupt request enabled.
11589 */
11590#define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
11591#define UART_BDH_LBKDIE_MASK (0x80U)
11592#define UART_BDH_LBKDIE_SHIFT (7U)
11593/*! LBKDIE - LIN Break Detect Interrupt Enable
11594 * 0b0..LBKDIF interrupt requests disabled.
11595 * 0b1..LBKDIF interrupt requests enabled.
11596 */
11597#define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
11598/*! @} */
11599
11600/*! @name BDL - UART Baud Rate Registers: Low */
11601/*! @{ */
11602#define UART_BDL_SBR_MASK (0xFFU)
11603#define UART_BDL_SBR_SHIFT (0U)
11604#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
11605/*! @} */
11606
11607/*! @name C1 - UART Control Register 1 */
11608/*! @{ */
11609#define UART_C1_PT_MASK (0x1U)
11610#define UART_C1_PT_SHIFT (0U)
11611/*! PT - Parity Type
11612 * 0b0..Even parity.
11613 * 0b1..Odd parity.
11614 */
11615#define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
11616#define UART_C1_PE_MASK (0x2U)
11617#define UART_C1_PE_SHIFT (1U)
11618/*! PE - Parity Enable
11619 * 0b0..Parity function disabled.
11620 * 0b1..Parity function enabled.
11621 */
11622#define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
11623#define UART_C1_ILT_MASK (0x4U)
11624#define UART_C1_ILT_SHIFT (2U)
11625/*! ILT - Idle Line Type Select
11626 * 0b0..Idle character bit count starts after start bit.
11627 * 0b1..Idle character bit count starts after stop bit.
11628 */
11629#define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
11630#define UART_C1_WAKE_MASK (0x8U)
11631#define UART_C1_WAKE_SHIFT (3U)
11632/*! WAKE - Receiver Wakeup Method Select
11633 * 0b0..Idle line wakeup.
11634 * 0b1..Address mark wakeup.
11635 */
11636#define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
11637#define UART_C1_M_MASK (0x10U)
11638#define UART_C1_M_SHIFT (4U)
11639/*! M - 9-bit or 8-bit Mode Select
11640 * 0b0..Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
11641 * 0b1..Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
11642 */
11643#define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
11644#define UART_C1_RSRC_MASK (0x20U)
11645#define UART_C1_RSRC_SHIFT (5U)
11646/*! RSRC - Receiver Source Select
11647 * 0b0..Selects internal loop back mode. The receiver input is internally connected to transmitter output.
11648 * 0b1..Single wire UART mode where the receiver input is connected to the transmit pin input signal.
11649 */
11650#define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
11651#define UART_C1_UARTSWAI_MASK (0x40U)
11652#define UART_C1_UARTSWAI_SHIFT (6U)
11653/*! UARTSWAI - UART Stops in Wait Mode
11654 * 0b0..UART clock continues to run in Wait mode.
11655 * 0b1..UART clock freezes while CPU is in Wait mode.
11656 */
11657#define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
11658#define UART_C1_LOOPS_MASK (0x80U)
11659#define UART_C1_LOOPS_SHIFT (7U)
11660/*! LOOPS - Loop Mode Select
11661 * 0b0..Normal operation.
11662 * 0b1..Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
11663 */
11664#define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
11665/*! @} */
11666
11667/*! @name C2 - UART Control Register 2 */
11668/*! @{ */
11669#define UART_C2_SBK_MASK (0x1U)
11670#define UART_C2_SBK_SHIFT (0U)
11671/*! SBK - Send Break
11672 * 0b0..Normal transmitter operation.
11673 * 0b1..Queue break characters to be sent.
11674 */
11675#define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
11676#define UART_C2_RWU_MASK (0x2U)
11677#define UART_C2_RWU_SHIFT (1U)
11678/*! RWU - Receiver Wakeup Control
11679 * 0b0..Normal operation.
11680 * 0b1..RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
11681 */
11682#define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
11683#define UART_C2_RE_MASK (0x4U)
11684#define UART_C2_RE_SHIFT (2U)
11685/*! RE - Receiver Enable
11686 * 0b0..Receiver off.
11687 * 0b1..Receiver on.
11688 */
11689#define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
11690#define UART_C2_TE_MASK (0x8U)
11691#define UART_C2_TE_SHIFT (3U)
11692/*! TE - Transmitter Enable
11693 * 0b0..Transmitter off.
11694 * 0b1..Transmitter on.
11695 */
11696#define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
11697#define UART_C2_ILIE_MASK (0x10U)
11698#define UART_C2_ILIE_SHIFT (4U)
11699/*! ILIE - Idle Line Interrupt Enable
11700 * 0b0..IDLE interrupt requests disabled.
11701 * 0b1..IDLE interrupt requests enabled.
11702 */
11703#define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
11704#define UART_C2_RIE_MASK (0x20U)
11705#define UART_C2_RIE_SHIFT (5U)
11706/*! RIE - Receiver Full Interrupt or DMA Transfer Enable
11707 * 0b0..RDRF interrupt and DMA transfer requests disabled.
11708 * 0b1..RDRF interrupt or DMA transfer requests enabled.
11709 */
11710#define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
11711#define UART_C2_TCIE_MASK (0x40U)
11712#define UART_C2_TCIE_SHIFT (6U)
11713/*! TCIE - Transmission Complete Interrupt Enable
11714 * 0b0..TC interrupt requests disabled.
11715 * 0b1..TC interrupt requests enabled.
11716 */
11717#define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
11718#define UART_C2_TIE_MASK (0x80U)
11719#define UART_C2_TIE_SHIFT (7U)
11720/*! TIE - Transmitter Interrupt or DMA Transfer Enable.
11721 * 0b0..TDRE interrupt and DMA transfer requests disabled.
11722 * 0b1..TDRE interrupt or DMA transfer requests enabled.
11723 */
11724#define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
11725/*! @} */
11726
11727/*! @name S1 - UART Status Register 1 */
11728/*! @{ */
11729#define UART_S1_PF_MASK (0x1U)
11730#define UART_S1_PF_SHIFT (0U)
11731/*! PF - Parity Error Flag
11732 * 0b0..No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
11733 * 0b1..At least one dataword was received with a parity error since the last time this flag was cleared.
11734 */
11735#define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
11736#define UART_S1_FE_MASK (0x2U)
11737#define UART_S1_FE_SHIFT (1U)
11738/*! FE - Framing Error Flag
11739 * 0b0..No framing error detected.
11740 * 0b1..Framing error.
11741 */
11742#define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
11743#define UART_S1_NF_MASK (0x4U)
11744#define UART_S1_NF_SHIFT (2U)
11745/*! NF - Noise Flag
11746 * 0b0..No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
11747 * 0b1..At least one dataword was received with noise detected since the last time the flag was cleared.
11748 */
11749#define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
11750#define UART_S1_OR_MASK (0x8U)
11751#define UART_S1_OR_SHIFT (3U)
11752/*! OR - Receiver Overrun Flag
11753 * 0b0..No overrun has occurred since the last time the flag was cleared.
11754 * 0b1..Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
11755 */
11756#define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
11757#define UART_S1_IDLE_MASK (0x10U)
11758#define UART_S1_IDLE_SHIFT (4U)
11759/*! IDLE - Idle Line Flag
11760 * 0b0..Receiver input is either active now or has never become active since the IDLE flag was last cleared.
11761 * 0b1..Receiver input has become idle or the flag has not been cleared since it last asserted.
11762 */
11763#define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
11764#define UART_S1_RDRF_MASK (0x20U)
11765#define UART_S1_RDRF_SHIFT (5U)
11766/*! RDRF - Receive Data Register Full Flag
11767 * 0b0..The number of datawords in the receive buffer is less than the number indicated by RXWATER.
11768 * 0b1..The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
11769 */
11770#define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
11771#define UART_S1_TC_MASK (0x40U)
11772#define UART_S1_TC_SHIFT (6U)
11773/*! TC - Transmit Complete Flag
11774 * 0b0..Transmitter active (sending data, a preamble, or a break).
11775 * 0b1..Transmitter idle (transmission activity complete).
11776 */
11777#define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
11778#define UART_S1_TDRE_MASK (0x80U)
11779#define UART_S1_TDRE_SHIFT (7U)
11780/*! TDRE - Transmit Data Register Empty Flag
11781 * 0b0..The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
11782 * 0b1..The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
11783 */
11784#define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
11785/*! @} */
11786
11787/*! @name S2 - UART Status Register 2 */
11788/*! @{ */
11789#define UART_S2_RAF_MASK (0x1U)
11790#define UART_S2_RAF_SHIFT (0U)
11791/*! RAF - Receiver Active Flag
11792 * 0b0..UART receiver idle/inactive waiting for a start bit.
11793 * 0b1..UART receiver active, RxD input not idle.
11794 */
11795#define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
11796#define UART_S2_LBKDE_MASK (0x2U)
11797#define UART_S2_LBKDE_SHIFT (1U)
11798/*! LBKDE - LIN Break Detection Enable
11799 * 0b0..Break character detection is disabled.
11800 * 0b1..Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1.
11801 */
11802#define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
11803#define UART_S2_BRK13_MASK (0x4U)
11804#define UART_S2_BRK13_SHIFT (2U)
11805/*! BRK13 - Break Transmit Character Length
11806 * 0b0..Break character is 10, 11, or 12 bits long.
11807 * 0b1..Break character is 13 or 14 bits long.
11808 */
11809#define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
11810#define UART_S2_RWUID_MASK (0x8U)
11811#define UART_S2_RWUID_SHIFT (3U)
11812/*! RWUID - Receive Wakeup Idle Detect
11813 * 0b0..S1[IDLE] is not set upon detection of an idle character.
11814 * 0b1..S1[IDLE] is set upon detection of an idle character.
11815 */
11816#define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
11817#define UART_S2_RXINV_MASK (0x10U)
11818#define UART_S2_RXINV_SHIFT (4U)
11819/*! RXINV - Receive Data Inversion
11820 * 0b0..Receive data is not inverted.
11821 * 0b1..Receive data is inverted.
11822 */
11823#define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
11824#define UART_S2_MSBF_MASK (0x20U)
11825#define UART_S2_MSBF_SHIFT (5U)
11826/*! MSBF - Most Significant Bit First
11827 * 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
11828 * 0b1..MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
11829 */
11830#define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
11831#define UART_S2_RXEDGIF_MASK (0x40U)
11832#define UART_S2_RXEDGIF_SHIFT (6U)
11833/*! RXEDGIF - RxD Pin Active Edge Interrupt Flag
11834 * 0b0..No active edge on the receive pin has occurred.
11835 * 0b1..An active edge on the receive pin has occurred.
11836 */
11837#define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
11838#define UART_S2_LBKDIF_MASK (0x80U)
11839#define UART_S2_LBKDIF_SHIFT (7U)
11840/*! LBKDIF - LIN Break Detect Interrupt Flag
11841 * 0b0..No LIN break character detected.
11842 * 0b1..LIN break character detected.
11843 */
11844#define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
11845/*! @} */
11846
11847/*! @name C3 - UART Control Register 3 */
11848/*! @{ */
11849#define UART_C3_PEIE_MASK (0x1U)
11850#define UART_C3_PEIE_SHIFT (0U)
11851/*! PEIE - Parity Error Interrupt Enable
11852 * 0b0..PF interrupt requests are disabled.
11853 * 0b1..PF interrupt requests are enabled.
11854 */
11855#define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
11856#define UART_C3_FEIE_MASK (0x2U)
11857#define UART_C3_FEIE_SHIFT (1U)
11858/*! FEIE - Framing Error Interrupt Enable
11859 * 0b0..FE interrupt requests are disabled.
11860 * 0b1..FE interrupt requests are enabled.
11861 */
11862#define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
11863#define UART_C3_NEIE_MASK (0x4U)
11864#define UART_C3_NEIE_SHIFT (2U)
11865/*! NEIE - Noise Error Interrupt Enable
11866 * 0b0..NF interrupt requests are disabled.
11867 * 0b1..NF interrupt requests are enabled.
11868 */
11869#define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
11870#define UART_C3_ORIE_MASK (0x8U)
11871#define UART_C3_ORIE_SHIFT (3U)
11872/*! ORIE - Overrun Error Interrupt Enable
11873 * 0b0..OR interrupts are disabled.
11874 * 0b1..OR interrupt requests are enabled.
11875 */
11876#define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
11877#define UART_C3_TXINV_MASK (0x10U)
11878#define UART_C3_TXINV_SHIFT (4U)
11879/*! TXINV - Transmit Data Inversion.
11880 * 0b0..Transmit data is not inverted.
11881 * 0b1..Transmit data is inverted.
11882 */
11883#define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
11884#define UART_C3_TXDIR_MASK (0x20U)
11885#define UART_C3_TXDIR_SHIFT (5U)
11886/*! TXDIR - Transmitter Pin Data Direction in Single-Wire mode
11887 * 0b0..TXD pin is an input in single wire mode.
11888 * 0b1..TXD pin is an output in single wire mode.
11889 */
11890#define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
11891#define UART_C3_T8_MASK (0x40U)
11892#define UART_C3_T8_SHIFT (6U)
11893#define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
11894#define UART_C3_R8_MASK (0x80U)
11895#define UART_C3_R8_SHIFT (7U)
11896#define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
11897/*! @} */
11898
11899/*! @name D - UART Data Register */
11900/*! @{ */
11901#define UART_D_RT_MASK (0xFFU)
11902#define UART_D_RT_SHIFT (0U)
11903#define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
11904/*! @} */
11905
11906/*! @name MA1 - UART Match Address Registers 1 */
11907/*! @{ */
11908#define UART_MA1_MA_MASK (0xFFU)
11909#define UART_MA1_MA_SHIFT (0U)
11910#define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
11911/*! @} */
11912
11913/*! @name MA2 - UART Match Address Registers 2 */
11914/*! @{ */
11915#define UART_MA2_MA_MASK (0xFFU)
11916#define UART_MA2_MA_SHIFT (0U)
11917#define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
11918/*! @} */
11919
11920/*! @name C4 - UART Control Register 4 */
11921/*! @{ */
11922#define UART_C4_BRFA_MASK (0x1FU)
11923#define UART_C4_BRFA_SHIFT (0U)
11924#define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
11925#define UART_C4_M10_MASK (0x20U)
11926#define UART_C4_M10_SHIFT (5U)
11927/*! M10 - 10-bit Mode select
11928 * 0b0..The parity bit is the ninth bit in the serial transmission.
11929 * 0b1..The parity bit is the tenth bit in the serial transmission.
11930 */
11931#define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
11932#define UART_C4_MAEN2_MASK (0x40U)
11933#define UART_C4_MAEN2_SHIFT (6U)
11934/*! MAEN2 - Match Address Mode Enable 2
11935 * 0b0..All data received is transferred to the data buffer if MAEN1 is cleared.
11936 * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
11937 */
11938#define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
11939#define UART_C4_MAEN1_MASK (0x80U)
11940#define UART_C4_MAEN1_SHIFT (7U)
11941/*! MAEN1 - Match Address Mode Enable 1
11942 * 0b0..All data received is transferred to the data buffer if MAEN2 is cleared.
11943 * 0b1..All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
11944 */
11945#define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
11946/*! @} */
11947
11948/*! @name C5 - UART Control Register 5 */
11949/*! @{ */
11950#define UART_C5_RDMAS_MASK (0x20U)
11951#define UART_C5_RDMAS_SHIFT (5U)
11952/*! RDMAS - Receiver Full DMA Select
11953 * 0b0..If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
11954 * 0b1..If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
11955 */
11956#define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
11957#define UART_C5_TDMAS_MASK (0x80U)
11958#define UART_C5_TDMAS_SHIFT (7U)
11959/*! TDMAS - Transmitter DMA Select
11960 * 0b0..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
11961 * 0b1..If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
11962 */
11963#define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
11964/*! @} */
11965
11966/*! @name ED - UART Extended Data Register */
11967/*! @{ */
11968#define UART_ED_PARITYE_MASK (0x40U)
11969#define UART_ED_PARITYE_SHIFT (6U)
11970/*! PARITYE
11971 * 0b0..The dataword was received without a parity error.
11972 * 0b1..The dataword was received with a parity error.
11973 */
11974#define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
11975#define UART_ED_NOISY_MASK (0x80U)
11976#define UART_ED_NOISY_SHIFT (7U)
11977/*! NOISY
11978 * 0b0..The dataword was received without noise.
11979 * 0b1..The data was received with noise.
11980 */
11981#define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
11982/*! @} */
11983
11984/*! @name MODEM - UART Modem Register */
11985/*! @{ */
11986#define UART_MODEM_TXCTSE_MASK (0x1U)
11987#define UART_MODEM_TXCTSE_SHIFT (0U)
11988/*! TXCTSE - Transmitter clear-to-send enable
11989 * 0b0..CTS has no effect on the transmitter.
11990 * 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
11991 */
11992#define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
11993#define UART_MODEM_TXRTSE_MASK (0x2U)
11994#define UART_MODEM_TXRTSE_SHIFT (1U)
11995/*! TXRTSE - Transmitter request-to-send enable
11996 * 0b0..The transmitter has no effect on RTS.
11997 * 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
11998 */
11999#define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
12000#define UART_MODEM_TXRTSPOL_MASK (0x4U)
12001#define UART_MODEM_TXRTSPOL_SHIFT (2U)
12002/*! TXRTSPOL - Transmitter request-to-send polarity
12003 * 0b0..Transmitter RTS is active low.
12004 * 0b1..Transmitter RTS is active high.
12005 */
12006#define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
12007#define UART_MODEM_RXRTSE_MASK (0x8U)
12008#define UART_MODEM_RXRTSE_SHIFT (3U)
12009/*! RXRTSE - Receiver request-to-send enable
12010 * 0b0..The receiver has no effect on RTS.
12011 * 0b1..RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
12012 */
12013#define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
12014/*! @} */
12015
12016/*! @name IR - UART Infrared Register */
12017/*! @{ */
12018#define UART_IR_TNP_MASK (0x3U)
12019#define UART_IR_TNP_SHIFT (0U)
12020/*! TNP - Transmitter narrow pulse
12021 * 0b00..3/16.
12022 * 0b01..1/16.
12023 * 0b10..1/32.
12024 * 0b11..1/4.
12025 */
12026#define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
12027#define UART_IR_IREN_MASK (0x4U)
12028#define UART_IR_IREN_SHIFT (2U)
12029/*! IREN - Infrared enable
12030 * 0b0..IR disabled.
12031 * 0b1..IR enabled.
12032 */
12033#define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
12034/*! @} */
12035
12036/*! @name PFIFO - UART FIFO Parameters */
12037/*! @{ */
12038#define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
12039#define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
12040/*! RXFIFOSIZE - Receive FIFO. Buffer Depth
12041 * 0b000..Receive FIFO/Buffer depth = 1 dataword.
12042 * 0b001..Receive FIFO/Buffer depth = 4 datawords.
12043 * 0b010..Receive FIFO/Buffer depth = 8 datawords.
12044 * 0b011..Receive FIFO/Buffer depth = 16 datawords.
12045 * 0b100..Receive FIFO/Buffer depth = 32 datawords.
12046 * 0b101..Receive FIFO/Buffer depth = 64 datawords.
12047 * 0b110..Receive FIFO/Buffer depth = 128 datawords.
12048 * 0b111..Reserved.
12049 */
12050#define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
12051#define UART_PFIFO_RXFE_MASK (0x8U)
12052#define UART_PFIFO_RXFE_SHIFT (3U)
12053/*! RXFE - Receive FIFO Enable
12054 * 0b0..Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
12055 * 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
12056 */
12057#define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
12058#define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
12059#define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
12060/*! TXFIFOSIZE - Transmit FIFO. Buffer Depth
12061 * 0b000..Transmit FIFO/Buffer depth = 1 dataword.
12062 * 0b001..Transmit FIFO/Buffer depth = 4 datawords.
12063 * 0b010..Transmit FIFO/Buffer depth = 8 datawords.
12064 * 0b011..Transmit FIFO/Buffer depth = 16 datawords.
12065 * 0b100..Transmit FIFO/Buffer depth = 32 datawords.
12066 * 0b101..Transmit FIFO/Buffer depth = 64 datawords.
12067 * 0b110..Transmit FIFO/Buffer depth = 128 datawords.
12068 * 0b111..Reserved.
12069 */
12070#define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
12071#define UART_PFIFO_TXFE_MASK (0x80U)
12072#define UART_PFIFO_TXFE_SHIFT (7U)
12073/*! TXFE - Transmit FIFO Enable
12074 * 0b0..Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
12075 * 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
12076 */
12077#define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
12078/*! @} */
12079
12080/*! @name CFIFO - UART FIFO Control Register */
12081/*! @{ */
12082#define UART_CFIFO_RXUFE_MASK (0x1U)
12083#define UART_CFIFO_RXUFE_SHIFT (0U)
12084/*! RXUFE - Receive FIFO Underflow Interrupt Enable
12085 * 0b0..RXUF flag does not generate an interrupt to the host.
12086 * 0b1..RXUF flag generates an interrupt to the host.
12087 */
12088#define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
12089#define UART_CFIFO_TXOFE_MASK (0x2U)
12090#define UART_CFIFO_TXOFE_SHIFT (1U)
12091/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
12092 * 0b0..TXOF flag does not generate an interrupt to the host.
12093 * 0b1..TXOF flag generates an interrupt to the host.
12094 */
12095#define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
12096#define UART_CFIFO_RXOFE_MASK (0x4U)
12097#define UART_CFIFO_RXOFE_SHIFT (2U)
12098/*! RXOFE - Receive FIFO Overflow Interrupt Enable
12099 * 0b0..RXOF flag does not generate an interrupt to the host.
12100 * 0b1..RXOF flag generates an interrupt to the host.
12101 */
12102#define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
12103#define UART_CFIFO_RXFLUSH_MASK (0x40U)
12104#define UART_CFIFO_RXFLUSH_SHIFT (6U)
12105/*! RXFLUSH - Receive FIFO/Buffer Flush
12106 * 0b0..No flush operation occurs.
12107 * 0b1..All data in the receive FIFO/buffer is cleared out.
12108 */
12109#define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
12110#define UART_CFIFO_TXFLUSH_MASK (0x80U)
12111#define UART_CFIFO_TXFLUSH_SHIFT (7U)
12112/*! TXFLUSH - Transmit FIFO/Buffer Flush
12113 * 0b0..No flush operation occurs.
12114 * 0b1..All data in the transmit FIFO/Buffer is cleared out.
12115 */
12116#define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
12117/*! @} */
12118
12119/*! @name SFIFO - UART FIFO Status Register */
12120/*! @{ */
12121#define UART_SFIFO_RXUF_MASK (0x1U)
12122#define UART_SFIFO_RXUF_SHIFT (0U)
12123/*! RXUF - Receiver Buffer Underflow Flag
12124 * 0b0..No receive buffer underflow has occurred since the last time the flag was cleared.
12125 * 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.
12126 */
12127#define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
12128#define UART_SFIFO_TXOF_MASK (0x2U)
12129#define UART_SFIFO_TXOF_SHIFT (1U)
12130/*! TXOF - Transmitter Buffer Overflow Flag
12131 * 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared.
12132 * 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.
12133 */
12134#define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
12135#define UART_SFIFO_RXOF_MASK (0x4U)
12136#define UART_SFIFO_RXOF_SHIFT (2U)
12137/*! RXOF - Receiver Buffer Overflow Flag
12138 * 0b0..No receive buffer overflow has occurred since the last time the flag was cleared.
12139 * 0b1..At least one receive buffer overflow has occurred since the last time the flag was cleared.
12140 */
12141#define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
12142#define UART_SFIFO_RXEMPT_MASK (0x40U)
12143#define UART_SFIFO_RXEMPT_SHIFT (6U)
12144/*! RXEMPT - Receive Buffer/FIFO Empty
12145 * 0b0..Receive buffer is not empty.
12146 * 0b1..Receive buffer is empty.
12147 */
12148#define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
12149#define UART_SFIFO_TXEMPT_MASK (0x80U)
12150#define UART_SFIFO_TXEMPT_SHIFT (7U)
12151/*! TXEMPT - Transmit Buffer/FIFO Empty
12152 * 0b0..Transmit buffer is not empty.
12153 * 0b1..Transmit buffer is empty.
12154 */
12155#define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
12156/*! @} */
12157
12158/*! @name TWFIFO - UART FIFO Transmit Watermark */
12159/*! @{ */
12160#define UART_TWFIFO_TXWATER_MASK (0xFFU)
12161#define UART_TWFIFO_TXWATER_SHIFT (0U)
12162#define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
12163/*! @} */
12164
12165/*! @name TCFIFO - UART FIFO Transmit Count */
12166/*! @{ */
12167#define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
12168#define UART_TCFIFO_TXCOUNT_SHIFT (0U)
12169#define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
12170/*! @} */
12171
12172/*! @name RWFIFO - UART FIFO Receive Watermark */
12173/*! @{ */
12174#define UART_RWFIFO_RXWATER_MASK (0xFFU)
12175#define UART_RWFIFO_RXWATER_SHIFT (0U)
12176#define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
12177/*! @} */
12178
12179/*! @name RCFIFO - UART FIFO Receive Count */
12180/*! @{ */
12181#define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
12182#define UART_RCFIFO_RXCOUNT_SHIFT (0U)
12183#define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
12184/*! @} */
12185
12186/*! @name C7816 - UART 7816 Control Register */
12187/*! @{ */
12188#define UART_C7816_ISO_7816E_MASK (0x1U)
12189#define UART_C7816_ISO_7816E_SHIFT (0U)
12190/*! ISO_7816E - ISO-7816 Functionality Enabled
12191 * 0b0..ISO-7816 functionality is turned off/not enabled.
12192 * 0b1..ISO-7816 functionality is turned on/enabled.
12193 */
12194#define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
12195#define UART_C7816_TTYPE_MASK (0x2U)
12196#define UART_C7816_TTYPE_SHIFT (1U)
12197/*! TTYPE - Transfer Type
12198 * 0b0..T = 0 per the ISO-7816 specification.
12199 * 0b1..T = 1 per the ISO-7816 specification.
12200 */
12201#define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
12202#define UART_C7816_INIT_MASK (0x4U)
12203#define UART_C7816_INIT_SHIFT (2U)
12204/*! INIT - Detect Initial Character
12205 * 0b0..Normal operating mode. Receiver does not seek to identify initial character.
12206 * 0b1..Receiver searches for initial character.
12207 */
12208#define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
12209#define UART_C7816_ANACK_MASK (0x8U)
12210#define UART_C7816_ANACK_SHIFT (3U)
12211/*! ANACK - Generate NACK on Error
12212 * 0b0..No NACK is automatically generated.
12213 * 0b1..A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.
12214 */
12215#define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
12216#define UART_C7816_ONACK_MASK (0x10U)
12217#define UART_C7816_ONACK_SHIFT (4U)
12218/*! ONACK - Generate NACK on Overflow
12219 * 0b0..The received data does not generate a NACK when the receipt of the data results in an overflow event.
12220 * 0b1..If the receiver buffer overflows, a NACK is automatically sent on a received character.
12221 */
12222#define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
12223/*! @} */
12224
12225/*! @name IE7816 - UART 7816 Interrupt Enable Register */
12226/*! @{ */
12227#define UART_IE7816_RXTE_MASK (0x1U)
12228#define UART_IE7816_RXTE_SHIFT (0U)
12229/*! RXTE - Receive Threshold Exceeded Interrupt Enable
12230 * 0b0..The assertion of IS7816[RXT] does not result in the generation of an interrupt.
12231 * 0b1..The assertion of IS7816[RXT] results in the generation of an interrupt.
12232 */
12233#define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
12234#define UART_IE7816_TXTE_MASK (0x2U)
12235#define UART_IE7816_TXTE_SHIFT (1U)
12236/*! TXTE - Transmit Threshold Exceeded Interrupt Enable
12237 * 0b0..The assertion of IS7816[TXT] does not result in the generation of an interrupt.
12238 * 0b1..The assertion of IS7816[TXT] results in the generation of an interrupt.
12239 */
12240#define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
12241#define UART_IE7816_GTVE_MASK (0x4U)
12242#define UART_IE7816_GTVE_SHIFT (2U)
12243/*! GTVE - Guard Timer Violated Interrupt Enable
12244 * 0b0..The assertion of IS7816[GTV] does not result in the generation of an interrupt.
12245 * 0b1..The assertion of IS7816[GTV] results in the generation of an interrupt.
12246 */
12247#define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
12248#define UART_IE7816_ADTE_MASK (0x8U)
12249#define UART_IE7816_ADTE_SHIFT (3U)
12250/*! ADTE - ATR Duration Timer Interrupt Enable
12251 * 0b0..The assertion of IS7816[ADT] does not result in the generation of an interrupt.
12252 * 0b1..The assertion of IS7816[ADT] results in the generation of an interrupt.
12253 */
12254#define UART_IE7816_ADTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
12255#define UART_IE7816_INITDE_MASK (0x10U)
12256#define UART_IE7816_INITDE_SHIFT (4U)
12257/*! INITDE - Initial Character Detected Interrupt Enable
12258 * 0b0..The assertion of IS7816[INITD] does not result in the generation of an interrupt.
12259 * 0b1..The assertion of IS7816[INITD] results in the generation of an interrupt.
12260 */
12261#define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
12262#define UART_IE7816_BWTE_MASK (0x20U)
12263#define UART_IE7816_BWTE_SHIFT (5U)
12264/*! BWTE - Block Wait Timer Interrupt Enable
12265 * 0b0..The assertion of IS7816[BWT] does not result in the generation of an interrupt.
12266 * 0b1..The assertion of IS7816[BWT] results in the generation of an interrupt.
12267 */
12268#define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
12269#define UART_IE7816_CWTE_MASK (0x40U)
12270#define UART_IE7816_CWTE_SHIFT (6U)
12271/*! CWTE - Character Wait Timer Interrupt Enable
12272 * 0b0..The assertion of IS7816[CWT] does not result in the generation of an interrupt.
12273 * 0b1..The assertion of IS7816[CWT] results in the generation of an interrupt.
12274 */
12275#define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
12276#define UART_IE7816_WTE_MASK (0x80U)
12277#define UART_IE7816_WTE_SHIFT (7U)
12278/*! WTE - Wait Timer Interrupt Enable
12279 * 0b0..The assertion of IS7816[WT] does not result in the generation of an interrupt.
12280 * 0b1..The assertion of IS7816[WT] results in the generation of an interrupt.
12281 */
12282#define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
12283/*! @} */
12284
12285/*! @name IS7816 - UART 7816 Interrupt Status Register */
12286/*! @{ */
12287#define UART_IS7816_RXT_MASK (0x1U)
12288#define UART_IS7816_RXT_SHIFT (0U)
12289/*! RXT - Receive Threshold Exceeded Interrupt
12290 * 0b0..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].
12291 * 0b1..The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
12292 */
12293#define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
12294#define UART_IS7816_TXT_MASK (0x2U)
12295#define UART_IS7816_TXT_SHIFT (1U)
12296/*! TXT - Transmit Threshold Exceeded Interrupt
12297 * 0b0..The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].
12298 * 0b1..The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].
12299 */
12300#define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
12301#define UART_IS7816_GTV_MASK (0x4U)
12302#define UART_IS7816_GTV_SHIFT (2U)
12303/*! GTV - Guard Timer Violated Interrupt
12304 * 0b0..A guard time (GT, CGT, or BGT) has not been violated.
12305 * 0b1..A guard time (GT, CGT, or BGT) has been violated.
12306 */
12307#define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
12308#define UART_IS7816_ADT_MASK (0x8U)
12309#define UART_IS7816_ADT_SHIFT (3U)
12310/*! ADT - ATR Duration Time Interrupt
12311 * 0b0..ATR Duration time (ADT) has not been violated.
12312 * 0b1..ATR Duration time (ADT) has been violated.
12313 */
12314#define UART_IS7816_ADT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
12315#define UART_IS7816_INITD_MASK (0x10U)
12316#define UART_IS7816_INITD_SHIFT (4U)
12317/*! INITD - Initial Character Detected Interrupt
12318 * 0b0..A valid initial character has not been received.
12319 * 0b1..A valid initial character has been received.
12320 */
12321#define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
12322#define UART_IS7816_BWT_MASK (0x20U)
12323#define UART_IS7816_BWT_SHIFT (5U)
12324/*! BWT - Block Wait Timer Interrupt
12325 * 0b0..Block wait time (BWT) has not been violated.
12326 * 0b1..Block wait time (BWT) has been violated.
12327 */
12328#define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
12329#define UART_IS7816_CWT_MASK (0x40U)
12330#define UART_IS7816_CWT_SHIFT (6U)
12331/*! CWT - Character Wait Timer Interrupt
12332 * 0b0..Character wait time (CWT) has not been violated.
12333 * 0b1..Character wait time (CWT) has been violated.
12334 */
12335#define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
12336#define UART_IS7816_WT_MASK (0x80U)
12337#define UART_IS7816_WT_SHIFT (7U)
12338/*! WT - Wait Timer Interrupt
12339 * 0b0..Wait time (WT) has not been violated.
12340 * 0b1..Wait time (WT) has been violated.
12341 */
12342#define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
12343/*! @} */
12344
12345/*! @name WP7816 - UART 7816 Wait Parameter Register */
12346/*! @{ */
12347#define UART_WP7816_WTX_MASK (0xFFU)
12348#define UART_WP7816_WTX_SHIFT (0U)
12349#define UART_WP7816_WTX(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
12350/*! @} */
12351
12352/*! @name WN7816 - UART 7816 Wait N Register */
12353/*! @{ */
12354#define UART_WN7816_GTN_MASK (0xFFU)
12355#define UART_WN7816_GTN_SHIFT (0U)
12356#define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
12357/*! @} */
12358
12359/*! @name WF7816 - UART 7816 Wait FD Register */
12360/*! @{ */
12361#define UART_WF7816_GTFD_MASK (0xFFU)
12362#define UART_WF7816_GTFD_SHIFT (0U)
12363#define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
12364/*! @} */
12365
12366/*! @name ET7816 - UART 7816 Error Threshold Register */
12367/*! @{ */
12368#define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
12369#define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
12370#define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
12371#define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
12372#define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
12373/*! TXTHRESHOLD - Transmit NACK Threshold
12374 * 0b0000..TXT asserts on the first NACK that is received.
12375 * 0b0001..TXT asserts on the second NACK that is received.
12376 */
12377#define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
12378/*! @} */
12379
12380/*! @name TL7816 - UART 7816 Transmit Length Register */
12381/*! @{ */
12382#define UART_TL7816_TLEN_MASK (0xFFU)
12383#define UART_TL7816_TLEN_SHIFT (0U)
12384#define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
12385/*! @} */
12386
12387/*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
12388/*! @{ */
12389#define UART_AP7816A_T0_ADTI_H_MASK (0xFFU)
12390#define UART_AP7816A_T0_ADTI_H_SHIFT (0U)
12391#define UART_AP7816A_T0_ADTI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
12392/*! @} */
12393
12394/*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
12395/*! @{ */
12396#define UART_AP7816B_T0_ADTI_L_MASK (0xFFU)
12397#define UART_AP7816B_T0_ADTI_L_SHIFT (0U)
12398#define UART_AP7816B_T0_ADTI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
12399/*! @} */
12400
12401/*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
12402/*! @{ */
12403#define UART_WP7816A_T0_WI_H_MASK (0xFFU)
12404#define UART_WP7816A_T0_WI_H_SHIFT (0U)
12405#define UART_WP7816A_T0_WI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
12406/*! @} */
12407
12408/*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
12409/*! @{ */
12410#define UART_WP7816B_T0_WI_L_MASK (0xFFU)
12411#define UART_WP7816B_T0_WI_L_SHIFT (0U)
12412#define UART_WP7816B_T0_WI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
12413/*! @} */
12414
12415/*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
12416/*! @{ */
12417#define UART_WP7816A_T1_BWI_H_MASK (0xFFU)
12418#define UART_WP7816A_T1_BWI_H_SHIFT (0U)
12419#define UART_WP7816A_T1_BWI_H(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
12420/*! @} */
12421
12422/*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
12423/*! @{ */
12424#define UART_WP7816B_T1_BWI_L_MASK (0xFFU)
12425#define UART_WP7816B_T1_BWI_L_SHIFT (0U)
12426#define UART_WP7816B_T1_BWI_L(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
12427/*! @} */
12428
12429/*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
12430/*! @{ */
12431#define UART_WGP7816_T1_BGI_MASK (0xFU)
12432#define UART_WGP7816_T1_BGI_SHIFT (0U)
12433#define UART_WGP7816_T1_BGI(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
12434#define UART_WGP7816_T1_CWI1_MASK (0xF0U)
12435#define UART_WGP7816_T1_CWI1_SHIFT (4U)
12436#define UART_WGP7816_T1_CWI1(x) (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
12437/*! @} */
12438
12439/*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
12440/*! @{ */
12441#define UART_WP7816C_T1_CWI2_MASK (0x1FU)
12442#define UART_WP7816C_T1_CWI2_SHIFT (0U)
12443#define UART_WP7816C_T1_CWI2(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
12444/*! @} */
12445
12446
12447/*!
12448 * @}
12449 */ /* end of group UART_Register_Masks */
12450
12451
12452/* UART - Peripheral instance base addresses */
12453/** Peripheral UART0 base address */
12454#define UART0_BASE (0x4006A000u)
12455/** Peripheral UART0 base pointer */
12456#define UART0 ((UART_Type *)UART0_BASE)
12457/** Peripheral UART1 base address */
12458#define UART1_BASE (0x4006B000u)
12459/** Peripheral UART1 base pointer */
12460#define UART1 ((UART_Type *)UART1_BASE)
12461/** Peripheral UART2 base address */
12462#define UART2_BASE (0x4006C000u)
12463/** Peripheral UART2 base pointer */
12464#define UART2 ((UART_Type *)UART2_BASE)
12465/** Array initializer of UART peripheral base addresses */
12466#define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE }
12467/** Array initializer of UART peripheral base pointers */
12468#define UART_BASE_PTRS { UART0, UART1, UART2 }
12469/** Interrupt vectors for the UART peripheral type */
12470#define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn }
12471#define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn }
12472
12473/*!
12474 * @}
12475 */ /* end of group UART_Peripheral_Access_Layer */
12476
12477
12478/* ----------------------------------------------------------------------------
12479 -- VREF Peripheral Access Layer
12480 ---------------------------------------------------------------------------- */
12481
12482/*!
12483 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
12484 * @{
12485 */
12486
12487/** VREF - Register Layout Typedef */
12488typedef struct {
12489 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
12490 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
12491} VREF_Type;
12492
12493/* ----------------------------------------------------------------------------
12494 -- VREF Register Masks
12495 ---------------------------------------------------------------------------- */
12496
12497/*!
12498 * @addtogroup VREF_Register_Masks VREF Register Masks
12499 * @{
12500 */
12501
12502/*! @name TRM - VREF Trim Register */
12503/*! @{ */
12504#define VREF_TRM_TRIM_MASK (0x3FU)
12505#define VREF_TRM_TRIM_SHIFT (0U)
12506/*! TRIM - Trim bits
12507 * 0b000000..Min
12508 * 0b111111..Max
12509 */
12510#define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
12511#define VREF_TRM_CHOPEN_MASK (0x40U)
12512#define VREF_TRM_CHOPEN_SHIFT (6U)
12513/*! CHOPEN - Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized.
12514 * 0b0..Chop oscillator is disabled.
12515 * 0b1..Chop oscillator is enabled.
12516 */
12517#define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
12518/*! @} */
12519
12520/*! @name SC - VREF Status and Control Register */
12521/*! @{ */
12522#define VREF_SC_MODE_LV_MASK (0x3U)
12523#define VREF_SC_MODE_LV_SHIFT (0U)
12524/*! MODE_LV - Buffer Mode selection
12525 * 0b00..Bandgap on only, for stabilization and startup
12526 * 0b01..High power buffer mode enabled
12527 * 0b10..Low-power buffer mode enabled
12528 * 0b11..Reserved
12529 */
12530#define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
12531#define VREF_SC_VREFST_MASK (0x4U)
12532#define VREF_SC_VREFST_SHIFT (2U)
12533/*! VREFST - Internal Voltage Reference stable
12534 * 0b0..The module is disabled or not stable.
12535 * 0b1..The module is stable.
12536 */
12537#define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
12538#define VREF_SC_ICOMPEN_MASK (0x20U)
12539#define VREF_SC_ICOMPEN_SHIFT (5U)
12540/*! ICOMPEN - Second order curvature compensation enable
12541 * 0b0..Disabled
12542 * 0b1..Enabled
12543 */
12544#define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
12545#define VREF_SC_REGEN_MASK (0x40U)
12546#define VREF_SC_REGEN_SHIFT (6U)
12547/*! REGEN - Regulator enable
12548 * 0b0..Internal 1.75 V regulator is disabled.
12549 * 0b1..Internal 1.75 V regulator is enabled.
12550 */
12551#define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
12552#define VREF_SC_VREFEN_MASK (0x80U)
12553#define VREF_SC_VREFEN_SHIFT (7U)
12554/*! VREFEN - Internal Voltage Reference enable
12555 * 0b0..The module is disabled.
12556 * 0b1..The module is enabled.
12557 */
12558#define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
12559/*! @} */
12560
12561
12562/*!
12563 * @}
12564 */ /* end of group VREF_Register_Masks */
12565
12566
12567/* VREF - Peripheral instance base addresses */
12568/** Peripheral VREF base address */
12569#define VREF_BASE (0x40074000u)
12570/** Peripheral VREF base pointer */
12571#define VREF ((VREF_Type *)VREF_BASE)
12572/** Array initializer of VREF peripheral base addresses */
12573#define VREF_BASE_ADDRS { VREF_BASE }
12574/** Array initializer of VREF peripheral base pointers */
12575#define VREF_BASE_PTRS { VREF }
12576
12577/*!
12578 * @}
12579 */ /* end of group VREF_Peripheral_Access_Layer */
12580
12581
12582/* ----------------------------------------------------------------------------
12583 -- WDOG Peripheral Access Layer
12584 ---------------------------------------------------------------------------- */
12585
12586/*!
12587 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
12588 * @{
12589 */
12590
12591/** WDOG - Register Layout Typedef */
12592typedef struct {
12593 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
12594 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
12595 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
12596 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
12597 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
12598 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
12599 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
12600 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
12601 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
12602 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
12603 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
12604 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
12605} WDOG_Type;
12606
12607/* ----------------------------------------------------------------------------
12608 -- WDOG Register Masks
12609 ---------------------------------------------------------------------------- */
12610
12611/*!
12612 * @addtogroup WDOG_Register_Masks WDOG Register Masks
12613 * @{
12614 */
12615
12616/*! @name STCTRLH - Watchdog Status and Control Register High */
12617/*! @{ */
12618#define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
12619#define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
12620/*! WDOGEN
12621 * 0b0..WDOG is disabled.
12622 * 0b1..WDOG is enabled.
12623 */
12624#define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
12625#define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
12626#define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
12627/*! CLKSRC
12628 * 0b0..WDOG clock sourced from LPO .
12629 * 0b1..WDOG clock sourced from alternate clock source.
12630 */
12631#define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
12632#define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
12633#define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
12634/*! IRQRSTEN
12635 * 0b0..WDOG time-out generates reset only.
12636 * 0b1..WDOG time-out initially generates an interrupt. After WCT, it generates a reset.
12637 */
12638#define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
12639#define WDOG_STCTRLH_WINEN_MASK (0x8U)
12640#define WDOG_STCTRLH_WINEN_SHIFT (3U)
12641/*! WINEN
12642 * 0b0..Windowing mode is disabled.
12643 * 0b1..Windowing mode is enabled.
12644 */
12645#define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
12646#define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
12647#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
12648/*! ALLOWUPDATE
12649 * 0b0..No further updates allowed to WDOG write-once registers.
12650 * 0b1..WDOG write-once registers can be unlocked for updating.
12651 */
12652#define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
12653#define WDOG_STCTRLH_DBGEN_MASK (0x20U)
12654#define WDOG_STCTRLH_DBGEN_SHIFT (5U)
12655/*! DBGEN
12656 * 0b0..WDOG is disabled in CPU Debug mode.
12657 * 0b1..WDOG is enabled in CPU Debug mode.
12658 */
12659#define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
12660#define WDOG_STCTRLH_STOPEN_MASK (0x40U)
12661#define WDOG_STCTRLH_STOPEN_SHIFT (6U)
12662/*! STOPEN
12663 * 0b0..WDOG is disabled in CPU Stop mode.
12664 * 0b1..WDOG is enabled in CPU Stop mode.
12665 */
12666#define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
12667#define WDOG_STCTRLH_WAITEN_MASK (0x80U)
12668#define WDOG_STCTRLH_WAITEN_SHIFT (7U)
12669/*! WAITEN
12670 * 0b0..WDOG is disabled in CPU Wait mode.
12671 * 0b1..WDOG is enabled in CPU Wait mode.
12672 */
12673#define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
12674#define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
12675#define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
12676#define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
12677#define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
12678#define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
12679/*! TESTSEL
12680 * 0b0..Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test.
12681 * 0b1..Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing.
12682 */
12683#define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
12684#define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
12685#define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
12686/*! BYTESEL
12687 * 0b00..Byte 0 selected
12688 * 0b01..Byte 1 selected
12689 * 0b10..Byte 2 selected
12690 * 0b11..Byte 3 selected
12691 */
12692#define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
12693#define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
12694#define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
12695/*! DISTESTWDOG
12696 * 0b0..WDOG functional test mode is not disabled.
12697 * 0b1..WDOG functional test mode is disabled permanently until reset.
12698 */
12699#define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
12700/*! @} */
12701
12702/*! @name STCTRLL - Watchdog Status and Control Register Low */
12703/*! @{ */
12704#define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
12705#define WDOG_STCTRLL_INTFLG_SHIFT (15U)
12706#define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
12707/*! @} */
12708
12709/*! @name TOVALH - Watchdog Time-out Value Register High */
12710/*! @{ */
12711#define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
12712#define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
12713#define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
12714/*! @} */
12715
12716/*! @name TOVALL - Watchdog Time-out Value Register Low */
12717/*! @{ */
12718#define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
12719#define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
12720#define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
12721/*! @} */
12722
12723/*! @name WINH - Watchdog Window Register High */
12724/*! @{ */
12725#define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
12726#define WDOG_WINH_WINHIGH_SHIFT (0U)
12727#define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
12728/*! @} */
12729
12730/*! @name WINL - Watchdog Window Register Low */
12731/*! @{ */
12732#define WDOG_WINL_WINLOW_MASK (0xFFFFU)
12733#define WDOG_WINL_WINLOW_SHIFT (0U)
12734#define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
12735/*! @} */
12736
12737/*! @name REFRESH - Watchdog Refresh register */
12738/*! @{ */
12739#define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
12740#define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
12741#define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
12742/*! @} */
12743
12744/*! @name UNLOCK - Watchdog Unlock register */
12745/*! @{ */
12746#define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
12747#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
12748#define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
12749/*! @} */
12750
12751/*! @name TMROUTH - Watchdog Timer Output Register High */
12752/*! @{ */
12753#define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
12754#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
12755#define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
12756/*! @} */
12757
12758/*! @name TMROUTL - Watchdog Timer Output Register Low */
12759/*! @{ */
12760#define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
12761#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
12762#define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
12763/*! @} */
12764
12765/*! @name RSTCNT - Watchdog Reset Count register */
12766/*! @{ */
12767#define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
12768#define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
12769#define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
12770/*! @} */
12771
12772/*! @name PRESC - Watchdog Prescaler register */
12773/*! @{ */
12774#define WDOG_PRESC_PRESCVAL_MASK (0x700U)
12775#define WDOG_PRESC_PRESCVAL_SHIFT (8U)
12776#define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
12777/*! @} */
12778
12779
12780/*!
12781 * @}
12782 */ /* end of group WDOG_Register_Masks */
12783
12784
12785/* WDOG - Peripheral instance base addresses */
12786/** Peripheral WDOG base address */
12787#define WDOG_BASE (0x40052000u)
12788/** Peripheral WDOG base pointer */
12789#define WDOG ((WDOG_Type *)WDOG_BASE)
12790/** Array initializer of WDOG peripheral base addresses */
12791#define WDOG_BASE_ADDRS { WDOG_BASE }
12792/** Array initializer of WDOG peripheral base pointers */
12793#define WDOG_BASE_PTRS { WDOG }
12794/** Interrupt vectors for the WDOG peripheral type */
12795#define WDOG_IRQS { WDOG_EWM_IRQn }
12796
12797/*!
12798 * @}
12799 */ /* end of group WDOG_Peripheral_Access_Layer */
12800
12801
12802/*
12803** End of section using anonymous unions
12804*/
12805
12806#if defined(__ARMCC_VERSION)
12807 #if (__ARMCC_VERSION >= 6010050)
12808 #pragma clang diagnostic pop
12809 #else
12810 #pragma pop
12811 #endif
12812#elif defined(__CWCC__)
12813 #pragma pop
12814#elif defined(__GNUC__)
12815 /* leave anonymous unions enabled */
12816#elif defined(__IAR_SYSTEMS_ICC__)
12817 #pragma language=default
12818#else
12819 #error Not supported compiler type
12820#endif
12821
12822/*!
12823 * @}
12824 */ /* end of group Peripheral_access_layer */
12825
12826
12827/* ----------------------------------------------------------------------------
12828 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
12829 ---------------------------------------------------------------------------- */
12830
12831/*!
12832 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
12833 * @{
12834 */
12835
12836#if defined(__ARMCC_VERSION)
12837 #if (__ARMCC_VERSION >= 6010050)
12838 #pragma clang system_header
12839 #endif
12840#elif defined(__IAR_SYSTEMS_ICC__)
12841 #pragma system_include
12842#endif
12843
12844/**
12845 * @brief Mask and left-shift a bit field value for use in a register bit range.
12846 * @param field Name of the register bit field.
12847 * @param value Value of the bit field.
12848 * @return Masked and shifted value.
12849 */
12850#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
12851/**
12852 * @brief Mask and right-shift a register value to extract a bit field value.
12853 * @param field Name of the register bit field.
12854 * @param value Value of the register.
12855 * @return Masked and shifted bit field value.
12856 */
12857#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
12858
12859/*!
12860 * @}
12861 */ /* end of group Bit_Field_Generic_Macros */
12862
12863
12864/* ----------------------------------------------------------------------------
12865 -- SDK Compatibility
12866 ---------------------------------------------------------------------------- */
12867
12868/*!
12869 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
12870 * @{
12871 */
12872
12873#define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
12874#define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
12875#define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
12876#define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
12877#define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
12878#define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
12879#define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
12880#define DSPI0 SPI0
12881#define DSPI1 SPI1
12882#define PTA_BASE GPIOA_BASE
12883#define PTA GPIOA
12884#define PTB_BASE GPIOB_BASE
12885#define PTB GPIOB
12886#define PTC_BASE GPIOC_BASE
12887#define PTC GPIOC
12888#define PTD_BASE GPIOD_BASE
12889#define PTD GPIOD
12890#define PTE_BASE GPIOE_BASE
12891#define PTE GPIOE
12892#define DMAMUX0 DMAMUX
12893#define Watchdog_IRQn WDOG_EWM_IRQn
12894#define Watchdog_IRQHandler WDOG_EWM_IRQHandler
12895#define LPTimer_IRQn LPTMR0_IRQn
12896#define LPTimer_IRQHandler LPTMR0_IRQHandler
12897#define LLW_IRQn LLWU_IRQn
12898#define LLW_IRQHandler LLWU_IRQHandler
12899
12900/*!
12901 * @}
12902 */ /* end of group SDK_Compatibility_Symbols */
12903
12904
12905#endif /* _MKV31F25612_H_ */
12906
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