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1/**************************************************************************//**
2 * @file ADUCM362.h
3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
4 * Device ADUCM362
5 * @version V3.10
6 * @date 23. November 2012
7 *
8 * @note
9 *
10 ******************************************************************************/
11/* Copyright (c) 2012 ARM LIMITED
12
13 All rights reserved.
14 Redistribution and use in source and binary forms, with or without
15 modification, are permitted provided that the following conditions are met:
16 - Redistributions of source code must retain the above copyright
17 notice, this list of conditions and the following disclaimer.
18 - Redistributions in binary form must reproduce the above copyright
19 notice, this list of conditions and the following disclaimer in the
20 documentation and/or other materials provided with the distribution.
21 - Neither the name of ARM nor the names of its contributors may be used
22 to endorse or promote products derived from this software without
23 specific prior written permission.
24 *
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 POSSIBILITY OF SUCH DAMAGE.
36
37 Portions Copyright (c) 2017-2019 Analog Devices, Inc.
38 ---------------------------------------------------------------------------*/
39
40/** @addtogroup CMSIS
41 * @{
42 */
43
44/** @addtogroup ADUCM362
45 * @{
46 */
47
48#ifndef __ADUCM362_H__
49#define __ADUCM362_H__
50
51#ifndef __NO_MMR_STRUCTS__
52// The new style CMSIS structure definitions for MMRs clash with
53// the old style defs. If the old style are required for compilation
54// then set __NO_MMR_STRUCTS__ to 0x1
55#define __NO_MMR_STRUCTS__ 0x0
56#endif
57
58#ifdef __cplusplus
59extern "C" {
60#endif
61
62
63
64/********************************************
65** Start of section using anonymous unions **
66*********************************************/
67
68#if defined(__ARMCC_VERSION)
69 #pragma push
70 #pragma anon_unions
71#elif defined(__CWCC__)
72 #pragma push
73 #pragma cpp_extensions on
74#elif defined(__GNUC__)
75 /* anonymous unions are enabled by default */
76#elif defined(__IAR_SYSTEMS_ICC__)
77 #pragma language=extended
78#else
79 #error Not supported compiler type
80#endif
81
82
83 /* Interrupt Number Definition */
84
85typedef enum {
86// ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
87 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
88 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
89 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
90 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
91 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
92 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
93 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
94 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
95 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
96 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
97// -------------------------- ADUCM362 Specific Interrupt Numbers ------------------------------
98 WUT_IRQn = 0, /*!< 0 WUT */
99 EINT0_IRQn = 1, /*!< 1 EINT0 */
100 EINT1_IRQn = 2, /*!< 2 EINT1 */
101 EINT2_IRQn = 3, /*!< 3 EINT2 */
102 EINT3_IRQn = 4, /*!< 4 EINT3 */
103 EINT4_IRQn = 5, /*!< 5 EINT4 */
104 EINT5_IRQn = 6, /*!< 6 EINT5 */
105 EINT6_IRQn = 7, /*!< 7 EINT6 */
106 EINT7_IRQn = 8, /*!< 8 EINT7 */
107 WDT_IRQn = 9, /*!< 9 WDT */
108 TIMER0_IRQn = 11, /*!< 11 TIMER0 */
109 TIMER1_IRQn = 12, /*!< 12 TIMER1 */
110 ADC0_IRQn = 13, /*!< 13 ADC0 */
111 ADC1_IRQn = 14, /*!< 14 ADC1 */
112 SINC2_IRQn = 15, /*!< 15 SINC2 */
113 FLASH_IRQn = 16, /*!< 16 FLASH */
114 UART_IRQn = 17, /*!< 17 UART */
115 SPI0_IRQn = 18, /*!< 18 SPI0 */
116 SPI1_IRQn = 19, /*!< 19 SPI1 */
117 I2CS_IRQn = 20, /*!< 20 I2CS */
118 I2CM_IRQn = 21, /*!< 21 I2CM */
119 DMA_ERR_IRQn = 22, /*!< 22 DMA_ERR */
120 DMA_SPI1_TX_IRQn = 23, /*!< 23 DMA_SPI1_TX */
121 DMA_SPI1_RX_IRQn = 24, /*!< 24 DMA_SPI1_RX */
122 DMA_UART_TX_IRQn = 25, /*!< 25 DMA_UART_TX */
123 DMA_UART_RX_IRQn = 26, /*!< 26 DMA_UART_RX */
124 DMA_I2CS_TX_IRQn = 27, /*!< 27 DMA_I2CS_TX */
125 DMA_I2CS_RX_IRQn = 28, /*!< 28 DMA_I2CS_RX */
126 DMA_I2CM_TX_IRQn = 29, /*!< 29 DMA_I2CM_TX */
127 DMA_I2CM_RX_IRQn = 30, /*!< 30 DMA_I2CM_RX */
128 DMA_DAC_IRQn = 31, /*!< 31 DMA_DAC */
129 DMA_ADC0_IRQn = 32, /*!< 32 DMA_ADC0 */
130 DMA_ADC1_IRQn = 33, /*!< 33 DMA_ADC1 */
131 DMA_SINC2_IRQn = 34, /*!< 34 DMA_SINC2 */
132 DMA_SPI0_TX_IRQn = 35, /*!< 35 DMA_SPI0_TX */
133 DMA_SPI0_RX_IRQn = 36, /*!< 36 DMA_SPI0_RX */
134 DMA_UART1_TX_IRQn = 37, /*!< 37 DMA_UART1_TX */
135 DMA_UART1_RX_IRQn = 38, /*!< 38 DMA_UART1_RX */
136 DMA_UART2_TX_IRQn = 39, /*!< 39 DMA_UART2_TX */
137 DMA_UART2_RX_IRQn = 40, /*!< 40 DMA_UART2_RX */
138 PWM_TRIP_IRQn = 41, /*!< 35 PWM_TRIP */
139 PWM_PAIR0_IRQn = 42, /*!< 36 PWM_PAIR0 */
140 PWM_PAIR1_IRQn = 43, /*!< 37 PWM_PAIR1 */
141 PWM_PAIR2_IRQn = 44, /*!< 38 PWM_PAIR2 */
142 UART1_IRQn = 47, /*!< 47 UART1 */
143 UART2_IRQn = 48, /*!< 48 UART2 */
144} IRQn_Type;
145
146
147/** @addtogroup Configuration_of_CMSIS
148 * @{
149 */
150
151/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
152
153#define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision r2p0 */
154#define __MPU_PRESENT 0 /*!< MPU present or not */
155#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
156#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
157/** @} */ /* End of group Configuration_of_CMSIS */
158
159#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
160#include "system_ADuCM362.h" /*!< ADUCM362 System */
161
162/** @addtogroup Device_Peripheral_Registers
163 * @{
164 */
165
166
167
168/* ADCCON[ADCEN] - Enable Bit */
169#define ADCCON_ADCEN_MSK (0x1 << 19 )
170#define ADCCON_ADCEN (0x1 << 19 )
171#define ADCCON_ADCEN_DIS (0x0 << 19 ) /* DIS */
172#define ADCCON_ADCEN_EN (0x1 << 19 ) /* EN */
173
174/* ADCCON[ADCCODE] - ADC Output Coding bits */
175#define ADCCON_ADCCODE_MSK (0x1 << 18 )
176#define ADCCON_ADCCODE (0x1 << 18 )
177#define ADCCON_ADCCODE_INT (0x0 << 18 ) /* INT */
178#define ADCCON_ADCCODE_UINT (0x1 << 18 ) /* UINT */
179
180/* ADCCON[BUFPOWN] - Negative buffer power down */
181#define ADCCON_BUFPOWN_MSK (0x1 << 17 )
182#define ADCCON_BUFPOWN (0x1 << 17 )
183#define ADCCON_BUFPOWN_DIS (0x0 << 17 ) /* Disable powerdown - Negative buffer is enabled */
184#define ADCCON_BUFPOWN_EN (0x1 << 17 ) /* Enable powerdown - Negative buffer is disabled */
185
186/* ADCCON[BUFPOWP] - Positive buffer power down */
187#define ADCCON_BUFPOWP_MSK (0x1 << 16 )
188#define ADCCON_BUFPOWP (0x1 << 16 )
189#define ADCCON_BUFPOWP_DIS (0x0 << 16 ) /* Disable powerdown - Positive buffer is enabled */
190#define ADCCON_BUFPOWP_EN (0x1 << 16 ) /* Enable powerdown - Positive buffer is disabled */
191
192/* ADCCON[BUFBYPP] - Positive buffer bypass */
193#define ADCCON_BUFBYPP_MSK (0x1 << 15 )
194#define ADCCON_BUFBYPP (0x1 << 15 )
195#define ADCCON_BUFBYPP_DIS (0x0 << 15 ) /* DIS */
196#define ADCCON_BUFBYPP_EN (0x1 << 15 ) /* EN */
197
198/* ADCCON[BUFBYPN] - Negative buffer bypass */
199#define ADCCON_BUFBYPN_MSK (0x1 << 14 )
200#define ADCCON_BUFBYPN (0x1 << 14 )
201#define ADCCON_BUFBYPN_DIS (0x0 << 14 ) /* DIS */
202#define ADCCON_BUFBYPN_EN (0x1 << 14 ) /* EN */
203
204/* ADCCON[ADCREF] - Reference selection */
205#define ADCCON_ADCREF_MSK (0x3 << 12 )
206#define ADCCON_ADCREF_INTREF (0x0 << 12 ) /* INTREF */
207#define ADCCON_ADCREF_EXTREF (0x1 << 12 ) /* EXTREF */
208#define ADCCON_ADCREF_EXTREF2 (0x2 << 12 ) /* EXTREF2 */
209#define ADCCON_ADCREF_AVDDREF (0x3 << 12 ) /* AVDDREF */
210
211/* ADCCON[ADCDIAG] - Diagnostic Current bits bits */
212#define ADCCON_ADCDIAG_MSK (0x3 << 10 )
213#define ADCCON_ADCDIAG_DIAG_OFF (0x0 << 10 ) /* DIAG_OFF */
214#define ADCCON_ADCDIAG_DIAG_POS (0x1 << 10 ) /* DIAG_POS */
215#define ADCCON_ADCDIAG_DIAG_NEG (0x2 << 10 ) /* DIAG_NEG */
216#define ADCCON_ADCDIAG_DIAG_ALL (0x3 << 10 ) /* DIAG_ALL */
217
218/* ADCCON[ADCCP] - AIN+ bits */
219#define ADCCON_ADCCP_MSK (0x1F << 5 )
220#define ADCCON_ADCCP_AIN0 (0x0 << 5 ) /* AIN0 */
221#define ADCCON_ADCCP_AIN1 (0x1 << 5 ) /* AIN1 */
222#define ADCCON_ADCCP_AIN2 (0x2 << 5 ) /* AIN2 */
223#define ADCCON_ADCCP_AIN3 (0x3 << 5 ) /* AIN3 */
224#define ADCCON_ADCCP_AIN4 (0x4 << 5 ) /* AIN4 */
225#define ADCCON_ADCCP_AIN5 (0x5 << 5 ) /* AIN5 */
226#define ADCCON_ADCCP_AIN6 (0x6 << 5 ) /* AIN6 */
227#define ADCCON_ADCCP_AIN7 (0x7 << 5 ) /* AIN7 */
228#define ADCCON_ADCCP_AIN8 (0x8 << 5 ) /* AIN8 */
229#define ADCCON_ADCCP_AIN9 (0x9 << 5 ) /* AIN9 */
230#define ADCCON_ADCCP_AIN10 (0xA << 5 ) /* AIN10 */
231#define ADCCON_ADCCP_AIN11 (0xB << 5 ) /* AIN11 */
232#define ADCCON_ADCCP_DAC (0xC << 5 ) /* DAC */
233#define ADCCON_ADCCP_AVDD4 (0xD << 5 ) /* AVDD4 */
234#define ADCCON_ADCCP_IOVDD4 (0xE << 5 ) /* IOVDD4 */
235#define ADCCON_ADCCP_AGND (0xF << 5 ) /* AGND */
236#define ADCCON_ADCCP_TEMP (0x10 << 5 ) /* TEMP */
237
238/* ADCCON[ADCCN] - AIN- bits */
239#define ADCCON_ADCCN_MSK (0x1F << 0 )
240#define ADCCON_ADCCN_AIN0 (0x0 << 0 ) /* AIN0 */
241#define ADCCON_ADCCN_AIN1 (0x1 << 0 ) /* AIN1 */
242#define ADCCON_ADCCN_AIN2 (0x2 << 0 ) /* AIN2 */
243#define ADCCON_ADCCN_AIN3 (0x3 << 0 ) /* AIN3 */
244#define ADCCON_ADCCN_AIN4 (0x4 << 0 ) /* AIN4 */
245#define ADCCON_ADCCN_AIN5 (0x5 << 0 ) /* AIN5 */
246#define ADCCON_ADCCN_AIN6 (0x6 << 0 ) /* AIN6 */
247#define ADCCON_ADCCN_AIN7 (0x7 << 0 ) /* AIN7 */
248#define ADCCON_ADCCN_AIN8 (0x8 << 0 ) /* AIN8 */
249#define ADCCON_ADCCN_AIN9 (0x9 << 0 ) /* AIN9 */
250#define ADCCON_ADCCN_AIN10 (0xA << 0 ) /* AIN10 */
251#define ADCCON_ADCCN_AIN11 (0xB << 0 ) /* AIN11 */
252#define ADCCON_ADCCN_DAC (0xC << 0 ) /* DAC */
253#define ADCCON_ADCCN_AGND (0xF << 0 ) /* AGND */
254#define ADCCON_ADCCN_TEMP (0x11 << 0 ) /* TEMP */
255
256/* ADCMDE[PGA] - PGA Gain Select bit */
257#define ADCMDE_PGA_MSK (0xF << 4 )
258#define ADCMDE_PGA_G1 (0x0 << 4 ) /* G1 */
259#define ADCMDE_PGA_G2 (0x1 << 4 ) /* G2 */
260#define ADCMDE_PGA_G4 (0x2 << 4 ) /* G4 */
261#define ADCMDE_PGA_G8 (0x3 << 4 ) /* G8 */
262#define ADCMDE_PGA_G16 (0x4 << 4 ) /* G16 */
263#define ADCMDE_PGA_G32 (0x5 << 4 ) /* G32 */
264#define ADCMDE_PGA_G64 (0x6 << 4 ) /* G64 */
265#define ADCMDE_PGA_G128 (0x7 << 4 ) /* G128 */
266
267/* ADCMDE[ADCMOD2] - ADC modulator gain of 2 control bits */
268#define ADCMDE_ADCMOD2_MSK (0x1 << 3 )
269#define ADCMDE_ADCMOD2 (0x1 << 3 )
270#define ADCMDE_ADCMOD2_MOD2OFF (0x0 << 3 ) /* MOD2OFF */
271#define ADCMDE_ADCMOD2_MOD2ON (0x1 << 3 ) /* MOD2ON */
272
273/* ADCMDE[ADCMD] - ADC Mode bits */
274#define ADCMDE_ADCMD_MSK (0x7 << 0 )
275#define ADCMDE_ADCMD_OFF (0x0 << 0 ) /* OFF */
276#define ADCMDE_ADCMD_CONT (0x1 << 0 ) /* CONT */
277#define ADCMDE_ADCMD_SINGLE (0x2 << 0 ) /* SINGLE */
278#define ADCMDE_ADCMD_IDLE (0x3 << 0 ) /* IDLE */
279#define ADCMDE_ADCMD_INTOCAL (0x4 << 0 ) /* INTOCAL */
280#define ADCMDE_ADCMD_INTGCAL (0x5 << 0 ) /* INTGCAL */
281#define ADCMDE_ADCMD_SYSOCAL (0x6 << 0 ) /* SYSOCAL */
282#define ADCMDE_ADCMD_SYSGCAL (0x7 << 0 ) /* SYSGCAL */
283
284/* ADCMSKI[ATHEX] - ADC Accumulator Comparator Threshold status bit mask */
285#define ADCMSKI_ATHEX_MSK (0x1 << 3 )
286#define ADCMSKI_ATHEX (0x1 << 3 )
287#define ADCMSKI_ATHEX_DIS (0x0 << 3 ) /* DIS */
288#define ADCMSKI_ATHEX_EN (0x1 << 3 ) /* EN */
289
290/* ADCMSKI[THEX] - ADC comparator threshold mask */
291#define ADCMSKI_THEX_MSK (0x1 << 2 )
292#define ADCMSKI_THEX (0x1 << 2 )
293#define ADCMSKI_THEX_DIS (0x0 << 2 ) /* DIS */
294#define ADCMSKI_THEX_EN (0x1 << 2 ) /* EN */
295
296/* ADCMSKI[OVR] - ADC overrange bit mask. */
297#define ADCMSKI_OVR_MSK (0x1 << 1 )
298#define ADCMSKI_OVR (0x1 << 1 )
299#define ADCMSKI_OVR_DIS (0x0 << 1 ) /* DIS */
300#define ADCMSKI_OVR_EN (0x1 << 1 ) /* EN */
301
302/* ADCMSKI[RDY] - valid conversion result mask */
303#define ADCMSKI_RDY_MSK (0x1 << 0 )
304#define ADCMSKI_RDY (0x1 << 0 )
305#define ADCMSKI_RDY_DIS (0x0 << 0 ) /* DIS */
306#define ADCMSKI_RDY_EN (0x1 << 0 ) /* EN */
307
308/* ADCFLT[CHOP] - Enables System-Chopping bits */
309#define ADCFLT_CHOP_MSK (0x1 << 15 )
310#define ADCFLT_CHOP (0x1 << 15 )
311#define ADCFLT_CHOP_OFF (0x0 << 15 ) /* OFF */
312#define ADCFLT_CHOP_ON (0x1 << 15 ) /* ON */
313
314/* ADCFLT[RAVG2] - Enables a running Average-By-2 bits */
315#define ADCFLT_RAVG2_MSK (0x1 << 14 )
316#define ADCFLT_RAVG2 (0x1 << 14 )
317#define ADCFLT_RAVG2_OFF (0x0 << 14 ) /* OFF */
318#define ADCFLT_RAVG2_ON (0x1 << 14 ) /* ON */
319
320/* ADCFLT[SINC4EN] - Enable the Sinc4 filter instead of Sinc3 filter. */
321#define ADCFLT_SINC4EN_MSK (0x1 << 12 )
322#define ADCFLT_SINC4EN (0x1 << 12 )
323#define ADCFLT_SINC4EN_DIS (0x0 << 12 ) /* DIS */
324#define ADCFLT_SINC4EN_EN (0x1 << 12 ) /* EN */
325
326/* ADCFLT[AF] - Averaging filter */
327#define ADCFLT_AF_MSK (0xF << 8 )
328
329/* ADCFLT[NOTCH2] - Inserts a notch at FNOTCH2 */
330#define ADCFLT_NOTCH2_MSK (0x1 << 7 )
331#define ADCFLT_NOTCH2 (0x1 << 7 )
332#define ADCFLT_NOTCH2_DIS (0x0 << 7 ) /* DIS */
333#define ADCFLT_NOTCH2_EN (0x1 << 7 ) /* EN */
334
335/* ADCFLT[SF] - SINC Filter value */
336#define ADCFLT_SF_MSK (0x7F << 0 )
337
338/* TCON[EVENTEN] - Enable time capture of an event */
339#define TCON_EVENTEN_MSK (0x1 << 12 )
340#define TCON_EVENTEN (0x1 << 12 )
341#define TCON_EVENTEN_DIS (0x0 << 12 ) /* DIS */
342#define TCON_EVENTEN_EN (0x1 << 12 ) /* EN */
343
344/* TCON[EVENT] - Event Select, selects 1 of the available events. */
345#define TCON_EVENT_MSK (0xF << 8 )
346
347/* TCON[RLD] - Timer reload on write to clear register */
348#define TCON_RLD_MSK (0x1 << 7 )
349#define TCON_RLD (0x1 << 7 )
350#define TCON_RLD_DIS (0x0 << 7 ) /* DIS */
351#define TCON_RLD_EN (0x1 << 7 ) /* EN */
352
353/* TCON[CLK] - Clock Select */
354#define TCON_CLK_MSK (0x3 << 5 )
355#define TCON_CLK_UCLK (0x0 << 5 ) /* UCLK - System Clock */
356#define TCON_CLK_PCLK (0x1 << 5 ) /* PCLK - Peripheral clock */
357#define TCON_CLK_LFOSC (0x2 << 5 ) /* LFOSC - Internal 32 kHz Oscillator */
358#define TCON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL - External 32 kHz crystal */
359
360/* TCON[ENABLE] - Enable */
361#define TCON_ENABLE_MSK (0x1 << 4 )
362#define TCON_ENABLE (0x1 << 4 )
363#define TCON_ENABLE_DIS (0x0 << 4 ) /* DIS */
364#define TCON_ENABLE_EN (0x1 << 4 ) /* EN */
365
366/* TCON[MOD] - Mode */
367#define TCON_MOD_MSK (0x1 << 3 )
368#define TCON_MOD (0x1 << 3 )
369#define TCON_MOD_FREERUN (0x0 << 3 ) /* FREERUN */
370#define TCON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC */
371
372/* TCON[UP] - Count-up */
373#define TCON_UP_MSK (0x1 << 2 )
374#define TCON_UP (0x1 << 2 )
375#define TCON_UP_DIS (0x0 << 2 ) /* DIS */
376#define TCON_UP_EN (0x1 << 2 ) /* EN */
377
378/* TCON[PRE] - Prescaler */
379#define TCON_PRE_MSK (0x3 << 0 )
380#define TCON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
381#define TCON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
382#define TCON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
383#define TCON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 - If the selected clock source is UCLK then this setting results in a prescaler of 4. */
384
385/* TCLRI[CAP] - Clear captured event interrupt */
386#define TCLRI_CAP_MSK (0x1 << 1 )
387#define TCLRI_CAP (0x1 << 1 )
388#define TCLRI_CAP_CLR (0x1 << 1 ) /* CLR */
389
390/* TCLRI[TMOUT] - Clear timeout interrupt */
391#define TCLRI_TMOUT_MSK (0x1 << 0 )
392#define TCLRI_TMOUT (0x1 << 0 )
393#define TCLRI_TMOUT_CLR (0x1 << 0 ) /* CLR */
394
395/* TSTA[CLRI] - Value updated in the timer clock domain */
396#define TSTA_CLRI_MSK (0x1 << 7 )
397#define TSTA_CLRI (0x1 << 7 )
398#define TSTA_CLRI_CLR (0x0 << 7 ) /* CLR */
399#define TSTA_CLRI_SET (0x1 << 7 ) /* SET */
400
401/* TSTA[CON] - Ready to receive commands */
402#define TSTA_CON_MSK (0x1 << 6 )
403#define TSTA_CON (0x1 << 6 )
404#define TSTA_CON_CLR (0x0 << 6 ) /* CLR */
405#define TSTA_CON_SET (0x1 << 6 ) /* SET */
406
407/* TSTA[CAP] - Capture event pending */
408#define TSTA_CAP_MSK (0x1 << 1 )
409#define TSTA_CAP (0x1 << 1 )
410#define TSTA_CAP_CLR (0x0 << 1 ) /* CLR */
411#define TSTA_CAP_SET (0x1 << 1 ) /* SET */
412
413/* TSTA[TMOUT] - Time out event occurred */
414#define TSTA_TMOUT_MSK (0x1 << 0 )
415#define TSTA_TMOUT (0x1 << 0 )
416#define TSTA_TMOUT_CLR (0x0 << 0 ) /* CLR */
417#define TSTA_TMOUT_SET (0x1 << 0 ) /* SET */
418
419/* GPCON[CON7] - Configuration bits for P0.7 */
420#define GPCON_CON7_MSK (0x3 << 14 )
421
422/* GPCON[CON6] - Configuration bits for P0.6 */
423#define GPCON_CON6_MSK (0x3 << 12 )
424
425/* GPCON[CON5] - Configuration bits for P0.5 */
426#define GPCON_CON5_MSK (0x3 << 10 )
427
428/* GPCON[CON4] - Configuration bits for P0.4 */
429#define GPCON_CON4_MSK (0x3 << 8 )
430
431/* GPCON[CON3] - Configuration bits for P0.3 */
432#define GPCON_CON3_MSK (0x3 << 6 )
433
434/* GPCON[CON2] - Configuration bits for P0.2 */
435#define GPCON_CON2_MSK (0x3 << 4 )
436
437/* GPCON[CON1] - Configuration bits for P0.1 */
438#define GPCON_CON1_MSK (0x3 << 2 )
439
440/* GPCON[CON0] - Configuration bits for P0.0 */
441#define GPCON_CON0_MSK (0x3 << 0 )
442
443/* GPOEN[OEN7] - Direction for port pin */
444#define GPOEN_OEN7_MSK (0x1 << 7 )
445#define GPOEN_OEN7 (0x1 << 7 )
446#define GPOEN_OEN7_IN (0x0 << 7 ) /* IN */
447#define GPOEN_OEN7_OUT (0x1 << 7 ) /* OUT */
448
449/* GPOEN[OEN6] - Direction for port pin */
450#define GPOEN_OEN6_MSK (0x1 << 6 )
451#define GPOEN_OEN6 (0x1 << 6 )
452#define GPOEN_OEN6_IN (0x0 << 6 ) /* IN */
453#define GPOEN_OEN6_OUT (0x1 << 6 ) /* OUT */
454
455/* GPOEN[OEN5] - Direction for port pin */
456#define GPOEN_OEN5_MSK (0x1 << 5 )
457#define GPOEN_OEN5 (0x1 << 5 )
458#define GPOEN_OEN5_IN (0x0 << 5 ) /* IN */
459#define GPOEN_OEN5_OUT (0x1 << 5 ) /* OUT */
460
461/* GPOEN[OEN4] - Direction for port pin */
462#define GPOEN_OEN4_MSK (0x1 << 4 )
463#define GPOEN_OEN4 (0x1 << 4 )
464#define GPOEN_OEN4_IN (0x0 << 4 ) /* IN */
465#define GPOEN_OEN4_OUT (0x1 << 4 ) /* OUT */
466
467/* GPOEN[OEN3] - Direction for port pin */
468#define GPOEN_OEN3_MSK (0x1 << 3 )
469#define GPOEN_OEN3 (0x1 << 3 )
470#define GPOEN_OEN3_IN (0x0 << 3 ) /* IN */
471#define GPOEN_OEN3_OUT (0x1 << 3 ) /* OUT */
472
473/* GPOEN[OEN2] - Direction for port pin */
474#define GPOEN_OEN2_MSK (0x1 << 2 )
475#define GPOEN_OEN2 (0x1 << 2 )
476#define GPOEN_OEN2_IN (0x0 << 2 ) /* IN */
477#define GPOEN_OEN2_OUT (0x1 << 2 ) /* OUT */
478
479/* GPOEN[OEN1] - Direction for port pin */
480#define GPOEN_OEN1_MSK (0x1 << 1 )
481#define GPOEN_OEN1 (0x1 << 1 )
482#define GPOEN_OEN1_IN (0x0 << 1 ) /* IN */
483#define GPOEN_OEN1_OUT (0x1 << 1 ) /* OUT */
484
485/* GPOEN[OEN0] - Direction for port pin */
486#define GPOEN_OEN0_MSK (0x1 << 0 )
487#define GPOEN_OEN0 (0x1 << 0 )
488#define GPOEN_OEN0_IN (0x0 << 0 ) /* IN */
489#define GPOEN_OEN0_OUT (0x1 << 0 ) /* OUT */
490
491/* GPIN[IN7] - Input for port pin */
492#define GPIN_IN7_MSK (0x1 << 7 )
493#define GPIN_IN7 (0x1 << 7 )
494#define GPIN_IN7_LOW (0x0 << 7 ) /* LOW */
495#define GPIN_IN7_HIGH (0x1 << 7 ) /* HIGH */
496
497/* GPIN[IN6] - Input for port pin */
498#define GPIN_IN6_MSK (0x1 << 6 )
499#define GPIN_IN6 (0x1 << 6 )
500#define GPIN_IN6_LOW (0x0 << 6 ) /* LOW */
501#define GPIN_IN6_HIGH (0x1 << 6 ) /* HIGH */
502
503/* GPIN[IN5] - Input for port pin */
504#define GPIN_IN5_MSK (0x1 << 5 )
505#define GPIN_IN5 (0x1 << 5 )
506#define GPIN_IN5_LOW (0x0 << 5 ) /* LOW */
507#define GPIN_IN5_HIGH (0x1 << 5 ) /* HIGH */
508
509/* GPIN[IN4] - Input for port pin */
510#define GPIN_IN4_MSK (0x1 << 4 )
511#define GPIN_IN4 (0x1 << 4 )
512#define GPIN_IN4_LOW (0x0 << 4 ) /* LOW */
513#define GPIN_IN4_HIGH (0x1 << 4 ) /* HIGH */
514
515/* GPIN[IN3] - Input for port pin */
516#define GPIN_IN3_MSK (0x1 << 3 )
517#define GPIN_IN3 (0x1 << 3 )
518#define GPIN_IN3_LOW (0x0 << 3 ) /* LOW */
519#define GPIN_IN3_HIGH (0x1 << 3 ) /* HIGH */
520
521/* GPIN[IN2] - Input for port pin */
522#define GPIN_IN2_MSK (0x1 << 2 )
523#define GPIN_IN2 (0x1 << 2 )
524#define GPIN_IN2_LOW (0x0 << 2 ) /* LOW */
525#define GPIN_IN2_HIGH (0x1 << 2 ) /* HIGH */
526
527/* GPIN[IN1] - Input for port pin */
528#define GPIN_IN1_MSK (0x1 << 1 )
529#define GPIN_IN1 (0x1 << 1 )
530#define GPIN_IN1_LOW (0x0 << 1 ) /* LOW */
531#define GPIN_IN1_HIGH (0x1 << 1 ) /* HIGH */
532
533/* GPIN[IN0] - Input for port pin */
534#define GPIN_IN0_MSK (0x1 << 0 )
535#define GPIN_IN0 (0x1 << 0 )
536#define GPIN_IN0_LOW (0x0 << 0 ) /* LOW */
537#define GPIN_IN0_HIGH (0x1 << 0 ) /* HIGH */
538
539/* GPOUT[OUT7] - Output for port pin */
540#define GPOUT_OUT7_MSK (0x1 << 7 )
541#define GPOUT_OUT7 (0x1 << 7 )
542#define GPOUT_OUT7_LOW (0x0 << 7 ) /* LOW */
543#define GPOUT_OUT7_HIGH (0x1 << 7 ) /* HIGH */
544
545/* GPOUT[OUT6] - Output for port pin */
546#define GPOUT_OUT6_MSK (0x1 << 6 )
547#define GPOUT_OUT6 (0x1 << 6 )
548#define GPOUT_OUT6_LOW (0x0 << 6 ) /* LOW */
549#define GPOUT_OUT6_HIGH (0x1 << 6 ) /* HIGH */
550
551/* GPOUT[OUT5] - Output for port pin */
552#define GPOUT_OUT5_MSK (0x1 << 5 )
553#define GPOUT_OUT5 (0x1 << 5 )
554#define GPOUT_OUT5_LOW (0x0 << 5 ) /* LOW */
555#define GPOUT_OUT5_HIGH (0x1 << 5 ) /* HIGH */
556
557/* GPOUT[OUT4] - Output for port pin */
558#define GPOUT_OUT4_MSK (0x1 << 4 )
559#define GPOUT_OUT4 (0x1 << 4 )
560#define GPOUT_OUT4_LOW (0x0 << 4 ) /* LOW */
561#define GPOUT_OUT4_HIGH (0x1 << 4 ) /* HIGH */
562
563/* GPOUT[OUT3] - Output for port pin */
564#define GPOUT_OUT3_MSK (0x1 << 3 )
565#define GPOUT_OUT3 (0x1 << 3 )
566#define GPOUT_OUT3_LOW (0x0 << 3 ) /* LOW */
567#define GPOUT_OUT3_HIGH (0x1 << 3 ) /* HIGH */
568
569/* GPOUT[OUT2] - Output for port pin */
570#define GPOUT_OUT2_MSK (0x1 << 2 )
571#define GPOUT_OUT2 (0x1 << 2 )
572#define GPOUT_OUT2_LOW (0x0 << 2 ) /* LOW */
573#define GPOUT_OUT2_HIGH (0x1 << 2 ) /* HIGH */
574
575/* GPOUT[OUT1] - Output for port pin */
576#define GPOUT_OUT1_MSK (0x1 << 1 )
577#define GPOUT_OUT1 (0x1 << 1 )
578#define GPOUT_OUT1_LOW (0x0 << 1 ) /* LOW */
579#define GPOUT_OUT1_HIGH (0x1 << 1 ) /* HIGH */
580
581/* GPOUT[OUT0] - Output for port pin */
582#define GPOUT_OUT0_MSK (0x1 << 0 )
583#define GPOUT_OUT0 (0x1 << 0 )
584#define GPOUT_OUT0_LOW (0x0 << 0 ) /* LOW */
585#define GPOUT_OUT0_HIGH (0x1 << 0 ) /* HIGH */
586
587/* GPSET[SET7] - Set Output High for port pin */
588#define GPSET_SET7_MSK (0x1 << 7 )
589#define GPSET_SET7 (0x1 << 7 )
590#define GPSET_SET7_SET (0x1 << 7 ) /* SET */
591
592/* GPSET[SET6] - Set Output High for port pin */
593#define GPSET_SET6_MSK (0x1 << 6 )
594#define GPSET_SET6 (0x1 << 6 )
595#define GPSET_SET6_SET (0x1 << 6 ) /* SET */
596
597/* GPSET[SET5] - Set Output High for port pin */
598#define GPSET_SET5_MSK (0x1 << 5 )
599#define GPSET_SET5 (0x1 << 5 )
600#define GPSET_SET5_SET (0x1 << 5 ) /* SET */
601
602/* GPSET[SET4] - Set Output High for port pin */
603#define GPSET_SET4_MSK (0x1 << 4 )
604#define GPSET_SET4 (0x1 << 4 )
605#define GPSET_SET4_SET (0x1 << 4 ) /* SET */
606
607/* GPSET[SET3] - Set Output High for port pin */
608#define GPSET_SET3_MSK (0x1 << 3 )
609#define GPSET_SET3 (0x1 << 3 )
610#define GPSET_SET3_SET (0x1 << 3 ) /* SET */
611
612/* GPSET[SET2] - Set Output High for port pin */
613#define GPSET_SET2_MSK (0x1 << 2 )
614#define GPSET_SET2 (0x1 << 2 )
615#define GPSET_SET2_SET (0x1 << 2 ) /* SET */
616
617/* GPSET[SET1] - Set Output High for port pin */
618#define GPSET_SET1_MSK (0x1 << 1 )
619#define GPSET_SET1 (0x1 << 1 )
620#define GPSET_SET1_SET (0x1 << 1 ) /* SET */
621
622/* GPSET[SET0] - Set Output High for port pin */
623#define GPSET_SET0_MSK (0x1 << 0 )
624#define GPSET_SET0 (0x1 << 0 )
625#define GPSET_SET0_SET (0x1 << 0 ) /* SET */
626
627/* GPCLR[CLR7] - Set Output Low for port pin */
628#define GPCLR_CLR7_MSK (0x1 << 7 )
629#define GPCLR_CLR7 (0x1 << 7 )
630#define GPCLR_CLR7_CLR (0x1 << 7 ) /* CLR */
631
632/* GPCLR[CLR6] - Set Output Low for port pin */
633#define GPCLR_CLR6_MSK (0x1 << 6 )
634#define GPCLR_CLR6 (0x1 << 6 )
635#define GPCLR_CLR6_CLR (0x1 << 6 ) /* CLR */
636
637/* GPCLR[CLR5] - Set Output Low for port pin */
638#define GPCLR_CLR5_MSK (0x1 << 5 )
639#define GPCLR_CLR5 (0x1 << 5 )
640#define GPCLR_CLR5_CLR (0x1 << 5 ) /* CLR */
641
642/* GPCLR[CLR4] - Set Output Low for port pin */
643#define GPCLR_CLR4_MSK (0x1 << 4 )
644#define GPCLR_CLR4 (0x1 << 4 )
645#define GPCLR_CLR4_CLR (0x1 << 4 ) /* CLR */
646
647/* GPCLR[CLR3] - Set Output Low for port pin */
648#define GPCLR_CLR3_MSK (0x1 << 3 )
649#define GPCLR_CLR3 (0x1 << 3 )
650#define GPCLR_CLR3_CLR (0x1 << 3 ) /* CLR */
651
652/* GPCLR[CLR2] - Set Output Low for port pin */
653#define GPCLR_CLR2_MSK (0x1 << 2 )
654#define GPCLR_CLR2 (0x1 << 2 )
655#define GPCLR_CLR2_CLR (0x1 << 2 ) /* CLR */
656
657/* GPCLR[CLR1] - Set Output Low for port pin */
658#define GPCLR_CLR1_MSK (0x1 << 1 )
659#define GPCLR_CLR1 (0x1 << 1 )
660#define GPCLR_CLR1_CLR (0x1 << 1 ) /* CLR */
661
662/* GPCLR[CLR0] - Set Output Low for port pin */
663#define GPCLR_CLR0_MSK (0x1 << 0 )
664#define GPCLR_CLR0 (0x1 << 0 )
665#define GPCLR_CLR0_CLR (0x1 << 0 ) /* CLR */
666
667/* GPTGL[TGL7] - Toggle Output for port pin */
668#define GPTGL_TGL7_MSK (0x1 << 7 )
669#define GPTGL_TGL7 (0x1 << 7 )
670#define GPTGL_TGL7_TGL (0x1 << 7 ) /* TGL */
671
672/* GPTGL[TGL6] - Toggle Output for port pin */
673#define GPTGL_TGL6_MSK (0x1 << 6 )
674#define GPTGL_TGL6 (0x1 << 6 )
675#define GPTGL_TGL6_TGL (0x1 << 6 ) /* TGL */
676
677/* GPTGL[TGL5] - Toggle Output for port pin */
678#define GPTGL_TGL5_MSK (0x1 << 5 )
679#define GPTGL_TGL5 (0x1 << 5 )
680#define GPTGL_TGL5_TGL (0x1 << 5 ) /* TGL */
681
682/* GPTGL[TGL4] - Toggle Output for port pin */
683#define GPTGL_TGL4_MSK (0x1 << 4 )
684#define GPTGL_TGL4 (0x1 << 4 )
685#define GPTGL_TGL4_TGL (0x1 << 4 ) /* TGL */
686
687/* GPTGL[TGL3] - Toggle Output for port pin */
688#define GPTGL_TGL3_MSK (0x1 << 3 )
689#define GPTGL_TGL3 (0x1 << 3 )
690#define GPTGL_TGL3_TGL (0x1 << 3 ) /* TGL */
691
692/* GPTGL[TGL2] - Toggle Output for port pin */
693#define GPTGL_TGL2_MSK (0x1 << 2 )
694#define GPTGL_TGL2 (0x1 << 2 )
695#define GPTGL_TGL2_TGL (0x1 << 2 ) /* TGL */
696
697/* GPTGL[TGL1] - Toggle Output for port pin */
698#define GPTGL_TGL1_MSK (0x1 << 1 )
699#define GPTGL_TGL1 (0x1 << 1 )
700#define GPTGL_TGL1_TGL (0x1 << 1 ) /* TGL */
701
702/* GPTGL[TGL0] - Toggle Output for port pin */
703#define GPTGL_TGL0_MSK (0x1 << 0 )
704#define GPTGL_TGL0 (0x1 << 0 )
705#define GPTGL_TGL0_TGL (0x1 << 0 ) /* TGL */
706
707/* SPIDIV[BCRST] - Bit counter reset */
708#define SPIDIV_BCRST_MSK (0x1 << 7 )
709#define SPIDIV_BCRST (0x1 << 7 )
710#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS */
711#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN */
712
713/* SPIDIV[DIV] - Factor used to divide UCLK to generate the serial clock */
714#define SPIDIV_DIV_MSK (0x3F << 0 )
715
716/* SPICON[MOD] - SPI IRQ Mode bits */
717#define SPICON_MOD_MSK (0x3 << 14 )
718#define SPICON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1 */
719#define SPICON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2 */
720#define SPICON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3 */
721#define SPICON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4 */
722
723/* SPICON[TFLUSH] - TX FIFO Flush Enable bit */
724#define SPICON_TFLUSH_MSK (0x1 << 13 )
725#define SPICON_TFLUSH (0x1 << 13 )
726#define SPICON_TFLUSH_DIS (0x0 << 13 ) /* DIS */
727#define SPICON_TFLUSH_EN (0x1 << 13 ) /* EN */
728
729/* SPICON[RFLUSH] - RX FIFO Flush Enable bit */
730#define SPICON_RFLUSH_MSK (0x1 << 12 )
731#define SPICON_RFLUSH (0x1 << 12 )
732#define SPICON_RFLUSH_DIS (0x0 << 12 ) /* DIS */
733#define SPICON_RFLUSH_EN (0x1 << 12 ) /* EN */
734
735/* SPICON[CON] - Continuous transfer enable */
736#define SPICON_CON_MSK (0x1 << 11 )
737#define SPICON_CON (0x1 << 11 )
738#define SPICON_CON_DIS (0x0 << 11 ) /* DIS */
739#define SPICON_CON_EN (0x1 << 11 ) /* EN */
740
741/* SPICON[LOOPBACK] - Loopback enable bit */
742#define SPICON_LOOPBACK_MSK (0x1 << 10 )
743#define SPICON_LOOPBACK (0x1 << 10 )
744#define SPICON_LOOPBACK_DIS (0x0 << 10 ) /* DIS */
745#define SPICON_LOOPBACK_EN (0x1 << 10 ) /* EN */
746
747/* SPICON[SOEN] - Slave MISO output enable bit */
748#define SPICON_SOEN_MSK (0x1 << 9 )
749#define SPICON_SOEN (0x1 << 9 )
750#define SPICON_SOEN_DIS (0x0 << 9 ) /* DIS */
751#define SPICON_SOEN_EN (0x1 << 9 ) /* EN */
752
753/* SPICON[RXOF] - RX Oveflow Overwrite enable */
754#define SPICON_RXOF_MSK (0x1 << 8 )
755#define SPICON_RXOF (0x1 << 8 )
756#define SPICON_RXOF_DIS (0x0 << 8 ) /* DIS */
757#define SPICON_RXOF_EN (0x1 << 8 ) /* EN */
758
759/* SPICON[ZEN] - Transmit zeros when empty */
760#define SPICON_ZEN_MSK (0x1 << 7 )
761#define SPICON_ZEN (0x1 << 7 )
762#define SPICON_ZEN_DIS (0x0 << 7 ) /* DIS */
763#define SPICON_ZEN_EN (0x1 << 7 ) /* EN */
764
765/* SPICON[TIM] - Transfer and interrupt mode */
766#define SPICON_TIM_MSK (0x1 << 6 )
767#define SPICON_TIM (0x1 << 6 )
768#define SPICON_TIM_RXRD (0x0 << 6 ) /* RXRD - Cleared by user to initiate transfer with a read of the SPIRX register */
769#define SPICON_TIM_TXWR (0x1 << 6 ) /* TXWR - Set by user to initiate transfer with a write to the SPITX register. */
770
771/* SPICON[LSB] - LSB First Transfer enable */
772#define SPICON_LSB_MSK (0x1 << 5 )
773#define SPICON_LSB (0x1 << 5 )
774#define SPICON_LSB_DIS (0x0 << 5 ) /* DIS */
775#define SPICON_LSB_EN (0x1 << 5 ) /* EN */
776
777/* SPICON[WOM] - Wired OR enable */
778#define SPICON_WOM_MSK (0x1 << 4 )
779#define SPICON_WOM (0x1 << 4 )
780#define SPICON_WOM_DIS (0x0 << 4 ) /* DIS */
781#define SPICON_WOM_EN (0x1 << 4 ) /* EN */
782
783/* SPICON[CPOL] - Clock polarity mode */
784#define SPICON_CPOL_MSK (0x1 << 3 )
785#define SPICON_CPOL (0x1 << 3 )
786#define SPICON_CPOL_LOW (0x0 << 3 ) /* LOW */
787#define SPICON_CPOL_HIGH (0x1 << 3 ) /* HIGH */
788
789/* SPICON[CPHA] - Clock phase mode */
790#define SPICON_CPHA_MSK (0x1 << 2 )
791#define SPICON_CPHA (0x1 << 2 )
792#define SPICON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING */
793#define SPICON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING */
794
795/* SPICON[MASEN] - Master enable */
796#define SPICON_MASEN_MSK (0x1 << 1 )
797#define SPICON_MASEN (0x1 << 1 )
798#define SPICON_MASEN_DIS (0x0 << 1 ) /* DIS */
799#define SPICON_MASEN_EN (0x1 << 1 ) /* EN */
800
801/* SPICON[ENABLE] - SPI Enable bit */
802#define SPICON_ENABLE_MSK (0x1 << 0 )
803#define SPICON_ENABLE (0x1 << 0 )
804#define SPICON_ENABLE_DIS (0x0 << 0 ) /* DIS */
805#define SPICON_ENABLE_EN (0x1 << 0 ) /* EN */
806
807/* SPIDMA[IENRXDMA] - Enable receive DMA request */
808#define SPIDMA_IENRXDMA_MSK (0x1 << 2 )
809#define SPIDMA_IENRXDMA (0x1 << 2 )
810#define SPIDMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS */
811#define SPIDMA_IENRXDMA_EN (0x1 << 2 ) /* EN */
812
813/* SPIDMA[IENTXDMA] - Enable transmit DMA request */
814#define SPIDMA_IENTXDMA_MSK (0x1 << 1 )
815#define SPIDMA_IENTXDMA (0x1 << 1 )
816#define SPIDMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS */
817#define SPIDMA_IENTXDMA_EN (0x1 << 1 ) /* EN */
818
819/* SPIDMA[ENABLE] - Enable DMA for data transfer */
820#define SPIDMA_ENABLE_MSK (0x1 << 0 )
821#define SPIDMA_ENABLE (0x1 << 0 )
822#define SPIDMA_ENABLE_DIS (0x0 << 0 ) /* DIS */
823#define SPIDMA_ENABLE_EN (0x1 << 0 ) /* EN */
824
825/* SPISTA[CSERR] - Detected an abrupt CS deassertion */
826#define SPISTA_CSERR_MSK (0x1 << 12 )
827#define SPISTA_CSERR (0x1 << 12 )
828#define SPISTA_CSERR_CLR (0x0 << 12 ) /* CLR */
829#define SPISTA_CSERR_SET (0x1 << 12 ) /* SET */
830
831/* SPISTA[CSRSG] - Detected an abrupt CS deassertion */
832#define SPISTA_CSRSG_MSK (0x1 << 14 )
833#define SPISTA_CSRSG (0x1 << 14 )
834#define SPISTA_CSRSG_CLR (0x0 << 14 ) /* CLR */
835#define SPISTA_CSRSG_SET (0x1 << 14 ) /* SET */
836
837/* SPISTA[RXS] - Set when there are more bytes in the RX FIFO than the TIM bit says */
838#define SPISTA_RXS_MSK (0x1 << 11 )
839#define SPISTA_RXS (0x1 << 11 )
840#define SPISTA_RXS_CLR (0x0 << 11 ) /* CLR */
841#define SPISTA_RXS_SET (0x1 << 11 ) /* SET */
842
843/* SPISTA[RXFSTA] - Receive FIFO Status */
844#define SPISTA_RXFSTA_MSK (0x7 << 8 )
845#define SPISTA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY */
846#define SPISTA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE */
847#define SPISTA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES */
848#define SPISTA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES */
849#define SPISTA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES */
850
851/* SPISTA[RXOF] - Receive FIFO overflow */
852#define SPISTA_RXOF_MSK (0x1 << 7 )
853#define SPISTA_RXOF (0x1 << 7 )
854#define SPISTA_RXOF_CLR (0x0 << 7 ) /* CLR */
855#define SPISTA_RXOF_SET (0x1 << 7 ) /* SET */
856
857/* SPISTA[RX] - Set when a receive interrupt occurs */
858#define SPISTA_RX_MSK (0x1 << 6 )
859#define SPISTA_RX (0x1 << 6 )
860#define SPISTA_RX_CLR (0x0 << 6 ) /* CLR */
861#define SPISTA_RX_SET (0x1 << 6 ) /* SET */
862
863/* SPISTA[TX] - Set when a transmit interrupt occurs */
864#define SPISTA_TX_MSK (0x1 << 5 )
865#define SPISTA_TX (0x1 << 5 )
866#define SPISTA_TX_CLR (0x0 << 5 ) /* CLR */
867#define SPISTA_TX_SET (0x1 << 5 ) /* SET */
868
869/* SPISTA[TXUR] - Transmit FIFO underflow */
870#define SPISTA_TXUR_MSK (0x1 << 4 )
871#define SPISTA_TXUR (0x1 << 4 )
872#define SPISTA_TXUR_CLR (0x0 << 4 ) /* CLR */
873#define SPISTA_TXUR_SET (0x1 << 4 ) /* SET */
874
875/* SPISTA[TXFSTA] - transmit FIFO Status */
876#define SPISTA_TXFSTA_MSK (0x7 << 1 )
877#define SPISTA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY */
878#define SPISTA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE */
879#define SPISTA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES */
880#define SPISTA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES */
881#define SPISTA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES */
882
883/* SPISTA[IRQ] - Interrupt status bit */
884#define SPISTA_IRQ_MSK (0x1 << 0 )
885#define SPISTA_IRQ (0x1 << 0 )
886#define SPISTA_IRQ_CLR (0x0 << 0 ) /* CLR */
887#define SPISTA_IRQ_SET (0x1 << 0 ) /* SET */
888
889/* SPIDIV[BCRST] - Bit counter reset */
890#define SPIDIV_BCRST_MSK (0x1 << 7 )
891#define SPIDIV_BCRST (0x1 << 7 )
892#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS */
893#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN */
894
895/* SPIDIV[DIV] - Factor used to divide UCLK to generate the serial clock */
896#define SPIDIV_DIV_MSK (0x3F << 0 )
897// ------------------------------------------------------------------------------------------------
898// ----- T0 -----
899// ------------------------------------------------------------------------------------------------
900
901
902/**
903 * @brief Timer 0 (pADI_TM0)
904 */
905
906#if (__NO_MMR_STRUCTS__==0)
907typedef struct { /*!< pADI_TM0 Structure */
908 __IO uint16_t LD; /*!< 16-bit load value */
909 __I uint16_t RESERVED0;
910 __IO uint16_t VAL; /*!< "16-bit timer value, read only." */
911 __I uint16_t RESERVED1;
912 __IO uint16_t CON; /*!< Control Register */
913 __I uint16_t RESERVED2;
914 __IO uint16_t CLRI; /*!< Clear interrupt register */
915 __I uint16_t RESERVED3;
916 __IO uint16_t CAP; /*!< Capture Register */
917 __I uint16_t RESERVED4[5];
918 __IO uint16_t STA; /*!< Status Register */
919} ADI_TIMER_TypeDef;
920#else // (__NO_MMR_STRUCTS__==0)
921#define T0LD (*(volatile unsigned short int *) 0x40000000)
922#define T0VAL (*(volatile unsigned short int *) 0x40000004)
923#define T0CON (*(volatile unsigned short int *) 0x40000008)
924#define T0CLRI (*(volatile unsigned short int *) 0x4000000C)
925#define T0CAP (*(volatile unsigned short int *) 0x40000010)
926#define T0STA (*(volatile unsigned short int *) 0x4000001C)
927#endif // (__NO_MMR_STRUCTS__==0)
928
929/* Reset Value for T0LD*/
930#define T0LD_RVAL 0x0
931
932/* T0LD[VALUE] - Load value */
933#define T0LD_VALUE_MSK (0xFFFF << 0 )
934
935/* Reset Value for T0VAL*/
936#define T0VAL_RVAL 0x0
937
938/* T0VAL[VALUE] - Current value */
939#define T0VAL_VALUE_MSK (0xFFFF << 0 )
940
941/* Reset Value for T0CON*/
942#define T0CON_RVAL 0xA
943
944/* T0CON[EVENTEN] - Enable time capture of an event */
945#define T0CON_EVENTEN_BBA (*(volatile unsigned long *) 0x42000130)
946#define T0CON_EVENTEN_MSK (0x1 << 12 )
947#define T0CON_EVENTEN (0x1 << 12 )
948#define T0CON_EVENTEN_DIS (0x0 << 12 ) /* DIS */
949#define T0CON_EVENTEN_EN (0x1 << 12 ) /* EN */
950
951/* T0CON[EVENT] - Event Select, selects 1 of the available events. */
952#define T0CON_EVENT_MSK (0xF << 8 )
953#define T0CON_EVENT_T2 (0x0 << 8 ) /* T2 - Wakeup Timer */
954#define T0CON_EVENT_EXT0 (0x1 << 8 ) /* EXT0 - External interrupt 0 */
955#define T0CON_EVENT_EXT1 (0x2 << 8 ) /* EXT1 - External interrupt 1 */
956#define T0CON_EVENT_EXT2 (0x3 << 8 ) /* EXT2 - External interrupt 2 */
957#define T0CON_EVENT_EXT3 (0x4 << 8 ) /* EXT3 - External interrupt 3 */
958#define T0CON_EVENT_EXT4 (0x5 << 8 ) /* EXT4 - External interrupt 4 */
959#define T0CON_EVENT_EXT5 (0x6 << 8 ) /* EXT5 - External interrupt 5 */
960#define T0CON_EVENT_EXT6 (0x7 << 8 ) /* EXT6 - External interrupt 6 */
961#define T0CON_EVENT_EXT7 (0x8 << 8 ) /* EXT7 - External interrupt 7 */
962#define T0CON_EVENT_T3 (0x9 << 8 ) /* T3 - Watchdog timer */
963#define T0CON_EVENT_T1 (0xA << 8 ) /* T1 - Timer1 */
964#define T0CON_EVENT_ADC0 (0xB << 8 ) /* ADC0 - ADC0 */
965#define T0CON_EVENT_ADC1 (0xC << 8 ) /* ADC1 - ADC1 */
966#define T0CON_EVENT_STEP (0xD << 8 ) /* STEP - STEP */
967#define T0CON_EVENT_DMADONE (0xE << 8 ) /* DMADONE */
968#define T0CON_EVENT_FEE (0xF << 8 ) /* FEE - Flash controller */
969
970/* T0CON[RLD] - Timer reload on write to clear register */
971#define T0CON_RLD_BBA (*(volatile unsigned long *) 0x4200011C)
972#define T0CON_RLD_MSK (0x1 << 7 )
973#define T0CON_RLD (0x1 << 7 )
974#define T0CON_RLD_DIS (0x0 << 7 ) /* DIS */
975#define T0CON_RLD_EN (0x1 << 7 ) /* EN */
976
977/* T0CON[CLK] - Clock Select */
978#define T0CON_CLK_MSK (0x3 << 5 )
979#define T0CON_CLK_UCLK (0x0 << 5 ) /* UCLK - System Clock */
980#define T0CON_CLK_PCLK (0x1 << 5 ) /* PCLK - Peripheral clock */
981#define T0CON_CLK_LFOSC (0x2 << 5 ) /* LFOSC - Internal 32 kHz Oscillator */
982#define T0CON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL - External 32 kHz crystal */
983
984/* T0CON[ENABLE] - Enable */
985#define T0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42000110)
986#define T0CON_ENABLE_MSK (0x1 << 4 )
987#define T0CON_ENABLE (0x1 << 4 )
988#define T0CON_ENABLE_DIS (0x0 << 4 ) /* DIS */
989#define T0CON_ENABLE_EN (0x1 << 4 ) /* EN */
990
991/* T0CON[MOD] - Mode */
992#define T0CON_MOD_BBA (*(volatile unsigned long *) 0x4200010C)
993#define T0CON_MOD_MSK (0x1 << 3 )
994#define T0CON_MOD (0x1 << 3 )
995#define T0CON_MOD_FREERUN (0x0 << 3 ) /* FREERUN */
996#define T0CON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC */
997
998/* T0CON[UP] - Count-up */
999#define T0CON_UP_BBA (*(volatile unsigned long *) 0x42000108)
1000#define T0CON_UP_MSK (0x1 << 2 )
1001#define T0CON_UP (0x1 << 2 )
1002#define T0CON_UP_DIS (0x0 << 2 ) /* DIS */
1003#define T0CON_UP_EN (0x1 << 2 ) /* EN */
1004
1005/* T0CON[PRE] - Prescaler */
1006#define T0CON_PRE_MSK (0x3 << 0 )
1007#define T0CON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
1008#define T0CON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
1009#define T0CON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
1010#define T0CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 - If the selected clock source is UCLK then this setting results in a prescaler of 4. */
1011
1012/* Reset Value for T0CLRI*/
1013#define T0CLRI_RVAL 0x0
1014
1015/* T0CLRI[CAP] - Clear captured event interrupt */
1016#define T0CLRI_CAP_BBA (*(volatile unsigned long *) 0x42000184)
1017#define T0CLRI_CAP_MSK (0x1 << 1 )
1018#define T0CLRI_CAP (0x1 << 1 )
1019#define T0CLRI_CAP_CLR (0x1 << 1 ) /* CLR */
1020
1021/* T0CLRI[TMOUT] - Clear timeout interrupt */
1022#define T0CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42000180)
1023#define T0CLRI_TMOUT_MSK (0x1 << 0 )
1024#define T0CLRI_TMOUT (0x1 << 0 )
1025#define T0CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR */
1026
1027/* Reset Value for T0CAP*/
1028#define T0CAP_RVAL 0x0
1029
1030/* T0CAP[VALUE] - Capture value */
1031#define T0CAP_VALUE_MSK (0xFFFF << 0 )
1032
1033/* Reset Value for T0STA*/
1034#define T0STA_RVAL 0x0
1035
1036/* T0STA[CLRI] - Value updated in the timer clock domain */
1037#define T0STA_CLRI_BBA (*(volatile unsigned long *) 0x4200039C)
1038#define T0STA_CLRI_MSK (0x1 << 7 )
1039#define T0STA_CLRI (0x1 << 7 )
1040#define T0STA_CLRI_CLR (0x0 << 7 ) /* CLR */
1041#define T0STA_CLRI_SET (0x1 << 7 ) /* SET */
1042
1043/* T0STA[CON] - Ready to receive commands */
1044#define T0STA_CON_BBA (*(volatile unsigned long *) 0x42000398)
1045#define T0STA_CON_MSK (0x1 << 6 )
1046#define T0STA_CON (0x1 << 6 )
1047#define T0STA_CON_CLR (0x0 << 6 ) /* CLR */
1048#define T0STA_CON_SET (0x1 << 6 ) /* SET */
1049
1050/* T0STA[CAP] - Capture event pending */
1051#define T0STA_CAP_BBA (*(volatile unsigned long *) 0x42000384)
1052#define T0STA_CAP_MSK (0x1 << 1 )
1053#define T0STA_CAP (0x1 << 1 )
1054#define T0STA_CAP_CLR (0x0 << 1 ) /* CLR */
1055#define T0STA_CAP_SET (0x1 << 1 ) /* SET */
1056
1057/* T0STA[TMOUT] - Time out event occurred */
1058#define T0STA_TMOUT_BBA (*(volatile unsigned long *) 0x42000380)
1059#define T0STA_TMOUT_MSK (0x1 << 0 )
1060#define T0STA_TMOUT (0x1 << 0 )
1061#define T0STA_TMOUT_CLR (0x0 << 0 ) /* CLR */
1062#define T0STA_TMOUT_SET (0x1 << 0 ) /* SET */
1063#if (__NO_MMR_STRUCTS__==1)
1064
1065#define T1LD (*(volatile unsigned short int *) 0x40000400)
1066#define T1VAL (*(volatile unsigned short int *) 0x40000404)
1067#define T1CON (*(volatile unsigned short int *) 0x40000408)
1068#define T1CLRI (*(volatile unsigned short int *) 0x4000040C)
1069#define T1CAP (*(volatile unsigned short int *) 0x40000410)
1070#define T1STA (*(volatile unsigned short int *) 0x4000041C)
1071#endif // (__NO_MMR_STRUCTS__==1)
1072
1073/* Reset Value for T1LD*/
1074#define T1LD_RVAL 0x0
1075
1076/* T1LD[VALUE] - Load value */
1077#define T1LD_VALUE_MSK (0xFFFF << 0 )
1078
1079/* Reset Value for T1VAL*/
1080#define T1VAL_RVAL 0x0
1081
1082/* T1VAL[VALUE] - Current value */
1083#define T1VAL_VALUE_MSK (0xFFFF << 0 )
1084
1085/* Reset Value for T1CON*/
1086#define T1CON_RVAL 0xA
1087
1088/* T1CON[EVENTEN] - Enable time capture of an event */
1089#define T1CON_EVENTEN_BBA (*(volatile unsigned long *) 0x42008130)
1090#define T1CON_EVENTEN_MSK (0x1 << 12 )
1091#define T1CON_EVENTEN (0x1 << 12 )
1092#define T1CON_EVENTEN_DIS (0x0 << 12 ) /* DIS */
1093#define T1CON_EVENTEN_EN (0x1 << 12 ) /* EN */
1094
1095/* T1CON[EVENT] - Event Select, selects 1 of the available events. */
1096#define T1CON_EVENT_MSK (0xF << 8 )
1097#define T1CON_EVENT_COM (0x0 << 8 ) /* COM */
1098#define T1CON_EVENT_T0 (0x1 << 8 ) /* T0 - Timer0 */
1099#define T1CON_EVENT_SPI0 (0x2 << 8 ) /* SPI0 */
1100#define T1CON_EVENT_SPI1 (0x3 << 8 ) /* SPI1 */
1101#define T1CON_EVENT_I2CS (0x4 << 8 ) /* I2CS */
1102#define T1CON_EVENT_I2CM (0x5 << 8 ) /* I2CM */
1103#define T1CON_EVENT_DMAERR (0x6 << 8 ) /* DMAERR */
1104#define T1CON_EVENT_DMADONE (0x7 << 8 ) /* DMADONE */
1105#define T1CON_EVENT_EXT1 (0x8 << 8 ) /* EXT1 */
1106#define T1CON_EVENT_EXT2 (0x9 << 8 ) /* EXT2 */
1107#define T1CON_EVENT_EXT3 (0xA << 8 ) /* EXT3 */
1108#define T1CON_EVENT_PWMTRIP (0xB << 8 ) /* PWMTRIP */
1109#define T1CON_EVENT_PWM0 (0xC << 8 ) /* PWM0 */
1110#define T1CON_EVENT_PWM1 (0xD << 8 ) /* PWM1 */
1111#define T1CON_EVENT_PWM2 (0xE << 8 ) /* PWM2 */
1112#define T1CON_EVENT_ADC0 (0xF << 8 ) /* ADC0 */
1113
1114/* T1CON[RLD] - Timer reload on write to clear register */
1115#define T1CON_RLD_BBA (*(volatile unsigned long *) 0x4200811C)
1116#define T1CON_RLD_MSK (0x1 << 7 )
1117#define T1CON_RLD (0x1 << 7 )
1118#define T1CON_RLD_DIS (0x0 << 7 ) /* DIS */
1119#define T1CON_RLD_EN (0x1 << 7 ) /* EN */
1120
1121/* T1CON[CLK] - Clock Select */
1122#define T1CON_CLK_MSK (0x3 << 5 )
1123#define T1CON_CLK_UCLK (0x0 << 5 ) /* UCLK - System Clock */
1124#define T1CON_CLK_PCLK (0x1 << 5 ) /* PCLK - Peripheral clock */
1125#define T1CON_CLK_LFOSC (0x2 << 5 ) /* LFOSC - Internal 32 kHz Oscillator */
1126#define T1CON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL - External 32 kHz crystal */
1127
1128/* T1CON[ENABLE] - Enable */
1129#define T1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42008110)
1130#define T1CON_ENABLE_MSK (0x1 << 4 )
1131#define T1CON_ENABLE (0x1 << 4 )
1132#define T1CON_ENABLE_DIS (0x0 << 4 ) /* DIS */
1133#define T1CON_ENABLE_EN (0x1 << 4 ) /* EN */
1134
1135/* T1CON[MOD] - Mode */
1136#define T1CON_MOD_BBA (*(volatile unsigned long *) 0x4200810C)
1137#define T1CON_MOD_MSK (0x1 << 3 )
1138#define T1CON_MOD (0x1 << 3 )
1139#define T1CON_MOD_FREERUN (0x0 << 3 ) /* FREERUN */
1140#define T1CON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC */
1141
1142/* T1CON[UP] - Count-up */
1143#define T1CON_UP_BBA (*(volatile unsigned long *) 0x42008108)
1144#define T1CON_UP_MSK (0x1 << 2 )
1145#define T1CON_UP (0x1 << 2 )
1146#define T1CON_UP_DIS (0x0 << 2 ) /* DIS */
1147#define T1CON_UP_EN (0x1 << 2 ) /* EN */
1148
1149/* T1CON[PRE] - Prescaler */
1150#define T1CON_PRE_MSK (0x3 << 0 )
1151#define T1CON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
1152#define T1CON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
1153#define T1CON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
1154#define T1CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 - If the selected clock source is UCLK then this setting results in a prescaler of 4. */
1155
1156/* Reset Value for T1CLRI*/
1157#define T1CLRI_RVAL 0x0
1158
1159/* T1CLRI[CAP] - Clear captured event interrupt */
1160#define T1CLRI_CAP_BBA (*(volatile unsigned long *) 0x42008184)
1161#define T1CLRI_CAP_MSK (0x1 << 1 )
1162#define T1CLRI_CAP (0x1 << 1 )
1163#define T1CLRI_CAP_CLR (0x1 << 1 ) /* CLR */
1164
1165/* T1CLRI[TMOUT] - Clear timeout interrupt */
1166#define T1CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42008180)
1167#define T1CLRI_TMOUT_MSK (0x1 << 0 )
1168#define T1CLRI_TMOUT (0x1 << 0 )
1169#define T1CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR */
1170
1171/* Reset Value for T1CAP*/
1172#define T1CAP_RVAL 0x0
1173
1174/* T1CAP[VALUE] - Capture value */
1175#define T1CAP_VALUE_MSK (0xFFFF << 0 )
1176
1177/* Reset Value for T1STA*/
1178#define T1STA_RVAL 0x0
1179
1180/* T1STA[CLRI] - Value updated in the timer clock domain */
1181#define T1STA_CLRI_BBA (*(volatile unsigned long *) 0x4200839C)
1182#define T1STA_CLRI_MSK (0x1 << 7 )
1183#define T1STA_CLRI (0x1 << 7 )
1184#define T1STA_CLRI_CLR (0x0 << 7 ) /* CLR */
1185#define T1STA_CLRI_SET (0x1 << 7 ) /* SET */
1186
1187/* T1STA[CON] - Ready to receive commands */
1188#define T1STA_CON_BBA (*(volatile unsigned long *) 0x42008398)
1189#define T1STA_CON_MSK (0x1 << 6 )
1190#define T1STA_CON (0x1 << 6 )
1191#define T1STA_CON_CLR (0x0 << 6 ) /* CLR */
1192#define T1STA_CON_SET (0x1 << 6 ) /* SET */
1193
1194/* T1STA[CAP] - Capture event pending */
1195#define T1STA_CAP_BBA (*(volatile unsigned long *) 0x42008384)
1196#define T1STA_CAP_MSK (0x1 << 1 )
1197#define T1STA_CAP (0x1 << 1 )
1198#define T1STA_CAP_CLR (0x0 << 1 ) /* CLR */
1199#define T1STA_CAP_SET (0x1 << 1 ) /* SET */
1200
1201/* T1STA[TMOUT] - Time out event occurred */
1202#define T1STA_TMOUT_BBA (*(volatile unsigned long *) 0x42008380)
1203#define T1STA_TMOUT_MSK (0x1 << 0 )
1204#define T1STA_TMOUT (0x1 << 0 )
1205#define T1STA_TMOUT_CLR (0x0 << 0 ) /* CLR */
1206#define T1STA_TMOUT_SET (0x1 << 0 ) /* SET */
1207// ------------------------------------------------------------------------------------------------
1208// ----- PWM -----
1209// ------------------------------------------------------------------------------------------------
1210
1211
1212/**
1213 * @brief Pulse Width Modulation (pADI_PWM)
1214 */
1215
1216#if (__NO_MMR_STRUCTS__==0)
1217typedef struct { /*!< pADI_PWM Structure */
1218 __IO uint16_t PWMCON0; /*!< PWM Control register */
1219 __I uint16_t RESERVED0;
1220 __IO uint8_t PWMCON1; /*!< Trip control register */
1221 __I uint8_t RESERVED1[3];
1222 __IO uint16_t PWMCLRI; /*!< PWM interrupt clear. Write to this register clears the latched PWM interrupt. */
1223 __I uint16_t RESERVED2[3];
1224 __IO uint16_t PWM0COM0; /*!< Compare Register 0 for PWM0 and PWM1 */
1225 __I uint16_t RESERVED3;
1226 __IO uint16_t PWM0COM1; /*!< Compare Register 1 for PWM0 and PWM1 */
1227 __I uint16_t RESERVED4;
1228 __IO uint16_t PWM0COM2; /*!< Compare Register 2 for PWM0 and PWM1 */
1229 __I uint16_t RESERVED5;
1230 __IO uint16_t PWM0LEN; /*!< Period Value register for PWM0 and PWM1 */
1231 __I uint16_t RESERVED6;
1232 __IO uint16_t PWM1COM0; /*!< Compare Register 0 for PWM2 and PWM3 */
1233 __I uint16_t RESERVED7;
1234 __IO uint16_t PWM1COM1; /*!< Compare Register 1 for PWM2 and PWM3 */
1235 __I uint16_t RESERVED8;
1236 __IO uint16_t PWM1COM2; /*!< Compare Register 2 for PWM2 and PWM3 */
1237 __I uint16_t RESERVED9;
1238 __IO uint16_t PWM1LEN; /*!< Period Value register for PWM2 and PWM3 */
1239 __I uint16_t RESERVED10;
1240 __IO uint16_t PWM2COM0; /*!< Compare Register 0 for PWM4 and PWM5 */
1241 __I uint16_t RESERVED11;
1242 __IO uint16_t PWM2COM1; /*!< Compare Register 1 for PWM4 and PWM5 */
1243 __I uint16_t RESERVED12;
1244 __IO uint16_t PWM2COM2; /*!< Compare Register 2 for PWM4 and PWM5 */
1245 __I uint16_t RESERVED13;
1246 __IO uint16_t PWM2LEN; /*!< Period Value register for PWM4 and PWM5 */
1247} ADI_PWM_TypeDef;
1248#else // (__NO_MMR_STRUCTS__==0)
1249#define PWMCON0 (*(volatile unsigned short int *) 0x40001000)
1250#define PWMCON1 (*(volatile unsigned char *) 0x40001004)
1251#define PWMCLRI (*(volatile unsigned short int *) 0x40001008)
1252#define PWM0COM0 (*(volatile unsigned short int *) 0x40001010)
1253#define PWM0COM1 (*(volatile unsigned short int *) 0x40001014)
1254#define PWM0COM2 (*(volatile unsigned short int *) 0x40001018)
1255#define PWM0LEN (*(volatile unsigned short int *) 0x4000101C)
1256#define PWM1COM0 (*(volatile unsigned short int *) 0x40001020)
1257#define PWM1COM1 (*(volatile unsigned short int *) 0x40001024)
1258#define PWM1COM2 (*(volatile unsigned short int *) 0x40001028)
1259#define PWM1LEN (*(volatile unsigned short int *) 0x4000102C)
1260#define PWM2COM0 (*(volatile unsigned short int *) 0x40001030)
1261#define PWM2COM1 (*(volatile unsigned short int *) 0x40001034)
1262#define PWM2COM2 (*(volatile unsigned short int *) 0x40001038)
1263#define PWM2LEN (*(volatile unsigned short int *) 0x4000103C)
1264#endif // (__NO_MMR_STRUCTS__==0)
1265
1266/* Reset Value for PWMCON0*/
1267#define PWMCON0_RVAL 0x12
1268
1269/* PWMCON0[SYNC] - PWM Synchronization */
1270#define PWMCON0_SYNC_BBA (*(volatile unsigned long *) 0x4202003C)
1271#define PWMCON0_SYNC_MSK (0x1 << 15 )
1272#define PWMCON0_SYNC (0x1 << 15 )
1273#define PWMCON0_SYNC_DIS (0x0 << 15 ) /* DIS */
1274#define PWMCON0_SYNC_EN (0x1 << 15 ) /* EN */
1275
1276/* PWMCON0[PWM5INV] - Inversion of PWM output */
1277#define PWMCON0_PWM5INV_BBA (*(volatile unsigned long *) 0x42020034)
1278#define PWMCON0_PWM5INV_MSK (0x1 << 13 )
1279#define PWMCON0_PWM5INV (0x1 << 13 )
1280#define PWMCON0_PWM5INV_DIS (0x0 << 13 ) /* DIS */
1281#define PWMCON0_PWM5INV_EN (0x1 << 13 ) /* EN */
1282
1283/* PWMCON0[PWM3INV] - Inversion of PWM output */
1284#define PWMCON0_PWM3INV_BBA (*(volatile unsigned long *) 0x42020030)
1285#define PWMCON0_PWM3INV_MSK (0x1 << 12 )
1286#define PWMCON0_PWM3INV (0x1 << 12 )
1287#define PWMCON0_PWM3INV_DIS (0x0 << 12 ) /* DIS */
1288#define PWMCON0_PWM3INV_EN (0x1 << 12 ) /* EN */
1289
1290/* PWMCON0[PWM1INV] - Inversion of PWM output */
1291#define PWMCON0_PWM1INV_BBA (*(volatile unsigned long *) 0x4202002C)
1292#define PWMCON0_PWM1INV_MSK (0x1 << 11 )
1293#define PWMCON0_PWM1INV (0x1 << 11 )
1294#define PWMCON0_PWM1INV_DIS (0x0 << 11 ) /* DIS */
1295#define PWMCON0_PWM1INV_EN (0x1 << 11 ) /* EN */
1296
1297/* PWMCON0[PWMIEN] - Enables PWM interrupts */
1298#define PWMCON0_PWMIEN_BBA (*(volatile unsigned long *) 0x42020028)
1299#define PWMCON0_PWMIEN_MSK (0x1 << 10 )
1300#define PWMCON0_PWMIEN (0x1 << 10 )
1301#define PWMCON0_PWMIEN_DIS (0x0 << 10 ) /* DIS */
1302#define PWMCON0_PWMIEN_EN (0x1 << 10 ) /* EN */
1303
1304/* PWMCON0[ENA] - enable PWM outputs */
1305#define PWMCON0_ENA_BBA (*(volatile unsigned long *) 0x42020024)
1306#define PWMCON0_ENA_MSK (0x1 << 9 )
1307#define PWMCON0_ENA (0x1 << 9 )
1308#define PWMCON0_ENA_DIS (0x0 << 9 ) /* DIS */
1309#define PWMCON0_ENA_EN (0x1 << 9 ) /* EN */
1310
1311/* PWMCON0[PRE] - PWM Clock Prescaler */
1312#define PWMCON0_PRE_MSK (0x7 << 6 )
1313
1314/* PWMCON0[POINV] - Invert all PWM outputs */
1315#define PWMCON0_POINV_BBA (*(volatile unsigned long *) 0x42020014)
1316#define PWMCON0_POINV_MSK (0x1 << 5 )
1317#define PWMCON0_POINV (0x1 << 5 )
1318#define PWMCON0_POINV_DIS (0x0 << 5 ) /* DIS */
1319#define PWMCON0_POINV_EN (0x1 << 5 ) /* EN */
1320
1321/* PWMCON0[HOFF] - High Side Off */
1322#define PWMCON0_HOFF_BBA (*(volatile unsigned long *) 0x42020010)
1323#define PWMCON0_HOFF_MSK (0x1 << 4 )
1324#define PWMCON0_HOFF (0x1 << 4 )
1325#define PWMCON0_HOFF_DIS (0x0 << 4 ) /* DIS */
1326#define PWMCON0_HOFF_EN (0x1 << 4 ) /* EN */
1327
1328/* PWMCON0[LCOMP] - Load Compare Registers */
1329#define PWMCON0_LCOMP_BBA (*(volatile unsigned long *) 0x4202000C)
1330#define PWMCON0_LCOMP_MSK (0x1 << 3 )
1331#define PWMCON0_LCOMP (0x1 << 3 )
1332#define PWMCON0_LCOMP_DIS (0x0 << 3 ) /* DIS */
1333#define PWMCON0_LCOMP_EN (0x1 << 3 ) /* EN */
1334
1335/* PWMCON0[DIR] - Direction Control */
1336#define PWMCON0_DIR_BBA (*(volatile unsigned long *) 0x42020008)
1337#define PWMCON0_DIR_MSK (0x1 << 2 )
1338#define PWMCON0_DIR (0x1 << 2 )
1339#define PWMCON0_DIR_DIS (0x0 << 2 ) /* DIS */
1340#define PWMCON0_DIR_EN (0x1 << 2 ) /* EN */
1341
1342/* PWMCON0[MOD] - Enables H-Bridge Mode */
1343#define PWMCON0_MOD_BBA (*(volatile unsigned long *) 0x42020004)
1344#define PWMCON0_MOD_MSK (0x1 << 1 )
1345#define PWMCON0_MOD (0x1 << 1 )
1346#define PWMCON0_MOD_DIS (0x0 << 1 ) /* DIS */
1347#define PWMCON0_MOD_EN (0x1 << 1 ) /* EN */
1348
1349/* PWMCON0[ENABLE] - Enables all PWM outputs */
1350#define PWMCON0_ENABLE_BBA (*(volatile unsigned long *) 0x42020000)
1351#define PWMCON0_ENABLE_MSK (0x1 << 0 )
1352#define PWMCON0_ENABLE (0x1 << 0 )
1353#define PWMCON0_ENABLE_DIS (0x0 << 0 ) /* DIS */
1354#define PWMCON0_ENABLE_EN (0x1 << 0 ) /* EN */
1355
1356/* Reset Value for PWMCON1*/
1357#define PWMCON1_RVAL 0x0
1358
1359/* PWMCON1[CONVSTART] - Enable adc conversion start from pwm */
1360#define PWMCON1_CONVSTART_BBA (*(volatile unsigned long *) 0x4202009C)
1361#define PWMCON1_CONVSTART_MSK (0x1 << 7 )
1362#define PWMCON1_CONVSTART (0x1 << 7 )
1363#define PWMCON1_CONVSTART_DIS (0x0 << 7 ) /* DIS */
1364#define PWMCON1_CONVSTART_EN (0x1 << 7 ) /* EN */
1365
1366/* PWMCON1[TRIPEN] - Enable PWM trip functionality */
1367#define PWMCON1_TRIPEN_BBA (*(volatile unsigned long *) 0x42020098)
1368#define PWMCON1_TRIPEN_MSK (0x1 << 6 )
1369#define PWMCON1_TRIPEN (0x1 << 6 )
1370#define PWMCON1_TRIPEN_DIS (0x0 << 6 ) /* DIS */
1371#define PWMCON1_TRIPEN_EN (0x1 << 6 ) /* EN */
1372
1373/* PWMCON1[CONVSTARTDELAY] - ADC conversion start delay configuration */
1374#define PWMCON1_CONVSTARTDELAY_MSK (0xF << 0 )
1375
1376/* Reset Value for PWMCLRI*/
1377#define PWMCLRI_RVAL 0x0
1378
1379/* PWMCLRI[TRIP] - Clear the latched trip interrupt */
1380#define PWMCLRI_TRIP_BBA (*(volatile unsigned long *) 0x42020110)
1381#define PWMCLRI_TRIP_MSK (0x1 << 4 )
1382#define PWMCLRI_TRIP (0x1 << 4 )
1383#define PWMCLRI_TRIP_DIS (0x0 << 4 ) /* DIS */
1384#define PWMCLRI_TRIP_EN (0x1 << 4 ) /* EN */
1385
1386/* PWMCLRI[PWM2] - Clear the latched PWM2 interrupt */
1387#define PWMCLRI_PWM2_BBA (*(volatile unsigned long *) 0x42020108)
1388#define PWMCLRI_PWM2_MSK (0x1 << 2 )
1389#define PWMCLRI_PWM2 (0x1 << 2 )
1390#define PWMCLRI_PWM2_DIS (0x0 << 2 ) /* DIS */
1391#define PWMCLRI_PWM2_EN (0x1 << 2 ) /* EN */
1392
1393/* PWMCLRI[PWM1] - Clear the latched PWM1 interrupt */
1394#define PWMCLRI_PWM1_BBA (*(volatile unsigned long *) 0x42020104)
1395#define PWMCLRI_PWM1_MSK (0x1 << 1 )
1396#define PWMCLRI_PWM1 (0x1 << 1 )
1397#define PWMCLRI_PWM1_DIS (0x0 << 1 ) /* DIS */
1398#define PWMCLRI_PWM1_EN (0x1 << 1 ) /* EN */
1399
1400/* PWMCLRI[PWM0] - Clear the latched PWM0 interrupt */
1401#define PWMCLRI_PWM0_BBA (*(volatile unsigned long *) 0x42020100)
1402#define PWMCLRI_PWM0_MSK (0x1 << 0 )
1403#define PWMCLRI_PWM0 (0x1 << 0 )
1404#define PWMCLRI_PWM0_DIS (0x0 << 0 ) /* DIS */
1405#define PWMCLRI_PWM0_EN (0x1 << 0 ) /* EN */
1406
1407/* Reset Value for PWM0COM0*/
1408#define PWM0COM0_RVAL 0x0
1409
1410/* Reset Value for PWM0COM1*/
1411#define PWM0COM1_RVAL 0x0
1412
1413/* Reset Value for PWM0COM2*/
1414#define PWM0COM2_RVAL 0x0
1415
1416/* Reset Value for PWM0LEN*/
1417#define PWM0LEN_RVAL 0x0
1418
1419/* Reset Value for PWM1COM0*/
1420#define PWM1COM0_RVAL 0x0
1421
1422/* Reset Value for PWM1COM1*/
1423#define PWM1COM1_RVAL 0x0
1424
1425/* Reset Value for PWM1COM2*/
1426#define PWM1COM2_RVAL 0x0
1427
1428/* Reset Value for PWM1LEN*/
1429#define PWM1LEN_RVAL 0x0
1430
1431/* Reset Value for PWM2COM0*/
1432#define PWM2COM0_RVAL 0x0
1433
1434/* Reset Value for PWM2COM1*/
1435#define PWM2COM1_RVAL 0x0
1436
1437/* Reset Value for PWM2COM2*/
1438#define PWM2COM2_RVAL 0x0
1439
1440/* Reset Value for PWM2LEN*/
1441#define PWM2LEN_RVAL 0x0
1442// ------------------------------------------------------------------------------------------------
1443// ----- PWRCTL -----
1444// ------------------------------------------------------------------------------------------------
1445
1446
1447/**
1448 * @brief Power Management Unit (pADI_PWRCTL)
1449 */
1450
1451#if (__NO_MMR_STRUCTS__==0)
1452typedef struct { /*!< pADI_PWRCTL Structure */
1453 __IO uint8_t PWRMOD; /*!< Power modes register */
1454 __I uint8_t RESERVED0[3];
1455 __IO uint16_t PWRKEY; /*!< Key protection for the PWRMOD register. */
1456} ADI_PWRCTL_TypeDef;
1457#else // (__NO_MMR_STRUCTS__==0)
1458#define PWRMOD (*(volatile unsigned char *) 0x40002400)
1459#define PWRKEY (*(volatile unsigned short int *) 0x40002404)
1460#endif // (__NO_MMR_STRUCTS__==0)
1461
1462/* Reset Value for PWRMOD*/
1463#define PWRMOD_RVAL 0x40
1464
1465/* PWRMOD[WICENACK] - For Deepsleep mode only */
1466#define PWRMOD_WICENACK_BBA (*(volatile unsigned long *) 0x4204800C)
1467#define PWRMOD_WICENACK_MSK (0x1 << 3 )
1468#define PWRMOD_WICENACK (0x1 << 3 )
1469#define PWRMOD_WICENACK_DIS (0x0 << 3 ) /* DIS */
1470#define PWRMOD_WICENACK_EN (0x1 << 3 ) /* EN */
1471
1472/* PWRMOD[MOD] - Power Mode */
1473#define PWRMOD_MOD_MSK (0x7 << 0 )
1474#define PWRMOD_MOD_FULLACTIVE (0x0 << 0 ) /* FULLACTIVE */
1475#define PWRMOD_MOD_MCUHALT (0x1 << 0 ) /* MCUHALT */
1476#define PWRMOD_MOD_PERHALT (0x2 << 0 ) /* PERHALT */
1477#define PWRMOD_MOD_SYSHALT (0x3 << 0 ) /* SYSHALT */
1478#define PWRMOD_MOD_TOTALHALT (0x4 << 0 ) /* TOTALHALT */
1479#define PWRMOD_MOD_HIBERNATE (0x5 << 0 ) /* HIBERNATE */
1480
1481/* Reset Value for PWRKEY*/
1482#define PWRKEY_RVAL 0x0
1483
1484/* PWRKEY[VALUE] - Key value */
1485#define PWRKEY_VALUE_MSK (0xFFFF << 0 )
1486#define PWRKEY_VALUE_KEY1 (0x4859 << 0 ) /* KEY1 */
1487#define PWRKEY_VALUE_KEY2 (0xF27B << 0 ) /* KEY2 */
1488// ------------------------------------------------------------------------------------------------
1489// ----- RESET -----
1490// ------------------------------------------------------------------------------------------------
1491
1492
1493/**
1494 * @brief Reset (pADI_RESET)
1495 */
1496
1497#if (__NO_MMR_STRUCTS__==0)
1498typedef struct { /*!< pADI_RESET Structure */
1499
1500 union {
1501 __IO uint8_t RSTSTA; /*!< Reset Status */
1502 __IO uint8_t RSTCLR; /*!< Reset Status Clear */
1503 } ;
1504} ADI_RESET_TypeDef;
1505#else // (__NO_MMR_STRUCTS__==0)
1506#define RSTSTA (*(volatile unsigned char *) 0x40002440)
1507#define RSTCLR (*(volatile unsigned char *) 0x40002440)
1508#endif // (__NO_MMR_STRUCTS__==0)
1509
1510/* Reset Value for RSTSTA*/
1511#define RSTSTA_RVAL 0x1
1512
1513/* RSTSTA[SWRST] - Software reset status bit */
1514#define RSTSTA_SWRST_BBA (*(volatile unsigned long *) 0x4204880C)
1515#define RSTSTA_SWRST_MSK (0x1 << 3 )
1516#define RSTSTA_SWRST (0x1 << 3 )
1517#define RSTSTA_SWRST_CLR (0x0 << 3 ) /* CLR */
1518#define RSTSTA_SWRST_SET (0x1 << 3 ) /* SET */
1519
1520/* RSTSTA[WDRST] - Watchdog reset status bit */
1521#define RSTSTA_WDRST_BBA (*(volatile unsigned long *) 0x42048808)
1522#define RSTSTA_WDRST_MSK (0x1 << 2 )
1523#define RSTSTA_WDRST (0x1 << 2 )
1524#define RSTSTA_WDRST_CLR (0x0 << 2 ) /* CLR */
1525#define RSTSTA_WDRST_SET (0x1 << 2 ) /* SET */
1526
1527/* RSTSTA[EXTRST] - External reset status bit */
1528#define RSTSTA_EXTRST_BBA (*(volatile unsigned long *) 0x42048804)
1529#define RSTSTA_EXTRST_MSK (0x1 << 1 )
1530#define RSTSTA_EXTRST (0x1 << 1 )
1531#define RSTSTA_EXTRST_CLR (0x0 << 1 ) /* CLR */
1532#define RSTSTA_EXTRST_SET (0x1 << 1 ) /* SET */
1533
1534/* RSTSTA[POR] - Power-on reset status bit */
1535#define RSTSTA_POR_BBA (*(volatile unsigned long *) 0x42048800)
1536#define RSTSTA_POR_MSK (0x1 << 0 )
1537#define RSTSTA_POR (0x1 << 0 )
1538#define RSTSTA_POR_CLR (0x0 << 0 ) /* CLR */
1539#define RSTSTA_POR_SET (0x1 << 0 ) /* SET */
1540
1541/* Reset Value for RSTCLR*/
1542#define RSTCLR_RVAL 0x1
1543
1544/* RSTCLR[SWRST] - Software reset status bit */
1545#define RSTCLR_SWRST_BBA (*(volatile unsigned long *) 0x4204880C)
1546#define RSTCLR_SWRST_MSK (0x1 << 3 )
1547#define RSTCLR_SWRST (0x1 << 3 )
1548#define RSTCLR_SWRST_DIS (0x0 << 3 ) /* DIS */
1549#define RSTCLR_SWRST_EN (0x1 << 3 ) /* EN */
1550
1551/* RSTCLR[WDRST] - Watchdog reset status bit */
1552#define RSTCLR_WDRST_BBA (*(volatile unsigned long *) 0x42048808)
1553#define RSTCLR_WDRST_MSK (0x1 << 2 )
1554#define RSTCLR_WDRST (0x1 << 2 )
1555#define RSTCLR_WDRST_DIS (0x0 << 2 ) /* DIS */
1556#define RSTCLR_WDRST_EN (0x1 << 2 ) /* EN */
1557
1558/* RSTCLR[EXTRST] - External reset status bit */
1559#define RSTCLR_EXTRST_BBA (*(volatile unsigned long *) 0x42048804)
1560#define RSTCLR_EXTRST_MSK (0x1 << 1 )
1561#define RSTCLR_EXTRST (0x1 << 1 )
1562#define RSTCLR_EXTRST_DIS (0x0 << 1 ) /* DIS */
1563#define RSTCLR_EXTRST_EN (0x1 << 1 ) /* EN */
1564
1565/* RSTCLR[POR] - Power-on reset status bit */
1566#define RSTCLR_POR_BBA (*(volatile unsigned long *) 0x42048800)
1567#define RSTCLR_POR_MSK (0x1 << 0 )
1568#define RSTCLR_POR (0x1 << 0 )
1569#define RSTCLR_POR_DIS (0x0 << 0 ) /* DIS */
1570#define RSTCLR_POR_EN (0x1 << 0 ) /* EN */
1571// ------------------------------------------------------------------------------------------------
1572// ----- INTERRUPT -----
1573// ------------------------------------------------------------------------------------------------
1574
1575
1576/**
1577 * @brief Interrupts (pADI_INTERRUPT)
1578 */
1579
1580#if (__NO_MMR_STRUCTS__==0)
1581typedef struct { /*!< pADI_INTERRUPT Structure */
1582 __IO uint16_t EI0CFG; /*!< External Interrupt configuration register 0 */
1583 __I uint16_t RESERVED0;
1584 __IO uint16_t EI1CFG; /*!< External Interrupt configuration register 1 */
1585 __I uint16_t RESERVED1[5];
1586 __IO uint16_t EICLR; /*!< External Interrupts Clear register */
1587} ADI_INTERRUPT_TypeDef;
1588#else // (__NO_MMR_STRUCTS__==0)
1589#define EI0CFG (*(volatile unsigned short int *) 0x40002420)
1590#define EI1CFG (*(volatile unsigned short int *) 0x40002424)
1591#define EICLR (*(volatile unsigned short int *) 0x40002430)
1592#endif // (__NO_MMR_STRUCTS__==0)
1593
1594/* Reset Value for EI0CFG*/
1595#define EI0CFG_RVAL 0x0
1596
1597/* EI0CFG[IRQ3EN] - External Interrupt 3 Enable */
1598#define EI0CFG_IRQ3EN_BBA (*(volatile unsigned long *) 0x4204843C)
1599#define EI0CFG_IRQ3EN_MSK (0x1 << 15 )
1600#define EI0CFG_IRQ3EN (0x1 << 15 )
1601#define EI0CFG_IRQ3EN_DIS (0x0 << 15 ) /* DIS */
1602#define EI0CFG_IRQ3EN_EN (0x1 << 15 ) /* EN */
1603
1604/* EI0CFG[IRQ3MDE] - External Interrupt 0 Mode */
1605#define EI0CFG_IRQ3MDE_MSK (0x7 << 12 )
1606#define EI0CFG_IRQ3MDE_RISE (0x0 << 12 ) /* RISE */
1607#define EI0CFG_IRQ3MDE_FALL (0x1 << 12 ) /* FALL */
1608#define EI0CFG_IRQ3MDE_RISEORFALL (0x2 << 12 ) /* RISEORFALL */
1609#define EI0CFG_IRQ3MDE_HIGHLEVEL (0x3 << 12 ) /* HIGHLEVEL */
1610#define EI0CFG_IRQ3MDE_LOWLEVEL (0x4 << 12 ) /* LOWLEVEL */
1611
1612/* EI0CFG[IRQ2EN] - External Interrupt 2 Enable */
1613#define EI0CFG_IRQ2EN_BBA (*(volatile unsigned long *) 0x4204842C)
1614#define EI0CFG_IRQ2EN_MSK (0x1 << 11 )
1615#define EI0CFG_IRQ2EN (0x1 << 11 )
1616#define EI0CFG_IRQ2EN_DIS (0x0 << 11 ) /* DIS */
1617#define EI0CFG_IRQ2EN_EN (0x1 << 11 ) /* EN */
1618
1619/* EI0CFG[IRQ2MDE] - External Interrupt 2 Mode */
1620#define EI0CFG_IRQ2MDE_MSK (0x7 << 8 )
1621#define EI0CFG_IRQ2MDE_RISE (0x0 << 8 ) /* RISE */
1622#define EI0CFG_IRQ2MDE_FALL (0x1 << 8 ) /* FALL */
1623#define EI0CFG_IRQ2MDE_RISEORFALL (0x2 << 8 ) /* RISEORFALL */
1624#define EI0CFG_IRQ2MDE_HIGHLEVEL (0x3 << 8 ) /* HIGHLEVEL */
1625#define EI0CFG_IRQ2MDE_LOWLEVEL (0x4 << 8 ) /* LOWLEVEL */
1626
1627/* EI0CFG[IRQ1EN] - External Interrupt 1 Enable */
1628#define EI0CFG_IRQ1EN_BBA (*(volatile unsigned long *) 0x4204841C)
1629#define EI0CFG_IRQ1EN_MSK (0x1 << 7 )
1630#define EI0CFG_IRQ1EN (0x1 << 7 )
1631#define EI0CFG_IRQ1EN_DIS (0x0 << 7 ) /* DIS */
1632#define EI0CFG_IRQ1EN_EN (0x1 << 7 ) /* EN */
1633
1634/* EI0CFG[IRQ1MDE] - External Interrupt 1 Mode */
1635#define EI0CFG_IRQ1MDE_MSK (0x7 << 4 )
1636#define EI0CFG_IRQ1MDE_RISE (0x0 << 4 ) /* RISE */
1637#define EI0CFG_IRQ1MDE_FALL (0x1 << 4 ) /* FALL */
1638#define EI0CFG_IRQ1MDE_RISEORFALL (0x2 << 4 ) /* RISEORFALL */
1639#define EI0CFG_IRQ1MDE_HIGHLEVEL (0x3 << 4 ) /* HIGHLEVEL */
1640#define EI0CFG_IRQ1MDE_LOWLEVEL (0x4 << 4 ) /* LOWLEVEL */
1641
1642/* EI0CFG[IRQ0EN] - External Interrupt 0 Enable */
1643#define EI0CFG_IRQ0EN_BBA (*(volatile unsigned long *) 0x4204840C)
1644#define EI0CFG_IRQ0EN_MSK (0x1 << 3 )
1645#define EI0CFG_IRQ0EN (0x1 << 3 )
1646#define EI0CFG_IRQ0EN_DIS (0x0 << 3 ) /* DIS */
1647#define EI0CFG_IRQ0EN_EN (0x1 << 3 ) /* EN */
1648
1649/* EI0CFG[IRQ0MDE] - External Interrupt 0 Mode */
1650#define EI0CFG_IRQ0MDE_MSK (0x7 << 0 )
1651#define EI0CFG_IRQ0MDE_RISE (0x0 << 0 ) /* RISE */
1652#define EI0CFG_IRQ0MDE_FALL (0x1 << 0 ) /* FALL */
1653#define EI0CFG_IRQ0MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL */
1654#define EI0CFG_IRQ0MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL */
1655#define EI0CFG_IRQ0MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL */
1656
1657/* Reset Value for EI1CFG*/
1658#define EI1CFG_RVAL 0x0
1659
1660/* EI1CFG[IRQ7EN] - External Interrupt 7 Enable */
1661#define EI1CFG_IRQ7EN_BBA (*(volatile unsigned long *) 0x420484BC)
1662#define EI1CFG_IRQ7EN_MSK (0x1 << 15 )
1663#define EI1CFG_IRQ7EN (0x1 << 15 )
1664#define EI1CFG_IRQ7EN_DIS (0x0 << 15 ) /* DIS */
1665#define EI1CFG_IRQ7EN_EN (0x1 << 15 ) /* EN */
1666
1667/* EI1CFG[IRQ7MDE] - External Interrupt 7 Mode */
1668#define EI1CFG_IRQ7MDE_MSK (0x7 << 12 )
1669#define EI1CFG_IRQ7MDE_RISE (0x0 << 12 ) /* RISE */
1670#define EI1CFG_IRQ7MDE_FALL (0x1 << 12 ) /* FALL */
1671#define EI1CFG_IRQ7MDE_RISEORFALL (0x2 << 12 ) /* RISEORFALL */
1672#define EI1CFG_IRQ7MDE_HIGHLEVEL (0x3 << 12 ) /* HIGHLEVEL */
1673#define EI1CFG_IRQ7MDE_LOWLEVEL (0x4 << 12 ) /* LOWLEVEL */
1674
1675/* EI1CFG[IRQ6EN] - External Interrupt 6 Enable */
1676#define EI1CFG_IRQ6EN_BBA (*(volatile unsigned long *) 0x420484AC)
1677#define EI1CFG_IRQ6EN_MSK (0x1 << 11 )
1678#define EI1CFG_IRQ6EN (0x1 << 11 )
1679#define EI1CFG_IRQ6EN_DIS (0x0 << 11 ) /* DIS */
1680#define EI1CFG_IRQ6EN_EN (0x1 << 11 ) /* EN */
1681
1682/* EI1CFG[IRQ6MDE] - External Interrupt 6 Mode */
1683#define EI1CFG_IRQ6MDE_MSK (0x7 << 8 )
1684#define EI1CFG_IRQ6MDE_RISE (0x0 << 8 ) /* RISE */
1685#define EI1CFG_IRQ6MDE_FALL (0x1 << 8 ) /* FALL */
1686#define EI1CFG_IRQ6MDE_RISEORFALL (0x2 << 8 ) /* RISEORFALL */
1687#define EI1CFG_IRQ6MDE_HIGHLEVEL (0x3 << 8 ) /* HIGHLEVEL */
1688#define EI1CFG_IRQ6MDE_LOWLEVEL (0x4 << 8 ) /* LOWLEVEL */
1689
1690/* EI1CFG[IRQ5EN] - External Interrupt 5 Enable */
1691#define EI1CFG_IRQ5EN_BBA (*(volatile unsigned long *) 0x4204849C)
1692#define EI1CFG_IRQ5EN_MSK (0x1 << 7 )
1693#define EI1CFG_IRQ5EN (0x1 << 7 )
1694#define EI1CFG_IRQ5EN_DIS (0x0 << 7 ) /* DIS */
1695#define EI1CFG_IRQ5EN_EN (0x1 << 7 ) /* EN */
1696
1697/* EI1CFG[IRQ5MDE] - External Interrupt 5 Mode */
1698#define EI1CFG_IRQ5MDE_MSK (0x7 << 4 )
1699#define EI1CFG_IRQ5MDE_RISE (0x0 << 4 ) /* RISE */
1700#define EI1CFG_IRQ5MDE_FALL (0x1 << 4 ) /* FALL */
1701#define EI1CFG_IRQ5MDE_RISEORFALL (0x2 << 4 ) /* RISEORFALL */
1702#define EI1CFG_IRQ5MDE_HIGHLEVEL (0x3 << 4 ) /* HIGHLEVEL */
1703#define EI1CFG_IRQ5MDE_LOWLEVEL (0x4 << 4 ) /* LOWLEVEL */
1704
1705/* EI1CFG[IRQ4EN] - External Interrupt 4 Enable */
1706#define EI1CFG_IRQ4EN_BBA (*(volatile unsigned long *) 0x4204848C)
1707#define EI1CFG_IRQ4EN_MSK (0x1 << 3 )
1708#define EI1CFG_IRQ4EN (0x1 << 3 )
1709#define EI1CFG_IRQ4EN_DIS (0x0 << 3 ) /* DIS */
1710#define EI1CFG_IRQ4EN_EN (0x1 << 3 ) /* EN */
1711
1712/* EI1CFG[IRQ4MDE] - External Interrupt 4 Mode */
1713#define EI1CFG_IRQ4MDE_MSK (0x7 << 0 )
1714#define EI1CFG_IRQ4MDE_RISE (0x0 << 0 ) /* RISE */
1715#define EI1CFG_IRQ4MDE_FALL (0x1 << 0 ) /* FALL */
1716#define EI1CFG_IRQ4MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL */
1717#define EI1CFG_IRQ4MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL */
1718#define EI1CFG_IRQ4MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL */
1719
1720/* Reset Value for EICLR*/
1721#define EICLR_RVAL 0x0
1722
1723/* EICLR[IRQ7] - Clears External interrupt 7 internal flag */
1724#define EICLR_IRQ7_BBA (*(volatile unsigned long *) 0x4204861C)
1725#define EICLR_IRQ7_MSK (0x1 << 7 )
1726#define EICLR_IRQ7 (0x1 << 7 )
1727#define EICLR_IRQ7_CLR (0x1 << 7 ) /* CLR */
1728
1729/* EICLR[IRQ6] - Clears External interrupt 6 internal flag */
1730#define EICLR_IRQ6_BBA (*(volatile unsigned long *) 0x42048618)
1731#define EICLR_IRQ6_MSK (0x1 << 6 )
1732#define EICLR_IRQ6 (0x1 << 6 )
1733#define EICLR_IRQ6_CLR (0x1 << 6 ) /* CLR */
1734
1735/* EICLR[IRQ5] - Clears External interrupt 5 internal flag */
1736#define EICLR_IRQ5_BBA (*(volatile unsigned long *) 0x42048614)
1737#define EICLR_IRQ5_MSK (0x1 << 5 )
1738#define EICLR_IRQ5 (0x1 << 5 )
1739#define EICLR_IRQ5_CLR (0x1 << 5 ) /* CLR */
1740
1741/* EICLR[IRQ4] - Clears External interrupt 4 internal flag */
1742#define EICLR_IRQ4_BBA (*(volatile unsigned long *) 0x42048610)
1743#define EICLR_IRQ4_MSK (0x1 << 4 )
1744#define EICLR_IRQ4 (0x1 << 4 )
1745#define EICLR_IRQ4_CLR (0x1 << 4 ) /* CLR */
1746
1747/* EICLR[IRQ3] - Clears External interrupt 3 internal flag */
1748#define EICLR_IRQ3_BBA (*(volatile unsigned long *) 0x4204860C)
1749#define EICLR_IRQ3_MSK (0x1 << 3 )
1750#define EICLR_IRQ3 (0x1 << 3 )
1751#define EICLR_IRQ3_CLR (0x1 << 3 ) /* CLR */
1752
1753/* EICLR[IRQ2] - Clears External interrupt 2 internal flag */
1754#define EICLR_IRQ2_BBA (*(volatile unsigned long *) 0x42048608)
1755#define EICLR_IRQ2_MSK (0x1 << 2 )
1756#define EICLR_IRQ2 (0x1 << 2 )
1757#define EICLR_IRQ2_CLR (0x1 << 2 ) /* CLR */
1758
1759/* EICLR[IRQ1] - Clears External interrupt 1 internal flag */
1760#define EICLR_IRQ1_BBA (*(volatile unsigned long *) 0x42048604)
1761#define EICLR_IRQ1_MSK (0x1 << 1 )
1762#define EICLR_IRQ1 (0x1 << 1 )
1763#define EICLR_IRQ1_CLR (0x1 << 1 ) /* CLR */
1764
1765/* EICLR[IRQ0] - Clears External interrupt 0 internal flag */
1766#define EICLR_IRQ0_BBA (*(volatile unsigned long *) 0x42048600)
1767#define EICLR_IRQ0_MSK (0x1 << 0 )
1768#define EICLR_IRQ0 (0x1 << 0 )
1769#define EICLR_IRQ0_CLR (0x1 << 0 ) /* CLR */
1770// ------------------------------------------------------------------------------------------------
1771// ----- WDT -----
1772// ------------------------------------------------------------------------------------------------
1773
1774
1775/**
1776 * @brief Watchdog Timer (pADI_WDT)
1777 */
1778
1779#if (__NO_MMR_STRUCTS__==0)
1780typedef struct { /*!< pADI_WDT Structure */
1781 __IO uint16_t T3LD; /*!< Load value. */
1782 __I uint16_t RESERVED0;
1783 __IO uint16_t T3VAL; /*!< "Current count value, read only." */
1784 __I uint16_t RESERVED1;
1785 __IO uint16_t T3CON; /*!< Control Register */
1786 __I uint16_t RESERVED2;
1787 __IO uint16_t T3CLRI; /*!< "Clear interrupt, write only." */
1788 __I uint16_t RESERVED3[5];
1789 __IO uint16_t T3STA; /*!< "Status register, read only." */
1790} ADI_WDT_TypeDef;
1791#else // (__NO_MMR_STRUCTS__==0)
1792#define T3LD (*(volatile unsigned short int *) 0x40002580)
1793#define T3VAL (*(volatile unsigned short int *) 0x40002584)
1794#define T3CON (*(volatile unsigned short int *) 0x40002588)
1795#define T3CLRI (*(volatile unsigned short int *) 0x4000258C)
1796#define T3STA (*(volatile unsigned short int *) 0x40002598)
1797#endif // (__NO_MMR_STRUCTS__==0)
1798
1799/* Reset Value for T3LD*/
1800#define T3LD_RVAL 0x1000
1801
1802/* T3LD[VALUE] - Current Value */
1803#define T3LD_VALUE_MSK (0xFFFF << 0 )
1804
1805/* Reset Value for T3VAL*/
1806#define T3VAL_RVAL 0x1000
1807
1808/* T3VAL[VALUE] - Current Value */
1809#define T3VAL_VALUE_MSK (0xFFFF << 0 )
1810
1811/* Reset Value for T3CON*/
1812#define T3CON_RVAL 0xE9
1813
1814/* T3CON[MOD] - Mode */
1815#define T3CON_MOD_BBA (*(volatile unsigned long *) 0x4204B118)
1816#define T3CON_MOD_MSK (0x1 << 6 )
1817#define T3CON_MOD (0x1 << 6 )
1818#define T3CON_MOD_FREERUN (0x0 << 6 ) /* FREERUN */
1819#define T3CON_MOD_PERIODIC (0x1 << 6 ) /* PERIODIC */
1820
1821/* T3CON[ENABLE] - Enable */
1822#define T3CON_ENABLE_BBA (*(volatile unsigned long *) 0x4204B114)
1823#define T3CON_ENABLE_MSK (0x1 << 5 )
1824#define T3CON_ENABLE (0x1 << 5 )
1825#define T3CON_ENABLE_DIS (0x0 << 5 ) /* DIS */
1826#define T3CON_ENABLE_EN (0x1 << 5 ) /* EN */
1827
1828/* T3CON[PRE] - Prescaler */
1829#define T3CON_PRE_MSK (0x3 << 2 )
1830#define T3CON_PRE_DIV1 (0x0 << 2 ) /* DIV1 */
1831#define T3CON_PRE_DIV16 (0x1 << 2 ) /* DIV16 */
1832#define T3CON_PRE_DIV256 (0x2 << 2 ) /* DIV256 */
1833#define T3CON_PRE_DIV4096 (0x3 << 2 ) /* DIV4096 */
1834
1835/* T3CON[IRQ] - Timer Interrupt , */
1836#define T3CON_IRQ_BBA (*(volatile unsigned long *) 0x4204B104)
1837#define T3CON_IRQ_MSK (0x1 << 1 )
1838#define T3CON_IRQ (0x1 << 1 )
1839#define T3CON_IRQ_DIS (0x0 << 1 ) /* DIS */
1840#define T3CON_IRQ_EN (0x1 << 1 ) /* EN */
1841
1842/* T3CON[PD] - Power down clear */
1843#define T3CON_PD_BBA (*(volatile unsigned long *) 0x4204B100)
1844#define T3CON_PD_MSK (0x1 << 0 )
1845#define T3CON_PD (0x1 << 0 )
1846#define T3CON_PD_DIS (0x0 << 0 ) /* DIS */
1847#define T3CON_PD_EN (0x1 << 0 ) /* EN */
1848
1849/* Reset Value for T3CLRI*/
1850#define T3CLRI_RVAL 0x0
1851
1852/* T3CLRI[VALUE] - Clear Watchdog */
1853#define T3CLRI_VALUE_MSK (0xFFFF << 0 )
1854#define T3CLRI_VALUE_CLR (0xCCCC << 0 ) /* CLR */
1855
1856/* Reset Value for T3STA*/
1857#define T3STA_RVAL 0x20
1858
1859/* T3STA[LOCK] - Lock status bit */
1860#define T3STA_LOCK_BBA (*(volatile unsigned long *) 0x4204B310)
1861#define T3STA_LOCK_MSK (0x1 << 4 )
1862#define T3STA_LOCK (0x1 << 4 )
1863#define T3STA_LOCK_CLR (0x0 << 4 ) /* CLR */
1864#define T3STA_LOCK_SET (0x1 << 4 ) /* SET */
1865
1866/* T3STA[CON] - T3CON write sync in progress */
1867#define T3STA_CON_BBA (*(volatile unsigned long *) 0x4204B30C)
1868#define T3STA_CON_MSK (0x1 << 3 )
1869#define T3STA_CON (0x1 << 3 )
1870#define T3STA_CON_CLR (0x0 << 3 ) /* CLR */
1871#define T3STA_CON_SET (0x1 << 3 ) /* SET */
1872
1873/* T3STA[LD] - T3LD write sync in progress */
1874#define T3STA_LD_BBA (*(volatile unsigned long *) 0x4204B308)
1875#define T3STA_LD_MSK (0x1 << 2 )
1876#define T3STA_LD (0x1 << 2 )
1877#define T3STA_LD_CLR (0x0 << 2 ) /* CLR */
1878#define T3STA_LD_SET (0x1 << 2 ) /* SET */
1879
1880/* T3STA[CLRI] - T3CLRI write sync in progress */
1881#define T3STA_CLRI_BBA (*(volatile unsigned long *) 0x4204B304)
1882#define T3STA_CLRI_MSK (0x1 << 1 )
1883#define T3STA_CLRI (0x1 << 1 )
1884#define T3STA_CLRI_CLR (0x0 << 1 ) /* CLR */
1885#define T3STA_CLRI_SET (0x1 << 1 ) /* SET */
1886
1887/* T3STA[IRQ] - Interrupt Pending */
1888#define T3STA_IRQ_BBA (*(volatile unsigned long *) 0x4204B300)
1889#define T3STA_IRQ_MSK (0x1 << 0 )
1890#define T3STA_IRQ (0x1 << 0 )
1891#define T3STA_IRQ_CLR (0x0 << 0 ) /* CLR */
1892#define T3STA_IRQ_SET (0x1 << 0 ) /* SET */
1893// ------------------------------------------------------------------------------------------------
1894// ----- WUT -----
1895// ------------------------------------------------------------------------------------------------
1896
1897
1898/**
1899 * @brief WakeUp Timer (pADI_WUT)
1900 */
1901
1902#if (__NO_MMR_STRUCTS__==0)
1903typedef struct { /*!< pADI_WUT Structure */
1904 __IO uint16_t T2VAL0; /*!< Current count value LSB */
1905 __I uint16_t RESERVED0;
1906 __IO uint16_t T2VAL1; /*!< Current count value MSB */
1907 __I uint16_t RESERVED1;
1908 __IO uint16_t T2CON; /*!< Control Register */
1909 __I uint16_t RESERVED2;
1910 __IO uint16_t T2INC; /*!< 12-bit register. Wake up field A */
1911 __I uint16_t RESERVED3;
1912 __IO uint16_t T2WUFB0; /*!< Wake up field B LSB */
1913 __I uint16_t RESERVED4;
1914 __IO uint16_t T2WUFB1; /*!< Wake up field B MSB */
1915 __I uint16_t RESERVED5;
1916 __IO uint16_t T2WUFC0; /*!< Wake up field C LSB */
1917 __I uint16_t RESERVED6;
1918 __IO uint16_t T2WUFC1; /*!< Wake up field C MSB */
1919 __I uint16_t RESERVED7;
1920 __IO uint16_t T2WUFD0; /*!< Wake up field D LSB */
1921 __I uint16_t RESERVED8;
1922 __IO uint16_t T2WUFD1; /*!< Wake up field D MSB */
1923 __I uint16_t RESERVED9;
1924 __IO uint16_t T2IEN; /*!< Interrupt enable */
1925 __I uint16_t RESERVED10;
1926 __IO uint16_t T2STA; /*!< Status */
1927 __I uint16_t RESERVED11;
1928 __IO uint16_t T2CLRI; /*!< Clear interrupts. Write only. */
1929 __I uint16_t RESERVED12[5];
1930 __IO uint16_t T2WUFA0; /*!< Wake up field A LSB. */
1931 __I uint16_t RESERVED13;
1932 __IO uint16_t T2WUFA1; /*!< Wake up field A MSB. */
1933} ADI_WUT_TypeDef;
1934#else // (__NO_MMR_STRUCTS__==0)
1935#define T2VAL0 (*(volatile unsigned short int *) 0x40002500)
1936#define T2VAL1 (*(volatile unsigned short int *) 0x40002504)
1937#define T2CON (*(volatile unsigned short int *) 0x40002508)
1938#define T2INC (*(volatile unsigned short int *) 0x4000250C)
1939#define T2WUFB0 (*(volatile unsigned short int *) 0x40002510)
1940#define T2WUFB1 (*(volatile unsigned short int *) 0x40002514)
1941#define T2WUFC0 (*(volatile unsigned short int *) 0x40002518)
1942#define T2WUFC1 (*(volatile unsigned short int *) 0x4000251C)
1943#define T2WUFD0 (*(volatile unsigned short int *) 0x40002520)
1944#define T2WUFD1 (*(volatile unsigned short int *) 0x40002524)
1945#define T2IEN (*(volatile unsigned short int *) 0x40002528)
1946#define T2STA (*(volatile unsigned short int *) 0x4000252C)
1947#define T2CLRI (*(volatile unsigned short int *) 0x40002530)
1948#define T2WUFA0 (*(volatile unsigned short int *) 0x4000253C)
1949#define T2WUFA1 (*(volatile unsigned short int *) 0x40002540)
1950#endif // (__NO_MMR_STRUCTS__==0)
1951
1952/* Reset Value for T2VAL0*/
1953#define T2VAL0_RVAL 0x0
1954
1955/* T2VAL0[VALUE] - Current Value */
1956#define T2VAL0_VALUE_MSK (0xFFFF << 0 )
1957
1958/* Reset Value for T2VAL1*/
1959#define T2VAL1_RVAL 0x0
1960
1961/* T2VAL1[VALUE] - Current Value */
1962#define T2VAL1_VALUE_MSK (0xFFFF << 0 )
1963
1964/* Reset Value for T2CON*/
1965#define T2CON_RVAL 0x40
1966
1967/* T2CON[STOPINC] - Stop wake up field A being updated */
1968#define T2CON_STOPINC_BBA (*(volatile unsigned long *) 0x4204A12C)
1969#define T2CON_STOPINC_MSK (0x1 << 11 )
1970#define T2CON_STOPINC (0x1 << 11 )
1971#define T2CON_STOPINC_DIS (0x0 << 11 ) /* DIS */
1972#define T2CON_STOPINC_EN (0x1 << 11 ) /* EN */
1973
1974/* T2CON[CLK] - Clock */
1975#define T2CON_CLK_MSK (0x3 << 9 )
1976#define T2CON_CLK_PCLK (0x0 << 9 ) /* PCLK */
1977#define T2CON_CLK_LFXTAL (0x1 << 9 ) /* LFXTAL */
1978#define T2CON_CLK_LFOSC (0x2 << 9 ) /* LFOSC */
1979#define T2CON_CLK_EXTCLK (0x3 << 9 ) /* EXTCLK */
1980
1981/* T2CON[WUEN] - WUEN */
1982#define T2CON_WUEN_BBA (*(volatile unsigned long *) 0x4204A120)
1983#define T2CON_WUEN_MSK (0x1 << 8 )
1984#define T2CON_WUEN (0x1 << 8 )
1985#define T2CON_WUEN_DIS (0x0 << 8 ) /* DIS */
1986#define T2CON_WUEN_EN (0x1 << 8 ) /* EN */
1987
1988/* T2CON[ENABLE] - Enable */
1989#define T2CON_ENABLE_BBA (*(volatile unsigned long *) 0x4204A11C)
1990#define T2CON_ENABLE_MSK (0x1 << 7 )
1991#define T2CON_ENABLE (0x1 << 7 )
1992#define T2CON_ENABLE_DIS (0x0 << 7 ) /* DIS */
1993#define T2CON_ENABLE_EN (0x1 << 7 ) /* EN */
1994
1995/* T2CON[MOD] - Mode */
1996#define T2CON_MOD_BBA (*(volatile unsigned long *) 0x4204A118)
1997#define T2CON_MOD_MSK (0x1 << 6 )
1998#define T2CON_MOD (0x1 << 6 )
1999#define T2CON_MOD_PERIODIC (0x0 << 6 ) /* PERIODIC */
2000#define T2CON_MOD_FREERUN (0x1 << 6 ) /* FREERUN */
2001
2002/* T2CON[FREEZE] - Freeze */
2003#define T2CON_FREEZE_BBA (*(volatile unsigned long *) 0x4204A10C)
2004#define T2CON_FREEZE_MSK (0x1 << 3 )
2005#define T2CON_FREEZE (0x1 << 3 )
2006#define T2CON_FREEZE_DIS (0x0 << 3 ) /* DIS */
2007#define T2CON_FREEZE_EN (0x1 << 3 ) /* EN */
2008
2009/* T2CON[PRE] - Prescaler */
2010#define T2CON_PRE_MSK (0x3 << 0 )
2011#define T2CON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
2012#define T2CON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
2013#define T2CON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
2014#define T2CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 */
2015
2016/* Reset Value for T2INC*/
2017#define T2INC_RVAL 0xC8
2018
2019/* T2INC[VALUE] - 12 bit value */
2020#define T2INC_VALUE_MSK (0xFFF << 0 )
2021
2022/* Reset Value for T2WUFB0*/
2023#define T2WUFB0_RVAL 0x1FFF
2024
2025/* T2WUFB0[VALUE] - Current Value */
2026#define T2WUFB0_VALUE_MSK (0xFFFF << 0 )
2027
2028/* Reset Value for T2WUFB1*/
2029#define T2WUFB1_RVAL 0x0
2030
2031/* T2WUFB1[VALUE] - Current Value */
2032#define T2WUFB1_VALUE_MSK (0xFFFF << 0 )
2033
2034/* Reset Value for T2WUFC0*/
2035#define T2WUFC0_RVAL 0x2FFF
2036
2037/* T2WUFC0[VALUE] - Current Value */
2038#define T2WUFC0_VALUE_MSK (0xFFFF << 0 )
2039
2040/* Reset Value for T2WUFC1*/
2041#define T2WUFC1_RVAL 0x0
2042
2043/* T2WUFC1[VALUE] - Current Value */
2044#define T2WUFC1_VALUE_MSK (0xFFFF << 0 )
2045
2046/* Reset Value for T2WUFD0*/
2047#define T2WUFD0_RVAL 0x3FFF
2048
2049/* T2WUFD0[VALUE] - Current Value */
2050#define T2WUFD0_VALUE_MSK (0xFFFF << 0 )
2051
2052/* Reset Value for T2WUFD1*/
2053#define T2WUFD1_RVAL 0x0
2054
2055/* T2WUFD1[VALUE] - Current Value */
2056#define T2WUFD1_VALUE_MSK (0xFFFF << 0 )
2057
2058/* Reset Value for T2IEN*/
2059#define T2IEN_RVAL 0x0
2060
2061/* T2IEN[ROLL] - Enable interrupt on Rollover */
2062#define T2IEN_ROLL_BBA (*(volatile unsigned long *) 0x4204A510)
2063#define T2IEN_ROLL_MSK (0x1 << 4 )
2064#define T2IEN_ROLL (0x1 << 4 )
2065#define T2IEN_ROLL_DIS (0x0 << 4 ) /* DIS */
2066#define T2IEN_ROLL_EN (0x1 << 4 ) /* EN */
2067
2068/* T2IEN[WUFD] - Enable interrupt on WUFD */
2069#define T2IEN_WUFD_BBA (*(volatile unsigned long *) 0x4204A50C)
2070#define T2IEN_WUFD_MSK (0x1 << 3 )
2071#define T2IEN_WUFD (0x1 << 3 )
2072#define T2IEN_WUFD_DIS (0x0 << 3 ) /* DIS */
2073#define T2IEN_WUFD_EN (0x1 << 3 ) /* EN */
2074
2075/* T2IEN[WUFC] - Enable interrupt on WUFC */
2076#define T2IEN_WUFC_BBA (*(volatile unsigned long *) 0x4204A508)
2077#define T2IEN_WUFC_MSK (0x1 << 2 )
2078#define T2IEN_WUFC (0x1 << 2 )
2079#define T2IEN_WUFC_DIS (0x0 << 2 ) /* DIS */
2080#define T2IEN_WUFC_EN (0x1 << 2 ) /* EN */
2081
2082/* T2IEN[WUFB] - Enable interrupt on WUFB */
2083#define T2IEN_WUFB_BBA (*(volatile unsigned long *) 0x4204A504)
2084#define T2IEN_WUFB_MSK (0x1 << 1 )
2085#define T2IEN_WUFB (0x1 << 1 )
2086#define T2IEN_WUFB_DIS (0x0 << 1 ) /* DIS */
2087#define T2IEN_WUFB_EN (0x1 << 1 ) /* EN */
2088
2089/* T2IEN[WUFA] - Enable interrupt on WUFA */
2090#define T2IEN_WUFA_BBA (*(volatile unsigned long *) 0x4204A500)
2091#define T2IEN_WUFA_MSK (0x1 << 0 )
2092#define T2IEN_WUFA (0x1 << 0 )
2093#define T2IEN_WUFA_DIS (0x0 << 0 ) /* DIS */
2094#define T2IEN_WUFA_EN (0x1 << 0 ) /* EN */
2095
2096/* Reset Value for T2STA*/
2097#define T2STA_RVAL 0x0
2098
2099/* T2STA[CON] - Sync */
2100#define T2STA_CON_BBA (*(volatile unsigned long *) 0x4204A5A0)
2101#define T2STA_CON_MSK (0x1 << 8 )
2102#define T2STA_CON (0x1 << 8 )
2103#define T2STA_CON_CLR (0x0 << 8 ) /* CLR */
2104#define T2STA_CON_SET (0x1 << 8 ) /* SET */
2105
2106/* T2STA[FREEZE] - Timer Value Freeze */
2107#define T2STA_FREEZE_BBA (*(volatile unsigned long *) 0x4204A59C)
2108#define T2STA_FREEZE_MSK (0x1 << 7 )
2109#define T2STA_FREEZE (0x1 << 7 )
2110#define T2STA_FREEZE_CLR (0x0 << 7 ) /* CLR */
2111#define T2STA_FREEZE_SET (0x1 << 7 ) /* SET */
2112
2113/* T2STA[ROLL] - Rollover Interrupt */
2114#define T2STA_ROLL_BBA (*(volatile unsigned long *) 0x4204A590)
2115#define T2STA_ROLL_MSK (0x1 << 4 )
2116#define T2STA_ROLL (0x1 << 4 )
2117#define T2STA_ROLL_CLR (0x0 << 4 ) /* CLR */
2118#define T2STA_ROLL_SET (0x1 << 4 ) /* SET */
2119
2120/* T2STA[WUFD] - WUFD Interrupt */
2121#define T2STA_WUFD_BBA (*(volatile unsigned long *) 0x4204A58C)
2122#define T2STA_WUFD_MSK (0x1 << 3 )
2123#define T2STA_WUFD (0x1 << 3 )
2124#define T2STA_WUFD_CLR (0x0 << 3 ) /* CLR */
2125#define T2STA_WUFD_SET (0x1 << 3 ) /* SET */
2126
2127/* T2STA[WUFC] - WUFC Interrupt */
2128#define T2STA_WUFC_BBA (*(volatile unsigned long *) 0x4204A588)
2129#define T2STA_WUFC_MSK (0x1 << 2 )
2130#define T2STA_WUFC (0x1 << 2 )
2131#define T2STA_WUFC_CLR (0x0 << 2 ) /* CLR */
2132#define T2STA_WUFC_SET (0x1 << 2 ) /* SET */
2133
2134/* T2STA[WUFB] - WUFB Interrupt */
2135#define T2STA_WUFB_BBA (*(volatile unsigned long *) 0x4204A584)
2136#define T2STA_WUFB_MSK (0x1 << 1 )
2137#define T2STA_WUFB (0x1 << 1 )
2138#define T2STA_WUFB_CLR (0x0 << 1 ) /* CLR */
2139#define T2STA_WUFB_SET (0x1 << 1 ) /* SET */
2140
2141/* T2STA[WUFA] - WUFA Interrupt */
2142#define T2STA_WUFA_BBA (*(volatile unsigned long *) 0x4204A580)
2143#define T2STA_WUFA_MSK (0x1 << 0 )
2144#define T2STA_WUFA (0x1 << 0 )
2145#define T2STA_WUFA_CLR (0x0 << 0 ) /* CLR */
2146#define T2STA_WUFA_SET (0x1 << 0 ) /* SET */
2147
2148/* Reset Value for T2CLRI*/
2149#define T2CLRI_RVAL 0x0
2150
2151/* T2CLRI[ROLL] - Clear interrupt on Rollover */
2152#define T2CLRI_ROLL_BBA (*(volatile unsigned long *) 0x4204A610)
2153#define T2CLRI_ROLL_MSK (0x1 << 4 )
2154#define T2CLRI_ROLL (0x1 << 4 )
2155#define T2CLRI_ROLL_CLR (0x1 << 4 ) /* CLR */
2156
2157/* T2CLRI[WUFD] - Clear interrupt on WUFD */
2158#define T2CLRI_WUFD_BBA (*(volatile unsigned long *) 0x4204A60C)
2159#define T2CLRI_WUFD_MSK (0x1 << 3 )
2160#define T2CLRI_WUFD (0x1 << 3 )
2161#define T2CLRI_WUFD_CLR (0x1 << 3 ) /* CLR */
2162
2163/* T2CLRI[WUFC] - Clear interrupt on WUFC */
2164#define T2CLRI_WUFC_BBA (*(volatile unsigned long *) 0x4204A608)
2165#define T2CLRI_WUFC_MSK (0x1 << 2 )
2166#define T2CLRI_WUFC (0x1 << 2 )
2167#define T2CLRI_WUFC_CLR (0x1 << 2 ) /* CLR */
2168
2169/* T2CLRI[WUFB] - Clear interrupt on WUFB */
2170#define T2CLRI_WUFB_BBA (*(volatile unsigned long *) 0x4204A604)
2171#define T2CLRI_WUFB_MSK (0x1 << 1 )
2172#define T2CLRI_WUFB (0x1 << 1 )
2173#define T2CLRI_WUFB_CLR (0x1 << 1 ) /* CLR */
2174
2175/* T2CLRI[WUFA] - Clear interrupt on WUFA */
2176#define T2CLRI_WUFA_BBA (*(volatile unsigned long *) 0x4204A600)
2177#define T2CLRI_WUFA_MSK (0x1 << 0 )
2178#define T2CLRI_WUFA (0x1 << 0 )
2179#define T2CLRI_WUFA_CLR (0x1 << 0 ) /* CLR */
2180
2181/* Reset Value for T2WUFA0*/
2182#define T2WUFA0_RVAL 0x1900
2183
2184/* T2WUFA0[VALUE] - Current Value */
2185#define T2WUFA0_VALUE_MSK (0xFFFF << 0 )
2186
2187/* Reset Value for T2WUFA1*/
2188#define T2WUFA1_RVAL 0x0
2189
2190/* T2WUFA1[VALUE] - Current Value */
2191#define T2WUFA1_VALUE_MSK (0xFFFF << 0 )
2192// ------------------------------------------------------------------------------------------------
2193// ----- CLKCTL -----
2194// ------------------------------------------------------------------------------------------------
2195
2196
2197/**
2198 * @brief Clock Control (pADI_CLKCTL)
2199 */
2200
2201#if (__NO_MMR_STRUCTS__==0)
2202typedef struct { /*!< pADI_CLKCTL Structure */
2203 __IO uint16_t CLKCON0; /*!< System clocking architecture control register */
2204 __I uint16_t RESERVED0;
2205 __IO uint16_t CLKCON1; /*!< System Clocks Control Register 1 */
2206 __I uint16_t RESERVED1[19];
2207 __IO uint16_t CLKDIS; /*!< System Clocks Control Register 1 */
2208 __I uint16_t RESERVED2[7];
2209 __IO uint16_t CLKCON2; /*!< System Clocks Control Register 2 */
2210 __I uint16_t RESERVED3[489];
2211 __IO uint8_t XOSCCON; /*!< Crystal Oscillator control */
2212 __I uint8_t RESERVED4[51];
2213 __IO uint16_t CLKSYSDIV; /*!< Sys Clock div2 Register */
2214} ADI_CLKCTL_TypeDef;
2215#else // (__NO_MMR_STRUCTS__==0)
2216#define CLKCON0 (*(volatile unsigned short int *) 0x40002000)
2217#define CLKCON1 (*(volatile unsigned short int *) 0x40002004)
2218#define CLKDIS (*(volatile unsigned short int *) 0x4000202C)
2219#define CLKCON2 (*(volatile unsigned short int *) 0x4000203C)
2220#define XOSCCON (*(volatile unsigned char *) 0x40002410)
2221#define CLKSYSDIV (*(volatile unsigned short int *) 0x40002444)
2222#endif // (__NO_MMR_STRUCTS__==0)
2223
2224/* Reset Value for CLKCON0*/
2225#define CLKCON0_RVAL 0x0
2226
2227/* CLKCON0[CLKOUT] - GPIO output clock multiplexer select bits */
2228#define CLKCON0_CLKOUT_MSK (0x7 << 5 )
2229#define CLKCON0_CLKOUT_UCLKCG (0x0 << 5 ) /* UCLKCG */
2230#define CLKCON0_CLKOUT_UCLK (0x1 << 5 ) /* UCLK */
2231#define CLKCON0_CLKOUT_PCLK (0x2 << 5 ) /* PCLK */
2232#define CLKCON0_CLKOUT_HFOSC (0x5 << 5 ) /* HFOSC */
2233#define CLKCON0_CLKOUT_LFOSC (0x6 << 5 ) /* LFOSC */
2234#define CLKCON0_CLKOUT_LFXTAL (0x7 << 5 ) /* LFXTAL */
2235
2236/* CLKCON0[CLKMUX] - Digital subsystem clock source select bits. */
2237#define CLKCON0_CLKMUX_MSK (0x3 << 3 )
2238#define CLKCON0_CLKMUX_HFOSC (0x0 << 3 ) /* HFOSC */
2239#define CLKCON0_CLKMUX_LFXTAL (0x1 << 3 ) /* LFXTAL */
2240#define CLKCON0_CLKMUX_LFOSC (0x2 << 3 ) /* LFOSC */
2241#define CLKCON0_CLKMUX_EXTCLK (0x3 << 3 ) /* EXTCLK */
2242
2243/* CLKCON0[CD] - Clock divide bits */
2244#define CLKCON0_CD_MSK (0x7 << 0 )
2245#define CLKCON0_CD_DIV1 (0x0 << 0 ) /* DIV1 */
2246#define CLKCON0_CD_DIV2 (0x1 << 0 ) /* DIV2 */
2247#define CLKCON0_CD_DIV4 (0x2 << 0 ) /* DIV4 */
2248#define CLKCON0_CD_DIV8 (0x3 << 0 ) /* DIV8 */
2249#define CLKCON0_CD_DIV16 (0x4 << 0 ) /* DIV16 */
2250#define CLKCON0_CD_DIV32 (0x5 << 0 ) /* DIV32 */
2251#define CLKCON0_CD_DIV64 (0x6 << 0 ) /* DIV64 */
2252#define CLKCON0_CD_DIV128 (0x7 << 0 ) /* DIV128 */
2253
2254/* Reset Value for CLKCON1*/
2255#define CLKCON1_RVAL 0x0
2256
2257/* CLKCON1[PWMCD] - Clock divide bits for PWM system clock */
2258#define CLKCON1_PWMCD_MSK (0x7 << 12 )
2259#define CLKCON1_PWMCD_DIV1 (0x0 << 12 ) /* DIV1 */
2260#define CLKCON1_PWMCD_DIV2 (0x1 << 12 ) /* DIV2 */
2261#define CLKCON1_PWMCD_DIV4 (0x2 << 12 ) /* DIV4 */
2262#define CLKCON1_PWMCD_DIV8 (0x3 << 12 ) /* DIV8 */
2263#define CLKCON1_PWMCD_DIV16 (0x4 << 12 ) /* DIV16 */
2264#define CLKCON1_PWMCD_DIV32 (0x5 << 12 ) /* DIV32 */
2265#define CLKCON1_PWMCD_DIV64 (0x6 << 12 ) /* DIV64 */
2266#define CLKCON1_PWMCD_DIV128 (0x7 << 12 ) /* DIV128 */
2267
2268/* CLKCON1[UARTCD] - Clock divide bits for UART system clock */
2269#define CLKCON1_UARTCD_MSK (0x7 << 9 )
2270#define CLKCON1_UARTCD_DIV1 (0x0 << 9 ) /* DIV1 */
2271#define CLKCON1_UARTCD_DIV2 (0x1 << 9 ) /* DIV2 */
2272#define CLKCON1_UARTCD_DIV4 (0x2 << 9 ) /* DIV4 */
2273#define CLKCON1_UARTCD_DIV8 (0x3 << 9 ) /* DIV8 */
2274#define CLKCON1_UARTCD_DIV16 (0x4 << 9 ) /* DIV16 */
2275#define CLKCON1_UARTCD_DIV32 (0x5 << 9 ) /* DIV32 */
2276#define CLKCON1_UARTCD_DIV64 (0x6 << 9 ) /* DIV64 */
2277#define CLKCON1_UARTCD_DIV128 (0x7 << 9 ) /* DIV128 */
2278
2279/* CLKCON1[I2CCD] - Clock divide bits for I2C system clock */
2280#define CLKCON1_I2CCD_MSK (0x7 << 6 )
2281#define CLKCON1_I2CCD_DIV1 (0x0 << 6 ) /* DIV1 */
2282#define CLKCON1_I2CCD_DIV2 (0x1 << 6 ) /* DIV2 */
2283#define CLKCON1_I2CCD_DIV4 (0x2 << 6 ) /* DIV4 */
2284#define CLKCON1_I2CCD_DIV8 (0x3 << 6 ) /* DIV8 */
2285#define CLKCON1_I2CCD_DIV16 (0x4 << 6 ) /* DIV16 */
2286#define CLKCON1_I2CCD_DIV32 (0x5 << 6 ) /* DIV32 */
2287#define CLKCON1_I2CCD_DIV64 (0x6 << 6 ) /* DIV64 */
2288#define CLKCON1_I2CCD_DIV128 (0x7 << 6 ) /* DIV128 */
2289
2290/* CLKCON1[SPI1CD] - Clock divide bits for SPI1 system clock */
2291#define CLKCON1_SPI1CD_MSK (0x7 << 3 )
2292#define CLKCON1_SPI1CD_DIV1 (0x0 << 3 ) /* DIV1 */
2293#define CLKCON1_SPI1CD_DIV2 (0x1 << 3 ) /* DIV2 */
2294#define CLKCON1_SPI1CD_DIV4 (0x2 << 3 ) /* DIV4 */
2295#define CLKCON1_SPI1CD_DIV8 (0x3 << 3 ) /* DIV8 */
2296#define CLKCON1_SPI1CD_DIV16 (0x4 << 3 ) /* DIV16 */
2297#define CLKCON1_SPI1CD_DIV32 (0x5 << 3 ) /* DIV32 */
2298#define CLKCON1_SPI1CD_DIV64 (0x6 << 3 ) /* DIV64 */
2299#define CLKCON1_SPI1CD_DIV128 (0x7 << 3 ) /* DIV128 */
2300
2301/* CLKCON1[SPI0CD] - Clock divide bits for SPI0 system clock */
2302#define CLKCON1_SPI0CD_MSK (0x7 << 0 )
2303#define CLKCON1_SPI0CD_DIV1 (0x0 << 0 ) /* DIV1 */
2304#define CLKCON1_SPI0CD_DIV2 (0x1 << 0 ) /* DIV2 */
2305#define CLKCON1_SPI0CD_DIV4 (0x2 << 0 ) /* DIV4 */
2306#define CLKCON1_SPI0CD_DIV8 (0x3 << 0 ) /* DIV8 */
2307#define CLKCON1_SPI0CD_DIV16 (0x4 << 0 ) /* DIV16 */
2308#define CLKCON1_SPI0CD_DIV32 (0x5 << 0 ) /* DIV32 */
2309#define CLKCON1_SPI0CD_DIV64 (0x6 << 0 ) /* DIV64 */
2310#define CLKCON1_SPI0CD_DIV128 (0x7 << 0 ) /* DIV128 */
2311
2312/* Reset Value for CLKDIS*/
2313#define CLKDIS_RVAL 0xFFFF
2314
2315/* CLKDIS[DISADCCLK] - Disable ADC system clock */
2316#define CLKDIS_DISADCCLK_BBA (*(volatile unsigned long *) 0x420405A4)
2317#define CLKDIS_DISADCCLK_MSK (0x1 << 9 )
2318#define CLKDIS_DISADCCLK (0x1 << 9 )
2319#define CLKDIS_DISADCCLK_DIS (0x0 << 9 ) /* DIS */
2320#define CLKDIS_DISADCCLK_EN (0x1 << 9 ) /* EN */
2321
2322/* CLKDIS[DISDMACLK] - Disable DMA system clock */
2323#define CLKDIS_DISDMACLK_BBA (*(volatile unsigned long *) 0x420405A0)
2324#define CLKDIS_DISDMACLK_MSK (0x1 << 8 )
2325#define CLKDIS_DISDMACLK (0x1 << 8 )
2326#define CLKDIS_DISDMACLK_DIS (0x0 << 8 ) /* DIS */
2327#define CLKDIS_DISDMACLK_EN (0x1 << 8 ) /* EN */
2328
2329/* CLKDIS[DISDACCLK] - Disable DAC system clock */
2330#define CLKDIS_DISDACCLK_BBA (*(volatile unsigned long *) 0x4204059C)
2331#define CLKDIS_DISDACCLK_MSK (0x1 << 7 )
2332#define CLKDIS_DISDACCLK (0x1 << 7 )
2333#define CLKDIS_DISDACCLK_DIS (0x0 << 7 ) /* DIS */
2334#define CLKDIS_DISDACCLK_EN (0x1 << 7 ) /* EN */
2335
2336/* CLKDIS[DIST1CLK] - Disable Timer 1 system clock */
2337#define CLKDIS_DIST1CLK_BBA (*(volatile unsigned long *) 0x42040598)
2338#define CLKDIS_DIST1CLK_MSK (0x1 << 6 )
2339#define CLKDIS_DIST1CLK (0x1 << 6 )
2340#define CLKDIS_DIST1CLK_DIS (0x0 << 6 ) /* DIS */
2341#define CLKDIS_DIST1CLK_EN (0x1 << 6 ) /* EN */
2342
2343/* CLKDIS[DIST0CLK] - Disable Timer 0 system clock */
2344#define CLKDIS_DIST0CLK_BBA (*(volatile unsigned long *) 0x42040594)
2345#define CLKDIS_DIST0CLK_MSK (0x1 << 5 )
2346#define CLKDIS_DIST0CLK (0x1 << 5 )
2347#define CLKDIS_DIST0CLK_DIS (0x0 << 5 ) /* DIS */
2348#define CLKDIS_DIST0CLK_EN (0x1 << 5 ) /* EN */
2349
2350/* CLKDIS[DISPWMCLK] - Disable PWM system clock */
2351#define CLKDIS_DISPWMCLK_BBA (*(volatile unsigned long *) 0x42040590)
2352#define CLKDIS_DISPWMCLK_MSK (0x1 << 4 )
2353#define CLKDIS_DISPWMCLK (0x1 << 4 )
2354#define CLKDIS_DISPWMCLK_DIS (0x0 << 4 ) /* DIS */
2355#define CLKDIS_DISPWMCLK_EN (0x1 << 4 ) /* EN */
2356
2357/* CLKDIS[DISUARTCLK] - Disable UART system clock */
2358#define CLKDIS_DISUARTCLK_BBA (*(volatile unsigned long *) 0x4204058C)
2359#define CLKDIS_DISUARTCLK_MSK (0x1 << 3 )
2360#define CLKDIS_DISUARTCLK (0x1 << 3 )
2361#define CLKDIS_DISUARTCLK_DIS (0x0 << 3 ) /* DIS */
2362#define CLKDIS_DISUARTCLK_EN (0x1 << 3 ) /* EN */
2363
2364/* CLKDIS[DISI2CCLK] - Disable I2C system clock */
2365#define CLKDIS_DISI2CCLK_BBA (*(volatile unsigned long *) 0x42040588)
2366#define CLKDIS_DISI2CCLK_MSK (0x1 << 2 )
2367#define CLKDIS_DISI2CCLK (0x1 << 2 )
2368#define CLKDIS_DISI2CCLK_DIS (0x0 << 2 ) /* DIS */
2369#define CLKDIS_DISI2CCLK_EN (0x1 << 2 ) /* EN */
2370
2371/* CLKDIS[DISSPI1CLK] - Disable SPI1 system clock */
2372#define CLKDIS_DISSPI1CLK_BBA (*(volatile unsigned long *) 0x42040584)
2373#define CLKDIS_DISSPI1CLK_MSK (0x1 << 1 )
2374#define CLKDIS_DISSPI1CLK (0x1 << 1 )
2375#define CLKDIS_DISSPI1CLK_DIS (0x0 << 1 ) /* DIS */
2376#define CLKDIS_DISSPI1CLK_EN (0x1 << 1 ) /* EN */
2377
2378/* CLKDIS[DISSPI0CLK] - Disable SPI0 system clock bits */
2379#define CLKDIS_DISSPI0CLK_BBA (*(volatile unsigned long *) 0x42040580)
2380#define CLKDIS_DISSPI0CLK_MSK (0x1 << 0 )
2381#define CLKDIS_DISSPI0CLK (0x1 << 0 )
2382#define CLKDIS_DISSPI0CLK_DIS (0x0 << 0 ) /* DIS */
2383#define CLKDIS_DISSPI0CLK_EN (0x1 << 0 ) /* EN */
2384
2385/* CLKCON2[DISUART1CLK] - Disable UART1 system clock */
2386#define CLKCON2_DISUART1CLK_BBA (*(volatile unsigned long *) 0x42040780)
2387#define CLKCON2_DISUART1CLK_MSK (0x1 << 0 )
2388#define CLKCON2_DISUART1CLK (0x1 << 0 )
2389#define CLKCON2_DISUART1CLK_DIS (0x0 << 0 ) /* DIS */
2390#define CLKCON2_DISUART1CLK_EN (0x1 << 0 ) /* EN */
2391
2392/* CLKCON2[DISUART2CLK] - Disable UART2 system clock */
2393#define CLKCON2_DISUART2CLK_BBA (*(volatile unsigned long *) 0x42040784)
2394#define CLKCON2_DISUART2CLK_MSK (0x1 << 1 )
2395#define CLKCON2_DISUART2CLK (0x1 << 1 )
2396#define CLKCON2_DISUART2CLK_DIS (0x0 << 1 ) /* DIS */
2397#define CLKCON2_DISUART2CLK_EN (0x1 << 1 ) /* EN */
2398
2399/* CLKCON2[UART1CD] - Clock divide bits for UART1 system clock */
2400#define CLKCON2_UART1CD_MSK (0x7 << 8 )
2401#define CLKCON2_UART1CD_DIV1 (0x0 << 8 ) /* DIV1 */
2402#define CLKCON2_UART1CD_DIV2 (0x1 << 8 ) /* DIV2 */
2403#define CLKCON2_UART1CD_DIV4 (0x2 << 8 ) /* DIV4 */
2404#define CLKCON2_UART1CD_DIV8 (0x3 << 8 ) /* DIV8 */
2405#define CLKCON2_UART1CD_DIV16 (0x4 << 8 ) /* DIV16 */
2406#define CLKCON2_UART1CD_DIV32 (0x5 << 8 ) /* DIV32 */
2407#define CLKCON2_UART1CD_DIV64 (0x6 << 8 ) /* DIV64 */
2408#define CLKCON2_UART1CD_DIV128 (0x7 << 8 ) /* DIV128 */
2409
2410/* CLKCON2[UART2CD] - Clock divide bits for UART2 system clock */
2411#define CLKCON2_UART2CD_MSK (0x7 << 11 )
2412#define CLKCON2_UART2CD_DIV1 (0x0 << 11 ) /* DIV1 */
2413#define CLKCON2_UART2CD_DIV2 (0x1 << 11 ) /* DIV2 */
2414#define CLKCON2_UART2CD_DIV4 (0x2 << 11 ) /* DIV4 */
2415#define CLKCON2_UART2CD_DIV8 (0x3 << 11 ) /* DIV8 */
2416#define CLKCON2_UART2CD_DIV16 (0x4 << 11 ) /* DIV16 */
2417#define CLKCON2_UART2CD_DIV32 (0x5 << 11 ) /* DIV32 */
2418#define CLKCON2_UART2CD_DIV64 (0x6 << 11 ) /* DIV64 */
2419#define CLKCON2_UART2CD_DIV128 (0x7 << 11 ) /* DIV128 */
2420
2421/* CLKCON2[DACCD] - Clock divide bit for DAC system clock */
2422#define CLKCON2_DACCD_BBA (*(volatile unsigned long *) 0x420407B8)
2423#define CLKCON2_DACCD_MSK (0x1 << 14 )
2424#define CLKCON2_DACCD (0x1 << 14 )
2425#define CLKCON2_DACCD_DIV8 (0x0 << 14 ) /* DIV8 */
2426#define CLKCON2_DACCD_DIV16 (0x1 << 14 ) /* DIV16 */
2427
2428/* Reset Value for XOSCCON*/
2429#define XOSCCON_RVAL 0x0
2430
2431/* XOSCCON[DIV2] - Divide by two enable */
2432#define XOSCCON_DIV2_BBA (*(volatile unsigned long *) 0x42048208)
2433#define XOSCCON_DIV2_MSK (0x1 << 2 )
2434#define XOSCCON_DIV2 (0x1 << 2 )
2435#define XOSCCON_DIV2_DIS (0x0 << 2 ) /* DIS */
2436#define XOSCCON_DIV2_EN (0x1 << 2 ) /* EN */
2437
2438/* XOSCCON[ENABLE] - Crystal oscillator circuit enable (Enable the oscillator circuitry.) */
2439#define XOSCCON_ENABLE_BBA (*(volatile unsigned long *) 0x42048200)
2440#define XOSCCON_ENABLE_MSK (0x1 << 0 )
2441#define XOSCCON_ENABLE (0x1 << 0 )
2442#define XOSCCON_ENABLE_DIS (0x0 << 0 ) /* DIS */
2443#define XOSCCON_ENABLE_EN (0x1 << 0 ) /* EN */
2444
2445/* Reset Value for CLKSYSDIV*/
2446//#define CLKSYSDIV_RVAL 0x0
2447
2448/* CLKSYSDIV[UCLKCD] - bits */
2449#define CLKSYSDIV_UCLKCD_MSK (0x3 << 0 )
2450#define CLKSYSDIV_UCLKCD_DIV1 (0x0 << 0 )
2451#define CLKSYSDIV_UCLKCD_DIV2 (0x1 << 0 )
2452#define CLKSYSDIV_UCLKCD_DIV4 (0x2 << 0 )
2453#define CLKSYSDIV_UCLKCD_DIV8 (0x3 << 0 )
2454// ------------------------------------------------------------------------------------------------
2455// ----- FEE -----
2456// ------------------------------------------------------------------------------------------------
2457
2458
2459/**
2460 * @brief Flash Controller (pADI_FEE)
2461 */
2462
2463#if (__NO_MMR_STRUCTS__==0)
2464typedef struct { /*!< pADI_FEE Structure */
2465 __IO uint16_t FEESTA; /*!< Status Register */
2466 __I uint16_t RESERVED0;
2467 __IO uint16_t FEECON0; /*!< Command Control Register */
2468 __I uint16_t RESERVED1;
2469 __IO uint16_t FEECMD; /*!< Command register */
2470 __I uint16_t RESERVED2[3];
2471 __IO uint16_t FEEADR0L; /*!< Low Page (Lower 16 bits) */
2472 __I uint16_t RESERVED3;
2473 __IO uint16_t FEEADR0H; /*!< Low Page (Upper 16 bits) */
2474 __I uint16_t RESERVED4;
2475 __IO uint16_t FEEADR1L; /*!< Hi Page (Lower 16 bits) */
2476 __I uint16_t RESERVED5;
2477 __IO uint16_t FEEADR1H; /*!< Hi Page (Upper 16 bits) */
2478 __I uint16_t RESERVED6;
2479 __IO uint16_t FEEKEY; /*!< Key */
2480 __I uint16_t RESERVED7[3];
2481 __IO uint16_t FEEPROL; /*!< Write Protection (Lower 16 bits) */
2482 __I uint16_t RESERVED8;
2483 __IO uint16_t FEEPROH; /*!< Write Protection (Upper 16 bits) */
2484 __I uint16_t RESERVED9;
2485 __IO uint16_t FEESIGL; /*!< Signature (Lower 16 bits) */
2486 __I uint16_t RESERVED10;
2487 __IO uint16_t FEESIGH; /*!< Signature (Upper 16 bits) */
2488 __I uint16_t RESERVED11;
2489 __IO uint16_t FEECON1; /*!< User Setup register */
2490 __I uint16_t RESERVED12[7];
2491 __IO uint16_t FEEADRAL; /*!< Abort address (Lower 16 bits) */
2492 __I uint16_t RESERVED13;
2493 __IO uint16_t FEEADRAH; /*!< Abort address (Upper 16 bits) */
2494 __I uint16_t RESERVED14[21];
2495 __IO uint16_t FEEAEN0; /*!< Lower 16 bits of the sys irq abort enable register. */
2496 __I uint16_t RESERVED15;
2497 __IO uint16_t FEEAEN1; /*!< Upper 16 bits of the sys irq abort enable register. */
2498 __I uint16_t RESERVED16;
2499 __IO uint16_t FEEAEN2; /*!< Upper 32..47 bits of the sys irq abort enable register. */
2500} ADI_FEE_TypeDef;
2501#else // (__NO_MMR_STRUCTS__==0)
2502#define FEESTA (*(volatile unsigned short int *) 0x40002800)
2503#define FEECON0 (*(volatile unsigned short int *) 0x40002804)
2504#define FEECMD (*(volatile unsigned short int *) 0x40002808)
2505#define FEEADR0L (*(volatile unsigned short int *) 0x40002810)
2506#define FEEADR0H (*(volatile unsigned short int *) 0x40002814)
2507#define FEEADR1L (*(volatile unsigned short int *) 0x40002818)
2508#define FEEADR1H (*(volatile unsigned short int *) 0x4000281C)
2509#define FEEKEY (*(volatile unsigned short int *) 0x40002820)
2510#define FEEPROL (*(volatile unsigned short int *) 0x40002828)
2511#define FEEPROH (*(volatile unsigned short int *) 0x4000282C)
2512#define FEESIGL (*(volatile unsigned short int *) 0x40002830)
2513#define FEESIGH (*(volatile unsigned short int *) 0x40002834)
2514#define FEECON1 (*(volatile unsigned short int *) 0x40002838)
2515#define FEEADRAL (*(volatile unsigned short int *) 0x40002848)
2516#define FEEADRAH (*(volatile unsigned short int *) 0x4000284C)
2517#define FEEAEN0 (*(volatile unsigned short int *) 0x40002878)
2518#define FEEAEN1 (*(volatile unsigned short int *) 0x4000287C)
2519#define FEEAEN2 (*(volatile unsigned short int *) 0x40002880)
2520#endif // (__NO_MMR_STRUCTS__==0)
2521
2522/* Reset Value for FEESTA*/
2523#define FEESTA_RVAL 0x0
2524
2525/* FEESTA[SIGNERR] - Info space signature check on reset error */
2526#define FEESTA_SIGNERR_BBA (*(volatile unsigned long *) 0x42050018)
2527#define FEESTA_SIGNERR_MSK (0x1 << 6 )
2528#define FEESTA_SIGNERR (0x1 << 6 )
2529#define FEESTA_SIGNERR_CLR (0x0 << 6 ) /* CLR */
2530#define FEESTA_SIGNERR_SET (0x1 << 6 ) /* SET */
2531
2532/* FEESTA[CMDRES] - Command result */
2533#define FEESTA_CMDRES_MSK (0x3 << 4 )
2534#define FEESTA_CMDRES_SUCCESS (0x0 << 4 ) /* SUCCESS */
2535#define FEESTA_CMDRES_PROTECTED (0x1 << 4 ) /* PROTECTED */
2536#define FEESTA_CMDRES_VERIFYERR (0x2 << 4 ) /* VERIFYERR */
2537#define FEESTA_CMDRES_ABORT (0x3 << 4 ) /* ABORT */
2538
2539/* FEESTA[WRDONE] - Write Complete */
2540#define FEESTA_WRDONE_BBA (*(volatile unsigned long *) 0x4205000C)
2541#define FEESTA_WRDONE_MSK (0x1 << 3 )
2542#define FEESTA_WRDONE (0x1 << 3 )
2543#define FEESTA_WRDONE_CLR (0x0 << 3 ) /* CLR */
2544#define FEESTA_WRDONE_SET (0x1 << 3 ) /* SET */
2545
2546/* FEESTA[CMDDONE] - Command complete */
2547#define FEESTA_CMDDONE_BBA (*(volatile unsigned long *) 0x42050008)
2548#define FEESTA_CMDDONE_MSK (0x1 << 2 )
2549#define FEESTA_CMDDONE (0x1 << 2 )
2550#define FEESTA_CMDDONE_CLR (0x0 << 2 ) /* CLR */
2551#define FEESTA_CMDDONE_SET (0x1 << 2 ) /* SET */
2552
2553/* FEESTA[WRBUSY] - Write busy */
2554#define FEESTA_WRBUSY_BBA (*(volatile unsigned long *) 0x42050004)
2555#define FEESTA_WRBUSY_MSK (0x1 << 1 )
2556#define FEESTA_WRBUSY (0x1 << 1 )
2557#define FEESTA_WRBUSY_CLR (0x0 << 1 ) /* CLR */
2558#define FEESTA_WRBUSY_SET (0x1 << 1 ) /* SET */
2559
2560/* FEESTA[CMDBUSY] - Command busy */
2561#define FEESTA_CMDBUSY_BBA (*(volatile unsigned long *) 0x42050000)
2562#define FEESTA_CMDBUSY_MSK (0x1 << 0 )
2563#define FEESTA_CMDBUSY (0x1 << 0 )
2564#define FEESTA_CMDBUSY_CLR (0x0 << 0 ) /* CLR */
2565#define FEESTA_CMDBUSY_SET (0x1 << 0 ) /* SET */
2566
2567/* Reset Value for FEECON0*/
2568#define FEECON0_RVAL 0x0
2569
2570/* FEECON0[WREN] - Write enable. */
2571#define FEECON0_WREN_BBA (*(volatile unsigned long *) 0x42050088)
2572#define FEECON0_WREN_MSK (0x1 << 2 )
2573#define FEECON0_WREN (0x1 << 2 )
2574#define FEECON0_WREN_DIS (0x0 << 2 ) /* DIS */
2575#define FEECON0_WREN_EN (0x1 << 2 ) /* EN */
2576
2577/* FEECON0[IENERR] - Error interrupt enable */
2578#define FEECON0_IENERR_BBA (*(volatile unsigned long *) 0x42050084)
2579#define FEECON0_IENERR_MSK (0x1 << 1 )
2580#define FEECON0_IENERR (0x1 << 1 )
2581#define FEECON0_IENERR_DIS (0x0 << 1 ) /* DIS */
2582#define FEECON0_IENERR_EN (0x1 << 1 ) /* EN */
2583
2584/* FEECON0[IENCMD] - Command complete interrupt enable */
2585#define FEECON0_IENCMD_BBA (*(volatile unsigned long *) 0x42050080)
2586#define FEECON0_IENCMD_MSK (0x1 << 0 )
2587#define FEECON0_IENCMD (0x1 << 0 )
2588#define FEECON0_IENCMD_DIS (0x0 << 0 ) /* DIS */
2589#define FEECON0_IENCMD_EN (0x1 << 0 ) /* EN */
2590
2591/* Reset Value for FEECMD*/
2592#define FEECMD_RVAL 0x0
2593
2594/* FEECMD[CMD] - Command */
2595#define FEECMD_CMD_MSK (0xF << 0 )
2596#define FEECMD_CMD_IDLE (0x0 << 0 ) /* IDLE - No command executed */
2597#define FEECMD_CMD_ERASEPAGE (0x1 << 0 ) /* ERASEPAGE - Erase Page */
2598#define FEECMD_CMD_SIGN (0x2 << 0 ) /* SIGN - Sign Range */
2599#define FEECMD_CMD_MASSERASE (0x3 << 0 ) /* MASSERASE - Mass Erase User Space */
2600#define FEECMD_CMD_ABORT (0x4 << 0 ) /* ABORT - Abort a running command */
2601
2602/* Reset Value for FEEADR0L*/
2603#define FEEADR0L_RVAL 0x0
2604
2605/* FEEADR0L[VALUE] - Value */
2606#define FEEADR0L_VALUE_MSK (0xFFFF << 0 )
2607
2608/* Reset Value for FEEADR0H*/
2609#define FEEADR0H_RVAL 0x0
2610
2611/* FEEADR0H[VALUE] - Value */
2612#define FEEADR0H_VALUE_MSK (0x3 << 0 )
2613
2614/* Reset Value for FEEADR1L*/
2615#define FEEADR1L_RVAL 0x0
2616
2617/* FEEADR1L[VALUE] - Value */
2618#define FEEADR1L_VALUE_MSK (0xFFFF << 0 )
2619
2620/* Reset Value for FEEADR1H*/
2621#define FEEADR1H_RVAL 0x0
2622
2623/* FEEADR1H[VALUE] - Value */
2624#define FEEADR1H_VALUE_MSK (0x3 << 0 )
2625
2626/* Reset Value for FEEKEY*/
2627#define FEEKEY_RVAL 0x0
2628
2629/* FEEKEY[VALUE] - Value */
2630#define FEEKEY_VALUE_MSK (0xFFFF << 0 )
2631#define FEEKEY_VALUE_USERKEY1 (0xF456 << 0 ) /* USERKEY1 */
2632#define FEEKEY_VALUE_USERKEY2 (0xF123 << 0 ) /* USERKEY2 */
2633
2634/* Reset Value for FEEPROL*/
2635#define FEEPROL_RVAL 0xFFFF
2636
2637/* FEEPROL[VALUE] - Value */
2638#define FEEPROL_VALUE_MSK (0xFFFF << 0 )
2639
2640/* Reset Value for FEEPROH*/
2641#define FEEPROH_RVAL 0xFFFF
2642
2643/* FEEPROH[VALUE] - Value */
2644#define FEEPROH_VALUE_MSK (0xFFFF << 0 )
2645
2646/* Reset Value for FEESIGL*/
2647#define FEESIGL_RVAL 0xFFFF
2648
2649/* FEESIGL[VALUE] - Value */
2650#define FEESIGL_VALUE_MSK (0xFFFF << 0 )
2651
2652/* Reset Value for FEESIGH*/
2653#define FEESIGH_RVAL 0xFFFF
2654
2655/* FEESIGH[VALUE] - Value */
2656#define FEESIGH_VALUE_MSK (0xFF << 0 )
2657
2658/* Reset Value for FEECON1*/
2659#define FEECON1_RVAL 0x1
2660
2661/* FEECON1[DBG] - Serial Wire debug enable , */
2662#define FEECON1_DBG_BBA (*(volatile unsigned long *) 0x42050700)
2663#define FEECON1_DBG_MSK (0x1 << 0 )
2664#define FEECON1_DBG (0x1 << 0 )
2665#define FEECON1_DBG_DIS (0x0 << 0 ) /* DIS */
2666#define FEECON1_DBG_EN (0x1 << 0 ) /* EN */
2667
2668/* Reset Value for FEEADRAL*/
2669#define FEEADRAL_RVAL 0x800
2670
2671/* FEEADRAL[VALUE] - Value */
2672#define FEEADRAL_VALUE_MSK (0xFFFF << 0 )
2673
2674/* Reset Value for FEEADRAH*/
2675#define FEEADRAH_RVAL 0x2
2676
2677/* FEEADRAH[VALUE] - Value */
2678#define FEEADRAH_VALUE_MSK (0xFFFF << 0 )
2679
2680/* Reset Value for FEEAEN0*/
2681#define FEEAEN0_RVAL 0x0
2682
2683/* FEEAEN0[SINC2] - */
2684#define FEEAEN0_SINC2_BBA (*(volatile unsigned long *) 0x42050F3C)
2685#define FEEAEN0_SINC2_MSK (0x1 << 15 )
2686#define FEEAEN0_SINC2 (0x1 << 15 )
2687#define FEEAEN0_SINC2_DIS (0x0 << 15 ) /* DIS */
2688#define FEEAEN0_SINC2_EN (0x1 << 15 ) /* EN */
2689
2690/* FEEAEN0[ADC1] - */
2691#define FEEAEN0_ADC1_BBA (*(volatile unsigned long *) 0x42050F38)
2692#define FEEAEN0_ADC1_MSK (0x1 << 14 )
2693#define FEEAEN0_ADC1 (0x1 << 14 )
2694#define FEEAEN0_ADC1_DIS (0x0 << 14 ) /* DIS */
2695#define FEEAEN0_ADC1_EN (0x1 << 14 ) /* EN */
2696
2697/* FEEAEN0[ADC0] - */
2698#define FEEAEN0_ADC0_BBA (*(volatile unsigned long *) 0x42050F34)
2699#define FEEAEN0_ADC0_MSK (0x1 << 13 )
2700#define FEEAEN0_ADC0 (0x1 << 13 )
2701#define FEEAEN0_ADC0_DIS (0x0 << 13 ) /* DIS */
2702#define FEEAEN0_ADC0_EN (0x1 << 13 ) /* EN */
2703
2704/* FEEAEN0[T1] - */
2705#define FEEAEN0_T1_BBA (*(volatile unsigned long *) 0x42050F30)
2706#define FEEAEN0_T1_MSK (0x1 << 12 )
2707#define FEEAEN0_T1 (0x1 << 12 )
2708#define FEEAEN0_T1_DIS (0x0 << 12 ) /* DIS */
2709#define FEEAEN0_T1_EN (0x1 << 12 ) /* EN */
2710
2711/* FEEAEN0[T0] - */
2712#define FEEAEN0_T0_BBA (*(volatile unsigned long *) 0x42050F2C)
2713#define FEEAEN0_T0_MSK (0x1 << 11 )
2714#define FEEAEN0_T0 (0x1 << 11 )
2715#define FEEAEN0_T0_DIS (0x0 << 11 ) /* DIS */
2716#define FEEAEN0_T0_EN (0x1 << 11 ) /* EN */
2717
2718/* FEEAEN0[T3] - */
2719#define FEEAEN0_T3_BBA (*(volatile unsigned long *) 0x42050F24)
2720#define FEEAEN0_T3_MSK (0x1 << 9 )
2721#define FEEAEN0_T3 (0x1 << 9 )
2722#define FEEAEN0_T3_DIS (0x0 << 9 ) /* DIS */
2723#define FEEAEN0_T3_EN (0x1 << 9 ) /* EN */
2724
2725/* FEEAEN0[EXTINT7] - */
2726#define FEEAEN0_EXTINT7_BBA (*(volatile unsigned long *) 0x42050F20)
2727#define FEEAEN0_EXTINT7_MSK (0x1 << 8 )
2728#define FEEAEN0_EXTINT7 (0x1 << 8 )
2729#define FEEAEN0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
2730#define FEEAEN0_EXTINT7_EN (0x1 << 8 ) /* EN */
2731
2732/* FEEAEN0[EXTINT6] - */
2733#define FEEAEN0_EXTINT6_BBA (*(volatile unsigned long *) 0x42050F1C)
2734#define FEEAEN0_EXTINT6_MSK (0x1 << 7 )
2735#define FEEAEN0_EXTINT6 (0x1 << 7 )
2736#define FEEAEN0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
2737#define FEEAEN0_EXTINT6_EN (0x1 << 7 ) /* EN */
2738
2739/* FEEAEN0[EXTINT5] - */
2740#define FEEAEN0_EXTINT5_BBA (*(volatile unsigned long *) 0x42050F18)
2741#define FEEAEN0_EXTINT5_MSK (0x1 << 6 )
2742#define FEEAEN0_EXTINT5 (0x1 << 6 )
2743#define FEEAEN0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
2744#define FEEAEN0_EXTINT5_EN (0x1 << 6 ) /* EN */
2745
2746/* FEEAEN0[EXTINT4] - */
2747#define FEEAEN0_EXTINT4_BBA (*(volatile unsigned long *) 0x42050F14)
2748#define FEEAEN0_EXTINT4_MSK (0x1 << 5 )
2749#define FEEAEN0_EXTINT4 (0x1 << 5 )
2750#define FEEAEN0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
2751#define FEEAEN0_EXTINT4_EN (0x1 << 5 ) /* EN */
2752
2753/* FEEAEN0[EXTINT3] - */
2754#define FEEAEN0_EXTINT3_BBA (*(volatile unsigned long *) 0x42050F10)
2755#define FEEAEN0_EXTINT3_MSK (0x1 << 4 )
2756#define FEEAEN0_EXTINT3 (0x1 << 4 )
2757#define FEEAEN0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
2758#define FEEAEN0_EXTINT3_EN (0x1 << 4 ) /* EN */
2759
2760/* FEEAEN0[EXTINT2] - */
2761#define FEEAEN0_EXTINT2_BBA (*(volatile unsigned long *) 0x42050F0C)
2762#define FEEAEN0_EXTINT2_MSK (0x1 << 3 )
2763#define FEEAEN0_EXTINT2 (0x1 << 3 )
2764#define FEEAEN0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
2765#define FEEAEN0_EXTINT2_EN (0x1 << 3 ) /* EN */
2766
2767/* FEEAEN0[EXTINT1] - */
2768#define FEEAEN0_EXTINT1_BBA (*(volatile unsigned long *) 0x42050F08)
2769#define FEEAEN0_EXTINT1_MSK (0x1 << 2 )
2770#define FEEAEN0_EXTINT1 (0x1 << 2 )
2771#define FEEAEN0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
2772#define FEEAEN0_EXTINT1_EN (0x1 << 2 ) /* EN */
2773
2774/* FEEAEN0[EXTINT0] - */
2775#define FEEAEN0_EXTINT0_BBA (*(volatile unsigned long *) 0x42050F04)
2776#define FEEAEN0_EXTINT0_MSK (0x1 << 1 )
2777#define FEEAEN0_EXTINT0 (0x1 << 1 )
2778#define FEEAEN0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
2779#define FEEAEN0_EXTINT0_EN (0x1 << 1 ) /* EN */
2780
2781/* FEEAEN0[T2] - */
2782#define FEEAEN0_T2_BBA (*(volatile unsigned long *) 0x42050F00)
2783#define FEEAEN0_T2_MSK (0x1 << 0 )
2784#define FEEAEN0_T2 (0x1 << 0 )
2785#define FEEAEN0_T2_DIS (0x0 << 0 ) /* DIS */
2786#define FEEAEN0_T2_EN (0x1 << 0 ) /* EN */
2787
2788/* Reset Value for FEEAEN1*/
2789#define FEEAEN1_RVAL 0x0
2790
2791/* FEEAEN1[DMADAC] - */
2792#define FEEAEN1_DMADAC_BBA (*(volatile unsigned long *) 0x42050FBC)
2793#define FEEAEN1_DMADAC_MSK (0x1 << 15 )
2794#define FEEAEN1_DMADAC (0x1 << 15 )
2795#define FEEAEN1_DMADAC_DIS (0x0 << 15 ) /* DIS */
2796#define FEEAEN1_DMADAC_EN (0x1 << 15 ) /* EN */
2797
2798/* FEEAEN1[DMAI2CMRX] - */
2799#define FEEAEN1_DMAI2CMRX_BBA (*(volatile unsigned long *) 0x42050FB8)
2800#define FEEAEN1_DMAI2CMRX_MSK (0x1 << 14 )
2801#define FEEAEN1_DMAI2CMRX (0x1 << 14 )
2802#define FEEAEN1_DMAI2CMRX_DIS (0x0 << 14 ) /* DIS */
2803#define FEEAEN1_DMAI2CMRX_EN (0x1 << 14 ) /* EN */
2804
2805/* FEEAEN1[DMAI2CMTX] - */
2806#define FEEAEN1_DMAI2CMTX_BBA (*(volatile unsigned long *) 0x42050FB4)
2807#define FEEAEN1_DMAI2CMTX_MSK (0x1 << 13 )
2808#define FEEAEN1_DMAI2CMTX (0x1 << 13 )
2809#define FEEAEN1_DMAI2CMTX_DIS (0x0 << 13 ) /* DIS */
2810#define FEEAEN1_DMAI2CMTX_EN (0x1 << 13 ) /* EN */
2811
2812/* FEEAEN1[DMAI2CSRX] - */
2813#define FEEAEN1_DMAI2CSRX_BBA (*(volatile unsigned long *) 0x42050FB0)
2814#define FEEAEN1_DMAI2CSRX_MSK (0x1 << 12 )
2815#define FEEAEN1_DMAI2CSRX (0x1 << 12 )
2816#define FEEAEN1_DMAI2CSRX_DIS (0x0 << 12 ) /* DIS */
2817#define FEEAEN1_DMAI2CSRX_EN (0x1 << 12 ) /* EN */
2818
2819/* FEEAEN1[DMAI2CSTX] - */
2820#define FEEAEN1_DMAI2CSTX_BBA (*(volatile unsigned long *) 0x42050FAC)
2821#define FEEAEN1_DMAI2CSTX_MSK (0x1 << 11 )
2822#define FEEAEN1_DMAI2CSTX (0x1 << 11 )
2823#define FEEAEN1_DMAI2CSTX_DIS (0x0 << 11 ) /* DIS */
2824#define FEEAEN1_DMAI2CSTX_EN (0x1 << 11 ) /* EN */
2825
2826/* FEEAEN1[DMAUARTRX] - */
2827#define FEEAEN1_DMAUARTRX_BBA (*(volatile unsigned long *) 0x42050FA8)
2828#define FEEAEN1_DMAUARTRX_MSK (0x1 << 10 )
2829#define FEEAEN1_DMAUARTRX (0x1 << 10 )
2830#define FEEAEN1_DMAUARTRX_DIS (0x0 << 10 ) /* DIS */
2831#define FEEAEN1_DMAUARTRX_EN (0x1 << 10 ) /* EN */
2832
2833/* FEEAEN1[DMAUARTTX] - */
2834#define FEEAEN1_DMAUARTTX_BBA (*(volatile unsigned long *) 0x42050FA4)
2835#define FEEAEN1_DMAUARTTX_MSK (0x1 << 9 )
2836#define FEEAEN1_DMAUARTTX (0x1 << 9 )
2837#define FEEAEN1_DMAUARTTX_DIS (0x0 << 9 ) /* DIS */
2838#define FEEAEN1_DMAUARTTX_EN (0x1 << 9 ) /* EN */
2839
2840/* FEEAEN1[DMASPI1RX] - */
2841#define FEEAEN1_DMASPI1RX_BBA (*(volatile unsigned long *) 0x42050FA0)
2842#define FEEAEN1_DMASPI1RX_MSK (0x1 << 8 )
2843#define FEEAEN1_DMASPI1RX (0x1 << 8 )
2844#define FEEAEN1_DMASPI1RX_DIS (0x0 << 8 ) /* DIS */
2845#define FEEAEN1_DMASPI1RX_EN (0x1 << 8 ) /* EN */
2846
2847/* FEEAEN1[DMASPI1TX] - */
2848#define FEEAEN1_DMASPI1TX_BBA (*(volatile unsigned long *) 0x42050F9C)
2849#define FEEAEN1_DMASPI1TX_MSK (0x1 << 7 )
2850#define FEEAEN1_DMASPI1TX (0x1 << 7 )
2851#define FEEAEN1_DMASPI1TX_DIS (0x0 << 7 ) /* DIS */
2852#define FEEAEN1_DMASPI1TX_EN (0x1 << 7 ) /* EN */
2853
2854/* FEEAEN1[DMAERROR] - */
2855#define FEEAEN1_DMAERROR_BBA (*(volatile unsigned long *) 0x42050F98)
2856#define FEEAEN1_DMAERROR_MSK (0x1 << 6 )
2857#define FEEAEN1_DMAERROR (0x1 << 6 )
2858#define FEEAEN1_DMAERROR_DIS (0x0 << 6 ) /* DIS */
2859#define FEEAEN1_DMAERROR_EN (0x1 << 6 ) /* EN */
2860
2861/* FEEAEN1[I2CM] - */
2862#define FEEAEN1_I2CM_BBA (*(volatile unsigned long *) 0x42050F94)
2863#define FEEAEN1_I2CM_MSK (0x1 << 5 )
2864#define FEEAEN1_I2CM (0x1 << 5 )
2865#define FEEAEN1_I2CM_DIS (0x0 << 5 ) /* DIS */
2866#define FEEAEN1_I2CM_EN (0x1 << 5 ) /* EN */
2867
2868/* FEEAEN1[I2CS] - */
2869#define FEEAEN1_I2CS_BBA (*(volatile unsigned long *) 0x42050F90)
2870#define FEEAEN1_I2CS_MSK (0x1 << 4 )
2871#define FEEAEN1_I2CS (0x1 << 4 )
2872#define FEEAEN1_I2CS_DIS (0x0 << 4 ) /* DIS */
2873#define FEEAEN1_I2CS_EN (0x1 << 4 ) /* EN */
2874
2875/* FEEAEN1[SPI1] - */
2876#define FEEAEN1_SPI1_BBA (*(volatile unsigned long *) 0x42050F8C)
2877#define FEEAEN1_SPI1_MSK (0x1 << 3 )
2878#define FEEAEN1_SPI1 (0x1 << 3 )
2879#define FEEAEN1_SPI1_DIS (0x0 << 3 ) /* DIS */
2880#define FEEAEN1_SPI1_EN (0x1 << 3 ) /* EN */
2881
2882/* FEEAEN1[SPI0] - */
2883#define FEEAEN1_SPI0_BBA (*(volatile unsigned long *) 0x42050F88)
2884#define FEEAEN1_SPI0_MSK (0x1 << 2 )
2885#define FEEAEN1_SPI0 (0x1 << 2 )
2886#define FEEAEN1_SPI0_DIS (0x0 << 2 ) /* DIS */
2887#define FEEAEN1_SPI0_EN (0x1 << 2 ) /* EN */
2888
2889/* FEEAEN1[UART] - */
2890#define FEEAEN1_UART_BBA (*(volatile unsigned long *) 0x42050F84)
2891#define FEEAEN1_UART_MSK (0x1 << 1 )
2892#define FEEAEN1_UART (0x1 << 1 )
2893#define FEEAEN1_UART_DIS (0x0 << 1 ) /* DIS */
2894#define FEEAEN1_UART_EN (0x1 << 1 ) /* EN */
2895
2896/* FEEAEN1[FEE] - */
2897#define FEEAEN1_FEE_BBA (*(volatile unsigned long *) 0x42050F80)
2898#define FEEAEN1_FEE_MSK (0x1 << 0 )
2899#define FEEAEN1_FEE (0x1 << 0 )
2900#define FEEAEN1_FEE_DIS (0x0 << 0 ) /* DIS */
2901#define FEEAEN1_FEE_EN (0x1 << 0 ) /* EN */
2902
2903/* Reset Value for FEEAEN2*/
2904#define FEEAEN2_RVAL 0x0
2905
2906/* FEEAEN2[PWM2] - */
2907#define FEEAEN2_PWM2_BBA (*(volatile unsigned long *) 0x42051018)
2908#define FEEAEN2_PWM2_MSK (0x1 << 6 )
2909#define FEEAEN2_PWM2 (0x1 << 6 )
2910#define FEEAEN2_PWM2_DIS (0x0 << 6 ) /* DIS */
2911#define FEEAEN2_PWM2_EN (0x1 << 6 ) /* EN */
2912
2913/* FEEAEN2[PWM1] - */
2914#define FEEAEN2_PWM1_BBA (*(volatile unsigned long *) 0x42051014)
2915#define FEEAEN2_PWM1_MSK (0x1 << 5 )
2916#define FEEAEN2_PWM1 (0x1 << 5 )
2917#define FEEAEN2_PWM1_DIS (0x0 << 5 ) /* DIS */
2918#define FEEAEN2_PWM1_EN (0x1 << 5 ) /* EN */
2919
2920/* FEEAEN2[PWM0] - */
2921#define FEEAEN2_PWM0_BBA (*(volatile unsigned long *) 0x42051010)
2922#define FEEAEN2_PWM0_MSK (0x1 << 4 )
2923#define FEEAEN2_PWM0 (0x1 << 4 )
2924#define FEEAEN2_PWM0_DIS (0x0 << 4 ) /* DIS */
2925#define FEEAEN2_PWM0_EN (0x1 << 4 ) /* EN */
2926
2927/* FEEAEN2[PWMTRIP] - */
2928#define FEEAEN2_PWMTRIP_BBA (*(volatile unsigned long *) 0x4205100C)
2929#define FEEAEN2_PWMTRIP_MSK (0x1 << 3 )
2930#define FEEAEN2_PWMTRIP (0x1 << 3 )
2931#define FEEAEN2_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
2932#define FEEAEN2_PWMTRIP_EN (0x1 << 3 ) /* EN */
2933
2934/* FEEAEN2[DMASINC2] - */
2935#define FEEAEN2_DMASINC2_BBA (*(volatile unsigned long *) 0x42051008)
2936#define FEEAEN2_DMASINC2_MSK (0x1 << 2 )
2937#define FEEAEN2_DMASINC2 (0x1 << 2 )
2938#define FEEAEN2_DMASINC2_DIS (0x0 << 2 ) /* DIS */
2939#define FEEAEN2_DMASINC2_EN (0x1 << 2 ) /* EN */
2940
2941/* FEEAEN2[DMAADC1] - */
2942#define FEEAEN2_DMAADC1_BBA (*(volatile unsigned long *) 0x42051004)
2943#define FEEAEN2_DMAADC1_MSK (0x1 << 1 )
2944#define FEEAEN2_DMAADC1 (0x1 << 1 )
2945#define FEEAEN2_DMAADC1_DIS (0x0 << 1 ) /* DIS */
2946#define FEEAEN2_DMAADC1_EN (0x1 << 1 ) /* EN */
2947
2948/* FEEAEN2[DMAADC0] - */
2949#define FEEAEN2_DMAADC0_BBA (*(volatile unsigned long *) 0x42051000)
2950#define FEEAEN2_DMAADC0_MSK (0x1 << 0 )
2951#define FEEAEN2_DMAADC0 (0x1 << 0 )
2952#define FEEAEN2_DMAADC0_DIS (0x0 << 0 ) /* DIS */
2953#define FEEAEN2_DMAADC0_EN (0x1 << 0 ) /* EN */
2954// ------------------------------------------------------------------------------------------------
2955// ----- I2C -----
2956// ------------------------------------------------------------------------------------------------
2957
2958
2959/**
2960 * @brief I2C (pADI_I2C)
2961 */
2962
2963#if (__NO_MMR_STRUCTS__==0)
2964typedef struct { /*!< pADI_I2C Structure */
2965 __IO uint16_t I2CMCON; /*!< Master Control Register */
2966 __I uint16_t RESERVED0;
2967 __IO uint16_t I2CMSTA; /*!< Master Status Register */
2968 __I uint16_t RESERVED1;
2969 __IO uint8_t I2CMRX; /*!< Master Receive Data */
2970 __I uint8_t RESERVED2[3];
2971 __IO uint8_t I2CMTX; /*!< Master Transmit Data */
2972 __I uint8_t RESERVED3[3];
2973 __IO uint16_t I2CMRXCNT; /*!< Master Receive Data Count */
2974 __I uint16_t RESERVED4;
2975 __IO uint16_t I2CMCRXCNT; /*!< Master Current Receive Data Count */
2976 __I uint16_t RESERVED5;
2977 __IO uint8_t I2CADR0; /*!< 1st Master Address Byte */
2978 __I uint8_t RESERVED6[3];
2979 __IO uint8_t I2CADR1; /*!< 2nd Master Address Byte */
2980 __I uint8_t RESERVED7[7];
2981 __IO uint16_t I2CDIV; /*!< Serial clock period divisor register */
2982 __I uint16_t RESERVED8;
2983 __IO uint16_t I2CSCON; /*!< Slave Control Register */
2984 __I uint16_t RESERVED9;
2985 __IO uint16_t I2CSSTA; /*!< "Slave I2C Status, Error and IRQ Register" */
2986 __I uint16_t RESERVED10;
2987 __IO uint16_t I2CSRX; /*!< Slave Receive Data Register */
2988 __I uint16_t RESERVED11;
2989 __IO uint16_t I2CSTX; /*!< Slave Transmit Data Register */
2990 __I uint16_t RESERVED12;
2991 __IO uint16_t I2CALT; /*!< Hardware General Call ID */
2992 __I uint16_t RESERVED13;
2993 __IO uint16_t I2CID0; /*!< 1st Slave Address Device ID */
2994 __I uint16_t RESERVED14;
2995 __IO uint16_t I2CID1; /*!< 2nd Slave Address Device ID */
2996 __I uint16_t RESERVED15;
2997 __IO uint16_t I2CID2; /*!< 3rd Slave Address Device ID */
2998 __I uint16_t RESERVED16;
2999 __IO uint16_t I2CID3; /*!< 4th Slave Address Device ID */
3000 __I uint16_t RESERVED17;
3001 __IO uint16_t I2CFSTA; /*!< Master and Slave Rx/Tx FIFO Status Register */
3002 __I uint16_t RESERVED18;
3003 __IO uint16_t I2CSHCON; /*!< Shared control register */
3004 __I uint16_t RESERVED19[3];
3005 __IO uint16_t I2CASSCL; /*!< Automatic Stretch control register */
3006} ADI_I2C_TypeDef;
3007#else // (__NO_MMR_STRUCTS__==0)
3008#define I2CMCON (*(volatile unsigned short int *) 0x40003000)
3009#define I2CMSTA (*(volatile unsigned short int *) 0x40003004)
3010#define I2CMRX (*(volatile unsigned char *) 0x40003008)
3011#define I2CMTX (*(volatile unsigned char *) 0x4000300C)
3012#define I2CMRXCNT (*(volatile unsigned short int *) 0x40003010)
3013#define I2CMCRXCNT (*(volatile unsigned short int *) 0x40003014)
3014#define I2CADR0 (*(volatile unsigned char *) 0x40003018)
3015#define I2CADR1 (*(volatile unsigned char *) 0x4000301C)
3016#define I2CDIV (*(volatile unsigned short int *) 0x40003024)
3017#define I2CSCON (*(volatile unsigned short int *) 0x40003028)
3018#define I2CSSTA (*(volatile unsigned short int *) 0x4000302C)
3019#define I2CSRX (*(volatile unsigned short int *) 0x40003030)
3020#define I2CSTX (*(volatile unsigned short int *) 0x40003034)
3021#define I2CALT (*(volatile unsigned short int *) 0x40003038)
3022#define I2CID0 (*(volatile unsigned short int *) 0x4000303C)
3023#define I2CID1 (*(volatile unsigned short int *) 0x40003040)
3024#define I2CID2 (*(volatile unsigned short int *) 0x40003044)
3025#define I2CID3 (*(volatile unsigned short int *) 0x40003048)
3026#define I2CFSTA (*(volatile unsigned short int *) 0x4000304C)
3027#define I2CSHCON (*(volatile unsigned short int *) 0x40003050)
3028#define I2CASSCL (*(volatile unsigned short int *) 0x40003058)
3029#endif // (__NO_MMR_STRUCTS__==0)
3030
3031/* Reset Value for I2CMCON*/
3032#define I2CMCON_RVAL 0x0
3033
3034/* I2CMCON[TXDMA] - Enable master Tx DMA request */
3035#define I2CMCON_TXDMA_BBA (*(volatile unsigned long *) 0x4206002C)
3036#define I2CMCON_TXDMA_MSK (0x1 << 11 )
3037#define I2CMCON_TXDMA (0x1 << 11 )
3038#define I2CMCON_TXDMA_DIS (0x0 << 11 ) /* DIS */
3039#define I2CMCON_TXDMA_EN (0x1 << 11 ) /* EN */
3040
3041/* I2CMCON[RXDMA] - Enable master Rx DMA request */
3042#define I2CMCON_RXDMA_BBA (*(volatile unsigned long *) 0x42060028)
3043#define I2CMCON_RXDMA_MSK (0x1 << 10 )
3044#define I2CMCON_RXDMA (0x1 << 10 )
3045#define I2CMCON_RXDMA_DIS (0x0 << 10 ) /* DIS */
3046#define I2CMCON_RXDMA_EN (0x1 << 10 ) /* EN */
3047
3048/* I2CMCON[IENCMP] - Transaction completed interrupt enable */
3049#define I2CMCON_IENCMP_BBA (*(volatile unsigned long *) 0x42060020)
3050#define I2CMCON_IENCMP_MSK (0x1 << 8 )
3051#define I2CMCON_IENCMP (0x1 << 8 )
3052#define I2CMCON_IENCMP_DIS (0x0 << 8 ) /* DIS */
3053#define I2CMCON_IENCMP_EN (0x1 << 8 ) /* EN */
3054
3055/* I2CMCON[IENNACK] - ACK not received interrupt enable */
3056#define I2CMCON_IENNACK_BBA (*(volatile unsigned long *) 0x4206001C)
3057#define I2CMCON_IENNACK_MSK (0x1 << 7 )
3058#define I2CMCON_IENNACK (0x1 << 7 )
3059#define I2CMCON_IENNACK_DIS (0x0 << 7 ) /* DIS */
3060#define I2CMCON_IENNACK_EN (0x1 << 7 ) /* EN */
3061
3062/* I2CMCON[IENALOST] - Arbitration lost interrupt enable */
3063#define I2CMCON_IENALOST_BBA (*(volatile unsigned long *) 0x42060018)
3064#define I2CMCON_IENALOST_MSK (0x1 << 6 )
3065#define I2CMCON_IENALOST (0x1 << 6 )
3066#define I2CMCON_IENALOST_DIS (0x0 << 6 ) /* DIS */
3067#define I2CMCON_IENALOST_EN (0x1 << 6 ) /* EN */
3068
3069/* I2CMCON[IENTX] - Transmit request interrupt enable */
3070#define I2CMCON_IENTX_BBA (*(volatile unsigned long *) 0x42060014)
3071#define I2CMCON_IENTX_MSK (0x1 << 5 )
3072#define I2CMCON_IENTX (0x1 << 5 )
3073#define I2CMCON_IENTX_DIS (0x0 << 5 ) /* DIS */
3074#define I2CMCON_IENTX_EN (0x1 << 5 ) /* EN */
3075
3076/* I2CMCON[IENRX] - Receive request interrupt enable */
3077#define I2CMCON_IENRX_BBA (*(volatile unsigned long *) 0x42060010)
3078#define I2CMCON_IENRX_MSK (0x1 << 4 )
3079#define I2CMCON_IENRX (0x1 << 4 )
3080#define I2CMCON_IENRX_DIS (0x0 << 4 ) /* DIS */
3081#define I2CMCON_IENRX_EN (0x1 << 4 ) /* EN */
3082
3083/* I2CMCON[STRETCH] - Stretch SCL */
3084#define I2CMCON_STRETCH_BBA (*(volatile unsigned long *) 0x4206000C)
3085#define I2CMCON_STRETCH_MSK (0x1 << 3 )
3086#define I2CMCON_STRETCH (0x1 << 3 )
3087#define I2CMCON_STRETCH_DIS (0x0 << 3 ) /* DIS */
3088#define I2CMCON_STRETCH_EN (0x1 << 3 ) /* EN */
3089
3090/* I2CMCON[LOOPBACK] - Internal loop back */
3091#define I2CMCON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42060008)
3092#define I2CMCON_LOOPBACK_MSK (0x1 << 2 )
3093#define I2CMCON_LOOPBACK (0x1 << 2 )
3094#define I2CMCON_LOOPBACK_DIS (0x0 << 2 ) /* DIS */
3095#define I2CMCON_LOOPBACK_EN (0x1 << 2 ) /* EN */
3096
3097/* I2CMCON[COMPETE] - Compete for ownership */
3098#define I2CMCON_COMPETE_BBA (*(volatile unsigned long *) 0x42060004)
3099#define I2CMCON_COMPETE_MSK (0x1 << 1 )
3100#define I2CMCON_COMPETE (0x1 << 1 )
3101#define I2CMCON_COMPETE_DIS (0x0 << 1 ) /* DIS */
3102#define I2CMCON_COMPETE_EN (0x1 << 1 ) /* EN */
3103
3104/* I2CMCON[MAS] - Master Enable */
3105#define I2CMCON_MAS_BBA (*(volatile unsigned long *) 0x42060000)
3106#define I2CMCON_MAS_MSK (0x1 << 0 )
3107#define I2CMCON_MAS (0x1 << 0 )
3108#define I2CMCON_MAS_DIS (0x0 << 0 ) /* DIS */
3109#define I2CMCON_MAS_EN (0x1 << 0 ) /* EN */
3110
3111/* Reset Value for I2CMSTA*/
3112#define I2CMSTA_RVAL 0x0
3113
3114/* I2CMSTA[TXUR] - Master Transmit FIFO underflow */
3115#define I2CMSTA_TXUR_BBA (*(volatile unsigned long *) 0x420600B0)
3116#define I2CMSTA_TXUR_MSK (0x1 << 12 )
3117#define I2CMSTA_TXUR (0x1 << 12 )
3118#define I2CMSTA_TXUR_CLR (0x0 << 12 ) /* CLR */
3119#define I2CMSTA_TXUR_SET (0x1 << 12 ) /* SET */
3120
3121/* I2CMSTA[MSTOP] - STOP driven by th eI2C master */
3122#define I2CMSTA_MSTOP_BBA (*(volatile unsigned long *) 0x420600AC)
3123#define I2CMSTA_MSTOP_MSK (0x1 << 11 )
3124#define I2CMSTA_MSTOP (0x1 << 11 )
3125#define I2CMSTA_MSTOP_CLR (0x0 << 11 ) /* CLR */
3126#define I2CMSTA_MSTOP_SET (0x1 << 11 ) /* SET */
3127
3128/* I2CMSTA[LINEBUSY] - Line is busy */
3129#define I2CMSTA_LINEBUSY_BBA (*(volatile unsigned long *) 0x420600A8)
3130#define I2CMSTA_LINEBUSY_MSK (0x1 << 10 )
3131#define I2CMSTA_LINEBUSY (0x1 << 10 )
3132#define I2CMSTA_LINEBUSY_CLR (0x0 << 10 ) /* CLR */
3133#define I2CMSTA_LINEBUSY_SET (0x1 << 10 ) /* SET */
3134
3135/* I2CMSTA[RXOF] - Receive FIFO overflow */
3136#define I2CMSTA_RXOF_BBA (*(volatile unsigned long *) 0x420600A4)
3137#define I2CMSTA_RXOF_MSK (0x1 << 9 )
3138#define I2CMSTA_RXOF (0x1 << 9 )
3139#define I2CMSTA_RXOF_CLR (0x0 << 9 ) /* CLR */
3140#define I2CMSTA_RXOF_SET (0x1 << 9 ) /* SET */
3141
3142/* I2CMSTA[TCOMP] - Transaction completed */
3143#define I2CMSTA_TCOMP_BBA (*(volatile unsigned long *) 0x420600A0)
3144#define I2CMSTA_TCOMP_MSK (0x1 << 8 )
3145#define I2CMSTA_TCOMP (0x1 << 8 )
3146#define I2CMSTA_TCOMP_CLR (0x0 << 8 ) /* CLR */
3147#define I2CMSTA_TCOMP_SET (0x1 << 8 ) /* SET */
3148
3149/* I2CMSTA[NACKDATA] - Ack not received in response to data write */
3150#define I2CMSTA_NACKDATA_BBA (*(volatile unsigned long *) 0x4206009C)
3151#define I2CMSTA_NACKDATA_MSK (0x1 << 7 )
3152#define I2CMSTA_NACKDATA (0x1 << 7 )
3153#define I2CMSTA_NACKDATA_CLR (0x0 << 7 ) /* CLR */
3154#define I2CMSTA_NACKDATA_SET (0x1 << 7 ) /* SET */
3155
3156/* I2CMSTA[BUSY] - Master Busy */
3157#define I2CMSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060098)
3158#define I2CMSTA_BUSY_MSK (0x1 << 6 )
3159#define I2CMSTA_BUSY (0x1 << 6 )
3160#define I2CMSTA_BUSY_CLR (0x0 << 6 ) /* CLR */
3161#define I2CMSTA_BUSY_SET (0x1 << 6 ) /* SET */
3162
3163/* I2CMSTA[ALOST] - Arbitration lost */
3164#define I2CMSTA_ALOST_BBA (*(volatile unsigned long *) 0x42060094)
3165#define I2CMSTA_ALOST_MSK (0x1 << 5 )
3166#define I2CMSTA_ALOST (0x1 << 5 )
3167#define I2CMSTA_ALOST_CLR (0x0 << 5 ) /* CLR */
3168#define I2CMSTA_ALOST_SET (0x1 << 5 ) /* SET */
3169
3170/* I2CMSTA[NACKADDR] - Ack not received in response to an address */
3171#define I2CMSTA_NACKADDR_BBA (*(volatile unsigned long *) 0x42060090)
3172#define I2CMSTA_NACKADDR_MSK (0x1 << 4 )
3173#define I2CMSTA_NACKADDR (0x1 << 4 )
3174#define I2CMSTA_NACKADDR_CLR (0x0 << 4 ) /* CLR */
3175#define I2CMSTA_NACKADDR_SET (0x1 << 4 ) /* SET */
3176
3177/* I2CMSTA[RXREQ] - Receive request */
3178#define I2CMSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206008C)
3179#define I2CMSTA_RXREQ_MSK (0x1 << 3 )
3180#define I2CMSTA_RXREQ (0x1 << 3 )
3181#define I2CMSTA_RXREQ_CLR (0x0 << 3 ) /* CLR */
3182#define I2CMSTA_RXREQ_SET (0x1 << 3 ) /* SET */
3183
3184/* I2CMSTA[TXREQ] - Transmit request */
3185#define I2CMSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060088)
3186#define I2CMSTA_TXREQ_MSK (0x1 << 2 )
3187#define I2CMSTA_TXREQ (0x1 << 2 )
3188#define I2CMSTA_TXREQ_CLR (0x0 << 2 ) /* CLR */
3189#define I2CMSTA_TXREQ_SET (0x1 << 2 ) /* SET */
3190
3191/* I2CMSTA[TXFSTA] - Transmit FIFO Status */
3192#define I2CMSTA_TXFSTA_MSK (0x3 << 0 )
3193#define I2CMSTA_TXFSTA_EMPTY (0x0 << 0 ) /* EMPTY */
3194#define I2CMSTA_TXFSTA_ONEBYTE (0x1 << 0 ) /* ONEBYTE */
3195#define I2CMSTA_TXFSTA_FULL (0x3 << 0 ) /* FULL */
3196
3197/* Reset Value for I2CMRX*/
3198#define I2CMRX_RVAL 0x0
3199
3200/* I2CMRX[VALUE] - Current Receive Value */
3201#define I2CMRX_VALUE_MSK (0xFF << 0 )
3202
3203/* Reset Value for I2CMTX*/
3204#define I2CMTX_RVAL 0x0
3205
3206/* I2CMTX[VALUE] - Current Transmit Value */
3207#define I2CMTX_VALUE_MSK (0xFF << 0 )
3208
3209/* Reset Value for I2CMRXCNT*/
3210#define I2CMRXCNT_RVAL 0x0
3211
3212/* I2CMRXCNT[EXTEND] - Extended Read */
3213#define I2CMRXCNT_EXTEND_BBA (*(volatile unsigned long *) 0x42060220)
3214#define I2CMRXCNT_EXTEND_MSK (0x1 << 8 )
3215#define I2CMRXCNT_EXTEND (0x1 << 8 )
3216#define I2CMRXCNT_EXTEND_DIS (0x0 << 8 ) /* DIS */
3217#define I2CMRXCNT_EXTEND_EN (0x1 << 8 ) /* EN */
3218
3219/* I2CMRXCNT[COUNT] - Receive count */
3220#define I2CMRXCNT_COUNT_MSK (0xFF << 0 )
3221
3222/* Reset Value for I2CMCRXCNT*/
3223#define I2CMCRXCNT_RVAL 0x0
3224
3225/* I2CMCRXCNT[VALUE] - Current Receive count */
3226#define I2CMCRXCNT_VALUE_MSK (0xFF << 0 )
3227
3228/* Reset Value for I2CADR0*/
3229#define I2CADR0_RVAL 0x0
3230
3231/* I2CADR0[VALUE] - Address byte */
3232#define I2CADR0_VALUE_MSK (0xFF << 0 )
3233
3234/* Reset Value for I2CADR1*/
3235#define I2CADR1_RVAL 0x0
3236
3237/* I2CADR1[VALUE] - Address byte */
3238#define I2CADR1_VALUE_MSK (0xFF << 0 )
3239
3240/* Reset Value for I2CDIV*/
3241#define I2CDIV_RVAL 0x1F1F
3242
3243/* I2CDIV[HIGH] - High Time */
3244#define I2CDIV_HIGH_MSK (0xFF << 8 )
3245
3246/* I2CDIV[LOW] - Low Time */
3247#define I2CDIV_LOW_MSK (0xFF << 0 )
3248
3249/* Reset Value for I2CSCON*/
3250#define I2CSCON_RVAL 0x0
3251
3252/* I2CSCON[TXDMA] - Enable slave Tx DMA request */
3253#define I2CSCON_TXDMA_BBA (*(volatile unsigned long *) 0x42060538)
3254#define I2CSCON_TXDMA_MSK (0x1 << 14 )
3255#define I2CSCON_TXDMA (0x1 << 14 )
3256#define I2CSCON_TXDMA_DIS (0x0 << 14 ) /* DIS */
3257#define I2CSCON_TXDMA_EN (0x1 << 14 ) /* EN */
3258
3259/* I2CSCON[RXDMA] - Enable slave Rx DMA request */
3260#define I2CSCON_RXDMA_BBA (*(volatile unsigned long *) 0x42060534)
3261#define I2CSCON_RXDMA_MSK (0x1 << 13 )
3262#define I2CSCON_RXDMA (0x1 << 13 )
3263#define I2CSCON_RXDMA_DIS (0x0 << 13 ) /* DIS */
3264#define I2CSCON_RXDMA_EN (0x1 << 13 ) /* EN */
3265
3266/* I2CSCON[IENREPST] - Repeated start interrupt enable */
3267#define I2CSCON_IENREPST_BBA (*(volatile unsigned long *) 0x42060530)
3268#define I2CSCON_IENREPST_MSK (0x1 << 12 )
3269#define I2CSCON_IENREPST (0x1 << 12 )
3270#define I2CSCON_IENREPST_DIS (0x0 << 12 ) /* DIS */
3271#define I2CSCON_IENREPST_EN (0x1 << 12 ) /* EN */
3272
3273/* I2CSCON[IENTX] - Transmit request interrupt enable */
3274#define I2CSCON_IENTX_BBA (*(volatile unsigned long *) 0x42060528)
3275#define I2CSCON_IENTX_MSK (0x1 << 10 )
3276#define I2CSCON_IENTX (0x1 << 10 )
3277#define I2CSCON_IENTX_DIS (0x0 << 10 ) /* DIS */
3278#define I2CSCON_IENTX_EN (0x1 << 10 ) /* EN */
3279
3280/* I2CSCON[IENRX] - Receive request interrupt enable */
3281#define I2CSCON_IENRX_BBA (*(volatile unsigned long *) 0x42060524)
3282#define I2CSCON_IENRX_MSK (0x1 << 9 )
3283#define I2CSCON_IENRX (0x1 << 9 )
3284#define I2CSCON_IENRX_DIS (0x0 << 9 ) /* DIS */
3285#define I2CSCON_IENRX_EN (0x1 << 9 ) /* EN */
3286
3287/* I2CSCON[IENSTOP] - Stop condition detected interrupt enable */
3288#define I2CSCON_IENSTOP_BBA (*(volatile unsigned long *) 0x42060520)
3289#define I2CSCON_IENSTOP_MSK (0x1 << 8 )
3290#define I2CSCON_IENSTOP (0x1 << 8 )
3291#define I2CSCON_IENSTOP_DIS (0x0 << 8 ) /* DIS */
3292#define I2CSCON_IENSTOP_EN (0x1 << 8 ) /* EN */
3293
3294/* I2CSCON[NACK] - NACK next communication */
3295#define I2CSCON_NACK_BBA (*(volatile unsigned long *) 0x4206051C)
3296#define I2CSCON_NACK_MSK (0x1 << 7 )
3297#define I2CSCON_NACK (0x1 << 7 )
3298#define I2CSCON_NACK_DIS (0x0 << 7 ) /* DIS */
3299#define I2CSCON_NACK_EN (0x1 << 7 ) /* EN */
3300
3301/* I2CSCON[STRETCH] - Stretch SCL */
3302#define I2CSCON_STRETCH_BBA (*(volatile unsigned long *) 0x42060518)
3303#define I2CSCON_STRETCH_MSK (0x1 << 6 )
3304#define I2CSCON_STRETCH (0x1 << 6 )
3305#define I2CSCON_STRETCH_DIS (0x0 << 6 ) /* DIS */
3306#define I2CSCON_STRETCH_EN (0x1 << 6 ) /* EN */
3307
3308/* I2CSCON[EARLYTXR] - Early transmit request mode */
3309#define I2CSCON_EARLYTXR_BBA (*(volatile unsigned long *) 0x42060514)
3310#define I2CSCON_EARLYTXR_MSK (0x1 << 5 )
3311#define I2CSCON_EARLYTXR (0x1 << 5 )
3312#define I2CSCON_EARLYTXR_DIS (0x0 << 5 ) /* DIS */
3313#define I2CSCON_EARLYTXR_EN (0x1 << 5 ) /* EN */
3314
3315/* I2CSCON[GCSB] - General call status bit clear */
3316#define I2CSCON_GCSB_BBA (*(volatile unsigned long *) 0x42060510)
3317#define I2CSCON_GCSB_MSK (0x1 << 4 )
3318#define I2CSCON_GCSB (0x1 << 4 )
3319#define I2CSCON_GCSB_CLR (0x1 << 4 ) /* CLR */
3320
3321/* I2CSCON[HGC] - Hardware general Call enable */
3322#define I2CSCON_HGC_BBA (*(volatile unsigned long *) 0x4206050C)
3323#define I2CSCON_HGC_MSK (0x1 << 3 )
3324#define I2CSCON_HGC (0x1 << 3 )
3325#define I2CSCON_HGC_DIS (0x0 << 3 ) /* DIS */
3326#define I2CSCON_HGC_EN (0x1 << 3 ) /* EN */
3327
3328/* I2CSCON[GC] - General Call enable */
3329#define I2CSCON_GC_BBA (*(volatile unsigned long *) 0x42060508)
3330#define I2CSCON_GC_MSK (0x1 << 2 )
3331#define I2CSCON_GC (0x1 << 2 )
3332#define I2CSCON_GC_DIS (0x0 << 2 ) /* DIS */
3333#define I2CSCON_GC_EN (0x1 << 2 ) /* EN */
3334
3335/* I2CSCON[ADR10] - Enable 10 bit addressing */
3336#define I2CSCON_ADR10_BBA (*(volatile unsigned long *) 0x42060504)
3337#define I2CSCON_ADR10_MSK (0x1 << 1 )
3338#define I2CSCON_ADR10 (0x1 << 1 )
3339#define I2CSCON_ADR10_DIS (0x0 << 1 ) /* DIS */
3340#define I2CSCON_ADR10_EN (0x1 << 1 ) /* EN */
3341
3342/* I2CSCON[SLV] - Slave Enable */
3343#define I2CSCON_SLV_BBA (*(volatile unsigned long *) 0x42060500)
3344#define I2CSCON_SLV_MSK (0x1 << 0 )
3345#define I2CSCON_SLV (0x1 << 0 )
3346#define I2CSCON_SLV_DIS (0x0 << 0 ) /* DIS */
3347#define I2CSCON_SLV_EN (0x1 << 0 ) /* EN */
3348
3349/* Reset Value for I2CSSTA*/
3350#define I2CSSTA_RVAL 0x1
3351
3352/* I2CSSTA[START] - Start and matching address */
3353#define I2CSSTA_START_BBA (*(volatile unsigned long *) 0x420605B8)
3354#define I2CSSTA_START_MSK (0x1 << 14 )
3355#define I2CSSTA_START (0x1 << 14 )
3356#define I2CSSTA_START_CLR (0x0 << 14 ) /* CLR */
3357#define I2CSSTA_START_SET (0x1 << 14 ) /* SET */
3358
3359/* I2CSSTA[REPSTART] - Repeated start and matching address */
3360#define I2CSSTA_REPSTART_BBA (*(volatile unsigned long *) 0x420605B4)
3361#define I2CSSTA_REPSTART_MSK (0x1 << 13 )
3362#define I2CSSTA_REPSTART (0x1 << 13 )
3363#define I2CSSTA_REPSTART_CLR (0x0 << 13 ) /* CLR */
3364#define I2CSSTA_REPSTART_SET (0x1 << 13 ) /* SET */
3365
3366/* I2CSSTA[IDMAT] - Device ID matched */
3367#define I2CSSTA_IDMAT_MSK (0x3 << 11 )
3368#define I2CSSTA_IDMAT_CLR (0x0 << 11 ) /* CLR */
3369#define I2CSSTA_IDMAT_SET (0x1 << 11 ) /* SET */
3370
3371/* I2CSSTA[STOP] - Stop after start and matching address */
3372#define I2CSSTA_STOP_BBA (*(volatile unsigned long *) 0x420605A8)
3373#define I2CSSTA_STOP_MSK (0x1 << 10 )
3374#define I2CSSTA_STOP (0x1 << 10 )
3375#define I2CSSTA_STOP_CLR (0x0 << 10 ) /* CLR */
3376#define I2CSSTA_STOP_SET (0x1 << 10 ) /* SET */
3377
3378/* I2CSSTA[GCID] - General ID */
3379#define I2CSSTA_GCID_MSK (0x3 << 8 )
3380#define I2CSSTA_GCID_CLR (0x0 << 8 ) /* CLR */
3381#define I2CSSTA_GCID_SET (0x1 << 8 ) /* SET */
3382
3383/* I2CSSTA[GCINT] - General call */
3384#define I2CSSTA_GCINT_BBA (*(volatile unsigned long *) 0x4206059C)
3385#define I2CSSTA_GCINT_MSK (0x1 << 7 )
3386#define I2CSSTA_GCINT (0x1 << 7 )
3387#define I2CSSTA_GCINT_CLR (0x0 << 7 ) /* CLR */
3388#define I2CSSTA_GCINT_SET (0x1 << 7 ) /* SET */
3389
3390/* I2CSSTA[BUSY] - Slave busy */
3391#define I2CSSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060598)
3392#define I2CSSTA_BUSY_MSK (0x1 << 6 )
3393#define I2CSSTA_BUSY (0x1 << 6 )
3394#define I2CSSTA_BUSY_CLR (0x0 << 6 ) /* CLR */
3395#define I2CSSTA_BUSY_SET (0x1 << 6 ) /* SET */
3396
3397/* I2CSSTA[NOACK] - Ack not generated by the slave */
3398#define I2CSSTA_NOACK_BBA (*(volatile unsigned long *) 0x42060594)
3399#define I2CSSTA_NOACK_MSK (0x1 << 5 )
3400#define I2CSSTA_NOACK (0x1 << 5 )
3401#define I2CSSTA_NOACK_CLR (0x0 << 5 ) /* CLR */
3402#define I2CSSTA_NOACK_SET (0x1 << 5 ) /* SET */
3403
3404/* I2CSSTA[RXOF] - Receive FIFO */
3405#define I2CSSTA_RXOF_BBA (*(volatile unsigned long *) 0x42060590)
3406#define I2CSSTA_RXOF_MSK (0x1 << 4 )
3407#define I2CSSTA_RXOF (0x1 << 4 )
3408#define I2CSSTA_RXOF_CLR (0x0 << 4 ) /* CLR */
3409#define I2CSSTA_RXOF_SET (0x1 << 4 ) /* SET */
3410
3411/* I2CSSTA[RXREQ] - Receive */
3412#define I2CSSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206058C)
3413#define I2CSSTA_RXREQ_MSK (0x1 << 3 )
3414#define I2CSSTA_RXREQ (0x1 << 3 )
3415#define I2CSSTA_RXREQ_CLR (0x0 << 3 ) /* CLR */
3416#define I2CSSTA_RXREQ_SET (0x1 << 3 ) /* SET */
3417
3418/* I2CSSTA[TXREQ] - Transmit */
3419#define I2CSSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060588)
3420#define I2CSSTA_TXREQ_MSK (0x1 << 2 )
3421#define I2CSSTA_TXREQ (0x1 << 2 )
3422#define I2CSSTA_TXREQ_CLR (0x0 << 2 ) /* CLR */
3423#define I2CSSTA_TXREQ_SET (0x1 << 2 ) /* SET */
3424
3425/* I2CSSTA[TXUR] - Transmit FIFO underflow */
3426#define I2CSSTA_TXUR_BBA (*(volatile unsigned long *) 0x42060584)
3427#define I2CSSTA_TXUR_MSK (0x1 << 1 )
3428#define I2CSSTA_TXUR (0x1 << 1 )
3429#define I2CSSTA_TXUR_CLR (0x0 << 1 ) /* CLR */
3430#define I2CSSTA_TXUR_SET (0x1 << 1 ) /* SET */
3431
3432/* I2CSSTA[TXFSEREQ] - Tx FIFO status or early request */
3433#define I2CSSTA_TXFSEREQ_BBA (*(volatile unsigned long *) 0x42060580)
3434#define I2CSSTA_TXFSEREQ_MSK (0x1 << 0 )
3435#define I2CSSTA_TXFSEREQ (0x1 << 0 )
3436#define I2CSSTA_TXFSEREQ_CLR (0x0 << 0 ) /* CLR */
3437#define I2CSSTA_TXFSEREQ_SET (0x1 << 0 ) /* SET */
3438
3439/* Reset Value for I2CSRX*/
3440#define I2CSRX_RVAL 0x0
3441
3442/* I2CSRX[VALUE] - Receive register */
3443#define I2CSRX_VALUE_MSK (0xFF << 0 )
3444
3445/* Reset Value for I2CSTX*/
3446#define I2CSTX_RVAL 0x0
3447
3448/* I2CSTX[VALUE] - Transmit register */
3449#define I2CSTX_VALUE_MSK (0xFF << 0 )
3450
3451/* Reset Value for I2CALT*/
3452#define I2CALT_RVAL 0x0
3453
3454/* I2CALT[VALUE] - Alt register */
3455#define I2CALT_VALUE_MSK (0xFF << 0 )
3456
3457/* Reset Value for I2CID0*/
3458#define I2CID0_RVAL 0x0
3459
3460/* I2CID0[VALUE] - Slave ID */
3461#define I2CID0_VALUE_MSK (0xFF << 0 )
3462
3463/* Reset Value for I2CID1*/
3464#define I2CID1_RVAL 0x0
3465
3466/* I2CID1[VALUE] - Slave ID */
3467#define I2CID1_VALUE_MSK (0xFF << 0 )
3468
3469/* Reset Value for I2CID2*/
3470#define I2CID2_RVAL 0x0
3471
3472/* I2CID2[VALUE] - Slave ID */
3473#define I2CID2_VALUE_MSK (0xFF << 0 )
3474
3475/* Reset Value for I2CID3*/
3476#define I2CID3_RVAL 0x0
3477
3478/* I2CID3[VALUE] - Slave ID */
3479#define I2CID3_VALUE_MSK (0xFF << 0 )
3480
3481/* Reset Value for I2CFSTA*/
3482#define I2CFSTA_RVAL 0x0
3483
3484/* I2CFSTA[MFLUSH] - Flush the master transmit FIFO */
3485#define I2CFSTA_MFLUSH_BBA (*(volatile unsigned long *) 0x420609A4)
3486#define I2CFSTA_MFLUSH_MSK (0x1 << 9 )
3487#define I2CFSTA_MFLUSH (0x1 << 9 )
3488#define I2CFSTA_MFLUSH_DIS (0x0 << 9 ) /* DIS */
3489#define I2CFSTA_MFLUSH_EN (0x1 << 9 ) /* EN */
3490
3491/* I2CFSTA[SFLUSH] - Flush the slave transmit FIFO */
3492#define I2CFSTA_SFLUSH_BBA (*(volatile unsigned long *) 0x420609A0)
3493#define I2CFSTA_SFLUSH_MSK (0x1 << 8 )
3494#define I2CFSTA_SFLUSH (0x1 << 8 )
3495#define I2CFSTA_SFLUSH_DIS (0x0 << 8 ) /* DIS */
3496#define I2CFSTA_SFLUSH_EN (0x1 << 8 ) /* EN */
3497
3498/* I2CFSTA[MRXFSTA] - Master receive FIFO Status */
3499#define I2CFSTA_MRXFSTA_MSK (0x3 << 6 )
3500#define I2CFSTA_MRXFSTA_EMPTY (0x0 << 6 ) /* EMPTY */
3501#define I2CFSTA_MRXFSTA_ONEBYTE (0x1 << 6 ) /* ONEBYTE */
3502#define I2CFSTA_MRXFSTA_TWOBYTES (0x2 << 6 ) /* TWOBYTES */
3503
3504/* I2CFSTA[MTXFSTA] - Master Transmit FIFO Status */
3505#define I2CFSTA_MTXFSTA_MSK (0x3 << 4 )
3506#define I2CFSTA_MTXFSTA_EMPTY (0x0 << 4 ) /* EMPTY */
3507#define I2CFSTA_MTXFSTA_ONEBYTE (0x1 << 4 ) /* ONEBYTE */
3508#define I2CFSTA_MTXFSTA_TWOBYTES (0x2 << 4 ) /* TWOBYTES */
3509
3510/* I2CFSTA[SRXFSTA] - Slave receive FIFO Status */
3511#define I2CFSTA_SRXFSTA_MSK (0x3 << 2 )
3512#define I2CFSTA_SRXFSTA_EMPTY (0x0 << 2 ) /* EMPTY */
3513#define I2CFSTA_SRXFSTA_ONEBYTE (0x1 << 2 ) /* ONEBYTE */
3514#define I2CFSTA_SRXFSTA_TWOBYTES (0x2 << 2 ) /* TWOBYTES */
3515
3516/* I2CFSTA[STXFSTA] - Slave Transmit FIFO Status */
3517#define I2CFSTA_STXFSTA_MSK (0x3 << 0 )
3518#define I2CFSTA_STXFSTA_EMPTY (0x0 << 0 ) /* EMPTY */
3519#define I2CFSTA_STXFSTA_ONEBYTE (0x1 << 0 ) /* ONEBYTE */
3520#define I2CFSTA_STXFSTA_TWOBYTES (0x2 << 0 ) /* TWOBYTES */
3521
3522/* I2CSHCON[RESET] - Reset START STOP detect circuit */
3523#define I2CSHCON_RESET_MSK (0x1 << 0 )
3524#define I2CSHCON_RESET (0x1 << 0 )
3525#define I2CSHCON_RESET_DIS (0x0 << 0 )
3526#define I2CSHCON_RESET_EN (0x1 << 0 )
3527
3528/* I2CASSCL[SSRTSTA] - stretch timeout for slave */
3529#define I2CASSCL_SSRTSTA_MSK (0x1 << 9 )
3530#define I2CASSCL_SSRTSTA (0x1 << 9 )
3531#define I2CASSCL_SSRTSTA_DIS (0x0 << 9 )
3532#define I2CASSCL_SSRTSTA_EN (0x1 << 9 )
3533
3534/* I2CASSCL[MSRTSTA] - stretch timeout for master */
3535#define I2CASSCL_MSRTSTA_MSK (0x1 << 8 )
3536#define I2CASSCL_MSRTSTA (0x1 << 8 )
3537#define I2CASSCL_MSRTSTA_DIS (0x0 << 8 )
3538#define I2CASSCL_MSRTSTA_EN (0x1 << 8 )
3539
3540/* I2CASSCL[SSTRCON] - automatic stretch mode for slave */
3541#define I2CASSCL_SSTRCON_MSK (0xF << 4 )
3542
3543/* I2CASSCL[MSTRCON] - automatic stretch mode for master */
3544#define I2CASSCL_MSTRCON_MSK (0xF << 0 )
3545
3546// ------------------------------------------------------------------------------------------------
3547// ----- SPI0 -----
3548// ------------------------------------------------------------------------------------------------
3549
3550
3551/**
3552 * @brief Serial Peripheral Interface (pADI_SPI0)
3553 */
3554
3555typedef struct { /*!< pADI_SPI0 Structure */
3556 __IO uint16_t SPISTA; /*!< Status Register */
3557 __I uint16_t RESERVED0;
3558 __IO uint8_t SPIRX; /*!< 8-bit Receive register. */
3559 __I uint8_t RESERVED1[3];
3560 __IO uint8_t SPITX; /*!< 8-bit Transmit register */
3561 __I uint8_t RESERVED2[3];
3562 __IO uint16_t SPIDIV; /*!< SPI Clock Divider Registers */
3563 __I uint16_t RESERVED3;
3564 __IO uint16_t SPICON; /*!< 16-bit configuration register */
3565 __I uint16_t RESERVED4;
3566 __IO uint16_t SPIDMA; /*!< DMA enable register */
3567 __I uint16_t RESERVED5;
3568 __IO uint16_t SPICNT; /*!< 8-bit received byte count register */
3569} ADI_SPI_TypeDef;
3570
3571#define SPI0STA (*(volatile unsigned short int *) 0x40004000)
3572#define SPI0RX (*(volatile unsigned char *) 0x40004004)
3573#define SPI0TX (*(volatile unsigned char *) 0x40004008)
3574#define SPI0DIV (*(volatile unsigned short int *) 0x4000400C)
3575#define SPI0CON (*(volatile unsigned short int *) 0x40004010)
3576#define SPI0DMA (*(volatile unsigned short int *) 0x40004014)
3577#define SPI0CNT (*(volatile unsigned short int *) 0x40004018)
3578
3579/* Reset Value for SPI0STA*/
3580#define SPI0STA_RVAL 0x0
3581
3582/* SPI0STA[CSRSG] - Detected a rising edge on CS, in CONT mode */
3583#define SPI0STA_CSRSG_BBA (*(volatile unsigned long *) 0x42080038)
3584#define SPI0STA_CSRSG_MSK (0x1 << 14 )
3585#define SPI0STA_CSRSG (0x1 << 14 )
3586#define SPI0STA_CSRSG_CLR (0x0 << 14 ) /* Cleared to 0 when the Status register is read. */
3587#define SPI0STA_CSRSG_SET (0x1 << 14 ) /* Set to 1 when there was a rising edge in CS line, when the device was in master mode, continuous transfer, High Frequency mode and CSIRQ_EN was asserted. */
3588
3589/* SPI0STA[CSFLG] - Detected a falling edge on CS, in CONT mode */
3590#define SPI0STA_CSFLG_BBA (*(volatile unsigned long *) 0x42080034)
3591#define SPI0STA_CSFLG_MSK (0x1 << 13 )
3592#define SPI0STA_CSFLG (0x1 << 13 )
3593#define SPI0STA_CSFLG_CLR (0x0 << 13 ) /* Cleared to 0 when the Status register is read. */
3594#define SPI0STA_CSFLG_SET (0x1 << 13 ) /* Set to 1 when there was a falling edge in CS line, when the device was in master mode, continuous transfer, High Frequency mode and CSIRQ_EN was asserted */
3595
3596/* SPI0STA[CSERR] - Detected an abrupt CS deassertion */
3597#define SPI0STA_CSERR_BBA (*(volatile unsigned long *) 0x42080030)
3598#define SPI0STA_CSERR_MSK (0x1 << 12 )
3599#define SPI0STA_CSERR (0x1 << 12 )
3600#define SPI0STA_CSERR_CLR (0x0 << 12 ) /* CLR */
3601#define SPI0STA_CSERR_SET (0x1 << 12 ) /* SET */
3602
3603/* SPI0STA[RXS] - Set when there are more bytes in the RX FIFO than the TIM bit says */
3604#define SPI0STA_RXS_BBA (*(volatile unsigned long *) 0x4208002C)
3605#define SPI0STA_RXS_MSK (0x1 << 11 )
3606#define SPI0STA_RXS (0x1 << 11 )
3607#define SPI0STA_RXS_CLR (0x0 << 11 ) /* CLR */
3608#define SPI0STA_RXS_SET (0x1 << 11 ) /* SET */
3609
3610/* SPI0STA[RXFSTA] - Receive FIFO Status */
3611#define SPI0STA_RXFSTA_MSK (0x7 << 8 )
3612#define SPI0STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY */
3613#define SPI0STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE */
3614#define SPI0STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES */
3615#define SPI0STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES */
3616#define SPI0STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES */
3617
3618/* SPI0STA[RXOF] - Receive FIFO overflow */
3619#define SPI0STA_RXOF_BBA (*(volatile unsigned long *) 0x4208001C)
3620#define SPI0STA_RXOF_MSK (0x1 << 7 )
3621#define SPI0STA_RXOF (0x1 << 7 )
3622#define SPI0STA_RXOF_CLR (0x0 << 7 ) /* CLR */
3623#define SPI0STA_RXOF_SET (0x1 << 7 ) /* SET */
3624
3625/* SPI0STA[RX] - Set when a receive interrupt occurs */
3626#define SPI0STA_RX_BBA (*(volatile unsigned long *) 0x42080018)
3627#define SPI0STA_RX_MSK (0x1 << 6 )
3628#define SPI0STA_RX (0x1 << 6 )
3629#define SPI0STA_RX_CLR (0x0 << 6 ) /* CLR */
3630#define SPI0STA_RX_SET (0x1 << 6 ) /* SET */
3631
3632/* SPI0STA[TX] - Set when a transmit interrupt occurs */
3633#define SPI0STA_TX_BBA (*(volatile unsigned long *) 0x42080014)
3634#define SPI0STA_TX_MSK (0x1 << 5 )
3635#define SPI0STA_TX (0x1 << 5 )
3636#define SPI0STA_TX_CLR (0x0 << 5 ) /* CLR */
3637#define SPI0STA_TX_SET (0x1 << 5 ) /* SET */
3638
3639/* SPI0STA[TXUR] - Transmit FIFO underflow */
3640#define SPI0STA_TXUR_BBA (*(volatile unsigned long *) 0x42080010)
3641#define SPI0STA_TXUR_MSK (0x1 << 4 )
3642#define SPI0STA_TXUR (0x1 << 4 )
3643#define SPI0STA_TXUR_CLR (0x0 << 4 ) /* CLR */
3644#define SPI0STA_TXUR_SET (0x1 << 4 ) /* SET */
3645
3646/* SPI0STA[TXFSTA] - transmit FIFO Status */
3647#define SPI0STA_TXFSTA_MSK (0x7 << 1 )
3648#define SPI0STA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY */
3649#define SPI0STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE */
3650#define SPI0STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES */
3651#define SPI0STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES */
3652#define SPI0STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES */
3653
3654/* SPI0STA[IRQ] - Interrupt status bit */
3655#define SPI0STA_IRQ_BBA (*(volatile unsigned long *) 0x42080000)
3656#define SPI0STA_IRQ_MSK (0x1 << 0 )
3657#define SPI0STA_IRQ (0x1 << 0 )
3658#define SPI0STA_IRQ_CLR (0x0 << 0 ) /* CLR */
3659#define SPI0STA_IRQ_SET (0x1 << 0 ) /* SET */
3660
3661/* Reset Value for SPI0RX*/
3662#define SPI0RX_RVAL 0x0
3663
3664/* SPI0RX[VALUE] - Received data */
3665#define SPI0RX_VALUE_MSK (0xFF << 0 )
3666
3667/* Reset Value for SPI0TX*/
3668#define SPI0TX_RVAL 0x0
3669
3670/* SPI0TX[VALUE] - Data to transmit */
3671#define SPI0TX_VALUE_MSK (0xFF << 0 )
3672
3673/* Reset Value for SPI0DIV*/
3674#define SPI0DIV_RVAL 0x0
3675
3676/* SPI0DIV[CSIRQ_EN] - Enable interrupt on every CS edge in CONT mode */
3677#define SPI0DIV_CSIRQ_EN_BBA (*(volatile unsigned long *) 0x420801A0)
3678#define SPI0DIV_CSIRQ_EN_MSK (0x1 << 8 )
3679#define SPI0DIV_CSIRQ_EN (0x1 << 8 )
3680#define SPI0DIV_CSIRQ_EN_DIS (0x0 << 8 )
3681#define SPI0DIV_CSIRQ_EN_EN (0x1 << 8 )
3682
3683/* SPI0DIV[BCRST] - Bit counter reset */
3684#define SPI0DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208019C)
3685#define SPI0DIV_BCRST_MSK (0x1 << 7 )
3686#define SPI0DIV_BCRST (0x1 << 7 )
3687#define SPI0DIV_BCRST_DIS (0x0 << 7 ) /* DIS */
3688#define SPI0DIV_BCRST_EN (0x1 << 7 ) /* EN */
3689
3690/* SPI0DIV[HFM] - High Frequency Mode */
3691#define SPI0DIV_HFM_BBA (*(volatile unsigned long *) 0x42080198)
3692#define SPI0DIV_HFM_MSK (0x1 << 6 )
3693#define SPI0DIV_HFM (0x1 << 6 )
3694#define SPI0DIV_HFM_DIS (0x0 << 6 )
3695#define SPI0DIV_HFM_EN (0x1 << 6 )
3696
3697/* SPI0DIV[DIV] - Factor used to divide UCLK to generate the serial clock */
3698#define SPI0DIV_DIV_MSK (0x3F << 0 )
3699
3700/* Reset Value for SPI0CON*/
3701#define SPI0CON_RVAL 0x0
3702
3703/* SPI0CON[MOD] - SPI IRQ Mode bits */
3704#define SPI0CON_MOD_MSK (0x3 << 14 )
3705#define SPI0CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1 */
3706#define SPI0CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2 */
3707#define SPI0CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3 */
3708#define SPI0CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4 */
3709
3710/* SPI0CON[TFLUSH] - TX FIFO Flush Enable bit */
3711#define SPI0CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42080234)
3712#define SPI0CON_TFLUSH_MSK (0x1 << 13 )
3713#define SPI0CON_TFLUSH (0x1 << 13 )
3714#define SPI0CON_TFLUSH_DIS (0x0 << 13 ) /* DIS */
3715#define SPI0CON_TFLUSH_EN (0x1 << 13 ) /* EN */
3716
3717/* SPI0CON[RFLUSH] - RX FIFO Flush Enable bit */
3718#define SPI0CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42080230)
3719#define SPI0CON_RFLUSH_MSK (0x1 << 12 )
3720#define SPI0CON_RFLUSH (0x1 << 12 )
3721#define SPI0CON_RFLUSH_DIS (0x0 << 12 ) /* DIS */
3722#define SPI0CON_RFLUSH_EN (0x1 << 12 ) /* EN */
3723
3724/* SPI0CON[CON] - Continuous transfer enable */
3725#define SPI0CON_CON_BBA (*(volatile unsigned long *) 0x4208022C)
3726#define SPI0CON_CON_MSK (0x1 << 11 )
3727#define SPI0CON_CON (0x1 << 11 )
3728#define SPI0CON_CON_DIS (0x0 << 11 ) /* DIS */
3729#define SPI0CON_CON_EN (0x1 << 11 ) /* EN */
3730
3731/* SPI0CON[LOOPBACK] - Loopback enable bit */
3732#define SPI0CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42080228)
3733#define SPI0CON_LOOPBACK_MSK (0x1 << 10 )
3734#define SPI0CON_LOOPBACK (0x1 << 10 )
3735#define SPI0CON_LOOPBACK_DIS (0x0 << 10 ) /* DIS */
3736#define SPI0CON_LOOPBACK_EN (0x1 << 10 ) /* EN */
3737
3738/* SPI0CON[SOEN] - Slave MISO output enable bit */
3739#define SPI0CON_SOEN_BBA (*(volatile unsigned long *) 0x42080224)
3740#define SPI0CON_SOEN_MSK (0x1 << 9 )
3741#define SPI0CON_SOEN (0x1 << 9 )
3742#define SPI0CON_SOEN_DIS (0x0 << 9 ) /* DIS */
3743#define SPI0CON_SOEN_EN (0x1 << 9 ) /* EN */
3744
3745/* SPI0CON[RXOF] - RX Oveflow Overwrite enable */
3746#define SPI0CON_RXOF_BBA (*(volatile unsigned long *) 0x42080220)
3747#define SPI0CON_RXOF_MSK (0x1 << 8 )
3748#define SPI0CON_RXOF (0x1 << 8 )
3749#define SPI0CON_RXOF_DIS (0x0 << 8 ) /* DIS */
3750#define SPI0CON_RXOF_EN (0x1 << 8 ) /* EN */
3751
3752/* SPI0CON[ZEN] - Transmit zeros when empty */
3753#define SPI0CON_ZEN_BBA (*(volatile unsigned long *) 0x4208021C)
3754#define SPI0CON_ZEN_MSK (0x1 << 7 )
3755#define SPI0CON_ZEN (0x1 << 7 )
3756#define SPI0CON_ZEN_DIS (0x0 << 7 ) /* DIS */
3757#define SPI0CON_ZEN_EN (0x1 << 7 ) /* EN */
3758
3759/* SPI0CON[TIM] - Transfer and interrupt mode */
3760#define SPI0CON_TIM_BBA (*(volatile unsigned long *) 0x42080218)
3761#define SPI0CON_TIM_MSK (0x1 << 6 )
3762#define SPI0CON_TIM (0x1 << 6 )
3763#define SPI0CON_TIM_RXRD (0x0 << 6 ) /* RXRD - Cleared by user to initiate transfer with a read of the SPIRX register */
3764#define SPI0CON_TIM_TXWR (0x1 << 6 ) /* TXWR - Set by user to initiate transfer with a write to the SPITX register. */
3765
3766/* SPI0CON[LSB] - LSB First Transfer enable */
3767#define SPI0CON_LSB_BBA (*(volatile unsigned long *) 0x42080214)
3768#define SPI0CON_LSB_MSK (0x1 << 5 )
3769#define SPI0CON_LSB (0x1 << 5 )
3770#define SPI0CON_LSB_DIS (0x0 << 5 ) /* DIS */
3771#define SPI0CON_LSB_EN (0x1 << 5 ) /* EN */
3772
3773/* SPI0CON[WOM] - Wired OR enable */
3774#define SPI0CON_WOM_BBA (*(volatile unsigned long *) 0x42080210)
3775#define SPI0CON_WOM_MSK (0x1 << 4 )
3776#define SPI0CON_WOM (0x1 << 4 )
3777#define SPI0CON_WOM_DIS (0x0 << 4 ) /* DIS */
3778#define SPI0CON_WOM_EN (0x1 << 4 ) /* EN */
3779
3780/* SPI0CON[CPOL] - Clock polarity mode */
3781#define SPI0CON_CPOL_BBA (*(volatile unsigned long *) 0x4208020C)
3782#define SPI0CON_CPOL_MSK (0x1 << 3 )
3783#define SPI0CON_CPOL (0x1 << 3 )
3784#define SPI0CON_CPOL_LOW (0x0 << 3 ) /* LOW */
3785#define SPI0CON_CPOL_HIGH (0x1 << 3 ) /* HIGH */
3786
3787/* SPI0CON[CPHA] - Clock phase mode */
3788#define SPI0CON_CPHA_BBA (*(volatile unsigned long *) 0x42080208)
3789#define SPI0CON_CPHA_MSK (0x1 << 2 )
3790#define SPI0CON_CPHA (0x1 << 2 )
3791#define SPI0CON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING */
3792#define SPI0CON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING */
3793
3794/* SPI0CON[MASEN] - Master enable */
3795#define SPI0CON_MASEN_BBA (*(volatile unsigned long *) 0x42080204)
3796#define SPI0CON_MASEN_MSK (0x1 << 1 )
3797#define SPI0CON_MASEN (0x1 << 1 )
3798#define SPI0CON_MASEN_DIS (0x0 << 1 ) /* DIS */
3799#define SPI0CON_MASEN_EN (0x1 << 1 ) /* EN */
3800
3801/* SPI0CON[ENABLE] - SPI Enable bit */
3802#define SPI0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42080200)
3803#define SPI0CON_ENABLE_MSK (0x1 << 0 )
3804#define SPI0CON_ENABLE (0x1 << 0 )
3805#define SPI0CON_ENABLE_DIS (0x0 << 0 ) /* DIS */
3806#define SPI0CON_ENABLE_EN (0x1 << 0 ) /* EN */
3807
3808/* Reset Value for SPI0DMA*/
3809#define SPI0DMA_RVAL 0x0
3810
3811/* SPI0DMA[IENRXDMA] - Enable receive DMA request */
3812#define SPI0DMA_IENRXDMA_BBA (*(volatile unsigned long *) 0x42080288)
3813#define SPI0DMA_IENRXDMA_MSK (0x1 << 2 )
3814#define SPI0DMA_IENRXDMA (0x1 << 2 )
3815#define SPI0DMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS */
3816#define SPI0DMA_IENRXDMA_EN (0x1 << 2 ) /* EN */
3817
3818/* SPI0DMA[IENTXDMA] - Enable transmit DMA request */
3819#define SPI0DMA_IENTXDMA_BBA (*(volatile unsigned long *) 0x42080284)
3820#define SPI0DMA_IENTXDMA_MSK (0x1 << 1 )
3821#define SPI0DMA_IENTXDMA (0x1 << 1 )
3822#define SPI0DMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS */
3823#define SPI0DMA_IENTXDMA_EN (0x1 << 1 ) /* EN */
3824
3825/* SPI0DMA[ENABLE] - Enable DMA for data transfer */
3826#define SPI0DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42080280)
3827#define SPI0DMA_ENABLE_MSK (0x1 << 0 )
3828#define SPI0DMA_ENABLE (0x1 << 0 )
3829#define SPI0DMA_ENABLE_DIS (0x0 << 0 ) /* DIS */
3830#define SPI0DMA_ENABLE_EN (0x1 << 0 ) /* EN */
3831
3832/* Reset Value for SPI0CNT*/
3833#define SPI0CNT_RVAL 0x0
3834
3835/* SPI0CNT[VALUE] - Count */
3836#define SPI0CNT_VALUE_MSK (0xFF << 0 )
3837
3838#define SPI1STA (*(volatile unsigned short int *) 0x40004400)
3839#define SPI1RX (*(volatile unsigned char *) 0x40004404)
3840#define SPI1TX (*(volatile unsigned char *) 0x40004408)
3841#define SPI1DIV (*(volatile unsigned short int *) 0x4000440C)
3842#define SPI1CON (*(volatile unsigned short int *) 0x40004410)
3843#define SPI1DMA (*(volatile unsigned short int *) 0x40004414)
3844#define SPI1CNT (*(volatile unsigned short int *) 0x40004418)
3845
3846/* Reset Value for SPI1STA*/
3847#define SPI1STA_RVAL 0x0
3848
3849/* SPI1STA[CSRSG] - Detected a rising edge on CS, in CONT mode */
3850#define SPI1STA_CSRSG_BBA (*(volatile unsigned long *) 0x42000038)
3851#define SPI1STA_CSRSG_MSK (0x1 << 14 )
3852#define SPI1STA_CSRSG (0x1 << 14 )
3853#define SPI1STA_CSRSG_CLR (0x0 << 14 ) /* Cleared to 0 when the Status register is read */
3854#define SPI1STA_CSRSG_SET (0x1 << 14 ) /* Set to 1 when there was a rising edge in CS line, when the device was in master mode, continuous transfer, High Frequency mode and CSIRQ_EN was asserted. */
3855
3856/* SPI1STA[CSFLG] - Detected a falling edge on CS, in CONT mode */
3857#define SPI1STA_CSFLG_BBA (*(volatile unsigned long *) 0x42000034)
3858#define SPI1STA_CSFLG_MSK (0x1 << 13 )
3859#define SPI1STA_CSFLG (0x1 << 13 )
3860#define SPI1STA_CSFLG_CLR (0x0 << 13 ) /* Cleared to 0 when the Status register is read. */
3861#define SPI1STA_CSFLG_SET (0x1 << 13 ) /* Set to 1 when there was a falling edge in CS line, when the device was in master mode, continuous transfer, High Frequency mode and CSIRQ_EN was asserted. */
3862
3863/* SPI1STA[CSERR] - Detected an abrupt CS deassertion */
3864#define SPI1STA_CSERR_BBA (*(volatile unsigned long *) 0x42088030)
3865#define SPI1STA_CSERR_MSK (0x1 << 12 )
3866#define SPI1STA_CSERR (0x1 << 12 )
3867#define SPI1STA_CSERR_CLR (0x0 << 12 ) /* CLR */
3868#define SPI1STA_CSERR_SET (0x1 << 12 ) /* SET */
3869
3870/* SPI1STA[RXS] - Set when there are more bytes in the RX FIFO than the TIM bit says */
3871#define SPI1STA_RXS_BBA (*(volatile unsigned long *) 0x4208802C)
3872#define SPI1STA_RXS_MSK (0x1 << 11 )
3873#define SPI1STA_RXS (0x1 << 11 )
3874#define SPI1STA_RXS_CLR (0x0 << 11 ) /* CLR */
3875#define SPI1STA_RXS_SET (0x1 << 11 ) /* SET */
3876
3877/* SPI1STA[RXFSTA] - Receive FIFO Status */
3878#define SPI1STA_RXFSTA_MSK (0x7 << 8 )
3879#define SPI1STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY */
3880#define SPI1STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE */
3881#define SPI1STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES */
3882#define SPI1STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES */
3883#define SPI1STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES */
3884
3885/* SPI1STA[RXOF] - Receive FIFO overflow */
3886#define SPI1STA_RXOF_BBA (*(volatile unsigned long *) 0x4208801C)
3887#define SPI1STA_RXOF_MSK (0x1 << 7 )
3888#define SPI1STA_RXOF (0x1 << 7 )
3889#define SPI1STA_RXOF_CLR (0x0 << 7 ) /* CLR */
3890#define SPI1STA_RXOF_SET (0x1 << 7 ) /* SET */
3891
3892/* SPI1STA[RX] - Set when a receive interrupt occurs */
3893#define SPI1STA_RX_BBA (*(volatile unsigned long *) 0x42088018)
3894#define SPI1STA_RX_MSK (0x1 << 6 )
3895#define SPI1STA_RX (0x1 << 6 )
3896#define SPI1STA_RX_CLR (0x0 << 6 ) /* CLR */
3897#define SPI1STA_RX_SET (0x1 << 6 ) /* SET */
3898
3899/* SPI1STA[TX] - Set when a transmit interrupt occurs */
3900#define SPI1STA_TX_BBA (*(volatile unsigned long *) 0x42088014)
3901#define SPI1STA_TX_MSK (0x1 << 5 )
3902#define SPI1STA_TX (0x1 << 5 )
3903#define SPI1STA_TX_CLR (0x0 << 5 ) /* CLR */
3904#define SPI1STA_TX_SET (0x1 << 5 ) /* SET */
3905
3906/* SPI1STA[TXUR] - Transmit FIFO underflow */
3907#define SPI1STA_TXUR_BBA (*(volatile unsigned long *) 0x42088010)
3908#define SPI1STA_TXUR_MSK (0x1 << 4 )
3909#define SPI1STA_TXUR (0x1 << 4 )
3910#define SPI1STA_TXUR_CLR (0x0 << 4 ) /* CLR */
3911#define SPI1STA_TXUR_SET (0x1 << 4 ) /* SET */
3912
3913/* SPI1STA[TXFSTA] - transmit FIFO Status */
3914#define SPI1STA_TXFSTA_MSK (0x7 << 1 )
3915#define SPI1STA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY */
3916#define SPI1STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE */
3917#define SPI1STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES */
3918#define SPI1STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES */
3919#define SPI1STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES */
3920
3921/* SPI1STA[IRQ] - Interrupt status bit */
3922#define SPI1STA_IRQ_BBA (*(volatile unsigned long *) 0x42088000)
3923#define SPI1STA_IRQ_MSK (0x1 << 0 )
3924#define SPI1STA_IRQ (0x1 << 0 )
3925#define SPI1STA_IRQ_CLR (0x0 << 0 ) /* CLR */
3926#define SPI1STA_IRQ_SET (0x1 << 0 ) /* SET */
3927
3928/* Reset Value for SPI1RX*/
3929#define SPI1RX_RVAL 0x0
3930
3931/* SPI1RX[VALUE] - Received data */
3932#define SPI1RX_VALUE_MSK (0xFF << 0 )
3933
3934/* Reset Value for SPI1TX*/
3935#define SPI1TX_RVAL 0x0
3936
3937/* SPI1TX[VALUE] - Data to transmit */
3938#define SPI1TX_VALUE_MSK (0xFF << 0 )
3939
3940/* Reset Value for SPI1DIV*/
3941#define SPI1DIV_RVAL 0x0
3942
3943/* SPI1DIV[CSIRQ_EN] - Enable interrupt on every CS edge in CONT mode */
3944#define SPI1DIV_CSIRQ_EN_BBA (*(volatile unsigned long *) 0x420001A0)
3945#define SPI1DIV_CSIRQ_EN_MSK (0x1 << 8 )
3946#define SPI1DIV_CSIRQ_EN (0x1 << 8 )
3947#define SPI1DIV_CSIRQ_EN_DIS (0x0 << 8 )
3948#define SPI1DIV_CSIRQ_EN_EN (0x1 << 8 )
3949
3950/* SPI1DIV[BCRST] - Bit counter reset */
3951#define SPI1DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208819C)
3952#define SPI1DIV_BCRST_MSK (0x1 << 7 )
3953#define SPI1DIV_BCRST (0x1 << 7 )
3954#define SPI1DIV_BCRST_DIS (0x0 << 7 ) /* DIS */
3955#define SPI1DIV_BCRST_EN (0x1 << 7 ) /* EN */
3956
3957/* SPI1DIV[HFM] - High Frequency Mode */
3958#define SPI1DIV_HFM_BBA (*(volatile unsigned long *) 0x42000198)
3959#define SPI1DIV_HFM_MSK (0x1 << 6 )
3960#define SPI1DIV_HFM (0x1 << 6 )
3961#define SPI1DIV_HFM_DIS (0x0 << 6 )
3962#define SPI1DIV_HFM_EN (0x1 << 6 )
3963
3964/* SPI1DIV[DIV] - Factor used to divide UCLK to generate the serial clock */
3965#define SPI1DIV_DIV_MSK (0x3F << 0 )
3966
3967/* Reset Value for SPI1CON*/
3968#define SPI1CON_RVAL 0x0
3969
3970/* SPI1CON[MOD] - SPI IRQ Mode bits */
3971#define SPI1CON_MOD_MSK (0x3 << 14 )
3972#define SPI1CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1 */
3973#define SPI1CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2 */
3974#define SPI1CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3 */
3975#define SPI1CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4 */
3976
3977/* SPI1CON[TFLUSH] - TX FIFO Flush Enable bit */
3978#define SPI1CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42088234)
3979#define SPI1CON_TFLUSH_MSK (0x1 << 13 )
3980#define SPI1CON_TFLUSH (0x1 << 13 )
3981#define SPI1CON_TFLUSH_DIS (0x0 << 13 ) /* DIS */
3982#define SPI1CON_TFLUSH_EN (0x1 << 13 ) /* EN */
3983
3984/* SPI1CON[RFLUSH] - RX FIFO Flush Enable bit */
3985#define SPI1CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42088230)
3986#define SPI1CON_RFLUSH_MSK (0x1 << 12 )
3987#define SPI1CON_RFLUSH (0x1 << 12 )
3988#define SPI1CON_RFLUSH_DIS (0x0 << 12 ) /* DIS */
3989#define SPI1CON_RFLUSH_EN (0x1 << 12 ) /* EN */
3990
3991/* SPI1CON[CON] - Continuous transfer enable */
3992#define SPI1CON_CON_BBA (*(volatile unsigned long *) 0x4208822C)
3993#define SPI1CON_CON_MSK (0x1 << 11 )
3994#define SPI1CON_CON (0x1 << 11 )
3995#define SPI1CON_CON_DIS (0x0 << 11 ) /* DIS */
3996#define SPI1CON_CON_EN (0x1 << 11 ) /* EN */
3997
3998/* SPI1CON[LOOPBACK] - Loopback enable bit */
3999#define SPI1CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42088228)
4000#define SPI1CON_LOOPBACK_MSK (0x1 << 10 )
4001#define SPI1CON_LOOPBACK (0x1 << 10 )
4002#define SPI1CON_LOOPBACK_DIS (0x0 << 10 ) /* DIS */
4003#define SPI1CON_LOOPBACK_EN (0x1 << 10 ) /* EN */
4004
4005/* SPI1CON[SOEN] - Slave MISO output enable bit */
4006#define SPI1CON_SOEN_BBA (*(volatile unsigned long *) 0x42088224)
4007#define SPI1CON_SOEN_MSK (0x1 << 9 )
4008#define SPI1CON_SOEN (0x1 << 9 )
4009#define SPI1CON_SOEN_DIS (0x0 << 9 ) /* DIS */
4010#define SPI1CON_SOEN_EN (0x1 << 9 ) /* EN */
4011
4012/* SPI1CON[RXOF] - RX Oveflow Overwrite enable */
4013#define SPI1CON_RXOF_BBA (*(volatile unsigned long *) 0x42088220)
4014#define SPI1CON_RXOF_MSK (0x1 << 8 )
4015#define SPI1CON_RXOF (0x1 << 8 )
4016#define SPI1CON_RXOF_DIS (0x0 << 8 ) /* DIS */
4017#define SPI1CON_RXOF_EN (0x1 << 8 ) /* EN */
4018
4019/* SPI1CON[ZEN] - Transmit zeros when empty */
4020#define SPI1CON_ZEN_BBA (*(volatile unsigned long *) 0x4208821C)
4021#define SPI1CON_ZEN_MSK (0x1 << 7 )
4022#define SPI1CON_ZEN (0x1 << 7 )
4023#define SPI1CON_ZEN_DIS (0x0 << 7 ) /* DIS */
4024#define SPI1CON_ZEN_EN (0x1 << 7 ) /* EN */
4025
4026/* SPI1CON[TIM] - Transfer and interrupt mode */
4027#define SPI1CON_TIM_BBA (*(volatile unsigned long *) 0x42088218)
4028#define SPI1CON_TIM_MSK (0x1 << 6 )
4029#define SPI1CON_TIM (0x1 << 6 )
4030#define SPI1CON_TIM_RXRD (0x0 << 6 ) /* RXRD - Cleared by user to initiate transfer with a read of the SPIRX register */
4031#define SPI1CON_TIM_TXWR (0x1 << 6 ) /* TXWR - Set by user to initiate transfer with a write to the SPITX register. */
4032
4033/* SPI1CON[LSB] - LSB First Transfer enable */
4034#define SPI1CON_LSB_BBA (*(volatile unsigned long *) 0x42088214)
4035#define SPI1CON_LSB_MSK (0x1 << 5 )
4036#define SPI1CON_LSB (0x1 << 5 )
4037#define SPI1CON_LSB_DIS (0x0 << 5 ) /* DIS */
4038#define SPI1CON_LSB_EN (0x1 << 5 ) /* EN */
4039
4040/* SPI1CON[WOM] - Wired OR enable */
4041#define SPI1CON_WOM_BBA (*(volatile unsigned long *) 0x42088210)
4042#define SPI1CON_WOM_MSK (0x1 << 4 )
4043#define SPI1CON_WOM (0x1 << 4 )
4044#define SPI1CON_WOM_DIS (0x0 << 4 ) /* DIS */
4045#define SPI1CON_WOM_EN (0x1 << 4 ) /* EN */
4046
4047/* SPI1CON[CPOL] - Clock polarity mode */
4048#define SPI1CON_CPOL_BBA (*(volatile unsigned long *) 0x4208820C)
4049#define SPI1CON_CPOL_MSK (0x1 << 3 )
4050#define SPI1CON_CPOL (0x1 << 3 )
4051#define SPI1CON_CPOL_LOW (0x0 << 3 ) /* LOW */
4052#define SPI1CON_CPOL_HIGH (0x1 << 3 ) /* HIGH */
4053
4054/* SPI1CON[CPHA] - Clock phase mode */
4055#define SPI1CON_CPHA_BBA (*(volatile unsigned long *) 0x42088208)
4056#define SPI1CON_CPHA_MSK (0x1 << 2 )
4057#define SPI1CON_CPHA (0x1 << 2 )
4058#define SPI1CON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING */
4059#define SPI1CON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING */
4060
4061/* SPI1CON[MASEN] - Master enable */
4062#define SPI1CON_MASEN_BBA (*(volatile unsigned long *) 0x42088204)
4063#define SPI1CON_MASEN_MSK (0x1 << 1 )
4064#define SPI1CON_MASEN (0x1 << 1 )
4065#define SPI1CON_MASEN_DIS (0x0 << 1 ) /* DIS */
4066#define SPI1CON_MASEN_EN (0x1 << 1 ) /* EN */
4067
4068/* SPI1CON[ENABLE] - SPI Enable bit */
4069#define SPI1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42088200)
4070#define SPI1CON_ENABLE_MSK (0x1 << 0 )
4071#define SPI1CON_ENABLE (0x1 << 0 )
4072#define SPI1CON_ENABLE_DIS (0x0 << 0 ) /* DIS */
4073#define SPI1CON_ENABLE_EN (0x1 << 0 ) /* EN */
4074
4075/* Reset Value for SPI1DMA*/
4076#define SPI1DMA_RVAL 0x0
4077
4078/* SPI1DMA[IENRXDMA] - Enable receive DMA request */
4079#define SPI1DMA_IENRXDMA_BBA (*(volatile unsigned long *) 0x42088288)
4080#define SPI1DMA_IENRXDMA_MSK (0x1 << 2 )
4081#define SPI1DMA_IENRXDMA (0x1 << 2 )
4082#define SPI1DMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS */
4083#define SPI1DMA_IENRXDMA_EN (0x1 << 2 ) /* EN */
4084
4085/* SPI1DMA[IENTXDMA] - Enable transmit DMA request */
4086#define SPI1DMA_IENTXDMA_BBA (*(volatile unsigned long *) 0x42088284)
4087#define SPI1DMA_IENTXDMA_MSK (0x1 << 1 )
4088#define SPI1DMA_IENTXDMA (0x1 << 1 )
4089#define SPI1DMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS */
4090#define SPI1DMA_IENTXDMA_EN (0x1 << 1 ) /* EN */
4091
4092/* SPI1DMA[ENABLE] - Enable DMA for data transfer */
4093#define SPI1DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42088280)
4094#define SPI1DMA_ENABLE_MSK (0x1 << 0 )
4095#define SPI1DMA_ENABLE (0x1 << 0 )
4096#define SPI1DMA_ENABLE_DIS (0x0 << 0 ) /* DIS */
4097#define SPI1DMA_ENABLE_EN (0x1 << 0 ) /* EN */
4098
4099/* Reset Value for SPI1CNT*/
4100#define SPI1CNT_RVAL 0x0
4101
4102/* SPI1CNT[VALUE] - Count */
4103#define SPI1CNT_VALUE_MSK (0xFF << 0 )
4104// ------------------------------------------------------------------------------------------------
4105// ----- UART -----
4106// ------------------------------------------------------------------------------------------------
4107
4108
4109/**
4110 * @brief UART (pADI_UART)
4111 */
4112
4113#if (__NO_MMR_STRUCTS__==0)
4114typedef struct { /*!< pADI_UART Structure */
4115
4116 union {
4117 __IO uint8_t COMTX; /*!< Transmit Holding register */
4118 __IO uint8_t COMRX; /*!< Receive Buffer register */
4119 } ;
4120 __I uint8_t RESERVED0[3];
4121 __IO uint8_t COMIEN; /*!< Interrupt Enable register */
4122 __I uint8_t RESERVED1[3];
4123 __IO uint8_t COMIIR; /*!< Interrupt Identification register */
4124 __I uint8_t RESERVED2[3];
4125 __IO uint8_t COMLCR; /*!< Line Control register */
4126 __I uint8_t RESERVED3[3];
4127 __IO uint8_t COMMCR; /*!< Module Control register */
4128 __I uint8_t RESERVED4[3];
4129 __IO uint8_t COMLSR; /*!< Line Status register */
4130 __I uint8_t RESERVED5[3];
4131 __IO uint8_t COMMSR; /*!< Modem Status register */
4132 __I uint8_t RESERVED6[11];
4133 __IO uint16_t COMFBR; /*!< Fractional baud rate divider register. */
4134 __I uint16_t RESERVED7;
4135 __IO uint16_t COMDIV; /*!< Baud rate Divisor register */
4136 __I uint16_t RESERVED8[3];
4137 __IO uint8_t COMCON; /*!< UART control register */
4138} ADI_UART_TypeDef;
4139#else // (__NO_MMR_STRUCTS__==0)
4140#define COM0TX (*(volatile unsigned char *) 0x40005000)
4141#define COM0RX (*(volatile unsigned char *) 0x40005000)
4142#define COM0IEN (*(volatile unsigned char *) 0x40005004)
4143#define COM0IIR (*(volatile unsigned char *) 0x40005008)
4144#define COM0LCR (*(volatile unsigned char *) 0x4000500C)
4145#define COM0MCR (*(volatile unsigned char *) 0x40005010)
4146#define COM0LSR (*(volatile unsigned char *) 0x40005014)
4147#define COM0MSR (*(volatile unsigned char *) 0x40005018)
4148#define COM0FBR (*(volatile unsigned short int *) 0x40005024)
4149#define COM0DIV (*(volatile unsigned short int *) 0x40005028)
4150#define COM0CON (*(volatile unsigned char *) 0x40005030)
4151#define COM1TX (*(volatile unsigned char *) 0x40005400)
4152#define COM1RX (*(volatile unsigned char *) 0x40005400)
4153#define COM1IEN (*(volatile unsigned char *) 0x40005404)
4154#define COM1IIR (*(volatile unsigned char *) 0x40005408)
4155#define COM1LCR (*(volatile unsigned char *) 0x4000540C)
4156#define COM1MCR (*(volatile unsigned char *) 0x40005410)
4157#define COM1LSR (*(volatile unsigned char *) 0x40005414)
4158#define COM1MSR (*(volatile unsigned char *) 0x40005418)
4159#define COM1FBR (*(volatile unsigned short int *) 0x40005424)
4160#define COM1DIV (*(volatile unsigned short int *) 0x40005428)
4161#define COM1CON (*(volatile unsigned char *) 0x40005430)
4162#define COM2TX (*(volatile unsigned char *) 0x40005800)
4163#define COM2RX (*(volatile unsigned char *) 0x40005800)
4164#define COM2IEN (*(volatile unsigned char *) 0x40005804)
4165#define COM2IIR (*(volatile unsigned char *) 0x40005808)
4166#define COM2LCR (*(volatile unsigned char *) 0x4000580C)
4167#define COM2MCR (*(volatile unsigned char *) 0x40005810)
4168#define COM2LSR (*(volatile unsigned char *) 0x40005814)
4169#define COM2MSR (*(volatile unsigned char *) 0x40005818)
4170#define COM2FBR (*(volatile unsigned short int *) 0x40005824)
4171#define COM2DIV (*(volatile unsigned short int *) 0x40005828)
4172#define COM2CON (*(volatile unsigned char *) 0x40005830)
4173
4174#endif // (__NO_MMR_STRUCTS__==0)
4175
4176/* Reset Value for COMTX*/
4177#define COMTX_RVAL 0x0
4178
4179/* COMTX[VALUE] - Value */
4180#define COMTX_VALUE_MSK (0xFF << 0 )
4181
4182/* Reset Value for COMRX*/
4183#define COMRX_RVAL 0x0
4184
4185/* COMRX[VALUE] - Value */
4186#define COMRX_VALUE_MSK (0xFF << 0 )
4187
4188/* Reset Value for COMIEN*/
4189#define COMIEN_RVAL 0x0
4190
4191/* COMIEN[EDMAR] - Enable DMA requests in transmit mode */
4192#define COMIEN_EDMAR_BBA (*(volatile unsigned long *) 0x420A0094)
4193#define COMIEN_EDMAR_MSK (0x1 << 5 )
4194#define COMIEN_EDMAR (0x1 << 5 )
4195#define COMIEN_EDMAR_DIS (0x0 << 5 ) /* DIS */
4196#define COMIEN_EDMAR_EN (0x1 << 5 ) /* EN */
4197
4198/* COMIEN[EDMAT] - Enable DMA requests in receive mode */
4199#define COMIEN_EDMAT_BBA (*(volatile unsigned long *) 0x420A0090)
4200#define COMIEN_EDMAT_MSK (0x1 << 4 )
4201#define COMIEN_EDMAT (0x1 << 4 )
4202#define COMIEN_EDMAT_DIS (0x0 << 4 ) /* DIS */
4203#define COMIEN_EDMAT_EN (0x1 << 4 ) /* EN */
4204
4205/* COMIEN[EDSSI] - Enable Modem Status interrupt */
4206#define COMIEN_EDSSI_BBA (*(volatile unsigned long *) 0x420A008C)
4207#define COMIEN_EDSSI_MSK (0x1 << 3 )
4208#define COMIEN_EDSSI (0x1 << 3 )
4209#define COMIEN_EDSSI_DIS (0x0 << 3 ) /* DIS */
4210#define COMIEN_EDSSI_EN (0x1 << 3 ) /* EN */
4211
4212/* COMIEN[ELSI] - Enable Rx status interrupt */
4213#define COMIEN_ELSI_BBA (*(volatile unsigned long *) 0x420A0088)
4214#define COMIEN_ELSI_MSK (0x1 << 2 )
4215#define COMIEN_ELSI (0x1 << 2 )
4216#define COMIEN_ELSI_DIS (0x0 << 2 ) /* DIS */
4217#define COMIEN_ELSI_EN (0x1 << 2 ) /* EN */
4218
4219/* COMIEN[ETBEI] - Enable transmit buffer empty interrupt */
4220#define COMIEN_ETBEI_BBA (*(volatile unsigned long *) 0x420A0084)
4221#define COMIEN_ETBEI_MSK (0x1 << 1 )
4222#define COMIEN_ETBEI (0x1 << 1 )
4223#define COMIEN_ETBEI_DIS (0x0 << 1 ) /* DIS */
4224#define COMIEN_ETBEI_EN (0x1 << 1 ) /* EN */
4225
4226/* COMIEN[ERBFI] - Enable receive buffer full interrupt */
4227#define COMIEN_ERBFI_BBA (*(volatile unsigned long *) 0x420A0080)
4228#define COMIEN_ERBFI_MSK (0x1 << 0 )
4229#define COMIEN_ERBFI (0x1 << 0 )
4230#define COMIEN_ERBFI_DIS (0x0 << 0 ) /* DIS */
4231#define COMIEN_ERBFI_EN (0x1 << 0 ) /* EN */
4232
4233/* Reset Value for COMIIR*/
4234#define COMIIR_RVAL 0x1
4235
4236/* COMIIR[STA] - Status bits. */
4237#define COMIIR_STA_MSK (0x3 << 1 )
4238#define COMIIR_STA_MODEMSTATUS (0x0 << 1 ) /* MODEMSTATUS - Modem status interrupt. */
4239#define COMIIR_STA_TXBUFEMPTY (0x1 << 1 ) /* TXBUFEMPTY - Transmit buffer empty interrupt. */
4240#define COMIIR_STA_RXBUFFULL (0x2 << 1 ) /* RXBUFFULL - Receive buffer full interrupt. Read RBR register to clear. */
4241#define COMIIR_STA_RXLINESTATUS (0x3 << 1 ) /* RXLINESTATUS - Receive line status interrupt. Read LSR register to clear. */
4242
4243/* COMIIR[NINT] - Interrupt flag. */
4244#define COMIIR_NINT_BBA (*(volatile unsigned long *) 0x420A0100)
4245#define COMIIR_NINT_MSK (0x1 << 0 )
4246#define COMIIR_NINT (0x1 << 0 )
4247#define COMIIR_NINT_CLR (0x0 << 0 ) /* CLR */
4248#define COMIIR_NINT_SET (0x1 << 0 ) /* SET */
4249
4250/* Reset Value for COMLCR*/
4251#define COMLCR_RVAL 0x0
4252
4253/* COMLCR[BRK] - Set Break. */
4254#define COMLCR_BRK_BBA (*(volatile unsigned long *) 0x420A0198)
4255#define COMLCR_BRK_MSK (0x1 << 6 )
4256#define COMLCR_BRK (0x1 << 6 )
4257#define COMLCR_BRK_DIS (0x0 << 6 ) /* DIS */
4258#define COMLCR_BRK_EN (0x1 << 6 ) /* EN */
4259
4260/* COMLCR[SP] - Stick Parity. */
4261#define COMLCR_SP_BBA (*(volatile unsigned long *) 0x420A0194)
4262#define COMLCR_SP_MSK (0x1 << 5 )
4263#define COMLCR_SP (0x1 << 5 )
4264#define COMLCR_SP_DIS (0x0 << 5 ) /* DIS */
4265#define COMLCR_SP_EN (0x1 << 5 ) /* EN */
4266
4267/* COMLCR[EPS] - Even Parity Select Bit. */
4268#define COMLCR_EPS_BBA (*(volatile unsigned long *) 0x420A0190)
4269#define COMLCR_EPS_MSK (0x1 << 4 )
4270#define COMLCR_EPS (0x1 << 4 )
4271#define COMLCR_EPS_DIS (0x0 << 4 ) /* DIS */
4272#define COMLCR_EPS_EN (0x1 << 4 ) /* EN */
4273
4274/* COMLCR[PEN] - Parity Enable Bit. */
4275#define COMLCR_PEN_BBA (*(volatile unsigned long *) 0x420A018C)
4276#define COMLCR_PEN_MSK (0x1 << 3 )
4277#define COMLCR_PEN (0x1 << 3 )
4278#define COMLCR_PEN_DIS (0x0 << 3 ) /* DIS */
4279#define COMLCR_PEN_EN (0x1 << 3 ) /* EN */
4280
4281/* COMLCR[STOP] - Stop Bit. */
4282#define COMLCR_STOP_BBA (*(volatile unsigned long *) 0x420A0188)
4283#define COMLCR_STOP_MSK (0x1 << 2 )
4284#define COMLCR_STOP (0x1 << 2 )
4285#define COMLCR_STOP_DIS (0x0 << 2 ) /* DIS */
4286#define COMLCR_STOP_EN (0x1 << 2 ) /* EN */
4287
4288/* COMLCR[WLS] - Word Length Select bits */
4289#define COMLCR_WLS_MSK (0x3 << 0 )
4290#define COMLCR_WLS_5BITS (0x0 << 0 ) /* 5BITS */
4291#define COMLCR_WLS_6BITS (0x1 << 0 ) /* 6BITS */
4292#define COMLCR_WLS_7BITS (0x2 << 0 ) /* 7BITS */
4293#define COMLCR_WLS_8BITS (0x3 << 0 ) /* 8BITS */
4294
4295/* Reset Value for COMMCR*/
4296#define COMMCR_RVAL 0x0
4297
4298/* COMMCR[LOOPBACK] - Loop Back. */
4299#define COMMCR_LOOPBACK_BBA (*(volatile unsigned long *) 0x420A0210)
4300#define COMMCR_LOOPBACK_MSK (0x1 << 4 )
4301#define COMMCR_LOOPBACK (0x1 << 4 )
4302#define COMMCR_LOOPBACK_DIS (0x0 << 4 ) /* DIS */
4303#define COMMCR_LOOPBACK_EN (0x1 << 4 ) /* EN */
4304
4305/* COMMCR[OUT1] - Parity Enable Bit. */
4306#define COMMCR_OUT1_BBA (*(volatile unsigned long *) 0x420A020C)
4307#define COMMCR_OUT1_MSK (0x1 << 3 )
4308#define COMMCR_OUT1 (0x1 << 3 )
4309#define COMMCR_OUT1_DIS (0x0 << 3 ) /* DIS */
4310#define COMMCR_OUT1_EN (0x1 << 3 ) /* EN */
4311
4312/* COMMCR[OUT2] - Stop Bit. */
4313#define COMMCR_OUT2_BBA (*(volatile unsigned long *) 0x420A0208)
4314#define COMMCR_OUT2_MSK (0x1 << 2 )
4315#define COMMCR_OUT2 (0x1 << 2 )
4316#define COMMCR_OUT2_DIS (0x0 << 2 ) /* DIS */
4317#define COMMCR_OUT2_EN (0x1 << 2 ) /* EN */
4318
4319/* COMMCR[RTS] - Request To Send. */
4320#define COMMCR_RTS_BBA (*(volatile unsigned long *) 0x420A0204)
4321#define COMMCR_RTS_MSK (0x1 << 1 )
4322#define COMMCR_RTS (0x1 << 1 )
4323#define COMMCR_RTS_DIS (0x0 << 1 ) /* DIS */
4324#define COMMCR_RTS_EN (0x1 << 1 ) /* EN */
4325
4326/* COMMCR[DTR] - Data Terminal Ready. */
4327#define COMMCR_DTR_BBA (*(volatile unsigned long *) 0x420A0200)
4328#define COMMCR_DTR_MSK (0x1 << 0 )
4329#define COMMCR_DTR (0x1 << 0 )
4330#define COMMCR_DTR_DIS (0x0 << 0 ) /* DIS */
4331#define COMMCR_DTR_EN (0x1 << 0 ) /* EN */
4332
4333/* Reset Value for COMLSR*/
4334#define COMLSR_RVAL 0x60
4335
4336/* COMLSR[TEMT] - COMTX and Shift Register Empty Status Bit. */
4337#define COMLSR_TEMT_BBA (*(volatile unsigned long *) 0x420A0298)
4338#define COMLSR_TEMT_MSK (0x1 << 6 )
4339#define COMLSR_TEMT (0x1 << 6 )
4340#define COMLSR_TEMT_CLR (0x0 << 6 ) /* CLR */
4341#define COMLSR_TEMT_SET (0x1 << 6 ) /* SET */
4342
4343/* COMLSR[THRE] - COMTX Empty Status Bit. */
4344#define COMLSR_THRE_BBA (*(volatile unsigned long *) 0x420A0294)
4345#define COMLSR_THRE_MSK (0x1 << 5 )
4346#define COMLSR_THRE (0x1 << 5 )
4347#define COMLSR_THRE_CLR (0x0 << 5 ) /* CLR */
4348#define COMLSR_THRE_SET (0x1 << 5 ) /* SET */
4349
4350/* COMLSR[BI] - Break Indicator. */
4351#define COMLSR_BI_BBA (*(volatile unsigned long *) 0x420A0290)
4352#define COMLSR_BI_MSK (0x1 << 4 )
4353#define COMLSR_BI (0x1 << 4 )
4354#define COMLSR_BI_CLR (0x0 << 4 ) /* CLR */
4355#define COMLSR_BI_SET (0x1 << 4 ) /* SET */
4356
4357/* COMLSR[FE] - Framing Error. */
4358#define COMLSR_FE_BBA (*(volatile unsigned long *) 0x420A028C)
4359#define COMLSR_FE_MSK (0x1 << 3 )
4360#define COMLSR_FE (0x1 << 3 )
4361#define COMLSR_FE_CLR (0x0 << 3 ) /* CLR */
4362#define COMLSR_FE_SET (0x1 << 3 ) /* SET */
4363
4364/* COMLSR[PE] - Parity Error. */
4365#define COMLSR_PE_BBA (*(volatile unsigned long *) 0x420A0288)
4366#define COMLSR_PE_MSK (0x1 << 2 )
4367#define COMLSR_PE (0x1 << 2 )
4368#define COMLSR_PE_CLR (0x0 << 2 ) /* CLR */
4369#define COMLSR_PE_SET (0x1 << 2 ) /* SET */
4370
4371/* COMLSR[OE] - Overrun Error. */
4372#define COMLSR_OE_BBA (*(volatile unsigned long *) 0x420A0284)
4373#define COMLSR_OE_MSK (0x1 << 1 )
4374#define COMLSR_OE (0x1 << 1 )
4375#define COMLSR_OE_CLR (0x0 << 1 ) /* CLR */
4376#define COMLSR_OE_SET (0x1 << 1 ) /* SET */
4377
4378/* COMLSR[DR] - Data Ready. */
4379#define COMLSR_DR_BBA (*(volatile unsigned long *) 0x420A0280)
4380#define COMLSR_DR_MSK (0x1 << 0 )
4381#define COMLSR_DR (0x1 << 0 )
4382#define COMLSR_DR_CLR (0x0 << 0 ) /* CLR */
4383#define COMLSR_DR_SET (0x1 << 0 ) /* SET */
4384
4385/* Reset Value for COMMSR*/
4386#define COMMSR_RVAL 0x0
4387
4388/* COMMSR[DCD] - Data Carrier Detect. */
4389#define COMMSR_DCD_BBA (*(volatile unsigned long *) 0x420A031C)
4390#define COMMSR_DCD_MSK (0x1 << 7 )
4391#define COMMSR_DCD (0x1 << 7 )
4392#define COMMSR_DCD_DIS (0x0 << 7 ) /* DIS */
4393#define COMMSR_DCD_EN (0x1 << 7 ) /* EN */
4394
4395/* COMMSR[RI] - Ring Indicator. */
4396#define COMMSR_RI_BBA (*(volatile unsigned long *) 0x420A0318)
4397#define COMMSR_RI_MSK (0x1 << 6 )
4398#define COMMSR_RI (0x1 << 6 )
4399#define COMMSR_RI_DIS (0x0 << 6 ) /* DIS */
4400#define COMMSR_RI_EN (0x1 << 6 ) /* EN */
4401
4402/* COMMSR[DSR] - Data Set Ready. */
4403#define COMMSR_DSR_BBA (*(volatile unsigned long *) 0x420A0314)
4404#define COMMSR_DSR_MSK (0x1 << 5 )
4405#define COMMSR_DSR (0x1 << 5 )
4406#define COMMSR_DSR_DIS (0x0 << 5 ) /* DIS */
4407#define COMMSR_DSR_EN (0x1 << 5 ) /* EN */
4408
4409/* COMMSR[CTS] - Clear To Send. */
4410#define COMMSR_CTS_BBA (*(volatile unsigned long *) 0x420A0310)
4411#define COMMSR_CTS_MSK (0x1 << 4 )
4412#define COMMSR_CTS (0x1 << 4 )
4413#define COMMSR_CTS_DIS (0x0 << 4 ) /* DIS */
4414#define COMMSR_CTS_EN (0x1 << 4 ) /* EN */
4415
4416/* COMMSR[DDCD] - Delta DCD. */
4417#define COMMSR_DDCD_BBA (*(volatile unsigned long *) 0x420A030C)
4418#define COMMSR_DDCD_MSK (0x1 << 3 )
4419#define COMMSR_DDCD (0x1 << 3 )
4420#define COMMSR_DDCD_DIS (0x0 << 3 ) /* DIS */
4421#define COMMSR_DDCD_EN (0x1 << 3 ) /* EN */
4422
4423/* COMMSR[TERI] - Trailing Edge RI. */
4424#define COMMSR_TERI_BBA (*(volatile unsigned long *) 0x420A0308)
4425#define COMMSR_TERI_MSK (0x1 << 2 )
4426#define COMMSR_TERI (0x1 << 2 )
4427#define COMMSR_TERI_DIS (0x0 << 2 ) /* DIS */
4428#define COMMSR_TERI_EN (0x1 << 2 ) /* EN */
4429
4430/* COMMSR[DDSR] - Delta DSR. */
4431#define COMMSR_DDSR_BBA (*(volatile unsigned long *) 0x420A0304)
4432#define COMMSR_DDSR_MSK (0x1 << 1 )
4433#define COMMSR_DDSR (0x1 << 1 )
4434#define COMMSR_DDSR_DIS (0x0 << 1 ) /* DIS */
4435#define COMMSR_DDSR_EN (0x1 << 1 ) /* EN */
4436
4437/* COMMSR[DCTS] - Delta CTS. */
4438#define COMMSR_DCTS_BBA (*(volatile unsigned long *) 0x420A0300)
4439#define COMMSR_DCTS_MSK (0x1 << 0 )
4440#define COMMSR_DCTS (0x1 << 0 )
4441#define COMMSR_DCTS_DIS (0x0 << 0 ) /* DIS */
4442#define COMMSR_DCTS_EN (0x1 << 0 ) /* EN */
4443
4444/* Reset Value for COMFBR*/
4445#define COMFBR_RVAL 0x0
4446
4447/* COMFBR[ENABLE] - Enable */
4448#define COMFBR_ENABLE_BBA (*(volatile unsigned long *) 0x420A04BC)
4449#define COMFBR_ENABLE_MSK (0x1 << 15 )
4450#define COMFBR_ENABLE (0x1 << 15 )
4451#define COMFBR_ENABLE_DIS (0x0 << 15 ) /* DIS */
4452#define COMFBR_ENABLE_EN (0x1 << 15 ) /* EN */
4453
4454/* COMFBR[DIVM] - Fractional M Divide bits */
4455#define COMFBR_DIVM_MSK (0x3 << 11 )
4456
4457/* COMFBR[DIVN] - Fractional N Divide bits */
4458#define COMFBR_DIVN_MSK (0x7FF << 0 )
4459
4460/* Reset Value for COMDIV*/
4461#define COMDIV_RVAL 0x1
4462
4463/* COMDIV[VALUE] - Sets the baudrate */
4464#define COMDIV_VALUE_MSK (0xFFFF << 0 )
4465
4466/* Reset Value for COMCON*/
4467#define COMCON_RVAL 0x0
4468
4469/* COMCON[DISABLE] - Uart Disable */
4470#define COMCON_DISABLE_BBA (*(volatile unsigned long *) 0x420A0600)
4471#define COMCON_DISABLE_MSK (0x1 << 0 )
4472#define COMCON_DISABLE (0x1 << 0 )
4473#define COMCON_DISABLE_DIS (0x0 << 0 ) /* DIS */
4474#define COMCON_DISABLE_EN (0x1 << 0 ) /* EN */
4475// ------------------------------------------------------------------------------------------------
4476// ----- GPIO0 -----
4477// ------------------------------------------------------------------------------------------------
4478
4479
4480/**
4481 * @brief General Purpose Input Output (pADI_GP0)
4482 */
4483
4484#if (__NO_MMR_STRUCTS__==0)
4485typedef struct { /*!< pADI_GP0 Structure */
4486 __IO uint16_t GPCON; /*!< GPIO Port 0 configuration */
4487 __I uint16_t RESERVED0;
4488 __IO uint8_t GPOEN; /*!< GPIO Port 0 output enable */
4489 __I uint8_t RESERVED1[3];
4490 __IO uint8_t GPPUL; /*!< GPIO Port 0 output pull up enable. */
4491 __I uint8_t RESERVED2[3];
4492 __IO uint8_t GPOCE; /*!< GPIO Port 0 tri state */
4493 __I uint8_t RESERVED3[7];
4494 __IO uint8_t GPIN; /*!< GPIO Port 0 data input. */
4495 __I uint8_t RESERVED4[3];
4496 __IO uint8_t GPOUT; /*!< GPIO Port 0 data out. */
4497 __I uint8_t RESERVED5[3];
4498 __IO uint8_t GPSET; /*!< GPIO Port 0 data out set */
4499 __I uint8_t RESERVED6[3];
4500 __IO uint8_t GPCLR; /*!< GPIO Port 0 data out clear. */
4501 __I uint8_t RESERVED7[3];
4502 __IO uint8_t GPTGL; /*!< GPIO Port 0 pin toggle. */
4503} ADI_GPIO_TypeDef;
4504#else // (__NO_MMR_STRUCTS__==0)
4505#define GP0CON (*(volatile unsigned short int *) 0x40006000)
4506#define GP0OEN (*(volatile unsigned char *) 0x40006004)
4507#define GP0PUL (*(volatile unsigned char *) 0x40006008)
4508#define GP0OCE (*(volatile unsigned char *) 0x4000600C)
4509#define GP0IN (*(volatile unsigned char *) 0x40006014)
4510#define GP0OUT (*(volatile unsigned char *) 0x40006018)
4511#define GP0SET (*(volatile unsigned char *) 0x4000601C)
4512#define GP0CLR (*(volatile unsigned char *) 0x40006020)
4513#define GP0TGL (*(volatile unsigned char *) 0x40006024)
4514#endif // (__NO_MMR_STRUCTS__==0)
4515
4516/* Reset Value for GP0CON*/
4517#define GP0CON_RVAL 0x0
4518
4519/* GP0CON[CON7] - Configuration bits for P0.7 */
4520#define GP0CON_CON7_MSK (0x3 << 14 )
4521#define GP0CON_CON7_PORB (0x0 << 14 ) /* PORB */
4522#define GP0CON_CON7_GPIO (0x1 << 14 ) /* GPIO */
4523#define GP0CON_CON7_UARTTXD (0x2 << 14 ) /* UARTTXD */
4524
4525/* GP0CON[CON6] - Configuration bits for P0.6 */
4526#define GP0CON_CON6_MSK (0x3 << 12 )
4527#define GP0CON_CON6_GPIOIRQ2 (0x0 << 12 ) /* GPIOIRQ2 */
4528#define GP0CON_CON6_UARTRXD (0x1 << 12 ) /* UARTRXD */
4529
4530/* GP0CON[CON5] - Configuration bits for P0.5 */
4531#define GP0CON_CON5_MSK (0x3 << 10 )
4532#define GP0CON_CON5_GPIOIRQ1 (0x0 << 10 ) /* GPIOIRQ1 */
4533#define GP0CON_CON5_UARTCTS (0x1 << 10 ) /* UARTCTS */
4534
4535/* GP0CON[CON4] - Configuration bits for P0.4 */
4536#define GP0CON_CON4_MSK (0x3 << 8 )
4537#define GP0CON_CON4_GPIO (0x0 << 8 ) /* GPIO */
4538#define GP0CON_CON4_UARTRTS (0x1 << 8 ) /* UARTRTS */
4539#define GP0CON_CON4_ECLKOUT (0x2 << 8 ) /* ECLKOUT */
4540
4541/* GP0CON[CON3] - Configuration bits for P0.3 */
4542#define GP0CON_CON3_MSK (0x3 << 6 )
4543#define GP0CON_CON3_GPIOIRQ0 (0x0 << 6 ) /* GPIOIRQ0 */
4544#define GP0CON_CON3_SPI1CS0 (0x1 << 6 ) /* SPI1CS0 */
4545
4546/* GP0CON[CON2] - Configuration bits for P0.2 */
4547#define GP0CON_CON2_MSK (0x3 << 4 )
4548#define GP0CON_CON2_GPIO (0x0 << 4 ) /* GPIO */
4549#define GP0CON_CON2_SPI1MOSI (0x1 << 4 ) /* SPI1MOSI */
4550#define GP0CON_CON2_I2CSDA (0x2 << 4 ) /* I2CSDA */
4551#define GP0CON_CON2_UARTTXD (0x3 << 4 ) /* UARTTXD */
4552
4553/* GP0CON[CON1] - Configuration bits for P0.1 */
4554#define GP0CON_CON1_MSK (0x3 << 2 )
4555#define GP0CON_CON1_GPIO (0x0 << 2 ) /* GPIO */
4556#define GP0CON_CON1_SPI1SCLK (0x1 << 2 ) /* SPI1SCLK */
4557#define GP0CON_CON1_I2CSCL (0x2 << 2 ) /* I2CSCL */
4558#define GP0CON_CON1_UARTRXD (0x3 << 2 ) /* UARTRXD */
4559
4560/* GP0CON[CON0] - Configuration bits for P0.0 */
4561#define GP0CON_CON0_MSK (0x3 << 0 )
4562#define GP0CON_CON0_GPIO (0x0 << 0 ) /* GPIO */
4563#define GP0CON_CON0_SPI1MISO (0x1 << 0 ) /* SPI1MISO */
4564
4565/* Reset Value for GP0OEN*/
4566#define GP0OEN_RVAL 0x0
4567
4568/* GP0OEN[OEN7] - Direction for port pin */
4569#define GP0OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C009C)
4570#define GP0OEN_OEN7_MSK (0x1 << 7 )
4571#define GP0OEN_OEN7 (0x1 << 7 )
4572#define GP0OEN_OEN7_IN (0x0 << 7 ) /* IN */
4573#define GP0OEN_OEN7_OUT (0x1 << 7 ) /* OUT */
4574
4575/* GP0OEN[OEN6] - Direction for port pin */
4576#define GP0OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0098)
4577#define GP0OEN_OEN6_MSK (0x1 << 6 )
4578#define GP0OEN_OEN6 (0x1 << 6 )
4579#define GP0OEN_OEN6_IN (0x0 << 6 ) /* IN */
4580#define GP0OEN_OEN6_OUT (0x1 << 6 ) /* OUT */
4581
4582/* GP0OEN[OEN5] - Direction for port pin */
4583#define GP0OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0094)
4584#define GP0OEN_OEN5_MSK (0x1 << 5 )
4585#define GP0OEN_OEN5 (0x1 << 5 )
4586#define GP0OEN_OEN5_IN (0x0 << 5 ) /* IN */
4587#define GP0OEN_OEN5_OUT (0x1 << 5 ) /* OUT */
4588
4589/* GP0OEN[OEN4] - Direction for port pin */
4590#define GP0OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0090)
4591#define GP0OEN_OEN4_MSK (0x1 << 4 )
4592#define GP0OEN_OEN4 (0x1 << 4 )
4593#define GP0OEN_OEN4_IN (0x0 << 4 ) /* IN */
4594#define GP0OEN_OEN4_OUT (0x1 << 4 ) /* OUT */
4595
4596/* GP0OEN[OEN3] - Direction for port pin */
4597#define GP0OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C008C)
4598#define GP0OEN_OEN3_MSK (0x1 << 3 )
4599#define GP0OEN_OEN3 (0x1 << 3 )
4600#define GP0OEN_OEN3_IN (0x0 << 3 ) /* IN */
4601#define GP0OEN_OEN3_OUT (0x1 << 3 ) /* OUT */
4602
4603/* GP0OEN[OEN2] - Direction for port pin */
4604#define GP0OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0088)
4605#define GP0OEN_OEN2_MSK (0x1 << 2 )
4606#define GP0OEN_OEN2 (0x1 << 2 )
4607#define GP0OEN_OEN2_IN (0x0 << 2 ) /* IN */
4608#define GP0OEN_OEN2_OUT (0x1 << 2 ) /* OUT */
4609
4610/* GP0OEN[OEN1] - Direction for port pin */
4611#define GP0OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0084)
4612#define GP0OEN_OEN1_MSK (0x1 << 1 )
4613#define GP0OEN_OEN1 (0x1 << 1 )
4614#define GP0OEN_OEN1_IN (0x0 << 1 ) /* IN */
4615#define GP0OEN_OEN1_OUT (0x1 << 1 ) /* OUT */
4616
4617/* GP0OEN[OEN0] - Direction for port pin */
4618#define GP0OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0080)
4619#define GP0OEN_OEN0_MSK (0x1 << 0 )
4620#define GP0OEN_OEN0 (0x1 << 0 )
4621#define GP0OEN_OEN0_IN (0x0 << 0 ) /* IN */
4622#define GP0OEN_OEN0_OUT (0x1 << 0 ) /* OUT */
4623
4624/* Reset Value for GP0PUL*/
4625#define GP0PUL_RVAL 0xFF
4626
4627/* GP0PUL[PUL7] - Pull Up Enable for port pin */
4628#define GP0PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C011C)
4629#define GP0PUL_PUL7_MSK (0x1 << 7 )
4630#define GP0PUL_PUL7 (0x1 << 7 )
4631#define GP0PUL_PUL7_DIS (0x0 << 7 ) /* DIS */
4632#define GP0PUL_PUL7_EN (0x1 << 7 ) /* EN */
4633
4634/* GP0PUL[PUL6] - Pull Up Enable for port pin */
4635#define GP0PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0118)
4636#define GP0PUL_PUL6_MSK (0x1 << 6 )
4637#define GP0PUL_PUL6 (0x1 << 6 )
4638#define GP0PUL_PUL6_DIS (0x0 << 6 ) /* DIS */
4639#define GP0PUL_PUL6_EN (0x1 << 6 ) /* EN */
4640
4641/* GP0PUL[PUL5] - Pull Up Enable for port pin */
4642#define GP0PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0114)
4643#define GP0PUL_PUL5_MSK (0x1 << 5 )
4644#define GP0PUL_PUL5 (0x1 << 5 )
4645#define GP0PUL_PUL5_DIS (0x0 << 5 ) /* DIS */
4646#define GP0PUL_PUL5_EN (0x1 << 5 ) /* EN */
4647
4648/* GP0PUL[PUL4] - Pull Up Enable for port pin */
4649#define GP0PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0110)
4650#define GP0PUL_PUL4_MSK (0x1 << 4 )
4651#define GP0PUL_PUL4 (0x1 << 4 )
4652#define GP0PUL_PUL4_DIS (0x0 << 4 ) /* DIS */
4653#define GP0PUL_PUL4_EN (0x1 << 4 ) /* EN */
4654
4655/* GP0PUL[PUL3] - Pull Up Enable for port pin */
4656#define GP0PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C010C)
4657#define GP0PUL_PUL3_MSK (0x1 << 3 )
4658#define GP0PUL_PUL3 (0x1 << 3 )
4659#define GP0PUL_PUL3_DIS (0x0 << 3 ) /* DIS */
4660#define GP0PUL_PUL3_EN (0x1 << 3 ) /* EN */
4661
4662/* GP0PUL[PUL2] - Pull Up Enable for port pin */
4663#define GP0PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0108)
4664#define GP0PUL_PUL2_MSK (0x1 << 2 )
4665#define GP0PUL_PUL2 (0x1 << 2 )
4666#define GP0PUL_PUL2_DIS (0x0 << 2 ) /* DIS */
4667#define GP0PUL_PUL2_EN (0x1 << 2 ) /* EN */
4668
4669/* GP0PUL[PUL1] - Pull Up Enable for port pin */
4670#define GP0PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0104)
4671#define GP0PUL_PUL1_MSK (0x1 << 1 )
4672#define GP0PUL_PUL1 (0x1 << 1 )
4673#define GP0PUL_PUL1_DIS (0x0 << 1 ) /* DIS */
4674#define GP0PUL_PUL1_EN (0x1 << 1 ) /* EN */
4675
4676/* GP0PUL[PUL0] - Pull Up Enable for port pin */
4677#define GP0PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0100)
4678#define GP0PUL_PUL0_MSK (0x1 << 0 )
4679#define GP0PUL_PUL0 (0x1 << 0 )
4680#define GP0PUL_PUL0_DIS (0x0 << 0 ) /* DIS */
4681#define GP0PUL_PUL0_EN (0x1 << 0 ) /* EN */
4682
4683/* Reset Value for GP0OCE*/
4684#define GP0OCE_RVAL 0x0
4685
4686/* GP0OCE[OCE7] - open circuit Enable for port pin */
4687#define GP0OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C019C)
4688#define GP0OCE_OCE7_MSK (0x1 << 7 )
4689#define GP0OCE_OCE7 (0x1 << 7 )
4690#define GP0OCE_OCE7_DIS (0x0 << 7 ) /* DIS */
4691#define GP0OCE_OCE7_EN (0x1 << 7 ) /* EN */
4692
4693/* GP0OCE[OCE6] - open circuit Enable for port pin */
4694#define GP0OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0198)
4695#define GP0OCE_OCE6_MSK (0x1 << 6 )
4696#define GP0OCE_OCE6 (0x1 << 6 )
4697#define GP0OCE_OCE6_DIS (0x0 << 6 ) /* DIS */
4698#define GP0OCE_OCE6_EN (0x1 << 6 ) /* EN */
4699
4700/* GP0OCE[OCE5] - open circuit Enable for port pin */
4701#define GP0OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0194)
4702#define GP0OCE_OCE5_MSK (0x1 << 5 )
4703#define GP0OCE_OCE5 (0x1 << 5 )
4704#define GP0OCE_OCE5_DIS (0x0 << 5 ) /* DIS */
4705#define GP0OCE_OCE5_EN (0x1 << 5 ) /* EN */
4706
4707/* GP0OCE[OCE4] - open circuit Enable for port pin */
4708#define GP0OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0190)
4709#define GP0OCE_OCE4_MSK (0x1 << 4 )
4710#define GP0OCE_OCE4 (0x1 << 4 )
4711#define GP0OCE_OCE4_DIS (0x0 << 4 ) /* DIS */
4712#define GP0OCE_OCE4_EN (0x1 << 4 ) /* EN */
4713
4714/* GP0OCE[OCE3] - open circuit Enable for port pin */
4715#define GP0OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C018C)
4716#define GP0OCE_OCE3_MSK (0x1 << 3 )
4717#define GP0OCE_OCE3 (0x1 << 3 )
4718#define GP0OCE_OCE3_DIS (0x0 << 3 ) /* DIS */
4719#define GP0OCE_OCE3_EN (0x1 << 3 ) /* EN */
4720
4721/* GP0OCE[OCE2] - open circuit Enable for port pin */
4722#define GP0OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0188)
4723#define GP0OCE_OCE2_MSK (0x1 << 2 )
4724#define GP0OCE_OCE2 (0x1 << 2 )
4725#define GP0OCE_OCE2_DIS (0x0 << 2 ) /* DIS */
4726#define GP0OCE_OCE2_EN (0x1 << 2 ) /* EN */
4727
4728/* GP0OCE[OCE1] - open circuit Enable for port pin */
4729#define GP0OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0184)
4730#define GP0OCE_OCE1_MSK (0x1 << 1 )
4731#define GP0OCE_OCE1 (0x1 << 1 )
4732#define GP0OCE_OCE1_DIS (0x0 << 1 ) /* DIS */
4733#define GP0OCE_OCE1_EN (0x1 << 1 ) /* EN */
4734
4735/* GP0OCE[OCE0] - open circuit Enable for port pin */
4736#define GP0OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0180)
4737#define GP0OCE_OCE0_MSK (0x1 << 0 )
4738#define GP0OCE_OCE0 (0x1 << 0 )
4739#define GP0OCE_OCE0_DIS (0x0 << 0 ) /* DIS */
4740#define GP0OCE_OCE0_EN (0x1 << 0 ) /* EN */
4741
4742/* Reset Value for GP0IN*/
4743#define GP0IN_RVAL 0xFF
4744
4745/* GP0IN[IN7] - Input for port pin */
4746#define GP0IN_IN7_BBA (*(volatile unsigned long *) 0x420C029C)
4747#define GP0IN_IN7_MSK (0x1 << 7 )
4748#define GP0IN_IN7 (0x1 << 7 )
4749#define GP0IN_IN7_LOW (0x0 << 7 ) /* LOW */
4750#define GP0IN_IN7_HIGH (0x1 << 7 ) /* HIGH */
4751
4752/* GP0IN[IN6] - Input for port pin */
4753#define GP0IN_IN6_BBA (*(volatile unsigned long *) 0x420C0298)
4754#define GP0IN_IN6_MSK (0x1 << 6 )
4755#define GP0IN_IN6 (0x1 << 6 )
4756#define GP0IN_IN6_LOW (0x0 << 6 ) /* LOW */
4757#define GP0IN_IN6_HIGH (0x1 << 6 ) /* HIGH */
4758
4759/* GP0IN[IN5] - Input for port pin */
4760#define GP0IN_IN5_BBA (*(volatile unsigned long *) 0x420C0294)
4761#define GP0IN_IN5_MSK (0x1 << 5 )
4762#define GP0IN_IN5 (0x1 << 5 )
4763#define GP0IN_IN5_LOW (0x0 << 5 ) /* LOW */
4764#define GP0IN_IN5_HIGH (0x1 << 5 ) /* HIGH */
4765
4766/* GP0IN[IN4] - Input for port pin */
4767#define GP0IN_IN4_BBA (*(volatile unsigned long *) 0x420C0290)
4768#define GP0IN_IN4_MSK (0x1 << 4 )
4769#define GP0IN_IN4 (0x1 << 4 )
4770#define GP0IN_IN4_LOW (0x0 << 4 ) /* LOW */
4771#define GP0IN_IN4_HIGH (0x1 << 4 ) /* HIGH */
4772
4773/* GP0IN[IN3] - Input for port pin */
4774#define GP0IN_IN3_BBA (*(volatile unsigned long *) 0x420C028C)
4775#define GP0IN_IN3_MSK (0x1 << 3 )
4776#define GP0IN_IN3 (0x1 << 3 )
4777#define GP0IN_IN3_LOW (0x0 << 3 ) /* LOW */
4778#define GP0IN_IN3_HIGH (0x1 << 3 ) /* HIGH */
4779
4780/* GP0IN[IN2] - Input for port pin */
4781#define GP0IN_IN2_BBA (*(volatile unsigned long *) 0x420C0288)
4782#define GP0IN_IN2_MSK (0x1 << 2 )
4783#define GP0IN_IN2 (0x1 << 2 )
4784#define GP0IN_IN2_LOW (0x0 << 2 ) /* LOW */
4785#define GP0IN_IN2_HIGH (0x1 << 2 ) /* HIGH */
4786
4787/* GP0IN[IN1] - Input for port pin */
4788#define GP0IN_IN1_BBA (*(volatile unsigned long *) 0x420C0284)
4789#define GP0IN_IN1_MSK (0x1 << 1 )
4790#define GP0IN_IN1 (0x1 << 1 )
4791#define GP0IN_IN1_LOW (0x0 << 1 ) /* LOW */
4792#define GP0IN_IN1_HIGH (0x1 << 1 ) /* HIGH */
4793
4794/* GP0IN[IN0] - Input for port pin */
4795#define GP0IN_IN0_BBA (*(volatile unsigned long *) 0x420C0280)
4796#define GP0IN_IN0_MSK (0x1 << 0 )
4797#define GP0IN_IN0 (0x1 << 0 )
4798#define GP0IN_IN0_LOW (0x0 << 0 ) /* LOW */
4799#define GP0IN_IN0_HIGH (0x1 << 0 ) /* HIGH */
4800
4801/* Reset Value for GP0OUT*/
4802#define GP0OUT_RVAL 0x0
4803
4804/* GP0OUT[OUT7] - Output for port pin */
4805#define GP0OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C031C)
4806#define GP0OUT_OUT7_MSK (0x1 << 7 )
4807#define GP0OUT_OUT7 (0x1 << 7 )
4808#define GP0OUT_OUT7_LOW (0x0 << 7 ) /* LOW */
4809#define GP0OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH */
4810
4811/* GP0OUT[OUT6] - Output for port pin */
4812#define GP0OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0318)
4813#define GP0OUT_OUT6_MSK (0x1 << 6 )
4814#define GP0OUT_OUT6 (0x1 << 6 )
4815#define GP0OUT_OUT6_LOW (0x0 << 6 ) /* LOW */
4816#define GP0OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH */
4817
4818/* GP0OUT[OUT5] - Output for port pin */
4819#define GP0OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0314)
4820#define GP0OUT_OUT5_MSK (0x1 << 5 )
4821#define GP0OUT_OUT5 (0x1 << 5 )
4822#define GP0OUT_OUT5_LOW (0x0 << 5 ) /* LOW */
4823#define GP0OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH */
4824
4825/* GP0OUT[OUT4] - Output for port pin */
4826#define GP0OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0310)
4827#define GP0OUT_OUT4_MSK (0x1 << 4 )
4828#define GP0OUT_OUT4 (0x1 << 4 )
4829#define GP0OUT_OUT4_LOW (0x0 << 4 ) /* LOW */
4830#define GP0OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH */
4831
4832/* GP0OUT[OUT3] - Output for port pin */
4833#define GP0OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C030C)
4834#define GP0OUT_OUT3_MSK (0x1 << 3 )
4835#define GP0OUT_OUT3 (0x1 << 3 )
4836#define GP0OUT_OUT3_LOW (0x0 << 3 ) /* LOW */
4837#define GP0OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH */
4838
4839/* GP0OUT[OUT2] - Output for port pin */
4840#define GP0OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0308)
4841#define GP0OUT_OUT2_MSK (0x1 << 2 )
4842#define GP0OUT_OUT2 (0x1 << 2 )
4843#define GP0OUT_OUT2_LOW (0x0 << 2 ) /* LOW */
4844#define GP0OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH */
4845
4846/* GP0OUT[OUT1] - Output for port pin */
4847#define GP0OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0304)
4848#define GP0OUT_OUT1_MSK (0x1 << 1 )
4849#define GP0OUT_OUT1 (0x1 << 1 )
4850#define GP0OUT_OUT1_LOW (0x0 << 1 ) /* LOW */
4851#define GP0OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH */
4852
4853/* GP0OUT[OUT0] - Output for port pin */
4854#define GP0OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0300)
4855#define GP0OUT_OUT0_MSK (0x1 << 0 )
4856#define GP0OUT_OUT0 (0x1 << 0 )
4857#define GP0OUT_OUT0_LOW (0x0 << 0 ) /* LOW */
4858#define GP0OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH */
4859
4860/* Reset Value for GP0SET*/
4861#define GP0SET_RVAL 0x0
4862
4863/* GP0SET[SET7] - Set Output High for port pin */
4864#define GP0SET_SET7_BBA (*(volatile unsigned long *) 0x420C039C)
4865#define GP0SET_SET7_MSK (0x1 << 7 )
4866#define GP0SET_SET7 (0x1 << 7 )
4867#define GP0SET_SET7_SET (0x1 << 7 ) /* SET */
4868
4869/* GP0SET[SET6] - Set Output High for port pin */
4870#define GP0SET_SET6_BBA (*(volatile unsigned long *) 0x420C0398)
4871#define GP0SET_SET6_MSK (0x1 << 6 )
4872#define GP0SET_SET6 (0x1 << 6 )
4873#define GP0SET_SET6_SET (0x1 << 6 ) /* SET */
4874
4875/* GP0SET[SET5] - Set Output High for port pin */
4876#define GP0SET_SET5_BBA (*(volatile unsigned long *) 0x420C0394)
4877#define GP0SET_SET5_MSK (0x1 << 5 )
4878#define GP0SET_SET5 (0x1 << 5 )
4879#define GP0SET_SET5_SET (0x1 << 5 ) /* SET */
4880
4881/* GP0SET[SET4] - Set Output High for port pin */
4882#define GP0SET_SET4_BBA (*(volatile unsigned long *) 0x420C0390)
4883#define GP0SET_SET4_MSK (0x1 << 4 )
4884#define GP0SET_SET4 (0x1 << 4 )
4885#define GP0SET_SET4_SET (0x1 << 4 ) /* SET */
4886
4887/* GP0SET[SET3] - Set Output High for port pin */
4888#define GP0SET_SET3_BBA (*(volatile unsigned long *) 0x420C038C)
4889#define GP0SET_SET3_MSK (0x1 << 3 )
4890#define GP0SET_SET3 (0x1 << 3 )
4891#define GP0SET_SET3_SET (0x1 << 3 ) /* SET */
4892
4893/* GP0SET[SET2] - Set Output High for port pin */
4894#define GP0SET_SET2_BBA (*(volatile unsigned long *) 0x420C0388)
4895#define GP0SET_SET2_MSK (0x1 << 2 )
4896#define GP0SET_SET2 (0x1 << 2 )
4897#define GP0SET_SET2_SET (0x1 << 2 ) /* SET */
4898
4899/* GP0SET[SET1] - Set Output High for port pin */
4900#define GP0SET_SET1_BBA (*(volatile unsigned long *) 0x420C0384)
4901#define GP0SET_SET1_MSK (0x1 << 1 )
4902#define GP0SET_SET1 (0x1 << 1 )
4903#define GP0SET_SET1_SET (0x1 << 1 ) /* SET */
4904
4905/* GP0SET[SET0] - Set Output High for port pin */
4906#define GP0SET_SET0_BBA (*(volatile unsigned long *) 0x420C0380)
4907#define GP0SET_SET0_MSK (0x1 << 0 )
4908#define GP0SET_SET0 (0x1 << 0 )
4909#define GP0SET_SET0_SET (0x1 << 0 ) /* SET */
4910
4911/* Reset Value for GP0CLR*/
4912#define GP0CLR_RVAL 0x0
4913
4914/* GP0CLR[CLR7] - Set Output Low for port pin */
4915#define GP0CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C041C)
4916#define GP0CLR_CLR7_MSK (0x1 << 7 )
4917#define GP0CLR_CLR7 (0x1 << 7 )
4918#define GP0CLR_CLR7_CLR (0x1 << 7 ) /* CLR */
4919
4920/* GP0CLR[CLR6] - Set Output Low for port pin */
4921#define GP0CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C0418)
4922#define GP0CLR_CLR6_MSK (0x1 << 6 )
4923#define GP0CLR_CLR6 (0x1 << 6 )
4924#define GP0CLR_CLR6_CLR (0x1 << 6 ) /* CLR */
4925
4926/* GP0CLR[CLR5] - Set Output Low for port pin */
4927#define GP0CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C0414)
4928#define GP0CLR_CLR5_MSK (0x1 << 5 )
4929#define GP0CLR_CLR5 (0x1 << 5 )
4930#define GP0CLR_CLR5_CLR (0x1 << 5 ) /* CLR */
4931
4932/* GP0CLR[CLR4] - Set Output Low for port pin */
4933#define GP0CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C0410)
4934#define GP0CLR_CLR4_MSK (0x1 << 4 )
4935#define GP0CLR_CLR4 (0x1 << 4 )
4936#define GP0CLR_CLR4_CLR (0x1 << 4 ) /* CLR */
4937
4938/* GP0CLR[CLR3] - Set Output Low for port pin */
4939#define GP0CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C040C)
4940#define GP0CLR_CLR3_MSK (0x1 << 3 )
4941#define GP0CLR_CLR3 (0x1 << 3 )
4942#define GP0CLR_CLR3_CLR (0x1 << 3 ) /* CLR */
4943
4944/* GP0CLR[CLR2] - Set Output Low for port pin */
4945#define GP0CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C0408)
4946#define GP0CLR_CLR2_MSK (0x1 << 2 )
4947#define GP0CLR_CLR2 (0x1 << 2 )
4948#define GP0CLR_CLR2_CLR (0x1 << 2 ) /* CLR */
4949
4950/* GP0CLR[CLR1] - Set Output Low for port pin */
4951#define GP0CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C0404)
4952#define GP0CLR_CLR1_MSK (0x1 << 1 )
4953#define GP0CLR_CLR1 (0x1 << 1 )
4954#define GP0CLR_CLR1_CLR (0x1 << 1 ) /* CLR */
4955
4956/* GP0CLR[CLR0] - Set Output Low for port pin */
4957#define GP0CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C0400)
4958#define GP0CLR_CLR0_MSK (0x1 << 0 )
4959#define GP0CLR_CLR0 (0x1 << 0 )
4960#define GP0CLR_CLR0_CLR (0x1 << 0 ) /* CLR */
4961
4962/* Reset Value for GP0TGL*/
4963#define GP0TGL_RVAL 0x0
4964
4965/* GP0TGL[TGL7] - Toggle Output for port pin */
4966#define GP0TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C049C)
4967#define GP0TGL_TGL7_MSK (0x1 << 7 )
4968#define GP0TGL_TGL7 (0x1 << 7 )
4969#define GP0TGL_TGL7_TGL (0x1 << 7 ) /* TGL */
4970
4971/* GP0TGL[TGL6] - Toggle Output for port pin */
4972#define GP0TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C0498)
4973#define GP0TGL_TGL6_MSK (0x1 << 6 )
4974#define GP0TGL_TGL6 (0x1 << 6 )
4975#define GP0TGL_TGL6_TGL (0x1 << 6 ) /* TGL */
4976
4977/* GP0TGL[TGL5] - Toggle Output for port pin */
4978#define GP0TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C0494)
4979#define GP0TGL_TGL5_MSK (0x1 << 5 )
4980#define GP0TGL_TGL5 (0x1 << 5 )
4981#define GP0TGL_TGL5_TGL (0x1 << 5 ) /* TGL */
4982
4983/* GP0TGL[TGL4] - Toggle Output for port pin */
4984#define GP0TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C0490)
4985#define GP0TGL_TGL4_MSK (0x1 << 4 )
4986#define GP0TGL_TGL4 (0x1 << 4 )
4987#define GP0TGL_TGL4_TGL (0x1 << 4 ) /* TGL */
4988
4989/* GP0TGL[TGL3] - Toggle Output for port pin */
4990#define GP0TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C048C)
4991#define GP0TGL_TGL3_MSK (0x1 << 3 )
4992#define GP0TGL_TGL3 (0x1 << 3 )
4993#define GP0TGL_TGL3_TGL (0x1 << 3 ) /* TGL */
4994
4995/* GP0TGL[TGL2] - Toggle Output for port pin */
4996#define GP0TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C0488)
4997#define GP0TGL_TGL2_MSK (0x1 << 2 )
4998#define GP0TGL_TGL2 (0x1 << 2 )
4999#define GP0TGL_TGL2_TGL (0x1 << 2 ) /* TGL */
5000
5001/* GP0TGL[TGL1] - Toggle Output for port pin */
5002#define GP0TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C0484)
5003#define GP0TGL_TGL1_MSK (0x1 << 1 )
5004#define GP0TGL_TGL1 (0x1 << 1 )
5005#define GP0TGL_TGL1_TGL (0x1 << 1 ) /* TGL */
5006
5007/* GP0TGL[TGL0] - Toggle Output for port pin */
5008#define GP0TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C0480)
5009#define GP0TGL_TGL0_MSK (0x1 << 0 )
5010#define GP0TGL_TGL0 (0x1 << 0 )
5011#define GP0TGL_TGL0_TGL (0x1 << 0 ) /* TGL */
5012#if (__NO_MMR_STRUCTS__==1)
5013
5014#define GP1CON (*(volatile unsigned short int *) 0x40006030)
5015#define GP1OEN (*(volatile unsigned char *) 0x40006034)
5016#define GP1PUL (*(volatile unsigned char *) 0x40006038)
5017#define GP1OCE (*(volatile unsigned char *) 0x4000603C)
5018#define GP1IN (*(volatile unsigned char *) 0x40006044)
5019#define GP1OUT (*(volatile unsigned char *) 0x40006048)
5020#define GP1SET (*(volatile unsigned char *) 0x4000604C)
5021#define GP1CLR (*(volatile unsigned char *) 0x40006050)
5022#define GP1TGL (*(volatile unsigned char *) 0x40006054)
5023#endif // (__NO_MMR_STRUCTS__==1)
5024
5025/* Reset Value for GP1CON*/
5026#define GP1CON_RVAL 0x0
5027
5028/* GP1CON[CON7] - Configuration bits for P1.7 */
5029#define GP1CON_CON7_MSK (0x3 << 14 )
5030#define GP1CON_CON7_GPIOIRQ7 (0x0 << 14 ) /* GPIOIRQ7 */
5031#define GP1CON_CON7_PWM5 (0x1 << 14 ) /* PWM5 */
5032#define GP1CON_CON7_SPI0CS (0x2 << 14 ) /* SPI0CS */
5033
5034/* GP1CON[CON6] - Configuration bits for P1.6 */
5035#define GP1CON_CON6_MSK (0x3 << 12 )
5036#define GP1CON_CON6_GPIOIRQ6 (0x0 << 12 ) /* GPIOIRQ6 */
5037#define GP1CON_CON6_PWM4 (0x1 << 12 ) /* PWM4 */
5038#define GP1CON_CON6_SPI0MOSI (0x2 << 12 ) /* SPI0MOSI */
5039
5040/* GP1CON[CON5] - Configuration bits for P1.5 */
5041#define GP1CON_CON5_MSK (0x3 << 10 )
5042#define GP1CON_CON5_GPIOIRQ5 (0x0 << 10 ) /* GPIOIRQ5 */
5043#define GP1CON_CON5_PWM3 (0x1 << 10 ) /* PWM3 */
5044#define GP1CON_CON5_SPI0SCLK (0x2 << 10 ) /* SPI0SCLK */
5045
5046/* GP1CON[CON4] - Configuration bits for P1.4 */
5047#define GP1CON_CON4_MSK (0x3 << 8 )
5048#define GP1CON_CON4_GPIO (0x0 << 8 ) /* GPIO */
5049#define GP1CON_CON4_PWM2 (0x1 << 8 ) /* PWM2 */
5050#define GP1CON_CON4_SPI0MISO (0x2 << 8 ) /* SPI0MISO */
5051
5052/* GP1CON[CON3] - Configuration bits for P1.3 */
5053#define GP1CON_CON3_MSK (0x3 << 6 )
5054#define GP1CON_CON3_GPIO (0x0 << 6 ) /* GPIO */
5055#define GP1CON_CON3_PWM1 (0x1 << 6 ) /* PWM1 */
5056
5057/* GP1CON[CON2] - Configuration bits for P1.2 */
5058#define GP1CON_CON2_MSK (0x3 << 4 )
5059#define GP1CON_CON2_GPIO (0x0 << 4 ) /* GPIO */
5060#define GP1CON_CON2_PWM0 (0x1 << 4 ) /* PWM0 */
5061
5062/* GP1CON[CON1] - Configuration bits for P1.1 */
5063#define GP1CON_CON1_MSK (0x3 << 2 )
5064#define GP1CON_CON1_GPIOIRQ4 (0x0 << 2 ) /* GPIOIRQ4 */
5065#define GP1CON_CON1_PWMTRIP (0x1 << 2 ) /* PWMTRIP */
5066
5067/* GP1CON[CON0] - Configuration bits for P1.0 */
5068#define GP1CON_CON0_MSK (0x3 << 0 )
5069#define GP1CON_CON0_GPIOIRQ3 (0x0 << 0 ) /* GPIOIRQ3 */
5070#define GP1CON_CON0_PWMSYNC (0x1 << 0 ) /* PWMSYNC */
5071#define GP1CON_CON0_EXTCLKIN (0x2 << 0 ) /* EXTCLKIN */
5072
5073/* Reset Value for GP1OEN*/
5074#define GP1OEN_RVAL 0x0
5075
5076/* GP1OEN[OEN7] - Direction for port pin */
5077#define GP1OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C069C)
5078#define GP1OEN_OEN7_MSK (0x1 << 7 )
5079#define GP1OEN_OEN7 (0x1 << 7 )
5080#define GP1OEN_OEN7_IN (0x0 << 7 ) /* IN */
5081#define GP1OEN_OEN7_OUT (0x1 << 7 ) /* OUT */
5082
5083/* GP1OEN[OEN6] - Direction for port pin */
5084#define GP1OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0698)
5085#define GP1OEN_OEN6_MSK (0x1 << 6 )
5086#define GP1OEN_OEN6 (0x1 << 6 )
5087#define GP1OEN_OEN6_IN (0x0 << 6 ) /* IN */
5088#define GP1OEN_OEN6_OUT (0x1 << 6 ) /* OUT */
5089
5090/* GP1OEN[OEN5] - Direction for port pin */
5091#define GP1OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0694)
5092#define GP1OEN_OEN5_MSK (0x1 << 5 )
5093#define GP1OEN_OEN5 (0x1 << 5 )
5094#define GP1OEN_OEN5_IN (0x0 << 5 ) /* IN */
5095#define GP1OEN_OEN5_OUT (0x1 << 5 ) /* OUT */
5096
5097/* GP1OEN[OEN4] - Direction for port pin */
5098#define GP1OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0690)
5099#define GP1OEN_OEN4_MSK (0x1 << 4 )
5100#define GP1OEN_OEN4 (0x1 << 4 )
5101#define GP1OEN_OEN4_IN (0x0 << 4 ) /* IN */
5102#define GP1OEN_OEN4_OUT (0x1 << 4 ) /* OUT */
5103
5104/* GP1OEN[OEN3] - Direction for port pin */
5105#define GP1OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C068C)
5106#define GP1OEN_OEN3_MSK (0x1 << 3 )
5107#define GP1OEN_OEN3 (0x1 << 3 )
5108#define GP1OEN_OEN3_IN (0x0 << 3 ) /* IN */
5109#define GP1OEN_OEN3_OUT (0x1 << 3 ) /* OUT */
5110
5111/* GP1OEN[OEN2] - Direction for port pin */
5112#define GP1OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0688)
5113#define GP1OEN_OEN2_MSK (0x1 << 2 )
5114#define GP1OEN_OEN2 (0x1 << 2 )
5115#define GP1OEN_OEN2_IN (0x0 << 2 ) /* IN */
5116#define GP1OEN_OEN2_OUT (0x1 << 2 ) /* OUT */
5117
5118/* GP1OEN[OEN1] - Direction for port pin */
5119#define GP1OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0684)
5120#define GP1OEN_OEN1_MSK (0x1 << 1 )
5121#define GP1OEN_OEN1 (0x1 << 1 )
5122#define GP1OEN_OEN1_IN (0x0 << 1 ) /* IN */
5123#define GP1OEN_OEN1_OUT (0x1 << 1 ) /* OUT */
5124
5125/* GP1OEN[OEN0] - Direction for port pin */
5126#define GP1OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0680)
5127#define GP1OEN_OEN0_MSK (0x1 << 0 )
5128#define GP1OEN_OEN0 (0x1 << 0 )
5129#define GP1OEN_OEN0_IN (0x0 << 0 ) /* IN */
5130#define GP1OEN_OEN0_OUT (0x1 << 0 ) /* OUT */
5131
5132/* Reset Value for GP1PUL*/
5133#define GP1PUL_RVAL 0xFF
5134
5135/* GP1PUL[PUL7] - Pull Up Enable for port pin */
5136#define GP1PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C071C)
5137#define GP1PUL_PUL7_MSK (0x1 << 7 )
5138#define GP1PUL_PUL7 (0x1 << 7 )
5139#define GP1PUL_PUL7_DIS (0x0 << 7 ) /* DIS */
5140#define GP1PUL_PUL7_EN (0x1 << 7 ) /* EN */
5141
5142/* GP1PUL[PUL6] - Pull Up Enable for port pin */
5143#define GP1PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0718)
5144#define GP1PUL_PUL6_MSK (0x1 << 6 )
5145#define GP1PUL_PUL6 (0x1 << 6 )
5146#define GP1PUL_PUL6_DIS (0x0 << 6 ) /* DIS */
5147#define GP1PUL_PUL6_EN (0x1 << 6 ) /* EN */
5148
5149/* GP1PUL[PUL5] - Pull Up Enable for port pin */
5150#define GP1PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0714)
5151#define GP1PUL_PUL5_MSK (0x1 << 5 )
5152#define GP1PUL_PUL5 (0x1 << 5 )
5153#define GP1PUL_PUL5_DIS (0x0 << 5 ) /* DIS */
5154#define GP1PUL_PUL5_EN (0x1 << 5 ) /* EN */
5155
5156/* GP1PUL[PUL4] - Pull Up Enable for port pin */
5157#define GP1PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0710)
5158#define GP1PUL_PUL4_MSK (0x1 << 4 )
5159#define GP1PUL_PUL4 (0x1 << 4 )
5160#define GP1PUL_PUL4_DIS (0x0 << 4 ) /* DIS */
5161#define GP1PUL_PUL4_EN (0x1 << 4 ) /* EN */
5162
5163/* GP1PUL[PUL3] - Pull Up Enable for port pin */
5164#define GP1PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C070C)
5165#define GP1PUL_PUL3_MSK (0x1 << 3 )
5166#define GP1PUL_PUL3 (0x1 << 3 )
5167#define GP1PUL_PUL3_DIS (0x0 << 3 ) /* DIS */
5168#define GP1PUL_PUL3_EN (0x1 << 3 ) /* EN */
5169
5170/* GP1PUL[PUL2] - Pull Up Enable for port pin */
5171#define GP1PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0708)
5172#define GP1PUL_PUL2_MSK (0x1 << 2 )
5173#define GP1PUL_PUL2 (0x1 << 2 )
5174#define GP1PUL_PUL2_DIS (0x0 << 2 ) /* DIS */
5175#define GP1PUL_PUL2_EN (0x1 << 2 ) /* EN */
5176
5177/* GP1PUL[PUL1] - Pull Up Enable for port pin */
5178#define GP1PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0704)
5179#define GP1PUL_PUL1_MSK (0x1 << 1 )
5180#define GP1PUL_PUL1 (0x1 << 1 )
5181#define GP1PUL_PUL1_DIS (0x0 << 1 ) /* DIS */
5182#define GP1PUL_PUL1_EN (0x1 << 1 ) /* EN */
5183
5184/* GP1PUL[PUL0] - Pull Up Enable for port pin */
5185#define GP1PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0700)
5186#define GP1PUL_PUL0_MSK (0x1 << 0 )
5187#define GP1PUL_PUL0 (0x1 << 0 )
5188#define GP1PUL_PUL0_DIS (0x0 << 0 ) /* DIS */
5189#define GP1PUL_PUL0_EN (0x1 << 0 ) /* EN */
5190
5191/* Reset Value for GP1OCE*/
5192#define GP1OCE_RVAL 0x0
5193
5194/* GP1OCE[OCE7] - open circuit Enable for port pin */
5195#define GP1OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C079C)
5196#define GP1OCE_OCE7_MSK (0x1 << 7 )
5197#define GP1OCE_OCE7 (0x1 << 7 )
5198#define GP1OCE_OCE7_DIS (0x0 << 7 ) /* DIS */
5199#define GP1OCE_OCE7_EN (0x1 << 7 ) /* EN */
5200
5201/* GP1OCE[OCE6] - open circuit Enable for port pin */
5202#define GP1OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0798)
5203#define GP1OCE_OCE6_MSK (0x1 << 6 )
5204#define GP1OCE_OCE6 (0x1 << 6 )
5205#define GP1OCE_OCE6_DIS (0x0 << 6 ) /* DIS */
5206#define GP1OCE_OCE6_EN (0x1 << 6 ) /* EN */
5207
5208/* GP1OCE[OCE5] - open circuit Enable for port pin */
5209#define GP1OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0794)
5210#define GP1OCE_OCE5_MSK (0x1 << 5 )
5211#define GP1OCE_OCE5 (0x1 << 5 )
5212#define GP1OCE_OCE5_DIS (0x0 << 5 ) /* DIS */
5213#define GP1OCE_OCE5_EN (0x1 << 5 ) /* EN */
5214
5215/* GP1OCE[OCE4] - open circuit Enable for port pin */
5216#define GP1OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0790)
5217#define GP1OCE_OCE4_MSK (0x1 << 4 )
5218#define GP1OCE_OCE4 (0x1 << 4 )
5219#define GP1OCE_OCE4_DIS (0x0 << 4 ) /* DIS */
5220#define GP1OCE_OCE4_EN (0x1 << 4 ) /* EN */
5221
5222/* GP1OCE[OCE3] - open circuit Enable for port pin */
5223#define GP1OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C078C)
5224#define GP1OCE_OCE3_MSK (0x1 << 3 )
5225#define GP1OCE_OCE3 (0x1 << 3 )
5226#define GP1OCE_OCE3_DIS (0x0 << 3 ) /* DIS */
5227#define GP1OCE_OCE3_EN (0x1 << 3 ) /* EN */
5228
5229/* GP1OCE[OCE2] - open circuit Enable for port pin */
5230#define GP1OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0788)
5231#define GP1OCE_OCE2_MSK (0x1 << 2 )
5232#define GP1OCE_OCE2 (0x1 << 2 )
5233#define GP1OCE_OCE2_DIS (0x0 << 2 ) /* DIS */
5234#define GP1OCE_OCE2_EN (0x1 << 2 ) /* EN */
5235
5236/* GP1OCE[OCE1] - open circuit Enable for port pin */
5237#define GP1OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0784)
5238#define GP1OCE_OCE1_MSK (0x1 << 1 )
5239#define GP1OCE_OCE1 (0x1 << 1 )
5240#define GP1OCE_OCE1_DIS (0x0 << 1 ) /* DIS */
5241#define GP1OCE_OCE1_EN (0x1 << 1 ) /* EN */
5242
5243/* GP1OCE[OCE0] - open circuit Enable for port pin */
5244#define GP1OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0780)
5245#define GP1OCE_OCE0_MSK (0x1 << 0 )
5246#define GP1OCE_OCE0 (0x1 << 0 )
5247#define GP1OCE_OCE0_DIS (0x0 << 0 ) /* DIS */
5248#define GP1OCE_OCE0_EN (0x1 << 0 ) /* EN */
5249
5250/* Reset Value for GP1IN*/
5251#define GP1IN_RVAL 0xFF
5252
5253/* GP1IN[IN7] - Input for port pin */
5254#define GP1IN_IN7_BBA (*(volatile unsigned long *) 0x420C089C)
5255#define GP1IN_IN7_MSK (0x1 << 7 )
5256#define GP1IN_IN7 (0x1 << 7 )
5257#define GP1IN_IN7_LOW (0x0 << 7 ) /* LOW */
5258#define GP1IN_IN7_HIGH (0x1 << 7 ) /* HIGH */
5259
5260/* GP1IN[IN6] - Input for port pin */
5261#define GP1IN_IN6_BBA (*(volatile unsigned long *) 0x420C0898)
5262#define GP1IN_IN6_MSK (0x1 << 6 )
5263#define GP1IN_IN6 (0x1 << 6 )
5264#define GP1IN_IN6_LOW (0x0 << 6 ) /* LOW */
5265#define GP1IN_IN6_HIGH (0x1 << 6 ) /* HIGH */
5266
5267/* GP1IN[IN5] - Input for port pin */
5268#define GP1IN_IN5_BBA (*(volatile unsigned long *) 0x420C0894)
5269#define GP1IN_IN5_MSK (0x1 << 5 )
5270#define GP1IN_IN5 (0x1 << 5 )
5271#define GP1IN_IN5_LOW (0x0 << 5 ) /* LOW */
5272#define GP1IN_IN5_HIGH (0x1 << 5 ) /* HIGH */
5273
5274/* GP1IN[IN4] - Input for port pin */
5275#define GP1IN_IN4_BBA (*(volatile unsigned long *) 0x420C0890)
5276#define GP1IN_IN4_MSK (0x1 << 4 )
5277#define GP1IN_IN4 (0x1 << 4 )
5278#define GP1IN_IN4_LOW (0x0 << 4 ) /* LOW */
5279#define GP1IN_IN4_HIGH (0x1 << 4 ) /* HIGH */
5280
5281/* GP1IN[IN3] - Input for port pin */
5282#define GP1IN_IN3_BBA (*(volatile unsigned long *) 0x420C088C)
5283#define GP1IN_IN3_MSK (0x1 << 3 )
5284#define GP1IN_IN3 (0x1 << 3 )
5285#define GP1IN_IN3_LOW (0x0 << 3 ) /* LOW */
5286#define GP1IN_IN3_HIGH (0x1 << 3 ) /* HIGH */
5287
5288/* GP1IN[IN2] - Input for port pin */
5289#define GP1IN_IN2_BBA (*(volatile unsigned long *) 0x420C0888)
5290#define GP1IN_IN2_MSK (0x1 << 2 )
5291#define GP1IN_IN2 (0x1 << 2 )
5292#define GP1IN_IN2_LOW (0x0 << 2 ) /* LOW */
5293#define GP1IN_IN2_HIGH (0x1 << 2 ) /* HIGH */
5294
5295/* GP1IN[IN1] - Input for port pin */
5296#define GP1IN_IN1_BBA (*(volatile unsigned long *) 0x420C0884)
5297#define GP1IN_IN1_MSK (0x1 << 1 )
5298#define GP1IN_IN1 (0x1 << 1 )
5299#define GP1IN_IN1_LOW (0x0 << 1 ) /* LOW */
5300#define GP1IN_IN1_HIGH (0x1 << 1 ) /* HIGH */
5301
5302/* GP1IN[IN0] - Input for port pin */
5303#define GP1IN_IN0_BBA (*(volatile unsigned long *) 0x420C0880)
5304#define GP1IN_IN0_MSK (0x1 << 0 )
5305#define GP1IN_IN0 (0x1 << 0 )
5306#define GP1IN_IN0_LOW (0x0 << 0 ) /* LOW */
5307#define GP1IN_IN0_HIGH (0x1 << 0 ) /* HIGH */
5308
5309/* Reset Value for GP1OUT*/
5310#define GP1OUT_RVAL 0x0
5311
5312/* GP1OUT[OUT7] - Output for port pin */
5313#define GP1OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C091C)
5314#define GP1OUT_OUT7_MSK (0x1 << 7 )
5315#define GP1OUT_OUT7 (0x1 << 7 )
5316#define GP1OUT_OUT7_LOW (0x0 << 7 ) /* LOW */
5317#define GP1OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH */
5318
5319/* GP1OUT[OUT6] - Output for port pin */
5320#define GP1OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0918)
5321#define GP1OUT_OUT6_MSK (0x1 << 6 )
5322#define GP1OUT_OUT6 (0x1 << 6 )
5323#define GP1OUT_OUT6_LOW (0x0 << 6 ) /* LOW */
5324#define GP1OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH */
5325
5326/* GP1OUT[OUT5] - Output for port pin */
5327#define GP1OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0914)
5328#define GP1OUT_OUT5_MSK (0x1 << 5 )
5329#define GP1OUT_OUT5 (0x1 << 5 )
5330#define GP1OUT_OUT5_LOW (0x0 << 5 ) /* LOW */
5331#define GP1OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH */
5332
5333/* GP1OUT[OUT4] - Output for port pin */
5334#define GP1OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0910)
5335#define GP1OUT_OUT4_MSK (0x1 << 4 )
5336#define GP1OUT_OUT4 (0x1 << 4 )
5337#define GP1OUT_OUT4_LOW (0x0 << 4 ) /* LOW */
5338#define GP1OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH */
5339
5340/* GP1OUT[OUT3] - Output for port pin */
5341#define GP1OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C090C)
5342#define GP1OUT_OUT3_MSK (0x1 << 3 )
5343#define GP1OUT_OUT3 (0x1 << 3 )
5344#define GP1OUT_OUT3_LOW (0x0 << 3 ) /* LOW */
5345#define GP1OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH */
5346
5347/* GP1OUT[OUT2] - Output for port pin */
5348#define GP1OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0908)
5349#define GP1OUT_OUT2_MSK (0x1 << 2 )
5350#define GP1OUT_OUT2 (0x1 << 2 )
5351#define GP1OUT_OUT2_LOW (0x0 << 2 ) /* LOW */
5352#define GP1OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH */
5353
5354/* GP1OUT[OUT1] - Output for port pin */
5355#define GP1OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0904)
5356#define GP1OUT_OUT1_MSK (0x1 << 1 )
5357#define GP1OUT_OUT1 (0x1 << 1 )
5358#define GP1OUT_OUT1_LOW (0x0 << 1 ) /* LOW */
5359#define GP1OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH */
5360
5361/* GP1OUT[OUT0] - Output for port pin */
5362#define GP1OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0900)
5363#define GP1OUT_OUT0_MSK (0x1 << 0 )
5364#define GP1OUT_OUT0 (0x1 << 0 )
5365#define GP1OUT_OUT0_LOW (0x0 << 0 ) /* LOW */
5366#define GP1OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH */
5367
5368/* Reset Value for GP1SET*/
5369#define GP1SET_RVAL 0x0
5370
5371/* GP1SET[SET7] - Set Output High for port pin */
5372#define GP1SET_SET7_BBA (*(volatile unsigned long *) 0x420C099C)
5373#define GP1SET_SET7_MSK (0x1 << 7 )
5374#define GP1SET_SET7 (0x1 << 7 )
5375#define GP1SET_SET7_SET (0x1 << 7 ) /* SET */
5376
5377/* GP1SET[SET6] - Set Output High for port pin */
5378#define GP1SET_SET6_BBA (*(volatile unsigned long *) 0x420C0998)
5379#define GP1SET_SET6_MSK (0x1 << 6 )
5380#define GP1SET_SET6 (0x1 << 6 )
5381#define GP1SET_SET6_SET (0x1 << 6 ) /* SET */
5382
5383/* GP1SET[SET5] - Set Output High for port pin */
5384#define GP1SET_SET5_BBA (*(volatile unsigned long *) 0x420C0994)
5385#define GP1SET_SET5_MSK (0x1 << 5 )
5386#define GP1SET_SET5 (0x1 << 5 )
5387#define GP1SET_SET5_SET (0x1 << 5 ) /* SET */
5388
5389/* GP1SET[SET4] - Set Output High for port pin */
5390#define GP1SET_SET4_BBA (*(volatile unsigned long *) 0x420C0990)
5391#define GP1SET_SET4_MSK (0x1 << 4 )
5392#define GP1SET_SET4 (0x1 << 4 )
5393#define GP1SET_SET4_SET (0x1 << 4 ) /* SET */
5394
5395/* GP1SET[SET3] - Set Output High for port pin */
5396#define GP1SET_SET3_BBA (*(volatile unsigned long *) 0x420C098C)
5397#define GP1SET_SET3_MSK (0x1 << 3 )
5398#define GP1SET_SET3 (0x1 << 3 )
5399#define GP1SET_SET3_SET (0x1 << 3 ) /* SET */
5400
5401/* GP1SET[SET2] - Set Output High for port pin */
5402#define GP1SET_SET2_BBA (*(volatile unsigned long *) 0x420C0988)
5403#define GP1SET_SET2_MSK (0x1 << 2 )
5404#define GP1SET_SET2 (0x1 << 2 )
5405#define GP1SET_SET2_SET (0x1 << 2 ) /* SET */
5406
5407/* GP1SET[SET1] - Set Output High for port pin */
5408#define GP1SET_SET1_BBA (*(volatile unsigned long *) 0x420C0984)
5409#define GP1SET_SET1_MSK (0x1 << 1 )
5410#define GP1SET_SET1 (0x1 << 1 )
5411#define GP1SET_SET1_SET (0x1 << 1 ) /* SET */
5412
5413/* GP1SET[SET0] - Set Output High for port pin */
5414#define GP1SET_SET0_BBA (*(volatile unsigned long *) 0x420C0980)
5415#define GP1SET_SET0_MSK (0x1 << 0 )
5416#define GP1SET_SET0 (0x1 << 0 )
5417#define GP1SET_SET0_SET (0x1 << 0 ) /* SET */
5418
5419/* Reset Value for GP1CLR*/
5420#define GP1CLR_RVAL 0x0
5421
5422/* GP1CLR[CLR7] - Set Output Low for port pin */
5423#define GP1CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C0A1C)
5424#define GP1CLR_CLR7_MSK (0x1 << 7 )
5425#define GP1CLR_CLR7 (0x1 << 7 )
5426#define GP1CLR_CLR7_CLR (0x1 << 7 ) /* CLR */
5427
5428/* GP1CLR[CLR6] - Set Output Low for port pin */
5429#define GP1CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C0A18)
5430#define GP1CLR_CLR6_MSK (0x1 << 6 )
5431#define GP1CLR_CLR6 (0x1 << 6 )
5432#define GP1CLR_CLR6_CLR (0x1 << 6 ) /* CLR */
5433
5434/* GP1CLR[CLR5] - Set Output Low for port pin */
5435#define GP1CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C0A14)
5436#define GP1CLR_CLR5_MSK (0x1 << 5 )
5437#define GP1CLR_CLR5 (0x1 << 5 )
5438#define GP1CLR_CLR5_CLR (0x1 << 5 ) /* CLR */
5439
5440/* GP1CLR[CLR4] - Set Output Low for port pin */
5441#define GP1CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C0A10)
5442#define GP1CLR_CLR4_MSK (0x1 << 4 )
5443#define GP1CLR_CLR4 (0x1 << 4 )
5444#define GP1CLR_CLR4_CLR (0x1 << 4 ) /* CLR */
5445
5446/* GP1CLR[CLR3] - Set Output Low for port pin */
5447#define GP1CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C0A0C)
5448#define GP1CLR_CLR3_MSK (0x1 << 3 )
5449#define GP1CLR_CLR3 (0x1 << 3 )
5450#define GP1CLR_CLR3_CLR (0x1 << 3 ) /* CLR */
5451
5452/* GP1CLR[CLR2] - Set Output Low for port pin */
5453#define GP1CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C0A08)
5454#define GP1CLR_CLR2_MSK (0x1 << 2 )
5455#define GP1CLR_CLR2 (0x1 << 2 )
5456#define GP1CLR_CLR2_CLR (0x1 << 2 ) /* CLR */
5457
5458/* GP1CLR[CLR1] - Set Output Low for port pin */
5459#define GP1CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C0A04)
5460#define GP1CLR_CLR1_MSK (0x1 << 1 )
5461#define GP1CLR_CLR1 (0x1 << 1 )
5462#define GP1CLR_CLR1_CLR (0x1 << 1 ) /* CLR */
5463
5464/* GP1CLR[CLR0] - Set Output Low for port pin */
5465#define GP1CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C0A00)
5466#define GP1CLR_CLR0_MSK (0x1 << 0 )
5467#define GP1CLR_CLR0 (0x1 << 0 )
5468#define GP1CLR_CLR0_CLR (0x1 << 0 ) /* CLR */
5469
5470/* Reset Value for GP1TGL*/
5471#define GP1TGL_RVAL 0x0
5472
5473/* GP1TGL[TGL7] - Toggle Output for port pin */
5474#define GP1TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C0A9C)
5475#define GP1TGL_TGL7_MSK (0x1 << 7 )
5476#define GP1TGL_TGL7 (0x1 << 7 )
5477#define GP1TGL_TGL7_TGL (0x1 << 7 ) /* TGL */
5478
5479/* GP1TGL[TGL6] - Toggle Output for port pin */
5480#define GP1TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C0A98)
5481#define GP1TGL_TGL6_MSK (0x1 << 6 )
5482#define GP1TGL_TGL6 (0x1 << 6 )
5483#define GP1TGL_TGL6_TGL (0x1 << 6 ) /* TGL */
5484
5485/* GP1TGL[TGL5] - Toggle Output for port pin */
5486#define GP1TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C0A94)
5487#define GP1TGL_TGL5_MSK (0x1 << 5 )
5488#define GP1TGL_TGL5 (0x1 << 5 )
5489#define GP1TGL_TGL5_TGL (0x1 << 5 ) /* TGL */
5490
5491/* GP1TGL[TGL4] - Toggle Output for port pin */
5492#define GP1TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C0A90)
5493#define GP1TGL_TGL4_MSK (0x1 << 4 )
5494#define GP1TGL_TGL4 (0x1 << 4 )
5495#define GP1TGL_TGL4_TGL (0x1 << 4 ) /* TGL */
5496
5497/* GP1TGL[TGL3] - Toggle Output for port pin */
5498#define GP1TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C0A8C)
5499#define GP1TGL_TGL3_MSK (0x1 << 3 )
5500#define GP1TGL_TGL3 (0x1 << 3 )
5501#define GP1TGL_TGL3_TGL (0x1 << 3 ) /* TGL */
5502
5503/* GP1TGL[TGL2] - Toggle Output for port pin */
5504#define GP1TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C0A88)
5505#define GP1TGL_TGL2_MSK (0x1 << 2 )
5506#define GP1TGL_TGL2 (0x1 << 2 )
5507#define GP1TGL_TGL2_TGL (0x1 << 2 ) /* TGL */
5508
5509/* GP1TGL[TGL1] - Toggle Output for port pin */
5510#define GP1TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C0A84)
5511#define GP1TGL_TGL1_MSK (0x1 << 1 )
5512#define GP1TGL_TGL1 (0x1 << 1 )
5513#define GP1TGL_TGL1_TGL (0x1 << 1 ) /* TGL */
5514
5515/* GP1TGL[TGL0] - Toggle Output for port pin */
5516#define GP1TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C0A80)
5517#define GP1TGL_TGL0_MSK (0x1 << 0 )
5518#define GP1TGL_TGL0 (0x1 << 0 )
5519#define GP1TGL_TGL0_TGL (0x1 << 0 ) /* TGL */
5520#if (__NO_MMR_STRUCTS__==1)
5521
5522#define GP2CON (*(volatile unsigned short int *) 0x40006060)
5523#define GP2OEN (*(volatile unsigned char *) 0x40006064)
5524#define GP2PUL (*(volatile unsigned char *) 0x40006068)
5525#define GP2OCE (*(volatile unsigned char *) 0x4000606C)
5526#define GP2IN (*(volatile unsigned char *) 0x40006074)
5527#define GP2OUT (*(volatile unsigned char *) 0x40006078)
5528#define GP2SET (*(volatile unsigned char *) 0x4000607C)
5529#define GP2CLR (*(volatile unsigned char *) 0x40006080)
5530#define GP2TGL (*(volatile unsigned char *) 0x40006084)
5531#endif // (__NO_MMR_STRUCTS__==1)
5532
5533/* Reset Value for GP2CON*/
5534#define GP2CON_RVAL 0x0
5535
5536/* GP2CON[CON4] - Configuration bits for P2.4 */
5537#define GP2CON_CON4_MSK (0x3 << 8 )
5538#define GP2CON_CON4_SWDATA (0x1 << 8 ) /* SWDATA */
5539
5540/* GP2CON[CON3] - Configuration bits for P2.3 */
5541#define GP2CON_CON3_MSK (0x3 << 6 )
5542#define GP2CON_CON3_SWCLK (0x1 << 6 ) /* SWCLK */
5543
5544/* GP2CON[CON2] - Configuration bits for P2.2 */
5545#define GP2CON_CON2_MSK (0x3 << 4 )
5546#define GP2CON_CON2_GPIO (0x0 << 4 ) /* GPIO */
5547
5548/* GP2CON[CON1] - Configuration bits for P2.1 */
5549#define GP2CON_CON1_MSK (0x3 << 2 )
5550#define GP2CON_CON1_GPIO (0x0 << 2 ) /* GPIO */
5551#define GP2CON_CON1_I2CSDA (0x1 << 2 ) /* I2CSDA */
5552
5553/* GP2CON[CON0] - Configuration bits for P2.0 */
5554#define GP2CON_CON0_MSK (0x3 << 0 )
5555#define GP2CON_CON0_GPIO (0x0 << 0 ) /* GPIO */
5556#define GP2CON_CON0_I2CSCL (0x1 << 0 ) /* I2CSCL */
5557
5558/* Reset Value for GP2OEN*/
5559#define GP2OEN_RVAL 0x0
5560
5561/* GP2OEN[OEN7] - Direction for port pin */
5562#define GP2OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C0C9C)
5563#define GP2OEN_OEN7_MSK (0x1 << 7 )
5564#define GP2OEN_OEN7 (0x1 << 7 )
5565#define GP2OEN_OEN7_IN (0x0 << 7 ) /* IN */
5566#define GP2OEN_OEN7_OUT (0x1 << 7 ) /* OUT */
5567
5568/* GP2OEN[OEN6] - Direction for port pin */
5569#define GP2OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0C98)
5570#define GP2OEN_OEN6_MSK (0x1 << 6 )
5571#define GP2OEN_OEN6 (0x1 << 6 )
5572#define GP2OEN_OEN6_IN (0x0 << 6 ) /* IN */
5573#define GP2OEN_OEN6_OUT (0x1 << 6 ) /* OUT */
5574
5575/* GP2OEN[OEN5] - Direction for port pin */
5576#define GP2OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0C94)
5577#define GP2OEN_OEN5_MSK (0x1 << 5 )
5578#define GP2OEN_OEN5 (0x1 << 5 )
5579#define GP2OEN_OEN5_IN (0x0 << 5 ) /* IN */
5580#define GP2OEN_OEN5_OUT (0x1 << 5 ) /* OUT */
5581
5582/* GP2OEN[OEN4] - Direction for port pin */
5583#define GP2OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0C90)
5584#define GP2OEN_OEN4_MSK (0x1 << 4 )
5585#define GP2OEN_OEN4 (0x1 << 4 )
5586#define GP2OEN_OEN4_IN (0x0 << 4 ) /* IN */
5587#define GP2OEN_OEN4_OUT (0x1 << 4 ) /* OUT */
5588
5589/* GP2OEN[OEN3] - Direction for port pin */
5590#define GP2OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C0C8C)
5591#define GP2OEN_OEN3_MSK (0x1 << 3 )
5592#define GP2OEN_OEN3 (0x1 << 3 )
5593#define GP2OEN_OEN3_IN (0x0 << 3 ) /* IN */
5594#define GP2OEN_OEN3_OUT (0x1 << 3 ) /* OUT */
5595
5596/* GP2OEN[OEN2] - Direction for port pin */
5597#define GP2OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0C88)
5598#define GP2OEN_OEN2_MSK (0x1 << 2 )
5599#define GP2OEN_OEN2 (0x1 << 2 )
5600#define GP2OEN_OEN2_IN (0x0 << 2 ) /* IN */
5601#define GP2OEN_OEN2_OUT (0x1 << 2 ) /* OUT */
5602
5603/* GP2OEN[OEN1] - Direction for port pin */
5604#define GP2OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0C84)
5605#define GP2OEN_OEN1_MSK (0x1 << 1 )
5606#define GP2OEN_OEN1 (0x1 << 1 )
5607#define GP2OEN_OEN1_IN (0x0 << 1 ) /* IN */
5608#define GP2OEN_OEN1_OUT (0x1 << 1 ) /* OUT */
5609
5610/* GP2OEN[OEN0] - Direction for port pin */
5611#define GP2OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0C80)
5612#define GP2OEN_OEN0_MSK (0x1 << 0 )
5613#define GP2OEN_OEN0 (0x1 << 0 )
5614#define GP2OEN_OEN0_IN (0x0 << 0 ) /* IN */
5615#define GP2OEN_OEN0_OUT (0x1 << 0 ) /* OUT */
5616
5617/* Reset Value for GP2PUL*/
5618#define GP2PUL_RVAL 0xFF
5619
5620/* GP2PUL[PUL7] - Pull Up Enable for port pin */
5621#define GP2PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C0D1C)
5622#define GP2PUL_PUL7_MSK (0x1 << 7 )
5623#define GP2PUL_PUL7 (0x1 << 7 )
5624#define GP2PUL_PUL7_DIS (0x0 << 7 ) /* DIS */
5625#define GP2PUL_PUL7_EN (0x1 << 7 ) /* EN */
5626
5627/* GP2PUL[PUL6] - Pull Up Enable for port pin */
5628#define GP2PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0D18)
5629#define GP2PUL_PUL6_MSK (0x1 << 6 )
5630#define GP2PUL_PUL6 (0x1 << 6 )
5631#define GP2PUL_PUL6_DIS (0x0 << 6 ) /* DIS */
5632#define GP2PUL_PUL6_EN (0x1 << 6 ) /* EN */
5633
5634/* GP2PUL[PUL5] - Pull Up Enable for port pin */
5635#define GP2PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0D14)
5636#define GP2PUL_PUL5_MSK (0x1 << 5 )
5637#define GP2PUL_PUL5 (0x1 << 5 )
5638#define GP2PUL_PUL5_DIS (0x0 << 5 ) /* DIS */
5639#define GP2PUL_PUL5_EN (0x1 << 5 ) /* EN */
5640
5641/* GP2PUL[PUL4] - Pull Up Enable for port pin */
5642#define GP2PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0D10)
5643#define GP2PUL_PUL4_MSK (0x1 << 4 )
5644#define GP2PUL_PUL4 (0x1 << 4 )
5645#define GP2PUL_PUL4_DIS (0x0 << 4 ) /* DIS */
5646#define GP2PUL_PUL4_EN (0x1 << 4 ) /* EN */
5647
5648/* GP2PUL[PUL3] - Pull Up Enable for port pin */
5649#define GP2PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C0D0C)
5650#define GP2PUL_PUL3_MSK (0x1 << 3 )
5651#define GP2PUL_PUL3 (0x1 << 3 )
5652#define GP2PUL_PUL3_DIS (0x0 << 3 ) /* DIS */
5653#define GP2PUL_PUL3_EN (0x1 << 3 ) /* EN */
5654
5655/* GP2PUL[PUL2] - Pull Up Enable for port pin */
5656#define GP2PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0D08)
5657#define GP2PUL_PUL2_MSK (0x1 << 2 )
5658#define GP2PUL_PUL2 (0x1 << 2 )
5659#define GP2PUL_PUL2_DIS (0x0 << 2 ) /* DIS */
5660#define GP2PUL_PUL2_EN (0x1 << 2 ) /* EN */
5661
5662/* GP2PUL[PUL1] - Pull Up Enable for port pin */
5663#define GP2PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0D04)
5664#define GP2PUL_PUL1_MSK (0x1 << 1 )
5665#define GP2PUL_PUL1 (0x1 << 1 )
5666#define GP2PUL_PUL1_DIS (0x0 << 1 ) /* DIS */
5667#define GP2PUL_PUL1_EN (0x1 << 1 ) /* EN */
5668
5669/* GP2PUL[PUL0] - Pull Up Enable for port pin */
5670#define GP2PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0D00)
5671#define GP2PUL_PUL0_MSK (0x1 << 0 )
5672#define GP2PUL_PUL0 (0x1 << 0 )
5673#define GP2PUL_PUL0_DIS (0x0 << 0 ) /* DIS */
5674#define GP2PUL_PUL0_EN (0x1 << 0 ) /* EN */
5675
5676/* Reset Value for GP2OCE*/
5677#define GP2OCE_RVAL 0x0
5678
5679/* GP2OCE[OCE7] - open circuit Enable for port pin */
5680#define GP2OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C0D9C)
5681#define GP2OCE_OCE7_MSK (0x1 << 7 )
5682#define GP2OCE_OCE7 (0x1 << 7 )
5683#define GP2OCE_OCE7_DIS (0x0 << 7 ) /* DIS */
5684#define GP2OCE_OCE7_EN (0x1 << 7 ) /* EN */
5685
5686/* GP2OCE[OCE6] - open circuit Enable for port pin */
5687#define GP2OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0D98)
5688#define GP2OCE_OCE6_MSK (0x1 << 6 )
5689#define GP2OCE_OCE6 (0x1 << 6 )
5690#define GP2OCE_OCE6_DIS (0x0 << 6 ) /* DIS */
5691#define GP2OCE_OCE6_EN (0x1 << 6 ) /* EN */
5692
5693/* GP2OCE[OCE5] - open circuit Enable for port pin */
5694#define GP2OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0D94)
5695#define GP2OCE_OCE5_MSK (0x1 << 5 )
5696#define GP2OCE_OCE5 (0x1 << 5 )
5697#define GP2OCE_OCE5_DIS (0x0 << 5 ) /* DIS */
5698#define GP2OCE_OCE5_EN (0x1 << 5 ) /* EN */
5699
5700/* GP2OCE[OCE4] - open circuit Enable for port pin */
5701#define GP2OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0D90)
5702#define GP2OCE_OCE4_MSK (0x1 << 4 )
5703#define GP2OCE_OCE4 (0x1 << 4 )
5704#define GP2OCE_OCE4_DIS (0x0 << 4 ) /* DIS */
5705#define GP2OCE_OCE4_EN (0x1 << 4 ) /* EN */
5706
5707/* GP2OCE[OCE3] - open circuit Enable for port pin */
5708#define GP2OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C0D8C)
5709#define GP2OCE_OCE3_MSK (0x1 << 3 )
5710#define GP2OCE_OCE3 (0x1 << 3 )
5711#define GP2OCE_OCE3_DIS (0x0 << 3 ) /* DIS */
5712#define GP2OCE_OCE3_EN (0x1 << 3 ) /* EN */
5713
5714/* GP2OCE[OCE2] - open circuit Enable for port pin */
5715#define GP2OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0D88)
5716#define GP2OCE_OCE2_MSK (0x1 << 2 )
5717#define GP2OCE_OCE2 (0x1 << 2 )
5718#define GP2OCE_OCE2_DIS (0x0 << 2 ) /* DIS */
5719#define GP2OCE_OCE2_EN (0x1 << 2 ) /* EN */
5720
5721/* GP2OCE[OCE1] - open circuit Enable for port pin */
5722#define GP2OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0D84)
5723#define GP2OCE_OCE1_MSK (0x1 << 1 )
5724#define GP2OCE_OCE1 (0x1 << 1 )
5725#define GP2OCE_OCE1_DIS (0x0 << 1 ) /* DIS */
5726#define GP2OCE_OCE1_EN (0x1 << 1 ) /* EN */
5727
5728/* GP2OCE[OCE0] - open circuit Enable for port pin */
5729#define GP2OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0D80)
5730#define GP2OCE_OCE0_MSK (0x1 << 0 )
5731#define GP2OCE_OCE0 (0x1 << 0 )
5732#define GP2OCE_OCE0_DIS (0x0 << 0 ) /* DIS */
5733#define GP2OCE_OCE0_EN (0x1 << 0 ) /* EN */
5734
5735/* Reset Value for GP2IN*/
5736#define GP2IN_RVAL 0x0
5737
5738/* GP2IN[IN7] - Input for port pin */
5739#define GP2IN_IN7_BBA (*(volatile unsigned long *) 0x420C0E9C)
5740#define GP2IN_IN7_MSK (0x1 << 7 )
5741#define GP2IN_IN7 (0x1 << 7 )
5742#define GP2IN_IN7_LOW (0x0 << 7 ) /* LOW */
5743#define GP2IN_IN7_HIGH (0x1 << 7 ) /* HIGH */
5744
5745/* GP2IN[IN6] - Input for port pin */
5746#define GP2IN_IN6_BBA (*(volatile unsigned long *) 0x420C0E98)
5747#define GP2IN_IN6_MSK (0x1 << 6 )
5748#define GP2IN_IN6 (0x1 << 6 )
5749#define GP2IN_IN6_LOW (0x0 << 6 ) /* LOW */
5750#define GP2IN_IN6_HIGH (0x1 << 6 ) /* HIGH */
5751
5752/* GP2IN[IN5] - Input for port pin */
5753#define GP2IN_IN5_BBA (*(volatile unsigned long *) 0x420C0E94)
5754#define GP2IN_IN5_MSK (0x1 << 5 )
5755#define GP2IN_IN5 (0x1 << 5 )
5756#define GP2IN_IN5_LOW (0x0 << 5 ) /* LOW */
5757#define GP2IN_IN5_HIGH (0x1 << 5 ) /* HIGH */
5758
5759/* GP2IN[IN4] - Input for port pin */
5760#define GP2IN_IN4_BBA (*(volatile unsigned long *) 0x420C0E90)
5761#define GP2IN_IN4_MSK (0x1 << 4 )
5762#define GP2IN_IN4 (0x1 << 4 )
5763#define GP2IN_IN4_LOW (0x0 << 4 ) /* LOW */
5764#define GP2IN_IN4_HIGH (0x1 << 4 ) /* HIGH */
5765
5766/* GP2IN[IN3] - Input for port pin */
5767#define GP2IN_IN3_BBA (*(volatile unsigned long *) 0x420C0E8C)
5768#define GP2IN_IN3_MSK (0x1 << 3 )
5769#define GP2IN_IN3 (0x1 << 3 )
5770#define GP2IN_IN3_LOW (0x0 << 3 ) /* LOW */
5771#define GP2IN_IN3_HIGH (0x1 << 3 ) /* HIGH */
5772
5773/* GP2IN[IN2] - Input for port pin */
5774#define GP2IN_IN2_BBA (*(volatile unsigned long *) 0x420C0E88)
5775#define GP2IN_IN2_MSK (0x1 << 2 )
5776#define GP2IN_IN2 (0x1 << 2 )
5777#define GP2IN_IN2_LOW (0x0 << 2 ) /* LOW */
5778#define GP2IN_IN2_HIGH (0x1 << 2 ) /* HIGH */
5779
5780/* GP2IN[IN1] - Input for port pin */
5781#define GP2IN_IN1_BBA (*(volatile unsigned long *) 0x420C0E84)
5782#define GP2IN_IN1_MSK (0x1 << 1 )
5783#define GP2IN_IN1 (0x1 << 1 )
5784#define GP2IN_IN1_LOW (0x0 << 1 ) /* LOW */
5785#define GP2IN_IN1_HIGH (0x1 << 1 ) /* HIGH */
5786
5787/* GP2IN[IN0] - Input for port pin */
5788#define GP2IN_IN0_BBA (*(volatile unsigned long *) 0x420C0E80)
5789#define GP2IN_IN0_MSK (0x1 << 0 )
5790#define GP2IN_IN0 (0x1 << 0 )
5791#define GP2IN_IN0_LOW (0x0 << 0 ) /* LOW */
5792#define GP2IN_IN0_HIGH (0x1 << 0 ) /* HIGH */
5793
5794/* Reset Value for GP2OUT*/
5795#define GP2OUT_RVAL 0x0
5796
5797/* GP2OUT[OUT7] - Output for port pin */
5798#define GP2OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C0F1C)
5799#define GP2OUT_OUT7_MSK (0x1 << 7 )
5800#define GP2OUT_OUT7 (0x1 << 7 )
5801#define GP2OUT_OUT7_LOW (0x0 << 7 ) /* LOW */
5802#define GP2OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH */
5803
5804/* GP2OUT[OUT6] - Output for port pin */
5805#define GP2OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0F18)
5806#define GP2OUT_OUT6_MSK (0x1 << 6 )
5807#define GP2OUT_OUT6 (0x1 << 6 )
5808#define GP2OUT_OUT6_LOW (0x0 << 6 ) /* LOW */
5809#define GP2OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH */
5810
5811/* GP2OUT[OUT5] - Output for port pin */
5812#define GP2OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0F14)
5813#define GP2OUT_OUT5_MSK (0x1 << 5 )
5814#define GP2OUT_OUT5 (0x1 << 5 )
5815#define GP2OUT_OUT5_LOW (0x0 << 5 ) /* LOW */
5816#define GP2OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH */
5817
5818/* GP2OUT[OUT4] - Output for port pin */
5819#define GP2OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0F10)
5820#define GP2OUT_OUT4_MSK (0x1 << 4 )
5821#define GP2OUT_OUT4 (0x1 << 4 )
5822#define GP2OUT_OUT4_LOW (0x0 << 4 ) /* LOW */
5823#define GP2OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH */
5824
5825/* GP2OUT[OUT3] - Output for port pin */
5826#define GP2OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C0F0C)
5827#define GP2OUT_OUT3_MSK (0x1 << 3 )
5828#define GP2OUT_OUT3 (0x1 << 3 )
5829#define GP2OUT_OUT3_LOW (0x0 << 3 ) /* LOW */
5830#define GP2OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH */
5831
5832/* GP2OUT[OUT2] - Output for port pin */
5833#define GP2OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0F08)
5834#define GP2OUT_OUT2_MSK (0x1 << 2 )
5835#define GP2OUT_OUT2 (0x1 << 2 )
5836#define GP2OUT_OUT2_LOW (0x0 << 2 ) /* LOW */
5837#define GP2OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH */
5838
5839/* GP2OUT[OUT1] - Output for port pin */
5840#define GP2OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0F04)
5841#define GP2OUT_OUT1_MSK (0x1 << 1 )
5842#define GP2OUT_OUT1 (0x1 << 1 )
5843#define GP2OUT_OUT1_LOW (0x0 << 1 ) /* LOW */
5844#define GP2OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH */
5845
5846/* GP2OUT[OUT0] - Output for port pin */
5847#define GP2OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0F00)
5848#define GP2OUT_OUT0_MSK (0x1 << 0 )
5849#define GP2OUT_OUT0 (0x1 << 0 )
5850#define GP2OUT_OUT0_LOW (0x0 << 0 ) /* LOW */
5851#define GP2OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH */
5852
5853/* Reset Value for GP2SET*/
5854#define GP2SET_RVAL 0x0
5855
5856/* GP2SET[SET7] - Set Output High for port pin */
5857#define GP2SET_SET7_BBA (*(volatile unsigned long *) 0x420C0F9C)
5858#define GP2SET_SET7_MSK (0x1 << 7 )
5859#define GP2SET_SET7 (0x1 << 7 )
5860#define GP2SET_SET7_SET (0x1 << 7 ) /* SET */
5861
5862/* GP2SET[SET6] - Set Output High for port pin */
5863#define GP2SET_SET6_BBA (*(volatile unsigned long *) 0x420C0F98)
5864#define GP2SET_SET6_MSK (0x1 << 6 )
5865#define GP2SET_SET6 (0x1 << 6 )
5866#define GP2SET_SET6_SET (0x1 << 6 ) /* SET */
5867
5868/* GP2SET[SET5] - Set Output High for port pin */
5869#define GP2SET_SET5_BBA (*(volatile unsigned long *) 0x420C0F94)
5870#define GP2SET_SET5_MSK (0x1 << 5 )
5871#define GP2SET_SET5 (0x1 << 5 )
5872#define GP2SET_SET5_SET (0x1 << 5 ) /* SET */
5873
5874/* GP2SET[SET4] - Set Output High for port pin */
5875#define GP2SET_SET4_BBA (*(volatile unsigned long *) 0x420C0F90)
5876#define GP2SET_SET4_MSK (0x1 << 4 )
5877#define GP2SET_SET4 (0x1 << 4 )
5878#define GP2SET_SET4_SET (0x1 << 4 ) /* SET */
5879
5880/* GP2SET[SET3] - Set Output High for port pin */
5881#define GP2SET_SET3_BBA (*(volatile unsigned long *) 0x420C0F8C)
5882#define GP2SET_SET3_MSK (0x1 << 3 )
5883#define GP2SET_SET3 (0x1 << 3 )
5884#define GP2SET_SET3_SET (0x1 << 3 ) /* SET */
5885
5886/* GP2SET[SET2] - Set Output High for port pin */
5887#define GP2SET_SET2_BBA (*(volatile unsigned long *) 0x420C0F88)
5888#define GP2SET_SET2_MSK (0x1 << 2 )
5889#define GP2SET_SET2 (0x1 << 2 )
5890#define GP2SET_SET2_SET (0x1 << 2 ) /* SET */
5891
5892/* GP2SET[SET1] - Set Output High for port pin */
5893#define GP2SET_SET1_BBA (*(volatile unsigned long *) 0x420C0F84)
5894#define GP2SET_SET1_MSK (0x1 << 1 )
5895#define GP2SET_SET1 (0x1 << 1 )
5896#define GP2SET_SET1_SET (0x1 << 1 ) /* SET */
5897
5898/* GP2SET[SET0] - Set Output High for port pin */
5899#define GP2SET_SET0_BBA (*(volatile unsigned long *) 0x420C0F80)
5900#define GP2SET_SET0_MSK (0x1 << 0 )
5901#define GP2SET_SET0 (0x1 << 0 )
5902#define GP2SET_SET0_SET (0x1 << 0 ) /* SET */
5903
5904/* Reset Value for GP2CLR*/
5905#define GP2CLR_RVAL 0x0
5906
5907/* GP2CLR[CLR7] - Set Output Low for port pin */
5908#define GP2CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C101C)
5909#define GP2CLR_CLR7_MSK (0x1 << 7 )
5910#define GP2CLR_CLR7 (0x1 << 7 )
5911#define GP2CLR_CLR7_CLR (0x1 << 7 ) /* CLR */
5912
5913/* GP2CLR[CLR6] - Set Output Low for port pin */
5914#define GP2CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C1018)
5915#define GP2CLR_CLR6_MSK (0x1 << 6 )
5916#define GP2CLR_CLR6 (0x1 << 6 )
5917#define GP2CLR_CLR6_CLR (0x1 << 6 ) /* CLR */
5918
5919/* GP2CLR[CLR5] - Set Output Low for port pin */
5920#define GP2CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C1014)
5921#define GP2CLR_CLR5_MSK (0x1 << 5 )
5922#define GP2CLR_CLR5 (0x1 << 5 )
5923#define GP2CLR_CLR5_CLR (0x1 << 5 ) /* CLR */
5924
5925/* GP2CLR[CLR4] - Set Output Low for port pin */
5926#define GP2CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C1010)
5927#define GP2CLR_CLR4_MSK (0x1 << 4 )
5928#define GP2CLR_CLR4 (0x1 << 4 )
5929#define GP2CLR_CLR4_CLR (0x1 << 4 ) /* CLR */
5930
5931/* GP2CLR[CLR3] - Set Output Low for port pin */
5932#define GP2CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C100C)
5933#define GP2CLR_CLR3_MSK (0x1 << 3 )
5934#define GP2CLR_CLR3 (0x1 << 3 )
5935#define GP2CLR_CLR3_CLR (0x1 << 3 ) /* CLR */
5936
5937/* GP2CLR[CLR2] - Set Output Low for port pin */
5938#define GP2CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C1008)
5939#define GP2CLR_CLR2_MSK (0x1 << 2 )
5940#define GP2CLR_CLR2 (0x1 << 2 )
5941#define GP2CLR_CLR2_CLR (0x1 << 2 ) /* CLR */
5942
5943/* GP2CLR[CLR1] - Set Output Low for port pin */
5944#define GP2CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C1004)
5945#define GP2CLR_CLR1_MSK (0x1 << 1 )
5946#define GP2CLR_CLR1 (0x1 << 1 )
5947#define GP2CLR_CLR1_CLR (0x1 << 1 ) /* CLR */
5948
5949/* GP2CLR[CLR0] - Set Output Low for port pin */
5950#define GP2CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C1000)
5951#define GP2CLR_CLR0_MSK (0x1 << 0 )
5952#define GP2CLR_CLR0 (0x1 << 0 )
5953#define GP2CLR_CLR0_CLR (0x1 << 0 ) /* CLR */
5954
5955/* Reset Value for GP2TGL*/
5956#define GP2TGL_RVAL 0x0
5957
5958/* GP2TGL[TGL7] - Toggle Output for port pin */
5959#define GP2TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C109C)
5960#define GP2TGL_TGL7_MSK (0x1 << 7 )
5961#define GP2TGL_TGL7 (0x1 << 7 )
5962#define GP2TGL_TGL7_TGL (0x1 << 7 ) /* TGL */
5963
5964/* GP2TGL[TGL6] - Toggle Output for port pin */
5965#define GP2TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C1098)
5966#define GP2TGL_TGL6_MSK (0x1 << 6 )
5967#define GP2TGL_TGL6 (0x1 << 6 )
5968#define GP2TGL_TGL6_TGL (0x1 << 6 ) /* TGL */
5969
5970/* GP2TGL[TGL5] - Toggle Output for port pin */
5971#define GP2TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C1094)
5972#define GP2TGL_TGL5_MSK (0x1 << 5 )
5973#define GP2TGL_TGL5 (0x1 << 5 )
5974#define GP2TGL_TGL5_TGL (0x1 << 5 ) /* TGL */
5975
5976/* GP2TGL[TGL4] - Toggle Output for port pin */
5977#define GP2TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C1090)
5978#define GP2TGL_TGL4_MSK (0x1 << 4 )
5979#define GP2TGL_TGL4 (0x1 << 4 )
5980#define GP2TGL_TGL4_TGL (0x1 << 4 ) /* TGL */
5981
5982/* GP2TGL[TGL3] - Toggle Output for port pin */
5983#define GP2TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C108C)
5984#define GP2TGL_TGL3_MSK (0x1 << 3 )
5985#define GP2TGL_TGL3 (0x1 << 3 )
5986#define GP2TGL_TGL3_TGL (0x1 << 3 ) /* TGL */
5987
5988/* GP2TGL[TGL2] - Toggle Output for port pin */
5989#define GP2TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C1088)
5990#define GP2TGL_TGL2_MSK (0x1 << 2 )
5991#define GP2TGL_TGL2 (0x1 << 2 )
5992#define GP2TGL_TGL2_TGL (0x1 << 2 ) /* TGL */
5993
5994/* GP2TGL[TGL1] - Toggle Output for port pin */
5995#define GP2TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C1084)
5996#define GP2TGL_TGL1_MSK (0x1 << 1 )
5997#define GP2TGL_TGL1 (0x1 << 1 )
5998#define GP2TGL_TGL1_TGL (0x1 << 1 ) /* TGL */
5999
6000/* GP2TGL[TGL0] - Toggle Output for port pin */
6001#define GP2TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C1080)
6002#define GP2TGL_TGL0_MSK (0x1 << 0 )
6003#define GP2TGL_TGL0 (0x1 << 0 )
6004#define GP2TGL_TGL0_TGL (0x1 << 0 ) /* TGL */
6005// ------------------------------------------------------------------------------------------------
6006// ----- ANA -----
6007// ------------------------------------------------------------------------------------------------
6008
6009
6010/**
6011 * @brief Analog Control (pADI_ANA)
6012 */
6013
6014#if (__NO_MMR_STRUCTS__==0)
6015typedef struct { /*!< pADI_ANA Structure */
6016 __I uint32_t RESERVED0[12];
6017 __IO uint16_t REFCTRL; /*!< Internal Reference Control register */
6018 __I uint16_t RESERVED1[7];
6019 __IO uint8_t IEXCCON; /*!< Controls the on-chip Excitation Current Sources */
6020 __I uint8_t RESERVED2[3];
6021 __IO uint8_t IEXCDAT; /*!< Sets the output current setting for both Excitation Current sources */
6022} ADI_ANA_TypeDef;
6023#else // (__NO_MMR_STRUCTS__==0)
6024#define REFCTRL (*(volatile unsigned short int *) 0x40008840)
6025#define IEXCCON (*(volatile unsigned char *) 0x40008850)
6026#define IEXCDAT (*(volatile unsigned char *) 0x40008854)
6027#endif // (__NO_MMR_STRUCTS__==0)
6028
6029/* Reset Value for REFCTRL*/
6030#define REFCTRL_RVAL 0x0
6031
6032/* REFCTRL[REFPD] - Power down reference */
6033#define REFCTRL_REFPD_BBA (*(volatile unsigned long *) 0x42110800)
6034#define REFCTRL_REFPD_MSK (0x1 << 0 )
6035#define REFCTRL_REFPD (0x1 << 0 )
6036#define REFCTRL_REFPD_DIS (0x0 << 0 ) /* DIS */
6037#define REFCTRL_REFPD_EN (0x1 << 0 ) /* EN */
6038
6039/* Reset Value for IEXCCON*/
6040#define IEXCCON_RVAL 0xC0
6041
6042/* IEXCCON[PD] - IEXC Power down- bits */
6043#define IEXCCON_PD_BBA (*(volatile unsigned long *) 0x42110A1C)
6044#define IEXCCON_PD_MSK (0x1 << 7 )
6045#define IEXCCON_PD (0x1 << 7 )
6046#define IEXCCON_PD_En (0x1 << 7 ) /* En */
6047#define IEXCCON_PD_off (0x0 << 7 ) /* off */
6048
6049/* IEXCCON[REFSEL] - IREF Source- bits */
6050#define IEXCCON_REFSEL_BBA (*(volatile unsigned long *) 0x42110A18)
6051#define IEXCCON_REFSEL_MSK (0x1 << 6 )
6052#define IEXCCON_REFSEL (0x1 << 6 )
6053#define IEXCCON_REFSEL_Ext (0x0 << 6 ) /* Ext */
6054#define IEXCCON_REFSEL_Int (0x1 << 6 ) /* Int */
6055
6056/* IEXCCON[IPSEL1] - Select IEXC1 pin AIN- bits */
6057#define IEXCCON_IPSEL1_MSK (0x7 << 3 )
6058#define IEXCCON_IPSEL1_Off (0x0 << 3 ) /* Off */
6059#define IEXCCON_IPSEL1_AIN4 (0x4 << 3 ) /* AIN4 */
6060#define IEXCCON_IPSEL1_AIN5 (0x5 << 3 ) /* AIN5 */
6061#define IEXCCON_IPSEL1_AIN6 (0x6 << 3 ) /* AIN6 */
6062#define IEXCCON_IPSEL1_AIN7 (0x7 << 3 ) /* AIN7 */
6063
6064/* IEXCCON[IPSEL0] - Select IEXC0 pin AIN- bits */
6065#define IEXCCON_IPSEL0_MSK (0x7 << 0 )
6066#define IEXCCON_IPSEL0_Off (0x0 << 0 ) /* Off */
6067#define IEXCCON_IPSEL0_AIN4 (0x4 << 0 ) /* AIN4 */
6068#define IEXCCON_IPSEL0_AIN5 (0x5 << 0 ) /* AIN5 */
6069#define IEXCCON_IPSEL0_AIN6 (0x6 << 0 ) /* AIN6 */
6070#define IEXCCON_IPSEL0_AIN7 (0x7 << 0 ) /* AIN7 */
6071
6072/* Reset Value for IEXCDAT*/
6073#define IEXCDAT_RVAL 0x6
6074
6075/* IEXCDAT[IDAT] - Output Current- bits */
6076#define IEXCDAT_IDAT_MSK (0x1F << 1 )
6077#define IEXCDAT_IDAT_0uA (0x0 << 1 ) /* 0uA */
6078#define IEXCDAT_IDAT_50uA (0x4 << 1 ) /* 50uA */
6079#define IEXCDAT_IDAT_100uA (0x5 << 1 ) /* 100uA */
6080#define IEXCDAT_IDAT_150uA (0x6 << 1 ) /* 150uA */
6081#define IEXCDAT_IDAT_200uA (0x7 << 1 ) /* 200uA */
6082#define IEXCDAT_IDAT_250uA (0x14 << 1 ) /* 250uA */
6083#define IEXCDAT_IDAT_300uA (0xA << 1 ) /* 300uA */
6084#define IEXCDAT_IDAT_400uA (0xB << 1 ) /* 400uA */
6085#define IEXCDAT_IDAT_450uA (0xE << 1 ) /* 450uA */
6086#define IEXCDAT_IDAT_500uA (0x15 << 1 ) /* 500uA */
6087#define IEXCDAT_IDAT_600uA (0xF << 1 ) /* 600uA */
6088#define IEXCDAT_IDAT_750uA (0x16 << 1 ) /* 750uA */
6089#define IEXCDAT_IDAT_800uA (0x13 << 1 ) /* 800uA */
6090#define IEXCDAT_IDAT_1mA (0x1F << 1 ) /* 1mA */
6091
6092/* IEXCDAT[IDAT0] - 10uA Enable */
6093#define IEXCDAT_IDAT0_BBA (*(volatile unsigned long *) 0x42110A80)
6094#define IEXCDAT_IDAT0_MSK (0x1 << 0 )
6095#define IEXCDAT_IDAT0 (0x1 << 0 )
6096#define IEXCDAT_IDAT0_DIS (0x0 << 0 ) /* DIS */
6097#define IEXCDAT_IDAT0_EN (0x1 << 0 ) /* EN */
6098// ------------------------------------------------------------------------------------------------
6099// ----- DMA -----
6100// ------------------------------------------------------------------------------------------------
6101
6102
6103/**
6104 * @brief Direct Memory Access (pADI_DMA)
6105 */
6106
6107#if (__NO_MMR_STRUCTS__==0)
6108typedef struct { /*!< pADI_DMA Structure */
6109 __IO uint32_t DMASTA; /*!< Returns the status of the controller when not in the reset state. */
6110 __IO uint32_t DMACFG; /*!< Configuraton */
6111 __IO uint32_t DMAPDBPTR; /*!< Channel primary control database pointer */
6112 __IO uint32_t DMAADBPTR; /*!< Channel alt control database pointer */
6113 __I uint32_t RESERVED0;
6114 __IO uint32_t DMASWREQ; /*!< Channel Software Request */
6115 __I uint32_t RESERVED1[2];
6116 __IO uint32_t DMARMSKSET; /*!< Channel Request Mask Set */
6117 __IO uint32_t DMARMSKCLR; /*!< Channel Request Mask Clear */
6118 __IO uint32_t DMAENSET; /*!< Channel Enable Set */
6119 __IO uint32_t DMAENCLR; /*!< Channel Enable Clear */
6120 __IO uint32_t DMAALTSET; /*!< Channel Primary-Alternate Set */
6121 __IO uint32_t DMAALTCLR; /*!< Channel Primary-Alternate Clear */
6122 __IO uint32_t DMAPRISET; /*!< Channel Priority Set */
6123 __IO uint32_t DMAPRICLR; /*!< Channel Priority Clear */
6124 __I uint32_t RESERVED2[3];
6125 __IO uint32_t DMAERRCLR; /*!< Bus Error Clear */
6126 __I uint32_t RESERVED3[492];
6127 __IO uint32_t DMABSSET; /*!< DMA channel bytes swap enable set */
6128 __IO uint32_t DMABSCLR; /*!< DMA channel bytes swap enable clear */
6129 __I uint32_t RESERVED4[66];
6130 __IO uint32_t DMAGETNMINUS1; /*!< Request n_minus_1 register update */
6131 __IO uint32_t DMANMINUS1; /*!< Current n_minus_1 value */
6132} ADI_DMA_TypeDef;
6133#else // (__NO_MMR_STRUCTS__==0)
6134#define DMASTA (*(volatile unsigned long *) 0x40010000)
6135#define DMACFG (*(volatile unsigned long *) 0x40010004)
6136#define DMAPDBPTR (*(volatile unsigned long *) 0x40010008)
6137#define DMAADBPTR (*(volatile unsigned long *) 0x4001000C)
6138#define DMASWREQ (*(volatile unsigned long *) 0x40010014)
6139#define DMARMSKSET (*(volatile unsigned long *) 0x40010020)
6140#define DMARMSKCLR (*(volatile unsigned long *) 0x40010024)
6141#define DMAENSET (*(volatile unsigned long *) 0x40010028)
6142#define DMAENCLR (*(volatile unsigned long *) 0x4001002C)
6143#define DMAALTSET (*(volatile unsigned long *) 0x40010030)
6144#define DMAALTCLR (*(volatile unsigned long *) 0x40010034)
6145#define DMAPRISET (*(volatile unsigned long *) 0x40010038)
6146#define DMAPRICLR (*(volatile unsigned long *) 0x4001003C)
6147#define DMAERRCLR (*(volatile unsigned long *) 0x4001004C)
6148#define DMABSSET (*(volatile unsigned long *) 0x40010800)
6149#define DMABSCLR (*(volatile unsigned long *) 0x40010804)
6150#define DMAGETNMINUS1 (*(volatile unsigned long *) 0x40010910)
6151#define DMANMINUS1 (*(volatile unsigned long *) 0x40010914)
6152#endif // (__NO_MMR_STRUCTS__==0)
6153
6154/* Reset Value for DMASTA*/
6155#define DMASTA_RVAL 0xB0000
6156
6157/* DMASTA[CHNLSMINUS1] - Number of available DMA channels minus one. */
6158#define DMASTA_CHNLSMINUS1_MSK (0x1F << 16 )
6159#define DMASTA_CHNLSMINUS1_FOURTEENCHNLS (0xD << 16 ) /* FOURTEENCHNLS - Controller configured to use 14 DMA channels */
6160#define DMASTA_CHNLSMINUS1_TWELVECHNLS (0xB << 16 ) /* TWELVECHNLS - Controller configured to use 12 DMA channels */
6161
6162/* DMASTA[STATE] - Current state of the control state machine. */
6163#define DMASTA_STATE_MSK (0xF << 4 )
6164#define DMASTA_STATE_IDLE (0x0 << 4 ) /* IDLE - Idle */
6165#define DMASTA_STATE_RDCHNLDATA (0x1 << 4 ) /* RDCHNLDATA - Reading channel controller data */
6166#define DMASTA_STATE_RDSRCENDPTR (0x2 << 4 ) /* RDSRCENDPTR - Reading source data end pointer */
6167#define DMASTA_STATE_RDDSTENDPTR (0x3 << 4 ) /* RDDSTENDPTR - Reading destination data end pointer */
6168#define DMASTA_STATE_RDSRCDATA (0x4 << 4 ) /* RDSRCDATA - Reading source data */
6169#define DMASTA_STATE_WRDSTDATA (0x5 << 4 ) /* WRDSTDATA - Writing destination data */
6170#define DMASTA_STATE_WAITDMAREQCLR (0x6 << 4 ) /* WAITDMAREQCLR - Waiting for DMA request to clear */
6171#define DMASTA_STATE_WRCHNLDATA (0x7 << 4 ) /* WRCHNLDATA - Writing channel controller data */
6172#define DMASTA_STATE_STALLED (0x8 << 4 ) /* STALLED - Stalled */
6173#define DMASTA_STATE_DONE (0x9 << 4 ) /* DONE - Done */
6174#define DMASTA_STATE_SCATRGATHR (0xA << 4 ) /* SCATRGATHR - Peripheral scatter-gather transition */
6175
6176/* DMASTA[ENABLE] - Master DMA controller enable status. */
6177#define DMASTA_ENABLE_BBA (*(volatile unsigned long *) 0x42200000)
6178#define DMASTA_ENABLE_MSK (0x1 << 0 )
6179#define DMASTA_ENABLE (0x1 << 0 )
6180#define DMASTA_ENABLE_CLR (0x0 << 0 ) /* CLR */
6181#define DMASTA_ENABLE_SET (0x1 << 0 ) /* SET */
6182
6183/* Reset Value for DMACFG*/
6184#define DMACFG_RVAL 0x0
6185
6186/* DMACFG[ENABLE] - Master DMA controller enable */
6187#define DMACFG_ENABLE_BBA (*(volatile unsigned long *) 0x42200080)
6188#define DMACFG_ENABLE_MSK (0x1 << 0 )
6189#define DMACFG_ENABLE (0x1 << 0 )
6190#define DMACFG_ENABLE_DIS (0x0 << 0 ) /* DIS */
6191#define DMACFG_ENABLE_EN (0x1 << 0 ) /* EN */
6192
6193/* Reset Value for DMAPDBPTR*/
6194#define DMAPDBPTR_RVAL 0x0
6195
6196/* DMAPDBPTR[CTRLBASEPTR] - Pointer to the base address of the primary data structure */
6197#define DMAPDBPTR_CTRLBASEPTR_MSK (0xFFFFFFFF << 0 )
6198
6199/* Reset Value for DMAADBPTR*/
6200#define DMAADBPTR_RVAL 0x100
6201
6202/* DMAADBPTR[ALTCBPTR] - Pointer to the base address of the alternate data structure */
6203#define DMAADBPTR_ALTCBPTR_MSK (0xFFFFFFFF << 0 )
6204
6205/* Reset Value for DMASWREQ*/
6206#define DMASWREQ_RVAL 0x0
6207/* DMASWREQ[UART1RX] - DMA UART1 RX */
6208#define DMASWREQ_UART1RX_BBA (*(volatile unsigned long *) 0x422002BC)
6209#define DMASWREQ_UART1RX_MSK (0x1 << 15 )
6210#define DMASWREQ_UART1RX (0x1 << 15 )
6211#define DMASWREQ_UART1RX_DIS (0x0 << 15 ) /* DIS */
6212#define DMASWREQ_UART1RX_EN (0x1 << 15 ) /* EN */
6213/* DMASWREQ[UART1TX] - DMA UART1 TX */
6214#define DMASWREQ_UART1TX_BBA (*(volatile unsigned long *) 0x422002B8)
6215#define DMASWREQ_UART1TX_MSK (0x1 << 14 )
6216#define DMASWREQ_UART1TX (0x1 << 14 )
6217#define DMASWREQ_UART1TX_DIS (0x0 << 14 ) /* DIS */
6218#define DMASWREQ_UART1TX_EN (0x1 << 14 ) /* EN */
6219/* DMASWREQ[SPI0RX] - DMA SPI 0 RX */
6220#define DMASWREQ_SPI0RX_BBA (*(volatile unsigned long *) 0x422002B4)
6221#define DMASWREQ_SPI0RX_MSK (0x1 << 13 )
6222#define DMASWREQ_SPI0RX (0x1 << 13 )
6223#define DMASWREQ_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6224#define DMASWREQ_SPI0RX_EN (0x1 << 13 ) /* EN */
6225/* DMASWREQ[SPI0TX] - DMA SPI 0 TX */
6226#define DMASWREQ_SPI0TX_BBA (*(volatile unsigned long *) 0x422002B0)
6227#define DMASWREQ_SPI0TX_MSK (0x1 << 12 )
6228#define DMASWREQ_SPI0TX (0x1 << 12 )
6229#define DMASWREQ_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6230#define DMASWREQ_SPI0TX_EN (0x1 << 12 ) /* EN */
6231/* DMASWREQ[SINC2] - SINC2 Output Step detection */
6232#define DMASWREQ_SINC2_BBA (*(volatile unsigned long *) 0x422002AC)
6233#define DMASWREQ_SINC2_MSK (0x1 << 11 )
6234#define DMASWREQ_SINC2 (0x1 << 11 )
6235#define DMASWREQ_SINC2_DIS (0x0 << 11 ) /* DIS */
6236#define DMASWREQ_SINC2_EN (0x1 << 11 ) /* EN */
6237
6238/* DMASWREQ[ADC1] - ADC1 */
6239#define DMASWREQ_ADC1_BBA (*(volatile unsigned long *) 0x422002A8)
6240#define DMASWREQ_ADC1_MSK (0x1 << 10 )
6241#define DMASWREQ_ADC1 (0x1 << 10 )
6242#define DMASWREQ_ADC1_DIS (0x0 << 10 ) /* DIS */
6243#define DMASWREQ_ADC1_EN (0x1 << 10 ) /* EN */
6244
6245/* DMASWREQ[ADC0] - ADC0 */
6246#define DMASWREQ_ADC0_BBA (*(volatile unsigned long *) 0x422002A4)
6247#define DMASWREQ_ADC0_MSK (0x1 << 9 )
6248#define DMASWREQ_ADC0 (0x1 << 9 )
6249#define DMASWREQ_ADC0_DIS (0x0 << 9 ) /* DIS */
6250#define DMASWREQ_ADC0_EN (0x1 << 9 ) /* EN */
6251
6252/* DMASWREQ[DAC] - DAC DMA Output */
6253#define DMASWREQ_DAC_BBA (*(volatile unsigned long *) 0x422002A0)
6254#define DMASWREQ_DAC_MSK (0x1 << 8 )
6255#define DMASWREQ_DAC (0x1 << 8 )
6256#define DMASWREQ_DAC_DIS (0x0 << 8 ) /* DIS */
6257#define DMASWREQ_DAC_EN (0x1 << 8 ) /* EN */
6258
6259/* DMASWREQ[I2CMRX] - DMA I2C Master RX */
6260#define DMASWREQ_I2CMRX_BBA (*(volatile unsigned long *) 0x4220029C)
6261#define DMASWREQ_I2CMRX_MSK (0x1 << 7 )
6262#define DMASWREQ_I2CMRX (0x1 << 7 )
6263#define DMASWREQ_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6264#define DMASWREQ_I2CMRX_EN (0x1 << 7 ) /* EN */
6265
6266/* DMASWREQ[I2CMTX] - DMA I2C Master TX */
6267#define DMASWREQ_I2CMTX_BBA (*(volatile unsigned long *) 0x42200298)
6268#define DMASWREQ_I2CMTX_MSK (0x1 << 6 )
6269#define DMASWREQ_I2CMTX (0x1 << 6 )
6270#define DMASWREQ_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6271#define DMASWREQ_I2CMTX_EN (0x1 << 6 ) /* EN */
6272
6273/* DMASWREQ[I2CSRX] - DMA I2C Slave RX */
6274#define DMASWREQ_I2CSRX_BBA (*(volatile unsigned long *) 0x42200294)
6275#define DMASWREQ_I2CSRX_MSK (0x1 << 5 )
6276#define DMASWREQ_I2CSRX (0x1 << 5 )
6277#define DMASWREQ_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6278#define DMASWREQ_I2CSRX_EN (0x1 << 5 ) /* EN */
6279
6280/* DMASWREQ[I2CSTX] - DMA I2C Slave TX */
6281#define DMASWREQ_I2CSTX_BBA (*(volatile unsigned long *) 0x42200290)
6282#define DMASWREQ_I2CSTX_MSK (0x1 << 4 )
6283#define DMASWREQ_I2CSTX (0x1 << 4 )
6284#define DMASWREQ_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6285#define DMASWREQ_I2CSTX_EN (0x1 << 4 ) /* EN */
6286
6287/* DMASWREQ[UARTRX] - DMA UART RX */
6288#define DMASWREQ_UARTRX_BBA (*(volatile unsigned long *) 0x4220028C)
6289#define DMASWREQ_UARTRX_MSK (0x1 << 3 )
6290#define DMASWREQ_UARTRX (0x1 << 3 )
6291#define DMASWREQ_UARTRX_DIS (0x0 << 3 ) /* DIS */
6292#define DMASWREQ_UARTRX_EN (0x1 << 3 ) /* EN */
6293
6294/* DMASWREQ[UARTTX] - DMA UART TX */
6295#define DMASWREQ_UARTTX_BBA (*(volatile unsigned long *) 0x42200288)
6296#define DMASWREQ_UARTTX_MSK (0x1 << 2 )
6297#define DMASWREQ_UARTTX (0x1 << 2 )
6298#define DMASWREQ_UARTTX_DIS (0x0 << 2 ) /* DIS */
6299#define DMASWREQ_UARTTX_EN (0x1 << 2 ) /* EN */
6300
6301/* DMASWREQ[SPI1RX] - DMA SPI 1 RX */
6302#define DMASWREQ_SPI1RX_BBA (*(volatile unsigned long *) 0x42200284)
6303#define DMASWREQ_SPI1RX_MSK (0x1 << 1 )
6304#define DMASWREQ_SPI1RX (0x1 << 1 )
6305#define DMASWREQ_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6306#define DMASWREQ_SPI1RX_EN (0x1 << 1 ) /* EN */
6307
6308/* DMASWREQ[SPI1TX] - DMA SPI 1 TX */
6309#define DMASWREQ_SPI1TX_BBA (*(volatile unsigned long *) 0x42200280)
6310#define DMASWREQ_SPI1TX_MSK (0x1 << 0 )
6311#define DMASWREQ_SPI1TX (0x1 << 0 )
6312#define DMASWREQ_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6313#define DMASWREQ_SPI1TX_EN (0x1 << 0 ) /* EN */
6314
6315/* Reset Value for DMARMSKSET*/
6316#define DMARMSKSET_RVAL 0x0
6317/* DMARMSKSET[UART1RX] - DMA UART1 RX */
6318#define DMARMSKSET_UART1RX_BBA (*(volatile unsigned long *) 0x4220043C)
6319#define DMARMSKSET_UART1RX_MSK (0x1 << 15 )
6320#define DMARMSKSET_UART1RX (0x1 << 15 )
6321#define DMARMSKSET_UART1RX_DIS (0x0 << 15 ) /* DIS */
6322#define DMARMSKSET_UART1RX_EN (0x1 << 15 ) /* EN */
6323/* DMARMSKSET[UART1TX] - DMA UART1 TX */
6324#define DMARMSKSET_UART1TX_BBA (*(volatile unsigned long *) 0x42200438)
6325#define DMARMSKSET_UART1TX_MSK (0x1 << 14 )
6326#define DMARMSKSET_UART1TX (0x1 << 14 )
6327#define DMARMSKSET_UART1TX_DIS (0x0 << 14 ) /* DIS */
6328#define DMARMSKSET_UART1TX_EN (0x1 << 14 ) /* EN */
6329/* DMARMSKSET[SPI0RX] - DMA SPI 0 RX */
6330#define DMARMSKSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200434)
6331#define DMARMSKSET_SPI0RX_MSK (0x1 << 13 )
6332#define DMARMSKSET_SPI0RX (0x1 << 13 )
6333#define DMARMSKSET_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6334#define DMARMSKSET_SPI0RX_EN (0x1 << 13 ) /* EN */
6335/* DMARMSKSET[SPI0TX] - DMA SPI 0 TX */
6336#define DMARMSKSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200430)
6337#define DMARMSKSET_SPI0TX_MSK (0x1 << 12 )
6338#define DMARMSKSET_SPI0TX (0x1 << 12 )
6339#define DMARMSKSET_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6340#define DMARMSKSET_SPI0TX_EN (0x1 << 12 ) /* EN */
6341
6342/* DMARMSKSET[SINC2] - SINC2 Output Step detection */
6343#define DMARMSKSET_SINC2_BBA (*(volatile unsigned long *) 0x4220042C)
6344#define DMARMSKSET_SINC2_MSK (0x1 << 11 )
6345#define DMARMSKSET_SINC2 (0x1 << 11 )
6346#define DMARMSKSET_SINC2_DIS (0x0 << 11 ) /* DIS */
6347#define DMARMSKSET_SINC2_EN (0x1 << 11 ) /* EN */
6348
6349/* DMARMSKSET[ADC1] - ADC1 */
6350#define DMARMSKSET_ADC1_BBA (*(volatile unsigned long *) 0x42200428)
6351#define DMARMSKSET_ADC1_MSK (0x1 << 10 )
6352#define DMARMSKSET_ADC1 (0x1 << 10 )
6353#define DMARMSKSET_ADC1_DIS (0x0 << 10 ) /* DIS */
6354#define DMARMSKSET_ADC1_EN (0x1 << 10 ) /* EN */
6355
6356/* DMARMSKSET[ADC0] - ADC0 */
6357#define DMARMSKSET_ADC0_BBA (*(volatile unsigned long *) 0x42200424)
6358#define DMARMSKSET_ADC0_MSK (0x1 << 9 )
6359#define DMARMSKSET_ADC0 (0x1 << 9 )
6360#define DMARMSKSET_ADC0_DIS (0x0 << 9 ) /* DIS */
6361#define DMARMSKSET_ADC0_EN (0x1 << 9 ) /* EN */
6362
6363/* DMARMSKSET[DAC] - DAC DMA Output */
6364#define DMARMSKSET_DAC_BBA (*(volatile unsigned long *) 0x42200420)
6365#define DMARMSKSET_DAC_MSK (0x1 << 8 )
6366#define DMARMSKSET_DAC (0x1 << 8 )
6367#define DMARMSKSET_DAC_DIS (0x0 << 8 ) /* DIS */
6368#define DMARMSKSET_DAC_EN (0x1 << 8 ) /* EN */
6369
6370/* DMARMSKSET[I2CMRX] - DMA I2C Master RX */
6371#define DMARMSKSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220041C)
6372#define DMARMSKSET_I2CMRX_MSK (0x1 << 7 )
6373#define DMARMSKSET_I2CMRX (0x1 << 7 )
6374#define DMARMSKSET_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6375#define DMARMSKSET_I2CMRX_EN (0x1 << 7 ) /* EN */
6376
6377/* DMARMSKSET[I2CMTX] - DMA I2C Master TX */
6378#define DMARMSKSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200418)
6379#define DMARMSKSET_I2CMTX_MSK (0x1 << 6 )
6380#define DMARMSKSET_I2CMTX (0x1 << 6 )
6381#define DMARMSKSET_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6382#define DMARMSKSET_I2CMTX_EN (0x1 << 6 ) /* EN */
6383
6384/* DMARMSKSET[I2CSRX] - DMA I2C Slave RX */
6385#define DMARMSKSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200414)
6386#define DMARMSKSET_I2CSRX_MSK (0x1 << 5 )
6387#define DMARMSKSET_I2CSRX (0x1 << 5 )
6388#define DMARMSKSET_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6389#define DMARMSKSET_I2CSRX_EN (0x1 << 5 ) /* EN */
6390
6391/* DMARMSKSET[I2CSTX] - DMA I2C Slave TX */
6392#define DMARMSKSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200410)
6393#define DMARMSKSET_I2CSTX_MSK (0x1 << 4 )
6394#define DMARMSKSET_I2CSTX (0x1 << 4 )
6395#define DMARMSKSET_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6396#define DMARMSKSET_I2CSTX_EN (0x1 << 4 ) /* EN */
6397
6398/* DMARMSKSET[UARTRX] - DMA UART RX */
6399#define DMARMSKSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220040C)
6400#define DMARMSKSET_UARTRX_MSK (0x1 << 3 )
6401#define DMARMSKSET_UARTRX (0x1 << 3 )
6402#define DMARMSKSET_UARTRX_DIS (0x0 << 3 ) /* DIS */
6403#define DMARMSKSET_UARTRX_EN (0x1 << 3 ) /* EN */
6404
6405/* DMARMSKSET[UARTTX] - DMA UART TX */
6406#define DMARMSKSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200408)
6407#define DMARMSKSET_UARTTX_MSK (0x1 << 2 )
6408#define DMARMSKSET_UARTTX (0x1 << 2 )
6409#define DMARMSKSET_UARTTX_DIS (0x0 << 2 ) /* DIS */
6410#define DMARMSKSET_UARTTX_EN (0x1 << 2 ) /* EN */
6411
6412/* DMARMSKSET[SPI1RX] - DMA SPI 1 RX */
6413#define DMARMSKSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200404)
6414#define DMARMSKSET_SPI1RX_MSK (0x1 << 1 )
6415#define DMARMSKSET_SPI1RX (0x1 << 1 )
6416#define DMARMSKSET_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6417#define DMARMSKSET_SPI1RX_EN (0x1 << 1 ) /* EN */
6418
6419/* DMARMSKSET[SPI1TX] - DMA SPI 1 TX */
6420#define DMARMSKSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200400)
6421#define DMARMSKSET_SPI1TX_MSK (0x1 << 0 )
6422#define DMARMSKSET_SPI1TX (0x1 << 0 )
6423#define DMARMSKSET_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6424#define DMARMSKSET_SPI1TX_EN (0x1 << 0 ) /* EN */
6425
6426/* Reset Value for DMARMSKCLR*/
6427#define DMARMSKCLR_RVAL 0x0
6428
6429/* DMARMSKCLR[UART1RX] - DMA UART1 RX */
6430#define DMARMSKCLR_UART1RX_BBA (*(volatile unsigned long *) 0x422004BC)
6431#define DMARMSKCLR_UART1RX_MSK (0x1 << 15 )
6432#define DMARMSKCLR_UART1RX (0x1 << 15 )
6433#define DMARMSKCLR_UART1RX_DIS (0x0 << 15 ) /* DIS */
6434#define DMARMSKCLR_UART1RX_EN (0x1 << 15 ) /* EN */
6435/* DMARMSKCLR[UART1TX] - DMA UART1 TX */
6436#define DMARMSKCLR_UART1TX_BBA (*(volatile unsigned long *) 0x422004B8)
6437#define DMARMSKCLR_UART1TX_MSK (0x1 << 14 )
6438#define DMARMSKCLR_UART1TX (0x1 << 14 )
6439#define DMARMSKCLR_UART1TX_DIS (0x0 << 14 ) /* DIS */
6440#define DMARMSKCLR_UART1TX_EN (0x1 << 14 ) /* EN */
6441/* DMARMSKCLR[SPI0RX] - DMA SPI 0 RX */
6442#define DMARMSKCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422004B4)
6443#define DMARMSKCLR_SPI0RX_MSK (0x1 << 13 )
6444#define DMARMSKCLR_SPI0RX (0x1 << 13 )
6445#define DMARMSKCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6446#define DMARMSKCLR_SPI0RX_EN (0x1 << 13 ) /* EN */
6447/* DMARMSKCLR[SPI0TX] - DMA SPI 0 TX */
6448#define DMARMSKCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422004B0)
6449#define DMARMSKCLR_SPI0TX_MSK (0x1 << 12 )
6450#define DMARMSKCLR_SPI0TX (0x1 << 12 )
6451#define DMARMSKCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6452#define DMARMSKCLR_SPI0TX_EN (0x1 << 12 ) /* EN */
6453/* DMARMSKCLR[SINC2] - SINC2 Output Step detection */
6454#define DMARMSKCLR_SINC2_BBA (*(volatile unsigned long *) 0x422004AC)
6455#define DMARMSKCLR_SINC2_MSK (0x1 << 11 )
6456#define DMARMSKCLR_SINC2 (0x1 << 11 )
6457#define DMARMSKCLR_SINC2_DIS (0x0 << 11 ) /* DIS */
6458#define DMARMSKCLR_SINC2_EN (0x1 << 11 ) /* EN */
6459
6460/* DMARMSKCLR[ADC1] - ADC1 */
6461#define DMARMSKCLR_ADC1_BBA (*(volatile unsigned long *) 0x422004A8)
6462#define DMARMSKCLR_ADC1_MSK (0x1 << 10 )
6463#define DMARMSKCLR_ADC1 (0x1 << 10 )
6464#define DMARMSKCLR_ADC1_DIS (0x0 << 10 ) /* DIS */
6465#define DMARMSKCLR_ADC1_EN (0x1 << 10 ) /* EN */
6466
6467/* DMARMSKCLR[ADC0] - ADC0 */
6468#define DMARMSKCLR_ADC0_BBA (*(volatile unsigned long *) 0x422004A4)
6469#define DMARMSKCLR_ADC0_MSK (0x1 << 9 )
6470#define DMARMSKCLR_ADC0 (0x1 << 9 )
6471#define DMARMSKCLR_ADC0_DIS (0x0 << 9 ) /* DIS */
6472#define DMARMSKCLR_ADC0_EN (0x1 << 9 ) /* EN */
6473
6474/* DMARMSKCLR[DAC] - DAC DMA Output */
6475#define DMARMSKCLR_DAC_BBA (*(volatile unsigned long *) 0x422004A0)
6476#define DMARMSKCLR_DAC_MSK (0x1 << 8 )
6477#define DMARMSKCLR_DAC (0x1 << 8 )
6478#define DMARMSKCLR_DAC_DIS (0x0 << 8 ) /* DIS */
6479#define DMARMSKCLR_DAC_EN (0x1 << 8 ) /* EN */
6480
6481/* DMARMSKCLR[I2CMRX] - DMA I2C Master RX */
6482#define DMARMSKCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220049C)
6483#define DMARMSKCLR_I2CMRX_MSK (0x1 << 7 )
6484#define DMARMSKCLR_I2CMRX (0x1 << 7 )
6485#define DMARMSKCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6486#define DMARMSKCLR_I2CMRX_EN (0x1 << 7 ) /* EN */
6487
6488/* DMARMSKCLR[I2CMTX] - DMA I2C Master TX */
6489#define DMARMSKCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200498)
6490#define DMARMSKCLR_I2CMTX_MSK (0x1 << 6 )
6491#define DMARMSKCLR_I2CMTX (0x1 << 6 )
6492#define DMARMSKCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6493#define DMARMSKCLR_I2CMTX_EN (0x1 << 6 ) /* EN */
6494
6495/* DMARMSKCLR[I2CSRX] - DMA I2C Slave RX */
6496#define DMARMSKCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200494)
6497#define DMARMSKCLR_I2CSRX_MSK (0x1 << 5 )
6498#define DMARMSKCLR_I2CSRX (0x1 << 5 )
6499#define DMARMSKCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6500#define DMARMSKCLR_I2CSRX_EN (0x1 << 5 ) /* EN */
6501
6502/* DMARMSKCLR[I2CSTX] - DMA I2C Slave TX */
6503#define DMARMSKCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200490)
6504#define DMARMSKCLR_I2CSTX_MSK (0x1 << 4 )
6505#define DMARMSKCLR_I2CSTX (0x1 << 4 )
6506#define DMARMSKCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6507#define DMARMSKCLR_I2CSTX_EN (0x1 << 4 ) /* EN */
6508
6509/* DMARMSKCLR[UARTRX] - DMA UART RX */
6510#define DMARMSKCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220048C)
6511#define DMARMSKCLR_UARTRX_MSK (0x1 << 3 )
6512#define DMARMSKCLR_UARTRX (0x1 << 3 )
6513#define DMARMSKCLR_UARTRX_DIS (0x0 << 3 ) /* DIS */
6514#define DMARMSKCLR_UARTRX_EN (0x1 << 3 ) /* EN */
6515
6516/* DMARMSKCLR[UARTTX] - DMA UART TX */
6517#define DMARMSKCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200488)
6518#define DMARMSKCLR_UARTTX_MSK (0x1 << 2 )
6519#define DMARMSKCLR_UARTTX (0x1 << 2 )
6520#define DMARMSKCLR_UARTTX_DIS (0x0 << 2 ) /* DIS */
6521#define DMARMSKCLR_UARTTX_EN (0x1 << 2 ) /* EN */
6522
6523/* DMARMSKCLR[SPI1RX] - DMA SPI 1 RX */
6524#define DMARMSKCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200484)
6525#define DMARMSKCLR_SPI1RX_MSK (0x1 << 1 )
6526#define DMARMSKCLR_SPI1RX (0x1 << 1 )
6527#define DMARMSKCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6528#define DMARMSKCLR_SPI1RX_EN (0x1 << 1 ) /* EN */
6529
6530/* DMARMSKCLR[SPI1TX] - DMA SPI 1 TX */
6531#define DMARMSKCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200480)
6532#define DMARMSKCLR_SPI1TX_MSK (0x1 << 0 )
6533#define DMARMSKCLR_SPI1TX (0x1 << 0 )
6534#define DMARMSKCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6535#define DMARMSKCLR_SPI1TX_EN (0x1 << 0 ) /* EN */
6536
6537/* Reset Value for DMAENSET*/
6538#define DMAENSET_RVAL 0x0
6539
6540
6541/* DMAENSET[UART1RX] - DMA UART1 RX */
6542#define DMAENSET_UART1RX_BBA (*(volatile unsigned long *) 0x4220053C)
6543#define DMAENSET_UART1RX_MSK (0x1 << 15 )
6544#define DMAENSET_UART1RX (0x1 << 15 )
6545#define DMAENSET_UART1RX_DIS (0x0 << 15 ) /* DIS */
6546#define DMAENSET_UART1RX_EN (0x1 << 15 ) /* EN */
6547/* DMAENSET[UART1TX] - DMA UART1 TX */
6548#define DMAENSET_UART1TX_BBA (*(volatile unsigned long *) 0x42200538)
6549#define DMAENSET_UART1TX_MSK (0x1 << 14 )
6550#define DMAENSET_UART1TX (0x1 << 14 )
6551#define DMAENSET_UART1TX_DIS (0x0 << 14 ) /* DIS */
6552#define DMAENSET_UART1TX_EN (0x1 << 14 ) /* EN */
6553/* DMAENSET[SPI0RX] - DMA SPI 0 RX */
6554#define DMAENSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200534)
6555#define DMAENSET_SPI0RX_MSK (0x1 << 13 )
6556#define DMAENSET_SPI0RX (0x1 << 13 )
6557#define DMAENSET_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6558#define DMAENSET_SPI0RX_EN (0x1 << 13 ) /* EN */
6559/* DMAENSET[SPI0TX] - DMA SPI 0 TX */
6560#define DMAENSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200530)
6561#define DMAENSET_SPI0TX_MSK (0x1 << 12 )
6562#define DMAENSET_SPI0TX (0x1 << 12 )
6563#define DMAENSET_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6564#define DMAENSET_SPI0TX_EN (0x1 << 12 ) /* EN */
6565
6566/* DMAENSET[SINC2] - SINC2 Output Step detection */
6567#define DMAENSET_SINC2_BBA (*(volatile unsigned long *) 0x4220052C)
6568#define DMAENSET_SINC2_MSK (0x1 << 11 )
6569#define DMAENSET_SINC2 (0x1 << 11 )
6570#define DMAENSET_SINC2_DIS (0x0 << 11 ) /* DIS */
6571#define DMAENSET_SINC2_EN (0x1 << 11 ) /* EN */
6572
6573/* DMAENSET[ADC1] - ADC1 */
6574#define DMAENSET_ADC1_BBA (*(volatile unsigned long *) 0x42200528)
6575#define DMAENSET_ADC1_MSK (0x1 << 10 )
6576#define DMAENSET_ADC1 (0x1 << 10 )
6577#define DMAENSET_ADC1_DIS (0x0 << 10 ) /* DIS */
6578#define DMAENSET_ADC1_EN (0x1 << 10 ) /* EN */
6579
6580/* DMAENSET[ADC0] - ADC0 */
6581#define DMAENSET_ADC0_BBA (*(volatile unsigned long *) 0x42200524)
6582#define DMAENSET_ADC0_MSK (0x1 << 9 )
6583#define DMAENSET_ADC0 (0x1 << 9 )
6584#define DMAENSET_ADC0_DIS (0x0 << 9 ) /* DIS */
6585#define DMAENSET_ADC0_EN (0x1 << 9 ) /* EN */
6586
6587/* DMAENSET[DAC] - DAC DMA Output */
6588#define DMAENSET_DAC_BBA (*(volatile unsigned long *) 0x42200520)
6589#define DMAENSET_DAC_MSK (0x1 << 8 )
6590#define DMAENSET_DAC (0x1 << 8 )
6591#define DMAENSET_DAC_DIS (0x0 << 8 ) /* DIS */
6592#define DMAENSET_DAC_EN (0x1 << 8 ) /* EN */
6593
6594/* DMAENSET[I2CMRX] - DMA I2C Master RX */
6595#define DMAENSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220051C)
6596#define DMAENSET_I2CMRX_MSK (0x1 << 7 )
6597#define DMAENSET_I2CMRX (0x1 << 7 )
6598#define DMAENSET_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6599#define DMAENSET_I2CMRX_EN (0x1 << 7 ) /* EN */
6600
6601/* DMAENSET[I2CMTX] - DMA I2C Master TX */
6602#define DMAENSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200518)
6603#define DMAENSET_I2CMTX_MSK (0x1 << 6 )
6604#define DMAENSET_I2CMTX (0x1 << 6 )
6605#define DMAENSET_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6606#define DMAENSET_I2CMTX_EN (0x1 << 6 ) /* EN */
6607
6608/* DMAENSET[I2CSRX] - DMA I2C Slave RX */
6609#define DMAENSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200514)
6610#define DMAENSET_I2CSRX_MSK (0x1 << 5 )
6611#define DMAENSET_I2CSRX (0x1 << 5 )
6612#define DMAENSET_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6613#define DMAENSET_I2CSRX_EN (0x1 << 5 ) /* EN */
6614
6615/* DMAENSET[I2CSTX] - DMA I2C Slave TX */
6616#define DMAENSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200510)
6617#define DMAENSET_I2CSTX_MSK (0x1 << 4 )
6618#define DMAENSET_I2CSTX (0x1 << 4 )
6619#define DMAENSET_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6620#define DMAENSET_I2CSTX_EN (0x1 << 4 ) /* EN */
6621
6622/* DMAENSET[UARTRX] - DMA UART RX */
6623#define DMAENSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220050C)
6624#define DMAENSET_UARTRX_MSK (0x1 << 3 )
6625#define DMAENSET_UARTRX (0x1 << 3 )
6626#define DMAENSET_UARTRX_DIS (0x0 << 3 ) /* DIS */
6627#define DMAENSET_UARTRX_EN (0x1 << 3 ) /* EN */
6628
6629/* DMAENSET[UARTTX] - DMA UART TX */
6630#define DMAENSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200508)
6631#define DMAENSET_UARTTX_MSK (0x1 << 2 )
6632#define DMAENSET_UARTTX (0x1 << 2 )
6633#define DMAENSET_UARTTX_DIS (0x0 << 2 ) /* DIS */
6634#define DMAENSET_UARTTX_EN (0x1 << 2 ) /* EN */
6635
6636/* DMAENSET[SPI1RX] - DMA SPI 1 RX */
6637#define DMAENSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200504)
6638#define DMAENSET_SPI1RX_MSK (0x1 << 1 )
6639#define DMAENSET_SPI1RX (0x1 << 1 )
6640#define DMAENSET_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6641#define DMAENSET_SPI1RX_EN (0x1 << 1 ) /* EN */
6642
6643/* DMAENSET[SPI1TX] - DMA SPI 1 TX */
6644#define DMAENSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200500)
6645#define DMAENSET_SPI1TX_MSK (0x1 << 0 )
6646#define DMAENSET_SPI1TX (0x1 << 0 )
6647#define DMAENSET_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6648#define DMAENSET_SPI1TX_EN (0x1 << 0 ) /* EN */
6649
6650/* Reset Value for DMAENCLR*/
6651#define DMAENCLR_RVAL 0x0
6652
6653/* DMAENCLR[UART1RX] - DMA UART1 RX */
6654#define DMAENCLR_UART1RX_BBA (*(volatile unsigned long *) 0x422005BC)
6655#define DMAENCLR_UART1RX_MSK (0x1 << 15 )
6656#define DMAENCLR_UART1RX (0x1 << 15 )
6657#define DMAENCLR_UART1RX_DIS (0x0 << 15 ) /* DIS */
6658#define DMAENCLR_UART1RX_EN (0x1 << 15 ) /* EN */
6659/* DMAENCLR[UART1TX] - DMA UART1 TX */
6660#define DMAENCLR_UART1TX_BBA (*(volatile unsigned long *) 0x422005B8)
6661#define DMAENCLR_UART1TX_MSK (0x1 << 14 )
6662#define DMAENCLR_UART1TX (0x1 << 14 )
6663#define DMAENCLR_UART1TX_DIS (0x0 << 14 ) /* DIS */
6664#define DMAENCLR_UART1TX_EN (0x1 << 14 ) /* EN */
6665/* DMAENCLR[SPI0RX] - DMA SPI 0 RX */
6666#define DMAENCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422005B4)
6667#define DMAENCLR_SPI0RX_MSK (0x1 << 13 )
6668#define DMAENCLR_SPI0RX (0x1 << 13 )
6669#define DMAENCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6670#define DMAENCLR_SPI0RX_EN (0x1 << 13 ) /* EN */
6671/* DMAENCLR[SPI0TX] - DMA SPI 0 TX */
6672#define DMAENCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422005B0)
6673#define DMAENCLR_SPI0TX_MSK (0x1 << 12 )
6674#define DMAENCLR_SPI0TX (0x1 << 12 )
6675#define DMAENCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6676#define DMAENCLR_SPI0TX_EN (0x1 << 12 ) /* EN */
6677
6678
6679/* DMAENCLR[SINC2] - SINC2 Output Step detection */
6680#define DMAENCLR_SINC2_BBA (*(volatile unsigned long *) 0x422005AC)
6681#define DMAENCLR_SINC2_MSK (0x1 << 11 )
6682#define DMAENCLR_SINC2 (0x1 << 11 )
6683#define DMAENCLR_SINC2_DIS (0x0 << 11 ) /* DIS */
6684#define DMAENCLR_SINC2_EN (0x1 << 11 ) /* EN */
6685
6686/* DMAENCLR[ADC1] - ADC1 */
6687#define DMAENCLR_ADC1_BBA (*(volatile unsigned long *) 0x422005A8)
6688#define DMAENCLR_ADC1_MSK (0x1 << 10 )
6689#define DMAENCLR_ADC1 (0x1 << 10 )
6690#define DMAENCLR_ADC1_DIS (0x0 << 10 ) /* DIS */
6691#define DMAENCLR_ADC1_EN (0x1 << 10 ) /* EN */
6692
6693/* DMAENCLR[ADC0] - ADC0 */
6694#define DMAENCLR_ADC0_BBA (*(volatile unsigned long *) 0x422005A4)
6695#define DMAENCLR_ADC0_MSK (0x1 << 9 )
6696#define DMAENCLR_ADC0 (0x1 << 9 )
6697#define DMAENCLR_ADC0_DIS (0x0 << 9 ) /* DIS */
6698#define DMAENCLR_ADC0_EN (0x1 << 9 ) /* EN */
6699
6700/* DMAENCLR[DAC] - DAC DMA Output */
6701#define DMAENCLR_DAC_BBA (*(volatile unsigned long *) 0x422005A0)
6702#define DMAENCLR_DAC_MSK (0x1 << 8 )
6703#define DMAENCLR_DAC (0x1 << 8 )
6704#define DMAENCLR_DAC_DIS (0x0 << 8 ) /* DIS */
6705#define DMAENCLR_DAC_EN (0x1 << 8 ) /* EN */
6706
6707/* DMAENCLR[I2CMRX] - DMA I2C Master RX */
6708#define DMAENCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220059C)
6709#define DMAENCLR_I2CMRX_MSK (0x1 << 7 )
6710#define DMAENCLR_I2CMRX (0x1 << 7 )
6711#define DMAENCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6712#define DMAENCLR_I2CMRX_EN (0x1 << 7 ) /* EN */
6713
6714/* DMAENCLR[I2CMTX] - DMA I2C Master TX */
6715#define DMAENCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200598)
6716#define DMAENCLR_I2CMTX_MSK (0x1 << 6 )
6717#define DMAENCLR_I2CMTX (0x1 << 6 )
6718#define DMAENCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6719#define DMAENCLR_I2CMTX_EN (0x1 << 6 ) /* EN */
6720
6721/* DMAENCLR[I2CSRX] - DMA I2C Slave RX */
6722#define DMAENCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200594)
6723#define DMAENCLR_I2CSRX_MSK (0x1 << 5 )
6724#define DMAENCLR_I2CSRX (0x1 << 5 )
6725#define DMAENCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6726#define DMAENCLR_I2CSRX_EN (0x1 << 5 ) /* EN */
6727
6728/* DMAENCLR[I2CSTX] - DMA I2C Slave TX */
6729#define DMAENCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200590)
6730#define DMAENCLR_I2CSTX_MSK (0x1 << 4 )
6731#define DMAENCLR_I2CSTX (0x1 << 4 )
6732#define DMAENCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6733#define DMAENCLR_I2CSTX_EN (0x1 << 4 ) /* EN */
6734
6735/* DMAENCLR[UARTRX] - DMA UART RX */
6736#define DMAENCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220058C)
6737#define DMAENCLR_UARTRX_MSK (0x1 << 3 )
6738#define DMAENCLR_UARTRX (0x1 << 3 )
6739#define DMAENCLR_UARTRX_DIS (0x0 << 3 ) /* DIS */
6740#define DMAENCLR_UARTRX_EN (0x1 << 3 ) /* EN */
6741
6742/* DMAENCLR[UARTTX] - DMA UART TX */
6743#define DMAENCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200588)
6744#define DMAENCLR_UARTTX_MSK (0x1 << 2 )
6745#define DMAENCLR_UARTTX (0x1 << 2 )
6746#define DMAENCLR_UARTTX_DIS (0x0 << 2 ) /* DIS */
6747#define DMAENCLR_UARTTX_EN (0x1 << 2 ) /* EN */
6748
6749/* DMAENCLR[SPI1RX] - DMA SPI 1 RX */
6750#define DMAENCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200584)
6751#define DMAENCLR_SPI1RX_MSK (0x1 << 1 )
6752#define DMAENCLR_SPI1RX (0x1 << 1 )
6753#define DMAENCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6754#define DMAENCLR_SPI1RX_EN (0x1 << 1 ) /* EN */
6755
6756/* DMAENCLR[SPI1TX] - DMA SPI 1 TX */
6757#define DMAENCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200580)
6758#define DMAENCLR_SPI1TX_MSK (0x1 << 0 )
6759#define DMAENCLR_SPI1TX (0x1 << 0 )
6760#define DMAENCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6761#define DMAENCLR_SPI1TX_EN (0x1 << 0 ) /* EN */
6762
6763/* Reset Value for DMAALTSET*/
6764#define DMAALTSET_RVAL 0x0
6765
6766/* DMAALTSET[UART1RX] - DMA UART1 RX */
6767#define DMAALTSET_UART1RX_BBA (*(volatile unsigned long *) 0x4220063C)
6768#define DMAALTSET_UART1RX_MSK (0x1 << 15 )
6769#define DMAALTSET_UART1RX (0x1 << 15 )
6770#define DMAALTSET_UART1RX_DIS (0x0 << 15 ) /* DIS */
6771#define DMAALTSET_UART1RX_EN (0x1 << 15 ) /* EN */
6772/* DMAALTSET[UART1TX] - DMA UART1 TX */
6773#define DMAALTSET_UART1TX_BBA (*(volatile unsigned long *) 0x42200638)
6774#define DMAALTSET_UART1TX_MSK (0x1 << 14 )
6775#define DMAALTSET_UART1TX (0x1 << 14 )
6776#define DMAALTSET_UART1TX_DIS (0x0 << 14 ) /* DIS */
6777#define DMAALTSET_UART1TX_EN (0x1 << 14 ) /* EN */
6778/* DMAALTSET[SPI0RX] - DMA SPI 0 RX */
6779#define DMAALTSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200634)
6780#define DMAALTSET_SPI0RX_MSK (0x1 << 13 )
6781#define DMAALTSET_SPI0RX (0x1 << 13 )
6782#define DMAALTSET_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6783#define DMAALTSET_SPI0RX_EN (0x1 << 13 ) /* EN */
6784/* DMAALTSET[SPI0TX] - DMA SPI 0 TX */
6785#define DMAALTSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200630)
6786#define DMAALTSET_SPI0TX_MSK (0x1 << 12 )
6787#define DMAALTSET_SPI0TX (0x1 << 12 )
6788#define DMAALTSET_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6789#define DMAALTSET_SPI0TX_EN (0x1 << 12 ) /* EN */
6790
6791/* DMAALTSET[SINC2] - SINC2 Output Step detection */
6792#define DMAALTSET_SINC2_BBA (*(volatile unsigned long *) 0x4220062C)
6793#define DMAALTSET_SINC2_MSK (0x1 << 11 )
6794#define DMAALTSET_SINC2 (0x1 << 11 )
6795#define DMAALTSET_SINC2_DIS (0x0 << 11 ) /* DIS */
6796#define DMAALTSET_SINC2_EN (0x1 << 11 ) /* EN */
6797
6798/* DMAALTSET[ADC1] - ADC1 */
6799#define DMAALTSET_ADC1_BBA (*(volatile unsigned long *) 0x42200628)
6800#define DMAALTSET_ADC1_MSK (0x1 << 10 )
6801#define DMAALTSET_ADC1 (0x1 << 10 )
6802#define DMAALTSET_ADC1_DIS (0x0 << 10 ) /* DIS */
6803#define DMAALTSET_ADC1_EN (0x1 << 10 ) /* EN */
6804
6805/* DMAALTSET[ADC0] - ADC0 */
6806#define DMAALTSET_ADC0_BBA (*(volatile unsigned long *) 0x42200624)
6807#define DMAALTSET_ADC0_MSK (0x1 << 9 )
6808#define DMAALTSET_ADC0 (0x1 << 9 )
6809#define DMAALTSET_ADC0_DIS (0x0 << 9 ) /* DIS */
6810#define DMAALTSET_ADC0_EN (0x1 << 9 ) /* EN */
6811
6812/* DMAALTSET[DAC] - DAC DMA Output */
6813#define DMAALTSET_DAC_BBA (*(volatile unsigned long *) 0x42200620)
6814#define DMAALTSET_DAC_MSK (0x1 << 8 )
6815#define DMAALTSET_DAC (0x1 << 8 )
6816#define DMAALTSET_DAC_DIS (0x0 << 8 ) /* DIS */
6817#define DMAALTSET_DAC_EN (0x1 << 8 ) /* EN */
6818
6819/* DMAALTSET[I2CMRX] - DMA I2C Master RX */
6820#define DMAALTSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220061C)
6821#define DMAALTSET_I2CMRX_MSK (0x1 << 7 )
6822#define DMAALTSET_I2CMRX (0x1 << 7 )
6823#define DMAALTSET_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6824#define DMAALTSET_I2CMRX_EN (0x1 << 7 ) /* EN */
6825
6826/* DMAALTSET[I2CMTX] - DMA I2C Master TX */
6827#define DMAALTSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200618)
6828#define DMAALTSET_I2CMTX_MSK (0x1 << 6 )
6829#define DMAALTSET_I2CMTX (0x1 << 6 )
6830#define DMAALTSET_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6831#define DMAALTSET_I2CMTX_EN (0x1 << 6 ) /* EN */
6832
6833/* DMAALTSET[I2CSRX] - DMA I2C Slave RX */
6834#define DMAALTSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200614)
6835#define DMAALTSET_I2CSRX_MSK (0x1 << 5 )
6836#define DMAALTSET_I2CSRX (0x1 << 5 )
6837#define DMAALTSET_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6838#define DMAALTSET_I2CSRX_EN (0x1 << 5 ) /* EN */
6839
6840/* DMAALTSET[I2CSTX] - DMA I2C Slave TX */
6841#define DMAALTSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200610)
6842#define DMAALTSET_I2CSTX_MSK (0x1 << 4 )
6843#define DMAALTSET_I2CSTX (0x1 << 4 )
6844#define DMAALTSET_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6845#define DMAALTSET_I2CSTX_EN (0x1 << 4 ) /* EN */
6846
6847/* DMAALTSET[UARTRX] - DMA UART RX */
6848#define DMAALTSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220060C)
6849#define DMAALTSET_UARTRX_MSK (0x1 << 3 )
6850#define DMAALTSET_UARTRX (0x1 << 3 )
6851#define DMAALTSET_UARTRX_DIS (0x0 << 3 ) /* DIS */
6852#define DMAALTSET_UARTRX_EN (0x1 << 3 ) /* EN */
6853
6854/* DMAALTSET[UARTTX] - DMA UART TX */
6855#define DMAALTSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200608)
6856#define DMAALTSET_UARTTX_MSK (0x1 << 2 )
6857#define DMAALTSET_UARTTX (0x1 << 2 )
6858#define DMAALTSET_UARTTX_DIS (0x0 << 2 ) /* DIS */
6859#define DMAALTSET_UARTTX_EN (0x1 << 2 ) /* EN */
6860
6861/* DMAALTSET[SPI1RX] - DMA SPI 1 RX */
6862#define DMAALTSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200604)
6863#define DMAALTSET_SPI1RX_MSK (0x1 << 1 )
6864#define DMAALTSET_SPI1RX (0x1 << 1 )
6865#define DMAALTSET_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6866#define DMAALTSET_SPI1RX_EN (0x1 << 1 ) /* EN */
6867
6868/* DMAALTSET[SPI1TX] - DMA SPI 1 TX */
6869#define DMAALTSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200600)
6870#define DMAALTSET_SPI1TX_MSK (0x1 << 0 )
6871#define DMAALTSET_SPI1TX (0x1 << 0 )
6872#define DMAALTSET_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6873#define DMAALTSET_SPI1TX_EN (0x1 << 0 ) /* EN */
6874
6875/* Reset Value for DMAALTCLR*/
6876#define DMAALTCLR_RVAL 0x0
6877
6878/* DMAALTCLR[UART1RX] - DMA UART1 RX */
6879#define DMAALTCLR_UART1RX_BBA (*(volatile unsigned long *) 0x422006BC)
6880#define DMAALTCLR_UART1RX_MSK (0x1 << 15 )
6881#define DMAALTCLR_UART1RX (0x1 << 15 )
6882#define DMAALTCLR_UART1RX_DIS (0x0 << 15 ) /* DIS */
6883#define DMAALTCLR_UART1RX_EN (0x1 << 15 ) /* EN */
6884/* DMAALTCLR[UART1TX] - DMA UART1 TX */
6885#define DMAALTCLR_UART1TX_BBA (*(volatile unsigned long *) 0x422006B8)
6886#define DMAALTCLR_UART1TX_MSK (0x1 << 14 )
6887#define DMAALTCLR_UART1TX (0x1 << 14 )
6888#define DMAALTCLR_UART1TX_DIS (0x0 << 14 ) /* DIS */
6889#define DMAALTCLR_UART1TX_EN (0x1 << 14 ) /* EN */
6890/* DMAALTCLR[SPI0RX] - DMA SPI 0 RX */
6891#define DMAALTCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422006B4)
6892#define DMAALTCLR_SPI0RX_MSK (0x1 << 13 )
6893#define DMAALTCLR_SPI0RX (0x1 << 13 )
6894#define DMAALTCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6895#define DMAALTCLR_SPI0RX_EN (0x1 << 13 ) /* EN */
6896/* DMAALTCLR[SPI0TX] - DMA SPI 0 TX */
6897#define DMAALTCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422006B0)
6898#define DMAALTCLR_SPI0TX_MSK (0x1 << 12 )
6899#define DMAALTCLR_SPI0TX (0x1 << 12 )
6900#define DMAALTCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6901#define DMAALTCLR_SPI0TX_EN (0x1 << 12 ) /* EN */
6902
6903
6904/* DMAALTCLR[SINC2] - SINC2 Output Step detection */
6905#define DMAALTCLR_SINC2_BBA (*(volatile unsigned long *) 0x422006AC)
6906#define DMAALTCLR_SINC2_MSK (0x1 << 11 )
6907#define DMAALTCLR_SINC2 (0x1 << 11 )
6908#define DMAALTCLR_SINC2_DIS (0x0 << 11 ) /* DIS */
6909#define DMAALTCLR_SINC2_EN (0x1 << 11 ) /* EN */
6910
6911/* DMAALTCLR[ADC1] - ADC1 */
6912#define DMAALTCLR_ADC1_BBA (*(volatile unsigned long *) 0x422006A8)
6913#define DMAALTCLR_ADC1_MSK (0x1 << 10 )
6914#define DMAALTCLR_ADC1 (0x1 << 10 )
6915#define DMAALTCLR_ADC1_DIS (0x0 << 10 ) /* DIS */
6916#define DMAALTCLR_ADC1_EN (0x1 << 10 ) /* EN */
6917
6918/* DMAALTCLR[ADC0] - ADC0 */
6919#define DMAALTCLR_ADC0_BBA (*(volatile unsigned long *) 0x422006A4)
6920#define DMAALTCLR_ADC0_MSK (0x1 << 9 )
6921#define DMAALTCLR_ADC0 (0x1 << 9 )
6922#define DMAALTCLR_ADC0_DIS (0x0 << 9 ) /* DIS */
6923#define DMAALTCLR_ADC0_EN (0x1 << 9 ) /* EN */
6924
6925/* DMAALTCLR[DAC] - DAC DMA Output */
6926#define DMAALTCLR_DAC_BBA (*(volatile unsigned long *) 0x422006A0)
6927#define DMAALTCLR_DAC_MSK (0x1 << 8 )
6928#define DMAALTCLR_DAC (0x1 << 8 )
6929#define DMAALTCLR_DAC_DIS (0x0 << 8 ) /* DIS */
6930#define DMAALTCLR_DAC_EN (0x1 << 8 ) /* EN */
6931
6932/* DMAALTCLR[I2CMRX] - DMA I2C Master RX */
6933#define DMAALTCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220069C)
6934#define DMAALTCLR_I2CMRX_MSK (0x1 << 7 )
6935#define DMAALTCLR_I2CMRX (0x1 << 7 )
6936#define DMAALTCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6937#define DMAALTCLR_I2CMRX_EN (0x1 << 7 ) /* EN */
6938
6939/* DMAALTCLR[I2CMTX] - DMA I2C Master TX */
6940#define DMAALTCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200698)
6941#define DMAALTCLR_I2CMTX_MSK (0x1 << 6 )
6942#define DMAALTCLR_I2CMTX (0x1 << 6 )
6943#define DMAALTCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6944#define DMAALTCLR_I2CMTX_EN (0x1 << 6 ) /* EN */
6945
6946/* DMAALTCLR[I2CSRX] - DMA I2C Slave RX */
6947#define DMAALTCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200694)
6948#define DMAALTCLR_I2CSRX_MSK (0x1 << 5 )
6949#define DMAALTCLR_I2CSRX (0x1 << 5 )
6950#define DMAALTCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6951#define DMAALTCLR_I2CSRX_EN (0x1 << 5 ) /* EN */
6952
6953/* DMAALTCLR[I2CSTX] - DMA I2C Slave TX */
6954#define DMAALTCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200690)
6955#define DMAALTCLR_I2CSTX_MSK (0x1 << 4 )
6956#define DMAALTCLR_I2CSTX (0x1 << 4 )
6957#define DMAALTCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6958#define DMAALTCLR_I2CSTX_EN (0x1 << 4 ) /* EN */
6959
6960/* DMAALTCLR[UARTRX] - DMA UART RX */
6961#define DMAALTCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220068C)
6962#define DMAALTCLR_UARTRX_MSK (0x1 << 3 )
6963#define DMAALTCLR_UARTRX (0x1 << 3 )
6964#define DMAALTCLR_UARTRX_DIS (0x0 << 3 ) /* DIS */
6965#define DMAALTCLR_UARTRX_EN (0x1 << 3 ) /* EN */
6966
6967/* DMAALTCLR[UARTTX] - DMA UART TX */
6968#define DMAALTCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200688)
6969#define DMAALTCLR_UARTTX_MSK (0x1 << 2 )
6970#define DMAALTCLR_UARTTX (0x1 << 2 )
6971#define DMAALTCLR_UARTTX_DIS (0x0 << 2 ) /* DIS */
6972#define DMAALTCLR_UARTTX_EN (0x1 << 2 ) /* EN */
6973
6974/* DMAALTCLR[SPI1RX] - DMA SPI 1 RX */
6975#define DMAALTCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200684)
6976#define DMAALTCLR_SPI1RX_MSK (0x1 << 1 )
6977#define DMAALTCLR_SPI1RX (0x1 << 1 )
6978#define DMAALTCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6979#define DMAALTCLR_SPI1RX_EN (0x1 << 1 ) /* EN */
6980
6981/* DMAALTCLR[SPI1TX] - DMA SPI 1 TX */
6982#define DMAALTCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200680)
6983#define DMAALTCLR_SPI1TX_MSK (0x1 << 0 )
6984#define DMAALTCLR_SPI1TX (0x1 << 0 )
6985#define DMAALTCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6986#define DMAALTCLR_SPI1TX_EN (0x1 << 0 ) /* EN */
6987
6988/* Reset Value for DMAPRISET*/
6989#define DMAPRISET_RVAL 0x0
6990/*DMAPRISET[UART1RX] - DMA UART1 RX */
6991#define DMAPRISET_UART1RX_BBA (*(volatile unsigned long *) 0x4220073C)
6992#define DMAPRISET_UART1RX_MSK (0x1 << 15 )
6993#define DMAPRISET_UART1RX (0x1 << 15 )
6994#define DMAPRISET_UART1RX_DIS (0x0 << 15 ) /* DIS */
6995#define DMAPRISET_UART1RX_EN (0x1 << 15 ) /* EN */
6996/* DMAPRISET[UART1TX] - DMA UART1 TX */
6997#define DMAPRISET_UART1TX_BBA (*(volatile unsigned long *) 0x42200738)
6998#define DMAPRISET_UART1TX_MSK (0x1 << 14 )
6999#define DMAPRISET_UART1TX (0x1 << 14 )
7000#define DMAPRISET_UART1TX_DIS (0x0 << 14 ) /* DIS */
7001#define DMAPRISET_UART1TX_EN (0x1 << 14 ) /* EN */
7002/* DMAPRISET[SPI0RX] - DMA SPI 0 RX */
7003#define DMAPRISET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200734)
7004#define DMAPRISET_SPI0RX_MSK (0x1 << 13 )
7005#define DMAPRISET_SPI0RX (0x1 << 13 )
7006#define DMAPRISET_SPI0RX_DIS (0x0 << 13 ) /* DIS */
7007#define DMAPRISET_SPI0RX_EN (0x1 << 13 ) /* EN */
7008/* DMAPRISET[SPI0TX] - DMA SPI 0 TX */
7009#define DMAPRISET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200730)
7010#define DMAPRISET_SPI0TX_MSK (0x1 << 12 )
7011#define DMAPRISET_SPI0TX (0x1 << 12 )
7012#define DMAPRISET_SPI0TX_DIS (0x0 << 12 ) /* DIS */
7013#define DMAPRISET_SPI0TX_EN (0x1 << 12 ) /* EN */
7014
7015
7016/* DMAPRISET[SINC2] - SINC2 Output Step detection */
7017#define DMAPRISET_SINC2_BBA (*(volatile unsigned long *) 0x4220072C)
7018#define DMAPRISET_SINC2_MSK (0x1 << 11 )
7019#define DMAPRISET_SINC2 (0x1 << 11 )
7020#define DMAPRISET_SINC2_DIS (0x0 << 11 ) /* DIS */
7021#define DMAPRISET_SINC2_EN (0x1 << 11 ) /* EN */
7022
7023/* DMAPRISET[ADC1] - ADC1 */
7024#define DMAPRISET_ADC1_BBA (*(volatile unsigned long *) 0x42200728)
7025#define DMAPRISET_ADC1_MSK (0x1 << 10 )
7026#define DMAPRISET_ADC1 (0x1 << 10 )
7027#define DMAPRISET_ADC1_DIS (0x0 << 10 ) /* DIS */
7028#define DMAPRISET_ADC1_EN (0x1 << 10 ) /* EN */
7029
7030/* DMAPRISET[ADC0] - ADC0 */
7031#define DMAPRISET_ADC0_BBA (*(volatile unsigned long *) 0x42200724)
7032#define DMAPRISET_ADC0_MSK (0x1 << 9 )
7033#define DMAPRISET_ADC0 (0x1 << 9 )
7034#define DMAPRISET_ADC0_DIS (0x0 << 9 ) /* DIS */
7035#define DMAPRISET_ADC0_EN (0x1 << 9 ) /* EN */
7036
7037/* DMAPRISET[DAC] - DAC DMA Output */
7038#define DMAPRISET_DAC_BBA (*(volatile unsigned long *) 0x42200720)
7039#define DMAPRISET_DAC_MSK (0x1 << 8 )
7040#define DMAPRISET_DAC (0x1 << 8 )
7041#define DMAPRISET_DAC_DIS (0x0 << 8 ) /* DIS */
7042#define DMAPRISET_DAC_EN (0x1 << 8 ) /* EN */
7043
7044/* DMAPRISET[I2CMRX] - DMA I2C Master RX */
7045#define DMAPRISET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220071C)
7046#define DMAPRISET_I2CMRX_MSK (0x1 << 7 )
7047#define DMAPRISET_I2CMRX (0x1 << 7 )
7048#define DMAPRISET_I2CMRX_DIS (0x0 << 7 ) /* DIS */
7049#define DMAPRISET_I2CMRX_EN (0x1 << 7 ) /* EN */
7050
7051/* DMAPRISET[I2CMTX] - DMA I2C Master TX */
7052#define DMAPRISET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200718)
7053#define DMAPRISET_I2CMTX_MSK (0x1 << 6 )
7054#define DMAPRISET_I2CMTX (0x1 << 6 )
7055#define DMAPRISET_I2CMTX_DIS (0x0 << 6 ) /* DIS */
7056#define DMAPRISET_I2CMTX_EN (0x1 << 6 ) /* EN */
7057
7058/* DMAPRISET[I2CSRX] - DMA I2C Slave RX */
7059#define DMAPRISET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200714)
7060#define DMAPRISET_I2CSRX_MSK (0x1 << 5 )
7061#define DMAPRISET_I2CSRX (0x1 << 5 )
7062#define DMAPRISET_I2CSRX_DIS (0x0 << 5 ) /* DIS */
7063#define DMAPRISET_I2CSRX_EN (0x1 << 5 ) /* EN */
7064
7065/* DMAPRISET[I2CSTX] - DMA I2C Slave TX */
7066#define DMAPRISET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200710)
7067#define DMAPRISET_I2CSTX_MSK (0x1 << 4 )
7068#define DMAPRISET_I2CSTX (0x1 << 4 )
7069#define DMAPRISET_I2CSTX_DIS (0x0 << 4 ) /* DIS */
7070#define DMAPRISET_I2CSTX_EN (0x1 << 4 ) /* EN */
7071
7072/* DMAPRISET[UARTRX] - DMA UART RX */
7073#define DMAPRISET_UARTRX_BBA (*(volatile unsigned long *) 0x4220070C)
7074#define DMAPRISET_UARTRX_MSK (0x1 << 3 )
7075#define DMAPRISET_UARTRX (0x1 << 3 )
7076#define DMAPRISET_UARTRX_DIS (0x0 << 3 ) /* DIS */
7077#define DMAPRISET_UARTRX_EN (0x1 << 3 ) /* EN */
7078
7079/* DMAPRISET[UARTTX] - DMA UART TX */
7080#define DMAPRISET_UARTTX_BBA (*(volatile unsigned long *) 0x42200708)
7081#define DMAPRISET_UARTTX_MSK (0x1 << 2 )
7082#define DMAPRISET_UARTTX (0x1 << 2 )
7083#define DMAPRISET_UARTTX_DIS (0x0 << 2 ) /* DIS */
7084#define DMAPRISET_UARTTX_EN (0x1 << 2 ) /* EN */
7085
7086/* DMAPRISET[SPI1RX] - DMA SPI 1 RX */
7087#define DMAPRISET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200704)
7088#define DMAPRISET_SPI1RX_MSK (0x1 << 1 )
7089#define DMAPRISET_SPI1RX (0x1 << 1 )
7090#define DMAPRISET_SPI1RX_DIS (0x0 << 1 ) /* DIS */
7091#define DMAPRISET_SPI1RX_EN (0x1 << 1 ) /* EN */
7092
7093/* DMAPRISET[SPI1TX] - DMA SPI 1 TX */
7094#define DMAPRISET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200700)
7095#define DMAPRISET_SPI1TX_MSK (0x1 << 0 )
7096#define DMAPRISET_SPI1TX (0x1 << 0 )
7097#define DMAPRISET_SPI1TX_DIS (0x0 << 0 ) /* DIS */
7098#define DMAPRISET_SPI1TX_EN (0x1 << 0 ) /* EN */
7099
7100/* Reset Value for DMAPRICLR*/
7101#define DMAPRICLR_RVAL 0x0
7102
7103/*DMAPRICLR[UART1RX] - DMA UART1 RX */
7104#define DMAPRICLR_UART1RX_BBA (*(volatile unsigned long *) 0x422007BC)
7105#define DMAPRICLR_UART1RX_MSK (0x1 << 15 )
7106#define DMAPRICLR_UART1RX (0x1 << 15 )
7107#define DMAPRICLR_UART1RX_DIS (0x0 << 15 ) /* DIS */
7108#define DMAPRICLR_UART1RX_EN (0x1 << 15 ) /* EN */
7109/* DMAPRICLR[UART1TX] - DMA UART1 TX */
7110#define DMAPRICLR_UART1TX_BBA (*(volatile unsigned long *) 0x422007B8)
7111#define DMAPRICLR_UART1TX_MSK (0x1 << 14 )
7112#define DMAPRICLR_UART1TX (0x1 << 14 )
7113#define DMAPRICLR_UART1TX_DIS (0x0 << 14 ) /* DIS */
7114#define DMAPRICLR_UART1TX_EN (0x1 << 14 ) /* EN */
7115/* DMAPRICLR[SPI0RX] - DMA SPI 0 RX */
7116#define DMAPRICLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422007B4)
7117#define DMAPRICLR_SPI0RX_MSK (0x1 << 13 )
7118#define DMAPRICLR_SPI0RX (0x1 << 13 )
7119#define DMAPRICLR_SPI0RX_DIS (0x0 << 13 ) /* DIS */
7120#define DMAPRICLR_SPI0RX_EN (0x1 << 13 ) /* EN */
7121/* DMAPRICLR[SPI0TX] - DMA SPI 0 TX */
7122#define DMAPRICLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422007B0)
7123#define DMAPRICLR_SPI0TX_MSK (0x1 << 12 )
7124#define DMAPRICLR_SPI0TX (0x1 << 12 )
7125#define DMAPRICLR_SPI0TX_DIS (0x0 << 12 ) /* DIS */
7126#define DMAPRICLR_SPI0TX_EN (0x1 << 12 ) /* EN */
7127
7128/* DMAPRICLR[SINC2] - SINC2 Output Step detection */
7129#define DMAPRICLR_SINC2_BBA (*(volatile unsigned long *) 0x422007AC)
7130#define DMAPRICLR_SINC2_MSK (0x1 << 11 )
7131#define DMAPRICLR_SINC2 (0x1 << 11 )
7132#define DMAPRICLR_SINC2_DIS (0x0 << 11 ) /* DIS */
7133#define DMAPRICLR_SINC2_EN (0x1 << 11 ) /* EN */
7134
7135/* DMAPRICLR[ADC1] - ADC1 */
7136#define DMAPRICLR_ADC1_BBA (*(volatile unsigned long *) 0x422007A8)
7137#define DMAPRICLR_ADC1_MSK (0x1 << 10 )
7138#define DMAPRICLR_ADC1 (0x1 << 10 )
7139#define DMAPRICLR_ADC1_DIS (0x0 << 10 ) /* DIS */
7140#define DMAPRICLR_ADC1_EN (0x1 << 10 ) /* EN */
7141
7142/* DMAPRICLR[ADC0] - ADC0 */
7143#define DMAPRICLR_ADC0_BBA (*(volatile unsigned long *) 0x422007A4)
7144#define DMAPRICLR_ADC0_MSK (0x1 << 9 )
7145#define DMAPRICLR_ADC0 (0x1 << 9 )
7146#define DMAPRICLR_ADC0_DIS (0x0 << 9 ) /* DIS */
7147#define DMAPRICLR_ADC0_EN (0x1 << 9 ) /* EN */
7148
7149/* DMAPRICLR[DAC] - DAC DMA Output */
7150#define DMAPRICLR_DAC_BBA (*(volatile unsigned long *) 0x422007A0)
7151#define DMAPRICLR_DAC_MSK (0x1 << 8 )
7152#define DMAPRICLR_DAC (0x1 << 8 )
7153#define DMAPRICLR_DAC_DIS (0x0 << 8 ) /* DIS */
7154#define DMAPRICLR_DAC_EN (0x1 << 8 ) /* EN */
7155
7156/* DMAPRICLR[I2CMRX] - DMA I2C Master RX */
7157#define DMAPRICLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220079C)
7158#define DMAPRICLR_I2CMRX_MSK (0x1 << 7 )
7159#define DMAPRICLR_I2CMRX (0x1 << 7 )
7160#define DMAPRICLR_I2CMRX_DIS (0x0 << 7 ) /* DIS */
7161#define DMAPRICLR_I2CMRX_EN (0x1 << 7 ) /* EN */
7162
7163/* DMAPRICLR[I2CMTX] - DMA I2C Master TX */
7164#define DMAPRICLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200798)
7165#define DMAPRICLR_I2CMTX_MSK (0x1 << 6 )
7166#define DMAPRICLR_I2CMTX (0x1 << 6 )
7167#define DMAPRICLR_I2CMTX_DIS (0x0 << 6 ) /* DIS */
7168#define DMAPRICLR_I2CMTX_EN (0x1 << 6 ) /* EN */
7169
7170/* DMAPRICLR[I2CSRX] - DMA I2C Slave RX */
7171#define DMAPRICLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200794)
7172#define DMAPRICLR_I2CSRX_MSK (0x1 << 5 )
7173#define DMAPRICLR_I2CSRX (0x1 << 5 )
7174#define DMAPRICLR_I2CSRX_DIS (0x0 << 5 ) /* DIS */
7175#define DMAPRICLR_I2CSRX_EN (0x1 << 5 ) /* EN */
7176
7177/* DMAPRICLR[I2CSTX] - DMA I2C Slave TX */
7178#define DMAPRICLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200790)
7179#define DMAPRICLR_I2CSTX_MSK (0x1 << 4 )
7180#define DMAPRICLR_I2CSTX (0x1 << 4 )
7181#define DMAPRICLR_I2CSTX_DIS (0x0 << 4 ) /* DIS */
7182#define DMAPRICLR_I2CSTX_EN (0x1 << 4 ) /* EN */
7183
7184/* DMAPRICLR[UARTRX] - DMA UART RX */
7185#define DMAPRICLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220078C)
7186#define DMAPRICLR_UARTRX_MSK (0x1 << 3 )
7187#define DMAPRICLR_UARTRX (0x1 << 3 )
7188#define DMAPRICLR_UARTRX_DIS (0x0 << 3 ) /* DIS */
7189#define DMAPRICLR_UARTRX_EN (0x1 << 3 ) /* EN */
7190
7191/* DMAPRICLR[UARTTX] - DMA UART TX */
7192#define DMAPRICLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200788)
7193#define DMAPRICLR_UARTTX_MSK (0x1 << 2 )
7194#define DMAPRICLR_UARTTX (0x1 << 2 )
7195#define DMAPRICLR_UARTTX_DIS (0x0 << 2 ) /* DIS */
7196#define DMAPRICLR_UARTTX_EN (0x1 << 2 ) /* EN */
7197
7198/* DMAPRICLR[SPI1RX] - DMA SPI 1 RX */
7199#define DMAPRICLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200784)
7200#define DMAPRICLR_SPI1RX_MSK (0x1 << 1 )
7201#define DMAPRICLR_SPI1RX (0x1 << 1 )
7202#define DMAPRICLR_SPI1RX_DIS (0x0 << 1 ) /* DIS */
7203#define DMAPRICLR_SPI1RX_EN (0x1 << 1 ) /* EN */
7204
7205/* DMAPRICLR[SPI1TX] - DMA SPI 1 TX */
7206#define DMAPRICLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200780)
7207#define DMAPRICLR_SPI1TX_MSK (0x1 << 0 )
7208#define DMAPRICLR_SPI1TX (0x1 << 0 )
7209#define DMAPRICLR_SPI1TX_DIS (0x0 << 0 ) /* DIS */
7210#define DMAPRICLR_SPI1TX_EN (0x1 << 0 ) /* EN */
7211
7212/* Reset Value for DMAERRCLR*/
7213#define DMAERRCLR_RVAL 0x0
7214
7215/* DMAERRCLR[ERROR] - DMA Error status */
7216#define DMAERRCLR_ERROR_BBA (*(volatile unsigned long *) 0x42200980)
7217#define DMAERRCLR_ERROR_MSK (0x1 << 0 )
7218#define DMAERRCLR_ERROR (0x1 << 0 )
7219#define DMAERRCLR_ERROR_DIS (0x0 << 0 ) /* DIS */
7220#define DMAERRCLR_ERROR_EN (0x1 << 0 ) /* EN */
7221
7222/* Reset Value for DMABSSET*/
7223#define DMABSSET_RVAL 0x0
7224
7225/* DMABSSET[CHBSWAPSET] - Byte swap status */
7226#define DMABSSET_CHBSWAPSET_MSK (0x3FFF << 0 )
7227
7228/* Reset Value for DMABSCLR*/
7229#define DMABSCLR_RVAL 0x0
7230
7231/* DMABSCLR[CHBSWAPCLR] - Disable byte swap */
7232#define DMABSCLR_CHBSWAPCLR_MSK (0x3FFF << 0 )
7233// ------------------------------------------------------------------------------------------------
7234// ----- NVIC -----
7235// ------------------------------------------------------------------------------------------------
7236
7237
7238/**
7239 * @brief Nested Vectored Interrupt Controller (pADI_NVIC)
7240 */
7241
7242#if (__NO_MMR_STRUCTS__==0)
7243#else // (__NO_MMR_STRUCTS__==0)
7244#define ICTR (*(volatile unsigned long *) 0xE000E004)
7245#define STCSR (*(volatile unsigned long *) 0xE000E010)
7246#define STRVR (*(volatile unsigned long *) 0xE000E014)
7247#define STCVR (*(volatile unsigned long *) 0xE000E018)
7248#define STCR (*(volatile unsigned long *) 0xE000E01C)
7249#define ISER0 (*(volatile unsigned long *) 0xE000E100)
7250#define ISER1 (*(volatile unsigned long *) 0xE000E104)
7251#define ICER0 (*(volatile unsigned long *) 0xE000E180)
7252#define ICER1 (*(volatile unsigned long *) 0xE000E184)
7253#define ISPR0 (*(volatile unsigned long *) 0xE000E200)
7254#define ISPR1 (*(volatile unsigned long *) 0xE000E204)
7255#define ICPR0 (*(volatile unsigned long *) 0xE000E280)
7256#define ICPR1 (*(volatile unsigned long *) 0xE000E284)
7257#define IABR0 (*(volatile unsigned long *) 0xE000E300)
7258#define IABR1 (*(volatile unsigned long *) 0xE000E304)
7259#define IPR0 (*(volatile unsigned long *) 0xE000E400)
7260#define IPR1 (*(volatile unsigned long *) 0xE000E404)
7261#define IPR2 (*(volatile unsigned long *) 0xE000E408)
7262#define IPR3 (*(volatile unsigned long *) 0xE000E40C)
7263#define IPR4 (*(volatile unsigned long *) 0xE000E410)
7264#define IPR5 (*(volatile unsigned long *) 0xE000E414)
7265#define IPR6 (*(volatile unsigned long *) 0xE000E418)
7266#define IPR7 (*(volatile unsigned long *) 0xE000E41C)
7267#define IPR8 (*(volatile unsigned long *) 0xE000E420)
7268#define IPR9 (*(volatile unsigned long *) 0xE000E424)
7269#define CPUID (*(volatile unsigned long *) 0xE000ED00)
7270#define ICSR (*(volatile unsigned long *) 0xE000ED04)
7271#define VTOR (*(volatile unsigned long *) 0xE000ED08)
7272#define AIRCR (*(volatile unsigned long *) 0xE000ED0C)
7273#define SCR (*(volatile unsigned long *) 0xE000ED10)
7274#define CCR (*(volatile unsigned long *) 0xE000ED14)
7275#define SHPR1 (*(volatile unsigned long *) 0xE000ED18)
7276#define SHPR2 (*(volatile unsigned long *) 0xE000ED1C)
7277#define SHPR3 (*(volatile unsigned long *) 0xE000ED20)
7278#define SHCSR (*(volatile unsigned long *) 0xE000ED24)
7279#define CFSR (*(volatile unsigned long *) 0xE000ED28)
7280#define HFSR (*(volatile unsigned long *) 0xE000ED2C)
7281#define MMFAR (*(volatile unsigned long *) 0xE000ED34)
7282#define BFAR (*(volatile unsigned long *) 0xE000ED38)
7283#define STIR (*(volatile unsigned long *) 0xE000EF00)
7284#endif // (__NO_MMR_STRUCTS__==0)
7285
7286/* Reset Value for ICTR*/
7287#define ICTR_RVAL 0x1
7288
7289/* ICTR[INTLINESNUM] - Total number of interrupt lines in groups of 32 */
7290#define ICTR_INTLINESNUM_MSK (0xF << 0 )
7291
7292/* Reset Value for STCSR*/
7293#define STCSR_RVAL 0x0
7294
7295/* STCSR[COUNTFLAG] - Returns 1 if timer counted to 0 since last time this register was read */
7296#define STCSR_COUNTFLAG_MSK (0x1 << 16 )
7297#define STCSR_COUNTFLAG (0x1 << 16 )
7298#define STCSR_COUNTFLAG_DIS (0x0 << 16 ) /* DIS */
7299#define STCSR_COUNTFLAG_EN (0x1 << 16 ) /* EN */
7300
7301/* STCSR[CLKSOURCE] - clock source used for SysTick */
7302#define STCSR_CLKSOURCE_MSK (0x1 << 2 )
7303#define STCSR_CLKSOURCE (0x1 << 2 )
7304#define STCSR_CLKSOURCE_DIS (0x0 << 2 ) /* DIS */
7305#define STCSR_CLKSOURCE_EN (0x1 << 2 ) /* EN */
7306
7307/* STCSR[TICKINT] - If 1, counting down to 0 will cause the SysTick exception to pended. */
7308#define STCSR_TICKINT_MSK (0x1 << 1 )
7309#define STCSR_TICKINT (0x1 << 1 )
7310#define STCSR_TICKINT_DIS (0x0 << 1 ) /* DIS */
7311#define STCSR_TICKINT_EN (0x1 << 1 ) /* EN */
7312
7313/* STCSR[ENABLE] - Enable bit */
7314#define STCSR_ENABLE_MSK (0x1 << 0 )
7315#define STCSR_ENABLE (0x1 << 0 )
7316#define STCSR_ENABLE_DIS (0x0 << 0 ) /* DIS */
7317#define STCSR_ENABLE_EN (0x1 << 0 ) /* EN */
7318
7319/* Reset Value for STRVR*/
7320#define STRVR_RVAL 0x0
7321
7322/* STRVR[RELOAD] - Value to load into the Current Value register when the counter reaches 0 */
7323#define STRVR_RELOAD_MSK (0xFFFFFF << 0 )
7324
7325/* Reset Value for STCVR*/
7326#define STCVR_RVAL 0x0
7327
7328/* STCVR[CURRENT] - Current counter value */
7329#define STCVR_CURRENT_MSK (0xFFFFFFFF << 0 )
7330
7331/* Reset Value for STCR*/
7332#define STCR_RVAL 0x0
7333
7334/* STCR[NOREF] - If reads as 1, the Reference clock is not provided */
7335#define STCR_NOREF_MSK (0x1 << 31 )
7336#define STCR_NOREF (0x1 << 31 )
7337#define STCR_NOREF_DIS (0x0 << 31 ) /* DIS */
7338#define STCR_NOREF_EN (0x1 << 31 ) /* EN */
7339
7340/* STCR[SKEW] - If reads as 1, the calibration value for 10ms is inexact */
7341#define STCR_SKEW_MSK (0x1 << 30 )
7342#define STCR_SKEW (0x1 << 30 )
7343#define STCR_SKEW_DIS (0x0 << 30 ) /* DIS */
7344#define STCR_SKEW_EN (0x1 << 30 ) /* EN */
7345
7346/* STCR[TENMS] - An optional Reload value to be used for 10ms (100Hz) timing */
7347#define STCR_TENMS_MSK (0xFFFFFF << 0 )
7348
7349/* Reset Value for ISER0*/
7350#define ISER0_RVAL 0x0
7351
7352/* ISER0[DMADAC] - */
7353#define ISER0_DMADAC_MSK (0x1 << 31 )
7354#define ISER0_DMADAC (0x1 << 31 )
7355#define ISER0_DMADAC_DIS (0x0 << 31 ) /* DIS */
7356#define ISER0_DMADAC_EN (0x1 << 31 ) /* EN */
7357
7358/* ISER0[DMAI2CMRX] - */
7359#define ISER0_DMAI2CMRX_MSK (0x1 << 30 )
7360#define ISER0_DMAI2CMRX (0x1 << 30 )
7361#define ISER0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
7362#define ISER0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
7363
7364/* ISER0[DMAI2CMTX] - */
7365#define ISER0_DMAI2CMTX_MSK (0x1 << 29 )
7366#define ISER0_DMAI2CMTX (0x1 << 29 )
7367#define ISER0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
7368#define ISER0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
7369
7370/* ISER0[DMAI2CSRX] - */
7371#define ISER0_DMAI2CSRX_MSK (0x1 << 28 )
7372#define ISER0_DMAI2CSRX (0x1 << 28 )
7373#define ISER0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
7374#define ISER0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
7375
7376/* ISER0[DMAI2CSTX] - */
7377#define ISER0_DMAI2CSTX_MSK (0x1 << 27 )
7378#define ISER0_DMAI2CSTX (0x1 << 27 )
7379#define ISER0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
7380#define ISER0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
7381
7382/* ISER0[DMAUARTRX] - */
7383#define ISER0_DMAUARTRX_MSK (0x1 << 26 )
7384#define ISER0_DMAUARTRX (0x1 << 26 )
7385#define ISER0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
7386#define ISER0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
7387
7388/* ISER0[DMAUARTTX] - */
7389#define ISER0_DMAUARTTX_MSK (0x1 << 25 )
7390#define ISER0_DMAUARTTX (0x1 << 25 )
7391#define ISER0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
7392#define ISER0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
7393
7394/* ISER0[DMASPI1RX] - */
7395#define ISER0_DMASPI1RX_MSK (0x1 << 24 )
7396#define ISER0_DMASPI1RX (0x1 << 24 )
7397#define ISER0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
7398#define ISER0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
7399
7400/* ISER0[DMASPI1TX] - */
7401#define ISER0_DMASPI1TX_MSK (0x1 << 23 )
7402#define ISER0_DMASPI1TX (0x1 << 23 )
7403#define ISER0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
7404#define ISER0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
7405
7406/* ISER0[DMAERROR] - */
7407#define ISER0_DMAERROR_MSK (0x1 << 22 )
7408#define ISER0_DMAERROR (0x1 << 22 )
7409#define ISER0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
7410#define ISER0_DMAERROR_EN (0x1 << 22 ) /* EN */
7411
7412/* ISER0[I2CM] - */
7413#define ISER0_I2CM_MSK (0x1 << 21 )
7414#define ISER0_I2CM (0x1 << 21 )
7415#define ISER0_I2CM_DIS (0x0 << 21 ) /* DIS */
7416#define ISER0_I2CM_EN (0x1 << 21 ) /* EN */
7417
7418/* ISER0[I2CS] - */
7419#define ISER0_I2CS_MSK (0x1 << 20 )
7420#define ISER0_I2CS (0x1 << 20 )
7421#define ISER0_I2CS_DIS (0x0 << 20 ) /* DIS */
7422#define ISER0_I2CS_EN (0x1 << 20 ) /* EN */
7423
7424/* ISER0[SPI1] - */
7425#define ISER0_SPI1_MSK (0x1 << 19 )
7426#define ISER0_SPI1 (0x1 << 19 )
7427#define ISER0_SPI1_DIS (0x0 << 19 ) /* DIS */
7428#define ISER0_SPI1_EN (0x1 << 19 ) /* EN */
7429
7430/* ISER0[SPI0] - */
7431#define ISER0_SPI0_MSK (0x1 << 18 )
7432#define ISER0_SPI0 (0x1 << 18 )
7433#define ISER0_SPI0_DIS (0x0 << 18 ) /* DIS */
7434#define ISER0_SPI0_EN (0x1 << 18 ) /* EN */
7435
7436/* ISER0[UART] - */
7437#define ISER0_UART_MSK (0x1 << 17 )
7438#define ISER0_UART (0x1 << 17 )
7439#define ISER0_UART_DIS (0x0 << 17 ) /* DIS */
7440#define ISER0_UART_EN (0x1 << 17 ) /* EN */
7441
7442/* ISER0[FEE] - */
7443#define ISER0_FEE_MSK (0x1 << 16 )
7444#define ISER0_FEE (0x1 << 16 )
7445#define ISER0_FEE_DIS (0x0 << 16 ) /* DIS */
7446#define ISER0_FEE_EN (0x1 << 16 ) /* EN */
7447
7448/* ISER0[SINC2] - */
7449#define ISER0_SINC2_MSK (0x1 << 15 )
7450#define ISER0_SINC2 (0x1 << 15 )
7451#define ISER0_SINC2_DIS (0x0 << 15 ) /* DIS */
7452#define ISER0_SINC2_EN (0x1 << 15 ) /* EN */
7453
7454/* ISER0[ADC1] - */
7455#define ISER0_ADC1_MSK (0x1 << 14 )
7456#define ISER0_ADC1 (0x1 << 14 )
7457#define ISER0_ADC1_DIS (0x0 << 14 ) /* DIS */
7458#define ISER0_ADC1_EN (0x1 << 14 ) /* EN */
7459
7460/* ISER0[ADC0] - */
7461#define ISER0_ADC0_MSK (0x1 << 13 )
7462#define ISER0_ADC0 (0x1 << 13 )
7463#define ISER0_ADC0_DIS (0x0 << 13 ) /* DIS */
7464#define ISER0_ADC0_EN (0x1 << 13 ) /* EN */
7465
7466/* ISER0[T1] - */
7467#define ISER0_T1_MSK (0x1 << 12 )
7468#define ISER0_T1 (0x1 << 12 )
7469#define ISER0_T1_DIS (0x0 << 12 ) /* DIS */
7470#define ISER0_T1_EN (0x1 << 12 ) /* EN */
7471
7472/* ISER0[T0] - */
7473#define ISER0_T0_MSK (0x1 << 11 )
7474#define ISER0_T0 (0x1 << 11 )
7475#define ISER0_T0_DIS (0x0 << 11 ) /* DIS */
7476#define ISER0_T0_EN (0x1 << 11 ) /* EN */
7477
7478/* ISER0[T3] - */
7479#define ISER0_T3_MSK (0x1 << 9 )
7480#define ISER0_T3 (0x1 << 9 )
7481#define ISER0_T3_DIS (0x0 << 9 ) /* DIS */
7482#define ISER0_T3_EN (0x1 << 9 ) /* EN */
7483
7484/* ISER0[EXTINT7] - */
7485#define ISER0_EXTINT7_MSK (0x1 << 8 )
7486#define ISER0_EXTINT7 (0x1 << 8 )
7487#define ISER0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
7488#define ISER0_EXTINT7_EN (0x1 << 8 ) /* EN */
7489
7490/* ISER0[EXTINT6] - */
7491#define ISER0_EXTINT6_MSK (0x1 << 7 )
7492#define ISER0_EXTINT6 (0x1 << 7 )
7493#define ISER0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
7494#define ISER0_EXTINT6_EN (0x1 << 7 ) /* EN */
7495
7496/* ISER0[EXTINT5] - */
7497#define ISER0_EXTINT5_MSK (0x1 << 6 )
7498#define ISER0_EXTINT5 (0x1 << 6 )
7499#define ISER0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
7500#define ISER0_EXTINT5_EN (0x1 << 6 ) /* EN */
7501
7502/* ISER0[EXTINT4] - */
7503#define ISER0_EXTINT4_MSK (0x1 << 5 )
7504#define ISER0_EXTINT4 (0x1 << 5 )
7505#define ISER0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
7506#define ISER0_EXTINT4_EN (0x1 << 5 ) /* EN */
7507
7508/* ISER0[EXTINT3] - */
7509#define ISER0_EXTINT3_MSK (0x1 << 4 )
7510#define ISER0_EXTINT3 (0x1 << 4 )
7511#define ISER0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
7512#define ISER0_EXTINT3_EN (0x1 << 4 ) /* EN */
7513
7514/* ISER0[EXTINT2] - */
7515#define ISER0_EXTINT2_MSK (0x1 << 3 )
7516#define ISER0_EXTINT2 (0x1 << 3 )
7517#define ISER0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
7518#define ISER0_EXTINT2_EN (0x1 << 3 ) /* EN */
7519
7520/* ISER0[EXTINT1] - */
7521#define ISER0_EXTINT1_MSK (0x1 << 2 )
7522#define ISER0_EXTINT1 (0x1 << 2 )
7523#define ISER0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
7524#define ISER0_EXTINT1_EN (0x1 << 2 ) /* EN */
7525
7526/* ISER0[EXTINT0] - */
7527#define ISER0_EXTINT0_MSK (0x1 << 1 )
7528#define ISER0_EXTINT0 (0x1 << 1 )
7529#define ISER0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
7530#define ISER0_EXTINT0_EN (0x1 << 1 ) /* EN */
7531
7532/* ISER0[T2] - */
7533#define ISER0_T2_MSK (0x1 << 0 )
7534#define ISER0_T2 (0x1 << 0 )
7535#define ISER0_T2_DIS (0x0 << 0 ) /* DIS */
7536#define ISER0_T2_EN (0x1 << 0 ) /* EN */
7537
7538/* Reset Value for ISER1*/
7539#define ISER1_RVAL 0x0
7540
7541/* ISER1[PWM2] - */
7542#define ISER1_PWM2_MSK (0x1 << 6 )
7543#define ISER1_PWM2 (0x1 << 6 )
7544#define ISER1_PWM2_DIS (0x0 << 6 ) /* DIS */
7545#define ISER1_PWM2_EN (0x1 << 6 ) /* EN */
7546
7547/* ISER1[PWM1] - */
7548#define ISER1_PWM1_MSK (0x1 << 5 )
7549#define ISER1_PWM1 (0x1 << 5 )
7550#define ISER1_PWM1_DIS (0x0 << 5 ) /* DIS */
7551#define ISER1_PWM1_EN (0x1 << 5 ) /* EN */
7552
7553/* ISER1[PWM0] - */
7554#define ISER1_PWM0_MSK (0x1 << 4 )
7555#define ISER1_PWM0 (0x1 << 4 )
7556#define ISER1_PWM0_DIS (0x0 << 4 ) /* DIS */
7557#define ISER1_PWM0_EN (0x1 << 4 ) /* EN */
7558
7559/* ISER1[PWMTRIP] - */
7560#define ISER1_PWMTRIP_MSK (0x1 << 3 )
7561#define ISER1_PWMTRIP (0x1 << 3 )
7562#define ISER1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
7563#define ISER1_PWMTRIP_EN (0x1 << 3 ) /* EN */
7564
7565/* ISER1[DMASINC2] - */
7566#define ISER1_DMASINC2_MSK (0x1 << 2 )
7567#define ISER1_DMASINC2 (0x1 << 2 )
7568#define ISER1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
7569#define ISER1_DMASINC2_EN (0x1 << 2 ) /* EN */
7570
7571/* ISER1[DMAADC1] - */
7572#define ISER1_DMAADC1_MSK (0x1 << 1 )
7573#define ISER1_DMAADC1 (0x1 << 1 )
7574#define ISER1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
7575#define ISER1_DMAADC1_EN (0x1 << 1 ) /* EN */
7576
7577/* ISER1[DMAADC0] - */
7578#define ISER1_DMAADC0_MSK (0x1 << 0 )
7579#define ISER1_DMAADC0 (0x1 << 0 )
7580#define ISER1_DMAADC0_DIS (0x0 << 0 ) /* DIS */
7581#define ISER1_DMAADC0_EN (0x1 << 0 ) /* EN */
7582
7583/* Reset Value for ICER0*/
7584#define ICER0_RVAL 0x0
7585
7586/* ICER0[DMADAC] - */
7587#define ICER0_DMADAC_MSK (0x1 << 31 )
7588#define ICER0_DMADAC (0x1 << 31 )
7589#define ICER0_DMADAC_DIS (0x0 << 31 ) /* DIS */
7590#define ICER0_DMADAC_EN (0x1 << 31 ) /* EN */
7591
7592/* ICER0[DMAI2CMRX] - */
7593#define ICER0_DMAI2CMRX_MSK (0x1 << 30 )
7594#define ICER0_DMAI2CMRX (0x1 << 30 )
7595#define ICER0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
7596#define ICER0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
7597
7598/* ICER0[DMAI2CMTX] - */
7599#define ICER0_DMAI2CMTX_MSK (0x1 << 29 )
7600#define ICER0_DMAI2CMTX (0x1 << 29 )
7601#define ICER0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
7602#define ICER0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
7603
7604/* ICER0[DMAI2CSRX] - */
7605#define ICER0_DMAI2CSRX_MSK (0x1 << 28 )
7606#define ICER0_DMAI2CSRX (0x1 << 28 )
7607#define ICER0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
7608#define ICER0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
7609
7610/* ICER0[DMAI2CSTX] - */
7611#define ICER0_DMAI2CSTX_MSK (0x1 << 27 )
7612#define ICER0_DMAI2CSTX (0x1 << 27 )
7613#define ICER0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
7614#define ICER0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
7615
7616/* ICER0[DMAUARTRX] - */
7617#define ICER0_DMAUARTRX_MSK (0x1 << 26 )
7618#define ICER0_DMAUARTRX (0x1 << 26 )
7619#define ICER0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
7620#define ICER0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
7621
7622/* ICER0[DMAUARTTX] - */
7623#define ICER0_DMAUARTTX_MSK (0x1 << 25 )
7624#define ICER0_DMAUARTTX (0x1 << 25 )
7625#define ICER0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
7626#define ICER0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
7627
7628/* ICER0[DMASPI1RX] - */
7629#define ICER0_DMASPI1RX_MSK (0x1 << 24 )
7630#define ICER0_DMASPI1RX (0x1 << 24 )
7631#define ICER0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
7632#define ICER0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
7633
7634/* ICER0[DMASPI1TX] - */
7635#define ICER0_DMASPI1TX_MSK (0x1 << 23 )
7636#define ICER0_DMASPI1TX (0x1 << 23 )
7637#define ICER0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
7638#define ICER0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
7639
7640/* ICER0[DMAERROR] - */
7641#define ICER0_DMAERROR_MSK (0x1 << 22 )
7642#define ICER0_DMAERROR (0x1 << 22 )
7643#define ICER0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
7644#define ICER0_DMAERROR_EN (0x1 << 22 ) /* EN */
7645
7646/* ICER0[I2CM] - */
7647#define ICER0_I2CM_MSK (0x1 << 21 )
7648#define ICER0_I2CM (0x1 << 21 )
7649#define ICER0_I2CM_DIS (0x0 << 21 ) /* DIS */
7650#define ICER0_I2CM_EN (0x1 << 21 ) /* EN */
7651
7652/* ICER0[I2CS] - */
7653#define ICER0_I2CS_MSK (0x1 << 20 )
7654#define ICER0_I2CS (0x1 << 20 )
7655#define ICER0_I2CS_DIS (0x0 << 20 ) /* DIS */
7656#define ICER0_I2CS_EN (0x1 << 20 ) /* EN */
7657
7658/* ICER0[SPI1] - */
7659#define ICER0_SPI1_MSK (0x1 << 19 )
7660#define ICER0_SPI1 (0x1 << 19 )
7661#define ICER0_SPI1_DIS (0x0 << 19 ) /* DIS */
7662#define ICER0_SPI1_EN (0x1 << 19 ) /* EN */
7663
7664/* ICER0[SPI0] - */
7665#define ICER0_SPI0_MSK (0x1 << 18 )
7666#define ICER0_SPI0 (0x1 << 18 )
7667#define ICER0_SPI0_DIS (0x0 << 18 ) /* DIS */
7668#define ICER0_SPI0_EN (0x1 << 18 ) /* EN */
7669
7670/* ICER0[UART] - */
7671#define ICER0_UART_MSK (0x1 << 17 )
7672#define ICER0_UART (0x1 << 17 )
7673#define ICER0_UART_DIS (0x0 << 17 ) /* DIS */
7674#define ICER0_UART_EN (0x1 << 17 ) /* EN */
7675
7676/* ICER0[FEE] - */
7677#define ICER0_FEE_MSK (0x1 << 16 )
7678#define ICER0_FEE (0x1 << 16 )
7679#define ICER0_FEE_DIS (0x0 << 16 ) /* DIS */
7680#define ICER0_FEE_EN (0x1 << 16 ) /* EN */
7681
7682/* ICER0[SINC2] - */
7683#define ICER0_SINC2_MSK (0x1 << 15 )
7684#define ICER0_SINC2 (0x1 << 15 )
7685#define ICER0_SINC2_DIS (0x0 << 15 ) /* DIS */
7686#define ICER0_SINC2_EN (0x1 << 15 ) /* EN */
7687
7688/* ICER0[ADC1] - */
7689#define ICER0_ADC1_MSK (0x1 << 14 )
7690#define ICER0_ADC1 (0x1 << 14 )
7691#define ICER0_ADC1_DIS (0x0 << 14 ) /* DIS */
7692#define ICER0_ADC1_EN (0x1 << 14 ) /* EN */
7693
7694/* ICER0[ADC0] - */
7695#define ICER0_ADC0_MSK (0x1 << 13 )
7696#define ICER0_ADC0 (0x1 << 13 )
7697#define ICER0_ADC0_DIS (0x0 << 13 ) /* DIS */
7698#define ICER0_ADC0_EN (0x1 << 13 ) /* EN */
7699
7700/* ICER0[T1] - */
7701#define ICER0_T1_MSK (0x1 << 12 )
7702#define ICER0_T1 (0x1 << 12 )
7703#define ICER0_T1_DIS (0x0 << 12 ) /* DIS */
7704#define ICER0_T1_EN (0x1 << 12 ) /* EN */
7705
7706/* ICER0[T0] - */
7707#define ICER0_T0_MSK (0x1 << 11 )
7708#define ICER0_T0 (0x1 << 11 )
7709#define ICER0_T0_DIS (0x0 << 11 ) /* DIS */
7710#define ICER0_T0_EN (0x1 << 11 ) /* EN */
7711
7712/* ICER0[T3] - */
7713#define ICER0_T3_MSK (0x1 << 9 )
7714#define ICER0_T3 (0x1 << 9 )
7715#define ICER0_T3_DIS (0x0 << 9 ) /* DIS */
7716#define ICER0_T3_EN (0x1 << 9 ) /* EN */
7717
7718/* ICER0[EXTINT7] - */
7719#define ICER0_EXTINT7_MSK (0x1 << 8 )
7720#define ICER0_EXTINT7 (0x1 << 8 )
7721#define ICER0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
7722#define ICER0_EXTINT7_EN (0x1 << 8 ) /* EN */
7723
7724/* ICER0[EXTINT6] - */
7725#define ICER0_EXTINT6_MSK (0x1 << 7 )
7726#define ICER0_EXTINT6 (0x1 << 7 )
7727#define ICER0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
7728#define ICER0_EXTINT6_EN (0x1 << 7 ) /* EN */
7729
7730/* ICER0[EXTINT5] - */
7731#define ICER0_EXTINT5_MSK (0x1 << 6 )
7732#define ICER0_EXTINT5 (0x1 << 6 )
7733#define ICER0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
7734#define ICER0_EXTINT5_EN (0x1 << 6 ) /* EN */
7735
7736/* ICER0[EXTINT4] - */
7737#define ICER0_EXTINT4_MSK (0x1 << 5 )
7738#define ICER0_EXTINT4 (0x1 << 5 )
7739#define ICER0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
7740#define ICER0_EXTINT4_EN (0x1 << 5 ) /* EN */
7741
7742/* ICER0[EXTINT3] - */
7743#define ICER0_EXTINT3_MSK (0x1 << 4 )
7744#define ICER0_EXTINT3 (0x1 << 4 )
7745#define ICER0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
7746#define ICER0_EXTINT3_EN (0x1 << 4 ) /* EN */
7747
7748/* ICER0[EXTINT2] - */
7749#define ICER0_EXTINT2_MSK (0x1 << 3 )
7750#define ICER0_EXTINT2 (0x1 << 3 )
7751#define ICER0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
7752#define ICER0_EXTINT2_EN (0x1 << 3 ) /* EN */
7753
7754/* ICER0[EXTINT1] - */
7755#define ICER0_EXTINT1_MSK (0x1 << 2 )
7756#define ICER0_EXTINT1 (0x1 << 2 )
7757#define ICER0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
7758#define ICER0_EXTINT1_EN (0x1 << 2 ) /* EN */
7759
7760/* ICER0[EXTINT0] - */
7761#define ICER0_EXTINT0_MSK (0x1 << 1 )
7762#define ICER0_EXTINT0 (0x1 << 1 )
7763#define ICER0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
7764#define ICER0_EXTINT0_EN (0x1 << 1 ) /* EN */
7765
7766/* ICER0[T2] - */
7767#define ICER0_T2_MSK (0x1 << 0 )
7768#define ICER0_T2 (0x1 << 0 )
7769#define ICER0_T2_DIS (0x0 << 0 ) /* DIS */
7770#define ICER0_T2_EN (0x1 << 0 ) /* EN */
7771
7772/* Reset Value for ICER1*/
7773#define ICER1_RVAL 0x0
7774
7775/* ICER1[PWM2] - */
7776#define ICER1_PWM2_MSK (0x1 << 6 )
7777#define ICER1_PWM2 (0x1 << 6 )
7778#define ICER1_PWM2_DIS (0x0 << 6 ) /* DIS */
7779#define ICER1_PWM2_EN (0x1 << 6 ) /* EN */
7780
7781/* ICER1[PWM1] - */
7782#define ICER1_PWM1_MSK (0x1 << 5 )
7783#define ICER1_PWM1 (0x1 << 5 )
7784#define ICER1_PWM1_DIS (0x0 << 5 ) /* DIS */
7785#define ICER1_PWM1_EN (0x1 << 5 ) /* EN */
7786
7787/* ICER1[PWM0] - */
7788#define ICER1_PWM0_MSK (0x1 << 4 )
7789#define ICER1_PWM0 (0x1 << 4 )
7790#define ICER1_PWM0_DIS (0x0 << 4 ) /* DIS */
7791#define ICER1_PWM0_EN (0x1 << 4 ) /* EN */
7792
7793/* ICER1[PWMTRIP] - */
7794#define ICER1_PWMTRIP_MSK (0x1 << 3 )
7795#define ICER1_PWMTRIP (0x1 << 3 )
7796#define ICER1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
7797#define ICER1_PWMTRIP_EN (0x1 << 3 ) /* EN */
7798
7799/* ICER1[DMASINC2] - */
7800#define ICER1_DMASINC2_MSK (0x1 << 2 )
7801#define ICER1_DMASINC2 (0x1 << 2 )
7802#define ICER1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
7803#define ICER1_DMASINC2_EN (0x1 << 2 ) /* EN */
7804
7805/* ICER1[DMAADC1] - */
7806#define ICER1_DMAADC1_MSK (0x1 << 1 )
7807#define ICER1_DMAADC1 (0x1 << 1 )
7808#define ICER1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
7809#define ICER1_DMAADC1_EN (0x1 << 1 ) /* EN */
7810
7811/* ICER1[DMAADC0] - */
7812#define ICER1_DMAADC0_MSK (0x1 << 0 )
7813#define ICER1_DMAADC0 (0x1 << 0 )
7814#define ICER1_DMAADC0_DIS (0x0 << 0 ) /* DIS */
7815#define ICER1_DMAADC0_EN (0x1 << 0 ) /* EN */
7816
7817/* Reset Value for ISPR0*/
7818#define ISPR0_RVAL 0x0
7819
7820/* ISPR0[DMADAC] - */
7821#define ISPR0_DMADAC_MSK (0x1 << 31 )
7822#define ISPR0_DMADAC (0x1 << 31 )
7823#define ISPR0_DMADAC_DIS (0x0 << 31 ) /* DIS */
7824#define ISPR0_DMADAC_EN (0x1 << 31 ) /* EN */
7825
7826/* ISPR0[DMAI2CMRX] - */
7827#define ISPR0_DMAI2CMRX_MSK (0x1 << 30 )
7828#define ISPR0_DMAI2CMRX (0x1 << 30 )
7829#define ISPR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
7830#define ISPR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
7831
7832/* ISPR0[DMAI2CMTX] - */
7833#define ISPR0_DMAI2CMTX_MSK (0x1 << 29 )
7834#define ISPR0_DMAI2CMTX (0x1 << 29 )
7835#define ISPR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
7836#define ISPR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
7837
7838/* ISPR0[DMAI2CSRX] - */
7839#define ISPR0_DMAI2CSRX_MSK (0x1 << 28 )
7840#define ISPR0_DMAI2CSRX (0x1 << 28 )
7841#define ISPR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
7842#define ISPR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
7843
7844/* ISPR0[DMAI2CSTX] - */
7845#define ISPR0_DMAI2CSTX_MSK (0x1 << 27 )
7846#define ISPR0_DMAI2CSTX (0x1 << 27 )
7847#define ISPR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
7848#define ISPR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
7849
7850/* ISPR0[DMAUARTRX] - */
7851#define ISPR0_DMAUARTRX_MSK (0x1 << 26 )
7852#define ISPR0_DMAUARTRX (0x1 << 26 )
7853#define ISPR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
7854#define ISPR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
7855
7856/* ISPR0[DMAUARTTX] - */
7857#define ISPR0_DMAUARTTX_MSK (0x1 << 25 )
7858#define ISPR0_DMAUARTTX (0x1 << 25 )
7859#define ISPR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
7860#define ISPR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
7861
7862/* ISPR0[DMASPI1RX] - */
7863#define ISPR0_DMASPI1RX_MSK (0x1 << 24 )
7864#define ISPR0_DMASPI1RX (0x1 << 24 )
7865#define ISPR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
7866#define ISPR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
7867
7868/* ISPR0[DMASPI1TX] - */
7869#define ISPR0_DMASPI1TX_MSK (0x1 << 23 )
7870#define ISPR0_DMASPI1TX (0x1 << 23 )
7871#define ISPR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
7872#define ISPR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
7873
7874/* ISPR0[DMAERROR] - */
7875#define ISPR0_DMAERROR_MSK (0x1 << 22 )
7876#define ISPR0_DMAERROR (0x1 << 22 )
7877#define ISPR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
7878#define ISPR0_DMAERROR_EN (0x1 << 22 ) /* EN */
7879
7880/* ISPR0[I2CM] - */
7881#define ISPR0_I2CM_MSK (0x1 << 21 )
7882#define ISPR0_I2CM (0x1 << 21 )
7883#define ISPR0_I2CM_DIS (0x0 << 21 ) /* DIS */
7884#define ISPR0_I2CM_EN (0x1 << 21 ) /* EN */
7885
7886/* ISPR0[I2CS] - */
7887#define ISPR0_I2CS_MSK (0x1 << 20 )
7888#define ISPR0_I2CS (0x1 << 20 )
7889#define ISPR0_I2CS_DIS (0x0 << 20 ) /* DIS */
7890#define ISPR0_I2CS_EN (0x1 << 20 ) /* EN */
7891
7892/* ISPR0[SPI1] - */
7893#define ISPR0_SPI1_MSK (0x1 << 19 )
7894#define ISPR0_SPI1 (0x1 << 19 )
7895#define ISPR0_SPI1_DIS (0x0 << 19 ) /* DIS */
7896#define ISPR0_SPI1_EN (0x1 << 19 ) /* EN */
7897
7898/* ISPR0[SPI0] - */
7899#define ISPR0_SPI0_MSK (0x1 << 18 )
7900#define ISPR0_SPI0 (0x1 << 18 )
7901#define ISPR0_SPI0_DIS (0x0 << 18 ) /* DIS */
7902#define ISPR0_SPI0_EN (0x1 << 18 ) /* EN */
7903
7904/* ISPR0[UART] - */
7905#define ISPR0_UART_MSK (0x1 << 17 )
7906#define ISPR0_UART (0x1 << 17 )
7907#define ISPR0_UART_DIS (0x0 << 17 ) /* DIS */
7908#define ISPR0_UART_EN (0x1 << 17 ) /* EN */
7909
7910/* ISPR0[FEE] - */
7911#define ISPR0_FEE_MSK (0x1 << 16 )
7912#define ISPR0_FEE (0x1 << 16 )
7913#define ISPR0_FEE_DIS (0x0 << 16 ) /* DIS */
7914#define ISPR0_FEE_EN (0x1 << 16 ) /* EN */
7915
7916/* ISPR0[SINC2] - */
7917#define ISPR0_SINC2_MSK (0x1 << 15 )
7918#define ISPR0_SINC2 (0x1 << 15 )
7919#define ISPR0_SINC2_DIS (0x0 << 15 ) /* DIS */
7920#define ISPR0_SINC2_EN (0x1 << 15 ) /* EN */
7921
7922/* ISPR0[ADC1] - */
7923#define ISPR0_ADC1_MSK (0x1 << 14 )
7924#define ISPR0_ADC1 (0x1 << 14 )
7925#define ISPR0_ADC1_DIS (0x0 << 14 ) /* DIS */
7926#define ISPR0_ADC1_EN (0x1 << 14 ) /* EN */
7927
7928/* ISPR0[ADC0] - */
7929#define ISPR0_ADC0_MSK (0x1 << 13 )
7930#define ISPR0_ADC0 (0x1 << 13 )
7931#define ISPR0_ADC0_DIS (0x0 << 13 ) /* DIS */
7932#define ISPR0_ADC0_EN (0x1 << 13 ) /* EN */
7933
7934/* ISPR0[T1] - */
7935#define ISPR0_T1_MSK (0x1 << 12 )
7936#define ISPR0_T1 (0x1 << 12 )
7937#define ISPR0_T1_DIS (0x0 << 12 ) /* DIS */
7938#define ISPR0_T1_EN (0x1 << 12 ) /* EN */
7939
7940/* ISPR0[T0] - */
7941#define ISPR0_T0_MSK (0x1 << 11 )
7942#define ISPR0_T0 (0x1 << 11 )
7943#define ISPR0_T0_DIS (0x0 << 11 ) /* DIS */
7944#define ISPR0_T0_EN (0x1 << 11 ) /* EN */
7945
7946/* ISPR0[T3] - */
7947#define ISPR0_T3_MSK (0x1 << 9 )
7948#define ISPR0_T3 (0x1 << 9 )
7949#define ISPR0_T3_DIS (0x0 << 9 ) /* DIS */
7950#define ISPR0_T3_EN (0x1 << 9 ) /* EN */
7951
7952/* ISPR0[EXTINT7] - */
7953#define ISPR0_EXTINT7_MSK (0x1 << 8 )
7954#define ISPR0_EXTINT7 (0x1 << 8 )
7955#define ISPR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
7956#define ISPR0_EXTINT7_EN (0x1 << 8 ) /* EN */
7957
7958/* ISPR0[EXTINT6] - */
7959#define ISPR0_EXTINT6_MSK (0x1 << 7 )
7960#define ISPR0_EXTINT6 (0x1 << 7 )
7961#define ISPR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
7962#define ISPR0_EXTINT6_EN (0x1 << 7 ) /* EN */
7963
7964/* ISPR0[EXTINT5] - */
7965#define ISPR0_EXTINT5_MSK (0x1 << 6 )
7966#define ISPR0_EXTINT5 (0x1 << 6 )
7967#define ISPR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
7968#define ISPR0_EXTINT5_EN (0x1 << 6 ) /* EN */
7969
7970/* ISPR0[EXTINT4] - */
7971#define ISPR0_EXTINT4_MSK (0x1 << 5 )
7972#define ISPR0_EXTINT4 (0x1 << 5 )
7973#define ISPR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
7974#define ISPR0_EXTINT4_EN (0x1 << 5 ) /* EN */
7975
7976/* ISPR0[EXTINT3] - */
7977#define ISPR0_EXTINT3_MSK (0x1 << 4 )
7978#define ISPR0_EXTINT3 (0x1 << 4 )
7979#define ISPR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
7980#define ISPR0_EXTINT3_EN (0x1 << 4 ) /* EN */
7981
7982/* ISPR0[EXTINT2] - */
7983#define ISPR0_EXTINT2_MSK (0x1 << 3 )
7984#define ISPR0_EXTINT2 (0x1 << 3 )
7985#define ISPR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
7986#define ISPR0_EXTINT2_EN (0x1 << 3 ) /* EN */
7987
7988/* ISPR0[EXTINT1] - */
7989#define ISPR0_EXTINT1_MSK (0x1 << 2 )
7990#define ISPR0_EXTINT1 (0x1 << 2 )
7991#define ISPR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
7992#define ISPR0_EXTINT1_EN (0x1 << 2 ) /* EN */
7993
7994/* ISPR0[EXTINT0] - */
7995#define ISPR0_EXTINT0_MSK (0x1 << 1 )
7996#define ISPR0_EXTINT0 (0x1 << 1 )
7997#define ISPR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
7998#define ISPR0_EXTINT0_EN (0x1 << 1 ) /* EN */
7999
8000/* ISPR0[T2] - */
8001#define ISPR0_T2_MSK (0x1 << 0 )
8002#define ISPR0_T2 (0x1 << 0 )
8003#define ISPR0_T2_DIS (0x0 << 0 ) /* DIS */
8004#define ISPR0_T2_EN (0x1 << 0 ) /* EN */
8005
8006/* Reset Value for ISPR1*/
8007#define ISPR1_RVAL 0x0
8008
8009/* ISPR1[PWM2] - */
8010#define ISPR1_PWM2_MSK (0x1 << 6 )
8011#define ISPR1_PWM2 (0x1 << 6 )
8012#define ISPR1_PWM2_DIS (0x0 << 6 ) /* DIS */
8013#define ISPR1_PWM2_EN (0x1 << 6 ) /* EN */
8014
8015/* ISPR1[PWM1] - */
8016#define ISPR1_PWM1_MSK (0x1 << 5 )
8017#define ISPR1_PWM1 (0x1 << 5 )
8018#define ISPR1_PWM1_DIS (0x0 << 5 ) /* DIS */
8019#define ISPR1_PWM1_EN (0x1 << 5 ) /* EN */
8020
8021/* ISPR1[PWM0] - */
8022#define ISPR1_PWM0_MSK (0x1 << 4 )
8023#define ISPR1_PWM0 (0x1 << 4 )
8024#define ISPR1_PWM0_DIS (0x0 << 4 ) /* DIS */
8025#define ISPR1_PWM0_EN (0x1 << 4 ) /* EN */
8026
8027/* ISPR1[PWMTRIP] - */
8028#define ISPR1_PWMTRIP_MSK (0x1 << 3 )
8029#define ISPR1_PWMTRIP (0x1 << 3 )
8030#define ISPR1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
8031#define ISPR1_PWMTRIP_EN (0x1 << 3 ) /* EN */
8032
8033/* ISPR1[DMASINC2] - */
8034#define ISPR1_DMASINC2_MSK (0x1 << 2 )
8035#define ISPR1_DMASINC2 (0x1 << 2 )
8036#define ISPR1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
8037#define ISPR1_DMASINC2_EN (0x1 << 2 ) /* EN */
8038
8039/* ISPR1[DMAADC1] - */
8040#define ISPR1_DMAADC1_MSK (0x1 << 1 )
8041#define ISPR1_DMAADC1 (0x1 << 1 )
8042#define ISPR1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
8043#define ISPR1_DMAADC1_EN (0x1 << 1 ) /* EN */
8044
8045/* ISPR1[DMAADC0] - */
8046#define ISPR1_DMAADC0_MSK (0x1 << 0 )
8047#define ISPR1_DMAADC0 (0x1 << 0 )
8048#define ISPR1_DMAADC0_DIS (0x0 << 0 ) /* DIS */
8049#define ISPR1_DMAADC0_EN (0x1 << 0 ) /* EN */
8050
8051/* Reset Value for ICPR0*/
8052#define ICPR0_RVAL 0x0
8053
8054/* ICPR0[DMADAC] - */
8055#define ICPR0_DMADAC_MSK (0x1 << 31 )
8056#define ICPR0_DMADAC (0x1 << 31 )
8057#define ICPR0_DMADAC_DIS (0x0 << 31 ) /* DIS */
8058#define ICPR0_DMADAC_EN (0x1 << 31 ) /* EN */
8059
8060/* ICPR0[DMAI2CMRX] - */
8061#define ICPR0_DMAI2CMRX_MSK (0x1 << 30 )
8062#define ICPR0_DMAI2CMRX (0x1 << 30 )
8063#define ICPR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
8064#define ICPR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
8065
8066/* ICPR0[DMAI2CMTX] - */
8067#define ICPR0_DMAI2CMTX_MSK (0x1 << 29 )
8068#define ICPR0_DMAI2CMTX (0x1 << 29 )
8069#define ICPR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
8070#define ICPR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
8071
8072/* ICPR0[DMAI2CSRX] - */
8073#define ICPR0_DMAI2CSRX_MSK (0x1 << 28 )
8074#define ICPR0_DMAI2CSRX (0x1 << 28 )
8075#define ICPR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
8076#define ICPR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
8077
8078/* ICPR0[DMAI2CSTX] - */
8079#define ICPR0_DMAI2CSTX_MSK (0x1 << 27 )
8080#define ICPR0_DMAI2CSTX (0x1 << 27 )
8081#define ICPR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
8082#define ICPR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
8083
8084/* ICPR0[DMAUARTRX] - */
8085#define ICPR0_DMAUARTRX_MSK (0x1 << 26 )
8086#define ICPR0_DMAUARTRX (0x1 << 26 )
8087#define ICPR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
8088#define ICPR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
8089
8090/* ICPR0[DMAUARTTX] - */
8091#define ICPR0_DMAUARTTX_MSK (0x1 << 25 )
8092#define ICPR0_DMAUARTTX (0x1 << 25 )
8093#define ICPR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
8094#define ICPR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
8095
8096/* ICPR0[DMASPI1RX] - */
8097#define ICPR0_DMASPI1RX_MSK (0x1 << 24 )
8098#define ICPR0_DMASPI1RX (0x1 << 24 )
8099#define ICPR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
8100#define ICPR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
8101
8102/* ICPR0[DMASPI1TX] - */
8103#define ICPR0_DMASPI1TX_MSK (0x1 << 23 )
8104#define ICPR0_DMASPI1TX (0x1 << 23 )
8105#define ICPR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
8106#define ICPR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
8107
8108/* ICPR0[DMAERROR] - */
8109#define ICPR0_DMAERROR_MSK (0x1 << 22 )
8110#define ICPR0_DMAERROR (0x1 << 22 )
8111#define ICPR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
8112#define ICPR0_DMAERROR_EN (0x1 << 22 ) /* EN */
8113
8114/* ICPR0[I2CM] - */
8115#define ICPR0_I2CM_MSK (0x1 << 21 )
8116#define ICPR0_I2CM (0x1 << 21 )
8117#define ICPR0_I2CM_DIS (0x0 << 21 ) /* DIS */
8118#define ICPR0_I2CM_EN (0x1 << 21 ) /* EN */
8119
8120/* ICPR0[I2CS] - */
8121#define ICPR0_I2CS_MSK (0x1 << 20 )
8122#define ICPR0_I2CS (0x1 << 20 )
8123#define ICPR0_I2CS_DIS (0x0 << 20 ) /* DIS */
8124#define ICPR0_I2CS_EN (0x1 << 20 ) /* EN */
8125
8126/* ICPR0[SPI1] - */
8127#define ICPR0_SPI1_MSK (0x1 << 19 )
8128#define ICPR0_SPI1 (0x1 << 19 )
8129#define ICPR0_SPI1_DIS (0x0 << 19 ) /* DIS */
8130#define ICPR0_SPI1_EN (0x1 << 19 ) /* EN */
8131
8132/* ICPR0[SPI0] - */
8133#define ICPR0_SPI0_MSK (0x1 << 18 )
8134#define ICPR0_SPI0 (0x1 << 18 )
8135#define ICPR0_SPI0_DIS (0x0 << 18 ) /* DIS */
8136#define ICPR0_SPI0_EN (0x1 << 18 ) /* EN */
8137
8138/* ICPR0[UART] - */
8139#define ICPR0_UART_MSK (0x1 << 17 )
8140#define ICPR0_UART (0x1 << 17 )
8141#define ICPR0_UART_DIS (0x0 << 17 ) /* DIS */
8142#define ICPR0_UART_EN (0x1 << 17 ) /* EN */
8143
8144/* ICPR0[FEE] - */
8145#define ICPR0_FEE_MSK (0x1 << 16 )
8146#define ICPR0_FEE (0x1 << 16 )
8147#define ICPR0_FEE_DIS (0x0 << 16 ) /* DIS */
8148#define ICPR0_FEE_EN (0x1 << 16 ) /* EN */
8149
8150/* ICPR0[SINC2] - */
8151#define ICPR0_SINC2_MSK (0x1 << 15 )
8152#define ICPR0_SINC2 (0x1 << 15 )
8153#define ICPR0_SINC2_DIS (0x0 << 15 ) /* DIS */
8154#define ICPR0_SINC2_EN (0x1 << 15 ) /* EN */
8155
8156/* ICPR0[ADC1] - */
8157#define ICPR0_ADC1_MSK (0x1 << 14 )
8158#define ICPR0_ADC1 (0x1 << 14 )
8159#define ICPR0_ADC1_DIS (0x0 << 14 ) /* DIS */
8160#define ICPR0_ADC1_EN (0x1 << 14 ) /* EN */
8161
8162/* ICPR0[ADC0] - */
8163#define ICPR0_ADC0_MSK (0x1 << 13 )
8164#define ICPR0_ADC0 (0x1 << 13 )
8165#define ICPR0_ADC0_DIS (0x0 << 13 ) /* DIS */
8166#define ICPR0_ADC0_EN (0x1 << 13 ) /* EN */
8167
8168/* ICPR0[T1] - */
8169#define ICPR0_T1_MSK (0x1 << 12 )
8170#define ICPR0_T1 (0x1 << 12 )
8171#define ICPR0_T1_DIS (0x0 << 12 ) /* DIS */
8172#define ICPR0_T1_EN (0x1 << 12 ) /* EN */
8173
8174/* ICPR0[T0] - */
8175#define ICPR0_T0_MSK (0x1 << 11 )
8176#define ICPR0_T0 (0x1 << 11 )
8177#define ICPR0_T0_DIS (0x0 << 11 ) /* DIS */
8178#define ICPR0_T0_EN (0x1 << 11 ) /* EN */
8179
8180/* ICPR0[T3] - */
8181#define ICPR0_T3_MSK (0x1 << 9 )
8182#define ICPR0_T3 (0x1 << 9 )
8183#define ICPR0_T3_DIS (0x0 << 9 ) /* DIS */
8184#define ICPR0_T3_EN (0x1 << 9 ) /* EN */
8185
8186/* ICPR0[EXTINT7] - */
8187#define ICPR0_EXTINT7_MSK (0x1 << 8 )
8188#define ICPR0_EXTINT7 (0x1 << 8 )
8189#define ICPR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
8190#define ICPR0_EXTINT7_EN (0x1 << 8 ) /* EN */
8191
8192/* ICPR0[EXTINT6] - */
8193#define ICPR0_EXTINT6_MSK (0x1 << 7 )
8194#define ICPR0_EXTINT6 (0x1 << 7 )
8195#define ICPR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
8196#define ICPR0_EXTINT6_EN (0x1 << 7 ) /* EN */
8197
8198/* ICPR0[EXTINT5] - */
8199#define ICPR0_EXTINT5_MSK (0x1 << 6 )
8200#define ICPR0_EXTINT5 (0x1 << 6 )
8201#define ICPR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
8202#define ICPR0_EXTINT5_EN (0x1 << 6 ) /* EN */
8203
8204/* ICPR0[EXTINT4] - */
8205#define ICPR0_EXTINT4_MSK (0x1 << 5 )
8206#define ICPR0_EXTINT4 (0x1 << 5 )
8207#define ICPR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
8208#define ICPR0_EXTINT4_EN (0x1 << 5 ) /* EN */
8209
8210/* ICPR0[EXTINT3] - */
8211#define ICPR0_EXTINT3_MSK (0x1 << 4 )
8212#define ICPR0_EXTINT3 (0x1 << 4 )
8213#define ICPR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
8214#define ICPR0_EXTINT3_EN (0x1 << 4 ) /* EN */
8215
8216/* ICPR0[EXTINT2] - */
8217#define ICPR0_EXTINT2_MSK (0x1 << 3 )
8218#define ICPR0_EXTINT2 (0x1 << 3 )
8219#define ICPR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
8220#define ICPR0_EXTINT2_EN (0x1 << 3 ) /* EN */
8221
8222/* ICPR0[EXTINT1] - */
8223#define ICPR0_EXTINT1_MSK (0x1 << 2 )
8224#define ICPR0_EXTINT1 (0x1 << 2 )
8225#define ICPR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
8226#define ICPR0_EXTINT1_EN (0x1 << 2 ) /* EN */
8227
8228/* ICPR0[EXTINT0] - */
8229#define ICPR0_EXTINT0_MSK (0x1 << 1 )
8230#define ICPR0_EXTINT0 (0x1 << 1 )
8231#define ICPR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
8232#define ICPR0_EXTINT0_EN (0x1 << 1 ) /* EN */
8233
8234/* ICPR0[T2] - */
8235#define ICPR0_T2_MSK (0x1 << 0 )
8236#define ICPR0_T2 (0x1 << 0 )
8237#define ICPR0_T2_DIS (0x0 << 0 ) /* DIS */
8238#define ICPR0_T2_EN (0x1 << 0 ) /* EN */
8239
8240/* Reset Value for ICPR1*/
8241#define ICPR1_RVAL 0x0
8242
8243/* ICPR1[PWM2] - */
8244#define ICPR1_PWM2_MSK (0x1 << 6 )
8245#define ICPR1_PWM2 (0x1 << 6 )
8246#define ICPR1_PWM2_DIS (0x0 << 6 ) /* DIS */
8247#define ICPR1_PWM2_EN (0x1 << 6 ) /* EN */
8248
8249/* ICPR1[PWM1] - */
8250#define ICPR1_PWM1_MSK (0x1 << 5 )
8251#define ICPR1_PWM1 (0x1 << 5 )
8252#define ICPR1_PWM1_DIS (0x0 << 5 ) /* DIS */
8253#define ICPR1_PWM1_EN (0x1 << 5 ) /* EN */
8254
8255/* ICPR1[PWM0] - */
8256#define ICPR1_PWM0_MSK (0x1 << 4 )
8257#define ICPR1_PWM0 (0x1 << 4 )
8258#define ICPR1_PWM0_DIS (0x0 << 4 ) /* DIS */
8259#define ICPR1_PWM0_EN (0x1 << 4 ) /* EN */
8260
8261/* ICPR1[PWMTRIP] - */
8262#define ICPR1_PWMTRIP_MSK (0x1 << 3 )
8263#define ICPR1_PWMTRIP (0x1 << 3 )
8264#define ICPR1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
8265#define ICPR1_PWMTRIP_EN (0x1 << 3 ) /* EN */
8266
8267/* ICPR1[DMASINC2] - */
8268#define ICPR1_DMASINC2_MSK (0x1 << 2 )
8269#define ICPR1_DMASINC2 (0x1 << 2 )
8270#define ICPR1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
8271#define ICPR1_DMASINC2_EN (0x1 << 2 ) /* EN */
8272
8273/* ICPR1[DMAADC1] - */
8274#define ICPR1_DMAADC1_MSK (0x1 << 1 )
8275#define ICPR1_DMAADC1 (0x1 << 1 )
8276#define ICPR1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
8277#define ICPR1_DMAADC1_EN (0x1 << 1 ) /* EN */
8278
8279/* ICPR1[DMAADC0] - */
8280#define ICPR1_DMAADC0_MSK (0x1 << 0 )
8281#define ICPR1_DMAADC0 (0x1 << 0 )
8282#define ICPR1_DMAADC0_DIS (0x0 << 0 ) /* DIS */
8283#define ICPR1_DMAADC0_EN (0x1 << 0 ) /* EN */
8284
8285/* Reset Value for IABR0*/
8286#define IABR0_RVAL 0x0
8287
8288/* IABR0[DMADAC] - */
8289#define IABR0_DMADAC_MSK (0x1 << 31 )
8290#define IABR0_DMADAC (0x1 << 31 )
8291#define IABR0_DMADAC_DIS (0x0 << 31 ) /* DIS */
8292#define IABR0_DMADAC_EN (0x1 << 31 ) /* EN */
8293
8294/* IABR0[DMAI2CMRX] - */
8295#define IABR0_DMAI2CMRX_MSK (0x1 << 30 )
8296#define IABR0_DMAI2CMRX (0x1 << 30 )
8297#define IABR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
8298#define IABR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
8299
8300/* IABR0[DMAI2CMTX] - */
8301#define IABR0_DMAI2CMTX_MSK (0x1 << 29 )
8302#define IABR0_DMAI2CMTX (0x1 << 29 )
8303#define IABR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
8304#define IABR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
8305
8306/* IABR0[DMAI2CSRX] - */
8307#define IABR0_DMAI2CSRX_MSK (0x1 << 28 )
8308#define IABR0_DMAI2CSRX (0x1 << 28 )
8309#define IABR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
8310#define IABR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
8311
8312/* IABR0[DMAI2CSTX] - */
8313#define IABR0_DMAI2CSTX_MSK (0x1 << 27 )
8314#define IABR0_DMAI2CSTX (0x1 << 27 )
8315#define IABR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
8316#define IABR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
8317
8318/* IABR0[DMAUARTRX] - */
8319#define IABR0_DMAUARTRX_MSK (0x1 << 26 )
8320#define IABR0_DMAUARTRX (0x1 << 26 )
8321#define IABR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
8322#define IABR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
8323
8324/* IABR0[DMAUARTTX] - */
8325#define IABR0_DMAUARTTX_MSK (0x1 << 25 )
8326#define IABR0_DMAUARTTX (0x1 << 25 )
8327#define IABR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
8328#define IABR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
8329
8330/* IABR0[DMASPI1RX] - */
8331#define IABR0_DMASPI1RX_MSK (0x1 << 24 )
8332#define IABR0_DMASPI1RX (0x1 << 24 )
8333#define IABR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
8334#define IABR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
8335
8336/* IABR0[DMASPI1TX] - */
8337#define IABR0_DMASPI1TX_MSK (0x1 << 23 )
8338#define IABR0_DMASPI1TX (0x1 << 23 )
8339#define IABR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
8340#define IABR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
8341
8342/* IABR0[DMAERROR] - */
8343#define IABR0_DMAERROR_MSK (0x1 << 22 )
8344#define IABR0_DMAERROR (0x1 << 22 )
8345#define IABR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
8346#define IABR0_DMAERROR_EN (0x1 << 22 ) /* EN */
8347
8348/* IABR0[I2CM] - */
8349#define IABR0_I2CM_MSK (0x1 << 21 )
8350#define IABR0_I2CM (0x1 << 21 )
8351#define IABR0_I2CM_DIS (0x0 << 21 ) /* DIS */
8352#define IABR0_I2CM_EN (0x1 << 21 ) /* EN */
8353
8354/* IABR0[I2CS] - */
8355#define IABR0_I2CS_MSK (0x1 << 20 )
8356#define IABR0_I2CS (0x1 << 20 )
8357#define IABR0_I2CS_DIS (0x0 << 20 ) /* DIS */
8358#define IABR0_I2CS_EN (0x1 << 20 ) /* EN */
8359
8360/* IABR0[SPI1] - */
8361#define IABR0_SPI1_MSK (0x1 << 19 )
8362#define IABR0_SPI1 (0x1 << 19 )
8363#define IABR0_SPI1_DIS (0x0 << 19 ) /* DIS */
8364#define IABR0_SPI1_EN (0x1 << 19 ) /* EN */
8365
8366/* IABR0[SPI0] - */
8367#define IABR0_SPI0_MSK (0x1 << 18 )
8368#define IABR0_SPI0 (0x1 << 18 )
8369#define IABR0_SPI0_DIS (0x0 << 18 ) /* DIS */
8370#define IABR0_SPI0_EN (0x1 << 18 ) /* EN */
8371
8372/* IABR0[UART] - */
8373#define IABR0_UART_MSK (0x1 << 17 )
8374#define IABR0_UART (0x1 << 17 )
8375#define IABR0_UART_DIS (0x0 << 17 ) /* DIS */
8376#define IABR0_UART_EN (0x1 << 17 ) /* EN */
8377
8378/* IABR0[FEE] - */
8379#define IABR0_FEE_MSK (0x1 << 16 )
8380#define IABR0_FEE (0x1 << 16 )
8381#define IABR0_FEE_DIS (0x0 << 16 ) /* DIS */
8382#define IABR0_FEE_EN (0x1 << 16 ) /* EN */
8383
8384/* IABR0[SINC2] - */
8385#define IABR0_SINC2_MSK (0x1 << 15 )
8386#define IABR0_SINC2 (0x1 << 15 )
8387#define IABR0_SINC2_DIS (0x0 << 15 ) /* DIS */
8388#define IABR0_SINC2_EN (0x1 << 15 ) /* EN */
8389
8390/* IABR0[ADC1] - */
8391#define IABR0_ADC1_MSK (0x1 << 14 )
8392#define IABR0_ADC1 (0x1 << 14 )
8393#define IABR0_ADC1_DIS (0x0 << 14 ) /* DIS */
8394#define IABR0_ADC1_EN (0x1 << 14 ) /* EN */
8395
8396/* IABR0[ADC0] - */
8397#define IABR0_ADC0_MSK (0x1 << 13 )
8398#define IABR0_ADC0 (0x1 << 13 )
8399#define IABR0_ADC0_DIS (0x0 << 13 ) /* DIS */
8400#define IABR0_ADC0_EN (0x1 << 13 ) /* EN */
8401
8402/* IABR0[T1] - */
8403#define IABR0_T1_MSK (0x1 << 12 )
8404#define IABR0_T1 (0x1 << 12 )
8405#define IABR0_T1_DIS (0x0 << 12 ) /* DIS */
8406#define IABR0_T1_EN (0x1 << 12 ) /* EN */
8407
8408/* IABR0[T0] - */
8409#define IABR0_T0_MSK (0x1 << 11 )
8410#define IABR0_T0 (0x1 << 11 )
8411#define IABR0_T0_DIS (0x0 << 11 ) /* DIS */
8412#define IABR0_T0_EN (0x1 << 11 ) /* EN */
8413
8414/* IABR0[T3] - */
8415#define IABR0_T3_MSK (0x1 << 9 )
8416#define IABR0_T3 (0x1 << 9 )
8417#define IABR0_T3_DIS (0x0 << 9 ) /* DIS */
8418#define IABR0_T3_EN (0x1 << 9 ) /* EN */
8419
8420/* IABR0[EXTINT7] - */
8421#define IABR0_EXTINT7_MSK (0x1 << 8 )
8422#define IABR0_EXTINT7 (0x1 << 8 )
8423#define IABR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
8424#define IABR0_EXTINT7_EN (0x1 << 8 ) /* EN */
8425
8426/* IABR0[EXTINT6] - */
8427#define IABR0_EXTINT6_MSK (0x1 << 7 )
8428#define IABR0_EXTINT6 (0x1 << 7 )
8429#define IABR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
8430#define IABR0_EXTINT6_EN (0x1 << 7 ) /* EN */
8431
8432/* IABR0[EXTINT5] - */
8433#define IABR0_EXTINT5_MSK (0x1 << 6 )
8434#define IABR0_EXTINT5 (0x1 << 6 )
8435#define IABR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
8436#define IABR0_EXTINT5_EN (0x1 << 6 ) /* EN */
8437
8438/* IABR0[EXTINT4] - */
8439#define IABR0_EXTINT4_MSK (0x1 << 5 )
8440#define IABR0_EXTINT4 (0x1 << 5 )
8441#define IABR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
8442#define IABR0_EXTINT4_EN (0x1 << 5 ) /* EN */
8443
8444/* IABR0[EXTINT3] - */
8445#define IABR0_EXTINT3_MSK (0x1 << 4 )
8446#define IABR0_EXTINT3 (0x1 << 4 )
8447#define IABR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
8448#define IABR0_EXTINT3_EN (0x1 << 4 ) /* EN */
8449
8450/* IABR0[EXTINT2] - */
8451#define IABR0_EXTINT2_MSK (0x1 << 3 )
8452#define IABR0_EXTINT2 (0x1 << 3 )
8453#define IABR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
8454#define IABR0_EXTINT2_EN (0x1 << 3 ) /* EN */
8455
8456/* IABR0[EXTINT1] - */
8457#define IABR0_EXTINT1_MSK (0x1 << 2 )
8458#define IABR0_EXTINT1 (0x1 << 2 )
8459#define IABR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
8460#define IABR0_EXTINT1_EN (0x1 << 2 ) /* EN */
8461
8462/* IABR0[EXTINT0] - */
8463#define IABR0_EXTINT0_MSK (0x1 << 1 )
8464#define IABR0_EXTINT0 (0x1 << 1 )
8465#define IABR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
8466#define IABR0_EXTINT0_EN (0x1 << 1 ) /* EN */
8467
8468/* IABR0[T2] - */
8469#define IABR0_T2_MSK (0x1 << 0 )
8470#define IABR0_T2 (0x1 << 0 )
8471#define IABR0_T2_DIS (0x0 << 0 ) /* DIS */
8472#define IABR0_T2_EN (0x1 << 0 ) /* EN */
8473
8474/* Reset Value for IABR1*/
8475#define IABR1_RVAL 0x0
8476
8477/* IABR1[PWM2] - */
8478#define IABR1_PWM2_MSK (0x1 << 6 )
8479#define IABR1_PWM2 (0x1 << 6 )
8480#define IABR1_PWM2_DIS (0x0 << 6 ) /* DIS */
8481#define IABR1_PWM2_EN (0x1 << 6 ) /* EN */
8482
8483/* IABR1[PWM1] - */
8484#define IABR1_PWM1_MSK (0x1 << 5 )
8485#define IABR1_PWM1 (0x1 << 5 )
8486#define IABR1_PWM1_DIS (0x0 << 5 ) /* DIS */
8487#define IABR1_PWM1_EN (0x1 << 5 ) /* EN */
8488
8489/* IABR1[PWM0] - */
8490#define IABR1_PWM0_MSK (0x1 << 4 )
8491#define IABR1_PWM0 (0x1 << 4 )
8492#define IABR1_PWM0_DIS (0x0 << 4 ) /* DIS */
8493#define IABR1_PWM0_EN (0x1 << 4 ) /* EN */
8494
8495/* IABR1[PWMTRIP] - */
8496#define IABR1_PWMTRIP_MSK (0x1 << 3 )
8497#define IABR1_PWMTRIP (0x1 << 3 )
8498#define IABR1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
8499#define IABR1_PWMTRIP_EN (0x1 << 3 ) /* EN */
8500
8501/* IABR1[DMASINC2] - */
8502#define IABR1_DMASINC2_MSK (0x1 << 2 )
8503#define IABR1_DMASINC2 (0x1 << 2 )
8504#define IABR1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
8505#define IABR1_DMASINC2_EN (0x1 << 2 ) /* EN */
8506
8507/* IABR1[DMAADC1] - */
8508#define IABR1_DMAADC1_MSK (0x1 << 1 )
8509#define IABR1_DMAADC1 (0x1 << 1 )
8510#define IABR1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
8511#define IABR1_DMAADC1_EN (0x1 << 1 ) /* EN */
8512
8513/* IABR1[DMAADC0] - */
8514#define IABR1_DMAADC0_MSK (0x1 << 0 )
8515#define IABR1_DMAADC0 (0x1 << 0 )
8516#define IABR1_DMAADC0_DIS (0x0 << 0 ) /* DIS */
8517#define IABR1_DMAADC0_EN (0x1 << 0 ) /* EN */
8518
8519/* Reset Value for IPR0*/
8520#define IPR0_RVAL 0x0
8521
8522/* IPR0[EXTINT2] - */
8523#define IPR0_EXTINT2_MSK (0xFF << 24 )
8524
8525/* IPR0[EXTINT1] - */
8526#define IPR0_EXTINT1_MSK (0xFF << 16 )
8527
8528/* IPR0[EXTINT0] - Priority of interrupt number 1 */
8529#define IPR0_EXTINT0_MSK (0xFF << 8 )
8530
8531/* IPR0[T2] - Priority of interrupt number 0 */
8532#define IPR0_T2_MSK (0xFF << 0 )
8533
8534/* Reset Value for IPR1*/
8535#define IPR1_RVAL 0x0
8536
8537/* IPR1[EXTINT6] - */
8538#define IPR1_EXTINT6_MSK (0xFF << 24 )
8539
8540/* IPR1[EXTINT5] - */
8541#define IPR1_EXTINT5_MSK (0xFF << 16 )
8542
8543/* IPR1[EXTINT4] - */
8544#define IPR1_EXTINT4_MSK (0xFF << 8 )
8545
8546/* IPR1[EXTINT3] - */
8547#define IPR1_EXTINT3_MSK (0xFF << 0 )
8548
8549/* Reset Value for IPR2*/
8550#define IPR2_RVAL 0x0
8551
8552/* IPR2[T0] - */
8553#define IPR2_T0_MSK (0xFF << 24 )
8554
8555/* IPR2[T3] - */
8556#define IPR2_T3_MSK (0xFF << 8 )
8557
8558/* IPR2[EXTINT7] - */
8559#define IPR2_EXTINT7_MSK (0xFF << 0 )
8560
8561/* Reset Value for IPR3*/
8562#define IPR3_RVAL 0x0
8563
8564/* IPR3[SINC2] - */
8565#define IPR3_SINC2_MSK (0xFF << 24 )
8566
8567/* IPR3[ADC1] - */
8568#define IPR3_ADC1_MSK (0xFF << 16 )
8569
8570/* IPR3[ADC0] - */
8571#define IPR3_ADC0_MSK (0xFF << 8 )
8572
8573/* IPR3[T1] - */
8574#define IPR3_T1_MSK (0xFF << 0 )
8575
8576/* Reset Value for IPR4*/
8577#define IPR4_RVAL 0x0
8578
8579/* IPR4[SPI1] - */
8580#define IPR4_SPI1_MSK (0xFF << 24 )
8581
8582/* IPR4[SPI0] - */
8583#define IPR4_SPI0_MSK (0xFF << 16 )
8584
8585/* IPR4[UART] - */
8586#define IPR4_UART_MSK (0xFF << 8 )
8587
8588/* IPR4[FEE] - */
8589#define IPR4_FEE_MSK (0xFF << 0 )
8590
8591/* Reset Value for IPR5*/
8592#define IPR5_RVAL 0x0
8593
8594/* IPR5[DMASPI1TX] - */
8595#define IPR5_DMASPI1TX_MSK (0xFF << 24 )
8596
8597/* IPR5[DMAERROR] - */
8598#define IPR5_DMAERROR_MSK (0xFF << 16 )
8599
8600/* IPR5[I2CM] - */
8601#define IPR5_I2CM_MSK (0xFF << 8 )
8602
8603/* IPR5[I2CS] - */
8604#define IPR5_I2CS_MSK (0xFF << 0 )
8605
8606/* Reset Value for IPR6*/
8607#define IPR6_RVAL 0x0
8608
8609/* IPR6[DMAI2CSTX] - */
8610#define IPR6_DMAI2CSTX_MSK (0xFF << 24 )
8611
8612/* IPR6[DMAUARTRX] - */
8613#define IPR6_DMAUARTRX_MSK (0xFF << 16 )
8614
8615/* IPR6[DMAUARTTX] - */
8616#define IPR6_DMAUARTTX_MSK (0xFF << 8 )
8617
8618/* IPR6[DMASPI1RX] - */
8619#define IPR6_DMASPI1RX_MSK (0xFF << 0 )
8620
8621/* Reset Value for IPR7*/
8622#define IPR7_RVAL 0x0
8623
8624/* IPR7[DMADAC] - */
8625#define IPR7_DMADAC_MSK (0xFF << 24 )
8626
8627/* IPR7[DMAI2CMRX] - */
8628#define IPR7_DMAI2CMRX_MSK (0xFF << 16 )
8629
8630/* IPR7[DMAI2CMTX] - */
8631#define IPR7_DMAI2CMTX_MSK (0xFF << 8 )
8632
8633/* IPR7[DMAI2CSRX] - */
8634#define IPR7_DMAI2CSRX_MSK (0xFF << 0 )
8635
8636/* Reset Value for IPR8*/
8637#define IPR8_RVAL 0x0
8638
8639/* IPR8[PWMTRIP] - */
8640#define IPR8_PWMTRIP_MSK (0xFF << 24 )
8641
8642/* IPR8[DMASINC2] - */
8643#define IPR8_DMASINC2_MSK (0xFF << 16 )
8644
8645/* IPR8[DMAADC1] - */
8646#define IPR8_DMAADC1_MSK (0xFF << 8 )
8647
8648/* IPR8[DMAADC0] - */
8649#define IPR8_DMAADC0_MSK (0xFF << 0 )
8650
8651/* Reset Value for IPR9*/
8652#define IPR9_RVAL 0x0
8653
8654/* IPR9[PWM2] - */
8655#define IPR9_PWM2_MSK (0xFF << 16 )
8656
8657/* IPR9[PWM1] - */
8658#define IPR9_PWM1_MSK (0xFF << 8 )
8659
8660/* IPR9[PWM0] - */
8661#define IPR9_PWM0_MSK (0xFF << 0 )
8662
8663/* Reset Value for CPUID*/
8664#define CPUID_RVAL 0x412FC230
8665
8666/* CPUID[IMPLEMENTER] - Indicates implementor */
8667#define CPUID_IMPLEMENTER_MSK (0xFF << 24 )
8668
8669/* CPUID[VARIANT] - Indicates processor revision */
8670#define CPUID_VARIANT_MSK (0xF << 20 )
8671
8672/* CPUID[PARTNO] - Indicates part number */
8673#define CPUID_PARTNO_MSK (0xFFF << 4 )
8674
8675/* CPUID[REVISION] - Indicates patch release */
8676#define CPUID_REVISION_MSK (0xF << 0 )
8677
8678/* Reset Value for ICSR*/
8679#define ICSR_RVAL 0x0
8680
8681/* ICSR[NMIPENDSET] - Setting this bit will activate an NMI */
8682#define ICSR_NMIPENDSET_MSK (0x1 << 31 )
8683#define ICSR_NMIPENDSET (0x1 << 31 )
8684#define ICSR_NMIPENDSET_DIS (0x0 << 31 ) /* DIS */
8685#define ICSR_NMIPENDSET_EN (0x1 << 31 ) /* EN */
8686
8687/* ICSR[PENDSVSET] - Set a pending PendSV interrupt */
8688#define ICSR_PENDSVSET_MSK (0x1 << 28 )
8689#define ICSR_PENDSVSET (0x1 << 28 )
8690#define ICSR_PENDSVSET_DIS (0x0 << 28 ) /* DIS */
8691#define ICSR_PENDSVSET_EN (0x1 << 28 ) /* EN */
8692
8693/* ICSR[PENDSVCLR] - Clear a pending PendSV interrupt */
8694#define ICSR_PENDSVCLR_MSK (0x1 << 27 )
8695#define ICSR_PENDSVCLR (0x1 << 27 )
8696#define ICSR_PENDSVCLR_DIS (0x0 << 27 ) /* DIS */
8697#define ICSR_PENDSVCLR_EN (0x1 << 27 ) /* EN */
8698
8699/* ICSR[PENDSTSET] - Set a pending SysTick. Reads back with current state */
8700#define ICSR_PENDSTSET_MSK (0x1 << 26 )
8701#define ICSR_PENDSTSET (0x1 << 26 )
8702#define ICSR_PENDSTSET_DIS (0x0 << 26 ) /* DIS */
8703#define ICSR_PENDSTSET_EN (0x1 << 26 ) /* EN */
8704
8705/* ICSR[PENDSTCLR] - Clear a pending SysTick */
8706#define ICSR_PENDSTCLR_MSK (0x1 << 25 )
8707#define ICSR_PENDSTCLR (0x1 << 25 )
8708#define ICSR_PENDSTCLR_DIS (0x0 << 25 ) /* DIS */
8709#define ICSR_PENDSTCLR_EN (0x1 << 25 ) /* EN */
8710
8711/* ICSR[ISRPREEMPT] - If set, a pending exception will be serviced on exit from the debug halt state */
8712#define ICSR_ISRPREEMPT_MSK (0x1 << 23 )
8713#define ICSR_ISRPREEMPT (0x1 << 23 )
8714#define ICSR_ISRPREEMPT_DIS (0x0 << 23 ) /* DIS */
8715#define ICSR_ISRPREEMPT_EN (0x1 << 23 ) /* EN */
8716
8717/* ICSR[ISRPENDING] - Indicates if an external configurable is pending */
8718#define ICSR_ISRPENDING_MSK (0x1 << 22 )
8719#define ICSR_ISRPENDING (0x1 << 22 )
8720#define ICSR_ISRPENDING_DIS (0x0 << 22 ) /* DIS */
8721#define ICSR_ISRPENDING_EN (0x1 << 22 ) /* EN */
8722
8723/* ICSR[VECTPENDING] - Indicates the exception number for the highest priority pending exception */
8724#define ICSR_VECTPENDING_MSK (0x1FF << 12 )
8725
8726/* ICSR[RETTOBASE] - */
8727#define ICSR_RETTOBASE_MSK (0x1 << 11 )
8728#define ICSR_RETTOBASE (0x1 << 11 )
8729#define ICSR_RETTOBASE_DIS (0x0 << 11 ) /* DIS */
8730#define ICSR_RETTOBASE_EN (0x1 << 11 ) /* EN */
8731
8732/* ICSR[VECTACTIVE] - Thread mode, or exception number */
8733#define ICSR_VECTACTIVE_MSK (0x1FF << 0 )
8734
8735/* Reset Value for VTOR*/
8736#define VTOR_RVAL 0x0
8737
8738/* VTOR[TBLBASE] - */
8739#define VTOR_TBLBASE_MSK (0x1 << 29 )
8740#define VTOR_TBLBASE (0x1 << 29 )
8741#define VTOR_TBLBASE_DIS (0x0 << 29 ) /* DIS */
8742#define VTOR_TBLBASE_EN (0x1 << 29 ) /* EN */
8743
8744/* VTOR[TBLOFF] - */
8745#define VTOR_TBLOFF_MSK (0x3FFFFF << 7 )
8746
8747/* Reset Value for AIRCR*/
8748#define AIRCR_RVAL 0xFA050000
8749
8750/* AIRCR[VECTKEYSTAT] - Reads as 0xFA05 */
8751#define AIRCR_VECTKEYSTAT_MSK (0xFFFF << 16 )
8752
8753/* AIRCR[ENDIANESS] - This bit is static or configured by a hardware input on reset */
8754#define AIRCR_ENDIANESS_MSK (0x1 << 15 )
8755#define AIRCR_ENDIANESS (0x1 << 15 )
8756#define AIRCR_ENDIANESS_DIS (0x0 << 15 ) /* DIS */
8757#define AIRCR_ENDIANESS_EN (0x1 << 15 ) /* EN */
8758
8759/* AIRCR[PRIGROUP] - Priority grouping position */
8760#define AIRCR_PRIGROUP_MSK (0x7 << 8 )
8761
8762/* AIRCR[SYSRESETREQ] - System Reset Request */
8763#define AIRCR_SYSRESETREQ_MSK (0x1 << 2 )
8764#define AIRCR_SYSRESETREQ (0x1 << 2 )
8765#define AIRCR_SYSRESETREQ_DIS (0x0 << 2 ) /* DIS */
8766#define AIRCR_SYSRESETREQ_EN (0x1 << 2 ) /* EN */
8767
8768/* AIRCR[VECTCLRACTIVE] - Clears all active state information for fixed and configurable exceptions */
8769#define AIRCR_VECTCLRACTIVE_MSK (0x1 << 1 )
8770#define AIRCR_VECTCLRACTIVE (0x1 << 1 )
8771#define AIRCR_VECTCLRACTIVE_DIS (0x0 << 1 ) /* DIS */
8772#define AIRCR_VECTCLRACTIVE_EN (0x1 << 1 ) /* EN */
8773
8774/* AIRCR[VECTRESET] - Local system reset */
8775#define AIRCR_VECTRESET_MSK (0x1 << 0 )
8776#define AIRCR_VECTRESET (0x1 << 0 )
8777#define AIRCR_VECTRESET_DIS (0x0 << 0 ) /* DIS */
8778#define AIRCR_VECTRESET_EN (0x1 << 0 ) /* EN */
8779
8780/* Reset Value for SCR*/
8781#define SCR_RVAL 0x0
8782
8783/* SCR[SEVONPEND] - */
8784#define SCR_SEVONPEND_MSK (0x1 << 4 )
8785#define SCR_SEVONPEND (0x1 << 4 )
8786#define SCR_SEVONPEND_DIS (0x0 << 4 ) /* DIS */
8787#define SCR_SEVONPEND_EN (0x1 << 4 ) /* EN */
8788
8789/* SCR[SLEEPDEEP] - Sleep deep bit */
8790#define SCR_SLEEPDEEP_MSK (0x1 << 2 )
8791#define SCR_SLEEPDEEP (0x1 << 2 )
8792#define SCR_SLEEPDEEP_DIS (0x0 << 2 ) /* DIS */
8793#define SCR_SLEEPDEEP_EN (0x1 << 2 ) /* EN */
8794
8795/* SCR[SLEEPONEXIT] - Sleep on exit when returning from handler mode to thread mode */
8796#define SCR_SLEEPONEXIT_MSK (0x1 << 1 )
8797#define SCR_SLEEPONEXIT (0x1 << 1 )
8798#define SCR_SLEEPONEXIT_DIS (0x0 << 1 ) /* DIS */
8799#define SCR_SLEEPONEXIT_EN (0x1 << 1 ) /* EN */
8800
8801/* Reset Value for CCR*/
8802#define CCR_RVAL 0x200
8803
8804/* CCR[STKALIGN] - */
8805#define CCR_STKALIGN_MSK (0x1 << 9 )
8806#define CCR_STKALIGN (0x1 << 9 )
8807#define CCR_STKALIGN_DIS (0x0 << 9 ) /* DIS */
8808#define CCR_STKALIGN_EN (0x1 << 9 ) /* EN */
8809
8810/* CCR[BFHFNMIGN] - */
8811#define CCR_BFHFNMIGN_MSK (0x1 << 8 )
8812#define CCR_BFHFNMIGN (0x1 << 8 )
8813#define CCR_BFHFNMIGN_DIS (0x0 << 8 ) /* DIS */
8814#define CCR_BFHFNMIGN_EN (0x1 << 8 ) /* EN */
8815
8816/* CCR[DIV0TRP] - */
8817#define CCR_DIV0TRP_MSK (0x1 << 4 )
8818#define CCR_DIV0TRP (0x1 << 4 )
8819#define CCR_DIV0TRP_DIS (0x0 << 4 ) /* DIS */
8820#define CCR_DIV0TRP_EN (0x1 << 4 ) /* EN */
8821
8822/* CCR[UNALIGNTRP] - */
8823#define CCR_UNALIGNTRP_MSK (0x1 << 3 )
8824#define CCR_UNALIGNTRP (0x1 << 3 )
8825#define CCR_UNALIGNTRP_DIS (0x0 << 3 ) /* DIS */
8826#define CCR_UNALIGNTRP_EN (0x1 << 3 ) /* EN */
8827
8828/* CCR[USERSETMPEND] - */
8829#define CCR_USERSETMPEND_MSK (0x1 << 1 )
8830#define CCR_USERSETMPEND (0x1 << 1 )
8831#define CCR_USERSETMPEND_DIS (0x0 << 1 ) /* DIS */
8832#define CCR_USERSETMPEND_EN (0x1 << 1 ) /* EN */
8833
8834/* CCR[NONBASETHRDENA] - */
8835#define CCR_NONBASETHRDENA_MSK (0x1 << 0 )
8836#define CCR_NONBASETHRDENA (0x1 << 0 )
8837#define CCR_NONBASETHRDENA_DIS (0x0 << 0 ) /* DIS */
8838#define CCR_NONBASETHRDENA_EN (0x1 << 0 ) /* EN */
8839
8840/* Reset Value for SHPR1*/
8841#define SHPR1_RVAL 0x0
8842
8843/* SHPR1[PRI7] - Priority of system handler 7 - reserved */
8844#define SHPR1_PRI7_MSK (0xFF << 24 )
8845
8846/* SHPR1[PRI6] - Priority of system handler 6 - UsageFault */
8847#define SHPR1_PRI6_MSK (0xFF << 16 )
8848
8849/* SHPR1[PRI5] - Priority of system handler 5 - BusFault */
8850#define SHPR1_PRI5_MSK (0xFF << 8 )
8851
8852/* SHPR1[PRI4] - Priority of system handler 4 - MemManage */
8853#define SHPR1_PRI4_MSK (0xFF << 0 )
8854
8855/* Reset Value for SHPR2*/
8856#define SHPR2_RVAL 0x0
8857
8858/* SHPR2[PRI11] - Priority of system handler 11 - SVCall */
8859#define SHPR2_PRI11_MSK (0xFF << 24 )
8860
8861/* SHPR2[PRI10] - Priority of system handler 10 - reserved */
8862#define SHPR2_PRI10_MSK (0xFF << 16 )
8863
8864/* SHPR2[PRI9] - Priority of system handler 9 - reserved */
8865#define SHPR2_PRI9_MSK (0xFF << 8 )
8866
8867/* SHPR2[PRI8] - Priority of system handler 8 - reserved */
8868#define SHPR2_PRI8_MSK (0xFF << 0 )
8869
8870/* Reset Value for SHPR3*/
8871#define SHPR3_RVAL 0x0
8872
8873/* SHPR3[PRI15] - Priority of system handler 15 - SysTick */
8874#define SHPR3_PRI15_MSK (0xFF << 24 )
8875
8876/* SHPR3[PRI14] - Priority of system handler 14 - PendSV */
8877#define SHPR3_PRI14_MSK (0xFF << 16 )
8878
8879/* SHPR3[PRI13] - Priority of system handler 13 - reserved */
8880#define SHPR3_PRI13_MSK (0xFF << 8 )
8881
8882/* SHPR3[PRI12] - Priority of system handler 12 - DebugMonitor */
8883#define SHPR3_PRI12_MSK (0xFF << 0 )
8884
8885/* Reset Value for SHCSR*/
8886#define SHCSR_RVAL 0x0
8887
8888/* SHCSR[USGFAULTENA] - Enable for UsageFault */
8889#define SHCSR_USGFAULTENA_MSK (0x1 << 18 )
8890#define SHCSR_USGFAULTENA (0x1 << 18 )
8891#define SHCSR_USGFAULTENA_DIS (0x0 << 18 ) /* DIS */
8892#define SHCSR_USGFAULTENA_EN (0x1 << 18 ) /* EN */
8893
8894/* SHCSR[BUSFAULTENA] - Enable for BusFault. */
8895#define SHCSR_BUSFAULTENA_MSK (0x1 << 17 )
8896#define SHCSR_BUSFAULTENA (0x1 << 17 )
8897#define SHCSR_BUSFAULTENA_DIS (0x0 << 17 ) /* DIS */
8898#define SHCSR_BUSFAULTENA_EN (0x1 << 17 ) /* EN */
8899
8900/* SHCSR[MEMFAULTENA] - Enable for MemManage fault. */
8901#define SHCSR_MEMFAULTENA_MSK (0x1 << 16 )
8902#define SHCSR_MEMFAULTENA (0x1 << 16 )
8903#define SHCSR_MEMFAULTENA_DIS (0x0 << 16 ) /* DIS */
8904#define SHCSR_MEMFAULTENA_EN (0x1 << 16 ) /* EN */
8905
8906/* SHCSR[SVCALLPENDED] - Reads as 1 if SVCall is Pending */
8907#define SHCSR_SVCALLPENDED_MSK (0x1 << 15 )
8908#define SHCSR_SVCALLPENDED (0x1 << 15 )
8909#define SHCSR_SVCALLPENDED_DIS (0x0 << 15 ) /* DIS */
8910#define SHCSR_SVCALLPENDED_EN (0x1 << 15 ) /* EN */
8911
8912/* SHCSR[BUSFAULTPENDED] - Reads as 1 if BusFault is Pending */
8913#define SHCSR_BUSFAULTPENDED_MSK (0x1 << 14 )
8914#define SHCSR_BUSFAULTPENDED (0x1 << 14 )
8915#define SHCSR_BUSFAULTPENDED_DIS (0x0 << 14 ) /* DIS */
8916#define SHCSR_BUSFAULTPENDED_EN (0x1 << 14 ) /* EN */
8917
8918/* SHCSR[MEMFAULTPENDED] - Reads as 1 if MemManage is Pending */
8919#define SHCSR_MEMFAULTPENDED_MSK (0x1 << 13 )
8920#define SHCSR_MEMFAULTPENDED (0x1 << 13 )
8921#define SHCSR_MEMFAULTPENDED_DIS (0x0 << 13 ) /* DIS */
8922#define SHCSR_MEMFAULTPENDED_EN (0x1 << 13 ) /* EN */
8923
8924/* SHCSR[USGFAULTPENDED] - Reads as 1 if UsageFault is Pending */
8925#define SHCSR_USGFAULTPENDED_MSK (0x1 << 12 )
8926#define SHCSR_USGFAULTPENDED (0x1 << 12 )
8927#define SHCSR_USGFAULTPENDED_DIS (0x0 << 12 ) /* DIS */
8928#define SHCSR_USGFAULTPENDED_EN (0x1 << 12 ) /* EN */
8929
8930/* SHCSR[SYSTICKACT] - Reads as 1 if SysTick is Active */
8931#define SHCSR_SYSTICKACT_MSK (0x1 << 11 )
8932#define SHCSR_SYSTICKACT (0x1 << 11 )
8933#define SHCSR_SYSTICKACT_DIS (0x0 << 11 ) /* DIS */
8934#define SHCSR_SYSTICKACT_EN (0x1 << 11 ) /* EN */
8935
8936/* SHCSR[PENDSVACT] - Reads as 1 if PendSV is Active */
8937#define SHCSR_PENDSVACT_MSK (0x1 << 10 )
8938#define SHCSR_PENDSVACT (0x1 << 10 )
8939#define SHCSR_PENDSVACT_DIS (0x0 << 10 ) /* DIS */
8940#define SHCSR_PENDSVACT_EN (0x1 << 10 ) /* EN */
8941
8942/* SHCSR[MONITORACT] - Reads as 1 if the Monitor is Active */
8943#define SHCSR_MONITORACT_MSK (0x1 << 8 )
8944#define SHCSR_MONITORACT (0x1 << 8 )
8945#define SHCSR_MONITORACT_DIS (0x0 << 8 ) /* DIS */
8946#define SHCSR_MONITORACT_EN (0x1 << 8 ) /* EN */
8947
8948/* SHCSR[SVCALLACT] - Reads as 1 if SVCall is Active */
8949#define SHCSR_SVCALLACT_MSK (0x1 << 7 )
8950#define SHCSR_SVCALLACT (0x1 << 7 )
8951#define SHCSR_SVCALLACT_DIS (0x0 << 7 ) /* DIS */
8952#define SHCSR_SVCALLACT_EN (0x1 << 7 ) /* EN */
8953
8954/* SHCSR[USGFAULTACT] - Reads as 1 if UsageFault is Active. */
8955#define SHCSR_USGFAULTACT_MSK (0x1 << 3 )
8956#define SHCSR_USGFAULTACT (0x1 << 3 )
8957#define SHCSR_USGFAULTACT_DIS (0x0 << 3 ) /* DIS */
8958#define SHCSR_USGFAULTACT_EN (0x1 << 3 ) /* EN */
8959
8960/* SHCSR[BUSFAULTACT] - Reads as 1 if BusFault is Active. */
8961#define SHCSR_BUSFAULTACT_MSK (0x1 << 1 )
8962#define SHCSR_BUSFAULTACT (0x1 << 1 )
8963#define SHCSR_BUSFAULTACT_DIS (0x0 << 1 ) /* DIS */
8964#define SHCSR_BUSFAULTACT_EN (0x1 << 1 ) /* EN */
8965
8966/* SHCSR[MEMFAULTACT] - Reads as 1 if MemManage is Active */
8967#define SHCSR_MEMFAULTACT_MSK (0x1 << 0 )
8968#define SHCSR_MEMFAULTACT (0x1 << 0 )
8969#define SHCSR_MEMFAULTACT_DIS (0x0 << 0 ) /* DIS */
8970#define SHCSR_MEMFAULTACT_EN (0x1 << 0 ) /* EN */
8971
8972/* Reset Value for CFSR*/
8973#define CFSR_RVAL 0x0
8974
8975/* CFSR[DIVBYZERO] - Divide by zero error */
8976#define CFSR_DIVBYZERO_MSK (0x1 << 25 )
8977#define CFSR_DIVBYZERO (0x1 << 25 )
8978#define CFSR_DIVBYZERO_DIS (0x0 << 25 ) /* DIS */
8979#define CFSR_DIVBYZERO_EN (0x1 << 25 ) /* EN */
8980
8981/* CFSR[UNALIGNED] - Unaligned access error */
8982#define CFSR_UNALIGNED_MSK (0x1 << 24 )
8983#define CFSR_UNALIGNED (0x1 << 24 )
8984#define CFSR_UNALIGNED_DIS (0x0 << 24 ) /* DIS */
8985#define CFSR_UNALIGNED_EN (0x1 << 24 ) /* EN */
8986
8987/* CFSR[NOCP] - Coprocessor access error */
8988#define CFSR_NOCP_MSK (0x1 << 19 )
8989#define CFSR_NOCP (0x1 << 19 )
8990#define CFSR_NOCP_DIS (0x0 << 19 ) /* DIS */
8991#define CFSR_NOCP_EN (0x1 << 19 ) /* EN */
8992
8993/* CFSR[INVPC] - Integrity check error on EXC_RETURN */
8994#define CFSR_INVPC_MSK (0x1 << 18 )
8995#define CFSR_INVPC (0x1 << 18 )
8996#define CFSR_INVPC_DIS (0x0 << 18 ) /* DIS */
8997#define CFSR_INVPC_EN (0x1 << 18 ) /* EN */
8998
8999/* CFSR[INVSTATE] - Invalid EPSR.T bit or illegal EPSR.IT bits for executing */
9000#define CFSR_INVSTATE_MSK (0x1 << 17 )
9001#define CFSR_INVSTATE (0x1 << 17 )
9002#define CFSR_INVSTATE_DIS (0x0 << 17 ) /* DIS */
9003#define CFSR_INVSTATE_EN (0x1 << 17 ) /* EN */
9004
9005/* CFSR[UNDEFINSTR] - Undefined instruction executed */
9006#define CFSR_UNDEFINSTR_MSK (0x1 << 16 )
9007#define CFSR_UNDEFINSTR (0x1 << 16 )
9008#define CFSR_UNDEFINSTR_DIS (0x0 << 16 ) /* DIS */
9009#define CFSR_UNDEFINSTR_EN (0x1 << 16 ) /* EN */
9010
9011/* CFSR[BFARVALID] - This bit is set if the BFAR register has valid contents */
9012#define CFSR_BFARVALID_MSK (0x1 << 15 )
9013#define CFSR_BFARVALID (0x1 << 15 )
9014#define CFSR_BFARVALID_DIS (0x0 << 15 ) /* DIS */
9015#define CFSR_BFARVALID_EN (0x1 << 15 ) /* EN */
9016
9017/* CFSR[STKERR] - This bit indicates a derived bus fault has occurred on exception entry */
9018#define CFSR_STKERR_MSK (0x1 << 12 )
9019#define CFSR_STKERR (0x1 << 12 )
9020#define CFSR_STKERR_DIS (0x0 << 12 ) /* DIS */
9021#define CFSR_STKERR_EN (0x1 << 12 ) /* EN */
9022
9023/* CFSR[UNSTKERR] - This bit indicates a derived bus fault has occurred on exception return */
9024#define CFSR_UNSTKERR_MSK (0x1 << 11 )
9025#define CFSR_UNSTKERR (0x1 << 11 )
9026#define CFSR_UNSTKERR_DIS (0x0 << 11 ) /* DIS */
9027#define CFSR_UNSTKERR_EN (0x1 << 11 ) /* EN */
9028
9029/* CFSR[IMPRECISERR] - Imprecise data access error */
9030#define CFSR_IMPRECISERR_MSK (0x1 << 10 )
9031#define CFSR_IMPRECISERR (0x1 << 10 )
9032#define CFSR_IMPRECISERR_DIS (0x0 << 10 ) /* DIS */
9033#define CFSR_IMPRECISERR_EN (0x1 << 10 ) /* EN */
9034
9035/* CFSR[PRECISERR] - Precise data access error. The BFAR is written with the faulting address */
9036#define CFSR_PRECISERR_MSK (0x1 << 9 )
9037#define CFSR_PRECISERR (0x1 << 9 )
9038#define CFSR_PRECISERR_DIS (0x0 << 9 ) /* DIS */
9039#define CFSR_PRECISERR_EN (0x1 << 9 ) /* EN */
9040
9041/* CFSR[IBUSERR] - This bit indicates a bus fault on an instruction prefetch */
9042#define CFSR_IBUSERR_MSK (0x1 << 8 )
9043#define CFSR_IBUSERR (0x1 << 8 )
9044#define CFSR_IBUSERR_DIS (0x0 << 8 ) /* DIS */
9045#define CFSR_IBUSERR_EN (0x1 << 8 ) /* EN */
9046
9047/* CFSR[MMARVALID] - This bit is set if the MMAR register has valid contents. */
9048#define CFSR_MMARVALID_MSK (0x1 << 7 )
9049#define CFSR_MMARVALID (0x1 << 7 )
9050#define CFSR_MMARVALID_DIS (0x0 << 7 ) /* DIS */
9051#define CFSR_MMARVALID_EN (0x1 << 7 ) /* EN */
9052
9053/* CFSR[MSTKERR] - A derived MemManage fault has occurred on exception entry */
9054#define CFSR_MSTKERR_MSK (0x1 << 4 )
9055#define CFSR_MSTKERR (0x1 << 4 )
9056#define CFSR_MSTKERR_DIS (0x0 << 4 ) /* DIS */
9057#define CFSR_MSTKERR_EN (0x1 << 4 ) /* EN */
9058
9059/* CFSR[MUNSTKERR] - A derived MemManage fault has occurred on exception return */
9060#define CFSR_MUNSTKERR_MSK (0x1 << 3 )
9061#define CFSR_MUNSTKERR (0x1 << 3 )
9062#define CFSR_MUNSTKERR_DIS (0x0 << 3 ) /* DIS */
9063#define CFSR_MUNSTKERR_EN (0x1 << 3 ) /* EN */
9064
9065/* CFSR[DACCVIOL] - Data access violation. The MMAR is set to the data address which the load store tried to access. */
9066#define CFSR_DACCVIOL_MSK (0x1 << 1 )
9067#define CFSR_DACCVIOL (0x1 << 1 )
9068#define CFSR_DACCVIOL_DIS (0x0 << 1 ) /* DIS */
9069#define CFSR_DACCVIOL_EN (0x1 << 1 ) /* EN */
9070
9071/* CFSR[IACCVIOL] - violation on an instruction fetch. */
9072#define CFSR_IACCVIOL_MSK (0x1 << 0 )
9073#define CFSR_IACCVIOL (0x1 << 0 )
9074#define CFSR_IACCVIOL_DIS (0x0 << 0 ) /* DIS */
9075#define CFSR_IACCVIOL_EN (0x1 << 0 ) /* EN */
9076
9077/* Reset Value for HFSR*/
9078#define HFSR_RVAL 0x0
9079
9080/* HFSR[DEBUGEVT] - Debug event, and the Debug Fault Status Register has been updated. */
9081#define HFSR_DEBUGEVT_MSK (0x1 << 31 )
9082#define HFSR_DEBUGEVT (0x1 << 31 )
9083#define HFSR_DEBUGEVT_DIS (0x0 << 31 ) /* DIS */
9084#define HFSR_DEBUGEVT_EN (0x1 << 31 ) /* EN */
9085
9086/* HFSR[FORCED] - Configurable fault cannot be activated due to priority or it was disabled. Priority escalated to a HardFault. */
9087#define HFSR_FORCED_MSK (0x1 << 30 )
9088#define HFSR_FORCED (0x1 << 30 )
9089#define HFSR_FORCED_DIS (0x0 << 30 ) /* DIS */
9090#define HFSR_FORCED_EN (0x1 << 30 ) /* EN */
9091
9092/* HFSR[VECTTBL] - Fault was due to vector table read on exception processing */
9093#define HFSR_VECTTBL_MSK (0x1 << 1 )
9094#define HFSR_VECTTBL (0x1 << 1 )
9095#define HFSR_VECTTBL_DIS (0x0 << 1 ) /* DIS */
9096#define HFSR_VECTTBL_EN (0x1 << 1 ) /* EN */
9097
9098/* Reset Value for MMFAR*/
9099#define MMFAR_RVAL 0x0
9100
9101/* MMFAR[ADDRESS] - Data address MPU faulted. */
9102#define MMFAR_ADDRESS_MSK (0xFFFFFFFF << 0 )
9103
9104/* Reset Value for BFAR*/
9105#define BFAR_RVAL 0x0
9106
9107/* BFAR[ADDRESS] - Updated on precise data access faults */
9108#define BFAR_ADDRESS_MSK (0xFFFFFFFF << 0 )
9109
9110/* Reset Value for STIR*/
9111#define STIR_RVAL 0x0
9112
9113/* STIR[INTID] - The value written in this field is the interrupt to be triggered. */
9114#define STIR_INTID_MSK (0x3FF << 0 )
9115// ------------------------------------------------------------------------------------------------
9116// ----- ADC0 -----
9117// ------------------------------------------------------------------------------------------------
9118
9119
9120/**
9121 * @brief Analog to Digital Converter (pADI_ADC0)
9122 */
9123
9124#if (__NO_MMR_STRUCTS__==0)
9125typedef struct { /*!< pADI_ADC0 Structure */
9126 __IO uint8_t STA; /*!< ADC Status register */
9127 __I uint8_t RESERVED0[3];
9128 __IO uint8_t MSKI; /*!< Interrupt control register */
9129 __I uint8_t RESERVED1[3];
9130 __IO uint32_t CON; /*!< Main control register */
9131 __IO uint16_t OF; /*!< Offset calibration register */
9132 __I uint16_t RESERVED2;
9133 __IO uint16_t INTGN; /*!< Gain calibration register when using internal reference */
9134 __I uint16_t RESERVED3;
9135 __IO uint16_t EXTGN; /*!< Gain calibration register when using external reference */
9136 __I uint16_t RESERVED4;
9137 __IO uint16_t VDDGN; /*!< Gain calibration register when using AVDD as the ADC reference */
9138 __I uint16_t RESERVED5;
9139 __IO uint16_t ADCCFG; /*!< "Control register for the VBIAS voltage generator, ground switch and external reference buffer" */
9140 __I uint16_t RESERVED6;
9141 __IO uint16_t FLT; /*!< Filter configuration register */
9142 __I uint16_t RESERVED7;
9143 __IO uint16_t MDE; /*!< mode control register */
9144 __I uint16_t RESERVED8;
9145 __IO uint16_t RCR; /*!< Number of ADC0 conversions before an ADC interrupt is generated. */
9146 __I uint16_t RESERVED9;
9147 __IO uint16_t RCV; /*!< "This 16-bit, read-only MMR holds the current number of ADC0 conversion results" */
9148 __I uint16_t RESERVED10;
9149 __IO uint16_t TH; /*!< Sets the threshold */
9150 __I uint16_t RESERVED11;
9151 __IO uint8_t THC; /*!< Determines how many cumulative ADC0 conversion result readings above ADC0TH must occur */
9152 __I uint8_t RESERVED12[3];
9153 __IO uint8_t THV; /*!< 8-bit threshold exceeded counter register */
9154 __I uint8_t RESERVED13[3];
9155 __IO uint32_t ACC; /*!< 32-bit accumulator register */
9156 __IO uint32_t ATH; /*!< Holds the threshold value for the accumulator comparator */
9157 __IO uint8_t PRO; /*!< Configuration register for Post processing of ADC0 results */
9158 __I uint8_t RESERVED14[3];
9159 __IO uint32_t DAT; /*!< conversion result register */
9160} ADI_ADC_TypeDef;
9161#else // (__NO_MMR_STRUCTS__==0)
9162#define ADC0STA (*(volatile unsigned char *) 0x40030000)
9163#define ADC0MSKI (*(volatile unsigned char *) 0x40030004)
9164#define ADC0CON (*(volatile unsigned long *) 0x40030008)
9165#define ADC0OF (*(volatile unsigned short int *) 0x4003000C)
9166#define ADC0INTGN (*(volatile unsigned short int *) 0x40030010)
9167#define ADC0EXTGN (*(volatile unsigned short int *) 0x40030014)
9168#define ADC0VDDGN (*(volatile unsigned short int *) 0x40030018)
9169#define ADCCFG (*(volatile unsigned short int *) 0x4003001C)
9170#define ADC0FLT (*(volatile unsigned short int *) 0x40030020)
9171#define ADC0MDE (*(volatile unsigned short int *) 0x40030024)
9172#define ADC0RCR (*(volatile unsigned short int *) 0x40030028)
9173#define ADC0RCV (*(volatile unsigned short int *) 0x4003002C)
9174#define ADC0TH (*(volatile unsigned short int *) 0x40030030)
9175#define ADC0THC (*(volatile unsigned char *) 0x40030034)
9176#define ADC0THV (*(volatile unsigned char *) 0x40030038)
9177#define ADC0ACC (*(volatile unsigned long *) 0x4003003C)
9178#define ADC0ATH (*(volatile unsigned long *) 0x40030040)
9179#define ADC0PRO (*(volatile unsigned char *) 0x40030044)
9180#define ADC0DAT (*(volatile unsigned long *) 0x40030048)
9181#endif // (__NO_MMR_STRUCTS__==0)
9182
9183/* Reset Value for ADC0STA*/
9184#define ADC0STA_RVAL 0x0
9185
9186/* ADC0STA[CAL] - ADC Calibration status register */
9187#define ADC0STA_CAL_BBA (*(volatile unsigned long *) 0x42600014)
9188#define ADC0STA_CAL_MSK (0x1 << 5 )
9189#define ADC0STA_CAL (0x1 << 5 )
9190#define ADC0STA_CAL_DIS (0x0 << 5 ) /* DIS */
9191#define ADC0STA_CAL_EN (0x1 << 5 ) /* EN */
9192
9193/* ADC0STA[ERR] - ADC conversion error status bit. */
9194#define ADC0STA_ERR_BBA (*(volatile unsigned long *) 0x42600010)
9195#define ADC0STA_ERR_MSK (0x1 << 4 )
9196#define ADC0STA_ERR (0x1 << 4 )
9197#define ADC0STA_ERR_DIS (0x0 << 4 ) /* DIS */
9198#define ADC0STA_ERR_EN (0x1 << 4 ) /* EN */
9199
9200/* ADC0STA[ATHEX] - ADC Accumulator Comparator Threshold status bit. */
9201#define ADC0STA_ATHEX_BBA (*(volatile unsigned long *) 0x4260000C)
9202#define ADC0STA_ATHEX_MSK (0x1 << 3 )
9203#define ADC0STA_ATHEX (0x1 << 3 )
9204#define ADC0STA_ATHEX_DIS (0x0 << 3 ) /* DIS */
9205#define ADC0STA_ATHEX_EN (0x1 << 3 ) /* EN */
9206
9207/* ADC0STA[THEX] - ADC comparator threshold. */
9208#define ADC0STA_THEX_BBA (*(volatile unsigned long *) 0x42600008)
9209#define ADC0STA_THEX_MSK (0x1 << 2 )
9210#define ADC0STA_THEX (0x1 << 2 )
9211#define ADC0STA_THEX_DIS (0x0 << 2 ) /* DIS */
9212#define ADC0STA_THEX_EN (0x1 << 2 ) /* EN */
9213
9214/* ADC0STA[OVR] - ADC overrange bit. */
9215#define ADC0STA_OVR_BBA (*(volatile unsigned long *) 0x42600004)
9216#define ADC0STA_OVR_MSK (0x1 << 1 )
9217#define ADC0STA_OVR (0x1 << 1 )
9218#define ADC0STA_OVR_DIS (0x0 << 1 ) /* DIS */
9219#define ADC0STA_OVR_EN (0x1 << 1 ) /* EN */
9220
9221/* ADC0STA[RDY] - valid conversion result */
9222#define ADC0STA_RDY_BBA (*(volatile unsigned long *) 0x42600000)
9223#define ADC0STA_RDY_MSK (0x1 << 0 )
9224#define ADC0STA_RDY (0x1 << 0 )
9225#define ADC0STA_RDY_DIS (0x0 << 0 ) /* DIS */
9226#define ADC0STA_RDY_EN (0x1 << 0 ) /* EN */
9227
9228/* Reset Value for ADC0MSKI*/
9229#define ADC0MSKI_RVAL 0x0
9230
9231/* ADC0MSKI[ATHEX] - ADC Accumulator Comparator Threshold status bit mask */
9232#define ADC0MSKI_ATHEX_BBA (*(volatile unsigned long *) 0x4260008C)
9233#define ADC0MSKI_ATHEX_MSK (0x1 << 3 )
9234#define ADC0MSKI_ATHEX (0x1 << 3 )
9235#define ADC0MSKI_ATHEX_DIS (0x0 << 3 ) /* DIS */
9236#define ADC0MSKI_ATHEX_EN (0x1 << 3 ) /* EN */
9237
9238/* ADC0MSKI[THEX] - ADC comparator threshold mask */
9239#define ADC0MSKI_THEX_BBA (*(volatile unsigned long *) 0x42600088)
9240#define ADC0MSKI_THEX_MSK (0x1 << 2 )
9241#define ADC0MSKI_THEX (0x1 << 2 )
9242#define ADC0MSKI_THEX_DIS (0x0 << 2 ) /* DIS */
9243#define ADC0MSKI_THEX_EN (0x1 << 2 ) /* EN */
9244
9245/* ADC0MSKI[OVR] - ADC overrange bit mask. */
9246#define ADC0MSKI_OVR_BBA (*(volatile unsigned long *) 0x42600084)
9247#define ADC0MSKI_OVR_MSK (0x1 << 1 )
9248#define ADC0MSKI_OVR (0x1 << 1 )
9249#define ADC0MSKI_OVR_DIS (0x0 << 1 ) /* DIS */
9250#define ADC0MSKI_OVR_EN (0x1 << 1 ) /* EN */
9251
9252/* ADC0MSKI[RDY] - valid conversion result mask */
9253#define ADC0MSKI_RDY_BBA (*(volatile unsigned long *) 0x42600080)
9254#define ADC0MSKI_RDY_MSK (0x1 << 0 )
9255#define ADC0MSKI_RDY (0x1 << 0 )
9256#define ADC0MSKI_RDY_DIS (0x0 << 0 ) /* DIS */
9257#define ADC0MSKI_RDY_EN (0x1 << 0 ) /* EN */
9258
9259/* Reset Value for ADC0CON*/
9260#define ADC0CON_RVAL 0x3038C
9261
9262/* ADC0CON[ADCEN] - Enable Bit */
9263#define ADC0CON_ADCEN_BBA (*(volatile unsigned long *) 0x4260014C)
9264#define ADC0CON_ADCEN_MSK (0x1 << 19 )
9265#define ADC0CON_ADCEN (0x1 << 19 )
9266#define ADC0CON_ADCEN_DIS (0x0 << 19 ) /* DIS */
9267#define ADC0CON_ADCEN_EN (0x1 << 19 ) /* EN */
9268
9269/* ADC0CON[ADCCODE] - ADC Output Coding bits */
9270#define ADC0CON_ADCCODE_BBA (*(volatile unsigned long *) 0x42600148)
9271#define ADC0CON_ADCCODE_MSK (0x1 << 18 )
9272#define ADC0CON_ADCCODE (0x1 << 18 )
9273#define ADC0CON_ADCCODE_INT (0x0 << 18 ) /* INT */
9274#define ADC0CON_ADCCODE_UINT (0x1 << 18 ) /* UINT */
9275
9276/* ADC0CON[BUFPOWN] - Negative buffer power down */
9277#define ADC0CON_BUFPOWN_BBA (*(volatile unsigned long *) 0x42600144)
9278#define ADC0CON_BUFPOWN_MSK (0x1 << 17 )
9279#define ADC0CON_BUFPOWN (0x1 << 17 )
9280#define ADC0CON_BUFPOWN_DIS (0x0 << 17 ) /* Disable powerdown - Negative buffer is enabled */
9281#define ADC0CON_BUFPOWN_EN (0x1 << 17 ) /* Enable powerdown - Negative buffer is disabled */
9282
9283/* ADC0CON[BUFPOWP] - Positive buffer power down */
9284#define ADC0CON_BUFPOWP_BBA (*(volatile unsigned long *) 0x42600140)
9285#define ADC0CON_BUFPOWP_MSK (0x1 << 16 )
9286#define ADC0CON_BUFPOWP (0x1 << 16 )
9287#define ADC0CON_BUFPOWP_DIS (0x0 << 16 ) /* Disable powerdown - Positive buffer is enabled */
9288#define ADC0CON_BUFPOWP_EN (0x1 << 16 ) /* Enable powerdown - Positive buffer is disabled */
9289
9290/* ADC0CON[BUFBYPP] - Positive buffer bypass */
9291#define ADC0CON_BUFBYPP_BBA (*(volatile unsigned long *) 0x4260013C)
9292#define ADC0CON_BUFBYPP_MSK (0x1 << 15 )
9293#define ADC0CON_BUFBYPP (0x1 << 15 )
9294#define ADC0CON_BUFBYPP_DIS (0x0 << 15 ) /* DIS */
9295#define ADC0CON_BUFBYPP_EN (0x1 << 15 ) /* EN */
9296
9297/* ADC0CON[BUFBYPN] - Negative buffer bypass */
9298#define ADC0CON_BUFBYPN_BBA (*(volatile unsigned long *) 0x42600138)
9299#define ADC0CON_BUFBYPN_MSK (0x1 << 14 )
9300#define ADC0CON_BUFBYPN (0x1 << 14 )
9301#define ADC0CON_BUFBYPN_DIS (0x0 << 14 ) /* DIS */
9302#define ADC0CON_BUFBYPN_EN (0x1 << 14 ) /* EN */
9303
9304/* ADC0CON[ADCREF] - Reference selection */
9305#define ADC0CON_ADCREF_MSK (0x3 << 12 )
9306#define ADC0CON_ADCREF_INTREF (0x0 << 12 ) /* INTREF */
9307#define ADC0CON_ADCREF_EXTREF (0x1 << 12 ) /* EXTREF */
9308#define ADC0CON_ADCREF_EXTREF2 (0x2 << 12 ) /* EXTREF2 */
9309#define ADC0CON_ADCREF_AVDDREF (0x3 << 12 ) /* AVDDREF */
9310
9311/* ADC0CON[ADCDIAG] - Diagnostic Current bits bits */
9312#define ADC0CON_ADCDIAG_MSK (0x3 << 10 )
9313#define ADC0CON_ADCDIAG_DIAG_OFF (0x0 << 10 ) /* DIAG_OFF */
9314#define ADC0CON_ADCDIAG_DIAG_POS (0x1 << 10 ) /* DIAG_POS */
9315#define ADC0CON_ADCDIAG_DIAG_NEG (0x2 << 10 ) /* DIAG_NEG */
9316#define ADC0CON_ADCDIAG_DIAG_ALL (0x3 << 10 ) /* DIAG_ALL */
9317
9318/* ADC0CON[ADCCP] - AIN+ bits */
9319#define ADC0CON_ADCCP_MSK (0x1F << 5 )
9320#define ADC0CON_ADCCP_AIN0 (0x0 << 5 ) /* AIN0 */
9321#define ADC0CON_ADCCP_AIN1 (0x1 << 5 ) /* AIN1 */
9322#define ADC0CON_ADCCP_AIN2 (0x2 << 5 ) /* AIN2 */
9323#define ADC0CON_ADCCP_AIN3 (0x3 << 5 ) /* AIN3 */
9324#define ADC0CON_ADCCP_AIN4 (0x4 << 5 ) /* AIN4 */
9325#define ADC0CON_ADCCP_AIN5 (0x5 << 5 ) /* AIN5 */
9326#define ADC0CON_ADCCP_AIN6 (0x6 << 5 ) /* AIN6 */
9327#define ADC0CON_ADCCP_AIN7 (0x7 << 5 ) /* AIN7 */
9328#define ADC0CON_ADCCP_AIN8 (0x8 << 5 ) /* AIN8 */
9329#define ADC0CON_ADCCP_AIN9 (0x9 << 5 ) /* AIN9 */
9330#define ADC0CON_ADCCP_AIN10 (0xA << 5 ) /* AIN10 */
9331#define ADC0CON_ADCCP_AIN11 (0xB << 5 ) /* AIN11 */
9332#define ADC0CON_ADCCP_DAC (0xC << 5 ) /* DAC */
9333#define ADC0CON_ADCCP_AVDD4 (0xD << 5 ) /* AVDD4 */
9334#define ADC0CON_ADCCP_IOVDD4 (0xE << 5 ) /* IOVDD4 */
9335#define ADC0CON_ADCCP_AGND (0xF << 5 ) /* AGND */
9336#define ADC0CON_ADCCP_TEMP (0x10 << 5 ) /* TEMP */
9337
9338/* ADC0CON[ADCCN] - AIN- bits */
9339#define ADC0CON_ADCCN_MSK (0x1F << 0 )
9340#define ADC0CON_ADCCN_AIN0 (0x0 << 0 ) /* AIN0 */
9341#define ADC0CON_ADCCN_AIN1 (0x1 << 0 ) /* AIN1 */
9342#define ADC0CON_ADCCN_AIN2 (0x2 << 0 ) /* AIN2 */
9343#define ADC0CON_ADCCN_AIN3 (0x3 << 0 ) /* AIN3 */
9344#define ADC0CON_ADCCN_AIN4 (0x4 << 0 ) /* AIN4 */
9345#define ADC0CON_ADCCN_AIN5 (0x5 << 0 ) /* AIN5 */
9346#define ADC0CON_ADCCN_AIN6 (0x6 << 0 ) /* AIN6 */
9347#define ADC0CON_ADCCN_AIN7 (0x7 << 0 ) /* AIN7 */
9348#define ADC0CON_ADCCN_AIN8 (0x8 << 0 ) /* AIN8 */
9349#define ADC0CON_ADCCN_AIN9 (0x9 << 0 ) /* AIN9 */
9350#define ADC0CON_ADCCN_AIN10 (0xA << 0 ) /* AIN10 */
9351#define ADC0CON_ADCCN_AIN11 (0xB << 0 ) /* AIN11 */
9352#define ADC0CON_ADCCN_DAC (0xC << 0 ) /* DAC */
9353#define ADC0CON_ADCCN_AGND (0xF << 0 ) /* AGND */
9354#define ADC0CON_ADCCN_TEMP (0x11 << 0 ) /* TEMP */
9355
9356/* Reset Value for ADC0OF*/
9357#define ADC0OF_RVAL 0x0
9358
9359/* ADC0OF[VALUE] - Offset */
9360#define ADC0OF_VALUE_MSK (0xFFFF << 0 )
9361
9362/* Reset Value for ADC0INTGN*/
9363#define ADC0INTGN_RVAL 0x5555
9364
9365/* ADC0INTGN[VALUE] - Gain with Int Ref */
9366#define ADC0INTGN_VALUE_MSK (0xFFFF << 0 )
9367
9368/* Reset Value for ADC0EXTGN*/
9369#define ADC0EXTGN_RVAL 0x5555
9370
9371/* ADC0EXTGN[VALUE] - Gain with Ext Ref */
9372#define ADC0EXTGN_VALUE_MSK (0xFFFF << 0 )
9373
9374/* Reset Value for ADC0VDDGN*/
9375#define ADC0VDDGN_RVAL 0x5555
9376
9377/* ADC0VDDGN[VALUE] - Gain with Avdd Ref */
9378#define ADC0VDDGN_VALUE_MSK (0xFFFF << 0 )
9379
9380/* Reset Value for ADCCFG*/
9381#define ADCCFG_RVAL 0xF
9382
9383/* ADCCFG[SIMU] - Enable both ADCs */
9384#define ADCCFG_SIMU_BBA (*(volatile unsigned long *) 0x426003BC)
9385#define ADCCFG_SIMU_MSK (0x1 << 15 )
9386#define ADCCFG_SIMU (0x1 << 15 )
9387#define ADCCFG_SIMU_DIS (0x0 << 15 ) /* DIS */
9388#define ADCCFG_SIMU_EN (0x1 << 15 ) /* EN */
9389
9390/* ADCCFG[BOOST30] - Boost the Vbias current source ability by 30 times */
9391#define ADCCFG_BOOST30_BBA (*(volatile unsigned long *) 0x426003B4)
9392#define ADCCFG_BOOST30_MSK (0x1 << 13 )
9393#define ADCCFG_BOOST30 (0x1 << 13 )
9394#define ADCCFG_BOOST30_DIS (0x0 << 13 ) /* DIS */
9395#define ADCCFG_BOOST30_EN (0x1 << 13 ) /* EN */
9396
9397/* ADCCFG[PINSEL] - Enable vbias generator, send vbias to selected ain pin bits */
9398#define ADCCFG_PINSEL_MSK (0x7 << 8 )
9399#define ADCCFG_PINSEL_DIS (0x0 << 8 ) /* Disable VBIAS generator */
9400#define ADCCFG_PINSEL_AIN7 (0x4 << 8 ) /* AIN7 */
9401#define ADCCFG_PINSEL_AIN11 (0x6 << 8 ) /* AIN11 */
9402
9403/* ADCCFG[GNDSWON] - GND_SW */
9404#define ADCCFG_GNDSWON_BBA (*(volatile unsigned long *) 0x4260039C)
9405#define ADCCFG_GNDSWON_MSK (0x1 << 7 )
9406#define ADCCFG_GNDSWON (0x1 << 7 )
9407#define ADCCFG_GNDSWON_DIS (0x0 << 7 ) /* DIS */
9408#define ADCCFG_GNDSWON_EN (0x1 << 7 ) /* EN */
9409
9410/* ADCCFG[GNDSWRESEN] - 20k resistor in series with GND_SW */
9411#define ADCCFG_GNDSWRESEN_BBA (*(volatile unsigned long *) 0x42600398)
9412#define ADCCFG_GNDSWRESEN_MSK (0x1 << 6 )
9413#define ADCCFG_GNDSWRESEN (0x1 << 6 )
9414#define ADCCFG_GNDSWRESEN_DIS (0x0 << 6 ) /* DIS */
9415#define ADCCFG_GNDSWRESEN_EN (0x1 << 6 ) /* EN */
9416
9417/* ADCCFG[EXTBUF] - Control signals for ext_ref buffers bits */
9418#define ADCCFG_EXTBUF_MSK (0x3 << 0 )
9419#define ADCCFG_EXTBUF_OFF (0x0 << 0 ) /* OFF */
9420#define ADCCFG_EXTBUF_VREFPN (0x1 << 0 ) /* VREFPN */
9421#define ADCCFG_EXTBUF_VREFP_VREF2P (0x2 << 0 ) /* VREFP_VREF2P */
9422#define ADCCFG_EXTBUF_VREFP_ONLY (0x3 << 0 ) /* VREFP_Only */
9423/* Reset Value for ADC0FLT*/
9424#define ADC0FLT_RVAL 0x7D
9425
9426/* ADC0FLT[CHOP] - Enables System-Chopping bits */
9427#define ADC0FLT_CHOP_BBA (*(volatile unsigned long *) 0x4260043C)
9428#define ADC0FLT_CHOP_MSK (0x1 << 15 )
9429#define ADC0FLT_CHOP (0x1 << 15 )
9430#define ADC0FLT_CHOP_OFF (0x0 << 15 ) /* OFF */
9431#define ADC0FLT_CHOP_ON (0x1 << 15 ) /* ON */
9432
9433/* ADC0FLT[RAVG2] - Enables a running Average-By-2 bits */
9434#define ADC0FLT_RAVG2_BBA (*(volatile unsigned long *) 0x42600438)
9435#define ADC0FLT_RAVG2_MSK (0x1 << 14 )
9436#define ADC0FLT_RAVG2 (0x1 << 14 )
9437#define ADC0FLT_RAVG2_OFF (0x0 << 14 ) /* OFF */
9438#define ADC0FLT_RAVG2_ON (0x1 << 14 ) /* ON */
9439
9440/* ADC0FLT[SINC4EN] - Enable the Sinc4 filter instead of Sinc3 filter. */
9441#define ADC0FLT_SINC4EN_BBA (*(volatile unsigned long *) 0x42600430)
9442#define ADC0FLT_SINC4EN_MSK (0x1 << 12 )
9443#define ADC0FLT_SINC4EN (0x1 << 12 )
9444#define ADC0FLT_SINC4EN_DIS (0x0 << 12 ) /* DIS */
9445#define ADC0FLT_SINC4EN_EN (0x1 << 12 ) /* EN */
9446
9447/* ADC0FLT[AF] - Averaging filter */
9448#define ADC0FLT_AF_MSK (0xF << 8 )
9449
9450/* ADC0FLT[NOTCH2] - Inserts a notch at FNOTCH2 */
9451#define ADC0FLT_NOTCH2_BBA (*(volatile unsigned long *) 0x4260041C)
9452#define ADC0FLT_NOTCH2_MSK (0x1 << 7 )
9453#define ADC0FLT_NOTCH2 (0x1 << 7 )
9454#define ADC0FLT_NOTCH2_DIS (0x0 << 7 ) /* DIS */
9455#define ADC0FLT_NOTCH2_EN (0x1 << 7 ) /* EN */
9456
9457/* ADC0FLT[SF] - SINC Filter value */
9458#define ADC0FLT_SF_MSK (0x7F << 0 )
9459
9460/* Reset Value for ADC0MDE*/
9461#define ADC0MDE_RVAL 0x0
9462
9463/* ADC0MDE[PGA] - PGA Gain Select bit */
9464#define ADC0MDE_PGA_MSK (0xF << 4 )
9465#define ADC0MDE_PGA_G1 (0x0 << 4 ) /* G1 */
9466#define ADC0MDE_PGA_G2 (0x1 << 4 ) /* G2 */
9467#define ADC0MDE_PGA_G4 (0x2 << 4 ) /* G4 */
9468#define ADC0MDE_PGA_G8 (0x3 << 4 ) /* G8 */
9469#define ADC0MDE_PGA_G16 (0x4 << 4 ) /* G16 */
9470#define ADC0MDE_PGA_G32 (0x5 << 4 ) /* G32 */
9471#define ADC0MDE_PGA_G64 (0x6 << 4 ) /* G64 */
9472#define ADC0MDE_PGA_G128 (0x7 << 4 ) /* G128 */
9473
9474/* ADC0MDE[ADCMOD2] - ADC modulator gain of 2 control bits */
9475#define ADC0MDE_ADCMOD2_BBA (*(volatile unsigned long *) 0x4260048C)
9476#define ADC0MDE_ADCMOD2_MSK (0x1 << 3 )
9477#define ADC0MDE_ADCMOD2 (0x1 << 3 )
9478#define ADC0MDE_ADCMOD2_MOD2OFF (0x0 << 3 ) /* MOD2OFF */
9479#define ADC0MDE_ADCMOD2_MOD2ON (0x1 << 3 ) /* MOD2ON */
9480
9481/* ADC0MDE[ADCMD] - ADC Mode bits */
9482#define ADC0MDE_ADCMD_MSK (0x7 << 0 )
9483#define ADC0MDE_ADCMD_OFF (0x0 << 0 ) /* OFF */
9484#define ADC0MDE_ADCMD_CONT (0x1 << 0 ) /* CONT */
9485#define ADC0MDE_ADCMD_SINGLE (0x2 << 0 ) /* SINGLE */
9486#define ADC0MDE_ADCMD_IDLE (0x3 << 0 ) /* IDLE */
9487#define ADC0MDE_ADCMD_INTOCAL (0x4 << 0 ) /* INTOCAL */
9488#define ADC0MDE_ADCMD_INTGCAL (0x5 << 0 ) /* INTGCAL */
9489#define ADC0MDE_ADCMD_SYSOCAL (0x6 << 0 ) /* SYSOCAL */
9490#define ADC0MDE_ADCMD_SYSGCAL (0x7 << 0 ) /* SYSGCAL */
9491
9492/* Reset Value for ADC0RCR*/
9493#define ADC0RCR_RVAL 0x1
9494
9495/* ADC0RCR[VALUE] - */
9496#define ADC0RCR_VALUE_MSK (0xFFFF << 0 )
9497
9498/* Reset Value for ADC0RCV*/
9499#define ADC0RCV_RVAL 0x0
9500
9501/* ADC0RCV[VALUE] - */
9502#define ADC0RCV_VALUE_MSK (0xFFFF << 0 )
9503
9504/* Reset Value for ADC0TH*/
9505#define ADC0TH_RVAL 0x0
9506
9507/* ADC0TH[VALUE] - */
9508#define ADC0TH_VALUE_MSK (0xFFFF << 0 )
9509
9510/* Reset Value for ADC0THC*/
9511#define ADC0THC_RVAL 0x1
9512
9513/* ADC0THC[VALUE] - */
9514#define ADC0THC_VALUE_MSK (0xFF << 0 )
9515
9516/* Reset Value for ADC0THV*/
9517#define ADC0THV_RVAL 0x0
9518
9519/* ADC0THV[VALUE] - */
9520#define ADC0THV_VALUE_MSK (0xFF << 0 )
9521
9522/* Reset Value for ADC0ACC*/
9523#define ADC0ACC_RVAL 0x0
9524
9525/* ADC0ACC[VALUE] - */
9526#define ADC0ACC_VALUE_MSK (0xFFFFFFFF << 0 )
9527
9528/* Reset Value for ADC0ATH*/
9529#define ADC0ATH_RVAL 0x0
9530
9531/* ADC0ATH[VALUE] - */
9532#define ADC0ATH_VALUE_MSK (0xFFFFFFFF << 0 )
9533
9534/* Reset Value for ADC0PRO*/
9535#define ADC0PRO_RVAL 0x0
9536
9537/* ADC0PRO[ACCEN] - ADC Accumulator Enable bits */
9538#define ADC0PRO_ACCEN_MSK (0x3 << 4 )
9539#define ADC0PRO_ACCEN_Off (0x0 << 4 ) /* Off */
9540#define ADC0PRO_ACCEN_En (0x1 << 4 ) /* En */
9541#define ADC0PRO_ACCEN_EnNDec (0x2 << 4 ) /* EnNDec */
9542#define ADC0PRO_ACCEN_EnAccCnt (0x3 << 4 ) /* EnAccCnt */
9543
9544/* ADC0PRO[CMPEN] - ADC Comparator Enable bits */
9545#define ADC0PRO_CMPEN_MSK (0x3 << 2 )
9546#define ADC0PRO_CMPEN_Off (0x0 << 2 ) /* Off */
9547#define ADC0PRO_CMPEN_En (0x1 << 2 ) /* En */
9548#define ADC0PRO_CMPEN_EnCnt (0x2 << 2 ) /* EnCnt */
9549#define ADC0PRO_CMPEN_EnCntDec (0x3 << 2 ) /* EnCntDec */
9550
9551/* ADC0PRO[OREN] - ADC OverRange Enable */
9552#define ADC0PRO_OREN_BBA (*(volatile unsigned long *) 0x42600884)
9553#define ADC0PRO_OREN_MSK (0x1 << 1 )
9554#define ADC0PRO_OREN (0x1 << 1 )
9555#define ADC0PRO_OREN_DIS (0x0 << 1 ) /* DIS */
9556#define ADC0PRO_OREN_EN (0x1 << 1 ) /* EN */
9557
9558/* ADC0PRO[RCEN] - ADC Result Counter Enable */
9559#define ADC0PRO_RCEN_BBA (*(volatile unsigned long *) 0x42600880)
9560#define ADC0PRO_RCEN_MSK (0x1 << 0 )
9561#define ADC0PRO_RCEN (0x1 << 0 )
9562#define ADC0PRO_RCEN_DIS (0x0 << 0 ) /* DIS */
9563#define ADC0PRO_RCEN_EN (0x1 << 0 ) /* EN */
9564
9565/* Reset Value for ADC0DAT*/
9566#define ADC0DAT_RVAL 0x0
9567
9568/* ADC0DAT[VALUE] - */
9569#define ADC0DAT_VALUE_MSK (0xFFFFFFFF << 0 )
9570#if (__NO_MMR_STRUCTS__==1)
9571
9572#define ADC1STA (*(volatile unsigned char *) 0x40030080)
9573#define ADC1MSKI (*(volatile unsigned char *) 0x40030084)
9574#define ADC1CON (*(volatile unsigned long *) 0x40030088)
9575#define ADC1OF (*(volatile unsigned short int *) 0x4003008C)
9576#define ADC1INTGN (*(volatile unsigned short int *) 0x40030090)
9577#define ADC1EXTGN (*(volatile unsigned short int *) 0x40030094)
9578#define ADC1VDDGN (*(volatile unsigned short int *) 0x40030098)
9579#define ADCSCFG1 (*(volatile unsigned short int *) 0x4003009C)
9580#define ADC1FLT (*(volatile unsigned short int *) 0x400300A0)
9581#define ADC1MDE (*(volatile unsigned short int *) 0x400300A4)
9582#define ADC1RCR (*(volatile unsigned short int *) 0x400300A8)
9583#define ADC1RCV (*(volatile unsigned short int *) 0x400300AC)
9584#define ADC1TH (*(volatile unsigned short int *) 0x400300B0)
9585#define ADC1THC (*(volatile unsigned char *) 0x400300B4)
9586#define ADC1THV (*(volatile unsigned char *) 0x400300B8)
9587#define ADC1ACC (*(volatile unsigned long *) 0x400300BC)
9588#define ADC1ATH (*(volatile unsigned long *) 0x400300C0)
9589#define ADC1PRO (*(volatile unsigned char *) 0x400300C4)
9590#define ADC1DAT (*(volatile unsigned long *) 0x400300C8)
9591#endif // (__NO_MMR_STRUCTS__==1)
9592
9593/* Reset Value for ADC1STA*/
9594#define ADC1STA_RVAL 0x0
9595
9596/* ADC1STA[CAL] - ADC Calibration status register */
9597#define ADC1STA_CAL_BBA (*(volatile unsigned long *) 0x42601014)
9598#define ADC1STA_CAL_MSK (0x1 << 5 )
9599#define ADC1STA_CAL (0x1 << 5 )
9600#define ADC1STA_CAL_DIS (0x0 << 5 ) /* DIS */
9601#define ADC1STA_CAL_EN (0x1 << 5 ) /* EN */
9602
9603/* ADC1STA[ERR] - ADC conversion error status bit. */
9604#define ADC1STA_ERR_BBA (*(volatile unsigned long *) 0x42601010)
9605#define ADC1STA_ERR_MSK (0x1 << 4 )
9606#define ADC1STA_ERR (0x1 << 4 )
9607#define ADC1STA_ERR_DIS (0x0 << 4 ) /* DIS */
9608#define ADC1STA_ERR_EN (0x1 << 4 ) /* EN */
9609
9610/* ADC1STA[ATHEX] - ADC Accumulator Comparator Threshold status bit. */
9611#define ADC1STA_ATHEX_BBA (*(volatile unsigned long *) 0x4260100C)
9612#define ADC1STA_ATHEX_MSK (0x1 << 3 )
9613#define ADC1STA_ATHEX (0x1 << 3 )
9614#define ADC1STA_ATHEX_DIS (0x0 << 3 ) /* DIS */
9615#define ADC1STA_ATHEX_EN (0x1 << 3 ) /* EN */
9616
9617/* ADC1STA[THEX] - ADC comparator threshold. */
9618#define ADC1STA_THEX_BBA (*(volatile unsigned long *) 0x42601008)
9619#define ADC1STA_THEX_MSK (0x1 << 2 )
9620#define ADC1STA_THEX (0x1 << 2 )
9621#define ADC1STA_THEX_DIS (0x0 << 2 ) /* DIS */
9622#define ADC1STA_THEX_EN (0x1 << 2 ) /* EN */
9623
9624/* ADC1STA[OVR] - ADC overrange bit. */
9625#define ADC1STA_OVR_BBA (*(volatile unsigned long *) 0x42601004)
9626#define ADC1STA_OVR_MSK (0x1 << 1 )
9627#define ADC1STA_OVR (0x1 << 1 )
9628#define ADC1STA_OVR_DIS (0x0 << 1 ) /* DIS */
9629#define ADC1STA_OVR_EN (0x1 << 1 ) /* EN */
9630
9631/* ADC1STA[RDY] - valid conversion result */
9632#define ADC1STA_RDY_BBA (*(volatile unsigned long *) 0x42601000)
9633#define ADC1STA_RDY_MSK (0x1 << 0 )
9634#define ADC1STA_RDY (0x1 << 0 )
9635#define ADC1STA_RDY_DIS (0x0 << 0 ) /* DIS */
9636#define ADC1STA_RDY_EN (0x1 << 0 ) /* EN */
9637
9638/* Reset Value for ADC1MSKI*/
9639#define ADC1MSKI_RVAL 0x0
9640
9641/* ADC1MSKI[ATHEX] - ADC Accumulator Comparator Threshold status bit mask */
9642#define ADC1MSKI_ATHEX_BBA (*(volatile unsigned long *) 0x4260108C)
9643#define ADC1MSKI_ATHEX_MSK (0x1 << 3 )
9644#define ADC1MSKI_ATHEX (0x1 << 3 )
9645#define ADC1MSKI_ATHEX_DIS (0x0 << 3 ) /* DIS */
9646#define ADC1MSKI_ATHEX_EN (0x1 << 3 ) /* EN */
9647
9648/* ADC1MSKI[THEX] - ADC comparator threshold mask */
9649#define ADC1MSKI_THEX_BBA (*(volatile unsigned long *) 0x42601088)
9650#define ADC1MSKI_THEX_MSK (0x1 << 2 )
9651#define ADC1MSKI_THEX (0x1 << 2 )
9652#define ADC1MSKI_THEX_DIS (0x0 << 2 ) /* DIS */
9653#define ADC1MSKI_THEX_EN (0x1 << 2 ) /* EN */
9654
9655/* ADC1MSKI[OVR] - ADC overrange bit mask. */
9656#define ADC1MSKI_OVR_BBA (*(volatile unsigned long *) 0x42601084)
9657#define ADC1MSKI_OVR_MSK (0x1 << 1 )
9658#define ADC1MSKI_OVR (0x1 << 1 )
9659#define ADC1MSKI_OVR_DIS (0x0 << 1 ) /* DIS */
9660#define ADC1MSKI_OVR_EN (0x1 << 1 ) /* EN */
9661
9662/* ADC1MSKI[RDY] - valid conversion result mask */
9663#define ADC1MSKI_RDY_BBA (*(volatile unsigned long *) 0x42601080)
9664#define ADC1MSKI_RDY_MSK (0x1 << 0 )
9665#define ADC1MSKI_RDY (0x1 << 0 )
9666#define ADC1MSKI_RDY_DIS (0x0 << 0 ) /* DIS */
9667#define ADC1MSKI_RDY_EN (0x1 << 0 ) /* EN */
9668
9669/* Reset Value for ADC1CON*/
9670#define ADC1CON_RVAL 0x303FF
9671
9672/* ADC1CON[ADCEN] - Enable Bit */
9673#define ADC1CON_ADCEN_BBA (*(volatile unsigned long *) 0x4260114C)
9674#define ADC1CON_ADCEN_MSK (0x1 << 19 )
9675#define ADC1CON_ADCEN (0x1 << 19 )
9676#define ADC1CON_ADCEN_DIS (0x0 << 19 ) /* DIS */
9677#define ADC1CON_ADCEN_EN (0x1 << 19 ) /* EN */
9678
9679/* ADC1CON[ADCCODE] - ADC Output Coding bits */
9680#define ADC1CON_ADCCODE_BBA (*(volatile unsigned long *) 0x42601148)
9681#define ADC1CON_ADCCODE_MSK (0x1 << 18 )
9682#define ADC1CON_ADCCODE (0x1 << 18 )
9683#define ADC1CON_ADCCODE_INT (0x0 << 18 ) /* INT */
9684#define ADC1CON_ADCCODE_UINT (0x1 << 18 ) /* UINT */
9685
9686/* ADC1CON[BUFPOWN] - Negative buffer power down */
9687#define ADC1CON_BUFPOWN_BBA (*(volatile unsigned long *) 0x42601144)
9688#define ADC1CON_BUFPOWN_MSK (0x1 << 17 )
9689#define ADC1CON_BUFPOWN (0x1 << 17 )
9690#define ADC1CON_BUFPOWN_DIS (0x0 << 17 ) /* Disable powerdown - Negative buffer is enabled */
9691#define ADC1CON_BUFPOWN_EN (0x1 << 17 ) /* Enable powerdown - Negative buffer is disabled */
9692
9693/* ADC1CON[BUFPOWP] - Positive buffer power down */
9694#define ADC1CON_BUFPOWP_BBA (*(volatile unsigned long *) 0x42601140)
9695#define ADC1CON_BUFPOWP_MSK (0x1 << 16 )
9696#define ADC1CON_BUFPOWP (0x1 << 16 )
9697#define ADC1CON_BUFPOWP_DIS (0x0 << 16 ) /* Disable powerdown - Positive buffer is enabled */
9698#define ADC1CON_BUFPOWP_EN (0x1 << 16 ) /* Enable powerdown - Positive buffer is disabled */
9699
9700/* ADC1CON[BUFBYPP] - Positive buffer bypass */
9701#define ADC1CON_BUFBYPP_BBA (*(volatile unsigned long *) 0x4260113C)
9702#define ADC1CON_BUFBYPP_MSK (0x1 << 15 )
9703#define ADC1CON_BUFBYPP (0x1 << 15 )
9704#define ADC1CON_BUFBYPP_DIS (0x0 << 15 ) /* DIS */
9705#define ADC1CON_BUFBYPP_EN (0x1 << 15 ) /* EN */
9706
9707/* ADC1CON[BUFBYPN] - Negative buffer bypass */
9708#define ADC1CON_BUFBYPN_BBA (*(volatile unsigned long *) 0x42601138)
9709#define ADC1CON_BUFBYPN_MSK (0x1 << 14 )
9710#define ADC1CON_BUFBYPN (0x1 << 14 )
9711#define ADC1CON_BUFBYPN_DIS (0x0 << 14 ) /* DIS */
9712#define ADC1CON_BUFBYPN_EN (0x1 << 14 ) /* EN */
9713
9714/* ADC1CON[ADCREF] - Reference selection */
9715#define ADC1CON_ADCREF_MSK (0x3 << 12 )
9716#define ADC1CON_ADCREF_INTREF (0x0 << 12 ) /* INTREF */
9717#define ADC1CON_ADCREF_EXTREF (0x1 << 12 ) /* EXTREF */
9718#define ADC1CON_ADCREF_EXTREF2 (0x2 << 12 ) /* EXTREF2 */
9719#define ADC1CON_ADCREF_AVDDREF (0x3 << 12 ) /* AVDDREF */
9720
9721/* ADC1CON[ADCDIAG] - Diagnostic Current bits bits */
9722#define ADC1CON_ADCDIAG_MSK (0x3 << 10 )
9723#define ADC1CON_ADCDIAG_DIAG_OFF (0x0 << 10 ) /* DIAG_OFF */
9724#define ADC1CON_ADCDIAG_DIAG_POS (0x1 << 10 ) /* DIAG_POS */
9725#define ADC1CON_ADCDIAG_DIAG_NEG (0x2 << 10 ) /* DIAG_NEG */
9726#define ADC1CON_ADCDIAG_DIAG_ALL (0x3 << 10 ) /* DIAG_ALL */
9727
9728/* ADC1CON[ADCCP] - AIN+ bits */
9729#define ADC1CON_ADCCP_MSK (0x1F << 5 )
9730#define ADC1CON_ADCCP_AIN0 (0x0 << 5 ) /* AIN0 */
9731#define ADC1CON_ADCCP_AIN1 (0x1 << 5 ) /* AIN1 */
9732#define ADC1CON_ADCCP_AIN2 (0x2 << 5 ) /* AIN2 */
9733#define ADC1CON_ADCCP_AIN3 (0x3 << 5 ) /* AIN3 */
9734#define ADC1CON_ADCCP_AIN4 (0x4 << 5 ) /* AIN4 */
9735#define ADC1CON_ADCCP_AIN5 (0x5 << 5 ) /* AIN5 */
9736#define ADC1CON_ADCCP_AIN6 (0x6 << 5 ) /* AIN6 */
9737#define ADC1CON_ADCCP_AIN7 (0x7 << 5 ) /* AIN7 */
9738#define ADC1CON_ADCCP_AIN8 (0x8 << 5 ) /* AIN8 */
9739#define ADC1CON_ADCCP_AIN9 (0x9 << 5 ) /* AIN9 */
9740#define ADC1CON_ADCCP_AIN10 (0xA << 5 ) /* AIN10 */
9741#define ADC1CON_ADCCP_AIN11 (0xB << 5 ) /* AIN11 */
9742#define ADC1CON_ADCCP_DAC (0xC << 5 ) /* DAC */
9743#define ADC1CON_ADCCP_AVDD4 (0xD << 5 ) /* AVDD4 */
9744#define ADC1CON_ADCCP_IOVDD4 (0xE << 5 ) /* IOVDD4 */
9745#define ADC1CON_ADCCP_AGND (0xF << 5 ) /* AGND */
9746#define ADC1CON_ADCCP_TEMP (0x10 << 5 ) /* TEMP */
9747
9748/* ADC1CON[ADCCN] - AIN- bits */
9749#define ADC1CON_ADCCN_MSK (0x1F << 0 )
9750#define ADC1CON_ADCCN_AIN0 (0x0 << 0 ) /* AIN0 */
9751#define ADC1CON_ADCCN_AIN1 (0x1 << 0 ) /* AIN1 */
9752#define ADC1CON_ADCCN_AIN2 (0x2 << 0 ) /* AIN2 */
9753#define ADC1CON_ADCCN_AIN3 (0x3 << 0 ) /* AIN3 */
9754#define ADC1CON_ADCCN_AIN4 (0x4 << 0 ) /* AIN4 */
9755#define ADC1CON_ADCCN_AIN5 (0x5 << 0 ) /* AIN5 */
9756#define ADC1CON_ADCCN_AIN6 (0x6 << 0 ) /* AIN6 */
9757#define ADC1CON_ADCCN_AIN7 (0x7 << 0 ) /* AIN7 */
9758#define ADC1CON_ADCCN_AIN8 (0x8 << 0 ) /* AIN8 */
9759#define ADC1CON_ADCCN_AIN9 (0x9 << 0 ) /* AIN9 */
9760#define ADC1CON_ADCCN_AIN10 (0xA << 0 ) /* AIN10 */
9761#define ADC1CON_ADCCN_AIN11 (0xB << 0 ) /* AIN11 */
9762#define ADC1CON_ADCCN_DAC (0xC << 0 ) /* DAC */
9763#define ADC1CON_ADCCN_AGND (0xF << 0 ) /* AGND */
9764#define ADC1CON_ADCCN_TEMP (0x11 << 0 ) /* TEMP */
9765
9766/* Reset Value for ADC1OF*/
9767#define ADC1OF_RVAL 0x0
9768
9769/* ADC1OF[VALUE] - Offset */
9770#define ADC1OF_VALUE_MSK (0xFFFF << 0 )
9771
9772/* Reset Value for ADC1INTGN*/
9773#define ADC1INTGN_RVAL 0x5555
9774
9775/* ADC1INTGN[VALUE] - Gain with Int Ref */
9776#define ADC1INTGN_VALUE_MSK (0xFFFF << 0 )
9777
9778/* Reset Value for ADC1EXTGN*/
9779#define ADC1EXTGN_RVAL 0x5555
9780
9781/* ADC1EXTGN[VALUE] - Gain with Ext Ref */
9782#define ADC1EXTGN_VALUE_MSK (0xFFFF << 0 )
9783
9784/* Reset Value for ADC1VDDGN*/
9785#define ADC1VDDGN_RVAL 0x5555
9786
9787/* ADC1VDDGN[VALUE] - Gain with Avdd Ref */
9788#define ADC1VDDGN_VALUE_MSK (0xFFFF << 0 )
9789
9790/* Reset Value for ADCSCFG1*/
9791#define ADCSCFG1_RVAL 0xF
9792
9793/* ADCSCFG1[SIMU] - Enable both ADCs */
9794#define ADCSCFG1_SIMU_BBA (*(volatile unsigned long *) 0x426013BC)
9795#define ADCSCFG1_SIMU_MSK (0x1 << 15 )
9796#define ADCSCFG1_SIMU (0x1 << 15 )
9797#define ADCSCFG1_SIMU_DIS (0x0 << 15 ) /* DIS */
9798#define ADCSCFG1_SIMU_EN (0x1 << 15 ) /* EN */
9799
9800/* ADCSCFG1[BOOST30] - Boost the Vbias current source ability by 30 times */
9801#define ADCSCFG1_BOOST30_BBA (*(volatile unsigned long *) 0x426013B4)
9802#define ADCSCFG1_BOOST30_MSK (0x1 << 13 )
9803#define ADCSCFG1_BOOST30 (0x1 << 13 )
9804#define ADCSCFG1_BOOST30_DIS (0x0 << 13 ) /* DIS */
9805#define ADCSCFG1_BOOST30_EN (0x1 << 13 ) /* EN */
9806
9807/* ADCSCFG1[PINSEL] - Enable vbias generator, send vbias to selected ain pin bits */
9808#define ADCSCFG1_PINSEL_MSK (0x7 << 8 )
9809#define ADCSCFG1_PINSEL_DIS (0x0 << 8 ) /* Disable VBIAS generator */
9810#define ADCSCFG1_PINSEL_AIN7 (0x4 << 8 ) /* AIN7 */
9811#define ADCSCFG1_PINSEL_AIN11 (0x6 << 8 ) /* AIN11 */
9812
9813/* ADCSCFG1[GNDSWON] - GND_SW */
9814#define ADCSCFG1_GNDSWON_BBA (*(volatile unsigned long *) 0x4260139C)
9815#define ADCSCFG1_GNDSWON_MSK (0x1 << 7 )
9816#define ADCSCFG1_GNDSWON (0x1 << 7 )
9817#define ADCSCFG1_GNDSWON_DIS (0x0 << 7 ) /* DIS */
9818#define ADCSCFG1_GNDSWON_EN (0x1 << 7 ) /* EN */
9819
9820/* ADCSCFG1[GNDSWRESEN] - 20k resistor in series with GND_SW */
9821#define ADCSCFG1_GNDSWRESEN_BBA (*(volatile unsigned long *) 0x42601398)
9822#define ADCSCFG1_GNDSWRESEN_MSK (0x1 << 6 )
9823#define ADCSCFG1_GNDSWRESEN (0x1 << 6 )
9824#define ADCSCFG1_GNDSWRESEN_DIS (0x0 << 6 ) /* DIS */
9825#define ADCSCFG1_GNDSWRESEN_EN (0x1 << 6 ) /* EN */
9826
9827/* ADCSCFG1[EXTBUF] - Control signals for ext_ref buffers bits */
9828#define ADCSCFG1_EXTBUF_MSK (0x3 << 0 )
9829#define ADCSCFG1_EXTBUF_OFF (0x0 << 0 ) /* OFF */
9830#define ADCSCFG1_EXTBUF_VREFPN (0x1 << 0 ) /* VREFPN */
9831#define ADCSCFG1_EXTBUF_VREFP_VREF2P (0x2 << 0 ) /* VREFP_VREF2P */
9832
9833/* Reset Value for ADC1FLT*/
9834#define ADC1FLT_RVAL 0x7D
9835
9836/* ADC1FLT[CHOP] - Enables System-Chopping bits */
9837#define ADC1FLT_CHOP_BBA (*(volatile unsigned long *) 0x4260143C)
9838#define ADC1FLT_CHOP_MSK (0x1 << 15 )
9839#define ADC1FLT_CHOP (0x1 << 15 )
9840#define ADC1FLT_CHOP_OFF (0x0 << 15 ) /* OFF */
9841#define ADC1FLT_CHOP_ON (0x1 << 15 ) /* ON */
9842
9843/* ADC1FLT[RAVG2] - Enables a running Average-By-2 bits */
9844#define ADC1FLT_RAVG2_BBA (*(volatile unsigned long *) 0x42601438)
9845#define ADC1FLT_RAVG2_MSK (0x1 << 14 )
9846#define ADC1FLT_RAVG2 (0x1 << 14 )
9847#define ADC1FLT_RAVG2_OFF (0x0 << 14 ) /* OFF */
9848#define ADC1FLT_RAVG2_ON (0x1 << 14 ) /* ON */
9849
9850/* ADC1FLT[SINC4EN] - Enable the Sinc4 filter instead of Sinc3 filter. */
9851#define ADC1FLT_SINC4EN_BBA (*(volatile unsigned long *) 0x42601430)
9852#define ADC1FLT_SINC4EN_MSK (0x1 << 12 )
9853#define ADC1FLT_SINC4EN (0x1 << 12 )
9854#define ADC1FLT_SINC4EN_DIS (0x0 << 12 ) /* DIS */
9855#define ADC1FLT_SINC4EN_EN (0x1 << 12 ) /* EN */
9856
9857/* ADC1FLT[AF] - Averaging filter */
9858#define ADC1FLT_AF_MSK (0xF << 8 )
9859
9860/* ADC1FLT[NOTCH2] - Inserts a notch at FNOTCH2 */
9861#define ADC1FLT_NOTCH2_BBA (*(volatile unsigned long *) 0x4260141C)
9862#define ADC1FLT_NOTCH2_MSK (0x1 << 7 )
9863#define ADC1FLT_NOTCH2 (0x1 << 7 )
9864#define ADC1FLT_NOTCH2_DIS (0x0 << 7 ) /* DIS */
9865#define ADC1FLT_NOTCH2_EN (0x1 << 7 ) /* EN */
9866
9867/* ADC1FLT[SF] - SINC Filter value */
9868#define ADC1FLT_SF_MSK (0x7F << 0 )
9869
9870/* Reset Value for ADC1MDE*/
9871#define ADC1MDE_RVAL 0x0
9872
9873/* ADC1MDE[PGA] - PGA Gain Select bit */
9874#define ADC1MDE_PGA_MSK (0xF << 4 )
9875#define ADC1MDE_PGA_G1 (0x0 << 4 ) /* G1 */
9876#define ADC1MDE_PGA_G2 (0x1 << 4 ) /* G2 */
9877#define ADC1MDE_PGA_G4 (0x2 << 4 ) /* G4 */
9878#define ADC1MDE_PGA_G8 (0x3 << 4 ) /* G8 */
9879#define ADC1MDE_PGA_G16 (0x4 << 4 ) /* G16 */
9880#define ADC1MDE_PGA_G32 (0x5 << 4 ) /* G32 */
9881#define ADC1MDE_PGA_G64 (0x6 << 4 ) /* G64 */
9882#define ADC1MDE_PGA_G128 (0x7 << 4 ) /* G128 */
9883
9884/* ADC1MDE[ADCMOD2] - ADC modulator gain of 2 control bits */
9885#define ADC1MDE_ADCMOD2_BBA (*(volatile unsigned long *) 0x4260148C)
9886#define ADC1MDE_ADCMOD2_MSK (0x1 << 3 )
9887#define ADC1MDE_ADCMOD2 (0x1 << 3 )
9888#define ADC1MDE_ADCMOD2_MOD2OFF (0x0 << 3 ) /* MOD2OFF */
9889#define ADC1MDE_ADCMOD2_MOD2ON (0x1 << 3 ) /* MOD2ON */
9890
9891/* ADC1MDE[ADCMD] - ADC Mode bits */
9892#define ADC1MDE_ADCMD_MSK (0x7 << 0 )
9893#define ADC1MDE_ADCMD_OFF (0x0 << 0 ) /* OFF */
9894#define ADC1MDE_ADCMD_CONT (0x1 << 0 ) /* CONT */
9895#define ADC1MDE_ADCMD_SINGLE (0x2 << 0 ) /* SINGLE */
9896#define ADC1MDE_ADCMD_IDLE (0x3 << 0 ) /* IDLE */
9897#define ADC1MDE_ADCMD_INTOCAL (0x4 << 0 ) /* INTOCAL */
9898#define ADC1MDE_ADCMD_INTGCAL (0x5 << 0 ) /* INTGCAL */
9899#define ADC1MDE_ADCMD_SYSOCAL (0x6 << 0 ) /* SYSOCAL */
9900#define ADC1MDE_ADCMD_SYSGCAL (0x7 << 0 ) /* SYSGCAL */
9901
9902/* Reset Value for ADC1RCR*/
9903#define ADC1RCR_RVAL 0x1
9904
9905/* ADC1RCR[VALUE] - */
9906#define ADC1RCR_VALUE_MSK (0xFFFF << 0 )
9907
9908/* Reset Value for ADC1RCV*/
9909#define ADC1RCV_RVAL 0x0
9910
9911/* ADC1RCV[VALUE] - */
9912#define ADC1RCV_VALUE_MSK (0xFFFF << 0 )
9913
9914/* Reset Value for ADC1TH*/
9915#define ADC1TH_RVAL 0x0
9916
9917/* ADC1TH[VALUE] - */
9918#define ADC1TH_VALUE_MSK (0xFFFF << 0 )
9919
9920/* Reset Value for ADC1THC*/
9921#define ADC1THC_RVAL 0x1
9922
9923/* ADC1THC[VALUE] - */
9924#define ADC1THC_VALUE_MSK (0xFF << 0 )
9925
9926/* Reset Value for ADC1THV*/
9927#define ADC1THV_RVAL 0x0
9928
9929/* ADC1THV[VALUE] - */
9930#define ADC1THV_VALUE_MSK (0xFF << 0 )
9931
9932/* Reset Value for ADC1ACC*/
9933#define ADC1ACC_RVAL 0x0
9934
9935/* ADC1ACC[VALUE] - */
9936#define ADC1ACC_VALUE_MSK (0xFFFFFFFF << 0 )
9937
9938/* Reset Value for ADC1ATH*/
9939#define ADC1ATH_RVAL 0x0
9940
9941/* ADC1ATH[VALUE] - */
9942#define ADC1ATH_VALUE_MSK (0xFFFFFFFF << 0 )
9943
9944/* Reset Value for ADC1PRO*/
9945#define ADC1PRO_RVAL 0x0
9946
9947/* ADC1PRO[ACCEN] - ADC Accumulator Enable bits */
9948#define ADC1PRO_ACCEN_MSK (0x3 << 4 )
9949#define ADC1PRO_ACCEN_Off (0x0 << 4 ) /* Off */
9950#define ADC1PRO_ACCEN_En (0x1 << 4 ) /* En */
9951#define ADC1PRO_ACCEN_EnNDec (0x2 << 4 ) /* EnNDec */
9952#define ADC1PRO_ACCEN_EnAccCnt (0x3 << 4 ) /* EnAccCnt */
9953
9954/* ADC1PRO[CMPEN] - ADC Comparator Enable bits */
9955#define ADC1PRO_CMPEN_MSK (0x3 << 2 )
9956#define ADC1PRO_CMPEN_Off (0x0 << 2 ) /* Off */
9957#define ADC1PRO_CMPEN_En (0x1 << 2 ) /* En */
9958#define ADC1PRO_CMPEN_EnCnt (0x2 << 2 ) /* EnCnt */
9959#define ADC1PRO_CMPEN_EnCntDec (0x3 << 2 ) /* EnCntDec */
9960
9961/* ADC1PRO[OREN] - ADC OverRange Enable */
9962#define ADC1PRO_OREN_BBA (*(volatile unsigned long *) 0x42601884)
9963#define ADC1PRO_OREN_MSK (0x1 << 1 )
9964#define ADC1PRO_OREN (0x1 << 1 )
9965#define ADC1PRO_OREN_DIS (0x0 << 1 ) /* DIS */
9966#define ADC1PRO_OREN_EN (0x1 << 1 ) /* EN */
9967
9968/* ADC1PRO[RCEN] - ADC Result Counter Enable */
9969#define ADC1PRO_RCEN_BBA (*(volatile unsigned long *) 0x42601880)
9970#define ADC1PRO_RCEN_MSK (0x1 << 0 )
9971#define ADC1PRO_RCEN (0x1 << 0 )
9972#define ADC1PRO_RCEN_DIS (0x0 << 0 ) /* DIS */
9973#define ADC1PRO_RCEN_EN (0x1 << 0 ) /* EN */
9974
9975/* Reset Value for ADC1DAT*/
9976#define ADC1DAT_RVAL 0x0
9977
9978/* ADC1DAT[VALUE] - */
9979#define ADC1DAT_VALUE_MSK (0xFFFFFFFF << 0 )
9980// ------------------------------------------------------------------------------------------------
9981// ----- ADCSTEP -----
9982// ------------------------------------------------------------------------------------------------
9983
9984
9985/**
9986 * @brief Analog to Digital Converter (pADI_ADCSTEP)
9987 */
9988
9989#if (__NO_MMR_STRUCTS__==0)
9990typedef struct { /*!< pADI_ADCSTEP Structure */
9991 __IO uint16_t DETCON; /*!< Control register for reference detection and the step detection filter */
9992 __I uint16_t RESERVED0;
9993 __IO uint8_t DETSTA; /*!< Status register for detection */
9994 __I uint8_t RESERVED1[3];
9995 __IO uint16_t STEPTH; /*!< Threshold for step detection filter */
9996 __I uint16_t RESERVED2;
9997 __IO uint32_t STEPDAT; /*!< Offers coarse data from the output of the step detection filter */
9998} ADI_ADCSTEP_TypeDef;
9999#else // (__NO_MMR_STRUCTS__==0)
10000#define DETCON (*(volatile unsigned short int *) 0x400300E0)
10001#define DETSTA (*(volatile unsigned char *) 0x400300E4)
10002#define STEPTH (*(volatile unsigned short int *) 0x400300E8)
10003#define STEPDAT (*(volatile unsigned long *) 0x400300EC)
10004#endif // (__NO_MMR_STRUCTS__==0)
10005
10006/* Reset Value for DETCON*/
10007#define DETCON_RVAL 0x0
10008
10009/* DETCON[REFDET] - Enable external reference detection circuit */
10010#define DETCON_REFDET_BBA (*(volatile unsigned long *) 0x42601C20)
10011#define DETCON_REFDET_MSK (0x1 << 8 )
10012#define DETCON_REFDET (0x1 << 8 )
10013#define DETCON_REFDET_DIS (0x0 << 8 ) /* DIS */
10014#define DETCON_REFDET_EN (0x1 << 8 ) /* EN */
10015
10016/* DETCON[SINC2] - Enable Sinc2 filter */
10017#define DETCON_SINC2_BBA (*(volatile unsigned long *) 0x42601C1C)
10018#define DETCON_SINC2_MSK (0x1 << 7 )
10019#define DETCON_SINC2 (0x1 << 7 )
10020#define DETCON_SINC2_DIS (0x0 << 7 ) /* DIS */
10021#define DETCON_SINC2_EN (0x1 << 7 ) /* EN */
10022
10023/* DETCON[STEPCTRL] - Control the method to generate the step flag */
10024#define DETCON_STEPCTRL_BBA (*(volatile unsigned long *) 0x42601C0C)
10025#define DETCON_STEPCTRL_MSK (0x1 << 3 )
10026#define DETCON_STEPCTRL (0x1 << 3 )
10027#define DETCON_STEPCTRL_DIS (0x0 << 3 ) /* DIS */
10028#define DETCON_STEPCTRL_EN (0x1 << 3 ) /* EN */
10029
10030/* DETCON[ADCSEL] - Select ADC */
10031#define DETCON_ADCSEL_BBA (*(volatile unsigned long *) 0x42601C08)
10032#define DETCON_ADCSEL_MSK (0x1 << 2 )
10033#define DETCON_ADCSEL (0x1 << 2 )
10034#define DETCON_ADCSEL_DIS (0x0 << 2 ) /* DIS */
10035#define DETCON_ADCSEL_EN (0x1 << 2 ) /* EN */
10036
10037/* DETCON[RATE] - Control the sinc2 filter's time interval */
10038#define DETCON_RATE_MSK (0x3 << 0 )
10039
10040/* Reset Value for DETSTA*/
10041#define DETSTA_RVAL 0x0
10042
10043/* DETSTA[REFSTA] - */
10044#define DETSTA_REFSTA_BBA (*(volatile unsigned long *) 0x42601C90)
10045#define DETSTA_REFSTA_MSK (0x1 << 4 )
10046#define DETSTA_REFSTA (0x1 << 4 )
10047#define DETSTA_REFSTA_DIS (0x0 << 4 ) /* DIS */
10048#define DETSTA_REFSTA_EN (0x1 << 4 ) /* EN */
10049
10050/* DETSTA[DATOF] - STEPDAT Overflow */
10051#define DETSTA_DATOF_BBA (*(volatile unsigned long *) 0x42601C8C)
10052#define DETSTA_DATOF_MSK (0x1 << 3 )
10053#define DETSTA_DATOF (0x1 << 3 )
10054#define DETSTA_DATOF_DIS (0x0 << 3 ) /* DIS */
10055#define DETSTA_DATOF_EN (0x1 << 3 ) /* EN */
10056
10057/* DETSTA[STEPERR] - */
10058#define DETSTA_STEPERR_BBA (*(volatile unsigned long *) 0x42601C88)
10059#define DETSTA_STEPERR_MSK (0x1 << 2 )
10060#define DETSTA_STEPERR (0x1 << 2 )
10061#define DETSTA_STEPERR_DIS (0x0 << 2 ) /* DIS */
10062#define DETSTA_STEPERR_EN (0x1 << 2 ) /* EN */
10063
10064/* DETSTA[STEPFLAG] - */
10065#define DETSTA_STEPFLAG_BBA (*(volatile unsigned long *) 0x42601C84)
10066#define DETSTA_STEPFLAG_MSK (0x1 << 1 )
10067#define DETSTA_STEPFLAG (0x1 << 1 )
10068#define DETSTA_STEPFLAG_DIS (0x0 << 1 ) /* DIS */
10069#define DETSTA_STEPFLAG_EN (0x1 << 1 ) /* EN */
10070
10071/* DETSTA[STEPDATRDY] - */
10072#define DETSTA_STEPDATRDY_BBA (*(volatile unsigned long *) 0x42601C80)
10073#define DETSTA_STEPDATRDY_MSK (0x1 << 0 )
10074#define DETSTA_STEPDATRDY (0x1 << 0 )
10075#define DETSTA_STEPDATRDY_DIS (0x0 << 0 ) /* DIS */
10076#define DETSTA_STEPDATRDY_EN (0x1 << 0 ) /* EN */
10077
10078/* Reset Value for STEPTH*/
10079#define STEPTH_RVAL 0x0
10080
10081/* STEPTH[VALUE] - */
10082#define STEPTH_VALUE_MSK (0x1FF << 0 )
10083
10084/* Reset Value for STEPDAT*/
10085#define STEPDAT_RVAL 0x0
10086
10087/* STEPDAT[VALUE] - */
10088#define STEPDAT_VALUE_MSK (0xFFFFFFFF << 0 )
10089// ------------------------------------------------------------------------------------------------
10090// ----- ADCDMA -----
10091// ------------------------------------------------------------------------------------------------
10092
10093
10094/**
10095 * @brief Analog to Digital Converter (pADI_ADCDMA)
10096 */
10097
10098#if (__NO_MMR_STRUCTS__==0)
10099typedef struct { /*!< pADI_ADCDMA Structure */
10100 __I uint32_t RESERVED0[2];
10101 __IO uint16_t ADCDMACON; /*!< ADC DMA mode Configuration register */
10102} ADI_ADCDMA_TypeDef;
10103#else // (__NO_MMR_STRUCTS__==0)
10104#define ADCDMACON (*(volatile unsigned short int *) 0x400300F8)
10105#endif // (__NO_MMR_STRUCTS__==0)
10106
10107/* Reset Value for ADCDMACON*/
10108#define ADCDMACON_RVAL 0x0
10109
10110/* ADCDMACON[SINC2DMAEN] - */
10111#define ADCDMACON_SINC2DMAEN_BBA (*(volatile unsigned long *) 0x42601F10)
10112#define ADCDMACON_SINC2DMAEN_MSK (0x1 << 4 )
10113#define ADCDMACON_SINC2DMAEN (0x1 << 4 )
10114#define ADCDMACON_SINC2DMAEN_DIS (0x0 << 4 ) /* DIS */
10115#define ADCDMACON_SINC2DMAEN_EN (0x1 << 4 ) /* EN */
10116
10117/* ADCDMACON[ADC1DMAEN] - */
10118#define ADCDMACON_ADC1DMAEN_BBA (*(volatile unsigned long *) 0x42601F0C)
10119#define ADCDMACON_ADC1DMAEN_MSK (0x1 << 3 )
10120#define ADCDMACON_ADC1DMAEN (0x1 << 3 )
10121#define ADCDMACON_ADC1DMAEN_DIS (0x0 << 3 ) /* DIS */
10122#define ADCDMACON_ADC1DMAEN_EN (0x1 << 3 ) /* EN */
10123
10124/* ADCDMACON[ADC1CTRL] - */
10125#define ADCDMACON_ADC1CTRL_BBA (*(volatile unsigned long *) 0x42601F08)
10126#define ADCDMACON_ADC1CTRL_MSK (0x1 << 2 )
10127#define ADCDMACON_ADC1CTRL (0x1 << 2 )
10128#define ADCDMACON_ADC1CTRL_DIS (0x0 << 2 ) /* DIS */
10129#define ADCDMACON_ADC1CTRL_EN (0x1 << 2 ) /* EN */
10130
10131/* ADCDMACON[ADC0DMAEN] - */
10132#define ADCDMACON_ADC0DMAEN_BBA (*(volatile unsigned long *) 0x42601F04)
10133#define ADCDMACON_ADC0DMAEN_MSK (0x1 << 1 )
10134#define ADCDMACON_ADC0DMAEN (0x1 << 1 )
10135#define ADCDMACON_ADC0DMAEN_DIS (0x0 << 1 ) /* DIS */
10136#define ADCDMACON_ADC0DMAEN_EN (0x1 << 1 ) /* EN */
10137
10138/* ADCDMACON[ADC0CTRL] - */
10139#define ADCDMACON_ADC0CTRL_BBA (*(volatile unsigned long *) 0x42601F00)
10140#define ADCDMACON_ADC0CTRL_MSK (0x1 << 0 )
10141#define ADCDMACON_ADC0CTRL (0x1 << 0 )
10142#define ADCDMACON_ADC0CTRL_DIS (0x0 << 0 ) /* DIS */
10143#define ADCDMACON_ADC0CTRL_EN (0x1 << 0 ) /* EN */
10144// ------------------------------------------------------------------------------------------------
10145// ----- DAC -----
10146// ------------------------------------------------------------------------------------------------
10147
10148
10149/**
10150 * @brief Digital To Analog Converter (pADI_DAC)
10151 */
10152
10153#if (__NO_MMR_STRUCTS__==0)
10154typedef struct { /*!< pADI_DAC Structure */
10155 __IO uint16_t DACCON; /*!< Control Register */
10156 __I uint16_t RESERVED0;
10157 __IO uint32_t DACDAT; /*!< Data Register */
10158} ADI_DAC_TypeDef;
10159#else // (__NO_MMR_STRUCTS__==0)
10160#define DACCON (*(volatile unsigned short int *) 0x40020000)
10161#define DACDAT (*(volatile unsigned long *) 0x40020004)
10162#endif // (__NO_MMR_STRUCTS__==0)
10163
10164/* Reset Value for DACCON*/
10165#define DACCON_RVAL 0x200
10166
10167/* DACCON[DMAEN] - bits */
10168#define DACCON_DMAEN_BBA (*(volatile unsigned long *) 0x42400028)
10169#define DACCON_DMAEN_MSK (0x1 << 10 )
10170#define DACCON_DMAEN (0x1 << 10 )
10171#define DACCON_DMAEN_Off (0x0 << 10 ) /* Off */
10172#define DACCON_DMAEN_On (0x1 << 10 ) /* On */
10173
10174/* DACCON[PD] - */
10175#define DACCON_PD_BBA (*(volatile unsigned long *) 0x42400024)
10176#define DACCON_PD_MSK (0x1 << 9 )
10177#define DACCON_PD (0x1 << 9 )
10178#define DACCON_PD_DIS (0x0 << 9 ) /* DIS */
10179#define DACCON_PD_EN (0x1 << 9 ) /* EN */
10180
10181/* DACCON[NPN] - */
10182#define DACCON_NPN_BBA (*(volatile unsigned long *) 0x42400020)
10183#define DACCON_NPN_MSK (0x1 << 8 )
10184#define DACCON_NPN (0x1 << 8 )
10185#define DACCON_NPN_DIS (0x0 << 8 ) /* DIS */
10186#define DACCON_NPN_EN (0x1 << 8 ) /* EN */
10187
10188/* DACCON[BUFBYP] - */
10189#define DACCON_BUFBYP_BBA (*(volatile unsigned long *) 0x42400018)
10190#define DACCON_BUFBYP_MSK (0x1 << 6 )
10191#define DACCON_BUFBYP (0x1 << 6 )
10192#define DACCON_BUFBYP_DIS (0x0 << 6 ) /* DIS */
10193#define DACCON_BUFBYP_EN (0x1 << 6 ) /* EN */
10194
10195/* DACCON[CLK] - bits */
10196#define DACCON_CLK_BBA (*(volatile unsigned long *) 0x42400014)
10197#define DACCON_CLK_MSK (0x1 << 5 )
10198#define DACCON_CLK (0x1 << 5 )
10199#define DACCON_CLK_HCLK (0x0 << 5 ) /* HCLK */
10200#define DACCON_CLK_Timer1 (0x1 << 5 ) /* Timer1 */
10201
10202/* DACCON[CLR] - bits */
10203#define DACCON_CLR_BBA (*(volatile unsigned long *) 0x42400010)
10204#define DACCON_CLR_MSK (0x1 << 4 )
10205#define DACCON_CLR (0x1 << 4 )
10206#define DACCON_CLR_Off (0x1 << 4 ) /* Off */
10207#define DACCON_CLR_On (0x0 << 4 ) /* On */
10208
10209/* DACCON[MDE] - Mode bits */
10210#define DACCON_MDE_MSK (0x3 << 2 )
10211#define DACCON_MDE_12bit (0x0 << 2 ) /* 12bit */
10212#define DACCON_MDE_16BitSlow (0x3 << 2 ) /* 16BitSlow */
10213#define DACCON_MDE_16BitFast (0x2 << 2 ) /* 16BitFast */
10214
10215/* DACCON[RNG] - DAC Range bits */
10216#define DACCON_RNG_MSK (0x3 << 0 )
10217#define DACCON_RNG_IntVref (0x0 << 0 ) /* IntVref */
10218#define DACCON_RNG_AVdd (0x3 << 0 ) /* AVdd */
10219
10220/* Reset Value for DACDAT*/
10221#define DACDAT_RVAL 0x0
10222
10223/* DACDAT[VALUE] - Data */
10224#define DACDAT_VALUE_MSK (0xFFFFF << 12 )
10225/********************************************
10226** End of section using anonymous unions **
10227*********************************************/
10228
10229#if defined(__ARMCC_VERSION)
10230 #pragma pop
10231#elif defined(__CWCC__)
10232 #pragma pop
10233#elif defined(__GNUC__)
10234 /* leave anonymous unions enabled */
10235#elif defined(__IAR_SYSTEMS_ICC__)
10236 #pragma language=default
10237#else
10238 #error Not supported compiler type
10239#endif
10240
10241/********************************************
10242** Miscellaneous Definitions **
10243*********************************************/
10244
10245//iEiNr in EiCfg()
10246#define EXTINT0 0x0
10247#define EXTINT1 0x1
10248#define EXTINT2 0x2
10249#define EXTINT3 0x3
10250#define EXTINT4 0x4
10251#define EXTINT5 0x5
10252#define EXTINT6 0x6
10253#define EXTINT7 0x7
10254#define EXTINT8 0x8
10255
10256//iEnable in EiCfg()
10257#define INT_DIS 0x0
10258#define INT_EN 0x1
10259
10260//iMode in EiCfg()
10261#define INT_RISE 0x0
10262#define INT_FALL 0x1
10263#define INT_EDGES 0x2
10264#define INT_HIGH 0x3
10265#define INT_LOW 0x4
10266
10267//Bit values.
10268#define BIT0 1
10269#define BIT1 2
10270#define BIT2 4
10271#define BIT3 8
10272#define BIT4 0x10
10273#define BIT5 0x20
10274#define BIT6 0x40
10275#define BIT7 0x80
10276
10277
10278// ------------------------------------------------------------------------------------------------
10279// ----- Peripheral memory map -----
10280// ------------------------------------------------------------------------------------------------
10281#define ADI_TM0_ADDR 0x40000000
10282#define ADI_TM1_ADDR 0x40000400
10283#define ADI_PWM_ADDR 0x40001000
10284#define ADI_PWRCTL_ADDR 0x40002400
10285#define ADI_RESET_ADDR 0x40002440
10286#define ADI_INTERRUPT_ADDR 0x40002420
10287#define ADI_WDT_ADDR 0x40002580
10288#define ADI_WUT_ADDR 0x40002500
10289#define ADI_CLKCTL_ADDR 0x40002000
10290#define ADI_FEE_ADDR 0x40002800
10291#define ADI_I2C_ADDR 0x40003000
10292#define ADI_SPI0_ADDR 0x40004000
10293#define ADI_SPI1_ADDR 0x40004400
10294#define ADI_UART_ADDR 0x40005000
10295#define ADI_UART1_ADDR 0x40005400
10296#define ADI_UART2_ADDR 0x40005800
10297#define ADI_GP0_ADDR 0x40006000
10298#define ADI_GP1_ADDR 0x40006030
10299#define ADI_GP2_ADDR 0x40006060
10300#define ADI_GP3_ADDR 0x40006090
10301#define ADI_ANA_ADDR 0x40008810
10302#define ADI_DMA_ADDR 0x40010000
10303#define ADI_NVIC_ADDR 0xE000E000
10304#define ADI_ADC0_ADDR 0x40030000
10305#define ADI_ADC1_ADDR 0x40030080
10306#define ADI_ADCSTEP_ADDR 0x400300E0
10307#define ADI_ADCTEST_ADDR 0x40030050
10308#define ADI_ADCDMA_ADDR 0x400300F0
10309#define ADI_EREFBUF_ADDR 0x400300D0
10310#define ADI_DAC_ADDR 0x40020000
10311
10312// ------------------------------------------------------------------------------------------------
10313// ----- Peripheral declaration -----
10314// ------------------------------------------------------------------------------------------------
10315#define pADI_TM0 ((ADI_TIMER_TypeDef *)ADI_TM0_ADDR)
10316#define pADI_TM1 ((ADI_TIMER_TypeDef *)ADI_TM1_ADDR)
10317#define pADI_PWM ((ADI_PWM_TypeDef *)ADI_PWM_ADDR)
10318#define pADI_PWRCTL ((ADI_PWRCTL_TypeDef *)ADI_PWRCTL_ADDR)
10319#define pADI_RESET ((ADI_RESET_TypeDef *)ADI_RESET_ADDR)
10320#define pADI_INTERRUPT ((ADI_INTERRUPT_TypeDef *)ADI_INTERRUPT_ADDR)
10321#define pADI_WDT ((ADI_WDT_TypeDef *)ADI_WDT_ADDR)
10322#define pADI_WUT ((ADI_WUT_TypeDef *)ADI_WUT_ADDR)
10323#define pADI_CLKCTL ((ADI_CLKCTL_TypeDef *)ADI_CLKCTL_ADDR)
10324#define pADI_FEE ((ADI_FEE_TypeDef *)ADI_FEE_ADDR)
10325#define pADI_I2C ((ADI_I2C_TypeDef *)ADI_I2C_ADDR)
10326#define pADI_SPI0 ((ADI_SPI_TypeDef *)ADI_SPI0_ADDR)
10327#define pADI_SPI1 ((ADI_SPI_TypeDef *)ADI_SPI1_ADDR)
10328#define pADI_UART ((ADI_UART_TypeDef *)ADI_UART_ADDR)
10329#define pADI_UART1 ((ADI_UART_TypeDef *)ADI_UART1_ADDR)
10330#define pADI_UART2 ((ADI_UART_TypeDef *)ADI_UART2_ADDR)
10331#define pADI_GP0 ((ADI_GPIO_TypeDef *)ADI_GP0_ADDR)
10332#define pADI_GP1 ((ADI_GPIO_TypeDef *)ADI_GP1_ADDR)
10333#define pADI_GP2 ((ADI_GPIO_TypeDef *)ADI_GP2_ADDR)
10334#define pADI_GP3 ((ADI_GPIO_TypeDef *)ADI_GP3_ADDR)
10335#define pADI_ANA ((ADI_ANA_TypeDef *)ADI_ANA_ADDR)
10336#define pADI_DMA ((ADI_DMA_TypeDef *)ADI_DMA_ADDR)
10337#define pADI_ADC0 ((ADI_ADC_TypeDef *)ADI_ADC0_ADDR)
10338#define pADI_ADC1 ((ADI_ADC_TypeDef *)ADI_ADC1_ADDR)
10339#define pADI_ADCSTEP ((ADI_ADCSTEP_TypeDef *)ADI_ADCSTEP_ADDR)
10340#define pADI_ADCDMA ((ADI_ADCDMA_TypeDef *)ADI_ADCDMA_ADDR)
10341#define pADI_DAC ((ADI_DAC_TypeDef *)ADI_DAC_ADDR)
10342
10343/** @} */ /* End of group Device_Peripheral_Registers */
10344/** @} */ /* End of group ADUCM362 */
10345/** @} */ /* End of group CMSIS */
10346
10347#ifdef __cplusplus
10348}
10349#endif
10350
10351
10352#endif // __ADUCM362_H__
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