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-rw-r--r--lib/chibios/os/common/ext/ADI/ADUCM36x/ADuCM360.h10031
-rw-r--r--lib/chibios/os/common/ext/ADI/ADUCM36x/ADuCM361.h9458
-rw-r--r--lib/chibios/os/common/ext/ADI/ADUCM36x/ADuCM362.h10352
-rw-r--r--lib/chibios/os/common/ext/ADI/ADUCM36x/ADuCM363.h9830
-rw-r--r--lib/chibios/os/common/ext/ADI/ADUCM36x/ADuCM36x.h16
-rw-r--r--lib/chibios/os/common/ext/ADI/ADUCM36x/system_ADuCM360.h112
-rw-r--r--lib/chibios/os/common/ext/ADI/ADUCM36x/system_ADuCM361.h112
-rw-r--r--lib/chibios/os/common/ext/ADI/ADUCM36x/system_ADuCM362.h113
-rw-r--r--lib/chibios/os/common/ext/ADI/ADUCM36x/system_ADuCM363.h112
-rw-r--r--lib/chibios/os/common/ext/ADI/ADUCM41x/ADuCM410.h7327
-rw-r--r--lib/chibios/os/common/ext/ADI/ADUCM41x/ADuCM41x.h10
-rw-r--r--lib/chibios/os/common/ext/ADI/ADUCM41x/system_ADuCM410.h45
12 files changed, 47518 insertions, 0 deletions
diff --git a/lib/chibios/os/common/ext/ADI/ADUCM36x/ADuCM360.h b/lib/chibios/os/common/ext/ADI/ADUCM36x/ADuCM360.h
new file mode 100644
index 000000000..9d65c8b0e
--- /dev/null
+++ b/lib/chibios/os/common/ext/ADI/ADUCM36x/ADuCM360.h
@@ -0,0 +1,10031 @@
1/**************************************************************************//**
2 * @file ADUCM360.h
3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
4 * Device ADUCM360
5 * @version V3.10
6 * @date 23. November 2012
7 *
8 * @note
9 *
10 ******************************************************************************/
11/* Copyright (c) 2012 ARM LIMITED
12
13 All rights reserved.
14 Redistribution and use in source and binary forms, with or without
15 modification, are permitted provided that the following conditions are met:
16 - Redistributions of source code must retain the above copyright
17 notice, this list of conditions and the following disclaimer.
18 - Redistributions in binary form must reproduce the above copyright
19 notice, this list of conditions and the following disclaimer in the
20 documentation and/or other materials provided with the distribution.
21 - Neither the name of ARM nor the names of its contributors may be used
22 to endorse or promote products derived from this software without
23 specific prior written permission.
24 *
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 POSSIBILITY OF SUCH DAMAGE.
36
37 Portions Copyright (c) 2017-2018 Analog Devices, Inc.
38 ---------------------------------------------------------------------------*/
39
40/** @addtogroup CMSIS
41 * @{
42 */
43
44/** @addtogroup ADUCM360
45 * @{
46 */
47
48#ifndef __ADUCM360_H__
49#define __ADUCM360_H__
50
51#ifndef __NO_MMR_STRUCTS__
52// The new style CMSIS structure definitions for MMRs clash with
53// the old style defs. If the old style are required for compilation
54// then set __NO_MMR_STRUCTS__ to 0x1
55#define __NO_MMR_STRUCTS__ 0x0
56#endif
57
58#ifdef __cplusplus
59extern "C" {
60#endif
61
62
63
64/********************************************
65** Start of section using anonymous unions **
66*********************************************/
67
68#if defined(__ARMCC_VERSION)
69 #pragma push
70 #pragma anon_unions
71#elif defined(__CWCC__)
72 #pragma push
73 #pragma cpp_extensions on
74#elif defined(__GNUC__)
75 /* anonymous unions are enabled by default */
76#elif defined(__IAR_SYSTEMS_ICC__)
77 #pragma language=extended
78#else
79 #error Not supported compiler type
80#endif
81
82
83 /* Interrupt Number Definition */
84
85typedef enum {
86// ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
87 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
88 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
89 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
90 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
91 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
92 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
93 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
94 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
95 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
96 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
97// -------------------------- ADUCM360 Specific Interrupt Numbers ------------------------------
98 WUT_IRQn = 0, /*!< 0 WUT */
99 EINT0_IRQn = 1, /*!< 1 EINT0 */
100 EINT1_IRQn = 2, /*!< 2 EINT1 */
101 EINT2_IRQn = 3, /*!< 3 EINT2 */
102 EINT3_IRQn = 4, /*!< 4 EINT3 */
103 EINT4_IRQn = 5, /*!< 5 EINT4 */
104 EINT5_IRQn = 6, /*!< 6 EINT5 */
105 EINT6_IRQn = 7, /*!< 7 EINT6 */
106 EINT7_IRQn = 8, /*!< 8 EINT7 */
107 WDT_IRQn = 9, /*!< 9 WDT */
108 TIMER0_IRQn = 11, /*!< 11 TIMER0 */
109 TIMER1_IRQn = 12, /*!< 12 TIMER1 */
110 ADC0_IRQn = 13, /*!< 13 ADC0 */
111 ADC1_IRQn = 14, /*!< 14 ADC1 */
112 SINC2_IRQn = 15, /*!< 15 SINC2 */
113 FLASH_IRQn = 16, /*!< 16 FLASH */
114 UART_IRQn = 17, /*!< 17 UART */
115 SPI0_IRQn = 18, /*!< 18 SPI0 */
116 SPI1_IRQn = 19, /*!< 19 SPI1 */
117 I2CS_IRQn = 20, /*!< 20 I2CS */
118 I2CM_IRQn = 21, /*!< 21 I2CM */
119 DMA_ERR_IRQn = 22, /*!< 22 DMA_ERR */
120 DMA_SPI1_TX_IRQn = 23, /*!< 23 DMA_SPI1_TX */
121 DMA_SPI1_RX_IRQn = 24, /*!< 24 DMA_SPI1_RX */
122 DMA_UART_TX_IRQn = 25, /*!< 25 DMA_UART_TX */
123 DMA_UART_RX_IRQn = 26, /*!< 26 DMA_UART_RX */
124 DMA_I2CS_TX_IRQn = 27, /*!< 27 DMA_I2CS_TX */
125 DMA_I2CS_RX_IRQn = 28, /*!< 28 DMA_I2CS_RX */
126 DMA_I2CM_TX_IRQn = 29, /*!< 29 DMA_I2CM_TX */
127 DMA_I2CM_RX_IRQn = 30, /*!< 30 DMA_I2CM_RX */
128 DMA_DAC_IRQn = 31, /*!< 31 DMA_DAC */
129 DMA_ADC0_IRQn = 32, /*!< 32 DMA_ADC0 */
130 DMA_ADC1_IRQn = 33, /*!< 33 DMA_ADC1 */
131 DMA_SINC2_IRQn = 34, /*!< 34 DMA_SINC2 */
132 PWM_TRIP_IRQn = 35, /*!< 35 PWM_TRIP */
133 PWM_PAIR0_IRQn = 36, /*!< 36 PWM_PAIR0 */
134 PWM_PAIR1_IRQn = 37, /*!< 37 PWM_PAIR1 */
135 PWM_PAIR2_IRQn = 38, /*!< 38 PWM_PAIR2 */
136} IRQn_Type;
137
138
139/** @addtogroup Configuration_of_CMSIS
140 * @{
141 */
142
143/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
144
145#define __CM3_REV 0x0200 /*!< Cortex-M3 Core Revision r2p0 */
146#define __MPU_PRESENT 0 /*!< MPU present or not */
147#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
148#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
149/** @} */ /* End of group Configuration_of_CMSIS */
150
151#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
152#include "system_ADuCM360.h" /*!< ADUCM360 System */
153
154/** @addtogroup Device_Peripheral_Registers
155 * @{
156 */
157
158
159
160/* ADCCON[ADCEN] - Enable Bit */
161#define ADCCON_ADCEN_MSK (0x1 << 19 )
162#define ADCCON_ADCEN (0x1 << 19 )
163#define ADCCON_ADCEN_DIS (0x0 << 19 ) /* DIS */
164#define ADCCON_ADCEN_EN (0x1 << 19 ) /* EN */
165
166/* ADCCON[ADCCODE] - ADC Output Coding bits */
167#define ADCCON_ADCCODE_MSK (0x1 << 18 )
168#define ADCCON_ADCCODE (0x1 << 18 )
169#define ADCCON_ADCCODE_INT (0x0 << 18 ) /* INT */
170#define ADCCON_ADCCODE_UINT (0x1 << 18 ) /* UINT */
171
172/* ADCCON[BUFPOWN] - Negative buffer power down */
173#define ADCCON_BUFPOWN_MSK (0x1 << 17 )
174#define ADCCON_BUFPOWN (0x1 << 17 )
175#define ADCCON_BUFPOWN_DIS (0x0 << 17 ) /* Disable powerdown - Negative buffer is enabled */
176#define ADCCON_BUFPOWN_EN (0x1 << 17 ) /* Enable powerdown - Negative buffer is disabled */
177
178/* ADCCON[BUFPOWP] - Positive buffer power down */
179#define ADCCON_BUFPOWP_MSK (0x1 << 16 )
180#define ADCCON_BUFPOWP (0x1 << 16 )
181#define ADCCON_BUFPOWP_DIS (0x0 << 16 ) /* Disable powerdown - Positive buffer is enabled */
182#define ADCCON_BUFPOWP_EN (0x1 << 16 ) /* Enable powerdown - Positive buffer is disabled */
183
184/* ADCCON[BUFBYPP] - Positive buffer bypass */
185#define ADCCON_BUFBYPP_MSK (0x1 << 15 )
186#define ADCCON_BUFBYPP (0x1 << 15 )
187#define ADCCON_BUFBYPP_DIS (0x0 << 15 ) /* DIS */
188#define ADCCON_BUFBYPP_EN (0x1 << 15 ) /* EN */
189
190/* ADCCON[BUFBYPN] - Negative buffer bypass */
191#define ADCCON_BUFBYPN_MSK (0x1 << 14 )
192#define ADCCON_BUFBYPN (0x1 << 14 )
193#define ADCCON_BUFBYPN_DIS (0x0 << 14 ) /* DIS */
194#define ADCCON_BUFBYPN_EN (0x1 << 14 ) /* EN */
195
196/* ADCCON[ADCREF] - Reference selection */
197#define ADCCON_ADCREF_MSK (0x3 << 12 )
198#define ADCCON_ADCREF_INTREF (0x0 << 12 ) /* INTREF */
199#define ADCCON_ADCREF_EXTREF (0x1 << 12 ) /* EXTREF */
200#define ADCCON_ADCREF_EXTREF2 (0x2 << 12 ) /* EXTREF2 */
201#define ADCCON_ADCREF_AVDDREF (0x3 << 12 ) /* AVDDREF */
202
203/* ADCCON[ADCDIAG] - Diagnostic Current bits bits */
204#define ADCCON_ADCDIAG_MSK (0x3 << 10 )
205#define ADCCON_ADCDIAG_DIAG_OFF (0x0 << 10 ) /* DIAG_OFF */
206#define ADCCON_ADCDIAG_DIAG_POS (0x1 << 10 ) /* DIAG_POS */
207#define ADCCON_ADCDIAG_DIAG_NEG (0x2 << 10 ) /* DIAG_NEG */
208#define ADCCON_ADCDIAG_DIAG_ALL (0x3 << 10 ) /* DIAG_ALL */
209
210/* ADCCON[ADCCP] - AIN+ bits */
211#define ADCCON_ADCCP_MSK (0x1F << 5 )
212#define ADCCON_ADCCP_AIN0 (0x0 << 5 ) /* AIN0 */
213#define ADCCON_ADCCP_AIN1 (0x1 << 5 ) /* AIN1 */
214#define ADCCON_ADCCP_AIN2 (0x2 << 5 ) /* AIN2 */
215#define ADCCON_ADCCP_AIN3 (0x3 << 5 ) /* AIN3 */
216#define ADCCON_ADCCP_AIN4 (0x4 << 5 ) /* AIN4 */
217#define ADCCON_ADCCP_AIN5 (0x5 << 5 ) /* AIN5 */
218#define ADCCON_ADCCP_AIN6 (0x6 << 5 ) /* AIN6 */
219#define ADCCON_ADCCP_AIN7 (0x7 << 5 ) /* AIN7 */
220#define ADCCON_ADCCP_AIN8 (0x8 << 5 ) /* AIN8 */
221#define ADCCON_ADCCP_AIN9 (0x9 << 5 ) /* AIN9 */
222#define ADCCON_ADCCP_AIN10 (0xA << 5 ) /* AIN10 */
223#define ADCCON_ADCCP_AIN11 (0xB << 5 ) /* AIN11 */
224#define ADCCON_ADCCP_DAC (0xC << 5 ) /* DAC */
225#define ADCCON_ADCCP_AVDD4 (0xD << 5 ) /* AVDD4 */
226#define ADCCON_ADCCP_IOVDD4 (0xE << 5 ) /* IOVDD4 */
227#define ADCCON_ADCCP_AGND (0xF << 5 ) /* AGND */
228#define ADCCON_ADCCP_TEMP (0x10 << 5 ) /* TEMP */
229
230/* ADCCON[ADCCN] - AIN- bits */
231#define ADCCON_ADCCN_MSK (0x1F << 0 )
232#define ADCCON_ADCCN_AIN0 (0x0 << 0 ) /* AIN0 */
233#define ADCCON_ADCCN_AIN1 (0x1 << 0 ) /* AIN1 */
234#define ADCCON_ADCCN_AIN2 (0x2 << 0 ) /* AIN2 */
235#define ADCCON_ADCCN_AIN3 (0x3 << 0 ) /* AIN3 */
236#define ADCCON_ADCCN_AIN4 (0x4 << 0 ) /* AIN4 */
237#define ADCCON_ADCCN_AIN5 (0x5 << 0 ) /* AIN5 */
238#define ADCCON_ADCCN_AIN6 (0x6 << 0 ) /* AIN6 */
239#define ADCCON_ADCCN_AIN7 (0x7 << 0 ) /* AIN7 */
240#define ADCCON_ADCCN_AIN8 (0x8 << 0 ) /* AIN8 */
241#define ADCCON_ADCCN_AIN9 (0x9 << 0 ) /* AIN9 */
242#define ADCCON_ADCCN_AIN10 (0xA << 0 ) /* AIN10 */
243#define ADCCON_ADCCN_AIN11 (0xB << 0 ) /* AIN11 */
244#define ADCCON_ADCCN_DAC (0xC << 0 ) /* DAC */
245#define ADCCON_ADCCN_AGND (0xF << 0 ) /* AGND */
246#define ADCCON_ADCCN_TEMP (0x11 << 0 ) /* TEMP */
247
248/* ADCMDE[PGA] - PGA Gain Select bit */
249#define ADCMDE_PGA_MSK (0xF << 4 )
250#define ADCMDE_PGA_G1 (0x0 << 4 ) /* G1 */
251#define ADCMDE_PGA_G2 (0x1 << 4 ) /* G2 */
252#define ADCMDE_PGA_G4 (0x2 << 4 ) /* G4 */
253#define ADCMDE_PGA_G8 (0x3 << 4 ) /* G8 */
254#define ADCMDE_PGA_G16 (0x4 << 4 ) /* G16 */
255#define ADCMDE_PGA_G32 (0x5 << 4 ) /* G32 */
256#define ADCMDE_PGA_G64 (0x6 << 4 ) /* G64 */
257#define ADCMDE_PGA_G128 (0x7 << 4 ) /* G128 */
258
259/* ADCMDE[ADCMOD2] - ADC modulator gain of 2 control bits */
260#define ADCMDE_ADCMOD2_MSK (0x1 << 3 )
261#define ADCMDE_ADCMOD2 (0x1 << 3 )
262#define ADCMDE_ADCMOD2_MOD2OFF (0x0 << 3 ) /* MOD2OFF */
263#define ADCMDE_ADCMOD2_MOD2ON (0x1 << 3 ) /* MOD2ON */
264
265/* ADCMDE[ADCMD] - ADC Mode bits */
266#define ADCMDE_ADCMD_MSK (0x7 << 0 )
267#define ADCMDE_ADCMD_OFF (0x0 << 0 ) /* OFF */
268#define ADCMDE_ADCMD_CONT (0x1 << 0 ) /* CONT */
269#define ADCMDE_ADCMD_SINGLE (0x2 << 0 ) /* SINGLE */
270#define ADCMDE_ADCMD_IDLE (0x3 << 0 ) /* IDLE */
271#define ADCMDE_ADCMD_INTOCAL (0x4 << 0 ) /* INTOCAL */
272#define ADCMDE_ADCMD_INTGCAL (0x5 << 0 ) /* INTGCAL */
273#define ADCMDE_ADCMD_SYSOCAL (0x6 << 0 ) /* SYSOCAL */
274#define ADCMDE_ADCMD_SYSGCAL (0x7 << 0 ) /* SYSGCAL */
275
276/* ADCMSKI[ATHEX] - ADC Accumulator Comparator Threshold status bit mask */
277#define ADCMSKI_ATHEX_MSK (0x1 << 3 )
278#define ADCMSKI_ATHEX (0x1 << 3 )
279#define ADCMSKI_ATHEX_DIS (0x0 << 3 ) /* DIS */
280#define ADCMSKI_ATHEX_EN (0x1 << 3 ) /* EN */
281
282/* ADCMSKI[THEX] - ADC comparator threshold mask */
283#define ADCMSKI_THEX_MSK (0x1 << 2 )
284#define ADCMSKI_THEX (0x1 << 2 )
285#define ADCMSKI_THEX_DIS (0x0 << 2 ) /* DIS */
286#define ADCMSKI_THEX_EN (0x1 << 2 ) /* EN */
287
288/* ADCMSKI[OVR] - ADC overrange bit mask. */
289#define ADCMSKI_OVR_MSK (0x1 << 1 )
290#define ADCMSKI_OVR (0x1 << 1 )
291#define ADCMSKI_OVR_DIS (0x0 << 1 ) /* DIS */
292#define ADCMSKI_OVR_EN (0x1 << 1 ) /* EN */
293
294/* ADCMSKI[RDY] - valid conversion result mask */
295#define ADCMSKI_RDY_MSK (0x1 << 0 )
296#define ADCMSKI_RDY (0x1 << 0 )
297#define ADCMSKI_RDY_DIS (0x0 << 0 ) /* DIS */
298#define ADCMSKI_RDY_EN (0x1 << 0 ) /* EN */
299
300/* ADCFLT[CHOP] - Enables System-Chopping bits */
301#define ADCFLT_CHOP_MSK (0x1 << 15 )
302#define ADCFLT_CHOP (0x1 << 15 )
303#define ADCFLT_CHOP_OFF (0x0 << 15 ) /* OFF */
304#define ADCFLT_CHOP_ON (0x1 << 15 ) /* ON */
305
306/* ADCFLT[RAVG2] - Enables a running Average-By-2 bits */
307#define ADCFLT_RAVG2_MSK (0x1 << 14 )
308#define ADCFLT_RAVG2 (0x1 << 14 )
309#define ADCFLT_RAVG2_OFF (0x0 << 14 ) /* OFF */
310#define ADCFLT_RAVG2_ON (0x1 << 14 ) /* ON */
311
312/* ADCFLT[SINC4EN] - Enable the Sinc4 filter instead of Sinc3 filter. */
313#define ADCFLT_SINC4EN_MSK (0x1 << 12 )
314#define ADCFLT_SINC4EN (0x1 << 12 )
315#define ADCFLT_SINC4EN_DIS (0x0 << 12 ) /* DIS */
316#define ADCFLT_SINC4EN_EN (0x1 << 12 ) /* EN */
317
318/* ADCFLT[AF] - Averaging filter */
319#define ADCFLT_AF_MSK (0xF << 8 )
320
321/* ADCFLT[NOTCH2] - Inserts a notch at FNOTCH2 */
322#define ADCFLT_NOTCH2_MSK (0x1 << 7 )
323#define ADCFLT_NOTCH2 (0x1 << 7 )
324#define ADCFLT_NOTCH2_DIS (0x0 << 7 ) /* DIS */
325#define ADCFLT_NOTCH2_EN (0x1 << 7 ) /* EN */
326
327/* ADCFLT[SF] - SINC Filter value */
328#define ADCFLT_SF_MSK (0x7F << 0 )
329
330/* TCON[EVENTEN] - Enable time capture of an event */
331#define TCON_EVENTEN_MSK (0x1 << 12 )
332#define TCON_EVENTEN (0x1 << 12 )
333#define TCON_EVENTEN_DIS (0x0 << 12 ) /* DIS */
334#define TCON_EVENTEN_EN (0x1 << 12 ) /* EN */
335
336/* TCON[EVENT] - Event Select, selects 1 of the available events. */
337#define TCON_EVENT_MSK (0xF << 8 )
338
339/* TCON[RLD] - Timer reload on write to clear register */
340#define TCON_RLD_MSK (0x1 << 7 )
341#define TCON_RLD (0x1 << 7 )
342#define TCON_RLD_DIS (0x0 << 7 ) /* DIS */
343#define TCON_RLD_EN (0x1 << 7 ) /* EN */
344
345/* TCON[CLK] - Clock Select */
346#define TCON_CLK_MSK (0x3 << 5 )
347#define TCON_CLK_UCLK (0x0 << 5 ) /* UCLK - System Clock */
348#define TCON_CLK_PCLK (0x1 << 5 ) /* PCLK - Peripheral clock */
349#define TCON_CLK_LFOSC (0x2 << 5 ) /* LFOSC - Internal 32 kHz Oscillator */
350#define TCON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL - External 32 kHz crystal */
351
352/* TCON[ENABLE] - Enable */
353#define TCON_ENABLE_MSK (0x1 << 4 )
354#define TCON_ENABLE (0x1 << 4 )
355#define TCON_ENABLE_DIS (0x0 << 4 ) /* DIS */
356#define TCON_ENABLE_EN (0x1 << 4 ) /* EN */
357
358/* TCON[MOD] - Mode */
359#define TCON_MOD_MSK (0x1 << 3 )
360#define TCON_MOD (0x1 << 3 )
361#define TCON_MOD_FREERUN (0x0 << 3 ) /* FREERUN */
362#define TCON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC */
363
364/* TCON[UP] - Count-up */
365#define TCON_UP_MSK (0x1 << 2 )
366#define TCON_UP (0x1 << 2 )
367#define TCON_UP_DIS (0x0 << 2 ) /* DIS */
368#define TCON_UP_EN (0x1 << 2 ) /* EN */
369
370/* TCON[PRE] - Prescaler */
371#define TCON_PRE_MSK (0x3 << 0 )
372#define TCON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
373#define TCON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
374#define TCON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
375#define TCON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 - If the selected clock source is UCLK then this setting results in a prescaler of 4. */
376
377/* TCLRI[CAP] - Clear captured event interrupt */
378#define TCLRI_CAP_MSK (0x1 << 1 )
379#define TCLRI_CAP (0x1 << 1 )
380#define TCLRI_CAP_CLR (0x1 << 1 ) /* CLR */
381
382/* TCLRI[TMOUT] - Clear timeout interrupt */
383#define TCLRI_TMOUT_MSK (0x1 << 0 )
384#define TCLRI_TMOUT (0x1 << 0 )
385#define TCLRI_TMOUT_CLR (0x1 << 0 ) /* CLR */
386
387/* TSTA[CLRI] - Value updated in the timer clock domain */
388#define TSTA_CLRI_MSK (0x1 << 7 )
389#define TSTA_CLRI (0x1 << 7 )
390#define TSTA_CLRI_CLR (0x0 << 7 ) /* CLR */
391#define TSTA_CLRI_SET (0x1 << 7 ) /* SET */
392
393/* TSTA[CON] - Ready to receive commands */
394#define TSTA_CON_MSK (0x1 << 6 )
395#define TSTA_CON (0x1 << 6 )
396#define TSTA_CON_CLR (0x0 << 6 ) /* CLR */
397#define TSTA_CON_SET (0x1 << 6 ) /* SET */
398
399/* TSTA[CAP] - Capture event pending */
400#define TSTA_CAP_MSK (0x1 << 1 )
401#define TSTA_CAP (0x1 << 1 )
402#define TSTA_CAP_CLR (0x0 << 1 ) /* CLR */
403#define TSTA_CAP_SET (0x1 << 1 ) /* SET */
404
405/* TSTA[TMOUT] - Time out event occurred */
406#define TSTA_TMOUT_MSK (0x1 << 0 )
407#define TSTA_TMOUT (0x1 << 0 )
408#define TSTA_TMOUT_CLR (0x0 << 0 ) /* CLR */
409#define TSTA_TMOUT_SET (0x1 << 0 ) /* SET */
410
411/* GPCON[CON7] - Configuration bits for P0.7 */
412#define GPCON_CON7_MSK (0x3 << 14 )
413
414/* GPCON[CON6] - Configuration bits for P0.6 */
415#define GPCON_CON6_MSK (0x3 << 12 )
416
417/* GPCON[CON5] - Configuration bits for P0.5 */
418#define GPCON_CON5_MSK (0x3 << 10 )
419
420/* GPCON[CON4] - Configuration bits for P0.4 */
421#define GPCON_CON4_MSK (0x3 << 8 )
422
423/* GPCON[CON3] - Configuration bits for P0.3 */
424#define GPCON_CON3_MSK (0x3 << 6 )
425
426/* GPCON[CON2] - Configuration bits for P0.2 */
427#define GPCON_CON2_MSK (0x3 << 4 )
428
429/* GPCON[CON1] - Configuration bits for P0.1 */
430#define GPCON_CON1_MSK (0x3 << 2 )
431
432/* GPCON[CON0] - Configuration bits for P0.0 */
433#define GPCON_CON0_MSK (0x3 << 0 )
434
435/* GPOEN[OEN7] - Direction for port pin */
436#define GPOEN_OEN7_MSK (0x1 << 7 )
437#define GPOEN_OEN7 (0x1 << 7 )
438#define GPOEN_OEN7_IN (0x0 << 7 ) /* IN */
439#define GPOEN_OEN7_OUT (0x1 << 7 ) /* OUT */
440
441/* GPOEN[OEN6] - Direction for port pin */
442#define GPOEN_OEN6_MSK (0x1 << 6 )
443#define GPOEN_OEN6 (0x1 << 6 )
444#define GPOEN_OEN6_IN (0x0 << 6 ) /* IN */
445#define GPOEN_OEN6_OUT (0x1 << 6 ) /* OUT */
446
447/* GPOEN[OEN5] - Direction for port pin */
448#define GPOEN_OEN5_MSK (0x1 << 5 )
449#define GPOEN_OEN5 (0x1 << 5 )
450#define GPOEN_OEN5_IN (0x0 << 5 ) /* IN */
451#define GPOEN_OEN5_OUT (0x1 << 5 ) /* OUT */
452
453/* GPOEN[OEN4] - Direction for port pin */
454#define GPOEN_OEN4_MSK (0x1 << 4 )
455#define GPOEN_OEN4 (0x1 << 4 )
456#define GPOEN_OEN4_IN (0x0 << 4 ) /* IN */
457#define GPOEN_OEN4_OUT (0x1 << 4 ) /* OUT */
458
459/* GPOEN[OEN3] - Direction for port pin */
460#define GPOEN_OEN3_MSK (0x1 << 3 )
461#define GPOEN_OEN3 (0x1 << 3 )
462#define GPOEN_OEN3_IN (0x0 << 3 ) /* IN */
463#define GPOEN_OEN3_OUT (0x1 << 3 ) /* OUT */
464
465/* GPOEN[OEN2] - Direction for port pin */
466#define GPOEN_OEN2_MSK (0x1 << 2 )
467#define GPOEN_OEN2 (0x1 << 2 )
468#define GPOEN_OEN2_IN (0x0 << 2 ) /* IN */
469#define GPOEN_OEN2_OUT (0x1 << 2 ) /* OUT */
470
471/* GPOEN[OEN1] - Direction for port pin */
472#define GPOEN_OEN1_MSK (0x1 << 1 )
473#define GPOEN_OEN1 (0x1 << 1 )
474#define GPOEN_OEN1_IN (0x0 << 1 ) /* IN */
475#define GPOEN_OEN1_OUT (0x1 << 1 ) /* OUT */
476
477/* GPOEN[OEN0] - Direction for port pin */
478#define GPOEN_OEN0_MSK (0x1 << 0 )
479#define GPOEN_OEN0 (0x1 << 0 )
480#define GPOEN_OEN0_IN (0x0 << 0 ) /* IN */
481#define GPOEN_OEN0_OUT (0x1 << 0 ) /* OUT */
482
483/* GPIN[IN7] - Input for port pin */
484#define GPIN_IN7_MSK (0x1 << 7 )
485#define GPIN_IN7 (0x1 << 7 )
486#define GPIN_IN7_LOW (0x0 << 7 ) /* LOW */
487#define GPIN_IN7_HIGH (0x1 << 7 ) /* HIGH */
488
489/* GPIN[IN6] - Input for port pin */
490#define GPIN_IN6_MSK (0x1 << 6 )
491#define GPIN_IN6 (0x1 << 6 )
492#define GPIN_IN6_LOW (0x0 << 6 ) /* LOW */
493#define GPIN_IN6_HIGH (0x1 << 6 ) /* HIGH */
494
495/* GPIN[IN5] - Input for port pin */
496#define GPIN_IN5_MSK (0x1 << 5 )
497#define GPIN_IN5 (0x1 << 5 )
498#define GPIN_IN5_LOW (0x0 << 5 ) /* LOW */
499#define GPIN_IN5_HIGH (0x1 << 5 ) /* HIGH */
500
501/* GPIN[IN4] - Input for port pin */
502#define GPIN_IN4_MSK (0x1 << 4 )
503#define GPIN_IN4 (0x1 << 4 )
504#define GPIN_IN4_LOW (0x0 << 4 ) /* LOW */
505#define GPIN_IN4_HIGH (0x1 << 4 ) /* HIGH */
506
507/* GPIN[IN3] - Input for port pin */
508#define GPIN_IN3_MSK (0x1 << 3 )
509#define GPIN_IN3 (0x1 << 3 )
510#define GPIN_IN3_LOW (0x0 << 3 ) /* LOW */
511#define GPIN_IN3_HIGH (0x1 << 3 ) /* HIGH */
512
513/* GPIN[IN2] - Input for port pin */
514#define GPIN_IN2_MSK (0x1 << 2 )
515#define GPIN_IN2 (0x1 << 2 )
516#define GPIN_IN2_LOW (0x0 << 2 ) /* LOW */
517#define GPIN_IN2_HIGH (0x1 << 2 ) /* HIGH */
518
519/* GPIN[IN1] - Input for port pin */
520#define GPIN_IN1_MSK (0x1 << 1 )
521#define GPIN_IN1 (0x1 << 1 )
522#define GPIN_IN1_LOW (0x0 << 1 ) /* LOW */
523#define GPIN_IN1_HIGH (0x1 << 1 ) /* HIGH */
524
525/* GPIN[IN0] - Input for port pin */
526#define GPIN_IN0_MSK (0x1 << 0 )
527#define GPIN_IN0 (0x1 << 0 )
528#define GPIN_IN0_LOW (0x0 << 0 ) /* LOW */
529#define GPIN_IN0_HIGH (0x1 << 0 ) /* HIGH */
530
531/* GPOUT[OUT7] - Output for port pin */
532#define GPOUT_OUT7_MSK (0x1 << 7 )
533#define GPOUT_OUT7 (0x1 << 7 )
534#define GPOUT_OUT7_LOW (0x0 << 7 ) /* LOW */
535#define GPOUT_OUT7_HIGH (0x1 << 7 ) /* HIGH */
536
537/* GPOUT[OUT6] - Output for port pin */
538#define GPOUT_OUT6_MSK (0x1 << 6 )
539#define GPOUT_OUT6 (0x1 << 6 )
540#define GPOUT_OUT6_LOW (0x0 << 6 ) /* LOW */
541#define GPOUT_OUT6_HIGH (0x1 << 6 ) /* HIGH */
542
543/* GPOUT[OUT5] - Output for port pin */
544#define GPOUT_OUT5_MSK (0x1 << 5 )
545#define GPOUT_OUT5 (0x1 << 5 )
546#define GPOUT_OUT5_LOW (0x0 << 5 ) /* LOW */
547#define GPOUT_OUT5_HIGH (0x1 << 5 ) /* HIGH */
548
549/* GPOUT[OUT4] - Output for port pin */
550#define GPOUT_OUT4_MSK (0x1 << 4 )
551#define GPOUT_OUT4 (0x1 << 4 )
552#define GPOUT_OUT4_LOW (0x0 << 4 ) /* LOW */
553#define GPOUT_OUT4_HIGH (0x1 << 4 ) /* HIGH */
554
555/* GPOUT[OUT3] - Output for port pin */
556#define GPOUT_OUT3_MSK (0x1 << 3 )
557#define GPOUT_OUT3 (0x1 << 3 )
558#define GPOUT_OUT3_LOW (0x0 << 3 ) /* LOW */
559#define GPOUT_OUT3_HIGH (0x1 << 3 ) /* HIGH */
560
561/* GPOUT[OUT2] - Output for port pin */
562#define GPOUT_OUT2_MSK (0x1 << 2 )
563#define GPOUT_OUT2 (0x1 << 2 )
564#define GPOUT_OUT2_LOW (0x0 << 2 ) /* LOW */
565#define GPOUT_OUT2_HIGH (0x1 << 2 ) /* HIGH */
566
567/* GPOUT[OUT1] - Output for port pin */
568#define GPOUT_OUT1_MSK (0x1 << 1 )
569#define GPOUT_OUT1 (0x1 << 1 )
570#define GPOUT_OUT1_LOW (0x0 << 1 ) /* LOW */
571#define GPOUT_OUT1_HIGH (0x1 << 1 ) /* HIGH */
572
573/* GPOUT[OUT0] - Output for port pin */
574#define GPOUT_OUT0_MSK (0x1 << 0 )
575#define GPOUT_OUT0 (0x1 << 0 )
576#define GPOUT_OUT0_LOW (0x0 << 0 ) /* LOW */
577#define GPOUT_OUT0_HIGH (0x1 << 0 ) /* HIGH */
578
579/* GPSET[SET7] - Set Output High for port pin */
580#define GPSET_SET7_MSK (0x1 << 7 )
581#define GPSET_SET7 (0x1 << 7 )
582#define GPSET_SET7_SET (0x1 << 7 ) /* SET */
583
584/* GPSET[SET6] - Set Output High for port pin */
585#define GPSET_SET6_MSK (0x1 << 6 )
586#define GPSET_SET6 (0x1 << 6 )
587#define GPSET_SET6_SET (0x1 << 6 ) /* SET */
588
589/* GPSET[SET5] - Set Output High for port pin */
590#define GPSET_SET5_MSK (0x1 << 5 )
591#define GPSET_SET5 (0x1 << 5 )
592#define GPSET_SET5_SET (0x1 << 5 ) /* SET */
593
594/* GPSET[SET4] - Set Output High for port pin */
595#define GPSET_SET4_MSK (0x1 << 4 )
596#define GPSET_SET4 (0x1 << 4 )
597#define GPSET_SET4_SET (0x1 << 4 ) /* SET */
598
599/* GPSET[SET3] - Set Output High for port pin */
600#define GPSET_SET3_MSK (0x1 << 3 )
601#define GPSET_SET3 (0x1 << 3 )
602#define GPSET_SET3_SET (0x1 << 3 ) /* SET */
603
604/* GPSET[SET2] - Set Output High for port pin */
605#define GPSET_SET2_MSK (0x1 << 2 )
606#define GPSET_SET2 (0x1 << 2 )
607#define GPSET_SET2_SET (0x1 << 2 ) /* SET */
608
609/* GPSET[SET1] - Set Output High for port pin */
610#define GPSET_SET1_MSK (0x1 << 1 )
611#define GPSET_SET1 (0x1 << 1 )
612#define GPSET_SET1_SET (0x1 << 1 ) /* SET */
613
614/* GPSET[SET0] - Set Output High for port pin */
615#define GPSET_SET0_MSK (0x1 << 0 )
616#define GPSET_SET0 (0x1 << 0 )
617#define GPSET_SET0_SET (0x1 << 0 ) /* SET */
618
619/* GPCLR[CLR7] - Set Output Low for port pin */
620#define GPCLR_CLR7_MSK (0x1 << 7 )
621#define GPCLR_CLR7 (0x1 << 7 )
622#define GPCLR_CLR7_CLR (0x1 << 7 ) /* CLR */
623
624/* GPCLR[CLR6] - Set Output Low for port pin */
625#define GPCLR_CLR6_MSK (0x1 << 6 )
626#define GPCLR_CLR6 (0x1 << 6 )
627#define GPCLR_CLR6_CLR (0x1 << 6 ) /* CLR */
628
629/* GPCLR[CLR5] - Set Output Low for port pin */
630#define GPCLR_CLR5_MSK (0x1 << 5 )
631#define GPCLR_CLR5 (0x1 << 5 )
632#define GPCLR_CLR5_CLR (0x1 << 5 ) /* CLR */
633
634/* GPCLR[CLR4] - Set Output Low for port pin */
635#define GPCLR_CLR4_MSK (0x1 << 4 )
636#define GPCLR_CLR4 (0x1 << 4 )
637#define GPCLR_CLR4_CLR (0x1 << 4 ) /* CLR */
638
639/* GPCLR[CLR3] - Set Output Low for port pin */
640#define GPCLR_CLR3_MSK (0x1 << 3 )
641#define GPCLR_CLR3 (0x1 << 3 )
642#define GPCLR_CLR3_CLR (0x1 << 3 ) /* CLR */
643
644/* GPCLR[CLR2] - Set Output Low for port pin */
645#define GPCLR_CLR2_MSK (0x1 << 2 )
646#define GPCLR_CLR2 (0x1 << 2 )
647#define GPCLR_CLR2_CLR (0x1 << 2 ) /* CLR */
648
649/* GPCLR[CLR1] - Set Output Low for port pin */
650#define GPCLR_CLR1_MSK (0x1 << 1 )
651#define GPCLR_CLR1 (0x1 << 1 )
652#define GPCLR_CLR1_CLR (0x1 << 1 ) /* CLR */
653
654/* GPCLR[CLR0] - Set Output Low for port pin */
655#define GPCLR_CLR0_MSK (0x1 << 0 )
656#define GPCLR_CLR0 (0x1 << 0 )
657#define GPCLR_CLR0_CLR (0x1 << 0 ) /* CLR */
658
659/* GPTGL[TGL7] - Toggle Output for port pin */
660#define GPTGL_TGL7_MSK (0x1 << 7 )
661#define GPTGL_TGL7 (0x1 << 7 )
662#define GPTGL_TGL7_TGL (0x1 << 7 ) /* TGL */
663
664/* GPTGL[TGL6] - Toggle Output for port pin */
665#define GPTGL_TGL6_MSK (0x1 << 6 )
666#define GPTGL_TGL6 (0x1 << 6 )
667#define GPTGL_TGL6_TGL (0x1 << 6 ) /* TGL */
668
669/* GPTGL[TGL5] - Toggle Output for port pin */
670#define GPTGL_TGL5_MSK (0x1 << 5 )
671#define GPTGL_TGL5 (0x1 << 5 )
672#define GPTGL_TGL5_TGL (0x1 << 5 ) /* TGL */
673
674/* GPTGL[TGL4] - Toggle Output for port pin */
675#define GPTGL_TGL4_MSK (0x1 << 4 )
676#define GPTGL_TGL4 (0x1 << 4 )
677#define GPTGL_TGL4_TGL (0x1 << 4 ) /* TGL */
678
679/* GPTGL[TGL3] - Toggle Output for port pin */
680#define GPTGL_TGL3_MSK (0x1 << 3 )
681#define GPTGL_TGL3 (0x1 << 3 )
682#define GPTGL_TGL3_TGL (0x1 << 3 ) /* TGL */
683
684/* GPTGL[TGL2] - Toggle Output for port pin */
685#define GPTGL_TGL2_MSK (0x1 << 2 )
686#define GPTGL_TGL2 (0x1 << 2 )
687#define GPTGL_TGL2_TGL (0x1 << 2 ) /* TGL */
688
689/* GPTGL[TGL1] - Toggle Output for port pin */
690#define GPTGL_TGL1_MSK (0x1 << 1 )
691#define GPTGL_TGL1 (0x1 << 1 )
692#define GPTGL_TGL1_TGL (0x1 << 1 ) /* TGL */
693
694/* GPTGL[TGL0] - Toggle Output for port pin */
695#define GPTGL_TGL0_MSK (0x1 << 0 )
696#define GPTGL_TGL0 (0x1 << 0 )
697#define GPTGL_TGL0_TGL (0x1 << 0 ) /* TGL */
698
699/* SPIDIV[BCRST] - Bit counter reset */
700#define SPIDIV_BCRST_MSK (0x1 << 7 )
701#define SPIDIV_BCRST (0x1 << 7 )
702#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS */
703#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN */
704
705/* SPIDIV[DIV] - Factor used to divide UCLK to generate the serial clock */
706#define SPIDIV_DIV_MSK (0x3F << 0 )
707
708/* SPICON[MOD] - SPI IRQ Mode bits */
709#define SPICON_MOD_MSK (0x3 << 14 )
710#define SPICON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1 */
711#define SPICON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2 */
712#define SPICON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3 */
713#define SPICON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4 */
714
715/* SPICON[TFLUSH] - TX FIFO Flush Enable bit */
716#define SPICON_TFLUSH_MSK (0x1 << 13 )
717#define SPICON_TFLUSH (0x1 << 13 )
718#define SPICON_TFLUSH_DIS (0x0 << 13 ) /* DIS */
719#define SPICON_TFLUSH_EN (0x1 << 13 ) /* EN */
720
721/* SPICON[RFLUSH] - RX FIFO Flush Enable bit */
722#define SPICON_RFLUSH_MSK (0x1 << 12 )
723#define SPICON_RFLUSH (0x1 << 12 )
724#define SPICON_RFLUSH_DIS (0x0 << 12 ) /* DIS */
725#define SPICON_RFLUSH_EN (0x1 << 12 ) /* EN */
726
727/* SPICON[CON] - Continuous transfer enable */
728#define SPICON_CON_MSK (0x1 << 11 )
729#define SPICON_CON (0x1 << 11 )
730#define SPICON_CON_DIS (0x0 << 11 ) /* DIS */
731#define SPICON_CON_EN (0x1 << 11 ) /* EN */
732
733/* SPICON[LOOPBACK] - Loopback enable bit */
734#define SPICON_LOOPBACK_MSK (0x1 << 10 )
735#define SPICON_LOOPBACK (0x1 << 10 )
736#define SPICON_LOOPBACK_DIS (0x0 << 10 ) /* DIS */
737#define SPICON_LOOPBACK_EN (0x1 << 10 ) /* EN */
738
739/* SPICON[SOEN] - Slave MISO output enable bit */
740#define SPICON_SOEN_MSK (0x1 << 9 )
741#define SPICON_SOEN (0x1 << 9 )
742#define SPICON_SOEN_DIS (0x0 << 9 ) /* DIS */
743#define SPICON_SOEN_EN (0x1 << 9 ) /* EN */
744
745/* SPICON[RXOF] - RX Oveflow Overwrite enable */
746#define SPICON_RXOF_MSK (0x1 << 8 )
747#define SPICON_RXOF (0x1 << 8 )
748#define SPICON_RXOF_DIS (0x0 << 8 ) /* DIS */
749#define SPICON_RXOF_EN (0x1 << 8 ) /* EN */
750
751/* SPICON[ZEN] - Transmit zeros when empty */
752#define SPICON_ZEN_MSK (0x1 << 7 )
753#define SPICON_ZEN (0x1 << 7 )
754#define SPICON_ZEN_DIS (0x0 << 7 ) /* DIS */
755#define SPICON_ZEN_EN (0x1 << 7 ) /* EN */
756
757/* SPICON[TIM] - Transfer and interrupt mode */
758#define SPICON_TIM_MSK (0x1 << 6 )
759#define SPICON_TIM (0x1 << 6 )
760#define SPICON_TIM_RXRD (0x0 << 6 ) /* RXRD - Cleared by user to initiate transfer with a read of the SPIRX register */
761#define SPICON_TIM_TXWR (0x1 << 6 ) /* TXWR - Set by user to initiate transfer with a write to the SPITX register. */
762
763/* SPICON[LSB] - LSB First Transfer enable */
764#define SPICON_LSB_MSK (0x1 << 5 )
765#define SPICON_LSB (0x1 << 5 )
766#define SPICON_LSB_DIS (0x0 << 5 ) /* DIS */
767#define SPICON_LSB_EN (0x1 << 5 ) /* EN */
768
769/* SPICON[WOM] - Wired OR enable */
770#define SPICON_WOM_MSK (0x1 << 4 )
771#define SPICON_WOM (0x1 << 4 )
772#define SPICON_WOM_DIS (0x0 << 4 ) /* DIS */
773#define SPICON_WOM_EN (0x1 << 4 ) /* EN */
774
775/* SPICON[CPOL] - Clock polarity mode */
776#define SPICON_CPOL_MSK (0x1 << 3 )
777#define SPICON_CPOL (0x1 << 3 )
778#define SPICON_CPOL_LOW (0x0 << 3 ) /* LOW */
779#define SPICON_CPOL_HIGH (0x1 << 3 ) /* HIGH */
780
781/* SPICON[CPHA] - Clock phase mode */
782#define SPICON_CPHA_MSK (0x1 << 2 )
783#define SPICON_CPHA (0x1 << 2 )
784#define SPICON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING */
785#define SPICON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING */
786
787/* SPICON[MASEN] - Master enable */
788#define SPICON_MASEN_MSK (0x1 << 1 )
789#define SPICON_MASEN (0x1 << 1 )
790#define SPICON_MASEN_DIS (0x0 << 1 ) /* DIS */
791#define SPICON_MASEN_EN (0x1 << 1 ) /* EN */
792
793/* SPICON[ENABLE] - SPI Enable bit */
794#define SPICON_ENABLE_MSK (0x1 << 0 )
795#define SPICON_ENABLE (0x1 << 0 )
796#define SPICON_ENABLE_DIS (0x0 << 0 ) /* DIS */
797#define SPICON_ENABLE_EN (0x1 << 0 ) /* EN */
798
799/* SPIDMA[IENRXDMA] - Enable receive DMA request */
800#define SPIDMA_IENRXDMA_MSK (0x1 << 2 )
801#define SPIDMA_IENRXDMA (0x1 << 2 )
802#define SPIDMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS */
803#define SPIDMA_IENRXDMA_EN (0x1 << 2 ) /* EN */
804
805/* SPIDMA[IENTXDMA] - Enable transmit DMA request */
806#define SPIDMA_IENTXDMA_MSK (0x1 << 1 )
807#define SPIDMA_IENTXDMA (0x1 << 1 )
808#define SPIDMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS */
809#define SPIDMA_IENTXDMA_EN (0x1 << 1 ) /* EN */
810
811/* SPIDMA[ENABLE] - Enable DMA for data transfer */
812#define SPIDMA_ENABLE_MSK (0x1 << 0 )
813#define SPIDMA_ENABLE (0x1 << 0 )
814#define SPIDMA_ENABLE_DIS (0x0 << 0 ) /* DIS */
815#define SPIDMA_ENABLE_EN (0x1 << 0 ) /* EN */
816
817/* SPISTA[CSERR] - Detected an abrupt CS deassertion */
818#define SPISTA_CSERR_MSK (0x1 << 12 )
819#define SPISTA_CSERR (0x1 << 12 )
820#define SPISTA_CSERR_CLR (0x0 << 12 ) /* CLR */
821#define SPISTA_CSERR_SET (0x1 << 12 ) /* SET */
822
823/* SPISTA[RXS] - Set when there are more bytes in the RX FIFO than the TIM bit says */
824#define SPISTA_RXS_MSK (0x1 << 11 )
825#define SPISTA_RXS (0x1 << 11 )
826#define SPISTA_RXS_CLR (0x0 << 11 ) /* CLR */
827#define SPISTA_RXS_SET (0x1 << 11 ) /* SET */
828
829/* SPISTA[RXFSTA] - Receive FIFO Status */
830#define SPISTA_RXFSTA_MSK (0x7 << 8 )
831#define SPISTA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY */
832#define SPISTA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE */
833#define SPISTA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES */
834#define SPISTA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES */
835#define SPISTA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES */
836
837/* SPISTA[RXOF] - Receive FIFO overflow */
838#define SPISTA_RXOF_MSK (0x1 << 7 )
839#define SPISTA_RXOF (0x1 << 7 )
840#define SPISTA_RXOF_CLR (0x0 << 7 ) /* CLR */
841#define SPISTA_RXOF_SET (0x1 << 7 ) /* SET */
842
843/* SPISTA[RX] - Set when a receive interrupt occurs */
844#define SPISTA_RX_MSK (0x1 << 6 )
845#define SPISTA_RX (0x1 << 6 )
846#define SPISTA_RX_CLR (0x0 << 6 ) /* CLR */
847#define SPISTA_RX_SET (0x1 << 6 ) /* SET */
848
849/* SPISTA[TX] - Set when a transmit interrupt occurs */
850#define SPISTA_TX_MSK (0x1 << 5 )
851#define SPISTA_TX (0x1 << 5 )
852#define SPISTA_TX_CLR (0x0 << 5 ) /* CLR */
853#define SPISTA_TX_SET (0x1 << 5 ) /* SET */
854
855/* SPISTA[TXUR] - Transmit FIFO underflow */
856#define SPISTA_TXUR_MSK (0x1 << 4 )
857#define SPISTA_TXUR (0x1 << 4 )
858#define SPISTA_TXUR_CLR (0x0 << 4 ) /* CLR */
859#define SPISTA_TXUR_SET (0x1 << 4 ) /* SET */
860
861/* SPISTA[TXFSTA] - transmit FIFO Status */
862#define SPISTA_TXFSTA_MSK (0x7 << 1 )
863#define SPISTA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY */
864#define SPISTA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE */
865#define SPISTA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES */
866#define SPISTA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES */
867#define SPISTA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES */
868
869/* SPISTA[IRQ] - Interrupt status bit */
870#define SPISTA_IRQ_MSK (0x1 << 0 )
871#define SPISTA_IRQ (0x1 << 0 )
872#define SPISTA_IRQ_CLR (0x0 << 0 ) /* CLR */
873#define SPISTA_IRQ_SET (0x1 << 0 ) /* SET */
874
875/* SPIDIV[BCRST] - Bit counter reset */
876#define SPIDIV_BCRST_MSK (0x1 << 7 )
877#define SPIDIV_BCRST (0x1 << 7 )
878#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS */
879#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN */
880
881/* SPIDIV[DIV] - Factor used to divide UCLK to generate the serial clock */
882#define SPIDIV_DIV_MSK (0x3F << 0 )
883// ------------------------------------------------------------------------------------------------
884// ----- T0 -----
885// ------------------------------------------------------------------------------------------------
886
887
888/**
889 * @brief Timer 0 (pADI_TM0)
890 */
891
892#if (__NO_MMR_STRUCTS__==0)
893typedef struct { /*!< pADI_TM0 Structure */
894 __IO uint16_t LD; /*!< 16-bit load value */
895 __I uint16_t RESERVED0;
896 __IO uint16_t VAL; /*!< "16-bit timer value, read only." */
897 __I uint16_t RESERVED1;
898 __IO uint16_t CON; /*!< Control Register */
899 __I uint16_t RESERVED2;
900 __IO uint16_t CLRI; /*!< Clear interrupt register */
901 __I uint16_t RESERVED3;
902 __IO uint16_t CAP; /*!< Capture Register */
903 __I uint16_t RESERVED4[5];
904 __IO uint16_t STA; /*!< Status Register */
905} ADI_TIMER_TypeDef;
906#else // (__NO_MMR_STRUCTS__==0)
907#define T0LD (*(volatile unsigned short int *) 0x40000000)
908#define T0VAL (*(volatile unsigned short int *) 0x40000004)
909#define T0CON (*(volatile unsigned short int *) 0x40000008)
910#define T0CLRI (*(volatile unsigned short int *) 0x4000000C)
911#define T0CAP (*(volatile unsigned short int *) 0x40000010)
912#define T0STA (*(volatile unsigned short int *) 0x4000001C)
913#endif // (__NO_MMR_STRUCTS__==0)
914
915/* Reset Value for T0LD*/
916#define T0LD_RVAL 0x0
917
918/* T0LD[VALUE] - Load value */
919#define T0LD_VALUE_MSK (0xFFFF << 0 )
920
921/* Reset Value for T0VAL*/
922#define T0VAL_RVAL 0x0
923
924/* T0VAL[VALUE] - Current value */
925#define T0VAL_VALUE_MSK (0xFFFF << 0 )
926
927/* Reset Value for T0CON*/
928#define T0CON_RVAL 0xA
929
930/* T0CON[EVENTEN] - Enable time capture of an event */
931#define T0CON_EVENTEN_BBA (*(volatile unsigned long *) 0x42000130)
932#define T0CON_EVENTEN_MSK (0x1 << 12 )
933#define T0CON_EVENTEN (0x1 << 12 )
934#define T0CON_EVENTEN_DIS (0x0 << 12 ) /* DIS */
935#define T0CON_EVENTEN_EN (0x1 << 12 ) /* EN */
936
937/* T0CON[EVENT] - Event Select, selects 1 of the available events. */
938#define T0CON_EVENT_MSK (0xF << 8 )
939#define T0CON_EVENT_T2 (0x0 << 8 ) /* T2 - Wakeup Timer */
940#define T0CON_EVENT_EXT0 (0x1 << 8 ) /* EXT0 - External interrupt 0 */
941#define T0CON_EVENT_EXT1 (0x2 << 8 ) /* EXT1 - External interrupt 1 */
942#define T0CON_EVENT_EXT2 (0x3 << 8 ) /* EXT2 - External interrupt 2 */
943#define T0CON_EVENT_EXT3 (0x4 << 8 ) /* EXT3 - External interrupt 3 */
944#define T0CON_EVENT_EXT4 (0x5 << 8 ) /* EXT4 - External interrupt 4 */
945#define T0CON_EVENT_EXT5 (0x6 << 8 ) /* EXT5 - External interrupt 5 */
946#define T0CON_EVENT_EXT6 (0x7 << 8 ) /* EXT6 - External interrupt 6 */
947#define T0CON_EVENT_EXT7 (0x8 << 8 ) /* EXT7 - External interrupt 7 */
948#define T0CON_EVENT_T3 (0x9 << 8 ) /* T3 - Watchdog timer */
949#define T0CON_EVENT_T1 (0xA << 8 ) /* T1 - Timer1 */
950#define T0CON_EVENT_ADC0 (0xB << 8 ) /* ADC0 - ADC0 */
951#define T0CON_EVENT_ADC1 (0xC << 8 ) /* ADC1 - ADC1 */
952#define T0CON_EVENT_STEP (0xD << 8 ) /* STEP - STEP */
953#define T0CON_EVENT_DMADONE (0xE << 8 ) /* DMADONE */
954#define T0CON_EVENT_FEE (0xF << 8 ) /* FEE - Flash controller */
955
956/* T0CON[RLD] - Timer reload on write to clear register */
957#define T0CON_RLD_BBA (*(volatile unsigned long *) 0x4200011C)
958#define T0CON_RLD_MSK (0x1 << 7 )
959#define T0CON_RLD (0x1 << 7 )
960#define T0CON_RLD_DIS (0x0 << 7 ) /* DIS */
961#define T0CON_RLD_EN (0x1 << 7 ) /* EN */
962
963/* T0CON[CLK] - Clock Select */
964#define T0CON_CLK_MSK (0x3 << 5 )
965#define T0CON_CLK_UCLK (0x0 << 5 ) /* UCLK - System Clock */
966#define T0CON_CLK_PCLK (0x1 << 5 ) /* PCLK - Peripheral clock */
967#define T0CON_CLK_LFOSC (0x2 << 5 ) /* LFOSC - Internal 32 kHz Oscillator */
968#define T0CON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL - External 32 kHz crystal */
969
970/* T0CON[ENABLE] - Enable */
971#define T0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42000110)
972#define T0CON_ENABLE_MSK (0x1 << 4 )
973#define T0CON_ENABLE (0x1 << 4 )
974#define T0CON_ENABLE_DIS (0x0 << 4 ) /* DIS */
975#define T0CON_ENABLE_EN (0x1 << 4 ) /* EN */
976
977/* T0CON[MOD] - Mode */
978#define T0CON_MOD_BBA (*(volatile unsigned long *) 0x4200010C)
979#define T0CON_MOD_MSK (0x1 << 3 )
980#define T0CON_MOD (0x1 << 3 )
981#define T0CON_MOD_FREERUN (0x0 << 3 ) /* FREERUN */
982#define T0CON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC */
983
984/* T0CON[UP] - Count-up */
985#define T0CON_UP_BBA (*(volatile unsigned long *) 0x42000108)
986#define T0CON_UP_MSK (0x1 << 2 )
987#define T0CON_UP (0x1 << 2 )
988#define T0CON_UP_DIS (0x0 << 2 ) /* DIS */
989#define T0CON_UP_EN (0x1 << 2 ) /* EN */
990
991/* T0CON[PRE] - Prescaler */
992#define T0CON_PRE_MSK (0x3 << 0 )
993#define T0CON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
994#define T0CON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
995#define T0CON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
996#define T0CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 - If the selected clock source is UCLK then this setting results in a prescaler of 4. */
997
998/* Reset Value for T0CLRI*/
999#define T0CLRI_RVAL 0x0
1000
1001/* T0CLRI[CAP] - Clear captured event interrupt */
1002#define T0CLRI_CAP_BBA (*(volatile unsigned long *) 0x42000184)
1003#define T0CLRI_CAP_MSK (0x1 << 1 )
1004#define T0CLRI_CAP (0x1 << 1 )
1005#define T0CLRI_CAP_CLR (0x1 << 1 ) /* CLR */
1006
1007/* T0CLRI[TMOUT] - Clear timeout interrupt */
1008#define T0CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42000180)
1009#define T0CLRI_TMOUT_MSK (0x1 << 0 )
1010#define T0CLRI_TMOUT (0x1 << 0 )
1011#define T0CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR */
1012
1013/* Reset Value for T0CAP*/
1014#define T0CAP_RVAL 0x0
1015
1016/* T0CAP[VALUE] - Capture value */
1017#define T0CAP_VALUE_MSK (0xFFFF << 0 )
1018
1019/* Reset Value for T0STA*/
1020#define T0STA_RVAL 0x0
1021
1022/* T0STA[CLRI] - Value updated in the timer clock domain */
1023#define T0STA_CLRI_BBA (*(volatile unsigned long *) 0x4200039C)
1024#define T0STA_CLRI_MSK (0x1 << 7 )
1025#define T0STA_CLRI (0x1 << 7 )
1026#define T0STA_CLRI_CLR (0x0 << 7 ) /* CLR */
1027#define T0STA_CLRI_SET (0x1 << 7 ) /* SET */
1028
1029/* T0STA[CON] - Ready to receive commands */
1030#define T0STA_CON_BBA (*(volatile unsigned long *) 0x42000398)
1031#define T0STA_CON_MSK (0x1 << 6 )
1032#define T0STA_CON (0x1 << 6 )
1033#define T0STA_CON_CLR (0x0 << 6 ) /* CLR */
1034#define T0STA_CON_SET (0x1 << 6 ) /* SET */
1035
1036/* T0STA[CAP] - Capture event pending */
1037#define T0STA_CAP_BBA (*(volatile unsigned long *) 0x42000384)
1038#define T0STA_CAP_MSK (0x1 << 1 )
1039#define T0STA_CAP (0x1 << 1 )
1040#define T0STA_CAP_CLR (0x0 << 1 ) /* CLR */
1041#define T0STA_CAP_SET (0x1 << 1 ) /* SET */
1042
1043/* T0STA[TMOUT] - Time out event occurred */
1044#define T0STA_TMOUT_BBA (*(volatile unsigned long *) 0x42000380)
1045#define T0STA_TMOUT_MSK (0x1 << 0 )
1046#define T0STA_TMOUT (0x1 << 0 )
1047#define T0STA_TMOUT_CLR (0x0 << 0 ) /* CLR */
1048#define T0STA_TMOUT_SET (0x1 << 0 ) /* SET */
1049#if (__NO_MMR_STRUCTS__==1)
1050
1051#define T1LD (*(volatile unsigned short int *) 0x40000400)
1052#define T1VAL (*(volatile unsigned short int *) 0x40000404)
1053#define T1CON (*(volatile unsigned short int *) 0x40000408)
1054#define T1CLRI (*(volatile unsigned short int *) 0x4000040C)
1055#define T1CAP (*(volatile unsigned short int *) 0x40000410)
1056#define T1STA (*(volatile unsigned short int *) 0x4000041C)
1057#endif // (__NO_MMR_STRUCTS__==1)
1058
1059/* Reset Value for T1LD*/
1060#define T1LD_RVAL 0x0
1061
1062/* T1LD[VALUE] - Load value */
1063#define T1LD_VALUE_MSK (0xFFFF << 0 )
1064
1065/* Reset Value for T1VAL*/
1066#define T1VAL_RVAL 0x0
1067
1068/* T1VAL[VALUE] - Current value */
1069#define T1VAL_VALUE_MSK (0xFFFF << 0 )
1070
1071/* Reset Value for T1CON*/
1072#define T1CON_RVAL 0xA
1073
1074/* T1CON[EVENTEN] - Enable time capture of an event */
1075#define T1CON_EVENTEN_BBA (*(volatile unsigned long *) 0x42008130)
1076#define T1CON_EVENTEN_MSK (0x1 << 12 )
1077#define T1CON_EVENTEN (0x1 << 12 )
1078#define T1CON_EVENTEN_DIS (0x0 << 12 ) /* DIS */
1079#define T1CON_EVENTEN_EN (0x1 << 12 ) /* EN */
1080
1081/* T1CON[EVENT] - Event Select, selects 1 of the available events. */
1082#define T1CON_EVENT_MSK (0xF << 8 )
1083#define T1CON_EVENT_COM (0x0 << 8 ) /* COM */
1084#define T1CON_EVENT_T0 (0x1 << 8 ) /* T0 - Timer0 */
1085#define T1CON_EVENT_SPI0 (0x2 << 8 ) /* SPI0 */
1086#define T1CON_EVENT_SPI1 (0x3 << 8 ) /* SPI1 */
1087#define T1CON_EVENT_I2CS (0x4 << 8 ) /* I2CS */
1088#define T1CON_EVENT_I2CM (0x5 << 8 ) /* I2CM */
1089#define T1CON_EVENT_DMAERR (0x6 << 8 ) /* DMAERR */
1090#define T1CON_EVENT_DMADONE (0x7 << 8 ) /* DMADONE */
1091#define T1CON_EVENT_EXT1 (0x8 << 8 ) /* EXT1 */
1092#define T1CON_EVENT_EXT2 (0x9 << 8 ) /* EXT2 */
1093#define T1CON_EVENT_EXT3 (0xA << 8 ) /* EXT3 */
1094#define T1CON_EVENT_PWMTRIP (0xB << 8 ) /* PWMTRIP */
1095#define T1CON_EVENT_PWM0 (0xC << 8 ) /* PWM0 */
1096#define T1CON_EVENT_PWM1 (0xD << 8 ) /* PWM1 */
1097#define T1CON_EVENT_PWM2 (0xE << 8 ) /* PWM2 */
1098#define T1CON_EVENT_ADC0 (0xF << 8 ) /* ADC0 */
1099
1100/* T1CON[RLD] - Timer reload on write to clear register */
1101#define T1CON_RLD_BBA (*(volatile unsigned long *) 0x4200811C)
1102#define T1CON_RLD_MSK (0x1 << 7 )
1103#define T1CON_RLD (0x1 << 7 )
1104#define T1CON_RLD_DIS (0x0 << 7 ) /* DIS */
1105#define T1CON_RLD_EN (0x1 << 7 ) /* EN */
1106
1107/* T1CON[CLK] - Clock Select */
1108#define T1CON_CLK_MSK (0x3 << 5 )
1109#define T1CON_CLK_UCLK (0x0 << 5 ) /* UCLK - System Clock */
1110#define T1CON_CLK_PCLK (0x1 << 5 ) /* PCLK - Peripheral clock */
1111#define T1CON_CLK_LFOSC (0x2 << 5 ) /* LFOSC - Internal 32 kHz Oscillator */
1112#define T1CON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL - External 32 kHz crystal */
1113
1114/* T1CON[ENABLE] - Enable */
1115#define T1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42008110)
1116#define T1CON_ENABLE_MSK (0x1 << 4 )
1117#define T1CON_ENABLE (0x1 << 4 )
1118#define T1CON_ENABLE_DIS (0x0 << 4 ) /* DIS */
1119#define T1CON_ENABLE_EN (0x1 << 4 ) /* EN */
1120
1121/* T1CON[MOD] - Mode */
1122#define T1CON_MOD_BBA (*(volatile unsigned long *) 0x4200810C)
1123#define T1CON_MOD_MSK (0x1 << 3 )
1124#define T1CON_MOD (0x1 << 3 )
1125#define T1CON_MOD_FREERUN (0x0 << 3 ) /* FREERUN */
1126#define T1CON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC */
1127
1128/* T1CON[UP] - Count-up */
1129#define T1CON_UP_BBA (*(volatile unsigned long *) 0x42008108)
1130#define T1CON_UP_MSK (0x1 << 2 )
1131#define T1CON_UP (0x1 << 2 )
1132#define T1CON_UP_DIS (0x0 << 2 ) /* DIS */
1133#define T1CON_UP_EN (0x1 << 2 ) /* EN */
1134
1135/* T1CON[PRE] - Prescaler */
1136#define T1CON_PRE_MSK (0x3 << 0 )
1137#define T1CON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
1138#define T1CON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
1139#define T1CON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
1140#define T1CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 - If the selected clock source is UCLK then this setting results in a prescaler of 4. */
1141
1142/* Reset Value for T1CLRI*/
1143#define T1CLRI_RVAL 0x0
1144
1145/* T1CLRI[CAP] - Clear captured event interrupt */
1146#define T1CLRI_CAP_BBA (*(volatile unsigned long *) 0x42008184)
1147#define T1CLRI_CAP_MSK (0x1 << 1 )
1148#define T1CLRI_CAP (0x1 << 1 )
1149#define T1CLRI_CAP_CLR (0x1 << 1 ) /* CLR */
1150
1151/* T1CLRI[TMOUT] - Clear timeout interrupt */
1152#define T1CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42008180)
1153#define T1CLRI_TMOUT_MSK (0x1 << 0 )
1154#define T1CLRI_TMOUT (0x1 << 0 )
1155#define T1CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR */
1156
1157/* Reset Value for T1CAP*/
1158#define T1CAP_RVAL 0x0
1159
1160/* T1CAP[VALUE] - Capture value */
1161#define T1CAP_VALUE_MSK (0xFFFF << 0 )
1162
1163/* Reset Value for T1STA*/
1164#define T1STA_RVAL 0x0
1165
1166/* T1STA[CLRI] - Value updated in the timer clock domain */
1167#define T1STA_CLRI_BBA (*(volatile unsigned long *) 0x4200839C)
1168#define T1STA_CLRI_MSK (0x1 << 7 )
1169#define T1STA_CLRI (0x1 << 7 )
1170#define T1STA_CLRI_CLR (0x0 << 7 ) /* CLR */
1171#define T1STA_CLRI_SET (0x1 << 7 ) /* SET */
1172
1173/* T1STA[CON] - Ready to receive commands */
1174#define T1STA_CON_BBA (*(volatile unsigned long *) 0x42008398)
1175#define T1STA_CON_MSK (0x1 << 6 )
1176#define T1STA_CON (0x1 << 6 )
1177#define T1STA_CON_CLR (0x0 << 6 ) /* CLR */
1178#define T1STA_CON_SET (0x1 << 6 ) /* SET */
1179
1180/* T1STA[CAP] - Capture event pending */
1181#define T1STA_CAP_BBA (*(volatile unsigned long *) 0x42008384)
1182#define T1STA_CAP_MSK (0x1 << 1 )
1183#define T1STA_CAP (0x1 << 1 )
1184#define T1STA_CAP_CLR (0x0 << 1 ) /* CLR */
1185#define T1STA_CAP_SET (0x1 << 1 ) /* SET */
1186
1187/* T1STA[TMOUT] - Time out event occurred */
1188#define T1STA_TMOUT_BBA (*(volatile unsigned long *) 0x42008380)
1189#define T1STA_TMOUT_MSK (0x1 << 0 )
1190#define T1STA_TMOUT (0x1 << 0 )
1191#define T1STA_TMOUT_CLR (0x0 << 0 ) /* CLR */
1192#define T1STA_TMOUT_SET (0x1 << 0 ) /* SET */
1193// ------------------------------------------------------------------------------------------------
1194// ----- PWM -----
1195// ------------------------------------------------------------------------------------------------
1196
1197
1198/**
1199 * @brief Pulse Width Modulation (pADI_PWM)
1200 */
1201
1202#if (__NO_MMR_STRUCTS__==0)
1203typedef struct { /*!< pADI_PWM Structure */
1204 __IO uint16_t PWMCON0; /*!< PWM Control register */
1205 __I uint16_t RESERVED0;
1206 __IO uint8_t PWMCON1; /*!< Trip control register */
1207 __I uint8_t RESERVED1[3];
1208 __IO uint16_t PWMCLRI; /*!< PWM interrupt clear. Write to this register clears the latched PWM interrupt. */
1209 __I uint16_t RESERVED2[3];
1210 __IO uint16_t PWM0COM0; /*!< Compare Register 0 for PWM0 and PWM1 */
1211 __I uint16_t RESERVED3;
1212 __IO uint16_t PWM0COM1; /*!< Compare Register 1 for PWM0 and PWM1 */
1213 __I uint16_t RESERVED4;
1214 __IO uint16_t PWM0COM2; /*!< Compare Register 2 for PWM0 and PWM1 */
1215 __I uint16_t RESERVED5;
1216 __IO uint16_t PWM0LEN; /*!< Period Value register for PWM0 and PWM1 */
1217 __I uint16_t RESERVED6;
1218 __IO uint16_t PWM1COM0; /*!< Compare Register 0 for PWM2 and PWM3 */
1219 __I uint16_t RESERVED7;
1220 __IO uint16_t PWM1COM1; /*!< Compare Register 1 for PWM2 and PWM3 */
1221 __I uint16_t RESERVED8;
1222 __IO uint16_t PWM1COM2; /*!< Compare Register 2 for PWM2 and PWM3 */
1223 __I uint16_t RESERVED9;
1224 __IO uint16_t PWM1LEN; /*!< Period Value register for PWM2 and PWM3 */
1225 __I uint16_t RESERVED10;
1226 __IO uint16_t PWM2COM0; /*!< Compare Register 0 for PWM4 and PWM5 */
1227 __I uint16_t RESERVED11;
1228 __IO uint16_t PWM2COM1; /*!< Compare Register 1 for PWM4 and PWM5 */
1229 __I uint16_t RESERVED12;
1230 __IO uint16_t PWM2COM2; /*!< Compare Register 2 for PWM4 and PWM5 */
1231 __I uint16_t RESERVED13;
1232 __IO uint16_t PWM2LEN; /*!< Period Value register for PWM4 and PWM5 */
1233} ADI_PWM_TypeDef;
1234#else // (__NO_MMR_STRUCTS__==0)
1235#define PWMCON0 (*(volatile unsigned short int *) 0x40001000)
1236#define PWMCON1 (*(volatile unsigned char *) 0x40001004)
1237#define PWMCLRI (*(volatile unsigned short int *) 0x40001008)
1238#define PWM0COM0 (*(volatile unsigned short int *) 0x40001010)
1239#define PWM0COM1 (*(volatile unsigned short int *) 0x40001014)
1240#define PWM0COM2 (*(volatile unsigned short int *) 0x40001018)
1241#define PWM0LEN (*(volatile unsigned short int *) 0x4000101C)
1242#define PWM1COM0 (*(volatile unsigned short int *) 0x40001020)
1243#define PWM1COM1 (*(volatile unsigned short int *) 0x40001024)
1244#define PWM1COM2 (*(volatile unsigned short int *) 0x40001028)
1245#define PWM1LEN (*(volatile unsigned short int *) 0x4000102C)
1246#define PWM2COM0 (*(volatile unsigned short int *) 0x40001030)
1247#define PWM2COM1 (*(volatile unsigned short int *) 0x40001034)
1248#define PWM2COM2 (*(volatile unsigned short int *) 0x40001038)
1249#define PWM2LEN (*(volatile unsigned short int *) 0x4000103C)
1250#endif // (__NO_MMR_STRUCTS__==0)
1251
1252/* Reset Value for PWMCON0*/
1253#define PWMCON0_RVAL 0x12
1254
1255/* PWMCON0[SYNC] - PWM Synchronization */
1256#define PWMCON0_SYNC_BBA (*(volatile unsigned long *) 0x4202003C)
1257#define PWMCON0_SYNC_MSK (0x1 << 15 )
1258#define PWMCON0_SYNC (0x1 << 15 )
1259#define PWMCON0_SYNC_DIS (0x0 << 15 ) /* DIS */
1260#define PWMCON0_SYNC_EN (0x1 << 15 ) /* EN */
1261
1262/* PWMCON0[PWM5INV] - Inversion of PWM output */
1263#define PWMCON0_PWM5INV_BBA (*(volatile unsigned long *) 0x42020034)
1264#define PWMCON0_PWM5INV_MSK (0x1 << 13 )
1265#define PWMCON0_PWM5INV (0x1 << 13 )
1266#define PWMCON0_PWM5INV_DIS (0x0 << 13 ) /* DIS */
1267#define PWMCON0_PWM5INV_EN (0x1 << 13 ) /* EN */
1268
1269/* PWMCON0[PWM3INV] - Inversion of PWM output */
1270#define PWMCON0_PWM3INV_BBA (*(volatile unsigned long *) 0x42020030)
1271#define PWMCON0_PWM3INV_MSK (0x1 << 12 )
1272#define PWMCON0_PWM3INV (0x1 << 12 )
1273#define PWMCON0_PWM3INV_DIS (0x0 << 12 ) /* DIS */
1274#define PWMCON0_PWM3INV_EN (0x1 << 12 ) /* EN */
1275
1276/* PWMCON0[PWM1INV] - Inversion of PWM output */
1277#define PWMCON0_PWM1INV_BBA (*(volatile unsigned long *) 0x4202002C)
1278#define PWMCON0_PWM1INV_MSK (0x1 << 11 )
1279#define PWMCON0_PWM1INV (0x1 << 11 )
1280#define PWMCON0_PWM1INV_DIS (0x0 << 11 ) /* DIS */
1281#define PWMCON0_PWM1INV_EN (0x1 << 11 ) /* EN */
1282
1283/* PWMCON0[PWMIEN] - Enables PWM interrupts */
1284#define PWMCON0_PWMIEN_BBA (*(volatile unsigned long *) 0x42020028)
1285#define PWMCON0_PWMIEN_MSK (0x1 << 10 )
1286#define PWMCON0_PWMIEN (0x1 << 10 )
1287#define PWMCON0_PWMIEN_DIS (0x0 << 10 ) /* DIS */
1288#define PWMCON0_PWMIEN_EN (0x1 << 10 ) /* EN */
1289
1290/* PWMCON0[ENA] - enable PWM outputs */
1291#define PWMCON0_ENA_BBA (*(volatile unsigned long *) 0x42020024)
1292#define PWMCON0_ENA_MSK (0x1 << 9 )
1293#define PWMCON0_ENA (0x1 << 9 )
1294#define PWMCON0_ENA_DIS (0x0 << 9 ) /* DIS */
1295#define PWMCON0_ENA_EN (0x1 << 9 ) /* EN */
1296
1297/* PWMCON0[PRE] - PWM Clock Prescaler */
1298#define PWMCON0_PRE_MSK (0x7 << 6 )
1299
1300/* PWMCON0[POINV] - Invert all PWM outputs */
1301#define PWMCON0_POINV_BBA (*(volatile unsigned long *) 0x42020014)
1302#define PWMCON0_POINV_MSK (0x1 << 5 )
1303#define PWMCON0_POINV (0x1 << 5 )
1304#define PWMCON0_POINV_DIS (0x0 << 5 ) /* DIS */
1305#define PWMCON0_POINV_EN (0x1 << 5 ) /* EN */
1306
1307/* PWMCON0[HOFF] - High Side Off */
1308#define PWMCON0_HOFF_BBA (*(volatile unsigned long *) 0x42020010)
1309#define PWMCON0_HOFF_MSK (0x1 << 4 )
1310#define PWMCON0_HOFF (0x1 << 4 )
1311#define PWMCON0_HOFF_DIS (0x0 << 4 ) /* DIS */
1312#define PWMCON0_HOFF_EN (0x1 << 4 ) /* EN */
1313
1314/* PWMCON0[LCOMP] - Load Compare Registers */
1315#define PWMCON0_LCOMP_BBA (*(volatile unsigned long *) 0x4202000C)
1316#define PWMCON0_LCOMP_MSK (0x1 << 3 )
1317#define PWMCON0_LCOMP (0x1 << 3 )
1318#define PWMCON0_LCOMP_DIS (0x0 << 3 ) /* DIS */
1319#define PWMCON0_LCOMP_EN (0x1 << 3 ) /* EN */
1320
1321/* PWMCON0[DIR] - Direction Control */
1322#define PWMCON0_DIR_BBA (*(volatile unsigned long *) 0x42020008)
1323#define PWMCON0_DIR_MSK (0x1 << 2 )
1324#define PWMCON0_DIR (0x1 << 2 )
1325#define PWMCON0_DIR_DIS (0x0 << 2 ) /* DIS */
1326#define PWMCON0_DIR_EN (0x1 << 2 ) /* EN */
1327
1328/* PWMCON0[MOD] - Enables H-Bridge Mode */
1329#define PWMCON0_MOD_BBA (*(volatile unsigned long *) 0x42020004)
1330#define PWMCON0_MOD_MSK (0x1 << 1 )
1331#define PWMCON0_MOD (0x1 << 1 )
1332#define PWMCON0_MOD_DIS (0x0 << 1 ) /* DIS */
1333#define PWMCON0_MOD_EN (0x1 << 1 ) /* EN */
1334
1335/* PWMCON0[ENABLE] - Enables all PWM outputs */
1336#define PWMCON0_ENABLE_BBA (*(volatile unsigned long *) 0x42020000)
1337#define PWMCON0_ENABLE_MSK (0x1 << 0 )
1338#define PWMCON0_ENABLE (0x1 << 0 )
1339#define PWMCON0_ENABLE_DIS (0x0 << 0 ) /* DIS */
1340#define PWMCON0_ENABLE_EN (0x1 << 0 ) /* EN */
1341
1342/* Reset Value for PWMCON1*/
1343#define PWMCON1_RVAL 0x0
1344
1345/* PWMCON1[CONVSTART] - Enable adc conversion start from pwm */
1346#define PWMCON1_CONVSTART_BBA (*(volatile unsigned long *) 0x4202009C)
1347#define PWMCON1_CONVSTART_MSK (0x1 << 7 )
1348#define PWMCON1_CONVSTART (0x1 << 7 )
1349#define PWMCON1_CONVSTART_DIS (0x0 << 7 ) /* DIS */
1350#define PWMCON1_CONVSTART_EN (0x1 << 7 ) /* EN */
1351
1352/* PWMCON1[TRIPEN] - Enable PWM trip functionality */
1353#define PWMCON1_TRIPEN_BBA (*(volatile unsigned long *) 0x42020098)
1354#define PWMCON1_TRIPEN_MSK (0x1 << 6 )
1355#define PWMCON1_TRIPEN (0x1 << 6 )
1356#define PWMCON1_TRIPEN_DIS (0x0 << 6 ) /* DIS */
1357#define PWMCON1_TRIPEN_EN (0x1 << 6 ) /* EN */
1358
1359/* PWMCON1[CONVSTARTDELAY] - ADC conversion start delay configuration */
1360#define PWMCON1_CONVSTARTDELAY_MSK (0xF << 0 )
1361
1362/* Reset Value for PWMCLRI*/
1363#define PWMCLRI_RVAL 0x0
1364
1365/* PWMCLRI[TRIP] - Clear the latched trip interrupt */
1366#define PWMCLRI_TRIP_BBA (*(volatile unsigned long *) 0x42020110)
1367#define PWMCLRI_TRIP_MSK (0x1 << 4 )
1368#define PWMCLRI_TRIP (0x1 << 4 )
1369#define PWMCLRI_TRIP_DIS (0x0 << 4 ) /* DIS */
1370#define PWMCLRI_TRIP_EN (0x1 << 4 ) /* EN */
1371
1372/* PWMCLRI[PWM2] - Clear the latched PWM2 interrupt */
1373#define PWMCLRI_PWM2_BBA (*(volatile unsigned long *) 0x42020108)
1374#define PWMCLRI_PWM2_MSK (0x1 << 2 )
1375#define PWMCLRI_PWM2 (0x1 << 2 )
1376#define PWMCLRI_PWM2_DIS (0x0 << 2 ) /* DIS */
1377#define PWMCLRI_PWM2_EN (0x1 << 2 ) /* EN */
1378
1379/* PWMCLRI[PWM1] - Clear the latched PWM1 interrupt */
1380#define PWMCLRI_PWM1_BBA (*(volatile unsigned long *) 0x42020104)
1381#define PWMCLRI_PWM1_MSK (0x1 << 1 )
1382#define PWMCLRI_PWM1 (0x1 << 1 )
1383#define PWMCLRI_PWM1_DIS (0x0 << 1 ) /* DIS */
1384#define PWMCLRI_PWM1_EN (0x1 << 1 ) /* EN */
1385
1386/* PWMCLRI[PWM0] - Clear the latched PWM0 interrupt */
1387#define PWMCLRI_PWM0_BBA (*(volatile unsigned long *) 0x42020100)
1388#define PWMCLRI_PWM0_MSK (0x1 << 0 )
1389#define PWMCLRI_PWM0 (0x1 << 0 )
1390#define PWMCLRI_PWM0_DIS (0x0 << 0 ) /* DIS */
1391#define PWMCLRI_PWM0_EN (0x1 << 0 ) /* EN */
1392
1393/* Reset Value for PWM0COM0*/
1394#define PWM0COM0_RVAL 0x0
1395
1396/* Reset Value for PWM0COM1*/
1397#define PWM0COM1_RVAL 0x0
1398
1399/* Reset Value for PWM0COM2*/
1400#define PWM0COM2_RVAL 0x0
1401
1402/* Reset Value for PWM0LEN*/
1403#define PWM0LEN_RVAL 0x0
1404
1405/* Reset Value for PWM1COM0*/
1406#define PWM1COM0_RVAL 0x0
1407
1408/* Reset Value for PWM1COM1*/
1409#define PWM1COM1_RVAL 0x0
1410
1411/* Reset Value for PWM1COM2*/
1412#define PWM1COM2_RVAL 0x0
1413
1414/* Reset Value for PWM1LEN*/
1415#define PWM1LEN_RVAL 0x0
1416
1417/* Reset Value for PWM2COM0*/
1418#define PWM2COM0_RVAL 0x0
1419
1420/* Reset Value for PWM2COM1*/
1421#define PWM2COM1_RVAL 0x0
1422
1423/* Reset Value for PWM2COM2*/
1424#define PWM2COM2_RVAL 0x0
1425
1426/* Reset Value for PWM2LEN*/
1427#define PWM2LEN_RVAL 0x0
1428// ------------------------------------------------------------------------------------------------
1429// ----- PWRCTL -----
1430// ------------------------------------------------------------------------------------------------
1431
1432
1433/**
1434 * @brief Power Management Unit (pADI_PWRCTL)
1435 */
1436
1437#if (__NO_MMR_STRUCTS__==0)
1438typedef struct { /*!< pADI_PWRCTL Structure */
1439 __IO uint8_t PWRMOD; /*!< Power modes register */
1440 __I uint8_t RESERVED0[3];
1441 __IO uint16_t PWRKEY; /*!< Key protection for the PWRMOD register. */
1442} ADI_PWRCTL_TypeDef;
1443#else // (__NO_MMR_STRUCTS__==0)
1444#define PWRMOD (*(volatile unsigned char *) 0x40002400)
1445#define PWRKEY (*(volatile unsigned short int *) 0x40002404)
1446#endif // (__NO_MMR_STRUCTS__==0)
1447
1448/* Reset Value for PWRMOD*/
1449#define PWRMOD_RVAL 0x40
1450
1451/* PWRMOD[WICENACK] - For Deepsleep mode only */
1452#define PWRMOD_WICENACK_BBA (*(volatile unsigned long *) 0x4204800C)
1453#define PWRMOD_WICENACK_MSK (0x1 << 3 )
1454#define PWRMOD_WICENACK (0x1 << 3 )
1455#define PWRMOD_WICENACK_DIS (0x0 << 3 ) /* DIS */
1456#define PWRMOD_WICENACK_EN (0x1 << 3 ) /* EN */
1457
1458/* PWRMOD[MOD] - Power Mode */
1459#define PWRMOD_MOD_MSK (0x7 << 0 )
1460#define PWRMOD_MOD_FULLACTIVE (0x0 << 0 ) /* FULLACTIVE */
1461#define PWRMOD_MOD_MCUHALT (0x1 << 0 ) /* MCUHALT */
1462#define PWRMOD_MOD_PERHALT (0x2 << 0 ) /* PERHALT */
1463#define PWRMOD_MOD_SYSHALT (0x3 << 0 ) /* SYSHALT */
1464#define PWRMOD_MOD_TOTALHALT (0x4 << 0 ) /* TOTALHALT */
1465#define PWRMOD_MOD_HIBERNATE (0x5 << 0 ) /* HIBERNATE */
1466
1467/* Reset Value for PWRKEY*/
1468#define PWRKEY_RVAL 0x0
1469
1470/* PWRKEY[VALUE] - Key value */
1471#define PWRKEY_VALUE_MSK (0xFFFF << 0 )
1472#define PWRKEY_VALUE_KEY1 (0x4859 << 0 ) /* KEY1 */
1473#define PWRKEY_VALUE_KEY2 (0xF27B << 0 ) /* KEY2 */
1474// ------------------------------------------------------------------------------------------------
1475// ----- RESET -----
1476// ------------------------------------------------------------------------------------------------
1477
1478
1479/**
1480 * @brief Reset (pADI_RESET)
1481 */
1482
1483#if (__NO_MMR_STRUCTS__==0)
1484typedef struct { /*!< pADI_RESET Structure */
1485
1486 union {
1487 __IO uint8_t RSTSTA; /*!< Reset Status */
1488 __IO uint8_t RSTCLR; /*!< Reset Status Clear */
1489 } ;
1490} ADI_RESET_TypeDef;
1491#else // (__NO_MMR_STRUCTS__==0)
1492#define RSTSTA (*(volatile unsigned char *) 0x40002440)
1493#define RSTCLR (*(volatile unsigned char *) 0x40002440)
1494#endif // (__NO_MMR_STRUCTS__==0)
1495
1496/* Reset Value for RSTSTA*/
1497#define RSTSTA_RVAL 0x1
1498
1499/* RSTSTA[SWRST] - Software reset status bit */
1500#define RSTSTA_SWRST_BBA (*(volatile unsigned long *) 0x4204880C)
1501#define RSTSTA_SWRST_MSK (0x1 << 3 )
1502#define RSTSTA_SWRST (0x1 << 3 )
1503#define RSTSTA_SWRST_CLR (0x0 << 3 ) /* CLR */
1504#define RSTSTA_SWRST_SET (0x1 << 3 ) /* SET */
1505
1506/* RSTSTA[WDRST] - Watchdog reset status bit */
1507#define RSTSTA_WDRST_BBA (*(volatile unsigned long *) 0x42048808)
1508#define RSTSTA_WDRST_MSK (0x1 << 2 )
1509#define RSTSTA_WDRST (0x1 << 2 )
1510#define RSTSTA_WDRST_CLR (0x0 << 2 ) /* CLR */
1511#define RSTSTA_WDRST_SET (0x1 << 2 ) /* SET */
1512
1513/* RSTSTA[EXTRST] - External reset status bit */
1514#define RSTSTA_EXTRST_BBA (*(volatile unsigned long *) 0x42048804)
1515#define RSTSTA_EXTRST_MSK (0x1 << 1 )
1516#define RSTSTA_EXTRST (0x1 << 1 )
1517#define RSTSTA_EXTRST_CLR (0x0 << 1 ) /* CLR */
1518#define RSTSTA_EXTRST_SET (0x1 << 1 ) /* SET */
1519
1520/* RSTSTA[POR] - Power-on reset status bit */
1521#define RSTSTA_POR_BBA (*(volatile unsigned long *) 0x42048800)
1522#define RSTSTA_POR_MSK (0x1 << 0 )
1523#define RSTSTA_POR (0x1 << 0 )
1524#define RSTSTA_POR_CLR (0x0 << 0 ) /* CLR */
1525#define RSTSTA_POR_SET (0x1 << 0 ) /* SET */
1526
1527/* Reset Value for RSTCLR*/
1528#define RSTCLR_RVAL 0x1
1529
1530/* RSTCLR[SWRST] - Software reset status bit */
1531#define RSTCLR_SWRST_BBA (*(volatile unsigned long *) 0x4204880C)
1532#define RSTCLR_SWRST_MSK (0x1 << 3 )
1533#define RSTCLR_SWRST (0x1 << 3 )
1534#define RSTCLR_SWRST_DIS (0x0 << 3 ) /* DIS */
1535#define RSTCLR_SWRST_EN (0x1 << 3 ) /* EN */
1536
1537/* RSTCLR[WDRST] - Watchdog reset status bit */
1538#define RSTCLR_WDRST_BBA (*(volatile unsigned long *) 0x42048808)
1539#define RSTCLR_WDRST_MSK (0x1 << 2 )
1540#define RSTCLR_WDRST (0x1 << 2 )
1541#define RSTCLR_WDRST_DIS (0x0 << 2 ) /* DIS */
1542#define RSTCLR_WDRST_EN (0x1 << 2 ) /* EN */
1543
1544/* RSTCLR[EXTRST] - External reset status bit */
1545#define RSTCLR_EXTRST_BBA (*(volatile unsigned long *) 0x42048804)
1546#define RSTCLR_EXTRST_MSK (0x1 << 1 )
1547#define RSTCLR_EXTRST (0x1 << 1 )
1548#define RSTCLR_EXTRST_DIS (0x0 << 1 ) /* DIS */
1549#define RSTCLR_EXTRST_EN (0x1 << 1 ) /* EN */
1550
1551/* RSTCLR[POR] - Power-on reset status bit */
1552#define RSTCLR_POR_BBA (*(volatile unsigned long *) 0x42048800)
1553#define RSTCLR_POR_MSK (0x1 << 0 )
1554#define RSTCLR_POR (0x1 << 0 )
1555#define RSTCLR_POR_DIS (0x0 << 0 ) /* DIS */
1556#define RSTCLR_POR_EN (0x1 << 0 ) /* EN */
1557// ------------------------------------------------------------------------------------------------
1558// ----- INTERRUPT -----
1559// ------------------------------------------------------------------------------------------------
1560
1561
1562/**
1563 * @brief Interrupts (pADI_INTERRUPT)
1564 */
1565
1566#if (__NO_MMR_STRUCTS__==0)
1567typedef struct { /*!< pADI_INTERRUPT Structure */
1568 __IO uint16_t EI0CFG; /*!< External Interrupt configuration register 0 */
1569 __I uint16_t RESERVED0;
1570 __IO uint16_t EI1CFG; /*!< External Interrupt configuration register 1 */
1571 __I uint16_t RESERVED1[5];
1572 __IO uint16_t EICLR; /*!< External Interrupts Clear register */
1573} ADI_INTERRUPT_TypeDef;
1574#else // (__NO_MMR_STRUCTS__==0)
1575#define EI0CFG (*(volatile unsigned short int *) 0x40002420)
1576#define EI1CFG (*(volatile unsigned short int *) 0x40002424)
1577#define EICLR (*(volatile unsigned short int *) 0x40002430)
1578#endif // (__NO_MMR_STRUCTS__==0)
1579
1580/* Reset Value for EI0CFG*/
1581#define EI0CFG_RVAL 0x0
1582
1583/* EI0CFG[IRQ3EN] - External Interrupt 3 Enable */
1584#define EI0CFG_IRQ3EN_BBA (*(volatile unsigned long *) 0x4204843C)
1585#define EI0CFG_IRQ3EN_MSK (0x1 << 15 )
1586#define EI0CFG_IRQ3EN (0x1 << 15 )
1587#define EI0CFG_IRQ3EN_DIS (0x0 << 15 ) /* DIS */
1588#define EI0CFG_IRQ3EN_EN (0x1 << 15 ) /* EN */
1589
1590/* EI0CFG[IRQ3MDE] - External Interrupt 0 Mode */
1591#define EI0CFG_IRQ3MDE_MSK (0x7 << 12 )
1592#define EI0CFG_IRQ3MDE_RISE (0x0 << 12 ) /* RISE */
1593#define EI0CFG_IRQ3MDE_FALL (0x1 << 12 ) /* FALL */
1594#define EI0CFG_IRQ3MDE_RISEORFALL (0x2 << 12 ) /* RISEORFALL */
1595#define EI0CFG_IRQ3MDE_HIGHLEVEL (0x3 << 12 ) /* HIGHLEVEL */
1596#define EI0CFG_IRQ3MDE_LOWLEVEL (0x4 << 12 ) /* LOWLEVEL */
1597
1598/* EI0CFG[IRQ2EN] - External Interrupt 2 Enable */
1599#define EI0CFG_IRQ2EN_BBA (*(volatile unsigned long *) 0x4204842C)
1600#define EI0CFG_IRQ2EN_MSK (0x1 << 11 )
1601#define EI0CFG_IRQ2EN (0x1 << 11 )
1602#define EI0CFG_IRQ2EN_DIS (0x0 << 11 ) /* DIS */
1603#define EI0CFG_IRQ2EN_EN (0x1 << 11 ) /* EN */
1604
1605/* EI0CFG[IRQ2MDE] - External Interrupt 2 Mode */
1606#define EI0CFG_IRQ2MDE_MSK (0x7 << 8 )
1607#define EI0CFG_IRQ2MDE_RISE (0x0 << 8 ) /* RISE */
1608#define EI0CFG_IRQ2MDE_FALL (0x1 << 8 ) /* FALL */
1609#define EI0CFG_IRQ2MDE_RISEORFALL (0x2 << 8 ) /* RISEORFALL */
1610#define EI0CFG_IRQ2MDE_HIGHLEVEL (0x3 << 8 ) /* HIGHLEVEL */
1611#define EI0CFG_IRQ2MDE_LOWLEVEL (0x4 << 8 ) /* LOWLEVEL */
1612
1613/* EI0CFG[IRQ1EN] - External Interrupt 1 Enable */
1614#define EI0CFG_IRQ1EN_BBA (*(volatile unsigned long *) 0x4204841C)
1615#define EI0CFG_IRQ1EN_MSK (0x1 << 7 )
1616#define EI0CFG_IRQ1EN (0x1 << 7 )
1617#define EI0CFG_IRQ1EN_DIS (0x0 << 7 ) /* DIS */
1618#define EI0CFG_IRQ1EN_EN (0x1 << 7 ) /* EN */
1619
1620/* EI0CFG[IRQ1MDE] - External Interrupt 1 Mode */
1621#define EI0CFG_IRQ1MDE_MSK (0x7 << 4 )
1622#define EI0CFG_IRQ1MDE_RISE (0x0 << 4 ) /* RISE */
1623#define EI0CFG_IRQ1MDE_FALL (0x1 << 4 ) /* FALL */
1624#define EI0CFG_IRQ1MDE_RISEORFALL (0x2 << 4 ) /* RISEORFALL */
1625#define EI0CFG_IRQ1MDE_HIGHLEVEL (0x3 << 4 ) /* HIGHLEVEL */
1626#define EI0CFG_IRQ1MDE_LOWLEVEL (0x4 << 4 ) /* LOWLEVEL */
1627
1628/* EI0CFG[IRQ0EN] - External Interrupt 0 Enable */
1629#define EI0CFG_IRQ0EN_BBA (*(volatile unsigned long *) 0x4204840C)
1630#define EI0CFG_IRQ0EN_MSK (0x1 << 3 )
1631#define EI0CFG_IRQ0EN (0x1 << 3 )
1632#define EI0CFG_IRQ0EN_DIS (0x0 << 3 ) /* DIS */
1633#define EI0CFG_IRQ0EN_EN (0x1 << 3 ) /* EN */
1634
1635/* EI0CFG[IRQ0MDE] - External Interrupt 0 Mode */
1636#define EI0CFG_IRQ0MDE_MSK (0x7 << 0 )
1637#define EI0CFG_IRQ0MDE_RISE (0x0 << 0 ) /* RISE */
1638#define EI0CFG_IRQ0MDE_FALL (0x1 << 0 ) /* FALL */
1639#define EI0CFG_IRQ0MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL */
1640#define EI0CFG_IRQ0MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL */
1641#define EI0CFG_IRQ0MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL */
1642
1643/* Reset Value for EI1CFG*/
1644#define EI1CFG_RVAL 0x0
1645
1646/* EI1CFG[IRQ7EN] - External Interrupt 7 Enable */
1647#define EI1CFG_IRQ7EN_BBA (*(volatile unsigned long *) 0x420484BC)
1648#define EI1CFG_IRQ7EN_MSK (0x1 << 15 )
1649#define EI1CFG_IRQ7EN (0x1 << 15 )
1650#define EI1CFG_IRQ7EN_DIS (0x0 << 15 ) /* DIS */
1651#define EI1CFG_IRQ7EN_EN (0x1 << 15 ) /* EN */
1652
1653/* EI1CFG[IRQ7MDE] - External Interrupt 7 Mode */
1654#define EI1CFG_IRQ7MDE_MSK (0x7 << 12 )
1655#define EI1CFG_IRQ7MDE_RISE (0x0 << 12 ) /* RISE */
1656#define EI1CFG_IRQ7MDE_FALL (0x1 << 12 ) /* FALL */
1657#define EI1CFG_IRQ7MDE_RISEORFALL (0x2 << 12 ) /* RISEORFALL */
1658#define EI1CFG_IRQ7MDE_HIGHLEVEL (0x3 << 12 ) /* HIGHLEVEL */
1659#define EI1CFG_IRQ7MDE_LOWLEVEL (0x4 << 12 ) /* LOWLEVEL */
1660
1661/* EI1CFG[IRQ6EN] - External Interrupt 6 Enable */
1662#define EI1CFG_IRQ6EN_BBA (*(volatile unsigned long *) 0x420484AC)
1663#define EI1CFG_IRQ6EN_MSK (0x1 << 11 )
1664#define EI1CFG_IRQ6EN (0x1 << 11 )
1665#define EI1CFG_IRQ6EN_DIS (0x0 << 11 ) /* DIS */
1666#define EI1CFG_IRQ6EN_EN (0x1 << 11 ) /* EN */
1667
1668/* EI1CFG[IRQ6MDE] - External Interrupt 6 Mode */
1669#define EI1CFG_IRQ6MDE_MSK (0x7 << 8 )
1670#define EI1CFG_IRQ6MDE_RISE (0x0 << 8 ) /* RISE */
1671#define EI1CFG_IRQ6MDE_FALL (0x1 << 8 ) /* FALL */
1672#define EI1CFG_IRQ6MDE_RISEORFALL (0x2 << 8 ) /* RISEORFALL */
1673#define EI1CFG_IRQ6MDE_HIGHLEVEL (0x3 << 8 ) /* HIGHLEVEL */
1674#define EI1CFG_IRQ6MDE_LOWLEVEL (0x4 << 8 ) /* LOWLEVEL */
1675
1676/* EI1CFG[IRQ5EN] - External Interrupt 5 Enable */
1677#define EI1CFG_IRQ5EN_BBA (*(volatile unsigned long *) 0x4204849C)
1678#define EI1CFG_IRQ5EN_MSK (0x1 << 7 )
1679#define EI1CFG_IRQ5EN (0x1 << 7 )
1680#define EI1CFG_IRQ5EN_DIS (0x0 << 7 ) /* DIS */
1681#define EI1CFG_IRQ5EN_EN (0x1 << 7 ) /* EN */
1682
1683/* EI1CFG[IRQ5MDE] - External Interrupt 5 Mode */
1684#define EI1CFG_IRQ5MDE_MSK (0x7 << 4 )
1685#define EI1CFG_IRQ5MDE_RISE (0x0 << 4 ) /* RISE */
1686#define EI1CFG_IRQ5MDE_FALL (0x1 << 4 ) /* FALL */
1687#define EI1CFG_IRQ5MDE_RISEORFALL (0x2 << 4 ) /* RISEORFALL */
1688#define EI1CFG_IRQ5MDE_HIGHLEVEL (0x3 << 4 ) /* HIGHLEVEL */
1689#define EI1CFG_IRQ5MDE_LOWLEVEL (0x4 << 4 ) /* LOWLEVEL */
1690
1691/* EI1CFG[IRQ4EN] - External Interrupt 4 Enable */
1692#define EI1CFG_IRQ4EN_BBA (*(volatile unsigned long *) 0x4204848C)
1693#define EI1CFG_IRQ4EN_MSK (0x1 << 3 )
1694#define EI1CFG_IRQ4EN (0x1 << 3 )
1695#define EI1CFG_IRQ4EN_DIS (0x0 << 3 ) /* DIS */
1696#define EI1CFG_IRQ4EN_EN (0x1 << 3 ) /* EN */
1697
1698/* EI1CFG[IRQ4MDE] - External Interrupt 4 Mode */
1699#define EI1CFG_IRQ4MDE_MSK (0x7 << 0 )
1700#define EI1CFG_IRQ4MDE_RISE (0x0 << 0 ) /* RISE */
1701#define EI1CFG_IRQ4MDE_FALL (0x1 << 0 ) /* FALL */
1702#define EI1CFG_IRQ4MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL */
1703#define EI1CFG_IRQ4MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL */
1704#define EI1CFG_IRQ4MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL */
1705
1706/* Reset Value for EICLR*/
1707#define EICLR_RVAL 0x0
1708
1709/* EICLR[IRQ7] - Clears External interrupt 7 internal flag */
1710#define EICLR_IRQ7_BBA (*(volatile unsigned long *) 0x4204861C)
1711#define EICLR_IRQ7_MSK (0x1 << 7 )
1712#define EICLR_IRQ7 (0x1 << 7 )
1713#define EICLR_IRQ7_CLR (0x1 << 7 ) /* CLR */
1714
1715/* EICLR[IRQ6] - Clears External interrupt 6 internal flag */
1716#define EICLR_IRQ6_BBA (*(volatile unsigned long *) 0x42048618)
1717#define EICLR_IRQ6_MSK (0x1 << 6 )
1718#define EICLR_IRQ6 (0x1 << 6 )
1719#define EICLR_IRQ6_CLR (0x1 << 6 ) /* CLR */
1720
1721/* EICLR[IRQ5] - Clears External interrupt 5 internal flag */
1722#define EICLR_IRQ5_BBA (*(volatile unsigned long *) 0x42048614)
1723#define EICLR_IRQ5_MSK (0x1 << 5 )
1724#define EICLR_IRQ5 (0x1 << 5 )
1725#define EICLR_IRQ5_CLR (0x1 << 5 ) /* CLR */
1726
1727/* EICLR[IRQ4] - Clears External interrupt 4 internal flag */
1728#define EICLR_IRQ4_BBA (*(volatile unsigned long *) 0x42048610)
1729#define EICLR_IRQ4_MSK (0x1 << 4 )
1730#define EICLR_IRQ4 (0x1 << 4 )
1731#define EICLR_IRQ4_CLR (0x1 << 4 ) /* CLR */
1732
1733/* EICLR[IRQ3] - Clears External interrupt 3 internal flag */
1734#define EICLR_IRQ3_BBA (*(volatile unsigned long *) 0x4204860C)
1735#define EICLR_IRQ3_MSK (0x1 << 3 )
1736#define EICLR_IRQ3 (0x1 << 3 )
1737#define EICLR_IRQ3_CLR (0x1 << 3 ) /* CLR */
1738
1739/* EICLR[IRQ2] - Clears External interrupt 2 internal flag */
1740#define EICLR_IRQ2_BBA (*(volatile unsigned long *) 0x42048608)
1741#define EICLR_IRQ2_MSK (0x1 << 2 )
1742#define EICLR_IRQ2 (0x1 << 2 )
1743#define EICLR_IRQ2_CLR (0x1 << 2 ) /* CLR */
1744
1745/* EICLR[IRQ1] - Clears External interrupt 1 internal flag */
1746#define EICLR_IRQ1_BBA (*(volatile unsigned long *) 0x42048604)
1747#define EICLR_IRQ1_MSK (0x1 << 1 )
1748#define EICLR_IRQ1 (0x1 << 1 )
1749#define EICLR_IRQ1_CLR (0x1 << 1 ) /* CLR */
1750
1751/* EICLR[IRQ0] - Clears External interrupt 0 internal flag */
1752#define EICLR_IRQ0_BBA (*(volatile unsigned long *) 0x42048600)
1753#define EICLR_IRQ0_MSK (0x1 << 0 )
1754#define EICLR_IRQ0 (0x1 << 0 )
1755#define EICLR_IRQ0_CLR (0x1 << 0 ) /* CLR */
1756// ------------------------------------------------------------------------------------------------
1757// ----- WDT -----
1758// ------------------------------------------------------------------------------------------------
1759
1760
1761/**
1762 * @brief Watchdog Timer (pADI_WDT)
1763 */
1764
1765#if (__NO_MMR_STRUCTS__==0)
1766typedef struct { /*!< pADI_WDT Structure */
1767 __IO uint16_t T3LD; /*!< Load value. */
1768 __I uint16_t RESERVED0;
1769 __IO uint16_t T3VAL; /*!< "Current count value, read only." */
1770 __I uint16_t RESERVED1;
1771 __IO uint16_t T3CON; /*!< Control Register */
1772 __I uint16_t RESERVED2;
1773 __IO uint16_t T3CLRI; /*!< "Clear interrupt, write only." */
1774 __I uint16_t RESERVED3[5];
1775 __IO uint16_t T3STA; /*!< "Status register, read only." */
1776} ADI_WDT_TypeDef;
1777#else // (__NO_MMR_STRUCTS__==0)
1778#define T3LD (*(volatile unsigned short int *) 0x40002580)
1779#define T3VAL (*(volatile unsigned short int *) 0x40002584)
1780#define T3CON (*(volatile unsigned short int *) 0x40002588)
1781#define T3CLRI (*(volatile unsigned short int *) 0x4000258C)
1782#define T3STA (*(volatile unsigned short int *) 0x40002598)
1783#endif // (__NO_MMR_STRUCTS__==0)
1784
1785/* Reset Value for T3LD*/
1786#define T3LD_RVAL 0x1000
1787
1788/* T3LD[VALUE] - Current Value */
1789#define T3LD_VALUE_MSK (0xFFFF << 0 )
1790
1791/* Reset Value for T3VAL*/
1792#define T3VAL_RVAL 0x1000
1793
1794/* T3VAL[VALUE] - Current Value */
1795#define T3VAL_VALUE_MSK (0xFFFF << 0 )
1796
1797/* Reset Value for T3CON*/
1798#define T3CON_RVAL 0xE9
1799
1800/* T3CON[MOD] - Mode */
1801#define T3CON_MOD_BBA (*(volatile unsigned long *) 0x4204B118)
1802#define T3CON_MOD_MSK (0x1 << 6 )
1803#define T3CON_MOD (0x1 << 6 )
1804#define T3CON_MOD_FREERUN (0x0 << 6 ) /* FREERUN */
1805#define T3CON_MOD_PERIODIC (0x1 << 6 ) /* PERIODIC */
1806
1807/* T3CON[ENABLE] - Enable */
1808#define T3CON_ENABLE_BBA (*(volatile unsigned long *) 0x4204B114)
1809#define T3CON_ENABLE_MSK (0x1 << 5 )
1810#define T3CON_ENABLE (0x1 << 5 )
1811#define T3CON_ENABLE_DIS (0x0 << 5 ) /* DIS */
1812#define T3CON_ENABLE_EN (0x1 << 5 ) /* EN */
1813
1814/* T3CON[PRE] - Prescaler */
1815#define T3CON_PRE_MSK (0x3 << 2 )
1816#define T3CON_PRE_DIV1 (0x0 << 2 ) /* DIV1 */
1817#define T3CON_PRE_DIV16 (0x1 << 2 ) /* DIV16 */
1818#define T3CON_PRE_DIV256 (0x2 << 2 ) /* DIV256 */
1819#define T3CON_PRE_DIV4096 (0x3 << 2 ) /* DIV4096 */
1820
1821/* T3CON[IRQ] - Timer Interrupt , */
1822#define T3CON_IRQ_BBA (*(volatile unsigned long *) 0x4204B104)
1823#define T3CON_IRQ_MSK (0x1 << 1 )
1824#define T3CON_IRQ (0x1 << 1 )
1825#define T3CON_IRQ_DIS (0x0 << 1 ) /* DIS */
1826#define T3CON_IRQ_EN (0x1 << 1 ) /* EN */
1827
1828/* T3CON[PD] - Power down clear */
1829#define T3CON_PD_BBA (*(volatile unsigned long *) 0x4204B100)
1830#define T3CON_PD_MSK (0x1 << 0 )
1831#define T3CON_PD (0x1 << 0 )
1832#define T3CON_PD_DIS (0x0 << 0 ) /* DIS */
1833#define T3CON_PD_EN (0x1 << 0 ) /* EN */
1834
1835/* Reset Value for T3CLRI*/
1836#define T3CLRI_RVAL 0x0
1837
1838/* T3CLRI[VALUE] - Clear Watchdog */
1839#define T3CLRI_VALUE_MSK (0xFFFF << 0 )
1840#define T3CLRI_VALUE_CLR (0xCCCC << 0 ) /* CLR */
1841
1842/* Reset Value for T3STA*/
1843#define T3STA_RVAL 0x20
1844
1845/* T3STA[LOCK] - Lock status bit */
1846#define T3STA_LOCK_BBA (*(volatile unsigned long *) 0x4204B310)
1847#define T3STA_LOCK_MSK (0x1 << 4 )
1848#define T3STA_LOCK (0x1 << 4 )
1849#define T3STA_LOCK_CLR (0x0 << 4 ) /* CLR */
1850#define T3STA_LOCK_SET (0x1 << 4 ) /* SET */
1851
1852/* T3STA[CON] - T3CON write sync in progress */
1853#define T3STA_CON_BBA (*(volatile unsigned long *) 0x4204B30C)
1854#define T3STA_CON_MSK (0x1 << 3 )
1855#define T3STA_CON (0x1 << 3 )
1856#define T3STA_CON_CLR (0x0 << 3 ) /* CLR */
1857#define T3STA_CON_SET (0x1 << 3 ) /* SET */
1858
1859/* T3STA[LD] - T3LD write sync in progress */
1860#define T3STA_LD_BBA (*(volatile unsigned long *) 0x4204B308)
1861#define T3STA_LD_MSK (0x1 << 2 )
1862#define T3STA_LD (0x1 << 2 )
1863#define T3STA_LD_CLR (0x0 << 2 ) /* CLR */
1864#define T3STA_LD_SET (0x1 << 2 ) /* SET */
1865
1866/* T3STA[CLRI] - T3CLRI write sync in progress */
1867#define T3STA_CLRI_BBA (*(volatile unsigned long *) 0x4204B304)
1868#define T3STA_CLRI_MSK (0x1 << 1 )
1869#define T3STA_CLRI (0x1 << 1 )
1870#define T3STA_CLRI_CLR (0x0 << 1 ) /* CLR */
1871#define T3STA_CLRI_SET (0x1 << 1 ) /* SET */
1872
1873/* T3STA[IRQ] - Interrupt Pending */
1874#define T3STA_IRQ_BBA (*(volatile unsigned long *) 0x4204B300)
1875#define T3STA_IRQ_MSK (0x1 << 0 )
1876#define T3STA_IRQ (0x1 << 0 )
1877#define T3STA_IRQ_CLR (0x0 << 0 ) /* CLR */
1878#define T3STA_IRQ_SET (0x1 << 0 ) /* SET */
1879// ------------------------------------------------------------------------------------------------
1880// ----- WUT -----
1881// ------------------------------------------------------------------------------------------------
1882
1883
1884/**
1885 * @brief WakeUp Timer (pADI_WUT)
1886 */
1887
1888#if (__NO_MMR_STRUCTS__==0)
1889typedef struct { /*!< pADI_WUT Structure */
1890 __IO uint16_t T2VAL0; /*!< Current count value LSB */
1891 __I uint16_t RESERVED0;
1892 __IO uint16_t T2VAL1; /*!< Current count value MSB */
1893 __I uint16_t RESERVED1;
1894 __IO uint16_t T2CON; /*!< Control Register */
1895 __I uint16_t RESERVED2;
1896 __IO uint16_t T2INC; /*!< 12-bit register. Wake up field A */
1897 __I uint16_t RESERVED3;
1898 __IO uint16_t T2WUFB0; /*!< Wake up field B LSB */
1899 __I uint16_t RESERVED4;
1900 __IO uint16_t T2WUFB1; /*!< Wake up field B MSB */
1901 __I uint16_t RESERVED5;
1902 __IO uint16_t T2WUFC0; /*!< Wake up field C LSB */
1903 __I uint16_t RESERVED6;
1904 __IO uint16_t T2WUFC1; /*!< Wake up field C MSB */
1905 __I uint16_t RESERVED7;
1906 __IO uint16_t T2WUFD0; /*!< Wake up field D LSB */
1907 __I uint16_t RESERVED8;
1908 __IO uint16_t T2WUFD1; /*!< Wake up field D MSB */
1909 __I uint16_t RESERVED9;
1910 __IO uint16_t T2IEN; /*!< Interrupt enable */
1911 __I uint16_t RESERVED10;
1912 __IO uint16_t T2STA; /*!< Status */
1913 __I uint16_t RESERVED11;
1914 __IO uint16_t T2CLRI; /*!< Clear interrupts. Write only. */
1915 __I uint16_t RESERVED12[5];
1916 __IO uint16_t T2WUFA0; /*!< Wake up field A LSB. */
1917 __I uint16_t RESERVED13;
1918 __IO uint16_t T2WUFA1; /*!< Wake up field A MSB. */
1919} ADI_WUT_TypeDef;
1920#else // (__NO_MMR_STRUCTS__==0)
1921#define T2VAL0 (*(volatile unsigned short int *) 0x40002500)
1922#define T2VAL1 (*(volatile unsigned short int *) 0x40002504)
1923#define T2CON (*(volatile unsigned short int *) 0x40002508)
1924#define T2INC (*(volatile unsigned short int *) 0x4000250C)
1925#define T2WUFB0 (*(volatile unsigned short int *) 0x40002510)
1926#define T2WUFB1 (*(volatile unsigned short int *) 0x40002514)
1927#define T2WUFC0 (*(volatile unsigned short int *) 0x40002518)
1928#define T2WUFC1 (*(volatile unsigned short int *) 0x4000251C)
1929#define T2WUFD0 (*(volatile unsigned short int *) 0x40002520)
1930#define T2WUFD1 (*(volatile unsigned short int *) 0x40002524)
1931#define T2IEN (*(volatile unsigned short int *) 0x40002528)
1932#define T2STA (*(volatile unsigned short int *) 0x4000252C)
1933#define T2CLRI (*(volatile unsigned short int *) 0x40002530)
1934#define T2WUFA0 (*(volatile unsigned short int *) 0x4000253C)
1935#define T2WUFA1 (*(volatile unsigned short int *) 0x40002540)
1936#endif // (__NO_MMR_STRUCTS__==0)
1937
1938/* Reset Value for T2VAL0*/
1939#define T2VAL0_RVAL 0x0
1940
1941/* T2VAL0[VALUE] - Current Value */
1942#define T2VAL0_VALUE_MSK (0xFFFF << 0 )
1943
1944/* Reset Value for T2VAL1*/
1945#define T2VAL1_RVAL 0x0
1946
1947/* T2VAL1[VALUE] - Current Value */
1948#define T2VAL1_VALUE_MSK (0xFFFF << 0 )
1949
1950/* Reset Value for T2CON*/
1951#define T2CON_RVAL 0x40
1952
1953/* T2CON[STOPINC] - Stop wake up field A being updated */
1954#define T2CON_STOPINC_BBA (*(volatile unsigned long *) 0x4204A12C)
1955#define T2CON_STOPINC_MSK (0x1 << 11 )
1956#define T2CON_STOPINC (0x1 << 11 )
1957#define T2CON_STOPINC_DIS (0x0 << 11 ) /* DIS */
1958#define T2CON_STOPINC_EN (0x1 << 11 ) /* EN */
1959
1960/* T2CON[CLK] - Clock */
1961#define T2CON_CLK_MSK (0x3 << 9 )
1962#define T2CON_CLK_PCLK (0x0 << 9 ) /* PCLK */
1963#define T2CON_CLK_LFXTAL (0x1 << 9 ) /* LFXTAL */
1964#define T2CON_CLK_LFOSC (0x2 << 9 ) /* LFOSC */
1965#define T2CON_CLK_EXTCLK (0x3 << 9 ) /* EXTCLK */
1966
1967/* T2CON[WUEN] - WUEN */
1968#define T2CON_WUEN_BBA (*(volatile unsigned long *) 0x4204A120)
1969#define T2CON_WUEN_MSK (0x1 << 8 )
1970#define T2CON_WUEN (0x1 << 8 )
1971#define T2CON_WUEN_DIS (0x0 << 8 ) /* DIS */
1972#define T2CON_WUEN_EN (0x1 << 8 ) /* EN */
1973
1974/* T2CON[ENABLE] - Enable */
1975#define T2CON_ENABLE_BBA (*(volatile unsigned long *) 0x4204A11C)
1976#define T2CON_ENABLE_MSK (0x1 << 7 )
1977#define T2CON_ENABLE (0x1 << 7 )
1978#define T2CON_ENABLE_DIS (0x0 << 7 ) /* DIS */
1979#define T2CON_ENABLE_EN (0x1 << 7 ) /* EN */
1980
1981/* T2CON[MOD] - Mode */
1982#define T2CON_MOD_BBA (*(volatile unsigned long *) 0x4204A118)
1983#define T2CON_MOD_MSK (0x1 << 6 )
1984#define T2CON_MOD (0x1 << 6 )
1985#define T2CON_MOD_PERIODIC (0x0 << 6 ) /* PERIODIC */
1986#define T2CON_MOD_FREERUN (0x1 << 6 ) /* FREERUN */
1987
1988/* T2CON[FREEZE] - Freeze */
1989#define T2CON_FREEZE_BBA (*(volatile unsigned long *) 0x4204A10C)
1990#define T2CON_FREEZE_MSK (0x1 << 3 )
1991#define T2CON_FREEZE (0x1 << 3 )
1992#define T2CON_FREEZE_DIS (0x0 << 3 ) /* DIS */
1993#define T2CON_FREEZE_EN (0x1 << 3 ) /* EN */
1994
1995/* T2CON[PRE] - Prescaler */
1996#define T2CON_PRE_MSK (0x3 << 0 )
1997#define T2CON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
1998#define T2CON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
1999#define T2CON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
2000#define T2CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 */
2001
2002/* Reset Value for T2INC*/
2003#define T2INC_RVAL 0xC8
2004
2005/* T2INC[VALUE] - 12 bit value */
2006#define T2INC_VALUE_MSK (0xFFF << 0 )
2007
2008/* Reset Value for T2WUFB0*/
2009#define T2WUFB0_RVAL 0x1FFF
2010
2011/* T2WUFB0[VALUE] - Current Value */
2012#define T2WUFB0_VALUE_MSK (0xFFFF << 0 )
2013
2014/* Reset Value for T2WUFB1*/
2015#define T2WUFB1_RVAL 0x0
2016
2017/* T2WUFB1[VALUE] - Current Value */
2018#define T2WUFB1_VALUE_MSK (0xFFFF << 0 )
2019
2020/* Reset Value for T2WUFC0*/
2021#define T2WUFC0_RVAL 0x2FFF
2022
2023/* T2WUFC0[VALUE] - Current Value */
2024#define T2WUFC0_VALUE_MSK (0xFFFF << 0 )
2025
2026/* Reset Value for T2WUFC1*/
2027#define T2WUFC1_RVAL 0x0
2028
2029/* T2WUFC1[VALUE] - Current Value */
2030#define T2WUFC1_VALUE_MSK (0xFFFF << 0 )
2031
2032/* Reset Value for T2WUFD0*/
2033#define T2WUFD0_RVAL 0x3FFF
2034
2035/* T2WUFD0[VALUE] - Current Value */
2036#define T2WUFD0_VALUE_MSK (0xFFFF << 0 )
2037
2038/* Reset Value for T2WUFD1*/
2039#define T2WUFD1_RVAL 0x0
2040
2041/* T2WUFD1[VALUE] - Current Value */
2042#define T2WUFD1_VALUE_MSK (0xFFFF << 0 )
2043
2044/* Reset Value for T2IEN*/
2045#define T2IEN_RVAL 0x0
2046
2047/* T2IEN[ROLL] - Enable interrupt on Rollover */
2048#define T2IEN_ROLL_BBA (*(volatile unsigned long *) 0x4204A510)
2049#define T2IEN_ROLL_MSK (0x1 << 4 )
2050#define T2IEN_ROLL (0x1 << 4 )
2051#define T2IEN_ROLL_DIS (0x0 << 4 ) /* DIS */
2052#define T2IEN_ROLL_EN (0x1 << 4 ) /* EN */
2053
2054/* T2IEN[WUFD] - Enable interrupt on WUFD */
2055#define T2IEN_WUFD_BBA (*(volatile unsigned long *) 0x4204A50C)
2056#define T2IEN_WUFD_MSK (0x1 << 3 )
2057#define T2IEN_WUFD (0x1 << 3 )
2058#define T2IEN_WUFD_DIS (0x0 << 3 ) /* DIS */
2059#define T2IEN_WUFD_EN (0x1 << 3 ) /* EN */
2060
2061/* T2IEN[WUFC] - Enable interrupt on WUFC */
2062#define T2IEN_WUFC_BBA (*(volatile unsigned long *) 0x4204A508)
2063#define T2IEN_WUFC_MSK (0x1 << 2 )
2064#define T2IEN_WUFC (0x1 << 2 )
2065#define T2IEN_WUFC_DIS (0x0 << 2 ) /* DIS */
2066#define T2IEN_WUFC_EN (0x1 << 2 ) /* EN */
2067
2068/* T2IEN[WUFB] - Enable interrupt on WUFB */
2069#define T2IEN_WUFB_BBA (*(volatile unsigned long *) 0x4204A504)
2070#define T2IEN_WUFB_MSK (0x1 << 1 )
2071#define T2IEN_WUFB (0x1 << 1 )
2072#define T2IEN_WUFB_DIS (0x0 << 1 ) /* DIS */
2073#define T2IEN_WUFB_EN (0x1 << 1 ) /* EN */
2074
2075/* T2IEN[WUFA] - Enable interrupt on WUFA */
2076#define T2IEN_WUFA_BBA (*(volatile unsigned long *) 0x4204A500)
2077#define T2IEN_WUFA_MSK (0x1 << 0 )
2078#define T2IEN_WUFA (0x1 << 0 )
2079#define T2IEN_WUFA_DIS (0x0 << 0 ) /* DIS */
2080#define T2IEN_WUFA_EN (0x1 << 0 ) /* EN */
2081
2082/* Reset Value for T2STA*/
2083#define T2STA_RVAL 0x0
2084
2085/* T2STA[CON] - Sync */
2086#define T2STA_CON_BBA (*(volatile unsigned long *) 0x4204A5A0)
2087#define T2STA_CON_MSK (0x1 << 8 )
2088#define T2STA_CON (0x1 << 8 )
2089#define T2STA_CON_CLR (0x0 << 8 ) /* CLR */
2090#define T2STA_CON_SET (0x1 << 8 ) /* SET */
2091
2092/* T2STA[FREEZE] - Timer Value Freeze */
2093#define T2STA_FREEZE_BBA (*(volatile unsigned long *) 0x4204A59C)
2094#define T2STA_FREEZE_MSK (0x1 << 7 )
2095#define T2STA_FREEZE (0x1 << 7 )
2096#define T2STA_FREEZE_CLR (0x0 << 7 ) /* CLR */
2097#define T2STA_FREEZE_SET (0x1 << 7 ) /* SET */
2098
2099/* T2STA[ROLL] - Rollover Interrupt */
2100#define T2STA_ROLL_BBA (*(volatile unsigned long *) 0x4204A590)
2101#define T2STA_ROLL_MSK (0x1 << 4 )
2102#define T2STA_ROLL (0x1 << 4 )
2103#define T2STA_ROLL_CLR (0x0 << 4 ) /* CLR */
2104#define T2STA_ROLL_SET (0x1 << 4 ) /* SET */
2105
2106/* T2STA[WUFD] - WUFD Interrupt */
2107#define T2STA_WUFD_BBA (*(volatile unsigned long *) 0x4204A58C)
2108#define T2STA_WUFD_MSK (0x1 << 3 )
2109#define T2STA_WUFD (0x1 << 3 )
2110#define T2STA_WUFD_CLR (0x0 << 3 ) /* CLR */
2111#define T2STA_WUFD_SET (0x1 << 3 ) /* SET */
2112
2113/* T2STA[WUFC] - WUFC Interrupt */
2114#define T2STA_WUFC_BBA (*(volatile unsigned long *) 0x4204A588)
2115#define T2STA_WUFC_MSK (0x1 << 2 )
2116#define T2STA_WUFC (0x1 << 2 )
2117#define T2STA_WUFC_CLR (0x0 << 2 ) /* CLR */
2118#define T2STA_WUFC_SET (0x1 << 2 ) /* SET */
2119
2120/* T2STA[WUFB] - WUFB Interrupt */
2121#define T2STA_WUFB_BBA (*(volatile unsigned long *) 0x4204A584)
2122#define T2STA_WUFB_MSK (0x1 << 1 )
2123#define T2STA_WUFB (0x1 << 1 )
2124#define T2STA_WUFB_CLR (0x0 << 1 ) /* CLR */
2125#define T2STA_WUFB_SET (0x1 << 1 ) /* SET */
2126
2127/* T2STA[WUFA] - WUFA Interrupt */
2128#define T2STA_WUFA_BBA (*(volatile unsigned long *) 0x4204A580)
2129#define T2STA_WUFA_MSK (0x1 << 0 )
2130#define T2STA_WUFA (0x1 << 0 )
2131#define T2STA_WUFA_CLR (0x0 << 0 ) /* CLR */
2132#define T2STA_WUFA_SET (0x1 << 0 ) /* SET */
2133
2134/* Reset Value for T2CLRI*/
2135#define T2CLRI_RVAL 0x0
2136
2137/* T2CLRI[ROLL] - Clear interrupt on Rollover */
2138#define T2CLRI_ROLL_BBA (*(volatile unsigned long *) 0x4204A610)
2139#define T2CLRI_ROLL_MSK (0x1 << 4 )
2140#define T2CLRI_ROLL (0x1 << 4 )
2141#define T2CLRI_ROLL_CLR (0x1 << 4 ) /* CLR */
2142
2143/* T2CLRI[WUFD] - Clear interrupt on WUFD */
2144#define T2CLRI_WUFD_BBA (*(volatile unsigned long *) 0x4204A60C)
2145#define T2CLRI_WUFD_MSK (0x1 << 3 )
2146#define T2CLRI_WUFD (0x1 << 3 )
2147#define T2CLRI_WUFD_CLR (0x1 << 3 ) /* CLR */
2148
2149/* T2CLRI[WUFC] - Clear interrupt on WUFC */
2150#define T2CLRI_WUFC_BBA (*(volatile unsigned long *) 0x4204A608)
2151#define T2CLRI_WUFC_MSK (0x1 << 2 )
2152#define T2CLRI_WUFC (0x1 << 2 )
2153#define T2CLRI_WUFC_CLR (0x1 << 2 ) /* CLR */
2154
2155/* T2CLRI[WUFB] - Clear interrupt on WUFB */
2156#define T2CLRI_WUFB_BBA (*(volatile unsigned long *) 0x4204A604)
2157#define T2CLRI_WUFB_MSK (0x1 << 1 )
2158#define T2CLRI_WUFB (0x1 << 1 )
2159#define T2CLRI_WUFB_CLR (0x1 << 1 ) /* CLR */
2160
2161/* T2CLRI[WUFA] - Clear interrupt on WUFA */
2162#define T2CLRI_WUFA_BBA (*(volatile unsigned long *) 0x4204A600)
2163#define T2CLRI_WUFA_MSK (0x1 << 0 )
2164#define T2CLRI_WUFA (0x1 << 0 )
2165#define T2CLRI_WUFA_CLR (0x1 << 0 ) /* CLR */
2166
2167/* Reset Value for T2WUFA0*/
2168#define T2WUFA0_RVAL 0x1900
2169
2170/* T2WUFA0[VALUE] - Current Value */
2171#define T2WUFA0_VALUE_MSK (0xFFFF << 0 )
2172
2173/* Reset Value for T2WUFA1*/
2174#define T2WUFA1_RVAL 0x0
2175
2176/* T2WUFA1[VALUE] - Current Value */
2177#define T2WUFA1_VALUE_MSK (0xFFFF << 0 )
2178// ------------------------------------------------------------------------------------------------
2179// ----- CLKCTL -----
2180// ------------------------------------------------------------------------------------------------
2181
2182
2183/**
2184 * @brief Clock Control (pADI_CLKCTL)
2185 */
2186
2187#if (__NO_MMR_STRUCTS__==0)
2188typedef struct { /*!< pADI_CLKCTL Structure */
2189 __IO uint16_t CLKCON0; /*!< System clocking architecture control register */
2190 __I uint16_t RESERVED0;
2191 __IO uint16_t CLKCON1; /*!< System Clocks Control Register 1 */
2192 __I uint16_t RESERVED1[19];
2193 __IO uint16_t CLKDIS; /*!< System Clocks Control Register 1 */
2194 __I uint16_t RESERVED2[497];
2195 __IO uint8_t XOSCCON; /*!< Crystal Oscillator control */
2196 __I uint8_t RESERVED3[51];
2197 __IO uint16_t CLKSYSDIV; /*!< Sys Clock div2 Register */
2198} ADI_CLKCTL_TypeDef;
2199#else // (__NO_MMR_STRUCTS__==0)
2200#define CLKCON0 (*(volatile unsigned short int *) 0x40002000)
2201#define CLKCON1 (*(volatile unsigned short int *) 0x40002004)
2202#define CLKDIS (*(volatile unsigned short int *) 0x4000202C)
2203#define XOSCCON (*(volatile unsigned char *) 0x40002410)
2204#define CLKSYSDIV (*(volatile unsigned short int *) 0x40002444)
2205#endif // (__NO_MMR_STRUCTS__==0)
2206
2207/* Reset Value for CLKCON0*/
2208#define CLKCON0_RVAL 0x0
2209
2210/* CLKCON0[CLKOUT] - GPIO output clock multiplexer select bits */
2211#define CLKCON0_CLKOUT_MSK (0x7 << 5 )
2212#define CLKCON0_CLKOUT_UCLKCG (0x0 << 5 ) /* UCLKCG */
2213#define CLKCON0_CLKOUT_UCLK (0x1 << 5 ) /* UCLK */
2214#define CLKCON0_CLKOUT_PCLK (0x2 << 5 ) /* PCLK */
2215#define CLKCON0_CLKOUT_HFOSC (0x5 << 5 ) /* HFOSC */
2216#define CLKCON0_CLKOUT_LFOSC (0x6 << 5 ) /* LFOSC */
2217#define CLKCON0_CLKOUT_LFXTAL (0x7 << 5 ) /* LFXTAL */
2218
2219/* CLKCON0[CLKMUX] - Digital subsystem clock source select bits. */
2220#define CLKCON0_CLKMUX_MSK (0x3 << 3 )
2221#define CLKCON0_CLKMUX_HFOSC (0x0 << 3 ) /* HFOSC */
2222#define CLKCON0_CLKMUX_LFXTAL (0x1 << 3 ) /* LFXTAL */
2223#define CLKCON0_CLKMUX_LFOSC (0x2 << 3 ) /* LFOSC */
2224#define CLKCON0_CLKMUX_EXTCLK (0x3 << 3 ) /* EXTCLK */
2225
2226/* CLKCON0[CD] - Clock divide bits */
2227#define CLKCON0_CD_MSK (0x7 << 0 )
2228#define CLKCON0_CD_DIV1 (0x0 << 0 ) /* DIV1 */
2229#define CLKCON0_CD_DIV2 (0x1 << 0 ) /* DIV2 */
2230#define CLKCON0_CD_DIV4 (0x2 << 0 ) /* DIV4 */
2231#define CLKCON0_CD_DIV8 (0x3 << 0 ) /* DIV8 */
2232#define CLKCON0_CD_DIV16 (0x4 << 0 ) /* DIV16 */
2233#define CLKCON0_CD_DIV32 (0x5 << 0 ) /* DIV32 */
2234#define CLKCON0_CD_DIV64 (0x6 << 0 ) /* DIV64 */
2235#define CLKCON0_CD_DIV128 (0x7 << 0 ) /* DIV128 */
2236
2237/* Reset Value for CLKCON1*/
2238#define CLKCON1_RVAL 0x0
2239
2240/* CLKCON1[PWMCD] - Clock divide bits for PWM system clock */
2241#define CLKCON1_PWMCD_MSK (0x7 << 12 )
2242#define CLKCON1_PWMCD_DIV1 (0x0 << 12 ) /* DIV1 */
2243#define CLKCON1_PWMCD_DIV2 (0x1 << 12 ) /* DIV2 */
2244#define CLKCON1_PWMCD_DIV4 (0x2 << 12 ) /* DIV4 */
2245#define CLKCON1_PWMCD_DIV8 (0x3 << 12 ) /* DIV8 */
2246#define CLKCON1_PWMCD_DIV16 (0x4 << 12 ) /* DIV16 */
2247#define CLKCON1_PWMCD_DIV32 (0x5 << 12 ) /* DIV32 */
2248#define CLKCON1_PWMCD_DIV64 (0x6 << 12 ) /* DIV64 */
2249#define CLKCON1_PWMCD_DIV128 (0x7 << 12 ) /* DIV128 */
2250
2251/* CLKCON1[UARTCD] - Clock divide bits for UART system clock */
2252#define CLKCON1_UARTCD_MSK (0x7 << 9 )
2253#define CLKCON1_UARTCD_DIV1 (0x0 << 9 ) /* DIV1 */
2254#define CLKCON1_UARTCD_DIV2 (0x1 << 9 ) /* DIV2 */
2255#define CLKCON1_UARTCD_DIV4 (0x2 << 9 ) /* DIV4 */
2256#define CLKCON1_UARTCD_DIV8 (0x3 << 9 ) /* DIV8 */
2257#define CLKCON1_UARTCD_DIV16 (0x4 << 9 ) /* DIV16 */
2258#define CLKCON1_UARTCD_DIV32 (0x5 << 9 ) /* DIV32 */
2259#define CLKCON1_UARTCD_DIV64 (0x6 << 9 ) /* DIV64 */
2260#define CLKCON1_UARTCD_DIV128 (0x7 << 9 ) /* DIV128 */
2261
2262/* CLKCON1[I2CCD] - Clock divide bits for I2C system clock */
2263#define CLKCON1_I2CCD_MSK (0x7 << 6 )
2264#define CLKCON1_I2CCD_DIV1 (0x0 << 6 ) /* DIV1 */
2265#define CLKCON1_I2CCD_DIV2 (0x1 << 6 ) /* DIV2 */
2266#define CLKCON1_I2CCD_DIV4 (0x2 << 6 ) /* DIV4 */
2267#define CLKCON1_I2CCD_DIV8 (0x3 << 6 ) /* DIV8 */
2268#define CLKCON1_I2CCD_DIV16 (0x4 << 6 ) /* DIV16 */
2269#define CLKCON1_I2CCD_DIV32 (0x5 << 6 ) /* DIV32 */
2270#define CLKCON1_I2CCD_DIV64 (0x6 << 6 ) /* DIV64 */
2271#define CLKCON1_I2CCD_DIV128 (0x7 << 6 ) /* DIV128 */
2272
2273/* CLKCON1[SPI1CD] - Clock divide bits for SPI1 system clock */
2274#define CLKCON1_SPI1CD_MSK (0x7 << 3 )
2275#define CLKCON1_SPI1CD_DIV1 (0x0 << 3 ) /* DIV1 */
2276#define CLKCON1_SPI1CD_DIV2 (0x1 << 3 ) /* DIV2 */
2277#define CLKCON1_SPI1CD_DIV4 (0x2 << 3 ) /* DIV4 */
2278#define CLKCON1_SPI1CD_DIV8 (0x3 << 3 ) /* DIV8 */
2279#define CLKCON1_SPI1CD_DIV16 (0x4 << 3 ) /* DIV16 */
2280#define CLKCON1_SPI1CD_DIV32 (0x5 << 3 ) /* DIV32 */
2281#define CLKCON1_SPI1CD_DIV64 (0x6 << 3 ) /* DIV64 */
2282#define CLKCON1_SPI1CD_DIV128 (0x7 << 3 ) /* DIV128 */
2283
2284/* CLKCON1[SPI0CD] - Clock divide bits for SPI0 system clock */
2285#define CLKCON1_SPI0CD_MSK (0x7 << 0 )
2286#define CLKCON1_SPI0CD_DIV1 (0x0 << 0 ) /* DIV1 */
2287#define CLKCON1_SPI0CD_DIV2 (0x1 << 0 ) /* DIV2 */
2288#define CLKCON1_SPI0CD_DIV4 (0x2 << 0 ) /* DIV4 */
2289#define CLKCON1_SPI0CD_DIV8 (0x3 << 0 ) /* DIV8 */
2290#define CLKCON1_SPI0CD_DIV16 (0x4 << 0 ) /* DIV16 */
2291#define CLKCON1_SPI0CD_DIV32 (0x5 << 0 ) /* DIV32 */
2292#define CLKCON1_SPI0CD_DIV64 (0x6 << 0 ) /* DIV64 */
2293#define CLKCON1_SPI0CD_DIV128 (0x7 << 0 ) /* DIV128 */
2294
2295/* Reset Value for CLKDIS*/
2296#define CLKDIS_RVAL 0xFFFF
2297
2298/* CLKDIS[DISADCCLK] - Disable ADC system clock */
2299#define CLKDIS_DISADCCLK_BBA (*(volatile unsigned long *) 0x420405A4)
2300#define CLKDIS_DISADCCLK_MSK (0x1 << 9 )
2301#define CLKDIS_DISADCCLK (0x1 << 9 )
2302#define CLKDIS_DISADCCLK_DIS (0x0 << 9 ) /* DIS */
2303#define CLKDIS_DISADCCLK_EN (0x1 << 9 ) /* EN */
2304
2305/* CLKDIS[DISDMACLK] - Disable DMA system clock */
2306#define CLKDIS_DISDMACLK_BBA (*(volatile unsigned long *) 0x420405A0)
2307#define CLKDIS_DISDMACLK_MSK (0x1 << 8 )
2308#define CLKDIS_DISDMACLK (0x1 << 8 )
2309#define CLKDIS_DISDMACLK_DIS (0x0 << 8 ) /* DIS */
2310#define CLKDIS_DISDMACLK_EN (0x1 << 8 ) /* EN */
2311
2312/* CLKDIS[DISDACCLK] - Disable DAC system clock */
2313#define CLKDIS_DISDACCLK_BBA (*(volatile unsigned long *) 0x4204059C)
2314#define CLKDIS_DISDACCLK_MSK (0x1 << 7 )
2315#define CLKDIS_DISDACCLK (0x1 << 7 )
2316#define CLKDIS_DISDACCLK_DIS (0x0 << 7 ) /* DIS */
2317#define CLKDIS_DISDACCLK_EN (0x1 << 7 ) /* EN */
2318
2319/* CLKDIS[DIST1CLK] - Disable Timer 1 system clock */
2320#define CLKDIS_DIST1CLK_BBA (*(volatile unsigned long *) 0x42040598)
2321#define CLKDIS_DIST1CLK_MSK (0x1 << 6 )
2322#define CLKDIS_DIST1CLK (0x1 << 6 )
2323#define CLKDIS_DIST1CLK_DIS (0x0 << 6 ) /* DIS */
2324#define CLKDIS_DIST1CLK_EN (0x1 << 6 ) /* EN */
2325
2326/* CLKDIS[DIST0CLK] - Disable Timer 0 system clock */
2327#define CLKDIS_DIST0CLK_BBA (*(volatile unsigned long *) 0x42040594)
2328#define CLKDIS_DIST0CLK_MSK (0x1 << 5 )
2329#define CLKDIS_DIST0CLK (0x1 << 5 )
2330#define CLKDIS_DIST0CLK_DIS (0x0 << 5 ) /* DIS */
2331#define CLKDIS_DIST0CLK_EN (0x1 << 5 ) /* EN */
2332
2333/* CLKDIS[DISPWMCLK] - Disable PWM system clock */
2334#define CLKDIS_DISPWMCLK_BBA (*(volatile unsigned long *) 0x42040590)
2335#define CLKDIS_DISPWMCLK_MSK (0x1 << 4 )
2336#define CLKDIS_DISPWMCLK (0x1 << 4 )
2337#define CLKDIS_DISPWMCLK_DIS (0x0 << 4 ) /* DIS */
2338#define CLKDIS_DISPWMCLK_EN (0x1 << 4 ) /* EN */
2339
2340/* CLKDIS[DISUARTCLK] - Disable UART system clock */
2341#define CLKDIS_DISUARTCLK_BBA (*(volatile unsigned long *) 0x4204058C)
2342#define CLKDIS_DISUARTCLK_MSK (0x1 << 3 )
2343#define CLKDIS_DISUARTCLK (0x1 << 3 )
2344#define CLKDIS_DISUARTCLK_DIS (0x0 << 3 ) /* DIS */
2345#define CLKDIS_DISUARTCLK_EN (0x1 << 3 ) /* EN */
2346
2347/* CLKDIS[DISI2CCLK] - Disable I2C system clock */
2348#define CLKDIS_DISI2CCLK_BBA (*(volatile unsigned long *) 0x42040588)
2349#define CLKDIS_DISI2CCLK_MSK (0x1 << 2 )
2350#define CLKDIS_DISI2CCLK (0x1 << 2 )
2351#define CLKDIS_DISI2CCLK_DIS (0x0 << 2 ) /* DIS */
2352#define CLKDIS_DISI2CCLK_EN (0x1 << 2 ) /* EN */
2353
2354/* CLKDIS[DISSPI1CLK] - Disable SPI1 system clock */
2355#define CLKDIS_DISSPI1CLK_BBA (*(volatile unsigned long *) 0x42040584)
2356#define CLKDIS_DISSPI1CLK_MSK (0x1 << 1 )
2357#define CLKDIS_DISSPI1CLK (0x1 << 1 )
2358#define CLKDIS_DISSPI1CLK_DIS (0x0 << 1 ) /* DIS */
2359#define CLKDIS_DISSPI1CLK_EN (0x1 << 1 ) /* EN */
2360
2361/* CLKDIS[DISSPI0CLK] - Disable SPI0 system clock bits */
2362#define CLKDIS_DISSPI0CLK_BBA (*(volatile unsigned long *) 0x42040580)
2363#define CLKDIS_DISSPI0CLK_MSK (0x1 << 0 )
2364#define CLKDIS_DISSPI0CLK (0x1 << 0 )
2365#define CLKDIS_DISSPI0CLK_DIS (0x0 << 0 ) /* DIS */
2366#define CLKDIS_DISSPI0CLK_EN (0x1 << 0 ) /* EN */
2367
2368/* Reset Value for XOSCCON*/
2369#define XOSCCON_RVAL 0x0
2370
2371/* XOSCCON[DIV2] - Divide by two enable */
2372#define XOSCCON_DIV2_BBA (*(volatile unsigned long *) 0x42048208)
2373#define XOSCCON_DIV2_MSK (0x1 << 2 )
2374#define XOSCCON_DIV2 (0x1 << 2 )
2375#define XOSCCON_DIV2_DIS (0x0 << 2 ) /* DIS */
2376#define XOSCCON_DIV2_EN (0x1 << 2 ) /* EN */
2377
2378/* XOSCCON[ENABLE] - Crystal oscillator circuit enable (Enable the oscillator circuitry.) */
2379#define XOSCCON_ENABLE_BBA (*(volatile unsigned long *) 0x42048200)
2380#define XOSCCON_ENABLE_MSK (0x1 << 0 )
2381#define XOSCCON_ENABLE (0x1 << 0 )
2382#define XOSCCON_ENABLE_DIS (0x0 << 0 ) /* DIS */
2383#define XOSCCON_ENABLE_EN (0x1 << 0 ) /* EN */
2384
2385/* Reset Value for CLKSYSDIV*/
2386#define CLKSYSDIV_RVAL 0x0
2387
2388/* CLKSYSDIV[DIV2EN] - bits */
2389#define CLKSYSDIV_DIV2EN_BBA (*(volatile unsigned long *) 0x42048880)
2390#define CLKSYSDIV_DIV2EN_MSK (0x1 << 0 )
2391#define CLKSYSDIV_DIV2EN (0x1 << 0 )
2392#define CLKSYSDIV_DIV2EN_DIS (0x0 << 0 ) /* DIS */
2393#define CLKSYSDIV_DIV2EN_EN (0x1 << 0 ) /* EN */
2394// ------------------------------------------------------------------------------------------------
2395// ----- FEE -----
2396// ------------------------------------------------------------------------------------------------
2397
2398
2399/**
2400 * @brief Flash Controller (pADI_FEE)
2401 */
2402
2403#if (__NO_MMR_STRUCTS__==0)
2404typedef struct { /*!< pADI_FEE Structure */
2405 __IO uint16_t FEESTA; /*!< Status Register */
2406 __I uint16_t RESERVED0;
2407 __IO uint16_t FEECON0; /*!< Command Control Register */
2408 __I uint16_t RESERVED1;
2409 __IO uint16_t FEECMD; /*!< Command register */
2410 __I uint16_t RESERVED2[3];
2411 __IO uint16_t FEEADR0L; /*!< Low Page (Lower 16 bits) */
2412 __I uint16_t RESERVED3;
2413 __IO uint16_t FEEADR0H; /*!< Low Page (Upper 16 bits) */
2414 __I uint16_t RESERVED4;
2415 __IO uint16_t FEEADR1L; /*!< Hi Page (Lower 16 bits) */
2416 __I uint16_t RESERVED5;
2417 __IO uint16_t FEEADR1H; /*!< Hi Page (Upper 16 bits) */
2418 __I uint16_t RESERVED6;
2419 __IO uint16_t FEEKEY; /*!< Key */
2420 __I uint16_t RESERVED7[3];
2421 __IO uint16_t FEEPROL; /*!< Write Protection (Lower 16 bits) */
2422 __I uint16_t RESERVED8;
2423 __IO uint16_t FEEPROH; /*!< Write Protection (Upper 16 bits) */
2424 __I uint16_t RESERVED9;
2425 __IO uint16_t FEESIGL; /*!< Signature (Lower 16 bits) */
2426 __I uint16_t RESERVED10;
2427 __IO uint16_t FEESIGH; /*!< Signature (Upper 16 bits) */
2428 __I uint16_t RESERVED11;
2429 __IO uint16_t FEECON1; /*!< User Setup register */
2430 __I uint16_t RESERVED12[7];
2431 __IO uint16_t FEEADRAL; /*!< Abort address (Lower 16 bits) */
2432 __I uint16_t RESERVED13;
2433 __IO uint16_t FEEADRAH; /*!< Abort address (Upper 16 bits) */
2434 __I uint16_t RESERVED14[21];
2435 __IO uint16_t FEEAEN0; /*!< Lower 16 bits of the sys irq abort enable register. */
2436 __I uint16_t RESERVED15;
2437 __IO uint16_t FEEAEN1; /*!< Upper 16 bits of the sys irq abort enable register. */
2438 __I uint16_t RESERVED16;
2439 __IO uint16_t FEEAEN2; /*!< Upper 32..47 bits of the sys irq abort enable register. */
2440} ADI_FEE_TypeDef;
2441#else // (__NO_MMR_STRUCTS__==0)
2442#define FEESTA (*(volatile unsigned short int *) 0x40002800)
2443#define FEECON0 (*(volatile unsigned short int *) 0x40002804)
2444#define FEECMD (*(volatile unsigned short int *) 0x40002808)
2445#define FEEADR0L (*(volatile unsigned short int *) 0x40002810)
2446#define FEEADR0H (*(volatile unsigned short int *) 0x40002814)
2447#define FEEADR1L (*(volatile unsigned short int *) 0x40002818)
2448#define FEEADR1H (*(volatile unsigned short int *) 0x4000281C)
2449#define FEEKEY (*(volatile unsigned short int *) 0x40002820)
2450#define FEEPROL (*(volatile unsigned short int *) 0x40002828)
2451#define FEEPROH (*(volatile unsigned short int *) 0x4000282C)
2452#define FEESIGL (*(volatile unsigned short int *) 0x40002830)
2453#define FEESIGH (*(volatile unsigned short int *) 0x40002834)
2454#define FEECON1 (*(volatile unsigned short int *) 0x40002838)
2455#define FEEADRAL (*(volatile unsigned short int *) 0x40002848)
2456#define FEEADRAH (*(volatile unsigned short int *) 0x4000284C)
2457#define FEEAEN0 (*(volatile unsigned short int *) 0x40002878)
2458#define FEEAEN1 (*(volatile unsigned short int *) 0x4000287C)
2459#define FEEAEN2 (*(volatile unsigned short int *) 0x40002880)
2460#endif // (__NO_MMR_STRUCTS__==0)
2461
2462/* Reset Value for FEESTA*/
2463#define FEESTA_RVAL 0x0
2464
2465/* FEESTA[SIGNERR] - Info space signature check on reset error */
2466#define FEESTA_SIGNERR_BBA (*(volatile unsigned long *) 0x42050018)
2467#define FEESTA_SIGNERR_MSK (0x1 << 6 )
2468#define FEESTA_SIGNERR (0x1 << 6 )
2469#define FEESTA_SIGNERR_CLR (0x0 << 6 ) /* CLR */
2470#define FEESTA_SIGNERR_SET (0x1 << 6 ) /* SET */
2471
2472/* FEESTA[CMDRES] - Command result */
2473#define FEESTA_CMDRES_MSK (0x3 << 4 )
2474#define FEESTA_CMDRES_SUCCESS (0x0 << 4 ) /* SUCCESS */
2475#define FEESTA_CMDRES_PROTECTED (0x1 << 4 ) /* PROTECTED */
2476#define FEESTA_CMDRES_VERIFYERR (0x2 << 4 ) /* VERIFYERR */
2477#define FEESTA_CMDRES_ABORT (0x3 << 4 ) /* ABORT */
2478
2479/* FEESTA[WRDONE] - Write Complete */
2480#define FEESTA_WRDONE_BBA (*(volatile unsigned long *) 0x4205000C)
2481#define FEESTA_WRDONE_MSK (0x1 << 3 )
2482#define FEESTA_WRDONE (0x1 << 3 )
2483#define FEESTA_WRDONE_CLR (0x0 << 3 ) /* CLR */
2484#define FEESTA_WRDONE_SET (0x1 << 3 ) /* SET */
2485
2486/* FEESTA[CMDDONE] - Command complete */
2487#define FEESTA_CMDDONE_BBA (*(volatile unsigned long *) 0x42050008)
2488#define FEESTA_CMDDONE_MSK (0x1 << 2 )
2489#define FEESTA_CMDDONE (0x1 << 2 )
2490#define FEESTA_CMDDONE_CLR (0x0 << 2 ) /* CLR */
2491#define FEESTA_CMDDONE_SET (0x1 << 2 ) /* SET */
2492
2493/* FEESTA[WRBUSY] - Write busy */
2494#define FEESTA_WRBUSY_BBA (*(volatile unsigned long *) 0x42050004)
2495#define FEESTA_WRBUSY_MSK (0x1 << 1 )
2496#define FEESTA_WRBUSY (0x1 << 1 )
2497#define FEESTA_WRBUSY_CLR (0x0 << 1 ) /* CLR */
2498#define FEESTA_WRBUSY_SET (0x1 << 1 ) /* SET */
2499
2500/* FEESTA[CMDBUSY] - Command busy */
2501#define FEESTA_CMDBUSY_BBA (*(volatile unsigned long *) 0x42050000)
2502#define FEESTA_CMDBUSY_MSK (0x1 << 0 )
2503#define FEESTA_CMDBUSY (0x1 << 0 )
2504#define FEESTA_CMDBUSY_CLR (0x0 << 0 ) /* CLR */
2505#define FEESTA_CMDBUSY_SET (0x1 << 0 ) /* SET */
2506
2507/* Reset Value for FEECON0*/
2508#define FEECON0_RVAL 0x0
2509
2510/* FEECON0[WREN] - Write enable. */
2511#define FEECON0_WREN_BBA (*(volatile unsigned long *) 0x42050088)
2512#define FEECON0_WREN_MSK (0x1 << 2 )
2513#define FEECON0_WREN (0x1 << 2 )
2514#define FEECON0_WREN_DIS (0x0 << 2 ) /* DIS */
2515#define FEECON0_WREN_EN (0x1 << 2 ) /* EN */
2516
2517/* FEECON0[IENERR] - Error interrupt enable */
2518#define FEECON0_IENERR_BBA (*(volatile unsigned long *) 0x42050084)
2519#define FEECON0_IENERR_MSK (0x1 << 1 )
2520#define FEECON0_IENERR (0x1 << 1 )
2521#define FEECON0_IENERR_DIS (0x0 << 1 ) /* DIS */
2522#define FEECON0_IENERR_EN (0x1 << 1 ) /* EN */
2523
2524/* FEECON0[IENCMD] - Command complete interrupt enable */
2525#define FEECON0_IENCMD_BBA (*(volatile unsigned long *) 0x42050080)
2526#define FEECON0_IENCMD_MSK (0x1 << 0 )
2527#define FEECON0_IENCMD (0x1 << 0 )
2528#define FEECON0_IENCMD_DIS (0x0 << 0 ) /* DIS */
2529#define FEECON0_IENCMD_EN (0x1 << 0 ) /* EN */
2530
2531/* Reset Value for FEECMD*/
2532#define FEECMD_RVAL 0x0
2533
2534/* FEECMD[CMD] - Command */
2535#define FEECMD_CMD_MSK (0xF << 0 )
2536#define FEECMD_CMD_IDLE (0x0 << 0 ) /* IDLE - No command executed */
2537#define FEECMD_CMD_ERASEPAGE (0x1 << 0 ) /* ERASEPAGE - Erase Page */
2538#define FEECMD_CMD_SIGN (0x2 << 0 ) /* SIGN - Sign Range */
2539#define FEECMD_CMD_MASSERASE (0x3 << 0 ) /* MASSERASE - Mass Erase User Space */
2540#define FEECMD_CMD_ABORT (0x4 << 0 ) /* ABORT - Abort a running command */
2541
2542/* Reset Value for FEEADR0L*/
2543#define FEEADR0L_RVAL 0x0
2544
2545/* FEEADR0L[VALUE] - Value */
2546#define FEEADR0L_VALUE_MSK (0xFFFF << 0 )
2547
2548/* Reset Value for FEEADR0H*/
2549#define FEEADR0H_RVAL 0x0
2550
2551/* FEEADR0H[VALUE] - Value */
2552#define FEEADR0H_VALUE_MSK (0x3 << 0 )
2553
2554/* Reset Value for FEEADR1L*/
2555#define FEEADR1L_RVAL 0x0
2556
2557/* FEEADR1L[VALUE] - Value */
2558#define FEEADR1L_VALUE_MSK (0xFFFF << 0 )
2559
2560/* Reset Value for FEEADR1H*/
2561#define FEEADR1H_RVAL 0x0
2562
2563/* FEEADR1H[VALUE] - Value */
2564#define FEEADR1H_VALUE_MSK (0x3 << 0 )
2565
2566/* Reset Value for FEEKEY*/
2567#define FEEKEY_RVAL 0x0
2568
2569/* FEEKEY[VALUE] - Value */
2570#define FEEKEY_VALUE_MSK (0xFFFF << 0 )
2571#define FEEKEY_VALUE_USERKEY1 (0xF456 << 0 ) /* USERKEY1 */
2572#define FEEKEY_VALUE_USERKEY2 (0xF123 << 0 ) /* USERKEY2 */
2573
2574/* Reset Value for FEEPROL*/
2575#define FEEPROL_RVAL 0xFFFF
2576
2577/* FEEPROL[VALUE] - Value */
2578#define FEEPROL_VALUE_MSK (0xFFFF << 0 )
2579
2580/* Reset Value for FEEPROH*/
2581#define FEEPROH_RVAL 0xFFFF
2582
2583/* FEEPROH[VALUE] - Value */
2584#define FEEPROH_VALUE_MSK (0xFFFF << 0 )
2585
2586/* Reset Value for FEESIGL*/
2587#define FEESIGL_RVAL 0xFFFF
2588
2589/* FEESIGL[VALUE] - Value */
2590#define FEESIGL_VALUE_MSK (0xFFFF << 0 )
2591
2592/* Reset Value for FEESIGH*/
2593#define FEESIGH_RVAL 0xFFFF
2594
2595/* FEESIGH[VALUE] - Value */
2596#define FEESIGH_VALUE_MSK (0xFF << 0 )
2597
2598/* Reset Value for FEECON1*/
2599#define FEECON1_RVAL 0x1
2600
2601/* FEECON1[DBG] - Serial Wire debug enable , */
2602#define FEECON1_DBG_BBA (*(volatile unsigned long *) 0x42050700)
2603#define FEECON1_DBG_MSK (0x1 << 0 )
2604#define FEECON1_DBG (0x1 << 0 )
2605#define FEECON1_DBG_DIS (0x0 << 0 ) /* DIS */
2606#define FEECON1_DBG_EN (0x1 << 0 ) /* EN */
2607
2608/* Reset Value for FEEADRAL*/
2609#define FEEADRAL_RVAL 0x800
2610
2611/* FEEADRAL[VALUE] - Value */
2612#define FEEADRAL_VALUE_MSK (0xFFFF << 0 )
2613
2614/* Reset Value for FEEADRAH*/
2615#define FEEADRAH_RVAL 0x2
2616
2617/* FEEADRAH[VALUE] - Value */
2618#define FEEADRAH_VALUE_MSK (0xFFFF << 0 )
2619
2620/* Reset Value for FEEAEN0*/
2621#define FEEAEN0_RVAL 0x0
2622
2623/* FEEAEN0[SINC2] - */
2624#define FEEAEN0_SINC2_BBA (*(volatile unsigned long *) 0x42050F3C)
2625#define FEEAEN0_SINC2_MSK (0x1 << 15 )
2626#define FEEAEN0_SINC2 (0x1 << 15 )
2627#define FEEAEN0_SINC2_DIS (0x0 << 15 ) /* DIS */
2628#define FEEAEN0_SINC2_EN (0x1 << 15 ) /* EN */
2629
2630/* FEEAEN0[ADC1] - */
2631#define FEEAEN0_ADC1_BBA (*(volatile unsigned long *) 0x42050F38)
2632#define FEEAEN0_ADC1_MSK (0x1 << 14 )
2633#define FEEAEN0_ADC1 (0x1 << 14 )
2634#define FEEAEN0_ADC1_DIS (0x0 << 14 ) /* DIS */
2635#define FEEAEN0_ADC1_EN (0x1 << 14 ) /* EN */
2636
2637/* FEEAEN0[ADC0] - */
2638#define FEEAEN0_ADC0_BBA (*(volatile unsigned long *) 0x42050F34)
2639#define FEEAEN0_ADC0_MSK (0x1 << 13 )
2640#define FEEAEN0_ADC0 (0x1 << 13 )
2641#define FEEAEN0_ADC0_DIS (0x0 << 13 ) /* DIS */
2642#define FEEAEN0_ADC0_EN (0x1 << 13 ) /* EN */
2643
2644/* FEEAEN0[T1] - */
2645#define FEEAEN0_T1_BBA (*(volatile unsigned long *) 0x42050F30)
2646#define FEEAEN0_T1_MSK (0x1 << 12 )
2647#define FEEAEN0_T1 (0x1 << 12 )
2648#define FEEAEN0_T1_DIS (0x0 << 12 ) /* DIS */
2649#define FEEAEN0_T1_EN (0x1 << 12 ) /* EN */
2650
2651/* FEEAEN0[T0] - */
2652#define FEEAEN0_T0_BBA (*(volatile unsigned long *) 0x42050F2C)
2653#define FEEAEN0_T0_MSK (0x1 << 11 )
2654#define FEEAEN0_T0 (0x1 << 11 )
2655#define FEEAEN0_T0_DIS (0x0 << 11 ) /* DIS */
2656#define FEEAEN0_T0_EN (0x1 << 11 ) /* EN */
2657
2658/* FEEAEN0[T3] - */
2659#define FEEAEN0_T3_BBA (*(volatile unsigned long *) 0x42050F24)
2660#define FEEAEN0_T3_MSK (0x1 << 9 )
2661#define FEEAEN0_T3 (0x1 << 9 )
2662#define FEEAEN0_T3_DIS (0x0 << 9 ) /* DIS */
2663#define FEEAEN0_T3_EN (0x1 << 9 ) /* EN */
2664
2665/* FEEAEN0[EXTINT7] - */
2666#define FEEAEN0_EXTINT7_BBA (*(volatile unsigned long *) 0x42050F20)
2667#define FEEAEN0_EXTINT7_MSK (0x1 << 8 )
2668#define FEEAEN0_EXTINT7 (0x1 << 8 )
2669#define FEEAEN0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
2670#define FEEAEN0_EXTINT7_EN (0x1 << 8 ) /* EN */
2671
2672/* FEEAEN0[EXTINT6] - */
2673#define FEEAEN0_EXTINT6_BBA (*(volatile unsigned long *) 0x42050F1C)
2674#define FEEAEN0_EXTINT6_MSK (0x1 << 7 )
2675#define FEEAEN0_EXTINT6 (0x1 << 7 )
2676#define FEEAEN0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
2677#define FEEAEN0_EXTINT6_EN (0x1 << 7 ) /* EN */
2678
2679/* FEEAEN0[EXTINT5] - */
2680#define FEEAEN0_EXTINT5_BBA (*(volatile unsigned long *) 0x42050F18)
2681#define FEEAEN0_EXTINT5_MSK (0x1 << 6 )
2682#define FEEAEN0_EXTINT5 (0x1 << 6 )
2683#define FEEAEN0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
2684#define FEEAEN0_EXTINT5_EN (0x1 << 6 ) /* EN */
2685
2686/* FEEAEN0[EXTINT4] - */
2687#define FEEAEN0_EXTINT4_BBA (*(volatile unsigned long *) 0x42050F14)
2688#define FEEAEN0_EXTINT4_MSK (0x1 << 5 )
2689#define FEEAEN0_EXTINT4 (0x1 << 5 )
2690#define FEEAEN0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
2691#define FEEAEN0_EXTINT4_EN (0x1 << 5 ) /* EN */
2692
2693/* FEEAEN0[EXTINT3] - */
2694#define FEEAEN0_EXTINT3_BBA (*(volatile unsigned long *) 0x42050F10)
2695#define FEEAEN0_EXTINT3_MSK (0x1 << 4 )
2696#define FEEAEN0_EXTINT3 (0x1 << 4 )
2697#define FEEAEN0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
2698#define FEEAEN0_EXTINT3_EN (0x1 << 4 ) /* EN */
2699
2700/* FEEAEN0[EXTINT2] - */
2701#define FEEAEN0_EXTINT2_BBA (*(volatile unsigned long *) 0x42050F0C)
2702#define FEEAEN0_EXTINT2_MSK (0x1 << 3 )
2703#define FEEAEN0_EXTINT2 (0x1 << 3 )
2704#define FEEAEN0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
2705#define FEEAEN0_EXTINT2_EN (0x1 << 3 ) /* EN */
2706
2707/* FEEAEN0[EXTINT1] - */
2708#define FEEAEN0_EXTINT1_BBA (*(volatile unsigned long *) 0x42050F08)
2709#define FEEAEN0_EXTINT1_MSK (0x1 << 2 )
2710#define FEEAEN0_EXTINT1 (0x1 << 2 )
2711#define FEEAEN0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
2712#define FEEAEN0_EXTINT1_EN (0x1 << 2 ) /* EN */
2713
2714/* FEEAEN0[EXTINT0] - */
2715#define FEEAEN0_EXTINT0_BBA (*(volatile unsigned long *) 0x42050F04)
2716#define FEEAEN0_EXTINT0_MSK (0x1 << 1 )
2717#define FEEAEN0_EXTINT0 (0x1 << 1 )
2718#define FEEAEN0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
2719#define FEEAEN0_EXTINT0_EN (0x1 << 1 ) /* EN */
2720
2721/* FEEAEN0[T2] - */
2722#define FEEAEN0_T2_BBA (*(volatile unsigned long *) 0x42050F00)
2723#define FEEAEN0_T2_MSK (0x1 << 0 )
2724#define FEEAEN0_T2 (0x1 << 0 )
2725#define FEEAEN0_T2_DIS (0x0 << 0 ) /* DIS */
2726#define FEEAEN0_T2_EN (0x1 << 0 ) /* EN */
2727
2728/* Reset Value for FEEAEN1*/
2729#define FEEAEN1_RVAL 0x0
2730
2731/* FEEAEN1[DMADAC] - */
2732#define FEEAEN1_DMADAC_BBA (*(volatile unsigned long *) 0x42050FBC)
2733#define FEEAEN1_DMADAC_MSK (0x1 << 15 )
2734#define FEEAEN1_DMADAC (0x1 << 15 )
2735#define FEEAEN1_DMADAC_DIS (0x0 << 15 ) /* DIS */
2736#define FEEAEN1_DMADAC_EN (0x1 << 15 ) /* EN */
2737
2738/* FEEAEN1[DMAI2CMRX] - */
2739#define FEEAEN1_DMAI2CMRX_BBA (*(volatile unsigned long *) 0x42050FB8)
2740#define FEEAEN1_DMAI2CMRX_MSK (0x1 << 14 )
2741#define FEEAEN1_DMAI2CMRX (0x1 << 14 )
2742#define FEEAEN1_DMAI2CMRX_DIS (0x0 << 14 ) /* DIS */
2743#define FEEAEN1_DMAI2CMRX_EN (0x1 << 14 ) /* EN */
2744
2745/* FEEAEN1[DMAI2CMTX] - */
2746#define FEEAEN1_DMAI2CMTX_BBA (*(volatile unsigned long *) 0x42050FB4)
2747#define FEEAEN1_DMAI2CMTX_MSK (0x1 << 13 )
2748#define FEEAEN1_DMAI2CMTX (0x1 << 13 )
2749#define FEEAEN1_DMAI2CMTX_DIS (0x0 << 13 ) /* DIS */
2750#define FEEAEN1_DMAI2CMTX_EN (0x1 << 13 ) /* EN */
2751
2752/* FEEAEN1[DMAI2CSRX] - */
2753#define FEEAEN1_DMAI2CSRX_BBA (*(volatile unsigned long *) 0x42050FB0)
2754#define FEEAEN1_DMAI2CSRX_MSK (0x1 << 12 )
2755#define FEEAEN1_DMAI2CSRX (0x1 << 12 )
2756#define FEEAEN1_DMAI2CSRX_DIS (0x0 << 12 ) /* DIS */
2757#define FEEAEN1_DMAI2CSRX_EN (0x1 << 12 ) /* EN */
2758
2759/* FEEAEN1[DMAI2CSTX] - */
2760#define FEEAEN1_DMAI2CSTX_BBA (*(volatile unsigned long *) 0x42050FAC)
2761#define FEEAEN1_DMAI2CSTX_MSK (0x1 << 11 )
2762#define FEEAEN1_DMAI2CSTX (0x1 << 11 )
2763#define FEEAEN1_DMAI2CSTX_DIS (0x0 << 11 ) /* DIS */
2764#define FEEAEN1_DMAI2CSTX_EN (0x1 << 11 ) /* EN */
2765
2766/* FEEAEN1[DMAUARTRX] - */
2767#define FEEAEN1_DMAUARTRX_BBA (*(volatile unsigned long *) 0x42050FA8)
2768#define FEEAEN1_DMAUARTRX_MSK (0x1 << 10 )
2769#define FEEAEN1_DMAUARTRX (0x1 << 10 )
2770#define FEEAEN1_DMAUARTRX_DIS (0x0 << 10 ) /* DIS */
2771#define FEEAEN1_DMAUARTRX_EN (0x1 << 10 ) /* EN */
2772
2773/* FEEAEN1[DMAUARTTX] - */
2774#define FEEAEN1_DMAUARTTX_BBA (*(volatile unsigned long *) 0x42050FA4)
2775#define FEEAEN1_DMAUARTTX_MSK (0x1 << 9 )
2776#define FEEAEN1_DMAUARTTX (0x1 << 9 )
2777#define FEEAEN1_DMAUARTTX_DIS (0x0 << 9 ) /* DIS */
2778#define FEEAEN1_DMAUARTTX_EN (0x1 << 9 ) /* EN */
2779
2780/* FEEAEN1[DMASPI1RX] - */
2781#define FEEAEN1_DMASPI1RX_BBA (*(volatile unsigned long *) 0x42050FA0)
2782#define FEEAEN1_DMASPI1RX_MSK (0x1 << 8 )
2783#define FEEAEN1_DMASPI1RX (0x1 << 8 )
2784#define FEEAEN1_DMASPI1RX_DIS (0x0 << 8 ) /* DIS */
2785#define FEEAEN1_DMASPI1RX_EN (0x1 << 8 ) /* EN */
2786
2787/* FEEAEN1[DMASPI1TX] - */
2788#define FEEAEN1_DMASPI1TX_BBA (*(volatile unsigned long *) 0x42050F9C)
2789#define FEEAEN1_DMASPI1TX_MSK (0x1 << 7 )
2790#define FEEAEN1_DMASPI1TX (0x1 << 7 )
2791#define FEEAEN1_DMASPI1TX_DIS (0x0 << 7 ) /* DIS */
2792#define FEEAEN1_DMASPI1TX_EN (0x1 << 7 ) /* EN */
2793
2794/* FEEAEN1[DMAERROR] - */
2795#define FEEAEN1_DMAERROR_BBA (*(volatile unsigned long *) 0x42050F98)
2796#define FEEAEN1_DMAERROR_MSK (0x1 << 6 )
2797#define FEEAEN1_DMAERROR (0x1 << 6 )
2798#define FEEAEN1_DMAERROR_DIS (0x0 << 6 ) /* DIS */
2799#define FEEAEN1_DMAERROR_EN (0x1 << 6 ) /* EN */
2800
2801/* FEEAEN1[I2CM] - */
2802#define FEEAEN1_I2CM_BBA (*(volatile unsigned long *) 0x42050F94)
2803#define FEEAEN1_I2CM_MSK (0x1 << 5 )
2804#define FEEAEN1_I2CM (0x1 << 5 )
2805#define FEEAEN1_I2CM_DIS (0x0 << 5 ) /* DIS */
2806#define FEEAEN1_I2CM_EN (0x1 << 5 ) /* EN */
2807
2808/* FEEAEN1[I2CS] - */
2809#define FEEAEN1_I2CS_BBA (*(volatile unsigned long *) 0x42050F90)
2810#define FEEAEN1_I2CS_MSK (0x1 << 4 )
2811#define FEEAEN1_I2CS (0x1 << 4 )
2812#define FEEAEN1_I2CS_DIS (0x0 << 4 ) /* DIS */
2813#define FEEAEN1_I2CS_EN (0x1 << 4 ) /* EN */
2814
2815/* FEEAEN1[SPI1] - */
2816#define FEEAEN1_SPI1_BBA (*(volatile unsigned long *) 0x42050F8C)
2817#define FEEAEN1_SPI1_MSK (0x1 << 3 )
2818#define FEEAEN1_SPI1 (0x1 << 3 )
2819#define FEEAEN1_SPI1_DIS (0x0 << 3 ) /* DIS */
2820#define FEEAEN1_SPI1_EN (0x1 << 3 ) /* EN */
2821
2822/* FEEAEN1[SPI0] - */
2823#define FEEAEN1_SPI0_BBA (*(volatile unsigned long *) 0x42050F88)
2824#define FEEAEN1_SPI0_MSK (0x1 << 2 )
2825#define FEEAEN1_SPI0 (0x1 << 2 )
2826#define FEEAEN1_SPI0_DIS (0x0 << 2 ) /* DIS */
2827#define FEEAEN1_SPI0_EN (0x1 << 2 ) /* EN */
2828
2829/* FEEAEN1[UART] - */
2830#define FEEAEN1_UART_BBA (*(volatile unsigned long *) 0x42050F84)
2831#define FEEAEN1_UART_MSK (0x1 << 1 )
2832#define FEEAEN1_UART (0x1 << 1 )
2833#define FEEAEN1_UART_DIS (0x0 << 1 ) /* DIS */
2834#define FEEAEN1_UART_EN (0x1 << 1 ) /* EN */
2835
2836/* FEEAEN1[FEE] - */
2837#define FEEAEN1_FEE_BBA (*(volatile unsigned long *) 0x42050F80)
2838#define FEEAEN1_FEE_MSK (0x1 << 0 )
2839#define FEEAEN1_FEE (0x1 << 0 )
2840#define FEEAEN1_FEE_DIS (0x0 << 0 ) /* DIS */
2841#define FEEAEN1_FEE_EN (0x1 << 0 ) /* EN */
2842
2843/* Reset Value for FEEAEN2*/
2844#define FEEAEN2_RVAL 0x0
2845
2846/* FEEAEN2[PWM2] - */
2847#define FEEAEN2_PWM2_BBA (*(volatile unsigned long *) 0x42051018)
2848#define FEEAEN2_PWM2_MSK (0x1 << 6 )
2849#define FEEAEN2_PWM2 (0x1 << 6 )
2850#define FEEAEN2_PWM2_DIS (0x0 << 6 ) /* DIS */
2851#define FEEAEN2_PWM2_EN (0x1 << 6 ) /* EN */
2852
2853/* FEEAEN2[PWM1] - */
2854#define FEEAEN2_PWM1_BBA (*(volatile unsigned long *) 0x42051014)
2855#define FEEAEN2_PWM1_MSK (0x1 << 5 )
2856#define FEEAEN2_PWM1 (0x1 << 5 )
2857#define FEEAEN2_PWM1_DIS (0x0 << 5 ) /* DIS */
2858#define FEEAEN2_PWM1_EN (0x1 << 5 ) /* EN */
2859
2860/* FEEAEN2[PWM0] - */
2861#define FEEAEN2_PWM0_BBA (*(volatile unsigned long *) 0x42051010)
2862#define FEEAEN2_PWM0_MSK (0x1 << 4 )
2863#define FEEAEN2_PWM0 (0x1 << 4 )
2864#define FEEAEN2_PWM0_DIS (0x0 << 4 ) /* DIS */
2865#define FEEAEN2_PWM0_EN (0x1 << 4 ) /* EN */
2866
2867/* FEEAEN2[PWMTRIP] - */
2868#define FEEAEN2_PWMTRIP_BBA (*(volatile unsigned long *) 0x4205100C)
2869#define FEEAEN2_PWMTRIP_MSK (0x1 << 3 )
2870#define FEEAEN2_PWMTRIP (0x1 << 3 )
2871#define FEEAEN2_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
2872#define FEEAEN2_PWMTRIP_EN (0x1 << 3 ) /* EN */
2873
2874/* FEEAEN2[DMASINC2] - */
2875#define FEEAEN2_DMASINC2_BBA (*(volatile unsigned long *) 0x42051008)
2876#define FEEAEN2_DMASINC2_MSK (0x1 << 2 )
2877#define FEEAEN2_DMASINC2 (0x1 << 2 )
2878#define FEEAEN2_DMASINC2_DIS (0x0 << 2 ) /* DIS */
2879#define FEEAEN2_DMASINC2_EN (0x1 << 2 ) /* EN */
2880
2881/* FEEAEN2[DMAADC1] - */
2882#define FEEAEN2_DMAADC1_BBA (*(volatile unsigned long *) 0x42051004)
2883#define FEEAEN2_DMAADC1_MSK (0x1 << 1 )
2884#define FEEAEN2_DMAADC1 (0x1 << 1 )
2885#define FEEAEN2_DMAADC1_DIS (0x0 << 1 ) /* DIS */
2886#define FEEAEN2_DMAADC1_EN (0x1 << 1 ) /* EN */
2887
2888/* FEEAEN2[DMAADC0] - */
2889#define FEEAEN2_DMAADC0_BBA (*(volatile unsigned long *) 0x42051000)
2890#define FEEAEN2_DMAADC0_MSK (0x1 << 0 )
2891#define FEEAEN2_DMAADC0 (0x1 << 0 )
2892#define FEEAEN2_DMAADC0_DIS (0x0 << 0 ) /* DIS */
2893#define FEEAEN2_DMAADC0_EN (0x1 << 0 ) /* EN */
2894// ------------------------------------------------------------------------------------------------
2895// ----- I2C -----
2896// ------------------------------------------------------------------------------------------------
2897
2898
2899/**
2900 * @brief I2C (pADI_I2C)
2901 */
2902
2903#if (__NO_MMR_STRUCTS__==0)
2904typedef struct { /*!< pADI_I2C Structure */
2905 __IO uint16_t I2CMCON; /*!< Master Control Register */
2906 __I uint16_t RESERVED0;
2907 __IO uint16_t I2CMSTA; /*!< Master Status Register */
2908 __I uint16_t RESERVED1;
2909 __IO uint8_t I2CMRX; /*!< Master Receive Data */
2910 __I uint8_t RESERVED2[3];
2911 __IO uint8_t I2CMTX; /*!< Master Transmit Data */
2912 __I uint8_t RESERVED3[3];
2913 __IO uint16_t I2CMRXCNT; /*!< Master Receive Data Count */
2914 __I uint16_t RESERVED4;
2915 __IO uint16_t I2CMCRXCNT; /*!< Master Current Receive Data Count */
2916 __I uint16_t RESERVED5;
2917 __IO uint8_t I2CADR0; /*!< 1st Master Address Byte */
2918 __I uint8_t RESERVED6[3];
2919 __IO uint8_t I2CADR1; /*!< 2nd Master Address Byte */
2920 __I uint8_t RESERVED7[7];
2921 __IO uint16_t I2CDIV; /*!< Serial clock period divisor register */
2922 __I uint16_t RESERVED8;
2923 __IO uint16_t I2CSCON; /*!< Slave Control Register */
2924 __I uint16_t RESERVED9;
2925 __IO uint16_t I2CSSTA; /*!< "Slave I2C Status, Error and IRQ Register" */
2926 __I uint16_t RESERVED10;
2927 __IO uint16_t I2CSRX; /*!< Slave Receive Data Register */
2928 __I uint16_t RESERVED11;
2929 __IO uint16_t I2CSTX; /*!< Slave Transmit Data Register */
2930 __I uint16_t RESERVED12;
2931 __IO uint16_t I2CALT; /*!< Hardware General Call ID */
2932 __I uint16_t RESERVED13;
2933 __IO uint16_t I2CID0; /*!< 1st Slave Address Device ID */
2934 __I uint16_t RESERVED14;
2935 __IO uint16_t I2CID1; /*!< 2nd Slave Address Device ID */
2936 __I uint16_t RESERVED15;
2937 __IO uint16_t I2CID2; /*!< 3rd Slave Address Device ID */
2938 __I uint16_t RESERVED16;
2939 __IO uint16_t I2CID3; /*!< 4th Slave Address Device ID */
2940 __I uint16_t RESERVED17;
2941 __IO uint16_t I2CFSTA; /*!< Master and Slave Rx/Tx FIFO Status Register */
2942} ADI_I2C_TypeDef;
2943#else // (__NO_MMR_STRUCTS__==0)
2944#define I2CMCON (*(volatile unsigned short int *) 0x40003000)
2945#define I2CMSTA (*(volatile unsigned short int *) 0x40003004)
2946#define I2CMRX (*(volatile unsigned char *) 0x40003008)
2947#define I2CMTX (*(volatile unsigned char *) 0x4000300C)
2948#define I2CMRXCNT (*(volatile unsigned short int *) 0x40003010)
2949#define I2CMCRXCNT (*(volatile unsigned short int *) 0x40003014)
2950#define I2CADR0 (*(volatile unsigned char *) 0x40003018)
2951#define I2CADR1 (*(volatile unsigned char *) 0x4000301C)
2952#define I2CDIV (*(volatile unsigned short int *) 0x40003024)
2953#define I2CSCON (*(volatile unsigned short int *) 0x40003028)
2954#define I2CSSTA (*(volatile unsigned short int *) 0x4000302C)
2955#define I2CSRX (*(volatile unsigned short int *) 0x40003030)
2956#define I2CSTX (*(volatile unsigned short int *) 0x40003034)
2957#define I2CALT (*(volatile unsigned short int *) 0x40003038)
2958#define I2CID0 (*(volatile unsigned short int *) 0x4000303C)
2959#define I2CID1 (*(volatile unsigned short int *) 0x40003040)
2960#define I2CID2 (*(volatile unsigned short int *) 0x40003044)
2961#define I2CID3 (*(volatile unsigned short int *) 0x40003048)
2962#define I2CFSTA (*(volatile unsigned short int *) 0x4000304C)
2963#endif // (__NO_MMR_STRUCTS__==0)
2964
2965/* Reset Value for I2CMCON*/
2966#define I2CMCON_RVAL 0x0
2967
2968/* I2CMCON[TXDMA] - Enable master Tx DMA request */
2969#define I2CMCON_TXDMA_BBA (*(volatile unsigned long *) 0x4206002C)
2970#define I2CMCON_TXDMA_MSK (0x1 << 11 )
2971#define I2CMCON_TXDMA (0x1 << 11 )
2972#define I2CMCON_TXDMA_DIS (0x0 << 11 ) /* DIS */
2973#define I2CMCON_TXDMA_EN (0x1 << 11 ) /* EN */
2974
2975/* I2CMCON[RXDMA] - Enable master Rx DMA request */
2976#define I2CMCON_RXDMA_BBA (*(volatile unsigned long *) 0x42060028)
2977#define I2CMCON_RXDMA_MSK (0x1 << 10 )
2978#define I2CMCON_RXDMA (0x1 << 10 )
2979#define I2CMCON_RXDMA_DIS (0x0 << 10 ) /* DIS */
2980#define I2CMCON_RXDMA_EN (0x1 << 10 ) /* EN */
2981
2982/* I2CMCON[IENCMP] - Transaction completed interrupt enable */
2983#define I2CMCON_IENCMP_BBA (*(volatile unsigned long *) 0x42060020)
2984#define I2CMCON_IENCMP_MSK (0x1 << 8 )
2985#define I2CMCON_IENCMP (0x1 << 8 )
2986#define I2CMCON_IENCMP_DIS (0x0 << 8 ) /* DIS */
2987#define I2CMCON_IENCMP_EN (0x1 << 8 ) /* EN */
2988
2989/* I2CMCON[IENNACK] - ACK not received interrupt enable */
2990#define I2CMCON_IENNACK_BBA (*(volatile unsigned long *) 0x4206001C)
2991#define I2CMCON_IENNACK_MSK (0x1 << 7 )
2992#define I2CMCON_IENNACK (0x1 << 7 )
2993#define I2CMCON_IENNACK_DIS (0x0 << 7 ) /* DIS */
2994#define I2CMCON_IENNACK_EN (0x1 << 7 ) /* EN */
2995
2996/* I2CMCON[IENALOST] - Arbitration lost interrupt enable */
2997#define I2CMCON_IENALOST_BBA (*(volatile unsigned long *) 0x42060018)
2998#define I2CMCON_IENALOST_MSK (0x1 << 6 )
2999#define I2CMCON_IENALOST (0x1 << 6 )
3000#define I2CMCON_IENALOST_DIS (0x0 << 6 ) /* DIS */
3001#define I2CMCON_IENALOST_EN (0x1 << 6 ) /* EN */
3002
3003/* I2CMCON[IENTX] - Transmit request interrupt enable */
3004#define I2CMCON_IENTX_BBA (*(volatile unsigned long *) 0x42060014)
3005#define I2CMCON_IENTX_MSK (0x1 << 5 )
3006#define I2CMCON_IENTX (0x1 << 5 )
3007#define I2CMCON_IENTX_DIS (0x0 << 5 ) /* DIS */
3008#define I2CMCON_IENTX_EN (0x1 << 5 ) /* EN */
3009
3010/* I2CMCON[IENRX] - Receive request interrupt enable */
3011#define I2CMCON_IENRX_BBA (*(volatile unsigned long *) 0x42060010)
3012#define I2CMCON_IENRX_MSK (0x1 << 4 )
3013#define I2CMCON_IENRX (0x1 << 4 )
3014#define I2CMCON_IENRX_DIS (0x0 << 4 ) /* DIS */
3015#define I2CMCON_IENRX_EN (0x1 << 4 ) /* EN */
3016
3017/* I2CMCON[STRETCH] - Stretch SCL */
3018#define I2CMCON_STRETCH_BBA (*(volatile unsigned long *) 0x4206000C)
3019#define I2CMCON_STRETCH_MSK (0x1 << 3 )
3020#define I2CMCON_STRETCH (0x1 << 3 )
3021#define I2CMCON_STRETCH_DIS (0x0 << 3 ) /* DIS */
3022#define I2CMCON_STRETCH_EN (0x1 << 3 ) /* EN */
3023
3024/* I2CMCON[LOOPBACK] - Internal loop back */
3025#define I2CMCON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42060008)
3026#define I2CMCON_LOOPBACK_MSK (0x1 << 2 )
3027#define I2CMCON_LOOPBACK (0x1 << 2 )
3028#define I2CMCON_LOOPBACK_DIS (0x0 << 2 ) /* DIS */
3029#define I2CMCON_LOOPBACK_EN (0x1 << 2 ) /* EN */
3030
3031/* I2CMCON[COMPETE] - Compete for ownership */
3032#define I2CMCON_COMPETE_BBA (*(volatile unsigned long *) 0x42060004)
3033#define I2CMCON_COMPETE_MSK (0x1 << 1 )
3034#define I2CMCON_COMPETE (0x1 << 1 )
3035#define I2CMCON_COMPETE_DIS (0x0 << 1 ) /* DIS */
3036#define I2CMCON_COMPETE_EN (0x1 << 1 ) /* EN */
3037
3038/* I2CMCON[MAS] - Master Enable */
3039#define I2CMCON_MAS_BBA (*(volatile unsigned long *) 0x42060000)
3040#define I2CMCON_MAS_MSK (0x1 << 0 )
3041#define I2CMCON_MAS (0x1 << 0 )
3042#define I2CMCON_MAS_DIS (0x0 << 0 ) /* DIS */
3043#define I2CMCON_MAS_EN (0x1 << 0 ) /* EN */
3044
3045/* Reset Value for I2CMSTA*/
3046#define I2CMSTA_RVAL 0x0
3047
3048/* I2CMSTA[TXUR] - Master Transmit FIFO underflow */
3049#define I2CMSTA_TXUR_BBA (*(volatile unsigned long *) 0x420600B0)
3050#define I2CMSTA_TXUR_MSK (0x1 << 12 )
3051#define I2CMSTA_TXUR (0x1 << 12 )
3052#define I2CMSTA_TXUR_CLR (0x0 << 12 ) /* CLR */
3053#define I2CMSTA_TXUR_SET (0x1 << 12 ) /* SET */
3054
3055/* I2CMSTA[MSTOP] - STOP driven by th eI2C master */
3056#define I2CMSTA_MSTOP_BBA (*(volatile unsigned long *) 0x420600AC)
3057#define I2CMSTA_MSTOP_MSK (0x1 << 11 )
3058#define I2CMSTA_MSTOP (0x1 << 11 )
3059#define I2CMSTA_MSTOP_CLR (0x0 << 11 ) /* CLR */
3060#define I2CMSTA_MSTOP_SET (0x1 << 11 ) /* SET */
3061
3062/* I2CMSTA[LINEBUSY] - Line is busy */
3063#define I2CMSTA_LINEBUSY_BBA (*(volatile unsigned long *) 0x420600A8)
3064#define I2CMSTA_LINEBUSY_MSK (0x1 << 10 )
3065#define I2CMSTA_LINEBUSY (0x1 << 10 )
3066#define I2CMSTA_LINEBUSY_CLR (0x0 << 10 ) /* CLR */
3067#define I2CMSTA_LINEBUSY_SET (0x1 << 10 ) /* SET */
3068
3069/* I2CMSTA[RXOF] - Receive FIFO overflow */
3070#define I2CMSTA_RXOF_BBA (*(volatile unsigned long *) 0x420600A4)
3071#define I2CMSTA_RXOF_MSK (0x1 << 9 )
3072#define I2CMSTA_RXOF (0x1 << 9 )
3073#define I2CMSTA_RXOF_CLR (0x0 << 9 ) /* CLR */
3074#define I2CMSTA_RXOF_SET (0x1 << 9 ) /* SET */
3075
3076/* I2CMSTA[TCOMP] - Transaction completed */
3077#define I2CMSTA_TCOMP_BBA (*(volatile unsigned long *) 0x420600A0)
3078#define I2CMSTA_TCOMP_MSK (0x1 << 8 )
3079#define I2CMSTA_TCOMP (0x1 << 8 )
3080#define I2CMSTA_TCOMP_CLR (0x0 << 8 ) /* CLR */
3081#define I2CMSTA_TCOMP_SET (0x1 << 8 ) /* SET */
3082
3083/* I2CMSTA[NACKDATA] - Ack not received in response to data write */
3084#define I2CMSTA_NACKDATA_BBA (*(volatile unsigned long *) 0x4206009C)
3085#define I2CMSTA_NACKDATA_MSK (0x1 << 7 )
3086#define I2CMSTA_NACKDATA (0x1 << 7 )
3087#define I2CMSTA_NACKDATA_CLR (0x0 << 7 ) /* CLR */
3088#define I2CMSTA_NACKDATA_SET (0x1 << 7 ) /* SET */
3089
3090/* I2CMSTA[BUSY] - Master Busy */
3091#define I2CMSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060098)
3092#define I2CMSTA_BUSY_MSK (0x1 << 6 )
3093#define I2CMSTA_BUSY (0x1 << 6 )
3094#define I2CMSTA_BUSY_CLR (0x0 << 6 ) /* CLR */
3095#define I2CMSTA_BUSY_SET (0x1 << 6 ) /* SET */
3096
3097/* I2CMSTA[ALOST] - Arbitration lost */
3098#define I2CMSTA_ALOST_BBA (*(volatile unsigned long *) 0x42060094)
3099#define I2CMSTA_ALOST_MSK (0x1 << 5 )
3100#define I2CMSTA_ALOST (0x1 << 5 )
3101#define I2CMSTA_ALOST_CLR (0x0 << 5 ) /* CLR */
3102#define I2CMSTA_ALOST_SET (0x1 << 5 ) /* SET */
3103
3104/* I2CMSTA[NACKADDR] - Ack not received in response to an address */
3105#define I2CMSTA_NACKADDR_BBA (*(volatile unsigned long *) 0x42060090)
3106#define I2CMSTA_NACKADDR_MSK (0x1 << 4 )
3107#define I2CMSTA_NACKADDR (0x1 << 4 )
3108#define I2CMSTA_NACKADDR_CLR (0x0 << 4 ) /* CLR */
3109#define I2CMSTA_NACKADDR_SET (0x1 << 4 ) /* SET */
3110
3111/* I2CMSTA[RXREQ] - Receive request */
3112#define I2CMSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206008C)
3113#define I2CMSTA_RXREQ_MSK (0x1 << 3 )
3114#define I2CMSTA_RXREQ (0x1 << 3 )
3115#define I2CMSTA_RXREQ_CLR (0x0 << 3 ) /* CLR */
3116#define I2CMSTA_RXREQ_SET (0x1 << 3 ) /* SET */
3117
3118/* I2CMSTA[TXREQ] - Transmit request */
3119#define I2CMSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060088)
3120#define I2CMSTA_TXREQ_MSK (0x1 << 2 )
3121#define I2CMSTA_TXREQ (0x1 << 2 )
3122#define I2CMSTA_TXREQ_CLR (0x0 << 2 ) /* CLR */
3123#define I2CMSTA_TXREQ_SET (0x1 << 2 ) /* SET */
3124
3125/* I2CMSTA[TXFSTA] - Transmit FIFO Status */
3126#define I2CMSTA_TXFSTA_MSK (0x3 << 0 )
3127#define I2CMSTA_TXFSTA_EMPTY (0x0 << 0 ) /* EMPTY */
3128#define I2CMSTA_TXFSTA_ONEBYTE (0x1 << 0 ) /* ONEBYTE */
3129#define I2CMSTA_TXFSTA_FULL (0x3 << 0 ) /* FULL */
3130
3131/* Reset Value for I2CMRX*/
3132#define I2CMRX_RVAL 0x0
3133
3134/* I2CMRX[VALUE] - Current Receive Value */
3135#define I2CMRX_VALUE_MSK (0xFF << 0 )
3136
3137/* Reset Value for I2CMTX*/
3138#define I2CMTX_RVAL 0x0
3139
3140/* I2CMTX[VALUE] - Current Transmit Value */
3141#define I2CMTX_VALUE_MSK (0xFF << 0 )
3142
3143/* Reset Value for I2CMRXCNT*/
3144#define I2CMRXCNT_RVAL 0x0
3145
3146/* I2CMRXCNT[EXTEND] - Extended Read */
3147#define I2CMRXCNT_EXTEND_BBA (*(volatile unsigned long *) 0x42060220)
3148#define I2CMRXCNT_EXTEND_MSK (0x1 << 8 )
3149#define I2CMRXCNT_EXTEND (0x1 << 8 )
3150#define I2CMRXCNT_EXTEND_DIS (0x0 << 8 ) /* DIS */
3151#define I2CMRXCNT_EXTEND_EN (0x1 << 8 ) /* EN */
3152
3153/* I2CMRXCNT[COUNT] - Receive count */
3154#define I2CMRXCNT_COUNT_MSK (0xFF << 0 )
3155
3156/* Reset Value for I2CMCRXCNT*/
3157#define I2CMCRXCNT_RVAL 0x0
3158
3159/* I2CMCRXCNT[VALUE] - Current Receive count */
3160#define I2CMCRXCNT_VALUE_MSK (0xFF << 0 )
3161
3162/* Reset Value for I2CADR0*/
3163#define I2CADR0_RVAL 0x0
3164
3165/* I2CADR0[VALUE] - Address byte */
3166#define I2CADR0_VALUE_MSK (0xFF << 0 )
3167
3168/* Reset Value for I2CADR1*/
3169#define I2CADR1_RVAL 0x0
3170
3171/* I2CADR1[VALUE] - Address byte */
3172#define I2CADR1_VALUE_MSK (0xFF << 0 )
3173
3174/* Reset Value for I2CDIV*/
3175#define I2CDIV_RVAL 0x1F1F
3176
3177/* I2CDIV[HIGH] - High Time */
3178#define I2CDIV_HIGH_MSK (0xFF << 8 )
3179
3180/* I2CDIV[LOW] - Low Time */
3181#define I2CDIV_LOW_MSK (0xFF << 0 )
3182
3183/* Reset Value for I2CSCON*/
3184#define I2CSCON_RVAL 0x0
3185
3186/* I2CSCON[TXDMA] - Enable slave Tx DMA request */
3187#define I2CSCON_TXDMA_BBA (*(volatile unsigned long *) 0x42060538)
3188#define I2CSCON_TXDMA_MSK (0x1 << 14 )
3189#define I2CSCON_TXDMA (0x1 << 14 )
3190#define I2CSCON_TXDMA_DIS (0x0 << 14 ) /* DIS */
3191#define I2CSCON_TXDMA_EN (0x1 << 14 ) /* EN */
3192
3193/* I2CSCON[RXDMA] - Enable slave Rx DMA request */
3194#define I2CSCON_RXDMA_BBA (*(volatile unsigned long *) 0x42060534)
3195#define I2CSCON_RXDMA_MSK (0x1 << 13 )
3196#define I2CSCON_RXDMA (0x1 << 13 )
3197#define I2CSCON_RXDMA_DIS (0x0 << 13 ) /* DIS */
3198#define I2CSCON_RXDMA_EN (0x1 << 13 ) /* EN */
3199
3200/* I2CSCON[IENREPST] - Repeated start interrupt enable */
3201#define I2CSCON_IENREPST_BBA (*(volatile unsigned long *) 0x42060530)
3202#define I2CSCON_IENREPST_MSK (0x1 << 12 )
3203#define I2CSCON_IENREPST (0x1 << 12 )
3204#define I2CSCON_IENREPST_DIS (0x0 << 12 ) /* DIS */
3205#define I2CSCON_IENREPST_EN (0x1 << 12 ) /* EN */
3206
3207/* I2CSCON[IENTX] - Transmit request interrupt enable */
3208#define I2CSCON_IENTX_BBA (*(volatile unsigned long *) 0x42060528)
3209#define I2CSCON_IENTX_MSK (0x1 << 10 )
3210#define I2CSCON_IENTX (0x1 << 10 )
3211#define I2CSCON_IENTX_DIS (0x0 << 10 ) /* DIS */
3212#define I2CSCON_IENTX_EN (0x1 << 10 ) /* EN */
3213
3214/* I2CSCON[IENRX] - Receive request interrupt enable */
3215#define I2CSCON_IENRX_BBA (*(volatile unsigned long *) 0x42060524)
3216#define I2CSCON_IENRX_MSK (0x1 << 9 )
3217#define I2CSCON_IENRX (0x1 << 9 )
3218#define I2CSCON_IENRX_DIS (0x0 << 9 ) /* DIS */
3219#define I2CSCON_IENRX_EN (0x1 << 9 ) /* EN */
3220
3221/* I2CSCON[IENSTOP] - Stop condition detected interrupt enable */
3222#define I2CSCON_IENSTOP_BBA (*(volatile unsigned long *) 0x42060520)
3223#define I2CSCON_IENSTOP_MSK (0x1 << 8 )
3224#define I2CSCON_IENSTOP (0x1 << 8 )
3225#define I2CSCON_IENSTOP_DIS (0x0 << 8 ) /* DIS */
3226#define I2CSCON_IENSTOP_EN (0x1 << 8 ) /* EN */
3227
3228/* I2CSCON[NACK] - NACK next communication */
3229#define I2CSCON_NACK_BBA (*(volatile unsigned long *) 0x4206051C)
3230#define I2CSCON_NACK_MSK (0x1 << 7 )
3231#define I2CSCON_NACK (0x1 << 7 )
3232#define I2CSCON_NACK_DIS (0x0 << 7 ) /* DIS */
3233#define I2CSCON_NACK_EN (0x1 << 7 ) /* EN */
3234
3235/* I2CSCON[STRETCH] - Stretch SCL */
3236#define I2CSCON_STRETCH_BBA (*(volatile unsigned long *) 0x42060518)
3237#define I2CSCON_STRETCH_MSK (0x1 << 6 )
3238#define I2CSCON_STRETCH (0x1 << 6 )
3239#define I2CSCON_STRETCH_DIS (0x0 << 6 ) /* DIS */
3240#define I2CSCON_STRETCH_EN (0x1 << 6 ) /* EN */
3241
3242/* I2CSCON[EARLYTXR] - Early transmit request mode */
3243#define I2CSCON_EARLYTXR_BBA (*(volatile unsigned long *) 0x42060514)
3244#define I2CSCON_EARLYTXR_MSK (0x1 << 5 )
3245#define I2CSCON_EARLYTXR (0x1 << 5 )
3246#define I2CSCON_EARLYTXR_DIS (0x0 << 5 ) /* DIS */
3247#define I2CSCON_EARLYTXR_EN (0x1 << 5 ) /* EN */
3248
3249/* I2CSCON[GCSB] - General call status bit clear */
3250#define I2CSCON_GCSB_BBA (*(volatile unsigned long *) 0x42060510)
3251#define I2CSCON_GCSB_MSK (0x1 << 4 )
3252#define I2CSCON_GCSB (0x1 << 4 )
3253#define I2CSCON_GCSB_CLR (0x1 << 4 ) /* CLR */
3254
3255/* I2CSCON[HGC] - Hardware general Call enable */
3256#define I2CSCON_HGC_BBA (*(volatile unsigned long *) 0x4206050C)
3257#define I2CSCON_HGC_MSK (0x1 << 3 )
3258#define I2CSCON_HGC (0x1 << 3 )
3259#define I2CSCON_HGC_DIS (0x0 << 3 ) /* DIS */
3260#define I2CSCON_HGC_EN (0x1 << 3 ) /* EN */
3261
3262/* I2CSCON[GC] - General Call enable */
3263#define I2CSCON_GC_BBA (*(volatile unsigned long *) 0x42060508)
3264#define I2CSCON_GC_MSK (0x1 << 2 )
3265#define I2CSCON_GC (0x1 << 2 )
3266#define I2CSCON_GC_DIS (0x0 << 2 ) /* DIS */
3267#define I2CSCON_GC_EN (0x1 << 2 ) /* EN */
3268
3269/* I2CSCON[ADR10] - Enable 10 bit addressing */
3270#define I2CSCON_ADR10_BBA (*(volatile unsigned long *) 0x42060504)
3271#define I2CSCON_ADR10_MSK (0x1 << 1 )
3272#define I2CSCON_ADR10 (0x1 << 1 )
3273#define I2CSCON_ADR10_DIS (0x0 << 1 ) /* DIS */
3274#define I2CSCON_ADR10_EN (0x1 << 1 ) /* EN */
3275
3276/* I2CSCON[SLV] - Slave Enable */
3277#define I2CSCON_SLV_BBA (*(volatile unsigned long *) 0x42060500)
3278#define I2CSCON_SLV_MSK (0x1 << 0 )
3279#define I2CSCON_SLV (0x1 << 0 )
3280#define I2CSCON_SLV_DIS (0x0 << 0 ) /* DIS */
3281#define I2CSCON_SLV_EN (0x1 << 0 ) /* EN */
3282
3283/* Reset Value for I2CSSTA*/
3284#define I2CSSTA_RVAL 0x1
3285
3286/* I2CSSTA[START] - Start and matching address */
3287#define I2CSSTA_START_BBA (*(volatile unsigned long *) 0x420605B8)
3288#define I2CSSTA_START_MSK (0x1 << 14 )
3289#define I2CSSTA_START (0x1 << 14 )
3290#define I2CSSTA_START_CLR (0x0 << 14 ) /* CLR */
3291#define I2CSSTA_START_SET (0x1 << 14 ) /* SET */
3292
3293/* I2CSSTA[REPSTART] - Repeated start and matching address */
3294#define I2CSSTA_REPSTART_BBA (*(volatile unsigned long *) 0x420605B4)
3295#define I2CSSTA_REPSTART_MSK (0x1 << 13 )
3296#define I2CSSTA_REPSTART (0x1 << 13 )
3297#define I2CSSTA_REPSTART_CLR (0x0 << 13 ) /* CLR */
3298#define I2CSSTA_REPSTART_SET (0x1 << 13 ) /* SET */
3299
3300/* I2CSSTA[IDMAT] - Device ID matched */
3301#define I2CSSTA_IDMAT_MSK (0x3 << 11 )
3302#define I2CSSTA_IDMAT_CLR (0x0 << 11 ) /* CLR */
3303#define I2CSSTA_IDMAT_SET (0x1 << 11 ) /* SET */
3304
3305/* I2CSSTA[STOP] - Stop after start and matching address */
3306#define I2CSSTA_STOP_BBA (*(volatile unsigned long *) 0x420605A8)
3307#define I2CSSTA_STOP_MSK (0x1 << 10 )
3308#define I2CSSTA_STOP (0x1 << 10 )
3309#define I2CSSTA_STOP_CLR (0x0 << 10 ) /* CLR */
3310#define I2CSSTA_STOP_SET (0x1 << 10 ) /* SET */
3311
3312/* I2CSSTA[GCID] - General ID */
3313#define I2CSSTA_GCID_MSK (0x3 << 8 )
3314#define I2CSSTA_GCID_CLR (0x0 << 8 ) /* CLR */
3315#define I2CSSTA_GCID_SET (0x1 << 8 ) /* SET */
3316
3317/* I2CSSTA[GCINT] - General call */
3318#define I2CSSTA_GCINT_BBA (*(volatile unsigned long *) 0x4206059C)
3319#define I2CSSTA_GCINT_MSK (0x1 << 7 )
3320#define I2CSSTA_GCINT (0x1 << 7 )
3321#define I2CSSTA_GCINT_CLR (0x0 << 7 ) /* CLR */
3322#define I2CSSTA_GCINT_SET (0x1 << 7 ) /* SET */
3323
3324/* I2CSSTA[BUSY] - Slave busy */
3325#define I2CSSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060598)
3326#define I2CSSTA_BUSY_MSK (0x1 << 6 )
3327#define I2CSSTA_BUSY (0x1 << 6 )
3328#define I2CSSTA_BUSY_CLR (0x0 << 6 ) /* CLR */
3329#define I2CSSTA_BUSY_SET (0x1 << 6 ) /* SET */
3330
3331/* I2CSSTA[NOACK] - Ack not generated by the slave */
3332#define I2CSSTA_NOACK_BBA (*(volatile unsigned long *) 0x42060594)
3333#define I2CSSTA_NOACK_MSK (0x1 << 5 )
3334#define I2CSSTA_NOACK (0x1 << 5 )
3335#define I2CSSTA_NOACK_CLR (0x0 << 5 ) /* CLR */
3336#define I2CSSTA_NOACK_SET (0x1 << 5 ) /* SET */
3337
3338/* I2CSSTA[RXOF] - Receive FIFO */
3339#define I2CSSTA_RXOF_BBA (*(volatile unsigned long *) 0x42060590)
3340#define I2CSSTA_RXOF_MSK (0x1 << 4 )
3341#define I2CSSTA_RXOF (0x1 << 4 )
3342#define I2CSSTA_RXOF_CLR (0x0 << 4 ) /* CLR */
3343#define I2CSSTA_RXOF_SET (0x1 << 4 ) /* SET */
3344
3345/* I2CSSTA[RXREQ] - Receive */
3346#define I2CSSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206058C)
3347#define I2CSSTA_RXREQ_MSK (0x1 << 3 )
3348#define I2CSSTA_RXREQ (0x1 << 3 )
3349#define I2CSSTA_RXREQ_CLR (0x0 << 3 ) /* CLR */
3350#define I2CSSTA_RXREQ_SET (0x1 << 3 ) /* SET */
3351
3352/* I2CSSTA[TXREQ] - Transmit */
3353#define I2CSSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060588)
3354#define I2CSSTA_TXREQ_MSK (0x1 << 2 )
3355#define I2CSSTA_TXREQ (0x1 << 2 )
3356#define I2CSSTA_TXREQ_CLR (0x0 << 2 ) /* CLR */
3357#define I2CSSTA_TXREQ_SET (0x1 << 2 ) /* SET */
3358
3359/* I2CSSTA[TXUR] - Transmit FIFO underflow */
3360#define I2CSSTA_TXUR_BBA (*(volatile unsigned long *) 0x42060584)
3361#define I2CSSTA_TXUR_MSK (0x1 << 1 )
3362#define I2CSSTA_TXUR (0x1 << 1 )
3363#define I2CSSTA_TXUR_CLR (0x0 << 1 ) /* CLR */
3364#define I2CSSTA_TXUR_SET (0x1 << 1 ) /* SET */
3365
3366/* I2CSSTA[TXFSEREQ] - Tx FIFO status or early request */
3367#define I2CSSTA_TXFSEREQ_BBA (*(volatile unsigned long *) 0x42060580)
3368#define I2CSSTA_TXFSEREQ_MSK (0x1 << 0 )
3369#define I2CSSTA_TXFSEREQ (0x1 << 0 )
3370#define I2CSSTA_TXFSEREQ_CLR (0x0 << 0 ) /* CLR */
3371#define I2CSSTA_TXFSEREQ_SET (0x1 << 0 ) /* SET */
3372
3373/* Reset Value for I2CSRX*/
3374#define I2CSRX_RVAL 0x0
3375
3376/* I2CSRX[VALUE] - Receive register */
3377#define I2CSRX_VALUE_MSK (0xFF << 0 )
3378
3379/* Reset Value for I2CSTX*/
3380#define I2CSTX_RVAL 0x0
3381
3382/* I2CSTX[VALUE] - Transmit register */
3383#define I2CSTX_VALUE_MSK (0xFF << 0 )
3384
3385/* Reset Value for I2CALT*/
3386#define I2CALT_RVAL 0x0
3387
3388/* I2CALT[VALUE] - Alt register */
3389#define I2CALT_VALUE_MSK (0xFF << 0 )
3390
3391/* Reset Value for I2CID0*/
3392#define I2CID0_RVAL 0x0
3393
3394/* I2CID0[VALUE] - Slave ID */
3395#define I2CID0_VALUE_MSK (0xFF << 0 )
3396
3397/* Reset Value for I2CID1*/
3398#define I2CID1_RVAL 0x0
3399
3400/* I2CID1[VALUE] - Slave ID */
3401#define I2CID1_VALUE_MSK (0xFF << 0 )
3402
3403/* Reset Value for I2CID2*/
3404#define I2CID2_RVAL 0x0
3405
3406/* I2CID2[VALUE] - Slave ID */
3407#define I2CID2_VALUE_MSK (0xFF << 0 )
3408
3409/* Reset Value for I2CID3*/
3410#define I2CID3_RVAL 0x0
3411
3412/* I2CID3[VALUE] - Slave ID */
3413#define I2CID3_VALUE_MSK (0xFF << 0 )
3414
3415/* Reset Value for I2CFSTA*/
3416#define I2CFSTA_RVAL 0x0
3417
3418/* I2CFSTA[MFLUSH] - Flush the master transmit FIFO */
3419#define I2CFSTA_MFLUSH_BBA (*(volatile unsigned long *) 0x420609A4)
3420#define I2CFSTA_MFLUSH_MSK (0x1 << 9 )
3421#define I2CFSTA_MFLUSH (0x1 << 9 )
3422#define I2CFSTA_MFLUSH_DIS (0x0 << 9 ) /* DIS */
3423#define I2CFSTA_MFLUSH_EN (0x1 << 9 ) /* EN */
3424
3425/* I2CFSTA[SFLUSH] - Flush the slave transmit FIFO */
3426#define I2CFSTA_SFLUSH_BBA (*(volatile unsigned long *) 0x420609A0)
3427#define I2CFSTA_SFLUSH_MSK (0x1 << 8 )
3428#define I2CFSTA_SFLUSH (0x1 << 8 )
3429#define I2CFSTA_SFLUSH_DIS (0x0 << 8 ) /* DIS */
3430#define I2CFSTA_SFLUSH_EN (0x1 << 8 ) /* EN */
3431
3432/* I2CFSTA[MRXFSTA] - Master receive FIFO Status */
3433#define I2CFSTA_MRXFSTA_MSK (0x3 << 6 )
3434#define I2CFSTA_MRXFSTA_EMPTY (0x0 << 6 ) /* EMPTY */
3435#define I2CFSTA_MRXFSTA_ONEBYTE (0x1 << 6 ) /* ONEBYTE */
3436#define I2CFSTA_MRXFSTA_TWOBYTES (0x2 << 6 ) /* TWOBYTES */
3437
3438/* I2CFSTA[MTXFSTA] - Master Transmit FIFO Status */
3439#define I2CFSTA_MTXFSTA_MSK (0x3 << 4 )
3440#define I2CFSTA_MTXFSTA_EMPTY (0x0 << 4 ) /* EMPTY */
3441#define I2CFSTA_MTXFSTA_ONEBYTE (0x1 << 4 ) /* ONEBYTE */
3442#define I2CFSTA_MTXFSTA_TWOBYTES (0x2 << 4 ) /* TWOBYTES */
3443
3444/* I2CFSTA[SRXFSTA] - Slave receive FIFO Status */
3445#define I2CFSTA_SRXFSTA_MSK (0x3 << 2 )
3446#define I2CFSTA_SRXFSTA_EMPTY (0x0 << 2 ) /* EMPTY */
3447#define I2CFSTA_SRXFSTA_ONEBYTE (0x1 << 2 ) /* ONEBYTE */
3448#define I2CFSTA_SRXFSTA_TWOBYTES (0x2 << 2 ) /* TWOBYTES */
3449
3450/* I2CFSTA[STXFSTA] - Slave Transmit FIFO Status */
3451#define I2CFSTA_STXFSTA_MSK (0x3 << 0 )
3452#define I2CFSTA_STXFSTA_EMPTY (0x0 << 0 ) /* EMPTY */
3453#define I2CFSTA_STXFSTA_ONEBYTE (0x1 << 0 ) /* ONEBYTE */
3454#define I2CFSTA_STXFSTA_TWOBYTES (0x2 << 0 ) /* TWOBYTES */
3455// ------------------------------------------------------------------------------------------------
3456// ----- SPI0 -----
3457// ------------------------------------------------------------------------------------------------
3458
3459
3460/**
3461 * @brief Serial Peripheral Interface (pADI_SPI0)
3462 */
3463
3464#if (__NO_MMR_STRUCTS__==0)
3465typedef struct { /*!< pADI_SPI0 Structure */
3466 __IO uint16_t SPISTA; /*!< Status Register */
3467 __I uint16_t RESERVED0;
3468 __IO uint8_t SPIRX; /*!< 8-bit Receive register. */
3469 __I uint8_t RESERVED1[3];
3470 __IO uint8_t SPITX; /*!< 8-bit Transmit register */
3471 __I uint8_t RESERVED2[3];
3472 __IO uint16_t SPIDIV; /*!< SPI Clock Divider Registers */
3473 __I uint16_t RESERVED3;
3474 __IO uint16_t SPICON; /*!< 16-bit configuration register */
3475 __I uint16_t RESERVED4;
3476 __IO uint16_t SPIDMA; /*!< DMA enable register */
3477 __I uint16_t RESERVED5;
3478 __IO uint16_t SPICNT; /*!< 8-bit received byte count register */
3479} ADI_SPI_TypeDef;
3480#else // (__NO_MMR_STRUCTS__==0)
3481#define SPI0STA (*(volatile unsigned short int *) 0x40004000)
3482#define SPI0RX (*(volatile unsigned char *) 0x40004004)
3483#define SPI0TX (*(volatile unsigned char *) 0x40004008)
3484#define SPI0DIV (*(volatile unsigned short int *) 0x4000400C)
3485#define SPI0CON (*(volatile unsigned short int *) 0x40004010)
3486#define SPI0DMA (*(volatile unsigned short int *) 0x40004014)
3487#define SPI0CNT (*(volatile unsigned short int *) 0x40004018)
3488#endif // (__NO_MMR_STRUCTS__==0)
3489
3490/* Reset Value for SPI0STA*/
3491#define SPI0STA_RVAL 0x0
3492
3493/* SPI0STA[CSERR] - Detected an abrupt CS deassertion */
3494#define SPI0STA_CSERR_BBA (*(volatile unsigned long *) 0x42080030)
3495#define SPI0STA_CSERR_MSK (0x1 << 12 )
3496#define SPI0STA_CSERR (0x1 << 12 )
3497#define SPI0STA_CSERR_CLR (0x0 << 12 ) /* CLR */
3498#define SPI0STA_CSERR_SET (0x1 << 12 ) /* SET */
3499
3500/* SPI0STA[RXS] - Set when there are more bytes in the RX FIFO than the TIM bit says */
3501#define SPI0STA_RXS_BBA (*(volatile unsigned long *) 0x4208002C)
3502#define SPI0STA_RXS_MSK (0x1 << 11 )
3503#define SPI0STA_RXS (0x1 << 11 )
3504#define SPI0STA_RXS_CLR (0x0 << 11 ) /* CLR */
3505#define SPI0STA_RXS_SET (0x1 << 11 ) /* SET */
3506
3507/* SPI0STA[RXFSTA] - Receive FIFO Status */
3508#define SPI0STA_RXFSTA_MSK (0x7 << 8 )
3509#define SPI0STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY */
3510#define SPI0STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE */
3511#define SPI0STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES */
3512#define SPI0STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES */
3513#define SPI0STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES */
3514
3515/* SPI0STA[RXOF] - Receive FIFO overflow */
3516#define SPI0STA_RXOF_BBA (*(volatile unsigned long *) 0x4208001C)
3517#define SPI0STA_RXOF_MSK (0x1 << 7 )
3518#define SPI0STA_RXOF (0x1 << 7 )
3519#define SPI0STA_RXOF_CLR (0x0 << 7 ) /* CLR */
3520#define SPI0STA_RXOF_SET (0x1 << 7 ) /* SET */
3521
3522/* SPI0STA[RX] - Set when a receive interrupt occurs */
3523#define SPI0STA_RX_BBA (*(volatile unsigned long *) 0x42080018)
3524#define SPI0STA_RX_MSK (0x1 << 6 )
3525#define SPI0STA_RX (0x1 << 6 )
3526#define SPI0STA_RX_CLR (0x0 << 6 ) /* CLR */
3527#define SPI0STA_RX_SET (0x1 << 6 ) /* SET */
3528
3529/* SPI0STA[TX] - Set when a transmit interrupt occurs */
3530#define SPI0STA_TX_BBA (*(volatile unsigned long *) 0x42080014)
3531#define SPI0STA_TX_MSK (0x1 << 5 )
3532#define SPI0STA_TX (0x1 << 5 )
3533#define SPI0STA_TX_CLR (0x0 << 5 ) /* CLR */
3534#define SPI0STA_TX_SET (0x1 << 5 ) /* SET */
3535
3536/* SPI0STA[TXUR] - Transmit FIFO underflow */
3537#define SPI0STA_TXUR_BBA (*(volatile unsigned long *) 0x42080010)
3538#define SPI0STA_TXUR_MSK (0x1 << 4 )
3539#define SPI0STA_TXUR (0x1 << 4 )
3540#define SPI0STA_TXUR_CLR (0x0 << 4 ) /* CLR */
3541#define SPI0STA_TXUR_SET (0x1 << 4 ) /* SET */
3542
3543/* SPI0STA[TXFSTA] - transmit FIFO Status */
3544#define SPI0STA_TXFSTA_MSK (0x7 << 1 )
3545#define SPI0STA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY */
3546#define SPI0STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE */
3547#define SPI0STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES */
3548#define SPI0STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES */
3549#define SPI0STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES */
3550
3551/* SPI0STA[IRQ] - Interrupt status bit */
3552#define SPI0STA_IRQ_BBA (*(volatile unsigned long *) 0x42080000)
3553#define SPI0STA_IRQ_MSK (0x1 << 0 )
3554#define SPI0STA_IRQ (0x1 << 0 )
3555#define SPI0STA_IRQ_CLR (0x0 << 0 ) /* CLR */
3556#define SPI0STA_IRQ_SET (0x1 << 0 ) /* SET */
3557
3558/* Reset Value for SPI0RX*/
3559#define SPI0RX_RVAL 0x0
3560
3561/* SPI0RX[VALUE] - Received data */
3562#define SPI0RX_VALUE_MSK (0xFF << 0 )
3563
3564/* Reset Value for SPI0TX*/
3565#define SPI0TX_RVAL 0x0
3566
3567/* SPI0TX[VALUE] - Data to transmit */
3568#define SPI0TX_VALUE_MSK (0xFF << 0 )
3569
3570/* Reset Value for SPI0DIV*/
3571#define SPI0DIV_RVAL 0x0
3572
3573/* SPI0DIV[BCRST] - Bit counter reset */
3574#define SPI0DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208019C)
3575#define SPI0DIV_BCRST_MSK (0x1 << 7 )
3576#define SPI0DIV_BCRST (0x1 << 7 )
3577#define SPI0DIV_BCRST_DIS (0x0 << 7 ) /* DIS */
3578#define SPI0DIV_BCRST_EN (0x1 << 7 ) /* EN */
3579
3580/* SPI0DIV[DIV] - Factor used to divide UCLK to generate the serial clock */
3581#define SPI0DIV_DIV_MSK (0x3F << 0 )
3582
3583/* Reset Value for SPI0CON*/
3584#define SPI0CON_RVAL 0x0
3585
3586/* SPI0CON[MOD] - SPI IRQ Mode bits */
3587#define SPI0CON_MOD_MSK (0x3 << 14 )
3588#define SPI0CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1 */
3589#define SPI0CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2 */
3590#define SPI0CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3 */
3591#define SPI0CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4 */
3592
3593/* SPI0CON[TFLUSH] - TX FIFO Flush Enable bit */
3594#define SPI0CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42080234)
3595#define SPI0CON_TFLUSH_MSK (0x1 << 13 )
3596#define SPI0CON_TFLUSH (0x1 << 13 )
3597#define SPI0CON_TFLUSH_DIS (0x0 << 13 ) /* DIS */
3598#define SPI0CON_TFLUSH_EN (0x1 << 13 ) /* EN */
3599
3600/* SPI0CON[RFLUSH] - RX FIFO Flush Enable bit */
3601#define SPI0CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42080230)
3602#define SPI0CON_RFLUSH_MSK (0x1 << 12 )
3603#define SPI0CON_RFLUSH (0x1 << 12 )
3604#define SPI0CON_RFLUSH_DIS (0x0 << 12 ) /* DIS */
3605#define SPI0CON_RFLUSH_EN (0x1 << 12 ) /* EN */
3606
3607/* SPI0CON[CON] - Continuous transfer enable */
3608#define SPI0CON_CON_BBA (*(volatile unsigned long *) 0x4208022C)
3609#define SPI0CON_CON_MSK (0x1 << 11 )
3610#define SPI0CON_CON (0x1 << 11 )
3611#define SPI0CON_CON_DIS (0x0 << 11 ) /* DIS */
3612#define SPI0CON_CON_EN (0x1 << 11 ) /* EN */
3613
3614/* SPI0CON[LOOPBACK] - Loopback enable bit */
3615#define SPI0CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42080228)
3616#define SPI0CON_LOOPBACK_MSK (0x1 << 10 )
3617#define SPI0CON_LOOPBACK (0x1 << 10 )
3618#define SPI0CON_LOOPBACK_DIS (0x0 << 10 ) /* DIS */
3619#define SPI0CON_LOOPBACK_EN (0x1 << 10 ) /* EN */
3620
3621/* SPI0CON[SOEN] - Slave MISO output enable bit */
3622#define SPI0CON_SOEN_BBA (*(volatile unsigned long *) 0x42080224)
3623#define SPI0CON_SOEN_MSK (0x1 << 9 )
3624#define SPI0CON_SOEN (0x1 << 9 )
3625#define SPI0CON_SOEN_DIS (0x0 << 9 ) /* DIS */
3626#define SPI0CON_SOEN_EN (0x1 << 9 ) /* EN */
3627
3628/* SPI0CON[RXOF] - RX Oveflow Overwrite enable */
3629#define SPI0CON_RXOF_BBA (*(volatile unsigned long *) 0x42080220)
3630#define SPI0CON_RXOF_MSK (0x1 << 8 )
3631#define SPI0CON_RXOF (0x1 << 8 )
3632#define SPI0CON_RXOF_DIS (0x0 << 8 ) /* DIS */
3633#define SPI0CON_RXOF_EN (0x1 << 8 ) /* EN */
3634
3635/* SPI0CON[ZEN] - Transmit zeros when empty */
3636#define SPI0CON_ZEN_BBA (*(volatile unsigned long *) 0x4208021C)
3637#define SPI0CON_ZEN_MSK (0x1 << 7 )
3638#define SPI0CON_ZEN (0x1 << 7 )
3639#define SPI0CON_ZEN_DIS (0x0 << 7 ) /* DIS */
3640#define SPI0CON_ZEN_EN (0x1 << 7 ) /* EN */
3641
3642/* SPI0CON[TIM] - Transfer and interrupt mode */
3643#define SPI0CON_TIM_BBA (*(volatile unsigned long *) 0x42080218)
3644#define SPI0CON_TIM_MSK (0x1 << 6 )
3645#define SPI0CON_TIM (0x1 << 6 )
3646#define SPI0CON_TIM_RXRD (0x0 << 6 ) /* RXRD - Cleared by user to initiate transfer with a read of the SPIRX register */
3647#define SPI0CON_TIM_TXWR (0x1 << 6 ) /* TXWR - Set by user to initiate transfer with a write to the SPITX register. */
3648
3649/* SPI0CON[LSB] - LSB First Transfer enable */
3650#define SPI0CON_LSB_BBA (*(volatile unsigned long *) 0x42080214)
3651#define SPI0CON_LSB_MSK (0x1 << 5 )
3652#define SPI0CON_LSB (0x1 << 5 )
3653#define SPI0CON_LSB_DIS (0x0 << 5 ) /* DIS */
3654#define SPI0CON_LSB_EN (0x1 << 5 ) /* EN */
3655
3656/* SPI0CON[WOM] - Wired OR enable */
3657#define SPI0CON_WOM_BBA (*(volatile unsigned long *) 0x42080210)
3658#define SPI0CON_WOM_MSK (0x1 << 4 )
3659#define SPI0CON_WOM (0x1 << 4 )
3660#define SPI0CON_WOM_DIS (0x0 << 4 ) /* DIS */
3661#define SPI0CON_WOM_EN (0x1 << 4 ) /* EN */
3662
3663/* SPI0CON[CPOL] - Clock polarity mode */
3664#define SPI0CON_CPOL_BBA (*(volatile unsigned long *) 0x4208020C)
3665#define SPI0CON_CPOL_MSK (0x1 << 3 )
3666#define SPI0CON_CPOL (0x1 << 3 )
3667#define SPI0CON_CPOL_LOW (0x0 << 3 ) /* LOW */
3668#define SPI0CON_CPOL_HIGH (0x1 << 3 ) /* HIGH */
3669
3670/* SPI0CON[CPHA] - Clock phase mode */
3671#define SPI0CON_CPHA_BBA (*(volatile unsigned long *) 0x42080208)
3672#define SPI0CON_CPHA_MSK (0x1 << 2 )
3673#define SPI0CON_CPHA (0x1 << 2 )
3674#define SPI0CON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING */
3675#define SPI0CON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING */
3676
3677/* SPI0CON[MASEN] - Master enable */
3678#define SPI0CON_MASEN_BBA (*(volatile unsigned long *) 0x42080204)
3679#define SPI0CON_MASEN_MSK (0x1 << 1 )
3680#define SPI0CON_MASEN (0x1 << 1 )
3681#define SPI0CON_MASEN_DIS (0x0 << 1 ) /* DIS */
3682#define SPI0CON_MASEN_EN (0x1 << 1 ) /* EN */
3683
3684/* SPI0CON[ENABLE] - SPI Enable bit */
3685#define SPI0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42080200)
3686#define SPI0CON_ENABLE_MSK (0x1 << 0 )
3687#define SPI0CON_ENABLE (0x1 << 0 )
3688#define SPI0CON_ENABLE_DIS (0x0 << 0 ) /* DIS */
3689#define SPI0CON_ENABLE_EN (0x1 << 0 ) /* EN */
3690
3691/* Reset Value for SPI0DMA*/
3692#define SPI0DMA_RVAL 0x0
3693
3694/* SPI0DMA[IENRXDMA] - Enable receive DMA request */
3695#define SPI0DMA_IENRXDMA_BBA (*(volatile unsigned long *) 0x42080288)
3696#define SPI0DMA_IENRXDMA_MSK (0x1 << 2 )
3697#define SPI0DMA_IENRXDMA (0x1 << 2 )
3698#define SPI0DMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS */
3699#define SPI0DMA_IENRXDMA_EN (0x1 << 2 ) /* EN */
3700
3701/* SPI0DMA[IENTXDMA] - Enable transmit DMA request */
3702#define SPI0DMA_IENTXDMA_BBA (*(volatile unsigned long *) 0x42080284)
3703#define SPI0DMA_IENTXDMA_MSK (0x1 << 1 )
3704#define SPI0DMA_IENTXDMA (0x1 << 1 )
3705#define SPI0DMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS */
3706#define SPI0DMA_IENTXDMA_EN (0x1 << 1 ) /* EN */
3707
3708/* SPI0DMA[ENABLE] - Enable DMA for data transfer */
3709#define SPI0DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42080280)
3710#define SPI0DMA_ENABLE_MSK (0x1 << 0 )
3711#define SPI0DMA_ENABLE (0x1 << 0 )
3712#define SPI0DMA_ENABLE_DIS (0x0 << 0 ) /* DIS */
3713#define SPI0DMA_ENABLE_EN (0x1 << 0 ) /* EN */
3714
3715/* Reset Value for SPI0CNT*/
3716#define SPI0CNT_RVAL 0x0
3717
3718/* SPI0CNT[VALUE] - Count */
3719#define SPI0CNT_VALUE_MSK (0xFF << 0 )
3720#if (__NO_MMR_STRUCTS__==1)
3721
3722#define SPI1STA (*(volatile unsigned short int *) 0x40004400)
3723#define SPI1RX (*(volatile unsigned char *) 0x40004404)
3724#define SPI1TX (*(volatile unsigned char *) 0x40004408)
3725#define SPI1DIV (*(volatile unsigned short int *) 0x4000440C)
3726#define SPI1CON (*(volatile unsigned short int *) 0x40004410)
3727#define SPI1DMA (*(volatile unsigned short int *) 0x40004414)
3728#define SPI1CNT (*(volatile unsigned short int *) 0x40004418)
3729#endif // (__NO_MMR_STRUCTS__==1)
3730
3731/* Reset Value for SPI1STA*/
3732#define SPI1STA_RVAL 0x0
3733
3734/* SPI1STA[CSERR] - Detected an abrupt CS deassertion */
3735#define SPI1STA_CSERR_BBA (*(volatile unsigned long *) 0x42088030)
3736#define SPI1STA_CSERR_MSK (0x1 << 12 )
3737#define SPI1STA_CSERR (0x1 << 12 )
3738#define SPI1STA_CSERR_CLR (0x0 << 12 ) /* CLR */
3739#define SPI1STA_CSERR_SET (0x1 << 12 ) /* SET */
3740
3741/* SPI1STA[RXS] - Set when there are more bytes in the RX FIFO than the TIM bit says */
3742#define SPI1STA_RXS_BBA (*(volatile unsigned long *) 0x4208802C)
3743#define SPI1STA_RXS_MSK (0x1 << 11 )
3744#define SPI1STA_RXS (0x1 << 11 )
3745#define SPI1STA_RXS_CLR (0x0 << 11 ) /* CLR */
3746#define SPI1STA_RXS_SET (0x1 << 11 ) /* SET */
3747
3748/* SPI1STA[RXFSTA] - Receive FIFO Status */
3749#define SPI1STA_RXFSTA_MSK (0x7 << 8 )
3750#define SPI1STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY */
3751#define SPI1STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE */
3752#define SPI1STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES */
3753#define SPI1STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES */
3754#define SPI1STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES */
3755
3756/* SPI1STA[RXOF] - Receive FIFO overflow */
3757#define SPI1STA_RXOF_BBA (*(volatile unsigned long *) 0x4208801C)
3758#define SPI1STA_RXOF_MSK (0x1 << 7 )
3759#define SPI1STA_RXOF (0x1 << 7 )
3760#define SPI1STA_RXOF_CLR (0x0 << 7 ) /* CLR */
3761#define SPI1STA_RXOF_SET (0x1 << 7 ) /* SET */
3762
3763/* SPI1STA[RX] - Set when a receive interrupt occurs */
3764#define SPI1STA_RX_BBA (*(volatile unsigned long *) 0x42088018)
3765#define SPI1STA_RX_MSK (0x1 << 6 )
3766#define SPI1STA_RX (0x1 << 6 )
3767#define SPI1STA_RX_CLR (0x0 << 6 ) /* CLR */
3768#define SPI1STA_RX_SET (0x1 << 6 ) /* SET */
3769
3770/* SPI1STA[TX] - Set when a transmit interrupt occurs */
3771#define SPI1STA_TX_BBA (*(volatile unsigned long *) 0x42088014)
3772#define SPI1STA_TX_MSK (0x1 << 5 )
3773#define SPI1STA_TX (0x1 << 5 )
3774#define SPI1STA_TX_CLR (0x0 << 5 ) /* CLR */
3775#define SPI1STA_TX_SET (0x1 << 5 ) /* SET */
3776
3777/* SPI1STA[TXUR] - Transmit FIFO underflow */
3778#define SPI1STA_TXUR_BBA (*(volatile unsigned long *) 0x42088010)
3779#define SPI1STA_TXUR_MSK (0x1 << 4 )
3780#define SPI1STA_TXUR (0x1 << 4 )
3781#define SPI1STA_TXUR_CLR (0x0 << 4 ) /* CLR */
3782#define SPI1STA_TXUR_SET (0x1 << 4 ) /* SET */
3783
3784/* SPI1STA[TXFSTA] - transmit FIFO Status */
3785#define SPI1STA_TXFSTA_MSK (0x7 << 1 )
3786#define SPI1STA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY */
3787#define SPI1STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE */
3788#define SPI1STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES */
3789#define SPI1STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES */
3790#define SPI1STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES */
3791
3792/* SPI1STA[IRQ] - Interrupt status bit */
3793#define SPI1STA_IRQ_BBA (*(volatile unsigned long *) 0x42088000)
3794#define SPI1STA_IRQ_MSK (0x1 << 0 )
3795#define SPI1STA_IRQ (0x1 << 0 )
3796#define SPI1STA_IRQ_CLR (0x0 << 0 ) /* CLR */
3797#define SPI1STA_IRQ_SET (0x1 << 0 ) /* SET */
3798
3799/* Reset Value for SPI1RX*/
3800#define SPI1RX_RVAL 0x0
3801
3802/* SPI1RX[VALUE] - Received data */
3803#define SPI1RX_VALUE_MSK (0xFF << 0 )
3804
3805/* Reset Value for SPI1TX*/
3806#define SPI1TX_RVAL 0x0
3807
3808/* SPI1TX[VALUE] - Data to transmit */
3809#define SPI1TX_VALUE_MSK (0xFF << 0 )
3810
3811/* Reset Value for SPI1DIV*/
3812#define SPI1DIV_RVAL 0x0
3813
3814/* SPI1DIV[BCRST] - Bit counter reset */
3815#define SPI1DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208819C)
3816#define SPI1DIV_BCRST_MSK (0x1 << 7 )
3817#define SPI1DIV_BCRST (0x1 << 7 )
3818#define SPI1DIV_BCRST_DIS (0x0 << 7 ) /* DIS */
3819#define SPI1DIV_BCRST_EN (0x1 << 7 ) /* EN */
3820
3821/* SPI1DIV[DIV] - Factor used to divide UCLK to generate the serial clock */
3822#define SPI1DIV_DIV_MSK (0x3F << 0 )
3823
3824/* Reset Value for SPI1CON*/
3825#define SPI1CON_RVAL 0x0
3826
3827/* SPI1CON[MOD] - SPI IRQ Mode bits */
3828#define SPI1CON_MOD_MSK (0x3 << 14 )
3829#define SPI1CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1 */
3830#define SPI1CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2 */
3831#define SPI1CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3 */
3832#define SPI1CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4 */
3833
3834/* SPI1CON[TFLUSH] - TX FIFO Flush Enable bit */
3835#define SPI1CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42088234)
3836#define SPI1CON_TFLUSH_MSK (0x1 << 13 )
3837#define SPI1CON_TFLUSH (0x1 << 13 )
3838#define SPI1CON_TFLUSH_DIS (0x0 << 13 ) /* DIS */
3839#define SPI1CON_TFLUSH_EN (0x1 << 13 ) /* EN */
3840
3841/* SPI1CON[RFLUSH] - RX FIFO Flush Enable bit */
3842#define SPI1CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42088230)
3843#define SPI1CON_RFLUSH_MSK (0x1 << 12 )
3844#define SPI1CON_RFLUSH (0x1 << 12 )
3845#define SPI1CON_RFLUSH_DIS (0x0 << 12 ) /* DIS */
3846#define SPI1CON_RFLUSH_EN (0x1 << 12 ) /* EN */
3847
3848/* SPI1CON[CON] - Continuous transfer enable */
3849#define SPI1CON_CON_BBA (*(volatile unsigned long *) 0x4208822C)
3850#define SPI1CON_CON_MSK (0x1 << 11 )
3851#define SPI1CON_CON (0x1 << 11 )
3852#define SPI1CON_CON_DIS (0x0 << 11 ) /* DIS */
3853#define SPI1CON_CON_EN (0x1 << 11 ) /* EN */
3854
3855/* SPI1CON[LOOPBACK] - Loopback enable bit */
3856#define SPI1CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42088228)
3857#define SPI1CON_LOOPBACK_MSK (0x1 << 10 )
3858#define SPI1CON_LOOPBACK (0x1 << 10 )
3859#define SPI1CON_LOOPBACK_DIS (0x0 << 10 ) /* DIS */
3860#define SPI1CON_LOOPBACK_EN (0x1 << 10 ) /* EN */
3861
3862/* SPI1CON[SOEN] - Slave MISO output enable bit */
3863#define SPI1CON_SOEN_BBA (*(volatile unsigned long *) 0x42088224)
3864#define SPI1CON_SOEN_MSK (0x1 << 9 )
3865#define SPI1CON_SOEN (0x1 << 9 )
3866#define SPI1CON_SOEN_DIS (0x0 << 9 ) /* DIS */
3867#define SPI1CON_SOEN_EN (0x1 << 9 ) /* EN */
3868
3869/* SPI1CON[RXOF] - RX Oveflow Overwrite enable */
3870#define SPI1CON_RXOF_BBA (*(volatile unsigned long *) 0x42088220)
3871#define SPI1CON_RXOF_MSK (0x1 << 8 )
3872#define SPI1CON_RXOF (0x1 << 8 )
3873#define SPI1CON_RXOF_DIS (0x0 << 8 ) /* DIS */
3874#define SPI1CON_RXOF_EN (0x1 << 8 ) /* EN */
3875
3876/* SPI1CON[ZEN] - Transmit zeros when empty */
3877#define SPI1CON_ZEN_BBA (*(volatile unsigned long *) 0x4208821C)
3878#define SPI1CON_ZEN_MSK (0x1 << 7 )
3879#define SPI1CON_ZEN (0x1 << 7 )
3880#define SPI1CON_ZEN_DIS (0x0 << 7 ) /* DIS */
3881#define SPI1CON_ZEN_EN (0x1 << 7 ) /* EN */
3882
3883/* SPI1CON[TIM] - Transfer and interrupt mode */
3884#define SPI1CON_TIM_BBA (*(volatile unsigned long *) 0x42088218)
3885#define SPI1CON_TIM_MSK (0x1 << 6 )
3886#define SPI1CON_TIM (0x1 << 6 )
3887#define SPI1CON_TIM_RXRD (0x0 << 6 ) /* RXRD - Cleared by user to initiate transfer with a read of the SPIRX register */
3888#define SPI1CON_TIM_TXWR (0x1 << 6 ) /* TXWR - Set by user to initiate transfer with a write to the SPITX register. */
3889
3890/* SPI1CON[LSB] - LSB First Transfer enable */
3891#define SPI1CON_LSB_BBA (*(volatile unsigned long *) 0x42088214)
3892#define SPI1CON_LSB_MSK (0x1 << 5 )
3893#define SPI1CON_LSB (0x1 << 5 )
3894#define SPI1CON_LSB_DIS (0x0 << 5 ) /* DIS */
3895#define SPI1CON_LSB_EN (0x1 << 5 ) /* EN */
3896
3897/* SPI1CON[WOM] - Wired OR enable */
3898#define SPI1CON_WOM_BBA (*(volatile unsigned long *) 0x42088210)
3899#define SPI1CON_WOM_MSK (0x1 << 4 )
3900#define SPI1CON_WOM (0x1 << 4 )
3901#define SPI1CON_WOM_DIS (0x0 << 4 ) /* DIS */
3902#define SPI1CON_WOM_EN (0x1 << 4 ) /* EN */
3903
3904/* SPI1CON[CPOL] - Clock polarity mode */
3905#define SPI1CON_CPOL_BBA (*(volatile unsigned long *) 0x4208820C)
3906#define SPI1CON_CPOL_MSK (0x1 << 3 )
3907#define SPI1CON_CPOL (0x1 << 3 )
3908#define SPI1CON_CPOL_LOW (0x0 << 3 ) /* LOW */
3909#define SPI1CON_CPOL_HIGH (0x1 << 3 ) /* HIGH */
3910
3911/* SPI1CON[CPHA] - Clock phase mode */
3912#define SPI1CON_CPHA_BBA (*(volatile unsigned long *) 0x42088208)
3913#define SPI1CON_CPHA_MSK (0x1 << 2 )
3914#define SPI1CON_CPHA (0x1 << 2 )
3915#define SPI1CON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING */
3916#define SPI1CON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING */
3917
3918/* SPI1CON[MASEN] - Master enable */
3919#define SPI1CON_MASEN_BBA (*(volatile unsigned long *) 0x42088204)
3920#define SPI1CON_MASEN_MSK (0x1 << 1 )
3921#define SPI1CON_MASEN (0x1 << 1 )
3922#define SPI1CON_MASEN_DIS (0x0 << 1 ) /* DIS */
3923#define SPI1CON_MASEN_EN (0x1 << 1 ) /* EN */
3924
3925/* SPI1CON[ENABLE] - SPI Enable bit */
3926#define SPI1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42088200)
3927#define SPI1CON_ENABLE_MSK (0x1 << 0 )
3928#define SPI1CON_ENABLE (0x1 << 0 )
3929#define SPI1CON_ENABLE_DIS (0x0 << 0 ) /* DIS */
3930#define SPI1CON_ENABLE_EN (0x1 << 0 ) /* EN */
3931
3932/* Reset Value for SPI1DMA*/
3933#define SPI1DMA_RVAL 0x0
3934
3935/* SPI1DMA[IENRXDMA] - Enable receive DMA request */
3936#define SPI1DMA_IENRXDMA_BBA (*(volatile unsigned long *) 0x42088288)
3937#define SPI1DMA_IENRXDMA_MSK (0x1 << 2 )
3938#define SPI1DMA_IENRXDMA (0x1 << 2 )
3939#define SPI1DMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS */
3940#define SPI1DMA_IENRXDMA_EN (0x1 << 2 ) /* EN */
3941
3942/* SPI1DMA[IENTXDMA] - Enable transmit DMA request */
3943#define SPI1DMA_IENTXDMA_BBA (*(volatile unsigned long *) 0x42088284)
3944#define SPI1DMA_IENTXDMA_MSK (0x1 << 1 )
3945#define SPI1DMA_IENTXDMA (0x1 << 1 )
3946#define SPI1DMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS */
3947#define SPI1DMA_IENTXDMA_EN (0x1 << 1 ) /* EN */
3948
3949/* SPI1DMA[ENABLE] - Enable DMA for data transfer */
3950#define SPI1DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42088280)
3951#define SPI1DMA_ENABLE_MSK (0x1 << 0 )
3952#define SPI1DMA_ENABLE (0x1 << 0 )
3953#define SPI1DMA_ENABLE_DIS (0x0 << 0 ) /* DIS */
3954#define SPI1DMA_ENABLE_EN (0x1 << 0 ) /* EN */
3955
3956/* Reset Value for SPI1CNT*/
3957#define SPI1CNT_RVAL 0x0
3958
3959/* SPI1CNT[VALUE] - Count */
3960#define SPI1CNT_VALUE_MSK (0xFF << 0 )
3961// ------------------------------------------------------------------------------------------------
3962// ----- UART -----
3963// ------------------------------------------------------------------------------------------------
3964
3965
3966/**
3967 * @brief UART (pADI_UART)
3968 */
3969
3970#if (__NO_MMR_STRUCTS__==0)
3971typedef struct { /*!< pADI_UART Structure */
3972
3973 union {
3974 __IO uint8_t COMTX; /*!< Transmit Holding register */
3975 __IO uint8_t COMRX; /*!< Receive Buffer register */
3976 } ;
3977 __I uint8_t RESERVED0[3];
3978 __IO uint8_t COMIEN; /*!< Interrupt Enable register */
3979 __I uint8_t RESERVED1[3];
3980 __IO uint8_t COMIIR; /*!< Interrupt Identification register */
3981 __I uint8_t RESERVED2[3];
3982 __IO uint8_t COMLCR; /*!< Line Control register */
3983 __I uint8_t RESERVED3[3];
3984 __IO uint8_t COMMCR; /*!< Module Control register */
3985 __I uint8_t RESERVED4[3];
3986 __IO uint8_t COMLSR; /*!< Line Status register */
3987 __I uint8_t RESERVED5[3];
3988 __IO uint8_t COMMSR; /*!< Modem Status register */
3989 __I uint8_t RESERVED6[11];
3990 __IO uint16_t COMFBR; /*!< Fractional baud rate divider register. */
3991 __I uint16_t RESERVED7;
3992 __IO uint16_t COMDIV; /*!< Baud rate Divisor register */
3993 __I uint16_t RESERVED8[3];
3994 __IO uint8_t COMCON; /*!< UART control register */
3995} ADI_UART_TypeDef;
3996#else // (__NO_MMR_STRUCTS__==0)
3997#define COMTX (*(volatile unsigned char *) 0x40005000)
3998#define COMRX (*(volatile unsigned char *) 0x40005000)
3999#define COMIEN (*(volatile unsigned char *) 0x40005004)
4000#define COMIIR (*(volatile unsigned char *) 0x40005008)
4001#define COMLCR (*(volatile unsigned char *) 0x4000500C)
4002#define COMMCR (*(volatile unsigned char *) 0x40005010)
4003#define COMLSR (*(volatile unsigned char *) 0x40005014)
4004#define COMMSR (*(volatile unsigned char *) 0x40005018)
4005#define COMFBR (*(volatile unsigned short int *) 0x40005024)
4006#define COMDIV (*(volatile unsigned short int *) 0x40005028)
4007#define COMCON (*(volatile unsigned char *) 0x40005030)
4008#endif // (__NO_MMR_STRUCTS__==0)
4009
4010/* Reset Value for COMTX*/
4011#define COMTX_RVAL 0x0
4012
4013/* COMTX[VALUE] - Value */
4014#define COMTX_VALUE_MSK (0xFF << 0 )
4015
4016/* Reset Value for COMRX*/
4017#define COMRX_RVAL 0x0
4018
4019/* COMRX[VALUE] - Value */
4020#define COMRX_VALUE_MSK (0xFF << 0 )
4021
4022/* Reset Value for COMIEN*/
4023#define COMIEN_RVAL 0x0
4024
4025/* COMIEN[EDMAR] - Enable DMA requests in transmit mode */
4026#define COMIEN_EDMAR_BBA (*(volatile unsigned long *) 0x420A0094)
4027#define COMIEN_EDMAR_MSK (0x1 << 5 )
4028#define COMIEN_EDMAR (0x1 << 5 )
4029#define COMIEN_EDMAR_DIS (0x0 << 5 ) /* DIS */
4030#define COMIEN_EDMAR_EN (0x1 << 5 ) /* EN */
4031
4032/* COMIEN[EDMAT] - Enable DMA requests in receive mode */
4033#define COMIEN_EDMAT_BBA (*(volatile unsigned long *) 0x420A0090)
4034#define COMIEN_EDMAT_MSK (0x1 << 4 )
4035#define COMIEN_EDMAT (0x1 << 4 )
4036#define COMIEN_EDMAT_DIS (0x0 << 4 ) /* DIS */
4037#define COMIEN_EDMAT_EN (0x1 << 4 ) /* EN */
4038
4039/* COMIEN[EDSSI] - Enable Modem Status interrupt */
4040#define COMIEN_EDSSI_BBA (*(volatile unsigned long *) 0x420A008C)
4041#define COMIEN_EDSSI_MSK (0x1 << 3 )
4042#define COMIEN_EDSSI (0x1 << 3 )
4043#define COMIEN_EDSSI_DIS (0x0 << 3 ) /* DIS */
4044#define COMIEN_EDSSI_EN (0x1 << 3 ) /* EN */
4045
4046/* COMIEN[ELSI] - Enable Rx status interrupt */
4047#define COMIEN_ELSI_BBA (*(volatile unsigned long *) 0x420A0088)
4048#define COMIEN_ELSI_MSK (0x1 << 2 )
4049#define COMIEN_ELSI (0x1 << 2 )
4050#define COMIEN_ELSI_DIS (0x0 << 2 ) /* DIS */
4051#define COMIEN_ELSI_EN (0x1 << 2 ) /* EN */
4052
4053/* COMIEN[ETBEI] - Enable transmit buffer empty interrupt */
4054#define COMIEN_ETBEI_BBA (*(volatile unsigned long *) 0x420A0084)
4055#define COMIEN_ETBEI_MSK (0x1 << 1 )
4056#define COMIEN_ETBEI (0x1 << 1 )
4057#define COMIEN_ETBEI_DIS (0x0 << 1 ) /* DIS */
4058#define COMIEN_ETBEI_EN (0x1 << 1 ) /* EN */
4059
4060/* COMIEN[ERBFI] - Enable receive buffer full interrupt */
4061#define COMIEN_ERBFI_BBA (*(volatile unsigned long *) 0x420A0080)
4062#define COMIEN_ERBFI_MSK (0x1 << 0 )
4063#define COMIEN_ERBFI (0x1 << 0 )
4064#define COMIEN_ERBFI_DIS (0x0 << 0 ) /* DIS */
4065#define COMIEN_ERBFI_EN (0x1 << 0 ) /* EN */
4066
4067/* Reset Value for COMIIR*/
4068#define COMIIR_RVAL 0x1
4069
4070/* COMIIR[STA] - Status bits. */
4071#define COMIIR_STA_MSK (0x3 << 1 )
4072#define COMIIR_STA_MODEMSTATUS (0x0 << 1 ) /* MODEMSTATUS - Modem status interrupt. */
4073#define COMIIR_STA_TXBUFEMPTY (0x1 << 1 ) /* TXBUFEMPTY - Transmit buffer empty interrupt. */
4074#define COMIIR_STA_RXBUFFULL (0x2 << 1 ) /* RXBUFFULL - Receive buffer full interrupt. Read RBR register to clear. */
4075#define COMIIR_STA_RXLINESTATUS (0x3 << 1 ) /* RXLINESTATUS - Receive line status interrupt. Read LSR register to clear. */
4076
4077/* COMIIR[NINT] - Interrupt flag. */
4078#define COMIIR_NINT_BBA (*(volatile unsigned long *) 0x420A0100)
4079#define COMIIR_NINT_MSK (0x1 << 0 )
4080#define COMIIR_NINT (0x1 << 0 )
4081#define COMIIR_NINT_CLR (0x0 << 0 ) /* CLR */
4082#define COMIIR_NINT_SET (0x1 << 0 ) /* SET */
4083
4084/* Reset Value for COMLCR*/
4085#define COMLCR_RVAL 0x0
4086
4087/* COMLCR[BRK] - Set Break. */
4088#define COMLCR_BRK_BBA (*(volatile unsigned long *) 0x420A0198)
4089#define COMLCR_BRK_MSK (0x1 << 6 )
4090#define COMLCR_BRK (0x1 << 6 )
4091#define COMLCR_BRK_DIS (0x0 << 6 ) /* DIS */
4092#define COMLCR_BRK_EN (0x1 << 6 ) /* EN */
4093
4094/* COMLCR[SP] - Stick Parity. */
4095#define COMLCR_SP_BBA (*(volatile unsigned long *) 0x420A0194)
4096#define COMLCR_SP_MSK (0x1 << 5 )
4097#define COMLCR_SP (0x1 << 5 )
4098#define COMLCR_SP_DIS (0x0 << 5 ) /* DIS */
4099#define COMLCR_SP_EN (0x1 << 5 ) /* EN */
4100
4101/* COMLCR[EPS] - Even Parity Select Bit. */
4102#define COMLCR_EPS_BBA (*(volatile unsigned long *) 0x420A0190)
4103#define COMLCR_EPS_MSK (0x1 << 4 )
4104#define COMLCR_EPS (0x1 << 4 )
4105#define COMLCR_EPS_DIS (0x0 << 4 ) /* DIS */
4106#define COMLCR_EPS_EN (0x1 << 4 ) /* EN */