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1/**************************************************************************//**
2 * @file ADUCM363.h
3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
4 * Device ADUCM360
5 * @version V3.10
6 * @date 23. November 2012
7 *
8 * @note
9 *
10 ******************************************************************************/
11/* Copyright (c) 2012 ARM LIMITED
12
13 All rights reserved.
14 Redistribution and use in source and binary forms, with or without
15 modification, are permitted provided that the following conditions are met:
16 - Redistributions of source code must retain the above copyright
17 notice, this list of conditions and the following disclaimer.
18 - Redistributions in binary form must reproduce the above copyright
19 notice, this list of conditions and the following disclaimer in the
20 documentation and/or other materials provided with the distribution.
21 - Neither the name of ARM nor the names of its contributors may be used
22 to endorse or promote products derived from this software without
23 specific prior written permission.
24 *
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
29 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 POSSIBILITY OF SUCH DAMAGE.
36
37 Portions Copyright (c) 2017-2019 Analog Devices, Inc.
38 ---------------------------------------------------------------------------*/
39
40/** @addtogroup CMSIS
41 * @{
42 */
43
44/** @addtogroup ADUCM363
45 * @{
46 */
47
48#ifndef __ADUCM363_H__
49#define __ADUCM363_H__
50
51#ifndef __NO_MMR_STRUCTS__
52// The new style CMSIS structure definitions for MMRs clash with
53// the old style defs. If the old style are required for compilation
54// then set __NO_MMR_STRUCTS__ to 0x1
55#define __NO_MMR_STRUCTS__ 0x0
56#endif
57
58#ifdef __cplusplus
59extern "C" {
60#endif
61
62
63
64/********************************************
65** Start of section using anonymous unions **
66*********************************************/
67
68#if defined(__ARMCC_VERSION)
69 #pragma push
70 #pragma anon_unions
71#elif defined(__CWCC__)
72 #pragma push
73 #pragma cpp_extensions on
74#elif defined(__GNUC__)
75 /* anonymous unions are enabled by default */
76#elif defined(__IAR_SYSTEMS_ICC__)
77 #pragma language=extended
78#else
79 #error Not supported compiler type
80#endif
81
82
83 /* Interrupt Number Definition */
84
85typedef enum {
86// ------------------------- Cortex-M3 Processor Exceptions Numbers -----------------------------
87 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
88 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
89 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
90 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation and No Match */
91 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory related Fault */
92 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
93 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
94 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
95 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
96 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
97// -------------------------- ADUCM363 Specific Interrupt Numbers ------------------------------
98 WUT_IRQn = 0, /*!< 0 WUT */
99 EINT0_IRQn = 1, /*!< 1 EINT0 */
100 EINT1_IRQn = 2, /*!< 2 EINT1 */
101 EINT2_IRQn = 3, /*!< 3 EINT2 */
102 EINT3_IRQn = 4, /*!< 4 EINT3 */
103 EINT4_IRQn = 5, /*!< 5 EINT4 */
104 EINT5_IRQn = 6, /*!< 6 EINT5 */
105 EINT6_IRQn = 7, /*!< 7 EINT6 */
106 EINT7_IRQn = 8, /*!< 8 EINT7 */
107 WDT_IRQn = 9, /*!< 9 WDT */
108 TIMER0_IRQn = 11, /*!< 11 TIMER0 */
109 TIMER1_IRQn = 12, /*!< 12 TIMER1 */
110 ADC1_IRQn = 14, /*!< 14 ADC1 */
111 SINC2_IRQn = 15, /*!< 15 SINC2 */
112 FLASH_IRQn = 16, /*!< 16 FLASH */
113 UART_IRQn = 17, /*!< 17 UART */
114 SPI0_IRQn = 18, /*!< 18 SPI0 */
115 SPI1_IRQn = 19, /*!< 19 SPI1 */
116 I2CS_IRQn = 20, /*!< 20 I2CS */
117 I2CM_IRQn = 21, /*!< 21 I2CM */
118 DMA_ERR_IRQn = 22, /*!< 22 DMA_ERR */
119 DMA_SPI1_TX_IRQn = 23, /*!< 23 DMA_SPI1_TX */
120 DMA_SPI1_RX_IRQn = 24, /*!< 24 DMA_SPI1_RX */
121 DMA_UART_TX_IRQn = 25, /*!< 25 DMA_UART_TX */
122 DMA_UART_RX_IRQn = 26, /*!< 26 DMA_UART_RX */
123 DMA_I2CS_TX_IRQn = 27, /*!< 27 DMA_I2CS_TX */
124 DMA_I2CS_RX_IRQn = 28, /*!< 28 DMA_I2CS_RX */
125 DMA_I2CM_TX_IRQn = 29, /*!< 29 DMA_I2CM_TX */
126 DMA_I2CM_RX_IRQn = 30, /*!< 30 DMA_I2CM_RX */
127 DMA_DAC_IRQn = 31, /*!< 31 DMA_DAC */
128 DMA_ADC1_IRQn = 33, /*!< 33 DMA_ADC1 */
129 DMA_SINC2_IRQn = 34, /*!< 34 DMA_SINC2 */
130 DMA_SPI0_TX_IRQn = 35, /*!< 35 DMA_SPI0_TX */
131 DMA_SPI0_RX_IRQn = 36, /*!< 36 DMA_SPI0_RX */
132 DMA_UART1_TX_IRQn = 37, /*!< 37 DMA_UART1_TX */
133 DMA_UART1_RX_IRQn = 38, /*!< 38 DMA_UART1_RX */
134 DMA_UART2_TX_IRQn = 39, /*!< 39 DMA_UART2_TX */
135 DMA_UART2_RX_IRQn = 40, /*!< 40 DMA_UART2_RX */
136 PWM_TRIP_IRQn = 41, /*!< 35 PWM_TRIP */
137 PWM_PAIR0_IRQn = 42, /*!< 36 PWM_PAIR0 */
138 PWM_PAIR1_IRQn = 43, /*!< 37 PWM_PAIR1 */
139 PWM_PAIR2_IRQn = 44, /*!< 38 PWM_PAIR2 */
140 UART1_IRQn = 47, /*!< 47 UART1 */
141 UART2_IRQn = 48, /*!< 48 UART2 */
142} IRQn_Type;
143
144
145/** @addtogroup Configuration_of_CMSIS
146 * @{
147 */
148
149/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M3 Processor and Core Peripherals */
150
151#define __CM3_REV 0x0201 /*!< Cortex-M3 Core Revision r2p0 */
152#define __MPU_PRESENT 0 /*!< MPU present or not */
153#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
154#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
155/** @} */ /* End of group Configuration_of_CMSIS */
156
157#include <core_cm3.h> /*!< Cortex-M3 processor and core peripherals */
158#include "system_ADuCM363.h" /*!< ADUCM363 System */
159
160/** @addtogroup Device_Peripheral_Registers
161 * @{
162 */
163
164
165
166/* ADCCON[ADCEN] - Enable Bit */
167#define ADCCON_ADCEN_MSK (0x1 << 19 )
168#define ADCCON_ADCEN (0x1 << 19 )
169#define ADCCON_ADCEN_DIS (0x0 << 19 ) /* DIS */
170#define ADCCON_ADCEN_EN (0x1 << 19 ) /* EN */
171
172/* ADCCON[ADCCODE] - ADC Output Coding bits */
173#define ADCCON_ADCCODE_MSK (0x1 << 18 )
174#define ADCCON_ADCCODE (0x1 << 18 )
175#define ADCCON_ADCCODE_INT (0x0 << 18 ) /* INT */
176#define ADCCON_ADCCODE_UINT (0x1 << 18 ) /* UINT */
177
178/* ADCCON[BUFPOWN] - Negative buffer power down */
179#define ADCCON_BUFPOWN_MSK (0x1 << 17 )
180#define ADCCON_BUFPOWN (0x1 << 17 )
181#define ADCCON_BUFPOWN_DIS (0x0 << 17 ) /* Disable powerdown - Negative buffer is enabled */
182#define ADCCON_BUFPOWN_EN (0x1 << 17 ) /* Enable powerdown - Negative buffer is disabled */
183
184/* ADCCON[BUFPOWP] - Positive buffer power down */
185#define ADCCON_BUFPOWP_MSK (0x1 << 16 )
186#define ADCCON_BUFPOWP (0x1 << 16 )
187#define ADCCON_BUFPOWP_DIS (0x0 << 16 ) /* Disable powerdown - Positive buffer is enabled */
188#define ADCCON_BUFPOWP_EN (0x1 << 16 ) /* Enable powerdown - Positive buffer is disabled */
189
190/* ADCCON[BUFBYPP] - Positive buffer bypass */
191#define ADCCON_BUFBYPP_MSK (0x1 << 15 )
192#define ADCCON_BUFBYPP (0x1 << 15 )
193#define ADCCON_BUFBYPP_DIS (0x0 << 15 ) /* DIS */
194#define ADCCON_BUFBYPP_EN (0x1 << 15 ) /* EN */
195
196/* ADCCON[BUFBYPN] - Negative buffer bypass */
197#define ADCCON_BUFBYPN_MSK (0x1 << 14 )
198#define ADCCON_BUFBYPN (0x1 << 14 )
199#define ADCCON_BUFBYPN_DIS (0x0 << 14 ) /* DIS */
200#define ADCCON_BUFBYPN_EN (0x1 << 14 ) /* EN */
201
202/* ADCCON[ADCREF] - Reference selection */
203#define ADCCON_ADCREF_MSK (0x3 << 12 )
204#define ADCCON_ADCREF_INTREF (0x0 << 12 ) /* INTREF */
205#define ADCCON_ADCREF_EXTREF (0x1 << 12 ) /* EXTREF */
206#define ADCCON_ADCREF_EXTREF2 (0x2 << 12 ) /* EXTREF2 */
207#define ADCCON_ADCREF_AVDDREF (0x3 << 12 ) /* AVDDREF */
208
209/* ADCCON[ADCDIAG] - Diagnostic Current bits bits */
210#define ADCCON_ADCDIAG_MSK (0x3 << 10 )
211#define ADCCON_ADCDIAG_DIAG_OFF (0x0 << 10 ) /* DIAG_OFF */
212#define ADCCON_ADCDIAG_DIAG_POS (0x1 << 10 ) /* DIAG_POS */
213#define ADCCON_ADCDIAG_DIAG_NEG (0x2 << 10 ) /* DIAG_NEG */
214#define ADCCON_ADCDIAG_DIAG_ALL (0x3 << 10 ) /* DIAG_ALL */
215
216/* ADCCON[ADCCP] - AIN+ bits */
217#define ADCCON_ADCCP_MSK (0x1F << 5 )
218#define ADCCON_ADCCP_AIN0 (0x0 << 5 ) /* AIN0 */
219#define ADCCON_ADCCP_AIN1 (0x1 << 5 ) /* AIN1 */
220#define ADCCON_ADCCP_AIN2 (0x2 << 5 ) /* AIN2 */
221#define ADCCON_ADCCP_AIN3 (0x3 << 5 ) /* AIN3 */
222#define ADCCON_ADCCP_AIN4 (0x4 << 5 ) /* AIN4 */
223#define ADCCON_ADCCP_AIN5 (0x5 << 5 ) /* AIN5 */
224#define ADCCON_ADCCP_AIN6 (0x6 << 5 ) /* AIN6 */
225#define ADCCON_ADCCP_AIN7 (0x7 << 5 ) /* AIN7 */
226#define ADCCON_ADCCP_AIN8 (0x8 << 5 ) /* AIN8 */
227#define ADCCON_ADCCP_AIN9 (0x9 << 5 ) /* AIN9 */
228#define ADCCON_ADCCP_AIN10 (0xA << 5 ) /* AIN10 */
229#define ADCCON_ADCCP_AIN11 (0xB << 5 ) /* AIN11 */
230#define ADCCON_ADCCP_DAC (0xC << 5 ) /* DAC */
231#define ADCCON_ADCCP_AVDD4 (0xD << 5 ) /* AVDD4 */
232#define ADCCON_ADCCP_IOVDD4 (0xE << 5 ) /* IOVDD4 */
233#define ADCCON_ADCCP_AGND (0xF << 5 ) /* AGND */
234#define ADCCON_ADCCP_TEMP (0x10 << 5 ) /* TEMP */
235
236/* ADCCON[ADCCN] - AIN- bits */
237#define ADCCON_ADCCN_MSK (0x1F << 0 )
238#define ADCCON_ADCCN_AIN0 (0x0 << 0 ) /* AIN0 */
239#define ADCCON_ADCCN_AIN1 (0x1 << 0 ) /* AIN1 */
240#define ADCCON_ADCCN_AIN2 (0x2 << 0 ) /* AIN2 */
241#define ADCCON_ADCCN_AIN3 (0x3 << 0 ) /* AIN3 */
242#define ADCCON_ADCCN_AIN4 (0x4 << 0 ) /* AIN4 */
243#define ADCCON_ADCCN_AIN5 (0x5 << 0 ) /* AIN5 */
244#define ADCCON_ADCCN_AIN6 (0x6 << 0 ) /* AIN6 */
245#define ADCCON_ADCCN_AIN7 (0x7 << 0 ) /* AIN7 */
246#define ADCCON_ADCCN_AIN8 (0x8 << 0 ) /* AIN8 */
247#define ADCCON_ADCCN_AIN9 (0x9 << 0 ) /* AIN9 */
248#define ADCCON_ADCCN_AIN10 (0xA << 0 ) /* AIN10 */
249#define ADCCON_ADCCN_AIN11 (0xB << 0 ) /* AIN11 */
250#define ADCCON_ADCCN_DAC (0xC << 0 ) /* DAC */
251#define ADCCON_ADCCN_AGND (0xF << 0 ) /* AGND */
252#define ADCCON_ADCCN_TEMP (0x11 << 0 ) /* TEMP */
253
254/* ADCMDE[PGA] - PGA Gain Select bit */
255#define ADCMDE_PGA_MSK (0xF << 4 )
256#define ADCMDE_PGA_G1 (0x0 << 4 ) /* G1 */
257#define ADCMDE_PGA_G2 (0x1 << 4 ) /* G2 */
258#define ADCMDE_PGA_G4 (0x2 << 4 ) /* G4 */
259#define ADCMDE_PGA_G8 (0x3 << 4 ) /* G8 */
260#define ADCMDE_PGA_G16 (0x4 << 4 ) /* G16 */
261#define ADCMDE_PGA_G32 (0x5 << 4 ) /* G32 */
262#define ADCMDE_PGA_G64 (0x6 << 4 ) /* G64 */
263#define ADCMDE_PGA_G128 (0x7 << 4 ) /* G128 */
264
265/* ADCMDE[ADCMOD2] - ADC modulator gain of 2 control bits */
266#define ADCMDE_ADCMOD2_MSK (0x1 << 3 )
267#define ADCMDE_ADCMOD2 (0x1 << 3 )
268#define ADCMDE_ADCMOD2_MOD2OFF (0x0 << 3 ) /* MOD2OFF */
269#define ADCMDE_ADCMOD2_MOD2ON (0x1 << 3 ) /* MOD2ON */
270
271/* ADCMDE[ADCMD] - ADC Mode bits */
272#define ADCMDE_ADCMD_MSK (0x7 << 0 )
273#define ADCMDE_ADCMD_OFF (0x0 << 0 ) /* OFF */
274#define ADCMDE_ADCMD_CONT (0x1 << 0 ) /* CONT */
275#define ADCMDE_ADCMD_SINGLE (0x2 << 0 ) /* SINGLE */
276#define ADCMDE_ADCMD_IDLE (0x3 << 0 ) /* IDLE */
277#define ADCMDE_ADCMD_INTOCAL (0x4 << 0 ) /* INTOCAL */
278#define ADCMDE_ADCMD_INTGCAL (0x5 << 0 ) /* INTGCAL */
279#define ADCMDE_ADCMD_SYSOCAL (0x6 << 0 ) /* SYSOCAL */
280#define ADCMDE_ADCMD_SYSGCAL (0x7 << 0 ) /* SYSGCAL */
281
282/* ADCMSKI[ATHEX] - ADC Accumulator Comparator Threshold status bit mask */
283#define ADCMSKI_ATHEX_MSK (0x1 << 3 )
284#define ADCMSKI_ATHEX (0x1 << 3 )
285#define ADCMSKI_ATHEX_DIS (0x0 << 3 ) /* DIS */
286#define ADCMSKI_ATHEX_EN (0x1 << 3 ) /* EN */
287
288/* ADCMSKI[THEX] - ADC comparator threshold mask */
289#define ADCMSKI_THEX_MSK (0x1 << 2 )
290#define ADCMSKI_THEX (0x1 << 2 )
291#define ADCMSKI_THEX_DIS (0x0 << 2 ) /* DIS */
292#define ADCMSKI_THEX_EN (0x1 << 2 ) /* EN */
293
294/* ADCMSKI[OVR] - ADC overrange bit mask. */
295#define ADCMSKI_OVR_MSK (0x1 << 1 )
296#define ADCMSKI_OVR (0x1 << 1 )
297#define ADCMSKI_OVR_DIS (0x0 << 1 ) /* DIS */
298#define ADCMSKI_OVR_EN (0x1 << 1 ) /* EN */
299
300/* ADCMSKI[RDY] - valid conversion result mask */
301#define ADCMSKI_RDY_MSK (0x1 << 0 )
302#define ADCMSKI_RDY (0x1 << 0 )
303#define ADCMSKI_RDY_DIS (0x0 << 0 ) /* DIS */
304#define ADCMSKI_RDY_EN (0x1 << 0 ) /* EN */
305
306/* ADCFLT[CHOP] - Enables System-Chopping bits */
307#define ADCFLT_CHOP_MSK (0x1 << 15 )
308#define ADCFLT_CHOP (0x1 << 15 )
309#define ADCFLT_CHOP_OFF (0x0 << 15 ) /* OFF */
310#define ADCFLT_CHOP_ON (0x1 << 15 ) /* ON */
311
312/* ADCFLT[RAVG2] - Enables a running Average-By-2 bits */
313#define ADCFLT_RAVG2_MSK (0x1 << 14 )
314#define ADCFLT_RAVG2 (0x1 << 14 )
315#define ADCFLT_RAVG2_OFF (0x0 << 14 ) /* OFF */
316#define ADCFLT_RAVG2_ON (0x1 << 14 ) /* ON */
317
318/* ADCFLT[SINC4EN] - Enable the Sinc4 filter instead of Sinc3 filter. */
319#define ADCFLT_SINC4EN_MSK (0x1 << 12 )
320#define ADCFLT_SINC4EN (0x1 << 12 )
321#define ADCFLT_SINC4EN_DIS (0x0 << 12 ) /* DIS */
322#define ADCFLT_SINC4EN_EN (0x1 << 12 ) /* EN */
323
324/* ADCFLT[AF] - Averaging filter */
325#define ADCFLT_AF_MSK (0xF << 8 )
326
327/* ADCFLT[NOTCH2] - Inserts a notch at FNOTCH2 */
328#define ADCFLT_NOTCH2_MSK (0x1 << 7 )
329#define ADCFLT_NOTCH2 (0x1 << 7 )
330#define ADCFLT_NOTCH2_DIS (0x0 << 7 ) /* DIS */
331#define ADCFLT_NOTCH2_EN (0x1 << 7 ) /* EN */
332
333/* ADCFLT[SF] - SINC Filter value */
334#define ADCFLT_SF_MSK (0x7F << 0 )
335
336/* TCON[EVENTEN] - Enable time capture of an event */
337#define TCON_EVENTEN_MSK (0x1 << 12 )
338#define TCON_EVENTEN (0x1 << 12 )
339#define TCON_EVENTEN_DIS (0x0 << 12 ) /* DIS */
340#define TCON_EVENTEN_EN (0x1 << 12 ) /* EN */
341
342/* TCON[EVENT] - Event Select, selects 1 of the available events. */
343#define TCON_EVENT_MSK (0xF << 8 )
344
345/* TCON[RLD] - Timer reload on write to clear register */
346#define TCON_RLD_MSK (0x1 << 7 )
347#define TCON_RLD (0x1 << 7 )
348#define TCON_RLD_DIS (0x0 << 7 ) /* DIS */
349#define TCON_RLD_EN (0x1 << 7 ) /* EN */
350
351/* TCON[CLK] - Clock Select */
352#define TCON_CLK_MSK (0x3 << 5 )
353#define TCON_CLK_UCLK (0x0 << 5 ) /* UCLK - System Clock */
354#define TCON_CLK_PCLK (0x1 << 5 ) /* PCLK - Peripheral clock */
355#define TCON_CLK_LFOSC (0x2 << 5 ) /* LFOSC - Internal 32 kHz Oscillator */
356#define TCON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL - External 32 kHz crystal */
357
358/* TCON[ENABLE] - Enable */
359#define TCON_ENABLE_MSK (0x1 << 4 )
360#define TCON_ENABLE (0x1 << 4 )
361#define TCON_ENABLE_DIS (0x0 << 4 ) /* DIS */
362#define TCON_ENABLE_EN (0x1 << 4 ) /* EN */
363
364/* TCON[MOD] - Mode */
365#define TCON_MOD_MSK (0x1 << 3 )
366#define TCON_MOD (0x1 << 3 )
367#define TCON_MOD_FREERUN (0x0 << 3 ) /* FREERUN */
368#define TCON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC */
369
370/* TCON[UP] - Count-up */
371#define TCON_UP_MSK (0x1 << 2 )
372#define TCON_UP (0x1 << 2 )
373#define TCON_UP_DIS (0x0 << 2 ) /* DIS */
374#define TCON_UP_EN (0x1 << 2 ) /* EN */
375
376/* TCON[PRE] - Prescaler */
377#define TCON_PRE_MSK (0x3 << 0 )
378#define TCON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
379#define TCON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
380#define TCON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
381#define TCON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 - If the selected clock source is UCLK then this setting results in a prescaler of 4. */
382
383/* TCLRI[CAP] - Clear captured event interrupt */
384#define TCLRI_CAP_MSK (0x1 << 1 )
385#define TCLRI_CAP (0x1 << 1 )
386#define TCLRI_CAP_CLR (0x1 << 1 ) /* CLR */
387
388/* TCLRI[TMOUT] - Clear timeout interrupt */
389#define TCLRI_TMOUT_MSK (0x1 << 0 )
390#define TCLRI_TMOUT (0x1 << 0 )
391#define TCLRI_TMOUT_CLR (0x1 << 0 ) /* CLR */
392
393/* TSTA[CLRI] - Value updated in the timer clock domain */
394#define TSTA_CLRI_MSK (0x1 << 7 )
395#define TSTA_CLRI (0x1 << 7 )
396#define TSTA_CLRI_CLR (0x0 << 7 ) /* CLR */
397#define TSTA_CLRI_SET (0x1 << 7 ) /* SET */
398
399/* TSTA[CON] - Ready to receive commands */
400#define TSTA_CON_MSK (0x1 << 6 )
401#define TSTA_CON (0x1 << 6 )
402#define TSTA_CON_CLR (0x0 << 6 ) /* CLR */
403#define TSTA_CON_SET (0x1 << 6 ) /* SET */
404
405/* TSTA[CAP] - Capture event pending */
406#define TSTA_CAP_MSK (0x1 << 1 )
407#define TSTA_CAP (0x1 << 1 )
408#define TSTA_CAP_CLR (0x0 << 1 ) /* CLR */
409#define TSTA_CAP_SET (0x1 << 1 ) /* SET */
410
411/* TSTA[TMOUT] - Time out event occurred */
412#define TSTA_TMOUT_MSK (0x1 << 0 )
413#define TSTA_TMOUT (0x1 << 0 )
414#define TSTA_TMOUT_CLR (0x0 << 0 ) /* CLR */
415#define TSTA_TMOUT_SET (0x1 << 0 ) /* SET */
416
417/* GPCON[CON7] - Configuration bits for P0.7 */
418#define GPCON_CON7_MSK (0x3 << 14 )
419
420/* GPCON[CON6] - Configuration bits for P0.6 */
421#define GPCON_CON6_MSK (0x3 << 12 )
422
423/* GPCON[CON5] - Configuration bits for P0.5 */
424#define GPCON_CON5_MSK (0x3 << 10 )
425
426/* GPCON[CON4] - Configuration bits for P0.4 */
427#define GPCON_CON4_MSK (0x3 << 8 )
428
429/* GPCON[CON3] - Configuration bits for P0.3 */
430#define GPCON_CON3_MSK (0x3 << 6 )
431
432/* GPCON[CON2] - Configuration bits for P0.2 */
433#define GPCON_CON2_MSK (0x3 << 4 )
434
435/* GPCON[CON1] - Configuration bits for P0.1 */
436#define GPCON_CON1_MSK (0x3 << 2 )
437
438/* GPCON[CON0] - Configuration bits for P0.0 */
439#define GPCON_CON0_MSK (0x3 << 0 )
440
441/* GPOEN[OEN7] - Direction for port pin */
442#define GPOEN_OEN7_MSK (0x1 << 7 )
443#define GPOEN_OEN7 (0x1 << 7 )
444#define GPOEN_OEN7_IN (0x0 << 7 ) /* IN */
445#define GPOEN_OEN7_OUT (0x1 << 7 ) /* OUT */
446
447/* GPOEN[OEN6] - Direction for port pin */
448#define GPOEN_OEN6_MSK (0x1 << 6 )
449#define GPOEN_OEN6 (0x1 << 6 )
450#define GPOEN_OEN6_IN (0x0 << 6 ) /* IN */
451#define GPOEN_OEN6_OUT (0x1 << 6 ) /* OUT */
452
453/* GPOEN[OEN5] - Direction for port pin */
454#define GPOEN_OEN5_MSK (0x1 << 5 )
455#define GPOEN_OEN5 (0x1 << 5 )
456#define GPOEN_OEN5_IN (0x0 << 5 ) /* IN */
457#define GPOEN_OEN5_OUT (0x1 << 5 ) /* OUT */
458
459/* GPOEN[OEN4] - Direction for port pin */
460#define GPOEN_OEN4_MSK (0x1 << 4 )
461#define GPOEN_OEN4 (0x1 << 4 )
462#define GPOEN_OEN4_IN (0x0 << 4 ) /* IN */
463#define GPOEN_OEN4_OUT (0x1 << 4 ) /* OUT */
464
465/* GPOEN[OEN3] - Direction for port pin */
466#define GPOEN_OEN3_MSK (0x1 << 3 )
467#define GPOEN_OEN3 (0x1 << 3 )
468#define GPOEN_OEN3_IN (0x0 << 3 ) /* IN */
469#define GPOEN_OEN3_OUT (0x1 << 3 ) /* OUT */
470
471/* GPOEN[OEN2] - Direction for port pin */
472#define GPOEN_OEN2_MSK (0x1 << 2 )
473#define GPOEN_OEN2 (0x1 << 2 )
474#define GPOEN_OEN2_IN (0x0 << 2 ) /* IN */
475#define GPOEN_OEN2_OUT (0x1 << 2 ) /* OUT */
476
477/* GPOEN[OEN1] - Direction for port pin */
478#define GPOEN_OEN1_MSK (0x1 << 1 )
479#define GPOEN_OEN1 (0x1 << 1 )
480#define GPOEN_OEN1_IN (0x0 << 1 ) /* IN */
481#define GPOEN_OEN1_OUT (0x1 << 1 ) /* OUT */
482
483/* GPOEN[OEN0] - Direction for port pin */
484#define GPOEN_OEN0_MSK (0x1 << 0 )
485#define GPOEN_OEN0 (0x1 << 0 )
486#define GPOEN_OEN0_IN (0x0 << 0 ) /* IN */
487#define GPOEN_OEN0_OUT (0x1 << 0 ) /* OUT */
488
489/* GPIN[IN7] - Input for port pin */
490#define GPIN_IN7_MSK (0x1 << 7 )
491#define GPIN_IN7 (0x1 << 7 )
492#define GPIN_IN7_LOW (0x0 << 7 ) /* LOW */
493#define GPIN_IN7_HIGH (0x1 << 7 ) /* HIGH */
494
495/* GPIN[IN6] - Input for port pin */
496#define GPIN_IN6_MSK (0x1 << 6 )
497#define GPIN_IN6 (0x1 << 6 )
498#define GPIN_IN6_LOW (0x0 << 6 ) /* LOW */
499#define GPIN_IN6_HIGH (0x1 << 6 ) /* HIGH */
500
501/* GPIN[IN5] - Input for port pin */
502#define GPIN_IN5_MSK (0x1 << 5 )
503#define GPIN_IN5 (0x1 << 5 )
504#define GPIN_IN5_LOW (0x0 << 5 ) /* LOW */
505#define GPIN_IN5_HIGH (0x1 << 5 ) /* HIGH */
506
507/* GPIN[IN4] - Input for port pin */
508#define GPIN_IN4_MSK (0x1 << 4 )
509#define GPIN_IN4 (0x1 << 4 )
510#define GPIN_IN4_LOW (0x0 << 4 ) /* LOW */
511#define GPIN_IN4_HIGH (0x1 << 4 ) /* HIGH */
512
513/* GPIN[IN3] - Input for port pin */
514#define GPIN_IN3_MSK (0x1 << 3 )
515#define GPIN_IN3 (0x1 << 3 )
516#define GPIN_IN3_LOW (0x0 << 3 ) /* LOW */
517#define GPIN_IN3_HIGH (0x1 << 3 ) /* HIGH */
518
519/* GPIN[IN2] - Input for port pin */
520#define GPIN_IN2_MSK (0x1 << 2 )
521#define GPIN_IN2 (0x1 << 2 )
522#define GPIN_IN2_LOW (0x0 << 2 ) /* LOW */
523#define GPIN_IN2_HIGH (0x1 << 2 ) /* HIGH */
524
525/* GPIN[IN1] - Input for port pin */
526#define GPIN_IN1_MSK (0x1 << 1 )
527#define GPIN_IN1 (0x1 << 1 )
528#define GPIN_IN1_LOW (0x0 << 1 ) /* LOW */
529#define GPIN_IN1_HIGH (0x1 << 1 ) /* HIGH */
530
531/* GPIN[IN0] - Input for port pin */
532#define GPIN_IN0_MSK (0x1 << 0 )
533#define GPIN_IN0 (0x1 << 0 )
534#define GPIN_IN0_LOW (0x0 << 0 ) /* LOW */
535#define GPIN_IN0_HIGH (0x1 << 0 ) /* HIGH */
536
537/* GPOUT[OUT7] - Output for port pin */
538#define GPOUT_OUT7_MSK (0x1 << 7 )
539#define GPOUT_OUT7 (0x1 << 7 )
540#define GPOUT_OUT7_LOW (0x0 << 7 ) /* LOW */
541#define GPOUT_OUT7_HIGH (0x1 << 7 ) /* HIGH */
542
543/* GPOUT[OUT6] - Output for port pin */
544#define GPOUT_OUT6_MSK (0x1 << 6 )
545#define GPOUT_OUT6 (0x1 << 6 )
546#define GPOUT_OUT6_LOW (0x0 << 6 ) /* LOW */
547#define GPOUT_OUT6_HIGH (0x1 << 6 ) /* HIGH */
548
549/* GPOUT[OUT5] - Output for port pin */
550#define GPOUT_OUT5_MSK (0x1 << 5 )
551#define GPOUT_OUT5 (0x1 << 5 )
552#define GPOUT_OUT5_LOW (0x0 << 5 ) /* LOW */
553#define GPOUT_OUT5_HIGH (0x1 << 5 ) /* HIGH */
554
555/* GPOUT[OUT4] - Output for port pin */
556#define GPOUT_OUT4_MSK (0x1 << 4 )
557#define GPOUT_OUT4 (0x1 << 4 )
558#define GPOUT_OUT4_LOW (0x0 << 4 ) /* LOW */
559#define GPOUT_OUT4_HIGH (0x1 << 4 ) /* HIGH */
560
561/* GPOUT[OUT3] - Output for port pin */
562#define GPOUT_OUT3_MSK (0x1 << 3 )
563#define GPOUT_OUT3 (0x1 << 3 )
564#define GPOUT_OUT3_LOW (0x0 << 3 ) /* LOW */
565#define GPOUT_OUT3_HIGH (0x1 << 3 ) /* HIGH */
566
567/* GPOUT[OUT2] - Output for port pin */
568#define GPOUT_OUT2_MSK (0x1 << 2 )
569#define GPOUT_OUT2 (0x1 << 2 )
570#define GPOUT_OUT2_LOW (0x0 << 2 ) /* LOW */
571#define GPOUT_OUT2_HIGH (0x1 << 2 ) /* HIGH */
572
573/* GPOUT[OUT1] - Output for port pin */
574#define GPOUT_OUT1_MSK (0x1 << 1 )
575#define GPOUT_OUT1 (0x1 << 1 )
576#define GPOUT_OUT1_LOW (0x0 << 1 ) /* LOW */
577#define GPOUT_OUT1_HIGH (0x1 << 1 ) /* HIGH */
578
579/* GPOUT[OUT0] - Output for port pin */
580#define GPOUT_OUT0_MSK (0x1 << 0 )
581#define GPOUT_OUT0 (0x1 << 0 )
582#define GPOUT_OUT0_LOW (0x0 << 0 ) /* LOW */
583#define GPOUT_OUT0_HIGH (0x1 << 0 ) /* HIGH */
584
585/* GPSET[SET7] - Set Output High for port pin */
586#define GPSET_SET7_MSK (0x1 << 7 )
587#define GPSET_SET7 (0x1 << 7 )
588#define GPSET_SET7_SET (0x1 << 7 ) /* SET */
589
590/* GPSET[SET6] - Set Output High for port pin */
591#define GPSET_SET6_MSK (0x1 << 6 )
592#define GPSET_SET6 (0x1 << 6 )
593#define GPSET_SET6_SET (0x1 << 6 ) /* SET */
594
595/* GPSET[SET5] - Set Output High for port pin */
596#define GPSET_SET5_MSK (0x1 << 5 )
597#define GPSET_SET5 (0x1 << 5 )
598#define GPSET_SET5_SET (0x1 << 5 ) /* SET */
599
600/* GPSET[SET4] - Set Output High for port pin */
601#define GPSET_SET4_MSK (0x1 << 4 )
602#define GPSET_SET4 (0x1 << 4 )
603#define GPSET_SET4_SET (0x1 << 4 ) /* SET */
604
605/* GPSET[SET3] - Set Output High for port pin */
606#define GPSET_SET3_MSK (0x1 << 3 )
607#define GPSET_SET3 (0x1 << 3 )
608#define GPSET_SET3_SET (0x1 << 3 ) /* SET */
609
610/* GPSET[SET2] - Set Output High for port pin */
611#define GPSET_SET2_MSK (0x1 << 2 )
612#define GPSET_SET2 (0x1 << 2 )
613#define GPSET_SET2_SET (0x1 << 2 ) /* SET */
614
615/* GPSET[SET1] - Set Output High for port pin */
616#define GPSET_SET1_MSK (0x1 << 1 )
617#define GPSET_SET1 (0x1 << 1 )
618#define GPSET_SET1_SET (0x1 << 1 ) /* SET */
619
620/* GPSET[SET0] - Set Output High for port pin */
621#define GPSET_SET0_MSK (0x1 << 0 )
622#define GPSET_SET0 (0x1 << 0 )
623#define GPSET_SET0_SET (0x1 << 0 ) /* SET */
624
625/* GPCLR[CLR7] - Set Output Low for port pin */
626#define GPCLR_CLR7_MSK (0x1 << 7 )
627#define GPCLR_CLR7 (0x1 << 7 )
628#define GPCLR_CLR7_CLR (0x1 << 7 ) /* CLR */
629
630/* GPCLR[CLR6] - Set Output Low for port pin */
631#define GPCLR_CLR6_MSK (0x1 << 6 )
632#define GPCLR_CLR6 (0x1 << 6 )
633#define GPCLR_CLR6_CLR (0x1 << 6 ) /* CLR */
634
635/* GPCLR[CLR5] - Set Output Low for port pin */
636#define GPCLR_CLR5_MSK (0x1 << 5 )
637#define GPCLR_CLR5 (0x1 << 5 )
638#define GPCLR_CLR5_CLR (0x1 << 5 ) /* CLR */
639
640/* GPCLR[CLR4] - Set Output Low for port pin */
641#define GPCLR_CLR4_MSK (0x1 << 4 )
642#define GPCLR_CLR4 (0x1 << 4 )
643#define GPCLR_CLR4_CLR (0x1 << 4 ) /* CLR */
644
645/* GPCLR[CLR3] - Set Output Low for port pin */
646#define GPCLR_CLR3_MSK (0x1 << 3 )
647#define GPCLR_CLR3 (0x1 << 3 )
648#define GPCLR_CLR3_CLR (0x1 << 3 ) /* CLR */
649
650/* GPCLR[CLR2] - Set Output Low for port pin */
651#define GPCLR_CLR2_MSK (0x1 << 2 )
652#define GPCLR_CLR2 (0x1 << 2 )
653#define GPCLR_CLR2_CLR (0x1 << 2 ) /* CLR */
654
655/* GPCLR[CLR1] - Set Output Low for port pin */
656#define GPCLR_CLR1_MSK (0x1 << 1 )
657#define GPCLR_CLR1 (0x1 << 1 )
658#define GPCLR_CLR1_CLR (0x1 << 1 ) /* CLR */
659
660/* GPCLR[CLR0] - Set Output Low for port pin */
661#define GPCLR_CLR0_MSK (0x1 << 0 )
662#define GPCLR_CLR0 (0x1 << 0 )
663#define GPCLR_CLR0_CLR (0x1 << 0 ) /* CLR */
664
665/* GPTGL[TGL7] - Toggle Output for port pin */
666#define GPTGL_TGL7_MSK (0x1 << 7 )
667#define GPTGL_TGL7 (0x1 << 7 )
668#define GPTGL_TGL7_TGL (0x1 << 7 ) /* TGL */
669
670/* GPTGL[TGL6] - Toggle Output for port pin */
671#define GPTGL_TGL6_MSK (0x1 << 6 )
672#define GPTGL_TGL6 (0x1 << 6 )
673#define GPTGL_TGL6_TGL (0x1 << 6 ) /* TGL */
674
675/* GPTGL[TGL5] - Toggle Output for port pin */
676#define GPTGL_TGL5_MSK (0x1 << 5 )
677#define GPTGL_TGL5 (0x1 << 5 )
678#define GPTGL_TGL5_TGL (0x1 << 5 ) /* TGL */
679
680/* GPTGL[TGL4] - Toggle Output for port pin */
681#define GPTGL_TGL4_MSK (0x1 << 4 )
682#define GPTGL_TGL4 (0x1 << 4 )
683#define GPTGL_TGL4_TGL (0x1 << 4 ) /* TGL */
684
685/* GPTGL[TGL3] - Toggle Output for port pin */
686#define GPTGL_TGL3_MSK (0x1 << 3 )
687#define GPTGL_TGL3 (0x1 << 3 )
688#define GPTGL_TGL3_TGL (0x1 << 3 ) /* TGL */
689
690/* GPTGL[TGL2] - Toggle Output for port pin */
691#define GPTGL_TGL2_MSK (0x1 << 2 )
692#define GPTGL_TGL2 (0x1 << 2 )
693#define GPTGL_TGL2_TGL (0x1 << 2 ) /* TGL */
694
695/* GPTGL[TGL1] - Toggle Output for port pin */
696#define GPTGL_TGL1_MSK (0x1 << 1 )
697#define GPTGL_TGL1 (0x1 << 1 )
698#define GPTGL_TGL1_TGL (0x1 << 1 ) /* TGL */
699
700/* GPTGL[TGL0] - Toggle Output for port pin */
701#define GPTGL_TGL0_MSK (0x1 << 0 )
702#define GPTGL_TGL0 (0x1 << 0 )
703#define GPTGL_TGL0_TGL (0x1 << 0 ) /* TGL */
704
705/* SPIDIV[BCRST] - Bit counter reset */
706#define SPIDIV_BCRST_MSK (0x1 << 7 )
707#define SPIDIV_BCRST (0x1 << 7 )
708#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS */
709#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN */
710
711/* SPIDIV[DIV] - Factor used to divide UCLK to generate the serial clock */
712#define SPIDIV_DIV_MSK (0x3F << 0 )
713
714/* SPICON[MOD] - SPI IRQ Mode bits */
715#define SPICON_MOD_MSK (0x3 << 14 )
716#define SPICON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1 */
717#define SPICON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2 */
718#define SPICON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3 */
719#define SPICON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4 */
720
721/* SPICON[TFLUSH] - TX FIFO Flush Enable bit */
722#define SPICON_TFLUSH_MSK (0x1 << 13 )
723#define SPICON_TFLUSH (0x1 << 13 )
724#define SPICON_TFLUSH_DIS (0x0 << 13 ) /* DIS */
725#define SPICON_TFLUSH_EN (0x1 << 13 ) /* EN */
726
727/* SPICON[RFLUSH] - RX FIFO Flush Enable bit */
728#define SPICON_RFLUSH_MSK (0x1 << 12 )
729#define SPICON_RFLUSH (0x1 << 12 )
730#define SPICON_RFLUSH_DIS (0x0 << 12 ) /* DIS */
731#define SPICON_RFLUSH_EN (0x1 << 12 ) /* EN */
732
733/* SPICON[CON] - Continuous transfer enable */
734#define SPICON_CON_MSK (0x1 << 11 )
735#define SPICON_CON (0x1 << 11 )
736#define SPICON_CON_DIS (0x0 << 11 ) /* DIS */
737#define SPICON_CON_EN (0x1 << 11 ) /* EN */
738
739/* SPICON[LOOPBACK] - Loopback enable bit */
740#define SPICON_LOOPBACK_MSK (0x1 << 10 )
741#define SPICON_LOOPBACK (0x1 << 10 )
742#define SPICON_LOOPBACK_DIS (0x0 << 10 ) /* DIS */
743#define SPICON_LOOPBACK_EN (0x1 << 10 ) /* EN */
744
745/* SPICON[SOEN] - Slave MISO output enable bit */
746#define SPICON_SOEN_MSK (0x1 << 9 )
747#define SPICON_SOEN (0x1 << 9 )
748#define SPICON_SOEN_DIS (0x0 << 9 ) /* DIS */
749#define SPICON_SOEN_EN (0x1 << 9 ) /* EN */
750
751/* SPICON[RXOF] - RX Oveflow Overwrite enable */
752#define SPICON_RXOF_MSK (0x1 << 8 )
753#define SPICON_RXOF (0x1 << 8 )
754#define SPICON_RXOF_DIS (0x0 << 8 ) /* DIS */
755#define SPICON_RXOF_EN (0x1 << 8 ) /* EN */
756
757/* SPICON[ZEN] - Transmit zeros when empty */
758#define SPICON_ZEN_MSK (0x1 << 7 )
759#define SPICON_ZEN (0x1 << 7 )
760#define SPICON_ZEN_DIS (0x0 << 7 ) /* DIS */
761#define SPICON_ZEN_EN (0x1 << 7 ) /* EN */
762
763/* SPICON[TIM] - Transfer and interrupt mode */
764#define SPICON_TIM_MSK (0x1 << 6 )
765#define SPICON_TIM (0x1 << 6 )
766#define SPICON_TIM_RXRD (0x0 << 6 ) /* RXRD - Cleared by user to initiate transfer with a read of the SPIRX register */
767#define SPICON_TIM_TXWR (0x1 << 6 ) /* TXWR - Set by user to initiate transfer with a write to the SPITX register. */
768
769/* SPICON[LSB] - LSB First Transfer enable */
770#define SPICON_LSB_MSK (0x1 << 5 )
771#define SPICON_LSB (0x1 << 5 )
772#define SPICON_LSB_DIS (0x0 << 5 ) /* DIS */
773#define SPICON_LSB_EN (0x1 << 5 ) /* EN */
774
775/* SPICON[WOM] - Wired OR enable */
776#define SPICON_WOM_MSK (0x1 << 4 )
777#define SPICON_WOM (0x1 << 4 )
778#define SPICON_WOM_DIS (0x0 << 4 ) /* DIS */
779#define SPICON_WOM_EN (0x1 << 4 ) /* EN */
780
781/* SPICON[CPOL] - Clock polarity mode */
782#define SPICON_CPOL_MSK (0x1 << 3 )
783#define SPICON_CPOL (0x1 << 3 )
784#define SPICON_CPOL_LOW (0x0 << 3 ) /* LOW */
785#define SPICON_CPOL_HIGH (0x1 << 3 ) /* HIGH */
786
787/* SPICON[CPHA] - Clock phase mode */
788#define SPICON_CPHA_MSK (0x1 << 2 )
789#define SPICON_CPHA (0x1 << 2 )
790#define SPICON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING */
791#define SPICON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING */
792
793/* SPICON[MASEN] - Master enable */
794#define SPICON_MASEN_MSK (0x1 << 1 )
795#define SPICON_MASEN (0x1 << 1 )
796#define SPICON_MASEN_DIS (0x0 << 1 ) /* DIS */
797#define SPICON_MASEN_EN (0x1 << 1 ) /* EN */
798
799/* SPICON[ENABLE] - SPI Enable bit */
800#define SPICON_ENABLE_MSK (0x1 << 0 )
801#define SPICON_ENABLE (0x1 << 0 )
802#define SPICON_ENABLE_DIS (0x0 << 0 ) /* DIS */
803#define SPICON_ENABLE_EN (0x1 << 0 ) /* EN */
804
805/* SPIDMA[IENRXDMA] - Enable receive DMA request */
806#define SPIDMA_IENRXDMA_MSK (0x1 << 2 )
807#define SPIDMA_IENRXDMA (0x1 << 2 )
808#define SPIDMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS */
809#define SPIDMA_IENRXDMA_EN (0x1 << 2 ) /* EN */
810
811/* SPIDMA[IENTXDMA] - Enable transmit DMA request */
812#define SPIDMA_IENTXDMA_MSK (0x1 << 1 )
813#define SPIDMA_IENTXDMA (0x1 << 1 )
814#define SPIDMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS */
815#define SPIDMA_IENTXDMA_EN (0x1 << 1 ) /* EN */
816
817/* SPIDMA[ENABLE] - Enable DMA for data transfer */
818#define SPIDMA_ENABLE_MSK (0x1 << 0 )
819#define SPIDMA_ENABLE (0x1 << 0 )
820#define SPIDMA_ENABLE_DIS (0x0 << 0 ) /* DIS */
821#define SPIDMA_ENABLE_EN (0x1 << 0 ) /* EN */
822
823/* SPISTA[CSERR] - Detected an abrupt CS deassertion */
824#define SPISTA_CSERR_MSK (0x1 << 12 )
825#define SPISTA_CSERR (0x1 << 12 )
826#define SPISTA_CSERR_CLR (0x0 << 12 ) /* CLR */
827#define SPISTA_CSERR_SET (0x1 << 12 ) /* SET */
828
829/* SPISTA[CSRSG] - Detected an abrupt CS deassertion */
830#define SPISTA_CSRSG_MSK (0x1 << 14 )
831#define SPISTA_CSRSG (0x1 << 14 )
832#define SPISTA_CSRSG_CLR (0x0 << 14 ) /* CLR */
833#define SPISTA_CSRSG_SET (0x1 << 14 ) /* SET */
834
835/* SPISTA[RXS] - Set when there are more bytes in the RX FIFO than the TIM bit says */
836#define SPISTA_RXS_MSK (0x1 << 11 )
837#define SPISTA_RXS (0x1 << 11 )
838#define SPISTA_RXS_CLR (0x0 << 11 ) /* CLR */
839#define SPISTA_RXS_SET (0x1 << 11 ) /* SET */
840
841/* SPISTA[RXFSTA] - Receive FIFO Status */
842#define SPISTA_RXFSTA_MSK (0x7 << 8 )
843#define SPISTA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY */
844#define SPISTA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE */
845#define SPISTA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES */
846#define SPISTA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES */
847#define SPISTA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES */
848
849/* SPISTA[RXOF] - Receive FIFO overflow */
850#define SPISTA_RXOF_MSK (0x1 << 7 )
851#define SPISTA_RXOF (0x1 << 7 )
852#define SPISTA_RXOF_CLR (0x0 << 7 ) /* CLR */
853#define SPISTA_RXOF_SET (0x1 << 7 ) /* SET */
854
855/* SPISTA[RX] - Set when a receive interrupt occurs */
856#define SPISTA_RX_MSK (0x1 << 6 )
857#define SPISTA_RX (0x1 << 6 )
858#define SPISTA_RX_CLR (0x0 << 6 ) /* CLR */
859#define SPISTA_RX_SET (0x1 << 6 ) /* SET */
860
861/* SPISTA[TX] - Set when a transmit interrupt occurs */
862#define SPISTA_TX_MSK (0x1 << 5 )
863#define SPISTA_TX (0x1 << 5 )
864#define SPISTA_TX_CLR (0x0 << 5 ) /* CLR */
865#define SPISTA_TX_SET (0x1 << 5 ) /* SET */
866
867/* SPISTA[TXUR] - Transmit FIFO underflow */
868#define SPISTA_TXUR_MSK (0x1 << 4 )
869#define SPISTA_TXUR (0x1 << 4 )
870#define SPISTA_TXUR_CLR (0x0 << 4 ) /* CLR */
871#define SPISTA_TXUR_SET (0x1 << 4 ) /* SET */
872
873/* SPISTA[TXFSTA] - transmit FIFO Status */
874#define SPISTA_TXFSTA_MSK (0x7 << 1 )
875#define SPISTA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY */
876#define SPISTA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE */
877#define SPISTA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES */
878#define SPISTA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES */
879#define SPISTA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES */
880
881/* SPISTA[IRQ] - Interrupt status bit */
882#define SPISTA_IRQ_MSK (0x1 << 0 )
883#define SPISTA_IRQ (0x1 << 0 )
884#define SPISTA_IRQ_CLR (0x0 << 0 ) /* CLR */
885#define SPISTA_IRQ_SET (0x1 << 0 ) /* SET */
886
887/* SPIDIV[BCRST] - Bit counter reset */
888#define SPIDIV_BCRST_MSK (0x1 << 7 )
889#define SPIDIV_BCRST (0x1 << 7 )
890#define SPIDIV_BCRST_DIS (0x0 << 7 ) /* DIS */
891#define SPIDIV_BCRST_EN (0x1 << 7 ) /* EN */
892
893/* SPIDIV[DIV] - Factor used to divide UCLK to generate the serial clock */
894#define SPIDIV_DIV_MSK (0x3F << 0 )
895// ------------------------------------------------------------------------------------------------
896// ----- T0 -----
897// ------------------------------------------------------------------------------------------------
898
899
900/**
901 * @brief Timer 0 (pADI_TM0)
902 */
903
904#if (__NO_MMR_STRUCTS__==0)
905typedef struct { /*!< pADI_TM0 Structure */
906 __IO uint16_t LD; /*!< 16-bit load value */
907 __I uint16_t RESERVED0;
908 __IO uint16_t VAL; /*!< "16-bit timer value, read only." */
909 __I uint16_t RESERVED1;
910 __IO uint16_t CON; /*!< Control Register */
911 __I uint16_t RESERVED2;
912 __IO uint16_t CLRI; /*!< Clear interrupt register */
913 __I uint16_t RESERVED3;
914 __IO uint16_t CAP; /*!< Capture Register */
915 __I uint16_t RESERVED4[5];
916 __IO uint16_t STA; /*!< Status Register */
917} ADI_TIMER_TypeDef;
918#else // (__NO_MMR_STRUCTS__==0)
919#define T0LD (*(volatile unsigned short int *) 0x40000000)
920#define T0VAL (*(volatile unsigned short int *) 0x40000004)
921#define T0CON (*(volatile unsigned short int *) 0x40000008)
922#define T0CLRI (*(volatile unsigned short int *) 0x4000000C)
923#define T0CAP (*(volatile unsigned short int *) 0x40000010)
924#define T0STA (*(volatile unsigned short int *) 0x4000001C)
925#endif // (__NO_MMR_STRUCTS__==0)
926
927/* Reset Value for T0LD*/
928#define T0LD_RVAL 0x0
929
930/* T0LD[VALUE] - Load value */
931#define T0LD_VALUE_MSK (0xFFFF << 0 )
932
933/* Reset Value for T0VAL*/
934#define T0VAL_RVAL 0x0
935
936/* T0VAL[VALUE] - Current value */
937#define T0VAL_VALUE_MSK (0xFFFF << 0 )
938
939/* Reset Value for T0CON*/
940#define T0CON_RVAL 0xA
941
942/* T0CON[EVENTEN] - Enable time capture of an event */
943#define T0CON_EVENTEN_BBA (*(volatile unsigned long *) 0x42000130)
944#define T0CON_EVENTEN_MSK (0x1 << 12 )
945#define T0CON_EVENTEN (0x1 << 12 )
946#define T0CON_EVENTEN_DIS (0x0 << 12 ) /* DIS */
947#define T0CON_EVENTEN_EN (0x1 << 12 ) /* EN */
948
949/* T0CON[EVENT] - Event Select, selects 1 of the available events. */
950#define T0CON_EVENT_MSK (0xF << 8 )
951#define T0CON_EVENT_T2 (0x0 << 8 ) /* T2 - Wakeup Timer */
952#define T0CON_EVENT_EXT0 (0x1 << 8 ) /* EXT0 - External interrupt 0 */
953#define T0CON_EVENT_EXT1 (0x2 << 8 ) /* EXT1 - External interrupt 1 */
954#define T0CON_EVENT_EXT2 (0x3 << 8 ) /* EXT2 - External interrupt 2 */
955#define T0CON_EVENT_EXT3 (0x4 << 8 ) /* EXT3 - External interrupt 3 */
956#define T0CON_EVENT_EXT4 (0x5 << 8 ) /* EXT4 - External interrupt 4 */
957#define T0CON_EVENT_EXT5 (0x6 << 8 ) /* EXT5 - External interrupt 5 */
958#define T0CON_EVENT_EXT6 (0x7 << 8 ) /* EXT6 - External interrupt 6 */
959#define T0CON_EVENT_EXT7 (0x8 << 8 ) /* EXT7 - External interrupt 7 */
960#define T0CON_EVENT_T3 (0x9 << 8 ) /* T3 - Watchdog timer */
961#define T0CON_EVENT_T1 (0xA << 8 ) /* T1 - Timer1 */
962#define T0CON_EVENT_ADC1 (0xC << 8 ) /* ADC1 - ADC1 */
963#define T0CON_EVENT_STEP (0xD << 8 ) /* STEP - STEP */
964#define T0CON_EVENT_DMADONE (0xE << 8 ) /* DMADONE */
965#define T0CON_EVENT_FEE (0xF << 8 ) /* FEE - Flash controller */
966
967/* T0CON[RLD] - Timer reload on write to clear register */
968#define T0CON_RLD_BBA (*(volatile unsigned long *) 0x4200011C)
969#define T0CON_RLD_MSK (0x1 << 7 )
970#define T0CON_RLD (0x1 << 7 )
971#define T0CON_RLD_DIS (0x0 << 7 ) /* DIS */
972#define T0CON_RLD_EN (0x1 << 7 ) /* EN */
973
974/* T0CON[CLK] - Clock Select */
975#define T0CON_CLK_MSK (0x3 << 5 )
976#define T0CON_CLK_UCLK (0x0 << 5 ) /* UCLK - System Clock */
977#define T0CON_CLK_PCLK (0x1 << 5 ) /* PCLK - Peripheral clock */
978#define T0CON_CLK_LFOSC (0x2 << 5 ) /* LFOSC - Internal 32 kHz Oscillator */
979#define T0CON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL - External 32 kHz crystal */
980
981/* T0CON[ENABLE] - Enable */
982#define T0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42000110)
983#define T0CON_ENABLE_MSK (0x1 << 4 )
984#define T0CON_ENABLE (0x1 << 4 )
985#define T0CON_ENABLE_DIS (0x0 << 4 ) /* DIS */
986#define T0CON_ENABLE_EN (0x1 << 4 ) /* EN */
987
988/* T0CON[MOD] - Mode */
989#define T0CON_MOD_BBA (*(volatile unsigned long *) 0x4200010C)
990#define T0CON_MOD_MSK (0x1 << 3 )
991#define T0CON_MOD (0x1 << 3 )
992#define T0CON_MOD_FREERUN (0x0 << 3 ) /* FREERUN */
993#define T0CON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC */
994
995/* T0CON[UP] - Count-up */
996#define T0CON_UP_BBA (*(volatile unsigned long *) 0x42000108)
997#define T0CON_UP_MSK (0x1 << 2 )
998#define T0CON_UP (0x1 << 2 )
999#define T0CON_UP_DIS (0x0 << 2 ) /* DIS */
1000#define T0CON_UP_EN (0x1 << 2 ) /* EN */
1001
1002/* T0CON[PRE] - Prescaler */
1003#define T0CON_PRE_MSK (0x3 << 0 )
1004#define T0CON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
1005#define T0CON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
1006#define T0CON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
1007#define T0CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 - If the selected clock source is UCLK then this setting results in a prescaler of 4. */
1008
1009/* Reset Value for T0CLRI*/
1010#define T0CLRI_RVAL 0x0
1011
1012/* T0CLRI[CAP] - Clear captured event interrupt */
1013#define T0CLRI_CAP_BBA (*(volatile unsigned long *) 0x42000184)
1014#define T0CLRI_CAP_MSK (0x1 << 1 )
1015#define T0CLRI_CAP (0x1 << 1 )
1016#define T0CLRI_CAP_CLR (0x1 << 1 ) /* CLR */
1017
1018/* T0CLRI[TMOUT] - Clear timeout interrupt */
1019#define T0CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42000180)
1020#define T0CLRI_TMOUT_MSK (0x1 << 0 )
1021#define T0CLRI_TMOUT (0x1 << 0 )
1022#define T0CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR */
1023
1024/* Reset Value for T0CAP*/
1025#define T0CAP_RVAL 0x0
1026
1027/* T0CAP[VALUE] - Capture value */
1028#define T0CAP_VALUE_MSK (0xFFFF << 0 )
1029
1030/* Reset Value for T0STA*/
1031#define T0STA_RVAL 0x0
1032
1033/* T0STA[CLRI] - Value updated in the timer clock domain */
1034#define T0STA_CLRI_BBA (*(volatile unsigned long *) 0x4200039C)
1035#define T0STA_CLRI_MSK (0x1 << 7 )
1036#define T0STA_CLRI (0x1 << 7 )
1037#define T0STA_CLRI_CLR (0x0 << 7 ) /* CLR */
1038#define T0STA_CLRI_SET (0x1 << 7 ) /* SET */
1039
1040/* T0STA[CON] - Ready to receive commands */
1041#define T0STA_CON_BBA (*(volatile unsigned long *) 0x42000398)
1042#define T0STA_CON_MSK (0x1 << 6 )
1043#define T0STA_CON (0x1 << 6 )
1044#define T0STA_CON_CLR (0x0 << 6 ) /* CLR */
1045#define T0STA_CON_SET (0x1 << 6 ) /* SET */
1046
1047/* T0STA[CAP] - Capture event pending */
1048#define T0STA_CAP_BBA (*(volatile unsigned long *) 0x42000384)
1049#define T0STA_CAP_MSK (0x1 << 1 )
1050#define T0STA_CAP (0x1 << 1 )
1051#define T0STA_CAP_CLR (0x0 << 1 ) /* CLR */
1052#define T0STA_CAP_SET (0x1 << 1 ) /* SET */
1053
1054/* T0STA[TMOUT] - Time out event occurred */
1055#define T0STA_TMOUT_BBA (*(volatile unsigned long *) 0x42000380)
1056#define T0STA_TMOUT_MSK (0x1 << 0 )
1057#define T0STA_TMOUT (0x1 << 0 )
1058#define T0STA_TMOUT_CLR (0x0 << 0 ) /* CLR */
1059#define T0STA_TMOUT_SET (0x1 << 0 ) /* SET */
1060#if (__NO_MMR_STRUCTS__==1)
1061
1062#define T1LD (*(volatile unsigned short int *) 0x40000400)
1063#define T1VAL (*(volatile unsigned short int *) 0x40000404)
1064#define T1CON (*(volatile unsigned short int *) 0x40000408)
1065#define T1CLRI (*(volatile unsigned short int *) 0x4000040C)
1066#define T1CAP (*(volatile unsigned short int *) 0x40000410)
1067#define T1STA (*(volatile unsigned short int *) 0x4000041C)
1068#endif // (__NO_MMR_STRUCTS__==1)
1069
1070/* Reset Value for T1LD*/
1071#define T1LD_RVAL 0x0
1072
1073/* T1LD[VALUE] - Load value */
1074#define T1LD_VALUE_MSK (0xFFFF << 0 )
1075
1076/* Reset Value for T1VAL*/
1077#define T1VAL_RVAL 0x0
1078
1079/* T1VAL[VALUE] - Current value */
1080#define T1VAL_VALUE_MSK (0xFFFF << 0 )
1081
1082/* Reset Value for T1CON*/
1083#define T1CON_RVAL 0xA
1084
1085/* T1CON[EVENTEN] - Enable time capture of an event */
1086#define T1CON_EVENTEN_BBA (*(volatile unsigned long *) 0x42008130)
1087#define T1CON_EVENTEN_MSK (0x1 << 12 )
1088#define T1CON_EVENTEN (0x1 << 12 )
1089#define T1CON_EVENTEN_DIS (0x0 << 12 ) /* DIS */
1090#define T1CON_EVENTEN_EN (0x1 << 12 ) /* EN */
1091
1092/* T1CON[EVENT] - Event Select, selects 1 of the available events. */
1093#define T1CON_EVENT_MSK (0xF << 8 )
1094#define T1CON_EVENT_COM (0x0 << 8 ) /* COM */
1095#define T1CON_EVENT_T0 (0x1 << 8 ) /* T0 - Timer0 */
1096#define T1CON_EVENT_SPI0 (0x2 << 8 ) /* SPI0 */
1097#define T1CON_EVENT_SPI1 (0x3 << 8 ) /* SPI1 */
1098#define T1CON_EVENT_I2CS (0x4 << 8 ) /* I2CS */
1099#define T1CON_EVENT_I2CM (0x5 << 8 ) /* I2CM */
1100#define T1CON_EVENT_DMAERR (0x6 << 8 ) /* DMAERR */
1101#define T1CON_EVENT_DMADONE (0x7 << 8 ) /* DMADONE */
1102#define T1CON_EVENT_EXT1 (0x8 << 8 ) /* EXT1 */
1103#define T1CON_EVENT_EXT2 (0x9 << 8 ) /* EXT2 */
1104#define T1CON_EVENT_EXT3 (0xA << 8 ) /* EXT3 */
1105#define T1CON_EVENT_PWMTRIP (0xB << 8 ) /* PWMTRIP */
1106#define T1CON_EVENT_PWM0 (0xC << 8 ) /* PWM0 */
1107#define T1CON_EVENT_PWM1 (0xD << 8 ) /* PWM1 */
1108#define T1CON_EVENT_PWM2 (0xE << 8 ) /* PWM2 */
1109
1110/* T1CON[RLD] - Timer reload on write to clear register */
1111#define T1CON_RLD_BBA (*(volatile unsigned long *) 0x4200811C)
1112#define T1CON_RLD_MSK (0x1 << 7 )
1113#define T1CON_RLD (0x1 << 7 )
1114#define T1CON_RLD_DIS (0x0 << 7 ) /* DIS */
1115#define T1CON_RLD_EN (0x1 << 7 ) /* EN */
1116
1117/* T1CON[CLK] - Clock Select */
1118#define T1CON_CLK_MSK (0x3 << 5 )
1119#define T1CON_CLK_UCLK (0x0 << 5 ) /* UCLK - System Clock */
1120#define T1CON_CLK_PCLK (0x1 << 5 ) /* PCLK - Peripheral clock */
1121#define T1CON_CLK_LFOSC (0x2 << 5 ) /* LFOSC - Internal 32 kHz Oscillator */
1122#define T1CON_CLK_LFXTAL (0x3 << 5 ) /* LFXTAL - External 32 kHz crystal */
1123
1124/* T1CON[ENABLE] - Enable */
1125#define T1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42008110)
1126#define T1CON_ENABLE_MSK (0x1 << 4 )
1127#define T1CON_ENABLE (0x1 << 4 )
1128#define T1CON_ENABLE_DIS (0x0 << 4 ) /* DIS */
1129#define T1CON_ENABLE_EN (0x1 << 4 ) /* EN */
1130
1131/* T1CON[MOD] - Mode */
1132#define T1CON_MOD_BBA (*(volatile unsigned long *) 0x4200810C)
1133#define T1CON_MOD_MSK (0x1 << 3 )
1134#define T1CON_MOD (0x1 << 3 )
1135#define T1CON_MOD_FREERUN (0x0 << 3 ) /* FREERUN */
1136#define T1CON_MOD_PERIODIC (0x1 << 3 ) /* PERIODIC */
1137
1138/* T1CON[UP] - Count-up */
1139#define T1CON_UP_BBA (*(volatile unsigned long *) 0x42008108)
1140#define T1CON_UP_MSK (0x1 << 2 )
1141#define T1CON_UP (0x1 << 2 )
1142#define T1CON_UP_DIS (0x0 << 2 ) /* DIS */
1143#define T1CON_UP_EN (0x1 << 2 ) /* EN */
1144
1145/* T1CON[PRE] - Prescaler */
1146#define T1CON_PRE_MSK (0x3 << 0 )
1147#define T1CON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
1148#define T1CON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
1149#define T1CON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
1150#define T1CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 - If the selected clock source is UCLK then this setting results in a prescaler of 4. */
1151
1152/* Reset Value for T1CLRI*/
1153#define T1CLRI_RVAL 0x0
1154
1155/* T1CLRI[CAP] - Clear captured event interrupt */
1156#define T1CLRI_CAP_BBA (*(volatile unsigned long *) 0x42008184)
1157#define T1CLRI_CAP_MSK (0x1 << 1 )
1158#define T1CLRI_CAP (0x1 << 1 )
1159#define T1CLRI_CAP_CLR (0x1 << 1 ) /* CLR */
1160
1161/* T1CLRI[TMOUT] - Clear timeout interrupt */
1162#define T1CLRI_TMOUT_BBA (*(volatile unsigned long *) 0x42008180)
1163#define T1CLRI_TMOUT_MSK (0x1 << 0 )
1164#define T1CLRI_TMOUT (0x1 << 0 )
1165#define T1CLRI_TMOUT_CLR (0x1 << 0 ) /* CLR */
1166
1167/* Reset Value for T1CAP*/
1168#define T1CAP_RVAL 0x0
1169
1170/* T1CAP[VALUE] - Capture value */
1171#define T1CAP_VALUE_MSK (0xFFFF << 0 )
1172
1173/* Reset Value for T1STA*/
1174#define T1STA_RVAL 0x0
1175
1176/* T1STA[CLRI] - Value updated in the timer clock domain */
1177#define T1STA_CLRI_BBA (*(volatile unsigned long *) 0x4200839C)
1178#define T1STA_CLRI_MSK (0x1 << 7 )
1179#define T1STA_CLRI (0x1 << 7 )
1180#define T1STA_CLRI_CLR (0x0 << 7 ) /* CLR */
1181#define T1STA_CLRI_SET (0x1 << 7 ) /* SET */
1182
1183/* T1STA[CON] - Ready to receive commands */
1184#define T1STA_CON_BBA (*(volatile unsigned long *) 0x42008398)
1185#define T1STA_CON_MSK (0x1 << 6 )
1186#define T1STA_CON (0x1 << 6 )
1187#define T1STA_CON_CLR (0x0 << 6 ) /* CLR */
1188#define T1STA_CON_SET (0x1 << 6 ) /* SET */
1189
1190/* T1STA[CAP] - Capture event pending */
1191#define T1STA_CAP_BBA (*(volatile unsigned long *) 0x42008384)
1192#define T1STA_CAP_MSK (0x1 << 1 )
1193#define T1STA_CAP (0x1 << 1 )
1194#define T1STA_CAP_CLR (0x0 << 1 ) /* CLR */
1195#define T1STA_CAP_SET (0x1 << 1 ) /* SET */
1196
1197/* T1STA[TMOUT] - Time out event occurred */
1198#define T1STA_TMOUT_BBA (*(volatile unsigned long *) 0x42008380)
1199#define T1STA_TMOUT_MSK (0x1 << 0 )
1200#define T1STA_TMOUT (0x1 << 0 )
1201#define T1STA_TMOUT_CLR (0x0 << 0 ) /* CLR */
1202#define T1STA_TMOUT_SET (0x1 << 0 ) /* SET */
1203// ------------------------------------------------------------------------------------------------
1204// ----- PWM -----
1205// ------------------------------------------------------------------------------------------------
1206
1207
1208/**
1209 * @brief Pulse Width Modulation (pADI_PWM)
1210 */
1211
1212#if (__NO_MMR_STRUCTS__==0)
1213typedef struct { /*!< pADI_PWM Structure */
1214 __IO uint16_t PWMCON0; /*!< PWM Control register */
1215 __I uint16_t RESERVED0;
1216 __IO uint8_t PWMCON1; /*!< Trip control register */
1217 __I uint8_t RESERVED1[3];
1218 __IO uint16_t PWMCLRI; /*!< PWM interrupt clear. Write to this register clears the latched PWM interrupt. */
1219 __I uint16_t RESERVED2[3];
1220 __IO uint16_t PWM0COM0; /*!< Compare Register 0 for PWM0 and PWM1 */
1221 __I uint16_t RESERVED3;
1222 __IO uint16_t PWM0COM1; /*!< Compare Register 1 for PWM0 and PWM1 */
1223 __I uint16_t RESERVED4;
1224 __IO uint16_t PWM0COM2; /*!< Compare Register 2 for PWM0 and PWM1 */
1225 __I uint16_t RESERVED5;
1226 __IO uint16_t PWM0LEN; /*!< Period Value register for PWM0 and PWM1 */
1227 __I uint16_t RESERVED6;
1228 __IO uint16_t PWM1COM0; /*!< Compare Register 0 for PWM2 and PWM3 */
1229 __I uint16_t RESERVED7;
1230 __IO uint16_t PWM1COM1; /*!< Compare Register 1 for PWM2 and PWM3 */
1231 __I uint16_t RESERVED8;
1232 __IO uint16_t PWM1COM2; /*!< Compare Register 2 for PWM2 and PWM3 */
1233 __I uint16_t RESERVED9;
1234 __IO uint16_t PWM1LEN; /*!< Period Value register for PWM2 and PWM3 */
1235 __I uint16_t RESERVED10;
1236 __IO uint16_t PWM2COM0; /*!< Compare Register 0 for PWM4 and PWM5 */
1237 __I uint16_t RESERVED11;
1238 __IO uint16_t PWM2COM1; /*!< Compare Register 1 for PWM4 and PWM5 */
1239 __I uint16_t RESERVED12;
1240 __IO uint16_t PWM2COM2; /*!< Compare Register 2 for PWM4 and PWM5 */
1241 __I uint16_t RESERVED13;
1242 __IO uint16_t PWM2LEN; /*!< Period Value register for PWM4 and PWM5 */
1243} ADI_PWM_TypeDef;
1244#else // (__NO_MMR_STRUCTS__==0)
1245#define PWMCON0 (*(volatile unsigned short int *) 0x40001000)
1246#define PWMCON1 (*(volatile unsigned char *) 0x40001004)
1247#define PWMCLRI (*(volatile unsigned short int *) 0x40001008)
1248#define PWM0COM0 (*(volatile unsigned short int *) 0x40001010)
1249#define PWM0COM1 (*(volatile unsigned short int *) 0x40001014)
1250#define PWM0COM2 (*(volatile unsigned short int *) 0x40001018)
1251#define PWM0LEN (*(volatile unsigned short int *) 0x4000101C)
1252#define PWM1COM0 (*(volatile unsigned short int *) 0x40001020)
1253#define PWM1COM1 (*(volatile unsigned short int *) 0x40001024)
1254#define PWM1COM2 (*(volatile unsigned short int *) 0x40001028)
1255#define PWM1LEN (*(volatile unsigned short int *) 0x4000102C)
1256#define PWM2COM0 (*(volatile unsigned short int *) 0x40001030)
1257#define PWM2COM1 (*(volatile unsigned short int *) 0x40001034)
1258#define PWM2COM2 (*(volatile unsigned short int *) 0x40001038)
1259#define PWM2LEN (*(volatile unsigned short int *) 0x4000103C)
1260#endif // (__NO_MMR_STRUCTS__==0)
1261
1262/* Reset Value for PWMCON0*/
1263#define PWMCON0_RVAL 0x12
1264
1265/* PWMCON0[SYNC] - PWM Synchronization */
1266#define PWMCON0_SYNC_BBA (*(volatile unsigned long *) 0x4202003C)
1267#define PWMCON0_SYNC_MSK (0x1 << 15 )
1268#define PWMCON0_SYNC (0x1 << 15 )
1269#define PWMCON0_SYNC_DIS (0x0 << 15 ) /* DIS */
1270#define PWMCON0_SYNC_EN (0x1 << 15 ) /* EN */
1271
1272/* PWMCON0[PWM5INV] - Inversion of PWM output */
1273#define PWMCON0_PWM5INV_BBA (*(volatile unsigned long *) 0x42020034)
1274#define PWMCON0_PWM5INV_MSK (0x1 << 13 )
1275#define PWMCON0_PWM5INV (0x1 << 13 )
1276#define PWMCON0_PWM5INV_DIS (0x0 << 13 ) /* DIS */
1277#define PWMCON0_PWM5INV_EN (0x1 << 13 ) /* EN */
1278
1279/* PWMCON0[PWM3INV] - Inversion of PWM output */
1280#define PWMCON0_PWM3INV_BBA (*(volatile unsigned long *) 0x42020030)
1281#define PWMCON0_PWM3INV_MSK (0x1 << 12 )
1282#define PWMCON0_PWM3INV (0x1 << 12 )
1283#define PWMCON0_PWM3INV_DIS (0x0 << 12 ) /* DIS */
1284#define PWMCON0_PWM3INV_EN (0x1 << 12 ) /* EN */
1285
1286/* PWMCON0[PWM1INV] - Inversion of PWM output */
1287#define PWMCON0_PWM1INV_BBA (*(volatile unsigned long *) 0x4202002C)
1288#define PWMCON0_PWM1INV_MSK (0x1 << 11 )
1289#define PWMCON0_PWM1INV (0x1 << 11 )
1290#define PWMCON0_PWM1INV_DIS (0x0 << 11 ) /* DIS */
1291#define PWMCON0_PWM1INV_EN (0x1 << 11 ) /* EN */
1292
1293/* PWMCON0[PWMIEN] - Enables PWM interrupts */
1294#define PWMCON0_PWMIEN_BBA (*(volatile unsigned long *) 0x42020028)
1295#define PWMCON0_PWMIEN_MSK (0x1 << 10 )
1296#define PWMCON0_PWMIEN (0x1 << 10 )
1297#define PWMCON0_PWMIEN_DIS (0x0 << 10 ) /* DIS */
1298#define PWMCON0_PWMIEN_EN (0x1 << 10 ) /* EN */
1299
1300/* PWMCON0[ENA] - enable PWM outputs */
1301#define PWMCON0_ENA_BBA (*(volatile unsigned long *) 0x42020024)
1302#define PWMCON0_ENA_MSK (0x1 << 9 )
1303#define PWMCON0_ENA (0x1 << 9 )
1304#define PWMCON0_ENA_DIS (0x0 << 9 ) /* DIS */
1305#define PWMCON0_ENA_EN (0x1 << 9 ) /* EN */
1306
1307/* PWMCON0[PRE] - PWM Clock Prescaler */
1308#define PWMCON0_PRE_MSK (0x7 << 6 )
1309
1310/* PWMCON0[POINV] - Invert all PWM outputs */
1311#define PWMCON0_POINV_BBA (*(volatile unsigned long *) 0x42020014)
1312#define PWMCON0_POINV_MSK (0x1 << 5 )
1313#define PWMCON0_POINV (0x1 << 5 )
1314#define PWMCON0_POINV_DIS (0x0 << 5 ) /* DIS */
1315#define PWMCON0_POINV_EN (0x1 << 5 ) /* EN */
1316
1317/* PWMCON0[HOFF] - High Side Off */
1318#define PWMCON0_HOFF_BBA (*(volatile unsigned long *) 0x42020010)
1319#define PWMCON0_HOFF_MSK (0x1 << 4 )
1320#define PWMCON0_HOFF (0x1 << 4 )
1321#define PWMCON0_HOFF_DIS (0x0 << 4 ) /* DIS */
1322#define PWMCON0_HOFF_EN (0x1 << 4 ) /* EN */
1323
1324/* PWMCON0[LCOMP] - Load Compare Registers */
1325#define PWMCON0_LCOMP_BBA (*(volatile unsigned long *) 0x4202000C)
1326#define PWMCON0_LCOMP_MSK (0x1 << 3 )
1327#define PWMCON0_LCOMP (0x1 << 3 )
1328#define PWMCON0_LCOMP_DIS (0x0 << 3 ) /* DIS */
1329#define PWMCON0_LCOMP_EN (0x1 << 3 ) /* EN */
1330
1331/* PWMCON0[DIR] - Direction Control */
1332#define PWMCON0_DIR_BBA (*(volatile unsigned long *) 0x42020008)
1333#define PWMCON0_DIR_MSK (0x1 << 2 )
1334#define PWMCON0_DIR (0x1 << 2 )
1335#define PWMCON0_DIR_DIS (0x0 << 2 ) /* DIS */
1336#define PWMCON0_DIR_EN (0x1 << 2 ) /* EN */
1337
1338/* PWMCON0[MOD] - Enables H-Bridge Mode */
1339#define PWMCON0_MOD_BBA (*(volatile unsigned long *) 0x42020004)
1340#define PWMCON0_MOD_MSK (0x1 << 1 )
1341#define PWMCON0_MOD (0x1 << 1 )
1342#define PWMCON0_MOD_DIS (0x0 << 1 ) /* DIS */
1343#define PWMCON0_MOD_EN (0x1 << 1 ) /* EN */
1344
1345/* PWMCON0[ENABLE] - Enables all PWM outputs */
1346#define PWMCON0_ENABLE_BBA (*(volatile unsigned long *) 0x42020000)
1347#define PWMCON0_ENABLE_MSK (0x1 << 0 )
1348#define PWMCON0_ENABLE (0x1 << 0 )
1349#define PWMCON0_ENABLE_DIS (0x0 << 0 ) /* DIS */
1350#define PWMCON0_ENABLE_EN (0x1 << 0 ) /* EN */
1351
1352/* Reset Value for PWMCON1*/
1353#define PWMCON1_RVAL 0x0
1354
1355/* PWMCON1[CONVSTART] - Enable adc conversion start from pwm */
1356#define PWMCON1_CONVSTART_BBA (*(volatile unsigned long *) 0x4202009C)
1357#define PWMCON1_CONVSTART_MSK (0x1 << 7 )
1358#define PWMCON1_CONVSTART (0x1 << 7 )
1359#define PWMCON1_CONVSTART_DIS (0x0 << 7 ) /* DIS */
1360#define PWMCON1_CONVSTART_EN (0x1 << 7 ) /* EN */
1361
1362/* PWMCON1[TRIPEN] - Enable PWM trip functionality */
1363#define PWMCON1_TRIPEN_BBA (*(volatile unsigned long *) 0x42020098)
1364#define PWMCON1_TRIPEN_MSK (0x1 << 6 )
1365#define PWMCON1_TRIPEN (0x1 << 6 )
1366#define PWMCON1_TRIPEN_DIS (0x0 << 6 ) /* DIS */
1367#define PWMCON1_TRIPEN_EN (0x1 << 6 ) /* EN */
1368
1369/* PWMCON1[CONVSTARTDELAY] - ADC conversion start delay configuration */
1370#define PWMCON1_CONVSTARTDELAY_MSK (0xF << 0 )
1371
1372/* Reset Value for PWMCLRI*/
1373#define PWMCLRI_RVAL 0x0
1374
1375/* PWMCLRI[TRIP] - Clear the latched trip interrupt */
1376#define PWMCLRI_TRIP_BBA (*(volatile unsigned long *) 0x42020110)
1377#define PWMCLRI_TRIP_MSK (0x1 << 4 )
1378#define PWMCLRI_TRIP (0x1 << 4 )
1379#define PWMCLRI_TRIP_DIS (0x0 << 4 ) /* DIS */
1380#define PWMCLRI_TRIP_EN (0x1 << 4 ) /* EN */
1381
1382/* PWMCLRI[PWM2] - Clear the latched PWM2 interrupt */
1383#define PWMCLRI_PWM2_BBA (*(volatile unsigned long *) 0x42020108)
1384#define PWMCLRI_PWM2_MSK (0x1 << 2 )
1385#define PWMCLRI_PWM2 (0x1 << 2 )
1386#define PWMCLRI_PWM2_DIS (0x0 << 2 ) /* DIS */
1387#define PWMCLRI_PWM2_EN (0x1 << 2 ) /* EN */
1388
1389/* PWMCLRI[PWM1] - Clear the latched PWM1 interrupt */
1390#define PWMCLRI_PWM1_BBA (*(volatile unsigned long *) 0x42020104)
1391#define PWMCLRI_PWM1_MSK (0x1 << 1 )
1392#define PWMCLRI_PWM1 (0x1 << 1 )
1393#define PWMCLRI_PWM1_DIS (0x0 << 1 ) /* DIS */
1394#define PWMCLRI_PWM1_EN (0x1 << 1 ) /* EN */
1395
1396/* PWMCLRI[PWM0] - Clear the latched PWM0 interrupt */
1397#define PWMCLRI_PWM0_BBA (*(volatile unsigned long *) 0x42020100)
1398#define PWMCLRI_PWM0_MSK (0x1 << 0 )
1399#define PWMCLRI_PWM0 (0x1 << 0 )
1400#define PWMCLRI_PWM0_DIS (0x0 << 0 ) /* DIS */
1401#define PWMCLRI_PWM0_EN (0x1 << 0 ) /* EN */
1402
1403/* Reset Value for PWM0COM0*/
1404#define PWM0COM0_RVAL 0x0
1405
1406/* Reset Value for PWM0COM1*/
1407#define PWM0COM1_RVAL 0x0
1408
1409/* Reset Value for PWM0COM2*/
1410#define PWM0COM2_RVAL 0x0
1411
1412/* Reset Value for PWM0LEN*/
1413#define PWM0LEN_RVAL 0x0
1414
1415/* Reset Value for PWM1COM0*/
1416#define PWM1COM0_RVAL 0x0
1417
1418/* Reset Value for PWM1COM1*/
1419#define PWM1COM1_RVAL 0x0
1420
1421/* Reset Value for PWM1COM2*/
1422#define PWM1COM2_RVAL 0x0
1423
1424/* Reset Value for PWM1LEN*/
1425#define PWM1LEN_RVAL 0x0
1426
1427/* Reset Value for PWM2COM0*/
1428#define PWM2COM0_RVAL 0x0
1429
1430/* Reset Value for PWM2COM1*/
1431#define PWM2COM1_RVAL 0x0
1432
1433/* Reset Value for PWM2COM2*/
1434#define PWM2COM2_RVAL 0x0
1435
1436/* Reset Value for PWM2LEN*/
1437#define PWM2LEN_RVAL 0x0
1438// ------------------------------------------------------------------------------------------------
1439// ----- PWRCTL -----
1440// ------------------------------------------------------------------------------------------------
1441
1442
1443/**
1444 * @brief Power Management Unit (pADI_PWRCTL)
1445 */
1446
1447#if (__NO_MMR_STRUCTS__==0)
1448typedef struct { /*!< pADI_PWRCTL Structure */
1449 __IO uint8_t PWRMOD; /*!< Power modes register */
1450 __I uint8_t RESERVED0[3];
1451 __IO uint16_t PWRKEY; /*!< Key protection for the PWRMOD register. */
1452} ADI_PWRCTL_TypeDef;
1453#else // (__NO_MMR_STRUCTS__==0)
1454#define PWRMOD (*(volatile unsigned char *) 0x40002400)
1455#define PWRKEY (*(volatile unsigned short int *) 0x40002404)
1456#endif // (__NO_MMR_STRUCTS__==0)
1457
1458/* Reset Value for PWRMOD*/
1459#define PWRMOD_RVAL 0x40
1460
1461/* PWRMOD[WICENACK] - For Deepsleep mode only */
1462#define PWRMOD_WICENACK_BBA (*(volatile unsigned long *) 0x4204800C)
1463#define PWRMOD_WICENACK_MSK (0x1 << 3 )
1464#define PWRMOD_WICENACK (0x1 << 3 )
1465#define PWRMOD_WICENACK_DIS (0x0 << 3 ) /* DIS */
1466#define PWRMOD_WICENACK_EN (0x1 << 3 ) /* EN */
1467
1468/* PWRMOD[MOD] - Power Mode */
1469#define PWRMOD_MOD_MSK (0x7 << 0 )
1470#define PWRMOD_MOD_FULLACTIVE (0x0 << 0 ) /* FULLACTIVE */
1471#define PWRMOD_MOD_MCUHALT (0x1 << 0 ) /* MCUHALT */
1472#define PWRMOD_MOD_PERHALT (0x2 << 0 ) /* PERHALT */
1473#define PWRMOD_MOD_SYSHALT (0x3 << 0 ) /* SYSHALT */
1474#define PWRMOD_MOD_TOTALHALT (0x4 << 0 ) /* TOTALHALT */
1475#define PWRMOD_MOD_HIBERNATE (0x5 << 0 ) /* HIBERNATE */
1476
1477/* Reset Value for PWRKEY*/
1478#define PWRKEY_RVAL 0x0
1479
1480/* PWRKEY[VALUE] - Key value */
1481#define PWRKEY_VALUE_MSK (0xFFFF << 0 )
1482#define PWRKEY_VALUE_KEY1 (0x4859 << 0 ) /* KEY1 */
1483#define PWRKEY_VALUE_KEY2 (0xF27B << 0 ) /* KEY2 */
1484// ------------------------------------------------------------------------------------------------
1485// ----- RESET -----
1486// ------------------------------------------------------------------------------------------------
1487
1488
1489/**
1490 * @brief Reset (pADI_RESET)
1491 */
1492
1493#if (__NO_MMR_STRUCTS__==0)
1494typedef struct { /*!< pADI_RESET Structure */
1495
1496 union {
1497 __IO uint8_t RSTSTA; /*!< Reset Status */
1498 __IO uint8_t RSTCLR; /*!< Reset Status Clear */
1499 } ;
1500} ADI_RESET_TypeDef;
1501#else // (__NO_MMR_STRUCTS__==0)
1502#define RSTSTA (*(volatile unsigned char *) 0x40002440)
1503#define RSTCLR (*(volatile unsigned char *) 0x40002440)
1504#endif // (__NO_MMR_STRUCTS__==0)
1505
1506/* Reset Value for RSTSTA*/
1507#define RSTSTA_RVAL 0x1
1508
1509/* RSTSTA[SWRST] - Software reset status bit */
1510#define RSTSTA_SWRST_BBA (*(volatile unsigned long *) 0x4204880C)
1511#define RSTSTA_SWRST_MSK (0x1 << 3 )
1512#define RSTSTA_SWRST (0x1 << 3 )
1513#define RSTSTA_SWRST_CLR (0x0 << 3 ) /* CLR */
1514#define RSTSTA_SWRST_SET (0x1 << 3 ) /* SET */
1515
1516/* RSTSTA[WDRST] - Watchdog reset status bit */
1517#define RSTSTA_WDRST_BBA (*(volatile unsigned long *) 0x42048808)
1518#define RSTSTA_WDRST_MSK (0x1 << 2 )
1519#define RSTSTA_WDRST (0x1 << 2 )
1520#define RSTSTA_WDRST_CLR (0x0 << 2 ) /* CLR */
1521#define RSTSTA_WDRST_SET (0x1 << 2 ) /* SET */
1522
1523/* RSTSTA[EXTRST] - External reset status bit */
1524#define RSTSTA_EXTRST_BBA (*(volatile unsigned long *) 0x42048804)
1525#define RSTSTA_EXTRST_MSK (0x1 << 1 )
1526#define RSTSTA_EXTRST (0x1 << 1 )
1527#define RSTSTA_EXTRST_CLR (0x0 << 1 ) /* CLR */
1528#define RSTSTA_EXTRST_SET (0x1 << 1 ) /* SET */
1529
1530/* RSTSTA[POR] - Power-on reset status bit */
1531#define RSTSTA_POR_BBA (*(volatile unsigned long *) 0x42048800)
1532#define RSTSTA_POR_MSK (0x1 << 0 )
1533#define RSTSTA_POR (0x1 << 0 )
1534#define RSTSTA_POR_CLR (0x0 << 0 ) /* CLR */
1535#define RSTSTA_POR_SET (0x1 << 0 ) /* SET */
1536
1537/* Reset Value for RSTCLR*/
1538#define RSTCLR_RVAL 0x1
1539
1540/* RSTCLR[SWRST] - Software reset status bit */
1541#define RSTCLR_SWRST_BBA (*(volatile unsigned long *) 0x4204880C)
1542#define RSTCLR_SWRST_MSK (0x1 << 3 )
1543#define RSTCLR_SWRST (0x1 << 3 )
1544#define RSTCLR_SWRST_DIS (0x0 << 3 ) /* DIS */
1545#define RSTCLR_SWRST_EN (0x1 << 3 ) /* EN */
1546
1547/* RSTCLR[WDRST] - Watchdog reset status bit */
1548#define RSTCLR_WDRST_BBA (*(volatile unsigned long *) 0x42048808)
1549#define RSTCLR_WDRST_MSK (0x1 << 2 )
1550#define RSTCLR_WDRST (0x1 << 2 )
1551#define RSTCLR_WDRST_DIS (0x0 << 2 ) /* DIS */
1552#define RSTCLR_WDRST_EN (0x1 << 2 ) /* EN */
1553
1554/* RSTCLR[EXTRST] - External reset status bit */
1555#define RSTCLR_EXTRST_BBA (*(volatile unsigned long *) 0x42048804)
1556#define RSTCLR_EXTRST_MSK (0x1 << 1 )
1557#define RSTCLR_EXTRST (0x1 << 1 )
1558#define RSTCLR_EXTRST_DIS (0x0 << 1 ) /* DIS */
1559#define RSTCLR_EXTRST_EN (0x1 << 1 ) /* EN */
1560
1561/* RSTCLR[POR] - Power-on reset status bit */
1562#define RSTCLR_POR_BBA (*(volatile unsigned long *) 0x42048800)
1563#define RSTCLR_POR_MSK (0x1 << 0 )
1564#define RSTCLR_POR (0x1 << 0 )
1565#define RSTCLR_POR_DIS (0x0 << 0 ) /* DIS */
1566#define RSTCLR_POR_EN (0x1 << 0 ) /* EN */
1567// ------------------------------------------------------------------------------------------------
1568// ----- INTERRUPT -----
1569// ------------------------------------------------------------------------------------------------
1570
1571
1572/**
1573 * @brief Interrupts (pADI_INTERRUPT)
1574 */
1575
1576#if (__NO_MMR_STRUCTS__==0)
1577typedef struct { /*!< pADI_INTERRUPT Structure */
1578 __IO uint16_t EI0CFG; /*!< External Interrupt configuration register 0 */
1579 __I uint16_t RESERVED0;
1580 __IO uint16_t EI1CFG; /*!< External Interrupt configuration register 1 */
1581 __I uint16_t RESERVED1[5];
1582 __IO uint16_t EICLR; /*!< External Interrupts Clear register */
1583} ADI_INTERRUPT_TypeDef;
1584#else // (__NO_MMR_STRUCTS__==0)
1585#define EI0CFG (*(volatile unsigned short int *) 0x40002420)
1586#define EI1CFG (*(volatile unsigned short int *) 0x40002424)
1587#define EICLR (*(volatile unsigned short int *) 0x40002430)
1588#endif // (__NO_MMR_STRUCTS__==0)
1589
1590/* Reset Value for EI0CFG*/
1591#define EI0CFG_RVAL 0x0
1592
1593/* EI0CFG[IRQ3EN] - External Interrupt 3 Enable */
1594#define EI0CFG_IRQ3EN_BBA (*(volatile unsigned long *) 0x4204843C)
1595#define EI0CFG_IRQ3EN_MSK (0x1 << 15 )
1596#define EI0CFG_IRQ3EN (0x1 << 15 )
1597#define EI0CFG_IRQ3EN_DIS (0x0 << 15 ) /* DIS */
1598#define EI0CFG_IRQ3EN_EN (0x1 << 15 ) /* EN */
1599
1600/* EI0CFG[IRQ3MDE] - External Interrupt 0 Mode */
1601#define EI0CFG_IRQ3MDE_MSK (0x7 << 12 )
1602#define EI0CFG_IRQ3MDE_RISE (0x0 << 12 ) /* RISE */
1603#define EI0CFG_IRQ3MDE_FALL (0x1 << 12 ) /* FALL */
1604#define EI0CFG_IRQ3MDE_RISEORFALL (0x2 << 12 ) /* RISEORFALL */
1605#define EI0CFG_IRQ3MDE_HIGHLEVEL (0x3 << 12 ) /* HIGHLEVEL */
1606#define EI0CFG_IRQ3MDE_LOWLEVEL (0x4 << 12 ) /* LOWLEVEL */
1607
1608/* EI0CFG[IRQ2EN] - External Interrupt 2 Enable */
1609#define EI0CFG_IRQ2EN_BBA (*(volatile unsigned long *) 0x4204842C)
1610#define EI0CFG_IRQ2EN_MSK (0x1 << 11 )
1611#define EI0CFG_IRQ2EN (0x1 << 11 )
1612#define EI0CFG_IRQ2EN_DIS (0x0 << 11 ) /* DIS */
1613#define EI0CFG_IRQ2EN_EN (0x1 << 11 ) /* EN */
1614
1615/* EI0CFG[IRQ2MDE] - External Interrupt 2 Mode */
1616#define EI0CFG_IRQ2MDE_MSK (0x7 << 8 )
1617#define EI0CFG_IRQ2MDE_RISE (0x0 << 8 ) /* RISE */
1618#define EI0CFG_IRQ2MDE_FALL (0x1 << 8 ) /* FALL */
1619#define EI0CFG_IRQ2MDE_RISEORFALL (0x2 << 8 ) /* RISEORFALL */
1620#define EI0CFG_IRQ2MDE_HIGHLEVEL (0x3 << 8 ) /* HIGHLEVEL */
1621#define EI0CFG_IRQ2MDE_LOWLEVEL (0x4 << 8 ) /* LOWLEVEL */
1622
1623/* EI0CFG[IRQ1EN] - External Interrupt 1 Enable */
1624#define EI0CFG_IRQ1EN_BBA (*(volatile unsigned long *) 0x4204841C)
1625#define EI0CFG_IRQ1EN_MSK (0x1 << 7 )
1626#define EI0CFG_IRQ1EN (0x1 << 7 )
1627#define EI0CFG_IRQ1EN_DIS (0x0 << 7 ) /* DIS */
1628#define EI0CFG_IRQ1EN_EN (0x1 << 7 ) /* EN */
1629
1630/* EI0CFG[IRQ1MDE] - External Interrupt 1 Mode */
1631#define EI0CFG_IRQ1MDE_MSK (0x7 << 4 )
1632#define EI0CFG_IRQ1MDE_RISE (0x0 << 4 ) /* RISE */
1633#define EI0CFG_IRQ1MDE_FALL (0x1 << 4 ) /* FALL */
1634#define EI0CFG_IRQ1MDE_RISEORFALL (0x2 << 4 ) /* RISEORFALL */
1635#define EI0CFG_IRQ1MDE_HIGHLEVEL (0x3 << 4 ) /* HIGHLEVEL */
1636#define EI0CFG_IRQ1MDE_LOWLEVEL (0x4 << 4 ) /* LOWLEVEL */
1637
1638/* EI0CFG[IRQ0EN] - External Interrupt 0 Enable */
1639#define EI0CFG_IRQ0EN_BBA (*(volatile unsigned long *) 0x4204840C)
1640#define EI0CFG_IRQ0EN_MSK (0x1 << 3 )
1641#define EI0CFG_IRQ0EN (0x1 << 3 )
1642#define EI0CFG_IRQ0EN_DIS (0x0 << 3 ) /* DIS */
1643#define EI0CFG_IRQ0EN_EN (0x1 << 3 ) /* EN */
1644
1645/* EI0CFG[IRQ0MDE] - External Interrupt 0 Mode */
1646#define EI0CFG_IRQ0MDE_MSK (0x7 << 0 )
1647#define EI0CFG_IRQ0MDE_RISE (0x0 << 0 ) /* RISE */
1648#define EI0CFG_IRQ0MDE_FALL (0x1 << 0 ) /* FALL */
1649#define EI0CFG_IRQ0MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL */
1650#define EI0CFG_IRQ0MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL */
1651#define EI0CFG_IRQ0MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL */
1652
1653/* Reset Value for EI1CFG*/
1654#define EI1CFG_RVAL 0x0
1655
1656/* EI1CFG[IRQ7EN] - External Interrupt 7 Enable */
1657#define EI1CFG_IRQ7EN_BBA (*(volatile unsigned long *) 0x420484BC)
1658#define EI1CFG_IRQ7EN_MSK (0x1 << 15 )
1659#define EI1CFG_IRQ7EN (0x1 << 15 )
1660#define EI1CFG_IRQ7EN_DIS (0x0 << 15 ) /* DIS */
1661#define EI1CFG_IRQ7EN_EN (0x1 << 15 ) /* EN */
1662
1663/* EI1CFG[IRQ7MDE] - External Interrupt 7 Mode */
1664#define EI1CFG_IRQ7MDE_MSK (0x7 << 12 )
1665#define EI1CFG_IRQ7MDE_RISE (0x0 << 12 ) /* RISE */
1666#define EI1CFG_IRQ7MDE_FALL (0x1 << 12 ) /* FALL */
1667#define EI1CFG_IRQ7MDE_RISEORFALL (0x2 << 12 ) /* RISEORFALL */
1668#define EI1CFG_IRQ7MDE_HIGHLEVEL (0x3 << 12 ) /* HIGHLEVEL */
1669#define EI1CFG_IRQ7MDE_LOWLEVEL (0x4 << 12 ) /* LOWLEVEL */
1670
1671/* EI1CFG[IRQ6EN] - External Interrupt 6 Enable */
1672#define EI1CFG_IRQ6EN_BBA (*(volatile unsigned long *) 0x420484AC)
1673#define EI1CFG_IRQ6EN_MSK (0x1 << 11 )
1674#define EI1CFG_IRQ6EN (0x1 << 11 )
1675#define EI1CFG_IRQ6EN_DIS (0x0 << 11 ) /* DIS */
1676#define EI1CFG_IRQ6EN_EN (0x1 << 11 ) /* EN */
1677
1678/* EI1CFG[IRQ6MDE] - External Interrupt 6 Mode */
1679#define EI1CFG_IRQ6MDE_MSK (0x7 << 8 )
1680#define EI1CFG_IRQ6MDE_RISE (0x0 << 8 ) /* RISE */
1681#define EI1CFG_IRQ6MDE_FALL (0x1 << 8 ) /* FALL */
1682#define EI1CFG_IRQ6MDE_RISEORFALL (0x2 << 8 ) /* RISEORFALL */
1683#define EI1CFG_IRQ6MDE_HIGHLEVEL (0x3 << 8 ) /* HIGHLEVEL */
1684#define EI1CFG_IRQ6MDE_LOWLEVEL (0x4 << 8 ) /* LOWLEVEL */
1685
1686/* EI1CFG[IRQ5EN] - External Interrupt 5 Enable */
1687#define EI1CFG_IRQ5EN_BBA (*(volatile unsigned long *) 0x4204849C)
1688#define EI1CFG_IRQ5EN_MSK (0x1 << 7 )
1689#define EI1CFG_IRQ5EN (0x1 << 7 )
1690#define EI1CFG_IRQ5EN_DIS (0x0 << 7 ) /* DIS */
1691#define EI1CFG_IRQ5EN_EN (0x1 << 7 ) /* EN */
1692
1693/* EI1CFG[IRQ5MDE] - External Interrupt 5 Mode */
1694#define EI1CFG_IRQ5MDE_MSK (0x7 << 4 )
1695#define EI1CFG_IRQ5MDE_RISE (0x0 << 4 ) /* RISE */
1696#define EI1CFG_IRQ5MDE_FALL (0x1 << 4 ) /* FALL */
1697#define EI1CFG_IRQ5MDE_RISEORFALL (0x2 << 4 ) /* RISEORFALL */
1698#define EI1CFG_IRQ5MDE_HIGHLEVEL (0x3 << 4 ) /* HIGHLEVEL */
1699#define EI1CFG_IRQ5MDE_LOWLEVEL (0x4 << 4 ) /* LOWLEVEL */
1700
1701/* EI1CFG[IRQ4EN] - External Interrupt 4 Enable */
1702#define EI1CFG_IRQ4EN_BBA (*(volatile unsigned long *) 0x4204848C)
1703#define EI1CFG_IRQ4EN_MSK (0x1 << 3 )
1704#define EI1CFG_IRQ4EN (0x1 << 3 )
1705#define EI1CFG_IRQ4EN_DIS (0x0 << 3 ) /* DIS */
1706#define EI1CFG_IRQ4EN_EN (0x1 << 3 ) /* EN */
1707
1708/* EI1CFG[IRQ4MDE] - External Interrupt 4 Mode */
1709#define EI1CFG_IRQ4MDE_MSK (0x7 << 0 )
1710#define EI1CFG_IRQ4MDE_RISE (0x0 << 0 ) /* RISE */
1711#define EI1CFG_IRQ4MDE_FALL (0x1 << 0 ) /* FALL */
1712#define EI1CFG_IRQ4MDE_RISEORFALL (0x2 << 0 ) /* RISEORFALL */
1713#define EI1CFG_IRQ4MDE_HIGHLEVEL (0x3 << 0 ) /* HIGHLEVEL */
1714#define EI1CFG_IRQ4MDE_LOWLEVEL (0x4 << 0 ) /* LOWLEVEL */
1715
1716/* Reset Value for EICLR*/
1717#define EICLR_RVAL 0x0
1718
1719/* EICLR[IRQ7] - Clears External interrupt 7 internal flag */
1720#define EICLR_IRQ7_BBA (*(volatile unsigned long *) 0x4204861C)
1721#define EICLR_IRQ7_MSK (0x1 << 7 )
1722#define EICLR_IRQ7 (0x1 << 7 )
1723#define EICLR_IRQ7_CLR (0x1 << 7 ) /* CLR */
1724
1725/* EICLR[IRQ6] - Clears External interrupt 6 internal flag */
1726#define EICLR_IRQ6_BBA (*(volatile unsigned long *) 0x42048618)
1727#define EICLR_IRQ6_MSK (0x1 << 6 )
1728#define EICLR_IRQ6 (0x1 << 6 )
1729#define EICLR_IRQ6_CLR (0x1 << 6 ) /* CLR */
1730
1731/* EICLR[IRQ5] - Clears External interrupt 5 internal flag */
1732#define EICLR_IRQ5_BBA (*(volatile unsigned long *) 0x42048614)
1733#define EICLR_IRQ5_MSK (0x1 << 5 )
1734#define EICLR_IRQ5 (0x1 << 5 )
1735#define EICLR_IRQ5_CLR (0x1 << 5 ) /* CLR */
1736
1737/* EICLR[IRQ4] - Clears External interrupt 4 internal flag */
1738#define EICLR_IRQ4_BBA (*(volatile unsigned long *) 0x42048610)
1739#define EICLR_IRQ4_MSK (0x1 << 4 )
1740#define EICLR_IRQ4 (0x1 << 4 )
1741#define EICLR_IRQ4_CLR (0x1 << 4 ) /* CLR */
1742
1743/* EICLR[IRQ3] - Clears External interrupt 3 internal flag */
1744#define EICLR_IRQ3_BBA (*(volatile unsigned long *) 0x4204860C)
1745#define EICLR_IRQ3_MSK (0x1 << 3 )
1746#define EICLR_IRQ3 (0x1 << 3 )
1747#define EICLR_IRQ3_CLR (0x1 << 3 ) /* CLR */
1748
1749/* EICLR[IRQ2] - Clears External interrupt 2 internal flag */
1750#define EICLR_IRQ2_BBA (*(volatile unsigned long *) 0x42048608)
1751#define EICLR_IRQ2_MSK (0x1 << 2 )
1752#define EICLR_IRQ2 (0x1 << 2 )
1753#define EICLR_IRQ2_CLR (0x1 << 2 ) /* CLR */
1754
1755/* EICLR[IRQ1] - Clears External interrupt 1 internal flag */
1756#define EICLR_IRQ1_BBA (*(volatile unsigned long *) 0x42048604)
1757#define EICLR_IRQ1_MSK (0x1 << 1 )
1758#define EICLR_IRQ1 (0x1 << 1 )
1759#define EICLR_IRQ1_CLR (0x1 << 1 ) /* CLR */
1760
1761/* EICLR[IRQ0] - Clears External interrupt 0 internal flag */
1762#define EICLR_IRQ0_BBA (*(volatile unsigned long *) 0x42048600)
1763#define EICLR_IRQ0_MSK (0x1 << 0 )
1764#define EICLR_IRQ0 (0x1 << 0 )
1765#define EICLR_IRQ0_CLR (0x1 << 0 ) /* CLR */
1766// ------------------------------------------------------------------------------------------------
1767// ----- WDT -----
1768// ------------------------------------------------------------------------------------------------
1769
1770
1771/**
1772 * @brief Watchdog Timer (pADI_WDT)
1773 */
1774
1775#if (__NO_MMR_STRUCTS__==0)
1776typedef struct { /*!< pADI_WDT Structure */
1777 __IO uint16_t T3LD; /*!< Load value. */
1778 __I uint16_t RESERVED0;
1779 __IO uint16_t T3VAL; /*!< "Current count value, read only." */
1780 __I uint16_t RESERVED1;
1781 __IO uint16_t T3CON; /*!< Control Register */
1782 __I uint16_t RESERVED2;
1783 __IO uint16_t T3CLRI; /*!< "Clear interrupt, write only." */
1784 __I uint16_t RESERVED3[5];
1785 __IO uint16_t T3STA; /*!< "Status register, read only." */
1786} ADI_WDT_TypeDef;
1787#else // (__NO_MMR_STRUCTS__==0)
1788#define T3LD (*(volatile unsigned short int *) 0x40002580)
1789#define T3VAL (*(volatile unsigned short int *) 0x40002584)
1790#define T3CON (*(volatile unsigned short int *) 0x40002588)
1791#define T3CLRI (*(volatile unsigned short int *) 0x4000258C)
1792#define T3STA (*(volatile unsigned short int *) 0x40002598)
1793#endif // (__NO_MMR_STRUCTS__==0)
1794
1795/* Reset Value for T3LD*/
1796#define T3LD_RVAL 0x1000
1797
1798/* T3LD[VALUE] - Current Value */
1799#define T3LD_VALUE_MSK (0xFFFF << 0 )
1800
1801/* Reset Value for T3VAL*/
1802#define T3VAL_RVAL 0x1000
1803
1804/* T3VAL[VALUE] - Current Value */
1805#define T3VAL_VALUE_MSK (0xFFFF << 0 )
1806
1807/* Reset Value for T3CON*/
1808#define T3CON_RVAL 0xE9
1809
1810/* T3CON[MOD] - Mode */
1811#define T3CON_MOD_BBA (*(volatile unsigned long *) 0x4204B118)
1812#define T3CON_MOD_MSK (0x1 << 6 )
1813#define T3CON_MOD (0x1 << 6 )
1814#define T3CON_MOD_FREERUN (0x0 << 6 ) /* FREERUN */
1815#define T3CON_MOD_PERIODIC (0x1 << 6 ) /* PERIODIC */
1816
1817/* T3CON[ENABLE] - Enable */
1818#define T3CON_ENABLE_BBA (*(volatile unsigned long *) 0x4204B114)
1819#define T3CON_ENABLE_MSK (0x1 << 5 )
1820#define T3CON_ENABLE (0x1 << 5 )
1821#define T3CON_ENABLE_DIS (0x0 << 5 ) /* DIS */
1822#define T3CON_ENABLE_EN (0x1 << 5 ) /* EN */
1823
1824/* T3CON[PRE] - Prescaler */
1825#define T3CON_PRE_MSK (0x3 << 2 )
1826#define T3CON_PRE_DIV1 (0x0 << 2 ) /* DIV1 */
1827#define T3CON_PRE_DIV16 (0x1 << 2 ) /* DIV16 */
1828#define T3CON_PRE_DIV256 (0x2 << 2 ) /* DIV256 */
1829#define T3CON_PRE_DIV4096 (0x3 << 2 ) /* DIV4096 */
1830
1831/* T3CON[IRQ] - Timer Interrupt , */
1832#define T3CON_IRQ_BBA (*(volatile unsigned long *) 0x4204B104)
1833#define T3CON_IRQ_MSK (0x1 << 1 )
1834#define T3CON_IRQ (0x1 << 1 )
1835#define T3CON_IRQ_DIS (0x0 << 1 ) /* DIS */
1836#define T3CON_IRQ_EN (0x1 << 1 ) /* EN */
1837
1838/* T3CON[PD] - Power down clear */
1839#define T3CON_PD_BBA (*(volatile unsigned long *) 0x4204B100)
1840#define T3CON_PD_MSK (0x1 << 0 )
1841#define T3CON_PD (0x1 << 0 )
1842#define T3CON_PD_DIS (0x0 << 0 ) /* DIS */
1843#define T3CON_PD_EN (0x1 << 0 ) /* EN */
1844
1845/* Reset Value for T3CLRI*/
1846#define T3CLRI_RVAL 0x0
1847
1848/* T3CLRI[VALUE] - Clear Watchdog */
1849#define T3CLRI_VALUE_MSK (0xFFFF << 0 )
1850#define T3CLRI_VALUE_CLR (0xCCCC << 0 ) /* CLR */
1851
1852/* Reset Value for T3STA*/
1853#define T3STA_RVAL 0x20
1854
1855/* T3STA[LOCK] - Lock status bit */
1856#define T3STA_LOCK_BBA (*(volatile unsigned long *) 0x4204B310)
1857#define T3STA_LOCK_MSK (0x1 << 4 )
1858#define T3STA_LOCK (0x1 << 4 )
1859#define T3STA_LOCK_CLR (0x0 << 4 ) /* CLR */
1860#define T3STA_LOCK_SET (0x1 << 4 ) /* SET */
1861
1862/* T3STA[CON] - T3CON write sync in progress */
1863#define T3STA_CON_BBA (*(volatile unsigned long *) 0x4204B30C)
1864#define T3STA_CON_MSK (0x1 << 3 )
1865#define T3STA_CON (0x1 << 3 )
1866#define T3STA_CON_CLR (0x0 << 3 ) /* CLR */
1867#define T3STA_CON_SET (0x1 << 3 ) /* SET */
1868
1869/* T3STA[LD] - T3LD write sync in progress */
1870#define T3STA_LD_BBA (*(volatile unsigned long *) 0x4204B308)
1871#define T3STA_LD_MSK (0x1 << 2 )
1872#define T3STA_LD (0x1 << 2 )
1873#define T3STA_LD_CLR (0x0 << 2 ) /* CLR */
1874#define T3STA_LD_SET (0x1 << 2 ) /* SET */
1875
1876/* T3STA[CLRI] - T3CLRI write sync in progress */
1877#define T3STA_CLRI_BBA (*(volatile unsigned long *) 0x4204B304)
1878#define T3STA_CLRI_MSK (0x1 << 1 )
1879#define T3STA_CLRI (0x1 << 1 )
1880#define T3STA_CLRI_CLR (0x0 << 1 ) /* CLR */
1881#define T3STA_CLRI_SET (0x1 << 1 ) /* SET */
1882
1883/* T3STA[IRQ] - Interrupt Pending */
1884#define T3STA_IRQ_BBA (*(volatile unsigned long *) 0x4204B300)
1885#define T3STA_IRQ_MSK (0x1 << 0 )
1886#define T3STA_IRQ (0x1 << 0 )
1887#define T3STA_IRQ_CLR (0x0 << 0 ) /* CLR */
1888#define T3STA_IRQ_SET (0x1 << 0 ) /* SET */
1889// ------------------------------------------------------------------------------------------------
1890// ----- WUT -----
1891// ------------------------------------------------------------------------------------------------
1892
1893
1894/**
1895 * @brief WakeUp Timer (pADI_WUT)
1896 */
1897
1898#if (__NO_MMR_STRUCTS__==0)
1899typedef struct { /*!< pADI_WUT Structure */
1900 __IO uint16_t T2VAL0; /*!< Current count value LSB */
1901 __I uint16_t RESERVED0;
1902 __IO uint16_t T2VAL1; /*!< Current count value MSB */
1903 __I uint16_t RESERVED1;
1904 __IO uint16_t T2CON; /*!< Control Register */
1905 __I uint16_t RESERVED2;
1906 __IO uint16_t T2INC; /*!< 12-bit register. Wake up field A */
1907 __I uint16_t RESERVED3;
1908 __IO uint16_t T2WUFB0; /*!< Wake up field B LSB */
1909 __I uint16_t RESERVED4;
1910 __IO uint16_t T2WUFB1; /*!< Wake up field B MSB */
1911 __I uint16_t RESERVED5;
1912 __IO uint16_t T2WUFC0; /*!< Wake up field C LSB */
1913 __I uint16_t RESERVED6;
1914 __IO uint16_t T2WUFC1; /*!< Wake up field C MSB */
1915 __I uint16_t RESERVED7;
1916 __IO uint16_t T2WUFD0; /*!< Wake up field D LSB */
1917 __I uint16_t RESERVED8;
1918 __IO uint16_t T2WUFD1; /*!< Wake up field D MSB */
1919 __I uint16_t RESERVED9;
1920 __IO uint16_t T2IEN; /*!< Interrupt enable */
1921 __I uint16_t RESERVED10;
1922 __IO uint16_t T2STA; /*!< Status */
1923 __I uint16_t RESERVED11;
1924 __IO uint16_t T2CLRI; /*!< Clear interrupts. Write only. */
1925 __I uint16_t RESERVED12[5];
1926 __IO uint16_t T2WUFA0; /*!< Wake up field A LSB. */
1927 __I uint16_t RESERVED13;
1928 __IO uint16_t T2WUFA1; /*!< Wake up field A MSB. */
1929} ADI_WUT_TypeDef;
1930#else // (__NO_MMR_STRUCTS__==0)
1931#define T2VAL0 (*(volatile unsigned short int *) 0x40002500)
1932#define T2VAL1 (*(volatile unsigned short int *) 0x40002504)
1933#define T2CON (*(volatile unsigned short int *) 0x40002508)
1934#define T2INC (*(volatile unsigned short int *) 0x4000250C)
1935#define T2WUFB0 (*(volatile unsigned short int *) 0x40002510)
1936#define T2WUFB1 (*(volatile unsigned short int *) 0x40002514)
1937#define T2WUFC0 (*(volatile unsigned short int *) 0x40002518)
1938#define T2WUFC1 (*(volatile unsigned short int *) 0x4000251C)
1939#define T2WUFD0 (*(volatile unsigned short int *) 0x40002520)
1940#define T2WUFD1 (*(volatile unsigned short int *) 0x40002524)
1941#define T2IEN (*(volatile unsigned short int *) 0x40002528)
1942#define T2STA (*(volatile unsigned short int *) 0x4000252C)
1943#define T2CLRI (*(volatile unsigned short int *) 0x40002530)
1944#define T2WUFA0 (*(volatile unsigned short int *) 0x4000253C)
1945#define T2WUFA1 (*(volatile unsigned short int *) 0x40002540)
1946#endif // (__NO_MMR_STRUCTS__==0)
1947
1948/* Reset Value for T2VAL0*/
1949#define T2VAL0_RVAL 0x0
1950
1951/* T2VAL0[VALUE] - Current Value */
1952#define T2VAL0_VALUE_MSK (0xFFFF << 0 )
1953
1954/* Reset Value for T2VAL1*/
1955#define T2VAL1_RVAL 0x0
1956
1957/* T2VAL1[VALUE] - Current Value */
1958#define T2VAL1_VALUE_MSK (0xFFFF << 0 )
1959
1960/* Reset Value for T2CON*/
1961#define T2CON_RVAL 0x40
1962
1963/* T2CON[STOPINC] - Stop wake up field A being updated */
1964#define T2CON_STOPINC_BBA (*(volatile unsigned long *) 0x4204A12C)
1965#define T2CON_STOPINC_MSK (0x1 << 11 )
1966#define T2CON_STOPINC (0x1 << 11 )
1967#define T2CON_STOPINC_DIS (0x0 << 11 ) /* DIS */
1968#define T2CON_STOPINC_EN (0x1 << 11 ) /* EN */
1969
1970/* T2CON[CLK] - Clock */
1971#define T2CON_CLK_MSK (0x3 << 9 )
1972#define T2CON_CLK_PCLK (0x0 << 9 ) /* PCLK */
1973#define T2CON_CLK_LFXTAL (0x1 << 9 ) /* LFXTAL */
1974#define T2CON_CLK_LFOSC (0x2 << 9 ) /* LFOSC */
1975#define T2CON_CLK_EXTCLK (0x3 << 9 ) /* EXTCLK */
1976
1977/* T2CON[WUEN] - WUEN */
1978#define T2CON_WUEN_BBA (*(volatile unsigned long *) 0x4204A120)
1979#define T2CON_WUEN_MSK (0x1 << 8 )
1980#define T2CON_WUEN (0x1 << 8 )
1981#define T2CON_WUEN_DIS (0x0 << 8 ) /* DIS */
1982#define T2CON_WUEN_EN (0x1 << 8 ) /* EN */
1983
1984/* T2CON[ENABLE] - Enable */
1985#define T2CON_ENABLE_BBA (*(volatile unsigned long *) 0x4204A11C)
1986#define T2CON_ENABLE_MSK (0x1 << 7 )
1987#define T2CON_ENABLE (0x1 << 7 )
1988#define T2CON_ENABLE_DIS (0x0 << 7 ) /* DIS */
1989#define T2CON_ENABLE_EN (0x1 << 7 ) /* EN */
1990
1991/* T2CON[MOD] - Mode */
1992#define T2CON_MOD_BBA (*(volatile unsigned long *) 0x4204A118)
1993#define T2CON_MOD_MSK (0x1 << 6 )
1994#define T2CON_MOD (0x1 << 6 )
1995#define T2CON_MOD_PERIODIC (0x0 << 6 ) /* PERIODIC */
1996#define T2CON_MOD_FREERUN (0x1 << 6 ) /* FREERUN */
1997
1998/* T2CON[FREEZE] - Freeze */
1999#define T2CON_FREEZE_BBA (*(volatile unsigned long *) 0x4204A10C)
2000#define T2CON_FREEZE_MSK (0x1 << 3 )
2001#define T2CON_FREEZE (0x1 << 3 )
2002#define T2CON_FREEZE_DIS (0x0 << 3 ) /* DIS */
2003#define T2CON_FREEZE_EN (0x1 << 3 ) /* EN */
2004
2005/* T2CON[PRE] - Prescaler */
2006#define T2CON_PRE_MSK (0x3 << 0 )
2007#define T2CON_PRE_DIV1 (0x0 << 0 ) /* DIV1 */
2008#define T2CON_PRE_DIV16 (0x1 << 0 ) /* DIV16 */
2009#define T2CON_PRE_DIV256 (0x2 << 0 ) /* DIV256 */
2010#define T2CON_PRE_DIV32768 (0x3 << 0 ) /* DIV32768 */
2011
2012/* Reset Value for T2INC*/
2013#define T2INC_RVAL 0xC8
2014
2015/* T2INC[VALUE] - 12 bit value */
2016#define T2INC_VALUE_MSK (0xFFF << 0 )
2017
2018/* Reset Value for T2WUFB0*/
2019#define T2WUFB0_RVAL 0x1FFF
2020
2021/* T2WUFB0[VALUE] - Current Value */
2022#define T2WUFB0_VALUE_MSK (0xFFFF << 0 )
2023
2024/* Reset Value for T2WUFB1*/
2025#define T2WUFB1_RVAL 0x0
2026
2027/* T2WUFB1[VALUE] - Current Value */
2028#define T2WUFB1_VALUE_MSK (0xFFFF << 0 )
2029
2030/* Reset Value for T2WUFC0*/
2031#define T2WUFC0_RVAL 0x2FFF
2032
2033/* T2WUFC0[VALUE] - Current Value */
2034#define T2WUFC0_VALUE_MSK (0xFFFF << 0 )
2035
2036/* Reset Value for T2WUFC1*/
2037#define T2WUFC1_RVAL 0x0
2038
2039/* T2WUFC1[VALUE] - Current Value */
2040#define T2WUFC1_VALUE_MSK (0xFFFF << 0 )
2041
2042/* Reset Value for T2WUFD0*/
2043#define T2WUFD0_RVAL 0x3FFF
2044
2045/* T2WUFD0[VALUE] - Current Value */
2046#define T2WUFD0_VALUE_MSK (0xFFFF << 0 )
2047
2048/* Reset Value for T2WUFD1*/
2049#define T2WUFD1_RVAL 0x0
2050
2051/* T2WUFD1[VALUE] - Current Value */
2052#define T2WUFD1_VALUE_MSK (0xFFFF << 0 )
2053
2054/* Reset Value for T2IEN*/
2055#define T2IEN_RVAL 0x0
2056
2057/* T2IEN[ROLL] - Enable interrupt on Rollover */
2058#define T2IEN_ROLL_BBA (*(volatile unsigned long *) 0x4204A510)
2059#define T2IEN_ROLL_MSK (0x1 << 4 )
2060#define T2IEN_ROLL (0x1 << 4 )
2061#define T2IEN_ROLL_DIS (0x0 << 4 ) /* DIS */
2062#define T2IEN_ROLL_EN (0x1 << 4 ) /* EN */
2063
2064/* T2IEN[WUFD] - Enable interrupt on WUFD */
2065#define T2IEN_WUFD_BBA (*(volatile unsigned long *) 0x4204A50C)
2066#define T2IEN_WUFD_MSK (0x1 << 3 )
2067#define T2IEN_WUFD (0x1 << 3 )
2068#define T2IEN_WUFD_DIS (0x0 << 3 ) /* DIS */
2069#define T2IEN_WUFD_EN (0x1 << 3 ) /* EN */
2070
2071/* T2IEN[WUFC] - Enable interrupt on WUFC */
2072#define T2IEN_WUFC_BBA (*(volatile unsigned long *) 0x4204A508)
2073#define T2IEN_WUFC_MSK (0x1 << 2 )
2074#define T2IEN_WUFC (0x1 << 2 )
2075#define T2IEN_WUFC_DIS (0x0 << 2 ) /* DIS */
2076#define T2IEN_WUFC_EN (0x1 << 2 ) /* EN */
2077
2078/* T2IEN[WUFB] - Enable interrupt on WUFB */
2079#define T2IEN_WUFB_BBA (*(volatile unsigned long *) 0x4204A504)
2080#define T2IEN_WUFB_MSK (0x1 << 1 )
2081#define T2IEN_WUFB (0x1 << 1 )
2082#define T2IEN_WUFB_DIS (0x0 << 1 ) /* DIS */
2083#define T2IEN_WUFB_EN (0x1 << 1 ) /* EN */
2084
2085/* T2IEN[WUFA] - Enable interrupt on WUFA */
2086#define T2IEN_WUFA_BBA (*(volatile unsigned long *) 0x4204A500)
2087#define T2IEN_WUFA_MSK (0x1 << 0 )
2088#define T2IEN_WUFA (0x1 << 0 )
2089#define T2IEN_WUFA_DIS (0x0 << 0 ) /* DIS */
2090#define T2IEN_WUFA_EN (0x1 << 0 ) /* EN */
2091
2092/* Reset Value for T2STA*/
2093#define T2STA_RVAL 0x0
2094
2095/* T2STA[CON] - Sync */
2096#define T2STA_CON_BBA (*(volatile unsigned long *) 0x4204A5A0)
2097#define T2STA_CON_MSK (0x1 << 8 )
2098#define T2STA_CON (0x1 << 8 )
2099#define T2STA_CON_CLR (0x0 << 8 ) /* CLR */
2100#define T2STA_CON_SET (0x1 << 8 ) /* SET */
2101
2102/* T2STA[FREEZE] - Timer Value Freeze */
2103#define T2STA_FREEZE_BBA (*(volatile unsigned long *) 0x4204A59C)
2104#define T2STA_FREEZE_MSK (0x1 << 7 )
2105#define T2STA_FREEZE (0x1 << 7 )
2106#define T2STA_FREEZE_CLR (0x0 << 7 ) /* CLR */
2107#define T2STA_FREEZE_SET (0x1 << 7 ) /* SET */
2108
2109/* T2STA[ROLL] - Rollover Interrupt */
2110#define T2STA_ROLL_BBA (*(volatile unsigned long *) 0x4204A590)
2111#define T2STA_ROLL_MSK (0x1 << 4 )
2112#define T2STA_ROLL (0x1 << 4 )
2113#define T2STA_ROLL_CLR (0x0 << 4 ) /* CLR */
2114#define T2STA_ROLL_SET (0x1 << 4 ) /* SET */
2115
2116/* T2STA[WUFD] - WUFD Interrupt */
2117#define T2STA_WUFD_BBA (*(volatile unsigned long *) 0x4204A58C)
2118#define T2STA_WUFD_MSK (0x1 << 3 )
2119#define T2STA_WUFD (0x1 << 3 )
2120#define T2STA_WUFD_CLR (0x0 << 3 ) /* CLR */
2121#define T2STA_WUFD_SET (0x1 << 3 ) /* SET */
2122
2123/* T2STA[WUFC] - WUFC Interrupt */
2124#define T2STA_WUFC_BBA (*(volatile unsigned long *) 0x4204A588)
2125#define T2STA_WUFC_MSK (0x1 << 2 )
2126#define T2STA_WUFC (0x1 << 2 )
2127#define T2STA_WUFC_CLR (0x0 << 2 ) /* CLR */
2128#define T2STA_WUFC_SET (0x1 << 2 ) /* SET */
2129
2130/* T2STA[WUFB] - WUFB Interrupt */
2131#define T2STA_WUFB_BBA (*(volatile unsigned long *) 0x4204A584)
2132#define T2STA_WUFB_MSK (0x1 << 1 )
2133#define T2STA_WUFB (0x1 << 1 )
2134#define T2STA_WUFB_CLR (0x0 << 1 ) /* CLR */
2135#define T2STA_WUFB_SET (0x1 << 1 ) /* SET */
2136
2137/* T2STA[WUFA] - WUFA Interrupt */
2138#define T2STA_WUFA_BBA (*(volatile unsigned long *) 0x4204A580)
2139#define T2STA_WUFA_MSK (0x1 << 0 )
2140#define T2STA_WUFA (0x1 << 0 )
2141#define T2STA_WUFA_CLR (0x0 << 0 ) /* CLR */
2142#define T2STA_WUFA_SET (0x1 << 0 ) /* SET */
2143
2144/* Reset Value for T2CLRI*/
2145#define T2CLRI_RVAL 0x0
2146
2147/* T2CLRI[ROLL] - Clear interrupt on Rollover */
2148#define T2CLRI_ROLL_BBA (*(volatile unsigned long *) 0x4204A610)
2149#define T2CLRI_ROLL_MSK (0x1 << 4 )
2150#define T2CLRI_ROLL (0x1 << 4 )
2151#define T2CLRI_ROLL_CLR (0x1 << 4 ) /* CLR */
2152
2153/* T2CLRI[WUFD] - Clear interrupt on WUFD */
2154#define T2CLRI_WUFD_BBA (*(volatile unsigned long *) 0x4204A60C)
2155#define T2CLRI_WUFD_MSK (0x1 << 3 )
2156#define T2CLRI_WUFD (0x1 << 3 )
2157#define T2CLRI_WUFD_CLR (0x1 << 3 ) /* CLR */
2158
2159/* T2CLRI[WUFC] - Clear interrupt on WUFC */
2160#define T2CLRI_WUFC_BBA (*(volatile unsigned long *) 0x4204A608)
2161#define T2CLRI_WUFC_MSK (0x1 << 2 )
2162#define T2CLRI_WUFC (0x1 << 2 )
2163#define T2CLRI_WUFC_CLR (0x1 << 2 ) /* CLR */
2164
2165/* T2CLRI[WUFB] - Clear interrupt on WUFB */
2166#define T2CLRI_WUFB_BBA (*(volatile unsigned long *) 0x4204A604)
2167#define T2CLRI_WUFB_MSK (0x1 << 1 )
2168#define T2CLRI_WUFB (0x1 << 1 )
2169#define T2CLRI_WUFB_CLR (0x1 << 1 ) /* CLR */
2170
2171/* T2CLRI[WUFA] - Clear interrupt on WUFA */
2172#define T2CLRI_WUFA_BBA (*(volatile unsigned long *) 0x4204A600)
2173#define T2CLRI_WUFA_MSK (0x1 << 0 )
2174#define T2CLRI_WUFA (0x1 << 0 )
2175#define T2CLRI_WUFA_CLR (0x1 << 0 ) /* CLR */
2176
2177/* Reset Value for T2WUFA0*/
2178#define T2WUFA0_RVAL 0x1900
2179
2180/* T2WUFA0[VALUE] - Current Value */
2181#define T2WUFA0_VALUE_MSK (0xFFFF << 0 )
2182
2183/* Reset Value for T2WUFA1*/
2184#define T2WUFA1_RVAL 0x0
2185
2186/* T2WUFA1[VALUE] - Current Value */
2187#define T2WUFA1_VALUE_MSK (0xFFFF << 0 )
2188// ------------------------------------------------------------------------------------------------
2189// ----- CLKCTL -----
2190// ------------------------------------------------------------------------------------------------
2191
2192
2193/**
2194 * @brief Clock Control (pADI_CLKCTL)
2195 */
2196
2197#if (__NO_MMR_STRUCTS__==0)
2198typedef struct { /*!< pADI_CLKCTL Structure */
2199 __IO uint16_t CLKCON0; /*!< System clocking architecture control register */
2200 __I uint16_t RESERVED0;
2201 __IO uint16_t CLKCON1; /*!< System Clocks Control Register 1 */
2202 __I uint16_t RESERVED1[19];
2203 __IO uint16_t CLKDIS; /*!< System Clocks Control Register 1 */
2204 __I uint16_t RESERVED2[7];
2205 __IO uint16_t CLKCON2; /*!< System Clocks Control Register 2 */
2206 __I uint16_t RESERVED3[489];
2207 __IO uint8_t XOSCCON; /*!< Crystal Oscillator control */
2208 __I uint8_t RESERVED4[51];
2209 __IO uint16_t CLKSYSDIV; /*!< Sys Clock div2 Register */
2210} ADI_CLKCTL_TypeDef;
2211#else // (__NO_MMR_STRUCTS__==0)
2212#define CLKCON0 (*(volatile unsigned short int *) 0x40002000)
2213#define CLKCON1 (*(volatile unsigned short int *) 0x40002004)
2214#define CLKDIS (*(volatile unsigned short int *) 0x4000202C)
2215#define CLKCON2 (*(volatile unsigned short int *) 0x4000203C)
2216#define XOSCCON (*(volatile unsigned char *) 0x40002410)
2217#define CLKSYSDIV (*(volatile unsigned short int *) 0x40002444)
2218#endif // (__NO_MMR_STRUCTS__==0)
2219
2220/* Reset Value for CLKCON0*/
2221#define CLKCON0_RVAL 0x0
2222
2223/* CLKCON0[CLKOUT] - GPIO output clock multiplexer select bits */
2224#define CLKCON0_CLKOUT_MSK (0x7 << 5 )
2225#define CLKCON0_CLKOUT_UCLKCG (0x0 << 5 ) /* UCLKCG */
2226#define CLKCON0_CLKOUT_UCLK (0x1 << 5 ) /* UCLK */
2227#define CLKCON0_CLKOUT_PCLK (0x2 << 5 ) /* PCLK */
2228#define CLKCON0_CLKOUT_HFOSC (0x5 << 5 ) /* HFOSC */
2229#define CLKCON0_CLKOUT_LFOSC (0x6 << 5 ) /* LFOSC */
2230#define CLKCON0_CLKOUT_LFXTAL (0x7 << 5 ) /* LFXTAL */
2231
2232/* CLKCON0[CLKMUX] - Digital subsystem clock source select bits. */
2233#define CLKCON0_CLKMUX_MSK (0x3 << 3 )
2234#define CLKCON0_CLKMUX_HFOSC (0x0 << 3 ) /* HFOSC */
2235#define CLKCON0_CLKMUX_LFXTAL (0x1 << 3 ) /* LFXTAL */
2236#define CLKCON0_CLKMUX_LFOSC (0x2 << 3 ) /* LFOSC */
2237#define CLKCON0_CLKMUX_EXTCLK (0x3 << 3 ) /* EXTCLK */
2238
2239/* CLKCON0[CD] - Clock divide bits */
2240#define CLKCON0_CD_MSK (0x7 << 0 )
2241#define CLKCON0_CD_DIV1 (0x0 << 0 ) /* DIV1 */
2242#define CLKCON0_CD_DIV2 (0x1 << 0 ) /* DIV2 */
2243#define CLKCON0_CD_DIV4 (0x2 << 0 ) /* DIV4 */
2244#define CLKCON0_CD_DIV8 (0x3 << 0 ) /* DIV8 */
2245#define CLKCON0_CD_DIV16 (0x4 << 0 ) /* DIV16 */
2246#define CLKCON0_CD_DIV32 (0x5 << 0 ) /* DIV32 */
2247#define CLKCON0_CD_DIV64 (0x6 << 0 ) /* DIV64 */
2248#define CLKCON0_CD_DIV128 (0x7 << 0 ) /* DIV128 */
2249
2250/* Reset Value for CLKCON1*/
2251#define CLKCON1_RVAL 0x0
2252
2253/* CLKCON1[PWMCD] - Clock divide bits for PWM system clock */
2254#define CLKCON1_PWMCD_MSK (0x7 << 12 )
2255#define CLKCON1_PWMCD_DIV1 (0x0 << 12 ) /* DIV1 */
2256#define CLKCON1_PWMCD_DIV2 (0x1 << 12 ) /* DIV2 */
2257#define CLKCON1_PWMCD_DIV4 (0x2 << 12 ) /* DIV4 */
2258#define CLKCON1_PWMCD_DIV8 (0x3 << 12 ) /* DIV8 */
2259#define CLKCON1_PWMCD_DIV16 (0x4 << 12 ) /* DIV16 */
2260#define CLKCON1_PWMCD_DIV32 (0x5 << 12 ) /* DIV32 */
2261#define CLKCON1_PWMCD_DIV64 (0x6 << 12 ) /* DIV64 */
2262#define CLKCON1_PWMCD_DIV128 (0x7 << 12 ) /* DIV128 */
2263
2264/* CLKCON1[UARTCD] - Clock divide bits for UART system clock */
2265#define CLKCON1_UARTCD_MSK (0x7 << 9 )
2266#define CLKCON1_UARTCD_DIV1 (0x0 << 9 ) /* DIV1 */
2267#define CLKCON1_UARTCD_DIV2 (0x1 << 9 ) /* DIV2 */
2268#define CLKCON1_UARTCD_DIV4 (0x2 << 9 ) /* DIV4 */
2269#define CLKCON1_UARTCD_DIV8 (0x3 << 9 ) /* DIV8 */
2270#define CLKCON1_UARTCD_DIV16 (0x4 << 9 ) /* DIV16 */
2271#define CLKCON1_UARTCD_DIV32 (0x5 << 9 ) /* DIV32 */
2272#define CLKCON1_UARTCD_DIV64 (0x6 << 9 ) /* DIV64 */
2273#define CLKCON1_UARTCD_DIV128 (0x7 << 9 ) /* DIV128 */
2274
2275/* CLKCON1[I2CCD] - Clock divide bits for I2C system clock */
2276#define CLKCON1_I2CCD_MSK (0x7 << 6 )
2277#define CLKCON1_I2CCD_DIV1 (0x0 << 6 ) /* DIV1 */
2278#define CLKCON1_I2CCD_DIV2 (0x1 << 6 ) /* DIV2 */
2279#define CLKCON1_I2CCD_DIV4 (0x2 << 6 ) /* DIV4 */
2280#define CLKCON1_I2CCD_DIV8 (0x3 << 6 ) /* DIV8 */
2281#define CLKCON1_I2CCD_DIV16 (0x4 << 6 ) /* DIV16 */
2282#define CLKCON1_I2CCD_DIV32 (0x5 << 6 ) /* DIV32 */
2283#define CLKCON1_I2CCD_DIV64 (0x6 << 6 ) /* DIV64 */
2284#define CLKCON1_I2CCD_DIV128 (0x7 << 6 ) /* DIV128 */
2285
2286/* CLKCON1[SPI1CD] - Clock divide bits for SPI1 system clock */
2287#define CLKCON1_SPI1CD_MSK (0x7 << 3 )
2288#define CLKCON1_SPI1CD_DIV1 (0x0 << 3 ) /* DIV1 */
2289#define CLKCON1_SPI1CD_DIV2 (0x1 << 3 ) /* DIV2 */
2290#define CLKCON1_SPI1CD_DIV4 (0x2 << 3 ) /* DIV4 */
2291#define CLKCON1_SPI1CD_DIV8 (0x3 << 3 ) /* DIV8 */
2292#define CLKCON1_SPI1CD_DIV16 (0x4 << 3 ) /* DIV16 */
2293#define CLKCON1_SPI1CD_DIV32 (0x5 << 3 ) /* DIV32 */
2294#define CLKCON1_SPI1CD_DIV64 (0x6 << 3 ) /* DIV64 */
2295#define CLKCON1_SPI1CD_DIV128 (0x7 << 3 ) /* DIV128 */
2296
2297/* CLKCON1[SPI0CD] - Clock divide bits for SPI0 system clock */
2298#define CLKCON1_SPI0CD_MSK (0x7 << 0 )
2299#define CLKCON1_SPI0CD_DIV1 (0x0 << 0 ) /* DIV1 */
2300#define CLKCON1_SPI0CD_DIV2 (0x1 << 0 ) /* DIV2 */
2301#define CLKCON1_SPI0CD_DIV4 (0x2 << 0 ) /* DIV4 */
2302#define CLKCON1_SPI0CD_DIV8 (0x3 << 0 ) /* DIV8 */
2303#define CLKCON1_SPI0CD_DIV16 (0x4 << 0 ) /* DIV16 */
2304#define CLKCON1_SPI0CD_DIV32 (0x5 << 0 ) /* DIV32 */
2305#define CLKCON1_SPI0CD_DIV64 (0x6 << 0 ) /* DIV64 */
2306#define CLKCON1_SPI0CD_DIV128 (0x7 << 0 ) /* DIV128 */
2307
2308/* Reset Value for CLKDIS*/
2309#define CLKDIS_RVAL 0xFFFF
2310
2311/* CLKDIS[DISADCCLK] - Disable ADC system clock */
2312#define CLKDIS_DISADCCLK_BBA (*(volatile unsigned long *) 0x420405A4)
2313#define CLKDIS_DISADCCLK_MSK (0x1 << 9 )
2314#define CLKDIS_DISADCCLK (0x1 << 9 )
2315#define CLKDIS_DISADCCLK_DIS (0x0 << 9 ) /* DIS */
2316#define CLKDIS_DISADCCLK_EN (0x1 << 9 ) /* EN */
2317
2318/* CLKDIS[DISDMACLK] - Disable DMA system clock */
2319#define CLKDIS_DISDMACLK_BBA (*(volatile unsigned long *) 0x420405A0)
2320#define CLKDIS_DISDMACLK_MSK (0x1 << 8 )
2321#define CLKDIS_DISDMACLK (0x1 << 8 )
2322#define CLKDIS_DISDMACLK_DIS (0x0 << 8 ) /* DIS */
2323#define CLKDIS_DISDMACLK_EN (0x1 << 8 ) /* EN */
2324
2325/* CLKDIS[DISDACCLK] - Disable DAC system clock */
2326#define CLKDIS_DISDACCLK_BBA (*(volatile unsigned long *) 0x4204059C)
2327#define CLKDIS_DISDACCLK_MSK (0x1 << 7 )
2328#define CLKDIS_DISDACCLK (0x1 << 7 )
2329#define CLKDIS_DISDACCLK_DIS (0x0 << 7 ) /* DIS */
2330#define CLKDIS_DISDACCLK_EN (0x1 << 7 ) /* EN */
2331
2332/* CLKDIS[DIST1CLK] - Disable Timer 1 system clock */
2333#define CLKDIS_DIST1CLK_BBA (*(volatile unsigned long *) 0x42040598)
2334#define CLKDIS_DIST1CLK_MSK (0x1 << 6 )
2335#define CLKDIS_DIST1CLK (0x1 << 6 )
2336#define CLKDIS_DIST1CLK_DIS (0x0 << 6 ) /* DIS */
2337#define CLKDIS_DIST1CLK_EN (0x1 << 6 ) /* EN */
2338
2339/* CLKDIS[DIST0CLK] - Disable Timer 0 system clock */
2340#define CLKDIS_DIST0CLK_BBA (*(volatile unsigned long *) 0x42040594)
2341#define CLKDIS_DIST0CLK_MSK (0x1 << 5 )
2342#define CLKDIS_DIST0CLK (0x1 << 5 )
2343#define CLKDIS_DIST0CLK_DIS (0x0 << 5 ) /* DIS */
2344#define CLKDIS_DIST0CLK_EN (0x1 << 5 ) /* EN */
2345
2346/* CLKDIS[DISPWMCLK] - Disable PWM system clock */
2347#define CLKDIS_DISPWMCLK_BBA (*(volatile unsigned long *) 0x42040590)
2348#define CLKDIS_DISPWMCLK_MSK (0x1 << 4 )
2349#define CLKDIS_DISPWMCLK (0x1 << 4 )
2350#define CLKDIS_DISPWMCLK_DIS (0x0 << 4 ) /* DIS */
2351#define CLKDIS_DISPWMCLK_EN (0x1 << 4 ) /* EN */
2352
2353/* CLKDIS[DISUARTCLK] - Disable UART system clock */
2354#define CLKDIS_DISUARTCLK_BBA (*(volatile unsigned long *) 0x4204058C)
2355#define CLKDIS_DISUARTCLK_MSK (0x1 << 3 )
2356#define CLKDIS_DISUARTCLK (0x1 << 3 )
2357#define CLKDIS_DISUARTCLK_DIS (0x0 << 3 ) /* DIS */
2358#define CLKDIS_DISUARTCLK_EN (0x1 << 3 ) /* EN */
2359
2360/* CLKDIS[DISI2CCLK] - Disable I2C system clock */
2361#define CLKDIS_DISI2CCLK_BBA (*(volatile unsigned long *) 0x42040588)
2362#define CLKDIS_DISI2CCLK_MSK (0x1 << 2 )
2363#define CLKDIS_DISI2CCLK (0x1 << 2 )
2364#define CLKDIS_DISI2CCLK_DIS (0x0 << 2 ) /* DIS */
2365#define CLKDIS_DISI2CCLK_EN (0x1 << 2 ) /* EN */
2366
2367/* CLKDIS[DISSPI1CLK] - Disable SPI1 system clock */
2368#define CLKDIS_DISSPI1CLK_BBA (*(volatile unsigned long *) 0x42040584)
2369#define CLKDIS_DISSPI1CLK_MSK (0x1 << 1 )
2370#define CLKDIS_DISSPI1CLK (0x1 << 1 )
2371#define CLKDIS_DISSPI1CLK_DIS (0x0 << 1 ) /* DIS */
2372#define CLKDIS_DISSPI1CLK_EN (0x1 << 1 ) /* EN */
2373
2374/* CLKDIS[DISSPI0CLK] - Disable SPI0 system clock bits */
2375#define CLKDIS_DISSPI0CLK_BBA (*(volatile unsigned long *) 0x42040580)
2376#define CLKDIS_DISSPI0CLK_MSK (0x1 << 0 )
2377#define CLKDIS_DISSPI0CLK (0x1 << 0 )
2378#define CLKDIS_DISSPI0CLK_DIS (0x0 << 0 ) /* DIS */
2379#define CLKDIS_DISSPI0CLK_EN (0x1 << 0 ) /* EN */
2380
2381/* CLKCON2[DISUART1CLK] - Disable UART1 system clock */
2382#define CLKCON2_DISUART1CLK_BBA (*(volatile unsigned long *) 0x42040780)
2383#define CLKCON2_DISUART1CLK_MSK (0x1 << 0 )
2384#define CLKCON2_DISUART1CLK (0x1 << 0 )
2385#define CLKCON2_DISUART1CLK_DIS (0x0 << 0 ) /* DIS */
2386#define CLKCON2_DISUART1CLK_EN (0x1 << 0 ) /* EN */
2387
2388/* CLKCON2[DISUART2CLK] - Disable UART2 system clock */
2389#define CLKCON2_DISUART2CLK_BBA (*(volatile unsigned long *) 0x42040784)
2390#define CLKCON2_DISUART2CLK_MSK (0x1 << 1 )
2391#define CLKCON2_DISUART2CLK (0x1 << 1 )
2392#define CLKCON2_DISUART2CLK_DIS (0x0 << 1 ) /* DIS */
2393#define CLKCON2_DISUART2CLK_EN (0x1 << 1 ) /* EN */
2394
2395/* CLKCON2[UART1CD] - Clock divide bits for UART1 system clock */
2396#define CLKCON2_UART1CD_MSK (0x7 << 8 )
2397#define CLKCON2_UART1CD_DIV1 (0x0 << 8 ) /* DIV1 */
2398#define CLKCON2_UART1CD_DIV2 (0x1 << 8 ) /* DIV2 */
2399#define CLKCON2_UART1CD_DIV4 (0x2 << 8 ) /* DIV4 */
2400#define CLKCON2_UART1CD_DIV8 (0x3 << 8 ) /* DIV8 */
2401#define CLKCON2_UART1CD_DIV16 (0x4 << 8 ) /* DIV16 */
2402#define CLKCON2_UART1CD_DIV32 (0x5 << 8 ) /* DIV32 */
2403#define CLKCON2_UART1CD_DIV64 (0x6 << 8 ) /* DIV64 */
2404#define CLKCON2_UART1CD_DIV128 (0x7 << 8 ) /* DIV128 */
2405
2406/* CLKCON2[UART2CD] - Clock divide bits for UART2 system clock */
2407#define CLKCON2_UART2CD_MSK (0x7 << 11 )
2408#define CLKCON2_UART2CD_DIV1 (0x0 << 11 ) /* DIV1 */
2409#define CLKCON2_UART2CD_DIV2 (0x1 << 11 ) /* DIV2 */
2410#define CLKCON2_UART2CD_DIV4 (0x2 << 11 ) /* DIV4 */
2411#define CLKCON2_UART2CD_DIV8 (0x3 << 11 ) /* DIV8 */
2412#define CLKCON2_UART2CD_DIV16 (0x4 << 11 ) /* DIV16 */
2413#define CLKCON2_UART2CD_DIV32 (0x5 << 11 ) /* DIV32 */
2414#define CLKCON2_UART2CD_DIV64 (0x6 << 11 ) /* DIV64 */
2415#define CLKCON2_UART2CD_DIV128 (0x7 << 11 ) /* DIV128 */
2416
2417/* CLKCON2[DACCD] - Clock divide bit for DAC system clock */
2418#define CLKCON2_DACCD_BBA (*(volatile unsigned long *) 0x420407B8)
2419#define CLKCON2_DACCD_MSK (0x1 << 14 )
2420#define CLKCON2_DACCD (0x1 << 14 )
2421#define CLKCON2_DACCD_DIV8 (0x0 << 14 ) /* DIV8 */
2422#define CLKCON2_DACCD_DIV16 (0x1 << 14 ) /* DIV16 */
2423
2424/* Reset Value for XOSCCON*/
2425#define XOSCCON_RVAL 0x0
2426
2427/* XOSCCON[DIV2] - Divide by two enable */
2428#define XOSCCON_DIV2_BBA (*(volatile unsigned long *) 0x42048208)
2429#define XOSCCON_DIV2_MSK (0x1 << 2 )
2430#define XOSCCON_DIV2 (0x1 << 2 )
2431#define XOSCCON_DIV2_DIS (0x0 << 2 ) /* DIS */
2432#define XOSCCON_DIV2_EN (0x1 << 2 ) /* EN */
2433
2434/* XOSCCON[ENABLE] - Crystal oscillator circuit enable (Enable the oscillator circuitry.) */
2435#define XOSCCON_ENABLE_BBA (*(volatile unsigned long *) 0x42048200)
2436#define XOSCCON_ENABLE_MSK (0x1 << 0 )
2437#define XOSCCON_ENABLE (0x1 << 0 )
2438#define XOSCCON_ENABLE_DIS (0x0 << 0 ) /* DIS */
2439#define XOSCCON_ENABLE_EN (0x1 << 0 ) /* EN */
2440
2441/* Reset Value for CLKSYSDIV*/
2442//#define CLKSYSDIV_RVAL 0x0
2443
2444/* CLKSYSDIV[UCLKCD] - bits */
2445#define CLKSYSDIV_UCLKCD_MSK (0x3 << 0 )
2446#define CLKSYSDIV_UCLKCD_DIV1 (0x0 << 0 )
2447#define CLKSYSDIV_UCLKCD_DIV2 (0x1 << 0 )
2448#define CLKSYSDIV_UCLKCD_DIV4 (0x2 << 0 )
2449#define CLKSYSDIV_UCLKCD_DIV8 (0x3 << 0 )
2450// ------------------------------------------------------------------------------------------------
2451// ----- FEE -----
2452// ------------------------------------------------------------------------------------------------
2453
2454
2455/**
2456 * @brief Flash Controller (pADI_FEE)
2457 */
2458
2459#if (__NO_MMR_STRUCTS__==0)
2460typedef struct { /*!< pADI_FEE Structure */
2461 __IO uint16_t FEESTA; /*!< Status Register */
2462 __I uint16_t RESERVED0;
2463 __IO uint16_t FEECON0; /*!< Command Control Register */
2464 __I uint16_t RESERVED1;
2465 __IO uint16_t FEECMD; /*!< Command register */
2466 __I uint16_t RESERVED2[3];
2467 __IO uint16_t FEEADR0L; /*!< Low Page (Lower 16 bits) */
2468 __I uint16_t RESERVED3;
2469 __IO uint16_t FEEADR0H; /*!< Low Page (Upper 16 bits) */
2470 __I uint16_t RESERVED4;
2471 __IO uint16_t FEEADR1L; /*!< Hi Page (Lower 16 bits) */
2472 __I uint16_t RESERVED5;
2473 __IO uint16_t FEEADR1H; /*!< Hi Page (Upper 16 bits) */
2474 __I uint16_t RESERVED6;
2475 __IO uint16_t FEEKEY; /*!< Key */
2476 __I uint16_t RESERVED7[3];
2477 __IO uint16_t FEEPROL; /*!< Write Protection (Lower 16 bits) */
2478 __I uint16_t RESERVED8;
2479 __IO uint16_t FEEPROH; /*!< Write Protection (Upper 16 bits) */
2480 __I uint16_t RESERVED9;
2481 __IO uint16_t FEESIGL; /*!< Signature (Lower 16 bits) */
2482 __I uint16_t RESERVED10;
2483 __IO uint16_t FEESIGH; /*!< Signature (Upper 16 bits) */
2484 __I uint16_t RESERVED11;
2485 __IO uint16_t FEECON1; /*!< User Setup register */
2486 __I uint16_t RESERVED12[7];
2487 __IO uint16_t FEEADRAL; /*!< Abort address (Lower 16 bits) */
2488 __I uint16_t RESERVED13;
2489 __IO uint16_t FEEADRAH; /*!< Abort address (Upper 16 bits) */
2490 __I uint16_t RESERVED14[21];
2491 __IO uint16_t FEEAEN0; /*!< Lower 16 bits of the sys irq abort enable register. */
2492 __I uint16_t RESERVED15;
2493 __IO uint16_t FEEAEN1; /*!< Upper 16 bits of the sys irq abort enable register. */
2494 __I uint16_t RESERVED16;
2495 __IO uint16_t FEEAEN2; /*!< Upper 32..47 bits of the sys irq abort enable register. */
2496} ADI_FEE_TypeDef;
2497#else // (__NO_MMR_STRUCTS__==0)
2498#define FEESTA (*(volatile unsigned short int *) 0x40002800)
2499#define FEECON0 (*(volatile unsigned short int *) 0x40002804)
2500#define FEECMD (*(volatile unsigned short int *) 0x40002808)
2501#define FEEADR0L (*(volatile unsigned short int *) 0x40002810)
2502#define FEEADR0H (*(volatile unsigned short int *) 0x40002814)
2503#define FEEADR1L (*(volatile unsigned short int *) 0x40002818)
2504#define FEEADR1H (*(volatile unsigned short int *) 0x4000281C)
2505#define FEEKEY (*(volatile unsigned short int *) 0x40002820)
2506#define FEEPROL (*(volatile unsigned short int *) 0x40002828)
2507#define FEEPROH (*(volatile unsigned short int *) 0x4000282C)
2508#define FEESIGL (*(volatile unsigned short int *) 0x40002830)
2509#define FEESIGH (*(volatile unsigned short int *) 0x40002834)
2510#define FEECON1 (*(volatile unsigned short int *) 0x40002838)
2511#define FEEADRAL (*(volatile unsigned short int *) 0x40002848)
2512#define FEEADRAH (*(volatile unsigned short int *) 0x4000284C)
2513#define FEEAEN0 (*(volatile unsigned short int *) 0x40002878)
2514#define FEEAEN1 (*(volatile unsigned short int *) 0x4000287C)
2515#define FEEAEN2 (*(volatile unsigned short int *) 0x40002880)
2516#endif // (__NO_MMR_STRUCTS__==0)
2517
2518/* Reset Value for FEESTA*/
2519#define FEESTA_RVAL 0x0
2520
2521/* FEESTA[SIGNERR] - Info space signature check on reset error */
2522#define FEESTA_SIGNERR_BBA (*(volatile unsigned long *) 0x42050018)
2523#define FEESTA_SIGNERR_MSK (0x1 << 6 )
2524#define FEESTA_SIGNERR (0x1 << 6 )
2525#define FEESTA_SIGNERR_CLR (0x0 << 6 ) /* CLR */
2526#define FEESTA_SIGNERR_SET (0x1 << 6 ) /* SET */
2527
2528/* FEESTA[CMDRES] - Command result */
2529#define FEESTA_CMDRES_MSK (0x3 << 4 )
2530#define FEESTA_CMDRES_SUCCESS (0x0 << 4 ) /* SUCCESS */
2531#define FEESTA_CMDRES_PROTECTED (0x1 << 4 ) /* PROTECTED */
2532#define FEESTA_CMDRES_VERIFYERR (0x2 << 4 ) /* VERIFYERR */
2533#define FEESTA_CMDRES_ABORT (0x3 << 4 ) /* ABORT */
2534
2535/* FEESTA[WRDONE] - Write Complete */
2536#define FEESTA_WRDONE_BBA (*(volatile unsigned long *) 0x4205000C)
2537#define FEESTA_WRDONE_MSK (0x1 << 3 )
2538#define FEESTA_WRDONE (0x1 << 3 )
2539#define FEESTA_WRDONE_CLR (0x0 << 3 ) /* CLR */
2540#define FEESTA_WRDONE_SET (0x1 << 3 ) /* SET */
2541
2542/* FEESTA[CMDDONE] - Command complete */
2543#define FEESTA_CMDDONE_BBA (*(volatile unsigned long *) 0x42050008)
2544#define FEESTA_CMDDONE_MSK (0x1 << 2 )
2545#define FEESTA_CMDDONE (0x1 << 2 )
2546#define FEESTA_CMDDONE_CLR (0x0 << 2 ) /* CLR */
2547#define FEESTA_CMDDONE_SET (0x1 << 2 ) /* SET */
2548
2549/* FEESTA[WRBUSY] - Write busy */
2550#define FEESTA_WRBUSY_BBA (*(volatile unsigned long *) 0x42050004)
2551#define FEESTA_WRBUSY_MSK (0x1 << 1 )
2552#define FEESTA_WRBUSY (0x1 << 1 )
2553#define FEESTA_WRBUSY_CLR (0x0 << 1 ) /* CLR */
2554#define FEESTA_WRBUSY_SET (0x1 << 1 ) /* SET */
2555
2556/* FEESTA[CMDBUSY] - Command busy */
2557#define FEESTA_CMDBUSY_BBA (*(volatile unsigned long *) 0x42050000)
2558#define FEESTA_CMDBUSY_MSK (0x1 << 0 )
2559#define FEESTA_CMDBUSY (0x1 << 0 )
2560#define FEESTA_CMDBUSY_CLR (0x0 << 0 ) /* CLR */
2561#define FEESTA_CMDBUSY_SET (0x1 << 0 ) /* SET */
2562
2563/* Reset Value for FEECON0*/
2564#define FEECON0_RVAL 0x0
2565
2566/* FEECON0[WREN] - Write enable. */
2567#define FEECON0_WREN_BBA (*(volatile unsigned long *) 0x42050088)
2568#define FEECON0_WREN_MSK (0x1 << 2 )
2569#define FEECON0_WREN (0x1 << 2 )
2570#define FEECON0_WREN_DIS (0x0 << 2 ) /* DIS */
2571#define FEECON0_WREN_EN (0x1 << 2 ) /* EN */
2572
2573/* FEECON0[IENERR] - Error interrupt enable */
2574#define FEECON0_IENERR_BBA (*(volatile unsigned long *) 0x42050084)
2575#define FEECON0_IENERR_MSK (0x1 << 1 )
2576#define FEECON0_IENERR (0x1 << 1 )
2577#define FEECON0_IENERR_DIS (0x0 << 1 ) /* DIS */
2578#define FEECON0_IENERR_EN (0x1 << 1 ) /* EN */
2579
2580/* FEECON0[IENCMD] - Command complete interrupt enable */
2581#define FEECON0_IENCMD_BBA (*(volatile unsigned long *) 0x42050080)
2582#define FEECON0_IENCMD_MSK (0x1 << 0 )
2583#define FEECON0_IENCMD (0x1 << 0 )
2584#define FEECON0_IENCMD_DIS (0x0 << 0 ) /* DIS */
2585#define FEECON0_IENCMD_EN (0x1 << 0 ) /* EN */
2586
2587/* Reset Value for FEECMD*/
2588#define FEECMD_RVAL 0x0
2589
2590/* FEECMD[CMD] - Command */
2591#define FEECMD_CMD_MSK (0xF << 0 )
2592#define FEECMD_CMD_IDLE (0x0 << 0 ) /* IDLE - No command executed */
2593#define FEECMD_CMD_ERASEPAGE (0x1 << 0 ) /* ERASEPAGE - Erase Page */
2594#define FEECMD_CMD_SIGN (0x2 << 0 ) /* SIGN - Sign Range */
2595#define FEECMD_CMD_MASSERASE (0x3 << 0 ) /* MASSERASE - Mass Erase User Space */
2596#define FEECMD_CMD_ABORT (0x4 << 0 ) /* ABORT - Abort a running command */
2597
2598/* Reset Value for FEEADR0L*/
2599#define FEEADR0L_RVAL 0x0
2600
2601/* FEEADR0L[VALUE] - Value */
2602#define FEEADR0L_VALUE_MSK (0xFFFF << 0 )
2603
2604/* Reset Value for FEEADR0H*/
2605#define FEEADR0H_RVAL 0x0
2606
2607/* FEEADR0H[VALUE] - Value */
2608#define FEEADR0H_VALUE_MSK (0x3 << 0 )
2609
2610/* Reset Value for FEEADR1L*/
2611#define FEEADR1L_RVAL 0x0
2612
2613/* FEEADR1L[VALUE] - Value */
2614#define FEEADR1L_VALUE_MSK (0xFFFF << 0 )
2615
2616/* Reset Value for FEEADR1H*/
2617#define FEEADR1H_RVAL 0x0
2618
2619/* FEEADR1H[VALUE] - Value */
2620#define FEEADR1H_VALUE_MSK (0x3 << 0 )
2621
2622/* Reset Value for FEEKEY*/
2623#define FEEKEY_RVAL 0x0
2624
2625/* FEEKEY[VALUE] - Value */
2626#define FEEKEY_VALUE_MSK (0xFFFF << 0 )
2627#define FEEKEY_VALUE_USERKEY1 (0xF456 << 0 ) /* USERKEY1 */
2628#define FEEKEY_VALUE_USERKEY2 (0xF123 << 0 ) /* USERKEY2 */
2629
2630/* Reset Value for FEEPROL*/
2631#define FEEPROL_RVAL 0xFFFF
2632
2633/* FEEPROL[VALUE] - Value */
2634#define FEEPROL_VALUE_MSK (0xFFFF << 0 )
2635
2636/* Reset Value for FEEPROH*/
2637#define FEEPROH_RVAL 0xFFFF
2638
2639/* FEEPROH[VALUE] - Value */
2640#define FEEPROH_VALUE_MSK (0xFFFF << 0 )
2641
2642/* Reset Value for FEESIGL*/
2643#define FEESIGL_RVAL 0xFFFF
2644
2645/* FEESIGL[VALUE] - Value */
2646#define FEESIGL_VALUE_MSK (0xFFFF << 0 )
2647
2648/* Reset Value for FEESIGH*/
2649#define FEESIGH_RVAL 0xFFFF
2650
2651/* FEESIGH[VALUE] - Value */
2652#define FEESIGH_VALUE_MSK (0xFF << 0 )
2653
2654/* Reset Value for FEECON1*/
2655#define FEECON1_RVAL 0x1
2656
2657/* FEECON1[DBG] - Serial Wire debug enable , */
2658#define FEECON1_DBG_BBA (*(volatile unsigned long *) 0x42050700)
2659#define FEECON1_DBG_MSK (0x1 << 0 )
2660#define FEECON1_DBG (0x1 << 0 )
2661#define FEECON1_DBG_DIS (0x0 << 0 ) /* DIS */
2662#define FEECON1_DBG_EN (0x1 << 0 ) /* EN */
2663
2664/* Reset Value for FEEADRAL*/
2665#define FEEADRAL_RVAL 0x800
2666
2667/* FEEADRAL[VALUE] - Value */
2668#define FEEADRAL_VALUE_MSK (0xFFFF << 0 )
2669
2670/* Reset Value for FEEADRAH*/
2671#define FEEADRAH_RVAL 0x2
2672
2673/* FEEADRAH[VALUE] - Value */
2674#define FEEADRAH_VALUE_MSK (0xFFFF << 0 )
2675
2676/* Reset Value for FEEAEN0*/
2677#define FEEAEN0_RVAL 0x0
2678
2679/* FEEAEN0[SINC2] - */
2680#define FEEAEN0_SINC2_BBA (*(volatile unsigned long *) 0x42050F3C)
2681#define FEEAEN0_SINC2_MSK (0x1 << 15 )
2682#define FEEAEN0_SINC2 (0x1 << 15 )
2683#define FEEAEN0_SINC2_DIS (0x0 << 15 ) /* DIS */
2684#define FEEAEN0_SINC2_EN (0x1 << 15 ) /* EN */
2685
2686/* FEEAEN0[ADC1] - */
2687#define FEEAEN0_ADC1_BBA (*(volatile unsigned long *) 0x42050F38)
2688#define FEEAEN0_ADC1_MSK (0x1 << 14 )
2689#define FEEAEN0_ADC1 (0x1 << 14 )
2690#define FEEAEN0_ADC1_DIS (0x0 << 14 ) /* DIS */
2691#define FEEAEN0_ADC1_EN (0x1 << 14 ) /* EN */
2692
2693/* FEEAEN0[T1] - */
2694#define FEEAEN0_T1_BBA (*(volatile unsigned long *) 0x42050F30)
2695#define FEEAEN0_T1_MSK (0x1 << 12 )
2696#define FEEAEN0_T1 (0x1 << 12 )
2697#define FEEAEN0_T1_DIS (0x0 << 12 ) /* DIS */
2698#define FEEAEN0_T1_EN (0x1 << 12 ) /* EN */
2699
2700/* FEEAEN0[T0] - */
2701#define FEEAEN0_T0_BBA (*(volatile unsigned long *) 0x42050F2C)
2702#define FEEAEN0_T0_MSK (0x1 << 11 )
2703#define FEEAEN0_T0 (0x1 << 11 )
2704#define FEEAEN0_T0_DIS (0x0 << 11 ) /* DIS */
2705#define FEEAEN0_T0_EN (0x1 << 11 ) /* EN */
2706
2707/* FEEAEN0[T3] - */
2708#define FEEAEN0_T3_BBA (*(volatile unsigned long *) 0x42050F24)
2709#define FEEAEN0_T3_MSK (0x1 << 9 )
2710#define FEEAEN0_T3 (0x1 << 9 )
2711#define FEEAEN0_T3_DIS (0x0 << 9 ) /* DIS */
2712#define FEEAEN0_T3_EN (0x1 << 9 ) /* EN */
2713
2714/* FEEAEN0[EXTINT7] - */
2715#define FEEAEN0_EXTINT7_BBA (*(volatile unsigned long *) 0x42050F20)
2716#define FEEAEN0_EXTINT7_MSK (0x1 << 8 )
2717#define FEEAEN0_EXTINT7 (0x1 << 8 )
2718#define FEEAEN0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
2719#define FEEAEN0_EXTINT7_EN (0x1 << 8 ) /* EN */
2720
2721/* FEEAEN0[EXTINT6] - */
2722#define FEEAEN0_EXTINT6_BBA (*(volatile unsigned long *) 0x42050F1C)
2723#define FEEAEN0_EXTINT6_MSK (0x1 << 7 )
2724#define FEEAEN0_EXTINT6 (0x1 << 7 )
2725#define FEEAEN0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
2726#define FEEAEN0_EXTINT6_EN (0x1 << 7 ) /* EN */
2727
2728/* FEEAEN0[EXTINT5] - */
2729#define FEEAEN0_EXTINT5_BBA (*(volatile unsigned long *) 0x42050F18)
2730#define FEEAEN0_EXTINT5_MSK (0x1 << 6 )
2731#define FEEAEN0_EXTINT5 (0x1 << 6 )
2732#define FEEAEN0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
2733#define FEEAEN0_EXTINT5_EN (0x1 << 6 ) /* EN */
2734
2735/* FEEAEN0[EXTINT4] - */
2736#define FEEAEN0_EXTINT4_BBA (*(volatile unsigned long *) 0x42050F14)
2737#define FEEAEN0_EXTINT4_MSK (0x1 << 5 )
2738#define FEEAEN0_EXTINT4 (0x1 << 5 )
2739#define FEEAEN0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
2740#define FEEAEN0_EXTINT4_EN (0x1 << 5 ) /* EN */
2741
2742/* FEEAEN0[EXTINT3] - */
2743#define FEEAEN0_EXTINT3_BBA (*(volatile unsigned long *) 0x42050F10)
2744#define FEEAEN0_EXTINT3_MSK (0x1 << 4 )
2745#define FEEAEN0_EXTINT3 (0x1 << 4 )
2746#define FEEAEN0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
2747#define FEEAEN0_EXTINT3_EN (0x1 << 4 ) /* EN */
2748
2749/* FEEAEN0[EXTINT2] - */
2750#define FEEAEN0_EXTINT2_BBA (*(volatile unsigned long *) 0x42050F0C)
2751#define FEEAEN0_EXTINT2_MSK (0x1 << 3 )
2752#define FEEAEN0_EXTINT2 (0x1 << 3 )
2753#define FEEAEN0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
2754#define FEEAEN0_EXTINT2_EN (0x1 << 3 ) /* EN */
2755
2756/* FEEAEN0[EXTINT1] - */
2757#define FEEAEN0_EXTINT1_BBA (*(volatile unsigned long *) 0x42050F08)
2758#define FEEAEN0_EXTINT1_MSK (0x1 << 2 )
2759#define FEEAEN0_EXTINT1 (0x1 << 2 )
2760#define FEEAEN0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
2761#define FEEAEN0_EXTINT1_EN (0x1 << 2 ) /* EN */
2762
2763/* FEEAEN0[EXTINT0] - */
2764#define FEEAEN0_EXTINT0_BBA (*(volatile unsigned long *) 0x42050F04)
2765#define FEEAEN0_EXTINT0_MSK (0x1 << 1 )
2766#define FEEAEN0_EXTINT0 (0x1 << 1 )
2767#define FEEAEN0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
2768#define FEEAEN0_EXTINT0_EN (0x1 << 1 ) /* EN */
2769
2770/* FEEAEN0[T2] - */
2771#define FEEAEN0_T2_BBA (*(volatile unsigned long *) 0x42050F00)
2772#define FEEAEN0_T2_MSK (0x1 << 0 )
2773#define FEEAEN0_T2 (0x1 << 0 )
2774#define FEEAEN0_T2_DIS (0x0 << 0 ) /* DIS */
2775#define FEEAEN0_T2_EN (0x1 << 0 ) /* EN */
2776
2777/* Reset Value for FEEAEN1*/
2778#define FEEAEN1_RVAL 0x0
2779
2780/* FEEAEN1[DMADAC] - */
2781#define FEEAEN1_DMADAC_BBA (*(volatile unsigned long *) 0x42050FBC)
2782#define FEEAEN1_DMADAC_MSK (0x1 << 15 )
2783#define FEEAEN1_DMADAC (0x1 << 15 )
2784#define FEEAEN1_DMADAC_DIS (0x0 << 15 ) /* DIS */
2785#define FEEAEN1_DMADAC_EN (0x1 << 15 ) /* EN */
2786
2787/* FEEAEN1[DMAI2CMRX] - */
2788#define FEEAEN1_DMAI2CMRX_BBA (*(volatile unsigned long *) 0x42050FB8)
2789#define FEEAEN1_DMAI2CMRX_MSK (0x1 << 14 )
2790#define FEEAEN1_DMAI2CMRX (0x1 << 14 )
2791#define FEEAEN1_DMAI2CMRX_DIS (0x0 << 14 ) /* DIS */
2792#define FEEAEN1_DMAI2CMRX_EN (0x1 << 14 ) /* EN */
2793
2794/* FEEAEN1[DMAI2CMTX] - */
2795#define FEEAEN1_DMAI2CMTX_BBA (*(volatile unsigned long *) 0x42050FB4)
2796#define FEEAEN1_DMAI2CMTX_MSK (0x1 << 13 )
2797#define FEEAEN1_DMAI2CMTX (0x1 << 13 )
2798#define FEEAEN1_DMAI2CMTX_DIS (0x0 << 13 ) /* DIS */
2799#define FEEAEN1_DMAI2CMTX_EN (0x1 << 13 ) /* EN */
2800
2801/* FEEAEN1[DMAI2CSRX] - */
2802#define FEEAEN1_DMAI2CSRX_BBA (*(volatile unsigned long *) 0x42050FB0)
2803#define FEEAEN1_DMAI2CSRX_MSK (0x1 << 12 )
2804#define FEEAEN1_DMAI2CSRX (0x1 << 12 )
2805#define FEEAEN1_DMAI2CSRX_DIS (0x0 << 12 ) /* DIS */
2806#define FEEAEN1_DMAI2CSRX_EN (0x1 << 12 ) /* EN */
2807
2808/* FEEAEN1[DMAI2CSTX] - */
2809#define FEEAEN1_DMAI2CSTX_BBA (*(volatile unsigned long *) 0x42050FAC)
2810#define FEEAEN1_DMAI2CSTX_MSK (0x1 << 11 )
2811#define FEEAEN1_DMAI2CSTX (0x1 << 11 )
2812#define FEEAEN1_DMAI2CSTX_DIS (0x0 << 11 ) /* DIS */
2813#define FEEAEN1_DMAI2CSTX_EN (0x1 << 11 ) /* EN */
2814
2815/* FEEAEN1[DMAUARTRX] - */
2816#define FEEAEN1_DMAUARTRX_BBA (*(volatile unsigned long *) 0x42050FA8)
2817#define FEEAEN1_DMAUARTRX_MSK (0x1 << 10 )
2818#define FEEAEN1_DMAUARTRX (0x1 << 10 )
2819#define FEEAEN1_DMAUARTRX_DIS (0x0 << 10 ) /* DIS */
2820#define FEEAEN1_DMAUARTRX_EN (0x1 << 10 ) /* EN */
2821
2822/* FEEAEN1[DMAUARTTX] - */
2823#define FEEAEN1_DMAUARTTX_BBA (*(volatile unsigned long *) 0x42050FA4)
2824#define FEEAEN1_DMAUARTTX_MSK (0x1 << 9 )
2825#define FEEAEN1_DMAUARTTX (0x1 << 9 )
2826#define FEEAEN1_DMAUARTTX_DIS (0x0 << 9 ) /* DIS */
2827#define FEEAEN1_DMAUARTTX_EN (0x1 << 9 ) /* EN */
2828
2829/* FEEAEN1[DMASPI1RX] - */
2830#define FEEAEN1_DMASPI1RX_BBA (*(volatile unsigned long *) 0x42050FA0)
2831#define FEEAEN1_DMASPI1RX_MSK (0x1 << 8 )
2832#define FEEAEN1_DMASPI1RX (0x1 << 8 )
2833#define FEEAEN1_DMASPI1RX_DIS (0x0 << 8 ) /* DIS */
2834#define FEEAEN1_DMASPI1RX_EN (0x1 << 8 ) /* EN */
2835
2836/* FEEAEN1[DMASPI1TX] - */
2837#define FEEAEN1_DMASPI1TX_BBA (*(volatile unsigned long *) 0x42050F9C)
2838#define FEEAEN1_DMASPI1TX_MSK (0x1 << 7 )
2839#define FEEAEN1_DMASPI1TX (0x1 << 7 )
2840#define FEEAEN1_DMASPI1TX_DIS (0x0 << 7 ) /* DIS */
2841#define FEEAEN1_DMASPI1TX_EN (0x1 << 7 ) /* EN */
2842
2843/* FEEAEN1[DMAERROR] - */
2844#define FEEAEN1_DMAERROR_BBA (*(volatile unsigned long *) 0x42050F98)
2845#define FEEAEN1_DMAERROR_MSK (0x1 << 6 )
2846#define FEEAEN1_DMAERROR (0x1 << 6 )
2847#define FEEAEN1_DMAERROR_DIS (0x0 << 6 ) /* DIS */
2848#define FEEAEN1_DMAERROR_EN (0x1 << 6 ) /* EN */
2849
2850/* FEEAEN1[I2CM] - */
2851#define FEEAEN1_I2CM_BBA (*(volatile unsigned long *) 0x42050F94)
2852#define FEEAEN1_I2CM_MSK (0x1 << 5 )
2853#define FEEAEN1_I2CM (0x1 << 5 )
2854#define FEEAEN1_I2CM_DIS (0x0 << 5 ) /* DIS */
2855#define FEEAEN1_I2CM_EN (0x1 << 5 ) /* EN */
2856
2857/* FEEAEN1[I2CS] - */
2858#define FEEAEN1_I2CS_BBA (*(volatile unsigned long *) 0x42050F90)
2859#define FEEAEN1_I2CS_MSK (0x1 << 4 )
2860#define FEEAEN1_I2CS (0x1 << 4 )
2861#define FEEAEN1_I2CS_DIS (0x0 << 4 ) /* DIS */
2862#define FEEAEN1_I2CS_EN (0x1 << 4 ) /* EN */
2863
2864/* FEEAEN1[SPI1] - */
2865#define FEEAEN1_SPI1_BBA (*(volatile unsigned long *) 0x42050F8C)
2866#define FEEAEN1_SPI1_MSK (0x1 << 3 )
2867#define FEEAEN1_SPI1 (0x1 << 3 )
2868#define FEEAEN1_SPI1_DIS (0x0 << 3 ) /* DIS */
2869#define FEEAEN1_SPI1_EN (0x1 << 3 ) /* EN */
2870
2871/* FEEAEN1[SPI0] - */
2872#define FEEAEN1_SPI0_BBA (*(volatile unsigned long *) 0x42050F88)
2873#define FEEAEN1_SPI0_MSK (0x1 << 2 )
2874#define FEEAEN1_SPI0 (0x1 << 2 )
2875#define FEEAEN1_SPI0_DIS (0x0 << 2 ) /* DIS */
2876#define FEEAEN1_SPI0_EN (0x1 << 2 ) /* EN */
2877
2878/* FEEAEN1[UART] - */
2879#define FEEAEN1_UART_BBA (*(volatile unsigned long *) 0x42050F84)
2880#define FEEAEN1_UART_MSK (0x1 << 1 )
2881#define FEEAEN1_UART (0x1 << 1 )
2882#define FEEAEN1_UART_DIS (0x0 << 1 ) /* DIS */
2883#define FEEAEN1_UART_EN (0x1 << 1 ) /* EN */
2884
2885/* FEEAEN1[FEE] - */
2886#define FEEAEN1_FEE_BBA (*(volatile unsigned long *) 0x42050F80)
2887#define FEEAEN1_FEE_MSK (0x1 << 0 )
2888#define FEEAEN1_FEE (0x1 << 0 )
2889#define FEEAEN1_FEE_DIS (0x0 << 0 ) /* DIS */
2890#define FEEAEN1_FEE_EN (0x1 << 0 ) /* EN */
2891
2892/* Reset Value for FEEAEN2*/
2893#define FEEAEN2_RVAL 0x0
2894
2895/* FEEAEN2[PWM2] - */
2896#define FEEAEN2_PWM2_BBA (*(volatile unsigned long *) 0x42051018)
2897#define FEEAEN2_PWM2_MSK (0x1 << 6 )
2898#define FEEAEN2_PWM2 (0x1 << 6 )
2899#define FEEAEN2_PWM2_DIS (0x0 << 6 ) /* DIS */
2900#define FEEAEN2_PWM2_EN (0x1 << 6 ) /* EN */
2901
2902/* FEEAEN2[PWM1] - */
2903#define FEEAEN2_PWM1_BBA (*(volatile unsigned long *) 0x42051014)
2904#define FEEAEN2_PWM1_MSK (0x1 << 5 )
2905#define FEEAEN2_PWM1 (0x1 << 5 )
2906#define FEEAEN2_PWM1_DIS (0x0 << 5 ) /* DIS */
2907#define FEEAEN2_PWM1_EN (0x1 << 5 ) /* EN */
2908
2909/* FEEAEN2[PWM0] - */
2910#define FEEAEN2_PWM0_BBA (*(volatile unsigned long *) 0x42051010)
2911#define FEEAEN2_PWM0_MSK (0x1 << 4 )
2912#define FEEAEN2_PWM0 (0x1 << 4 )
2913#define FEEAEN2_PWM0_DIS (0x0 << 4 ) /* DIS */
2914#define FEEAEN2_PWM0_EN (0x1 << 4 ) /* EN */
2915
2916/* FEEAEN2[PWMTRIP] - */
2917#define FEEAEN2_PWMTRIP_BBA (*(volatile unsigned long *) 0x4205100C)
2918#define FEEAEN2_PWMTRIP_MSK (0x1 << 3 )
2919#define FEEAEN2_PWMTRIP (0x1 << 3 )
2920#define FEEAEN2_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
2921#define FEEAEN2_PWMTRIP_EN (0x1 << 3 ) /* EN */
2922
2923/* FEEAEN2[DMASINC2] - */
2924#define FEEAEN2_DMASINC2_BBA (*(volatile unsigned long *) 0x42051008)
2925#define FEEAEN2_DMASINC2_MSK (0x1 << 2 )
2926#define FEEAEN2_DMASINC2 (0x1 << 2 )
2927#define FEEAEN2_DMASINC2_DIS (0x0 << 2 ) /* DIS */
2928#define FEEAEN2_DMASINC2_EN (0x1 << 2 ) /* EN */
2929
2930/* FEEAEN2[DMAADC1] - */
2931#define FEEAEN2_DMAADC1_BBA (*(volatile unsigned long *) 0x42051004)
2932#define FEEAEN2_DMAADC1_MSK (0x1 << 1 )
2933#define FEEAEN2_DMAADC1 (0x1 << 1 )
2934#define FEEAEN2_DMAADC1_DIS (0x0 << 1 ) /* DIS */
2935#define FEEAEN2_DMAADC1_EN (0x1 << 1 ) /* EN */
2936
2937// ------------------------------------------------------------------------------------------------
2938// ----- I2C -----
2939// ------------------------------------------------------------------------------------------------
2940
2941
2942/**
2943 * @brief I2C (pADI_I2C)
2944 */
2945
2946#if (__NO_MMR_STRUCTS__==0)
2947typedef struct { /*!< pADI_I2C Structure */
2948 __IO uint16_t I2CMCON; /*!< Master Control Register */
2949 __I uint16_t RESERVED0;
2950 __IO uint16_t I2CMSTA; /*!< Master Status Register */
2951 __I uint16_t RESERVED1;
2952 __IO uint8_t I2CMRX; /*!< Master Receive Data */
2953 __I uint8_t RESERVED2[3];
2954 __IO uint8_t I2CMTX; /*!< Master Transmit Data */
2955 __I uint8_t RESERVED3[3];
2956 __IO uint16_t I2CMRXCNT; /*!< Master Receive Data Count */
2957 __I uint16_t RESERVED4;
2958 __IO uint16_t I2CMCRXCNT; /*!< Master Current Receive Data Count */
2959 __I uint16_t RESERVED5;
2960 __IO uint8_t I2CADR0; /*!< 1st Master Address Byte */
2961 __I uint8_t RESERVED6[3];
2962 __IO uint8_t I2CADR1; /*!< 2nd Master Address Byte */
2963 __I uint8_t RESERVED7[7];
2964 __IO uint16_t I2CDIV; /*!< Serial clock period divisor register */
2965 __I uint16_t RESERVED8;
2966 __IO uint16_t I2CSCON; /*!< Slave Control Register */
2967 __I uint16_t RESERVED9;
2968 __IO uint16_t I2CSSTA; /*!< "Slave I2C Status, Error and IRQ Register" */
2969 __I uint16_t RESERVED10;
2970 __IO uint16_t I2CSRX; /*!< Slave Receive Data Register */
2971 __I uint16_t RESERVED11;
2972 __IO uint16_t I2CSTX; /*!< Slave Transmit Data Register */
2973 __I uint16_t RESERVED12;
2974 __IO uint16_t I2CALT; /*!< Hardware General Call ID */
2975 __I uint16_t RESERVED13;
2976 __IO uint16_t I2CID0; /*!< 1st Slave Address Device ID */
2977 __I uint16_t RESERVED14;
2978 __IO uint16_t I2CID1; /*!< 2nd Slave Address Device ID */
2979 __I uint16_t RESERVED15;
2980 __IO uint16_t I2CID2; /*!< 3rd Slave Address Device ID */
2981 __I uint16_t RESERVED16;
2982 __IO uint16_t I2CID3; /*!< 4th Slave Address Device ID */
2983 __I uint16_t RESERVED17;
2984 __IO uint16_t I2CFSTA; /*!< Master and Slave Rx/Tx FIFO Status Register */
2985 __I uint16_t RESERVED18;
2986 __IO uint16_t I2CSHCON; /*!< Shared control register */
2987 __I uint16_t RESERVED19[3];
2988 __IO uint16_t I2CASSCL; /*!< Automatic Stretch control register */
2989} ADI_I2C_TypeDef;
2990#else // (__NO_MMR_STRUCTS__==0)
2991#define I2CMCON (*(volatile unsigned short int *) 0x40003000)
2992#define I2CMSTA (*(volatile unsigned short int *) 0x40003004)
2993#define I2CMRX (*(volatile unsigned char *) 0x40003008)
2994#define I2CMTX (*(volatile unsigned char *) 0x4000300C)
2995#define I2CMRXCNT (*(volatile unsigned short int *) 0x40003010)
2996#define I2CMCRXCNT (*(volatile unsigned short int *) 0x40003014)
2997#define I2CADR0 (*(volatile unsigned char *) 0x40003018)
2998#define I2CADR1 (*(volatile unsigned char *) 0x4000301C)
2999#define I2CDIV (*(volatile unsigned short int *) 0x40003024)
3000#define I2CSCON (*(volatile unsigned short int *) 0x40003028)
3001#define I2CSSTA (*(volatile unsigned short int *) 0x4000302C)
3002#define I2CSRX (*(volatile unsigned short int *) 0x40003030)
3003#define I2CSTX (*(volatile unsigned short int *) 0x40003034)
3004#define I2CALT (*(volatile unsigned short int *) 0x40003038)
3005#define I2CID0 (*(volatile unsigned short int *) 0x4000303C)
3006#define I2CID1 (*(volatile unsigned short int *) 0x40003040)
3007#define I2CID2 (*(volatile unsigned short int *) 0x40003044)
3008#define I2CID3 (*(volatile unsigned short int *) 0x40003048)
3009#define I2CFSTA (*(volatile unsigned short int *) 0x4000304C)
3010#define I2CSHCON (*(volatile unsigned short int *) 0x40003050)
3011#define I2CASSCL (*(volatile unsigned short int *) 0x40003058)
3012#endif // (__NO_MMR_STRUCTS__==0)
3013
3014/* Reset Value for I2CMCON*/
3015#define I2CMCON_RVAL 0x0
3016
3017/* I2CMCON[TXDMA] - Enable master Tx DMA request */
3018#define I2CMCON_TXDMA_BBA (*(volatile unsigned long *) 0x4206002C)
3019#define I2CMCON_TXDMA_MSK (0x1 << 11 )
3020#define I2CMCON_TXDMA (0x1 << 11 )
3021#define I2CMCON_TXDMA_DIS (0x0 << 11 ) /* DIS */
3022#define I2CMCON_TXDMA_EN (0x1 << 11 ) /* EN */
3023
3024/* I2CMCON[RXDMA] - Enable master Rx DMA request */
3025#define I2CMCON_RXDMA_BBA (*(volatile unsigned long *) 0x42060028)
3026#define I2CMCON_RXDMA_MSK (0x1 << 10 )
3027#define I2CMCON_RXDMA (0x1 << 10 )
3028#define I2CMCON_RXDMA_DIS (0x0 << 10 ) /* DIS */
3029#define I2CMCON_RXDMA_EN (0x1 << 10 ) /* EN */
3030
3031/* I2CMCON[IENCMP] - Transaction completed interrupt enable */
3032#define I2CMCON_IENCMP_BBA (*(volatile unsigned long *) 0x42060020)
3033#define I2CMCON_IENCMP_MSK (0x1 << 8 )
3034#define I2CMCON_IENCMP (0x1 << 8 )
3035#define I2CMCON_IENCMP_DIS (0x0 << 8 ) /* DIS */
3036#define I2CMCON_IENCMP_EN (0x1 << 8 ) /* EN */
3037
3038/* I2CMCON[IENNACK] - ACK not received interrupt enable */
3039#define I2CMCON_IENNACK_BBA (*(volatile unsigned long *) 0x4206001C)
3040#define I2CMCON_IENNACK_MSK (0x1 << 7 )
3041#define I2CMCON_IENNACK (0x1 << 7 )
3042#define I2CMCON_IENNACK_DIS (0x0 << 7 ) /* DIS */
3043#define I2CMCON_IENNACK_EN (0x1 << 7 ) /* EN */
3044
3045/* I2CMCON[IENALOST] - Arbitration lost interrupt enable */
3046#define I2CMCON_IENALOST_BBA (*(volatile unsigned long *) 0x42060018)
3047#define I2CMCON_IENALOST_MSK (0x1 << 6 )
3048#define I2CMCON_IENALOST (0x1 << 6 )
3049#define I2CMCON_IENALOST_DIS (0x0 << 6 ) /* DIS */
3050#define I2CMCON_IENALOST_EN (0x1 << 6 ) /* EN */
3051
3052/* I2CMCON[IENTX] - Transmit request interrupt enable */
3053#define I2CMCON_IENTX_BBA (*(volatile unsigned long *) 0x42060014)
3054#define I2CMCON_IENTX_MSK (0x1 << 5 )
3055#define I2CMCON_IENTX (0x1 << 5 )
3056#define I2CMCON_IENTX_DIS (0x0 << 5 ) /* DIS */
3057#define I2CMCON_IENTX_EN (0x1 << 5 ) /* EN */
3058
3059/* I2CMCON[IENRX] - Receive request interrupt enable */
3060#define I2CMCON_IENRX_BBA (*(volatile unsigned long *) 0x42060010)
3061#define I2CMCON_IENRX_MSK (0x1 << 4 )
3062#define I2CMCON_IENRX (0x1 << 4 )
3063#define I2CMCON_IENRX_DIS (0x0 << 4 ) /* DIS */
3064#define I2CMCON_IENRX_EN (0x1 << 4 ) /* EN */
3065
3066/* I2CMCON[STRETCH] - Stretch SCL */
3067#define I2CMCON_STRETCH_BBA (*(volatile unsigned long *) 0x4206000C)
3068#define I2CMCON_STRETCH_MSK (0x1 << 3 )
3069#define I2CMCON_STRETCH (0x1 << 3 )
3070#define I2CMCON_STRETCH_DIS (0x0 << 3 ) /* DIS */
3071#define I2CMCON_STRETCH_EN (0x1 << 3 ) /* EN */
3072
3073/* I2CMCON[LOOPBACK] - Internal loop back */
3074#define I2CMCON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42060008)
3075#define I2CMCON_LOOPBACK_MSK (0x1 << 2 )
3076#define I2CMCON_LOOPBACK (0x1 << 2 )
3077#define I2CMCON_LOOPBACK_DIS (0x0 << 2 ) /* DIS */
3078#define I2CMCON_LOOPBACK_EN (0x1 << 2 ) /* EN */
3079
3080/* I2CMCON[COMPETE] - Compete for ownership */
3081#define I2CMCON_COMPETE_BBA (*(volatile unsigned long *) 0x42060004)
3082#define I2CMCON_COMPETE_MSK (0x1 << 1 )
3083#define I2CMCON_COMPETE (0x1 << 1 )
3084#define I2CMCON_COMPETE_DIS (0x0 << 1 ) /* DIS */
3085#define I2CMCON_COMPETE_EN (0x1 << 1 ) /* EN */
3086
3087/* I2CMCON[MAS] - Master Enable */
3088#define I2CMCON_MAS_BBA (*(volatile unsigned long *) 0x42060000)
3089#define I2CMCON_MAS_MSK (0x1 << 0 )
3090#define I2CMCON_MAS (0x1 << 0 )
3091#define I2CMCON_MAS_DIS (0x0 << 0 ) /* DIS */
3092#define I2CMCON_MAS_EN (0x1 << 0 ) /* EN */
3093
3094/* Reset Value for I2CMSTA*/
3095#define I2CMSTA_RVAL 0x0
3096
3097/* I2CMSTA[TXUR] - Master Transmit FIFO underflow */
3098#define I2CMSTA_TXUR_BBA (*(volatile unsigned long *) 0x420600B0)
3099#define I2CMSTA_TXUR_MSK (0x1 << 12 )
3100#define I2CMSTA_TXUR (0x1 << 12 )
3101#define I2CMSTA_TXUR_CLR (0x0 << 12 ) /* CLR */
3102#define I2CMSTA_TXUR_SET (0x1 << 12 ) /* SET */
3103
3104/* I2CMSTA[MSTOP] - STOP driven by th eI2C master */
3105#define I2CMSTA_MSTOP_BBA (*(volatile unsigned long *) 0x420600AC)
3106#define I2CMSTA_MSTOP_MSK (0x1 << 11 )
3107#define I2CMSTA_MSTOP (0x1 << 11 )
3108#define I2CMSTA_MSTOP_CLR (0x0 << 11 ) /* CLR */
3109#define I2CMSTA_MSTOP_SET (0x1 << 11 ) /* SET */
3110
3111/* I2CMSTA[LINEBUSY] - Line is busy */
3112#define I2CMSTA_LINEBUSY_BBA (*(volatile unsigned long *) 0x420600A8)
3113#define I2CMSTA_LINEBUSY_MSK (0x1 << 10 )
3114#define I2CMSTA_LINEBUSY (0x1 << 10 )
3115#define I2CMSTA_LINEBUSY_CLR (0x0 << 10 ) /* CLR */
3116#define I2CMSTA_LINEBUSY_SET (0x1 << 10 ) /* SET */
3117
3118/* I2CMSTA[RXOF] - Receive FIFO overflow */
3119#define I2CMSTA_RXOF_BBA (*(volatile unsigned long *) 0x420600A4)
3120#define I2CMSTA_RXOF_MSK (0x1 << 9 )
3121#define I2CMSTA_RXOF (0x1 << 9 )
3122#define I2CMSTA_RXOF_CLR (0x0 << 9 ) /* CLR */
3123#define I2CMSTA_RXOF_SET (0x1 << 9 ) /* SET */
3124
3125/* I2CMSTA[TCOMP] - Transaction completed */
3126#define I2CMSTA_TCOMP_BBA (*(volatile unsigned long *) 0x420600A0)
3127#define I2CMSTA_TCOMP_MSK (0x1 << 8 )
3128#define I2CMSTA_TCOMP (0x1 << 8 )
3129#define I2CMSTA_TCOMP_CLR (0x0 << 8 ) /* CLR */
3130#define I2CMSTA_TCOMP_SET (0x1 << 8 ) /* SET */
3131
3132/* I2CMSTA[NACKDATA] - Ack not received in response to data write */
3133#define I2CMSTA_NACKDATA_BBA (*(volatile unsigned long *) 0x4206009C)
3134#define I2CMSTA_NACKDATA_MSK (0x1 << 7 )
3135#define I2CMSTA_NACKDATA (0x1 << 7 )
3136#define I2CMSTA_NACKDATA_CLR (0x0 << 7 ) /* CLR */
3137#define I2CMSTA_NACKDATA_SET (0x1 << 7 ) /* SET */
3138
3139/* I2CMSTA[BUSY] - Master Busy */
3140#define I2CMSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060098)
3141#define I2CMSTA_BUSY_MSK (0x1 << 6 )
3142#define I2CMSTA_BUSY (0x1 << 6 )
3143#define I2CMSTA_BUSY_CLR (0x0 << 6 ) /* CLR */
3144#define I2CMSTA_BUSY_SET (0x1 << 6 ) /* SET */
3145
3146/* I2CMSTA[ALOST] - Arbitration lost */
3147#define I2CMSTA_ALOST_BBA (*(volatile unsigned long *) 0x42060094)
3148#define I2CMSTA_ALOST_MSK (0x1 << 5 )
3149#define I2CMSTA_ALOST (0x1 << 5 )
3150#define I2CMSTA_ALOST_CLR (0x0 << 5 ) /* CLR */
3151#define I2CMSTA_ALOST_SET (0x1 << 5 ) /* SET */
3152
3153/* I2CMSTA[NACKADDR] - Ack not received in response to an address */
3154#define I2CMSTA_NACKADDR_BBA (*(volatile unsigned long *) 0x42060090)
3155#define I2CMSTA_NACKADDR_MSK (0x1 << 4 )
3156#define I2CMSTA_NACKADDR (0x1 << 4 )
3157#define I2CMSTA_NACKADDR_CLR (0x0 << 4 ) /* CLR */
3158#define I2CMSTA_NACKADDR_SET (0x1 << 4 ) /* SET */
3159
3160/* I2CMSTA[RXREQ] - Receive request */
3161#define I2CMSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206008C)
3162#define I2CMSTA_RXREQ_MSK (0x1 << 3 )
3163#define I2CMSTA_RXREQ (0x1 << 3 )
3164#define I2CMSTA_RXREQ_CLR (0x0 << 3 ) /* CLR */
3165#define I2CMSTA_RXREQ_SET (0x1 << 3 ) /* SET */
3166
3167/* I2CMSTA[TXREQ] - Transmit request */
3168#define I2CMSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060088)
3169#define I2CMSTA_TXREQ_MSK (0x1 << 2 )
3170#define I2CMSTA_TXREQ (0x1 << 2 )
3171#define I2CMSTA_TXREQ_CLR (0x0 << 2 ) /* CLR */
3172#define I2CMSTA_TXREQ_SET (0x1 << 2 ) /* SET */
3173
3174/* I2CMSTA[TXFSTA] - Transmit FIFO Status */
3175#define I2CMSTA_TXFSTA_MSK (0x3 << 0 )
3176#define I2CMSTA_TXFSTA_EMPTY (0x0 << 0 ) /* EMPTY */
3177#define I2CMSTA_TXFSTA_ONEBYTE (0x1 << 0 ) /* ONEBYTE */
3178#define I2CMSTA_TXFSTA_FULL (0x3 << 0 ) /* FULL */
3179
3180/* Reset Value for I2CMRX*/
3181#define I2CMRX_RVAL 0x0
3182
3183/* I2CMRX[VALUE] - Current Receive Value */
3184#define I2CMRX_VALUE_MSK (0xFF << 0 )
3185
3186/* Reset Value for I2CMTX*/
3187#define I2CMTX_RVAL 0x0
3188
3189/* I2CMTX[VALUE] - Current Transmit Value */
3190#define I2CMTX_VALUE_MSK (0xFF << 0 )
3191
3192/* Reset Value for I2CMRXCNT*/
3193#define I2CMRXCNT_RVAL 0x0
3194
3195/* I2CMRXCNT[EXTEND] - Extended Read */
3196#define I2CMRXCNT_EXTEND_BBA (*(volatile unsigned long *) 0x42060220)
3197#define I2CMRXCNT_EXTEND_MSK (0x1 << 8 )
3198#define I2CMRXCNT_EXTEND (0x1 << 8 )
3199#define I2CMRXCNT_EXTEND_DIS (0x0 << 8 ) /* DIS */
3200#define I2CMRXCNT_EXTEND_EN (0x1 << 8 ) /* EN */
3201
3202/* I2CMRXCNT[COUNT] - Receive count */
3203#define I2CMRXCNT_COUNT_MSK (0xFF << 0 )
3204
3205/* Reset Value for I2CMCRXCNT*/
3206#define I2CMCRXCNT_RVAL 0x0
3207
3208/* I2CMCRXCNT[VALUE] - Current Receive count */
3209#define I2CMCRXCNT_VALUE_MSK (0xFF << 0 )
3210
3211/* Reset Value for I2CADR0*/
3212#define I2CADR0_RVAL 0x0
3213
3214/* I2CADR0[VALUE] - Address byte */
3215#define I2CADR0_VALUE_MSK (0xFF << 0 )
3216
3217/* Reset Value for I2CADR1*/
3218#define I2CADR1_RVAL 0x0
3219
3220/* I2CADR1[VALUE] - Address byte */
3221#define I2CADR1_VALUE_MSK (0xFF << 0 )
3222
3223/* Reset Value for I2CDIV*/
3224#define I2CDIV_RVAL 0x1F1F
3225
3226/* I2CDIV[HIGH] - High Time */
3227#define I2CDIV_HIGH_MSK (0xFF << 8 )
3228
3229/* I2CDIV[LOW] - Low Time */
3230#define I2CDIV_LOW_MSK (0xFF << 0 )
3231
3232/* Reset Value for I2CSCON*/
3233#define I2CSCON_RVAL 0x0
3234
3235/* I2CSCON[TXDMA] - Enable slave Tx DMA request */
3236#define I2CSCON_TXDMA_BBA (*(volatile unsigned long *) 0x42060538)
3237#define I2CSCON_TXDMA_MSK (0x1 << 14 )
3238#define I2CSCON_TXDMA (0x1 << 14 )
3239#define I2CSCON_TXDMA_DIS (0x0 << 14 ) /* DIS */
3240#define I2CSCON_TXDMA_EN (0x1 << 14 ) /* EN */
3241
3242/* I2CSCON[RXDMA] - Enable slave Rx DMA request */
3243#define I2CSCON_RXDMA_BBA (*(volatile unsigned long *) 0x42060534)
3244#define I2CSCON_RXDMA_MSK (0x1 << 13 )
3245#define I2CSCON_RXDMA (0x1 << 13 )
3246#define I2CSCON_RXDMA_DIS (0x0 << 13 ) /* DIS */
3247#define I2CSCON_RXDMA_EN (0x1 << 13 ) /* EN */
3248
3249/* I2CSCON[IENREPST] - Repeated start interrupt enable */
3250#define I2CSCON_IENREPST_BBA (*(volatile unsigned long *) 0x42060530)
3251#define I2CSCON_IENREPST_MSK (0x1 << 12 )
3252#define I2CSCON_IENREPST (0x1 << 12 )
3253#define I2CSCON_IENREPST_DIS (0x0 << 12 ) /* DIS */
3254#define I2CSCON_IENREPST_EN (0x1 << 12 ) /* EN */
3255
3256/* I2CSCON[IENTX] - Transmit request interrupt enable */
3257#define I2CSCON_IENTX_BBA (*(volatile unsigned long *) 0x42060528)
3258#define I2CSCON_IENTX_MSK (0x1 << 10 )
3259#define I2CSCON_IENTX (0x1 << 10 )
3260#define I2CSCON_IENTX_DIS (0x0 << 10 ) /* DIS */
3261#define I2CSCON_IENTX_EN (0x1 << 10 ) /* EN */
3262
3263/* I2CSCON[IENRX] - Receive request interrupt enable */
3264#define I2CSCON_IENRX_BBA (*(volatile unsigned long *) 0x42060524)
3265#define I2CSCON_IENRX_MSK (0x1 << 9 )
3266#define I2CSCON_IENRX (0x1 << 9 )
3267#define I2CSCON_IENRX_DIS (0x0 << 9 ) /* DIS */
3268#define I2CSCON_IENRX_EN (0x1 << 9 ) /* EN */
3269
3270/* I2CSCON[IENSTOP] - Stop condition detected interrupt enable */
3271#define I2CSCON_IENSTOP_BBA (*(volatile unsigned long *) 0x42060520)
3272#define I2CSCON_IENSTOP_MSK (0x1 << 8 )
3273#define I2CSCON_IENSTOP (0x1 << 8 )
3274#define I2CSCON_IENSTOP_DIS (0x0 << 8 ) /* DIS */
3275#define I2CSCON_IENSTOP_EN (0x1 << 8 ) /* EN */
3276
3277/* I2CSCON[NACK] - NACK next communication */
3278#define I2CSCON_NACK_BBA (*(volatile unsigned long *) 0x4206051C)
3279#define I2CSCON_NACK_MSK (0x1 << 7 )
3280#define I2CSCON_NACK (0x1 << 7 )
3281#define I2CSCON_NACK_DIS (0x0 << 7 ) /* DIS */
3282#define I2CSCON_NACK_EN (0x1 << 7 ) /* EN */
3283
3284/* I2CSCON[STRETCH] - Stretch SCL */
3285#define I2CSCON_STRETCH_BBA (*(volatile unsigned long *) 0x42060518)
3286#define I2CSCON_STRETCH_MSK (0x1 << 6 )
3287#define I2CSCON_STRETCH (0x1 << 6 )
3288#define I2CSCON_STRETCH_DIS (0x0 << 6 ) /* DIS */
3289#define I2CSCON_STRETCH_EN (0x1 << 6 ) /* EN */
3290
3291/* I2CSCON[EARLYTXR] - Early transmit request mode */
3292#define I2CSCON_EARLYTXR_BBA (*(volatile unsigned long *) 0x42060514)
3293#define I2CSCON_EARLYTXR_MSK (0x1 << 5 )
3294#define I2CSCON_EARLYTXR (0x1 << 5 )
3295#define I2CSCON_EARLYTXR_DIS (0x0 << 5 ) /* DIS */
3296#define I2CSCON_EARLYTXR_EN (0x1 << 5 ) /* EN */
3297
3298/* I2CSCON[GCSB] - General call status bit clear */
3299#define I2CSCON_GCSB_BBA (*(volatile unsigned long *) 0x42060510)
3300#define I2CSCON_GCSB_MSK (0x1 << 4 )
3301#define I2CSCON_GCSB (0x1 << 4 )
3302#define I2CSCON_GCSB_CLR (0x1 << 4 ) /* CLR */
3303
3304/* I2CSCON[HGC] - Hardware general Call enable */
3305#define I2CSCON_HGC_BBA (*(volatile unsigned long *) 0x4206050C)
3306#define I2CSCON_HGC_MSK (0x1 << 3 )
3307#define I2CSCON_HGC (0x1 << 3 )
3308#define I2CSCON_HGC_DIS (0x0 << 3 ) /* DIS */
3309#define I2CSCON_HGC_EN (0x1 << 3 ) /* EN */
3310
3311/* I2CSCON[GC] - General Call enable */
3312#define I2CSCON_GC_BBA (*(volatile unsigned long *) 0x42060508)
3313#define I2CSCON_GC_MSK (0x1 << 2 )
3314#define I2CSCON_GC (0x1 << 2 )
3315#define I2CSCON_GC_DIS (0x0 << 2 ) /* DIS */
3316#define I2CSCON_GC_EN (0x1 << 2 ) /* EN */
3317
3318/* I2CSCON[ADR10] - Enable 10 bit addressing */
3319#define I2CSCON_ADR10_BBA (*(volatile unsigned long *) 0x42060504)
3320#define I2CSCON_ADR10_MSK (0x1 << 1 )
3321#define I2CSCON_ADR10 (0x1 << 1 )
3322#define I2CSCON_ADR10_DIS (0x0 << 1 ) /* DIS */
3323#define I2CSCON_ADR10_EN (0x1 << 1 ) /* EN */
3324
3325/* I2CSCON[SLV] - Slave Enable */
3326#define I2CSCON_SLV_BBA (*(volatile unsigned long *) 0x42060500)
3327#define I2CSCON_SLV_MSK (0x1 << 0 )
3328#define I2CSCON_SLV (0x1 << 0 )
3329#define I2CSCON_SLV_DIS (0x0 << 0 ) /* DIS */
3330#define I2CSCON_SLV_EN (0x1 << 0 ) /* EN */
3331
3332/* Reset Value for I2CSSTA*/
3333#define I2CSSTA_RVAL 0x1
3334
3335/* I2CSSTA[START] - Start and matching address */
3336#define I2CSSTA_START_BBA (*(volatile unsigned long *) 0x420605B8)
3337#define I2CSSTA_START_MSK (0x1 << 14 )
3338#define I2CSSTA_START (0x1 << 14 )
3339#define I2CSSTA_START_CLR (0x0 << 14 ) /* CLR */
3340#define I2CSSTA_START_SET (0x1 << 14 ) /* SET */
3341
3342/* I2CSSTA[REPSTART] - Repeated start and matching address */
3343#define I2CSSTA_REPSTART_BBA (*(volatile unsigned long *) 0x420605B4)
3344#define I2CSSTA_REPSTART_MSK (0x1 << 13 )
3345#define I2CSSTA_REPSTART (0x1 << 13 )
3346#define I2CSSTA_REPSTART_CLR (0x0 << 13 ) /* CLR */
3347#define I2CSSTA_REPSTART_SET (0x1 << 13 ) /* SET */
3348
3349/* I2CSSTA[IDMAT] - Device ID matched */
3350#define I2CSSTA_IDMAT_MSK (0x3 << 11 )
3351#define I2CSSTA_IDMAT_CLR (0x0 << 11 ) /* CLR */
3352#define I2CSSTA_IDMAT_SET (0x1 << 11 ) /* SET */
3353
3354/* I2CSSTA[STOP] - Stop after start and matching address */
3355#define I2CSSTA_STOP_BBA (*(volatile unsigned long *) 0x420605A8)
3356#define I2CSSTA_STOP_MSK (0x1 << 10 )
3357#define I2CSSTA_STOP (0x1 << 10 )
3358#define I2CSSTA_STOP_CLR (0x0 << 10 ) /* CLR */
3359#define I2CSSTA_STOP_SET (0x1 << 10 ) /* SET */
3360
3361/* I2CSSTA[GCID] - General ID */
3362#define I2CSSTA_GCID_MSK (0x3 << 8 )
3363#define I2CSSTA_GCID_CLR (0x0 << 8 ) /* CLR */
3364#define I2CSSTA_GCID_SET (0x1 << 8 ) /* SET */
3365
3366/* I2CSSTA[GCINT] - General call */
3367#define I2CSSTA_GCINT_BBA (*(volatile unsigned long *) 0x4206059C)
3368#define I2CSSTA_GCINT_MSK (0x1 << 7 )
3369#define I2CSSTA_GCINT (0x1 << 7 )
3370#define I2CSSTA_GCINT_CLR (0x0 << 7 ) /* CLR */
3371#define I2CSSTA_GCINT_SET (0x1 << 7 ) /* SET */
3372
3373/* I2CSSTA[BUSY] - Slave busy */
3374#define I2CSSTA_BUSY_BBA (*(volatile unsigned long *) 0x42060598)
3375#define I2CSSTA_BUSY_MSK (0x1 << 6 )
3376#define I2CSSTA_BUSY (0x1 << 6 )
3377#define I2CSSTA_BUSY_CLR (0x0 << 6 ) /* CLR */
3378#define I2CSSTA_BUSY_SET (0x1 << 6 ) /* SET */
3379
3380/* I2CSSTA[NOACK] - Ack not generated by the slave */
3381#define I2CSSTA_NOACK_BBA (*(volatile unsigned long *) 0x42060594)
3382#define I2CSSTA_NOACK_MSK (0x1 << 5 )
3383#define I2CSSTA_NOACK (0x1 << 5 )
3384#define I2CSSTA_NOACK_CLR (0x0 << 5 ) /* CLR */
3385#define I2CSSTA_NOACK_SET (0x1 << 5 ) /* SET */
3386
3387/* I2CSSTA[RXOF] - Receive FIFO */
3388#define I2CSSTA_RXOF_BBA (*(volatile unsigned long *) 0x42060590)
3389#define I2CSSTA_RXOF_MSK (0x1 << 4 )
3390#define I2CSSTA_RXOF (0x1 << 4 )
3391#define I2CSSTA_RXOF_CLR (0x0 << 4 ) /* CLR */
3392#define I2CSSTA_RXOF_SET (0x1 << 4 ) /* SET */
3393
3394/* I2CSSTA[RXREQ] - Receive */
3395#define I2CSSTA_RXREQ_BBA (*(volatile unsigned long *) 0x4206058C)
3396#define I2CSSTA_RXREQ_MSK (0x1 << 3 )
3397#define I2CSSTA_RXREQ (0x1 << 3 )
3398#define I2CSSTA_RXREQ_CLR (0x0 << 3 ) /* CLR */
3399#define I2CSSTA_RXREQ_SET (0x1 << 3 ) /* SET */
3400
3401/* I2CSSTA[TXREQ] - Transmit */
3402#define I2CSSTA_TXREQ_BBA (*(volatile unsigned long *) 0x42060588)
3403#define I2CSSTA_TXREQ_MSK (0x1 << 2 )
3404#define I2CSSTA_TXREQ (0x1 << 2 )
3405#define I2CSSTA_TXREQ_CLR (0x0 << 2 ) /* CLR */
3406#define I2CSSTA_TXREQ_SET (0x1 << 2 ) /* SET */
3407
3408/* I2CSSTA[TXUR] - Transmit FIFO underflow */
3409#define I2CSSTA_TXUR_BBA (*(volatile unsigned long *) 0x42060584)
3410#define I2CSSTA_TXUR_MSK (0x1 << 1 )
3411#define I2CSSTA_TXUR (0x1 << 1 )
3412#define I2CSSTA_TXUR_CLR (0x0 << 1 ) /* CLR */
3413#define I2CSSTA_TXUR_SET (0x1 << 1 ) /* SET */
3414
3415/* I2CSSTA[TXFSEREQ] - Tx FIFO status or early request */
3416#define I2CSSTA_TXFSEREQ_BBA (*(volatile unsigned long *) 0x42060580)
3417#define I2CSSTA_TXFSEREQ_MSK (0x1 << 0 )
3418#define I2CSSTA_TXFSEREQ (0x1 << 0 )
3419#define I2CSSTA_TXFSEREQ_CLR (0x0 << 0 ) /* CLR */
3420#define I2CSSTA_TXFSEREQ_SET (0x1 << 0 ) /* SET */
3421
3422/* Reset Value for I2CSRX*/
3423#define I2CSRX_RVAL 0x0
3424
3425/* I2CSRX[VALUE] - Receive register */
3426#define I2CSRX_VALUE_MSK (0xFF << 0 )
3427
3428/* Reset Value for I2CSTX*/
3429#define I2CSTX_RVAL 0x0
3430
3431/* I2CSTX[VALUE] - Transmit register */
3432#define I2CSTX_VALUE_MSK (0xFF << 0 )
3433
3434/* Reset Value for I2CALT*/
3435#define I2CALT_RVAL 0x0
3436
3437/* I2CALT[VALUE] - Alt register */
3438#define I2CALT_VALUE_MSK (0xFF << 0 )
3439
3440/* Reset Value for I2CID0*/
3441#define I2CID0_RVAL 0x0
3442
3443/* I2CID0[VALUE] - Slave ID */
3444#define I2CID0_VALUE_MSK (0xFF << 0 )
3445
3446/* Reset Value for I2CID1*/
3447#define I2CID1_RVAL 0x0
3448
3449/* I2CID1[VALUE] - Slave ID */
3450#define I2CID1_VALUE_MSK (0xFF << 0 )
3451
3452/* Reset Value for I2CID2*/
3453#define I2CID2_RVAL 0x0
3454
3455/* I2CID2[VALUE] - Slave ID */
3456#define I2CID2_VALUE_MSK (0xFF << 0 )
3457
3458/* Reset Value for I2CID3*/
3459#define I2CID3_RVAL 0x0
3460
3461/* I2CID3[VALUE] - Slave ID */
3462#define I2CID3_VALUE_MSK (0xFF << 0 )
3463
3464/* Reset Value for I2CFSTA*/
3465#define I2CFSTA_RVAL 0x0
3466
3467/* I2CFSTA[MFLUSH] - Flush the master transmit FIFO */
3468#define I2CFSTA_MFLUSH_BBA (*(volatile unsigned long *) 0x420609A4)
3469#define I2CFSTA_MFLUSH_MSK (0x1 << 9 )
3470#define I2CFSTA_MFLUSH (0x1 << 9 )
3471#define I2CFSTA_MFLUSH_DIS (0x0 << 9 ) /* DIS */
3472#define I2CFSTA_MFLUSH_EN (0x1 << 9 ) /* EN */
3473
3474/* I2CFSTA[SFLUSH] - Flush the slave transmit FIFO */
3475#define I2CFSTA_SFLUSH_BBA (*(volatile unsigned long *) 0x420609A0)
3476#define I2CFSTA_SFLUSH_MSK (0x1 << 8 )
3477#define I2CFSTA_SFLUSH (0x1 << 8 )
3478#define I2CFSTA_SFLUSH_DIS (0x0 << 8 ) /* DIS */
3479#define I2CFSTA_SFLUSH_EN (0x1 << 8 ) /* EN */
3480
3481/* I2CFSTA[MRXFSTA] - Master receive FIFO Status */
3482#define I2CFSTA_MRXFSTA_MSK (0x3 << 6 )
3483#define I2CFSTA_MRXFSTA_EMPTY (0x0 << 6 ) /* EMPTY */
3484#define I2CFSTA_MRXFSTA_ONEBYTE (0x1 << 6 ) /* ONEBYTE */
3485#define I2CFSTA_MRXFSTA_TWOBYTES (0x2 << 6 ) /* TWOBYTES */
3486
3487/* I2CFSTA[MTXFSTA] - Master Transmit FIFO Status */
3488#define I2CFSTA_MTXFSTA_MSK (0x3 << 4 )
3489#define I2CFSTA_MTXFSTA_EMPTY (0x0 << 4 ) /* EMPTY */
3490#define I2CFSTA_MTXFSTA_ONEBYTE (0x1 << 4 ) /* ONEBYTE */
3491#define I2CFSTA_MTXFSTA_TWOBYTES (0x2 << 4 ) /* TWOBYTES */
3492
3493/* I2CFSTA[SRXFSTA] - Slave receive FIFO Status */
3494#define I2CFSTA_SRXFSTA_MSK (0x3 << 2 )
3495#define I2CFSTA_SRXFSTA_EMPTY (0x0 << 2 ) /* EMPTY */
3496#define I2CFSTA_SRXFSTA_ONEBYTE (0x1 << 2 ) /* ONEBYTE */
3497#define I2CFSTA_SRXFSTA_TWOBYTES (0x2 << 2 ) /* TWOBYTES */
3498
3499/* I2CFSTA[STXFSTA] - Slave Transmit FIFO Status */
3500#define I2CFSTA_STXFSTA_MSK (0x3 << 0 )
3501#define I2CFSTA_STXFSTA_EMPTY (0x0 << 0 ) /* EMPTY */
3502#define I2CFSTA_STXFSTA_ONEBYTE (0x1 << 0 ) /* ONEBYTE */
3503#define I2CFSTA_STXFSTA_TWOBYTES (0x2 << 0 ) /* TWOBYTES */
3504
3505/* I2CSHCON[RESET] - Reset START STOP detect circuit */
3506#define I2CSHCON_RESET_MSK (0x1 << 0 )
3507#define I2CSHCON_RESET (0x1 << 0 )
3508#define I2CSHCON_RESET_DIS (0x0 << 0 )
3509#define I2CSHCON_RESET_EN (0x1 << 0 )
3510
3511/* I2CASSCL[SSRTSTA] - stretch timeout for slave */
3512#define I2CASSCL_SSRTSTA_MSK (0x1 << 9 )
3513#define I2CASSCL_SSRTSTA (0x1 << 9 )
3514#define I2CASSCL_SSRTSTA_DIS (0x0 << 9 )
3515#define I2CASSCL_SSRTSTA_EN (0x1 << 9 )
3516
3517/* I2CASSCL[MSRTSTA] - stretch timeout for master */
3518#define I2CASSCL_MSRTSTA_MSK (0x1 << 8 )
3519#define I2CASSCL_MSRTSTA (0x1 << 8 )
3520#define I2CASSCL_MSRTSTA_DIS (0x0 << 8 )
3521#define I2CASSCL_MSRTSTA_EN (0x1 << 8 )
3522
3523/* I2CASSCL[SSTRCON] - automatic stretch mode for slave */
3524#define I2CASSCL_SSTRCON_MSK (0xF << 4 )
3525
3526/* I2CASSCL[MSTRCON] - automatic stretch mode for master */
3527#define I2CASSCL_MSTRCON_MSK (0xF << 0 )
3528
3529// ------------------------------------------------------------------------------------------------
3530// ----- SPI0 -----
3531// ------------------------------------------------------------------------------------------------
3532
3533
3534/**
3535 * @brief Serial Peripheral Interface (pADI_SPI0)
3536 */
3537
3538typedef struct { /*!< pADI_SPI0 Structure */
3539 __IO uint16_t SPISTA; /*!< Status Register */
3540 __I uint16_t RESERVED0;
3541 __IO uint8_t SPIRX; /*!< 8-bit Receive register. */
3542 __I uint8_t RESERVED1[3];
3543 __IO uint8_t SPITX; /*!< 8-bit Transmit register */
3544 __I uint8_t RESERVED2[3];
3545 __IO uint16_t SPIDIV; /*!< SPI Clock Divider Registers */
3546 __I uint16_t RESERVED3;
3547 __IO uint16_t SPICON; /*!< 16-bit configuration register */
3548 __I uint16_t RESERVED4;
3549 __IO uint16_t SPIDMA; /*!< DMA enable register */
3550 __I uint16_t RESERVED5;
3551 __IO uint16_t SPICNT; /*!< 8-bit received byte count register */
3552} ADI_SPI_TypeDef;
3553
3554#define SPI0STA (*(volatile unsigned short int *) 0x40004000)
3555#define SPI0RX (*(volatile unsigned char *) 0x40004004)
3556#define SPI0TX (*(volatile unsigned char *) 0x40004008)
3557#define SPI0DIV (*(volatile unsigned short int *) 0x4000400C)
3558#define SPI0CON (*(volatile unsigned short int *) 0x40004010)
3559#define SPI0DMA (*(volatile unsigned short int *) 0x40004014)
3560#define SPI0CNT (*(volatile unsigned short int *) 0x40004018)
3561
3562/* Reset Value for SPI0STA*/
3563#define SPI0STA_RVAL 0x0
3564
3565/* SPI0STA[CSRSG] - Detected a rising edge on CS, in CONT mode */
3566#define SPI0STA_CSRSG_BBA (*(volatile unsigned long *) 0x42080038)
3567#define SPI0STA_CSRSG_MSK (0x1 << 14 )
3568#define SPI0STA_CSRSG (0x1 << 14 )
3569#define SPI0STA_CSRSG_CLR (0x0 << 14 ) /* Cleared to 0 when the Status register is read. */
3570#define SPI0STA_CSRSG_SET (0x1 << 14 ) /* Set to 1 when there was a rising edge in CS line, when the device was in master mode, continuous transfer, High Frequency mode and CSIRQ_EN was asserted. */
3571
3572/* SPI0STA[CSFLG] - Detected a falling edge on CS, in CONT mode */
3573#define SPI0STA_CSFLG_BBA (*(volatile unsigned long *) 0x42080034)
3574#define SPI0STA_CSFLG_MSK (0x1 << 13 )
3575#define SPI0STA_CSFLG (0x1 << 13 )
3576#define SPI0STA_CSFLG_CLR (0x0 << 13 ) /* Cleared to 0 when the Status register is read. */
3577#define SPI0STA_CSFLG_SET (0x1 << 13 ) /* Set to 1 when there was a falling edge in CS line, when the device was in master mode, continuous transfer, High Frequency mode and CSIRQ_EN was asserted */
3578
3579/* SPI0STA[CSERR] - Detected an abrupt CS deassertion */
3580#define SPI0STA_CSERR_BBA (*(volatile unsigned long *) 0x42080030)
3581#define SPI0STA_CSERR_MSK (0x1 << 12 )
3582#define SPI0STA_CSERR (0x1 << 12 )
3583#define SPI0STA_CSERR_CLR (0x0 << 12 ) /* CLR */
3584#define SPI0STA_CSERR_SET (0x1 << 12 ) /* SET */
3585
3586/* SPI0STA[RXS] - Set when there are more bytes in the RX FIFO than the TIM bit says */
3587#define SPI0STA_RXS_BBA (*(volatile unsigned long *) 0x4208002C)
3588#define SPI0STA_RXS_MSK (0x1 << 11 )
3589#define SPI0STA_RXS (0x1 << 11 )
3590#define SPI0STA_RXS_CLR (0x0 << 11 ) /* CLR */
3591#define SPI0STA_RXS_SET (0x1 << 11 ) /* SET */
3592
3593/* SPI0STA[RXFSTA] - Receive FIFO Status */
3594#define SPI0STA_RXFSTA_MSK (0x7 << 8 )
3595#define SPI0STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY */
3596#define SPI0STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE */
3597#define SPI0STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES */
3598#define SPI0STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES */
3599#define SPI0STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES */
3600
3601/* SPI0STA[RXOF] - Receive FIFO overflow */
3602#define SPI0STA_RXOF_BBA (*(volatile unsigned long *) 0x4208001C)
3603#define SPI0STA_RXOF_MSK (0x1 << 7 )
3604#define SPI0STA_RXOF (0x1 << 7 )
3605#define SPI0STA_RXOF_CLR (0x0 << 7 ) /* CLR */
3606#define SPI0STA_RXOF_SET (0x1 << 7 ) /* SET */
3607
3608/* SPI0STA[RX] - Set when a receive interrupt occurs */
3609#define SPI0STA_RX_BBA (*(volatile unsigned long *) 0x42080018)
3610#define SPI0STA_RX_MSK (0x1 << 6 )
3611#define SPI0STA_RX (0x1 << 6 )
3612#define SPI0STA_RX_CLR (0x0 << 6 ) /* CLR */
3613#define SPI0STA_RX_SET (0x1 << 6 ) /* SET */
3614
3615/* SPI0STA[TX] - Set when a transmit interrupt occurs */
3616#define SPI0STA_TX_BBA (*(volatile unsigned long *) 0x42080014)
3617#define SPI0STA_TX_MSK (0x1 << 5 )
3618#define SPI0STA_TX (0x1 << 5 )
3619#define SPI0STA_TX_CLR (0x0 << 5 ) /* CLR */
3620#define SPI0STA_TX_SET (0x1 << 5 ) /* SET */
3621
3622/* SPI0STA[TXUR] - Transmit FIFO underflow */
3623#define SPI0STA_TXUR_BBA (*(volatile unsigned long *) 0x42080010)
3624#define SPI0STA_TXUR_MSK (0x1 << 4 )
3625#define SPI0STA_TXUR (0x1 << 4 )
3626#define SPI0STA_TXUR_CLR (0x0 << 4 ) /* CLR */
3627#define SPI0STA_TXUR_SET (0x1 << 4 ) /* SET */
3628
3629/* SPI0STA[TXFSTA] - transmit FIFO Status */
3630#define SPI0STA_TXFSTA_MSK (0x7 << 1 )
3631#define SPI0STA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY */
3632#define SPI0STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE */
3633#define SPI0STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES */
3634#define SPI0STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES */
3635#define SPI0STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES */
3636
3637/* SPI0STA[IRQ] - Interrupt status bit */
3638#define SPI0STA_IRQ_BBA (*(volatile unsigned long *) 0x42080000)
3639#define SPI0STA_IRQ_MSK (0x1 << 0 )
3640#define SPI0STA_IRQ (0x1 << 0 )
3641#define SPI0STA_IRQ_CLR (0x0 << 0 ) /* CLR */
3642#define SPI0STA_IRQ_SET (0x1 << 0 ) /* SET */
3643
3644/* Reset Value for SPI0RX*/
3645#define SPI0RX_RVAL 0x0
3646
3647/* SPI0RX[VALUE] - Received data */
3648#define SPI0RX_VALUE_MSK (0xFF << 0 )
3649
3650/* Reset Value for SPI0TX*/
3651#define SPI0TX_RVAL 0x0
3652
3653/* SPI0TX[VALUE] - Data to transmit */
3654#define SPI0TX_VALUE_MSK (0xFF << 0 )
3655
3656/* Reset Value for SPI0DIV*/
3657#define SPI0DIV_RVAL 0x0
3658
3659/* SPI0DIV[CSIRQ_EN] - Enable interrupt on every CS edge in CONT mode */
3660#define SPI0DIV_CSIRQ_EN_BBA (*(volatile unsigned long *) 0x420801A0)
3661#define SPI0DIV_CSIRQ_EN_MSK (0x1 << 8 )
3662#define SPI0DIV_CSIRQ_EN (0x1 << 8 )
3663#define SPI0DIV_CSIRQ_EN_DIS (0x0 << 8 )
3664#define SPI0DIV_CSIRQ_EN_EN (0x1 << 8 )
3665
3666/* SPI0DIV[BCRST] - Bit counter reset */
3667#define SPI0DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208019C)
3668#define SPI0DIV_BCRST_MSK (0x1 << 7 )
3669#define SPI0DIV_BCRST (0x1 << 7 )
3670#define SPI0DIV_BCRST_DIS (0x0 << 7 ) /* DIS */
3671#define SPI0DIV_BCRST_EN (0x1 << 7 ) /* EN */
3672
3673/* SPI0DIV[HFM] - High Frequency Mode */
3674#define SPI0DIV_HFM_BBA (*(volatile unsigned long *) 0x42080198)
3675#define SPI0DIV_HFM_MSK (0x1 << 6 )
3676#define SPI0DIV_HFM (0x1 << 6 )
3677#define SPI0DIV_HFM_DIS (0x0 << 6 )
3678#define SPI0DIV_HFM_EN (0x1 << 6 )
3679
3680/* SPI0DIV[DIV] - Factor used to divide UCLK to generate the serial clock */
3681#define SPI0DIV_DIV_MSK (0x3F << 0 )
3682
3683/* Reset Value for SPI0CON*/
3684#define SPI0CON_RVAL 0x0
3685
3686/* SPI0CON[MOD] - SPI IRQ Mode bits */
3687#define SPI0CON_MOD_MSK (0x3 << 14 )
3688#define SPI0CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1 */
3689#define SPI0CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2 */
3690#define SPI0CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3 */
3691#define SPI0CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4 */
3692
3693/* SPI0CON[TFLUSH] - TX FIFO Flush Enable bit */
3694#define SPI0CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42080234)
3695#define SPI0CON_TFLUSH_MSK (0x1 << 13 )
3696#define SPI0CON_TFLUSH (0x1 << 13 )
3697#define SPI0CON_TFLUSH_DIS (0x0 << 13 ) /* DIS */
3698#define SPI0CON_TFLUSH_EN (0x1 << 13 ) /* EN */
3699
3700/* SPI0CON[RFLUSH] - RX FIFO Flush Enable bit */
3701#define SPI0CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42080230)
3702#define SPI0CON_RFLUSH_MSK (0x1 << 12 )
3703#define SPI0CON_RFLUSH (0x1 << 12 )
3704#define SPI0CON_RFLUSH_DIS (0x0 << 12 ) /* DIS */
3705#define SPI0CON_RFLUSH_EN (0x1 << 12 ) /* EN */
3706
3707/* SPI0CON[CON] - Continuous transfer enable */
3708#define SPI0CON_CON_BBA (*(volatile unsigned long *) 0x4208022C)
3709#define SPI0CON_CON_MSK (0x1 << 11 )
3710#define SPI0CON_CON (0x1 << 11 )
3711#define SPI0CON_CON_DIS (0x0 << 11 ) /* DIS */
3712#define SPI0CON_CON_EN (0x1 << 11 ) /* EN */
3713
3714/* SPI0CON[LOOPBACK] - Loopback enable bit */
3715#define SPI0CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42080228)
3716#define SPI0CON_LOOPBACK_MSK (0x1 << 10 )
3717#define SPI0CON_LOOPBACK (0x1 << 10 )
3718#define SPI0CON_LOOPBACK_DIS (0x0 << 10 ) /* DIS */
3719#define SPI0CON_LOOPBACK_EN (0x1 << 10 ) /* EN */
3720
3721/* SPI0CON[SOEN] - Slave MISO output enable bit */
3722#define SPI0CON_SOEN_BBA (*(volatile unsigned long *) 0x42080224)
3723#define SPI0CON_SOEN_MSK (0x1 << 9 )
3724#define SPI0CON_SOEN (0x1 << 9 )
3725#define SPI0CON_SOEN_DIS (0x0 << 9 ) /* DIS */
3726#define SPI0CON_SOEN_EN (0x1 << 9 ) /* EN */
3727
3728/* SPI0CON[RXOF] - RX Oveflow Overwrite enable */
3729#define SPI0CON_RXOF_BBA (*(volatile unsigned long *) 0x42080220)
3730#define SPI0CON_RXOF_MSK (0x1 << 8 )
3731#define SPI0CON_RXOF (0x1 << 8 )
3732#define SPI0CON_RXOF_DIS (0x0 << 8 ) /* DIS */
3733#define SPI0CON_RXOF_EN (0x1 << 8 ) /* EN */
3734
3735/* SPI0CON[ZEN] - Transmit zeros when empty */
3736#define SPI0CON_ZEN_BBA (*(volatile unsigned long *) 0x4208021C)
3737#define SPI0CON_ZEN_MSK (0x1 << 7 )
3738#define SPI0CON_ZEN (0x1 << 7 )
3739#define SPI0CON_ZEN_DIS (0x0 << 7 ) /* DIS */
3740#define SPI0CON_ZEN_EN (0x1 << 7 ) /* EN */
3741
3742/* SPI0CON[TIM] - Transfer and interrupt mode */
3743#define SPI0CON_TIM_BBA (*(volatile unsigned long *) 0x42080218)
3744#define SPI0CON_TIM_MSK (0x1 << 6 )
3745#define SPI0CON_TIM (0x1 << 6 )
3746#define SPI0CON_TIM_RXRD (0x0 << 6 ) /* RXRD - Cleared by user to initiate transfer with a read of the SPIRX register */
3747#define SPI0CON_TIM_TXWR (0x1 << 6 ) /* TXWR - Set by user to initiate transfer with a write to the SPITX register. */
3748
3749/* SPI0CON[LSB] - LSB First Transfer enable */
3750#define SPI0CON_LSB_BBA (*(volatile unsigned long *) 0x42080214)
3751#define SPI0CON_LSB_MSK (0x1 << 5 )
3752#define SPI0CON_LSB (0x1 << 5 )
3753#define SPI0CON_LSB_DIS (0x0 << 5 ) /* DIS */
3754#define SPI0CON_LSB_EN (0x1 << 5 ) /* EN */
3755
3756/* SPI0CON[WOM] - Wired OR enable */
3757#define SPI0CON_WOM_BBA (*(volatile unsigned long *) 0x42080210)
3758#define SPI0CON_WOM_MSK (0x1 << 4 )
3759#define SPI0CON_WOM (0x1 << 4 )
3760#define SPI0CON_WOM_DIS (0x0 << 4 ) /* DIS */
3761#define SPI0CON_WOM_EN (0x1 << 4 ) /* EN */
3762
3763/* SPI0CON[CPOL] - Clock polarity mode */
3764#define SPI0CON_CPOL_BBA (*(volatile unsigned long *) 0x4208020C)
3765#define SPI0CON_CPOL_MSK (0x1 << 3 )
3766#define SPI0CON_CPOL (0x1 << 3 )
3767#define SPI0CON_CPOL_LOW (0x0 << 3 ) /* LOW */
3768#define SPI0CON_CPOL_HIGH (0x1 << 3 ) /* HIGH */
3769
3770/* SPI0CON[CPHA] - Clock phase mode */
3771#define SPI0CON_CPHA_BBA (*(volatile unsigned long *) 0x42080208)
3772#define SPI0CON_CPHA_MSK (0x1 << 2 )
3773#define SPI0CON_CPHA (0x1 << 2 )
3774#define SPI0CON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING */
3775#define SPI0CON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING */
3776
3777/* SPI0CON[MASEN] - Master enable */
3778#define SPI0CON_MASEN_BBA (*(volatile unsigned long *) 0x42080204)
3779#define SPI0CON_MASEN_MSK (0x1 << 1 )
3780#define SPI0CON_MASEN (0x1 << 1 )
3781#define SPI0CON_MASEN_DIS (0x0 << 1 ) /* DIS */
3782#define SPI0CON_MASEN_EN (0x1 << 1 ) /* EN */
3783
3784/* SPI0CON[ENABLE] - SPI Enable bit */
3785#define SPI0CON_ENABLE_BBA (*(volatile unsigned long *) 0x42080200)
3786#define SPI0CON_ENABLE_MSK (0x1 << 0 )
3787#define SPI0CON_ENABLE (0x1 << 0 )
3788#define SPI0CON_ENABLE_DIS (0x0 << 0 ) /* DIS */
3789#define SPI0CON_ENABLE_EN (0x1 << 0 ) /* EN */
3790
3791/* Reset Value for SPI0DMA*/
3792#define SPI0DMA_RVAL 0x0
3793
3794/* SPI0DMA[IENRXDMA] - Enable receive DMA request */
3795#define SPI0DMA_IENRXDMA_BBA (*(volatile unsigned long *) 0x42080288)
3796#define SPI0DMA_IENRXDMA_MSK (0x1 << 2 )
3797#define SPI0DMA_IENRXDMA (0x1 << 2 )
3798#define SPI0DMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS */
3799#define SPI0DMA_IENRXDMA_EN (0x1 << 2 ) /* EN */
3800
3801/* SPI0DMA[IENTXDMA] - Enable transmit DMA request */
3802#define SPI0DMA_IENTXDMA_BBA (*(volatile unsigned long *) 0x42080284)
3803#define SPI0DMA_IENTXDMA_MSK (0x1 << 1 )
3804#define SPI0DMA_IENTXDMA (0x1 << 1 )
3805#define SPI0DMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS */
3806#define SPI0DMA_IENTXDMA_EN (0x1 << 1 ) /* EN */
3807
3808/* SPI0DMA[ENABLE] - Enable DMA for data transfer */
3809#define SPI0DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42080280)
3810#define SPI0DMA_ENABLE_MSK (0x1 << 0 )
3811#define SPI0DMA_ENABLE (0x1 << 0 )
3812#define SPI0DMA_ENABLE_DIS (0x0 << 0 ) /* DIS */
3813#define SPI0DMA_ENABLE_EN (0x1 << 0 ) /* EN */
3814
3815/* Reset Value for SPI0CNT*/
3816#define SPI0CNT_RVAL 0x0
3817
3818/* SPI0CNT[VALUE] - Count */
3819#define SPI0CNT_VALUE_MSK (0xFF << 0 )
3820
3821#define SPI1STA (*(volatile unsigned short int *) 0x40004400)
3822#define SPI1RX (*(volatile unsigned char *) 0x40004404)
3823#define SPI1TX (*(volatile unsigned char *) 0x40004408)
3824#define SPI1DIV (*(volatile unsigned short int *) 0x4000440C)
3825#define SPI1CON (*(volatile unsigned short int *) 0x40004410)
3826#define SPI1DMA (*(volatile unsigned short int *) 0x40004414)
3827#define SPI1CNT (*(volatile unsigned short int *) 0x40004418)
3828
3829/* Reset Value for SPI1STA*/
3830#define SPI1STA_RVAL 0x0
3831
3832/* SPI1STA[CSRSG] - Detected a rising edge on CS, in CONT mode */
3833#define SPI1STA_CSRSG_BBA (*(volatile unsigned long *) 0x42000038)
3834#define SPI1STA_CSRSG_MSK (0x1 << 14 )
3835#define SPI1STA_CSRSG (0x1 << 14 )
3836#define SPI1STA_CSRSG_CLR (0x0 << 14 ) /* Cleared to 0 when the Status register is read */
3837#define SPI1STA_CSRSG_SET (0x1 << 14 ) /* Set to 1 when there was a rising edge in CS line, when the device was in master mode, continuous transfer, High Frequency mode and CSIRQ_EN was asserted. */
3838
3839/* SPI1STA[CSFLG] - Detected a falling edge on CS, in CONT mode */
3840#define SPI1STA_CSFLG_BBA (*(volatile unsigned long *) 0x42000034)
3841#define SPI1STA_CSFLG_MSK (0x1 << 13 )
3842#define SPI1STA_CSFLG (0x1 << 13 )
3843#define SPI1STA_CSFLG_CLR (0x0 << 13 ) /* Cleared to 0 when the Status register is read. */
3844#define SPI1STA_CSFLG_SET (0x1 << 13 ) /* Set to 1 when there was a falling edge in CS line, when the device was in master mode, continuous transfer, High Frequency mode and CSIRQ_EN was asserted. */
3845
3846/* SPI1STA[CSERR] - Detected an abrupt CS deassertion */
3847#define SPI1STA_CSERR_BBA (*(volatile unsigned long *) 0x42088030)
3848#define SPI1STA_CSERR_MSK (0x1 << 12 )
3849#define SPI1STA_CSERR (0x1 << 12 )
3850#define SPI1STA_CSERR_CLR (0x0 << 12 ) /* CLR */
3851#define SPI1STA_CSERR_SET (0x1 << 12 ) /* SET */
3852
3853/* SPI1STA[RXS] - Set when there are more bytes in the RX FIFO than the TIM bit says */
3854#define SPI1STA_RXS_BBA (*(volatile unsigned long *) 0x4208802C)
3855#define SPI1STA_RXS_MSK (0x1 << 11 )
3856#define SPI1STA_RXS (0x1 << 11 )
3857#define SPI1STA_RXS_CLR (0x0 << 11 ) /* CLR */
3858#define SPI1STA_RXS_SET (0x1 << 11 ) /* SET */
3859
3860/* SPI1STA[RXFSTA] - Receive FIFO Status */
3861#define SPI1STA_RXFSTA_MSK (0x7 << 8 )
3862#define SPI1STA_RXFSTA_EMPTY (0x0 << 8 ) /* EMPTY */
3863#define SPI1STA_RXFSTA_ONEBYTE (0x1 << 8 ) /* ONEBYTE */
3864#define SPI1STA_RXFSTA_TWOBYTES (0x2 << 8 ) /* TWOBYTES */
3865#define SPI1STA_RXFSTA_THREEBYTES (0x3 << 8 ) /* THREEBYTES */
3866#define SPI1STA_RXFSTA_FOURBYTES (0x4 << 8 ) /* FOURBYTES */
3867
3868/* SPI1STA[RXOF] - Receive FIFO overflow */
3869#define SPI1STA_RXOF_BBA (*(volatile unsigned long *) 0x4208801C)
3870#define SPI1STA_RXOF_MSK (0x1 << 7 )
3871#define SPI1STA_RXOF (0x1 << 7 )
3872#define SPI1STA_RXOF_CLR (0x0 << 7 ) /* CLR */
3873#define SPI1STA_RXOF_SET (0x1 << 7 ) /* SET */
3874
3875/* SPI1STA[RX] - Set when a receive interrupt occurs */
3876#define SPI1STA_RX_BBA (*(volatile unsigned long *) 0x42088018)
3877#define SPI1STA_RX_MSK (0x1 << 6 )
3878#define SPI1STA_RX (0x1 << 6 )
3879#define SPI1STA_RX_CLR (0x0 << 6 ) /* CLR */
3880#define SPI1STA_RX_SET (0x1 << 6 ) /* SET */
3881
3882/* SPI1STA[TX] - Set when a transmit interrupt occurs */
3883#define SPI1STA_TX_BBA (*(volatile unsigned long *) 0x42088014)
3884#define SPI1STA_TX_MSK (0x1 << 5 )
3885#define SPI1STA_TX (0x1 << 5 )
3886#define SPI1STA_TX_CLR (0x0 << 5 ) /* CLR */
3887#define SPI1STA_TX_SET (0x1 << 5 ) /* SET */
3888
3889/* SPI1STA[TXUR] - Transmit FIFO underflow */
3890#define SPI1STA_TXUR_BBA (*(volatile unsigned long *) 0x42088010)
3891#define SPI1STA_TXUR_MSK (0x1 << 4 )
3892#define SPI1STA_TXUR (0x1 << 4 )
3893#define SPI1STA_TXUR_CLR (0x0 << 4 ) /* CLR */
3894#define SPI1STA_TXUR_SET (0x1 << 4 ) /* SET */
3895
3896/* SPI1STA[TXFSTA] - transmit FIFO Status */
3897#define SPI1STA_TXFSTA_MSK (0x7 << 1 )
3898#define SPI1STA_TXFSTA_EMPTY (0x0 << 1 ) /* EMPTY */
3899#define SPI1STA_TXFSTA_ONEBYTE (0x1 << 1 ) /* ONEBYTE */
3900#define SPI1STA_TXFSTA_TWOBYTES (0x2 << 1 ) /* TWOBYTES */
3901#define SPI1STA_TXFSTA_THREEBYTES (0x3 << 1 ) /* THREEBYTES */
3902#define SPI1STA_TXFSTA_FOURBYTES (0x4 << 1 ) /* FOURBYTES */
3903
3904/* SPI1STA[IRQ] - Interrupt status bit */
3905#define SPI1STA_IRQ_BBA (*(volatile unsigned long *) 0x42088000)
3906#define SPI1STA_IRQ_MSK (0x1 << 0 )
3907#define SPI1STA_IRQ (0x1 << 0 )
3908#define SPI1STA_IRQ_CLR (0x0 << 0 ) /* CLR */
3909#define SPI1STA_IRQ_SET (0x1 << 0 ) /* SET */
3910
3911/* Reset Value for SPI1RX*/
3912#define SPI1RX_RVAL 0x0
3913
3914/* SPI1RX[VALUE] - Received data */
3915#define SPI1RX_VALUE_MSK (0xFF << 0 )
3916
3917/* Reset Value for SPI1TX*/
3918#define SPI1TX_RVAL 0x0
3919
3920/* SPI1TX[VALUE] - Data to transmit */
3921#define SPI1TX_VALUE_MSK (0xFF << 0 )
3922
3923/* Reset Value for SPI1DIV*/
3924#define SPI1DIV_RVAL 0x0
3925
3926/* SPI1DIV[CSIRQ_EN] - Enable interrupt on every CS edge in CONT mode */
3927#define SPI1DIV_CSIRQ_EN_BBA (*(volatile unsigned long *) 0x420001A0)
3928#define SPI1DIV_CSIRQ_EN_MSK (0x1 << 8 )
3929#define SPI1DIV_CSIRQ_EN (0x1 << 8 )
3930#define SPI1DIV_CSIRQ_EN_DIS (0x0 << 8 )
3931#define SPI1DIV_CSIRQ_EN_EN (0x1 << 8 )
3932
3933/* SPI1DIV[BCRST] - Bit counter reset */
3934#define SPI1DIV_BCRST_BBA (*(volatile unsigned long *) 0x4208819C)
3935#define SPI1DIV_BCRST_MSK (0x1 << 7 )
3936#define SPI1DIV_BCRST (0x1 << 7 )
3937#define SPI1DIV_BCRST_DIS (0x0 << 7 ) /* DIS */
3938#define SPI1DIV_BCRST_EN (0x1 << 7 ) /* EN */
3939
3940/* SPI1DIV[HFM] - High Frequency Mode */
3941#define SPI1DIV_HFM_BBA (*(volatile unsigned long *) 0x42000198)
3942#define SPI1DIV_HFM_MSK (0x1 << 6 )
3943#define SPI1DIV_HFM (0x1 << 6 )
3944#define SPI1DIV_HFM_DIS (0x0 << 6 )
3945#define SPI1DIV_HFM_EN (0x1 << 6 )
3946
3947/* SPI1DIV[DIV] - Factor used to divide UCLK to generate the serial clock */
3948#define SPI1DIV_DIV_MSK (0x3F << 0 )
3949
3950/* Reset Value for SPI1CON*/
3951#define SPI1CON_RVAL 0x0
3952
3953/* SPI1CON[MOD] - SPI IRQ Mode bits */
3954#define SPI1CON_MOD_MSK (0x3 << 14 )
3955#define SPI1CON_MOD_TX1RX1 (0x0 << 14 ) /* TX1RX1 */
3956#define SPI1CON_MOD_TX2RX2 (0x1 << 14 ) /* TX2RX2 */
3957#define SPI1CON_MOD_TX3RX3 (0x2 << 14 ) /* TX3RX3 */
3958#define SPI1CON_MOD_TX4RX4 (0x3 << 14 ) /* TX4RX4 */
3959
3960/* SPI1CON[TFLUSH] - TX FIFO Flush Enable bit */
3961#define SPI1CON_TFLUSH_BBA (*(volatile unsigned long *) 0x42088234)
3962#define SPI1CON_TFLUSH_MSK (0x1 << 13 )
3963#define SPI1CON_TFLUSH (0x1 << 13 )
3964#define SPI1CON_TFLUSH_DIS (0x0 << 13 ) /* DIS */
3965#define SPI1CON_TFLUSH_EN (0x1 << 13 ) /* EN */
3966
3967/* SPI1CON[RFLUSH] - RX FIFO Flush Enable bit */
3968#define SPI1CON_RFLUSH_BBA (*(volatile unsigned long *) 0x42088230)
3969#define SPI1CON_RFLUSH_MSK (0x1 << 12 )
3970#define SPI1CON_RFLUSH (0x1 << 12 )
3971#define SPI1CON_RFLUSH_DIS (0x0 << 12 ) /* DIS */
3972#define SPI1CON_RFLUSH_EN (0x1 << 12 ) /* EN */
3973
3974/* SPI1CON[CON] - Continuous transfer enable */
3975#define SPI1CON_CON_BBA (*(volatile unsigned long *) 0x4208822C)
3976#define SPI1CON_CON_MSK (0x1 << 11 )
3977#define SPI1CON_CON (0x1 << 11 )
3978#define SPI1CON_CON_DIS (0x0 << 11 ) /* DIS */
3979#define SPI1CON_CON_EN (0x1 << 11 ) /* EN */
3980
3981/* SPI1CON[LOOPBACK] - Loopback enable bit */
3982#define SPI1CON_LOOPBACK_BBA (*(volatile unsigned long *) 0x42088228)
3983#define SPI1CON_LOOPBACK_MSK (0x1 << 10 )
3984#define SPI1CON_LOOPBACK (0x1 << 10 )
3985#define SPI1CON_LOOPBACK_DIS (0x0 << 10 ) /* DIS */
3986#define SPI1CON_LOOPBACK_EN (0x1 << 10 ) /* EN */
3987
3988/* SPI1CON[SOEN] - Slave MISO output enable bit */
3989#define SPI1CON_SOEN_BBA (*(volatile unsigned long *) 0x42088224)
3990#define SPI1CON_SOEN_MSK (0x1 << 9 )
3991#define SPI1CON_SOEN (0x1 << 9 )
3992#define SPI1CON_SOEN_DIS (0x0 << 9 ) /* DIS */
3993#define SPI1CON_SOEN_EN (0x1 << 9 ) /* EN */
3994
3995/* SPI1CON[RXOF] - RX Oveflow Overwrite enable */
3996#define SPI1CON_RXOF_BBA (*(volatile unsigned long *) 0x42088220)
3997#define SPI1CON_RXOF_MSK (0x1 << 8 )
3998#define SPI1CON_RXOF (0x1 << 8 )
3999#define SPI1CON_RXOF_DIS (0x0 << 8 ) /* DIS */
4000#define SPI1CON_RXOF_EN (0x1 << 8 ) /* EN */
4001
4002/* SPI1CON[ZEN] - Transmit zeros when empty */
4003#define SPI1CON_ZEN_BBA (*(volatile unsigned long *) 0x4208821C)
4004#define SPI1CON_ZEN_MSK (0x1 << 7 )
4005#define SPI1CON_ZEN (0x1 << 7 )
4006#define SPI1CON_ZEN_DIS (0x0 << 7 ) /* DIS */
4007#define SPI1CON_ZEN_EN (0x1 << 7 ) /* EN */
4008
4009/* SPI1CON[TIM] - Transfer and interrupt mode */
4010#define SPI1CON_TIM_BBA (*(volatile unsigned long *) 0x42088218)
4011#define SPI1CON_TIM_MSK (0x1 << 6 )
4012#define SPI1CON_TIM (0x1 << 6 )
4013#define SPI1CON_TIM_RXRD (0x0 << 6 ) /* RXRD - Cleared by user to initiate transfer with a read of the SPIRX register */
4014#define SPI1CON_TIM_TXWR (0x1 << 6 ) /* TXWR - Set by user to initiate transfer with a write to the SPITX register. */
4015
4016/* SPI1CON[LSB] - LSB First Transfer enable */
4017#define SPI1CON_LSB_BBA (*(volatile unsigned long *) 0x42088214)
4018#define SPI1CON_LSB_MSK (0x1 << 5 )
4019#define SPI1CON_LSB (0x1 << 5 )
4020#define SPI1CON_LSB_DIS (0x0 << 5 ) /* DIS */
4021#define SPI1CON_LSB_EN (0x1 << 5 ) /* EN */
4022
4023/* SPI1CON[WOM] - Wired OR enable */
4024#define SPI1CON_WOM_BBA (*(volatile unsigned long *) 0x42088210)
4025#define SPI1CON_WOM_MSK (0x1 << 4 )
4026#define SPI1CON_WOM (0x1 << 4 )
4027#define SPI1CON_WOM_DIS (0x0 << 4 ) /* DIS */
4028#define SPI1CON_WOM_EN (0x1 << 4 ) /* EN */
4029
4030/* SPI1CON[CPOL] - Clock polarity mode */
4031#define SPI1CON_CPOL_BBA (*(volatile unsigned long *) 0x4208820C)
4032#define SPI1CON_CPOL_MSK (0x1 << 3 )
4033#define SPI1CON_CPOL (0x1 << 3 )
4034#define SPI1CON_CPOL_LOW (0x0 << 3 ) /* LOW */
4035#define SPI1CON_CPOL_HIGH (0x1 << 3 ) /* HIGH */
4036
4037/* SPI1CON[CPHA] - Clock phase mode */
4038#define SPI1CON_CPHA_BBA (*(volatile unsigned long *) 0x42088208)
4039#define SPI1CON_CPHA_MSK (0x1 << 2 )
4040#define SPI1CON_CPHA (0x1 << 2 )
4041#define SPI1CON_CPHA_SAMPLELEADING (0x0 << 2 ) /* SAMPLELEADING */
4042#define SPI1CON_CPHA_SAMPLETRAILING (0x1 << 2 ) /* SAMPLETRAILING */
4043
4044/* SPI1CON[MASEN] - Master enable */
4045#define SPI1CON_MASEN_BBA (*(volatile unsigned long *) 0x42088204)
4046#define SPI1CON_MASEN_MSK (0x1 << 1 )
4047#define SPI1CON_MASEN (0x1 << 1 )
4048#define SPI1CON_MASEN_DIS (0x0 << 1 ) /* DIS */
4049#define SPI1CON_MASEN_EN (0x1 << 1 ) /* EN */
4050
4051/* SPI1CON[ENABLE] - SPI Enable bit */
4052#define SPI1CON_ENABLE_BBA (*(volatile unsigned long *) 0x42088200)
4053#define SPI1CON_ENABLE_MSK (0x1 << 0 )
4054#define SPI1CON_ENABLE (0x1 << 0 )
4055#define SPI1CON_ENABLE_DIS (0x0 << 0 ) /* DIS */
4056#define SPI1CON_ENABLE_EN (0x1 << 0 ) /* EN */
4057
4058/* Reset Value for SPI1DMA*/
4059#define SPI1DMA_RVAL 0x0
4060
4061/* SPI1DMA[IENRXDMA] - Enable receive DMA request */
4062#define SPI1DMA_IENRXDMA_BBA (*(volatile unsigned long *) 0x42088288)
4063#define SPI1DMA_IENRXDMA_MSK (0x1 << 2 )
4064#define SPI1DMA_IENRXDMA (0x1 << 2 )
4065#define SPI1DMA_IENRXDMA_DIS (0x0 << 2 ) /* DIS */
4066#define SPI1DMA_IENRXDMA_EN (0x1 << 2 ) /* EN */
4067
4068/* SPI1DMA[IENTXDMA] - Enable transmit DMA request */
4069#define SPI1DMA_IENTXDMA_BBA (*(volatile unsigned long *) 0x42088284)
4070#define SPI1DMA_IENTXDMA_MSK (0x1 << 1 )
4071#define SPI1DMA_IENTXDMA (0x1 << 1 )
4072#define SPI1DMA_IENTXDMA_DIS (0x0 << 1 ) /* DIS */
4073#define SPI1DMA_IENTXDMA_EN (0x1 << 1 ) /* EN */
4074
4075/* SPI1DMA[ENABLE] - Enable DMA for data transfer */
4076#define SPI1DMA_ENABLE_BBA (*(volatile unsigned long *) 0x42088280)
4077#define SPI1DMA_ENABLE_MSK (0x1 << 0 )
4078#define SPI1DMA_ENABLE (0x1 << 0 )
4079#define SPI1DMA_ENABLE_DIS (0x0 << 0 ) /* DIS */
4080#define SPI1DMA_ENABLE_EN (0x1 << 0 ) /* EN */
4081
4082/* Reset Value for SPI1CNT*/
4083#define SPI1CNT_RVAL 0x0
4084
4085/* SPI1CNT[VALUE] - Count */
4086#define SPI1CNT_VALUE_MSK (0xFF << 0 )
4087// ------------------------------------------------------------------------------------------------
4088// ----- UART -----
4089// ------------------------------------------------------------------------------------------------
4090
4091
4092/**
4093 * @brief UART (pADI_UART)
4094 */
4095
4096#if (__NO_MMR_STRUCTS__==0)
4097typedef struct { /*!< pADI_UART Structure */
4098
4099 union {
4100 __IO uint8_t COMTX; /*!< Transmit Holding register */
4101 __IO uint8_t COMRX; /*!< Receive Buffer register */
4102 } ;
4103 __I uint8_t RESERVED0[3];
4104 __IO uint8_t COMIEN; /*!< Interrupt Enable register */
4105 __I uint8_t RESERVED1[3];
4106 __IO uint8_t COMIIR; /*!< Interrupt Identification register */
4107 __I uint8_t RESERVED2[3];
4108 __IO uint8_t COMLCR; /*!< Line Control register */
4109 __I uint8_t RESERVED3[3];
4110 __IO uint8_t COMMCR; /*!< Module Control register */
4111 __I uint8_t RESERVED4[3];
4112 __IO uint8_t COMLSR; /*!< Line Status register */
4113 __I uint8_t RESERVED5[3];
4114 __IO uint8_t COMMSR; /*!< Modem Status register */
4115 __I uint8_t RESERVED6[11];
4116 __IO uint16_t COMFBR; /*!< Fractional baud rate divider register. */
4117 __I uint16_t RESERVED7;
4118 __IO uint16_t COMDIV; /*!< Baud rate Divisor register */
4119 __I uint16_t RESERVED8[3];
4120 __IO uint8_t COMCON; /*!< UART control register */
4121} ADI_UART_TypeDef;
4122#else // (__NO_MMR_STRUCTS__==0)
4123#define COM0TX (*(volatile unsigned char *) 0x40005000)
4124#define COM0RX (*(volatile unsigned char *) 0x40005000)
4125#define COM0IEN (*(volatile unsigned char *) 0x40005004)
4126#define COM0IIR (*(volatile unsigned char *) 0x40005008)
4127#define COM0LCR (*(volatile unsigned char *) 0x4000500C)
4128#define COM0MCR (*(volatile unsigned char *) 0x40005010)
4129#define COM0LSR (*(volatile unsigned char *) 0x40005014)
4130#define COM0MSR (*(volatile unsigned char *) 0x40005018)
4131#define COM0FBR (*(volatile unsigned short int *) 0x40005024)
4132#define COM0DIV (*(volatile unsigned short int *) 0x40005028)
4133#define COM0CON (*(volatile unsigned char *) 0x40005030)
4134#define COM1TX (*(volatile unsigned char *) 0x40005400)
4135#define COM1RX (*(volatile unsigned char *) 0x40005400)
4136#define COM1IEN (*(volatile unsigned char *) 0x40005404)
4137#define COM1IIR (*(volatile unsigned char *) 0x40005408)
4138#define COM1LCR (*(volatile unsigned char *) 0x4000540C)
4139#define COM1MCR (*(volatile unsigned char *) 0x40005410)
4140#define COM1LSR (*(volatile unsigned char *) 0x40005414)
4141#define COM1MSR (*(volatile unsigned char *) 0x40005418)
4142#define COM1FBR (*(volatile unsigned short int *) 0x40005424)
4143#define COM1DIV (*(volatile unsigned short int *) 0x40005428)
4144#define COM1CON (*(volatile unsigned char *) 0x40005430)
4145#define COM2TX (*(volatile unsigned char *) 0x40005800)
4146#define COM2RX (*(volatile unsigned char *) 0x40005800)
4147#define COM2IEN (*(volatile unsigned char *) 0x40005804)
4148#define COM2IIR (*(volatile unsigned char *) 0x40005808)
4149#define COM2LCR (*(volatile unsigned char *) 0x4000580C)
4150#define COM2MCR (*(volatile unsigned char *) 0x40005810)
4151#define COM2LSR (*(volatile unsigned char *) 0x40005814)
4152#define COM2MSR (*(volatile unsigned char *) 0x40005818)
4153#define COM2FBR (*(volatile unsigned short int *) 0x40005824)
4154#define COM2DIV (*(volatile unsigned short int *) 0x40005828)
4155#define COM2CON (*(volatile unsigned char *) 0x40005830)
4156
4157#endif // (__NO_MMR_STRUCTS__==0)
4158
4159/* Reset Value for COMTX*/
4160#define COMTX_RVAL 0x0
4161
4162/* COMTX[VALUE] - Value */
4163#define COMTX_VALUE_MSK (0xFF << 0 )
4164
4165/* Reset Value for COMRX*/
4166#define COMRX_RVAL 0x0
4167
4168/* COMRX[VALUE] - Value */
4169#define COMRX_VALUE_MSK (0xFF << 0 )
4170
4171/* Reset Value for COMIEN*/
4172#define COMIEN_RVAL 0x0
4173
4174/* COMIEN[EDMAR] - Enable DMA requests in transmit mode */
4175#define COMIEN_EDMAR_BBA (*(volatile unsigned long *) 0x420A0094)
4176#define COMIEN_EDMAR_MSK (0x1 << 5 )
4177#define COMIEN_EDMAR (0x1 << 5 )
4178#define COMIEN_EDMAR_DIS (0x0 << 5 ) /* DIS */
4179#define COMIEN_EDMAR_EN (0x1 << 5 ) /* EN */
4180
4181/* COMIEN[EDMAT] - Enable DMA requests in receive mode */
4182#define COMIEN_EDMAT_BBA (*(volatile unsigned long *) 0x420A0090)
4183#define COMIEN_EDMAT_MSK (0x1 << 4 )
4184#define COMIEN_EDMAT (0x1 << 4 )
4185#define COMIEN_EDMAT_DIS (0x0 << 4 ) /* DIS */
4186#define COMIEN_EDMAT_EN (0x1 << 4 ) /* EN */
4187
4188/* COMIEN[EDSSI] - Enable Modem Status interrupt */
4189#define COMIEN_EDSSI_BBA (*(volatile unsigned long *) 0x420A008C)
4190#define COMIEN_EDSSI_MSK (0x1 << 3 )
4191#define COMIEN_EDSSI (0x1 << 3 )
4192#define COMIEN_EDSSI_DIS (0x0 << 3 ) /* DIS */
4193#define COMIEN_EDSSI_EN (0x1 << 3 ) /* EN */
4194
4195/* COMIEN[ELSI] - Enable Rx status interrupt */
4196#define COMIEN_ELSI_BBA (*(volatile unsigned long *) 0x420A0088)
4197#define COMIEN_ELSI_MSK (0x1 << 2 )
4198#define COMIEN_ELSI (0x1 << 2 )
4199#define COMIEN_ELSI_DIS (0x0 << 2 ) /* DIS */
4200#define COMIEN_ELSI_EN (0x1 << 2 ) /* EN */
4201
4202/* COMIEN[ETBEI] - Enable transmit buffer empty interrupt */
4203#define COMIEN_ETBEI_BBA (*(volatile unsigned long *) 0x420A0084)
4204#define COMIEN_ETBEI_MSK (0x1 << 1 )
4205#define COMIEN_ETBEI (0x1 << 1 )
4206#define COMIEN_ETBEI_DIS (0x0 << 1 ) /* DIS */
4207#define COMIEN_ETBEI_EN (0x1 << 1 ) /* EN */
4208
4209/* COMIEN[ERBFI] - Enable receive buffer full interrupt */
4210#define COMIEN_ERBFI_BBA (*(volatile unsigned long *) 0x420A0080)
4211#define COMIEN_ERBFI_MSK (0x1 << 0 )
4212#define COMIEN_ERBFI (0x1 << 0 )
4213#define COMIEN_ERBFI_DIS (0x0 << 0 ) /* DIS */
4214#define COMIEN_ERBFI_EN (0x1 << 0 ) /* EN */
4215
4216/* Reset Value for COMIIR*/
4217#define COMIIR_RVAL 0x1
4218
4219/* COMIIR[STA] - Status bits. */
4220#define COMIIR_STA_MSK (0x3 << 1 )
4221#define COMIIR_STA_MODEMSTATUS (0x0 << 1 ) /* MODEMSTATUS - Modem status interrupt. */
4222#define COMIIR_STA_TXBUFEMPTY (0x1 << 1 ) /* TXBUFEMPTY - Transmit buffer empty interrupt. */
4223#define COMIIR_STA_RXBUFFULL (0x2 << 1 ) /* RXBUFFULL - Receive buffer full interrupt. Read RBR register to clear. */
4224#define COMIIR_STA_RXLINESTATUS (0x3 << 1 ) /* RXLINESTATUS - Receive line status interrupt. Read LSR register to clear. */
4225
4226/* COMIIR[NINT] - Interrupt flag. */
4227#define COMIIR_NINT_BBA (*(volatile unsigned long *) 0x420A0100)
4228#define COMIIR_NINT_MSK (0x1 << 0 )
4229#define COMIIR_NINT (0x1 << 0 )
4230#define COMIIR_NINT_CLR (0x0 << 0 ) /* CLR */
4231#define COMIIR_NINT_SET (0x1 << 0 ) /* SET */
4232
4233/* Reset Value for COMLCR*/
4234#define COMLCR_RVAL 0x0
4235
4236/* COMLCR[BRK] - Set Break. */
4237#define COMLCR_BRK_BBA (*(volatile unsigned long *) 0x420A0198)
4238#define COMLCR_BRK_MSK (0x1 << 6 )
4239#define COMLCR_BRK (0x1 << 6 )
4240#define COMLCR_BRK_DIS (0x0 << 6 ) /* DIS */
4241#define COMLCR_BRK_EN (0x1 << 6 ) /* EN */
4242
4243/* COMLCR[SP] - Stick Parity. */
4244#define COMLCR_SP_BBA (*(volatile unsigned long *) 0x420A0194)
4245#define COMLCR_SP_MSK (0x1 << 5 )
4246#define COMLCR_SP (0x1 << 5 )
4247#define COMLCR_SP_DIS (0x0 << 5 ) /* DIS */
4248#define COMLCR_SP_EN (0x1 << 5 ) /* EN */
4249
4250/* COMLCR[EPS] - Even Parity Select Bit. */
4251#define COMLCR_EPS_BBA (*(volatile unsigned long *) 0x420A0190)
4252#define COMLCR_EPS_MSK (0x1 << 4 )
4253#define COMLCR_EPS (0x1 << 4 )
4254#define COMLCR_EPS_DIS (0x0 << 4 ) /* DIS */
4255#define COMLCR_EPS_EN (0x1 << 4 ) /* EN */
4256
4257/* COMLCR[PEN] - Parity Enable Bit. */
4258#define COMLCR_PEN_BBA (*(volatile unsigned long *) 0x420A018C)
4259#define COMLCR_PEN_MSK (0x1 << 3 )
4260#define COMLCR_PEN (0x1 << 3 )
4261#define COMLCR_PEN_DIS (0x0 << 3 ) /* DIS */
4262#define COMLCR_PEN_EN (0x1 << 3 ) /* EN */
4263
4264/* COMLCR[STOP] - Stop Bit. */
4265#define COMLCR_STOP_BBA (*(volatile unsigned long *) 0x420A0188)
4266#define COMLCR_STOP_MSK (0x1 << 2 )
4267#define COMLCR_STOP (0x1 << 2 )
4268#define COMLCR_STOP_DIS (0x0 << 2 ) /* DIS */
4269#define COMLCR_STOP_EN (0x1 << 2 ) /* EN */
4270
4271/* COMLCR[WLS] - Word Length Select bits */
4272#define COMLCR_WLS_MSK (0x3 << 0 )
4273#define COMLCR_WLS_5BITS (0x0 << 0 ) /* 5BITS */
4274#define COMLCR_WLS_6BITS (0x1 << 0 ) /* 6BITS */
4275#define COMLCR_WLS_7BITS (0x2 << 0 ) /* 7BITS */
4276#define COMLCR_WLS_8BITS (0x3 << 0 ) /* 8BITS */
4277
4278/* Reset Value for COMMCR*/
4279#define COMMCR_RVAL 0x0
4280
4281/* COMMCR[LOOPBACK] - Loop Back. */
4282#define COMMCR_LOOPBACK_BBA (*(volatile unsigned long *) 0x420A0210)
4283#define COMMCR_LOOPBACK_MSK (0x1 << 4 )
4284#define COMMCR_LOOPBACK (0x1 << 4 )
4285#define COMMCR_LOOPBACK_DIS (0x0 << 4 ) /* DIS */
4286#define COMMCR_LOOPBACK_EN (0x1 << 4 ) /* EN */
4287
4288/* COMMCR[OUT1] - Parity Enable Bit. */
4289#define COMMCR_OUT1_BBA (*(volatile unsigned long *) 0x420A020C)
4290#define COMMCR_OUT1_MSK (0x1 << 3 )
4291#define COMMCR_OUT1 (0x1 << 3 )
4292#define COMMCR_OUT1_DIS (0x0 << 3 ) /* DIS */
4293#define COMMCR_OUT1_EN (0x1 << 3 ) /* EN */
4294
4295/* COMMCR[OUT2] - Stop Bit. */
4296#define COMMCR_OUT2_BBA (*(volatile unsigned long *) 0x420A0208)
4297#define COMMCR_OUT2_MSK (0x1 << 2 )
4298#define COMMCR_OUT2 (0x1 << 2 )
4299#define COMMCR_OUT2_DIS (0x0 << 2 ) /* DIS */
4300#define COMMCR_OUT2_EN (0x1 << 2 ) /* EN */
4301
4302/* COMMCR[RTS] - Request To Send. */
4303#define COMMCR_RTS_BBA (*(volatile unsigned long *) 0x420A0204)
4304#define COMMCR_RTS_MSK (0x1 << 1 )
4305#define COMMCR_RTS (0x1 << 1 )
4306#define COMMCR_RTS_DIS (0x0 << 1 ) /* DIS */
4307#define COMMCR_RTS_EN (0x1 << 1 ) /* EN */
4308
4309/* COMMCR[DTR] - Data Terminal Ready. */
4310#define COMMCR_DTR_BBA (*(volatile unsigned long *) 0x420A0200)
4311#define COMMCR_DTR_MSK (0x1 << 0 )
4312#define COMMCR_DTR (0x1 << 0 )
4313#define COMMCR_DTR_DIS (0x0 << 0 ) /* DIS */
4314#define COMMCR_DTR_EN (0x1 << 0 ) /* EN */
4315
4316/* Reset Value for COMLSR*/
4317#define COMLSR_RVAL 0x60
4318
4319/* COMLSR[TEMT] - COMTX and Shift Register Empty Status Bit. */
4320#define COMLSR_TEMT_BBA (*(volatile unsigned long *) 0x420A0298)
4321#define COMLSR_TEMT_MSK (0x1 << 6 )
4322#define COMLSR_TEMT (0x1 << 6 )
4323#define COMLSR_TEMT_CLR (0x0 << 6 ) /* CLR */
4324#define COMLSR_TEMT_SET (0x1 << 6 ) /* SET */
4325
4326/* COMLSR[THRE] - COMTX Empty Status Bit. */
4327#define COMLSR_THRE_BBA (*(volatile unsigned long *) 0x420A0294)
4328#define COMLSR_THRE_MSK (0x1 << 5 )
4329#define COMLSR_THRE (0x1 << 5 )
4330#define COMLSR_THRE_CLR (0x0 << 5 ) /* CLR */
4331#define COMLSR_THRE_SET (0x1 << 5 ) /* SET */
4332
4333/* COMLSR[BI] - Break Indicator. */
4334#define COMLSR_BI_BBA (*(volatile unsigned long *) 0x420A0290)
4335#define COMLSR_BI_MSK (0x1 << 4 )
4336#define COMLSR_BI (0x1 << 4 )
4337#define COMLSR_BI_CLR (0x0 << 4 ) /* CLR */
4338#define COMLSR_BI_SET (0x1 << 4 ) /* SET */
4339
4340/* COMLSR[FE] - Framing Error. */
4341#define COMLSR_FE_BBA (*(volatile unsigned long *) 0x420A028C)
4342#define COMLSR_FE_MSK (0x1 << 3 )
4343#define COMLSR_FE (0x1 << 3 )
4344#define COMLSR_FE_CLR (0x0 << 3 ) /* CLR */
4345#define COMLSR_FE_SET (0x1 << 3 ) /* SET */
4346
4347/* COMLSR[PE] - Parity Error. */
4348#define COMLSR_PE_BBA (*(volatile unsigned long *) 0x420A0288)
4349#define COMLSR_PE_MSK (0x1 << 2 )
4350#define COMLSR_PE (0x1 << 2 )
4351#define COMLSR_PE_CLR (0x0 << 2 ) /* CLR */
4352#define COMLSR_PE_SET (0x1 << 2 ) /* SET */
4353
4354/* COMLSR[OE] - Overrun Error. */
4355#define COMLSR_OE_BBA (*(volatile unsigned long *) 0x420A0284)
4356#define COMLSR_OE_MSK (0x1 << 1 )
4357#define COMLSR_OE (0x1 << 1 )
4358#define COMLSR_OE_CLR (0x0 << 1 ) /* CLR */
4359#define COMLSR_OE_SET (0x1 << 1 ) /* SET */
4360
4361/* COMLSR[DR] - Data Ready. */
4362#define COMLSR_DR_BBA (*(volatile unsigned long *) 0x420A0280)
4363#define COMLSR_DR_MSK (0x1 << 0 )
4364#define COMLSR_DR (0x1 << 0 )
4365#define COMLSR_DR_CLR (0x0 << 0 ) /* CLR */
4366#define COMLSR_DR_SET (0x1 << 0 ) /* SET */
4367
4368/* Reset Value for COMMSR*/
4369#define COMMSR_RVAL 0x0
4370
4371/* COMMSR[DCD] - Data Carrier Detect. */
4372#define COMMSR_DCD_BBA (*(volatile unsigned long *) 0x420A031C)
4373#define COMMSR_DCD_MSK (0x1 << 7 )
4374#define COMMSR_DCD (0x1 << 7 )
4375#define COMMSR_DCD_DIS (0x0 << 7 ) /* DIS */
4376#define COMMSR_DCD_EN (0x1 << 7 ) /* EN */
4377
4378/* COMMSR[RI] - Ring Indicator. */
4379#define COMMSR_RI_BBA (*(volatile unsigned long *) 0x420A0318)
4380#define COMMSR_RI_MSK (0x1 << 6 )
4381#define COMMSR_RI (0x1 << 6 )
4382#define COMMSR_RI_DIS (0x0 << 6 ) /* DIS */
4383#define COMMSR_RI_EN (0x1 << 6 ) /* EN */
4384
4385/* COMMSR[DSR] - Data Set Ready. */
4386#define COMMSR_DSR_BBA (*(volatile unsigned long *) 0x420A0314)
4387#define COMMSR_DSR_MSK (0x1 << 5 )
4388#define COMMSR_DSR (0x1 << 5 )
4389#define COMMSR_DSR_DIS (0x0 << 5 ) /* DIS */
4390#define COMMSR_DSR_EN (0x1 << 5 ) /* EN */
4391
4392/* COMMSR[CTS] - Clear To Send. */
4393#define COMMSR_CTS_BBA (*(volatile unsigned long *) 0x420A0310)
4394#define COMMSR_CTS_MSK (0x1 << 4 )
4395#define COMMSR_CTS (0x1 << 4 )
4396#define COMMSR_CTS_DIS (0x0 << 4 ) /* DIS */
4397#define COMMSR_CTS_EN (0x1 << 4 ) /* EN */
4398
4399/* COMMSR[DDCD] - Delta DCD. */
4400#define COMMSR_DDCD_BBA (*(volatile unsigned long *) 0x420A030C)
4401#define COMMSR_DDCD_MSK (0x1 << 3 )
4402#define COMMSR_DDCD (0x1 << 3 )
4403#define COMMSR_DDCD_DIS (0x0 << 3 ) /* DIS */
4404#define COMMSR_DDCD_EN (0x1 << 3 ) /* EN */
4405
4406/* COMMSR[TERI] - Trailing Edge RI. */
4407#define COMMSR_TERI_BBA (*(volatile unsigned long *) 0x420A0308)
4408#define COMMSR_TERI_MSK (0x1 << 2 )
4409#define COMMSR_TERI (0x1 << 2 )
4410#define COMMSR_TERI_DIS (0x0 << 2 ) /* DIS */
4411#define COMMSR_TERI_EN (0x1 << 2 ) /* EN */
4412
4413/* COMMSR[DDSR] - Delta DSR. */
4414#define COMMSR_DDSR_BBA (*(volatile unsigned long *) 0x420A0304)
4415#define COMMSR_DDSR_MSK (0x1 << 1 )
4416#define COMMSR_DDSR (0x1 << 1 )
4417#define COMMSR_DDSR_DIS (0x0 << 1 ) /* DIS */
4418#define COMMSR_DDSR_EN (0x1 << 1 ) /* EN */
4419
4420/* COMMSR[DCTS] - Delta CTS. */
4421#define COMMSR_DCTS_BBA (*(volatile unsigned long *) 0x420A0300)
4422#define COMMSR_DCTS_MSK (0x1 << 0 )
4423#define COMMSR_DCTS (0x1 << 0 )
4424#define COMMSR_DCTS_DIS (0x0 << 0 ) /* DIS */
4425#define COMMSR_DCTS_EN (0x1 << 0 ) /* EN */
4426
4427/* Reset Value for COMFBR*/
4428#define COMFBR_RVAL 0x0
4429
4430/* COMFBR[ENABLE] - Enable */
4431#define COMFBR_ENABLE_BBA (*(volatile unsigned long *) 0x420A04BC)
4432#define COMFBR_ENABLE_MSK (0x1 << 15 )
4433#define COMFBR_ENABLE (0x1 << 15 )
4434#define COMFBR_ENABLE_DIS (0x0 << 15 ) /* DIS */
4435#define COMFBR_ENABLE_EN (0x1 << 15 ) /* EN */
4436
4437/* COMFBR[DIVM] - Fractional M Divide bits */
4438#define COMFBR_DIVM_MSK (0x3 << 11 )
4439
4440/* COMFBR[DIVN] - Fractional N Divide bits */
4441#define COMFBR_DIVN_MSK (0x7FF << 0 )
4442
4443/* Reset Value for COMDIV*/
4444#define COMDIV_RVAL 0x1
4445
4446/* COMDIV[VALUE] - Sets the baudrate */
4447#define COMDIV_VALUE_MSK (0xFFFF << 0 )
4448
4449/* Reset Value for COMCON*/
4450#define COMCON_RVAL 0x0
4451
4452/* COMCON[DISABLE] - Uart Disable */
4453#define COMCON_DISABLE_BBA (*(volatile unsigned long *) 0x420A0600)
4454#define COMCON_DISABLE_MSK (0x1 << 0 )
4455#define COMCON_DISABLE (0x1 << 0 )
4456#define COMCON_DISABLE_DIS (0x0 << 0 ) /* DIS */
4457#define COMCON_DISABLE_EN (0x1 << 0 ) /* EN */
4458// ------------------------------------------------------------------------------------------------
4459// ----- GPIO0 -----
4460// ------------------------------------------------------------------------------------------------
4461
4462
4463/**
4464 * @brief General Purpose Input Output (pADI_GP0)
4465 */
4466
4467#if (__NO_MMR_STRUCTS__==0)
4468typedef struct { /*!< pADI_GP0 Structure */
4469 __IO uint16_t GPCON; /*!< GPIO Port 0 configuration */
4470 __I uint16_t RESERVED0;
4471 __IO uint8_t GPOEN; /*!< GPIO Port 0 output enable */
4472 __I uint8_t RESERVED1[3];
4473 __IO uint8_t GPPUL; /*!< GPIO Port 0 output pull up enable. */
4474 __I uint8_t RESERVED2[3];
4475 __IO uint8_t GPOCE; /*!< GPIO Port 0 tri state */
4476 __I uint8_t RESERVED3[7];
4477 __IO uint8_t GPIN; /*!< GPIO Port 0 data input. */
4478 __I uint8_t RESERVED4[3];
4479 __IO uint8_t GPOUT; /*!< GPIO Port 0 data out. */
4480 __I uint8_t RESERVED5[3];
4481 __IO uint8_t GPSET; /*!< GPIO Port 0 data out set */
4482 __I uint8_t RESERVED6[3];
4483 __IO uint8_t GPCLR; /*!< GPIO Port 0 data out clear. */
4484 __I uint8_t RESERVED7[3];
4485 __IO uint8_t GPTGL; /*!< GPIO Port 0 pin toggle. */
4486} ADI_GPIO_TypeDef;
4487#else // (__NO_MMR_STRUCTS__==0)
4488#define GP0CON (*(volatile unsigned short int *) 0x40006000)
4489#define GP0OEN (*(volatile unsigned char *) 0x40006004)
4490#define GP0PUL (*(volatile unsigned char *) 0x40006008)
4491#define GP0OCE (*(volatile unsigned char *) 0x4000600C)
4492#define GP0IN (*(volatile unsigned char *) 0x40006014)
4493#define GP0OUT (*(volatile unsigned char *) 0x40006018)
4494#define GP0SET (*(volatile unsigned char *) 0x4000601C)
4495#define GP0CLR (*(volatile unsigned char *) 0x40006020)
4496#define GP0TGL (*(volatile unsigned char *) 0x40006024)
4497#endif // (__NO_MMR_STRUCTS__==0)
4498
4499/* Reset Value for GP0CON*/
4500#define GP0CON_RVAL 0x0
4501
4502/* GP0CON[CON7] - Configuration bits for P0.7 */
4503#define GP0CON_CON7_MSK (0x3 << 14 )
4504#define GP0CON_CON7_PORB (0x0 << 14 ) /* PORB */
4505#define GP0CON_CON7_GPIO (0x1 << 14 ) /* GPIO */
4506#define GP0CON_CON7_UARTTXD (0x2 << 14 ) /* UARTTXD */
4507
4508/* GP0CON[CON6] - Configuration bits for P0.6 */
4509#define GP0CON_CON6_MSK (0x3 << 12 )
4510#define GP0CON_CON6_GPIOIRQ2 (0x0 << 12 ) /* GPIOIRQ2 */
4511#define GP0CON_CON6_UARTRXD (0x1 << 12 ) /* UARTRXD */
4512
4513/* GP0CON[CON5] - Configuration bits for P0.5 */
4514#define GP0CON_CON5_MSK (0x3 << 10 )
4515#define GP0CON_CON5_GPIOIRQ1 (0x0 << 10 ) /* GPIOIRQ1 */
4516#define GP0CON_CON5_UARTCTS (0x1 << 10 ) /* UARTCTS */
4517
4518/* GP0CON[CON4] - Configuration bits for P0.4 */
4519#define GP0CON_CON4_MSK (0x3 << 8 )
4520#define GP0CON_CON4_GPIO (0x0 << 8 ) /* GPIO */
4521#define GP0CON_CON4_UARTRTS (0x1 << 8 ) /* UARTRTS */
4522#define GP0CON_CON4_ECLKOUT (0x2 << 8 ) /* ECLKOUT */
4523
4524/* GP0CON[CON3] - Configuration bits for P0.3 */
4525#define GP0CON_CON3_MSK (0x3 << 6 )
4526#define GP0CON_CON3_GPIOIRQ0 (0x0 << 6 ) /* GPIOIRQ0 */
4527#define GP0CON_CON3_SPI1CS0 (0x1 << 6 ) /* SPI1CS0 */
4528
4529/* GP0CON[CON2] - Configuration bits for P0.2 */
4530#define GP0CON_CON2_MSK (0x3 << 4 )
4531#define GP0CON_CON2_GPIO (0x0 << 4 ) /* GPIO */
4532#define GP0CON_CON2_SPI1MOSI (0x1 << 4 ) /* SPI1MOSI */
4533#define GP0CON_CON2_I2CSDA (0x2 << 4 ) /* I2CSDA */
4534#define GP0CON_CON2_UARTTXD (0x3 << 4 ) /* UARTTXD */
4535
4536/* GP0CON[CON1] - Configuration bits for P0.1 */
4537#define GP0CON_CON1_MSK (0x3 << 2 )
4538#define GP0CON_CON1_GPIO (0x0 << 2 ) /* GPIO */
4539#define GP0CON_CON1_SPI1SCLK (0x1 << 2 ) /* SPI1SCLK */
4540#define GP0CON_CON1_I2CSCL (0x2 << 2 ) /* I2CSCL */
4541#define GP0CON_CON1_UARTRXD (0x3 << 2 ) /* UARTRXD */
4542
4543/* GP0CON[CON0] - Configuration bits for P0.0 */
4544#define GP0CON_CON0_MSK (0x3 << 0 )
4545#define GP0CON_CON0_GPIO (0x0 << 0 ) /* GPIO */
4546#define GP0CON_CON0_SPI1MISO (0x1 << 0 ) /* SPI1MISO */
4547
4548/* Reset Value for GP0OEN*/
4549#define GP0OEN_RVAL 0x0
4550
4551/* GP0OEN[OEN7] - Direction for port pin */
4552#define GP0OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C009C)
4553#define GP0OEN_OEN7_MSK (0x1 << 7 )
4554#define GP0OEN_OEN7 (0x1 << 7 )
4555#define GP0OEN_OEN7_IN (0x0 << 7 ) /* IN */
4556#define GP0OEN_OEN7_OUT (0x1 << 7 ) /* OUT */
4557
4558/* GP0OEN[OEN6] - Direction for port pin */
4559#define GP0OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0098)
4560#define GP0OEN_OEN6_MSK (0x1 << 6 )
4561#define GP0OEN_OEN6 (0x1 << 6 )
4562#define GP0OEN_OEN6_IN (0x0 << 6 ) /* IN */
4563#define GP0OEN_OEN6_OUT (0x1 << 6 ) /* OUT */
4564
4565/* GP0OEN[OEN5] - Direction for port pin */
4566#define GP0OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0094)
4567#define GP0OEN_OEN5_MSK (0x1 << 5 )
4568#define GP0OEN_OEN5 (0x1 << 5 )
4569#define GP0OEN_OEN5_IN (0x0 << 5 ) /* IN */
4570#define GP0OEN_OEN5_OUT (0x1 << 5 ) /* OUT */
4571
4572/* GP0OEN[OEN4] - Direction for port pin */
4573#define GP0OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0090)
4574#define GP0OEN_OEN4_MSK (0x1 << 4 )
4575#define GP0OEN_OEN4 (0x1 << 4 )
4576#define GP0OEN_OEN4_IN (0x0 << 4 ) /* IN */
4577#define GP0OEN_OEN4_OUT (0x1 << 4 ) /* OUT */
4578
4579/* GP0OEN[OEN3] - Direction for port pin */
4580#define GP0OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C008C)
4581#define GP0OEN_OEN3_MSK (0x1 << 3 )
4582#define GP0OEN_OEN3 (0x1 << 3 )
4583#define GP0OEN_OEN3_IN (0x0 << 3 ) /* IN */
4584#define GP0OEN_OEN3_OUT (0x1 << 3 ) /* OUT */
4585
4586/* GP0OEN[OEN2] - Direction for port pin */
4587#define GP0OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0088)
4588#define GP0OEN_OEN2_MSK (0x1 << 2 )
4589#define GP0OEN_OEN2 (0x1 << 2 )
4590#define GP0OEN_OEN2_IN (0x0 << 2 ) /* IN */
4591#define GP0OEN_OEN2_OUT (0x1 << 2 ) /* OUT */
4592
4593/* GP0OEN[OEN1] - Direction for port pin */
4594#define GP0OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0084)
4595#define GP0OEN_OEN1_MSK (0x1 << 1 )
4596#define GP0OEN_OEN1 (0x1 << 1 )
4597#define GP0OEN_OEN1_IN (0x0 << 1 ) /* IN */
4598#define GP0OEN_OEN1_OUT (0x1 << 1 ) /* OUT */
4599
4600/* GP0OEN[OEN0] - Direction for port pin */
4601#define GP0OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0080)
4602#define GP0OEN_OEN0_MSK (0x1 << 0 )
4603#define GP0OEN_OEN0 (0x1 << 0 )
4604#define GP0OEN_OEN0_IN (0x0 << 0 ) /* IN */
4605#define GP0OEN_OEN0_OUT (0x1 << 0 ) /* OUT */
4606
4607/* Reset Value for GP0PUL*/
4608#define GP0PUL_RVAL 0xFF
4609
4610/* GP0PUL[PUL7] - Pull Up Enable for port pin */
4611#define GP0PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C011C)
4612#define GP0PUL_PUL7_MSK (0x1 << 7 )
4613#define GP0PUL_PUL7 (0x1 << 7 )
4614#define GP0PUL_PUL7_DIS (0x0 << 7 ) /* DIS */
4615#define GP0PUL_PUL7_EN (0x1 << 7 ) /* EN */
4616
4617/* GP0PUL[PUL6] - Pull Up Enable for port pin */
4618#define GP0PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0118)
4619#define GP0PUL_PUL6_MSK (0x1 << 6 )
4620#define GP0PUL_PUL6 (0x1 << 6 )
4621#define GP0PUL_PUL6_DIS (0x0 << 6 ) /* DIS */
4622#define GP0PUL_PUL6_EN (0x1 << 6 ) /* EN */
4623
4624/* GP0PUL[PUL5] - Pull Up Enable for port pin */
4625#define GP0PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0114)
4626#define GP0PUL_PUL5_MSK (0x1 << 5 )
4627#define GP0PUL_PUL5 (0x1 << 5 )
4628#define GP0PUL_PUL5_DIS (0x0 << 5 ) /* DIS */
4629#define GP0PUL_PUL5_EN (0x1 << 5 ) /* EN */
4630
4631/* GP0PUL[PUL4] - Pull Up Enable for port pin */
4632#define GP0PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0110)
4633#define GP0PUL_PUL4_MSK (0x1 << 4 )
4634#define GP0PUL_PUL4 (0x1 << 4 )
4635#define GP0PUL_PUL4_DIS (0x0 << 4 ) /* DIS */
4636#define GP0PUL_PUL4_EN (0x1 << 4 ) /* EN */
4637
4638/* GP0PUL[PUL3] - Pull Up Enable for port pin */
4639#define GP0PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C010C)
4640#define GP0PUL_PUL3_MSK (0x1 << 3 )
4641#define GP0PUL_PUL3 (0x1 << 3 )
4642#define GP0PUL_PUL3_DIS (0x0 << 3 ) /* DIS */
4643#define GP0PUL_PUL3_EN (0x1 << 3 ) /* EN */
4644
4645/* GP0PUL[PUL2] - Pull Up Enable for port pin */
4646#define GP0PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0108)
4647#define GP0PUL_PUL2_MSK (0x1 << 2 )
4648#define GP0PUL_PUL2 (0x1 << 2 )
4649#define GP0PUL_PUL2_DIS (0x0 << 2 ) /* DIS */
4650#define GP0PUL_PUL2_EN (0x1 << 2 ) /* EN */
4651
4652/* GP0PUL[PUL1] - Pull Up Enable for port pin */
4653#define GP0PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0104)
4654#define GP0PUL_PUL1_MSK (0x1 << 1 )
4655#define GP0PUL_PUL1 (0x1 << 1 )
4656#define GP0PUL_PUL1_DIS (0x0 << 1 ) /* DIS */
4657#define GP0PUL_PUL1_EN (0x1 << 1 ) /* EN */
4658
4659/* GP0PUL[PUL0] - Pull Up Enable for port pin */
4660#define GP0PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0100)
4661#define GP0PUL_PUL0_MSK (0x1 << 0 )
4662#define GP0PUL_PUL0 (0x1 << 0 )
4663#define GP0PUL_PUL0_DIS (0x0 << 0 ) /* DIS */
4664#define GP0PUL_PUL0_EN (0x1 << 0 ) /* EN */
4665
4666/* Reset Value for GP0OCE*/
4667#define GP0OCE_RVAL 0x0
4668
4669/* GP0OCE[OCE7] - open circuit Enable for port pin */
4670#define GP0OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C019C)
4671#define GP0OCE_OCE7_MSK (0x1 << 7 )
4672#define GP0OCE_OCE7 (0x1 << 7 )
4673#define GP0OCE_OCE7_DIS (0x0 << 7 ) /* DIS */
4674#define GP0OCE_OCE7_EN (0x1 << 7 ) /* EN */
4675
4676/* GP0OCE[OCE6] - open circuit Enable for port pin */
4677#define GP0OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0198)
4678#define GP0OCE_OCE6_MSK (0x1 << 6 )
4679#define GP0OCE_OCE6 (0x1 << 6 )
4680#define GP0OCE_OCE6_DIS (0x0 << 6 ) /* DIS */
4681#define GP0OCE_OCE6_EN (0x1 << 6 ) /* EN */
4682
4683/* GP0OCE[OCE5] - open circuit Enable for port pin */
4684#define GP0OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0194)
4685#define GP0OCE_OCE5_MSK (0x1 << 5 )
4686#define GP0OCE_OCE5 (0x1 << 5 )
4687#define GP0OCE_OCE5_DIS (0x0 << 5 ) /* DIS */
4688#define GP0OCE_OCE5_EN (0x1 << 5 ) /* EN */
4689
4690/* GP0OCE[OCE4] - open circuit Enable for port pin */
4691#define GP0OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0190)
4692#define GP0OCE_OCE4_MSK (0x1 << 4 )
4693#define GP0OCE_OCE4 (0x1 << 4 )
4694#define GP0OCE_OCE4_DIS (0x0 << 4 ) /* DIS */
4695#define GP0OCE_OCE4_EN (0x1 << 4 ) /* EN */
4696
4697/* GP0OCE[OCE3] - open circuit Enable for port pin */
4698#define GP0OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C018C)
4699#define GP0OCE_OCE3_MSK (0x1 << 3 )
4700#define GP0OCE_OCE3 (0x1 << 3 )
4701#define GP0OCE_OCE3_DIS (0x0 << 3 ) /* DIS */
4702#define GP0OCE_OCE3_EN (0x1 << 3 ) /* EN */
4703
4704/* GP0OCE[OCE2] - open circuit Enable for port pin */
4705#define GP0OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0188)
4706#define GP0OCE_OCE2_MSK (0x1 << 2 )
4707#define GP0OCE_OCE2 (0x1 << 2 )
4708#define GP0OCE_OCE2_DIS (0x0 << 2 ) /* DIS */
4709#define GP0OCE_OCE2_EN (0x1 << 2 ) /* EN */
4710
4711/* GP0OCE[OCE1] - open circuit Enable for port pin */
4712#define GP0OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0184)
4713#define GP0OCE_OCE1_MSK (0x1 << 1 )
4714#define GP0OCE_OCE1 (0x1 << 1 )
4715#define GP0OCE_OCE1_DIS (0x0 << 1 ) /* DIS */
4716#define GP0OCE_OCE1_EN (0x1 << 1 ) /* EN */
4717
4718/* GP0OCE[OCE0] - open circuit Enable for port pin */
4719#define GP0OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0180)
4720#define GP0OCE_OCE0_MSK (0x1 << 0 )
4721#define GP0OCE_OCE0 (0x1 << 0 )
4722#define GP0OCE_OCE0_DIS (0x0 << 0 ) /* DIS */
4723#define GP0OCE_OCE0_EN (0x1 << 0 ) /* EN */
4724
4725/* Reset Value for GP0IN*/
4726#define GP0IN_RVAL 0xFF
4727
4728/* GP0IN[IN7] - Input for port pin */
4729#define GP0IN_IN7_BBA (*(volatile unsigned long *) 0x420C029C)
4730#define GP0IN_IN7_MSK (0x1 << 7 )
4731#define GP0IN_IN7 (0x1 << 7 )
4732#define GP0IN_IN7_LOW (0x0 << 7 ) /* LOW */
4733#define GP0IN_IN7_HIGH (0x1 << 7 ) /* HIGH */
4734
4735/* GP0IN[IN6] - Input for port pin */
4736#define GP0IN_IN6_BBA (*(volatile unsigned long *) 0x420C0298)
4737#define GP0IN_IN6_MSK (0x1 << 6 )
4738#define GP0IN_IN6 (0x1 << 6 )
4739#define GP0IN_IN6_LOW (0x0 << 6 ) /* LOW */
4740#define GP0IN_IN6_HIGH (0x1 << 6 ) /* HIGH */
4741
4742/* GP0IN[IN5] - Input for port pin */
4743#define GP0IN_IN5_BBA (*(volatile unsigned long *) 0x420C0294)
4744#define GP0IN_IN5_MSK (0x1 << 5 )
4745#define GP0IN_IN5 (0x1 << 5 )
4746#define GP0IN_IN5_LOW (0x0 << 5 ) /* LOW */
4747#define GP0IN_IN5_HIGH (0x1 << 5 ) /* HIGH */
4748
4749/* GP0IN[IN4] - Input for port pin */
4750#define GP0IN_IN4_BBA (*(volatile unsigned long *) 0x420C0290)
4751#define GP0IN_IN4_MSK (0x1 << 4 )
4752#define GP0IN_IN4 (0x1 << 4 )
4753#define GP0IN_IN4_LOW (0x0 << 4 ) /* LOW */
4754#define GP0IN_IN4_HIGH (0x1 << 4 ) /* HIGH */
4755
4756/* GP0IN[IN3] - Input for port pin */
4757#define GP0IN_IN3_BBA (*(volatile unsigned long *) 0x420C028C)
4758#define GP0IN_IN3_MSK (0x1 << 3 )
4759#define GP0IN_IN3 (0x1 << 3 )
4760#define GP0IN_IN3_LOW (0x0 << 3 ) /* LOW */
4761#define GP0IN_IN3_HIGH (0x1 << 3 ) /* HIGH */
4762
4763/* GP0IN[IN2] - Input for port pin */
4764#define GP0IN_IN2_BBA (*(volatile unsigned long *) 0x420C0288)
4765#define GP0IN_IN2_MSK (0x1 << 2 )
4766#define GP0IN_IN2 (0x1 << 2 )
4767#define GP0IN_IN2_LOW (0x0 << 2 ) /* LOW */
4768#define GP0IN_IN2_HIGH (0x1 << 2 ) /* HIGH */
4769
4770/* GP0IN[IN1] - Input for port pin */
4771#define GP0IN_IN1_BBA (*(volatile unsigned long *) 0x420C0284)
4772#define GP0IN_IN1_MSK (0x1 << 1 )
4773#define GP0IN_IN1 (0x1 << 1 )
4774#define GP0IN_IN1_LOW (0x0 << 1 ) /* LOW */
4775#define GP0IN_IN1_HIGH (0x1 << 1 ) /* HIGH */
4776
4777/* GP0IN[IN0] - Input for port pin */
4778#define GP0IN_IN0_BBA (*(volatile unsigned long *) 0x420C0280)
4779#define GP0IN_IN0_MSK (0x1 << 0 )
4780#define GP0IN_IN0 (0x1 << 0 )
4781#define GP0IN_IN0_LOW (0x0 << 0 ) /* LOW */
4782#define GP0IN_IN0_HIGH (0x1 << 0 ) /* HIGH */
4783
4784/* Reset Value for GP0OUT*/
4785#define GP0OUT_RVAL 0x0
4786
4787/* GP0OUT[OUT7] - Output for port pin */
4788#define GP0OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C031C)
4789#define GP0OUT_OUT7_MSK (0x1 << 7 )
4790#define GP0OUT_OUT7 (0x1 << 7 )
4791#define GP0OUT_OUT7_LOW (0x0 << 7 ) /* LOW */
4792#define GP0OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH */
4793
4794/* GP0OUT[OUT6] - Output for port pin */
4795#define GP0OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0318)
4796#define GP0OUT_OUT6_MSK (0x1 << 6 )
4797#define GP0OUT_OUT6 (0x1 << 6 )
4798#define GP0OUT_OUT6_LOW (0x0 << 6 ) /* LOW */
4799#define GP0OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH */
4800
4801/* GP0OUT[OUT5] - Output for port pin */
4802#define GP0OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0314)
4803#define GP0OUT_OUT5_MSK (0x1 << 5 )
4804#define GP0OUT_OUT5 (0x1 << 5 )
4805#define GP0OUT_OUT5_LOW (0x0 << 5 ) /* LOW */
4806#define GP0OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH */
4807
4808/* GP0OUT[OUT4] - Output for port pin */
4809#define GP0OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0310)
4810#define GP0OUT_OUT4_MSK (0x1 << 4 )
4811#define GP0OUT_OUT4 (0x1 << 4 )
4812#define GP0OUT_OUT4_LOW (0x0 << 4 ) /* LOW */
4813#define GP0OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH */
4814
4815/* GP0OUT[OUT3] - Output for port pin */
4816#define GP0OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C030C)
4817#define GP0OUT_OUT3_MSK (0x1 << 3 )
4818#define GP0OUT_OUT3 (0x1 << 3 )
4819#define GP0OUT_OUT3_LOW (0x0 << 3 ) /* LOW */
4820#define GP0OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH */
4821
4822/* GP0OUT[OUT2] - Output for port pin */
4823#define GP0OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0308)
4824#define GP0OUT_OUT2_MSK (0x1 << 2 )
4825#define GP0OUT_OUT2 (0x1 << 2 )
4826#define GP0OUT_OUT2_LOW (0x0 << 2 ) /* LOW */
4827#define GP0OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH */
4828
4829/* GP0OUT[OUT1] - Output for port pin */
4830#define GP0OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0304)
4831#define GP0OUT_OUT1_MSK (0x1 << 1 )
4832#define GP0OUT_OUT1 (0x1 << 1 )
4833#define GP0OUT_OUT1_LOW (0x0 << 1 ) /* LOW */
4834#define GP0OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH */
4835
4836/* GP0OUT[OUT0] - Output for port pin */
4837#define GP0OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0300)
4838#define GP0OUT_OUT0_MSK (0x1 << 0 )
4839#define GP0OUT_OUT0 (0x1 << 0 )
4840#define GP0OUT_OUT0_LOW (0x0 << 0 ) /* LOW */
4841#define GP0OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH */
4842
4843/* Reset Value for GP0SET*/
4844#define GP0SET_RVAL 0x0
4845
4846/* GP0SET[SET7] - Set Output High for port pin */
4847#define GP0SET_SET7_BBA (*(volatile unsigned long *) 0x420C039C)
4848#define GP0SET_SET7_MSK (0x1 << 7 )
4849#define GP0SET_SET7 (0x1 << 7 )
4850#define GP0SET_SET7_SET (0x1 << 7 ) /* SET */
4851
4852/* GP0SET[SET6] - Set Output High for port pin */
4853#define GP0SET_SET6_BBA (*(volatile unsigned long *) 0x420C0398)
4854#define GP0SET_SET6_MSK (0x1 << 6 )
4855#define GP0SET_SET6 (0x1 << 6 )
4856#define GP0SET_SET6_SET (0x1 << 6 ) /* SET */
4857
4858/* GP0SET[SET5] - Set Output High for port pin */
4859#define GP0SET_SET5_BBA (*(volatile unsigned long *) 0x420C0394)
4860#define GP0SET_SET5_MSK (0x1 << 5 )
4861#define GP0SET_SET5 (0x1 << 5 )
4862#define GP0SET_SET5_SET (0x1 << 5 ) /* SET */
4863
4864/* GP0SET[SET4] - Set Output High for port pin */
4865#define GP0SET_SET4_BBA (*(volatile unsigned long *) 0x420C0390)
4866#define GP0SET_SET4_MSK (0x1 << 4 )
4867#define GP0SET_SET4 (0x1 << 4 )
4868#define GP0SET_SET4_SET (0x1 << 4 ) /* SET */
4869
4870/* GP0SET[SET3] - Set Output High for port pin */
4871#define GP0SET_SET3_BBA (*(volatile unsigned long *) 0x420C038C)
4872#define GP0SET_SET3_MSK (0x1 << 3 )
4873#define GP0SET_SET3 (0x1 << 3 )
4874#define GP0SET_SET3_SET (0x1 << 3 ) /* SET */
4875
4876/* GP0SET[SET2] - Set Output High for port pin */
4877#define GP0SET_SET2_BBA (*(volatile unsigned long *) 0x420C0388)
4878#define GP0SET_SET2_MSK (0x1 << 2 )
4879#define GP0SET_SET2 (0x1 << 2 )
4880#define GP0SET_SET2_SET (0x1 << 2 ) /* SET */
4881
4882/* GP0SET[SET1] - Set Output High for port pin */
4883#define GP0SET_SET1_BBA (*(volatile unsigned long *) 0x420C0384)
4884#define GP0SET_SET1_MSK (0x1 << 1 )
4885#define GP0SET_SET1 (0x1 << 1 )
4886#define GP0SET_SET1_SET (0x1 << 1 ) /* SET */
4887
4888/* GP0SET[SET0] - Set Output High for port pin */
4889#define GP0SET_SET0_BBA (*(volatile unsigned long *) 0x420C0380)
4890#define GP0SET_SET0_MSK (0x1 << 0 )
4891#define GP0SET_SET0 (0x1 << 0 )
4892#define GP0SET_SET0_SET (0x1 << 0 ) /* SET */
4893
4894/* Reset Value for GP0CLR*/
4895#define GP0CLR_RVAL 0x0
4896
4897/* GP0CLR[CLR7] - Set Output Low for port pin */
4898#define GP0CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C041C)
4899#define GP0CLR_CLR7_MSK (0x1 << 7 )
4900#define GP0CLR_CLR7 (0x1 << 7 )
4901#define GP0CLR_CLR7_CLR (0x1 << 7 ) /* CLR */
4902
4903/* GP0CLR[CLR6] - Set Output Low for port pin */
4904#define GP0CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C0418)
4905#define GP0CLR_CLR6_MSK (0x1 << 6 )
4906#define GP0CLR_CLR6 (0x1 << 6 )
4907#define GP0CLR_CLR6_CLR (0x1 << 6 ) /* CLR */
4908
4909/* GP0CLR[CLR5] - Set Output Low for port pin */
4910#define GP0CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C0414)
4911#define GP0CLR_CLR5_MSK (0x1 << 5 )
4912#define GP0CLR_CLR5 (0x1 << 5 )
4913#define GP0CLR_CLR5_CLR (0x1 << 5 ) /* CLR */
4914
4915/* GP0CLR[CLR4] - Set Output Low for port pin */
4916#define GP0CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C0410)
4917#define GP0CLR_CLR4_MSK (0x1 << 4 )
4918#define GP0CLR_CLR4 (0x1 << 4 )
4919#define GP0CLR_CLR4_CLR (0x1 << 4 ) /* CLR */
4920
4921/* GP0CLR[CLR3] - Set Output Low for port pin */
4922#define GP0CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C040C)
4923#define GP0CLR_CLR3_MSK (0x1 << 3 )
4924#define GP0CLR_CLR3 (0x1 << 3 )
4925#define GP0CLR_CLR3_CLR (0x1 << 3 ) /* CLR */
4926
4927/* GP0CLR[CLR2] - Set Output Low for port pin */
4928#define GP0CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C0408)
4929#define GP0CLR_CLR2_MSK (0x1 << 2 )
4930#define GP0CLR_CLR2 (0x1 << 2 )
4931#define GP0CLR_CLR2_CLR (0x1 << 2 ) /* CLR */
4932
4933/* GP0CLR[CLR1] - Set Output Low for port pin */
4934#define GP0CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C0404)
4935#define GP0CLR_CLR1_MSK (0x1 << 1 )
4936#define GP0CLR_CLR1 (0x1 << 1 )
4937#define GP0CLR_CLR1_CLR (0x1 << 1 ) /* CLR */
4938
4939/* GP0CLR[CLR0] - Set Output Low for port pin */
4940#define GP0CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C0400)
4941#define GP0CLR_CLR0_MSK (0x1 << 0 )
4942#define GP0CLR_CLR0 (0x1 << 0 )
4943#define GP0CLR_CLR0_CLR (0x1 << 0 ) /* CLR */
4944
4945/* Reset Value for GP0TGL*/
4946#define GP0TGL_RVAL 0x0
4947
4948/* GP0TGL[TGL7] - Toggle Output for port pin */
4949#define GP0TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C049C)
4950#define GP0TGL_TGL7_MSK (0x1 << 7 )
4951#define GP0TGL_TGL7 (0x1 << 7 )
4952#define GP0TGL_TGL7_TGL (0x1 << 7 ) /* TGL */
4953
4954/* GP0TGL[TGL6] - Toggle Output for port pin */
4955#define GP0TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C0498)
4956#define GP0TGL_TGL6_MSK (0x1 << 6 )
4957#define GP0TGL_TGL6 (0x1 << 6 )
4958#define GP0TGL_TGL6_TGL (0x1 << 6 ) /* TGL */
4959
4960/* GP0TGL[TGL5] - Toggle Output for port pin */
4961#define GP0TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C0494)
4962#define GP0TGL_TGL5_MSK (0x1 << 5 )
4963#define GP0TGL_TGL5 (0x1 << 5 )
4964#define GP0TGL_TGL5_TGL (0x1 << 5 ) /* TGL */
4965
4966/* GP0TGL[TGL4] - Toggle Output for port pin */
4967#define GP0TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C0490)
4968#define GP0TGL_TGL4_MSK (0x1 << 4 )
4969#define GP0TGL_TGL4 (0x1 << 4 )
4970#define GP0TGL_TGL4_TGL (0x1 << 4 ) /* TGL */
4971
4972/* GP0TGL[TGL3] - Toggle Output for port pin */
4973#define GP0TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C048C)
4974#define GP0TGL_TGL3_MSK (0x1 << 3 )
4975#define GP0TGL_TGL3 (0x1 << 3 )
4976#define GP0TGL_TGL3_TGL (0x1 << 3 ) /* TGL */
4977
4978/* GP0TGL[TGL2] - Toggle Output for port pin */
4979#define GP0TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C0488)
4980#define GP0TGL_TGL2_MSK (0x1 << 2 )
4981#define GP0TGL_TGL2 (0x1 << 2 )
4982#define GP0TGL_TGL2_TGL (0x1 << 2 ) /* TGL */
4983
4984/* GP0TGL[TGL1] - Toggle Output for port pin */
4985#define GP0TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C0484)
4986#define GP0TGL_TGL1_MSK (0x1 << 1 )
4987#define GP0TGL_TGL1 (0x1 << 1 )
4988#define GP0TGL_TGL1_TGL (0x1 << 1 ) /* TGL */
4989
4990/* GP0TGL[TGL0] - Toggle Output for port pin */
4991#define GP0TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C0480)
4992#define GP0TGL_TGL0_MSK (0x1 << 0 )
4993#define GP0TGL_TGL0 (0x1 << 0 )
4994#define GP0TGL_TGL0_TGL (0x1 << 0 ) /* TGL */
4995#if (__NO_MMR_STRUCTS__==1)
4996
4997#define GP1CON (*(volatile unsigned short int *) 0x40006030)
4998#define GP1OEN (*(volatile unsigned char *) 0x40006034)
4999#define GP1PUL (*(volatile unsigned char *) 0x40006038)
5000#define GP1OCE (*(volatile unsigned char *) 0x4000603C)
5001#define GP1IN (*(volatile unsigned char *) 0x40006044)
5002#define GP1OUT (*(volatile unsigned char *) 0x40006048)
5003#define GP1SET (*(volatile unsigned char *) 0x4000604C)
5004#define GP1CLR (*(volatile unsigned char *) 0x40006050)
5005#define GP1TGL (*(volatile unsigned char *) 0x40006054)
5006#endif // (__NO_MMR_STRUCTS__==1)
5007
5008/* Reset Value for GP1CON*/
5009#define GP1CON_RVAL 0x0
5010
5011/* GP1CON[CON7] - Configuration bits for P1.7 */
5012#define GP1CON_CON7_MSK (0x3 << 14 )
5013#define GP1CON_CON7_GPIOIRQ7 (0x0 << 14 ) /* GPIOIRQ7 */
5014#define GP1CON_CON7_PWM5 (0x1 << 14 ) /* PWM5 */
5015#define GP1CON_CON7_SPI0CS (0x2 << 14 ) /* SPI0CS */
5016
5017/* GP1CON[CON6] - Configuration bits for P1.6 */
5018#define GP1CON_CON6_MSK (0x3 << 12 )
5019#define GP1CON_CON6_GPIOIRQ6 (0x0 << 12 ) /* GPIOIRQ6 */
5020#define GP1CON_CON6_PWM4 (0x1 << 12 ) /* PWM4 */
5021#define GP1CON_CON6_SPI0MOSI (0x2 << 12 ) /* SPI0MOSI */
5022
5023/* GP1CON[CON5] - Configuration bits for P1.5 */
5024#define GP1CON_CON5_MSK (0x3 << 10 )
5025#define GP1CON_CON5_GPIOIRQ5 (0x0 << 10 ) /* GPIOIRQ5 */
5026#define GP1CON_CON5_PWM3 (0x1 << 10 ) /* PWM3 */
5027#define GP1CON_CON5_SPI0SCLK (0x2 << 10 ) /* SPI0SCLK */
5028
5029/* GP1CON[CON4] - Configuration bits for P1.4 */
5030#define GP1CON_CON4_MSK (0x3 << 8 )
5031#define GP1CON_CON4_GPIO (0x0 << 8 ) /* GPIO */
5032#define GP1CON_CON4_PWM2 (0x1 << 8 ) /* PWM2 */
5033#define GP1CON_CON4_SPI0MISO (0x2 << 8 ) /* SPI0MISO */
5034
5035/* GP1CON[CON3] - Configuration bits for P1.3 */
5036#define GP1CON_CON3_MSK (0x3 << 6 )
5037#define GP1CON_CON3_GPIO (0x0 << 6 ) /* GPIO */
5038#define GP1CON_CON3_PWM1 (0x1 << 6 ) /* PWM1 */
5039
5040/* GP1CON[CON2] - Configuration bits for P1.2 */
5041#define GP1CON_CON2_MSK (0x3 << 4 )
5042#define GP1CON_CON2_GPIO (0x0 << 4 ) /* GPIO */
5043#define GP1CON_CON2_PWM0 (0x1 << 4 ) /* PWM0 */
5044
5045/* GP1CON[CON1] - Configuration bits for P1.1 */
5046#define GP1CON_CON1_MSK (0x3 << 2 )
5047#define GP1CON_CON1_GPIOIRQ4 (0x0 << 2 ) /* GPIOIRQ4 */
5048#define GP1CON_CON1_PWMTRIP (0x1 << 2 ) /* PWMTRIP */
5049
5050/* GP1CON[CON0] - Configuration bits for P1.0 */
5051#define GP1CON_CON0_MSK (0x3 << 0 )
5052#define GP1CON_CON0_GPIOIRQ3 (0x0 << 0 ) /* GPIOIRQ3 */
5053#define GP1CON_CON0_PWMSYNC (0x1 << 0 ) /* PWMSYNC */
5054#define GP1CON_CON0_EXTCLKIN (0x2 << 0 ) /* EXTCLKIN */
5055
5056/* Reset Value for GP1OEN*/
5057#define GP1OEN_RVAL 0x0
5058
5059/* GP1OEN[OEN7] - Direction for port pin */
5060#define GP1OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C069C)
5061#define GP1OEN_OEN7_MSK (0x1 << 7 )
5062#define GP1OEN_OEN7 (0x1 << 7 )
5063#define GP1OEN_OEN7_IN (0x0 << 7 ) /* IN */
5064#define GP1OEN_OEN7_OUT (0x1 << 7 ) /* OUT */
5065
5066/* GP1OEN[OEN6] - Direction for port pin */
5067#define GP1OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0698)
5068#define GP1OEN_OEN6_MSK (0x1 << 6 )
5069#define GP1OEN_OEN6 (0x1 << 6 )
5070#define GP1OEN_OEN6_IN (0x0 << 6 ) /* IN */
5071#define GP1OEN_OEN6_OUT (0x1 << 6 ) /* OUT */
5072
5073/* GP1OEN[OEN5] - Direction for port pin */
5074#define GP1OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0694)
5075#define GP1OEN_OEN5_MSK (0x1 << 5 )
5076#define GP1OEN_OEN5 (0x1 << 5 )
5077#define GP1OEN_OEN5_IN (0x0 << 5 ) /* IN */
5078#define GP1OEN_OEN5_OUT (0x1 << 5 ) /* OUT */
5079
5080/* GP1OEN[OEN4] - Direction for port pin */
5081#define GP1OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0690)
5082#define GP1OEN_OEN4_MSK (0x1 << 4 )
5083#define GP1OEN_OEN4 (0x1 << 4 )
5084#define GP1OEN_OEN4_IN (0x0 << 4 ) /* IN */
5085#define GP1OEN_OEN4_OUT (0x1 << 4 ) /* OUT */
5086
5087/* GP1OEN[OEN3] - Direction for port pin */
5088#define GP1OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C068C)
5089#define GP1OEN_OEN3_MSK (0x1 << 3 )
5090#define GP1OEN_OEN3 (0x1 << 3 )
5091#define GP1OEN_OEN3_IN (0x0 << 3 ) /* IN */
5092#define GP1OEN_OEN3_OUT (0x1 << 3 ) /* OUT */
5093
5094/* GP1OEN[OEN2] - Direction for port pin */
5095#define GP1OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0688)
5096#define GP1OEN_OEN2_MSK (0x1 << 2 )
5097#define GP1OEN_OEN2 (0x1 << 2 )
5098#define GP1OEN_OEN2_IN (0x0 << 2 ) /* IN */
5099#define GP1OEN_OEN2_OUT (0x1 << 2 ) /* OUT */
5100
5101/* GP1OEN[OEN1] - Direction for port pin */
5102#define GP1OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0684)
5103#define GP1OEN_OEN1_MSK (0x1 << 1 )
5104#define GP1OEN_OEN1 (0x1 << 1 )
5105#define GP1OEN_OEN1_IN (0x0 << 1 ) /* IN */
5106#define GP1OEN_OEN1_OUT (0x1 << 1 ) /* OUT */
5107
5108/* GP1OEN[OEN0] - Direction for port pin */
5109#define GP1OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0680)
5110#define GP1OEN_OEN0_MSK (0x1 << 0 )
5111#define GP1OEN_OEN0 (0x1 << 0 )
5112#define GP1OEN_OEN0_IN (0x0 << 0 ) /* IN */
5113#define GP1OEN_OEN0_OUT (0x1 << 0 ) /* OUT */
5114
5115/* Reset Value for GP1PUL*/
5116#define GP1PUL_RVAL 0xFF
5117
5118/* GP1PUL[PUL7] - Pull Up Enable for port pin */
5119#define GP1PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C071C)
5120#define GP1PUL_PUL7_MSK (0x1 << 7 )
5121#define GP1PUL_PUL7 (0x1 << 7 )
5122#define GP1PUL_PUL7_DIS (0x0 << 7 ) /* DIS */
5123#define GP1PUL_PUL7_EN (0x1 << 7 ) /* EN */
5124
5125/* GP1PUL[PUL6] - Pull Up Enable for port pin */
5126#define GP1PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0718)
5127#define GP1PUL_PUL6_MSK (0x1 << 6 )
5128#define GP1PUL_PUL6 (0x1 << 6 )
5129#define GP1PUL_PUL6_DIS (0x0 << 6 ) /* DIS */
5130#define GP1PUL_PUL6_EN (0x1 << 6 ) /* EN */
5131
5132/* GP1PUL[PUL5] - Pull Up Enable for port pin */
5133#define GP1PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0714)
5134#define GP1PUL_PUL5_MSK (0x1 << 5 )
5135#define GP1PUL_PUL5 (0x1 << 5 )
5136#define GP1PUL_PUL5_DIS (0x0 << 5 ) /* DIS */
5137#define GP1PUL_PUL5_EN (0x1 << 5 ) /* EN */
5138
5139/* GP1PUL[PUL4] - Pull Up Enable for port pin */
5140#define GP1PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0710)
5141#define GP1PUL_PUL4_MSK (0x1 << 4 )
5142#define GP1PUL_PUL4 (0x1 << 4 )
5143#define GP1PUL_PUL4_DIS (0x0 << 4 ) /* DIS */
5144#define GP1PUL_PUL4_EN (0x1 << 4 ) /* EN */
5145
5146/* GP1PUL[PUL3] - Pull Up Enable for port pin */
5147#define GP1PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C070C)
5148#define GP1PUL_PUL3_MSK (0x1 << 3 )
5149#define GP1PUL_PUL3 (0x1 << 3 )
5150#define GP1PUL_PUL3_DIS (0x0 << 3 ) /* DIS */
5151#define GP1PUL_PUL3_EN (0x1 << 3 ) /* EN */
5152
5153/* GP1PUL[PUL2] - Pull Up Enable for port pin */
5154#define GP1PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0708)
5155#define GP1PUL_PUL2_MSK (0x1 << 2 )
5156#define GP1PUL_PUL2 (0x1 << 2 )
5157#define GP1PUL_PUL2_DIS (0x0 << 2 ) /* DIS */
5158#define GP1PUL_PUL2_EN (0x1 << 2 ) /* EN */
5159
5160/* GP1PUL[PUL1] - Pull Up Enable for port pin */
5161#define GP1PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0704)
5162#define GP1PUL_PUL1_MSK (0x1 << 1 )
5163#define GP1PUL_PUL1 (0x1 << 1 )
5164#define GP1PUL_PUL1_DIS (0x0 << 1 ) /* DIS */
5165#define GP1PUL_PUL1_EN (0x1 << 1 ) /* EN */
5166
5167/* GP1PUL[PUL0] - Pull Up Enable for port pin */
5168#define GP1PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0700)
5169#define GP1PUL_PUL0_MSK (0x1 << 0 )
5170#define GP1PUL_PUL0 (0x1 << 0 )
5171#define GP1PUL_PUL0_DIS (0x0 << 0 ) /* DIS */
5172#define GP1PUL_PUL0_EN (0x1 << 0 ) /* EN */
5173
5174/* Reset Value for GP1OCE*/
5175#define GP1OCE_RVAL 0x0
5176
5177/* GP1OCE[OCE7] - open circuit Enable for port pin */
5178#define GP1OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C079C)
5179#define GP1OCE_OCE7_MSK (0x1 << 7 )
5180#define GP1OCE_OCE7 (0x1 << 7 )
5181#define GP1OCE_OCE7_DIS (0x0 << 7 ) /* DIS */
5182#define GP1OCE_OCE7_EN (0x1 << 7 ) /* EN */
5183
5184/* GP1OCE[OCE6] - open circuit Enable for port pin */
5185#define GP1OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0798)
5186#define GP1OCE_OCE6_MSK (0x1 << 6 )
5187#define GP1OCE_OCE6 (0x1 << 6 )
5188#define GP1OCE_OCE6_DIS (0x0 << 6 ) /* DIS */
5189#define GP1OCE_OCE6_EN (0x1 << 6 ) /* EN */
5190
5191/* GP1OCE[OCE5] - open circuit Enable for port pin */
5192#define GP1OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0794)
5193#define GP1OCE_OCE5_MSK (0x1 << 5 )
5194#define GP1OCE_OCE5 (0x1 << 5 )
5195#define GP1OCE_OCE5_DIS (0x0 << 5 ) /* DIS */
5196#define GP1OCE_OCE5_EN (0x1 << 5 ) /* EN */
5197
5198/* GP1OCE[OCE4] - open circuit Enable for port pin */
5199#define GP1OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0790)
5200#define GP1OCE_OCE4_MSK (0x1 << 4 )
5201#define GP1OCE_OCE4 (0x1 << 4 )
5202#define GP1OCE_OCE4_DIS (0x0 << 4 ) /* DIS */
5203#define GP1OCE_OCE4_EN (0x1 << 4 ) /* EN */
5204
5205/* GP1OCE[OCE3] - open circuit Enable for port pin */
5206#define GP1OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C078C)
5207#define GP1OCE_OCE3_MSK (0x1 << 3 )
5208#define GP1OCE_OCE3 (0x1 << 3 )
5209#define GP1OCE_OCE3_DIS (0x0 << 3 ) /* DIS */
5210#define GP1OCE_OCE3_EN (0x1 << 3 ) /* EN */
5211
5212/* GP1OCE[OCE2] - open circuit Enable for port pin */
5213#define GP1OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0788)
5214#define GP1OCE_OCE2_MSK (0x1 << 2 )
5215#define GP1OCE_OCE2 (0x1 << 2 )
5216#define GP1OCE_OCE2_DIS (0x0 << 2 ) /* DIS */
5217#define GP1OCE_OCE2_EN (0x1 << 2 ) /* EN */
5218
5219/* GP1OCE[OCE1] - open circuit Enable for port pin */
5220#define GP1OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0784)
5221#define GP1OCE_OCE1_MSK (0x1 << 1 )
5222#define GP1OCE_OCE1 (0x1 << 1 )
5223#define GP1OCE_OCE1_DIS (0x0 << 1 ) /* DIS */
5224#define GP1OCE_OCE1_EN (0x1 << 1 ) /* EN */
5225
5226/* GP1OCE[OCE0] - open circuit Enable for port pin */
5227#define GP1OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0780)
5228#define GP1OCE_OCE0_MSK (0x1 << 0 )
5229#define GP1OCE_OCE0 (0x1 << 0 )
5230#define GP1OCE_OCE0_DIS (0x0 << 0 ) /* DIS */
5231#define GP1OCE_OCE0_EN (0x1 << 0 ) /* EN */
5232
5233/* Reset Value for GP1IN*/
5234#define GP1IN_RVAL 0xFF
5235
5236/* GP1IN[IN7] - Input for port pin */
5237#define GP1IN_IN7_BBA (*(volatile unsigned long *) 0x420C089C)
5238#define GP1IN_IN7_MSK (0x1 << 7 )
5239#define GP1IN_IN7 (0x1 << 7 )
5240#define GP1IN_IN7_LOW (0x0 << 7 ) /* LOW */
5241#define GP1IN_IN7_HIGH (0x1 << 7 ) /* HIGH */
5242
5243/* GP1IN[IN6] - Input for port pin */
5244#define GP1IN_IN6_BBA (*(volatile unsigned long *) 0x420C0898)
5245#define GP1IN_IN6_MSK (0x1 << 6 )
5246#define GP1IN_IN6 (0x1 << 6 )
5247#define GP1IN_IN6_LOW (0x0 << 6 ) /* LOW */
5248#define GP1IN_IN6_HIGH (0x1 << 6 ) /* HIGH */
5249
5250/* GP1IN[IN5] - Input for port pin */
5251#define GP1IN_IN5_BBA (*(volatile unsigned long *) 0x420C0894)
5252#define GP1IN_IN5_MSK (0x1 << 5 )
5253#define GP1IN_IN5 (0x1 << 5 )
5254#define GP1IN_IN5_LOW (0x0 << 5 ) /* LOW */
5255#define GP1IN_IN5_HIGH (0x1 << 5 ) /* HIGH */
5256
5257/* GP1IN[IN4] - Input for port pin */
5258#define GP1IN_IN4_BBA (*(volatile unsigned long *) 0x420C0890)
5259#define GP1IN_IN4_MSK (0x1 << 4 )
5260#define GP1IN_IN4 (0x1 << 4 )
5261#define GP1IN_IN4_LOW (0x0 << 4 ) /* LOW */
5262#define GP1IN_IN4_HIGH (0x1 << 4 ) /* HIGH */
5263
5264/* GP1IN[IN3] - Input for port pin */
5265#define GP1IN_IN3_BBA (*(volatile unsigned long *) 0x420C088C)
5266#define GP1IN_IN3_MSK (0x1 << 3 )
5267#define GP1IN_IN3 (0x1 << 3 )
5268#define GP1IN_IN3_LOW (0x0 << 3 ) /* LOW */
5269#define GP1IN_IN3_HIGH (0x1 << 3 ) /* HIGH */
5270
5271/* GP1IN[IN2] - Input for port pin */
5272#define GP1IN_IN2_BBA (*(volatile unsigned long *) 0x420C0888)
5273#define GP1IN_IN2_MSK (0x1 << 2 )
5274#define GP1IN_IN2 (0x1 << 2 )
5275#define GP1IN_IN2_LOW (0x0 << 2 ) /* LOW */
5276#define GP1IN_IN2_HIGH (0x1 << 2 ) /* HIGH */
5277
5278/* GP1IN[IN1] - Input for port pin */
5279#define GP1IN_IN1_BBA (*(volatile unsigned long *) 0x420C0884)
5280#define GP1IN_IN1_MSK (0x1 << 1 )
5281#define GP1IN_IN1 (0x1 << 1 )
5282#define GP1IN_IN1_LOW (0x0 << 1 ) /* LOW */
5283#define GP1IN_IN1_HIGH (0x1 << 1 ) /* HIGH */
5284
5285/* GP1IN[IN0] - Input for port pin */
5286#define GP1IN_IN0_BBA (*(volatile unsigned long *) 0x420C0880)
5287#define GP1IN_IN0_MSK (0x1 << 0 )
5288#define GP1IN_IN0 (0x1 << 0 )
5289#define GP1IN_IN0_LOW (0x0 << 0 ) /* LOW */
5290#define GP1IN_IN0_HIGH (0x1 << 0 ) /* HIGH */
5291
5292/* Reset Value for GP1OUT*/
5293#define GP1OUT_RVAL 0x0
5294
5295/* GP1OUT[OUT7] - Output for port pin */
5296#define GP1OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C091C)
5297#define GP1OUT_OUT7_MSK (0x1 << 7 )
5298#define GP1OUT_OUT7 (0x1 << 7 )
5299#define GP1OUT_OUT7_LOW (0x0 << 7 ) /* LOW */
5300#define GP1OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH */
5301
5302/* GP1OUT[OUT6] - Output for port pin */
5303#define GP1OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0918)
5304#define GP1OUT_OUT6_MSK (0x1 << 6 )
5305#define GP1OUT_OUT6 (0x1 << 6 )
5306#define GP1OUT_OUT6_LOW (0x0 << 6 ) /* LOW */
5307#define GP1OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH */
5308
5309/* GP1OUT[OUT5] - Output for port pin */
5310#define GP1OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0914)
5311#define GP1OUT_OUT5_MSK (0x1 << 5 )
5312#define GP1OUT_OUT5 (0x1 << 5 )
5313#define GP1OUT_OUT5_LOW (0x0 << 5 ) /* LOW */
5314#define GP1OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH */
5315
5316/* GP1OUT[OUT4] - Output for port pin */
5317#define GP1OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0910)
5318#define GP1OUT_OUT4_MSK (0x1 << 4 )
5319#define GP1OUT_OUT4 (0x1 << 4 )
5320#define GP1OUT_OUT4_LOW (0x0 << 4 ) /* LOW */
5321#define GP1OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH */
5322
5323/* GP1OUT[OUT3] - Output for port pin */
5324#define GP1OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C090C)
5325#define GP1OUT_OUT3_MSK (0x1 << 3 )
5326#define GP1OUT_OUT3 (0x1 << 3 )
5327#define GP1OUT_OUT3_LOW (0x0 << 3 ) /* LOW */
5328#define GP1OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH */
5329
5330/* GP1OUT[OUT2] - Output for port pin */
5331#define GP1OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0908)
5332#define GP1OUT_OUT2_MSK (0x1 << 2 )
5333#define GP1OUT_OUT2 (0x1 << 2 )
5334#define GP1OUT_OUT2_LOW (0x0 << 2 ) /* LOW */
5335#define GP1OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH */
5336
5337/* GP1OUT[OUT1] - Output for port pin */
5338#define GP1OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0904)
5339#define GP1OUT_OUT1_MSK (0x1 << 1 )
5340#define GP1OUT_OUT1 (0x1 << 1 )
5341#define GP1OUT_OUT1_LOW (0x0 << 1 ) /* LOW */
5342#define GP1OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH */
5343
5344/* GP1OUT[OUT0] - Output for port pin */
5345#define GP1OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0900)
5346#define GP1OUT_OUT0_MSK (0x1 << 0 )
5347#define GP1OUT_OUT0 (0x1 << 0 )
5348#define GP1OUT_OUT0_LOW (0x0 << 0 ) /* LOW */
5349#define GP1OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH */
5350
5351/* Reset Value for GP1SET*/
5352#define GP1SET_RVAL 0x0
5353
5354/* GP1SET[SET7] - Set Output High for port pin */
5355#define GP1SET_SET7_BBA (*(volatile unsigned long *) 0x420C099C)
5356#define GP1SET_SET7_MSK (0x1 << 7 )
5357#define GP1SET_SET7 (0x1 << 7 )
5358#define GP1SET_SET7_SET (0x1 << 7 ) /* SET */
5359
5360/* GP1SET[SET6] - Set Output High for port pin */
5361#define GP1SET_SET6_BBA (*(volatile unsigned long *) 0x420C0998)
5362#define GP1SET_SET6_MSK (0x1 << 6 )
5363#define GP1SET_SET6 (0x1 << 6 )
5364#define GP1SET_SET6_SET (0x1 << 6 ) /* SET */
5365
5366/* GP1SET[SET5] - Set Output High for port pin */
5367#define GP1SET_SET5_BBA (*(volatile unsigned long *) 0x420C0994)
5368#define GP1SET_SET5_MSK (0x1 << 5 )
5369#define GP1SET_SET5 (0x1 << 5 )
5370#define GP1SET_SET5_SET (0x1 << 5 ) /* SET */
5371
5372/* GP1SET[SET4] - Set Output High for port pin */
5373#define GP1SET_SET4_BBA (*(volatile unsigned long *) 0x420C0990)
5374#define GP1SET_SET4_MSK (0x1 << 4 )
5375#define GP1SET_SET4 (0x1 << 4 )
5376#define GP1SET_SET4_SET (0x1 << 4 ) /* SET */
5377
5378/* GP1SET[SET3] - Set Output High for port pin */
5379#define GP1SET_SET3_BBA (*(volatile unsigned long *) 0x420C098C)
5380#define GP1SET_SET3_MSK (0x1 << 3 )
5381#define GP1SET_SET3 (0x1 << 3 )
5382#define GP1SET_SET3_SET (0x1 << 3 ) /* SET */
5383
5384/* GP1SET[SET2] - Set Output High for port pin */
5385#define GP1SET_SET2_BBA (*(volatile unsigned long *) 0x420C0988)
5386#define GP1SET_SET2_MSK (0x1 << 2 )
5387#define GP1SET_SET2 (0x1 << 2 )
5388#define GP1SET_SET2_SET (0x1 << 2 ) /* SET */
5389
5390/* GP1SET[SET1] - Set Output High for port pin */
5391#define GP1SET_SET1_BBA (*(volatile unsigned long *) 0x420C0984)
5392#define GP1SET_SET1_MSK (0x1 << 1 )
5393#define GP1SET_SET1 (0x1 << 1 )
5394#define GP1SET_SET1_SET (0x1 << 1 ) /* SET */
5395
5396/* GP1SET[SET0] - Set Output High for port pin */
5397#define GP1SET_SET0_BBA (*(volatile unsigned long *) 0x420C0980)
5398#define GP1SET_SET0_MSK (0x1 << 0 )
5399#define GP1SET_SET0 (0x1 << 0 )
5400#define GP1SET_SET0_SET (0x1 << 0 ) /* SET */
5401
5402/* Reset Value for GP1CLR*/
5403#define GP1CLR_RVAL 0x0
5404
5405/* GP1CLR[CLR7] - Set Output Low for port pin */
5406#define GP1CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C0A1C)
5407#define GP1CLR_CLR7_MSK (0x1 << 7 )
5408#define GP1CLR_CLR7 (0x1 << 7 )
5409#define GP1CLR_CLR7_CLR (0x1 << 7 ) /* CLR */
5410
5411/* GP1CLR[CLR6] - Set Output Low for port pin */
5412#define GP1CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C0A18)
5413#define GP1CLR_CLR6_MSK (0x1 << 6 )
5414#define GP1CLR_CLR6 (0x1 << 6 )
5415#define GP1CLR_CLR6_CLR (0x1 << 6 ) /* CLR */
5416
5417/* GP1CLR[CLR5] - Set Output Low for port pin */
5418#define GP1CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C0A14)
5419#define GP1CLR_CLR5_MSK (0x1 << 5 )
5420#define GP1CLR_CLR5 (0x1 << 5 )
5421#define GP1CLR_CLR5_CLR (0x1 << 5 ) /* CLR */
5422
5423/* GP1CLR[CLR4] - Set Output Low for port pin */
5424#define GP1CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C0A10)
5425#define GP1CLR_CLR4_MSK (0x1 << 4 )
5426#define GP1CLR_CLR4 (0x1 << 4 )
5427#define GP1CLR_CLR4_CLR (0x1 << 4 ) /* CLR */
5428
5429/* GP1CLR[CLR3] - Set Output Low for port pin */
5430#define GP1CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C0A0C)
5431#define GP1CLR_CLR3_MSK (0x1 << 3 )
5432#define GP1CLR_CLR3 (0x1 << 3 )
5433#define GP1CLR_CLR3_CLR (0x1 << 3 ) /* CLR */
5434
5435/* GP1CLR[CLR2] - Set Output Low for port pin */
5436#define GP1CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C0A08)
5437#define GP1CLR_CLR2_MSK (0x1 << 2 )
5438#define GP1CLR_CLR2 (0x1 << 2 )
5439#define GP1CLR_CLR2_CLR (0x1 << 2 ) /* CLR */
5440
5441/* GP1CLR[CLR1] - Set Output Low for port pin */
5442#define GP1CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C0A04)
5443#define GP1CLR_CLR1_MSK (0x1 << 1 )
5444#define GP1CLR_CLR1 (0x1 << 1 )
5445#define GP1CLR_CLR1_CLR (0x1 << 1 ) /* CLR */
5446
5447/* GP1CLR[CLR0] - Set Output Low for port pin */
5448#define GP1CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C0A00)
5449#define GP1CLR_CLR0_MSK (0x1 << 0 )
5450#define GP1CLR_CLR0 (0x1 << 0 )
5451#define GP1CLR_CLR0_CLR (0x1 << 0 ) /* CLR */
5452
5453/* Reset Value for GP1TGL*/
5454#define GP1TGL_RVAL 0x0
5455
5456/* GP1TGL[TGL7] - Toggle Output for port pin */
5457#define GP1TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C0A9C)
5458#define GP1TGL_TGL7_MSK (0x1 << 7 )
5459#define GP1TGL_TGL7 (0x1 << 7 )
5460#define GP1TGL_TGL7_TGL (0x1 << 7 ) /* TGL */
5461
5462/* GP1TGL[TGL6] - Toggle Output for port pin */
5463#define GP1TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C0A98)
5464#define GP1TGL_TGL6_MSK (0x1 << 6 )
5465#define GP1TGL_TGL6 (0x1 << 6 )
5466#define GP1TGL_TGL6_TGL (0x1 << 6 ) /* TGL */
5467
5468/* GP1TGL[TGL5] - Toggle Output for port pin */
5469#define GP1TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C0A94)
5470#define GP1TGL_TGL5_MSK (0x1 << 5 )
5471#define GP1TGL_TGL5 (0x1 << 5 )
5472#define GP1TGL_TGL5_TGL (0x1 << 5 ) /* TGL */
5473
5474/* GP1TGL[TGL4] - Toggle Output for port pin */
5475#define GP1TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C0A90)
5476#define GP1TGL_TGL4_MSK (0x1 << 4 )
5477#define GP1TGL_TGL4 (0x1 << 4 )
5478#define GP1TGL_TGL4_TGL (0x1 << 4 ) /* TGL */
5479
5480/* GP1TGL[TGL3] - Toggle Output for port pin */
5481#define GP1TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C0A8C)
5482#define GP1TGL_TGL3_MSK (0x1 << 3 )
5483#define GP1TGL_TGL3 (0x1 << 3 )
5484#define GP1TGL_TGL3_TGL (0x1 << 3 ) /* TGL */
5485
5486/* GP1TGL[TGL2] - Toggle Output for port pin */
5487#define GP1TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C0A88)
5488#define GP1TGL_TGL2_MSK (0x1 << 2 )
5489#define GP1TGL_TGL2 (0x1 << 2 )
5490#define GP1TGL_TGL2_TGL (0x1 << 2 ) /* TGL */
5491
5492/* GP1TGL[TGL1] - Toggle Output for port pin */
5493#define GP1TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C0A84)
5494#define GP1TGL_TGL1_MSK (0x1 << 1 )
5495#define GP1TGL_TGL1 (0x1 << 1 )
5496#define GP1TGL_TGL1_TGL (0x1 << 1 ) /* TGL */
5497
5498/* GP1TGL[TGL0] - Toggle Output for port pin */
5499#define GP1TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C0A80)
5500#define GP1TGL_TGL0_MSK (0x1 << 0 )
5501#define GP1TGL_TGL0 (0x1 << 0 )
5502#define GP1TGL_TGL0_TGL (0x1 << 0 ) /* TGL */
5503#if (__NO_MMR_STRUCTS__==1)
5504
5505#define GP2CON (*(volatile unsigned short int *) 0x40006060)
5506#define GP2OEN (*(volatile unsigned char *) 0x40006064)
5507#define GP2PUL (*(volatile unsigned char *) 0x40006068)
5508#define GP2OCE (*(volatile unsigned char *) 0x4000606C)
5509#define GP2IN (*(volatile unsigned char *) 0x40006074)
5510#define GP2OUT (*(volatile unsigned char *) 0x40006078)
5511#define GP2SET (*(volatile unsigned char *) 0x4000607C)
5512#define GP2CLR (*(volatile unsigned char *) 0x40006080)
5513#define GP2TGL (*(volatile unsigned char *) 0x40006084)
5514#endif // (__NO_MMR_STRUCTS__==1)
5515
5516/* Reset Value for GP2CON*/
5517#define GP2CON_RVAL 0x0
5518
5519/* GP2CON[CON4] - Configuration bits for P2.4 */
5520#define GP2CON_CON4_MSK (0x3 << 8 )
5521#define GP2CON_CON4_SWDATA (0x1 << 8 ) /* SWDATA */
5522
5523/* GP2CON[CON3] - Configuration bits for P2.3 */
5524#define GP2CON_CON3_MSK (0x3 << 6 )
5525#define GP2CON_CON3_SWCLK (0x1 << 6 ) /* SWCLK */
5526
5527/* GP2CON[CON2] - Configuration bits for P2.2 */
5528#define GP2CON_CON2_MSK (0x3 << 4 )
5529#define GP2CON_CON2_GPIO (0x0 << 4 ) /* GPIO */
5530
5531/* GP2CON[CON1] - Configuration bits for P2.1 */
5532#define GP2CON_CON1_MSK (0x3 << 2 )
5533#define GP2CON_CON1_GPIO (0x0 << 2 ) /* GPIO */
5534#define GP2CON_CON1_I2CSDA (0x1 << 2 ) /* I2CSDA */
5535
5536/* GP2CON[CON0] - Configuration bits for P2.0 */
5537#define GP2CON_CON0_MSK (0x3 << 0 )
5538#define GP2CON_CON0_GPIO (0x0 << 0 ) /* GPIO */
5539#define GP2CON_CON0_I2CSCL (0x1 << 0 ) /* I2CSCL */
5540
5541/* Reset Value for GP2OEN*/
5542#define GP2OEN_RVAL 0x0
5543
5544/* GP2OEN[OEN7] - Direction for port pin */
5545#define GP2OEN_OEN7_BBA (*(volatile unsigned long *) 0x420C0C9C)
5546#define GP2OEN_OEN7_MSK (0x1 << 7 )
5547#define GP2OEN_OEN7 (0x1 << 7 )
5548#define GP2OEN_OEN7_IN (0x0 << 7 ) /* IN */
5549#define GP2OEN_OEN7_OUT (0x1 << 7 ) /* OUT */
5550
5551/* GP2OEN[OEN6] - Direction for port pin */
5552#define GP2OEN_OEN6_BBA (*(volatile unsigned long *) 0x420C0C98)
5553#define GP2OEN_OEN6_MSK (0x1 << 6 )
5554#define GP2OEN_OEN6 (0x1 << 6 )
5555#define GP2OEN_OEN6_IN (0x0 << 6 ) /* IN */
5556#define GP2OEN_OEN6_OUT (0x1 << 6 ) /* OUT */
5557
5558/* GP2OEN[OEN5] - Direction for port pin */
5559#define GP2OEN_OEN5_BBA (*(volatile unsigned long *) 0x420C0C94)
5560#define GP2OEN_OEN5_MSK (0x1 << 5 )
5561#define GP2OEN_OEN5 (0x1 << 5 )
5562#define GP2OEN_OEN5_IN (0x0 << 5 ) /* IN */
5563#define GP2OEN_OEN5_OUT (0x1 << 5 ) /* OUT */
5564
5565/* GP2OEN[OEN4] - Direction for port pin */
5566#define GP2OEN_OEN4_BBA (*(volatile unsigned long *) 0x420C0C90)
5567#define GP2OEN_OEN4_MSK (0x1 << 4 )
5568#define GP2OEN_OEN4 (0x1 << 4 )
5569#define GP2OEN_OEN4_IN (0x0 << 4 ) /* IN */
5570#define GP2OEN_OEN4_OUT (0x1 << 4 ) /* OUT */
5571
5572/* GP2OEN[OEN3] - Direction for port pin */
5573#define GP2OEN_OEN3_BBA (*(volatile unsigned long *) 0x420C0C8C)
5574#define GP2OEN_OEN3_MSK (0x1 << 3 )
5575#define GP2OEN_OEN3 (0x1 << 3 )
5576#define GP2OEN_OEN3_IN (0x0 << 3 ) /* IN */
5577#define GP2OEN_OEN3_OUT (0x1 << 3 ) /* OUT */
5578
5579/* GP2OEN[OEN2] - Direction for port pin */
5580#define GP2OEN_OEN2_BBA (*(volatile unsigned long *) 0x420C0C88)
5581#define GP2OEN_OEN2_MSK (0x1 << 2 )
5582#define GP2OEN_OEN2 (0x1 << 2 )
5583#define GP2OEN_OEN2_IN (0x0 << 2 ) /* IN */
5584#define GP2OEN_OEN2_OUT (0x1 << 2 ) /* OUT */
5585
5586/* GP2OEN[OEN1] - Direction for port pin */
5587#define GP2OEN_OEN1_BBA (*(volatile unsigned long *) 0x420C0C84)
5588#define GP2OEN_OEN1_MSK (0x1 << 1 )
5589#define GP2OEN_OEN1 (0x1 << 1 )
5590#define GP2OEN_OEN1_IN (0x0 << 1 ) /* IN */
5591#define GP2OEN_OEN1_OUT (0x1 << 1 ) /* OUT */
5592
5593/* GP2OEN[OEN0] - Direction for port pin */
5594#define GP2OEN_OEN0_BBA (*(volatile unsigned long *) 0x420C0C80)
5595#define GP2OEN_OEN0_MSK (0x1 << 0 )
5596#define GP2OEN_OEN0 (0x1 << 0 )
5597#define GP2OEN_OEN0_IN (0x0 << 0 ) /* IN */
5598#define GP2OEN_OEN0_OUT (0x1 << 0 ) /* OUT */
5599
5600/* Reset Value for GP2PUL*/
5601#define GP2PUL_RVAL 0xFF
5602
5603/* GP2PUL[PUL7] - Pull Up Enable for port pin */
5604#define GP2PUL_PUL7_BBA (*(volatile unsigned long *) 0x420C0D1C)
5605#define GP2PUL_PUL7_MSK (0x1 << 7 )
5606#define GP2PUL_PUL7 (0x1 << 7 )
5607#define GP2PUL_PUL7_DIS (0x0 << 7 ) /* DIS */
5608#define GP2PUL_PUL7_EN (0x1 << 7 ) /* EN */
5609
5610/* GP2PUL[PUL6] - Pull Up Enable for port pin */
5611#define GP2PUL_PUL6_BBA (*(volatile unsigned long *) 0x420C0D18)
5612#define GP2PUL_PUL6_MSK (0x1 << 6 )
5613#define GP2PUL_PUL6 (0x1 << 6 )
5614#define GP2PUL_PUL6_DIS (0x0 << 6 ) /* DIS */
5615#define GP2PUL_PUL6_EN (0x1 << 6 ) /* EN */
5616
5617/* GP2PUL[PUL5] - Pull Up Enable for port pin */
5618#define GP2PUL_PUL5_BBA (*(volatile unsigned long *) 0x420C0D14)
5619#define GP2PUL_PUL5_MSK (0x1 << 5 )
5620#define GP2PUL_PUL5 (0x1 << 5 )
5621#define GP2PUL_PUL5_DIS (0x0 << 5 ) /* DIS */
5622#define GP2PUL_PUL5_EN (0x1 << 5 ) /* EN */
5623
5624/* GP2PUL[PUL4] - Pull Up Enable for port pin */
5625#define GP2PUL_PUL4_BBA (*(volatile unsigned long *) 0x420C0D10)
5626#define GP2PUL_PUL4_MSK (0x1 << 4 )
5627#define GP2PUL_PUL4 (0x1 << 4 )
5628#define GP2PUL_PUL4_DIS (0x0 << 4 ) /* DIS */
5629#define GP2PUL_PUL4_EN (0x1 << 4 ) /* EN */
5630
5631/* GP2PUL[PUL3] - Pull Up Enable for port pin */
5632#define GP2PUL_PUL3_BBA (*(volatile unsigned long *) 0x420C0D0C)
5633#define GP2PUL_PUL3_MSK (0x1 << 3 )
5634#define GP2PUL_PUL3 (0x1 << 3 )
5635#define GP2PUL_PUL3_DIS (0x0 << 3 ) /* DIS */
5636#define GP2PUL_PUL3_EN (0x1 << 3 ) /* EN */
5637
5638/* GP2PUL[PUL2] - Pull Up Enable for port pin */
5639#define GP2PUL_PUL2_BBA (*(volatile unsigned long *) 0x420C0D08)
5640#define GP2PUL_PUL2_MSK (0x1 << 2 )
5641#define GP2PUL_PUL2 (0x1 << 2 )
5642#define GP2PUL_PUL2_DIS (0x0 << 2 ) /* DIS */
5643#define GP2PUL_PUL2_EN (0x1 << 2 ) /* EN */
5644
5645/* GP2PUL[PUL1] - Pull Up Enable for port pin */
5646#define GP2PUL_PUL1_BBA (*(volatile unsigned long *) 0x420C0D04)
5647#define GP2PUL_PUL1_MSK (0x1 << 1 )
5648#define GP2PUL_PUL1 (0x1 << 1 )
5649#define GP2PUL_PUL1_DIS (0x0 << 1 ) /* DIS */
5650#define GP2PUL_PUL1_EN (0x1 << 1 ) /* EN */
5651
5652/* GP2PUL[PUL0] - Pull Up Enable for port pin */
5653#define GP2PUL_PUL0_BBA (*(volatile unsigned long *) 0x420C0D00)
5654#define GP2PUL_PUL0_MSK (0x1 << 0 )
5655#define GP2PUL_PUL0 (0x1 << 0 )
5656#define GP2PUL_PUL0_DIS (0x0 << 0 ) /* DIS */
5657#define GP2PUL_PUL0_EN (0x1 << 0 ) /* EN */
5658
5659/* Reset Value for GP2OCE*/
5660#define GP2OCE_RVAL 0x0
5661
5662/* GP2OCE[OCE7] - open circuit Enable for port pin */
5663#define GP2OCE_OCE7_BBA (*(volatile unsigned long *) 0x420C0D9C)
5664#define GP2OCE_OCE7_MSK (0x1 << 7 )
5665#define GP2OCE_OCE7 (0x1 << 7 )
5666#define GP2OCE_OCE7_DIS (0x0 << 7 ) /* DIS */
5667#define GP2OCE_OCE7_EN (0x1 << 7 ) /* EN */
5668
5669/* GP2OCE[OCE6] - open circuit Enable for port pin */
5670#define GP2OCE_OCE6_BBA (*(volatile unsigned long *) 0x420C0D98)
5671#define GP2OCE_OCE6_MSK (0x1 << 6 )
5672#define GP2OCE_OCE6 (0x1 << 6 )
5673#define GP2OCE_OCE6_DIS (0x0 << 6 ) /* DIS */
5674#define GP2OCE_OCE6_EN (0x1 << 6 ) /* EN */
5675
5676/* GP2OCE[OCE5] - open circuit Enable for port pin */
5677#define GP2OCE_OCE5_BBA (*(volatile unsigned long *) 0x420C0D94)
5678#define GP2OCE_OCE5_MSK (0x1 << 5 )
5679#define GP2OCE_OCE5 (0x1 << 5 )
5680#define GP2OCE_OCE5_DIS (0x0 << 5 ) /* DIS */
5681#define GP2OCE_OCE5_EN (0x1 << 5 ) /* EN */
5682
5683/* GP2OCE[OCE4] - open circuit Enable for port pin */
5684#define GP2OCE_OCE4_BBA (*(volatile unsigned long *) 0x420C0D90)
5685#define GP2OCE_OCE4_MSK (0x1 << 4 )
5686#define GP2OCE_OCE4 (0x1 << 4 )
5687#define GP2OCE_OCE4_DIS (0x0 << 4 ) /* DIS */
5688#define GP2OCE_OCE4_EN (0x1 << 4 ) /* EN */
5689
5690/* GP2OCE[OCE3] - open circuit Enable for port pin */
5691#define GP2OCE_OCE3_BBA (*(volatile unsigned long *) 0x420C0D8C)
5692#define GP2OCE_OCE3_MSK (0x1 << 3 )
5693#define GP2OCE_OCE3 (0x1 << 3 )
5694#define GP2OCE_OCE3_DIS (0x0 << 3 ) /* DIS */
5695#define GP2OCE_OCE3_EN (0x1 << 3 ) /* EN */
5696
5697/* GP2OCE[OCE2] - open circuit Enable for port pin */
5698#define GP2OCE_OCE2_BBA (*(volatile unsigned long *) 0x420C0D88)
5699#define GP2OCE_OCE2_MSK (0x1 << 2 )
5700#define GP2OCE_OCE2 (0x1 << 2 )
5701#define GP2OCE_OCE2_DIS (0x0 << 2 ) /* DIS */
5702#define GP2OCE_OCE2_EN (0x1 << 2 ) /* EN */
5703
5704/* GP2OCE[OCE1] - open circuit Enable for port pin */
5705#define GP2OCE_OCE1_BBA (*(volatile unsigned long *) 0x420C0D84)
5706#define GP2OCE_OCE1_MSK (0x1 << 1 )
5707#define GP2OCE_OCE1 (0x1 << 1 )
5708#define GP2OCE_OCE1_DIS (0x0 << 1 ) /* DIS */
5709#define GP2OCE_OCE1_EN (0x1 << 1 ) /* EN */
5710
5711/* GP2OCE[OCE0] - open circuit Enable for port pin */
5712#define GP2OCE_OCE0_BBA (*(volatile unsigned long *) 0x420C0D80)
5713#define GP2OCE_OCE0_MSK (0x1 << 0 )
5714#define GP2OCE_OCE0 (0x1 << 0 )
5715#define GP2OCE_OCE0_DIS (0x0 << 0 ) /* DIS */
5716#define GP2OCE_OCE0_EN (0x1 << 0 ) /* EN */
5717
5718/* Reset Value for GP2IN*/
5719#define GP2IN_RVAL 0x0
5720
5721/* GP2IN[IN7] - Input for port pin */
5722#define GP2IN_IN7_BBA (*(volatile unsigned long *) 0x420C0E9C)
5723#define GP2IN_IN7_MSK (0x1 << 7 )
5724#define GP2IN_IN7 (0x1 << 7 )
5725#define GP2IN_IN7_LOW (0x0 << 7 ) /* LOW */
5726#define GP2IN_IN7_HIGH (0x1 << 7 ) /* HIGH */
5727
5728/* GP2IN[IN6] - Input for port pin */
5729#define GP2IN_IN6_BBA (*(volatile unsigned long *) 0x420C0E98)
5730#define GP2IN_IN6_MSK (0x1 << 6 )
5731#define GP2IN_IN6 (0x1 << 6 )
5732#define GP2IN_IN6_LOW (0x0 << 6 ) /* LOW */
5733#define GP2IN_IN6_HIGH (0x1 << 6 ) /* HIGH */
5734
5735/* GP2IN[IN5] - Input for port pin */
5736#define GP2IN_IN5_BBA (*(volatile unsigned long *) 0x420C0E94)
5737#define GP2IN_IN5_MSK (0x1 << 5 )
5738#define GP2IN_IN5 (0x1 << 5 )
5739#define GP2IN_IN5_LOW (0x0 << 5 ) /* LOW */
5740#define GP2IN_IN5_HIGH (0x1 << 5 ) /* HIGH */
5741
5742/* GP2IN[IN4] - Input for port pin */
5743#define GP2IN_IN4_BBA (*(volatile unsigned long *) 0x420C0E90)
5744#define GP2IN_IN4_MSK (0x1 << 4 )
5745#define GP2IN_IN4 (0x1 << 4 )
5746#define GP2IN_IN4_LOW (0x0 << 4 ) /* LOW */
5747#define GP2IN_IN4_HIGH (0x1 << 4 ) /* HIGH */
5748
5749/* GP2IN[IN3] - Input for port pin */
5750#define GP2IN_IN3_BBA (*(volatile unsigned long *) 0x420C0E8C)
5751#define GP2IN_IN3_MSK (0x1 << 3 )
5752#define GP2IN_IN3 (0x1 << 3 )
5753#define GP2IN_IN3_LOW (0x0 << 3 ) /* LOW */
5754#define GP2IN_IN3_HIGH (0x1 << 3 ) /* HIGH */
5755
5756/* GP2IN[IN2] - Input for port pin */
5757#define GP2IN_IN2_BBA (*(volatile unsigned long *) 0x420C0E88)
5758#define GP2IN_IN2_MSK (0x1 << 2 )
5759#define GP2IN_IN2 (0x1 << 2 )
5760#define GP2IN_IN2_LOW (0x0 << 2 ) /* LOW */
5761#define GP2IN_IN2_HIGH (0x1 << 2 ) /* HIGH */
5762
5763/* GP2IN[IN1] - Input for port pin */
5764#define GP2IN_IN1_BBA (*(volatile unsigned long *) 0x420C0E84)
5765#define GP2IN_IN1_MSK (0x1 << 1 )
5766#define GP2IN_IN1 (0x1 << 1 )
5767#define GP2IN_IN1_LOW (0x0 << 1 ) /* LOW */
5768#define GP2IN_IN1_HIGH (0x1 << 1 ) /* HIGH */
5769
5770/* GP2IN[IN0] - Input for port pin */
5771#define GP2IN_IN0_BBA (*(volatile unsigned long *) 0x420C0E80)
5772#define GP2IN_IN0_MSK (0x1 << 0 )
5773#define GP2IN_IN0 (0x1 << 0 )
5774#define GP2IN_IN0_LOW (0x0 << 0 ) /* LOW */
5775#define GP2IN_IN0_HIGH (0x1 << 0 ) /* HIGH */
5776
5777/* Reset Value for GP2OUT*/
5778#define GP2OUT_RVAL 0x0
5779
5780/* GP2OUT[OUT7] - Output for port pin */
5781#define GP2OUT_OUT7_BBA (*(volatile unsigned long *) 0x420C0F1C)
5782#define GP2OUT_OUT7_MSK (0x1 << 7 )
5783#define GP2OUT_OUT7 (0x1 << 7 )
5784#define GP2OUT_OUT7_LOW (0x0 << 7 ) /* LOW */
5785#define GP2OUT_OUT7_HIGH (0x1 << 7 ) /* HIGH */
5786
5787/* GP2OUT[OUT6] - Output for port pin */
5788#define GP2OUT_OUT6_BBA (*(volatile unsigned long *) 0x420C0F18)
5789#define GP2OUT_OUT6_MSK (0x1 << 6 )
5790#define GP2OUT_OUT6 (0x1 << 6 )
5791#define GP2OUT_OUT6_LOW (0x0 << 6 ) /* LOW */
5792#define GP2OUT_OUT6_HIGH (0x1 << 6 ) /* HIGH */
5793
5794/* GP2OUT[OUT5] - Output for port pin */
5795#define GP2OUT_OUT5_BBA (*(volatile unsigned long *) 0x420C0F14)
5796#define GP2OUT_OUT5_MSK (0x1 << 5 )
5797#define GP2OUT_OUT5 (0x1 << 5 )
5798#define GP2OUT_OUT5_LOW (0x0 << 5 ) /* LOW */
5799#define GP2OUT_OUT5_HIGH (0x1 << 5 ) /* HIGH */
5800
5801/* GP2OUT[OUT4] - Output for port pin */
5802#define GP2OUT_OUT4_BBA (*(volatile unsigned long *) 0x420C0F10)
5803#define GP2OUT_OUT4_MSK (0x1 << 4 )
5804#define GP2OUT_OUT4 (0x1 << 4 )
5805#define GP2OUT_OUT4_LOW (0x0 << 4 ) /* LOW */
5806#define GP2OUT_OUT4_HIGH (0x1 << 4 ) /* HIGH */
5807
5808/* GP2OUT[OUT3] - Output for port pin */
5809#define GP2OUT_OUT3_BBA (*(volatile unsigned long *) 0x420C0F0C)
5810#define GP2OUT_OUT3_MSK (0x1 << 3 )
5811#define GP2OUT_OUT3 (0x1 << 3 )
5812#define GP2OUT_OUT3_LOW (0x0 << 3 ) /* LOW */
5813#define GP2OUT_OUT3_HIGH (0x1 << 3 ) /* HIGH */
5814
5815/* GP2OUT[OUT2] - Output for port pin */
5816#define GP2OUT_OUT2_BBA (*(volatile unsigned long *) 0x420C0F08)
5817#define GP2OUT_OUT2_MSK (0x1 << 2 )
5818#define GP2OUT_OUT2 (0x1 << 2 )
5819#define GP2OUT_OUT2_LOW (0x0 << 2 ) /* LOW */
5820#define GP2OUT_OUT2_HIGH (0x1 << 2 ) /* HIGH */
5821
5822/* GP2OUT[OUT1] - Output for port pin */
5823#define GP2OUT_OUT1_BBA (*(volatile unsigned long *) 0x420C0F04)
5824#define GP2OUT_OUT1_MSK (0x1 << 1 )
5825#define GP2OUT_OUT1 (0x1 << 1 )
5826#define GP2OUT_OUT1_LOW (0x0 << 1 ) /* LOW */
5827#define GP2OUT_OUT1_HIGH (0x1 << 1 ) /* HIGH */
5828
5829/* GP2OUT[OUT0] - Output for port pin */
5830#define GP2OUT_OUT0_BBA (*(volatile unsigned long *) 0x420C0F00)
5831#define GP2OUT_OUT0_MSK (0x1 << 0 )
5832#define GP2OUT_OUT0 (0x1 << 0 )
5833#define GP2OUT_OUT0_LOW (0x0 << 0 ) /* LOW */
5834#define GP2OUT_OUT0_HIGH (0x1 << 0 ) /* HIGH */
5835
5836/* Reset Value for GP2SET*/
5837#define GP2SET_RVAL 0x0
5838
5839/* GP2SET[SET7] - Set Output High for port pin */
5840#define GP2SET_SET7_BBA (*(volatile unsigned long *) 0x420C0F9C)
5841#define GP2SET_SET7_MSK (0x1 << 7 )
5842#define GP2SET_SET7 (0x1 << 7 )
5843#define GP2SET_SET7_SET (0x1 << 7 ) /* SET */
5844
5845/* GP2SET[SET6] - Set Output High for port pin */
5846#define GP2SET_SET6_BBA (*(volatile unsigned long *) 0x420C0F98)
5847#define GP2SET_SET6_MSK (0x1 << 6 )
5848#define GP2SET_SET6 (0x1 << 6 )
5849#define GP2SET_SET6_SET (0x1 << 6 ) /* SET */
5850
5851/* GP2SET[SET5] - Set Output High for port pin */
5852#define GP2SET_SET5_BBA (*(volatile unsigned long *) 0x420C0F94)
5853#define GP2SET_SET5_MSK (0x1 << 5 )
5854#define GP2SET_SET5 (0x1 << 5 )
5855#define GP2SET_SET5_SET (0x1 << 5 ) /* SET */
5856
5857/* GP2SET[SET4] - Set Output High for port pin */
5858#define GP2SET_SET4_BBA (*(volatile unsigned long *) 0x420C0F90)
5859#define GP2SET_SET4_MSK (0x1 << 4 )
5860#define GP2SET_SET4 (0x1 << 4 )
5861#define GP2SET_SET4_SET (0x1 << 4 ) /* SET */
5862
5863/* GP2SET[SET3] - Set Output High for port pin */
5864#define GP2SET_SET3_BBA (*(volatile unsigned long *) 0x420C0F8C)
5865#define GP2SET_SET3_MSK (0x1 << 3 )
5866#define GP2SET_SET3 (0x1 << 3 )
5867#define GP2SET_SET3_SET (0x1 << 3 ) /* SET */
5868
5869/* GP2SET[SET2] - Set Output High for port pin */
5870#define GP2SET_SET2_BBA (*(volatile unsigned long *) 0x420C0F88)
5871#define GP2SET_SET2_MSK (0x1 << 2 )
5872#define GP2SET_SET2 (0x1 << 2 )
5873#define GP2SET_SET2_SET (0x1 << 2 ) /* SET */
5874
5875/* GP2SET[SET1] - Set Output High for port pin */
5876#define GP2SET_SET1_BBA (*(volatile unsigned long *) 0x420C0F84)
5877#define GP2SET_SET1_MSK (0x1 << 1 )
5878#define GP2SET_SET1 (0x1 << 1 )
5879#define GP2SET_SET1_SET (0x1 << 1 ) /* SET */
5880
5881/* GP2SET[SET0] - Set Output High for port pin */
5882#define GP2SET_SET0_BBA (*(volatile unsigned long *) 0x420C0F80)
5883#define GP2SET_SET0_MSK (0x1 << 0 )
5884#define GP2SET_SET0 (0x1 << 0 )
5885#define GP2SET_SET0_SET (0x1 << 0 ) /* SET */
5886
5887/* Reset Value for GP2CLR*/
5888#define GP2CLR_RVAL 0x0
5889
5890/* GP2CLR[CLR7] - Set Output Low for port pin */
5891#define GP2CLR_CLR7_BBA (*(volatile unsigned long *) 0x420C101C)
5892#define GP2CLR_CLR7_MSK (0x1 << 7 )
5893#define GP2CLR_CLR7 (0x1 << 7 )
5894#define GP2CLR_CLR7_CLR (0x1 << 7 ) /* CLR */
5895
5896/* GP2CLR[CLR6] - Set Output Low for port pin */
5897#define GP2CLR_CLR6_BBA (*(volatile unsigned long *) 0x420C1018)
5898#define GP2CLR_CLR6_MSK (0x1 << 6 )
5899#define GP2CLR_CLR6 (0x1 << 6 )
5900#define GP2CLR_CLR6_CLR (0x1 << 6 ) /* CLR */
5901
5902/* GP2CLR[CLR5] - Set Output Low for port pin */
5903#define GP2CLR_CLR5_BBA (*(volatile unsigned long *) 0x420C1014)
5904#define GP2CLR_CLR5_MSK (0x1 << 5 )
5905#define GP2CLR_CLR5 (0x1 << 5 )
5906#define GP2CLR_CLR5_CLR (0x1 << 5 ) /* CLR */
5907
5908/* GP2CLR[CLR4] - Set Output Low for port pin */
5909#define GP2CLR_CLR4_BBA (*(volatile unsigned long *) 0x420C1010)
5910#define GP2CLR_CLR4_MSK (0x1 << 4 )
5911#define GP2CLR_CLR4 (0x1 << 4 )
5912#define GP2CLR_CLR4_CLR (0x1 << 4 ) /* CLR */
5913
5914/* GP2CLR[CLR3] - Set Output Low for port pin */
5915#define GP2CLR_CLR3_BBA (*(volatile unsigned long *) 0x420C100C)
5916#define GP2CLR_CLR3_MSK (0x1 << 3 )
5917#define GP2CLR_CLR3 (0x1 << 3 )
5918#define GP2CLR_CLR3_CLR (0x1 << 3 ) /* CLR */
5919
5920/* GP2CLR[CLR2] - Set Output Low for port pin */
5921#define GP2CLR_CLR2_BBA (*(volatile unsigned long *) 0x420C1008)
5922#define GP2CLR_CLR2_MSK (0x1 << 2 )
5923#define GP2CLR_CLR2 (0x1 << 2 )
5924#define GP2CLR_CLR2_CLR (0x1 << 2 ) /* CLR */
5925
5926/* GP2CLR[CLR1] - Set Output Low for port pin */
5927#define GP2CLR_CLR1_BBA (*(volatile unsigned long *) 0x420C1004)
5928#define GP2CLR_CLR1_MSK (0x1 << 1 )
5929#define GP2CLR_CLR1 (0x1 << 1 )
5930#define GP2CLR_CLR1_CLR (0x1 << 1 ) /* CLR */
5931
5932/* GP2CLR[CLR0] - Set Output Low for port pin */
5933#define GP2CLR_CLR0_BBA (*(volatile unsigned long *) 0x420C1000)
5934#define GP2CLR_CLR0_MSK (0x1 << 0 )
5935#define GP2CLR_CLR0 (0x1 << 0 )
5936#define GP2CLR_CLR0_CLR (0x1 << 0 ) /* CLR */
5937
5938/* Reset Value for GP2TGL*/
5939#define GP2TGL_RVAL 0x0
5940
5941/* GP2TGL[TGL7] - Toggle Output for port pin */
5942#define GP2TGL_TGL7_BBA (*(volatile unsigned long *) 0x420C109C)
5943#define GP2TGL_TGL7_MSK (0x1 << 7 )
5944#define GP2TGL_TGL7 (0x1 << 7 )
5945#define GP2TGL_TGL7_TGL (0x1 << 7 ) /* TGL */
5946
5947/* GP2TGL[TGL6] - Toggle Output for port pin */
5948#define GP2TGL_TGL6_BBA (*(volatile unsigned long *) 0x420C1098)
5949#define GP2TGL_TGL6_MSK (0x1 << 6 )
5950#define GP2TGL_TGL6 (0x1 << 6 )
5951#define GP2TGL_TGL6_TGL (0x1 << 6 ) /* TGL */
5952
5953/* GP2TGL[TGL5] - Toggle Output for port pin */
5954#define GP2TGL_TGL5_BBA (*(volatile unsigned long *) 0x420C1094)
5955#define GP2TGL_TGL5_MSK (0x1 << 5 )
5956#define GP2TGL_TGL5 (0x1 << 5 )
5957#define GP2TGL_TGL5_TGL (0x1 << 5 ) /* TGL */
5958
5959/* GP2TGL[TGL4] - Toggle Output for port pin */
5960#define GP2TGL_TGL4_BBA (*(volatile unsigned long *) 0x420C1090)
5961#define GP2TGL_TGL4_MSK (0x1 << 4 )
5962#define GP2TGL_TGL4 (0x1 << 4 )
5963#define GP2TGL_TGL4_TGL (0x1 << 4 ) /* TGL */
5964
5965/* GP2TGL[TGL3] - Toggle Output for port pin */
5966#define GP2TGL_TGL3_BBA (*(volatile unsigned long *) 0x420C108C)
5967#define GP2TGL_TGL3_MSK (0x1 << 3 )
5968#define GP2TGL_TGL3 (0x1 << 3 )
5969#define GP2TGL_TGL3_TGL (0x1 << 3 ) /* TGL */
5970
5971/* GP2TGL[TGL2] - Toggle Output for port pin */
5972#define GP2TGL_TGL2_BBA (*(volatile unsigned long *) 0x420C1088)
5973#define GP2TGL_TGL2_MSK (0x1 << 2 )
5974#define GP2TGL_TGL2 (0x1 << 2 )
5975#define GP2TGL_TGL2_TGL (0x1 << 2 ) /* TGL */
5976
5977/* GP2TGL[TGL1] - Toggle Output for port pin */
5978#define GP2TGL_TGL1_BBA (*(volatile unsigned long *) 0x420C1084)
5979#define GP2TGL_TGL1_MSK (0x1 << 1 )
5980#define GP2TGL_TGL1 (0x1 << 1 )
5981#define GP2TGL_TGL1_TGL (0x1 << 1 ) /* TGL */
5982
5983/* GP2TGL[TGL0] - Toggle Output for port pin */
5984#define GP2TGL_TGL0_BBA (*(volatile unsigned long *) 0x420C1080)
5985#define GP2TGL_TGL0_MSK (0x1 << 0 )
5986#define GP2TGL_TGL0 (0x1 << 0 )
5987#define GP2TGL_TGL0_TGL (0x1 << 0 ) /* TGL */
5988// ------------------------------------------------------------------------------------------------
5989// ----- ANA -----
5990// ------------------------------------------------------------------------------------------------
5991
5992
5993/**
5994 * @brief Analog Control (pADI_ANA)
5995 */
5996
5997#if (__NO_MMR_STRUCTS__==0)
5998typedef struct { /*!< pADI_ANA Structure */
5999 __I uint32_t RESERVED0[12];
6000 __IO uint16_t REFCTRL; /*!< Internal Reference Control register */
6001 __I uint16_t RESERVED1[7];
6002 __IO uint8_t IEXCCON; /*!< Controls the on-chip Excitation Current Sources */
6003 __I uint8_t RESERVED2[3];
6004 __IO uint8_t IEXCDAT; /*!< Sets the output current setting for both Excitation Current sources */
6005} ADI_ANA_TypeDef;
6006#else // (__NO_MMR_STRUCTS__==0)
6007#define REFCTRL (*(volatile unsigned short int *) 0x40008840)
6008#define IEXCCON (*(volatile unsigned char *) 0x40008850)
6009#define IEXCDAT (*(volatile unsigned char *) 0x40008854)
6010#endif // (__NO_MMR_STRUCTS__==0)
6011
6012/* Reset Value for REFCTRL*/
6013#define REFCTRL_RVAL 0x0
6014
6015/* REFCTRL[REFPD] - Power down reference */
6016#define REFCTRL_REFPD_BBA (*(volatile unsigned long *) 0x42110800)
6017#define REFCTRL_REFPD_MSK (0x1 << 0 )
6018#define REFCTRL_REFPD (0x1 << 0 )
6019#define REFCTRL_REFPD_DIS (0x0 << 0 ) /* DIS */
6020#define REFCTRL_REFPD_EN (0x1 << 0 ) /* EN */
6021
6022/* Reset Value for IEXCCON*/
6023#define IEXCCON_RVAL 0xC0
6024
6025/* IEXCCON[PD] - IEXC Power down- bits */
6026#define IEXCCON_PD_BBA (*(volatile unsigned long *) 0x42110A1C)
6027#define IEXCCON_PD_MSK (0x1 << 7 )
6028#define IEXCCON_PD (0x1 << 7 )
6029#define IEXCCON_PD_En (0x1 << 7 ) /* En */
6030#define IEXCCON_PD_off (0x0 << 7 ) /* off */
6031
6032/* IEXCCON[REFSEL] - IREF Source- bits */
6033#define IEXCCON_REFSEL_BBA (*(volatile unsigned long *) 0x42110A18)
6034#define IEXCCON_REFSEL_MSK (0x1 << 6 )
6035#define IEXCCON_REFSEL (0x1 << 6 )
6036#define IEXCCON_REFSEL_Ext (0x0 << 6 ) /* Ext */
6037#define IEXCCON_REFSEL_Int (0x1 << 6 ) /* Int */
6038
6039/* IEXCCON[IPSEL1] - Select IEXC1 pin AIN- bits */
6040#define IEXCCON_IPSEL1_MSK (0x7 << 3 )
6041#define IEXCCON_IPSEL1_Off (0x0 << 3 ) /* Off */
6042#define IEXCCON_IPSEL1_AIN4 (0x4 << 3 ) /* AIN4 */
6043#define IEXCCON_IPSEL1_AIN5 (0x5 << 3 ) /* AIN5 */
6044#define IEXCCON_IPSEL1_AIN6 (0x6 << 3 ) /* AIN6 */
6045#define IEXCCON_IPSEL1_AIN7 (0x7 << 3 ) /* AIN7 */
6046
6047/* IEXCCON[IPSEL0] - Select IEXC0 pin AIN- bits */
6048#define IEXCCON_IPSEL0_MSK (0x7 << 0 )
6049#define IEXCCON_IPSEL0_Off (0x0 << 0 ) /* Off */
6050#define IEXCCON_IPSEL0_AIN4 (0x4 << 0 ) /* AIN4 */
6051#define IEXCCON_IPSEL0_AIN5 (0x5 << 0 ) /* AIN5 */
6052#define IEXCCON_IPSEL0_AIN6 (0x6 << 0 ) /* AIN6 */
6053#define IEXCCON_IPSEL0_AIN7 (0x7 << 0 ) /* AIN7 */
6054
6055/* Reset Value for IEXCDAT*/
6056#define IEXCDAT_RVAL 0x6
6057
6058/* IEXCDAT[IDAT] - Output Current- bits */
6059#define IEXCDAT_IDAT_MSK (0x1F << 1 )
6060#define IEXCDAT_IDAT_0uA (0x0 << 1 ) /* 0uA */
6061#define IEXCDAT_IDAT_50uA (0x4 << 1 ) /* 50uA */
6062#define IEXCDAT_IDAT_100uA (0x5 << 1 ) /* 100uA */
6063#define IEXCDAT_IDAT_150uA (0x6 << 1 ) /* 150uA */
6064#define IEXCDAT_IDAT_200uA (0x7 << 1 ) /* 200uA */
6065#define IEXCDAT_IDAT_250uA (0x14 << 1 ) /* 250uA */
6066#define IEXCDAT_IDAT_300uA (0xA << 1 ) /* 300uA */
6067#define IEXCDAT_IDAT_400uA (0xB << 1 ) /* 400uA */
6068#define IEXCDAT_IDAT_450uA (0xE << 1 ) /* 450uA */
6069#define IEXCDAT_IDAT_500uA (0x15 << 1 ) /* 500uA */
6070#define IEXCDAT_IDAT_600uA (0xF << 1 ) /* 600uA */
6071#define IEXCDAT_IDAT_750uA (0x16 << 1 ) /* 750uA */
6072#define IEXCDAT_IDAT_800uA (0x13 << 1 ) /* 800uA */
6073#define IEXCDAT_IDAT_1mA (0x1F << 1 ) /* 1mA */
6074
6075/* IEXCDAT[IDAT0] - 10uA Enable */
6076#define IEXCDAT_IDAT0_BBA (*(volatile unsigned long *) 0x42110A80)
6077#define IEXCDAT_IDAT0_MSK (0x1 << 0 )
6078#define IEXCDAT_IDAT0 (0x1 << 0 )
6079#define IEXCDAT_IDAT0_DIS (0x0 << 0 ) /* DIS */
6080#define IEXCDAT_IDAT0_EN (0x1 << 0 ) /* EN */
6081// ------------------------------------------------------------------------------------------------
6082// ----- DMA -----
6083// ------------------------------------------------------------------------------------------------
6084
6085
6086/**
6087 * @brief Direct Memory Access (pADI_DMA)
6088 */
6089
6090#if (__NO_MMR_STRUCTS__==0)
6091typedef struct { /*!< pADI_DMA Structure */
6092 __IO uint32_t DMASTA; /*!< Returns the status of the controller when not in the reset state. */
6093 __IO uint32_t DMACFG; /*!< Configuraton */
6094 __IO uint32_t DMAPDBPTR; /*!< Channel primary control database pointer */
6095 __IO uint32_t DMAADBPTR; /*!< Channel alt control database pointer */
6096 __I uint32_t RESERVED0;
6097 __IO uint32_t DMASWREQ; /*!< Channel Software Request */
6098 __I uint32_t RESERVED1[2];
6099 __IO uint32_t DMARMSKSET; /*!< Channel Request Mask Set */
6100 __IO uint32_t DMARMSKCLR; /*!< Channel Request Mask Clear */
6101 __IO uint32_t DMAENSET; /*!< Channel Enable Set */
6102 __IO uint32_t DMAENCLR; /*!< Channel Enable Clear */
6103 __IO uint32_t DMAALTSET; /*!< Channel Primary-Alternate Set */
6104 __IO uint32_t DMAALTCLR; /*!< Channel Primary-Alternate Clear */
6105 __IO uint32_t DMAPRISET; /*!< Channel Priority Set */
6106 __IO uint32_t DMAPRICLR; /*!< Channel Priority Clear */
6107 __I uint32_t RESERVED2[3];
6108 __IO uint32_t DMAERRCLR; /*!< Bus Error Clear */
6109 __I uint32_t RESERVED3[492];
6110 __IO uint32_t DMABSSET; /*!< DMA channel bytes swap enable set */
6111 __IO uint32_t DMABSCLR; /*!< DMA channel bytes swap enable clear */
6112 __I uint32_t RESERVED4[66];
6113 __IO uint32_t DMAGETNMINUS1; /*!< Request n_minus_1 register update */
6114 __IO uint32_t DMANMINUS1; /*!< Current n_minus_1 value */
6115} ADI_DMA_TypeDef;
6116#else // (__NO_MMR_STRUCTS__==0)
6117#define DMASTA (*(volatile unsigned long *) 0x40010000)
6118#define DMACFG (*(volatile unsigned long *) 0x40010004)
6119#define DMAPDBPTR (*(volatile unsigned long *) 0x40010008)
6120#define DMAADBPTR (*(volatile unsigned long *) 0x4001000C)
6121#define DMASWREQ (*(volatile unsigned long *) 0x40010014)
6122#define DMARMSKSET (*(volatile unsigned long *) 0x40010020)
6123#define DMARMSKCLR (*(volatile unsigned long *) 0x40010024)
6124#define DMAENSET (*(volatile unsigned long *) 0x40010028)
6125#define DMAENCLR (*(volatile unsigned long *) 0x4001002C)
6126#define DMAALTSET (*(volatile unsigned long *) 0x40010030)
6127#define DMAALTCLR (*(volatile unsigned long *) 0x40010034)
6128#define DMAPRISET (*(volatile unsigned long *) 0x40010038)
6129#define DMAPRICLR (*(volatile unsigned long *) 0x4001003C)
6130#define DMAERRCLR (*(volatile unsigned long *) 0x4001004C)
6131#define DMABSSET (*(volatile unsigned long *) 0x40010800)
6132#define DMABSCLR (*(volatile unsigned long *) 0x40010804)
6133#define DMAGETNMINUS1 (*(volatile unsigned long *) 0x40010910)
6134#define DMANMINUS1 (*(volatile unsigned long *) 0x40010914)
6135#endif // (__NO_MMR_STRUCTS__==0)
6136
6137/* Reset Value for DMASTA*/
6138#define DMASTA_RVAL 0xB0000
6139
6140/* DMASTA[CHNLSMINUS1] - Number of available DMA channels minus one. */
6141#define DMASTA_CHNLSMINUS1_MSK (0x1F << 16 )
6142#define DMASTA_CHNLSMINUS1_FOURTEENCHNLS (0xD << 16 ) /* FOURTEENCHNLS - Controller configured to use 14 DMA channels */
6143#define DMASTA_CHNLSMINUS1_TWELVECHNLS (0xB << 16 ) /* TWELVECHNLS - Controller configured to use 12 DMA channels */
6144
6145/* DMASTA[STATE] - Current state of the control state machine. */
6146#define DMASTA_STATE_MSK (0xF << 4 )
6147#define DMASTA_STATE_IDLE (0x0 << 4 ) /* IDLE - Idle */
6148#define DMASTA_STATE_RDCHNLDATA (0x1 << 4 ) /* RDCHNLDATA - Reading channel controller data */
6149#define DMASTA_STATE_RDSRCENDPTR (0x2 << 4 ) /* RDSRCENDPTR - Reading source data end pointer */
6150#define DMASTA_STATE_RDDSTENDPTR (0x3 << 4 ) /* RDDSTENDPTR - Reading destination data end pointer */
6151#define DMASTA_STATE_RDSRCDATA (0x4 << 4 ) /* RDSRCDATA - Reading source data */
6152#define DMASTA_STATE_WRDSTDATA (0x5 << 4 ) /* WRDSTDATA - Writing destination data */
6153#define DMASTA_STATE_WAITDMAREQCLR (0x6 << 4 ) /* WAITDMAREQCLR - Waiting for DMA request to clear */
6154#define DMASTA_STATE_WRCHNLDATA (0x7 << 4 ) /* WRCHNLDATA - Writing channel controller data */
6155#define DMASTA_STATE_STALLED (0x8 << 4 ) /* STALLED - Stalled */
6156#define DMASTA_STATE_DONE (0x9 << 4 ) /* DONE - Done */
6157#define DMASTA_STATE_SCATRGATHR (0xA << 4 ) /* SCATRGATHR - Peripheral scatter-gather transition */
6158
6159/* DMASTA[ENABLE] - Master DMA controller enable status. */
6160#define DMASTA_ENABLE_BBA (*(volatile unsigned long *) 0x42200000)
6161#define DMASTA_ENABLE_MSK (0x1 << 0 )
6162#define DMASTA_ENABLE (0x1 << 0 )
6163#define DMASTA_ENABLE_CLR (0x0 << 0 ) /* CLR */
6164#define DMASTA_ENABLE_SET (0x1 << 0 ) /* SET */
6165
6166/* Reset Value for DMACFG*/
6167#define DMACFG_RVAL 0x0
6168
6169/* DMACFG[ENABLE] - Master DMA controller enable */
6170#define DMACFG_ENABLE_BBA (*(volatile unsigned long *) 0x42200080)
6171#define DMACFG_ENABLE_MSK (0x1 << 0 )
6172#define DMACFG_ENABLE (0x1 << 0 )
6173#define DMACFG_ENABLE_DIS (0x0 << 0 ) /* DIS */
6174#define DMACFG_ENABLE_EN (0x1 << 0 ) /* EN */
6175
6176/* Reset Value for DMAPDBPTR*/
6177#define DMAPDBPTR_RVAL 0x0
6178
6179/* DMAPDBPTR[CTRLBASEPTR] - Pointer to the base address of the primary data structure */
6180#define DMAPDBPTR_CTRLBASEPTR_MSK (0xFFFFFFFF << 0 )
6181
6182/* Reset Value for DMAADBPTR*/
6183#define DMAADBPTR_RVAL 0x100
6184
6185/* DMAADBPTR[ALTCBPTR] - Pointer to the base address of the alternate data structure */
6186#define DMAADBPTR_ALTCBPTR_MSK (0xFFFFFFFF << 0 )
6187
6188/* Reset Value for DMASWREQ*/
6189#define DMASWREQ_RVAL 0x0
6190/* DMASWREQ[UART1RX] - DMA UART1 RX */
6191#define DMASWREQ_UART1RX_BBA (*(volatile unsigned long *) 0x422002BC)
6192#define DMASWREQ_UART1RX_MSK (0x1 << 15 )
6193#define DMASWREQ_UART1RX (0x1 << 15 )
6194#define DMASWREQ_UART1RX_DIS (0x0 << 15 ) /* DIS */
6195#define DMASWREQ_UART1RX_EN (0x1 << 15 ) /* EN */
6196/* DMASWREQ[UART1TX] - DMA UART1 TX */
6197#define DMASWREQ_UART1TX_BBA (*(volatile unsigned long *) 0x422002B8)
6198#define DMASWREQ_UART1TX_MSK (0x1 << 14 )
6199#define DMASWREQ_UART1TX (0x1 << 14 )
6200#define DMASWREQ_UART1TX_DIS (0x0 << 14 ) /* DIS */
6201#define DMASWREQ_UART1TX_EN (0x1 << 14 ) /* EN */
6202/* DMASWREQ[SPI0RX] - DMA SPI 0 RX */
6203#define DMASWREQ_SPI0RX_BBA (*(volatile unsigned long *) 0x422002B4)
6204#define DMASWREQ_SPI0RX_MSK (0x1 << 13 )
6205#define DMASWREQ_SPI0RX (0x1 << 13 )
6206#define DMASWREQ_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6207#define DMASWREQ_SPI0RX_EN (0x1 << 13 ) /* EN */
6208/* DMASWREQ[SPI0TX] - DMA SPI 0 TX */
6209#define DMASWREQ_SPI0TX_BBA (*(volatile unsigned long *) 0x422002B0)
6210#define DMASWREQ_SPI0TX_MSK (0x1 << 12 )
6211#define DMASWREQ_SPI0TX (0x1 << 12 )
6212#define DMASWREQ_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6213#define DMASWREQ_SPI0TX_EN (0x1 << 12 ) /* EN */
6214/* DMASWREQ[SINC2] - SINC2 Output Step detection */
6215#define DMASWREQ_SINC2_BBA (*(volatile unsigned long *) 0x422002AC)
6216#define DMASWREQ_SINC2_MSK (0x1 << 11 )
6217#define DMASWREQ_SINC2 (0x1 << 11 )
6218#define DMASWREQ_SINC2_DIS (0x0 << 11 ) /* DIS */
6219#define DMASWREQ_SINC2_EN (0x1 << 11 ) /* EN */
6220
6221/* DMASWREQ[ADC1] - ADC1 */
6222#define DMASWREQ_ADC1_BBA (*(volatile unsigned long *) 0x422002A8)
6223#define DMASWREQ_ADC1_MSK (0x1 << 10 )
6224#define DMASWREQ_ADC1 (0x1 << 10 )
6225#define DMASWREQ_ADC1_DIS (0x0 << 10 ) /* DIS */
6226#define DMASWREQ_ADC1_EN (0x1 << 10 ) /* EN */
6227
6228/* DMASWREQ[DAC] - DAC DMA Output */
6229#define DMASWREQ_DAC_BBA (*(volatile unsigned long *) 0x422002A0)
6230#define DMASWREQ_DAC_MSK (0x1 << 8 )
6231#define DMASWREQ_DAC (0x1 << 8 )
6232#define DMASWREQ_DAC_DIS (0x0 << 8 ) /* DIS */
6233#define DMASWREQ_DAC_EN (0x1 << 8 ) /* EN */
6234
6235/* DMASWREQ[I2CMRX] - DMA I2C Master RX */
6236#define DMASWREQ_I2CMRX_BBA (*(volatile unsigned long *) 0x4220029C)
6237#define DMASWREQ_I2CMRX_MSK (0x1 << 7 )
6238#define DMASWREQ_I2CMRX (0x1 << 7 )
6239#define DMASWREQ_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6240#define DMASWREQ_I2CMRX_EN (0x1 << 7 ) /* EN */
6241
6242/* DMASWREQ[I2CMTX] - DMA I2C Master TX */
6243#define DMASWREQ_I2CMTX_BBA (*(volatile unsigned long *) 0x42200298)
6244#define DMASWREQ_I2CMTX_MSK (0x1 << 6 )
6245#define DMASWREQ_I2CMTX (0x1 << 6 )
6246#define DMASWREQ_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6247#define DMASWREQ_I2CMTX_EN (0x1 << 6 ) /* EN */
6248
6249/* DMASWREQ[I2CSRX] - DMA I2C Slave RX */
6250#define DMASWREQ_I2CSRX_BBA (*(volatile unsigned long *) 0x42200294)
6251#define DMASWREQ_I2CSRX_MSK (0x1 << 5 )
6252#define DMASWREQ_I2CSRX (0x1 << 5 )
6253#define DMASWREQ_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6254#define DMASWREQ_I2CSRX_EN (0x1 << 5 ) /* EN */
6255
6256/* DMASWREQ[I2CSTX] - DMA I2C Slave TX */
6257#define DMASWREQ_I2CSTX_BBA (*(volatile unsigned long *) 0x42200290)
6258#define DMASWREQ_I2CSTX_MSK (0x1 << 4 )
6259#define DMASWREQ_I2CSTX (0x1 << 4 )
6260#define DMASWREQ_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6261#define DMASWREQ_I2CSTX_EN (0x1 << 4 ) /* EN */
6262
6263/* DMASWREQ[UARTRX] - DMA UART RX */
6264#define DMASWREQ_UARTRX_BBA (*(volatile unsigned long *) 0x4220028C)
6265#define DMASWREQ_UARTRX_MSK (0x1 << 3 )
6266#define DMASWREQ_UARTRX (0x1 << 3 )
6267#define DMASWREQ_UARTRX_DIS (0x0 << 3 ) /* DIS */
6268#define DMASWREQ_UARTRX_EN (0x1 << 3 ) /* EN */
6269
6270/* DMASWREQ[UARTTX] - DMA UART TX */
6271#define DMASWREQ_UARTTX_BBA (*(volatile unsigned long *) 0x42200288)
6272#define DMASWREQ_UARTTX_MSK (0x1 << 2 )
6273#define DMASWREQ_UARTTX (0x1 << 2 )
6274#define DMASWREQ_UARTTX_DIS (0x0 << 2 ) /* DIS */
6275#define DMASWREQ_UARTTX_EN (0x1 << 2 ) /* EN */
6276
6277/* DMASWREQ[SPI1RX] - DMA SPI 1 RX */
6278#define DMASWREQ_SPI1RX_BBA (*(volatile unsigned long *) 0x42200284)
6279#define DMASWREQ_SPI1RX_MSK (0x1 << 1 )
6280#define DMASWREQ_SPI1RX (0x1 << 1 )
6281#define DMASWREQ_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6282#define DMASWREQ_SPI1RX_EN (0x1 << 1 ) /* EN */
6283
6284/* DMASWREQ[SPI1TX] - DMA SPI 1 TX */
6285#define DMASWREQ_SPI1TX_BBA (*(volatile unsigned long *) 0x42200280)
6286#define DMASWREQ_SPI1TX_MSK (0x1 << 0 )
6287#define DMASWREQ_SPI1TX (0x1 << 0 )
6288#define DMASWREQ_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6289#define DMASWREQ_SPI1TX_EN (0x1 << 0 ) /* EN */
6290
6291/* Reset Value for DMARMSKSET*/
6292#define DMARMSKSET_RVAL 0x0
6293/* DMARMSKSET[UART1RX] - DMA UART1 RX */
6294#define DMARMSKSET_UART1RX_BBA (*(volatile unsigned long *) 0x4220043C)
6295#define DMARMSKSET_UART1RX_MSK (0x1 << 15 )
6296#define DMARMSKSET_UART1RX (0x1 << 15 )
6297#define DMARMSKSET_UART1RX_DIS (0x0 << 15 ) /* DIS */
6298#define DMARMSKSET_UART1RX_EN (0x1 << 15 ) /* EN */
6299/* DMARMSKSET[UART1TX] - DMA UART1 TX */
6300#define DMARMSKSET_UART1TX_BBA (*(volatile unsigned long *) 0x42200438)
6301#define DMARMSKSET_UART1TX_MSK (0x1 << 14 )
6302#define DMARMSKSET_UART1TX (0x1 << 14 )
6303#define DMARMSKSET_UART1TX_DIS (0x0 << 14 ) /* DIS */
6304#define DMARMSKSET_UART1TX_EN (0x1 << 14 ) /* EN */
6305/* DMARMSKSET[SPI0RX] - DMA SPI 0 RX */
6306#define DMARMSKSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200434)
6307#define DMARMSKSET_SPI0RX_MSK (0x1 << 13 )
6308#define DMARMSKSET_SPI0RX (0x1 << 13 )
6309#define DMARMSKSET_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6310#define DMARMSKSET_SPI0RX_EN (0x1 << 13 ) /* EN */
6311/* DMARMSKSET[SPI0TX] - DMA SPI 0 TX */
6312#define DMARMSKSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200430)
6313#define DMARMSKSET_SPI0TX_MSK (0x1 << 12 )
6314#define DMARMSKSET_SPI0TX (0x1 << 12 )
6315#define DMARMSKSET_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6316#define DMARMSKSET_SPI0TX_EN (0x1 << 12 ) /* EN */
6317
6318/* DMARMSKSET[SINC2] - SINC2 Output Step detection */
6319#define DMARMSKSET_SINC2_BBA (*(volatile unsigned long *) 0x4220042C)
6320#define DMARMSKSET_SINC2_MSK (0x1 << 11 )
6321#define DMARMSKSET_SINC2 (0x1 << 11 )
6322#define DMARMSKSET_SINC2_DIS (0x0 << 11 ) /* DIS */
6323#define DMARMSKSET_SINC2_EN (0x1 << 11 ) /* EN */
6324
6325/* DMARMSKSET[ADC1] - ADC1 */
6326#define DMARMSKSET_ADC1_BBA (*(volatile unsigned long *) 0x42200428)
6327#define DMARMSKSET_ADC1_MSK (0x1 << 10 )
6328#define DMARMSKSET_ADC1 (0x1 << 10 )
6329#define DMARMSKSET_ADC1_DIS (0x0 << 10 ) /* DIS */
6330#define DMARMSKSET_ADC1_EN (0x1 << 10 ) /* EN */
6331
6332/* DMARMSKSET[DAC] - DAC DMA Output */
6333#define DMARMSKSET_DAC_BBA (*(volatile unsigned long *) 0x42200420)
6334#define DMARMSKSET_DAC_MSK (0x1 << 8 )
6335#define DMARMSKSET_DAC (0x1 << 8 )
6336#define DMARMSKSET_DAC_DIS (0x0 << 8 ) /* DIS */
6337#define DMARMSKSET_DAC_EN (0x1 << 8 ) /* EN */
6338
6339/* DMARMSKSET[I2CMRX] - DMA I2C Master RX */
6340#define DMARMSKSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220041C)
6341#define DMARMSKSET_I2CMRX_MSK (0x1 << 7 )
6342#define DMARMSKSET_I2CMRX (0x1 << 7 )
6343#define DMARMSKSET_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6344#define DMARMSKSET_I2CMRX_EN (0x1 << 7 ) /* EN */
6345
6346/* DMARMSKSET[I2CMTX] - DMA I2C Master TX */
6347#define DMARMSKSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200418)
6348#define DMARMSKSET_I2CMTX_MSK (0x1 << 6 )
6349#define DMARMSKSET_I2CMTX (0x1 << 6 )
6350#define DMARMSKSET_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6351#define DMARMSKSET_I2CMTX_EN (0x1 << 6 ) /* EN */
6352
6353/* DMARMSKSET[I2CSRX] - DMA I2C Slave RX */
6354#define DMARMSKSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200414)
6355#define DMARMSKSET_I2CSRX_MSK (0x1 << 5 )
6356#define DMARMSKSET_I2CSRX (0x1 << 5 )
6357#define DMARMSKSET_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6358#define DMARMSKSET_I2CSRX_EN (0x1 << 5 ) /* EN */
6359
6360/* DMARMSKSET[I2CSTX] - DMA I2C Slave TX */
6361#define DMARMSKSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200410)
6362#define DMARMSKSET_I2CSTX_MSK (0x1 << 4 )
6363#define DMARMSKSET_I2CSTX (0x1 << 4 )
6364#define DMARMSKSET_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6365#define DMARMSKSET_I2CSTX_EN (0x1 << 4 ) /* EN */
6366
6367/* DMARMSKSET[UARTRX] - DMA UART RX */
6368#define DMARMSKSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220040C)
6369#define DMARMSKSET_UARTRX_MSK (0x1 << 3 )
6370#define DMARMSKSET_UARTRX (0x1 << 3 )
6371#define DMARMSKSET_UARTRX_DIS (0x0 << 3 ) /* DIS */
6372#define DMARMSKSET_UARTRX_EN (0x1 << 3 ) /* EN */
6373
6374/* DMARMSKSET[UARTTX] - DMA UART TX */
6375#define DMARMSKSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200408)
6376#define DMARMSKSET_UARTTX_MSK (0x1 << 2 )
6377#define DMARMSKSET_UARTTX (0x1 << 2 )
6378#define DMARMSKSET_UARTTX_DIS (0x0 << 2 ) /* DIS */
6379#define DMARMSKSET_UARTTX_EN (0x1 << 2 ) /* EN */
6380
6381/* DMARMSKSET[SPI1RX] - DMA SPI 1 RX */
6382#define DMARMSKSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200404)
6383#define DMARMSKSET_SPI1RX_MSK (0x1 << 1 )
6384#define DMARMSKSET_SPI1RX (0x1 << 1 )
6385#define DMARMSKSET_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6386#define DMARMSKSET_SPI1RX_EN (0x1 << 1 ) /* EN */
6387
6388/* DMARMSKSET[SPI1TX] - DMA SPI 1 TX */
6389#define DMARMSKSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200400)
6390#define DMARMSKSET_SPI1TX_MSK (0x1 << 0 )
6391#define DMARMSKSET_SPI1TX (0x1 << 0 )
6392#define DMARMSKSET_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6393#define DMARMSKSET_SPI1TX_EN (0x1 << 0 ) /* EN */
6394
6395/* Reset Value for DMARMSKCLR*/
6396#define DMARMSKCLR_RVAL 0x0
6397
6398/* DMARMSKCLR[UART1RX] - DMA UART1 RX */
6399#define DMARMSKCLR_UART1RX_BBA (*(volatile unsigned long *) 0x422004BC)
6400#define DMARMSKCLR_UART1RX_MSK (0x1 << 15 )
6401#define DMARMSKCLR_UART1RX (0x1 << 15 )
6402#define DMARMSKCLR_UART1RX_DIS (0x0 << 15 ) /* DIS */
6403#define DMARMSKCLR_UART1RX_EN (0x1 << 15 ) /* EN */
6404/* DMARMSKCLR[UART1TX] - DMA UART1 TX */
6405#define DMARMSKCLR_UART1TX_BBA (*(volatile unsigned long *) 0x422004B8)
6406#define DMARMSKCLR_UART1TX_MSK (0x1 << 14 )
6407#define DMARMSKCLR_UART1TX (0x1 << 14 )
6408#define DMARMSKCLR_UART1TX_DIS (0x0 << 14 ) /* DIS */
6409#define DMARMSKCLR_UART1TX_EN (0x1 << 14 ) /* EN */
6410/* DMARMSKCLR[SPI0RX] - DMA SPI 0 RX */
6411#define DMARMSKCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422004B4)
6412#define DMARMSKCLR_SPI0RX_MSK (0x1 << 13 )
6413#define DMARMSKCLR_SPI0RX (0x1 << 13 )
6414#define DMARMSKCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6415#define DMARMSKCLR_SPI0RX_EN (0x1 << 13 ) /* EN */
6416/* DMARMSKCLR[SPI0TX] - DMA SPI 0 TX */
6417#define DMARMSKCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422004B0)
6418#define DMARMSKCLR_SPI0TX_MSK (0x1 << 12 )
6419#define DMARMSKCLR_SPI0TX (0x1 << 12 )
6420#define DMARMSKCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6421#define DMARMSKCLR_SPI0TX_EN (0x1 << 12 ) /* EN */
6422/* DMARMSKCLR[SINC2] - SINC2 Output Step detection */
6423#define DMARMSKCLR_SINC2_BBA (*(volatile unsigned long *) 0x422004AC)
6424#define DMARMSKCLR_SINC2_MSK (0x1 << 11 )
6425#define DMARMSKCLR_SINC2 (0x1 << 11 )
6426#define DMARMSKCLR_SINC2_DIS (0x0 << 11 ) /* DIS */
6427#define DMARMSKCLR_SINC2_EN (0x1 << 11 ) /* EN */
6428
6429/* DMARMSKCLR[ADC1] - ADC1 */
6430#define DMARMSKCLR_ADC1_BBA (*(volatile unsigned long *) 0x422004A8)
6431#define DMARMSKCLR_ADC1_MSK (0x1 << 10 )
6432#define DMARMSKCLR_ADC1 (0x1 << 10 )
6433#define DMARMSKCLR_ADC1_DIS (0x0 << 10 ) /* DIS */
6434#define DMARMSKCLR_ADC1_EN (0x1 << 10 ) /* EN */
6435
6436/* DMARMSKCLR[DAC] - DAC DMA Output */
6437#define DMARMSKCLR_DAC_BBA (*(volatile unsigned long *) 0x422004A0)
6438#define DMARMSKCLR_DAC_MSK (0x1 << 8 )
6439#define DMARMSKCLR_DAC (0x1 << 8 )
6440#define DMARMSKCLR_DAC_DIS (0x0 << 8 ) /* DIS */
6441#define DMARMSKCLR_DAC_EN (0x1 << 8 ) /* EN */
6442
6443/* DMARMSKCLR[I2CMRX] - DMA I2C Master RX */
6444#define DMARMSKCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220049C)
6445#define DMARMSKCLR_I2CMRX_MSK (0x1 << 7 )
6446#define DMARMSKCLR_I2CMRX (0x1 << 7 )
6447#define DMARMSKCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6448#define DMARMSKCLR_I2CMRX_EN (0x1 << 7 ) /* EN */
6449
6450/* DMARMSKCLR[I2CMTX] - DMA I2C Master TX */
6451#define DMARMSKCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200498)
6452#define DMARMSKCLR_I2CMTX_MSK (0x1 << 6 )
6453#define DMARMSKCLR_I2CMTX (0x1 << 6 )
6454#define DMARMSKCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6455#define DMARMSKCLR_I2CMTX_EN (0x1 << 6 ) /* EN */
6456
6457/* DMARMSKCLR[I2CSRX] - DMA I2C Slave RX */
6458#define DMARMSKCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200494)
6459#define DMARMSKCLR_I2CSRX_MSK (0x1 << 5 )
6460#define DMARMSKCLR_I2CSRX (0x1 << 5 )
6461#define DMARMSKCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6462#define DMARMSKCLR_I2CSRX_EN (0x1 << 5 ) /* EN */
6463
6464/* DMARMSKCLR[I2CSTX] - DMA I2C Slave TX */
6465#define DMARMSKCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200490)
6466#define DMARMSKCLR_I2CSTX_MSK (0x1 << 4 )
6467#define DMARMSKCLR_I2CSTX (0x1 << 4 )
6468#define DMARMSKCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6469#define DMARMSKCLR_I2CSTX_EN (0x1 << 4 ) /* EN */
6470
6471/* DMARMSKCLR[UARTRX] - DMA UART RX */
6472#define DMARMSKCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220048C)
6473#define DMARMSKCLR_UARTRX_MSK (0x1 << 3 )
6474#define DMARMSKCLR_UARTRX (0x1 << 3 )
6475#define DMARMSKCLR_UARTRX_DIS (0x0 << 3 ) /* DIS */
6476#define DMARMSKCLR_UARTRX_EN (0x1 << 3 ) /* EN */
6477
6478/* DMARMSKCLR[UARTTX] - DMA UART TX */
6479#define DMARMSKCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200488)
6480#define DMARMSKCLR_UARTTX_MSK (0x1 << 2 )
6481#define DMARMSKCLR_UARTTX (0x1 << 2 )
6482#define DMARMSKCLR_UARTTX_DIS (0x0 << 2 ) /* DIS */
6483#define DMARMSKCLR_UARTTX_EN (0x1 << 2 ) /* EN */
6484
6485/* DMARMSKCLR[SPI1RX] - DMA SPI 1 RX */
6486#define DMARMSKCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200484)
6487#define DMARMSKCLR_SPI1RX_MSK (0x1 << 1 )
6488#define DMARMSKCLR_SPI1RX (0x1 << 1 )
6489#define DMARMSKCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6490#define DMARMSKCLR_SPI1RX_EN (0x1 << 1 ) /* EN */
6491
6492/* DMARMSKCLR[SPI1TX] - DMA SPI 1 TX */
6493#define DMARMSKCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200480)
6494#define DMARMSKCLR_SPI1TX_MSK (0x1 << 0 )
6495#define DMARMSKCLR_SPI1TX (0x1 << 0 )
6496#define DMARMSKCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6497#define DMARMSKCLR_SPI1TX_EN (0x1 << 0 ) /* EN */
6498
6499/* Reset Value for DMAENSET*/
6500#define DMAENSET_RVAL 0x0
6501
6502
6503/* DMAENSET[UART1RX] - DMA UART1 RX */
6504#define DMAENSET_UART1RX_BBA (*(volatile unsigned long *) 0x4220053C)
6505#define DMAENSET_UART1RX_MSK (0x1 << 15 )
6506#define DMAENSET_UART1RX (0x1 << 15 )
6507#define DMAENSET_UART1RX_DIS (0x0 << 15 ) /* DIS */
6508#define DMAENSET_UART1RX_EN (0x1 << 15 ) /* EN */
6509/* DMAENSET[UART1TX] - DMA UART1 TX */
6510#define DMAENSET_UART1TX_BBA (*(volatile unsigned long *) 0x42200538)
6511#define DMAENSET_UART1TX_MSK (0x1 << 14 )
6512#define DMAENSET_UART1TX (0x1 << 14 )
6513#define DMAENSET_UART1TX_DIS (0x0 << 14 ) /* DIS */
6514#define DMAENSET_UART1TX_EN (0x1 << 14 ) /* EN */
6515/* DMAENSET[SPI0RX] - DMA SPI 0 RX */
6516#define DMAENSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200534)
6517#define DMAENSET_SPI0RX_MSK (0x1 << 13 )
6518#define DMAENSET_SPI0RX (0x1 << 13 )
6519#define DMAENSET_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6520#define DMAENSET_SPI0RX_EN (0x1 << 13 ) /* EN */
6521/* DMAENSET[SPI0TX] - DMA SPI 0 TX */
6522#define DMAENSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200530)
6523#define DMAENSET_SPI0TX_MSK (0x1 << 12 )
6524#define DMAENSET_SPI0TX (0x1 << 12 )
6525#define DMAENSET_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6526#define DMAENSET_SPI0TX_EN (0x1 << 12 ) /* EN */
6527
6528/* DMAENSET[SINC2] - SINC2 Output Step detection */
6529#define DMAENSET_SINC2_BBA (*(volatile unsigned long *) 0x4220052C)
6530#define DMAENSET_SINC2_MSK (0x1 << 11 )
6531#define DMAENSET_SINC2 (0x1 << 11 )
6532#define DMAENSET_SINC2_DIS (0x0 << 11 ) /* DIS */
6533#define DMAENSET_SINC2_EN (0x1 << 11 ) /* EN */
6534
6535/* DMAENSET[ADC1] - ADC1 */
6536#define DMAENSET_ADC1_BBA (*(volatile unsigned long *) 0x42200528)
6537#define DMAENSET_ADC1_MSK (0x1 << 10 )
6538#define DMAENSET_ADC1 (0x1 << 10 )
6539#define DMAENSET_ADC1_DIS (0x0 << 10 ) /* DIS */
6540#define DMAENSET_ADC1_EN (0x1 << 10 ) /* EN */
6541
6542/* DMAENSET[DAC] - DAC DMA Output */
6543#define DMAENSET_DAC_BBA (*(volatile unsigned long *) 0x42200520)
6544#define DMAENSET_DAC_MSK (0x1 << 8 )
6545#define DMAENSET_DAC (0x1 << 8 )
6546#define DMAENSET_DAC_DIS (0x0 << 8 ) /* DIS */
6547#define DMAENSET_DAC_EN (0x1 << 8 ) /* EN */
6548
6549/* DMAENSET[I2CMRX] - DMA I2C Master RX */
6550#define DMAENSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220051C)
6551#define DMAENSET_I2CMRX_MSK (0x1 << 7 )
6552#define DMAENSET_I2CMRX (0x1 << 7 )
6553#define DMAENSET_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6554#define DMAENSET_I2CMRX_EN (0x1 << 7 ) /* EN */
6555
6556/* DMAENSET[I2CMTX] - DMA I2C Master TX */
6557#define DMAENSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200518)
6558#define DMAENSET_I2CMTX_MSK (0x1 << 6 )
6559#define DMAENSET_I2CMTX (0x1 << 6 )
6560#define DMAENSET_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6561#define DMAENSET_I2CMTX_EN (0x1 << 6 ) /* EN */
6562
6563/* DMAENSET[I2CSRX] - DMA I2C Slave RX */
6564#define DMAENSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200514)
6565#define DMAENSET_I2CSRX_MSK (0x1 << 5 )
6566#define DMAENSET_I2CSRX (0x1 << 5 )
6567#define DMAENSET_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6568#define DMAENSET_I2CSRX_EN (0x1 << 5 ) /* EN */
6569
6570/* DMAENSET[I2CSTX] - DMA I2C Slave TX */
6571#define DMAENSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200510)
6572#define DMAENSET_I2CSTX_MSK (0x1 << 4 )
6573#define DMAENSET_I2CSTX (0x1 << 4 )
6574#define DMAENSET_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6575#define DMAENSET_I2CSTX_EN (0x1 << 4 ) /* EN */
6576
6577/* DMAENSET[UARTRX] - DMA UART RX */
6578#define DMAENSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220050C)
6579#define DMAENSET_UARTRX_MSK (0x1 << 3 )
6580#define DMAENSET_UARTRX (0x1 << 3 )
6581#define DMAENSET_UARTRX_DIS (0x0 << 3 ) /* DIS */
6582#define DMAENSET_UARTRX_EN (0x1 << 3 ) /* EN */
6583
6584/* DMAENSET[UARTTX] - DMA UART TX */
6585#define DMAENSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200508)
6586#define DMAENSET_UARTTX_MSK (0x1 << 2 )
6587#define DMAENSET_UARTTX (0x1 << 2 )
6588#define DMAENSET_UARTTX_DIS (0x0 << 2 ) /* DIS */
6589#define DMAENSET_UARTTX_EN (0x1 << 2 ) /* EN */
6590
6591/* DMAENSET[SPI1RX] - DMA SPI 1 RX */
6592#define DMAENSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200504)
6593#define DMAENSET_SPI1RX_MSK (0x1 << 1 )
6594#define DMAENSET_SPI1RX (0x1 << 1 )
6595#define DMAENSET_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6596#define DMAENSET_SPI1RX_EN (0x1 << 1 ) /* EN */
6597
6598/* DMAENSET[SPI1TX] - DMA SPI 1 TX */
6599#define DMAENSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200500)
6600#define DMAENSET_SPI1TX_MSK (0x1 << 0 )
6601#define DMAENSET_SPI1TX (0x1 << 0 )
6602#define DMAENSET_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6603#define DMAENSET_SPI1TX_EN (0x1 << 0 ) /* EN */
6604
6605/* Reset Value for DMAENCLR*/
6606#define DMAENCLR_RVAL 0x0
6607
6608/* DMAENCLR[UART1RX] - DMA UART1 RX */
6609#define DMAENCLR_UART1RX_BBA (*(volatile unsigned long *) 0x422005BC)
6610#define DMAENCLR_UART1RX_MSK (0x1 << 15 )
6611#define DMAENCLR_UART1RX (0x1 << 15 )
6612#define DMAENCLR_UART1RX_DIS (0x0 << 15 ) /* DIS */
6613#define DMAENCLR_UART1RX_EN (0x1 << 15 ) /* EN */
6614/* DMAENCLR[UART1TX] - DMA UART1 TX */
6615#define DMAENCLR_UART1TX_BBA (*(volatile unsigned long *) 0x422005B8)
6616#define DMAENCLR_UART1TX_MSK (0x1 << 14 )
6617#define DMAENCLR_UART1TX (0x1 << 14 )
6618#define DMAENCLR_UART1TX_DIS (0x0 << 14 ) /* DIS */
6619#define DMAENCLR_UART1TX_EN (0x1 << 14 ) /* EN */
6620/* DMAENCLR[SPI0RX] - DMA SPI 0 RX */
6621#define DMAENCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422005B4)
6622#define DMAENCLR_SPI0RX_MSK (0x1 << 13 )
6623#define DMAENCLR_SPI0RX (0x1 << 13 )
6624#define DMAENCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6625#define DMAENCLR_SPI0RX_EN (0x1 << 13 ) /* EN */
6626/* DMAENCLR[SPI0TX] - DMA SPI 0 TX */
6627#define DMAENCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422005B0)
6628#define DMAENCLR_SPI0TX_MSK (0x1 << 12 )
6629#define DMAENCLR_SPI0TX (0x1 << 12 )
6630#define DMAENCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6631#define DMAENCLR_SPI0TX_EN (0x1 << 12 ) /* EN */
6632
6633
6634/* DMAENCLR[SINC2] - SINC2 Output Step detection */
6635#define DMAENCLR_SINC2_BBA (*(volatile unsigned long *) 0x422005AC)
6636#define DMAENCLR_SINC2_MSK (0x1 << 11 )
6637#define DMAENCLR_SINC2 (0x1 << 11 )
6638#define DMAENCLR_SINC2_DIS (0x0 << 11 ) /* DIS */
6639#define DMAENCLR_SINC2_EN (0x1 << 11 ) /* EN */
6640
6641/* DMAENCLR[ADC1] - ADC1 */
6642#define DMAENCLR_ADC1_BBA (*(volatile unsigned long *) 0x422005A8)
6643#define DMAENCLR_ADC1_MSK (0x1 << 10 )
6644#define DMAENCLR_ADC1 (0x1 << 10 )
6645#define DMAENCLR_ADC1_DIS (0x0 << 10 ) /* DIS */
6646#define DMAENCLR_ADC1_EN (0x1 << 10 ) /* EN */
6647
6648/* DMAENCLR[DAC] - DAC DMA Output */
6649#define DMAENCLR_DAC_BBA (*(volatile unsigned long *) 0x422005A0)
6650#define DMAENCLR_DAC_MSK (0x1 << 8 )
6651#define DMAENCLR_DAC (0x1 << 8 )
6652#define DMAENCLR_DAC_DIS (0x0 << 8 ) /* DIS */
6653#define DMAENCLR_DAC_EN (0x1 << 8 ) /* EN */
6654
6655/* DMAENCLR[I2CMRX] - DMA I2C Master RX */
6656#define DMAENCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220059C)
6657#define DMAENCLR_I2CMRX_MSK (0x1 << 7 )
6658#define DMAENCLR_I2CMRX (0x1 << 7 )
6659#define DMAENCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6660#define DMAENCLR_I2CMRX_EN (0x1 << 7 ) /* EN */
6661
6662/* DMAENCLR[I2CMTX] - DMA I2C Master TX */
6663#define DMAENCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200598)
6664#define DMAENCLR_I2CMTX_MSK (0x1 << 6 )
6665#define DMAENCLR_I2CMTX (0x1 << 6 )
6666#define DMAENCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6667#define DMAENCLR_I2CMTX_EN (0x1 << 6 ) /* EN */
6668
6669/* DMAENCLR[I2CSRX] - DMA I2C Slave RX */
6670#define DMAENCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200594)
6671#define DMAENCLR_I2CSRX_MSK (0x1 << 5 )
6672#define DMAENCLR_I2CSRX (0x1 << 5 )
6673#define DMAENCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6674#define DMAENCLR_I2CSRX_EN (0x1 << 5 ) /* EN */
6675
6676/* DMAENCLR[I2CSTX] - DMA I2C Slave TX */
6677#define DMAENCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200590)
6678#define DMAENCLR_I2CSTX_MSK (0x1 << 4 )
6679#define DMAENCLR_I2CSTX (0x1 << 4 )
6680#define DMAENCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6681#define DMAENCLR_I2CSTX_EN (0x1 << 4 ) /* EN */
6682
6683/* DMAENCLR[UARTRX] - DMA UART RX */
6684#define DMAENCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220058C)
6685#define DMAENCLR_UARTRX_MSK (0x1 << 3 )
6686#define DMAENCLR_UARTRX (0x1 << 3 )
6687#define DMAENCLR_UARTRX_DIS (0x0 << 3 ) /* DIS */
6688#define DMAENCLR_UARTRX_EN (0x1 << 3 ) /* EN */
6689
6690/* DMAENCLR[UARTTX] - DMA UART TX */
6691#define DMAENCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200588)
6692#define DMAENCLR_UARTTX_MSK (0x1 << 2 )
6693#define DMAENCLR_UARTTX (0x1 << 2 )
6694#define DMAENCLR_UARTTX_DIS (0x0 << 2 ) /* DIS */
6695#define DMAENCLR_UARTTX_EN (0x1 << 2 ) /* EN */
6696
6697/* DMAENCLR[SPI1RX] - DMA SPI 1 RX */
6698#define DMAENCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200584)
6699#define DMAENCLR_SPI1RX_MSK (0x1 << 1 )
6700#define DMAENCLR_SPI1RX (0x1 << 1 )
6701#define DMAENCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6702#define DMAENCLR_SPI1RX_EN (0x1 << 1 ) /* EN */
6703
6704/* DMAENCLR[SPI1TX] - DMA SPI 1 TX */
6705#define DMAENCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200580)
6706#define DMAENCLR_SPI1TX_MSK (0x1 << 0 )
6707#define DMAENCLR_SPI1TX (0x1 << 0 )
6708#define DMAENCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6709#define DMAENCLR_SPI1TX_EN (0x1 << 0 ) /* EN */
6710
6711/* Reset Value for DMAALTSET*/
6712#define DMAALTSET_RVAL 0x0
6713
6714/* DMAALTSET[UART1RX] - DMA UART1 RX */
6715#define DMAALTSET_UART1RX_BBA (*(volatile unsigned long *) 0x4220063C)
6716#define DMAALTSET_UART1RX_MSK (0x1 << 15 )
6717#define DMAALTSET_UART1RX (0x1 << 15 )
6718#define DMAALTSET_UART1RX_DIS (0x0 << 15 ) /* DIS */
6719#define DMAALTSET_UART1RX_EN (0x1 << 15 ) /* EN */
6720/* DMAALTSET[UART1TX] - DMA UART1 TX */
6721#define DMAALTSET_UART1TX_BBA (*(volatile unsigned long *) 0x42200638)
6722#define DMAALTSET_UART1TX_MSK (0x1 << 14 )
6723#define DMAALTSET_UART1TX (0x1 << 14 )
6724#define DMAALTSET_UART1TX_DIS (0x0 << 14 ) /* DIS */
6725#define DMAALTSET_UART1TX_EN (0x1 << 14 ) /* EN */
6726/* DMAALTSET[SPI0RX] - DMA SPI 0 RX */
6727#define DMAALTSET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200634)
6728#define DMAALTSET_SPI0RX_MSK (0x1 << 13 )
6729#define DMAALTSET_SPI0RX (0x1 << 13 )
6730#define DMAALTSET_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6731#define DMAALTSET_SPI0RX_EN (0x1 << 13 ) /* EN */
6732/* DMAALTSET[SPI0TX] - DMA SPI 0 TX */
6733#define DMAALTSET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200630)
6734#define DMAALTSET_SPI0TX_MSK (0x1 << 12 )
6735#define DMAALTSET_SPI0TX (0x1 << 12 )
6736#define DMAALTSET_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6737#define DMAALTSET_SPI0TX_EN (0x1 << 12 ) /* EN */
6738
6739/* DMAALTSET[SINC2] - SINC2 Output Step detection */
6740#define DMAALTSET_SINC2_BBA (*(volatile unsigned long *) 0x4220062C)
6741#define DMAALTSET_SINC2_MSK (0x1 << 11 )
6742#define DMAALTSET_SINC2 (0x1 << 11 )
6743#define DMAALTSET_SINC2_DIS (0x0 << 11 ) /* DIS */
6744#define DMAALTSET_SINC2_EN (0x1 << 11 ) /* EN */
6745
6746/* DMAALTSET[ADC1] - ADC1 */
6747#define DMAALTSET_ADC1_BBA (*(volatile unsigned long *) 0x42200628)
6748#define DMAALTSET_ADC1_MSK (0x1 << 10 )
6749#define DMAALTSET_ADC1 (0x1 << 10 )
6750#define DMAALTSET_ADC1_DIS (0x0 << 10 ) /* DIS */
6751#define DMAALTSET_ADC1_EN (0x1 << 10 ) /* EN */
6752
6753/* DMAALTSET[DAC] - DAC DMA Output */
6754#define DMAALTSET_DAC_BBA (*(volatile unsigned long *) 0x42200620)
6755#define DMAALTSET_DAC_MSK (0x1 << 8 )
6756#define DMAALTSET_DAC (0x1 << 8 )
6757#define DMAALTSET_DAC_DIS (0x0 << 8 ) /* DIS */
6758#define DMAALTSET_DAC_EN (0x1 << 8 ) /* EN */
6759
6760/* DMAALTSET[I2CMRX] - DMA I2C Master RX */
6761#define DMAALTSET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220061C)
6762#define DMAALTSET_I2CMRX_MSK (0x1 << 7 )
6763#define DMAALTSET_I2CMRX (0x1 << 7 )
6764#define DMAALTSET_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6765#define DMAALTSET_I2CMRX_EN (0x1 << 7 ) /* EN */
6766
6767/* DMAALTSET[I2CMTX] - DMA I2C Master TX */
6768#define DMAALTSET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200618)
6769#define DMAALTSET_I2CMTX_MSK (0x1 << 6 )
6770#define DMAALTSET_I2CMTX (0x1 << 6 )
6771#define DMAALTSET_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6772#define DMAALTSET_I2CMTX_EN (0x1 << 6 ) /* EN */
6773
6774/* DMAALTSET[I2CSRX] - DMA I2C Slave RX */
6775#define DMAALTSET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200614)
6776#define DMAALTSET_I2CSRX_MSK (0x1 << 5 )
6777#define DMAALTSET_I2CSRX (0x1 << 5 )
6778#define DMAALTSET_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6779#define DMAALTSET_I2CSRX_EN (0x1 << 5 ) /* EN */
6780
6781/* DMAALTSET[I2CSTX] - DMA I2C Slave TX */
6782#define DMAALTSET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200610)
6783#define DMAALTSET_I2CSTX_MSK (0x1 << 4 )
6784#define DMAALTSET_I2CSTX (0x1 << 4 )
6785#define DMAALTSET_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6786#define DMAALTSET_I2CSTX_EN (0x1 << 4 ) /* EN */
6787
6788/* DMAALTSET[UARTRX] - DMA UART RX */
6789#define DMAALTSET_UARTRX_BBA (*(volatile unsigned long *) 0x4220060C)
6790#define DMAALTSET_UARTRX_MSK (0x1 << 3 )
6791#define DMAALTSET_UARTRX (0x1 << 3 )
6792#define DMAALTSET_UARTRX_DIS (0x0 << 3 ) /* DIS */
6793#define DMAALTSET_UARTRX_EN (0x1 << 3 ) /* EN */
6794
6795/* DMAALTSET[UARTTX] - DMA UART TX */
6796#define DMAALTSET_UARTTX_BBA (*(volatile unsigned long *) 0x42200608)
6797#define DMAALTSET_UARTTX_MSK (0x1 << 2 )
6798#define DMAALTSET_UARTTX (0x1 << 2 )
6799#define DMAALTSET_UARTTX_DIS (0x0 << 2 ) /* DIS */
6800#define DMAALTSET_UARTTX_EN (0x1 << 2 ) /* EN */
6801
6802/* DMAALTSET[SPI1RX] - DMA SPI 1 RX */
6803#define DMAALTSET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200604)
6804#define DMAALTSET_SPI1RX_MSK (0x1 << 1 )
6805#define DMAALTSET_SPI1RX (0x1 << 1 )
6806#define DMAALTSET_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6807#define DMAALTSET_SPI1RX_EN (0x1 << 1 ) /* EN */
6808
6809/* DMAALTSET[SPI1TX] - DMA SPI 1 TX */
6810#define DMAALTSET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200600)
6811#define DMAALTSET_SPI1TX_MSK (0x1 << 0 )
6812#define DMAALTSET_SPI1TX (0x1 << 0 )
6813#define DMAALTSET_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6814#define DMAALTSET_SPI1TX_EN (0x1 << 0 ) /* EN */
6815
6816/* Reset Value for DMAALTCLR*/
6817#define DMAALTCLR_RVAL 0x0
6818
6819/* DMAALTCLR[UART1RX] - DMA UART1 RX */
6820#define DMAALTCLR_UART1RX_BBA (*(volatile unsigned long *) 0x422006BC)
6821#define DMAALTCLR_UART1RX_MSK (0x1 << 15 )
6822#define DMAALTCLR_UART1RX (0x1 << 15 )
6823#define DMAALTCLR_UART1RX_DIS (0x0 << 15 ) /* DIS */
6824#define DMAALTCLR_UART1RX_EN (0x1 << 15 ) /* EN */
6825/* DMAALTCLR[UART1TX] - DMA UART1 TX */
6826#define DMAALTCLR_UART1TX_BBA (*(volatile unsigned long *) 0x422006B8)
6827#define DMAALTCLR_UART1TX_MSK (0x1 << 14 )
6828#define DMAALTCLR_UART1TX (0x1 << 14 )
6829#define DMAALTCLR_UART1TX_DIS (0x0 << 14 ) /* DIS */
6830#define DMAALTCLR_UART1TX_EN (0x1 << 14 ) /* EN */
6831/* DMAALTCLR[SPI0RX] - DMA SPI 0 RX */
6832#define DMAALTCLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422006B4)
6833#define DMAALTCLR_SPI0RX_MSK (0x1 << 13 )
6834#define DMAALTCLR_SPI0RX (0x1 << 13 )
6835#define DMAALTCLR_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6836#define DMAALTCLR_SPI0RX_EN (0x1 << 13 ) /* EN */
6837/* DMAALTCLR[SPI0TX] - DMA SPI 0 TX */
6838#define DMAALTCLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422006B0)
6839#define DMAALTCLR_SPI0TX_MSK (0x1 << 12 )
6840#define DMAALTCLR_SPI0TX (0x1 << 12 )
6841#define DMAALTCLR_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6842#define DMAALTCLR_SPI0TX_EN (0x1 << 12 ) /* EN */
6843
6844
6845/* DMAALTCLR[SINC2] - SINC2 Output Step detection */
6846#define DMAALTCLR_SINC2_BBA (*(volatile unsigned long *) 0x422006AC)
6847#define DMAALTCLR_SINC2_MSK (0x1 << 11 )
6848#define DMAALTCLR_SINC2 (0x1 << 11 )
6849#define DMAALTCLR_SINC2_DIS (0x0 << 11 ) /* DIS */
6850#define DMAALTCLR_SINC2_EN (0x1 << 11 ) /* EN */
6851
6852/* DMAALTCLR[ADC1] - ADC1 */
6853#define DMAALTCLR_ADC1_BBA (*(volatile unsigned long *) 0x422006A8)
6854#define DMAALTCLR_ADC1_MSK (0x1 << 10 )
6855#define DMAALTCLR_ADC1 (0x1 << 10 )
6856#define DMAALTCLR_ADC1_DIS (0x0 << 10 ) /* DIS */
6857#define DMAALTCLR_ADC1_EN (0x1 << 10 ) /* EN */
6858
6859/* DMAALTCLR[DAC] - DAC DMA Output */
6860#define DMAALTCLR_DAC_BBA (*(volatile unsigned long *) 0x422006A0)
6861#define DMAALTCLR_DAC_MSK (0x1 << 8 )
6862#define DMAALTCLR_DAC (0x1 << 8 )
6863#define DMAALTCLR_DAC_DIS (0x0 << 8 ) /* DIS */
6864#define DMAALTCLR_DAC_EN (0x1 << 8 ) /* EN */
6865
6866/* DMAALTCLR[I2CMRX] - DMA I2C Master RX */
6867#define DMAALTCLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220069C)
6868#define DMAALTCLR_I2CMRX_MSK (0x1 << 7 )
6869#define DMAALTCLR_I2CMRX (0x1 << 7 )
6870#define DMAALTCLR_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6871#define DMAALTCLR_I2CMRX_EN (0x1 << 7 ) /* EN */
6872
6873/* DMAALTCLR[I2CMTX] - DMA I2C Master TX */
6874#define DMAALTCLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200698)
6875#define DMAALTCLR_I2CMTX_MSK (0x1 << 6 )
6876#define DMAALTCLR_I2CMTX (0x1 << 6 )
6877#define DMAALTCLR_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6878#define DMAALTCLR_I2CMTX_EN (0x1 << 6 ) /* EN */
6879
6880/* DMAALTCLR[I2CSRX] - DMA I2C Slave RX */
6881#define DMAALTCLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200694)
6882#define DMAALTCLR_I2CSRX_MSK (0x1 << 5 )
6883#define DMAALTCLR_I2CSRX (0x1 << 5 )
6884#define DMAALTCLR_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6885#define DMAALTCLR_I2CSRX_EN (0x1 << 5 ) /* EN */
6886
6887/* DMAALTCLR[I2CSTX] - DMA I2C Slave TX */
6888#define DMAALTCLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200690)
6889#define DMAALTCLR_I2CSTX_MSK (0x1 << 4 )
6890#define DMAALTCLR_I2CSTX (0x1 << 4 )
6891#define DMAALTCLR_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6892#define DMAALTCLR_I2CSTX_EN (0x1 << 4 ) /* EN */
6893
6894/* DMAALTCLR[UARTRX] - DMA UART RX */
6895#define DMAALTCLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220068C)
6896#define DMAALTCLR_UARTRX_MSK (0x1 << 3 )
6897#define DMAALTCLR_UARTRX (0x1 << 3 )
6898#define DMAALTCLR_UARTRX_DIS (0x0 << 3 ) /* DIS */
6899#define DMAALTCLR_UARTRX_EN (0x1 << 3 ) /* EN */
6900
6901/* DMAALTCLR[UARTTX] - DMA UART TX */
6902#define DMAALTCLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200688)
6903#define DMAALTCLR_UARTTX_MSK (0x1 << 2 )
6904#define DMAALTCLR_UARTTX (0x1 << 2 )
6905#define DMAALTCLR_UARTTX_DIS (0x0 << 2 ) /* DIS */
6906#define DMAALTCLR_UARTTX_EN (0x1 << 2 ) /* EN */
6907
6908/* DMAALTCLR[SPI1RX] - DMA SPI 1 RX */
6909#define DMAALTCLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200684)
6910#define DMAALTCLR_SPI1RX_MSK (0x1 << 1 )
6911#define DMAALTCLR_SPI1RX (0x1 << 1 )
6912#define DMAALTCLR_SPI1RX_DIS (0x0 << 1 ) /* DIS */
6913#define DMAALTCLR_SPI1RX_EN (0x1 << 1 ) /* EN */
6914
6915/* DMAALTCLR[SPI1TX] - DMA SPI 1 TX */
6916#define DMAALTCLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200680)
6917#define DMAALTCLR_SPI1TX_MSK (0x1 << 0 )
6918#define DMAALTCLR_SPI1TX (0x1 << 0 )
6919#define DMAALTCLR_SPI1TX_DIS (0x0 << 0 ) /* DIS */
6920#define DMAALTCLR_SPI1TX_EN (0x1 << 0 ) /* EN */
6921
6922/* Reset Value for DMAPRISET*/
6923#define DMAPRISET_RVAL 0x0
6924/*DMAPRISET[UART1RX] - DMA UART1 RX */
6925#define DMAPRISET_UART1RX_BBA (*(volatile unsigned long *) 0x4220073C)
6926#define DMAPRISET_UART1RX_MSK (0x1 << 15 )
6927#define DMAPRISET_UART1RX (0x1 << 15 )
6928#define DMAPRISET_UART1RX_DIS (0x0 << 15 ) /* DIS */
6929#define DMAPRISET_UART1RX_EN (0x1 << 15 ) /* EN */
6930/* DMAPRISET[UART1TX] - DMA UART1 TX */
6931#define DMAPRISET_UART1TX_BBA (*(volatile unsigned long *) 0x42200738)
6932#define DMAPRISET_UART1TX_MSK (0x1 << 14 )
6933#define DMAPRISET_UART1TX (0x1 << 14 )
6934#define DMAPRISET_UART1TX_DIS (0x0 << 14 ) /* DIS */
6935#define DMAPRISET_UART1TX_EN (0x1 << 14 ) /* EN */
6936/* DMAPRISET[SPI0RX] - DMA SPI 0 RX */
6937#define DMAPRISET_SPI0RX_BBA (*(volatile unsigned long *) 0x42200734)
6938#define DMAPRISET_SPI0RX_MSK (0x1 << 13 )
6939#define DMAPRISET_SPI0RX (0x1 << 13 )
6940#define DMAPRISET_SPI0RX_DIS (0x0 << 13 ) /* DIS */
6941#define DMAPRISET_SPI0RX_EN (0x1 << 13 ) /* EN */
6942/* DMAPRISET[SPI0TX] - DMA SPI 0 TX */
6943#define DMAPRISET_SPI0TX_BBA (*(volatile unsigned long *) 0x42200730)
6944#define DMAPRISET_SPI0TX_MSK (0x1 << 12 )
6945#define DMAPRISET_SPI0TX (0x1 << 12 )
6946#define DMAPRISET_SPI0TX_DIS (0x0 << 12 ) /* DIS */
6947#define DMAPRISET_SPI0TX_EN (0x1 << 12 ) /* EN */
6948
6949
6950/* DMAPRISET[SINC2] - SINC2 Output Step detection */
6951#define DMAPRISET_SINC2_BBA (*(volatile unsigned long *) 0x4220072C)
6952#define DMAPRISET_SINC2_MSK (0x1 << 11 )
6953#define DMAPRISET_SINC2 (0x1 << 11 )
6954#define DMAPRISET_SINC2_DIS (0x0 << 11 ) /* DIS */
6955#define DMAPRISET_SINC2_EN (0x1 << 11 ) /* EN */
6956
6957/* DMAPRISET[ADC1] - ADC1 */
6958#define DMAPRISET_ADC1_BBA (*(volatile unsigned long *) 0x42200728)
6959#define DMAPRISET_ADC1_MSK (0x1 << 10 )
6960#define DMAPRISET_ADC1 (0x1 << 10 )
6961#define DMAPRISET_ADC1_DIS (0x0 << 10 ) /* DIS */
6962#define DMAPRISET_ADC1_EN (0x1 << 10 ) /* EN */
6963
6964/* DMAPRISET[DAC] - DAC DMA Output */
6965#define DMAPRISET_DAC_BBA (*(volatile unsigned long *) 0x42200720)
6966#define DMAPRISET_DAC_MSK (0x1 << 8 )
6967#define DMAPRISET_DAC (0x1 << 8 )
6968#define DMAPRISET_DAC_DIS (0x0 << 8 ) /* DIS */
6969#define DMAPRISET_DAC_EN (0x1 << 8 ) /* EN */
6970
6971/* DMAPRISET[I2CMRX] - DMA I2C Master RX */
6972#define DMAPRISET_I2CMRX_BBA (*(volatile unsigned long *) 0x4220071C)
6973#define DMAPRISET_I2CMRX_MSK (0x1 << 7 )
6974#define DMAPRISET_I2CMRX (0x1 << 7 )
6975#define DMAPRISET_I2CMRX_DIS (0x0 << 7 ) /* DIS */
6976#define DMAPRISET_I2CMRX_EN (0x1 << 7 ) /* EN */
6977
6978/* DMAPRISET[I2CMTX] - DMA I2C Master TX */
6979#define DMAPRISET_I2CMTX_BBA (*(volatile unsigned long *) 0x42200718)
6980#define DMAPRISET_I2CMTX_MSK (0x1 << 6 )
6981#define DMAPRISET_I2CMTX (0x1 << 6 )
6982#define DMAPRISET_I2CMTX_DIS (0x0 << 6 ) /* DIS */
6983#define DMAPRISET_I2CMTX_EN (0x1 << 6 ) /* EN */
6984
6985/* DMAPRISET[I2CSRX] - DMA I2C Slave RX */
6986#define DMAPRISET_I2CSRX_BBA (*(volatile unsigned long *) 0x42200714)
6987#define DMAPRISET_I2CSRX_MSK (0x1 << 5 )
6988#define DMAPRISET_I2CSRX (0x1 << 5 )
6989#define DMAPRISET_I2CSRX_DIS (0x0 << 5 ) /* DIS */
6990#define DMAPRISET_I2CSRX_EN (0x1 << 5 ) /* EN */
6991
6992/* DMAPRISET[I2CSTX] - DMA I2C Slave TX */
6993#define DMAPRISET_I2CSTX_BBA (*(volatile unsigned long *) 0x42200710)
6994#define DMAPRISET_I2CSTX_MSK (0x1 << 4 )
6995#define DMAPRISET_I2CSTX (0x1 << 4 )
6996#define DMAPRISET_I2CSTX_DIS (0x0 << 4 ) /* DIS */
6997#define DMAPRISET_I2CSTX_EN (0x1 << 4 ) /* EN */
6998
6999/* DMAPRISET[UARTRX] - DMA UART RX */
7000#define DMAPRISET_UARTRX_BBA (*(volatile unsigned long *) 0x4220070C)
7001#define DMAPRISET_UARTRX_MSK (0x1 << 3 )
7002#define DMAPRISET_UARTRX (0x1 << 3 )
7003#define DMAPRISET_UARTRX_DIS (0x0 << 3 ) /* DIS */
7004#define DMAPRISET_UARTRX_EN (0x1 << 3 ) /* EN */
7005
7006/* DMAPRISET[UARTTX] - DMA UART TX */
7007#define DMAPRISET_UARTTX_BBA (*(volatile unsigned long *) 0x42200708)
7008#define DMAPRISET_UARTTX_MSK (0x1 << 2 )
7009#define DMAPRISET_UARTTX (0x1 << 2 )
7010#define DMAPRISET_UARTTX_DIS (0x0 << 2 ) /* DIS */
7011#define DMAPRISET_UARTTX_EN (0x1 << 2 ) /* EN */
7012
7013/* DMAPRISET[SPI1RX] - DMA SPI 1 RX */
7014#define DMAPRISET_SPI1RX_BBA (*(volatile unsigned long *) 0x42200704)
7015#define DMAPRISET_SPI1RX_MSK (0x1 << 1 )
7016#define DMAPRISET_SPI1RX (0x1 << 1 )
7017#define DMAPRISET_SPI1RX_DIS (0x0 << 1 ) /* DIS */
7018#define DMAPRISET_SPI1RX_EN (0x1 << 1 ) /* EN */
7019
7020/* DMAPRISET[SPI1TX] - DMA SPI 1 TX */
7021#define DMAPRISET_SPI1TX_BBA (*(volatile unsigned long *) 0x42200700)
7022#define DMAPRISET_SPI1TX_MSK (0x1 << 0 )
7023#define DMAPRISET_SPI1TX (0x1 << 0 )
7024#define DMAPRISET_SPI1TX_DIS (0x0 << 0 ) /* DIS */
7025#define DMAPRISET_SPI1TX_EN (0x1 << 0 ) /* EN */
7026
7027/* Reset Value for DMAPRICLR*/
7028#define DMAPRICLR_RVAL 0x0
7029
7030/*DMAPRICLR[UART1RX] - DMA UART1 RX */
7031#define DMAPRICLR_UART1RX_BBA (*(volatile unsigned long *) 0x422007BC)
7032#define DMAPRICLR_UART1RX_MSK (0x1 << 15 )
7033#define DMAPRICLR_UART1RX (0x1 << 15 )
7034#define DMAPRICLR_UART1RX_DIS (0x0 << 15 ) /* DIS */
7035#define DMAPRICLR_UART1RX_EN (0x1 << 15 ) /* EN */
7036/* DMAPRICLR[UART1TX] - DMA UART1 TX */
7037#define DMAPRICLR_UART1TX_BBA (*(volatile unsigned long *) 0x422007B8)
7038#define DMAPRICLR_UART1TX_MSK (0x1 << 14 )
7039#define DMAPRICLR_UART1TX (0x1 << 14 )
7040#define DMAPRICLR_UART1TX_DIS (0x0 << 14 ) /* DIS */
7041#define DMAPRICLR_UART1TX_EN (0x1 << 14 ) /* EN */
7042/* DMAPRICLR[SPI0RX] - DMA SPI 0 RX */
7043#define DMAPRICLR_SPI0RX_BBA (*(volatile unsigned long *) 0x422007B4)
7044#define DMAPRICLR_SPI0RX_MSK (0x1 << 13 )
7045#define DMAPRICLR_SPI0RX (0x1 << 13 )
7046#define DMAPRICLR_SPI0RX_DIS (0x0 << 13 ) /* DIS */
7047#define DMAPRICLR_SPI0RX_EN (0x1 << 13 ) /* EN */
7048/* DMAPRICLR[SPI0TX] - DMA SPI 0 TX */
7049#define DMAPRICLR_SPI0TX_BBA (*(volatile unsigned long *) 0x422007B0)
7050#define DMAPRICLR_SPI0TX_MSK (0x1 << 12 )
7051#define DMAPRICLR_SPI0TX (0x1 << 12 )
7052#define DMAPRICLR_SPI0TX_DIS (0x0 << 12 ) /* DIS */
7053#define DMAPRICLR_SPI0TX_EN (0x1 << 12 ) /* EN */
7054
7055/* DMAPRICLR[SINC2] - SINC2 Output Step detection */
7056#define DMAPRICLR_SINC2_BBA (*(volatile unsigned long *) 0x422007AC)
7057#define DMAPRICLR_SINC2_MSK (0x1 << 11 )
7058#define DMAPRICLR_SINC2 (0x1 << 11 )
7059#define DMAPRICLR_SINC2_DIS (0x0 << 11 ) /* DIS */
7060#define DMAPRICLR_SINC2_EN (0x1 << 11 ) /* EN */
7061
7062/* DMAPRICLR[ADC1] - ADC1 */
7063#define DMAPRICLR_ADC1_BBA (*(volatile unsigned long *) 0x422007A8)
7064#define DMAPRICLR_ADC1_MSK (0x1 << 10 )
7065#define DMAPRICLR_ADC1 (0x1 << 10 )
7066#define DMAPRICLR_ADC1_DIS (0x0 << 10 ) /* DIS */
7067#define DMAPRICLR_ADC1_EN (0x1 << 10 ) /* EN */
7068
7069/* DMAPRICLR[DAC] - DAC DMA Output */
7070#define DMAPRICLR_DAC_BBA (*(volatile unsigned long *) 0x422007A0)
7071#define DMAPRICLR_DAC_MSK (0x1 << 8 )
7072#define DMAPRICLR_DAC (0x1 << 8 )
7073#define DMAPRICLR_DAC_DIS (0x0 << 8 ) /* DIS */
7074#define DMAPRICLR_DAC_EN (0x1 << 8 ) /* EN */
7075
7076/* DMAPRICLR[I2CMRX] - DMA I2C Master RX */
7077#define DMAPRICLR_I2CMRX_BBA (*(volatile unsigned long *) 0x4220079C)
7078#define DMAPRICLR_I2CMRX_MSK (0x1 << 7 )
7079#define DMAPRICLR_I2CMRX (0x1 << 7 )
7080#define DMAPRICLR_I2CMRX_DIS (0x0 << 7 ) /* DIS */
7081#define DMAPRICLR_I2CMRX_EN (0x1 << 7 ) /* EN */
7082
7083/* DMAPRICLR[I2CMTX] - DMA I2C Master TX */
7084#define DMAPRICLR_I2CMTX_BBA (*(volatile unsigned long *) 0x42200798)
7085#define DMAPRICLR_I2CMTX_MSK (0x1 << 6 )
7086#define DMAPRICLR_I2CMTX (0x1 << 6 )
7087#define DMAPRICLR_I2CMTX_DIS (0x0 << 6 ) /* DIS */
7088#define DMAPRICLR_I2CMTX_EN (0x1 << 6 ) /* EN */
7089
7090/* DMAPRICLR[I2CSRX] - DMA I2C Slave RX */
7091#define DMAPRICLR_I2CSRX_BBA (*(volatile unsigned long *) 0x42200794)
7092#define DMAPRICLR_I2CSRX_MSK (0x1 << 5 )
7093#define DMAPRICLR_I2CSRX (0x1 << 5 )
7094#define DMAPRICLR_I2CSRX_DIS (0x0 << 5 ) /* DIS */
7095#define DMAPRICLR_I2CSRX_EN (0x1 << 5 ) /* EN */
7096
7097/* DMAPRICLR[I2CSTX] - DMA I2C Slave TX */
7098#define DMAPRICLR_I2CSTX_BBA (*(volatile unsigned long *) 0x42200790)
7099#define DMAPRICLR_I2CSTX_MSK (0x1 << 4 )
7100#define DMAPRICLR_I2CSTX (0x1 << 4 )
7101#define DMAPRICLR_I2CSTX_DIS (0x0 << 4 ) /* DIS */
7102#define DMAPRICLR_I2CSTX_EN (0x1 << 4 ) /* EN */
7103
7104/* DMAPRICLR[UARTRX] - DMA UART RX */
7105#define DMAPRICLR_UARTRX_BBA (*(volatile unsigned long *) 0x4220078C)
7106#define DMAPRICLR_UARTRX_MSK (0x1 << 3 )
7107#define DMAPRICLR_UARTRX (0x1 << 3 )
7108#define DMAPRICLR_UARTRX_DIS (0x0 << 3 ) /* DIS */
7109#define DMAPRICLR_UARTRX_EN (0x1 << 3 ) /* EN */
7110
7111/* DMAPRICLR[UARTTX] - DMA UART TX */
7112#define DMAPRICLR_UARTTX_BBA (*(volatile unsigned long *) 0x42200788)
7113#define DMAPRICLR_UARTTX_MSK (0x1 << 2 )
7114#define DMAPRICLR_UARTTX (0x1 << 2 )
7115#define DMAPRICLR_UARTTX_DIS (0x0 << 2 ) /* DIS */
7116#define DMAPRICLR_UARTTX_EN (0x1 << 2 ) /* EN */
7117
7118/* DMAPRICLR[SPI1RX] - DMA SPI 1 RX */
7119#define DMAPRICLR_SPI1RX_BBA (*(volatile unsigned long *) 0x42200784)
7120#define DMAPRICLR_SPI1RX_MSK (0x1 << 1 )
7121#define DMAPRICLR_SPI1RX (0x1 << 1 )
7122#define DMAPRICLR_SPI1RX_DIS (0x0 << 1 ) /* DIS */
7123#define DMAPRICLR_SPI1RX_EN (0x1 << 1 ) /* EN */
7124
7125/* DMAPRICLR[SPI1TX] - DMA SPI 1 TX */
7126#define DMAPRICLR_SPI1TX_BBA (*(volatile unsigned long *) 0x42200780)
7127#define DMAPRICLR_SPI1TX_MSK (0x1 << 0 )
7128#define DMAPRICLR_SPI1TX (0x1 << 0 )
7129#define DMAPRICLR_SPI1TX_DIS (0x0 << 0 ) /* DIS */
7130#define DMAPRICLR_SPI1TX_EN (0x1 << 0 ) /* EN */
7131
7132/* Reset Value for DMAERRCLR*/
7133#define DMAERRCLR_RVAL 0x0
7134
7135/* DMAERRCLR[ERROR] - DMA Error status */
7136#define DMAERRCLR_ERROR_BBA (*(volatile unsigned long *) 0x42200980)
7137#define DMAERRCLR_ERROR_MSK (0x1 << 0 )
7138#define DMAERRCLR_ERROR (0x1 << 0 )
7139#define DMAERRCLR_ERROR_DIS (0x0 << 0 ) /* DIS */
7140#define DMAERRCLR_ERROR_EN (0x1 << 0 ) /* EN */
7141
7142/* Reset Value for DMABSSET*/
7143#define DMABSSET_RVAL 0x0
7144
7145/* DMABSSET[CHBSWAPSET] - Byte swap status */
7146#define DMABSSET_CHBSWAPSET_MSK (0x3FFF << 0 )
7147
7148/* Reset Value for DMABSCLR*/
7149#define DMABSCLR_RVAL 0x0
7150
7151/* DMABSCLR[CHBSWAPCLR] - Disable byte swap */
7152#define DMABSCLR_CHBSWAPCLR_MSK (0x3FFF << 0 )
7153// ------------------------------------------------------------------------------------------------
7154// ----- NVIC -----
7155// ------------------------------------------------------------------------------------------------
7156
7157
7158/**
7159 * @brief Nested Vectored Interrupt Controller (pADI_NVIC)
7160 */
7161
7162#if (__NO_MMR_STRUCTS__==0)
7163#else // (__NO_MMR_STRUCTS__==0)
7164#define ICTR (*(volatile unsigned long *) 0xE000E004)
7165#define STCSR (*(volatile unsigned long *) 0xE000E010)
7166#define STRVR (*(volatile unsigned long *) 0xE000E014)
7167#define STCVR (*(volatile unsigned long *) 0xE000E018)
7168#define STCR (*(volatile unsigned long *) 0xE000E01C)
7169#define ISER0 (*(volatile unsigned long *) 0xE000E100)
7170#define ISER1 (*(volatile unsigned long *) 0xE000E104)
7171#define ICER0 (*(volatile unsigned long *) 0xE000E180)
7172#define ICER1 (*(volatile unsigned long *) 0xE000E184)
7173#define ISPR0 (*(volatile unsigned long *) 0xE000E200)
7174#define ISPR1 (*(volatile unsigned long *) 0xE000E204)
7175#define ICPR0 (*(volatile unsigned long *) 0xE000E280)
7176#define ICPR1 (*(volatile unsigned long *) 0xE000E284)
7177#define IABR0 (*(volatile unsigned long *) 0xE000E300)
7178#define IABR1 (*(volatile unsigned long *) 0xE000E304)
7179#define IPR0 (*(volatile unsigned long *) 0xE000E400)
7180#define IPR1 (*(volatile unsigned long *) 0xE000E404)
7181#define IPR2 (*(volatile unsigned long *) 0xE000E408)
7182#define IPR3 (*(volatile unsigned long *) 0xE000E40C)
7183#define IPR4 (*(volatile unsigned long *) 0xE000E410)
7184#define IPR5 (*(volatile unsigned long *) 0xE000E414)
7185#define IPR6 (*(volatile unsigned long *) 0xE000E418)
7186#define IPR7 (*(volatile unsigned long *) 0xE000E41C)
7187#define IPR8 (*(volatile unsigned long *) 0xE000E420)
7188#define IPR9 (*(volatile unsigned long *) 0xE000E424)
7189#define CPUID (*(volatile unsigned long *) 0xE000ED00)
7190#define ICSR (*(volatile unsigned long *) 0xE000ED04)
7191#define VTOR (*(volatile unsigned long *) 0xE000ED08)
7192#define AIRCR (*(volatile unsigned long *) 0xE000ED0C)
7193#define SCR (*(volatile unsigned long *) 0xE000ED10)
7194#define CCR (*(volatile unsigned long *) 0xE000ED14)
7195#define SHPR1 (*(volatile unsigned long *) 0xE000ED18)
7196#define SHPR2 (*(volatile unsigned long *) 0xE000ED1C)
7197#define SHPR3 (*(volatile unsigned long *) 0xE000ED20)
7198#define SHCSR (*(volatile unsigned long *) 0xE000ED24)
7199#define CFSR (*(volatile unsigned long *) 0xE000ED28)
7200#define HFSR (*(volatile unsigned long *) 0xE000ED2C)
7201#define MMFAR (*(volatile unsigned long *) 0xE000ED34)
7202#define BFAR (*(volatile unsigned long *) 0xE000ED38)
7203#define STIR (*(volatile unsigned long *) 0xE000EF00)
7204#endif // (__NO_MMR_STRUCTS__==0)
7205
7206/* Reset Value for ICTR*/
7207#define ICTR_RVAL 0x1
7208
7209/* ICTR[INTLINESNUM] - Total number of interrupt lines in groups of 32 */
7210#define ICTR_INTLINESNUM_MSK (0xF << 0 )
7211
7212/* Reset Value for STCSR*/
7213#define STCSR_RVAL 0x0
7214
7215/* STCSR[COUNTFLAG] - Returns 1 if timer counted to 0 since last time this register was read */
7216#define STCSR_COUNTFLAG_MSK (0x1 << 16 )
7217#define STCSR_COUNTFLAG (0x1 << 16 )
7218#define STCSR_COUNTFLAG_DIS (0x0 << 16 ) /* DIS */
7219#define STCSR_COUNTFLAG_EN (0x1 << 16 ) /* EN */
7220
7221/* STCSR[CLKSOURCE] - clock source used for SysTick */
7222#define STCSR_CLKSOURCE_MSK (0x1 << 2 )
7223#define STCSR_CLKSOURCE (0x1 << 2 )
7224#define STCSR_CLKSOURCE_DIS (0x0 << 2 ) /* DIS */
7225#define STCSR_CLKSOURCE_EN (0x1 << 2 ) /* EN */
7226
7227/* STCSR[TICKINT] - If 1, counting down to 0 will cause the SysTick exception to pended. */
7228#define STCSR_TICKINT_MSK (0x1 << 1 )
7229#define STCSR_TICKINT (0x1 << 1 )
7230#define STCSR_TICKINT_DIS (0x0 << 1 ) /* DIS */
7231#define STCSR_TICKINT_EN (0x1 << 1 ) /* EN */
7232
7233/* STCSR[ENABLE] - Enable bit */
7234#define STCSR_ENABLE_MSK (0x1 << 0 )
7235#define STCSR_ENABLE (0x1 << 0 )
7236#define STCSR_ENABLE_DIS (0x0 << 0 ) /* DIS */
7237#define STCSR_ENABLE_EN (0x1 << 0 ) /* EN */
7238
7239/* Reset Value for STRVR*/
7240#define STRVR_RVAL 0x0
7241
7242/* STRVR[RELOAD] - Value to load into the Current Value register when the counter reaches 0 */
7243#define STRVR_RELOAD_MSK (0xFFFFFF << 0 )
7244
7245/* Reset Value for STCVR*/
7246#define STCVR_RVAL 0x0
7247
7248/* STCVR[CURRENT] - Current counter value */
7249#define STCVR_CURRENT_MSK (0xFFFFFFFF << 0 )
7250
7251/* Reset Value for STCR*/
7252#define STCR_RVAL 0x0
7253
7254/* STCR[NOREF] - If reads as 1, the Reference clock is not provided */
7255#define STCR_NOREF_MSK (0x1 << 31 )
7256#define STCR_NOREF (0x1 << 31 )
7257#define STCR_NOREF_DIS (0x0 << 31 ) /* DIS */
7258#define STCR_NOREF_EN (0x1 << 31 ) /* EN */
7259
7260/* STCR[SKEW] - If reads as 1, the calibration value for 10ms is inexact */
7261#define STCR_SKEW_MSK (0x1 << 30 )
7262#define STCR_SKEW (0x1 << 30 )
7263#define STCR_SKEW_DIS (0x0 << 30 ) /* DIS */
7264#define STCR_SKEW_EN (0x1 << 30 ) /* EN */
7265
7266/* STCR[TENMS] - An optional Reload value to be used for 10ms (100Hz) timing */
7267#define STCR_TENMS_MSK (0xFFFFFF << 0 )
7268
7269/* Reset Value for ISER0*/
7270#define ISER0_RVAL 0x0
7271
7272/* ISER0[DMADAC] - */
7273#define ISER0_DMADAC_MSK (0x1 << 31 )
7274#define ISER0_DMADAC (0x1 << 31 )
7275#define ISER0_DMADAC_DIS (0x0 << 31 ) /* DIS */
7276#define ISER0_DMADAC_EN (0x1 << 31 ) /* EN */
7277
7278/* ISER0[DMAI2CMRX] - */
7279#define ISER0_DMAI2CMRX_MSK (0x1 << 30 )
7280#define ISER0_DMAI2CMRX (0x1 << 30 )
7281#define ISER0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
7282#define ISER0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
7283
7284/* ISER0[DMAI2CMTX] - */
7285#define ISER0_DMAI2CMTX_MSK (0x1 << 29 )
7286#define ISER0_DMAI2CMTX (0x1 << 29 )
7287#define ISER0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
7288#define ISER0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
7289
7290/* ISER0[DMAI2CSRX] - */
7291#define ISER0_DMAI2CSRX_MSK (0x1 << 28 )
7292#define ISER0_DMAI2CSRX (0x1 << 28 )
7293#define ISER0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
7294#define ISER0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
7295
7296/* ISER0[DMAI2CSTX] - */
7297#define ISER0_DMAI2CSTX_MSK (0x1 << 27 )
7298#define ISER0_DMAI2CSTX (0x1 << 27 )
7299#define ISER0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
7300#define ISER0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
7301
7302/* ISER0[DMAUARTRX] - */
7303#define ISER0_DMAUARTRX_MSK (0x1 << 26 )
7304#define ISER0_DMAUARTRX (0x1 << 26 )
7305#define ISER0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
7306#define ISER0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
7307
7308/* ISER0[DMAUARTTX] - */
7309#define ISER0_DMAUARTTX_MSK (0x1 << 25 )
7310#define ISER0_DMAUARTTX (0x1 << 25 )
7311#define ISER0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
7312#define ISER0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
7313
7314/* ISER0[DMASPI1RX] - */
7315#define ISER0_DMASPI1RX_MSK (0x1 << 24 )
7316#define ISER0_DMASPI1RX (0x1 << 24 )
7317#define ISER0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
7318#define ISER0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
7319
7320/* ISER0[DMASPI1TX] - */
7321#define ISER0_DMASPI1TX_MSK (0x1 << 23 )
7322#define ISER0_DMASPI1TX (0x1 << 23 )
7323#define ISER0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
7324#define ISER0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
7325
7326/* ISER0[DMAERROR] - */
7327#define ISER0_DMAERROR_MSK (0x1 << 22 )
7328#define ISER0_DMAERROR (0x1 << 22 )
7329#define ISER0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
7330#define ISER0_DMAERROR_EN (0x1 << 22 ) /* EN */
7331
7332/* ISER0[I2CM] - */
7333#define ISER0_I2CM_MSK (0x1 << 21 )
7334#define ISER0_I2CM (0x1 << 21 )
7335#define ISER0_I2CM_DIS (0x0 << 21 ) /* DIS */
7336#define ISER0_I2CM_EN (0x1 << 21 ) /* EN */
7337
7338/* ISER0[I2CS] - */
7339#define ISER0_I2CS_MSK (0x1 << 20 )
7340#define ISER0_I2CS (0x1 << 20 )
7341#define ISER0_I2CS_DIS (0x0 << 20 ) /* DIS */
7342#define ISER0_I2CS_EN (0x1 << 20 ) /* EN */
7343
7344/* ISER0[SPI1] - */
7345#define ISER0_SPI1_MSK (0x1 << 19 )
7346#define ISER0_SPI1 (0x1 << 19 )
7347#define ISER0_SPI1_DIS (0x0 << 19 ) /* DIS */
7348#define ISER0_SPI1_EN (0x1 << 19 ) /* EN */
7349
7350/* ISER0[SPI0] - */
7351#define ISER0_SPI0_MSK (0x1 << 18 )
7352#define ISER0_SPI0 (0x1 << 18 )
7353#define ISER0_SPI0_DIS (0x0 << 18 ) /* DIS */
7354#define ISER0_SPI0_EN (0x1 << 18 ) /* EN */
7355
7356/* ISER0[UART] - */
7357#define ISER0_UART_MSK (0x1 << 17 )
7358#define ISER0_UART (0x1 << 17 )
7359#define ISER0_UART_DIS (0x0 << 17 ) /* DIS */
7360#define ISER0_UART_EN (0x1 << 17 ) /* EN */
7361
7362/* ISER0[FEE] - */
7363#define ISER0_FEE_MSK (0x1 << 16 )
7364#define ISER0_FEE (0x1 << 16 )
7365#define ISER0_FEE_DIS (0x0 << 16 ) /* DIS */
7366#define ISER0_FEE_EN (0x1 << 16 ) /* EN */
7367
7368/* ISER0[SINC2] - */
7369#define ISER0_SINC2_MSK (0x1 << 15 )
7370#define ISER0_SINC2 (0x1 << 15 )
7371#define ISER0_SINC2_DIS (0x0 << 15 ) /* DIS */
7372#define ISER0_SINC2_EN (0x1 << 15 ) /* EN */
7373
7374/* ISER0[ADC1] - */
7375#define ISER0_ADC1_MSK (0x1 << 14 )
7376#define ISER0_ADC1 (0x1 << 14 )
7377#define ISER0_ADC1_DIS (0x0 << 14 ) /* DIS */
7378#define ISER0_ADC1_EN (0x1 << 14 ) /* EN */
7379
7380/* ISER0[T1] - */
7381#define ISER0_T1_MSK (0x1 << 12 )
7382#define ISER0_T1 (0x1 << 12 )
7383#define ISER0_T1_DIS (0x0 << 12 ) /* DIS */
7384#define ISER0_T1_EN (0x1 << 12 ) /* EN */
7385
7386/* ISER0[T0] - */
7387#define ISER0_T0_MSK (0x1 << 11 )
7388#define ISER0_T0 (0x1 << 11 )
7389#define ISER0_T0_DIS (0x0 << 11 ) /* DIS */
7390#define ISER0_T0_EN (0x1 << 11 ) /* EN */
7391
7392/* ISER0[T3] - */
7393#define ISER0_T3_MSK (0x1 << 9 )
7394#define ISER0_T3 (0x1 << 9 )
7395#define ISER0_T3_DIS (0x0 << 9 ) /* DIS */
7396#define ISER0_T3_EN (0x1 << 9 ) /* EN */
7397
7398/* ISER0[EXTINT7] - */
7399#define ISER0_EXTINT7_MSK (0x1 << 8 )
7400#define ISER0_EXTINT7 (0x1 << 8 )
7401#define ISER0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
7402#define ISER0_EXTINT7_EN (0x1 << 8 ) /* EN */
7403
7404/* ISER0[EXTINT6] - */
7405#define ISER0_EXTINT6_MSK (0x1 << 7 )
7406#define ISER0_EXTINT6 (0x1 << 7 )
7407#define ISER0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
7408#define ISER0_EXTINT6_EN (0x1 << 7 ) /* EN */
7409
7410/* ISER0[EXTINT5] - */
7411#define ISER0_EXTINT5_MSK (0x1 << 6 )
7412#define ISER0_EXTINT5 (0x1 << 6 )
7413#define ISER0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
7414#define ISER0_EXTINT5_EN (0x1 << 6 ) /* EN */
7415
7416/* ISER0[EXTINT4] - */
7417#define ISER0_EXTINT4_MSK (0x1 << 5 )
7418#define ISER0_EXTINT4 (0x1 << 5 )
7419#define ISER0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
7420#define ISER0_EXTINT4_EN (0x1 << 5 ) /* EN */
7421
7422/* ISER0[EXTINT3] - */
7423#define ISER0_EXTINT3_MSK (0x1 << 4 )
7424#define ISER0_EXTINT3 (0x1 << 4 )
7425#define ISER0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
7426#define ISER0_EXTINT3_EN (0x1 << 4 ) /* EN */
7427
7428/* ISER0[EXTINT2] - */
7429#define ISER0_EXTINT2_MSK (0x1 << 3 )
7430#define ISER0_EXTINT2 (0x1 << 3 )
7431#define ISER0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
7432#define ISER0_EXTINT2_EN (0x1 << 3 ) /* EN */
7433
7434/* ISER0[EXTINT1] - */
7435#define ISER0_EXTINT1_MSK (0x1 << 2 )
7436#define ISER0_EXTINT1 (0x1 << 2 )
7437#define ISER0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
7438#define ISER0_EXTINT1_EN (0x1 << 2 ) /* EN */
7439
7440/* ISER0[EXTINT0] - */
7441#define ISER0_EXTINT0_MSK (0x1 << 1 )
7442#define ISER0_EXTINT0 (0x1 << 1 )
7443#define ISER0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
7444#define ISER0_EXTINT0_EN (0x1 << 1 ) /* EN */
7445
7446/* ISER0[T2] - */
7447#define ISER0_T2_MSK (0x1 << 0 )
7448#define ISER0_T2 (0x1 << 0 )
7449#define ISER0_T2_DIS (0x0 << 0 ) /* DIS */
7450#define ISER0_T2_EN (0x1 << 0 ) /* EN */
7451
7452/* Reset Value for ISER1*/
7453#define ISER1_RVAL 0x0
7454
7455/* ISER1[PWM2] - */
7456#define ISER1_PWM2_MSK (0x1 << 6 )
7457#define ISER1_PWM2 (0x1 << 6 )
7458#define ISER1_PWM2_DIS (0x0 << 6 ) /* DIS */
7459#define ISER1_PWM2_EN (0x1 << 6 ) /* EN */
7460
7461/* ISER1[PWM1] - */
7462#define ISER1_PWM1_MSK (0x1 << 5 )
7463#define ISER1_PWM1 (0x1 << 5 )
7464#define ISER1_PWM1_DIS (0x0 << 5 ) /* DIS */
7465#define ISER1_PWM1_EN (0x1 << 5 ) /* EN */
7466
7467/* ISER1[PWM0] - */
7468#define ISER1_PWM0_MSK (0x1 << 4 )
7469#define ISER1_PWM0 (0x1 << 4 )
7470#define ISER1_PWM0_DIS (0x0 << 4 ) /* DIS */
7471#define ISER1_PWM0_EN (0x1 << 4 ) /* EN */
7472
7473/* ISER1[PWMTRIP] - */
7474#define ISER1_PWMTRIP_MSK (0x1 << 3 )
7475#define ISER1_PWMTRIP (0x1 << 3 )
7476#define ISER1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
7477#define ISER1_PWMTRIP_EN (0x1 << 3 ) /* EN */
7478
7479/* ISER1[DMASINC2] - */
7480#define ISER1_DMASINC2_MSK (0x1 << 2 )
7481#define ISER1_DMASINC2 (0x1 << 2 )
7482#define ISER1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
7483#define ISER1_DMASINC2_EN (0x1 << 2 ) /* EN */
7484
7485/* ISER1[DMAADC1] - */
7486#define ISER1_DMAADC1_MSK (0x1 << 1 )
7487#define ISER1_DMAADC1 (0x1 << 1 )
7488#define ISER1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
7489#define ISER1_DMAADC1_EN (0x1 << 1 ) /* EN */
7490
7491/* Reset Value for ICER0*/
7492#define ICER0_RVAL 0x0
7493
7494/* ICER0[DMADAC] - */
7495#define ICER0_DMADAC_MSK (0x1 << 31 )
7496#define ICER0_DMADAC (0x1 << 31 )
7497#define ICER0_DMADAC_DIS (0x0 << 31 ) /* DIS */
7498#define ICER0_DMADAC_EN (0x1 << 31 ) /* EN */
7499
7500/* ICER0[DMAI2CMRX] - */
7501#define ICER0_DMAI2CMRX_MSK (0x1 << 30 )
7502#define ICER0_DMAI2CMRX (0x1 << 30 )
7503#define ICER0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
7504#define ICER0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
7505
7506/* ICER0[DMAI2CMTX] - */
7507#define ICER0_DMAI2CMTX_MSK (0x1 << 29 )
7508#define ICER0_DMAI2CMTX (0x1 << 29 )
7509#define ICER0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
7510#define ICER0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
7511
7512/* ICER0[DMAI2CSRX] - */
7513#define ICER0_DMAI2CSRX_MSK (0x1 << 28 )
7514#define ICER0_DMAI2CSRX (0x1 << 28 )
7515#define ICER0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
7516#define ICER0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
7517
7518/* ICER0[DMAI2CSTX] - */
7519#define ICER0_DMAI2CSTX_MSK (0x1 << 27 )
7520#define ICER0_DMAI2CSTX (0x1 << 27 )
7521#define ICER0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
7522#define ICER0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
7523
7524/* ICER0[DMAUARTRX] - */
7525#define ICER0_DMAUARTRX_MSK (0x1 << 26 )
7526#define ICER0_DMAUARTRX (0x1 << 26 )
7527#define ICER0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
7528#define ICER0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
7529
7530/* ICER0[DMAUARTTX] - */
7531#define ICER0_DMAUARTTX_MSK (0x1 << 25 )
7532#define ICER0_DMAUARTTX (0x1 << 25 )
7533#define ICER0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
7534#define ICER0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
7535
7536/* ICER0[DMASPI1RX] - */
7537#define ICER0_DMASPI1RX_MSK (0x1 << 24 )
7538#define ICER0_DMASPI1RX (0x1 << 24 )
7539#define ICER0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
7540#define ICER0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
7541
7542/* ICER0[DMASPI1TX] - */
7543#define ICER0_DMASPI1TX_MSK (0x1 << 23 )
7544#define ICER0_DMASPI1TX (0x1 << 23 )
7545#define ICER0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
7546#define ICER0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
7547
7548/* ICER0[DMAERROR] - */
7549#define ICER0_DMAERROR_MSK (0x1 << 22 )
7550#define ICER0_DMAERROR (0x1 << 22 )
7551#define ICER0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
7552#define ICER0_DMAERROR_EN (0x1 << 22 ) /* EN */
7553
7554/* ICER0[I2CM] - */
7555#define ICER0_I2CM_MSK (0x1 << 21 )
7556#define ICER0_I2CM (0x1 << 21 )
7557#define ICER0_I2CM_DIS (0x0 << 21 ) /* DIS */
7558#define ICER0_I2CM_EN (0x1 << 21 ) /* EN */
7559
7560/* ICER0[I2CS] - */
7561#define ICER0_I2CS_MSK (0x1 << 20 )
7562#define ICER0_I2CS (0x1 << 20 )
7563#define ICER0_I2CS_DIS (0x0 << 20 ) /* DIS */
7564#define ICER0_I2CS_EN (0x1 << 20 ) /* EN */
7565
7566/* ICER0[SPI1] - */
7567#define ICER0_SPI1_MSK (0x1 << 19 )
7568#define ICER0_SPI1 (0x1 << 19 )
7569#define ICER0_SPI1_DIS (0x0 << 19 ) /* DIS */
7570#define ICER0_SPI1_EN (0x1 << 19 ) /* EN */
7571
7572/* ICER0[SPI0] - */
7573#define ICER0_SPI0_MSK (0x1 << 18 )
7574#define ICER0_SPI0 (0x1 << 18 )
7575#define ICER0_SPI0_DIS (0x0 << 18 ) /* DIS */
7576#define ICER0_SPI0_EN (0x1 << 18 ) /* EN */
7577
7578/* ICER0[UART] - */
7579#define ICER0_UART_MSK (0x1 << 17 )
7580#define ICER0_UART (0x1 << 17 )
7581#define ICER0_UART_DIS (0x0 << 17 ) /* DIS */
7582#define ICER0_UART_EN (0x1 << 17 ) /* EN */
7583
7584/* ICER0[FEE] - */
7585#define ICER0_FEE_MSK (0x1 << 16 )
7586#define ICER0_FEE (0x1 << 16 )
7587#define ICER0_FEE_DIS (0x0 << 16 ) /* DIS */
7588#define ICER0_FEE_EN (0x1 << 16 ) /* EN */
7589
7590/* ICER0[SINC2] - */
7591#define ICER0_SINC2_MSK (0x1 << 15 )
7592#define ICER0_SINC2 (0x1 << 15 )
7593#define ICER0_SINC2_DIS (0x0 << 15 ) /* DIS */
7594#define ICER0_SINC2_EN (0x1 << 15 ) /* EN */
7595
7596/* ICER0[ADC1] - */
7597#define ICER0_ADC1_MSK (0x1 << 14 )
7598#define ICER0_ADC1 (0x1 << 14 )
7599#define ICER0_ADC1_DIS (0x0 << 14 ) /* DIS */
7600#define ICER0_ADC1_EN (0x1 << 14 ) /* EN */
7601
7602/* ICER0[T1] - */
7603#define ICER0_T1_MSK (0x1 << 12 )
7604#define ICER0_T1 (0x1 << 12 )
7605#define ICER0_T1_DIS (0x0 << 12 ) /* DIS */
7606#define ICER0_T1_EN (0x1 << 12 ) /* EN */
7607
7608/* ICER0[T0] - */
7609#define ICER0_T0_MSK (0x1 << 11 )
7610#define ICER0_T0 (0x1 << 11 )
7611#define ICER0_T0_DIS (0x0 << 11 ) /* DIS */
7612#define ICER0_T0_EN (0x1 << 11 ) /* EN */
7613
7614/* ICER0[T3] - */
7615#define ICER0_T3_MSK (0x1 << 9 )
7616#define ICER0_T3 (0x1 << 9 )
7617#define ICER0_T3_DIS (0x0 << 9 ) /* DIS */
7618#define ICER0_T3_EN (0x1 << 9 ) /* EN */
7619
7620/* ICER0[EXTINT7] - */
7621#define ICER0_EXTINT7_MSK (0x1 << 8 )
7622#define ICER0_EXTINT7 (0x1 << 8 )
7623#define ICER0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
7624#define ICER0_EXTINT7_EN (0x1 << 8 ) /* EN */
7625
7626/* ICER0[EXTINT6] - */
7627#define ICER0_EXTINT6_MSK (0x1 << 7 )
7628#define ICER0_EXTINT6 (0x1 << 7 )
7629#define ICER0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
7630#define ICER0_EXTINT6_EN (0x1 << 7 ) /* EN */
7631
7632/* ICER0[EXTINT5] - */
7633#define ICER0_EXTINT5_MSK (0x1 << 6 )
7634#define ICER0_EXTINT5 (0x1 << 6 )
7635#define ICER0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
7636#define ICER0_EXTINT5_EN (0x1 << 6 ) /* EN */
7637
7638/* ICER0[EXTINT4] - */
7639#define ICER0_EXTINT4_MSK (0x1 << 5 )
7640#define ICER0_EXTINT4 (0x1 << 5 )
7641#define ICER0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
7642#define ICER0_EXTINT4_EN (0x1 << 5 ) /* EN */
7643
7644/* ICER0[EXTINT3] - */
7645#define ICER0_EXTINT3_MSK (0x1 << 4 )
7646#define ICER0_EXTINT3 (0x1 << 4 )
7647#define ICER0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
7648#define ICER0_EXTINT3_EN (0x1 << 4 ) /* EN */
7649
7650/* ICER0[EXTINT2] - */
7651#define ICER0_EXTINT2_MSK (0x1 << 3 )
7652#define ICER0_EXTINT2 (0x1 << 3 )
7653#define ICER0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
7654#define ICER0_EXTINT2_EN (0x1 << 3 ) /* EN */
7655
7656/* ICER0[EXTINT1] - */
7657#define ICER0_EXTINT1_MSK (0x1 << 2 )
7658#define ICER0_EXTINT1 (0x1 << 2 )
7659#define ICER0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
7660#define ICER0_EXTINT1_EN (0x1 << 2 ) /* EN */
7661
7662/* ICER0[EXTINT0] - */
7663#define ICER0_EXTINT0_MSK (0x1 << 1 )
7664#define ICER0_EXTINT0 (0x1 << 1 )
7665#define ICER0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
7666#define ICER0_EXTINT0_EN (0x1 << 1 ) /* EN */
7667
7668/* ICER0[T2] - */
7669#define ICER0_T2_MSK (0x1 << 0 )
7670#define ICER0_T2 (0x1 << 0 )
7671#define ICER0_T2_DIS (0x0 << 0 ) /* DIS */
7672#define ICER0_T2_EN (0x1 << 0 ) /* EN */
7673
7674/* Reset Value for ICER1*/
7675#define ICER1_RVAL 0x0
7676
7677/* ICER1[PWM2] - */
7678#define ICER1_PWM2_MSK (0x1 << 6 )
7679#define ICER1_PWM2 (0x1 << 6 )
7680#define ICER1_PWM2_DIS (0x0 << 6 ) /* DIS */
7681#define ICER1_PWM2_EN (0x1 << 6 ) /* EN */
7682
7683/* ICER1[PWM1] - */
7684#define ICER1_PWM1_MSK (0x1 << 5 )
7685#define ICER1_PWM1 (0x1 << 5 )
7686#define ICER1_PWM1_DIS (0x0 << 5 ) /* DIS */
7687#define ICER1_PWM1_EN (0x1 << 5 ) /* EN */
7688
7689/* ICER1[PWM0] - */
7690#define ICER1_PWM0_MSK (0x1 << 4 )
7691#define ICER1_PWM0 (0x1 << 4 )
7692#define ICER1_PWM0_DIS (0x0 << 4 ) /* DIS */
7693#define ICER1_PWM0_EN (0x1 << 4 ) /* EN */
7694
7695/* ICER1[PWMTRIP] - */
7696#define ICER1_PWMTRIP_MSK (0x1 << 3 )
7697#define ICER1_PWMTRIP (0x1 << 3 )
7698#define ICER1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
7699#define ICER1_PWMTRIP_EN (0x1 << 3 ) /* EN */
7700
7701/* ICER1[DMASINC2] - */
7702#define ICER1_DMASINC2_MSK (0x1 << 2 )
7703#define ICER1_DMASINC2 (0x1 << 2 )
7704#define ICER1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
7705#define ICER1_DMASINC2_EN (0x1 << 2 ) /* EN */
7706
7707/* ICER1[DMAADC1] - */
7708#define ICER1_DMAADC1_MSK (0x1 << 1 )
7709#define ICER1_DMAADC1 (0x1 << 1 )
7710#define ICER1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
7711#define ICER1_DMAADC1_EN (0x1 << 1 ) /* EN */
7712
7713/* Reset Value for ISPR0*/
7714#define ISPR0_RVAL 0x0
7715
7716/* ISPR0[DMADAC] - */
7717#define ISPR0_DMADAC_MSK (0x1 << 31 )
7718#define ISPR0_DMADAC (0x1 << 31 )
7719#define ISPR0_DMADAC_DIS (0x0 << 31 ) /* DIS */
7720#define ISPR0_DMADAC_EN (0x1 << 31 ) /* EN */
7721
7722/* ISPR0[DMAI2CMRX] - */
7723#define ISPR0_DMAI2CMRX_MSK (0x1 << 30 )
7724#define ISPR0_DMAI2CMRX (0x1 << 30 )
7725#define ISPR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
7726#define ISPR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
7727
7728/* ISPR0[DMAI2CMTX] - */
7729#define ISPR0_DMAI2CMTX_MSK (0x1 << 29 )
7730#define ISPR0_DMAI2CMTX (0x1 << 29 )
7731#define ISPR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
7732#define ISPR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
7733
7734/* ISPR0[DMAI2CSRX] - */
7735#define ISPR0_DMAI2CSRX_MSK (0x1 << 28 )
7736#define ISPR0_DMAI2CSRX (0x1 << 28 )
7737#define ISPR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
7738#define ISPR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
7739
7740/* ISPR0[DMAI2CSTX] - */
7741#define ISPR0_DMAI2CSTX_MSK (0x1 << 27 )
7742#define ISPR0_DMAI2CSTX (0x1 << 27 )
7743#define ISPR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
7744#define ISPR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
7745
7746/* ISPR0[DMAUARTRX] - */
7747#define ISPR0_DMAUARTRX_MSK (0x1 << 26 )
7748#define ISPR0_DMAUARTRX (0x1 << 26 )
7749#define ISPR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
7750#define ISPR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
7751
7752/* ISPR0[DMAUARTTX] - */
7753#define ISPR0_DMAUARTTX_MSK (0x1 << 25 )
7754#define ISPR0_DMAUARTTX (0x1 << 25 )
7755#define ISPR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
7756#define ISPR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
7757
7758/* ISPR0[DMASPI1RX] - */
7759#define ISPR0_DMASPI1RX_MSK (0x1 << 24 )
7760#define ISPR0_DMASPI1RX (0x1 << 24 )
7761#define ISPR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
7762#define ISPR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
7763
7764/* ISPR0[DMASPI1TX] - */
7765#define ISPR0_DMASPI1TX_MSK (0x1 << 23 )
7766#define ISPR0_DMASPI1TX (0x1 << 23 )
7767#define ISPR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
7768#define ISPR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
7769
7770/* ISPR0[DMAERROR] - */
7771#define ISPR0_DMAERROR_MSK (0x1 << 22 )
7772#define ISPR0_DMAERROR (0x1 << 22 )
7773#define ISPR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
7774#define ISPR0_DMAERROR_EN (0x1 << 22 ) /* EN */
7775
7776/* ISPR0[I2CM] - */
7777#define ISPR0_I2CM_MSK (0x1 << 21 )
7778#define ISPR0_I2CM (0x1 << 21 )
7779#define ISPR0_I2CM_DIS (0x0 << 21 ) /* DIS */
7780#define ISPR0_I2CM_EN (0x1 << 21 ) /* EN */
7781
7782/* ISPR0[I2CS] - */
7783#define ISPR0_I2CS_MSK (0x1 << 20 )
7784#define ISPR0_I2CS (0x1 << 20 )
7785#define ISPR0_I2CS_DIS (0x0 << 20 ) /* DIS */
7786#define ISPR0_I2CS_EN (0x1 << 20 ) /* EN */
7787
7788/* ISPR0[SPI1] - */
7789#define ISPR0_SPI1_MSK (0x1 << 19 )
7790#define ISPR0_SPI1 (0x1 << 19 )
7791#define ISPR0_SPI1_DIS (0x0 << 19 ) /* DIS */
7792#define ISPR0_SPI1_EN (0x1 << 19 ) /* EN */
7793
7794/* ISPR0[SPI0] - */
7795#define ISPR0_SPI0_MSK (0x1 << 18 )
7796#define ISPR0_SPI0 (0x1 << 18 )
7797#define ISPR0_SPI0_DIS (0x0 << 18 ) /* DIS */
7798#define ISPR0_SPI0_EN (0x1 << 18 ) /* EN */
7799
7800/* ISPR0[UART] - */
7801#define ISPR0_UART_MSK (0x1 << 17 )
7802#define ISPR0_UART (0x1 << 17 )
7803#define ISPR0_UART_DIS (0x0 << 17 ) /* DIS */
7804#define ISPR0_UART_EN (0x1 << 17 ) /* EN */
7805
7806/* ISPR0[FEE] - */
7807#define ISPR0_FEE_MSK (0x1 << 16 )
7808#define ISPR0_FEE (0x1 << 16 )
7809#define ISPR0_FEE_DIS (0x0 << 16 ) /* DIS */
7810#define ISPR0_FEE_EN (0x1 << 16 ) /* EN */
7811
7812/* ISPR0[SINC2] - */
7813#define ISPR0_SINC2_MSK (0x1 << 15 )
7814#define ISPR0_SINC2 (0x1 << 15 )
7815#define ISPR0_SINC2_DIS (0x0 << 15 ) /* DIS */
7816#define ISPR0_SINC2_EN (0x1 << 15 ) /* EN */
7817
7818/* ISPR0[ADC1] - */
7819#define ISPR0_ADC1_MSK (0x1 << 14 )
7820#define ISPR0_ADC1 (0x1 << 14 )
7821#define ISPR0_ADC1_DIS (0x0 << 14 ) /* DIS */
7822#define ISPR0_ADC1_EN (0x1 << 14 ) /* EN */
7823
7824/* ISPR0[T1] - */
7825#define ISPR0_T1_MSK (0x1 << 12 )
7826#define ISPR0_T1 (0x1 << 12 )
7827#define ISPR0_T1_DIS (0x0 << 12 ) /* DIS */
7828#define ISPR0_T1_EN (0x1 << 12 ) /* EN */
7829
7830/* ISPR0[T0] - */
7831#define ISPR0_T0_MSK (0x1 << 11 )
7832#define ISPR0_T0 (0x1 << 11 )
7833#define ISPR0_T0_DIS (0x0 << 11 ) /* DIS */
7834#define ISPR0_T0_EN (0x1 << 11 ) /* EN */
7835
7836/* ISPR0[T3] - */
7837#define ISPR0_T3_MSK (0x1 << 9 )
7838#define ISPR0_T3 (0x1 << 9 )
7839#define ISPR0_T3_DIS (0x0 << 9 ) /* DIS */
7840#define ISPR0_T3_EN (0x1 << 9 ) /* EN */
7841
7842/* ISPR0[EXTINT7] - */
7843#define ISPR0_EXTINT7_MSK (0x1 << 8 )
7844#define ISPR0_EXTINT7 (0x1 << 8 )
7845#define ISPR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
7846#define ISPR0_EXTINT7_EN (0x1 << 8 ) /* EN */
7847
7848/* ISPR0[EXTINT6] - */
7849#define ISPR0_EXTINT6_MSK (0x1 << 7 )
7850#define ISPR0_EXTINT6 (0x1 << 7 )
7851#define ISPR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
7852#define ISPR0_EXTINT6_EN (0x1 << 7 ) /* EN */
7853
7854/* ISPR0[EXTINT5] - */
7855#define ISPR0_EXTINT5_MSK (0x1 << 6 )
7856#define ISPR0_EXTINT5 (0x1 << 6 )
7857#define ISPR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
7858#define ISPR0_EXTINT5_EN (0x1 << 6 ) /* EN */
7859
7860/* ISPR0[EXTINT4] - */
7861#define ISPR0_EXTINT4_MSK (0x1 << 5 )
7862#define ISPR0_EXTINT4 (0x1 << 5 )
7863#define ISPR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
7864#define ISPR0_EXTINT4_EN (0x1 << 5 ) /* EN */
7865
7866/* ISPR0[EXTINT3] - */
7867#define ISPR0_EXTINT3_MSK (0x1 << 4 )
7868#define ISPR0_EXTINT3 (0x1 << 4 )
7869#define ISPR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
7870#define ISPR0_EXTINT3_EN (0x1 << 4 ) /* EN */
7871
7872/* ISPR0[EXTINT2] - */
7873#define ISPR0_EXTINT2_MSK (0x1 << 3 )
7874#define ISPR0_EXTINT2 (0x1 << 3 )
7875#define ISPR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
7876#define ISPR0_EXTINT2_EN (0x1 << 3 ) /* EN */
7877
7878/* ISPR0[EXTINT1] - */
7879#define ISPR0_EXTINT1_MSK (0x1 << 2 )
7880#define ISPR0_EXTINT1 (0x1 << 2 )
7881#define ISPR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
7882#define ISPR0_EXTINT1_EN (0x1 << 2 ) /* EN */
7883
7884/* ISPR0[EXTINT0] - */
7885#define ISPR0_EXTINT0_MSK (0x1 << 1 )
7886#define ISPR0_EXTINT0 (0x1 << 1 )
7887#define ISPR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
7888#define ISPR0_EXTINT0_EN (0x1 << 1 ) /* EN */
7889
7890/* ISPR0[T2] - */
7891#define ISPR0_T2_MSK (0x1 << 0 )
7892#define ISPR0_T2 (0x1 << 0 )
7893#define ISPR0_T2_DIS (0x0 << 0 ) /* DIS */
7894#define ISPR0_T2_EN (0x1 << 0 ) /* EN */
7895
7896/* Reset Value for ISPR1*/
7897#define ISPR1_RVAL 0x0
7898
7899/* ISPR1[PWM2] - */
7900#define ISPR1_PWM2_MSK (0x1 << 6 )
7901#define ISPR1_PWM2 (0x1 << 6 )
7902#define ISPR1_PWM2_DIS (0x0 << 6 ) /* DIS */
7903#define ISPR1_PWM2_EN (0x1 << 6 ) /* EN */
7904
7905/* ISPR1[PWM1] - */
7906#define ISPR1_PWM1_MSK (0x1 << 5 )
7907#define ISPR1_PWM1 (0x1 << 5 )
7908#define ISPR1_PWM1_DIS (0x0 << 5 ) /* DIS */
7909#define ISPR1_PWM1_EN (0x1 << 5 ) /* EN */
7910
7911/* ISPR1[PWM0] - */
7912#define ISPR1_PWM0_MSK (0x1 << 4 )
7913#define ISPR1_PWM0 (0x1 << 4 )
7914#define ISPR1_PWM0_DIS (0x0 << 4 ) /* DIS */
7915#define ISPR1_PWM0_EN (0x1 << 4 ) /* EN */
7916
7917/* ISPR1[PWMTRIP] - */
7918#define ISPR1_PWMTRIP_MSK (0x1 << 3 )
7919#define ISPR1_PWMTRIP (0x1 << 3 )
7920#define ISPR1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
7921#define ISPR1_PWMTRIP_EN (0x1 << 3 ) /* EN */
7922
7923/* ISPR1[DMASINC2] - */
7924#define ISPR1_DMASINC2_MSK (0x1 << 2 )
7925#define ISPR1_DMASINC2 (0x1 << 2 )
7926#define ISPR1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
7927#define ISPR1_DMASINC2_EN (0x1 << 2 ) /* EN */
7928
7929/* ISPR1[DMAADC1] - */
7930#define ISPR1_DMAADC1_MSK (0x1 << 1 )
7931#define ISPR1_DMAADC1 (0x1 << 1 )
7932#define ISPR1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
7933#define ISPR1_DMAADC1_EN (0x1 << 1 ) /* EN */
7934
7935/* Reset Value for ICPR0*/
7936#define ICPR0_RVAL 0x0
7937
7938/* ICPR0[DMADAC] - */
7939#define ICPR0_DMADAC_MSK (0x1 << 31 )
7940#define ICPR0_DMADAC (0x1 << 31 )
7941#define ICPR0_DMADAC_DIS (0x0 << 31 ) /* DIS */
7942#define ICPR0_DMADAC_EN (0x1 << 31 ) /* EN */
7943
7944/* ICPR0[DMAI2CMRX] - */
7945#define ICPR0_DMAI2CMRX_MSK (0x1 << 30 )
7946#define ICPR0_DMAI2CMRX (0x1 << 30 )
7947#define ICPR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
7948#define ICPR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
7949
7950/* ICPR0[DMAI2CMTX] - */
7951#define ICPR0_DMAI2CMTX_MSK (0x1 << 29 )
7952#define ICPR0_DMAI2CMTX (0x1 << 29 )
7953#define ICPR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
7954#define ICPR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
7955
7956/* ICPR0[DMAI2CSRX] - */
7957#define ICPR0_DMAI2CSRX_MSK (0x1 << 28 )
7958#define ICPR0_DMAI2CSRX (0x1 << 28 )
7959#define ICPR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
7960#define ICPR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
7961
7962/* ICPR0[DMAI2CSTX] - */
7963#define ICPR0_DMAI2CSTX_MSK (0x1 << 27 )
7964#define ICPR0_DMAI2CSTX (0x1 << 27 )
7965#define ICPR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
7966#define ICPR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
7967
7968/* ICPR0[DMAUARTRX] - */
7969#define ICPR0_DMAUARTRX_MSK (0x1 << 26 )
7970#define ICPR0_DMAUARTRX (0x1 << 26 )
7971#define ICPR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
7972#define ICPR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
7973
7974/* ICPR0[DMAUARTTX] - */
7975#define ICPR0_DMAUARTTX_MSK (0x1 << 25 )
7976#define ICPR0_DMAUARTTX (0x1 << 25 )
7977#define ICPR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
7978#define ICPR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
7979
7980/* ICPR0[DMASPI1RX] - */
7981#define ICPR0_DMASPI1RX_MSK (0x1 << 24 )
7982#define ICPR0_DMASPI1RX (0x1 << 24 )
7983#define ICPR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
7984#define ICPR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
7985
7986/* ICPR0[DMASPI1TX] - */
7987#define ICPR0_DMASPI1TX_MSK (0x1 << 23 )
7988#define ICPR0_DMASPI1TX (0x1 << 23 )
7989#define ICPR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
7990#define ICPR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
7991
7992/* ICPR0[DMAERROR] - */
7993#define ICPR0_DMAERROR_MSK (0x1 << 22 )
7994#define ICPR0_DMAERROR (0x1 << 22 )
7995#define ICPR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
7996#define ICPR0_DMAERROR_EN (0x1 << 22 ) /* EN */
7997
7998/* ICPR0[I2CM] - */
7999#define ICPR0_I2CM_MSK (0x1 << 21 )
8000#define ICPR0_I2CM (0x1 << 21 )
8001#define ICPR0_I2CM_DIS (0x0 << 21 ) /* DIS */
8002#define ICPR0_I2CM_EN (0x1 << 21 ) /* EN */
8003
8004/* ICPR0[I2CS] - */
8005#define ICPR0_I2CS_MSK (0x1 << 20 )
8006#define ICPR0_I2CS (0x1 << 20 )
8007#define ICPR0_I2CS_DIS (0x0 << 20 ) /* DIS */
8008#define ICPR0_I2CS_EN (0x1 << 20 ) /* EN */
8009
8010/* ICPR0[SPI1] - */
8011#define ICPR0_SPI1_MSK (0x1 << 19 )
8012#define ICPR0_SPI1 (0x1 << 19 )
8013#define ICPR0_SPI1_DIS (0x0 << 19 ) /* DIS */
8014#define ICPR0_SPI1_EN (0x1 << 19 ) /* EN */
8015
8016/* ICPR0[SPI0] - */
8017#define ICPR0_SPI0_MSK (0x1 << 18 )
8018#define ICPR0_SPI0 (0x1 << 18 )
8019#define ICPR0_SPI0_DIS (0x0 << 18 ) /* DIS */
8020#define ICPR0_SPI0_EN (0x1 << 18 ) /* EN */
8021
8022/* ICPR0[UART] - */
8023#define ICPR0_UART_MSK (0x1 << 17 )
8024#define ICPR0_UART (0x1 << 17 )
8025#define ICPR0_UART_DIS (0x0 << 17 ) /* DIS */
8026#define ICPR0_UART_EN (0x1 << 17 ) /* EN */
8027
8028/* ICPR0[FEE] - */
8029#define ICPR0_FEE_MSK (0x1 << 16 )
8030#define ICPR0_FEE (0x1 << 16 )
8031#define ICPR0_FEE_DIS (0x0 << 16 ) /* DIS */
8032#define ICPR0_FEE_EN (0x1 << 16 ) /* EN */
8033
8034/* ICPR0[SINC2] - */
8035#define ICPR0_SINC2_MSK (0x1 << 15 )
8036#define ICPR0_SINC2 (0x1 << 15 )
8037#define ICPR0_SINC2_DIS (0x0 << 15 ) /* DIS */
8038#define ICPR0_SINC2_EN (0x1 << 15 ) /* EN */
8039
8040/* ICPR0[ADC1] - */
8041#define ICPR0_ADC1_MSK (0x1 << 14 )
8042#define ICPR0_ADC1 (0x1 << 14 )
8043#define ICPR0_ADC1_DIS (0x0 << 14 ) /* DIS */
8044#define ICPR0_ADC1_EN (0x1 << 14 ) /* EN */
8045
8046/* ICPR0[T1] - */
8047#define ICPR0_T1_MSK (0x1 << 12 )
8048#define ICPR0_T1 (0x1 << 12 )
8049#define ICPR0_T1_DIS (0x0 << 12 ) /* DIS */
8050#define ICPR0_T1_EN (0x1 << 12 ) /* EN */
8051
8052/* ICPR0[T0] - */
8053#define ICPR0_T0_MSK (0x1 << 11 )
8054#define ICPR0_T0 (0x1 << 11 )
8055#define ICPR0_T0_DIS (0x0 << 11 ) /* DIS */
8056#define ICPR0_T0_EN (0x1 << 11 ) /* EN */
8057
8058/* ICPR0[T3] - */
8059#define ICPR0_T3_MSK (0x1 << 9 )
8060#define ICPR0_T3 (0x1 << 9 )
8061#define ICPR0_T3_DIS (0x0 << 9 ) /* DIS */
8062#define ICPR0_T3_EN (0x1 << 9 ) /* EN */
8063
8064/* ICPR0[EXTINT7] - */
8065#define ICPR0_EXTINT7_MSK (0x1 << 8 )
8066#define ICPR0_EXTINT7 (0x1 << 8 )
8067#define ICPR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
8068#define ICPR0_EXTINT7_EN (0x1 << 8 ) /* EN */
8069
8070/* ICPR0[EXTINT6] - */
8071#define ICPR0_EXTINT6_MSK (0x1 << 7 )
8072#define ICPR0_EXTINT6 (0x1 << 7 )
8073#define ICPR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
8074#define ICPR0_EXTINT6_EN (0x1 << 7 ) /* EN */
8075
8076/* ICPR0[EXTINT5] - */
8077#define ICPR0_EXTINT5_MSK (0x1 << 6 )
8078#define ICPR0_EXTINT5 (0x1 << 6 )
8079#define ICPR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
8080#define ICPR0_EXTINT5_EN (0x1 << 6 ) /* EN */
8081
8082/* ICPR0[EXTINT4] - */
8083#define ICPR0_EXTINT4_MSK (0x1 << 5 )
8084#define ICPR0_EXTINT4 (0x1 << 5 )
8085#define ICPR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
8086#define ICPR0_EXTINT4_EN (0x1 << 5 ) /* EN */
8087
8088/* ICPR0[EXTINT3] - */
8089#define ICPR0_EXTINT3_MSK (0x1 << 4 )
8090#define ICPR0_EXTINT3 (0x1 << 4 )
8091#define ICPR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
8092#define ICPR0_EXTINT3_EN (0x1 << 4 ) /* EN */
8093
8094/* ICPR0[EXTINT2] - */
8095#define ICPR0_EXTINT2_MSK (0x1 << 3 )
8096#define ICPR0_EXTINT2 (0x1 << 3 )
8097#define ICPR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
8098#define ICPR0_EXTINT2_EN (0x1 << 3 ) /* EN */
8099
8100/* ICPR0[EXTINT1] - */
8101#define ICPR0_EXTINT1_MSK (0x1 << 2 )
8102#define ICPR0_EXTINT1 (0x1 << 2 )
8103#define ICPR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
8104#define ICPR0_EXTINT1_EN (0x1 << 2 ) /* EN */
8105
8106/* ICPR0[EXTINT0] - */
8107#define ICPR0_EXTINT0_MSK (0x1 << 1 )
8108#define ICPR0_EXTINT0 (0x1 << 1 )
8109#define ICPR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
8110#define ICPR0_EXTINT0_EN (0x1 << 1 ) /* EN */
8111
8112/* ICPR0[T2] - */
8113#define ICPR0_T2_MSK (0x1 << 0 )
8114#define ICPR0_T2 (0x1 << 0 )
8115#define ICPR0_T2_DIS (0x0 << 0 ) /* DIS */
8116#define ICPR0_T2_EN (0x1 << 0 ) /* EN */
8117
8118/* Reset Value for ICPR1*/
8119#define ICPR1_RVAL 0x0
8120
8121/* ICPR1[PWM2] - */
8122#define ICPR1_PWM2_MSK (0x1 << 6 )
8123#define ICPR1_PWM2 (0x1 << 6 )
8124#define ICPR1_PWM2_DIS (0x0 << 6 ) /* DIS */
8125#define ICPR1_PWM2_EN (0x1 << 6 ) /* EN */
8126
8127/* ICPR1[PWM1] - */
8128#define ICPR1_PWM1_MSK (0x1 << 5 )
8129#define ICPR1_PWM1 (0x1 << 5 )
8130#define ICPR1_PWM1_DIS (0x0 << 5 ) /* DIS */
8131#define ICPR1_PWM1_EN (0x1 << 5 ) /* EN */
8132
8133/* ICPR1[PWM0] - */
8134#define ICPR1_PWM0_MSK (0x1 << 4 )
8135#define ICPR1_PWM0 (0x1 << 4 )
8136#define ICPR1_PWM0_DIS (0x0 << 4 ) /* DIS */
8137#define ICPR1_PWM0_EN (0x1 << 4 ) /* EN */
8138
8139/* ICPR1[PWMTRIP] - */
8140#define ICPR1_PWMTRIP_MSK (0x1 << 3 )
8141#define ICPR1_PWMTRIP (0x1 << 3 )
8142#define ICPR1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
8143#define ICPR1_PWMTRIP_EN (0x1 << 3 ) /* EN */
8144
8145/* ICPR1[DMASINC2] - */
8146#define ICPR1_DMASINC2_MSK (0x1 << 2 )
8147#define ICPR1_DMASINC2 (0x1 << 2 )
8148#define ICPR1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
8149#define ICPR1_DMASINC2_EN (0x1 << 2 ) /* EN */
8150
8151/* ICPR1[DMAADC1] - */
8152#define ICPR1_DMAADC1_MSK (0x1 << 1 )
8153#define ICPR1_DMAADC1 (0x1 << 1 )
8154#define ICPR1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
8155#define ICPR1_DMAADC1_EN (0x1 << 1 ) /* EN */
8156
8157/* Reset Value for IABR0*/
8158#define IABR0_RVAL 0x0
8159
8160/* IABR0[DMADAC] - */
8161#define IABR0_DMADAC_MSK (0x1 << 31 )
8162#define IABR0_DMADAC (0x1 << 31 )
8163#define IABR0_DMADAC_DIS (0x0 << 31 ) /* DIS */
8164#define IABR0_DMADAC_EN (0x1 << 31 ) /* EN */
8165
8166/* IABR0[DMAI2CMRX] - */
8167#define IABR0_DMAI2CMRX_MSK (0x1 << 30 )
8168#define IABR0_DMAI2CMRX (0x1 << 30 )
8169#define IABR0_DMAI2CMRX_DIS (0x0 << 30 ) /* DIS */
8170#define IABR0_DMAI2CMRX_EN (0x1 << 30 ) /* EN */
8171
8172/* IABR0[DMAI2CMTX] - */
8173#define IABR0_DMAI2CMTX_MSK (0x1 << 29 )
8174#define IABR0_DMAI2CMTX (0x1 << 29 )
8175#define IABR0_DMAI2CMTX_DIS (0x0 << 29 ) /* DIS */
8176#define IABR0_DMAI2CMTX_EN (0x1 << 29 ) /* EN */
8177
8178/* IABR0[DMAI2CSRX] - */
8179#define IABR0_DMAI2CSRX_MSK (0x1 << 28 )
8180#define IABR0_DMAI2CSRX (0x1 << 28 )
8181#define IABR0_DMAI2CSRX_DIS (0x0 << 28 ) /* DIS */
8182#define IABR0_DMAI2CSRX_EN (0x1 << 28 ) /* EN */
8183
8184/* IABR0[DMAI2CSTX] - */
8185#define IABR0_DMAI2CSTX_MSK (0x1 << 27 )
8186#define IABR0_DMAI2CSTX (0x1 << 27 )
8187#define IABR0_DMAI2CSTX_DIS (0x0 << 27 ) /* DIS */
8188#define IABR0_DMAI2CSTX_EN (0x1 << 27 ) /* EN */
8189
8190/* IABR0[DMAUARTRX] - */
8191#define IABR0_DMAUARTRX_MSK (0x1 << 26 )
8192#define IABR0_DMAUARTRX (0x1 << 26 )
8193#define IABR0_DMAUARTRX_DIS (0x0 << 26 ) /* DIS */
8194#define IABR0_DMAUARTRX_EN (0x1 << 26 ) /* EN */
8195
8196/* IABR0[DMAUARTTX] - */
8197#define IABR0_DMAUARTTX_MSK (0x1 << 25 )
8198#define IABR0_DMAUARTTX (0x1 << 25 )
8199#define IABR0_DMAUARTTX_DIS (0x0 << 25 ) /* DIS */
8200#define IABR0_DMAUARTTX_EN (0x1 << 25 ) /* EN */
8201
8202/* IABR0[DMASPI1RX] - */
8203#define IABR0_DMASPI1RX_MSK (0x1 << 24 )
8204#define IABR0_DMASPI1RX (0x1 << 24 )
8205#define IABR0_DMASPI1RX_DIS (0x0 << 24 ) /* DIS */
8206#define IABR0_DMASPI1RX_EN (0x1 << 24 ) /* EN */
8207
8208/* IABR0[DMASPI1TX] - */
8209#define IABR0_DMASPI1TX_MSK (0x1 << 23 )
8210#define IABR0_DMASPI1TX (0x1 << 23 )
8211#define IABR0_DMASPI1TX_DIS (0x0 << 23 ) /* DIS */
8212#define IABR0_DMASPI1TX_EN (0x1 << 23 ) /* EN */
8213
8214/* IABR0[DMAERROR] - */
8215#define IABR0_DMAERROR_MSK (0x1 << 22 )
8216#define IABR0_DMAERROR (0x1 << 22 )
8217#define IABR0_DMAERROR_DIS (0x0 << 22 ) /* DIS */
8218#define IABR0_DMAERROR_EN (0x1 << 22 ) /* EN */
8219
8220/* IABR0[I2CM] - */
8221#define IABR0_I2CM_MSK (0x1 << 21 )
8222#define IABR0_I2CM (0x1 << 21 )
8223#define IABR0_I2CM_DIS (0x0 << 21 ) /* DIS */
8224#define IABR0_I2CM_EN (0x1 << 21 ) /* EN */
8225
8226/* IABR0[I2CS] - */
8227#define IABR0_I2CS_MSK (0x1 << 20 )
8228#define IABR0_I2CS (0x1 << 20 )
8229#define IABR0_I2CS_DIS (0x0 << 20 ) /* DIS */
8230#define IABR0_I2CS_EN (0x1 << 20 ) /* EN */
8231
8232/* IABR0[SPI1] - */
8233#define IABR0_SPI1_MSK (0x1 << 19 )
8234#define IABR0_SPI1 (0x1 << 19 )
8235#define IABR0_SPI1_DIS (0x0 << 19 ) /* DIS */
8236#define IABR0_SPI1_EN (0x1 << 19 ) /* EN */
8237
8238/* IABR0[SPI0] - */
8239#define IABR0_SPI0_MSK (0x1 << 18 )
8240#define IABR0_SPI0 (0x1 << 18 )
8241#define IABR0_SPI0_DIS (0x0 << 18 ) /* DIS */
8242#define IABR0_SPI0_EN (0x1 << 18 ) /* EN */
8243
8244/* IABR0[UART] - */
8245#define IABR0_UART_MSK (0x1 << 17 )
8246#define IABR0_UART (0x1 << 17 )
8247#define IABR0_UART_DIS (0x0 << 17 ) /* DIS */
8248#define IABR0_UART_EN (0x1 << 17 ) /* EN */
8249
8250/* IABR0[FEE] - */
8251#define IABR0_FEE_MSK (0x1 << 16 )
8252#define IABR0_FEE (0x1 << 16 )
8253#define IABR0_FEE_DIS (0x0 << 16 ) /* DIS */
8254#define IABR0_FEE_EN (0x1 << 16 ) /* EN */
8255
8256/* IABR0[SINC2] - */
8257#define IABR0_SINC2_MSK (0x1 << 15 )
8258#define IABR0_SINC2 (0x1 << 15 )
8259#define IABR0_SINC2_DIS (0x0 << 15 ) /* DIS */
8260#define IABR0_SINC2_EN (0x1 << 15 ) /* EN */
8261
8262/* IABR0[ADC1] - */
8263#define IABR0_ADC1_MSK (0x1 << 14 )
8264#define IABR0_ADC1 (0x1 << 14 )
8265#define IABR0_ADC1_DIS (0x0 << 14 ) /* DIS */
8266#define IABR0_ADC1_EN (0x1 << 14 ) /* EN */
8267
8268/* IABR0[T1] - */
8269#define IABR0_T1_MSK (0x1 << 12 )
8270#define IABR0_T1 (0x1 << 12 )
8271#define IABR0_T1_DIS (0x0 << 12 ) /* DIS */
8272#define IABR0_T1_EN (0x1 << 12 ) /* EN */
8273
8274/* IABR0[T0] - */
8275#define IABR0_T0_MSK (0x1 << 11 )
8276#define IABR0_T0 (0x1 << 11 )
8277#define IABR0_T0_DIS (0x0 << 11 ) /* DIS */
8278#define IABR0_T0_EN (0x1 << 11 ) /* EN */
8279
8280/* IABR0[T3] - */
8281#define IABR0_T3_MSK (0x1 << 9 )
8282#define IABR0_T3 (0x1 << 9 )
8283#define IABR0_T3_DIS (0x0 << 9 ) /* DIS */
8284#define IABR0_T3_EN (0x1 << 9 ) /* EN */
8285
8286/* IABR0[EXTINT7] - */
8287#define IABR0_EXTINT7_MSK (0x1 << 8 )
8288#define IABR0_EXTINT7 (0x1 << 8 )
8289#define IABR0_EXTINT7_DIS (0x0 << 8 ) /* DIS */
8290#define IABR0_EXTINT7_EN (0x1 << 8 ) /* EN */
8291
8292/* IABR0[EXTINT6] - */
8293#define IABR0_EXTINT6_MSK (0x1 << 7 )
8294#define IABR0_EXTINT6 (0x1 << 7 )
8295#define IABR0_EXTINT6_DIS (0x0 << 7 ) /* DIS */
8296#define IABR0_EXTINT6_EN (0x1 << 7 ) /* EN */
8297
8298/* IABR0[EXTINT5] - */
8299#define IABR0_EXTINT5_MSK (0x1 << 6 )
8300#define IABR0_EXTINT5 (0x1 << 6 )
8301#define IABR0_EXTINT5_DIS (0x0 << 6 ) /* DIS */
8302#define IABR0_EXTINT5_EN (0x1 << 6 ) /* EN */
8303
8304/* IABR0[EXTINT4] - */
8305#define IABR0_EXTINT4_MSK (0x1 << 5 )
8306#define IABR0_EXTINT4 (0x1 << 5 )
8307#define IABR0_EXTINT4_DIS (0x0 << 5 ) /* DIS */
8308#define IABR0_EXTINT4_EN (0x1 << 5 ) /* EN */
8309
8310/* IABR0[EXTINT3] - */
8311#define IABR0_EXTINT3_MSK (0x1 << 4 )
8312#define IABR0_EXTINT3 (0x1 << 4 )
8313#define IABR0_EXTINT3_DIS (0x0 << 4 ) /* DIS */
8314#define IABR0_EXTINT3_EN (0x1 << 4 ) /* EN */
8315
8316/* IABR0[EXTINT2] - */
8317#define IABR0_EXTINT2_MSK (0x1 << 3 )
8318#define IABR0_EXTINT2 (0x1 << 3 )
8319#define IABR0_EXTINT2_DIS (0x0 << 3 ) /* DIS */
8320#define IABR0_EXTINT2_EN (0x1 << 3 ) /* EN */
8321
8322/* IABR0[EXTINT1] - */
8323#define IABR0_EXTINT1_MSK (0x1 << 2 )
8324#define IABR0_EXTINT1 (0x1 << 2 )
8325#define IABR0_EXTINT1_DIS (0x0 << 2 ) /* DIS */
8326#define IABR0_EXTINT1_EN (0x1 << 2 ) /* EN */
8327
8328/* IABR0[EXTINT0] - */
8329#define IABR0_EXTINT0_MSK (0x1 << 1 )
8330#define IABR0_EXTINT0 (0x1 << 1 )
8331#define IABR0_EXTINT0_DIS (0x0 << 1 ) /* DIS */
8332#define IABR0_EXTINT0_EN (0x1 << 1 ) /* EN */
8333
8334/* IABR0[T2] - */
8335#define IABR0_T2_MSK (0x1 << 0 )
8336#define IABR0_T2 (0x1 << 0 )
8337#define IABR0_T2_DIS (0x0 << 0 ) /* DIS */
8338#define IABR0_T2_EN (0x1 << 0 ) /* EN */
8339
8340/* Reset Value for IABR1*/
8341#define IABR1_RVAL 0x0
8342
8343/* IABR1[PWM2] - */
8344#define IABR1_PWM2_MSK (0x1 << 6 )
8345#define IABR1_PWM2 (0x1 << 6 )
8346#define IABR1_PWM2_DIS (0x0 << 6 ) /* DIS */
8347#define IABR1_PWM2_EN (0x1 << 6 ) /* EN */
8348
8349/* IABR1[PWM1] - */
8350#define IABR1_PWM1_MSK (0x1 << 5 )
8351#define IABR1_PWM1 (0x1 << 5 )
8352#define IABR1_PWM1_DIS (0x0 << 5 ) /* DIS */
8353#define IABR1_PWM1_EN (0x1 << 5 ) /* EN */
8354
8355/* IABR1[PWM0] - */
8356#define IABR1_PWM0_MSK (0x1 << 4 )
8357#define IABR1_PWM0 (0x1 << 4 )
8358#define IABR1_PWM0_DIS (0x0 << 4 ) /* DIS */
8359#define IABR1_PWM0_EN (0x1 << 4 ) /* EN */
8360
8361/* IABR1[PWMTRIP] - */
8362#define IABR1_PWMTRIP_MSK (0x1 << 3 )
8363#define IABR1_PWMTRIP (0x1 << 3 )
8364#define IABR1_PWMTRIP_DIS (0x0 << 3 ) /* DIS */
8365#define IABR1_PWMTRIP_EN (0x1 << 3 ) /* EN */
8366
8367/* IABR1[DMASINC2] - */
8368#define IABR1_DMASINC2_MSK (0x1 << 2 )
8369#define IABR1_DMASINC2 (0x1 << 2 )
8370#define IABR1_DMASINC2_DIS (0x0 << 2 ) /* DIS */
8371#define IABR1_DMASINC2_EN (0x1 << 2 ) /* EN */
8372
8373/* IABR1[DMAADC1] - */
8374#define IABR1_DMAADC1_MSK (0x1 << 1 )
8375#define IABR1_DMAADC1 (0x1 << 1 )
8376#define IABR1_DMAADC1_DIS (0x0 << 1 ) /* DIS */
8377#define IABR1_DMAADC1_EN (0x1 << 1 ) /* EN */
8378
8379/* Reset Value for IPR0*/
8380#define IPR0_RVAL 0x0
8381
8382/* IPR0[EXTINT2] - */
8383#define IPR0_EXTINT2_MSK (0xFF << 24 )
8384
8385/* IPR0[EXTINT1] - */
8386#define IPR0_EXTINT1_MSK (0xFF << 16 )
8387
8388/* IPR0[EXTINT0] - Priority of interrupt number 1 */
8389#define IPR0_EXTINT0_MSK (0xFF << 8 )
8390
8391/* IPR0[T2] - Priority of interrupt number 0 */
8392#define IPR0_T2_MSK (0xFF << 0 )
8393
8394/* Reset Value for IPR1*/
8395#define IPR1_RVAL 0x0
8396
8397/* IPR1[EXTINT6] - */
8398#define IPR1_EXTINT6_MSK (0xFF << 24 )
8399
8400/* IPR1[EXTINT5] - */
8401#define IPR1_EXTINT5_MSK (0xFF << 16 )
8402
8403/* IPR1[EXTINT4] - */
8404#define IPR1_EXTINT4_MSK (0xFF << 8 )
8405
8406/* IPR1[EXTINT3] - */
8407#define IPR1_EXTINT3_MSK (0xFF << 0 )
8408
8409/* Reset Value for IPR2*/
8410#define IPR2_RVAL 0x0
8411
8412/* IPR2[T0] - */
8413#define IPR2_T0_MSK (0xFF << 24 )
8414
8415/* IPR2[T3] - */
8416#define IPR2_T3_MSK (0xFF << 8 )
8417
8418/* IPR2[EXTINT7] - */
8419#define IPR2_EXTINT7_MSK (0xFF << 0 )
8420
8421/* Reset Value for IPR3*/
8422#define IPR3_RVAL 0x0
8423
8424/* IPR3[SINC2] - */
8425#define IPR3_SINC2_MSK (0xFF << 24 )
8426
8427/* IPR3[ADC1] - */
8428#define IPR3_ADC1_MSK (0xFF << 16 )
8429
8430/* IPR3[T1] - */
8431#define IPR3_T1_MSK (0xFF << 0 )
8432
8433/* Reset Value for IPR4*/
8434#define IPR4_RVAL 0x0
8435
8436/* IPR4[SPI1] - */
8437#define IPR4_SPI1_MSK (0xFF << 24 )
8438
8439/* IPR4[SPI0] - */
8440#define IPR4_SPI0_MSK (0xFF << 16 )
8441
8442/* IPR4[UART] - */
8443#define IPR4_UART_MSK (0xFF << 8 )
8444
8445/* IPR4[FEE] - */
8446#define IPR4_FEE_MSK (0xFF << 0 )
8447
8448/* Reset Value for IPR5*/
8449#define IPR5_RVAL 0x0
8450
8451/* IPR5[DMASPI1TX] - */
8452#define IPR5_DMASPI1TX_MSK (0xFF << 24 )
8453
8454/* IPR5[DMAERROR] - */
8455#define IPR5_DMAERROR_MSK (0xFF << 16 )
8456
8457/* IPR5[I2CM] - */
8458#define IPR5_I2CM_MSK (0xFF << 8 )
8459
8460/* IPR5[I2CS] - */
8461#define IPR5_I2CS_MSK (0xFF << 0 )
8462
8463/* Reset Value for IPR6*/
8464#define IPR6_RVAL 0x0
8465
8466/* IPR6[DMAI2CSTX] - */
8467#define IPR6_DMAI2CSTX_MSK (0xFF << 24 )
8468
8469/* IPR6[DMAUARTRX] - */
8470#define IPR6_DMAUARTRX_MSK (0xFF << 16 )
8471
8472/* IPR6[DMAUARTTX] - */
8473#define IPR6_DMAUARTTX_MSK (0xFF << 8 )
8474
8475/* IPR6[DMASPI1RX] - */
8476#define IPR6_DMASPI1RX_MSK (0xFF << 0 )
8477
8478/* Reset Value for IPR7*/
8479#define IPR7_RVAL 0x0
8480
8481/* IPR7[DMADAC] - */
8482#define IPR7_DMADAC_MSK (0xFF << 24 )
8483
8484/* IPR7[DMAI2CMRX] - */
8485#define IPR7_DMAI2CMRX_MSK (0xFF << 16 )
8486
8487/* IPR7[DMAI2CMTX] - */
8488#define IPR7_DMAI2CMTX_MSK (0xFF << 8 )
8489
8490/* IPR7[DMAI2CSRX] - */
8491#define IPR7_DMAI2CSRX_MSK (0xFF << 0 )
8492
8493/* Reset Value for IPR8*/
8494#define IPR8_RVAL 0x0
8495
8496/* IPR8[PWMTRIP] - */
8497#define IPR8_PWMTRIP_MSK (0xFF << 24 )
8498
8499/* IPR8[DMASINC2] - */
8500#define IPR8_DMASINC2_MSK (0xFF << 16 )
8501
8502/* IPR8[DMAADC1] - */
8503#define IPR8_DMAADC1_MSK (0xFF << 8 )
8504
8505/* Reset Value for IPR9*/
8506#define IPR9_RVAL 0x0
8507
8508/* IPR9[PWM2] - */
8509#define IPR9_PWM2_MSK (0xFF << 16 )
8510
8511/* IPR9[PWM1] - */
8512#define IPR9_PWM1_MSK (0xFF << 8 )
8513
8514/* IPR9[PWM0] - */
8515#define IPR9_PWM0_MSK (0xFF << 0 )
8516
8517/* Reset Value for CPUID*/
8518#define CPUID_RVAL 0x412FC230
8519
8520/* CPUID[IMPLEMENTER] - Indicates implementor */
8521#define CPUID_IMPLEMENTER_MSK (0xFF << 24 )
8522
8523/* CPUID[VARIANT] - Indicates processor revision */
8524#define CPUID_VARIANT_MSK (0xF << 20 )
8525
8526/* CPUID[PARTNO] - Indicates part number */
8527#define CPUID_PARTNO_MSK (0xFFF << 4 )
8528
8529/* CPUID[REVISION] - Indicates patch release */
8530#define CPUID_REVISION_MSK (0xF << 0 )
8531
8532/* Reset Value for ICSR*/
8533#define ICSR_RVAL 0x0
8534
8535/* ICSR[NMIPENDSET] - Setting this bit will activate an NMI */
8536#define ICSR_NMIPENDSET_MSK (0x1 << 31 )
8537#define ICSR_NMIPENDSET (0x1 << 31 )
8538#define ICSR_NMIPENDSET_DIS (0x0 << 31 ) /* DIS */
8539#define ICSR_NMIPENDSET_EN (0x1 << 31 ) /* EN */
8540
8541/* ICSR[PENDSVSET] - Set a pending PendSV interrupt */
8542#define ICSR_PENDSVSET_MSK (0x1 << 28 )
8543#define ICSR_PENDSVSET (0x1 << 28 )
8544#define ICSR_PENDSVSET_DIS (0x0 << 28 ) /* DIS */
8545#define ICSR_PENDSVSET_EN (0x1 << 28 ) /* EN */
8546
8547/* ICSR[PENDSVCLR] - Clear a pending PendSV interrupt */
8548#define ICSR_PENDSVCLR_MSK (0x1 << 27 )
8549#define ICSR_PENDSVCLR (0x1 << 27 )
8550#define ICSR_PENDSVCLR_DIS (0x0 << 27 ) /* DIS */
8551#define ICSR_PENDSVCLR_EN (0x1 << 27 ) /* EN */
8552
8553/* ICSR[PENDSTSET] - Set a pending SysTick. Reads back with current state */
8554#define ICSR_PENDSTSET_MSK (0x1 << 26 )
8555#define ICSR_PENDSTSET (0x1 << 26 )
8556#define ICSR_PENDSTSET_DIS (0x0 << 26 ) /* DIS */
8557#define ICSR_PENDSTSET_EN (0x1 << 26 ) /* EN */
8558
8559/* ICSR[PENDSTCLR] - Clear a pending SysTick */
8560#define ICSR_PENDSTCLR_MSK (0x1 << 25 )
8561#define ICSR_PENDSTCLR (0x1 << 25 )
8562#define ICSR_PENDSTCLR_DIS (0x0 << 25 ) /* DIS */
8563#define ICSR_PENDSTCLR_EN (0x1 << 25 ) /* EN */
8564
8565/* ICSR[ISRPREEMPT] - If set, a pending exception will be serviced on exit from the debug halt state */
8566#define ICSR_ISRPREEMPT_MSK (0x1 << 23 )
8567#define ICSR_ISRPREEMPT (0x1 << 23 )
8568#define ICSR_ISRPREEMPT_DIS (0x0 << 23 ) /* DIS */
8569#define ICSR_ISRPREEMPT_EN (0x1 << 23 ) /* EN */
8570
8571/* ICSR[ISRPENDING] - Indicates if an external configurable is pending */
8572#define ICSR_ISRPENDING_MSK (0x1 << 22 )
8573#define ICSR_ISRPENDING (0x1 << 22 )
8574#define ICSR_ISRPENDING_DIS (0x0 << 22 ) /* DIS */
8575#define ICSR_ISRPENDING_EN (0x1 << 22 ) /* EN */
8576
8577/* ICSR[VECTPENDING] - Indicates the exception number for the highest priority pending exception */
8578#define ICSR_VECTPENDING_MSK (0x1FF << 12 )
8579
8580/* ICSR[RETTOBASE] - */
8581#define ICSR_RETTOBASE_MSK (0x1 << 11 )
8582#define ICSR_RETTOBASE (0x1 << 11 )
8583#define ICSR_RETTOBASE_DIS (0x0 << 11 ) /* DIS */
8584#define ICSR_RETTOBASE_EN (0x1 << 11 ) /* EN */
8585
8586/* ICSR[VECTACTIVE] - Thread mode, or exception number */
8587#define ICSR_VECTACTIVE_MSK (0x1FF << 0 )
8588
8589/* Reset Value for VTOR*/
8590#define VTOR_RVAL 0x0
8591
8592/* VTOR[TBLBASE] - */
8593#define VTOR_TBLBASE_MSK (0x1 << 29 )
8594#define VTOR_TBLBASE (0x1 << 29 )
8595#define VTOR_TBLBASE_DIS (0x0 << 29 ) /* DIS */
8596#define VTOR_TBLBASE_EN (0x1 << 29 ) /* EN */
8597
8598/* VTOR[TBLOFF] - */
8599#define VTOR_TBLOFF_MSK (0x3FFFFF << 7 )
8600
8601/* Reset Value for AIRCR*/
8602#define AIRCR_RVAL 0xFA050000
8603
8604/* AIRCR[VECTKEYSTAT] - Reads as 0xFA05 */
8605#define AIRCR_VECTKEYSTAT_MSK (0xFFFF << 16 )
8606
8607/* AIRCR[ENDIANESS] - This bit is static or configured by a hardware input on reset */
8608#define AIRCR_ENDIANESS_MSK (0x1 << 15 )
8609#define AIRCR_ENDIANESS (0x1 << 15 )
8610#define AIRCR_ENDIANESS_DIS (0x0 << 15 ) /* DIS */
8611#define AIRCR_ENDIANESS_EN (0x1 << 15 ) /* EN */
8612
8613/* AIRCR[PRIGROUP] - Priority grouping position */
8614#define AIRCR_PRIGROUP_MSK (0x7 << 8 )
8615
8616/* AIRCR[SYSRESETREQ] - System Reset Request */
8617#define AIRCR_SYSRESETREQ_MSK (0x1 << 2 )
8618#define AIRCR_SYSRESETREQ (0x1 << 2 )
8619#define AIRCR_SYSRESETREQ_DIS (0x0 << 2 ) /* DIS */
8620#define AIRCR_SYSRESETREQ_EN (0x1 << 2 ) /* EN */
8621
8622/* AIRCR[VECTCLRACTIVE] - Clears all active state information for fixed and configurable exceptions */
8623#define AIRCR_VECTCLRACTIVE_MSK (0x1 << 1 )
8624#define AIRCR_VECTCLRACTIVE (0x1 << 1 )
8625#define AIRCR_VECTCLRACTIVE_DIS (0x0 << 1 ) /* DIS */
8626#define AIRCR_VECTCLRACTIVE_EN (0x1 << 1 ) /* EN */
8627
8628/* AIRCR[VECTRESET] - Local system reset */
8629#define AIRCR_VECTRESET_MSK (0x1 << 0 )
8630#define AIRCR_VECTRESET (0x1 << 0 )
8631#define AIRCR_VECTRESET_DIS (0x0 << 0 ) /* DIS */
8632#define AIRCR_VECTRESET_EN (0x1 << 0 ) /* EN */
8633
8634/* Reset Value for SCR*/
8635#define SCR_RVAL 0x0
8636
8637/* SCR[SEVONPEND] - */
8638#define SCR_SEVONPEND_MSK (0x1 << 4 )
8639#define SCR_SEVONPEND (0x1 << 4 )
8640#define SCR_SEVONPEND_DIS (0x0 << 4 ) /* DIS */
8641#define SCR_SEVONPEND_EN (0x1 << 4 ) /* EN */
8642
8643/* SCR[SLEEPDEEP] - Sleep deep bit */
8644#define SCR_SLEEPDEEP_MSK (0x1 << 2 )
8645#define SCR_SLEEPDEEP (0x1 << 2 )
8646#define SCR_SLEEPDEEP_DIS (0x0 << 2 ) /* DIS */
8647#define SCR_SLEEPDEEP_EN (0x1 << 2 ) /* EN */
8648
8649/* SCR[SLEEPONEXIT] - Sleep on exit when returning from handler mode to thread mode */
8650#define SCR_SLEEPONEXIT_MSK (0x1 << 1 )
8651#define SCR_SLEEPONEXIT (0x1 << 1 )
8652#define SCR_SLEEPONEXIT_DIS (0x0 << 1 ) /* DIS */
8653#define SCR_SLEEPONEXIT_EN (0x1 << 1 ) /* EN */
8654
8655/* Reset Value for CCR*/
8656#define CCR_RVAL 0x200
8657
8658/* CCR[STKALIGN] - */
8659#define CCR_STKALIGN_MSK (0x1 << 9 )
8660#define CCR_STKALIGN (0x1 << 9 )
8661#define CCR_STKALIGN_DIS (0x0 << 9 ) /* DIS */
8662#define CCR_STKALIGN_EN (0x1 << 9 ) /* EN */
8663
8664/* CCR[BFHFNMIGN] - */
8665#define CCR_BFHFNMIGN_MSK (0x1 << 8 )
8666#define CCR_BFHFNMIGN (0x1 << 8 )
8667#define CCR_BFHFNMIGN_DIS (0x0 << 8 ) /* DIS */
8668#define CCR_BFHFNMIGN_EN (0x1 << 8 ) /* EN */
8669
8670/* CCR[DIV0TRP] - */
8671#define CCR_DIV0TRP_MSK (0x1 << 4 )
8672#define CCR_DIV0TRP (0x1 << 4 )
8673#define CCR_DIV0TRP_DIS (0x0 << 4 ) /* DIS */
8674#define CCR_DIV0TRP_EN (0x1 << 4 ) /* EN */
8675
8676/* CCR[UNALIGNTRP] - */
8677#define CCR_UNALIGNTRP_MSK (0x1 << 3 )
8678#define CCR_UNALIGNTRP (0x1 << 3 )
8679#define CCR_UNALIGNTRP_DIS (0x0 << 3 ) /* DIS */
8680#define CCR_UNALIGNTRP_EN (0x1 << 3 ) /* EN */
8681
8682/* CCR[USERSETMPEND] - */
8683#define CCR_USERSETMPEND_MSK (0x1 << 1 )
8684#define CCR_USERSETMPEND (0x1 << 1 )
8685#define CCR_USERSETMPEND_DIS (0x0 << 1 ) /* DIS */
8686#define CCR_USERSETMPEND_EN (0x1 << 1 ) /* EN */
8687
8688/* CCR[NONBASETHRDENA] - */
8689#define CCR_NONBASETHRDENA_MSK (0x1 << 0 )
8690#define CCR_NONBASETHRDENA (0x1 << 0 )
8691#define CCR_NONBASETHRDENA_DIS (0x0 << 0 ) /* DIS */
8692#define CCR_NONBASETHRDENA_EN (0x1 << 0 ) /* EN */
8693
8694/* Reset Value for SHPR1*/
8695#define SHPR1_RVAL 0x0
8696
8697/* SHPR1[PRI7] - Priority of system handler 7 - reserved */
8698#define SHPR1_PRI7_MSK (0xFF << 24 )
8699
8700/* SHPR1[PRI6] - Priority of system handler 6 - UsageFault */
8701#define SHPR1_PRI6_MSK (0xFF << 16 )
8702
8703/* SHPR1[PRI5] - Priority of system handler 5 - BusFault */
8704#define SHPR1_PRI5_MSK (0xFF << 8 )
8705
8706/* SHPR1[PRI4] - Priority of system handler 4 - MemManage */
8707#define SHPR1_PRI4_MSK (0xFF << 0 )
8708
8709/* Reset Value for SHPR2*/
8710#define SHPR2_RVAL 0x0
8711
8712/* SHPR2[PRI11] - Priority of system handler 11 - SVCall */
8713#define SHPR2_PRI11_MSK (0xFF << 24 )
8714
8715/* SHPR2[PRI10] - Priority of system handler 10 - reserved */
8716#define SHPR2_PRI10_MSK (0xFF << 16 )
8717
8718/* SHPR2[PRI9] - Priority of system handler 9 - reserved */
8719#define SHPR2_PRI9_MSK (0xFF << 8 )
8720
8721/* SHPR2[PRI8] - Priority of system handler 8 - reserved */
8722#define SHPR2_PRI8_MSK (0xFF << 0 )
8723
8724/* Reset Value for SHPR3*/
8725#define SHPR3_RVAL 0x0
8726
8727/* SHPR3[PRI15] - Priority of system handler 15 - SysTick */
8728#define SHPR3_PRI15_MSK (0xFF << 24 )
8729
8730/* SHPR3[PRI14] - Priority of system handler 14 - PendSV */
8731#define SHPR3_PRI14_MSK (0xFF << 16 )
8732
8733/* SHPR3[PRI13] - Priority of system handler 13 - reserved */
8734#define SHPR3_PRI13_MSK (0xFF << 8 )
8735
8736/* SHPR3[PRI12] - Priority of system handler 12 - DebugMonitor */
8737#define SHPR3_PRI12_MSK (0xFF << 0 )
8738
8739/* Reset Value for SHCSR*/
8740#define SHCSR_RVAL 0x0
8741
8742/* SHCSR[USGFAULTENA] - Enable for UsageFault */
8743#define SHCSR_USGFAULTENA_MSK (0x1 << 18 )
8744#define SHCSR_USGFAULTENA (0x1 << 18 )
8745#define SHCSR_USGFAULTENA_DIS (0x0 << 18 ) /* DIS */
8746#define SHCSR_USGFAULTENA_EN (0x1 << 18 ) /* EN */
8747
8748/* SHCSR[BUSFAULTENA] - Enable for BusFault. */
8749#define SHCSR_BUSFAULTENA_MSK (0x1 << 17 )
8750#define SHCSR_BUSFAULTENA (0x1 << 17 )
8751#define SHCSR_BUSFAULTENA_DIS (0x0 << 17 ) /* DIS */
8752#define SHCSR_BUSFAULTENA_EN (0x1 << 17 ) /* EN */
8753
8754/* SHCSR[MEMFAULTENA] - Enable for MemManage fault. */
8755#define SHCSR_MEMFAULTENA_MSK (0x1 << 16 )
8756#define SHCSR_MEMFAULTENA (0x1 << 16 )
8757#define SHCSR_MEMFAULTENA_DIS (0x0 << 16 ) /* DIS */
8758#define SHCSR_MEMFAULTENA_EN (0x1 << 16 ) /* EN */
8759
8760/* SHCSR[SVCALLPENDED] - Reads as 1 if SVCall is Pending */
8761#define SHCSR_SVCALLPENDED_MSK (0x1 << 15 )
8762#define SHCSR_SVCALLPENDED (0x1 << 15 )
8763#define SHCSR_SVCALLPENDED_DIS (0x0 << 15 ) /* DIS */
8764#define SHCSR_SVCALLPENDED_EN (0x1 << 15 ) /* EN */
8765
8766/* SHCSR[BUSFAULTPENDED] - Reads as 1 if BusFault is Pending */
8767#define SHCSR_BUSFAULTPENDED_MSK (0x1 << 14 )
8768#define SHCSR_BUSFAULTPENDED (0x1 << 14 )
8769#define SHCSR_BUSFAULTPENDED_DIS (0x0 << 14 ) /* DIS */
8770#define SHCSR_BUSFAULTPENDED_EN (0x1 << 14 ) /* EN */
8771
8772/* SHCSR[MEMFAULTPENDED] - Reads as 1 if MemManage is Pending */
8773#define SHCSR_MEMFAULTPENDED_MSK (0x1 << 13 )
8774#define SHCSR_MEMFAULTPENDED (0x1 << 13 )
8775#define SHCSR_MEMFAULTPENDED_DIS (0x0 << 13 ) /* DIS */
8776#define SHCSR_MEMFAULTPENDED_EN (0x1 << 13 ) /* EN */
8777
8778/* SHCSR[USGFAULTPENDED] - Reads as 1 if UsageFault is Pending */
8779#define SHCSR_USGFAULTPENDED_MSK (0x1 << 12 )
8780#define SHCSR_USGFAULTPENDED (0x1 << 12 )
8781#define SHCSR_USGFAULTPENDED_DIS (0x0 << 12 ) /* DIS */
8782#define SHCSR_USGFAULTPENDED_EN (0x1 << 12 ) /* EN */
8783
8784/* SHCSR[SYSTICKACT] - Reads as 1 if SysTick is Active */
8785#define SHCSR_SYSTICKACT_MSK (0x1 << 11 )
8786#define SHCSR_SYSTICKACT (0x1 << 11 )
8787#define SHCSR_SYSTICKACT_DIS (0x0 << 11 ) /* DIS */
8788#define SHCSR_SYSTICKACT_EN (0x1 << 11 ) /* EN */
8789
8790/* SHCSR[PENDSVACT] - Reads as 1 if PendSV is Active */
8791#define SHCSR_PENDSVACT_MSK (0x1 << 10 )
8792#define SHCSR_PENDSVACT (0x1 << 10 )
8793#define SHCSR_PENDSVACT_DIS (0x0 << 10 ) /* DIS */
8794#define SHCSR_PENDSVACT_EN (0x1 << 10 ) /* EN */
8795
8796/* SHCSR[MONITORACT] - Reads as 1 if the Monitor is Active */
8797#define SHCSR_MONITORACT_MSK (0x1 << 8 )
8798#define SHCSR_MONITORACT (0x1 << 8 )
8799#define SHCSR_MONITORACT_DIS (0x0 << 8 ) /* DIS */
8800#define SHCSR_MONITORACT_EN (0x1 << 8 ) /* EN */
8801
8802/* SHCSR[SVCALLACT] - Reads as 1 if SVCall is Active */
8803#define SHCSR_SVCALLACT_MSK (0x1 << 7 )
8804#define SHCSR_SVCALLACT (0x1 << 7 )
8805#define SHCSR_SVCALLACT_DIS (0x0 << 7 ) /* DIS */
8806#define SHCSR_SVCALLACT_EN (0x1 << 7 ) /* EN */
8807
8808/* SHCSR[USGFAULTACT] - Reads as 1 if UsageFault is Active. */
8809#define SHCSR_USGFAULTACT_MSK (0x1 << 3 )
8810#define SHCSR_USGFAULTACT (0x1 << 3 )
8811#define SHCSR_USGFAULTACT_DIS (0x0 << 3 ) /* DIS */
8812#define SHCSR_USGFAULTACT_EN (0x1 << 3 ) /* EN */
8813
8814/* SHCSR[BUSFAULTACT] - Reads as 1 if BusFault is Active. */
8815#define SHCSR_BUSFAULTACT_MSK (0x1 << 1 )
8816#define SHCSR_BUSFAULTACT (0x1 << 1 )
8817#define SHCSR_BUSFAULTACT_DIS (0x0 << 1 ) /* DIS */
8818#define SHCSR_BUSFAULTACT_EN (0x1 << 1 ) /* EN */
8819
8820/* SHCSR[MEMFAULTACT] - Reads as 1 if MemManage is Active */
8821#define SHCSR_MEMFAULTACT_MSK (0x1 << 0 )
8822#define SHCSR_MEMFAULTACT (0x1 << 0 )
8823#define SHCSR_MEMFAULTACT_DIS (0x0 << 0 ) /* DIS */
8824#define SHCSR_MEMFAULTACT_EN (0x1 << 0 ) /* EN */
8825
8826/* Reset Value for CFSR*/
8827#define CFSR_RVAL 0x0
8828
8829/* CFSR[DIVBYZERO] - Divide by zero error */
8830#define CFSR_DIVBYZERO_MSK (0x1 << 25 )
8831#define CFSR_DIVBYZERO (0x1 << 25 )
8832#define CFSR_DIVBYZERO_DIS (0x0 << 25 ) /* DIS */
8833#define CFSR_DIVBYZERO_EN (0x1 << 25 ) /* EN */
8834
8835/* CFSR[UNALIGNED] - Unaligned access error */
8836#define CFSR_UNALIGNED_MSK (0x1 << 24 )
8837#define CFSR_UNALIGNED (0x1 << 24 )
8838#define CFSR_UNALIGNED_DIS (0x0 << 24 ) /* DIS */
8839#define CFSR_UNALIGNED_EN (0x1 << 24 ) /* EN */
8840
8841/* CFSR[NOCP] - Coprocessor access error */
8842#define CFSR_NOCP_MSK (0x1 << 19 )
8843#define CFSR_NOCP (0x1 << 19 )
8844#define CFSR_NOCP_DIS (0x0 << 19 ) /* DIS */
8845#define CFSR_NOCP_EN (0x1 << 19 ) /* EN */
8846
8847/* CFSR[INVPC] - Integrity check error on EXC_RETURN */
8848#define CFSR_INVPC_MSK (0x1 << 18 )
8849#define CFSR_INVPC (0x1 << 18 )
8850#define CFSR_INVPC_DIS (0x0 << 18 ) /* DIS */
8851#define CFSR_INVPC_EN (0x1 << 18 ) /* EN */
8852
8853/* CFSR[INVSTATE] - Invalid EPSR.T bit or illegal EPSR.IT bits for executing */
8854#define CFSR_INVSTATE_MSK (0x1 << 17 )
8855#define CFSR_INVSTATE (0x1 << 17 )
8856#define CFSR_INVSTATE_DIS (0x0 << 17 ) /* DIS */
8857#define CFSR_INVSTATE_EN (0x1 << 17 ) /* EN */
8858
8859/* CFSR[UNDEFINSTR] - Undefined instruction executed */
8860#define CFSR_UNDEFINSTR_MSK (0x1 << 16 )
8861#define CFSR_UNDEFINSTR (0x1 << 16 )
8862#define CFSR_UNDEFINSTR_DIS (0x0 << 16 ) /* DIS */
8863#define CFSR_UNDEFINSTR_EN (0x1 << 16 ) /* EN */
8864
8865/* CFSR[BFARVALID] - This bit is set if the BFAR register has valid contents */
8866#define CFSR_BFARVALID_MSK (0x1 << 15 )
8867#define CFSR_BFARVALID (0x1 << 15 )
8868#define CFSR_BFARVALID_DIS (0x0 << 15 ) /* DIS */
8869#define CFSR_BFARVALID_EN (0x1 << 15 ) /* EN */
8870
8871/* CFSR[STKERR] - This bit indicates a derived bus fault has occurred on exception entry */
8872#define CFSR_STKERR_MSK (0x1 << 12 )
8873#define CFSR_STKERR (0x1 << 12 )
8874#define CFSR_STKERR_DIS (0x0 << 12 ) /* DIS */
8875#define CFSR_STKERR_EN (0x1 << 12 ) /* EN */
8876
8877/* CFSR[UNSTKERR] - This bit indicates a derived bus fault has occurred on exception return */
8878#define CFSR_UNSTKERR_MSK (0x1 << 11 )
8879#define CFSR_UNSTKERR (0x1 << 11 )
8880#define CFSR_UNSTKERR_DIS (0x0 << 11 ) /* DIS */
8881#define CFSR_UNSTKERR_EN (0x1 << 11 ) /* EN */
8882
8883/* CFSR[IMPRECISERR] - Imprecise data access error */
8884#define CFSR_IMPRECISERR_MSK (0x1 << 10 )
8885#define CFSR_IMPRECISERR (0x1 << 10 )
8886#define CFSR_IMPRECISERR_DIS (0x0 << 10 ) /* DIS */
8887#define CFSR_IMPRECISERR_EN (0x1 << 10 ) /* EN */
8888
8889/* CFSR[PRECISERR] - Precise data access error. The BFAR is written with the faulting address */
8890#define CFSR_PRECISERR_MSK (0x1 << 9 )
8891#define CFSR_PRECISERR (0x1 << 9 )
8892#define CFSR_PRECISERR_DIS (0x0 << 9 ) /* DIS */
8893#define CFSR_PRECISERR_EN (0x1 << 9 ) /* EN */
8894
8895/* CFSR[IBUSERR] - This bit indicates a bus fault on an instruction prefetch */
8896#define CFSR_IBUSERR_MSK (0x1 << 8 )
8897#define CFSR_IBUSERR (0x1 << 8 )
8898#define CFSR_IBUSERR_DIS (0x0 << 8 ) /* DIS */
8899#define CFSR_IBUSERR_EN (0x1 << 8 ) /* EN */
8900
8901/* CFSR[MMARVALID] - This bit is set if the MMAR register has valid contents. */
8902#define CFSR_MMARVALID_MSK (0x1 << 7 )
8903#define CFSR_MMARVALID (0x1 << 7 )
8904#define CFSR_MMARVALID_DIS (0x0 << 7 ) /* DIS */
8905#define CFSR_MMARVALID_EN (0x1 << 7 ) /* EN */
8906
8907/* CFSR[MSTKERR] - A derived MemManage fault has occurred on exception entry */
8908#define CFSR_MSTKERR_MSK (0x1 << 4 )
8909#define CFSR_MSTKERR (0x1 << 4 )
8910#define CFSR_MSTKERR_DIS (0x0 << 4 ) /* DIS */
8911#define CFSR_MSTKERR_EN (0x1 << 4 ) /* EN */
8912
8913/* CFSR[MUNSTKERR] - A derived MemManage fault has occurred on exception return */
8914#define CFSR_MUNSTKERR_MSK (0x1 << 3 )
8915#define CFSR_MUNSTKERR (0x1 << 3 )
8916#define CFSR_MUNSTKERR_DIS (0x0 << 3 ) /* DIS */
8917#define CFSR_MUNSTKERR_EN (0x1 << 3 ) /* EN */
8918
8919/* CFSR[DACCVIOL] - Data access violation. The MMAR is set to the data address which the load store tried to access. */
8920#define CFSR_DACCVIOL_MSK (0x1 << 1 )
8921#define CFSR_DACCVIOL (0x1 << 1 )
8922#define CFSR_DACCVIOL_DIS (0x0 << 1 ) /* DIS */
8923#define CFSR_DACCVIOL_EN (0x1 << 1 ) /* EN */
8924
8925/* CFSR[IACCVIOL] - violation on an instruction fetch. */
8926#define CFSR_IACCVIOL_MSK (0x1 << 0 )
8927#define CFSR_IACCVIOL (0x1 << 0 )
8928#define CFSR_IACCVIOL_DIS (0x0 << 0 ) /* DIS */
8929#define CFSR_IACCVIOL_EN (0x1 << 0 ) /* EN */
8930
8931/* Reset Value for HFSR*/
8932#define HFSR_RVAL 0x0
8933
8934/* HFSR[DEBUGEVT] - Debug event, and the Debug Fault Status Register has been updated. */
8935#define HFSR_DEBUGEVT_MSK (0x1 << 31 )
8936#define HFSR_DEBUGEVT (0x1 << 31 )
8937#define HFSR_DEBUGEVT_DIS (0x0 << 31 ) /* DIS */
8938#define HFSR_DEBUGEVT_EN (0x1 << 31 ) /* EN */
8939
8940/* HFSR[FORCED] - Configurable fault cannot be activated due to priority or it was disabled. Priority escalated to a HardFault. */
8941#define HFSR_FORCED_MSK (0x1 << 30 )
8942#define HFSR_FORCED (0x1 << 30 )
8943#define HFSR_FORCED_DIS (0x0 << 30 ) /* DIS */
8944#define HFSR_FORCED_EN (0x1 << 30 ) /* EN */
8945
8946/* HFSR[VECTTBL] - Fault was due to vector table read on exception processing */
8947#define HFSR_VECTTBL_MSK (0x1 << 1 )
8948#define HFSR_VECTTBL (0x1 << 1 )
8949#define HFSR_VECTTBL_DIS (0x0 << 1 ) /* DIS */
8950#define HFSR_VECTTBL_EN (0x1 << 1 ) /* EN */
8951
8952/* Reset Value for MMFAR*/
8953#define MMFAR_RVAL 0x0
8954
8955/* MMFAR[ADDRESS] - Data address MPU faulted. */
8956#define MMFAR_ADDRESS_MSK (0xFFFFFFFF << 0 )
8957
8958/* Reset Value for BFAR*/
8959#define BFAR_RVAL 0x0
8960
8961/* BFAR[ADDRESS] - Updated on precise data access faults */
8962#define BFAR_ADDRESS_MSK (0xFFFFFFFF << 0 )
8963
8964/* Reset Value for STIR*/
8965#define STIR_RVAL 0x0
8966
8967/* STIR[INTID] - The value written in this field is the interrupt to be triggered. */
8968#define STIR_INTID_MSK (0x3FF << 0 )
8969// ------------------------------------------------------------------------------------------------
8970// ----- ADC1 -----
8971// ------------------------------------------------------------------------------------------------
8972
8973
8974/**
8975 * @brief Analog to Digital Converter (pADI_ADC1)
8976 */
8977
8978#if (__NO_MMR_STRUCTS__==0)
8979typedef struct { /*!< pADI_ADC1 Structure */
8980 __IO uint8_t STA; /*!< ADC Status register */
8981 __I uint8_t RESERVED0[3];
8982 __IO uint8_t MSKI; /*!< Interrupt control register */
8983 __I uint8_t RESERVED1[3];
8984 __IO uint32_t CON; /*!< Main control register */
8985 __IO uint16_t OF; /*!< Offset calibration register */
8986 __I uint16_t RESERVED2;
8987 __IO uint16_t INTGN; /*!< Gain calibration register when using internal reference */
8988 __I uint16_t RESERVED3;
8989 __IO uint16_t EXTGN; /*!< Gain calibration register when using external reference */
8990 __I uint16_t RESERVED4;
8991 __IO uint16_t VDDGN; /*!< Gain calibration register when using AVDD as the ADC reference */
8992 __I uint16_t RESERVED5;
8993 __IO uint16_t ADCCFG; /*!< "Control register for the VBIAS voltage generator, ground switch and external reference buffer" */
8994 __I uint16_t RESERVED6;
8995 __IO uint16_t FLT; /*!< Filter configuration register */
8996 __I uint16_t RESERVED7;
8997 __IO uint16_t MDE; /*!< mode control register */
8998 __I uint16_t RESERVED8;
8999 __IO uint16_t RCR; /*!< Number of ADC conversions before an ADC interrupt is generated. */
9000 __I uint16_t RESERVED9;
9001 __IO uint16_t RCV; /*!< "This 16-bit, read-only MMR holds the current number of ADC conversion results" */
9002 __I uint16_t RESERVED10;
9003 __IO uint16_t TH; /*!< Sets the threshold */
9004 __I uint16_t RESERVED11;
9005 __IO uint8_t THC; /*!< Determines how many cumulative ADC conversion result readings above ADCxTH must occur */
9006 __I uint8_t RESERVED12[3];
9007 __IO uint8_t THV; /*!< 8-bit threshold exceeded counter register */
9008 __I uint8_t RESERVED13[3];
9009 __IO uint32_t ACC; /*!< 32-bit accumulator register */
9010 __IO uint32_t ATH; /*!< Holds the threshold value for the accumulator comparator */
9011 __IO uint8_t PRO; /*!< Configuration register for Post processing of ADC results */
9012 __I uint8_t RESERVED14[3];
9013 __IO uint32_t DAT; /*!< conversion result register */
9014} ADI_ADC_TypeDef;
9015#else // (__NO_MMR_STRUCTS__==0)
9016#define ADCCFG (*(volatile unsigned short int *) 0x4003001C)
9017#endif // (__NO_MMR_STRUCTS__==0)
9018
9019/* Reset Value for ADCCFG*/
9020#define ADCCFG_RVAL 0xF
9021
9022/* ADCCFG[SIMU] - Enable both ADCs */
9023#define ADCCFG_SIMU_BBA (*(volatile unsigned long *) 0x426003BC)
9024#define ADCCFG_SIMU_MSK (0x1 << 15 )
9025#define ADCCFG_SIMU (0x1 << 15 )
9026#define ADCCFG_SIMU_DIS (0x0 << 15 ) /* DIS */
9027#define ADCCFG_SIMU_EN (0x1 << 15 ) /* EN */
9028
9029/* ADCCFG[BOOST30] - Boost the Vbias current source ability by 30 times */
9030#define ADCCFG_BOOST30_BBA (*(volatile unsigned long *) 0x426003B4)
9031#define ADCCFG_BOOST30_MSK (0x1 << 13 )
9032#define ADCCFG_BOOST30 (0x1 << 13 )
9033#define ADCCFG_BOOST30_DIS (0x0 << 13 ) /* DIS */
9034#define ADCCFG_BOOST30_EN (0x1 << 13 ) /* EN */
9035
9036/* ADCCFG[PINSEL] - Enable vbias generator, send vbias to selected ain pin bits */
9037#define ADCCFG_PINSEL_MSK (0x7 << 8 )
9038#define ADCCFG_PINSEL_DIS (0x0 << 8 ) /* Disable VBIAS generator */
9039#define ADCCFG_PINSEL_AIN7 (0x4 << 8 ) /* AIN7 */
9040#define ADCCFG_PINSEL_AIN11 (0x6 << 8 ) /* AIN11 */
9041
9042/* ADCCFG[GNDSWON] - GND_SW */
9043#define ADCCFG_GNDSWON_BBA (*(volatile unsigned long *) 0x4260039C)
9044#define ADCCFG_GNDSWON_MSK (0x1 << 7 )
9045#define ADCCFG_GNDSWON (0x1 << 7 )
9046#define ADCCFG_GNDSWON_DIS (0x0 << 7 ) /* DIS */
9047#define ADCCFG_GNDSWON_EN (0x1 << 7 ) /* EN */
9048
9049/* ADCCFG[GNDSWRESEN] - 20k resistor in series with GND_SW */
9050#define ADCCFG_GNDSWRESEN_BBA (*(volatile unsigned long *) 0x42600398)
9051#define ADCCFG_GNDSWRESEN_MSK (0x1 << 6 )
9052#define ADCCFG_GNDSWRESEN (0x1 << 6 )
9053#define ADCCFG_GNDSWRESEN_DIS (0x0 << 6 ) /* DIS */
9054#define ADCCFG_GNDSWRESEN_EN (0x1 << 6 ) /* EN */
9055
9056/* ADCCFG[EXTBUF] - Control signals for ext_ref buffers bits */
9057#define ADCCFG_EXTBUF_MSK (0x3 << 0 )
9058#define ADCCFG_EXTBUF_OFF (0x0 << 0 ) /* OFF */
9059#define ADCCFG_EXTBUF_VREFPN (0x1 << 0 ) /* VREFPN */
9060#define ADCCFG_EXTBUF_VREFP_VREF2P (0x2 << 0 ) /* VREFP_VREF2P */
9061#define ADCCFG_EXTBUF_VREFP_ONLY (0x3 << 0 ) /* VREFP_Only */
9062
9063#if (__NO_MMR_STRUCTS__==1)
9064
9065#define ADC1STA (*(volatile unsigned char *) 0x40030080)
9066#define ADC1MSKI (*(volatile unsigned char *) 0x40030084)
9067#define ADC1CON (*(volatile unsigned long *) 0x40030088)
9068#define ADC1OF (*(volatile unsigned short int *) 0x4003008C)
9069#define ADC1INTGN (*(volatile unsigned short int *) 0x40030090)
9070#define ADC1EXTGN (*(volatile unsigned short int *) 0x40030094)
9071#define ADC1VDDGN (*(volatile unsigned short int *) 0x40030098)
9072#define ADCSCFG1 (*(volatile unsigned short int *) 0x4003009C)
9073#define ADC1FLT (*(volatile unsigned short int *) 0x400300A0)
9074#define ADC1MDE (*(volatile unsigned short int *) 0x400300A4)
9075#define ADC1RCR (*(volatile unsigned short int *) 0x400300A8)
9076#define ADC1RCV (*(volatile unsigned short int *) 0x400300AC)
9077#define ADC1TH (*(volatile unsigned short int *) 0x400300B0)
9078#define ADC1THC (*(volatile unsigned char *) 0x400300B4)
9079#define ADC1THV (*(volatile unsigned char *) 0x400300B8)
9080#define ADC1ACC (*(volatile unsigned long *) 0x400300BC)
9081#define ADC1ATH (*(volatile unsigned long *) 0x400300C0)
9082#define ADC1PRO (*(volatile unsigned char *) 0x400300C4)
9083#define ADC1DAT (*(volatile unsigned long *) 0x400300C8)
9084#endif // (__NO_MMR_STRUCTS__==1)
9085
9086/* Reset Value for ADC1STA*/
9087#define ADC1STA_RVAL 0x0
9088
9089/* ADC1STA[CAL] - ADC Calibration status register */
9090#define ADC1STA_CAL_BBA (*(volatile unsigned long *) 0x42601014)
9091#define ADC1STA_CAL_MSK (0x1 << 5 )
9092#define ADC1STA_CAL (0x1 << 5 )
9093#define ADC1STA_CAL_DIS (0x0 << 5 ) /* DIS */
9094#define ADC1STA_CAL_EN (0x1 << 5 ) /* EN */
9095
9096/* ADC1STA[ERR] - ADC conversion error status bit. */
9097#define ADC1STA_ERR_BBA (*(volatile unsigned long *) 0x42601010)
9098#define ADC1STA_ERR_MSK (0x1 << 4 )
9099#define ADC1STA_ERR (0x1 << 4 )
9100#define ADC1STA_ERR_DIS (0x0 << 4 ) /* DIS */
9101#define ADC1STA_ERR_EN (0x1 << 4 ) /* EN */
9102
9103/* ADC1STA[ATHEX] - ADC Accumulator Comparator Threshold status bit. */
9104#define ADC1STA_ATHEX_BBA (*(volatile unsigned long *) 0x4260100C)
9105#define ADC1STA_ATHEX_MSK (0x1 << 3 )
9106#define ADC1STA_ATHEX (0x1 << 3 )
9107#define ADC1STA_ATHEX_DIS (0x0 << 3 ) /* DIS */
9108#define ADC1STA_ATHEX_EN (0x1 << 3 ) /* EN */
9109
9110/* ADC1STA[THEX] - ADC comparator threshold. */
9111#define ADC1STA_THEX_BBA (*(volatile unsigned long *) 0x42601008)
9112#define ADC1STA_THEX_MSK (0x1 << 2 )
9113#define ADC1STA_THEX (0x1 << 2 )
9114#define ADC1STA_THEX_DIS (0x0 << 2 ) /* DIS */
9115#define ADC1STA_THEX_EN (0x1 << 2 ) /* EN */
9116
9117/* ADC1STA[OVR] - ADC overrange bit. */
9118#define ADC1STA_OVR_BBA (*(volatile unsigned long *) 0x42601004)
9119#define ADC1STA_OVR_MSK (0x1 << 1 )
9120#define ADC1STA_OVR (0x1 << 1 )
9121#define ADC1STA_OVR_DIS (0x0 << 1 ) /* DIS */
9122#define ADC1STA_OVR_EN (0x1 << 1 ) /* EN */
9123
9124/* ADC1STA[RDY] - valid conversion result */
9125#define ADC1STA_RDY_BBA (*(volatile unsigned long *) 0x42601000)
9126#define ADC1STA_RDY_MSK (0x1 << 0 )
9127#define ADC1STA_RDY (0x1 << 0 )
9128#define ADC1STA_RDY_DIS (0x0 << 0 ) /* DIS */
9129#define ADC1STA_RDY_EN (0x1 << 0 ) /* EN */
9130
9131/* Reset Value for ADC1MSKI*/
9132#define ADC1MSKI_RVAL 0x0
9133
9134/* ADC1MSKI[ATHEX] - ADC Accumulator Comparator Threshold status bit mask */
9135#define ADC1MSKI_ATHEX_BBA (*(volatile unsigned long *) 0x4260108C)
9136#define ADC1MSKI_ATHEX_MSK (0x1 << 3 )
9137#define ADC1MSKI_ATHEX (0x1 << 3 )
9138#define ADC1MSKI_ATHEX_DIS (0x0 << 3 ) /* DIS */
9139#define ADC1MSKI_ATHEX_EN (0x1 << 3 ) /* EN */
9140
9141/* ADC1MSKI[THEX] - ADC comparator threshold mask */
9142#define ADC1MSKI_THEX_BBA (*(volatile unsigned long *) 0x42601088)
9143#define ADC1MSKI_THEX_MSK (0x1 << 2 )
9144#define ADC1MSKI_THEX (0x1 << 2 )
9145#define ADC1MSKI_THEX_DIS (0x0 << 2 ) /* DIS */
9146#define ADC1MSKI_THEX_EN (0x1 << 2 ) /* EN */
9147
9148/* ADC1MSKI[OVR] - ADC overrange bit mask. */
9149#define ADC1MSKI_OVR_BBA (*(volatile unsigned long *) 0x42601084)
9150#define ADC1MSKI_OVR_MSK (0x1 << 1 )
9151#define ADC1MSKI_OVR (0x1 << 1 )
9152#define ADC1MSKI_OVR_DIS (0x0 << 1 ) /* DIS */
9153#define ADC1MSKI_OVR_EN (0x1 << 1 ) /* EN */
9154
9155/* ADC1MSKI[RDY] - valid conversion result mask */
9156#define ADC1MSKI_RDY_BBA (*(volatile unsigned long *) 0x42601080)
9157#define ADC1MSKI_RDY_MSK (0x1 << 0 )
9158#define ADC1MSKI_RDY (0x1 << 0 )
9159#define ADC1MSKI_RDY_DIS (0x0 << 0 ) /* DIS */
9160#define ADC1MSKI_RDY_EN (0x1 << 0 ) /* EN */
9161
9162/* Reset Value for ADC1CON*/
9163#define ADC1CON_RVAL 0x303FF
9164
9165/* ADC1CON[ADCEN] - Enable Bit */
9166#define ADC1CON_ADCEN_BBA (*(volatile unsigned long *) 0x4260114C)
9167#define ADC1CON_ADCEN_MSK (0x1 << 19 )
9168#define ADC1CON_ADCEN (0x1 << 19 )
9169#define ADC1CON_ADCEN_DIS (0x0 << 19 ) /* DIS */
9170#define ADC1CON_ADCEN_EN (0x1 << 19 ) /* EN */
9171
9172/* ADC1CON[ADCCODE] - ADC Output Coding bits */
9173#define ADC1CON_ADCCODE_BBA (*(volatile unsigned long *) 0x42601148)
9174#define ADC1CON_ADCCODE_MSK (0x1 << 18 )
9175#define ADC1CON_ADCCODE (0x1 << 18 )
9176#define ADC1CON_ADCCODE_INT (0x0 << 18 ) /* INT */
9177#define ADC1CON_ADCCODE_UINT (0x1 << 18 ) /* UINT */
9178
9179/* ADC1CON[BUFPOWN] - Negative buffer power down */
9180#define ADC1CON_BUFPOWN_BBA (*(volatile unsigned long *) 0x42601144)
9181#define ADC1CON_BUFPOWN_MSK (0x1 << 17 )
9182#define ADC1CON_BUFPOWN (0x1 << 17 )
9183#define ADC1CON_BUFPOWN_DIS (0x0 << 17 ) /* Disable powerdown - Negative buffer is enabled */
9184#define ADC1CON_BUFPOWN_EN (0x1 << 17 ) /* Enable powerdown - Negative buffer is disabled */
9185
9186/* ADC1CON[BUFPOWP] - Positive buffer power down */
9187#define ADC1CON_BUFPOWP_BBA (*(volatile unsigned long *) 0x42601140)
9188#define ADC1CON_BUFPOWP_MSK (0x1 << 16 )
9189#define ADC1CON_BUFPOWP (0x1 << 16 )
9190#define ADC1CON_BUFPOWP_DIS (0x0 << 16 ) /* Disable powerdown - Positive buffer is enabled */
9191#define ADC1CON_BUFPOWP_EN (0x1 << 16 ) /* Enable powerdown - Positive buffer is disabled */
9192
9193/* ADC1CON[BUFBYPP] - Positive buffer bypass */
9194#define ADC1CON_BUFBYPP_BBA (*(volatile unsigned long *) 0x4260113C)
9195#define ADC1CON_BUFBYPP_MSK (0x1 << 15 )
9196#define ADC1CON_BUFBYPP (0x1 << 15 )
9197#define ADC1CON_BUFBYPP_DIS (0x0 << 15 ) /* DIS */
9198#define ADC1CON_BUFBYPP_EN (0x1 << 15 ) /* EN */
9199
9200/* ADC1CON[BUFBYPN] - Negative buffer bypass */
9201#define ADC1CON_BUFBYPN_BBA (*(volatile unsigned long *) 0x42601138)
9202#define ADC1CON_BUFBYPN_MSK (0x1 << 14 )
9203#define ADC1CON_BUFBYPN (0x1 << 14 )
9204#define ADC1CON_BUFBYPN_DIS (0x0 << 14 ) /* DIS */
9205#define ADC1CON_BUFBYPN_EN (0x1 << 14 ) /* EN */
9206
9207/* ADC1CON[ADCREF] - Reference selection */
9208#define ADC1CON_ADCREF_MSK (0x3 << 12 )
9209#define ADC1CON_ADCREF_INTREF (0x0 << 12 ) /* INTREF */
9210#define ADC1CON_ADCREF_EXTREF (0x1 << 12 ) /* EXTREF */
9211#define ADC1CON_ADCREF_EXTREF2 (0x2 << 12 ) /* EXTREF2 */
9212#define ADC1CON_ADCREF_AVDDREF (0x3 << 12 ) /* AVDDREF */
9213
9214/* ADC1CON[ADCDIAG] - Diagnostic Current bits bits */
9215#define ADC1CON_ADCDIAG_MSK (0x3 << 10 )
9216#define ADC1CON_ADCDIAG_DIAG_OFF (0x0 << 10 ) /* DIAG_OFF */
9217#define ADC1CON_ADCDIAG_DIAG_POS (0x1 << 10 ) /* DIAG_POS */
9218#define ADC1CON_ADCDIAG_DIAG_NEG (0x2 << 10 ) /* DIAG_NEG */
9219#define ADC1CON_ADCDIAG_DIAG_ALL (0x3 << 10 ) /* DIAG_ALL */
9220
9221/* ADC1CON[ADCCP] - AIN+ bits */
9222#define ADC1CON_ADCCP_MSK (0x1F << 5 )
9223#define ADC1CON_ADCCP_AIN0 (0x0 << 5 ) /* AIN0 */
9224#define ADC1CON_ADCCP_AIN1 (0x1 << 5 ) /* AIN1 */
9225#define ADC1CON_ADCCP_AIN2 (0x2 << 5 ) /* AIN2 */
9226#define ADC1CON_ADCCP_AIN3 (0x3 << 5 ) /* AIN3 */
9227#define ADC1CON_ADCCP_AIN4 (0x4 << 5 ) /* AIN4 */
9228#define ADC1CON_ADCCP_AIN5 (0x5 << 5 ) /* AIN5 */
9229#define ADC1CON_ADCCP_AIN6 (0x6 << 5 ) /* AIN6 */
9230#define ADC1CON_ADCCP_AIN7 (0x7 << 5 ) /* AIN7 */
9231#define ADC1CON_ADCCP_AIN8 (0x8 << 5 ) /* AIN8 */
9232#define ADC1CON_ADCCP_AIN9 (0x9 << 5 ) /* AIN9 */
9233#define ADC1CON_ADCCP_AIN10 (0xA << 5 ) /* AIN10 */
9234#define ADC1CON_ADCCP_AIN11 (0xB << 5 ) /* AIN11 */
9235#define ADC1CON_ADCCP_DAC (0xC << 5 ) /* DAC */
9236#define ADC1CON_ADCCP_AVDD4 (0xD << 5 ) /* AVDD4 */
9237#define ADC1CON_ADCCP_IOVDD4 (0xE << 5 ) /* IOVDD4 */
9238#define ADC1CON_ADCCP_AGND (0xF << 5 ) /* AGND */
9239#define ADC1CON_ADCCP_TEMP (0x10 << 5 ) /* TEMP */
9240
9241/* ADC1CON[ADCCN] - AIN- bits */
9242#define ADC1CON_ADCCN_MSK (0x1F << 0 )
9243#define ADC1CON_ADCCN_AIN0 (0x0 << 0 ) /* AIN0 */
9244#define ADC1CON_ADCCN_AIN1 (0x1 << 0 ) /* AIN1 */
9245#define ADC1CON_ADCCN_AIN2 (0x2 << 0 ) /* AIN2 */
9246#define ADC1CON_ADCCN_AIN3 (0x3 << 0 ) /* AIN3 */
9247#define ADC1CON_ADCCN_AIN4 (0x4 << 0 ) /* AIN4 */
9248#define ADC1CON_ADCCN_AIN5 (0x5 << 0 ) /* AIN5 */
9249#define ADC1CON_ADCCN_AIN6 (0x6 << 0 ) /* AIN6 */
9250#define ADC1CON_ADCCN_AIN7 (0x7 << 0 ) /* AIN7 */
9251#define ADC1CON_ADCCN_AIN8 (0x8 << 0 ) /* AIN8 */
9252#define ADC1CON_ADCCN_AIN9 (0x9 << 0 ) /* AIN9 */
9253#define ADC1CON_ADCCN_AIN10 (0xA << 0 ) /* AIN10 */
9254#define ADC1CON_ADCCN_AIN11 (0xB << 0 ) /* AIN11 */
9255#define ADC1CON_ADCCN_DAC (0xC << 0 ) /* DAC */
9256#define ADC1CON_ADCCN_AGND (0xF << 0 ) /* AGND */
9257#define ADC1CON_ADCCN_TEMP (0x11 << 0 ) /* TEMP */
9258
9259/* Reset Value for ADC1OF*/
9260#define ADC1OF_RVAL 0x0
9261
9262/* ADC1OF[VALUE] - Offset */
9263#define ADC1OF_VALUE_MSK (0xFFFF << 0 )
9264
9265/* Reset Value for ADC1INTGN*/
9266#define ADC1INTGN_RVAL 0x5555
9267
9268/* ADC1INTGN[VALUE] - Gain with Int Ref */
9269#define ADC1INTGN_VALUE_MSK (0xFFFF << 0 )
9270
9271/* Reset Value for ADC1EXTGN*/
9272#define ADC1EXTGN_RVAL 0x5555
9273
9274/* ADC1EXTGN[VALUE] - Gain with Ext Ref */
9275#define ADC1EXTGN_VALUE_MSK (0xFFFF << 0 )
9276
9277/* Reset Value for ADC1VDDGN*/
9278#define ADC1VDDGN_RVAL 0x5555
9279
9280/* ADC1VDDGN[VALUE] - Gain with Avdd Ref */
9281#define ADC1VDDGN_VALUE_MSK (0xFFFF << 0 )
9282
9283/* Reset Value for ADCSCFG1*/
9284#define ADCSCFG1_RVAL 0xF
9285
9286/* ADCSCFG1[SIMU] - Enable both ADCs */
9287#define ADCSCFG1_SIMU_BBA (*(volatile unsigned long *) 0x426013BC)
9288#define ADCSCFG1_SIMU_MSK (0x1 << 15 )
9289#define ADCSCFG1_SIMU (0x1 << 15 )
9290#define ADCSCFG1_SIMU_DIS (0x0 << 15 ) /* DIS */
9291#define ADCSCFG1_SIMU_EN (0x1 << 15 ) /* EN */
9292
9293/* ADCSCFG1[BOOST30] - Boost the Vbias current source ability by 30 times */
9294#define ADCSCFG1_BOOST30_BBA (*(volatile unsigned long *) 0x426013B4)
9295#define ADCSCFG1_BOOST30_MSK (0x1 << 13 )
9296#define ADCSCFG1_BOOST30 (0x1 << 13 )
9297#define ADCSCFG1_BOOST30_DIS (0x0 << 13 ) /* DIS */
9298#define ADCSCFG1_BOOST30_EN (0x1 << 13 ) /* EN */
9299
9300/* ADCSCFG1[PINSEL] - Enable vbias generator, send vbias to selected ain pin bits */
9301#define ADCSCFG1_PINSEL_MSK (0x7 << 8 )
9302#define ADCSCFG1_PINSEL_DIS (0x0 << 8 ) /* Disable VBIAS generator */
9303#define ADCSCFG1_PINSEL_AIN7 (0x4 << 8 ) /* AIN7 */
9304#define ADCSCFG1_PINSEL_AIN11 (0x6 << 8 ) /* AIN11 */
9305
9306/* ADCSCFG1[GNDSWON] - GND_SW */
9307#define ADCSCFG1_GNDSWON_BBA (*(volatile unsigned long *) 0x4260139C)
9308#define ADCSCFG1_GNDSWON_MSK (0x1 << 7 )
9309#define ADCSCFG1_GNDSWON (0x1 << 7 )
9310#define ADCSCFG1_GNDSWON_DIS (0x0 << 7 ) /* DIS */
9311#define ADCSCFG1_GNDSWON_EN (0x1 << 7 ) /* EN */
9312
9313/* ADCSCFG1[GNDSWRESEN] - 20k resistor in series with GND_SW */
9314#define ADCSCFG1_GNDSWRESEN_BBA (*(volatile unsigned long *) 0x42601398)
9315#define ADCSCFG1_GNDSWRESEN_MSK (0x1 << 6 )
9316#define ADCSCFG1_GNDSWRESEN (0x1 << 6 )
9317#define ADCSCFG1_GNDSWRESEN_DIS (0x0 << 6 ) /* DIS */
9318#define ADCSCFG1_GNDSWRESEN_EN (0x1 << 6 ) /* EN */
9319
9320/* ADCSCFG1[EXTBUF] - Control signals for ext_ref buffers bits */
9321#define ADCSCFG1_EXTBUF_MSK (0x3 << 0 )
9322#define ADCSCFG1_EXTBUF_OFF (0x0 << 0 ) /* OFF */
9323#define ADCSCFG1_EXTBUF_VREFPN (0x1 << 0 ) /* VREFPN */
9324#define ADCSCFG1_EXTBUF_VREFP_VREF2P (0x2 << 0 ) /* VREFP_VREF2P */
9325
9326/* Reset Value for ADC1FLT*/
9327#define ADC1FLT_RVAL 0x7D
9328
9329/* ADC1FLT[CHOP] - Enables System-Chopping bits */
9330#define ADC1FLT_CHOP_BBA (*(volatile unsigned long *) 0x4260143C)
9331#define ADC1FLT_CHOP_MSK (0x1 << 15 )
9332#define ADC1FLT_CHOP (0x1 << 15 )
9333#define ADC1FLT_CHOP_OFF (0x0 << 15 ) /* OFF */
9334#define ADC1FLT_CHOP_ON (0x1 << 15 ) /* ON */
9335
9336/* ADC1FLT[RAVG2] - Enables a running Average-By-2 bits */
9337#define ADC1FLT_RAVG2_BBA (*(volatile unsigned long *) 0x42601438)
9338#define ADC1FLT_RAVG2_MSK (0x1 << 14 )
9339#define ADC1FLT_RAVG2 (0x1 << 14 )
9340#define ADC1FLT_RAVG2_OFF (0x0 << 14 ) /* OFF */
9341#define ADC1FLT_RAVG2_ON (0x1 << 14 ) /* ON */
9342
9343/* ADC1FLT[SINC4EN] - Enable the Sinc4 filter instead of Sinc3 filter. */
9344#define ADC1FLT_SINC4EN_BBA (*(volatile unsigned long *) 0x42601430)
9345#define ADC1FLT_SINC4EN_MSK (0x1 << 12 )
9346#define ADC1FLT_SINC4EN (0x1 << 12 )
9347#define ADC1FLT_SINC4EN_DIS (0x0 << 12 ) /* DIS */
9348#define ADC1FLT_SINC4EN_EN (0x1 << 12 ) /* EN */
9349
9350/* ADC1FLT[AF] - Averaging filter */
9351#define ADC1FLT_AF_MSK (0xF << 8 )
9352
9353/* ADC1FLT[NOTCH2] - Inserts a notch at FNOTCH2 */
9354#define ADC1FLT_NOTCH2_BBA (*(volatile unsigned long *) 0x4260141C)
9355#define ADC1FLT_NOTCH2_MSK (0x1 << 7 )
9356#define ADC1FLT_NOTCH2 (0x1 << 7 )
9357#define ADC1FLT_NOTCH2_DIS (0x0 << 7 ) /* DIS */
9358#define ADC1FLT_NOTCH2_EN (0x1 << 7 ) /* EN */
9359
9360/* ADC1FLT[SF] - SINC Filter value */
9361#define ADC1FLT_SF_MSK (0x7F << 0 )
9362
9363/* Reset Value for ADC1MDE*/
9364#define ADC1MDE_RVAL 0x0
9365
9366/* ADC1MDE[PGA] - PGA Gain Select bit */
9367#define ADC1MDE_PGA_MSK (0xF << 4 )
9368#define ADC1MDE_PGA_G1 (0x0 << 4 ) /* G1 */
9369#define ADC1MDE_PGA_G2 (0x1 << 4 ) /* G2 */
9370#define ADC1MDE_PGA_G4 (0x2 << 4 ) /* G4 */
9371#define ADC1MDE_PGA_G8 (0x3 << 4 ) /* G8 */
9372#define ADC1MDE_PGA_G16 (0x4 << 4 ) /* G16 */
9373#define ADC1MDE_PGA_G32 (0x5 << 4 ) /* G32 */
9374#define ADC1MDE_PGA_G64 (0x6 << 4 ) /* G64 */
9375#define ADC1MDE_PGA_G128 (0x7 << 4 ) /* G128 */
9376
9377/* ADC1MDE[ADCMOD2] - ADC modulator gain of 2 control bits */
9378#define ADC1MDE_ADCMOD2_BBA (*(volatile unsigned long *) 0x4260148C)
9379#define ADC1MDE_ADCMOD2_MSK (0x1 << 3 )
9380#define ADC1MDE_ADCMOD2 (0x1 << 3 )
9381#define ADC1MDE_ADCMOD2_MOD2OFF (0x0 << 3 ) /* MOD2OFF */
9382#define ADC1MDE_ADCMOD2_MOD2ON (0x1 << 3 ) /* MOD2ON */
9383
9384/* ADC1MDE[ADCMD] - ADC Mode bits */
9385#define ADC1MDE_ADCMD_MSK (0x7 << 0 )
9386#define ADC1MDE_ADCMD_OFF (0x0 << 0 ) /* OFF */
9387#define ADC1MDE_ADCMD_CONT (0x1 << 0 ) /* CONT */
9388#define ADC1MDE_ADCMD_SINGLE (0x2 << 0 ) /* SINGLE */
9389#define ADC1MDE_ADCMD_IDLE (0x3 << 0 ) /* IDLE */
9390#define ADC1MDE_ADCMD_INTOCAL (0x4 << 0 ) /* INTOCAL */
9391#define ADC1MDE_ADCMD_INTGCAL (0x5 << 0 ) /* INTGCAL */
9392#define ADC1MDE_ADCMD_SYSOCAL (0x6 << 0 ) /* SYSOCAL */
9393#define ADC1MDE_ADCMD_SYSGCAL (0x7 << 0 ) /* SYSGCAL */
9394
9395/* Reset Value for ADC1RCR*/
9396#define ADC1RCR_RVAL 0x1
9397
9398/* ADC1RCR[VALUE] - */
9399#define ADC1RCR_VALUE_MSK (0xFFFF << 0 )
9400
9401/* Reset Value for ADC1RCV*/
9402#define ADC1RCV_RVAL 0x0
9403
9404/* ADC1RCV[VALUE] - */
9405#define ADC1RCV_VALUE_MSK (0xFFFF << 0 )
9406
9407/* Reset Value for ADC1TH*/
9408#define ADC1TH_RVAL 0x0
9409
9410/* ADC1TH[VALUE] - */
9411#define ADC1TH_VALUE_MSK (0xFFFF << 0 )
9412
9413/* Reset Value for ADC1THC*/
9414#define ADC1THC_RVAL 0x1
9415
9416/* ADC1THC[VALUE] - */
9417#define ADC1THC_VALUE_MSK (0xFF << 0 )
9418
9419/* Reset Value for ADC1THV*/
9420#define ADC1THV_RVAL 0x0
9421
9422/* ADC1THV[VALUE] - */
9423#define ADC1THV_VALUE_MSK (0xFF << 0 )
9424
9425/* Reset Value for ADC1ACC*/
9426#define ADC1ACC_RVAL 0x0
9427
9428/* ADC1ACC[VALUE] - */
9429#define ADC1ACC_VALUE_MSK (0xFFFFFFFF << 0 )
9430
9431/* Reset Value for ADC1ATH*/
9432#define ADC1ATH_RVAL 0x0
9433
9434/* ADC1ATH[VALUE] - */
9435#define ADC1ATH_VALUE_MSK (0xFFFFFFFF << 0 )
9436
9437/* Reset Value for ADC1PRO*/
9438#define ADC1PRO_RVAL 0x0
9439
9440/* ADC1PRO[ACCEN] - ADC Accumulator Enable bits */
9441#define ADC1PRO_ACCEN_MSK (0x3 << 4 )
9442#define ADC1PRO_ACCEN_Off (0x0 << 4 ) /* Off */
9443#define ADC1PRO_ACCEN_En (0x1 << 4 ) /* En */
9444#define ADC1PRO_ACCEN_EnNDec (0x2 << 4 ) /* EnNDec */
9445#define ADC1PRO_ACCEN_EnAccCnt (0x3 << 4 ) /* EnAccCnt */
9446
9447/* ADC1PRO[CMPEN] - ADC Comparator Enable bits */
9448#define ADC1PRO_CMPEN_MSK (0x3 << 2 )
9449#define ADC1PRO_CMPEN_Off (0x0 << 2 ) /* Off */
9450#define ADC1PRO_CMPEN_En (0x1 << 2 ) /* En */
9451#define ADC1PRO_CMPEN_EnCnt (0x2 << 2 ) /* EnCnt */
9452#define ADC1PRO_CMPEN_EnCntDec (0x3 << 2 ) /* EnCntDec */
9453
9454/* ADC1PRO[OREN] - ADC OverRange Enable */
9455#define ADC1PRO_OREN_BBA (*(volatile unsigned long *) 0x42601884)
9456#define ADC1PRO_OREN_MSK (0x1 << 1 )
9457#define ADC1PRO_OREN (0x1 << 1 )
9458#define ADC1PRO_OREN_DIS (0x0 << 1 ) /* DIS */
9459#define ADC1PRO_OREN_EN (0x1 << 1 ) /* EN */
9460
9461/* ADC1PRO[RCEN] - ADC Result Counter Enable */
9462#define ADC1PRO_RCEN_BBA (*(volatile unsigned long *) 0x42601880)
9463#define ADC1PRO_RCEN_MSK (0x1 << 0 )
9464#define ADC1PRO_RCEN (0x1 << 0 )
9465#define ADC1PRO_RCEN_DIS (0x0 << 0 ) /* DIS */
9466#define ADC1PRO_RCEN_EN (0x1 << 0 ) /* EN */
9467
9468/* Reset Value for ADC1DAT*/
9469#define ADC1DAT_RVAL 0x0
9470
9471/* ADC1DAT[VALUE] - */
9472#define ADC1DAT_VALUE_MSK (0xFFFFFFFF << 0 )
9473// ------------------------------------------------------------------------------------------------
9474// ----- ADCSTEP -----
9475// ------------------------------------------------------------------------------------------------
9476
9477
9478/**
9479 * @brief Analog to Digital Converter (pADI_ADCSTEP)
9480 */
9481
9482#if (__NO_MMR_STRUCTS__==0)
9483typedef struct { /*!< pADI_ADCSTEP Structure */
9484 __IO uint16_t DETCON; /*!< Control register for reference detection and the step detection filter */
9485 __I uint16_t RESERVED0;
9486 __IO uint8_t DETSTA; /*!< Status register for detection */
9487 __I uint8_t RESERVED1[3];
9488 __IO uint16_t STEPTH; /*!< Threshold for step detection filter */
9489 __I uint16_t RESERVED2;
9490 __IO uint32_t STEPDAT; /*!< Offers coarse data from the output of the step detection filter */
9491} ADI_ADCSTEP_TypeDef;
9492#else // (__NO_MMR_STRUCTS__==0)
9493#define DETCON (*(volatile unsigned short int *) 0x400300E0)
9494#define DETSTA (*(volatile unsigned char *) 0x400300E4)
9495#define STEPTH (*(volatile unsigned short int *) 0x400300E8)
9496#define STEPDAT (*(volatile unsigned long *) 0x400300EC)
9497#endif // (__NO_MMR_STRUCTS__==0)
9498
9499/* Reset Value for DETCON*/
9500#define DETCON_RVAL 0x0
9501
9502/* DETCON[REFDET] - Enable external reference detection circuit */
9503#define DETCON_REFDET_BBA (*(volatile unsigned long *) 0x42601C20)
9504#define DETCON_REFDET_MSK (0x1 << 8 )
9505#define DETCON_REFDET (0x1 << 8 )
9506#define DETCON_REFDET_DIS (0x0 << 8 ) /* DIS */
9507#define DETCON_REFDET_EN (0x1 << 8 ) /* EN */
9508
9509/* DETCON[SINC2] - Enable Sinc2 filter */
9510#define DETCON_SINC2_BBA (*(volatile unsigned long *) 0x42601C1C)
9511#define DETCON_SINC2_MSK (0x1 << 7 )
9512#define DETCON_SINC2 (0x1 << 7 )
9513#define DETCON_SINC2_DIS (0x0 << 7 ) /* DIS */
9514#define DETCON_SINC2_EN (0x1 << 7 ) /* EN */
9515
9516/* DETCON[STEPCTRL] - Control the method to generate the step flag */
9517#define DETCON_STEPCTRL_BBA (*(volatile unsigned long *) 0x42601C0C)
9518#define DETCON_STEPCTRL_MSK (0x1 << 3 )
9519#define DETCON_STEPCTRL (0x1 << 3 )
9520#define DETCON_STEPCTRL_DIS (0x0 << 3 ) /* DIS */
9521#define DETCON_STEPCTRL_EN (0x1 << 3 ) /* EN */
9522
9523/* DETCON[ADCSEL] - Select ADC */
9524#define DETCON_ADCSEL_BBA (*(volatile unsigned long *) 0x42601C08)
9525#define DETCON_ADCSEL_MSK (0x1 << 2 )
9526#define DETCON_ADCSEL (0x1 << 2 )
9527#define DETCON_ADCSEL_DIS (0x0 << 2 ) /* DIS */
9528#define DETCON_ADCSEL_EN (0x1 << 2 ) /* EN */
9529
9530/* DETCON[RATE] - Control the sinc2 filter's time interval */
9531#define DETCON_RATE_MSK (0x3 << 0 )
9532
9533/* Reset Value for DETSTA*/
9534#define DETSTA_RVAL 0x0
9535
9536/* DETSTA[REFSTA] - */
9537#define DETSTA_REFSTA_BBA (*(volatile unsigned long *) 0x42601C90)
9538#define DETSTA_REFSTA_MSK (0x1 << 4 )
9539#define DETSTA_REFSTA (0x1 << 4 )
9540#define DETSTA_REFSTA_DIS (0x0 << 4 ) /* DIS */
9541#define DETSTA_REFSTA_EN (0x1 << 4 ) /* EN */
9542
9543/* DETSTA[DATOF] - STEPDAT Overflow */
9544#define DETSTA_DATOF_BBA (*(volatile unsigned long *) 0x42601C8C)
9545#define DETSTA_DATOF_MSK (0x1 << 3 )
9546#define DETSTA_DATOF (0x1 << 3 )
9547#define DETSTA_DATOF_DIS (0x0 << 3 ) /* DIS */
9548#define DETSTA_DATOF_EN (0x1 << 3 ) /* EN */
9549
9550/* DETSTA[STEPERR] - */
9551#define DETSTA_STEPERR_BBA (*(volatile unsigned long *) 0x42601C88)
9552#define DETSTA_STEPERR_MSK (0x1 << 2 )
9553#define DETSTA_STEPERR (0x1 << 2 )
9554#define DETSTA_STEPERR_DIS (0x0 << 2 ) /* DIS */
9555#define DETSTA_STEPERR_EN (0x1 << 2 ) /* EN */
9556
9557/* DETSTA[STEPFLAG] - */
9558#define DETSTA_STEPFLAG_BBA (*(volatile unsigned long *) 0x42601C84)
9559#define DETSTA_STEPFLAG_MSK (0x1 << 1 )
9560#define DETSTA_STEPFLAG (0x1 << 1 )
9561#define DETSTA_STEPFLAG_DIS (0x0 << 1 ) /* DIS */
9562#define DETSTA_STEPFLAG_EN (0x1 << 1 ) /* EN */
9563
9564/* DETSTA[STEPDATRDY] - */
9565#define DETSTA_STEPDATRDY_BBA (*(volatile unsigned long *) 0x42601C80)
9566#define DETSTA_STEPDATRDY_MSK (0x1 << 0 )
9567#define DETSTA_STEPDATRDY (0x1 << 0 )
9568#define DETSTA_STEPDATRDY_DIS (0x0 << 0 ) /* DIS */
9569#define DETSTA_STEPDATRDY_EN (0x1 << 0 ) /* EN */
9570
9571/* Reset Value for STEPTH*/
9572#define STEPTH_RVAL 0x0
9573
9574/* STEPTH[VALUE] - */
9575#define STEPTH_VALUE_MSK (0x1FF << 0 )
9576
9577/* Reset Value for STEPDAT*/
9578#define STEPDAT_RVAL 0x0
9579
9580/* STEPDAT[VALUE] - */
9581#define STEPDAT_VALUE_MSK (0xFFFFFFFF << 0 )
9582// ------------------------------------------------------------------------------------------------
9583// ----- ADCDMA -----
9584// ------------------------------------------------------------------------------------------------
9585
9586
9587/**
9588 * @brief Analog to Digital Converter (pADI_ADCDMA)
9589 */
9590
9591#if (__NO_MMR_STRUCTS__==0)
9592typedef struct { /*!< pADI_ADCDMA Structure */
9593 __I uint32_t RESERVED0[2];
9594 __IO uint16_t ADCDMACON; /*!< ADC DMA mode Configuration register */
9595} ADI_ADCDMA_TypeDef;
9596#else // (__NO_MMR_STRUCTS__==0)
9597#define ADCDMACON (*(volatile unsigned short int *) 0x400300F8)
9598#endif // (__NO_MMR_STRUCTS__==0)
9599
9600/* Reset Value for ADCDMACON*/
9601#define ADCDMACON_RVAL 0x0
9602
9603/* ADCDMACON[SINC2DMAEN] - */
9604#define ADCDMACON_SINC2DMAEN_BBA (*(volatile unsigned long *) 0x42601F10)
9605#define ADCDMACON_SINC2DMAEN_MSK (0x1 << 4 )
9606#define ADCDMACON_SINC2DMAEN (0x1 << 4 )
9607#define ADCDMACON_SINC2DMAEN_DIS (0x0 << 4 ) /* DIS */
9608#define ADCDMACON_SINC2DMAEN_EN (0x1 << 4 ) /* EN */
9609
9610/* ADCDMACON[ADC1DMAEN] - */
9611#define ADCDMACON_ADC1DMAEN_BBA (*(volatile unsigned long *) 0x42601F0C)
9612#define ADCDMACON_ADC1DMAEN_MSK (0x1 << 3 )
9613#define ADCDMACON_ADC1DMAEN (0x1 << 3 )
9614#define ADCDMACON_ADC1DMAEN_DIS (0x0 << 3 ) /* DIS */
9615#define ADCDMACON_ADC1DMAEN_EN (0x1 << 3 ) /* EN */
9616
9617/* ADCDMACON[ADC1CTRL] - */
9618#define ADCDMACON_ADC1CTRL_BBA (*(volatile unsigned long *) 0x42601F08)
9619#define ADCDMACON_ADC1CTRL_MSK (0x1 << 2 )
9620#define ADCDMACON_ADC1CTRL (0x1 << 2 )
9621#define ADCDMACON_ADC1CTRL_DIS (0x0 << 2 ) /* DIS */
9622#define ADCDMACON_ADC1CTRL_EN (0x1 << 2 ) /* EN */
9623
9624// ------------------------------------------------------------------------------------------------
9625// ----- DAC -----
9626// ------------------------------------------------------------------------------------------------
9627
9628
9629/**
9630 * @brief Digital To Analog Converter (pADI_DAC)
9631 */
9632
9633#if (__NO_MMR_STRUCTS__==0)
9634typedef struct { /*!< pADI_DAC Structure */
9635 __IO uint16_t DACCON; /*!< Control Register */
9636 __I uint16_t RESERVED0;
9637 __IO uint32_t DACDAT; /*!< Data Register */
9638} ADI_DAC_TypeDef;
9639#else // (__NO_MMR_STRUCTS__==0)
9640#define DACCON (*(volatile unsigned short int *) 0x40020000)
9641#define DACDAT (*(volatile unsigned long *) 0x40020004)
9642#endif // (__NO_MMR_STRUCTS__==0)
9643
9644/* Reset Value for DACCON*/
9645#define DACCON_RVAL 0x200
9646
9647/* DACCON[DMAEN] - bits */
9648#define DACCON_DMAEN_BBA (*(volatile unsigned long *) 0x42400028)
9649#define DACCON_DMAEN_MSK (0x1 << 10 )
9650#define DACCON_DMAEN (0x1 << 10 )
9651#define DACCON_DMAEN_Off (0x0 << 10 ) /* Off */
9652#define DACCON_DMAEN_On (0x1 << 10 ) /* On */
9653
9654/* DACCON[PD] - */
9655#define DACCON_PD_BBA (*(volatile unsigned long *) 0x42400024)
9656#define DACCON_PD_MSK (0x1 << 9 )
9657#define DACCON_PD (0x1 << 9 )
9658#define DACCON_PD_DIS (0x0 << 9 ) /* DIS */
9659#define DACCON_PD_EN (0x1 << 9 ) /* EN */
9660
9661/* DACCON[NPN] - */
9662#define DACCON_NPN_BBA (*(volatile unsigned long *) 0x42400020)
9663#define DACCON_NPN_MSK (0x1 << 8 )
9664#define DACCON_NPN (0x1 << 8 )
9665#define DACCON_NPN_DIS (0x0 << 8 ) /* DIS */
9666#define DACCON_NPN_EN (0x1 << 8 ) /* EN */
9667
9668/* DACCON[BUFBYP] - */
9669#define DACCON_BUFBYP_BBA (*(volatile unsigned long *) 0x42400018)
9670#define DACCON_BUFBYP_MSK (0x1 << 6 )
9671#define DACCON_BUFBYP (0x1 << 6 )
9672#define DACCON_BUFBYP_DIS (0x0 << 6 ) /* DIS */
9673#define DACCON_BUFBYP_EN (0x1 << 6 ) /* EN */
9674
9675/* DACCON[CLK] - bits */
9676#define DACCON_CLK_BBA (*(volatile unsigned long *) 0x42400014)
9677#define DACCON_CLK_MSK (0x1 << 5 )
9678#define DACCON_CLK (0x1 << 5 )
9679#define DACCON_CLK_HCLK (0x0 << 5 ) /* HCLK */
9680#define DACCON_CLK_Timer1 (0x1 << 5 ) /* Timer1 */
9681
9682/* DACCON[CLR] - bits */
9683#define DACCON_CLR_BBA (*(volatile unsigned long *) 0x42400010)
9684#define DACCON_CLR_MSK (0x1 << 4 )
9685#define DACCON_CLR (0x1 << 4 )
9686#define DACCON_CLR_Off (0x1 << 4 ) /* Off */
9687#define DACCON_CLR_On (0x0 << 4 ) /* On */
9688
9689/* DACCON[MDE] - Mode bits */
9690#define DACCON_MDE_MSK (0x3 << 2 )
9691#define DACCON_MDE_12bit (0x0 << 2 ) /* 12bit */
9692#define DACCON_MDE_16BitSlow (0x3 << 2 ) /* 16BitSlow */
9693#define DACCON_MDE_16BitFast (0x2 << 2 ) /* 16BitFast */
9694
9695/* DACCON[RNG] - DAC Range bits */
9696#define DACCON_RNG_MSK (0x3 << 0 )
9697#define DACCON_RNG_IntVref (0x0 << 0 ) /* IntVref */
9698#define DACCON_RNG_AVdd (0x3 << 0 ) /* AVdd */
9699
9700/* Reset Value for DACDAT*/
9701#define DACDAT_RVAL 0x0
9702
9703/* DACDAT[VALUE] - Data */
9704#define DACDAT_VALUE_MSK (0xFFFFF << 12 )
9705/********************************************
9706** End of section using anonymous unions **
9707*********************************************/
9708
9709#if defined(__ARMCC_VERSION)
9710 #pragma pop
9711#elif defined(__CWCC__)
9712 #pragma pop
9713#elif defined(__GNUC__)
9714 /* leave anonymous unions enabled */
9715#elif defined(__IAR_SYSTEMS_ICC__)
9716 #pragma language=default
9717#else
9718 #error Not supported compiler type
9719#endif
9720
9721/********************************************
9722** Miscellaneous Definitions **
9723*********************************************/
9724
9725//iEiNr in EiCfg()
9726#define EXTINT0 0x0
9727#define EXTINT1 0x1
9728#define EXTINT2 0x2
9729#define EXTINT3 0x3
9730#define EXTINT4 0x4
9731#define EXTINT5 0x5
9732#define EXTINT6 0x6
9733#define EXTINT7 0x7
9734#define EXTINT8 0x8
9735
9736//iEnable in EiCfg()
9737#define INT_DIS 0x0
9738#define INT_EN 0x1
9739
9740//iMode in EiCfg()
9741#define INT_RISE 0x0
9742#define INT_FALL 0x1
9743#define INT_EDGES 0x2
9744#define INT_HIGH 0x3
9745#define INT_LOW 0x4
9746
9747//Bit values.
9748#define BIT0 1
9749#define BIT1 2
9750#define BIT2 4
9751#define BIT3 8
9752#define BIT4 0x10
9753#define BIT5 0x20
9754#define BIT6 0x40
9755#define BIT7 0x80
9756
9757
9758// ------------------------------------------------------------------------------------------------
9759// ----- Peripheral memory map -----
9760// ------------------------------------------------------------------------------------------------
9761#define ADI_TM0_ADDR 0x40000000
9762#define ADI_TM1_ADDR 0x40000400
9763#define ADI_PWM_ADDR 0x40001000
9764#define ADI_PWRCTL_ADDR 0x40002400
9765#define ADI_RESET_ADDR 0x40002440
9766#define ADI_INTERRUPT_ADDR 0x40002420
9767#define ADI_WDT_ADDR 0x40002580
9768#define ADI_WUT_ADDR 0x40002500
9769#define ADI_CLKCTL_ADDR 0x40002000
9770#define ADI_FEE_ADDR 0x40002800
9771#define ADI_I2C_ADDR 0x40003000
9772#define ADI_SPI0_ADDR 0x40004000
9773#define ADI_SPI1_ADDR 0x40004400
9774#define ADI_UART_ADDR 0x40005000
9775#define ADI_UART1_ADDR 0x40005400
9776#define ADI_UART2_ADDR 0x40005800
9777#define ADI_GP0_ADDR 0x40006000
9778#define ADI_GP1_ADDR 0x40006030
9779#define ADI_GP2_ADDR 0x40006060
9780#define ADI_GP3_ADDR 0x40006090
9781#define ADI_ANA_ADDR 0x40008810
9782#define ADI_DMA_ADDR 0x40010000
9783#define ADI_NVIC_ADDR 0xE000E000
9784#define ADI_ADC1_ADDR 0x40030080
9785#define ADI_ADCSTEP_ADDR 0x400300E0
9786#define ADI_ADCTEST_ADDR 0x40030050
9787#define ADI_ADCDMA_ADDR 0x400300F0
9788#define ADI_EREFBUF_ADDR 0x400300D0
9789#define ADI_DAC_ADDR 0x40020000
9790
9791// ------------------------------------------------------------------------------------------------
9792// ----- Peripheral declaration -----
9793// ------------------------------------------------------------------------------------------------
9794#define pADI_TM0 ((ADI_TIMER_TypeDef *)ADI_TM0_ADDR)
9795#define pADI_TM1 ((ADI_TIMER_TypeDef *)ADI_TM1_ADDR)
9796#define pADI_PWM ((ADI_PWM_TypeDef *)ADI_PWM_ADDR)
9797#define pADI_PWRCTL ((ADI_PWRCTL_TypeDef *)ADI_PWRCTL_ADDR)
9798#define pADI_RESET ((ADI_RESET_TypeDef *)ADI_RESET_ADDR)
9799#define pADI_INTERRUPT ((ADI_INTERRUPT_TypeDef *)ADI_INTERRUPT_ADDR)
9800#define pADI_WDT ((ADI_WDT_TypeDef *)ADI_WDT_ADDR)
9801#define pADI_WUT ((ADI_WUT_TypeDef *)ADI_WUT_ADDR)
9802#define pADI_CLKCTL ((ADI_CLKCTL_TypeDef *)ADI_CLKCTL_ADDR)
9803#define pADI_FEE ((ADI_FEE_TypeDef *)ADI_FEE_ADDR)
9804#define pADI_I2C ((ADI_I2C_TypeDef *)ADI_I2C_ADDR)
9805#define pADI_SPI0 ((ADI_SPI_TypeDef *)ADI_SPI0_ADDR)
9806#define pADI_SPI1 ((ADI_SPI_TypeDef *)ADI_SPI1_ADDR)
9807#define pADI_UART ((ADI_UART_TypeDef *)ADI_UART_ADDR)
9808#define pADI_UART1 ((ADI_UART_TypeDef *)ADI_UART1_ADDR)
9809#define pADI_UART2 ((ADI_UART_TypeDef *)ADI_UART2_ADDR)
9810#define pADI_GP0 ((ADI_GPIO_TypeDef *)ADI_GP0_ADDR)
9811#define pADI_GP1 ((ADI_GPIO_TypeDef *)ADI_GP1_ADDR)
9812#define pADI_GP2 ((ADI_GPIO_TypeDef *)ADI_GP2_ADDR)
9813#define pADI_GP3 ((ADI_GPIO_TypeDef *)ADI_GP3_ADDR)
9814#define pADI_ANA ((ADI_ANA_TypeDef *)ADI_ANA_ADDR)
9815#define pADI_DMA ((ADI_DMA_TypeDef *)ADI_DMA_ADDR)
9816#define pADI_ADC1 ((ADI_ADC_TypeDef *)ADI_ADC1_ADDR)
9817#define pADI_ADCSTEP ((ADI_ADCSTEP_TypeDef *)ADI_ADCSTEP_ADDR)
9818#define pADI_ADCDMA ((ADI_ADCDMA_TypeDef *)ADI_ADCDMA_ADDR)
9819#define pADI_DAC ((ADI_DAC_TypeDef *)ADI_DAC_ADDR)
9820
9821/** @} */ /* End of group Device_Peripheral_Registers */
9822/** @} */ /* End of group ADUCM363 */
9823/** @} */ /* End of group CMSIS */
9824
9825#ifdef __cplusplus
9826}
9827#endif
9828
9829
9830#endif // __ADUCM363_H__
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 05:25:04 +0100