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1/* ================================================================================
2 Project : ADuCM410
3 File : ADuCM410_device.h
4 Description : C typedef structures for bit-fields and enums for enumerations.
5
6 Copyright (c) 2019 Analog Devices, Inc. All Rights Reserved.
7 This software is proprietary and confidential to Analog Devices, Inc. and
8 its licensors.
9
10 This file was auto-generated. Do not make local changes to this file.
11 ================================================================================ */
12
13#ifndef __ADUCM410_H__
14#define __ADUCM410_H__
15
16/* =========================================================================
17 *! \enum IRQn_Type
18 *! \brief Interrupt Number Assignments
19 * ========================================================================= */
20
21typedef enum
22{
23 RESET_IRQn = -15, /*!<* RESET */
24 NonMaskableInt_IRQn = -14, /*!<* NonMaskableInt */
25 HardFault_IRQn = -13, /*!<* HardFault */
26 MemoryManagement_IRQn = -12, /*!<* MemoryManagement */
27 BusFault_IRQn = -11, /*!<* BusFault */
28 UsageFault_IRQn = -10, /*!<* UsageFault */
29 SVCall_IRQn = -5, /*!<* SVCall */
30 DebugMonitor_IRQn = -4, /*!<* DebugMonitor */
31 PendSV_IRQn = -2, /*!<* PendSV */
32 SysTick_IRQn = -1, /*!<* SysTick */
33 WUT_IRQn = 0, /*!<* WUT */
34 EINT0_IRQn = 1, /*!<* EINT0 */
35 EINT1_IRQn = 2, /*!<* EINT1 */
36 EINT2_IRQn = 3, /*!<* EINT2 */
37 EINT3_IRQn = 4, /*!<* EINT3 */
38 EINT4_IRQn = 5, /*!<* EINT4 */
39 EINT5_IRQn = 6, /*!<* EINT5 */
40 EINT6_IRQn = 7, /*!<* EINT6 */
41 EINT7_IRQn = 8, /*!<* EINT7 */
42 EINT8_IRQn = 9, /*!<* EINT8 */
43 EINT9_IRQn = 10, /*!<* EINT9 */
44 WDT_IRQn = 11, /*!<* WDT */
45 GPT0_IRQn = 12, /*!<* GPT0 */
46 GPT1_IRQn = 13, /*!<* GPT1 */
47 GPT2_IRQn = 14, /*!<* GPT2 */
48 GPT3_IRQn = 15, /*!<* GPT3 */
49 GPT4_IRQn = 16, /*!<* GPT4 */
50 MDIO_IRQn = 17, /*!<* MDIO */
51 FLASH_IRQn = 18, /*!<* FLASH */
52 UART0_IRQn = 19, /*!<* UART0 */
53 UART1_IRQn = 20, /*!<* UART1 */
54 SPI0_IRQn = 21, /*!<* SPI0 */
55 SPI1_IRQn = 22, /*!<* SPI1 */
56 SPI2_IRQn = 23, /*!<* SPI2 */
57 I2C0S_IRQn = 24, /*!<* I2C0S */
58 I2C0M_IRQn = 25, /*!<* I2C0M */
59 I2C1S_IRQn = 26, /*!<* I2C1S */
60 I2C1M_IRQn = 27, /*!<* I2C1M */
61 I2C2S_IRQn = 28, /*!<* I2C2S */
62 I2C2M_IRQn = 29, /*!<* I2C2M */
63 PLA0_IRQn = 30, /*!<* PLA0 */
64 PLA1_IRQn = 31, /*!<* PLA1 */
65 PLA2_IRQn = 32, /*!<* PLA2 */
66 PLA3_IRQn = 33, /*!<* PLA3 */
67 PWM_TRIP_IRQn = 34, /*!<* PWM_TRIP */
68 PWM0_IRQn = 35, /*!<* PWM0 */
69 PWM1_IRQn = 36, /*!<* PWM1 */
70 PWM2_IRQn = 37, /*!<* PWM2 */
71 PWM3_IRQn = 38, /*!<* PWM3 */
72 SRAM_ERR_IRQn = 39, /*!<* SRAM_ERR */
73 DMA_ERR_IRQn = 40, /*!<* DMA_ERR */
74 DMA_SPI0_TX_IRQn = 41, /*!<* DMA_SPI0_TX */
75 DMA_SPI0_RX_IRQn = 42, /*!<* DMA_SPI0_RX */
76 DMA_SPI1_TX_IRQn = 43, /*!<* DMA_SPI1_TX */
77 DMA_SPI1_RX_IRQn = 44, /*!<* DMA_SPI1_RX */
78 DMA_SPI2_TX_IRQn = 45, /*!<* DMA_SPI2_TX */
79 DMA_SPI2_RX_IRQn = 46, /*!<* DMA_SPI2_RX */
80 DMA_UART0_TX_IRQn = 47, /*!<* DMA_UART0_TX */
81 DMA_UART0_RX_IRQn = 48, /*!<* DMA_UART0_RX */
82 DMA_UART1_TX_IRQn = 49, /*!<* DMA_UART1_TX */
83 DMA_UART1_RX_IRQn = 50, /*!<* DMA_UART1_RX */
84 DMA_I2C0S_TX_IRQn = 51, /*!<* DMA_I2C0S_TX */
85 DMA_I2C0S_RX_IRQn = 52, /*!<* DMA_I2C0S_RX */
86 DMA_I2C0M_IRQn = 53, /*!<* DMA_I2C0M */
87 DMA_I2C1S_TX_IRQn = 54, /*!<* DMA_I2C1S_TX */
88 DMA_I2C1S_RX_IRQn = 55, /*!<* DMA_I2C1S_RX */
89 DMA_I2C1M_IRQn = 56, /*!<* DMA_I2C1M */
90 DMA_I2C2S_TX_IRQn = 57, /*!<* DMA_I2C2S_TX */
91 DMA_I2C2S_RX_IRQn = 58, /*!<* DMA_I2C2S_RX */
92 DMA_I2C2M_IRQn = 59, /*!<* DMA_I2C2M */
93 DMA_MDIO_TX_IRQn = 60, /*!<* DMA_MDIO_TX */
94 DMA_MDIO_RX_IRQn = 61, /*!<* DMA_MDIO_RX */
95 DMA_FLASH_IRQn = 62, /*!<* DMA_FLASH */
96 DMA_ADC_IRQn = 63, /*!<* DMA_ADC */
97 PLL_IRQn = 64, /*!<* PLL */
98 HFOSC_IRQn = 65, /*!<* HFOSC */
99 ADC_IRQn = 66, /*!<* ADC */
100 SEQ_IRQn = 67, /*!<* SEQ */
101 COMP0_IRQn = 68, /*!<* COMP0 */
102 COMP1_IRQn = 69, /*!<* COMP1 */
103 COMP2_IRQn = 70, /*!<* COMP2 */
104 COMP3_IRQn = 71, /*!<* COMP3 */
105 VDAC_IRQn = 72, /*!<* VDAC */
106 DMA_TRIG0_IRQn = 81, /*!<* DMA_TRIG0 */
107 DMA_TRIG1_IRQn = 82, /*!<* DMA_TRIG1 */
108 DMA_SW0_IRQn = 83, /*!<* DMA_SW0 */
109 DMA_SW1_IRQn = 84, /*!<* DMA_SW1 */
110 CACHE_IRQn = 85, /*!<* CACHE */
111 DIG_COMP_IRQn = 86, /*!<* DIG_COMP */
112 GPIO_INTA_IRQn = 87, /*!<* GPIO_INTA */
113 GPIO_INTB_IRQn = 88, /*!<* GPIO_INTB */
114} IRQn_Type; /* typedef name for fixed interrupt numbers */
115
116
117/** @addtogroup Configuration_of_CMSIS
118 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
119 * @todo switch to M33 when port is done.
120 * @{
121 */
122#define __CM4_REV 0x0001U /*!< Core revision r0p1 */
123#define __MPU_PRESENT 1U /*!< ADUCM41X provides an MPU */
124#define __NVIC_PRIO_BITS 3U /*!< ADUCM41X uses 3 Bits for the Priority Levels */
125#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
126#define __FPU_PRESENT 1U /*!< FPU present */
127
128//#include <core_cm33.h> /*!< Cortex-M33 processor and core peripherals */
129#include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
130#include "system_ADuCM410.h" /*!< ADUCM410 System */
131/** @} */
132
133#ifdef __cplusplus
134extern "C" {
135#endif
136
137#ifndef TMR_ADDR_RDEF_H_
138#define TMR_ADDR_RDEF_H_ /* TMR: GPT0 */
139
140/* ====================================================================================================
141 TMR Module Instances Address and Mask Definitions
142 ==================================================================================================== */
143#define INST_GPT0 (0X40000000U) /* gpt0: */
144#define INST_GPT1 (0X40000400U) /* gpt1: */
145#define INST_GPT2 (0X40000800U) /* gpt2: */
146
147#define MASK_TMR (0XFFFFFFFFU) /* TMR: GPT0 */
148
149/* ====================================================================================================
150 TMR Module Register Address Offset Definitions
151 ==================================================================================================== */
152#define IDX_TMR_LD (0X00000000U) /* 16-bit Load Value Register */
153#define IDX_TMR_VAL (0X00000004U) /* 16-bit Timer Value Register */
154#define IDX_TMR_CON (0X00000008U) /* Control Register */
155#define IDX_TMR_CLRI (0X0000000CU) /* Clear Interrupt Register */
156#define IDX_TMR_STA (0X0000001CU) /* Status Register */
157
158/* ====================================================================================================
159 TMR Module Register ResetValue Definitions
160 ==================================================================================================== */
161#define RSTVAL_TMR_LD (0X0)
162#define RSTVAL_TMR_VAL (0X0)
163#define RSTVAL_TMR_CON (0XA)
164#define RSTVAL_TMR_CLRI (0X0)
165#define RSTVAL_TMR_STA (0X0)
166
167/* ====================================================================================================
168 TMR Module Register BitPositions, Lengths, Masks and Enumerations Definitions
169 ==================================================================================================== */
170
171/* ----------------------------------------------------------------------------------------------------
172 LD Value Description
173 ---------------------------------------------------------------------------------------------------- */
174#define BITP_TMR_LD_LOAD (0U) /* Load Value */
175#define BITL_TMR_LD_LOAD (16U) /* Load Value */
176#define BITM_TMR_LD_LOAD (0XFFFFU) /* Load Value */
177
178/* ----------------------------------------------------------------------------------------------------
179 VAL Value Description
180 ---------------------------------------------------------------------------------------------------- */
181#define BITP_TMR_VAL_COUNT_VAL (0U) /* Current Count */
182#define BITL_TMR_VAL_COUNT_VAL (16U) /* Current Count */
183#define BITM_TMR_VAL_COUNT_VAL (0XFFFFU) /* Current Count */
184
185/* ----------------------------------------------------------------------------------------------------
186 CON Value Description
187 ---------------------------------------------------------------------------------------------------- */
188#define BITP_TMR_CON_PRE (0U) /* Prescaler */
189#define BITL_TMR_CON_PRE (2U) /* Prescaler */
190#define BITM_TMR_CON_PRE (0X0003U) /* Prescaler */
191#define BITP_TMR_CON_UP (2U) /* Count up */
192#define BITL_TMR_CON_UP (1U) /* Count up */
193#define BITM_TMR_CON_UP (0X0004U) /* Count up */
194#define BITP_TMR_CON_MOD (3U) /* Timer Mode */
195#define BITL_TMR_CON_MOD (1U) /* Timer Mode */
196#define BITM_TMR_CON_MOD (0X0008U) /* Timer Mode */
197#define BITP_TMR_CON_ENABLE (4U) /* Timer Enable */
198#define BITL_TMR_CON_ENABLE (1U) /* Timer Enable */
199#define BITM_TMR_CON_ENABLE (0X0010U) /* Timer Enable */
200#define BITP_TMR_CON_CLK (5U) /* Clock Select */
201#define BITL_TMR_CON_CLK (2U) /* Clock Select */
202#define BITM_TMR_CON_CLK (0X0060U) /* Clock Select */
203#define BITP_TMR_CON_RLD (7U) /* Reload Control */
204#define BITL_TMR_CON_RLD (1U) /* Reload Control */
205#define BITM_TMR_CON_RLD (0X0080U) /* Reload Control */
206
207#define ENUM_TMR_CON_RLD_EN (0X0001U) /* Resets the Up/down Counter When GPTCLRI[0] is Set */
208#define ENUM_TMR_CON_RLD_DIS (0X0000U) /* Up/Down Counter is Only Reset on a Timeout Event */
209#define ENUM_TMR_CON_CLK_PCLK0 (0X0000U) /* PCLK. */
210#define ENUM_TMR_CON_CLK_HCLK (0X0001U) /* ROOT_CLK */
211#define ENUM_TMR_CON_CLK_LFOSC (0X0002U) /* LFOSC. 32 KHz OSC */
212#define ENUM_TMR_CON_CLK_HFXTAL (0X0003U) /* HFXTAL. 16 MHz OSC or XTAL (Dependent on CLKCON0.11) */
213#define ENUM_TMR_CON_ENABLE_DIS (0X0000U) /* DIS. Timer is Disabled (default) */
214#define ENUM_TMR_CON_ENABLE_EN (0X0001U) /* EN. Timer is Enabled */
215#define ENUM_TMR_CON_MOD_FREERUN (0X0000U) /* FREERUN.Timer Runs in Free Running Mode */
216#define ENUM_TMR_CON_MOD_PERIODIC (0X0001U) /* PERIODIC. Timer Runs in Periodic Mode (default) */
217#define ENUM_TMR_CON_UP_DIS (0X0000U) /* DIS. Timer is Set to Count Down (default) */
218#define ENUM_TMR_CON_UP_EN (0X0001U) /* EN. Timer is Set to Count up */
219#define ENUM_TMR_CON_PRE_DIV1OR4 (0X0000U) /* Source_clock / [1 or 4] */
220#define ENUM_TMR_CON_PRE_DIV16 (0X0001U) /* Source_clock / 16 */
221#define ENUM_TMR_CON_PRE_DIV256 (0X0002U) /* Source_clock / 256 */
222#define ENUM_TMR_CON_PRE_DIV32768 (0X0003U) /* Source_clock / 32,768 */
223
224/* ----------------------------------------------------------------------------------------------------
225 CLRI Value Description
226 ---------------------------------------------------------------------------------------------------- */
227#define BITP_TMR_CLRI_TMOUT (0U) /* Clear Timeout Interrupt */
228#define BITL_TMR_CLRI_TMOUT (1U) /* Clear Timeout Interrupt */
229#define BITM_TMR_CLRI_TMOUT (0X0001U) /* Clear Timeout Interrupt */
230
231/* ----------------------------------------------------------------------------------------------------
232 STA Value Description
233 ---------------------------------------------------------------------------------------------------- */
234#define BITP_TMR_STA_TMOUT (0U) /* Timeout Event Occurred */
235#define BITL_TMR_STA_TMOUT (1U) /* Timeout Event Occurred */
236#define BITM_TMR_STA_TMOUT (0X0001U) /* Timeout Event Occurred */
237#define BITP_TMR_STA_BUSY (6U) /* Timer Busy */
238#define BITL_TMR_STA_BUSY (1U) /* Timer Busy */
239#define BITM_TMR_STA_BUSY (0X0040U) /* Timer Busy */
240#define BITP_TMR_STA_PDOK (7U) /* GPTCLRI Synchronization */
241#define BITL_TMR_STA_PDOK (1U) /* GPTCLRI Synchronization */
242#define BITM_TMR_STA_PDOK (0X0080U) /* GPTCLRI Synchronization */
243
244#define ENUM_TMR_STA_PDOK_CLR_FLAG (0X0000U) /* CLR. the Interrupt is Cleared in the Timer Clock Domain */
245#define ENUM_TMR_STA_PDOK_SET_FLAG (0X0001U) /* SET. GPTCLRI[0] is Being Updated in the Timer Clock Domain */
246#define ENUM_TMR_STA_BUSY_CLR_FLAG (0X0000U) /* Timer Ready to Receive Commands to GPTCON */
247#define ENUM_TMR_STA_BUSY_SET_FLAG (0X0001U) /* Timer Not Ready to Receive Commands to GPTCON */
248#define ENUM_TMR_STA_TMOUT_CLR_FLAG (0X0000U) /* No Timeout Event Has Occurred */
249#define ENUM_TMR_STA_TMOUT_SET_FLAG (0X0001U) /* a Timeout Event Has Occurred */
250
251#endif /* end ifndef TMR_ADDR_RDEF_H_ */
252
253
254#ifndef TIMER_ADDR_RDEF_H_
255#define TIMER_ADDR_RDEF_H_ /* TIMER: Timer */
256
257/* ====================================================================================================
258 TIMER Module Instances Address and Mask Definitions
259 ==================================================================================================== */
260#define INST_GPTH0 (0X40000C00U) /* gpth0: */
261#define INST_GPTH1 (0X40001000U) /* gpth1: */
262
263#define MASK_TIMER (0X000000FFU) /* TIMER: Timer */
264
265/* ====================================================================================================
266 TIMER Module Register Address Offset Definitions
267 ==================================================================================================== */
268#define IDX_TIMER_CTL (0X00U) /* Timer Control */
269#define IDX_TIMER_CNT (0X04U) /* Count Value */
270#define IDX_TIMER_STATUS (0X08U) /* Timer Status */
271#define IDX_TIMER_CFG0 (0X10U) /* Capture Compare Configuration */
272#define IDX_TIMER_CFG1 (0X14U) /* Capture Compare Configuration */
273#define IDX_TIMER_CFG2 (0X18U) /* Capture Compare Configuration */
274#define IDX_TIMER_CFG3 (0X1CU) /* Capture Compare Configuration */
275#define IDX_TIMER_CC0 (0X20U) /* Compare and Capture Value */
276#define IDX_TIMER_CC1 (0X24U) /* Compare and Capture Value */
277#define IDX_TIMER_CC2 (0X28U) /* Compare and Capture Value */
278#define IDX_TIMER_CC3 (0X2CU) /* Compare and Capture Value */
279
280/* ====================================================================================================
281 TIMER Module Register ResetValue Definitions
282 ==================================================================================================== */
283#define RSTVAL_TIMER_CTL (0X170)
284#define RSTVAL_TIMER_CNT (0X0)
285#define RSTVAL_TIMER_STATUS (0X0)
286#define RSTVAL_TIMER_CFG0 (0X0)
287#define RSTVAL_TIMER_CFG1 (0X0)
288#define RSTVAL_TIMER_CFG2 (0X0)
289#define RSTVAL_TIMER_CFG3 (0X0)
290#define RSTVAL_TIMER_CC0 (0X0)
291#define RSTVAL_TIMER_CC1 (0X0)
292#define RSTVAL_TIMER_CC2 (0X0)
293#define RSTVAL_TIMER_CC3 (0X0)
294
295/* ====================================================================================================
296 TIMER Module Register BitPositions, Lengths, Masks and Enumerations Definitions
297 ==================================================================================================== */
298
299/* ----------------------------------------------------------------------------------------------------
300 CTL Value Description
301 ---------------------------------------------------------------------------------------------------- */
302#define BITP_TIMER_CTL_EN (0U) /* Timer Enable */
303#define BITL_TIMER_CTL_EN (1U) /* Timer Enable */
304#define BITM_TIMER_CTL_EN (0X00000001U) /* Timer Enable */
305#define BITP_TIMER_CTL_SEL (2U) /* Clock Source Select */
306#define BITL_TIMER_CTL_SEL (2U) /* Clock Source Select */
307#define BITM_TIMER_CTL_SEL (0X0000000CU) /* Clock Source Select */
308#define BITP_TIMER_CTL_PRE (4U) /* Timer Prescale */
309#define BITL_TIMER_CTL_PRE (5U) /* Timer Prescale */
310#define BITM_TIMER_CTL_PRE (0X000001F0U) /* Timer Prescale */
311
312#define ENUM_TIMER_CTL_SEL_PCLK (0X00000000U) /* PCLK */
313#define ENUM_TIMER_CTL_SEL_SYSCLK (0X00000001U) /* HCLK */
314#define ENUM_TIMER_CTL_SEL_LFOSC (0X00000002U) /* High Frequency Oscillator */
315#define ENUM_TIMER_CTL_SEL_HFXSTAL (0X00000003U) /* High Frequency XTALL */
316
317/* ----------------------------------------------------------------------------------------------------
318 CNT Value Description
319 ---------------------------------------------------------------------------------------------------- */
320#define BITP_TIMER_CNT_CNT (0U) /* Current Counter Value. */
321#define BITL_TIMER_CNT_CNT (32U) /* Current Counter Value. */
322#define BITM_TIMER_CNT_CNT (0XFFFFFFFFU) /* Current Counter Value. */
323
324/* ----------------------------------------------------------------------------------------------------
325 STATUS Value Description
326 ---------------------------------------------------------------------------------------------------- */
327#define BITP_TIMER_STATUS_CC0_STATUS (0U) /* CC0 Status */
328#define BITL_TIMER_STATUS_CC0_STATUS (1U) /* CC0 Status */
329#define BITM_TIMER_STATUS_CC0_STATUS (0X00000001U) /* CC0 Status */
330#define BITP_TIMER_STATUS_CC1_STATUS (1U) /* CC1 Status */
331#define BITL_TIMER_STATUS_CC1_STATUS (1U) /* CC1 Status */
332#define BITM_TIMER_STATUS_CC1_STATUS (0X00000002U) /* CC1 Status */
333#define BITP_TIMER_STATUS_CC2_STATUS (2U) /* CC2 Status */
334#define BITL_TIMER_STATUS_CC2_STATUS (1U) /* CC2 Status */
335#define BITM_TIMER_STATUS_CC2_STATUS (0X00000004U) /* CC2 Status */
336#define BITP_TIMER_STATUS_CC3_STATUS (3U) /* CC3 Status */
337#define BITL_TIMER_STATUS_CC3_STATUS (1U) /* CC3 Status */
338#define BITM_TIMER_STATUS_CC3_STATUS (0X00000008U) /* CC3 Status */
339
340/* ----------------------------------------------------------------------------------------------------
341 CFG0 Value Description
342 ---------------------------------------------------------------------------------------------------- */
343#define BITP_TIMER_CFG_N__MODE (0U) /* Capture or Compare Mode */
344#define BITL_TIMER_CFG_N__MODE (1U) /* Capture or Compare Mode */
345#define BITM_TIMER_CFG_N__MODE (0X00000001U) /* Capture or Compare Mode */
346#define BITP_TIMER_CFG_N__CC_EN (1U) /* Capture Compare Enabled */
347#define BITL_TIMER_CFG_N__CC_EN (1U) /* Capture Compare Enabled */
348#define BITM_TIMER_CFG_N__CC_EN (0X00000002U) /* Capture Compare Enabled */
349#define BITP_TIMER_CFG_N__EVENT_SEL (2U) /* Capture Events Select */
350#define BITL_TIMER_CFG_N__EVENT_SEL (4U) /* Capture Events Select */
351#define BITM_TIMER_CFG_N__EVENT_SEL (0X0000003CU) /* Capture Events Select */
352
353#define ENUM_TIMER_CFG_N__MODE_CMP (0X00000000U) /* Compare */
354#define ENUM_TIMER_CFG_N__MODE_CAP (0X00000001U) /* Capture */
355
356/* ----------------------------------------------------------------------------------------------------
357 CC0 Value Description
358 ---------------------------------------------------------------------------------------------------- */
359#define BITP_TIMER_CC_N__CC (0U) /* Capture or Compare Value */
360#define BITL_TIMER_CC_N__CC (32U) /* Capture or Compare Value */
361#define BITM_TIMER_CC_N__CC (0XFFFFFFFFU) /* Capture or Compare Value */
362
363#endif /* end ifndef TIMER_ADDR_RDEF_H_ */
364
365
366#ifndef MISC16_ADDR_RDEF_H_
367#define MISC16_ADDR_RDEF_H_ /* MISC16: Your module description, here. */
368
369/* ====================================================================================================
370 MISC16 Module Instances Address and Mask Definitions
371 ==================================================================================================== */
372#define INST_MISC (0X40002000U) /* misc: */
373
374#define MASK_MISC16 (0X00000FFFU) /* MISC16: Your module description, here. */
375
376/* ====================================================================================================
377 MISC16 Module Register Address Offset Definitions
378 ==================================================================================================== */
379#define IDX_MISC16_ADIID (0X020U) /* ADI ID */
380#define IDX_MISC16_CHIPID (0X024U) /* Chip ID */
381#define IDX_MISC16_USERKEY (0X134U) /* Open to Customer to Protect Important Registers */
382
383/* ====================================================================================================
384 MISC16 Module Register ResetValue Definitions
385 ==================================================================================================== */
386#define RSTVAL_MISC16_ADIID (0X4144)
387#define RSTVAL_MISC16_CHIPID (0X571)
388#define RSTVAL_MISC16_USERKEY (0X0)
389
390/* ====================================================================================================
391 MISC16 Module Register BitPositions, Lengths, Masks and Enumerations Definitions
392 ==================================================================================================== */
393
394/* ----------------------------------------------------------------------------------------------------
395 ADIID Value Description
396 ---------------------------------------------------------------------------------------------------- */
397#define BITP_MISC16_ADIID_ADIID (0U) /* ADI ID */
398#define BITL_MISC16_ADIID_ADIID (16U) /* ADI ID */
399#define BITM_MISC16_ADIID_ADIID (0X0000FFFFU) /* ADI ID */
400
401/* ----------------------------------------------------------------------------------------------------
402 CHIPID Value Description
403 ---------------------------------------------------------------------------------------------------- */
404#define BITP_MISC16_CHIPID_REVISION (0U) /* Silicon Revision Number */
405#define BITL_MISC16_CHIPID_REVISION (4U) /* Silicon Revision Number */
406#define BITM_MISC16_CHIPID_REVISION (0X0000000FU) /* Silicon Revision Number */
407#define BITP_MISC16_CHIPID_PARTID (4U) /* Part Identifier */
408#define BITL_MISC16_CHIPID_PARTID (12U) /* Part Identifier */
409#define BITM_MISC16_CHIPID_PARTID (0X0000FFF0U) /* Part Identifier */
410
411/* ----------------------------------------------------------------------------------------------------
412 USERKEY Value Description
413 ---------------------------------------------------------------------------------------------------- */
414#define BITP_MISC16_USERKEY_KEY (0U) /* User Key */
415#define BITL_MISC16_USERKEY_KEY (32U) /* User Key */
416#define BITM_MISC16_USERKEY_KEY (0XFFFFFFFFU) /* User Key */
417
418#endif /* end ifndef MISC16_ADDR_RDEF_H_ */
419
420
421#ifndef WUT_ADDR_RDEF_H_
422#define WUT_ADDR_RDEF_H_ /* WUT: WUT */
423
424/* ====================================================================================================
425 WUT Module Instances Address and Mask Definitions
426 ==================================================================================================== */
427#define INST_WUT (0X40003000U) /* wut: */
428
429#define MASK_WUT (0XFFFFFFFFU) /* WUT: WUT */
430
431/* ====================================================================================================
432 WUT Module Register Address Offset Definitions
433 ==================================================================================================== */
434#define IDX_WUT_T4VAL0 (0X00000000U) /* Current Count Value - LS 16 Bits */
435#define IDX_WUT_T4VAL1 (0X00000004U) /* Current Count Value - MS 16 Bits */
436#define IDX_WUT_T4CON (0X00000008U) /* Control Register */
437#define IDX_WUT_T4INC (0X0000000CU) /* 12-bit Interval for Wakeup Field a */
438#define IDX_WUT_T4WUFB0 (0X00000010U) /* Wakeup Field B - LS 16 Bits */
439#define IDX_WUT_T4WUFB1 (0X00000014U) /* Wakeup Field B - MS 16 Bits */
440#define IDX_WUT_T4WUFC0 (0X00000018U) /* Wakeup Field C - LS 16 Bits */
441#define IDX_WUT_T4WUFC1 (0X0000001CU) /* Wakeup Field C - MS 16 Bits */
442#define IDX_WUT_T4WUFD0 (0X00000020U) /* Wakeup Field D - LS 16 Bits */
443#define IDX_WUT_T4WUFD1 (0X00000024U) /* Wakeup Field D - MS 16 Bits */
444#define IDX_WUT_T4IEN (0X00000028U) /* Interrupt Enable Register */
445#define IDX_WUT_T4STA (0X0000002CU) /* Status Register */
446#define IDX_WUT_T4CLRI (0X00000030U) /* Clear Interrupt Register */
447#define IDX_WUT_T4WUFA0 (0X0000003CU) /* Wakeup Field a - LS 16 Bits */
448#define IDX_WUT_T4WUFA1 (0X00000040U) /* Wakeup Field a - MS 16 Bits */
449
450/* ====================================================================================================
451 WUT Module Register ResetValue Definitions
452 ==================================================================================================== */
453#define RSTVAL_WUT_T4VAL0 (0X0)
454#define RSTVAL_WUT_T4VAL1 (0X0)
455#define RSTVAL_WUT_T4CON (0X40)
456#define RSTVAL_WUT_T4INC (0XC8)
457#define RSTVAL_WUT_T4WUFB0 (0X1FFF)
458#define RSTVAL_WUT_T4WUFB1 (0X0)
459#define RSTVAL_WUT_T4WUFC0 (0X2FFF)
460#define RSTVAL_WUT_T4WUFC1 (0X0)
461#define RSTVAL_WUT_T4WUFD0 (0X3FFF)
462#define RSTVAL_WUT_T4WUFD1 (0X0)
463#define RSTVAL_WUT_T4IEN (0X0)
464#define RSTVAL_WUT_T4STA (0X0)
465#define RSTVAL_WUT_T4CLRI (0X0)
466#define RSTVAL_WUT_T4WUFA0 (0X1900)
467#define RSTVAL_WUT_T4WUFA1 (0X0)
468
469/* ====================================================================================================
470 WUT Module Register BitPositions, Lengths, Masks and Enumerations Definitions
471 ==================================================================================================== */
472
473/* ----------------------------------------------------------------------------------------------------
474 T4VAL0 Value Description
475 ---------------------------------------------------------------------------------------------------- */
476#define BITP_WUT_T4VAL0_T4VALL (0U) /* Current Count Low */
477#define BITL_WUT_T4VAL0_T4VALL (16U) /* Current Count Low */
478#define BITM_WUT_T4VAL0_T4VALL (0XFFFFU) /* Current Count Low */
479
480/* ----------------------------------------------------------------------------------------------------
481 T4VAL1 Value Description
482 ---------------------------------------------------------------------------------------------------- */
483#define BITP_WUT_T4VAL1_T4VALH (0U) /* Current Count High */
484#define BITL_WUT_T4VAL1_T4VALH (16U) /* Current Count High */
485#define BITM_WUT_T4VAL1_T4VALH (0XFFFFU) /* Current Count High */
486
487/* ----------------------------------------------------------------------------------------------------
488 T4CON Value Description
489 ---------------------------------------------------------------------------------------------------- */
490#define BITP_WUT_T4CON_PRE (0U) /* Prescaler */
491#define BITL_WUT_T4CON_PRE (2U) /* Prescaler */
492#define BITM_WUT_T4CON_PRE (0X0003U) /* Prescaler */
493#define BITP_WUT_T4CON_FREEZE (3U) /* Freeze Enable */
494#define BITL_WUT_T4CON_FREEZE (1U) /* Freeze Enable */
495#define BITM_WUT_T4CON_FREEZE (0X0008U) /* Freeze Enable */
496#define BITP_WUT_T4CON_TMODE (6U) /* Timer Mode */
497#define BITL_WUT_T4CON_TMODE (1U) /* Timer Mode */
498#define BITM_WUT_T4CON_TMODE (0X0040U) /* Timer Mode */
499#define BITP_WUT_T4CON_ENABLE (7U) /* Timer Enable */
500#define BITL_WUT_T4CON_ENABLE (1U) /* Timer Enable */
501#define BITM_WUT_T4CON_ENABLE (0X0080U) /* Timer Enable */
502#define BITP_WUT_T4CON_WUEN (8U) /* Wakeup Enable */
503#define BITL_WUT_T4CON_WUEN (1U) /* Wakeup Enable */
504#define BITM_WUT_T4CON_WUEN (0X0100U) /* Wakeup Enable */
505#define BITP_WUT_T4CON_CLK (9U) /* Clock Select */
506#define BITL_WUT_T4CON_CLK (2U) /* Clock Select */
507#define BITM_WUT_T4CON_CLK (0X0600U) /* Clock Select */
508#define BITP_WUT_T4CON_STOP_WUFA (11U) /* Disables Updating Field a Register T4WUFA */
509#define BITL_WUT_T4CON_STOP_WUFA (1U) /* Disables Updating Field a Register T4WUFA */
510#define BITM_WUT_T4CON_STOP_WUFA (0X0800U) /* Disables Updating Field a Register T4WUFA */
511
512#define ENUM_WUT_T4CON_CLK_PCLK (0X0000U) /* PCLK: PCLK (default) */
513#define ENUM_WUT_T4CON_CLK_LFOSC (0X0001U) /* LFOSC: 32 KHz Internal Oscillator */
514#define ENUM_WUT_T4CON_CLK_LFOSC1 (0X0002U) /* LFOSC: 32kHz Internal Oscillator */
515#define ENUM_WUT_T4CON_CLK_ECLKIN (0X0003U) /* ECLKIN: External Clock from P1.0 */
516#define ENUM_WUT_T4CON_WUEN_DIS (0X0000U) /* DIS: Cleared by User to Disable the Wake up Timer When the Core Clock is off */
517#define ENUM_WUT_T4CON_WUEN_EN (0X0001U) /* EN: Set by User to Enable the Wake up Timer Even When the Core Clock is Off. */
518#define ENUM_WUT_T4CON_ENABLE_DIS (0X0000U) /* DIS: Disable the Timer (default). */
519#define ENUM_WUT_T4CON_ENABLE_EN (0X0001U) /* EN: Enable the Timer. */
520#define ENUM_WUT_T4CON_TMODE_PERIODIC (0X0000U) /* PERIODIC: Cleared by User to Operate in Periodic Mode. in This Mode, the Timer Counts up to T4WUFD */
521#define ENUM_WUT_T4CON_TMODE_FREERUN (0X0001U) /* FREERUN: Set by User to Operate in Free Running Mode (default). */
522#define ENUM_WUT_T4CON_FREEZE_DIS (0X0000U) /* DIS: Cleared by User to Disable This Feature (default). */
523#define ENUM_WUT_T4CON_FREEZE_EN (0X0001U) /* EN: Set by User to Enable the Freeze of the High 16-bits After the Lower Bits Have Been Read from T4VAL0. This Ensures That the Software Will Read an Atomic Shot of the Timer. T4VAL1 Unfreezes After It Has Been Read. */
524#define ENUM_WUT_T4CON_PRE_PREDIV1 (0X0000U) /* PREDIV1: Source Clock/1 (default). If the Selected Clock Source is PCLK, Then This Setting Results in a Prescaler of 4. */
525#define ENUM_WUT_T4CON_PRE_PREDIV16 (0X0001U) /* PREDIV16: Source Clock/16 */
526#define ENUM_WUT_T4CON_PRE_PREDIV256 (0X0002U) /* PREDIV256: Source Clock/256 */
527#define ENUM_WUT_T4CON_PRE_PREDIV32768 (0X0003U) /* PREDIV32768: Source Clock/32,768 */
528
529/* ----------------------------------------------------------------------------------------------------
530 T4INC Value Description
531 ---------------------------------------------------------------------------------------------------- */
532#define BITP_WUT_T4INC_INTERVAL (0U) /* Interval for Wakeup Field a */
533#define BITL_WUT_T4INC_INTERVAL (12U) /* Interval for Wakeup Field a */
534#define BITM_WUT_T4INC_INTERVAL (0X0FFFU) /* Interval for Wakeup Field a */
535
536/* ----------------------------------------------------------------------------------------------------
537 T4WUFB0 Value Description
538 ---------------------------------------------------------------------------------------------------- */
539#define BITP_WUT_T4WUFB0_T4WUFBL (0U) /* Wakeup Field B Low */
540#define BITL_WUT_T4WUFB0_T4WUFBL (16U) /* Wakeup Field B Low */
541#define BITM_WUT_T4WUFB0_T4WUFBL (0XFFFFU) /* Wakeup Field B Low */
542
543/* ----------------------------------------------------------------------------------------------------
544 T4WUFB1 Value Description
545 ---------------------------------------------------------------------------------------------------- */
546#define BITP_WUT_T4WUFB1_T4WUFBH (0U) /* Wakeup Field B High */
547#define BITL_WUT_T4WUFB1_T4WUFBH (16U) /* Wakeup Field B High */
548#define BITM_WUT_T4WUFB1_T4WUFBH (0XFFFFU) /* Wakeup Field B High */
549
550/* ----------------------------------------------------------------------------------------------------
551 T4WUFC0 Value Description
552 ---------------------------------------------------------------------------------------------------- */
553#define BITP_WUT_T4WUFC0_T4WUFCL (0U) /* Wakeup Field C Low */
554#define BITL_WUT_T4WUFC0_T4WUFCL (16U) /* Wakeup Field C Low */
555#define BITM_WUT_T4WUFC0_T4WUFCL (0XFFFFU) /* Wakeup Field C Low */
556
557/* ----------------------------------------------------------------------------------------------------
558 T4WUFC1 Value Description
559 ---------------------------------------------------------------------------------------------------- */
560#define BITP_WUT_T4WUFC1_T4WUFCH (0U) /* Wakeup Field C High */
561#define BITL_WUT_T4WUFC1_T4WUFCH (16U) /* Wakeup Field C High */
562#define BITM_WUT_T4WUFC1_T4WUFCH (0XFFFFU) /* Wakeup Field C High */
563
564/* ----------------------------------------------------------------------------------------------------
565 T4WUFD0 Value Description
566 ---------------------------------------------------------------------------------------------------- */
567#define BITP_WUT_T4WUFD0_T4WUFD0 (0U) /* Wakeup Field D Low */
568#define BITL_WUT_T4WUFD0_T4WUFD0 (16U) /* Wakeup Field D Low */
569#define BITM_WUT_T4WUFD0_T4WUFD0 (0XFFFFU) /* Wakeup Field D Low */
570
571/* ----------------------------------------------------------------------------------------------------
572 T4WUFD1 Value Description
573 ---------------------------------------------------------------------------------------------------- */
574#define BITP_WUT_T4WUFD1_T4WUFDH (0U) /* Wakeup Field D High */
575#define BITL_WUT_T4WUFD1_T4WUFDH (16U) /* Wakeup Field D High */
576#define BITM_WUT_T4WUFD1_T4WUFDH (0XFFFFU) /* Wakeup Field D High */
577
578/* ----------------------------------------------------------------------------------------------------
579 T4IEN Value Description
580 ---------------------------------------------------------------------------------------------------- */
581#define BITP_WUT_T4IEN_WUFA (0U) /* T4WUFA Interrupt Enable */
582#define BITL_WUT_T4IEN_WUFA (1U) /* T4WUFA Interrupt Enable */
583#define BITM_WUT_T4IEN_WUFA (0X0001U) /* T4WUFA Interrupt Enable */
584#define BITP_WUT_T4IEN_WUFB (1U) /* T4WUFB Interrupt Enable */
585#define BITL_WUT_T4IEN_WUFB (1U) /* T4WUFB Interrupt Enable */
586#define BITM_WUT_T4IEN_WUFB (0X0002U) /* T4WUFB Interrupt Enable */
587#define BITP_WUT_T4IEN_WUFC (2U) /* T4WUFC Interrupt Enable */
588#define BITL_WUT_T4IEN_WUFC (1U) /* T4WUFC Interrupt Enable */
589#define BITM_WUT_T4IEN_WUFC (0X0004U) /* T4WUFC Interrupt Enable */
590#define BITP_WUT_T4IEN_WUFD (3U) /* T4WUFD Interrupt Enable */
591#define BITL_WUT_T4IEN_WUFD (1U) /* T4WUFD Interrupt Enable */
592#define BITM_WUT_T4IEN_WUFD (0X0008U) /* T4WUFD Interrupt Enable */
593#define BITP_WUT_T4IEN_ROLL (4U) /* Rollover Interrupt Enable */
594#define BITL_WUT_T4IEN_ROLL (1U) /* Rollover Interrupt Enable */
595#define BITM_WUT_T4IEN_ROLL (0X0010U) /* Rollover Interrupt Enable */
596
597/* ----------------------------------------------------------------------------------------------------
598 T4STA Value Description
599 ---------------------------------------------------------------------------------------------------- */
600#define BITP_WUT_T4STA_WUFA (0U) /* T4WUFA Interrupt Flag */
601#define BITL_WUT_T4STA_WUFA (1U) /* T4WUFA Interrupt Flag */
602#define BITM_WUT_T4STA_WUFA (0X0001U) /* T4WUFA Interrupt Flag */
603#define BITP_WUT_T4STA_WUFB (1U) /* T4WUFB Interrupt Flag */
604#define BITL_WUT_T4STA_WUFB (1U) /* T4WUFB Interrupt Flag */
605#define BITM_WUT_T4STA_WUFB (0X0002U) /* T4WUFB Interrupt Flag */
606#define BITP_WUT_T4STA_WUFC (2U) /* T4WUFC Interrupt Flag */
607#define BITL_WUT_T4STA_WUFC (1U) /* T4WUFC Interrupt Flag */
608#define BITM_WUT_T4STA_WUFC (0X0004U) /* T4WUFC Interrupt Flag */
609#define BITP_WUT_T4STA_WUFD (3U) /* T4WUFD Interrupt Flag */
610#define BITL_WUT_T4STA_WUFD (1U) /* T4WUFD Interrupt Flag */
611#define BITM_WUT_T4STA_WUFD (0X0008U) /* T4WUFD Interrupt Flag */
612#define BITP_WUT_T4STA_ROLL (4U) /* Rollover Interrupt Flag */
613#define BITL_WUT_T4STA_ROLL (1U) /* Rollover Interrupt Flag */
614#define BITM_WUT_T4STA_ROLL (0X0010U) /* Rollover Interrupt Flag */
615#define BITP_WUT_T4STA_IRQCRY (6U) /* Wakeup Status to Powerdown */
616#define BITL_WUT_T4STA_IRQCRY (1U) /* Wakeup Status to Powerdown */
617#define BITM_WUT_T4STA_IRQCRY (0X0040U) /* Wakeup Status to Powerdown */
618#define BITP_WUT_T4STA_FREEZE (7U) /* Timer Value Freeze */
619#define BITL_WUT_T4STA_FREEZE (1U) /* Timer Value Freeze */
620#define BITM_WUT_T4STA_FREEZE (0X0080U) /* Timer Value Freeze */
621#define BITP_WUT_T4STA_PDOK (8U) /* Enable Bit Synchronized */
622#define BITL_WUT_T4STA_PDOK (1U) /* Enable Bit Synchronized */
623#define BITM_WUT_T4STA_PDOK (0X0100U) /* Enable Bit Synchronized */
624
625/* ----------------------------------------------------------------------------------------------------
626 T4CLRI Value Description
627 ---------------------------------------------------------------------------------------------------- */
628#define BITP_WUT_T4CLRI_WUFA (0U) /* T4WUFA Interrupt Clear */
629#define BITL_WUT_T4CLRI_WUFA (1U) /* T4WUFA Interrupt Clear */
630#define BITM_WUT_T4CLRI_WUFA (0X0001U) /* T4WUFA Interrupt Clear */
631#define BITP_WUT_T4CLRI_WUFB (1U) /* T4WUFB Interrupt Clear */
632#define BITL_WUT_T4CLRI_WUFB (1U) /* T4WUFB Interrupt Clear */
633#define BITM_WUT_T4CLRI_WUFB (0X0002U) /* T4WUFB Interrupt Clear */
634#define BITP_WUT_T4CLRI_WUFC (2U) /* T4WUFC Interrupt Clear */
635#define BITL_WUT_T4CLRI_WUFC (1U) /* T4WUFC Interrupt Clear */
636#define BITM_WUT_T4CLRI_WUFC (0X0004U) /* T4WUFC Interrupt Clear */
637#define BITP_WUT_T4CLRI_WUFD (3U) /* T4WUFD Interrupt Clear */
638#define BITL_WUT_T4CLRI_WUFD (1U) /* T4WUFD Interrupt Clear */
639#define BITM_WUT_T4CLRI_WUFD (0X0008U) /* T4WUFD Interrupt Clear */
640#define BITP_WUT_T4CLRI_ROLL (4U) /* Rollover Interrupt Clear */
641#define BITL_WUT_T4CLRI_ROLL (1U) /* Rollover Interrupt Clear */
642#define BITM_WUT_T4CLRI_ROLL (0X0010U) /* Rollover Interrupt Clear */
643
644/* ----------------------------------------------------------------------------------------------------
645 T4WUFA0 Value Description
646 ---------------------------------------------------------------------------------------------------- */
647#define BITP_WUT_T4WUFA0_T4WUFAL (0U) /* Wakeup Field a Low */
648#define BITL_WUT_T4WUFA0_T4WUFAL (16U) /* Wakeup Field a Low */
649#define BITM_WUT_T4WUFA0_T4WUFAL (0XFFFFU) /* Wakeup Field a Low */
650
651/* ----------------------------------------------------------------------------------------------------
652 T4WUFA1 Value Description
653 ---------------------------------------------------------------------------------------------------- */
654#define BITP_WUT_T4WUFA1_T4WUFAH (0U) /* Wakeup Field a High */
655#define BITL_WUT_T4WUFA1_T4WUFAH (16U) /* Wakeup Field a High */
656#define BITM_WUT_T4WUFA1_T4WUFAH (0XFFFFU) /* Wakeup Field a High */
657
658#endif /* end ifndef WUT_ADDR_RDEF_H_ */
659
660
661#ifndef WDT_ADDR_RDEF_H_
662#define WDT_ADDR_RDEF_H_ /* WDT: Watchdog Timer Register Map */
663
664/* ====================================================================================================
665 WDT Module Instances Address and Mask Definitions
666 ==================================================================================================== */
667#define INST_WDT (0X40004000U) /* wdt: */
668
669#define MASK_WDT (0X000000FFU) /* WDT: Watchdog Timer Register Map */
670
671/* ====================================================================================================
672 WDT Module Register Address Offset Definitions
673 ==================================================================================================== */
674#define IDX_WDT_LD (0X00U) /* Watchdog Timer Load Value */
675#define IDX_WDT_VALS (0X04U) /* Current Count Value */
676#define IDX_WDT_CON (0X08U) /* Watchdog Timer Control Register */
677#define IDX_WDT_CLRI (0X0CU) /* Refresh Watchdog Register */
678#define IDX_WDT_STA (0X18U) /* Timer Status */
679#define IDX_WDT_MINLD (0X1CU) /* Minimum Load Value */
680
681/* ====================================================================================================
682 WDT Module Register ResetValue Definitions
683 ==================================================================================================== */
684#define RSTVAL_WDT_LD (0X1000)
685#define RSTVAL_WDT_VALS (0X1000)
686#define RSTVAL_WDT_CON (0X69)
687#define RSTVAL_WDT_CLRI (0X0)
688#define RSTVAL_WDT_STA (0X0)
689#define RSTVAL_WDT_MINLD (0X800)
690
691/* ====================================================================================================
692 WDT Module Register BitPositions, Lengths, Masks and Enumerations Definitions
693 ==================================================================================================== */
694
695/* ----------------------------------------------------------------------------------------------------
696 LD Value Description
697 ---------------------------------------------------------------------------------------------------- */
698#define BITP_WDT_LD_LOAD (0U) /* WDT Load Value */
699#define BITL_WDT_LD_LOAD (16U) /* WDT Load Value */
700#define BITM_WDT_LD_LOAD (0XFFFFU) /* WDT Load Value */
701
702/* ----------------------------------------------------------------------------------------------------
703 VALS Value Description
704 ---------------------------------------------------------------------------------------------------- */
705#define BITP_WDT_VALS_CCOUNT (0U) /* Current WDT Count Value. */
706#define BITL_WDT_VALS_CCOUNT (16U) /* Current WDT Count Value. */
707#define BITM_WDT_VALS_CCOUNT (0XFFFFU) /* Current WDT Count Value. */
708
709/* ----------------------------------------------------------------------------------------------------
710 CON Value Description
711 ---------------------------------------------------------------------------------------------------- */
712#define BITP_WDT_CON_PDSTOP (0U) /* Power Down Stop Enable */
713#define BITL_WDT_CON_PDSTOP (1U) /* Power Down Stop Enable */
714#define BITM_WDT_CON_PDSTOP (0X0001U) /* Power Down Stop Enable */
715#define BITP_WDT_CON_IRQ (1U) /* WDT Interrupt Enable */
716#define BITL_WDT_CON_IRQ (1U) /* WDT Interrupt Enable */
717#define BITM_WDT_CON_IRQ (0X0002U) /* WDT Interrupt Enable */
718#define BITP_WDT_CON_PRE (2U) /* Prescaler. */
719#define BITL_WDT_CON_PRE (2U) /* Prescaler. */
720#define BITM_WDT_CON_PRE (0X000CU) /* Prescaler. */
721#define BITP_WDT_CON_EN (5U) /* Timer Enable */
722#define BITL_WDT_CON_EN (1U) /* Timer Enable */
723#define BITM_WDT_CON_EN (0X0020U) /* Timer Enable */
724#define BITP_WDT_CON_MDE (6U) /* Timer Mode Select */
725#define BITL_WDT_CON_MDE (1U) /* Timer Mode Select */
726#define BITM_WDT_CON_MDE (0X0040U) /* Timer Mode Select */
727#define BITP_WDT_CON_CLKDIV2 (8U) /* Clock Source */
728#define BITL_WDT_CON_CLKDIV2 (1U) /* Clock Source */
729#define BITM_WDT_CON_CLKDIV2 (0X0100U) /* Clock Source */
730#define BITP_WDT_CON_MINLOADEN (9U) /* Timer Window Control */
731#define BITL_WDT_CON_MINLOADEN (1U) /* Timer Window Control */
732#define BITM_WDT_CON_MINLOADEN (0X0200U) /* Timer Window Control */
733#define BITP_WDT_CON_WDTIRQEN (10U) /* WDT Interrupt Enable */
734#define BITL_WDT_CON_WDTIRQEN (1U) /* WDT Interrupt Enable */
735#define BITM_WDT_CON_WDTIRQEN (0X0400U) /* WDT Interrupt Enable */
736
737#define ENUM_WDT_CON_MDE_FREE (0X0000U) /* Free-running Mode */
738#define ENUM_WDT_CON_MDE_PERIODIC (0X0001U) /* Periodic Mode (default) */
739#define ENUM_WDT_CON_PRE_DIV1 (0X0000U) /* Source Clock/1 */
740#define ENUM_WDT_CON_PRE_DIV16 (0X0001U) /* Source Clock/16. */
741#define ENUM_WDT_CON_PRE_DIV256 (0X0002U) /* Source Clock/256 (default). */
742#define ENUM_WDT_CON_PRE_DIV4096 (0X0003U) /* Source Clock/4096 */
743#define ENUM_WDT_CON_IRQ_RESET (0X0000U) /* Watchdog Timer Timeout Creates a Reset. */
744#define ENUM_WDT_CON_IRQ_INTERRUPT (0X0001U) /* Watchdog Timer Timeout Creates an Interrupt Instead of Reset. */
745#define ENUM_WDT_CON_PDSTOP_CONTINUE (0X0000U) /* Continue Counting When in Hibernate */
746#define ENUM_WDT_CON_PDSTOP_STOPED (0X0001U) /* Stop Counter When in Hibernate. */
747
748/* ----------------------------------------------------------------------------------------------------
749 CLRI Value Description
750 ---------------------------------------------------------------------------------------------------- */
751#define BITP_WDT_CLRI_CLRWDG (0U) /* Refresh Register */
752#define BITL_WDT_CLRI_CLRWDG (16U) /* Refresh Register */
753#define BITM_WDT_CLRI_CLRWDG (0XFFFFU) /* Refresh Register */
754
755/* ----------------------------------------------------------------------------------------------------
756 STA Value Description
757 ---------------------------------------------------------------------------------------------------- */
758#define BITP_WDT_STA_IRQ (0U) /* WDT Interrupt */
759#define BITL_WDT_STA_IRQ (1U) /* WDT Interrupt */
760#define BITM_WDT_STA_IRQ (0X0001U) /* WDT Interrupt */
761#define BITP_WDT_STA_CLRI (1U) /* WDTCLRI Write Status */
762#define BITL_WDT_STA_CLRI (1U) /* WDTCLRI Write Status */
763#define BITM_WDT_STA_CLRI (0X0002U) /* WDTCLRI Write Status */
764#define BITP_WDT_STA_TLD (2U) /* WDTVAL Write Status */
765#define BITL_WDT_STA_TLD (1U) /* WDTVAL Write Status */
766#define BITM_WDT_STA_TLD (0X0004U) /* WDTVAL Write Status */
767#define BITP_WDT_STA_CON (3U) /* WDTCON Write Status */
768#define BITL_WDT_STA_CON (1U) /* WDTCON Write Status */
769#define BITM_WDT_STA_CON (0X0008U) /* WDTCON Write Status */
770#define BITP_WDT_STA_LOCKS (4U) /* Lock Status */
771#define BITL_WDT_STA_LOCKS (1U) /* Lock Status */
772#define BITM_WDT_STA_LOCKS (0X0010U) /* Lock Status */
773#define BITP_WDT_STA_OTPWRDONE (5U) /* Reset Type Status */
774#define BITL_WDT_STA_OTPWRDONE (1U) /* Reset Type Status */
775#define BITM_WDT_STA_OTPWRDONE (0X0020U) /* Reset Type Status */
776#define BITP_WDT_STA_TMINLD (6U) /* WDTMINLD Write Status */
777#define BITL_WDT_STA_TMINLD (1U) /* WDTMINLD Write Status */
778#define BITM_WDT_STA_TMINLD (0X0040U) /* WDTMINLD Write Status */
779
780#define ENUM_WDT_STA_LOCKS_OPENED (0X0000U) /* Timer Operation Not Locked */
781#define ENUM_WDT_STA_LOCKS_LOCKED (0X0001U) /* Timer Enabled and Locked */
782#define ENUM_WDT_STA_IRQ_CLEARED (0X0000U) /* Watchdog Timer Interrupt Not Pending */
783#define ENUM_WDT_STA_IRQ_PENDING (0X0001U) /* Watchdog Timer Interrupt Pending */
784
785/* ----------------------------------------------------------------------------------------------------
786 MINLD Value Description
787 ---------------------------------------------------------------------------------------------------- */
788#define BITP_WDT_MINLD_MINLOAD (0U) /* WDT Min Load Value */
789#define BITL_WDT_MINLD_MINLOAD (16U) /* WDT Min Load Value */
790#define BITM_WDT_MINLD_MINLOAD (0XFFFFU) /* WDT Min Load Value */
791
792#endif /* end ifndef WDT_ADDR_RDEF_H_ */
793
794
795#ifndef ALWAYS_ON_ADDR_RDEF_H_
796#define ALWAYS_ON_ADDR_RDEF_H_ /* ALWAYS_ON: Always on clock, reset, power management and test */
797
798/* ====================================================================================================
799 ALWAYS_ON Module Instances Address and Mask Definitions
800 ==================================================================================================== */
801#define INST_ALLON (0X40005000U) /* allon: */
802
803#define MASK_ALWAYS_ON (0XFFFFFFFFU) /* ALWAYS_ON: Always on clock, reset, power management and test */
804
805/* ====================================================================================================
806 ALWAYS_ON Module Register Address Offset Definitions
807 ==================================================================================================== */
808#define IDX_ALWAYS_ON_PWRMOD (0X00000000U) /* Power Modes */
809#define IDX_ALWAYS_ON_PWRKEY (0X00000004U) /* Key Protection for PWRMOD */
810#define IDX_ALWAYS_ON_RSTCFG (0X00000008U) /* Reset Configuration */
811#define IDX_ALWAYS_ON_RSTKEY (0X0000000CU) /* Key Protection for RSTCFG */
812#define IDX_ALWAYS_ON_EI0CFG (0X00000020U) /* External Interrupt Configuration 0 */
813#define IDX_ALWAYS_ON_EI1CFG (0X00000024U) /* External Interrupt Configuration 1 */
814#define IDX_ALWAYS_ON_EI2CFG (0X00000028U) /* External Interrupt Configuration 2 */
815#define IDX_ALWAYS_ON_EICLR (0X00000030U) /* External Interrupt Clear */
816#define IDX_ALWAYS_ON_RSTSTA (0X00000040U) /* Reset Status */
817
818/* ====================================================================================================
819 ALWAYS_ON Module Register ResetValue Definitions
820 ==================================================================================================== */
821#define RSTVAL_ALWAYS_ON_PWRMOD (0X0)
822#define RSTVAL_ALWAYS_ON_PWRKEY (0X0)
823#define RSTVAL_ALWAYS_ON_RSTCFG (0X0)
824#define RSTVAL_ALWAYS_ON_RSTKEY (0X0)
825#define RSTVAL_ALWAYS_ON_EI0CFG (0X0)
826#define RSTVAL_ALWAYS_ON_EI1CFG (0X0)
827#define RSTVAL_ALWAYS_ON_EI2CFG (0X0)
828#define RSTVAL_ALWAYS_ON_EICLR (0X0)
829#define RSTVAL_ALWAYS_ON_RSTSTA (0X0)
830
831/* ====================================================================================================
832 ALWAYS_ON Module Register BitPositions, Lengths, Masks and Enumerations Definitions
833 ==================================================================================================== */
834
835/* ----------------------------------------------------------------------------------------------------
836 PWRMOD Value Description
837 ---------------------------------------------------------------------------------------------------- */
838#define BITP_ALWAYS_ON_PWRMOD_PWRMOD (0U) /* Power Modes Control Bits */
839#define BITL_ALWAYS_ON_PWRMOD_PWRMOD (2U) /* Power Modes Control Bits */
840#define BITM_ALWAYS_ON_PWRMOD_PWRMOD (0X0003U) /* Power Modes Control Bits */
841#define BITP_ALWAYS_ON_PWRMOD_WICENACK (3U) /* WIC Acknowledgment for SLEEPDEEP */
842#define BITL_ALWAYS_ON_PWRMOD_WICENACK (1U) /* WIC Acknowledgment for SLEEPDEEP */
843#define BITM_ALWAYS_ON_PWRMOD_WICENACK (0X0008U) /* WIC Acknowledgment for SLEEPDEEP */
844
845#define ENUM_ALWAYS_ON_PWRMOD_WICENACK_NOACK (0X0000U) /* No description provided */
846#define ENUM_ALWAYS_ON_PWRMOD_WICENACK_ACK (0X0001U) /* No description provided */
847#define ENUM_ALWAYS_ON_PWRMOD_PWRMOD_FULLACTIVE (0X0000U) /* Active Mode */
848#define ENUM_ALWAYS_ON_PWRMOD_PWRMOD_CORESLEEP (0X0001U) /* CORE_SLEEP Mode */
849#define ENUM_ALWAYS_ON_PWRMOD_PWRMOD_SYSSLEEP (0X0002U) /* SYS_SLEEP Mode */
850#define ENUM_ALWAYS_ON_PWRMOD_PWRMOD_HIBERNATE (0X0003U) /* Hibernate Mode */
851
852/* ----------------------------------------------------------------------------------------------------
853 PWRKEY Value Description
854 ---------------------------------------------------------------------------------------------------- */
855#define BITP_ALWAYS_ON_PWRKEY_PWRKEY (0U) /* Power Control Key Register */
856#define BITL_ALWAYS_ON_PWRKEY_PWRKEY (16U) /* Power Control Key Register */
857#define BITM_ALWAYS_ON_PWRKEY_PWRKEY (0XFFFFU) /* Power Control Key Register */
858
859/* ----------------------------------------------------------------------------------------------------
860 RSTCFG Value Description
861 ---------------------------------------------------------------------------------------------------- */
862#define BITP_ALWAYS_ON_RSTCFG_GPIO_PLA_RETAIN (0U) /* GPIO/PLA Retain Their Status After WDT and Software Reset */
863#define BITL_ALWAYS_ON_RSTCFG_GPIO_PLA_RETAIN (1U) /* GPIO/PLA Retain Their Status After WDT and Software Reset */
864#define BITM_ALWAYS_ON_RSTCFG_GPIO_PLA_RETAIN (0X0001U) /* GPIO/PLA Retain Their Status After WDT and Software Reset */
865#define BITP_ALWAYS_ON_RSTCFG_LV_RETAIN (2U) /* LV Die Retain Status After Watchdog or Software Reset */
866#define BITL_ALWAYS_ON_RSTCFG_LV_RETAIN (1U) /* LV Die Retain Status After Watchdog or Software Reset */
867#define BITM_ALWAYS_ON_RSTCFG_LV_RETAIN (0X0004U) /* LV Die Retain Status After Watchdog or Software Reset */
868#define BITP_ALWAYS_ON_RSTCFG_ANA_RETAIN (3U) /* Analog Block Retain Status After Watchdog or Software Reset */
869#define BITL_ALWAYS_ON_RSTCFG_ANA_RETAIN (1U) /* Analog Block Retain Status After Watchdog or Software Reset */
870#define BITM_ALWAYS_ON_RSTCFG_ANA_RETAIN (0X0008U) /* Analog Block Retain Status After Watchdog or Software Reset */
871
872#define ENUM_ALWAYS_ON_RSTCFG_ANA_RETAIN_DIS (0X0000U) /* GPIO/PLA Retain Status After Watchdog or Software Reset. */
873#define ENUM_ALWAYS_ON_RSTCFG_ANA_RETAIN_EN (0X0001U) /* GPIO/PLA not Retain Status After Watchdog or Software Reset */
874#define ENUM_ALWAYS_ON_RSTCFG_LV_RETAIN_DIS (0X0000U) /* LV Die Retain Status After Watchdog or Software Reset. */
875#define ENUM_ALWAYS_ON_RSTCFG_LV_RETAIN_EN (0X0001U) /* LV Die not Retain Status After Watchdog or Software Reset */
876#define ENUM_ALWAYS_ON_RSTCFG_GPIO_PLA_RETAIN_DIS (0X0000U) /* GPIO/PLA Retain Status After Watchdog or Software Reset. */
877#define ENUM_ALWAYS_ON_RSTCFG_GPIO_PLA_RETAIN_EN (0X0001U) /* GPIO/PLA not Retain Status After Watchdog or Software Reset */
878
879/* ----------------------------------------------------------------------------------------------------
880 RSTKEY Value Description
881 ---------------------------------------------------------------------------------------------------- */
882#define BITP_ALWAYS_ON_RSTKEY_RSTKEY (0U) /* Reset Configuration Key Register */
883#define BITL_ALWAYS_ON_RSTKEY_RSTKEY (16U) /* Reset Configuration Key Register */
884#define BITM_ALWAYS_ON_RSTKEY_RSTKEY (0XFFFFU) /* Reset Configuration Key Register */
885
886#define ENUM_ALWAYS_ON_RSTKEY_RSTKEY_RSTKEY1 (0X2009U) /* First Key to Write Reset Configuration */
887#define ENUM_ALWAYS_ON_RSTKEY_RSTKEY_RSTKEY2 (0X0426U) /* Second Key to Write Reset Configuration */
888
889/* ----------------------------------------------------------------------------------------------------
890 EI0CFG Value Description
891 ---------------------------------------------------------------------------------------------------- */
892#define BITP_ALWAYS_ON_EI0CFG_IRQ0MDE (0U) /* External Interrupt 0 Mode Registers */
893#define BITL_ALWAYS_ON_EI0CFG_IRQ0MDE (3U) /* External Interrupt 0 Mode Registers */
894#define BITM_ALWAYS_ON_EI0CFG_IRQ0MDE (0X0007U) /* External Interrupt 0 Mode Registers */
895#define BITP_ALWAYS_ON_EI0CFG_IRQ0EN (3U) /* External Interrupt 0 Enable Bit */
896#define BITL_ALWAYS_ON_EI0CFG_IRQ0EN (1U) /* External Interrupt 0 Enable Bit */
897#define BITM_ALWAYS_ON_EI0CFG_IRQ0EN (0X0008U) /* External Interrupt 0 Enable Bit */
898#define BITP_ALWAYS_ON_EI0CFG_IRQ1MDE (4U) /* External Interrupt 1 Mode Registers */
899#define BITL_ALWAYS_ON_EI0CFG_IRQ1MDE (3U) /* External Interrupt 1 Mode Registers */
900#define BITM_ALWAYS_ON_EI0CFG_IRQ1MDE (0X0070U) /* External Interrupt 1 Mode Registers */
901#define BITP_ALWAYS_ON_EI0CFG_IRQ1EN (7U) /* External Interrupt 1 Enable Bit */
902#define BITL_ALWAYS_ON_EI0CFG_IRQ1EN (1U) /* External Interrupt 1 Enable Bit */
903#define BITM_ALWAYS_ON_EI0CFG_IRQ1EN (0X0080U) /* External Interrupt 1 Enable Bit */
904#define BITP_ALWAYS_ON_EI0CFG_IRQ2MDE (8U) /* External Interrupt 2 Mode Registers */
905#define BITL_ALWAYS_ON_EI0CFG_IRQ2MDE (3U) /* External Interrupt 2 Mode Registers */
906#define BITM_ALWAYS_ON_EI0CFG_IRQ2MDE (0X0700U) /* External Interrupt 2 Mode Registers */
907#define BITP_ALWAYS_ON_EI0CFG_IRQ2EN (11U) /* External Interrupt 2 Enable Bit */
908#define BITL_ALWAYS_ON_EI0CFG_IRQ2EN (1U) /* External Interrupt 2 Enable Bit */
909#define BITM_ALWAYS_ON_EI0CFG_IRQ2EN (0X0800U) /* External Interrupt 2 Enable Bit */
910#define BITP_ALWAYS_ON_EI0CFG_IRQ3MDE (12U) /* External Interrupt 3 Mode Registers */
911#define BITL_ALWAYS_ON_EI0CFG_IRQ3MDE (3U) /* External Interrupt 3 Mode Registers */
912#define BITM_ALWAYS_ON_EI0CFG_IRQ3MDE (0X7000U) /* External Interrupt 3 Mode Registers */
913#define BITP_ALWAYS_ON_EI0CFG_IRQ3EN (15U) /* External Interrupt 3 Enable Bit */
914#define BITL_ALWAYS_ON_EI0CFG_IRQ3EN (1U) /* External Interrupt 3 Enable Bit */
915#define BITM_ALWAYS_ON_EI0CFG_IRQ3EN (0X8000U) /* External Interrupt 3 Enable Bit */
916
917#define ENUM_ALWAYS_ON_EI0CFG_IRQ3EN_DIS (0X0000U) /* External Interrupt 3 Disabled */
918#define ENUM_ALWAYS_ON_EI0CFG_IRQ3EN_EN (0X0001U) /* External Interrupt 3 Enabled */
919#define ENUM_ALWAYS_ON_EI0CFG_IRQ3MDE_RISE (0X0000U) /* Rising Edge */
920#define ENUM_ALWAYS_ON_EI0CFG_IRQ3MDE_FALL (0X0001U) /* Falling Edge */
921#define ENUM_ALWAYS_ON_EI0CFG_IRQ3MDE_RISEORFALL (0X0002U) /* Rising or Falling Edge */
922#define ENUM_ALWAYS_ON_EI0CFG_IRQ3MDE_HIGHLEVEL (0X0003U) /* High Level */
923#define ENUM_ALWAYS_ON_EI0CFG_IRQ3MDE_LOWLEVEL (0X0004U) /* Low Level */
924#define ENUM_ALWAYS_ON_EI0CFG_IRQ3MDE_FALLAUX (0X0005U) /* Falling Edge (same as 001) */
925#define ENUM_ALWAYS_ON_EI0CFG_IRQ3MDE_RISEORFALLAUX (0X0006U) /* Rising or Falling Edge (same as 010) */
926#define ENUM_ALWAYS_ON_EI0CFG_IRQ3MDE_HIGHLEVELAUX (0X0007U) /* High Level (same as 011) */
927#define ENUM_ALWAYS_ON_EI0CFG_IRQ2EN_DIS (0X0000U) /* External Interrupt 2 Disabled */
928#define ENUM_ALWAYS_ON_EI0CFG_IRQ2EN_EN (0X0001U) /* External Interrupt 2 Enabled */
929#define ENUM_ALWAYS_ON_EI0CFG_IRQ2MDE_RISE (0X0000U) /* Rising Edge */
930#define ENUM_ALWAYS_ON_EI0CFG_IRQ2MDE_FALL (0X0001U) /* Falling Edge */
931#define ENUM_ALWAYS_ON_EI0CFG_IRQ2MDE_RISEORFALL (0X0002U) /* Rising or Falling Edge */
932#define ENUM_ALWAYS_ON_EI0CFG_IRQ2MDE_HIGHLEVEL (0X0003U) /* High Level */
933#define ENUM_ALWAYS_ON_EI0CFG_IRQ2MDE_LOWLEVEL (0X0004U) /* Low Level */
934#define ENUM_ALWAYS_ON_EI0CFG_IRQ2MDE_FALLAUX (0X0005U) /* Falling Edge (same as 001) */
935#define ENUM_ALWAYS_ON_EI0CFG_IRQ2MDE_RISEORFALLAUX (0X0006U) /* Rising or Falling Edge (same as 010) */
936#define ENUM_ALWAYS_ON_EI0CFG_IRQ2MDE_HIGHLEVELAUX (0X0007U) /* High Level (same as 011) */
937#define ENUM_ALWAYS_ON_EI0CFG_IRQ1EN_DIS (0X0000U) /* External Interrupt 0 Disabled */
938#define ENUM_ALWAYS_ON_EI0CFG_IRQ1EN_EN (0X0001U) /* External Interrupt 0 Enabled */
939#define ENUM_ALWAYS_ON_EI0CFG_IRQ1MDE_RISE (0X0000U) /* Rising Edge */
940#define ENUM_ALWAYS_ON_EI0CFG_IRQ1MDE_FALL (0X0001U) /* Falling Edge */
941#define ENUM_ALWAYS_ON_EI0CFG_IRQ1MDE_RISEORFALL (0X0002U) /* Rising or Falling Edge */
942#define ENUM_ALWAYS_ON_EI0CFG_IRQ1MDE_HIGHLEVEL (0X0003U) /* High Level */
943#define ENUM_ALWAYS_ON_EI0CFG_IRQ1MDE_LOWLEVEL (0X0004U) /* Low Level */
944#define ENUM_ALWAYS_ON_EI0CFG_IRQ1MDE_FALLAUX (0X0005U) /* Falling Edge (same as 001) */
945#define ENUM_ALWAYS_ON_EI0CFG_IRQ1MDE_RISEORFALLAUX (0X0006U) /* Rising or Falling Edge (same as 010) */
946#define ENUM_ALWAYS_ON_EI0CFG_IRQ1MDE_HIGHLEVELAUX (0X0007U) /* High Level (same as 011) */
947#define ENUM_ALWAYS_ON_EI0CFG_IRQ0EN_DIS (0X0000U) /* External Interrupt 0 Disabled */
948#define ENUM_ALWAYS_ON_EI0CFG_IRQ0EN_EN (0X0001U) /* External Interrupt 0 Enabled */
949#define ENUM_ALWAYS_ON_EI0CFG_IRQ0MDE_RISE (0X0000U) /* Rising Edge */
950#define ENUM_ALWAYS_ON_EI0CFG_IRQ0MDE_FALL (0X0001U) /* Falling Edge */
951#define ENUM_ALWAYS_ON_EI0CFG_IRQ0MDE_RISEORFALL (0X0002U) /* Rising or Falling Edge */
952#define ENUM_ALWAYS_ON_EI0CFG_IRQ0MDE_HIGHLEVEL (0X0003U) /* High Level */
953#define ENUM_ALWAYS_ON_EI0CFG_IRQ0MDE_LOWLEVEL (0X0004U) /* Low Level */
954#define ENUM_ALWAYS_ON_EI0CFG_IRQ0MDE_FALLAUX (0X0005U) /* Falling Edge (same as 001) */
955#define ENUM_ALWAYS_ON_EI0CFG_IRQ0MDE_RISEORFALLAUX (0X0006U) /* Rising or Falling Edge (same as 010) */
956#define ENUM_ALWAYS_ON_EI0CFG_IRQ0MDE_HIGHLEVELAUX (0X0007U) /* High Level (same as 011) */
957
958/* ----------------------------------------------------------------------------------------------------
959 EI1CFG Value Description
960 ---------------------------------------------------------------------------------------------------- */
961#define BITP_ALWAYS_ON_EI1CFG_IRQ4MDE (0U) /* External Interrupt 4 Mode Registers */
962#define BITL_ALWAYS_ON_EI1CFG_IRQ4MDE (3U) /* External Interrupt 4 Mode Registers */
963#define BITM_ALWAYS_ON_EI1CFG_IRQ4MDE (0X0007U) /* External Interrupt 4 Mode Registers */
964#define BITP_ALWAYS_ON_EI1CFG_IRQ4EN (3U) /* External Interrupt 4 Enable Bit */
965#define BITL_ALWAYS_ON_EI1CFG_IRQ4EN (1U) /* External Interrupt 4 Enable Bit */
966#define BITM_ALWAYS_ON_EI1CFG_IRQ4EN (0X0008U) /* External Interrupt 4 Enable Bit */
967#define BITP_ALWAYS_ON_EI1CFG_IRQ5MDE (4U) /* External Interrupt 5 Mode Registers */
968#define BITL_ALWAYS_ON_EI1CFG_IRQ5MDE (3U) /* External Interrupt 5 Mode Registers */
969#define BITM_ALWAYS_ON_EI1CFG_IRQ5MDE (0X0070U) /* External Interrupt 5 Mode Registers */
970#define BITP_ALWAYS_ON_EI1CFG_IRQ5EN (7U) /* External Interrupt 5 Enable Bit */
971#define BITL_ALWAYS_ON_EI1CFG_IRQ5EN (1U) /* External Interrupt 5 Enable Bit */
972#define BITM_ALWAYS_ON_EI1CFG_IRQ5EN (0X0080U) /* External Interrupt 5 Enable Bit */
973#define BITP_ALWAYS_ON_EI1CFG_IRQ6MDE (8U) /* External Interrupt 6 Mode Registers */
974#define BITL_ALWAYS_ON_EI1CFG_IRQ6MDE (3U) /* External Interrupt 6 Mode Registers */
975#define BITM_ALWAYS_ON_EI1CFG_IRQ6MDE (0X0700U) /* External Interrupt 6 Mode Registers */
976#define BITP_ALWAYS_ON_EI1CFG_IRQ6EN (11U) /* External Interrupt 6 Enable Bit */
977#define BITL_ALWAYS_ON_EI1CFG_IRQ6EN (1U) /* External Interrupt 6 Enable Bit */
978#define BITM_ALWAYS_ON_EI1CFG_IRQ6EN (0X0800U) /* External Interrupt 6 Enable Bit */
979#define BITP_ALWAYS_ON_EI1CFG_IRQ7MDE (12U) /* External Interrupt 7 Mode Registers */
980#define BITL_ALWAYS_ON_EI1CFG_IRQ7MDE (3U) /* External Interrupt 7 Mode Registers */
981#define BITM_ALWAYS_ON_EI1CFG_IRQ7MDE (0X7000U) /* External Interrupt 7 Mode Registers */
982#define BITP_ALWAYS_ON_EI1CFG_IRQ7EN (15U) /* External Interrupt 7 Enable Bit */
983#define BITL_ALWAYS_ON_EI1CFG_IRQ7EN (1U) /* External Interrupt 7 Enable Bit */
984#define BITM_ALWAYS_ON_EI1CFG_IRQ7EN (0X8000U) /* External Interrupt 7 Enable Bit */
985
986#define ENUM_ALWAYS_ON_EI1CFG_IRQ7EN_DIS (0X0000U) /* External Interrupt 7 Disabled */
987#define ENUM_ALWAYS_ON_EI1CFG_IRQ7EN_EN (0X0001U) /* External Interrupt 7 Enabled */
988#define ENUM_ALWAYS_ON_EI1CFG_IRQ7MDE_RISE (0X0000U) /* Rising Edge */
989#define ENUM_ALWAYS_ON_EI1CFG_IRQ7MDE_FALL (0X0001U) /* Falling Edge */
990#define ENUM_ALWAYS_ON_EI1CFG_IRQ7MDE_RISEORFALL (0X0002U) /* Rising or Falling Edge */
991#define ENUM_ALWAYS_ON_EI1CFG_IRQ7MDE_HIGHLEVEL (0X0003U) /* High Level */
992#define ENUM_ALWAYS_ON_EI1CFG_IRQ7MDE_LOWLEVEL (0X0004U) /* Low Level */
993#define ENUM_ALWAYS_ON_EI1CFG_IRQ7MDE_FALLAUX (0X0005U) /* Falling Edge (same as 001) */
994#define ENUM_ALWAYS_ON_EI1CFG_IRQ7MDE_RISEORFALLAUX (0X0006U) /* Rising or Falling Edge (same as 010) */
995#define ENUM_ALWAYS_ON_EI1CFG_IRQ7MDE_HIGHLEVELAUX (0X0007U) /* High Level (same as 011) */
996#define ENUM_ALWAYS_ON_EI1CFG_IRQ6EN_DIS (0X0000U) /* External Interrupt 6 Disabled */
997#define ENUM_ALWAYS_ON_EI1CFG_IRQ6EN_EN (0X0001U) /* External Interrupt 6 Enabled */
998#define ENUM_ALWAYS_ON_EI1CFG_IRQ6MDE_RISE (0X0000U) /* Rising Edge */
999#define ENUM_ALWAYS_ON_EI1CFG_IRQ6MDE_FALL (0X0001U) /* Falling Edge */
1000#define ENUM_ALWAYS_ON_EI1CFG_IRQ6MDE_RISEORFALL (0X0002U) /* Rising or Falling Edge */
1001#define ENUM_ALWAYS_ON_EI1CFG_IRQ6MDE_HIGHLEVEL (0X0003U) /* High Level */
1002#define ENUM_ALWAYS_ON_EI1CFG_IRQ6MDE_LOWLEVEL (0X0004U) /* Low Level */
1003#define ENUM_ALWAYS_ON_EI1CFG_IRQ6MDE_FALLAUX (0X0005U) /* Falling Edge (same as 001) */
1004#define ENUM_ALWAYS_ON_EI1CFG_IRQ6MDE_RISEORFALLAUX (0X0006U) /* Rising or Falling Edge (same as 010) */
1005#define ENUM_ALWAYS_ON_EI1CFG_IRQ6MDE_HIGHLEVELAUX (0X0007U) /* High Level (same as 011) */
1006#define ENUM_ALWAYS_ON_EI1CFG_IRQ5EN_DIS (0X0000U) /* External Interrupt 5 Disabled */
1007#define ENUM_ALWAYS_ON_EI1CFG_IRQ5EN_EN (0X0001U) /* External Interrupt 5 Enabled */
1008#define ENUM_ALWAYS_ON_EI1CFG_IRQ5MDE_RISING (0X0000U) /* Rising Edge */
1009#define ENUM_ALWAYS_ON_EI1CFG_IRQ5MDE_FALLING (0X0001U) /* Falling Edge */
1010#define ENUM_ALWAYS_ON_EI1CFG_IRQ5MDE_RISEORFALL (0X0002U) /* Rising or Falling Edge */
1011#define ENUM_ALWAYS_ON_EI1CFG_IRQ5MDE_HIGHLEVEL (0X0003U) /* High Level */
1012#define ENUM_ALWAYS_ON_EI1CFG_IRQ5MDE_LOWLEVEL (0X0004U) /* Low Level */
1013#define ENUM_ALWAYS_ON_EI1CFG_IRQ5MDE_FALLAUX (0X0005U) /* Falling Edge (same as 001) */
1014#define ENUM_ALWAYS_ON_EI1CFG_IRQ5MDE_RISEORFALLAUX (0X0006U) /* Rising or Falling Edge (same as 010) */
1015#define ENUM_ALWAYS_ON_EI1CFG_IRQ5MDE_HIGHLEVELAUX (0X0007U) /* High Level (same as 011) */
1016#define ENUM_ALWAYS_ON_EI1CFG_IRQ4EN_DIS (0X0000U) /* External Interrupt 4 Disabled */
1017#define ENUM_ALWAYS_ON_EI1CFG_IRQ4EN_EN (0X0001U) /* External Interrupt 4 Enabled */
1018#define ENUM_ALWAYS_ON_EI1CFG_IRQ4MDE_RISE (0X0000U) /* Rising Edge */
1019#define ENUM_ALWAYS_ON_EI1CFG_IRQ4MDE_FALL (0X0001U) /* Falling Edge */
1020#define ENUM_ALWAYS_ON_EI1CFG_IRQ4MDE_RISEORFALL (0X0002U) /* Rising or Falling Edge */
1021#define ENUM_ALWAYS_ON_EI1CFG_IRQ4MDE_HIGHLEVEL (0X0003U) /* High Level */
1022#define ENUM_ALWAYS_ON_EI1CFG_IRQ4MDE_LOWLEVEL (0X0004U) /* Low Level */
1023#define ENUM_ALWAYS_ON_EI1CFG_IRQ4MDE_FALLAUX (0X0005U) /* Falling Edge (same as 001) */
1024#define ENUM_ALWAYS_ON_EI1CFG_IRQ4MDE_RISEORFALLAUX (0X0006U) /* Rising or Falling Edge (same as 010) */
1025#define ENUM_ALWAYS_ON_EI1CFG_IRQ4MDE_HIGHLEVELAUX (0X0007U) /* High Level (same as 011) */
1026
1027/* ----------------------------------------------------------------------------------------------------
1028 EI2CFG Value Description
1029 ---------------------------------------------------------------------------------------------------- */
1030#define BITP_ALWAYS_ON_EI2CFG_IRQ8MDE (0U) /* External Interrupt 8 Mode Registers */
1031#define BITL_ALWAYS_ON_EI2CFG_IRQ8MDE (3U) /* External Interrupt 8 Mode Registers */
1032#define BITM_ALWAYS_ON_EI2CFG_IRQ8MDE (0X0007U) /* External Interrupt 8 Mode Registers */
1033#define BITP_ALWAYS_ON_EI2CFG_IRQ8EN (3U) /* External Interrupt 8 Enable Bit */
1034#define BITL_ALWAYS_ON_EI2CFG_IRQ8EN (1U) /* External Interrupt 8 Enable Bit */
1035#define BITM_ALWAYS_ON_EI2CFG_IRQ8EN (0X0008U) /* External Interrupt 8 Enable Bit */
1036#define BITP_ALWAYS_ON_EI2CFG_IRQ9MDE (4U) /* External Interrupt 8 Mode Registers */
1037#define BITL_ALWAYS_ON_EI2CFG_IRQ9MDE (3U) /* External Interrupt 8 Mode Registers */
1038#define BITM_ALWAYS_ON_EI2CFG_IRQ9MDE (0X0070U) /* External Interrupt 8 Mode Registers */
1039#define BITP_ALWAYS_ON_EI2CFG_IRQ9EN (7U) /* External Interrupt 8 Enable Bit */
1040#define BITL_ALWAYS_ON_EI2CFG_IRQ9EN (1U) /* External Interrupt 8 Enable Bit */
1041#define BITM_ALWAYS_ON_EI2CFG_IRQ9EN (0X0080U) /* External Interrupt 8 Enable Bit */
1042
1043#define ENUM_ALWAYS_ON_EI2CFG_IRQ9EN_DIS (0X0000U) /* External Interrupt 8 Disabled */
1044#define ENUM_ALWAYS_ON_EI2CFG_IRQ9EN_EN (0X0001U) /* External Interrupt 8 Enabled */
1045#define ENUM_ALWAYS_ON_EI2CFG_IRQ9MDE_RISE (0X0000U) /* Rising Edge */
1046#define ENUM_ALWAYS_ON_EI2CFG_IRQ9MDE_FALL (0X0001U) /* Falling Edge */
1047#define ENUM_ALWAYS_ON_EI2CFG_IRQ9MDE_RISEORFALL (0X0002U) /* Rising or Falling Edge */
1048#define ENUM_ALWAYS_ON_EI2CFG_IRQ9MDE_HIGHLEVEL (0X0003U) /* High Level */
1049#define ENUM_ALWAYS_ON_EI2CFG_IRQ9MDE_LOWLEVEL (0X0004U) /* Low Level */
1050#define ENUM_ALWAYS_ON_EI2CFG_IRQ9MDE_FALLAUX (0X0005U) /* Falling Edge (same as 001) */
1051#define ENUM_ALWAYS_ON_EI2CFG_IRQ9MDE_RISEORFALLAUX (0X0006U) /* Rising or Falling Edge (same as 010) */
1052#define ENUM_ALWAYS_ON_EI2CFG_IRQ9MDE_HIGHLEVELAUX (0X0007U) /* High Level (same as 011) */
1053#define ENUM_ALWAYS_ON_EI2CFG_IRQ8EN_DIS (0X0000U) /* External Interrupt 8 Disabled */
1054#define ENUM_ALWAYS_ON_EI2CFG_IRQ8EN_EN (0X0001U) /* External Interrupt 8 Enabled */
1055#define ENUM_ALWAYS_ON_EI2CFG_IRQ8MDE_RISE (0X0000U) /* Rising Edge */
1056#define ENUM_ALWAYS_ON_EI2CFG_IRQ8MDE_FALL (0X0001U) /* Falling Edge */
1057#define ENUM_ALWAYS_ON_EI2CFG_IRQ8MDE_RISEORFALL (0X0002U) /* Rising or Falling Edge */
1058#define ENUM_ALWAYS_ON_EI2CFG_IRQ8MDE_HIGHLEVEL (0X0003U) /* High Level */
1059#define ENUM_ALWAYS_ON_EI2CFG_IRQ8MDE_LOWLEVEL (0X0004U) /* Low Level */
1060#define ENUM_ALWAYS_ON_EI2CFG_IRQ8MDE_FALLAUX (0X0005U) /* Falling Edge (same as 001) */
1061#define ENUM_ALWAYS_ON_EI2CFG_IRQ8MDE_RISEORFALLAUX (0X0006U) /* Rising or Falling Edge (same as 010) */
1062#define ENUM_ALWAYS_ON_EI2CFG_IRQ8MDE_HIGHLEVELAUX (0X0007U) /* High Level (same as 011) */
1063
1064/* ----------------------------------------------------------------------------------------------------
1065 EICLR Value Description
1066 ---------------------------------------------------------------------------------------------------- */
1067#define BITP_ALWAYS_ON_EICLR_IRQ0 (0U) /* External Interrupt 0 */
1068#define BITL_ALWAYS_ON_EICLR_IRQ0 (1U) /* External Interrupt 0 */
1069#define BITM_ALWAYS_ON_EICLR_IRQ0 (0X0001U) /* External Interrupt 0 */
1070#define BITP_ALWAYS_ON_EICLR_IRQ1 (1U) /* External Interrupt 1 */
1071#define BITL_ALWAYS_ON_EICLR_IRQ1 (1U) /* External Interrupt 1 */
1072#define BITM_ALWAYS_ON_EICLR_IRQ1 (0X0002U) /* External Interrupt 1 */
1073#define BITP_ALWAYS_ON_EICLR_IRQ2 (2U) /* External Interrupt 2 */
1074#define BITL_ALWAYS_ON_EICLR_IRQ2 (1U) /* External Interrupt 2 */
1075#define BITM_ALWAYS_ON_EICLR_IRQ2 (0X0004U) /* External Interrupt 2 */
1076#define BITP_ALWAYS_ON_EICLR_IRQ3 (3U) /* External Interrupt 3 */
1077#define BITL_ALWAYS_ON_EICLR_IRQ3 (1U) /* External Interrupt 3 */
1078#define BITM_ALWAYS_ON_EICLR_IRQ3 (0X0008U) /* External Interrupt 3 */
1079#define BITP_ALWAYS_ON_EICLR_IRQ4 (4U) /* External Interrupt 4 */
1080#define BITL_ALWAYS_ON_EICLR_IRQ4 (1U) /* External Interrupt 4 */
1081#define BITM_ALWAYS_ON_EICLR_IRQ4 (0X0010U) /* External Interrupt 4 */
1082#define BITP_ALWAYS_ON_EICLR_IRQ5 (5U) /* External Interrupt 5 */
1083#define BITL_ALWAYS_ON_EICLR_IRQ5 (1U) /* External Interrupt 5 */
1084#define BITM_ALWAYS_ON_EICLR_IRQ5 (0X0020U) /* External Interrupt 5 */
1085#define BITP_ALWAYS_ON_EICLR_IRQ6 (6U) /* External Interrupt 6 */
1086#define BITL_ALWAYS_ON_EICLR_IRQ6 (1U) /* External Interrupt 6 */
1087#define BITM_ALWAYS_ON_EICLR_IRQ6 (0X0040U) /* External Interrupt 6 */
1088#define BITP_ALWAYS_ON_EICLR_IRQ7 (7U) /* External Interrupt 7 */
1089#define BITL_ALWAYS_ON_EICLR_IRQ7 (1U) /* External Interrupt 7 */
1090#define BITM_ALWAYS_ON_EICLR_IRQ7 (0X0080U) /* External Interrupt 7 */
1091#define BITP_ALWAYS_ON_EICLR_IRQ8 (8U) /* External Interrupt 8 */
1092#define BITL_ALWAYS_ON_EICLR_IRQ8 (1U) /* External Interrupt 8 */
1093#define BITM_ALWAYS_ON_EICLR_IRQ8 (0X0100U) /* External Interrupt 8 */
1094#define BITP_ALWAYS_ON_EICLR_IRQ9 (9U) /* External Interrupt 9 */
1095#define BITL_ALWAYS_ON_EICLR_IRQ9 (1U) /* External Interrupt 9 */
1096#define BITM_ALWAYS_ON_EICLR_IRQ9 (0X0200U) /* External Interrupt 9 */
1097
1098#define ENUM_ALWAYS_ON_EICLR_IRQ9_NOTCLR (0X0000U) /* No description provided */
1099#define ENUM_ALWAYS_ON_EICLR_IRQ9_CLR (0X0001U) /* No description provided */
1100#define ENUM_ALWAYS_ON_EICLR_IRQ8_NOTCLR (0X0000U) /* No description provided */
1101#define ENUM_ALWAYS_ON_EICLR_IRQ8_CLR (0X0001U) /* No description provided */
1102#define ENUM_ALWAYS_ON_EICLR_IRQ7_NOTCLR (0X0000U) /* No description provided */
1103#define ENUM_ALWAYS_ON_EICLR_IRQ7_CLR (0X0001U) /* No description provided */
1104#define ENUM_ALWAYS_ON_EICLR_IRQ6_NOTCLR (0X0000U) /* No description provided */
1105#define ENUM_ALWAYS_ON_EICLR_IRQ6_CLR (0X0001U) /* No description provided */
1106#define ENUM_ALWAYS_ON_EICLR_IRQ5_NOTCLR (0X0000U) /* No description provided */
1107#define ENUM_ALWAYS_ON_EICLR_IRQ5_CLR (0X0001U) /* No description provided */
1108#define ENUM_ALWAYS_ON_EICLR_IRQ4_NOTCLR (0X0000U) /* No description provided */
1109#define ENUM_ALWAYS_ON_EICLR_IRQ4_CLR (0X0001U) /* No description provided */
1110#define ENUM_ALWAYS_ON_EICLR_IRQ3_NOTCLR (0X0000U) /* No description provided */
1111#define ENUM_ALWAYS_ON_EICLR_IRQ3_CLR (0X0001U) /* No description provided */
1112#define ENUM_ALWAYS_ON_EICLR_IRQ2_NOTCLR (0X0000U) /* No description provided */
1113#define ENUM_ALWAYS_ON_EICLR_IRQ2_CLR (0X0001U) /* No description provided */
1114#define ENUM_ALWAYS_ON_EICLR_IRQ1_NOTCLR (0X0000U) /* No description provided */
1115#define ENUM_ALWAYS_ON_EICLR_IRQ1_CLR (0X0001U) /* No description provided */
1116#define ENUM_ALWAYS_ON_EICLR_IRQ0_NOTCLR (0X0000U) /* No description provided */
1117#define ENUM_ALWAYS_ON_EICLR_IRQ0_CLR (0X0001U) /* No description provided */
1118
1119/* ----------------------------------------------------------------------------------------------------
1120 RSTSTA Value Description
1121 ---------------------------------------------------------------------------------------------------- */
1122#define BITP_ALWAYS_ON_RSTSTA_POR (0U) /* Power-on Reset */
1123#define BITL_ALWAYS_ON_RSTSTA_POR (1U) /* Power-on Reset */
1124#define BITM_ALWAYS_ON_RSTSTA_POR (0X0001U) /* Power-on Reset */
1125#define BITP_ALWAYS_ON_RSTSTA_EXTRST (1U) /* External Reset */
1126#define BITL_ALWAYS_ON_RSTSTA_EXTRST (1U) /* External Reset */
1127#define BITM_ALWAYS_ON_RSTSTA_EXTRST (0X0002U) /* External Reset */
1128#define BITP_ALWAYS_ON_RSTSTA_WDRST (2U) /* Watchdog Timeout */
1129#define BITL_ALWAYS_ON_RSTSTA_WDRST (1U) /* Watchdog Timeout */
1130#define BITM_ALWAYS_ON_RSTSTA_WDRST (0X0004U) /* Watchdog Timeout */
1131#define BITP_ALWAYS_ON_RSTSTA_SWRST (3U) /* Software Reset */
1132#define BITL_ALWAYS_ON_RSTSTA_SWRST (1U) /* Software Reset */
1133#define BITM_ALWAYS_ON_RSTSTA_SWRST (0X0008U) /* Software Reset */
1134
1135#endif /* end ifndef ALWAYS_ON_ADDR_RDEF_H_ */
1136
1137
1138#ifndef PLA_ADDR_RDEF_H_
1139#define PLA_ADDR_RDEF_H_ /* PLA: PLA Register Map */
1140
1141/* ====================================================================================================
1142 PLA Module Instances Address and Mask Definitions
1143 ==================================================================================================== */
1144#define INST_PLA (0X40006000U) /* pla: */
1145
1146#define MASK_PLA (0XFFFFFFFFU) /* PLA: PLA Register Map */
1147
1148/* ====================================================================================================
1149 PLA Module Register Address Offset Definitions
1150 ==================================================================================================== */
1151#define IDX_PLA_PLA_ELEM0 (0X00000000U) /* ELEMx Configuration Register */
1152#define IDX_PLA_PLA_ELEM1 (0X00000004U) /* ELEMx Configuration Register */
1153#define IDX_PLA_PLA_ELEM2 (0X00000008U) /* ELEMx Configuration Register */
1154#define IDX_PLA_PLA_ELEM3 (0X0000000CU) /* ELEMx Configuration Register */
1155#define IDX_PLA_PLA_ELEM4 (0X00000010U) /* ELEMx Configuration Register */
1156#define IDX_PLA_PLA_ELEM5 (0X00000014U) /* ELEMx Configuration Register */
1157#define IDX_PLA_PLA_ELEM6 (0X00000018U) /* ELEMx Configuration Register */
1158#define IDX_PLA_PLA_ELEM7 (0X0000001CU) /* ELEMx Configuration Register */
1159#define IDX_PLA_PLA_ELEM8 (0X00000020U) /* ELEMx Configuration Register */
1160#define IDX_PLA_PLA_ELEM9 (0X00000024U) /* ELEMx Configuration Register */
1161#define IDX_PLA_PLA_ELEM10 (0X00000028U) /* ELEMx Configuration Register */
1162#define IDX_PLA_PLA_ELEM11 (0X0000002CU) /* ELEMx Configuration Register */
1163#define IDX_PLA_PLA_ELEM12 (0X00000030U) /* ELEMx Configuration Register */
1164#define IDX_PLA_PLA_ELEM13 (0X00000034U) /* ELEMx Configuration Register */
1165#define IDX_PLA_PLA_ELEM14 (0X00000038U) /* ELEMx Configuration Register */
1166#define IDX_PLA_PLA_ELEM15 (0X0000003CU) /* ELEMx Configuration Register */
1167#define IDX_PLA_PLA_ELEM16 (0X00000040U) /* ELEMx Configuration Register */
1168#define IDX_PLA_PLA_ELEM17 (0X00000044U) /* ELEMx Configuration Register */
1169#define IDX_PLA_PLA_ELEM18 (0X00000048U) /* ELEMx Configuration Register */
1170#define IDX_PLA_PLA_ELEM19 (0X0000004CU) /* ELEMx Configuration Register */
1171#define IDX_PLA_PLA_ELEM20 (0X00000050U) /* ELEMx Configuration Register */
1172#define IDX_PLA_PLA_ELEM21 (0X00000054U) /* ELEMx Configuration Register */
1173#define IDX_PLA_PLA_ELEM22 (0X00000058U) /* ELEMx Configuration Register */
1174#define IDX_PLA_PLA_ELEM23 (0X0000005CU) /* ELEMx Configuration Register */
1175#define IDX_PLA_PLA_ELEM24 (0X00000060U) /* ELEMx Configuration Register */
1176#define IDX_PLA_PLA_ELEM25 (0X00000064U) /* ELEMx Configuration Register */
1177#define IDX_PLA_PLA_ELEM26 (0X00000068U) /* ELEMx Configuration Register */
1178#define IDX_PLA_PLA_ELEM27 (0X0000006CU) /* ELEMx Configuration Register */
1179#define IDX_PLA_PLA_ELEM28 (0X00000070U) /* ELEMx Configuration Register */
1180#define IDX_PLA_PLA_ELEM29 (0X00000074U) /* ELEMx Configuration Register */
1181#define IDX_PLA_PLA_ELEM30 (0X00000078U) /* ELEMx Configuration Register */
1182#define IDX_PLA_PLA_ELEM31 (0X0000007CU) /* ELEMx Configuration Register */
1183#define IDX_PLA_PLA_CLK (0X00000080U) /* PLA Clock Select */
1184#define IDX_PLA_PLA_IRQ0 (0X00000084U) /* Interrupt Register for Block 0 */
1185#define IDX_PLA_PLA_IRQ1 (0X00000088U) /* Interrupt Register for Block1 */
1186#define IDX_PLA_PLA_ADC (0X0000008CU) /* ADC Configuration Register */
1187#define IDX_PLA_PLA_DIN0 (0X00000090U) /* AMBA Bus Data Input for Block 0 */
1188#define IDX_PLA_PLA_DOUT0 (0X00000098U) /* AMBA Bus Data Output for Block 0 */
1189#define IDX_PLA_PLA_DOUT1 (0X0000009CU) /* AMBA Bus Data Output for Block1 */
1190#define IDX_PLA_PLA_LCK (0X000000A0U) /* Write Lock Register. */
1191#define IDX_PLA_PLA_IRQTYPE (0X000000A4U) /* PLA Interrupt Request and DMA Request Type */
1192
1193/* ====================================================================================================
1194 PLA Module Register ResetValue Definitions
1195 ==================================================================================================== */
1196#define RSTVAL_PLA_PLA_ELEM0 (0X0)
1197#define RSTVAL_PLA_PLA_ELEM1 (0X0)
1198#define RSTVAL_PLA_PLA_ELEM2 (0X0)
1199#define RSTVAL_PLA_PLA_ELEM3 (0X0)
1200#define RSTVAL_PLA_PLA_ELEM4 (0X0)
1201#define RSTVAL_PLA_PLA_ELEM5 (0X0)
1202#define RSTVAL_PLA_PLA_ELEM6 (0X0)
1203#define RSTVAL_PLA_PLA_ELEM7 (0X0)
1204#define RSTVAL_PLA_PLA_ELEM8 (0X0)
1205#define RSTVAL_PLA_PLA_ELEM9 (0X0)
1206#define RSTVAL_PLA_PLA_ELEM10 (0X0)
1207#define RSTVAL_PLA_PLA_ELEM11 (0X0)
1208#define RSTVAL_PLA_PLA_ELEM12 (0X0)
1209#define RSTVAL_PLA_PLA_ELEM13 (0X0)
1210#define RSTVAL_PLA_PLA_ELEM14 (0X0)
1211#define RSTVAL_PLA_PLA_ELEM15 (0X0)
1212#define RSTVAL_PLA_PLA_ELEM16 (0X0)
1213#define RSTVAL_PLA_PLA_ELEM17 (0X0)
1214#define RSTVAL_PLA_PLA_ELEM18 (0X0)
1215#define RSTVAL_PLA_PLA_ELEM19 (0X0)
1216#define RSTVAL_PLA_PLA_ELEM20 (0X0)
1217#define RSTVAL_PLA_PLA_ELEM21 (0X0)
1218#define RSTVAL_PLA_PLA_ELEM22 (0X0)
1219#define RSTVAL_PLA_PLA_ELEM23 (0X0)
1220#define RSTVAL_PLA_PLA_ELEM24 (0X0)
1221#define RSTVAL_PLA_PLA_ELEM25 (0X0)
1222#define RSTVAL_PLA_PLA_ELEM26 (0X0)
1223#define RSTVAL_PLA_PLA_ELEM27 (0X0)
1224#define RSTVAL_PLA_PLA_ELEM28 (0X0)
1225#define RSTVAL_PLA_PLA_ELEM29 (0X0)
1226#define RSTVAL_PLA_PLA_ELEM30 (0X0)
1227#define RSTVAL_PLA_PLA_ELEM31 (0X0)
1228#define RSTVAL_PLA_PLA_CLK (0X0)
1229#define RSTVAL_PLA_PLA_IRQ0 (0X0)
1230#define RSTVAL_PLA_PLA_IRQ1 (0X0)
1231#define RSTVAL_PLA_PLA_ADC (0X0)
1232#define RSTVAL_PLA_PLA_DIN0 (0X0)
1233#define RSTVAL_PLA_PLA_DOUT0 (0X0)
1234#define RSTVAL_PLA_PLA_DOUT1 (0X0)
1235#define RSTVAL_PLA_PLA_LCK (0X0)
1236#define RSTVAL_PLA_PLA_IRQTYPE (0X0)
1237
1238/* ====================================================================================================
1239 PLA Module Register BitPositions, Lengths, Masks and Enumerations Definitions
1240 ==================================================================================================== */
1241
1242/* ----------------------------------------------------------------------------------------------------
1243 PLA_ELEM0 Value Description
1244 ---------------------------------------------------------------------------------------------------- */
1245#define BITP_PLA_PLA_ELEM_N__MUX4 (0U) /* Select or Bypass Flip-flop Output */
1246#define BITL_PLA_PLA_ELEM_N__MUX4 (1U) /* Select or Bypass Flip-flop Output */
1247#define BITM_PLA_PLA_ELEM_N__MUX4 (0X0001U) /* Select or Bypass Flip-flop Output */
1248#define BITP_PLA_PLA_ELEM_N__TBL (1U) /* Configures Output */
1249#define BITL_PLA_PLA_ELEM_N__TBL (4U) /* Configures Output */
1250#define BITM_PLA_PLA_ELEM_N__TBL (0X001EU) /* Configures Output */
1251#define BITP_PLA_PLA_ELEM_N__MUX3 (5U) /* Mux Between GPIO Bus Input or Odd Feedback Input */
1252#define BITL_PLA_PLA_ELEM_N__MUX3 (1U) /* Mux Between GPIO Bus Input or Odd Feedback Input */
1253#define BITM_PLA_PLA_ELEM_N__MUX3 (0X0020U) /* Mux Between GPIO Bus Input or Odd Feedback Input */
1254#define BITP_PLA_PLA_ELEM_N__MUX2 (6U) /* Mux Between PLA_DINx Register/Block0 Output or Even Feedback */
1255#define BITL_PLA_PLA_ELEM_N__MUX2 (1U) /* Mux Between PLA_DINx Register/Block0 Output or Even Feedback */
1256#define BITM_PLA_PLA_ELEM_N__MUX2 (0X0040U) /* Mux Between PLA_DINx Register/Block0 Output or Even Feedback */
1257#define BITP_PLA_PLA_ELEM_N__MUX1 (7U) /* Mux for Odd Element Feedback (In Respective Block) */
1258#define BITL_PLA_PLA_ELEM_N__MUX1 (3U) /* Mux for Odd Element Feedback (In Respective Block) */
1259#define BITM_PLA_PLA_ELEM_N__MUX1 (0X0380U) /* Mux for Odd Element Feedback (In Respective Block) */
1260#define BITP_PLA_PLA_ELEM_N__MUX0 (10U) /* Mux for Even Element Feedback(in Respective Block) */
1261#define BITL_PLA_PLA_ELEM_N__MUX0 (3U) /* Mux for Even Element Feedback(in Respective Block) */
1262#define BITM_PLA_PLA_ELEM_N__MUX0 (0X1C00U) /* Mux for Even Element Feedback(in Respective Block) */
1263
1264#define ENUM_PLA_PLA_ELEM_N__MUX0_ELEM0 (0X0000U) /* Feedback from Element 0 (all Except Element 0) / Input from Other Block (Element 0 Only) */
1265#define ENUM_PLA_PLA_ELEM_N__MUX0_ELEM2 (0X0001U) /* Feedback from Element 2 */
1266#define ENUM_PLA_PLA_ELEM_N__MUX0_ELEM4 (0X0002U) /* Feedback from Element 4 */
1267#define ENUM_PLA_PLA_ELEM_N__MUX0_ELEM6 (0X0003U) /* Feedback from Element 6 */
1268#define ENUM_PLA_PLA_ELEM_N__MUX0_ELEM8 (0X0004U) /* Feedback from Element 8 */
1269#define ENUM_PLA_PLA_ELEM_N__MUX0_ELEM10 (0X0005U) /* Feedback from Element 10 */
1270#define ENUM_PLA_PLA_ELEM_N__MUX0_ELEM12 (0X0006U) /* Feedback from Element 12 */
1271#define ENUM_PLA_PLA_ELEM_N__MUX0_ELEM14 (0X0007U) /* Feedback from Element 14 */
1272#define ENUM_PLA_PLA_ELEM_N__MUX1_ELEM1 (0X0000U) /* Feedback from Element 1 */
1273#define ENUM_PLA_PLA_ELEM_N__MUX1_ELEM3 (0X0001U) /* Feedback from Element 3 */
1274#define ENUM_PLA_PLA_ELEM_N__MUX1_ELEM5 (0X0002U) /* Feedback from Element 5 */
1275#define ENUM_PLA_PLA_ELEM_N__MUX1_ELEM7 (0X0003U) /* Feedback from Element 7 */
1276#define ENUM_PLA_PLA_ELEM_N__MUX1_ELEM9 (0X0004U) /* Feedback from Element 9 */
1277#define ENUM_PLA_PLA_ELEM_N__MUX1_ELEM11 (0X0005U) /* Feedback from Element 11 */
1278#define ENUM_PLA_PLA_ELEM_N__MUX1_ELEM13 (0X0006U) /* Feedback from Element 13 */
1279#define ENUM_PLA_PLA_ELEM_N__MUX1_ELEM15 (0X0007U) /* Feedback from Element 15 */
1280#define ENUM_PLA_PLA_ELEM_N__MUX2_MMR (0X0000U) /* PLA_DINx Input */
1281#define ENUM_PLA_PLA_ELEM_N__MUX2_EVEN (0X0001U) /* Even Feedback Mux */
1282#define ENUM_PLA_PLA_ELEM_N__MUX3_ODD (0X0000U) /* Odd Feedback Mux */
1283#define ENUM_PLA_PLA_ELEM_N__MUX3_GPIO (0X0001U) /* GPIO Input */
1284#define ENUM_PLA_PLA_ELEM_N__TBL_LOW (0X0000U) /* 0. */
1285#define ENUM_PLA_PLA_ELEM_N__TBL_FUN_NOR (0X0001U) /* NOR. */
1286#define ENUM_PLA_PLA_ELEM_N__TBL_BANDNOTA (0X0002U) /* B and Not A. */
1287#define ENUM_PLA_PLA_ELEM_N__TBL_NOTA (0X0003U) /* NOT A. */
1288#define ENUM_PLA_PLA_ELEM_N__TBL_AANDNOTB (0X0004U) /* A and Not B. */
1289#define ENUM_PLA_PLA_ELEM_N__TBL_NOTB (0X0005U) /* Not B. */
1290#define ENUM_PLA_PLA_ELEM_N__TBL_EXOR (0X0006U) /* EXOR. */
1291#define ENUM_PLA_PLA_ELEM_N__TBL_FUN_NAND (0X0007U) /* NAND. */
1292#define ENUM_PLA_PLA_ELEM_N__TBL_FUN_AND (0X0008U) /* AND. */
1293#define ENUM_PLA_PLA_ELEM_N__TBL_EXNOR (0X0009U) /* EXNOR. */
1294#define ENUM_PLA_PLA_ELEM_N__TBL_B (0X000AU) /* B. */
1295#define ENUM_PLA_PLA_ELEM_N__TBL_BORNOTA (0X000BU) /* B or Not A. */
1296#define ENUM_PLA_PLA_ELEM_N__TBL_A (0X000CU) /* A. */
1297#define ENUM_PLA_PLA_ELEM_N__TBL_AORNOTB (0X000DU) /* A or Not B. */
1298#define ENUM_PLA_PLA_ELEM_N__TBL_FUN_OR (0X000EU) /* OR */
1299#define ENUM_PLA_PLA_ELEM_N__TBL_HIGH (0X000FU) /* 1. */
1300#define ENUM_PLA_PLA_ELEM_N__MUX4_FF (0X0000U) /* FF Output */
1301#define ENUM_PLA_PLA_ELEM_N__MUX4_BYPASS (0X0001U) /* Bypass Output */
1302
1303/* ----------------------------------------------------------------------------------------------------
1304 PLA_CLK Value Description
1305 ---------------------------------------------------------------------------------------------------- */
1306#define BITP_PLA_PLA_CLK_BLOCK0 (0U) /* Clock Select for Block 0 */
1307#define BITL_PLA_PLA_CLK_BLOCK0 (3U) /* Clock Select for Block 0 */
1308#define BITM_PLA_PLA_CLK_BLOCK0 (0X0007U) /* Clock Select for Block 0 */
1309#define BITP_PLA_PLA_CLK_BLOCK1 (4U) /* Clock Select for Block 1 */
1310#define BITL_PLA_PLA_CLK_BLOCK1 (3U) /* Clock Select for Block 1 */
1311#define BITM_PLA_PLA_CLK_BLOCK1 (0X0070U) /* Clock Select for Block 1 */
1312
1313#define ENUM_PLA_PLA_CLK_BLOCK1_PLACLK0 (0X0000U) /* GPIO Clock 0 */
1314#define ENUM_PLA_PLA_CLK_BLOCK1_PLACLK1 (0X0001U) /* GPIO Clock 1 */
1315#define ENUM_PLA_PLA_CLK_BLOCK1_PLACLK2 (0X0002U) /* GPIO Clock 2 */
1316#define ENUM_PLA_PLA_CLK_BLOCK1_PCLK0 (0X0003U) /* PCLK0 */
1317#define ENUM_PLA_PLA_CLK_BLOCK1_MOSC (0X0004U) /* MOSC (16 MHz) */
1318#define ENUM_PLA_PLA_CLK_BLOCK1_T0 (0X0005U) /* Timer 0 */
1319#define ENUM_PLA_PLA_CLK_BLOCK1_T2 (0X0006U) /* Timer 2 */
1320#define ENUM_PLA_PLA_CLK_BLOCK1_KOSC (0X0007U) /* KOSC (32 KHz) */
1321#define ENUM_PLA_PLA_CLK_BLOCK0_PLACLK0 (0X0000U) /* GPIO Clock 0 */
1322#define ENUM_PLA_PLA_CLK_BLOCK0_PLACLK1 (0X0001U) /* GPIO Clock 1 */
1323#define ENUM_PLA_PLA_CLK_BLOCK0_PLACLK2 (0X0002U) /* GPIO Clock 2 */
1324#define ENUM_PLA_PLA_CLK_BLOCK0_PCLK0 (0X0003U) /* PCLK0 */
1325#define ENUM_PLA_PLA_CLK_BLOCK0_MOSC (0X0004U) /* MOSC (16 MHz) */
1326#define ENUM_PLA_PLA_CLK_BLOCK0_T0 (0X0005U) /* Timer 0 */
1327#define ENUM_PLA_PLA_CLK_BLOCK0_T2 (0X0006U) /* Timer 2 */
1328#define ENUM_PLA_PLA_CLK_BLOCK0_KOSC (0X0007U) /* KOSC (32 KHz) */
1329
1330/* ----------------------------------------------------------------------------------------------------
1331 PLA_IRQ0 Value Description
1332 ---------------------------------------------------------------------------------------------------- */
1333#define BITP_PLA_PLA_IRQ0_IRQ0_SRC (0U) /* IRQ0 Source Select */
1334#define BITL_PLA_PLA_IRQ0_IRQ0_SRC (4U) /* IRQ0 Source Select */
1335#define BITM_PLA_PLA_IRQ0_IRQ0_SRC (0X000FU) /* IRQ0 Source Select */
1336#define BITP_PLA_PLA_IRQ0_IRQ0_EN (4U) /* IRQ0 Enable */
1337#define BITL_PLA_PLA_IRQ0_IRQ0_EN (1U) /* IRQ0 Enable */
1338#define BITM_PLA_PLA_IRQ0_IRQ0_EN (0X0010U) /* IRQ0 Enable */
1339#define BITP_PLA_PLA_IRQ0_IRQ1_SRC (8U) /* IRQ1 Source Select */
1340#define BITL_PLA_PLA_IRQ0_IRQ1_SRC (4U) /* IRQ1 Source Select */
1341#define BITM_PLA_PLA_IRQ0_IRQ1_SRC (0X0F00U) /* IRQ1 Source Select */
1342#define BITP_PLA_PLA_IRQ0_IRQ1_EN (12U) /* IRQ1 Enable */
1343#define BITL_PLA_PLA_IRQ0_IRQ1_EN (1U) /* IRQ1 Enable */
1344#define BITM_PLA_PLA_IRQ0_IRQ1_EN (0X1000U) /* IRQ1 Enable */
1345
1346#define ENUM_PLA_PLA_IRQ0_IRQ1_EN_DIS (0X0000U) /* Disable IRQ1 Interrupt */
1347#define ENUM_PLA_PLA_IRQ0_IRQ1_EN_EN (0X0001U) /* Enable IRQ1 Interrupt */
1348#define ENUM_PLA_PLA_IRQ0_IRQ0_EN_DIS (0X0000U) /* Disable IRQ0 Interrupt */
1349#define ENUM_PLA_PLA_IRQ0_IRQ0_EN_EN (0X0001U) /* Enable IRQ0 Interrupt */
1350
1351/* ----------------------------------------------------------------------------------------------------
1352 PLA_IRQ1 Value Description
1353 ---------------------------------------------------------------------------------------------------- */
1354#define BITP_PLA_PLA_IRQ1_IRQ2_SRC (0U) /* IRQ2 Source Select */
1355#define BITL_PLA_PLA_IRQ1_IRQ2_SRC (4U) /* IRQ2 Source Select */
1356#define BITM_PLA_PLA_IRQ1_IRQ2_SRC (0X000FU) /* IRQ2 Source Select */
1357#define BITP_PLA_PLA_IRQ1_IRQ2_EN (4U) /* IRQ2 Enable */
1358#define BITL_PLA_PLA_IRQ1_IRQ2_EN (1U) /* IRQ2 Enable */
1359#define BITM_PLA_PLA_IRQ1_IRQ2_EN (0X0010U) /* IRQ2 Enable */
1360#define BITP_PLA_PLA_IRQ1_IRQ3_SRC (8U) /* IRQ3 Source Select */
1361#define BITL_PLA_PLA_IRQ1_IRQ3_SRC (4U) /* IRQ3 Source Select */
1362#define BITM_PLA_PLA_IRQ1_IRQ3_SRC (0X0F00U) /* IRQ3 Source Select */
1363#define BITP_PLA_PLA_IRQ1_IRQ3_EN (12U) /* IRQ3 Enable */
1364#define BITL_PLA_PLA_IRQ1_IRQ3_EN (1U) /* IRQ3 Enable */
1365#define BITM_PLA_PLA_IRQ1_IRQ3_EN (0X1000U) /* IRQ3 Enable */
1366
1367#define ENUM_PLA_PLA_IRQ1_IRQ3_EN_DIS (0X0000U) /* Disable IRQ3 Interrupt */
1368#define ENUM_PLA_PLA_IRQ1_IRQ3_EN_EN (0X0001U) /* Enable IRQ3 Interrupt */
1369#define ENUM_PLA_PLA_IRQ1_IRQ2_EN_DIS (0X0000U) /* Disable IRQ2 Interrupt */
1370#define ENUM_PLA_PLA_IRQ1_IRQ2_EN_EN (0X0001U) /* Enable IRQ2 Interrupt */
1371
1372/* ----------------------------------------------------------------------------------------------------
1373 PLA_ADC Value Description
1374 ---------------------------------------------------------------------------------------------------- */
1375#define BITP_PLA_PLA_ADC_CONVST_SRC (0U) /* Element for ADC Start Convert Source */
1376#define BITL_PLA_PLA_ADC_CONVST_SRC (5U) /* Element for ADC Start Convert Source */
1377#define BITM_PLA_PLA_ADC_CONVST_SRC (0X001FU) /* Element for ADC Start Convert Source */
1378#define BITP_PLA_PLA_ADC_CONVST_EN (5U) /* Bit to Enable ADC Start Convert from PLA */
1379#define BITL_PLA_PLA_ADC_CONVST_EN (1U) /* Bit to Enable ADC Start Convert from PLA */
1380#define BITM_PLA_PLA_ADC_CONVST_EN (0X0020U) /* Bit to Enable ADC Start Convert from PLA */
1381
1382#define ENUM_PLA_PLA_ADC_CONVST_EN_DISABLE (0X0000U) /* Disable */
1383#define ENUM_PLA_PLA_ADC_CONVST_EN_ENABLE (0X0001U) /* Enable */
1384
1385/* ----------------------------------------------------------------------------------------------------
1386 PLA_DIN0 Value Description
1387 ---------------------------------------------------------------------------------------------------- */
1388#define BITP_PLA_PLA_DIN0_DIN (0U) /* Input Bit to Element 15 to Element 0. */
1389#define BITL_PLA_PLA_DIN0_DIN (16U) /* Input Bit to Element 15 to Element 0. */
1390#define BITM_PLA_PLA_DIN0_DIN (0XFFFFU) /* Input Bit to Element 15 to Element 0. */
1391
1392/* ----------------------------------------------------------------------------------------------------
1393 PLA_DOUT0 Value Description
1394 ---------------------------------------------------------------------------------------------------- */
1395#define BITP_PLA_PLA_DOUT0_E0 (0U) /* Output Bit from Element 0 */
1396#define BITL_PLA_PLA_DOUT0_E0 (1U) /* Output Bit from Element 0 */
1397#define BITM_PLA_PLA_DOUT0_E0 (0X0001U) /* Output Bit from Element 0 */
1398#define BITP_PLA_PLA_DOUT0_E1 (1U) /* Output Bit from Element 1 */
1399#define BITL_PLA_PLA_DOUT0_E1 (1U) /* Output Bit from Element 1 */
1400#define BITM_PLA_PLA_DOUT0_E1 (0X0002U) /* Output Bit from Element 1 */
1401#define BITP_PLA_PLA_DOUT0_E2 (2U) /* Output Bit from Element 2 */
1402#define BITL_PLA_PLA_DOUT0_E2 (1U) /* Output Bit from Element 2 */
1403#define BITM_PLA_PLA_DOUT0_E2 (0X0004U) /* Output Bit from Element 2 */
1404#define BITP_PLA_PLA_DOUT0_E3 (3U) /* Output Bit from Element 3 */
1405#define BITL_PLA_PLA_DOUT0_E3 (1U) /* Output Bit from Element 3 */
1406#define BITM_PLA_PLA_DOUT0_E3 (0X0008U) /* Output Bit from Element 3 */
1407#define BITP_PLA_PLA_DOUT0_E4 (4U) /* Output Bit from Element 4 */
1408#define BITL_PLA_PLA_DOUT0_E4 (1U) /* Output Bit from Element 4 */
1409#define BITM_PLA_PLA_DOUT0_E4 (0X0010U) /* Output Bit from Element 4 */
1410#define BITP_PLA_PLA_DOUT0_E5 (5U) /* Output Bit from Element 5 */
1411#define BITL_PLA_PLA_DOUT0_E5 (1U) /* Output Bit from Element 5 */
1412#define BITM_PLA_PLA_DOUT0_E5 (0X0020U) /* Output Bit from Element 5 */
1413#define BITP_PLA_PLA_DOUT0_E6 (6U) /* Output Bit from Element 6 */
1414#define BITL_PLA_PLA_DOUT0_E6 (1U) /* Output Bit from Element 6 */
1415#define BITM_PLA_PLA_DOUT0_E6 (0X0040U) /* Output Bit from Element 6 */
1416#define BITP_PLA_PLA_DOUT0_E7 (7U) /* Output Bit from Element 7 */
1417#define BITL_PLA_PLA_DOUT0_E7 (1U) /* Output Bit from Element 7 */
1418#define BITM_PLA_PLA_DOUT0_E7 (0X0080U) /* Output Bit from Element 7 */
1419#define BITP_PLA_PLA_DOUT0_E8 (8U) /* Output Bit from Element 8 */
1420#define BITL_PLA_PLA_DOUT0_E8 (1U) /* Output Bit from Element 8 */
1421#define BITM_PLA_PLA_DOUT0_E8 (0X0100U) /* Output Bit from Element 8 */
1422#define BITP_PLA_PLA_DOUT0_E9 (9U) /* Output Bit from Element 9 */
1423#define BITL_PLA_PLA_DOUT0_E9 (1U) /* Output Bit from Element 9 */
1424#define BITM_PLA_PLA_DOUT0_E9 (0X0200U) /* Output Bit from Element 9 */
1425#define BITP_PLA_PLA_DOUT0_E10 (10U) /* Output Bit from Element 10 */
1426#define BITL_PLA_PLA_DOUT0_E10 (1U) /* Output Bit from Element 10 */
1427#define BITM_PLA_PLA_DOUT0_E10 (0X0400U) /* Output Bit from Element 10 */
1428#define BITP_PLA_PLA_DOUT0_E11 (11U) /* Output Bit from Element 11 */
1429#define BITL_PLA_PLA_DOUT0_E11 (1U) /* Output Bit from Element 11 */
1430#define BITM_PLA_PLA_DOUT0_E11 (0X0800U) /* Output Bit from Element 11 */
1431#define BITP_PLA_PLA_DOUT0_E12 (12U) /* Output Bit from Element 12 */
1432#define BITL_PLA_PLA_DOUT0_E12 (1U) /* Output Bit from Element 12 */
1433#define BITM_PLA_PLA_DOUT0_E12 (0X1000U) /* Output Bit from Element 12 */
1434#define BITP_PLA_PLA_DOUT0_E13 (13U) /* Output Bit from Element 13 */
1435#define BITL_PLA_PLA_DOUT0_E13 (1U) /* Output Bit from Element 13 */
1436#define BITM_PLA_PLA_DOUT0_E13 (0X2000U) /* Output Bit from Element 13 */
1437#define BITP_PLA_PLA_DOUT0_E14 (14U) /* Output Bit from Element 14 */
1438#define BITL_PLA_PLA_DOUT0_E14 (1U) /* Output Bit from Element 14 */
1439#define BITM_PLA_PLA_DOUT0_E14 (0X4000U) /* Output Bit from Element 14 */
1440#define BITP_PLA_PLA_DOUT0_E15 (15U) /* Output Bit from Element 15 */
1441#define BITL_PLA_PLA_DOUT0_E15 (1U) /* Output Bit from Element 15 */
1442#define BITM_PLA_PLA_DOUT0_E15 (0X8000U) /* Output Bit from Element 15 */
1443
1444/* ----------------------------------------------------------------------------------------------------
1445 PLA_DOUT1 Value Description
1446 ---------------------------------------------------------------------------------------------------- */
1447#define BITP_PLA_PLA_DOUT1_E16 (0U) /* Output Bit from Element 16 */
1448#define BITL_PLA_PLA_DOUT1_E16 (1U) /* Output Bit from Element 16 */
1449#define BITM_PLA_PLA_DOUT1_E16 (0X0001U) /* Output Bit from Element 16 */
1450#define BITP_PLA_PLA_DOUT1_E17 (1U) /* Output Bit from Element 17 */
1451#define BITL_PLA_PLA_DOUT1_E17 (1U) /* Output Bit from Element 17 */
1452#define BITM_PLA_PLA_DOUT1_E17 (0X0002U) /* Output Bit from Element 17 */
1453#define BITP_PLA_PLA_DOUT1_E18 (2U) /* Output Bit from Element 18 */
1454#define BITL_PLA_PLA_DOUT1_E18 (1U) /* Output Bit from Element 18 */
1455#define BITM_PLA_PLA_DOUT1_E18 (0X0004U) /* Output Bit from Element 18 */
1456#define BITP_PLA_PLA_DOUT1_E19 (3U) /* Output Bit from Element 19 */
1457#define BITL_PLA_PLA_DOUT1_E19 (1U) /* Output Bit from Element 19 */
1458#define BITM_PLA_PLA_DOUT1_E19 (0X0008U) /* Output Bit from Element 19 */
1459#define BITP_PLA_PLA_DOUT1_E20 (4U) /* Output Bit from Element 20 */
1460#define BITL_PLA_PLA_DOUT1_E20 (1U) /* Output Bit from Element 20 */
1461#define BITM_PLA_PLA_DOUT1_E20 (0X0010U) /* Output Bit from Element 20 */
1462#define BITP_PLA_PLA_DOUT1_E21 (5U) /* Output Bit from Element 21 */
1463#define BITL_PLA_PLA_DOUT1_E21 (1U) /* Output Bit from Element 21 */
1464#define BITM_PLA_PLA_DOUT1_E21 (0X0020U) /* Output Bit from Element 21 */
1465#define BITP_PLA_PLA_DOUT1_E22 (6U) /* Output Bit from Element 22 */
1466#define BITL_PLA_PLA_DOUT1_E22 (1U) /* Output Bit from Element 22 */
1467#define BITM_PLA_PLA_DOUT1_E22 (0X0040U) /* Output Bit from Element 22 */
1468#define BITP_PLA_PLA_DOUT1_E23 (7U) /* Output Bit from Element 23 */
1469#define BITL_PLA_PLA_DOUT1_E23 (1U) /* Output Bit from Element 23 */
1470#define BITM_PLA_PLA_DOUT1_E23 (0X0080U) /* Output Bit from Element 23 */
1471#define BITP_PLA_PLA_DOUT1_E24 (8U) /* Output Bit from Element 24 */
1472#define BITL_PLA_PLA_DOUT1_E24 (1U) /* Output Bit from Element 24 */
1473#define BITM_PLA_PLA_DOUT1_E24 (0X0100U) /* Output Bit from Element 24 */
1474#define BITP_PLA_PLA_DOUT1_E25 (9U) /* Output Bit from Element 25 */
1475#define BITL_PLA_PLA_DOUT1_E25 (1U) /* Output Bit from Element 25 */
1476#define BITM_PLA_PLA_DOUT1_E25 (0X0200U) /* Output Bit from Element 25 */
1477#define BITP_PLA_PLA_DOUT1_E26 (10U) /* Output Bit from Element 26 */
1478#define BITL_PLA_PLA_DOUT1_E26 (1U) /* Output Bit from Element 26 */
1479#define BITM_PLA_PLA_DOUT1_E26 (0X0400U) /* Output Bit from Element 26 */
1480#define BITP_PLA_PLA_DOUT1_E27 (11U) /* Output Bit from Element 27 */
1481#define BITL_PLA_PLA_DOUT1_E27 (1U) /* Output Bit from Element 27 */
1482#define BITM_PLA_PLA_DOUT1_E27 (0X0800U) /* Output Bit from Element 27 */
1483#define BITP_PLA_PLA_DOUT1_E28 (12U) /* Output Bit from Element 28 */
1484#define BITL_PLA_PLA_DOUT1_E28 (1U) /* Output Bit from Element 28 */
1485#define BITM_PLA_PLA_DOUT1_E28 (0X1000U) /* Output Bit from Element 28 */
1486#define BITP_PLA_PLA_DOUT1_E29 (13U) /* Output Bit from Element 29 */
1487#define BITL_PLA_PLA_DOUT1_E29 (1U) /* Output Bit from Element 29 */
1488#define BITM_PLA_PLA_DOUT1_E29 (0X2000U) /* Output Bit from Element 29 */
1489#define BITP_PLA_PLA_DOUT1_E30 (14U) /* Output Bit from Element 30 */
1490#define BITL_PLA_PLA_DOUT1_E30 (1U) /* Output Bit from Element 30 */
1491#define BITM_PLA_PLA_DOUT1_E30 (0X4000U) /* Output Bit from Element 30 */
1492#define BITP_PLA_PLA_DOUT1_E31 (15U) /* Output Bit from Element 31 */
1493#define BITL_PLA_PLA_DOUT1_E31 (1U) /* Output Bit from Element 31 */
1494#define BITM_PLA_PLA_DOUT1_E31 (0X8000U) /* Output Bit from Element 31 */
1495
1496/* ----------------------------------------------------------------------------------------------------
1497 PLA_LCK Value Description
1498 ---------------------------------------------------------------------------------------------------- */
1499#define BITP_PLA_PLA_LCK_LOCKED (0U) /* Set to Disable Writing to Registers */
1500#define BITL_PLA_PLA_LCK_LOCKED (1U) /* Set to Disable Writing to Registers */
1501#define BITM_PLA_PLA_LCK_LOCKED (0X0001U) /* Set to Disable Writing to Registers */
1502
1503#define ENUM_PLA_PLA_LCK_LOCKED_DIS (0X0000U) /* Writing to Registers Allowed */
1504#define ENUM_PLA_PLA_LCK_LOCKED_EN (0X0001U) /* Writing to Registers Disabled */
1505
1506/* ----------------------------------------------------------------------------------------------------
1507 PLA_IRQTYPE Value Description
1508 ---------------------------------------------------------------------------------------------------- */
1509#define BITP_PLA_PLA_IRQTYPE_IRQ0_TYPE (0U) /* IRQ0 and DMA Request 0 Type */
1510#define BITL_PLA_PLA_IRQTYPE_IRQ0_TYPE (2U) /* IRQ0 and DMA Request 0 Type */
1511#define BITM_PLA_PLA_IRQTYPE_IRQ0_TYPE (0X0003U) /* IRQ0 and DMA Request 0 Type */
1512#define BITP_PLA_PLA_IRQTYPE_IRQ1_TYPE (2U) /* IRQ1 and DMA Request 1Type */
1513#define BITL_PLA_PLA_IRQTYPE_IRQ1_TYPE (2U) /* IRQ1 and DMA Request 1Type */
1514#define BITM_PLA_PLA_IRQTYPE_IRQ1_TYPE (0X000CU) /* IRQ1 and DMA Request 1Type */
1515#define BITP_PLA_PLA_IRQTYPE_IRQ2_TYPE (4U) /* IRQ2 and DMA Request 2 Type */
1516#define BITL_PLA_PLA_IRQTYPE_IRQ2_TYPE (2U) /* IRQ2 and DMA Request 2 Type */
1517#define BITM_PLA_PLA_IRQTYPE_IRQ2_TYPE (0X0030U) /* IRQ2 and DMA Request 2 Type */
1518#define BITP_PLA_PLA_IRQTYPE_IRQ3_TYPE (6U) /* IRQ3 and DMA Request 3 Type */
1519#define BITL_PLA_PLA_IRQTYPE_IRQ3_TYPE (2U) /* IRQ3 and DMA Request 3 Type */
1520#define BITM_PLA_PLA_IRQTYPE_IRQ3_TYPE (0X00C0U) /* IRQ3 and DMA Request 3 Type */
1521
1522#define ENUM_PLA_PLA_IRQTYPE_IRQ3_TYPE_HIGH_LEVEL (0X0000U) /* High Level Trigger Interrupt and High Level Trigger DMA Request */
1523#define ENUM_PLA_PLA_IRQTYPE_IRQ3_TYPE_RISING_EDGE (0X0001U) /* Rising Edge Trigger Interrupt and High Level Trigger DMA Request */
1524#define ENUM_PLA_PLA_IRQTYPE_IRQ3_TYPE_LOW_LEVEL (0X0002U) /* Low Level Trigger Interrupt and Low Level Trigger DMA Request */
1525#define ENUM_PLA_PLA_IRQTYPE_IRQ3_TYPE_FALLING_EDGE (0X0003U) /* Falling Edge Trigger Interrupt and Low Level Trigger DMA Request */
1526#define ENUM_PLA_PLA_IRQTYPE_IRQ2_TYPE_HIGH_LEVEL (0X0000U) /* High Level Trigger Interrupt and High Level Trigger DMA Request */
1527#define ENUM_PLA_PLA_IRQTYPE_IRQ2_TYPE_RISING_EDGE (0X0001U) /* Rising Edge Trigger Interrupt and High Level Trigger DMA Request */
1528#define ENUM_PLA_PLA_IRQTYPE_IRQ2_TYPE_LOW_LEVEL (0X0002U) /* Low Level Trigger Interrupt and Low Level Trigger DMA Request */
1529#define ENUM_PLA_PLA_IRQTYPE_IRQ2_TYPE_FALLING_EDGE (0X0003U) /* Falling Edge Trigger Interrupt and Low Level Trigger DMA Request */
1530#define ENUM_PLA_PLA_IRQTYPE_IRQ1_TYPE_HIGH_LEVEL (0X0000U) /* High Level Trigger Interrupt and High Level Trigger DMA Request */
1531#define ENUM_PLA_PLA_IRQTYPE_IRQ1_TYPE_RISING_EDGE (0X0001U) /* Rising Edge Trigger Interrupt and High Level Trigger DMA Request */
1532#define ENUM_PLA_PLA_IRQTYPE_IRQ1_TYPE_LOW_LEVEL (0X0002U) /* Low Level Trigger Interrupt and Low Level Trigger DMA Request */
1533#define ENUM_PLA_PLA_IRQTYPE_IRQ1_TYPE_FALLING_EDGE (0X0003U) /* Falling Edge Trigger Interrupt and Low Level Trigger DMA Request */
1534#define ENUM_PLA_PLA_IRQTYPE_IRQ0_TYPE_HIGH_LEVEL (0X0000U) /* High Level Trigger Interrupt and High Level Trigger DMA Request */
1535#define ENUM_PLA_PLA_IRQTYPE_IRQ0_TYPE_RISING_EDGE (0X0001U) /* Rising Edge Trigger Interrupt and Rising Edge Trigger DMA Request */
1536#define ENUM_PLA_PLA_IRQTYPE_IRQ0_TYPE_LOW_LEVEL (0X0002U) /* Low Level Trigger Interrupt and Low Level Trigger DMA Request */
1537#define ENUM_PLA_PLA_IRQTYPE_IRQ0_TYPE_FALLING_EDGE (0X0003U) /* Falling Edge Trigger Interrupt and Falling Edge Trigger DMA Request */
1538
1539#endif /* end ifndef PLA_ADDR_RDEF_H_ */
1540
1541
1542#ifndef DMAREQ_ADDR_RDEF_H_
1543#define DMAREQ_ADDR_RDEF_H_ /* DMAREQ: Your module description, here. */
1544
1545/* ====================================================================================================
1546 DMAREQ Module Instances Address and Mask Definitions
1547 ==================================================================================================== */
1548#define INST_DMAREQ (0X40007000U) /* dmareq: */
1549
1550#define MASK_DMAREQ (0X000000FFU) /* DMAREQ: Your module description, here. */
1551
1552/* ====================================================================================================
1553 DMAREQ Module Register Address Offset Definitions
1554 ==================================================================================================== */
1555#define IDX_DMAREQ_REQEN (0X00U) /* GPT/GPT32 and PLA DMA Request Enable */
1556#define IDX_DMAREQ_REQ0SEL (0X04U) /* GPT/GPT32 and PLA DMA Request 0 Select */
1557#define IDX_DMAREQ_REQ1SEL (0X08U) /* GPT/GPT32 and PLA DMA Request 1 Select */
1558#define IDX_DMAREQ_PLAREQEN (0X0CU) /* PLA DMA Requests Enable */
1559#define IDX_DMAREQ_GPTREQEN (0X10U) /* GPT/GPT32 DMA Requests Enable */
1560#define IDX_DMAREQ_GPT_MDA_REQ_TTYPE (0X14U) /* GPT and GPT32 Require Type */
1561
1562/* ====================================================================================================
1563 DMAREQ Module Register ResetValue Definitions
1564 ==================================================================================================== */
1565#define RSTVAL_DMAREQ_REQEN (0X0)
1566#define RSTVAL_DMAREQ_REQ0SEL (0X0)
1567#define RSTVAL_DMAREQ_REQ1SEL (0X0)
1568#define RSTVAL_DMAREQ_PLAREQEN (0X0)
1569#define RSTVAL_DMAREQ_GPTREQEN (0X0)
1570#define RSTVAL_DMAREQ_GPT_MDA_REQ_TTYPE (0X0)
1571
1572/* ====================================================================================================
1573 DMAREQ Module Register BitPositions, Lengths, Masks and Enumerations Definitions
1574 ==================================================================================================== */
1575
1576/* ----------------------------------------------------------------------------------------------------
1577 REQEN Value Description
1578 ---------------------------------------------------------------------------------------------------- */
1579#define BITP_DMAREQ_REQEN_GPLA_DMA_EN0 (0U) /* GPT/GPT32 and PLA DMA Request 0 Enable */
1580#define BITL_DMAREQ_REQEN_GPLA_DMA_EN0 (1U) /* GPT/GPT32 and PLA DMA Request 0 Enable */
1581#define BITM_DMAREQ_REQEN_GPLA_DMA_EN0 (0X01U) /* GPT/GPT32 and PLA DMA Request 0 Enable */
1582#define BITP_DMAREQ_REQEN_GPLA_DMA_EN1 (1U) /* GPT/GPT32 and PLA DMA Request 1 Enable */
1583#define BITL_DMAREQ_REQEN_GPLA_DMA_EN1 (1U) /* GPT/GPT32 and PLA DMA Request 1 Enable */
1584#define BITM_DMAREQ_REQEN_GPLA_DMA_EN1 (0X02U) /* GPT/GPT32 and PLA DMA Request 1 Enable */
1585
1586/* ----------------------------------------------------------------------------------------------------
1587 REQ0SEL Value Description
1588 ---------------------------------------------------------------------------------------------------- */
1589#define BITP_DMAREQ_REQ0SEL_DMA_REQ0_SEL (0U) /* GPT/GPT32 and PLA DMA Request 0 Source Select */
1590#define BITL_DMAREQ_REQ0SEL_DMA_REQ0_SEL (4U) /* GPT/GPT32 and PLA DMA Request 0 Source Select */
1591#define BITM_DMAREQ_REQ0SEL_DMA_REQ0_SEL (0X0FU) /* GPT/GPT32 and PLA DMA Request 0 Source Select */
1592
1593#define ENUM_DMAREQ_REQ0SEL_DMA_REQ0_SEL_PLA_REQ0 (0X00U) /* PLA DMA Request 0 */
1594#define ENUM_DMAREQ_REQ0SEL_DMA_REQ0_SEL_PLA_REQ1 (0X01U) /* PLA DMA Request 1 */
1595#define ENUM_DMAREQ_REQ0SEL_DMA_REQ0_SEL_PLA_REQ2 (0X02U) /* PLA DMA Request 2 */
1596#define ENUM_DMAREQ_REQ0SEL_DMA_REQ0_SEL_PLA_REQ3 (0X03U) /* PLA DMA Request 3 */
1597#define ENUM_DMAREQ_REQ0SEL_DMA_REQ0_SEL_GPT_REQ0 (0X04U) /* GPT 0 DMA Request */
1598#define ENUM_DMAREQ_REQ0SEL_DMA_REQ0_SEL_GPT_REQ1 (0X05U) /* GPT 1 DMA Request */
1599#define ENUM_DMAREQ_REQ0SEL_DMA_REQ0_SEL_GPT_REQ2 (0X06U) /* GPT 2 DMA Request */
1600#define ENUM_DMAREQ_REQ0SEL_DMA_REQ0_SEL_GPT32_REQ0 (0X07U) /* GPT32 0 DMA Request */
1601#define ENUM_DMAREQ_REQ0SEL_DMA_REQ0_SEL_GPT32_REQ1 (0X08U) /* GPT32 1 DMA Request */
1602
1603/* ----------------------------------------------------------------------------------------------------
1604 REQ1SEL Value Description
1605 ---------------------------------------------------------------------------------------------------- */
1606#define BITP_DMAREQ_REQ1SEL_DMA_REQ1_SEL (0U) /* GPT/GPT32 and PLA DMA Request 1 Source Select */
1607#define BITL_DMAREQ_REQ1SEL_DMA_REQ1_SEL (4U) /* GPT/GPT32 and PLA DMA Request 1 Source Select */
1608#define BITM_DMAREQ_REQ1SEL_DMA_REQ1_SEL (0X0FU) /* GPT/GPT32 and PLA DMA Request 1 Source Select */
1609
1610#define ENUM_DMAREQ_REQ1SEL_DMA_REQ1_SEL_PLA_REQ0 (0X00U) /* PLA DMA Request 0 */
1611#define ENUM_DMAREQ_REQ1SEL_DMA_REQ1_SEL_PLA_REQ1 (0X01U) /* PLA DMA Request 1 */
1612#define ENUM_DMAREQ_REQ1SEL_DMA_REQ1_SEL_PLA_REQ2 (0X02U) /* PLA DMA Request 2 */
1613#define ENUM_DMAREQ_REQ1SEL_DMA_REQ1_SEL_PLA_REQ3 (0X03U) /* PLA DMA Request 3 */
1614#define ENUM_DMAREQ_REQ1SEL_DMA_REQ1_SEL_GPT_REQ0 (0X04U) /* GPT 0 DMA Request */
1615#define ENUM_DMAREQ_REQ1SEL_DMA_REQ1_SEL_GPT_REQ1 (0X05U) /* GPT 1 DMA Request */
1616#define ENUM_DMAREQ_REQ1SEL_DMA_REQ1_SEL_GPT_REQ2 (0X06U) /* GPT 2 DMA Request */
1617#define ENUM_DMAREQ_REQ1SEL_DMA_REQ1_SEL_GPT32_REQ0 (0X07U) /* GPT32 0 DMA Request */
1618#define ENUM_DMAREQ_REQ1SEL_DMA_REQ1_SEL_GPT32_REQ1 (0X08U) /* GPT32 1 DMA Request */
1619
1620/* ----------------------------------------------------------------------------------------------------
1621 PLAREQEN Value Description
1622 ---------------------------------------------------------------------------------------------------- */
1623#define BITP_DMAREQ_PLAREQEN_PLA_DMA_REQ0_EN (0U) /* PLA DMA Request 0 Enable */
1624#define BITL_DMAREQ_PLAREQEN_PLA_DMA_REQ0_EN (1U) /* PLA DMA Request 0 Enable */
1625#define BITM_DMAREQ_PLAREQEN_PLA_DMA_REQ0_EN (0X01U) /* PLA DMA Request 0 Enable */
1626#define BITP_DMAREQ_PLAREQEN_PLA_DMA_REQ1_EN (1U) /* PLA DMA Request 1 Enable */
1627#define BITL_DMAREQ_PLAREQEN_PLA_DMA_REQ1_EN (1U) /* PLA DMA Request 1 Enable */
1628#define BITM_DMAREQ_PLAREQEN_PLA_DMA_REQ1_EN (0X02U) /* PLA DMA Request 1 Enable */
1629#define BITP_DMAREQ_PLAREQEN_PLA_DMA_REQ2_EN (2U) /* PLA DMA Request 2 Enable */
1630#define BITL_DMAREQ_PLAREQEN_PLA_DMA_REQ2_EN (1U) /* PLA DMA Request 2 Enable */
1631#define BITM_DMAREQ_PLAREQEN_PLA_DMA_REQ2_EN (0X04U) /* PLA DMA Request 2 Enable */
1632#define BITP_DMAREQ_PLAREQEN_PLA_DMA_REQ3_EN (3U) /* PLA DMA Request 3 Enable */
1633#define BITL_DMAREQ_PLAREQEN_PLA_DMA_REQ3_EN (1U) /* PLA DMA Request 3 Enable */
1634#define BITM_DMAREQ_PLAREQEN_PLA_DMA_REQ3_EN (0X08U) /* PLA DMA Request 3 Enable */
1635
1636/* ----------------------------------------------------------------------------------------------------
1637 GPTREQEN Value Description
1638 ---------------------------------------------------------------------------------------------------- */
1639#define BITP_DMAREQ_GPTREQEN_GPT_DMA_REQ0_EN (0U) /* GPT 0 DMA Request Enable */
1640#define BITL_DMAREQ_GPTREQEN_GPT_DMA_REQ0_EN (1U) /* GPT 0 DMA Request Enable */
1641#define BITM_DMAREQ_GPTREQEN_GPT_DMA_REQ0_EN (0X01U) /* GPT 0 DMA Request Enable */
1642#define BITP_DMAREQ_GPTREQEN_GPT_DMA_REQ1_EN (1U) /* GPT 1 DMA Request Enable */
1643#define BITL_DMAREQ_GPTREQEN_GPT_DMA_REQ1_EN (1U) /* GPT 1 DMA Request Enable */
1644#define BITM_DMAREQ_GPTREQEN_GPT_DMA_REQ1_EN (0X02U) /* GPT 1 DMA Request Enable */
1645#define BITP_DMAREQ_GPTREQEN_GPT_DMA_REQ2_EN (2U) /* GPT 2 DMA Request Enable */
1646#define BITL_DMAREQ_GPTREQEN_GPT_DMA_REQ2_EN (1U) /* GPT 2 DMA Request Enable */
1647#define BITM_DMAREQ_GPTREQEN_GPT_DMA_REQ2_EN (0X04U) /* GPT 2 DMA Request Enable */
1648#define BITP_DMAREQ_GPTREQEN_GPT32_DMA_REQ0_EN (3U) /* GPT32 0 DMA Request Enable */
1649#define BITL_DMAREQ_GPTREQEN_GPT32_DMA_REQ0_EN (1U) /* GPT32 0 DMA Request Enable */
1650#define BITM_DMAREQ_GPTREQEN_GPT32_DMA_REQ0_EN (0X08U) /* GPT32 0 DMA Request Enable */
1651#define BITP_DMAREQ_GPTREQEN_GPT32_DMA_REQ1_EN (4U) /* GPT32 1 DMA Request Enable */
1652#define BITL_DMAREQ_GPTREQEN_GPT32_DMA_REQ1_EN (1U) /* GPT32 1 DMA Request Enable */
1653#define BITM_DMAREQ_GPTREQEN_GPT32_DMA_REQ1_EN (0X10U) /* GPT32 1 DMA Request Enable */
1654
1655/* ----------------------------------------------------------------------------------------------------
1656 GPT_MDA_REQ_TTYPE Value Description
1657 ---------------------------------------------------------------------------------------------------- */
1658#define BITP_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ0_TYPE (0U) /* GPT Req0 DMA Require Type */
1659#define BITL_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ0_TYPE (2U) /* GPT Req0 DMA Require Type */
1660#define BITM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ0_TYPE (0X0003U) /* GPT Req0 DMA Require Type */
1661#define BITP_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ1_TYPE (2U) /* GPT Req1 DMA Require Type */
1662#define BITL_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ1_TYPE (2U) /* GPT Req1 DMA Require Type */
1663#define BITM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ1_TYPE (0X000CU) /* GPT Req1 DMA Require Type */
1664#define BITP_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ2_TYPE (4U) /* GPT Req2 DMA Require Type */
1665#define BITL_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ2_TYPE (2U) /* GPT Req2 DMA Require Type */
1666#define BITM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ2_TYPE (0X0030U) /* GPT Req2 DMA Require Type */
1667#define BITP_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ0_TYPE (6U) /* GPT32 Req0 DMA Require Type */
1668#define BITL_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ0_TYPE (2U) /* GPT32 Req0 DMA Require Type */
1669#define BITM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ0_TYPE (0X00C0U) /* GPT32 Req0 DMA Require Type */
1670#define BITP_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ1_TYPE (8U) /* GPT32 Req1 DMA Require Type */
1671#define BITL_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ1_TYPE (2U) /* GPT32 Req1 DMA Require Type */
1672#define BITM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ1_TYPE (0X0300U) /* GPT32 Req1 DMA Require Type */
1673
1674#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ1_TYPE_HIGH_LEVEL (0X0000U) /* High Level Trigger Interrupt and High Level Trigger DMA Request */
1675#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ1_TYPE_RISING_EDGE (0X0001U) /* Rising Edge Trigger Interrupt and Rising Edge Trigger DMA Request */
1676#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ1_TYPE_LOW_LEVEL (0X0002U) /* Low Level Trigger Interrupt and Low Level Trigger DMA Request */
1677#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ1_TYPE_FALLING_EDGE (0X0003U) /* Falling Edge Trigger Interrupt and Falling Edge Trigger DMA Request */
1678#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ0_TYPE_HIGH_LEVEL (0X0000U) /* High Level Trigger Interrupt and High Level Trigger DMA Request */
1679#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ0_TYPE_RISING_EDGE (0X0001U) /* Rising Edge Trigger Interrupt and Rising Edge Trigger DMA Request */
1680#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ0_TYPE_LOW_LEVEL (0X0002U) /* Low Level Trigger Interrupt and Low Level Trigger DMA Request */
1681#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT32_REQ0_TYPE_FALLING_EDGE (0X0003U) /* Falling Edge Trigger Interrupt and Falling Edge Trigger DMA Request */
1682#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ2_TYPE_HIGH_LEVEL (0X0000U) /* High Level Trigger Interrupt and High Level Trigger DMA Request */
1683#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ2_TYPE_RISING_EDGE (0X0001U) /* Rising Edge Trigger Interrupt and Rising Edge Trigger DMA Request */
1684#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ2_TYPE_LOW_LEVEL (0X0002U) /* Low Level Trigger Interrupt and Low Level Trigger DMA Request */
1685#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ2_TYPE_FALLING_EDGE (0X0003U) /* Falling Edge Trigger Interrupt and Falling Edge Trigger DMA Request */
1686#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ1_TYPE_HIGH_LEVEL (0X0000U) /* High Level Trigger Interrupt and High Level Trigger DMA Request */
1687#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ1_TYPE_RISING_EDGE (0X0001U) /* Rising Edge Trigger Interrupt and Rising Edge Trigger DMA Request */
1688#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ1_TYPE_LOW_LEVEL (0X0002U) /* Low Level Trigger Interrupt and Low Level Trigger DMA Request */
1689#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ1_TYPE_FALLING_EDGE (0X0003U) /* Falling Edge Trigger Interrupt and Falling Edge Trigger DMA Request */
1690#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ0_TYPE_HIGH_LEVEL (0X0000U) /* High Level Trigger Interrupt and High Level Trigger DMA Request */
1691#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ0_TYPE_RISING_EDGE (0X0001U) /* Rising Edge Trigger Interrupt and Rising Edge Trigger DMA Request */
1692#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ0_TYPE_LOW_LEVEL (0X0002U) /* Low Level Trigger Interrupt and Low Level Trigger DMA Request */
1693#define ENUM_DMAREQ_GPT_MDA_REQ_TTYPE_GPT_REQ0_TYPE_FALLING_EDGE (0X0003U) /* Falling Edge Trigger Interrupt and Falling Edge Trigger DMA Request */
1694
1695#endif /* end ifndef DMAREQ_ADDR_RDEF_H_ */
1696
1697
1698#ifndef UART_ADDR_RDEF_H_
1699#define UART_ADDR_RDEF_H_ /* UART: Universal Asynchronous Receiver/Transmitter */
1700
1701/* ====================================================================================================
1702 UART Module Instances Address and Mask Definitions
1703 ==================================================================================================== */
1704#define INST_UART0 (0X40020000U) /* uart0: */
1705#define INST_UART1 (0X40020400U) /* uart1: */
1706
1707#define MASK_UART (0X000000FFU) /* UART: Universal Asynchronous Receiver/Transmitter */
1708
1709/* ====================================================================================================
1710 UART Module Register Address Offset Definitions
1711 ==================================================================================================== */
1712#define IDX_UART_RX (0X00U) /* Receive/transfer Buffer Register */
1713#define IDX_UART_IEN (0X04U) /* Interrupt Enable */
1714#define IDX_UART_IIR (0X08U) /* Interrupt ID */
1715#define IDX_UART_LCR (0X0CU) /* Line Control */
1716#define IDX_UART_MCR (0X10U) /* Modem Control */
1717#define IDX_UART_LSR (0X14U) /* Line Status */
1718#define IDX_UART_MSR (0X18U) /* Modem Status */
1719#define IDX_UART_SCR (0X1CU) /* Scratch Buffer */
1720#define IDX_UART_FCR (0X20U) /* FIFO Control */
1721#define IDX_UART_FBR (0X24U) /* Fractional Baud Rate */
1722#define IDX_UART_DIV (0X28U) /* Baudrate Divider */
1723#define IDX_UART_LCR2 (0X2CU) /* Second Line Control */
1724#define IDX_UART_CTL (0X30U) /* UART Control Register */
1725#define IDX_UART_RFC (0X34U) /* RX FIFO Byte Count */
1726#define IDX_UART_TFC (0X38U) /* TX FIFO Byte Count */
1727#define IDX_UART_RSC (0X3CU) /* RS485 Half-duplex Control */
1728#define IDX_UART_ACR (0X40U) /* Auto Baud Control */
1729#define IDX_UART_ASRL (0X44U) /* Auto Baud Status (Low) */
1730#define IDX_UART_ASRH (0X48U) /* Auto Baud Status (High) */
1731
1732/* ====================================================================================================
1733 UART Module Register ResetValue Definitions
1734 ==================================================================================================== */
1735#define RSTVAL_UART_RX (0X0)
1736#define RSTVAL_UART_IEN (0X0)
1737#define RSTVAL_UART_IIR (0X1)
1738#define RSTVAL_UART_LCR (0X0)
1739#define RSTVAL_UART_MCR (0X0)
1740#define RSTVAL_UART_LSR (0X60)
1741#define RSTVAL_UART_SCR (0X0)
1742#define RSTVAL_UART_FCR (0X0)
1743#define RSTVAL_UART_FBR (0X0)
1744#define RSTVAL_UART_DIV (0X0)
1745#define RSTVAL_UART_LCR2 (0X2)
1746#define RSTVAL_UART_CTL (0X100)
1747#define RSTVAL_UART_RFC (0X0)
1748#define RSTVAL_UART_TFC (0X0)
1749#define RSTVAL_UART_RSC (0X0)
1750#define RSTVAL_UART_ACR (0X0)
1751#define RSTVAL_UART_ASRL (0X0)
1752#define RSTVAL_UART_ASRH (0X0)
1753
1754/* ====================================================================================================
1755 UART Module Register BitPositions, Lengths, Masks and Enumerations Definitions
1756 ==================================================================================================== */
1757
1758/* ----------------------------------------------------------------------------------------------------
1759 RX Value Description
1760 ---------------------------------------------------------------------------------------------------- */
1761#define BITP_UART_RX_RBR (0U) /* Receive Buffer Register */
1762#define BITL_UART_RX_RBR (8U) /* Receive Buffer Register */
1763#define BITM_UART_RX_RBR (0X00FFU) /* Receive Buffer Register */
1764
1765/* ----------------------------------------------------------------------------------------------------
1766 IEN Value Description
1767 ---------------------------------------------------------------------------------------------------- */
1768#define BITP_UART_IEN_ERBFI (0U) /* Receive Buffer Full Interrupt */
1769#define BITL_UART_IEN_ERBFI (1U) /* Receive Buffer Full Interrupt */
1770#define BITM_UART_IEN_ERBFI (0X0001U) /* Receive Buffer Full Interrupt */
1771#define BITP_UART_IEN_ETBEI (1U) /* Transmit Buffer Empty Interrupt */
1772#define BITL_UART_IEN_ETBEI (1U) /* Transmit Buffer Empty Interrupt */
1773#define BITM_UART_IEN_ETBEI (0X0002U) /* Transmit Buffer Empty Interrupt */
1774#define BITP_UART_IEN_ELSI (2U) /* Rx Status Interrupt */
1775#define BITL_UART_IEN_ELSI (1U) /* Rx Status Interrupt */
1776#define BITM_UART_IEN_ELSI (0X0004U) /* Rx Status Interrupt */
1777#define BITP_UART_IEN_EDSSI (3U) /* Modem Status Interrupt */
1778#define BITL_UART_IEN_EDSSI (1U) /* Modem Status Interrupt */
1779#define BITM_UART_IEN_EDSSI (0X0008U) /* Modem Status Interrupt */
1780#define BITP_UART_IEN_EDMAT (4U) /* DMA Requests in Transmit Mode */
1781#define BITL_UART_IEN_EDMAT (1U) /* DMA Requests in Transmit Mode */
1782#define BITM_UART_IEN_EDMAT (0X0010U) /* DMA Requests in Transmit Mode */
1783#define BITP_UART_IEN_EDMAR (5U) /* DMA Requests in Receive Mode */
1784#define BITL_UART_IEN_EDMAR (1U) /* DMA Requests in Receive Mode */
1785#define BITM_UART_IEN_EDMAR (0X0020U) /* DMA Requests in Receive Mode */
1786
1787#define ENUM_UART_IEN_EDMAR_DIS (0X0000U) /* DMA Requests Disabled */
1788#define ENUM_UART_IEN_EDMAR_EN (0X0001U) /* DMA Requests Enabled */
1789#define ENUM_UART_IEN_EDMAT_DIS (0X0000U) /* DMA Requests are Disabled */
1790#define ENUM_UART_IEN_EDMAT_EN (0X0001U) /* DMA Requests are Enabled */
1791#define ENUM_UART_IEN_EDSSI_DIS (0X0000U) /* Interrupt Disabled */
1792#define ENUM_UART_IEN_EDSSI_EN (0X0001U) /* Interrupt Enabled */
1793#define ENUM_UART_IEN_ELSI_DIS (0X0000U) /* Interrupt Disabled */
1794#define ENUM_UART_IEN_ELSI_EN (0X0001U) /* Interrupt Enabled */
1795#define ENUM_UART_IEN_ETBEI_DIS (0X0000U) /* Interrupt Disabled */
1796#define ENUM_UART_IEN_ETBEI_EN (0X0001U) /* Interrupt Enabled */
1797#define ENUM_UART_IEN_ERBFI_DIS (0X0000U) /* Interrupt Disabled */
1798#define ENUM_UART_IEN_ERBFI_EN (0X0001U) /* Interrupt Enabled */
1799
1800/* ----------------------------------------------------------------------------------------------------
1801 IIR Value Description
1802 ---------------------------------------------------------------------------------------------------- */
1803#define BITP_UART_IIR_NIRQ (0U) /* Interrupt Flag */
1804#define BITL_UART_IIR_NIRQ (1U) /* Interrupt Flag */
1805#define BITM_UART_IIR_NIRQ (0X0001U) /* Interrupt Flag */
1806#define BITP_UART_IIR_STAT (1U) /* Interrupt Status */
1807#define BITL_UART_IIR_STAT (3U) /* Interrupt Status */
1808#define BITM_UART_IIR_STAT (0X000EU) /* Interrupt Status */
1809#define BITP_UART_IIR_FEND (6U) /* FIFO Enabled */
1810#define BITL_UART_IIR_FEND (2U) /* FIFO Enabled */
1811#define BITM_UART_IIR_FEND (0X00C0U) /* FIFO Enabled */
1812
1813#define ENUM_UART_IIR_FEND_DIS (0X0000U) /* FIFO Not Enabled, 16450 Mode */
1814#define ENUM_UART_IIR_FEND_EN (0X0003U) /* FIFO Enabled, 16550 Mode */
1815#define ENUM_UART_IIR_STAT_MODEMINT (0X0000U) /* Modem Status Interrupt (Read MSR Register to Clear) */
1816#define ENUM_UART_IIR_STAT_TXEMPTYINT (0X0001U) /* Transmit Buffer Empty Interrupt (Write to Tx Register or Read IIR Register to Clear) */
1817#define ENUM_UART_IIR_STAT_RXFULLINT (0X0002U) /* Receive Buffer Full Interrupt (Read Rx Register to Clear) */
1818#define ENUM_UART_IIR_STAT_RXTIMEOUTINT (0X0006U) /* Receive FIFO Time-out Interrupt (Read Rx Register to Clear) */
1819#define ENUM_UART_IIR_STAT_RXLINEINT (0X0003U) /* Receive Line Status Interrupt (Read LSR Register to Clear) */
1820
1821/* ----------------------------------------------------------------------------------------------------
1822 LCR Value Description
1823 ---------------------------------------------------------------------------------------------------- */
1824#define BITP_UART_LCR_WLS (0U) /* Word Length Select */
1825#define BITL_UART_LCR_WLS (2U) /* Word Length Select */
1826#define BITM_UART_LCR_WLS (0X0003U) /* Word Length Select */
1827#define BITP_UART_LCR_STOPPED (2U) /* Stop Bit */
1828#define BITL_UART_LCR_STOPPED (1U) /* Stop Bit */
1829#define BITM_UART_LCR_STOPPED (0X0004U) /* Stop Bit */
1830#define BITP_UART_LCR_PEN (3U) /* Parity Enable */
1831#define BITL_UART_LCR_PEN (1U) /* Parity Enable */
1832#define BITM_UART_LCR_PEN (0X0008U) /* Parity Enable */
1833#define BITP_UART_LCR_EPS (4U) /* Parity Select */
1834#define BITL_UART_LCR_EPS (1U) /* Parity Select */
1835#define BITM_UART_LCR_EPS (0X0010U) /* Parity Select */
1836#define BITP_UART_LCR_SP (5U) /* Stick Parity */
1837#define BITL_UART_LCR_SP (1U) /* Stick Parity */
1838#define BITM_UART_LCR_SP (0X0020U) /* Stick Parity */
1839#define BITP_UART_LCR_BRK (6U) /* Set Break */
1840#define BITL_UART_LCR_BRK (1U) /* Set Break */
1841#define BITM_UART_LCR_BRK (0X0040U) /* Set Break */
1842
1843#define ENUM_UART_LCR_SP_STICK (0X0000U) /* Parity Will Not Be Forced Based on Parity Select and Parity Enable Bits. */
1844#define ENUM_UART_LCR_SP_EPSPEN (0X0001U) /* Parity Forced Based on Parity Select and Parity Enable Bits. */
1845#define ENUM_UART_LCR_EPS_ODD (0X0000U) /* Odd Parity Will Be Transmitted and Checked. */
1846#define ENUM_UART_LCR_EPS_EVEN (0X0001U) /* Even Parity Will Be Transmitted and Checked. */
1847#define ENUM_UART_LCR_PEN_DIS (0X0000U) /* Parity Will Not Be Transmitted or Checked. */
1848#define ENUM_UART_LCR_PEN_EN (0X0001U) /* Parity Will Be Transmitted and Checked. */
1849#define ENUM_UART_LCR_STOPPED_ONTBIT (0X0000U) /* Send 1 Stop Bit Regardless of the Word Length Select Bit */
1850#define ENUM_UART_LCR_STOPPED_MULTIBIT (0X0001U) /* Send a Number of Stop Bits Based on the Word Length as Follows: WLS = 00, 1.5 Stop Bits Transmitted (5-bit Word Length) WLS = 01 or 10 or 11, 2 Stop Bits Transmitted (6 or 7 or 8-bit Word Length) */
1851#define ENUM_UART_LCR_WLS_BITS5 (0X0000U) /* 5 Bits */
1852#define ENUM_UART_LCR_WLS_BITS6 (0X0001U) /* 6 Bits */
1853#define ENUM_UART_LCR_WLS_BITS7 (0X0002U) /* 7 Bits */
1854#define ENUM_UART_LCR_WLS_BITS8 (0X0003U) /* 8 Bits */
1855
1856/* ----------------------------------------------------------------------------------------------------
1857 MCR Value Description
1858 ---------------------------------------------------------------------------------------------------- */
1859#define BITP_UART_MCR_DTR (0U) /* Data Terminal Ready */
1860#define BITL_UART_MCR_DTR (1U) /* Data Terminal Ready */
1861#define BITM_UART_MCR_DTR (0X0001U) /* Data Terminal Ready */
1862#define BITP_UART_MCR_RTS (1U) /* Request to Send */
1863#define BITL_UART_MCR_RTS (1U) /* Request to Send */
1864#define BITM_UART_MCR_RTS (0X0002U) /* Request to Send */
1865#define BITP_UART_MCR_OUT1 (2U) /* Output 1 */
1866#define BITL_UART_MCR_OUT1 (1U) /* Output 1 */
1867#define BITM_UART_MCR_OUT1 (0X0004U) /* Output 1 */
1868#define BITP_UART_MCR_OUT2 (3U) /* Output 2 */
1869#define BITL_UART_MCR_OUT2 (1U) /* Output 2 */
1870#define BITM_UART_MCR_OUT2 (0X0008U) /* Output 2 */
1871#define BITP_UART_MCR_LOOPBACK (4U) /* Loop Back Mode */
1872#define BITL_UART_MCR_LOOPBACK (1U) /* Loop Back Mode */
1873#define BITM_UART_MCR_LOOPBACK (0X0010U) /* Loop Back Mode */
1874
1875#define ENUM_UART_MCR_LOOPBACK_DIS (0X0000U) /* Normal Operation - Loopback Disabled */
1876#define ENUM_UART_MCR_LOOPBACK_EN (0X0001U) /* Loopback Enabled */
1877#define ENUM_UART_MCR_OUT2_FORCE1 (0X0000U) /* Force NOUT2 to a Logic 1 */
1878#define ENUM_UART_MCR_OUT2_FORCE0 (0X0001U) /* Force NOUT2 to a Logic 0 */
1879#define ENUM_UART_MCR_OUT1_FORCE1 (0X0000U) /* Force NOUT1 to a Logic 1 */
1880#define ENUM_UART_MCR_OUT1_FORCE0 (0X0001U) /* Force NOUT1 to a Logic 0 */
1881#define ENUM_UART_MCR_RTS_FORCE1 (0X0000U) /* Force NRTS to a Logic 1 */
1882#define ENUM_UART_MCR_RTS_FORCE0 (0X0001U) /* Force NRTS to a Logic 0 */
1883#define ENUM_UART_MCR_DTR_FORCE1 (0X0000U) /* Force NDTR to a Logic 1 */
1884#define ENUM_UART_MCR_DTR_FORCE0 (0X0001U) /* Force NDTR to a Logic 0 */
1885
1886/* ----------------------------------------------------------------------------------------------------
1887 LSR Value Description
1888 ---------------------------------------------------------------------------------------------------- */
1889#define BITP_UART_LSR_DR (0U) /* Data Ready */
1890#define BITL_UART_LSR_DR (1U) /* Data Ready */
1891#define BITM_UART_LSR_DR (0X0001U) /* Data Ready */
1892#define BITP_UART_LSR_OE (1U) /* Overrun Error */
1893#define BITL_UART_LSR_OE (1U) /* Overrun Error */
1894#define BITM_UART_LSR_OE (0X0002U) /* Overrun Error */
1895#define BITP_UART_LSR_PE (2U) /* Parity Error */
1896#define BITL_UART_LSR_PE (1U) /* Parity Error */
1897#define BITM_UART_LSR_PE (0X0004U) /* Parity Error */
1898#define BITP_UART_LSR_FE (3U) /* Framing Error */
1899#define BITL_UART_LSR_FE (1U) /* Framing Error */
1900#define BITM_UART_LSR_FE (0X0008U) /* Framing Error */
1901#define BITP_UART_LSR_BI (4U) /* Break Indicator */
1902#define BITL_UART_LSR_BI (1U) /* Break Indicator */
1903#define BITM_UART_LSR_BI (0X0010U) /* Break Indicator */
1904#define BITP_UART_LSR_THRE (5U) /* Transmit Register Empty */
1905#define BITL_UART_LSR_THRE (1U) /* Transmit Register Empty */
1906#define BITM_UART_LSR_THRE (0X0020U) /* Transmit Register Empty */
1907#define BITP_UART_LSR_TEMT (6U) /* Transmit and Shift Register Empty Status */
1908#define BITL_UART_LSR_TEMT (1U) /* Transmit and Shift Register Empty Status */
1909#define BITM_UART_LSR_TEMT (0X0040U) /* Transmit and Shift Register Empty Status */
1910#define BITP_UART_LSR_FIFOERR (7U) /* FIFO Error */
1911#define BITL_UART_LSR_FIFOERR (1U) /* FIFO Error */
1912#define BITM_UART_LSR_FIFOERR (0X0080U) /* FIFO Error */
1913
1914#define ENUM_UART_LSR_TEMT_NOTEMPTY (0X0000U) /* Tx Register Has Been Written to and Contains Data to Be Transmitted. Care Should Be Taken Not to Overwrite Its Value. */
1915#define ENUM_UART_LSR_TEMT_EMPTY (0X0001U) /* Tx Register and the Transmit Shift Register are Empty and It is Safe to Write New Data to the Tx Register. Data Has Been Transmitted. */
1916#define ENUM_UART_LSR_THRE_NOTEMPTY (0X0000U) /* Tx Register Has Been Written to and Contains Data to Be Transmitted. Care Should Be Taken Not to Overwrite Its Value. */
1917#define ENUM_UART_LSR_THRE_EMPTY (0X0001U) /* Tx Register is Empty and It is Safe to Write New Data to Tx Register the Previous Data May Not Have Been Transmitted Yet and Can Still Be Present in the Shift Register. */
1918#define ENUM_UART_LSR_FE_OKAY (0X0000U) /* No Invalid Stop Bit Was Detected. */
1919#define ENUM_UART_LSR_FE_INVALIDSTOP (0X0001U) /* An Invalid Stop Bit Was Detected on a Received Word. */
1920#define ENUM_UART_LSR_PE_NOERR (0X0000U) /* No Parity Error Was Detected. */
1921#define ENUM_UART_LSR_PE_ERRORS (0X0001U) /* A Parity Error Occurred on a Received Word. */
1922#define ENUM_UART_LSR_OE_OKAY (0X0000U) /* Receive Data Has Not Been Overwritten. */
1923#define ENUM_UART_LSR_OE_OVERWRITTEN (0X0001U) /* Receive Data Was Overwritten by New Data Before Rx Register Was Read. */
1924#define ENUM_UART_LSR_DR_NOTREADY (0X0000U) /* Rx Register Does Not Contain New Receive Data. */
1925#define ENUM_UART_LSR_DR_READY (0X0001U) /* Rx Register Contains Receive Data That Should Be Read. */
1926
1927/* ----------------------------------------------------------------------------------------------------
1928 MSR Value Description
1929 ---------------------------------------------------------------------------------------------------- */
1930#define BITP_UART_MSR_DCTS (0U) /* Delta CTS */
1931#define BITL_UART_MSR_DCTS (1U) /* Delta CTS */
1932#define BITM_UART_MSR_DCTS (0X0001U) /* Delta CTS */
1933#define BITP_UART_MSR_DDSR (1U) /* Delta DSR */
1934#define BITL_UART_MSR_DDSR (1U) /* Delta DSR */
1935#define BITM_UART_MSR_DDSR (0X0002U) /* Delta DSR */
1936#define BITP_UART_MSR_TERI (2U) /* Trailing Edge RI */
1937#define BITL_UART_MSR_TERI (1U) /* Trailing Edge RI */
1938#define BITM_UART_MSR_TERI (0X0004U) /* Trailing Edge RI */
1939#define BITP_UART_MSR_DDCD (3U) /* Delta DCD */
1940#define BITL_UART_MSR_DDCD (1U) /* Delta DCD */
1941#define BITM_UART_MSR_DDCD (0X0008U) /* Delta DCD */
1942#define BITP_UART_MSR_CTS (4U) /* Clear to Send */
1943#define BITL_UART_MSR_CTS (1U) /* Clear to Send */
1944#define BITM_UART_MSR_CTS (0X0010U) /* Clear to Send */
1945#define BITP_UART_MSR_DSR (5U) /* Data Set Ready */
1946#define BITL_UART_MSR_DSR (1U) /* Data Set Ready */
1947#define BITM_UART_MSR_DSR (0X0020U) /* Data Set Ready */
1948#define BITP_UART_MSR_RI (6U) /* Ring Indicator */
1949#define BITL_UART_MSR_RI (1U) /* Ring Indicator */
1950#define BITM_UART_MSR_RI (0X0040U) /* Ring Indicator */
1951#define BITP_UART_MSR_DCD (7U) /* Data Carrier Detect */
1952#define BITL_UART_MSR_DCD (1U) /* Data Carrier Detect */
1953#define BITM_UART_MSR_DCD (0X0080U) /* Data Carrier Detect */
1954
1955#define ENUM_UART_MSR_DCD_HIGH (0X0000U) /* NDCD is Currently Logic High. */
1956#define ENUM_UART_MSR_DCD_LOW (0X0001U) /* NDCD is Currently Logic Low. */
1957#define ENUM_UART_MSR_RI_HIGH (0X0000U) /* NRI is Currently Logic High. */
1958#define ENUM_UART_MSR_RI_LOW (0X0001U) /* NRI is Currently Logic Low. */
1959#define ENUM_UART_MSR_DSR_HIGH (0X0000U) /* NDSR is Currently Logic High */
1960#define ENUM_UART_MSR_DSR_LOW (0X0001U) /* NDSR is Currently Logic Low */
1961#define ENUM_UART_MSR_CTS_HIGH (0X0000U) /* NCTS is Currently Logic High */
1962#define ENUM_UART_MSR_CTS_LOW (0X0001U) /* NCTS is Currently Logic Low */
1963#define ENUM_UART_MSR_DDCD_NOCHANGE (0X0000U) /* Data Carrier Detect Bit Has Not Changed State Since MSR Register Was Last Read */
1964#define ENUM_UART_MSR_DDCD_CHANGED (0X0001U) /* Data Carrier Detect Bit Changed State Since MSR Register Last Read */
1965#define ENUM_UART_MSR_TERI_NOTCHANGED (0X0000U) /* Ring Indicator Bit Has Not Changed from 0 to 1 Since MSR Register Last Read */
1966#define ENUM_UART_MSR_TERI_CHANGED (0X0001U) /* Ring Indicator Bit Changed from 0 to 1 Since MSR Register Last Read */
1967#define ENUM_UART_MSR_DDSR_NOCHANGE (0X0000U) /* Data Set Ready Bit Has Not Changed State Since MSR Register Was Last Read */
1968#define ENUM_UART_MSR_DDSR_CHANGED (0X0001U) /* Data Set Ready Bit Changed State Since MSR Register Last Read */
1969#define ENUM_UART_MSR_DCTS_NOCHANGE (0X0000U) /* Clear to Send Bit Has Not Changed State Since MSR Register Was Last Read */
1970#define ENUM_UART_MSR_DCTS_CHANGED (0X0001U) /* Clear to Send Bit Changed State Since MSR Register Last Read */
1971
1972/* ----------------------------------------------------------------------------------------------------
1973 SCR Value Description
1974 ---------------------------------------------------------------------------------------------------- */
1975#define BITP_UART_SCR_SCR (0U) /* Scratch */
1976#define BITL_UART_SCR_SCR (8U) /* Scratch */
1977#define BITM_UART_SCR_SCR (0X00FFU) /* Scratch */
1978
1979/* ----------------------------------------------------------------------------------------------------
1980 FCR Value Description
1981 ---------------------------------------------------------------------------------------------------- */
1982#define BITP_UART_FCR_FIFOEN (0U) /* FIFO Enable as to Work in 16550 Mode */
1983#define BITL_UART_FCR_FIFOEN (1U) /* FIFO Enable as to Work in 16550 Mode */
1984#define BITM_UART_FCR_FIFOEN (0X0001U) /* FIFO Enable as to Work in 16550 Mode */
1985#define BITP_UART_FCR_RFCLR (1U) /* Clear RX FIFO */
1986#define BITL_UART_FCR_RFCLR (1U) /* Clear RX FIFO */
1987#define BITM_UART_FCR_RFCLR (0X0002U) /* Clear RX FIFO */
1988#define BITP_UART_FCR_TFCLR (2U) /* Clear TX FIFO */
1989#define BITL_UART_FCR_TFCLR (1U) /* Clear TX FIFO */
1990#define BITM_UART_FCR_TFCLR (0X0004U) /* Clear TX FIFO */
1991#define BITP_UART_FCR_FDMAMD (3U) /* FIFO DMA Mode */
1992#define BITL_UART_FCR_FDMAMD (1U) /* FIFO DMA Mode */
1993#define BITM_UART_FCR_FDMAMD (0X0008U) /* FIFO DMA Mode */
1994#define BITP_UART_FCR_RFTRIG (6U) /* RX FIFO Trig Level */
1995#define BITL_UART_FCR_RFTRIG (2U) /* RX FIFO Trig Level */
1996#define BITM_UART_FCR_RFTRIG (0X00C0U) /* RX FIFO Trig Level */
1997
1998#define ENUM_UART_FCR_RFTRIG_BYTE1 (0X0000U) /* 1 Byte to Trig RX Interrupt */
1999#define ENUM_UART_FCR_RFTRIG_BYTE4 (0X0001U) /* 4 Byte to Trig RX Interrupt */
2000#define ENUM_UART_FCR_RFTRIG_BYTE8 (0X0002U) /* 8 Byte to Trig RX Interrupt */
2001#define ENUM_UART_FCR_RFTRIG_BYTE14 (0X0003U) /* 14 Byte to Trig RX Interrupt */
2002#define ENUM_UART_FCR_FDMAMD_MODE0 (0X0000U) /* In DMA Mode 0, RX DMA Request Will Be Asserted Whenever There's Data in RBR or RX FIFO and De-assert Whenever RBR or RX FIFO is Empty; TX DMA Request Will Be Asserted Whenever THR or TX FIFO is Empty and De-assert Whenever Data Written To. */
2003#define ENUM_UART_FCR_FDMAMD_MODE1 (0X0001U) /* In DMA Mode 1, RX DMA Request Will Be Asserted Whenever RX FIFO Trig Level or Time Out Reached and De-assert Thereafter When RX FIFO is Empty; TX DMA Request Will Be Asserted Whenever TX FIFO is Empty and De-assert Thereafter When TX FIFO is Completely Filled up Full. */
2004
2005/* ----------------------------------------------------------------------------------------------------
2006 FBR Value Description
2007 ---------------------------------------------------------------------------------------------------- */
2008#define BITP_UART_FBR_DIVN (0U) /* Fractional Baud Rate N Divide Bits 0 to 2047 */
2009#define BITL_UART_FBR_DIVN (11U) /* Fractional Baud Rate N Divide Bits 0 to 2047 */
2010#define BITM_UART_FBR_DIVN (0X07FFU) /* Fractional Baud Rate N Divide Bits 0 to 2047 */
2011#define BITP_UART_FBR_DIVM (11U) /* Fractional Baud Rate M Divide Bits 1 to 3 */
2012#define BITL_UART_FBR_DIVM (2U) /* Fractional Baud Rate M Divide Bits 1 to 3 */
2013#define BITM_UART_FBR_DIVM (0X1800U) /* Fractional Baud Rate M Divide Bits 1 to 3 */
2014#define BITP_UART_FBR_FBEN (15U) /* Fractional Baud Rate Generator Enable */
2015#define BITL_UART_FBR_FBEN (1U) /* Fractional Baud Rate Generator Enable */
2016#define BITM_UART_FBR_FBEN (0X8000U) /* Fractional Baud Rate Generator Enable */
2017
2018/* ----------------------------------------------------------------------------------------------------
2019 DIV Value Description
2020 ---------------------------------------------------------------------------------------------------- */
2021#define BITP_UART_DIV_DIV (0U) /* Baud Rate Divider */
2022#define BITL_UART_DIV_DIV (16U) /* Baud Rate Divider */
2023#define BITM_UART_DIV_DIV (0XFFFFU) /* Baud Rate Divider */
2024
2025/* ----------------------------------------------------------------------------------------------------
2026 LCR2 Value Description
2027 ---------------------------------------------------------------------------------------------------- */
2028#define BITP_UART_LCR2_OSR (0U) /* Over Sample Rate */
2029#define BITL_UART_LCR2_OSR (2U) /* Over Sample Rate */
2030#define BITM_UART_LCR2_OSR (0X0003U) /* Over Sample Rate */
2031
2032#define ENUM_UART_LCR2_OSR_OSR4 (0X0000U) /* Over Sample by 4 */
2033#define ENUM_UART_LCR2_OSR_OSR8 (0X0001U) /* Over Sample by 8 */
2034#define ENUM_UART_LCR2_OSR_OSR16 (0X0002U) /* Over Sample by 16 */
2035#define ENUM_UART_LCR2_OSR_OSR32 (0X0003U) /* Over Sample by 32 */
2036
2037/* ----------------------------------------------------------------------------------------------------
2038 CTL Value Description
2039 ---------------------------------------------------------------------------------------------------- */
2040#define BITP_UART_CTL_FORCECLK (1U) /* Force UCLK on */
2041#define BITL_UART_CTL_FORCECLK (1U) /* Force UCLK on */
2042#define BITM_UART_CTL_FORCECLK (0X0002U) /* Force UCLK on */
2043#define BITP_UART_CTL_RXINV (4U) /* Invert Receiver Line */
2044#define BITL_UART_CTL_RXINV (1U) /* Invert Receiver Line */
2045#define BITM_UART_CTL_RXINV (0X0010U) /* Invert Receiver Line */
2046#define BITP_UART_CTL_REV (8U) /* UART Revision ID */
2047#define BITL_UART_CTL_REV (8U) /* UART Revision ID */
2048#define BITM_UART_CTL_REV (0XFF00U) /* UART Revision ID */
2049
2050#define ENUM_UART_CTL_RXINV_EN000 (0X0000U) /* Don't Invert Receiver Line (idling High) */
2051#define ENUM_UART_CTL_RXINV_EN001 (0X0001U) /* Invert Receiver Line (idling Low) */
2052#define ENUM_UART_CTL_FORCECLK_GATEUCLK (0X0000U) /* UCLK Automatically Gated */
2053#define ENUM_UART_CTL_FORCECLK_UCLKEN (0X0001U) /* UCLK Always Working */
2054
2055/* ----------------------------------------------------------------------------------------------------
2056 RFC Value Description
2057 ---------------------------------------------------------------------------------------------------- */
2058#define BITP_UART_RFC_RFC (0U) /* Current RX FIFO Data Bytes */
2059#define BITL_UART_RFC_RFC (5U) /* Current RX FIFO Data Bytes */
2060#define BITM_UART_RFC_RFC (0X001FU) /* Current RX FIFO Data Bytes */
2061
2062/* ----------------------------------------------------------------------------------------------------
2063 TFC Value Description
2064 ---------------------------------------------------------------------------------------------------- */
2065#define BITP_UART_TFC_TFC (0U) /* Current TX FIFO Data Bytes */
2066#define BITL_UART_TFC_TFC (5U) /* Current TX FIFO Data Bytes */
2067#define BITM_UART_TFC_TFC (0X001FU) /* Current TX FIFO Data Bytes */
2068
2069/* ----------------------------------------------------------------------------------------------------
2070 RSC Value Description
2071 ---------------------------------------------------------------------------------------------------- */
2072#define BITP_UART_RSC_OENP (0U) /* SOUT_EN Polarity */
2073#define BITL_UART_RSC_OENP (1U) /* SOUT_EN Polarity */
2074#define BITM_UART_RSC_OENP (0X0001U) /* SOUT_EN Polarity */
2075#define BITP_UART_RSC_OENSP (1U) /* SOUT_EN De-assert Before Full Stop Bit(s) */
2076#define BITL_UART_RSC_OENSP (1U) /* SOUT_EN De-assert Before Full Stop Bit(s) */
2077#define BITM_UART_RSC_OENSP (0X0002U) /* SOUT_EN De-assert Before Full Stop Bit(s) */
2078#define BITP_UART_RSC_DISRX (2U) /* Disable RX When Transmitting */
2079#define BITL_UART_RSC_DISRX (1U) /* Disable RX When Transmitting */
2080#define BITM_UART_RSC_DISRX (0X0004U) /* Disable RX When Transmitting */
2081#define BITP_UART_RSC_DISTX (3U) /* Hold off TX When Receiving */
2082#define BITL_UART_RSC_DISTX (1U) /* Hold off TX When Receiving */
2083#define BITM_UART_RSC_DISTX (0X0008U) /* Hold off TX When Receiving */
2084
2085#define ENUM_UART_RSC_OENSP_FULLBIT (0X0000U) /* SOUT_EN De-assert Same Time as Full Stop Bit(s) */
2086#define ENUM_UART_RSC_OENSP_HALFBIT (0X0001U) /* SOUT_EN De-assert Half-bit Earlier Than Full Stop Bit(s) */
2087#define ENUM_UART_RSC_OENP_HIGHACTIVE (0X0000U) /* High Active */
2088#define ENUM_UART_RSC_OENP_LOWACTIVE (0X0001U) /* Low Active */
2089
2090/* ----------------------------------------------------------------------------------------------------
2091 ACR Value Description
2092 ---------------------------------------------------------------------------------------------------- */
2093#define BITP_UART_ACR_ABE (0U) /* Auto Baud Enable */
2094#define BITL_UART_ACR_ABE (1U) /* Auto Baud Enable */
2095#define BITM_UART_ACR_ABE (0X0001U) /* Auto Baud Enable */
2096#define BITP_UART_ACR_DNIEN (1U) /* Enable Done Interrupt */
2097#define BITL_UART_ACR_DNIEN (1U) /* Enable Done Interrupt */
2098#define BITM_UART_ACR_DNIEN (0X0002U) /* Enable Done Interrupt */
2099#define BITP_UART_ACR_TOIEN (2U) /* Enable Time-out Interrupt */
2100#define BITL_UART_ACR_TOIEN (1U) /* Enable Time-out Interrupt */
2101#define BITM_UART_ACR_TOIEN (0X0004U) /* Enable Time-out Interrupt */
2102#define BITP_UART_ACR_SEC (4U) /* Starting Edge Count */
2103#define BITL_UART_ACR_SEC (3U) /* Starting Edge Count */
2104#define BITM_UART_ACR_SEC (0X0070U) /* Starting Edge Count */
2105#define BITP_UART_ACR_EEC (8U) /* Ending Edge Count */
2106#define BITL_UART_ACR_EEC (4U) /* Ending Edge Count */
2107#define BITM_UART_ACR_EEC (0X0F00U) /* Ending Edge Count */
2108
2109#define ENUM_UART_ACR_EEC_FIRST (0X0000U) /* First Edge */
2110#define ENUM_UART_ACR_EEC_SECOND (0X0001U) /* Second Edge */
2111#define ENUM_UART_ACR_EEC_THIRD (0X0002U) /* Third Edge */
2112#define ENUM_UART_ACR_EEC_FOURTH (0X0003U) /* Fourth Edge */
2113#define ENUM_UART_ACR_EEC_FIFTH (0X0004U) /* Fifth Edge */
2114#define ENUM_UART_ACR_EEC_SIXTH (0X0005U) /* Sixth Edge */
2115#define ENUM_UART_ACR_EEC_SEVENTH (0X0006U) /* Seventh Edge */
2116#define ENUM_UART_ACR_EEC_EIGHTH (0X0007U) /* Eighth Edge */
2117#define ENUM_UART_ACR_EEC_NINTH (0X0008U) /* Ninth Edge */
2118#define ENUM_UART_ACR_SEC_FIRST (0X0000U) /* First Edge (always the Falling Edge of START Bit) */
2119#define ENUM_UART_ACR_SEC_SECOND (0X0001U) /* Second Edge */
2120#define ENUM_UART_ACR_SEC_THIRD (0X0002U) /* Third Edge */
2121#define ENUM_UART_ACR_SEC_FOURTH (0X0003U) /* Fourth Edge */
2122#define ENUM_UART_ACR_SEC_FIFTH (0X0004U) /* Fifth Edge */
2123#define ENUM_UART_ACR_SEC_SIXTH (0X0005U) /* Sixth Edge */
2124#define ENUM_UART_ACR_SEC_SEVENTH (0X0006U) /* Seventh Edge */
2125#define ENUM_UART_ACR_SEC_EIGHTH (0X0007U) /* Eighth Edge */
2126
2127/* ----------------------------------------------------------------------------------------------------
2128 ASRL Value Description
2129 ---------------------------------------------------------------------------------------------------- */
2130#define BITP_UART_ASRL_DONE (0U) /* Auto Baud Done Successfully */
2131#define BITL_UART_ASRL_DONE (1U) /* Auto Baud Done Successfully */
2132#define BITM_UART_ASRL_DONE (0X0001U) /* Auto Baud Done Successfully */
2133#define BITP_UART_ASRL_BRKTO (1U) /* Timed Out Due to Long Time Break Condition */
2134#define BITL_UART_ASRL_BRKTO (1U) /* Timed Out Due to Long Time Break Condition */
2135#define BITM_UART_ASRL_BRKTO (0X0002U) /* Timed Out Due to Long Time Break Condition */
2136#define BITP_UART_ASRL_NSETO (2U) /* Timed Out Due to No Valid Start Edge Found */
2137#define BITL_UART_ASRL_NSETO (1U) /* Timed Out Due to No Valid Start Edge Found */
2138#define BITM_UART_ASRL_NSETO (0X0004U) /* Timed Out Due to No Valid Start Edge Found */
2139#define BITP_UART_ASRL_NEETO (3U) /* Timed Out Due to No Valid Ending Edge Found */
2140#define BITL_UART_ASRL_NEETO (1U) /* Timed Out Due to No Valid Ending Edge Found */
2141#define BITM_UART_ASRL_NEETO (0X0008U) /* Timed Out Due to No Valid Ending Edge Found */
2142#define BITP_UART_ASRL_CNT (4U) /* Auto Baud Counter Value */
2143#define BITL_UART_ASRL_CNT (12U) /* Auto Baud Counter Value */
2144#define BITM_UART_ASRL_CNT (0XFFF0U) /* Auto Baud Counter Value */
2145
2146/* ----------------------------------------------------------------------------------------------------
2147 ASRH Value Description
2148 ---------------------------------------------------------------------------------------------------- */
2149#define BITP_UART_ASRH_CNT (0U) /* Auto Baud Counter Value */
2150#define BITL_UART_ASRH_CNT (8U) /* Auto Baud Counter Value */
2151#define BITM_UART_ASRH_CNT (0X00FFU) /* Auto Baud Counter Value */
2152
2153#endif /* end ifndef UART_ADDR_RDEF_H_ */
2154
2155
2156#ifndef I2C_ADDR_RDEF_H_
2157#define I2C_ADDR_RDEF_H_ /* I2C: I2C Master/Slave */
2158
2159/* ====================================================================================================
2160 I2C Module Instances Address and Mask Definitions
2161 ==================================================================================================== */
2162#define INST_I2C0 (0X40020800U) /* i2c0: */
2163#define INST_I2C1 (0X40020C00U) /* i2c1: */
2164#define INST_I2C2 (0X40021000U) /* i2c2: */
2165
2166#define MASK_I2C (0X0000007FU) /* I2C: I2C Master/Slave */
2167
2168/* ====================================================================================================
2169 I2C Module Register Address Offset Definitions
2170 ==================================================================================================== */
2171#define IDX_I2C_MCTL (0X00U) /* Master Control */
2172#define IDX_I2C_MSTAT (0X04U) /* Master Status */
2173#define IDX_I2C_MRX (0X08U) /* Master Receive Data */
2174#define IDX_I2C_MTX (0X0CU) /* Master Transmit Data */
2175#define IDX_I2C_MRXCNT (0X10U) /* Master Receive Data Count */
2176#define IDX_I2C_MCRXCNT (0X14U) /* Master Current Receive Data Count */
2177#define IDX_I2C_ADDR0 (0X18U) /* 1st Master Address Byte */
2178#define IDX_I2C_ADDR1 (0X1CU) /* 2nd Master Address Byte */
2179#define IDX_I2C_BYT (0X20U) /* Start Byte */
2180#define IDX_I2C_DIV (0X24U) /* Serial Clock Period Divisor */
2181#define IDX_I2C_SCTL (0X28U) /* Slave Control */
2182#define IDX_I2C_SSTAT (0X2CU) /* Slave I2C Status/Error/IRQ */
2183#define IDX_I2C_SRX (0X30U) /* Slave Receive */
2184#define IDX_I2C_STX (0X34U) /* Slave Transmit */
2185#define IDX_I2C_ALT (0X38U) /* Hardware General Call ID */
2186#define IDX_I2C_ID0 (0X3CU) /* 1st Slave Address Device ID */
2187#define IDX_I2C_ID1 (0X40U) /* 2nd Slave Address Device ID */
2188#define IDX_I2C_ID2 (0X44U) /* 3rd Slave Address Device ID */
2189#define IDX_I2C_ID3 (0X48U) /* 4th Slave Address Device ID */
2190#define IDX_I2C_STAT (0X4CU) /* Master and Slave FIFO Status */
2191#define IDX_I2C_SHCTL (0X50U) /* Shared Control */
2192#define IDX_I2C_TCTL (0X54U) /* Timing Control Register */
2193#define IDX_I2C_ASTRETCH_SCL (0X58U) /* Automatic Stretch SCL Register */
2194#define IDX_I2C_IDFSTA (0X5CU) /* ID FIFO Status Register */
2195#define IDX_I2C_SLV_ADDR1 (0X60U) /* Slave 10 Bits Address 1st Byte. */
2196#define IDX_I2C_SLV_ADDR2 (0X64U) /* Slave 10 Bits Address 2nd Byte. */
2197#define IDX_I2C_SSTAT2 (0X68U) /* Slave I2C Status/IRQ 2 */
2198
2199/* ====================================================================================================
2200 I2C Module Register ResetValue Definitions
2201 ==================================================================================================== */
2202#define RSTVAL_I2C_MCTL (0X0)
2203#define RSTVAL_I2C_MSTAT (0X6000)
2204#define RSTVAL_I2C_MRX (0X0)
2205#define RSTVAL_I2C_MTX (0X0)
2206#define RSTVAL_I2C_MRXCNT (0X0)
2207#define RSTVAL_I2C_MCRXCNT (0X0)
2208#define RSTVAL_I2C_ADDR0 (0X0)
2209#define RSTVAL_I2C_ADDR1 (0X0)
2210#define RSTVAL_I2C_BYT (0X0)
2211#define RSTVAL_I2C_DIV (0XC6C7)
2212#define RSTVAL_I2C_SCTL (0X0)
2213#define RSTVAL_I2C_SSTAT (0X1)
2214#define RSTVAL_I2C_SRX (0X0)
2215#define RSTVAL_I2C_STX (0X0)
2216#define RSTVAL_I2C_ALT (0X0)
2217#define RSTVAL_I2C_ID0 (0X0)
2218#define RSTVAL_I2C_ID1 (0X0)
2219#define RSTVAL_I2C_ID2 (0X0)
2220#define RSTVAL_I2C_ID3 (0X0)
2221#define RSTVAL_I2C_STAT (0X0)
2222#define RSTVAL_I2C_SHCTL (0X0)
2223#define RSTVAL_I2C_TCTL (0X205)
2224#define RSTVAL_I2C_ASTRETCH_SCL (0X0)
2225#define RSTVAL_I2C_IDFSTA (0X0)
2226#define RSTVAL_I2C_SLV_ADDR1 (0X0)
2227#define RSTVAL_I2C_SLV_ADDR2 (0X0)
2228#define RSTVAL_I2C_SSTAT2 (0X0)
2229
2230/* ====================================================================================================
2231 I2C Module Register BitPositions, Lengths, Masks and Enumerations Definitions
2232 ==================================================================================================== */
2233
2234/* ----------------------------------------------------------------------------------------------------
2235 MCTL Value Description
2236 ---------------------------------------------------------------------------------------------------- */
2237#define BITP_I2C_MCTL_MASEN (0U) /* Master Enable */
2238#define BITL_I2C_MCTL_MASEN (1U) /* Master Enable */
2239#define BITM_I2C_MCTL_MASEN (0X0001U) /* Master Enable */
2240#define BITP_I2C_MCTL_COMPETE (1U) /* Start Back-off Disable */
2241#define BITL_I2C_MCTL_COMPETE (1U) /* Start Back-off Disable */
2242#define BITM_I2C_MCTL_COMPETE (0X0002U) /* Start Back-off Disable */
2243#define BITP_I2C_MCTL_LOOPBACK (2U) /* Internal Loopback Enable */
2244#define BITL_I2C_MCTL_LOOPBACK (1U) /* Internal Loopback Enable */
2245#define BITM_I2C_MCTL_LOOPBACK (0X0004U) /* Internal Loopback Enable */
2246#define BITP_I2C_MCTL_IENMRX (4U) /* Receive Request Interrupt Enable */
2247#define BITL_I2C_MCTL_IENMRX (1U) /* Receive Request Interrupt Enable */
2248#define BITM_I2C_MCTL_IENMRX (0X0010U) /* Receive Request Interrupt Enable */
2249#define BITP_I2C_MCTL_IENMTX (5U) /* Transmit Request Interrupt Enable. */
2250#define BITL_I2C_MCTL_IENMTX (1U) /* Transmit Request Interrupt Enable. */
2251#define BITM_I2C_MCTL_IENMTX (0X0020U) /* Transmit Request Interrupt Enable. */
2252#define BITP_I2C_MCTL_IENALOST (6U) /* Arbitration Lost Interrupt Enable */
2253#define BITL_I2C_MCTL_IENALOST (1U) /* Arbitration Lost Interrupt Enable */
2254#define BITM_I2C_MCTL_IENALOST (0X0040U) /* Arbitration Lost Interrupt Enable */
2255#define BITP_I2C_MCTL_IENACK (7U) /* ACK Not Received Interrupt Enable */
2256#define BITL_I2C_MCTL_IENACK (1U) /* ACK Not Received Interrupt Enable */
2257#define BITM_I2C_MCTL_IENACK (0X0080U) /* ACK Not Received Interrupt Enable */
2258#define BITP_I2C_MCTL_IENCMP (8U) /* Transaction Completed (Or Stop Detected) Interrupt Enable */
2259#define BITL_I2C_MCTL_IENCMP (1U) /* Transaction Completed (Or Stop Detected) Interrupt Enable */
2260#define BITM_I2C_MCTL_IENCMP (0X0100U) /* Transaction Completed (Or Stop Detected) Interrupt Enable */
2261#define BITP_I2C_MCTL_MXMITDEC (9U) /* Decrement Master TX FIFO Status When Transmitted One Byte */
2262#define BITL_I2C_MCTL_MXMITDEC (1U) /* Decrement Master TX FIFO Status When Transmitted One Byte */
2263#define BITM_I2C_MCTL_MXMITDEC (0X0200U) /* Decrement Master TX FIFO Status When Transmitted One Byte */
2264#define BITP_I2C_MCTL_MRXDMA (10U) /* Enable Master Rx DMA Request */
2265#define BITL_I2C_MCTL_MRXDMA (1U) /* Enable Master Rx DMA Request */
2266#define BITM_I2C_MCTL_MRXDMA (0X0400U) /* Enable Master Rx DMA Request */
2267#define BITP_I2C_MCTL_MTXDMA (11U) /* Enable Master Tx DMA Request */
2268#define BITL_I2C_MCTL_MTXDMA (1U) /* Enable Master Tx DMA Request */
2269#define BITM_I2C_MCTL_MTXDMA (0X0800U) /* Enable Master Tx DMA Request */
2270#define BITP_I2C_MCTL_BUS_CLR_EN (12U) /* Bus-Clear Enable */
2271#define BITL_I2C_MCTL_BUS_CLR_EN (1U) /* Bus-Clear Enable */
2272#define BITM_I2C_MCTL_BUS_CLR_EN (0X1000U) /* Bus-Clear Enable */
2273#define BITP_I2C_MCTL_PRESTOP_BUS_CLR (13U) /* Prestop Bus-Clear */
2274#define BITL_I2C_MCTL_PRESTOP_BUS_CLR (1U) /* Prestop Bus-Clear */
2275#define BITM_I2C_MCTL_PRESTOP_BUS_CLR (0X2000U) /* Prestop Bus-Clear */
2276
2277/* ----------------------------------------------------------------------------------------------------
2278 MSTAT Value Description
2279 ---------------------------------------------------------------------------------------------------- */
2280#define BITP_I2C_MSTAT_MTXFSTA (0U) /* Master Transmit FIFO Status */
2281#define BITL_I2C_MSTAT_MTXFSTA (2U) /* Master Transmit FIFO Status */
2282#define BITM_I2C_MSTAT_MTXFSTA (0X0003U) /* Master Transmit FIFO Status */
2283#define BITP_I2C_MSTAT_MTXREQ (2U) /* Master Transmit Interrupt Bit */
2284#define BITL_I2C_MSTAT_MTXREQ (1U) /* Master Transmit Interrupt Bit */
2285#define BITM_I2C_MSTAT_MTXREQ (0X0004U) /* Master Transmit Interrupt Bit */
2286#define BITP_I2C_MSTAT_MRXREQ (3U) /* Master Receive Request */
2287#define BITL_I2C_MSTAT_MRXREQ (1U) /* Master Receive Request */
2288#define BITM_I2C_MSTAT_MRXREQ (0X0008U) /* Master Receive Request */
2289#define BITP_I2C_MSTAT_NACKADDR (4U) /* ACK Not Received in Response to an Address */
2290#define BITL_I2C_MSTAT_NACKADDR (1U) /* ACK Not Received in Response to an Address */
2291#define BITM_I2C_MSTAT_NACKADDR (0X0010U) /* ACK Not Received in Response to an Address */
2292#define BITP_I2C_MSTAT_ALOST (5U) /* Arbitration Lost */
2293#define BITL_I2C_MSTAT_ALOST (1U) /* Arbitration Lost */
2294#define BITM_I2C_MSTAT_ALOST (0X0020U) /* Arbitration Lost */
2295#define BITP_I2C_MSTAT_MBUSY (6U) /* Master Busy */
2296#define BITL_I2C_MSTAT_MBUSY (1U) /* Master Busy */
2297#define BITM_I2C_MSTAT_MBUSY (0X0040U) /* Master Busy */
2298#define BITP_I2C_MSTAT_NACKDATA (7U) /* ACK Not Received in Response to Data Write */
2299#define BITL_I2C_MSTAT_NACKDATA (1U) /* ACK Not Received in Response to Data Write */
2300#define BITM_I2C_MSTAT_NACKDATA (0X0080U) /* ACK Not Received in Response to Data Write */
2301#define BITP_I2C_MSTAT_TCOMP (8U) /* Transaction Complete or Stop Detected */
2302#define BITL_I2C_MSTAT_TCOMP (1U) /* Transaction Complete or Stop Detected */
2303#define BITM_I2C_MSTAT_TCOMP (0X0100U) /* Transaction Complete or Stop Detected */
2304#define BITP_I2C_MSTAT_MRXOF (9U) /* Master Receive FIFO Overflow */
2305#define BITL_I2C_MSTAT_MRXOF (1U) /* Master Receive FIFO Overflow */
2306#define BITM_I2C_MSTAT_MRXOF (0X0200U) /* Master Receive FIFO Overflow */
2307#define BITP_I2C_MSTAT_LINEBUSY (10U) /* Line is Busy */
2308#define BITL_I2C_MSTAT_LINEBUSY (1U) /* Line is Busy */
2309#define BITM_I2C_MSTAT_LINEBUSY (0X0400U) /* Line is Busy */
2310#define BITP_I2C_MSTAT_MSTOP (11U) /* STOP Driven by This I2C Master */
2311#define BITL_I2C_MSTAT_MSTOP (1U) /* STOP Driven by This I2C Master */
2312#define BITM_I2C_MSTAT_MSTOP (0X0800U) /* STOP Driven by This I2C Master */
2313#define BITP_I2C_MSTAT_MTXUFLOW (12U) /* Master Transmit Underflow */
2314#define BITL_I2C_MSTAT_MTXUFLOW (1U) /* Master Transmit Underflow */
2315#define BITM_I2C_MSTAT_MTXUFLOW (0X1000U) /* Master Transmit Underflow */
2316#define BITP_I2C_MSTAT_SDA_FILTERED (13U) /* State of SDA Line */
2317#define BITL_I2C_MSTAT_SDA_FILTERED (1U) /* State of SDA Line */
2318#define BITM_I2C_MSTAT_SDA_FILTERED (0X2000U) /* State of SDA Line */
2319#define BITP_I2C_MSTAT_SCL_FILTERED (14U) /* State of SCL Line */
2320#define BITL_I2C_MSTAT_SCL_FILTERED (1U) /* State of SCL Line */
2321#define BITM_I2C_MSTAT_SCL_FILTERED (0X4000U) /* State of SCL Line */
2322#define BITP_I2C_MSTAT_MSTR_HS_MODE (15U) /* Master High Speed Mode Flag */
2323#define BITL_I2C_MSTAT_MSTR_HS_MODE (1U) /* Master High Speed Mode Flag */
2324#define BITM_I2C_MSTAT_MSTR_HS_MODE (0X8000U) /* Master High Speed Mode Flag */
2325
2326/* ----------------------------------------------------------------------------------------------------
2327 MRX Value Description
2328 ---------------------------------------------------------------------------------------------------- */
2329#define BITP_I2C_MRX_ICMRX (0U) /* Master Receive Register */
2330#define BITL_I2C_MRX_ICMRX (8U) /* Master Receive Register */
2331#define BITM_I2C_MRX_ICMRX (0X00FFU) /* Master Receive Register */
2332
2333/* ----------------------------------------------------------------------------------------------------
2334 MTX Value Description
2335 ---------------------------------------------------------------------------------------------------- */
2336#define BITP_I2C_MTX_I2CMRX (0U) /* Master Transmit Register */
2337#define BITL_I2C_MTX_I2CMRX (8U) /* Master Transmit Register */
2338#define BITM_I2C_MTX_I2CMRX (0X00FFU) /* Master Transmit Register */
2339
2340/* ----------------------------------------------------------------------------------------------------
2341 MRXCNT Value Description
2342 ---------------------------------------------------------------------------------------------------- */
2343#define BITP_I2C_MRXCNT_COUNT (0U) /* Receive Count */
2344#define BITL_I2C_MRXCNT_COUNT (8U) /* Receive Count */
2345#define BITM_I2C_MRXCNT_COUNT (0X00FFU) /* Receive Count */
2346#define BITP_I2C_MRXCNT_EXTEND (8U) /* Extended Read */
2347#define BITL_I2C_MRXCNT_EXTEND (1U) /* Extended Read */
2348#define BITM_I2C_MRXCNT_EXTEND (0X0100U) /* Extended Read */
2349
2350/* ----------------------------------------------------------------------------------------------------
2351 MCRXCNT Value Description
2352 ---------------------------------------------------------------------------------------------------- */
2353#define BITP_I2C_MCRXCNT_COUNT (0U) /* Current Receive Count */
2354#define BITL_I2C_MCRXCNT_COUNT (8U) /* Current Receive Count */
2355#define BITM_I2C_MCRXCNT_COUNT (0X00FFU) /* Current Receive Count */
2356
2357/* ----------------------------------------------------------------------------------------------------
2358 ADDR0 Value Description
2359 ---------------------------------------------------------------------------------------------------- */
2360#define BITP_I2C_ADDR0_ADR1 (0U) /* Address Byte 1 */
2361#define BITL_I2C_ADDR0_ADR1 (8U) /* Address Byte 1 */
2362#define BITM_I2C_ADDR0_ADR1 (0X00FFU) /* Address Byte 1 */
2363
2364/* ----------------------------------------------------------------------------------------------------
2365 ADDR1 Value Description
2366 ---------------------------------------------------------------------------------------------------- */
2367#define BITP_I2C_ADDR1_ADR2 (0U) /* Address Byte 2 */
2368#define BITL_I2C_ADDR1_ADR2 (8U) /* Address Byte 2 */
2369#define BITM_I2C_ADDR1_ADR2 (0X00FFU) /* Address Byte 2 */
2370
2371/* ----------------------------------------------------------------------------------------------------
2372 BYT Value Description
2373 ---------------------------------------------------------------------------------------------------- */
2374#define BITP_I2C_BYT_SBYTE (0U) /* Start Byte */
2375#define BITL_I2C_BYT_SBYTE (8U) /* Start Byte */
2376#define BITM_I2C_BYT_SBYTE (0X00FFU) /* Start Byte */
2377
2378/* ----------------------------------------------------------------------------------------------------
2379 DIV Value Description
2380 ---------------------------------------------------------------------------------------------------- */
2381#define BITP_I2C_DIV_LOW (0U) /* Serial Clock Low Time */
2382#define BITL_I2C_DIV_LOW (8U) /* Serial Clock Low Time */
2383#define BITM_I2C_DIV_LOW (0X00FFU) /* Serial Clock Low Time */
2384#define BITP_I2C_DIV_HIGH (8U) /* Serial Clock High Time */
2385#define BITL_I2C_DIV_HIGH (8U) /* Serial Clock High Time */
2386#define BITM_I2C_DIV_HIGH (0XFF00U) /* Serial Clock High Time */
2387
2388/* ----------------------------------------------------------------------------------------------------
2389 SCTL Value Description
2390 ---------------------------------------------------------------------------------------------------- */
2391#define BITP_I2C_SCTL_SLVEN (0U) /* Slave Enable */
2392#define BITL_I2C_SCTL_SLVEN (1U) /* Slave Enable */
2393#define BITM_I2C_SCTL_SLVEN (0X0001U) /* Slave Enable */
2394#define BITP_I2C_SCTL_ADR10EN (1U) /* Enabled 10-bit Addressing */
2395#define BITL_I2C_SCTL_ADR10EN (1U) /* Enabled 10-bit Addressing */
2396#define BITM_I2C_SCTL_ADR10EN (0X0002U) /* Enabled 10-bit Addressing */
2397#define BITP_I2C_SCTL_GCEN (2U) /* General Call Enable */
2398#define BITL_I2C_SCTL_GCEN (1U) /* General Call Enable */
2399#define BITM_I2C_SCTL_GCEN (0X0004U) /* General Call Enable */
2400#define BITP_I2C_SCTL_HGCEN (3U) /* Hardware General Call Enable */
2401#define BITL_I2C_SCTL_HGCEN (1U) /* Hardware General Call Enable */
2402#define BITM_I2C_SCTL_HGCEN (0X0008U) /* Hardware General Call Enable */
2403#define BITP_I2C_SCTL_GCSBCLR (4U) /* General Call Status Bit Clear */
2404#define BITL_I2C_SCTL_GCSBCLR (1U) /* General Call Status Bit Clear */
2405#define BITM_I2C_SCTL_GCSBCLR (0X0010U) /* General Call Status Bit Clear */
2406#define BITP_I2C_SCTL_EARLYTXR (5U) /* Early Transmit Request Mode */
2407#define BITL_I2C_SCTL_EARLYTXR (1U) /* Early Transmit Request Mode */
2408#define BITM_I2C_SCTL_EARLYTXR (0X0020U) /* Early Transmit Request Mode */
2409#define BITP_I2C_SCTL_NACK (7U) /* NACK Next Communication */
2410#define BITL_I2C_SCTL_NACK (1U) /* NACK Next Communication */
2411#define BITM_I2C_SCTL_NACK (0X0080U) /* NACK Next Communication */
2412#define BITP_I2C_SCTL_IENSTOP (8U) /* Stop Condition Detected Interrupt Enable */
2413#define BITL_I2C_SCTL_IENSTOP (1U) /* Stop Condition Detected Interrupt Enable */
2414#define BITM_I2C_SCTL_IENSTOP (0X0100U) /* Stop Condition Detected Interrupt Enable */
2415#define BITP_I2C_SCTL_IENSRX (9U) /* Slave Receive Request Interrupt Enable */
2416#define BITL_I2C_SCTL_IENSRX (1U) /* Slave Receive Request Interrupt Enable */
2417#define BITM_I2C_SCTL_IENSRX (0X0200U) /* Slave Receive Request Interrupt Enable */
2418#define BITP_I2C_SCTL_IENSTX (10U) /* Slave Transmit Request Interrupt Enable */
2419#define BITL_I2C_SCTL_IENSTX (1U) /* Slave Transmit Request Interrupt Enable */
2420#define BITM_I2C_SCTL_IENSTX (0X0400U) /* Slave Transmit Request Interrupt Enable */
2421#define BITP_I2C_SCTL_SXMITDEC (11U) /* Decrement Slave Tx FIFO Status When Transmitted a Byte */
2422#define BITL_I2C_SCTL_SXMITDEC (1U) /* Decrement Slave Tx FIFO Status When Transmitted a Byte */
2423#define BITM_I2C_SCTL_SXMITDEC (0X0800U) /* Decrement Slave Tx FIFO Status When Transmitted a Byte */
2424#define BITP_I2C_SCTL_IENREPST (12U) /* Repeated Start Interrupt Enable */
2425#define BITL_I2C_SCTL_IENREPST (1U) /* Repeated Start Interrupt Enable */
2426#define BITM_I2C_SCTL_IENREPST (0X1000U) /* Repeated Start Interrupt Enable */
2427#define BITP_I2C_SCTL_SRXDMA (13U) /* Enable Slave Rx DMA Request */
2428#define BITL_I2C_SCTL_SRXDMA (1U) /* Enable Slave Rx DMA Request */
2429#define BITM_I2C_SCTL_SRXDMA (0X2000U) /* Enable Slave Rx DMA Request */
2430#define BITP_I2C_SCTL_STXDMA (14U) /* Enable Slave Tx DMA Request */
2431#define BITL_I2C_SCTL_STXDMA (1U) /* Enable Slave Tx DMA Request */
2432#define BITM_I2C_SCTL_STXDMA (0X4000U) /* Enable Slave Tx DMA Request */
2433#define BITP_I2C_SCTL_ID_FIFO_EN (15U) /* ID FIFO Enable */
2434#define BITL_I2C_SCTL_ID_FIFO_EN (1U) /* ID FIFO Enable */
2435#define BITM_I2C_SCTL_ID_FIFO_EN (0X8000U) /* ID FIFO Enable */
2436
2437/* ----------------------------------------------------------------------------------------------------
2438 SSTAT Value Description
2439 ---------------------------------------------------------------------------------------------------- */
2440#define BITP_I2C_SSTAT_STXFSEREQ (0U) /* Slave Tx FIFO Status or Early Request */
2441#define BITL_I2C_SSTAT_STXFSEREQ (1U) /* Slave Tx FIFO Status or Early Request */
2442#define BITM_I2C_SSTAT_STXFSEREQ (0X0001U) /* Slave Tx FIFO Status or Early Request */
2443#define BITP_I2C_SSTAT_STXUR (1U) /* Slave Transmit FIFO Underflow */
2444#define BITL_I2C_SSTAT_STXUR (1U) /* Slave Transmit FIFO Underflow */
2445#define BITM_I2C_SSTAT_STXUR (0X0002U) /* Slave Transmit FIFO Underflow */
2446#define BITP_I2C_SSTAT_STXREQ (2U) /* Slave Transmit Interrupt Bit */
2447#define BITL_I2C_SSTAT_STXREQ (1U) /* Slave Transmit Interrupt Bit */
2448#define BITM_I2C_SSTAT_STXREQ (0X0004U) /* Slave Transmit Interrupt Bit */
2449#define BITP_I2C_SSTAT_SRXREQ (3U) /* Slave Receive Request */
2450#define BITL_I2C_SSTAT_SRXREQ (1U) /* Slave Receive Request */
2451#define BITM_I2C_SSTAT_SRXREQ (0X0008U) /* Slave Receive Request */
2452#define BITP_I2C_SSTAT_SRXOF (4U) /* Slave Receive FIFO Overflow */
2453#define BITL_I2C_SSTAT_SRXOF (1U) /* Slave Receive FIFO Overflow */
2454#define BITM_I2C_SSTAT_SRXOF (0X0010U) /* Slave Receive FIFO Overflow */
2455#define BITP_I2C_SSTAT_NOACK (5U) /* Ack Not Generated by the Slave */
2456#define BITL_I2C_SSTAT_NOACK (1U) /* Ack Not Generated by the Slave */
2457#define BITM_I2C_SSTAT_NOACK (0X0020U) /* Ack Not Generated by the Slave */
2458#define BITP_I2C_SSTAT_SBUSY (6U) /* Slave Busy */
2459#define BITL_I2C_SSTAT_SBUSY (1U) /* Slave Busy */
2460#define BITM_I2C_SSTAT_SBUSY (0X0040U) /* Slave Busy */
2461#define BITP_I2C_SSTAT_GCINT (7U) /* General Call Interrupt */
2462#define BITL_I2C_SSTAT_GCINT (1U) /* General Call Interrupt */
2463#define BITM_I2C_SSTAT_GCINT (0X0080U) /* General Call Interrupt */
2464#define BITP_I2C_SSTAT_GCID (8U) /* General ID */
2465#define BITL_I2C_SSTAT_GCID (2U) /* General ID */
2466#define BITM_I2C_SSTAT_GCID (0X0300U) /* General ID */
2467#define BITP_I2C_SSTAT_STOP (10U) /* Stop After Start and Matching Address */
2468#define BITL_I2C_SSTAT_STOP (1U) /* Stop After Start and Matching Address */
2469#define BITM_I2C_SSTAT_STOP (0X0400U) /* Stop After Start and Matching Address */
2470#define BITP_I2C_SSTAT_IDMAT (11U) /* Device ID Matched */
2471#define BITL_I2C_SSTAT_IDMAT (2U) /* Device ID Matched */
2472#define BITM_I2C_SSTAT_IDMAT (0X1800U) /* Device ID Matched */
2473#define BITP_I2C_SSTAT_REPSTART (13U) /* Repeated Start and Matching Address */
2474#define BITL_I2C_SSTAT_REPSTART (1U) /* Repeated Start and Matching Address */
2475#define BITM_I2C_SSTAT_REPSTART (0X2000U) /* Repeated Start and Matching Address */
2476#define BITP_I2C_SSTAT_START (14U) /* Start and Matching Address */
2477#define BITL_I2C_SSTAT_START (1U) /* Start and Matching Address */
2478#define BITM_I2C_SSTAT_START (0X4000U) /* Start and Matching Address */
2479#define BITP_I2C_SSTAT_SLV_HS_MODE (15U) /* Slave High Speed Mode Flag */
2480#define BITL_I2C_SSTAT_SLV_HS_MODE (1U) /* Slave High Speed Mode Flag */
2481#define BITM_I2C_SSTAT_SLV_HS_MODE (0X8000U) /* Slave High Speed Mode Flag */
2482
2483#define ENUM_I2C_SSTAT_IDMAT_ID0 (0X0000U) /* Received Address Matched ID Register 0 */
2484#define ENUM_I2C_SSTAT_IDMAT_ID1 (0X0001U) /* Received Address Matched ID Register 1 */
2485#define ENUM_I2C_SSTAT_IDMAT_ID2 (0X0002U) /* Received Address Matched ID Register 2 */
2486#define ENUM_I2C_SSTAT_IDMAT_ID3 (0X0003U) /* Received Address Matched ID Register 3 */
2487#define ENUM_I2C_SSTAT_GCID_NONE (0X0000U) /* No general call */
2488#define ENUM_I2C_SSTAT_GCID_RESETPROGADDR (0X0001U) /* General call Reset and Program Address */
2489#define ENUM_I2C_SSTAT_GCID_PROGADDR (0X0002U) /* General Call Program Address */
2490#define ENUM_I2C_SSTAT_GCID_MATCHID (0X0003U) /* General Call Matching Alternative ID */
2491
2492/* ----------------------------------------------------------------------------------------------------
2493 SRX Value Description
2494 ---------------------------------------------------------------------------------------------------- */
2495#define BITP_I2C_SRX_I2CSRX (0U) /* Slave Receive Register */
2496#define BITL_I2C_SRX_I2CSRX (8U) /* Slave Receive Register */
2497#define BITM_I2C_SRX_I2CSRX (0X00FFU) /* Slave Receive Register */
2498
2499/* ----------------------------------------------------------------------------------------------------
2500 STX Value Description
2501 ---------------------------------------------------------------------------------------------------- */
2502#define BITP_I2C_STX_I2CSTX (0U) /* Slave Transmit Register */
2503#define BITL_I2C_STX_I2CSTX (8U) /* Slave Transmit Register */
2504#define BITM_I2C_STX_I2CSTX (0X00FFU) /* Slave Transmit Register */
2505#define BITP_I2C_STX_ID_SEL (8U) /* ID FIFO Selection */
2506#define BITL_I2C_STX_ID_SEL (2U) /* ID FIFO Selection */
2507#define BITM_I2C_STX_ID_SEL (0X0300U) /* ID FIFO Selection */
2508
2509#define ENUM_I2C_STX_ID_SEL_FIFO0 (0X0000U) /* Select Address Matched ID Register 0 */
2510#define ENUM_I2C_STX_ID_SEL_FIFO1 (0X0001U) /* Select Address Matched ID Register 1 */
2511#define ENUM_I2C_STX_ID_SEL_FIFO2 (0X0002U) /* Select Address Matched ID Register 2 */
2512#define ENUM_I2C_STX_ID_SEL_FIFO3 (0X0003U) /* Select Address Matched ID Register 3 */
2513
2514/* ----------------------------------------------------------------------------------------------------
2515 ALT Value Description
2516 ---------------------------------------------------------------------------------------------------- */
2517#define BITP_I2C_ALT_ALT (0U) /* Slave Alt */
2518#define BITL_I2C_ALT_ALT (8U) /* Slave Alt */
2519#define BITM_I2C_ALT_ALT (0X00FFU) /* Slave Alt */
2520
2521/* ----------------------------------------------------------------------------------------------------
2522 ID0 Value Description
2523 ---------------------------------------------------------------------------------------------------- */
2524#define BITP_I2C_ID0_ID0 (0U) /* Slave Device ID 0 */
2525#define BITL_I2C_ID0_ID0 (8U) /* Slave Device ID 0 */
2526#define BITM_I2C_ID0_ID0 (0X00FFU) /* Slave Device ID 0 */
2527
2528/* ----------------------------------------------------------------------------------------------------
2529 ID1 Value Description
2530 ---------------------------------------------------------------------------------------------------- */
2531#define BITP_I2C_ID1_ID1 (0U) /* Slave Device ID 1 */
2532#define BITL_I2C_ID1_ID1 (8U) /* Slave Device ID 1 */
2533#define BITM_I2C_ID1_ID1 (0X00FFU) /* Slave Device ID 1 */
2534
2535/* ----------------------------------------------------------------------------------------------------
2536 ID2 Value Description
2537 ---------------------------------------------------------------------------------------------------- */
2538#define BITP_I2C_ID2_ID2 (0U) /* Slave Device ID 2 */
2539#define BITL_I2C_ID2_ID2 (8U) /* Slave Device ID 2 */
2540#define BITM_I2C_ID2_ID2 (0X00FFU) /* Slave Device ID 2 */
2541
2542/* ----------------------------------------------------------------------------------------------------
2543 ID3 Value Description
2544 ---------------------------------------------------------------------------------------------------- */
2545#define BITP_I2C_ID3_ID3 (0U) /* Slave Device ID 3 */
2546#define BITL_I2C_ID3_ID3 (8U) /* Slave Device ID 3 */
2547#define BITM_I2C_ID3_ID3 (0X00FFU) /* Slave Device ID 3 */
2548
2549/* ----------------------------------------------------------------------------------------------------
2550 STAT Value Description
2551 ---------------------------------------------------------------------------------------------------- */
2552#define BITP_I2C_STAT_STXFSTA (0U) /* Slave Transmit FIFO Status */
2553#define BITL_I2C_STAT_STXFSTA (2U) /* Slave Transmit FIFO Status */
2554#define BITM_I2C_STAT_STXFSTA (0X0003U) /* Slave Transmit FIFO Status */
2555#define BITP_I2C_STAT_SRXFSTA (2U) /* Slave Receive FIFO Status */
2556#define BITL_I2C_STAT_SRXFSTA (2U) /* Slave Receive FIFO Status */
2557#define BITM_I2C_STAT_SRXFSTA (0X000CU) /* Slave Receive FIFO Status */
2558#define BITP_I2C_STAT_MTXSFA (4U) /* Master Transmit FIFO Status */
2559#define BITL_I2C_STAT_MTXSFA (2U) /* Master Transmit FIFO Status */
2560#define BITM_I2C_STAT_MTXSFA (0X0030U) /* Master Transmit FIFO Status */
2561#define BITP_I2C_STAT_MRXFSTA (6U) /* Master Receive FIFO Status */
2562#define BITL_I2C_STAT_MRXFSTA (2U) /* Master Receive FIFO Status */
2563#define BITM_I2C_STAT_MRXFSTA (0X00C0U) /* Master Receive FIFO Status */
2564#define BITP_I2C_STAT_SFLUSH (8U) /* Flush the Slave Transmit FIFO */
2565#define BITL_I2C_STAT_SFLUSH (1U) /* Flush the Slave Transmit FIFO */
2566#define BITM_I2C_STAT_SFLUSH (0X0100U) /* Flush the Slave Transmit FIFO */
2567#define BITP_I2C_STAT_MFLUSH (9U) /* Flush the Master Transmit FIFO */
2568#define BITL_I2C_STAT_MFLUSH (1U) /* Flush the Master Transmit FIFO */
2569#define BITM_I2C_STAT_MFLUSH (0X0200U) /* Flush the Master Transmit FIFO */
2570#define BITP_I2C_STAT_STX_FLUSH_ALL (10U) /* Flush All the Slave Transmit ID FIFOs. */
2571#define BITL_I2C_STAT_STX_FLUSH_ALL (1U) /* Flush All the Slave Transmit ID FIFOs. */
2572#define BITM_I2C_STAT_STX_FLUSH_ALL (0X0400U) /* Flush All the Slave Transmit ID FIFOs. */
2573
2574#define ENUM_I2C_STAT_MRXFSTA_EMPTY (0X0000U) /* FIFO Empty */
2575#define ENUM_I2C_STAT_MRXFSTA_ONE (0X0001U) /* 1 Bytes In The FIFO */
2576#define ENUM_I2C_STAT_MRXFSTA_TWO (0X0002U) /* 2 Bytes in the FIFO */
2577#define ENUM_I2C_STAT_MRXFSTA_RESERVED (0X0003U) /* Reserved */
2578#define ENUM_I2C_STAT_MTXSFA_EMPTY (0X0000U) /* FIFO Empty */
2579#define ENUM_I2C_STAT_MTXSFA_ONE (0X0001U) /* 1 Bytes in the FIFO */
2580#define ENUM_I2C_STAT_MTXSFA_TWO (0X0002U) /* 2 Bytes in the FIFO */
2581#define ENUM_I2C_STAT_MTXSFA_RESERVED (0X0003U) /* Reserved */
2582#define ENUM_I2C_STAT_SRXFSTA_EMPTY (0X0000U) /* FIFO Empty */
2583#define ENUM_I2C_STAT_SRXFSTA_ONE (0X0001U) /* 1 Bytes in the FIFO */
2584#define ENUM_I2C_STAT_SRXFSTA_TWO (0X0002U) /* 2 Bytes in the FIFO */
2585#define ENUM_I2C_STAT_SRXFSTA_RESERVED (0X0003U) /* Reserved */
2586#define ENUM_I2C_STAT_STXFSTA_EMPTY (0X0000U) /* FIFO Empty */
2587#define ENUM_I2C_STAT_STXFSTA_ONE (0X0001U) /* 1 Bytes in the FIFO */
2588#define ENUM_I2C_STAT_STXFSTA_TWO (0X0002U) /* 2 Bytes in the FIFO */
2589#define ENUM_I2C_STAT_STXFSTA_RESERVED (0X0003U) /* Reserved */
2590
2591/* ----------------------------------------------------------------------------------------------------
2592 SHCTL Value Description
2593 ---------------------------------------------------------------------------------------------------- */
2594#define BITP_I2C_SHCTL_RESET (0U) /* Reset START STOP Detect Circuit */
2595#define BITL_I2C_SHCTL_RESET (1U) /* Reset START STOP Detect Circuit */
2596#define BITM_I2C_SHCTL_RESET (0X0001U) /* Reset START STOP Detect Circuit */
2597#define BITP_I2C_SHCTL_ADR_BUSY (6U) /* ADR Busy Flag */
2598#define BITL_I2C_SHCTL_ADR_BUSY (1U) /* ADR Busy Flag */
2599#define BITM_I2C_SHCTL_ADR_BUSY (0X0040U) /* ADR Busy Flag */
2600#define BITP_I2C_SHCTL_SDA_DLY (8U) /* Delay Between SDAOUT and SDAOEN */
2601#define BITL_I2C_SHCTL_SDA_DLY (4U) /* Delay Between SDAOUT and SDAOEN */
2602#define BITM_I2C_SHCTL_SDA_DLY (0X0F00U) /* Delay Between SDAOUT and SDAOEN */
2603#define BITP_I2C_SHCTL_SCL_DLY (12U) /* Delay Between SCLOUT and SCLOEN */
2604#define BITL_I2C_SHCTL_SCL_DLY (4U) /* Delay Between SCLOUT and SCLOEN */
2605#define BITM_I2C_SHCTL_SCL_DLY (0XF000U) /* Delay Between SCLOUT and SCLOEN */
2606
2607/* ----------------------------------------------------------------------------------------------------
2608 TCTL Value Description
2609 ---------------------------------------------------------------------------------------------------- */
2610#define BITP_I2C_TCTL_THDATIN (0U) /* Data in Hold Start */
2611#define BITL_I2C_TCTL_THDATIN (6U) /* Data in Hold Start */
2612#define BITM_I2C_TCTL_THDATIN (0X003FU) /* Data in Hold Start */
2613#define BITP_I2C_TCTL_FILTEROFF (8U) /* Input Filter Control */
2614#define BITL_I2C_TCTL_FILTEROFF (1U) /* Input Filter Control */
2615#define BITM_I2C_TCTL_FILTEROFF (0X0100U) /* Input Filter Control */
2616#define BITP_I2C_TCTL_PRE_DIV (9U) /* Presale Divide Counter for SCK DIV */
2617#define BITL_I2C_TCTL_PRE_DIV (3U) /* Presale Divide Counter for SCK DIV */
2618#define BITM_I2C_TCTL_PRE_DIV (0X0E00U) /* Presale Divide Counter for SCK DIV */
2619#define BITP_I2C_TCTL_FILTER_TICKS (12U) /* SCK & SDA Gglitch Filter Ticks. */
2620#define BITL_I2C_TCTL_FILTER_TICKS (4U) /* SCK & SDA Gglitch Filter Ticks. */
2621#define BITM_I2C_TCTL_FILTER_TICKS (0XF000U) /* SCK & SDA Gglitch Filter Ticks. */
2622
2623/* ----------------------------------------------------------------------------------------------------
2624 ASTRETCH_SCL Value Description
2625 ---------------------------------------------------------------------------------------------------- */
2626#define BITP_I2C_ASTRETCH_SCL_STRETCH_MODE_MAS (0U) /* Master Automatic Stretch Mode */
2627#define BITL_I2C_ASTRETCH_SCL_STRETCH_MODE_MAS (4U) /* Master Automatic Stretch Mode */
2628#define BITM_I2C_ASTRETCH_SCL_STRETCH_MODE_MAS (0X000FU) /* Master Automatic Stretch Mode */
2629#define BITP_I2C_ASTRETCH_SCL_STRECTH_MODE_SLV (4U) /* Slave Automatic Stretch Mode */
2630#define BITL_I2C_ASTRETCH_SCL_STRECTH_MODE_SLV (4U) /* Slave Automatic Stretch Mode */
2631#define BITM_I2C_ASTRETCH_SCL_STRECTH_MODE_SLV (0X00F0U) /* Slave Automatic Stretch Mode */
2632#define BITP_I2C_ASTRETCH_SCL_TIMEOUT_SSCL_MAS (8U) /* Master Automatic Stretch Timeout */
2633#define BITL_I2C_ASTRETCH_SCL_TIMEOUT_SSCL_MAS (1U) /* Master Automatic Stretch Timeout */
2634#define BITM_I2C_ASTRETCH_SCL_TIMEOUT_SSCL_MAS (0X0100U) /* Master Automatic Stretch Timeout */
2635#define BITP_I2C_ASTRETCH_SCL_TIMEOUT_SSCL_SLV (9U) /* Slave Automatic Stretch Timeout */
2636#define BITL_I2C_ASTRETCH_SCL_TIMEOUT_SSCL_SLV (1U) /* Slave Automatic Stretch Timeout */
2637#define BITM_I2C_ASTRETCH_SCL_TIMEOUT_SSCL_SLV (0X0200U) /* Slave Automatic Stretch Timeout */
2638#define BITP_I2C_ASTRETCH_SCL_MAN_RLS_EN (10U) /* Manual Release Stretch Enable */
2639#define BITL_I2C_ASTRETCH_SCL_MAN_RLS_EN (1U) /* Manual Release Stretch Enable */
2640#define BITM_I2C_ASTRETCH_SCL_MAN_RLS_EN (0X0400U) /* Manual Release Stretch Enable */
2641#define BITP_I2C_ASTRETCH_SCL_SSCL_AFTER_ACK (11U) /* Slave RX Stretch After ACK Mode */
2642#define BITL_I2C_ASTRETCH_SCL_SSCL_AFTER_ACK (1U) /* Slave RX Stretch After ACK Mode */
2643#define BITM_I2C_ASTRETCH_SCL_SSCL_AFTER_ACK (0X0800U) /* Slave RX Stretch After ACK Mode */
2644#define BITP_I2C_ASTRETCH_SCL_SSCL_RLS (12U) /* Slave Manual Clear Stretch */
2645#define BITL_I2C_ASTRETCH_SCL_SSCL_RLS (1U) /* Slave Manual Clear Stretch */
2646#define BITM_I2C_ASTRETCH_SCL_SSCL_RLS (0X1000U) /* Slave Manual Clear Stretch */
2647#define BITP_I2C_ASTRETCH_SCL_ADDR_ACK_IEN (13U) /* Slave ADDRESS ACK Interruption Enable */
2648#define BITL_I2C_ASTRETCH_SCL_ADDR_ACK_IEN (1U) /* Slave ADDRESS ACK Interruption Enable */
2649#define BITM_I2C_ASTRETCH_SCL_ADDR_ACK_IEN (0X2000U) /* Slave ADDRESS ACK Interruption Enable */
2650#define BITP_I2C_ASTRETCH_SCL_SSCL_IRQ_IEN (14U) /* Slave Stretch Interruption Enable */
2651#define BITL_I2C_ASTRETCH_SCL_SSCL_IRQ_IEN (1U) /* Slave Stretch Interruption Enable */
2652#define BITM_I2C_ASTRETCH_SCL_SSCL_IRQ_IEN (0X4000U) /* Slave Stretch Interruption Enable */
2653#define BITP_I2C_ASTRETCH_SCL_CLR_ADDR_ACK_IRQ (15U) /* Write Clear the Address ACK IRQ. */
2654#define BITL_I2C_ASTRETCH_SCL_CLR_ADDR_ACK_IRQ (1U) /* Write Clear the Address ACK IRQ. */
2655#define BITM_I2C_ASTRETCH_SCL_CLR_ADDR_ACK_IRQ (0X8000U) /* Write Clear the Address ACK IRQ. */
2656
2657/* ----------------------------------------------------------------------------------------------------
2658 IDFSTA Value Description
2659 ---------------------------------------------------------------------------------------------------- */
2660#define BITP_I2C_IDFSTA_STX0FSTA (0U) /* Slave Transmit ID0 FIFO Status */
2661#define BITL_I2C_IDFSTA_STX0FSTA (2U) /* Slave Transmit ID0 FIFO Status */
2662#define BITM_I2C_IDFSTA_STX0FSTA (0X0003U) /* Slave Transmit ID0 FIFO Status */
2663#define BITP_I2C_IDFSTA_STX1FSTA (2U) /* Slave Transmit ID1 FIFO Status */
2664#define BITL_I2C_IDFSTA_STX1FSTA (2U) /* Slave Transmit ID1 FIFO Status */
2665#define BITM_I2C_IDFSTA_STX1FSTA (0X000CU) /* Slave Transmit ID1 FIFO Status */
2666#define BITP_I2C_IDFSTA_STX2FSTA (4U) /* Slave Transmit ID2 FIFO Status */
2667#define BITL_I2C_IDFSTA_STX2FSTA (2U) /* Slave Transmit ID2 FIFO Status */
2668#define BITM_I2C_IDFSTA_STX2FSTA (0X0030U) /* Slave Transmit ID2 FIFO Status */
2669#define BITP_I2C_IDFSTA_STX3FSTA (6U) /* Slave Transmit ID3 FIFO Status */
2670#define BITL_I2C_IDFSTA_STX3FSTA (2U) /* Slave Transmit ID3 FIFO Status */
2671#define BITM_I2C_IDFSTA_STX3FSTA (0X00C0U) /* Slave Transmit ID3 FIFO Status */
2672#define BITP_I2C_IDFSTA_SFLUSH0 (8U) /* Flush the Slave Transmit ID0 FIFO */
2673#define BITL_I2C_IDFSTA_SFLUSH0 (1U) /* Flush the Slave Transmit ID0 FIFO */
2674#define BITM_I2C_IDFSTA_SFLUSH0 (0X0100U) /* Flush the Slave Transmit ID0 FIFO */
2675#define BITP_I2C_IDFSTA_SFLUSH1 (9U) /* Flush the Slave Transmit ID1 FIFO */
2676#define BITL_I2C_IDFSTA_SFLUSH1 (1U) /* Flush the Slave Transmit ID1 FIFO */
2677#define BITM_I2C_IDFSTA_SFLUSH1 (0X0200U) /* Flush the Slave Transmit ID1 FIFO */
2678#define BITP_I2C_IDFSTA_SFLUSH2 (10U) /* Flush the Slave Transmit ID2 FIFO */
2679#define BITL_I2C_IDFSTA_SFLUSH2 (1U) /* Flush the Slave Transmit ID2 FIFO */
2680#define BITM_I2C_IDFSTA_SFLUSH2 (0X0400U) /* Flush the Slave Transmit ID2 FIFO */
2681#define BITP_I2C_IDFSTA_SFLUSH3 (11U) /* Flush the Slave Transmit ID3 FIFO */
2682#define BITL_I2C_IDFSTA_SFLUSH3 (1U) /* Flush the Slave Transmit ID3 FIFO */
2683#define BITM_I2C_IDFSTA_SFLUSH3 (0X0800U) /* Flush the Slave Transmit ID3 FIFO */
2684#define BITP_I2C_IDFSTA_STX0UR (12U) /* Slave Transmit ID0 FIFO Underflow */
2685#define BITL_I2C_IDFSTA_STX0UR (1U) /* Slave Transmit ID0 FIFO Underflow */
2686#define BITM_I2C_IDFSTA_STX0UR (0X1000U) /* Slave Transmit ID0 FIFO Underflow */
2687#define BITP_I2C_IDFSTA_STX1UR (13U) /* Slave Transmit ID1 FIFO Underflow */
2688#define BITL_I2C_IDFSTA_STX1UR (1U) /* Slave Transmit ID1 FIFO Underflow */
2689#define BITM_I2C_IDFSTA_STX1UR (0X2000U) /* Slave Transmit ID1 FIFO Underflow */
2690#define BITP_I2C_IDFSTA_STX2UR (14U) /* Slave Transmit ID2 FIFO Underflow */
2691#define BITL_I2C_IDFSTA_STX2UR (1U) /* Slave Transmit ID2 FIFO Underflow */
2692#define BITM_I2C_IDFSTA_STX2UR (0X4000U) /* Slave Transmit ID2 FIFO Underflow */
2693#define BITP_I2C_IDFSTA_STX3UR (15U) /* Slave Transmit ID3 FIFO Underflow */
2694#define BITL_I2C_IDFSTA_STX3UR (1U) /* Slave Transmit ID3 FIFO Underflow */
2695#define BITM_I2C_IDFSTA_STX3UR (0X8000U) /* Slave Transmit ID3 FIFO Underflow */
2696
2697#define ENUM_I2C_IDFSTA_STX3FSTA_EMPTY (0X0000U) /* FIFO Empty */
2698#define ENUM_I2C_IDFSTA_STX3FSTA_ONE (0X0001U) /* 1 Bytes in the FIFO */
2699#define ENUM_I2C_IDFSTA_STX3FSTA_TWO (0X0002U) /* 2 Bytes in the FIFO */
2700#define ENUM_I2C_IDFSTA_STX3FSTA_RESERVED (0X0003U) /* Reserved */
2701#define ENUM_I2C_IDFSTA_STX2FSTA_EMPTY (0X0000U) /* FIFO Empty */
2702#define ENUM_I2C_IDFSTA_STX2FSTA_ONE (0X0001U) /* 1 Bytes in the FIFO */
2703#define ENUM_I2C_IDFSTA_STX2FSTA_TWO (0X0002U) /* 2 Bytes in the FIFO */
2704#define ENUM_I2C_IDFSTA_STX2FSTA_RESERVED (0X0003U) /* Reserved */
2705#define ENUM_I2C_IDFSTA_STX1FSTA_EMPTY (0X0000U) /* FIFO Empty */
2706#define ENUM_I2C_IDFSTA_STX1FSTA_ONE (0X0001U) /* 1 Bytes in the FIFO */
2707#define ENUM_I2C_IDFSTA_STX1FSTA_TWO (0X0002U) /* 2 Bytes in the FIFO */
2708#define ENUM_I2C_IDFSTA_STX1FSTA_RESERVED (0X0003U) /* Reserved */
2709#define ENUM_I2C_IDFSTA_STX0FSTA_EMPTY (0X0000U) /* FIFO Empty */
2710#define ENUM_I2C_IDFSTA_STX0FSTA_ONE (0X0001U) /* 1 Bytes in the FIFO */
2711#define ENUM_I2C_IDFSTA_STX0FSTA_TWO (0X0002U) /* 2 Bytes in the FIFO */
2712#define ENUM_I2C_IDFSTA_STX0FSTA_RESERVED (0X0003U) /* Reserved */
2713
2714/* ----------------------------------------------------------------------------------------------------
2715 SLV_ADDR1 Value Description
2716 ---------------------------------------------------------------------------------------------------- */
2717#define BITP_I2C_SLV_ADDR1_SLV_ADR1 (0U) /* Slave 10 Bits Address 1st Byte */
2718#define BITL_I2C_SLV_ADDR1_SLV_ADR1 (8U) /* Slave 10 Bits Address 1st Byte */
2719#define BITM_I2C_SLV_ADDR1_SLV_ADR1 (0X00FFU) /* Slave 10 Bits Address 1st Byte */
2720
2721/* ----------------------------------------------------------------------------------------------------
2722 SLV_ADDR2 Value Description
2723 ---------------------------------------------------------------------------------------------------- */
2724#define BITP_I2C_SLV_ADDR2_SLV_ADR2 (0U) /* Slave 10 Bit Address 2nd Byte */
2725#define BITL_I2C_SLV_ADDR2_SLV_ADR2 (8U) /* Slave 10 Bit Address 2nd Byte */
2726#define BITM_I2C_SLV_ADDR2_SLV_ADR2 (0X00FFU) /* Slave 10 Bit Address 2nd Byte */
2727
2728/* ----------------------------------------------------------------------------------------------------
2729 SSTAT2 Value Description
2730 ---------------------------------------------------------------------------------------------------- */
2731#define BITP_I2C_SSTAT2_SSCL_IRQ (0U) /* Stretch Interruption State. */
2732#define BITL_I2C_SSTAT2_SSCL_IRQ (1U) /* Stretch Interruption State. */
2733#define BITM_I2C_SSTAT2_SSCL_IRQ (0X0001U) /* Stretch Interruption State. */
2734#define BITP_I2C_SSTAT2_ADDR_ACK_IRQ (1U) /* Slave ADDR ACK Interruption State. */
2735#define BITL_I2C_SSTAT2_ADDR_ACK_IRQ (1U) /* Slave ADDR ACK Interruption State. */
2736#define BITM_I2C_SSTAT2_ADDR_ACK_IRQ (0X0002U) /* Slave ADDR ACK Interruption State. */
2737#define BITP_I2C_SSTAT2_RW_DIRECTION (2U) /* Slave I2C RW Direction. */
2738#define BITL_I2C_SSTAT2_RW_DIRECTION (1U) /* Slave I2C RW Direction. */
2739#define BITM_I2C_SSTAT2_RW_DIRECTION (0X0004U) /* Slave I2C RW Direction. */
2740
2741#endif /* end ifndef I2C_ADDR_RDEF_H_ */
2742
2743
2744#ifndef MDIO_ADDR_RDEF_H_
2745#define MDIO_ADDR_RDEF_H_ /* MDIO: MDIO Interface */
2746
2747/* ====================================================================================================
2748 MDIO Module Instances Address and Mask Definitions
2749 ==================================================================================================== */
2750#define INST_MDIO (0X40022000U) /* mdio: */
2751
2752#define MASK_MDIO (0XFFFFFFFFU) /* MDIO: MDIO Interface */
2753
2754/* ====================================================================================================
2755 MDIO Module Register Address Offset Definitions
2756 ==================================================================================================== */
2757#define IDX_MDIO_MDCON (0X00000000U) /* MDIO Block Control */
2758#define IDX_MDIO_MDFRM (0X00000004U) /* MDIO Received Frame Control Information */
2759#define IDX_MDIO_MDRXD (0X00000008U) /* MDIO Received Data */
2760#define IDX_MDIO_MDADR (0X0000000CU) /* MDIO Received Address */
2761#define IDX_MDIO_MDTXD (0X00000010U) /* MDIO Data for Transmission */
2762#define IDX_MDIO_MDPHY (0X00000014U) /* MDIO PHYADDR Software Values and Selection and DEVADD */
2763#define IDX_MDIO_MDSTA (0X00000018U) /* MDIO Progress Signaling Through Frame */
2764#define IDX_MDIO_MDIEN (0X0000001CU) /* MDIO Interrupt Enables */
2765#define IDX_MDIO_MDPIN (0X00000020U) /* MDIO Read PHYADDR Pins */
2766#define IDX_MDIO_DMAEN (0X00000028U) /* MDIO DMA Enable */
2767#define IDX_MDIO_MDTESTCON (0X0000002CU) /* MDIO Test Controller Protected by Test Key */
2768
2769/* ====================================================================================================
2770 MDIO Module Register ResetValue Definitions
2771 ==================================================================================================== */
2772#define RSTVAL_MDIO_MDCON (0X0)
2773#define RSTVAL_MDIO_MDFRM (0X0)
2774#define RSTVAL_MDIO_MDTXD (0X0)
2775#define RSTVAL_MDIO_MDPHY (0X400)
2776#define RSTVAL_MDIO_MDSTA (0X0)
2777#define RSTVAL_MDIO_MDIEN (0X0)
2778#define RSTVAL_MDIO_MDPIN (0X0)
2779#define RSTVAL_MDIO_DMAEN (0X0)
2780#define RSTVAL_MDIO_MDTESTCON (0X800)
2781
2782/* ====================================================================================================
2783 MDIO Module Register BitPositions, Lengths, Masks and Enumerations Definitions
2784 ==================================================================================================== */
2785
2786/* ----------------------------------------------------------------------------------------------------
2787 MDCON Value Description
2788 ---------------------------------------------------------------------------------------------------- */
2789#define BITP_MDIO_MDCON_MD_RST (0U) /* Write 1 to Reset MDIO Block. */
2790#define BITL_MDIO_MDCON_MD_RST (1U) /* Write 1 to Reset MDIO Block. */
2791#define BITM_MDIO_MDCON_MD_RST (0X0001U) /* Write 1 to Reset MDIO Block. */
2792#define BITP_MDIO_MDCON_MD_PHM (1U) /* Enable PHY Address Bit Width */
2793#define BITL_MDIO_MDCON_MD_PHM (1U) /* Enable PHY Address Bit Width */
2794#define BITM_MDIO_MDCON_MD_PHM (0X0002U) /* Enable PHY Address Bit Width */
2795#define BITP_MDIO_MDCON_MD_DRV (2U) /* Enable Open-drain or Push-pull of MDIO Drive */
2796#define BITL_MDIO_MDCON_MD_DRV (1U) /* Enable Open-drain or Push-pull of MDIO Drive */
2797#define BITM_MDIO_MDCON_MD_DRV (0X0004U) /* Enable Open-drain or Push-pull of MDIO Drive */
2798#define BITP_MDIO_MDCON_MD_EN (8U) /* MD Enable */
2799#define BITL_MDIO_MDCON_MD_EN (1U) /* MD Enable */
2800#define BITM_MDIO_MDCON_MD_EN (0X0100U) /* MD Enable */
2801
2802#define ENUM_MDIO_MDCON_MD_DRV_MD_DRV_OD (0X0000U) /* MDIO Drive Open Drain. */
2803#define ENUM_MDIO_MDCON_MD_DRV_MD_DRV_PP (0X0001U) /* MDIO Drive Push-pull. */
2804#define ENUM_MDIO_MDCON_MD_PHM_EN_5BIT (0X0000U) /* 5bits PHYADD is active */
2805#define ENUM_MDIO_MDCON_MD_PHM_EN_3BITS (0X0001U) /* 3bits PHYADD is active, two MSBS are ignored */
2806#define ENUM_MDIO_MDCON_MD_RST_RSTACTIVE (0X0001U) /* Reset MDIO */
2807#define ENUM_MDIO_MDCON_MD_RST_RSTINACTIVE (0X0000U) /* Reset MDIO */
2808
2809/* ----------------------------------------------------------------------------------------------------
2810 MDFRM Value Description
2811 ---------------------------------------------------------------------------------------------------- */
2812#define BITP_MDIO_MDFRM_MD_OP (0U) /* Received OP */
2813#define BITL_MDIO_MDFRM_MD_OP (2U) /* Received OP */
2814#define BITM_MDIO_MDFRM_MD_OP (0X0003U) /* Received OP */
2815#define BITP_MDIO_MDFRM_MD_PHY (2U) /* Received PHYADR. */
2816#define BITL_MDIO_MDFRM_MD_PHY (5U) /* Received PHYADR. */
2817#define BITM_MDIO_MDFRM_MD_PHY (0X007CU) /* Received PHYADR. */
2818#define BITP_MDIO_MDFRM_MD_DEV (7U) /* Received DEVADD */
2819#define BITL_MDIO_MDFRM_MD_DEV (5U) /* Received DEVADD */
2820#define BITM_MDIO_MDFRM_MD_DEV (0X0F80U) /* Received DEVADD */
2821
2822#define ENUM_MDIO_MDFRM_MD_OP_MD_OP_ADF (0X0000U) /* Address Frame. */
2823#define ENUM_MDIO_MDFRM_MD_OP_MD_OP_WRF (0X0001U) /* Write Frame. */
2824#define ENUM_MDIO_MDFRM_MD_OP_MD_OP_INCF (0X0002U) /* PostReadIncAdd Frame. */
2825#define ENUM_MDIO_MDFRM_MD_OP_MD_OP_RDF (0X0003U) /* Read Frame. */
2826
2827/* ----------------------------------------------------------------------------------------------------
2828 MDRXD Value Description
2829 ---------------------------------------------------------------------------------------------------- */
2830#define BITP_MDIO_MDRXD_MD_RXD (0U) /* Received Data */
2831#define BITL_MDIO_MDRXD_MD_RXD (16U) /* Received Data */
2832#define BITM_MDIO_MDRXD_MD_RXD (0XFFFFU) /* Received Data */
2833
2834/* ----------------------------------------------------------------------------------------------------
2835 MDADR Value Description
2836 ---------------------------------------------------------------------------------------------------- */
2837#define BITP_MDIO_MDADR_MD_ADR (0U) /* Received Address */
2838#define BITL_MDIO_MDADR_MD_ADR (16U) /* Received Address */
2839#define BITM_MDIO_MDADR_MD_ADR (0XFFFFU) /* Received Address */
2840
2841/* ----------------------------------------------------------------------------------------------------
2842 MDTXD Value Description
2843 ---------------------------------------------------------------------------------------------------- */
2844#define BITP_MDIO_MDTXD_MD_TXD (0U) /* TX Data */
2845#define BITL_MDIO_MDTXD_MD_TXD (16U) /* TX Data */
2846#define BITM_MDIO_MDTXD_MD_TXD (0XFFFFU) /* TX Data */
2847
2848/* ----------------------------------------------------------------------------------------------------
2849 MDPHY Value Description
2850 ---------------------------------------------------------------------------------------------------- */
2851#define BITP_MDIO_MDPHY_MD_PHYSW (0U) /* Software Provided PHYADR */
2852#define BITL_MDIO_MDPHY_MD_PHYSW (5U) /* Software Provided PHYADR */
2853#define BITM_MDIO_MDPHY_MD_PHYSW (0X001FU) /* Software Provided PHYADR */
2854#define BITP_MDIO_MDPHY_MD_PHYSEL (5U) /* Selects Expected PHYADR Bits */
2855#define BITL_MDIO_MDPHY_MD_PHYSEL (5U) /* Selects Expected PHYADR Bits */
2856#define BITM_MDIO_MDPHY_MD_PHYSEL (0X03E0U) /* Selects Expected PHYADR Bits */
2857#define BITP_MDIO_MDPHY_MD_DEVADD (10U) /* Expected DEVADD */
2858#define BITL_MDIO_MDPHY_MD_DEVADD (5U) /* Expected DEVADD */
2859#define BITM_MDIO_MDPHY_MD_DEVADD (0X7C00U) /* Expected DEVADD */
2860
2861/* ----------------------------------------------------------------------------------------------------
2862 MDSTA Value Description
2863 ---------------------------------------------------------------------------------------------------- */
2864#define BITP_MDIO_MDSTA_MD_WRF (0U) /* Write Frame Status */
2865#define BITL_MDIO_MDSTA_MD_WRF (1U) /* Write Frame Status */
2866#define BITM_MDIO_MDSTA_MD_WRF (0X0001U) /* Write Frame Status */
2867#define BITP_MDIO_MDSTA_MD_ADRF (1U) /* Address Frame Status */
2868#define BITL_MDIO_MDSTA_MD_ADRF (1U) /* Address Frame Status */
2869#define BITM_MDIO_MDSTA_MD_ADRF (0X0002U) /* Address Frame Status */
2870#define BITP_MDIO_MDSTA_MD_INCF (2U) /* Post Read Increment Address Frame Status */
2871#define BITL_MDIO_MDSTA_MD_INCF (1U) /* Post Read Increment Address Frame Status */
2872#define BITM_MDIO_MDSTA_MD_INCF (0X0004U) /* Post Read Increment Address Frame Status */
2873#define BITP_MDIO_MDSTA_MD_RDF (3U) /* Read Frame Status */
2874#define BITL_MDIO_MDSTA_MD_RDF (1U) /* Read Frame Status */
2875#define BITM_MDIO_MDSTA_MD_RDF (0X0008U) /* Read Frame Status */
2876#define BITP_MDIO_MDSTA_MD_DEVM (4U) /* Device Address Matching Status */
2877#define BITL_MDIO_MDSTA_MD_DEVM (1U) /* Device Address Matching Status */
2878#define BITM_MDIO_MDSTA_MD_DEVM (0X0010U) /* Device Address Matching Status */
2879#define BITP_MDIO_MDSTA_MD_DEVN (5U) /* Device Address None Match Status */
2880#define BITL_MDIO_MDSTA_MD_DEVN (1U) /* Device Address None Match Status */
2881#define BITM_MDIO_MDSTA_MD_DEVN (0X0020U) /* Device Address None Match Status */
2882#define BITP_MDIO_MDSTA_MD_PHYM (6U) /* PHY Address Matching Status */
2883#define BITL_MDIO_MDSTA_MD_PHYM (1U) /* PHY Address Matching Status */
2884#define BITM_MDIO_MDSTA_MD_PHYM (0X0040U) /* PHY Address Matching Status */
2885#define BITP_MDIO_MDSTA_MD_PHYN (7U) /* PHY Address Non Matching Status */
2886#define BITL_MDIO_MDSTA_MD_PHYN (1U) /* PHY Address Non Matching Status */
2887#define BITM_MDIO_MDSTA_MD_PHYN (0X0080U) /* PHY Address Non Matching Status */
2888
2889/* ----------------------------------------------------------------------------------------------------
2890 MDIEN Value Description
2891 ---------------------------------------------------------------------------------------------------- */
2892#define BITP_MDIO_MDIEN_MD_WRFI (0U) /* Interrupt Enable for MD_WRF */
2893#define BITL_MDIO_MDIEN_MD_WRFI (1U) /* Interrupt Enable for MD_WRF */
2894#define BITM_MDIO_MDIEN_MD_WRFI (0X0001U) /* Interrupt Enable for MD_WRF */
2895#define BITP_MDIO_MDIEN_MD_ADRI (1U) /* Interrupt Enable for MD_ADRF */
2896#define BITL_MDIO_MDIEN_MD_ADRI (1U) /* Interrupt Enable for MD_ADRF */
2897#define BITM_MDIO_MDIEN_MD_ADRI (0X0002U) /* Interrupt Enable for MD_ADRF */
2898#define BITP_MDIO_MDIEN_MD_INCFI (2U) /* Interrupt Enable for MD_INCF */
2899#define BITL_MDIO_MDIEN_MD_INCFI (1U) /* Interrupt Enable for MD_INCF */
2900#define BITM_MDIO_MDIEN_MD_INCFI (0X0004U) /* Interrupt Enable for MD_INCF */
2901#define BITP_MDIO_MDIEN_MD_RDFI (3U) /* Interrupt Enable for MD_RDF */
2902#define BITL_MDIO_MDIEN_MD_RDFI (1U) /* Interrupt Enable for MD_RDF */
2903#define BITM_MDIO_MDIEN_MD_RDFI (0X0008U) /* Interrupt Enable for MD_RDF */
2904#define BITP_MDIO_MDIEN_MD_DEVMI (4U) /* Interrupt Enable for MD_DEVM */
2905#define BITL_MDIO_MDIEN_MD_DEVMI (1U) /* Interrupt Enable for MD_DEVM */
2906#define BITM_MDIO_MDIEN_MD_DEVMI (0X0010U) /* Interrupt Enable for MD_DEVM */
2907#define BITP_MDIO_MDIEN_MD_DEVNI (5U) /* Interrupt Enable for MD_DEVN */
2908#define BITL_MDIO_MDIEN_MD_DEVNI (1U) /* Interrupt Enable for MD_DEVN */
2909#define BITM_MDIO_MDIEN_MD_DEVNI (0X0020U) /* Interrupt Enable for MD_DEVN */
2910#define BITP_MDIO_MDIEN_MD_PHYMI (6U) /* Interrupt Enable for MD_PHYM */
2911#define BITL_MDIO_MDIEN_MD_PHYMI (1U) /* Interrupt Enable for MD_PHYM */
2912#define BITM_MDIO_MDIEN_MD_PHYMI (0X0040U) /* Interrupt Enable for MD_PHYM */
2913#define BITP_MDIO_MDIEN_MD_PHYNI (7U) /* Interrupt Enable for MD_PHYN */
2914#define BITL_MDIO_MDIEN_MD_PHYNI (1U) /* Interrupt Enable for MD_PHYN */
2915#define BITM_MDIO_MDIEN_MD_PHYNI (0X0080U) /* Interrupt Enable for MD_PHYN */
2916
2917/* ----------------------------------------------------------------------------------------------------
2918 MDPIN Value Description
2919 ---------------------------------------------------------------------------------------------------- */
2920#define BITP_MDIO_MDPIN_MD_PIN (0U) /* PRTADR Pins */
2921#define BITL_MDIO_MDPIN_MD_PIN (5U) /* PRTADR Pins */
2922#define BITM_MDIO_MDPIN_MD_PIN (0X001FU) /* PRTADR Pins */
2923
2924/* ----------------------------------------------------------------------------------------------------
2925 DMAEN Value Description
2926 ---------------------------------------------------------------------------------------------------- */
2927#define BITP_MDIO_DMAEN_RD_DATA (0U) /* Read Data */
2928#define BITL_MDIO_DMAEN_RD_DATA (1U) /* Read Data */
2929#define BITM_MDIO_DMAEN_RD_DATA (0X0001U) /* Read Data */
2930#define BITP_MDIO_DMAEN_INCRD_DATA (1U) /* Increment Read Data */
2931#define BITL_MDIO_DMAEN_INCRD_DATA (1U) /* Increment Read Data */
2932#define BITM_MDIO_DMAEN_INCRD_DATA (0X0002U) /* Increment Read Data */
2933#define BITP_MDIO_DMAEN_WR_ADR (2U) /* Write Address */
2934#define BITL_MDIO_DMAEN_WR_ADR (1U) /* Write Address */
2935#define BITM_MDIO_DMAEN_WR_ADR (0X0004U) /* Write Address */
2936#define BITP_MDIO_DMAEN_WR_DATA (3U) /* Write Data */
2937#define BITL_MDIO_DMAEN_WR_DATA (1U) /* Write Data */
2938#define BITM_MDIO_DMAEN_WR_DATA (0X0008U) /* Write Data */
2939
2940/* ----------------------------------------------------------------------------------------------------
2941 MDTESTCON Value Description
2942 ---------------------------------------------------------------------------------------------------- */
2943#define BITP_MDIO_MDTESTCON_TA_0_VALUE (11U) /* Output Value During First Bit of OP */
2944#define BITL_MDIO_MDTESTCON_TA_0_VALUE (1U) /* Output Value During First Bit of OP */
2945#define BITM_MDIO_MDTESTCON_TA_0_VALUE (0X0800U) /* Output Value During First Bit of OP */
2946#define BITP_MDIO_MDTESTCON_TA_1_VALUE (12U) /* Output Value During Second Bit of OP */
2947#define BITL_MDIO_MDTESTCON_TA_1_VALUE (1U) /* Output Value During Second Bit of OP */
2948#define BITM_MDIO_MDTESTCON_TA_1_VALUE (0X1000U) /* Output Value During Second Bit of OP */
2949#define BITP_MDIO_MDTESTCON_EN_TA_OUTPUT (13U) /* Enable Output Different During OP Phase */
2950#define BITL_MDIO_MDTESTCON_EN_TA_OUTPUT (1U) /* Enable Output Different During OP Phase */
2951#define BITM_MDIO_MDTESTCON_EN_TA_OUTPUT (0X2000U) /* Enable Output Different During OP Phase */
2952
2953#endif /* end ifndef MDIO_ADDR_RDEF_H_ */
2954
2955
2956#ifndef DMA_ADDR_RDEF_H_
2957#define DMA_ADDR_RDEF_H_ /* DMA: DMA */
2958
2959/* ====================================================================================================
2960 DMA Module Instances Address and Mask Definitions
2961 ==================================================================================================== */
2962#define INST_DMA (0X40040000U) /* dma: */
2963
2964#define MASK_DMA (0X00000FFFU) /* DMA: DMA */
2965
2966/* ====================================================================================================
2967 DMA Module Register Address Offset Definitions
2968 ==================================================================================================== */
2969#define IDX_DMA_STAT (0X000U) /* DMA Status */
2970#define IDX_DMA_CFG (0X004U) /* DMA Configuration */
2971#define IDX_DMA_PDBPTR (0X008U) /* DMA Channel Primary Control Data Base Pointer */
2972#define IDX_DMA_ADBPTR (0X00CU) /* DMA Channel Alternate Control Data Base Pointer */
2973#define IDX_DMA_SWREQ (0X014U) /* DMA Channel Software Request */
2974#define IDX_DMA_RMSKSET (0X020U) /* DMA Channel Request Mask Set */
2975#define IDX_DMA_RMSKCLR (0X024U) /* DMA Channel Request Mask Clear */
2976#define IDX_DMA_ENSET (0X028U) /* DMA Channel Enable Set */
2977#define IDX_DMA_ENCLR (0X02CU) /* DMA Channel Enable Clear */
2978#define IDX_DMA_ALTSET (0X030U) /* DMA Channel Primary-alternate Set */
2979#define IDX_DMA_ALTCLR (0X034U) /* DMA Channel Primary-alternate Clear */
2980#define IDX_DMA_PRISET (0X038U) /* DMA Channel Priority Set */
2981#define IDX_DMA_PRICLR (0X03CU) /* DMA Channel Priority Clear */
2982#define IDX_DMA_ERRCHNLCLR (0X048U) /* DMA per Channel Error Clear */
2983#define IDX_DMA_ERRCLR (0X04CU) /* DMA Bus Error Clear */
2984#define IDX_DMA_INVALIDDESCCLR (0X050U) /* DMA per Channel Invalid Descriptor Clear */
2985#define IDX_DMA_BSSET (0X800U) /* DMA Channel Bytes Swap Enable Set */
2986#define IDX_DMA_BSCLR (0X804U) /* DMA Channel Bytes Swap Enable Clear */
2987#define IDX_DMA_SRCADDRSET (0X810U) /* DMA Channel Source Address Decrement Enable Set */
2988#define IDX_DMA_SRCADDRCLR (0X814U) /* DMA Channel Source Address Decrement Enable Clear */
2989#define IDX_DMA_DSTADDRSET (0X818U) /* DMA Channel Destination Address Decrement Enable Set */
2990#define IDX_DMA_DSTADDRCLR (0X81CU) /* DMA Channel Destination Address Decrement Enable Clear */
2991#define IDX_DMA_REVID (0XFE0U) /* DMA Controller Revision ID */
2992
2993/* ====================================================================================================
2994 DMA Module Register ResetValue Definitions
2995 ==================================================================================================== */
2996#define RSTVAL_DMA_STAT (0X1E0000)
2997#define RSTVAL_DMA_CFG (0X0)
2998#define RSTVAL_DMA_PDBPTR (0X0)
2999#define RSTVAL_DMA_ADBPTR (0X200)
3000#define RSTVAL_DMA_SWREQ (0X0)
3001#define RSTVAL_DMA_RMSKSET (0X0)
3002#define RSTVAL_DMA_RMSKCLR (0X0)
3003#define RSTVAL_DMA_ENSET (0X0)
3004#define RSTVAL_DMA_ENCLR (0X0)
3005#define RSTVAL_DMA_ALTSET (0X0)
3006#define RSTVAL_DMA_ALTCLR (0X0)
3007#define RSTVAL_DMA_PRISET (0X0)
3008#define RSTVAL_DMA_PRICLR (0X0)
3009#define RSTVAL_DMA_ERRCHNLCLR (0X0)
3010#define RSTVAL_DMA_ERRCLR (0X0)
3011#define RSTVAL_DMA_INVALIDDESCCLR (0X0)
3012#define RSTVAL_DMA_BSSET (0X0)
3013#define RSTVAL_DMA_BSCLR (0X0)
3014#define RSTVAL_DMA_SRCADDRSET (0X0)
3015#define RSTVAL_DMA_SRCADDRCLR (0X0)
3016#define RSTVAL_DMA_DSTADDRSET (0X0)
3017#define RSTVAL_DMA_DSTADDRCLR (0X0)
3018#define RSTVAL_DMA_REVID (0X2)
3019
3020/* ====================================================================================================
3021 DMA Module Register BitPositions, Lengths, Masks and Enumerations Definitions
3022 ==================================================================================================== */
3023
3024/* ----------------------------------------------------------------------------------------------------
3025 STAT Value Description
3026 ---------------------------------------------------------------------------------------------------- */
3027#define BITP_DMA_STAT_MEN (0U) /* Enable Status of the Controller */
3028#define BITL_DMA_STAT_MEN (1U) /* Enable Status of the Controller */
3029#define BITM_DMA_STAT_MEN (0X00000001U) /* Enable Status of the Controller */
3030#define BITP_DMA_STAT_CHANM1 (16U) /* Number of Available DMA Channels Minus 1 */
3031#define BITL_DMA_STAT_CHANM1 (5U) /* Number of Available DMA Channels Minus 1 */
3032#define BITM_DMA_STAT_CHANM1 (0X001F0000U) /* Number of Available DMA Channels Minus 1 */
3033
3034/* ----------------------------------------------------------------------------------------------------
3035 CFG Value Description
3036 ---------------------------------------------------------------------------------------------------- */
3037#define BITP_DMA_CFG_MEN (0U) /* Controller Enable */
3038#define BITL_DMA_CFG_MEN (1U) /* Controller Enable */
3039#define BITM_DMA_CFG_MEN (0X00000001U) /* Controller Enable */
3040
3041/* ----------------------------------------------------------------------------------------------------
3042 PDBPTR Value Description
3043 ---------------------------------------------------------------------------------------------------- */
3044#define BITP_DMA_PDBPTR_ADDR (0U) /* Pointer to the Base Address of the Primary Data Structure */
3045#define BITL_DMA_PDBPTR_ADDR (32U) /* Pointer to the Base Address of the Primary Data Structure */
3046#define BITM_DMA_PDBPTR_ADDR (0XFFFFFFFFU) /* Pointer to the Base Address of the Primary Data Structure */
3047
3048/* ----------------------------------------------------------------------------------------------------
3049 ADBPTR Value Description
3050 ---------------------------------------------------------------------------------------------------- */
3051#define BITP_DMA_ADBPTR_ADDR (0U) /* Base Address of the Alternate Data Structure */
3052#define BITL_DMA_ADBPTR_ADDR (32U) /* Base Address of the Alternate Data Structure */
3053#define BITM_DMA_ADBPTR_ADDR (0XFFFFFFFFU) /* Base Address of the Alternate Data Structure */
3054
3055/* ----------------------------------------------------------------------------------------------------
3056 SWREQ Value Description
3057 ---------------------------------------------------------------------------------------------------- */
3058#define BITP_DMA_SWREQ_CHAN (0U) /* Generate Software Request */
3059#define BITL_DMA_SWREQ_CHAN (31U) /* Generate Software Request */
3060#define BITM_DMA_SWREQ_CHAN (0X7FFFFFFFU) /* Generate Software Request */
3061
3062/* ----------------------------------------------------------------------------------------------------
3063 RMSKSET Value Description
3064 ---------------------------------------------------------------------------------------------------- */
3065#define BITP_DMA_RMSKSET_CHAN (0U) /* Mask Requests from DMA Channels */
3066#define BITL_DMA_RMSKSET_CHAN (31U) /* Mask Requests from DMA Channels */
3067#define BITM_DMA_RMSKSET_CHAN (0X7FFFFFFFU) /* Mask Requests from DMA Channels */
3068
3069/* ----------------------------------------------------------------------------------------------------
3070 RMSKCLR Value Description
3071 ---------------------------------------------------------------------------------------------------- */
3072#define BITP_DMA_RMSKCLR_CHAN (0U) /* Clear REQ_MASK_SET Bits in DMARMSKSET */
3073#define BITL_DMA_RMSKCLR_CHAN (31U) /* Clear REQ_MASK_SET Bits in DMARMSKSET */
3074#define BITM_DMA_RMSKCLR_CHAN (0X7FFFFFFFU) /* Clear REQ_MASK_SET Bits in DMARMSKSET */
3075
3076/* ----------------------------------------------------------------------------------------------------
3077 ENSET Value Description
3078 ---------------------------------------------------------------------------------------------------- */
3079#define BITP_DMA_ENSET_CHAN (0U) /* Enable DMA Channels */
3080#define BITL_DMA_ENSET_CHAN (31U) /* Enable DMA Channels */
3081#define BITM_DMA_ENSET_CHAN (0X7FFFFFFFU) /* Enable DMA Channels */
3082
3083/* ----------------------------------------------------------------------------------------------------
3084 ENCLR Value Description
3085 ---------------------------------------------------------------------------------------------------- */
3086#define BITP_DMA_ENCLR_CHAN (0U) /* Disable DMA Channels */
3087#define BITL_DMA_ENCLR_CHAN (31U) /* Disable DMA Channels */
3088#define BITM_DMA_ENCLR_CHAN (0X7FFFFFFFU) /* Disable DMA Channels */
3089
3090/* ----------------------------------------------------------------------------------------------------
3091 ALTSET Value Description
3092 ---------------------------------------------------------------------------------------------------- */
3093#define BITP_DMA_ALTSET_CHAN (0U) /* Control Structure Status / Select Alt Structure */
3094#define BITL_DMA_ALTSET_CHAN (31U) /* Control Structure Status / Select Alt Structure */
3095#define BITM_DMA_ALTSET_CHAN (0X7FFFFFFFU) /* Control Structure Status / Select Alt Structure */
3096
3097/* ----------------------------------------------------------------------------------------------------
3098 ALTCLR Value Description
3099 ---------------------------------------------------------------------------------------------------- */
3100#define BITP_DMA_ALTCLR_CHAN (0U) /* Select Primary Data Structure */
3101#define BITL_DMA_ALTCLR_CHAN (31U) /* Select Primary Data Structure */
3102#define BITM_DMA_ALTCLR_CHAN (0X7FFFFFFFU) /* Select Primary Data Structure */
3103
3104/* ----------------------------------------------------------------------------------------------------
3105 PRISET Value Description
3106 ---------------------------------------------------------------------------------------------------- */
3107#define BITP_DMA_PRISET_CHAN (0U) /* Configure Channel for High Priority */
3108#define BITL_DMA_PRISET_CHAN (31U) /* Configure Channel for High Priority */
3109#define BITM_DMA_PRISET_CHAN (0X7FFFFFFFU) /* Configure Channel for High Priority */
3110
3111/* ----------------------------------------------------------------------------------------------------
3112 PRICLR Value Description
3113 ---------------------------------------------------------------------------------------------------- */
3114#define BITP_DMA_PRICLR_CHPRICLR (0U) /* Configure Channel for Default Priority Level */
3115#define BITL_DMA_PRICLR_CHPRICLR (31U) /* Configure Channel for Default Priority Level */
3116#define BITM_DMA_PRICLR_CHPRICLR (0X7FFFFFFFU) /* Configure Channel for Default Priority Level */
3117
3118/* ----------------------------------------------------------------------------------------------------
3119 ERRCHNLCLR Value Description
3120 ---------------------------------------------------------------------------------------------------- */
3121#define BITP_DMA_ERRCHNLCLR_CHAN (0U) /* Per Channel Bus Error Status/ Clear */
3122#define BITL_DMA_ERRCHNLCLR_CHAN (31U) /* Per Channel Bus Error Status/ Clear */
3123#define BITM_DMA_ERRCHNLCLR_CHAN (0X7FFFFFFFU) /* Per Channel Bus Error Status/ Clear */
3124
3125/* ----------------------------------------------------------------------------------------------------
3126 ERRCLR Value Description
3127 ---------------------------------------------------------------------------------------------------- */
3128#define BITP_DMA_ERRCLR_CHAN (0U) /* Bus Error Status */
3129#define BITL_DMA_ERRCLR_CHAN (31U) /* Bus Error Status */
3130#define BITM_DMA_ERRCLR_CHAN (0X7FFFFFFFU) /* Bus Error Status */
3131
3132/* ----------------------------------------------------------------------------------------------------
3133 INVALIDDESCCLR Value Description
3134 ---------------------------------------------------------------------------------------------------- */
3135#define BITP_DMA_INVALIDDESCCLR_CHAN (0U) /* Per Channel Invalid Descriptor Status */
3136#define BITL_DMA_INVALIDDESCCLR_CHAN (31U) /* Per Channel Invalid Descriptor Status */
3137#define BITM_DMA_INVALIDDESCCLR_CHAN (0X7FFFFFFFU) /* Per Channel Invalid Descriptor Status */
3138
3139/* ----------------------------------------------------------------------------------------------------
3140 BSSET Value Description
3141 ---------------------------------------------------------------------------------------------------- */
3142#define BITP_DMA_BSSET_CHAN (0U) /* Byte Swap Status */
3143#define BITL_DMA_BSSET_CHAN (31U) /* Byte Swap Status */
3144#define BITM_DMA_BSSET_CHAN (0X7FFFFFFFU) /* Byte Swap Status */
3145
3146/* ----------------------------------------------------------------------------------------------------
3147 BSCLR Value Description
3148 ---------------------------------------------------------------------------------------------------- */
3149#define BITP_DMA_BSCLR_CHAN (0U) /* Disable Byte Swap */
3150#define BITL_DMA_BSCLR_CHAN (31U) /* Disable Byte Swap */
3151#define BITM_DMA_BSCLR_CHAN (0X7FFFFFFFU) /* Disable Byte Swap */
3152
3153/* ----------------------------------------------------------------------------------------------------
3154 SRCADDRSET Value Description
3155 ---------------------------------------------------------------------------------------------------- */
3156#define BITP_DMA_SRCADDRSET_CHAN (0U) /* Source Address Decrement Status / Configure */
3157#define BITL_DMA_SRCADDRSET_CHAN (31U) /* Source Address Decrement Status / Configure */
3158#define BITM_DMA_SRCADDRSET_CHAN (0X7FFFFFFFU) /* Source Address Decrement Status / Configure */
3159
3160/* ----------------------------------------------------------------------------------------------------
3161 SRCADDRCLR Value Description
3162 ---------------------------------------------------------------------------------------------------- */
3163#define BITP_DMA_SRCADDRCLR_CHAN (0U) /* Disable Source Address Decrement */
3164#define BITL_DMA_SRCADDRCLR_CHAN (31U) /* Disable Source Address Decrement */
3165#define BITM_DMA_SRCADDRCLR_CHAN (0X7FFFFFFFU) /* Disable Source Address Decrement */
3166
3167/* ----------------------------------------------------------------------------------------------------
3168 DSTADDRSET Value Description
3169 ---------------------------------------------------------------------------------------------------- */
3170#define BITP_DMA_DSTADDRSET_CHAN (0U) /* Destination Address Decrement Status */
3171#define BITL_DMA_DSTADDRSET_CHAN (31U) /* Destination Address Decrement Status */
3172#define BITM_DMA_DSTADDRSET_CHAN (0X7FFFFFFFU) /* Destination Address Decrement Status */
3173
3174/* ----------------------------------------------------------------------------------------------------
3175 DSTADDRCLR Value Description
3176 ---------------------------------------------------------------------------------------------------- */
3177#define BITP_DMA_DSTADDRCLR_CHAN (0U) /* Disable Destination Address Decrement */
3178#define BITL_DMA_DSTADDRCLR_CHAN (31U) /* Disable Destination Address Decrement */
3179#define BITM_DMA_DSTADDRCLR_CHAN (0X7FFFFFFFU) /* Disable Destination Address Decrement */
3180
3181/* ----------------------------------------------------------------------------------------------------
3182 REVID Value Description
3183 ---------------------------------------------------------------------------------------------------- */
3184#define BITP_DMA_REVID_DMAREVID (0U) /* DMA Controller Revision ID */
3185#define BITL_DMA_REVID_DMAREVID (8U) /* DMA Controller Revision ID */
3186#define BITM_DMA_REVID_DMAREVID (0X000000FFU) /* DMA Controller Revision ID */
3187
3188#endif /* end ifndef DMA_ADDR_RDEF_H_ */
3189
3190
3191#ifndef CC_ADDR_RDEF_H_
3192#define CC_ADDR_RDEF_H_ /* CC: Cache Controller */
3193
3194/* ====================================================================================================
3195 CC Module Instances Address and Mask Definitions
3196 ==================================================================================================== */
3197#define INST_CACHE (0X40044000U) /* cache: */
3198
3199#define MASK_CC (0X000000FFU) /* CC: Cache Controller */
3200
3201/* ====================================================================================================
3202 CC Module Register Address Offset Definitions
3203 ==================================================================================================== */
3204#define IDX_CC_STAT (0X00U) /* Cache Status Register */
3205#define IDX_CC_SETUP (0X04U) /* Cache Setup Register */
3206#define IDX_CC_KEY (0X08U) /* Cache Key Register */
3207#define IDX_CC_PERFSETUP (0X0CU) /* Cache Performance Monitor Setup Register */
3208#define IDX_CC_ACCESSCNTR (0X10U) /* Cache Miss Counter */
3209#define IDX_CC_MSTRSETUP (0X24U) /* Cache Master Setup Register */
3210#define IDX_CC_ECCSTAT (0X34U) /* Cache SRAM ECC Status Register */
3211#define IDX_CC_ECCADDR (0X38U) /* Cache SRAM ECC Address Register */
3212
3213/* ====================================================================================================
3214 CC Module Register ResetValue Definitions
3215 ==================================================================================================== */
3216#define RSTVAL_CC_STAT (0X0)
3217#define RSTVAL_CC_SETUP (0X0)
3218#define RSTVAL_CC_KEY (0X0)
3219#define RSTVAL_CC_PERFSETUP (0X0)
3220#define RSTVAL_CC_ACCESSCNTR (0X0)
3221#define RSTVAL_CC_MSTRSETUP (0X0)
3222#define RSTVAL_CC_ECCSTAT (0X0)
3223#define RSTVAL_CC_ECCADDR (0X0)
3224
3225/* ====================================================================================================
3226 CC Module Register BitPositions, Lengths, Masks and Enumerations Definitions
3227 ==================================================================================================== */
3228
3229/* ----------------------------------------------------------------------------------------------------
3230 STAT Value Description
3231 ---------------------------------------------------------------------------------------------------- */
3232#define BITP_CC_STAT_CCEN (0U) /* Code Cache Enable Status */
3233#define BITL_CC_STAT_CCEN (1U) /* Code Cache Enable Status */
3234#define BITM_CC_STAT_CCEN (0X00000001U) /* Code Cache Enable Status */
3235#define BITP_CC_STAT_CCLCK (1U) /* Code Cache Lock Status */
3236#define BITL_CC_STAT_CCLCK (1U) /* Code Cache Lock Status */
3237#define BITM_CC_STAT_CCLCK (0X00000002U) /* Code Cache Lock Status */
3238#define BITP_CC_STAT_CCWIPE (3U) /* Code Cache Memory Wipe in Progress */
3239#define BITL_CC_STAT_CCWIPE (1U) /* Code Cache Memory Wipe in Progress */
3240#define BITM_CC_STAT_CCWIPE (0X00000008U) /* Code Cache Memory Wipe in Progress */
3241
3242/* ----------------------------------------------------------------------------------------------------
3243 SETUP Value Description
3244 ---------------------------------------------------------------------------------------------------- */
3245#define BITP_CC_SETUP_CCEN (0U) /* Code Cache Enable */
3246#define BITL_CC_SETUP_CCEN (1U) /* Code Cache Enable */
3247#define BITM_CC_SETUP_CCEN (0X00000001U) /* Code Cache Enable */
3248#define BITP_CC_SETUP_CCFLUSHDIS (8U) /* Disable Automatic Cache and Buffer Flush on Any Flash Update */
3249#define BITL_CC_SETUP_CCFLUSHDIS (1U) /* Disable Automatic Cache and Buffer Flush on Any Flash Update */
3250#define BITM_CC_SETUP_CCFLUSHDIS (0X00000100U) /* Disable Automatic Cache and Buffer Flush on Any Flash Update */
3251
3252/* ----------------------------------------------------------------------------------------------------
3253 KEY Value Description
3254 ---------------------------------------------------------------------------------------------------- */
3255#define BITP_CC_KEY_KEY (0U) /* Cache Key Register */
3256#define BITL_CC_KEY_KEY (32U) /* Cache Key Register */
3257#define BITM_CC_KEY_KEY (0XFFFFFFFFU) /* Cache Key Register */
3258
3259/* ----------------------------------------------------------------------------------------------------
3260 PERFSETUP Value Description
3261 ---------------------------------------------------------------------------------------------------- */
3262#define BITP_CC_PERFSETUP_STOPCNTR (0U) /* Performance Counter Stop */
3263#define BITL_CC_PERFSETUP_STOPCNTR (1U) /* Performance Counter Stop */
3264#define BITM_CC_PERFSETUP_STOPCNTR (0X00000001U) /* Performance Counter Stop */
3265#define BITP_CC_PERFSETUP_STRTCNTR (1U) /* Performance Counter Start */
3266#define BITL_CC_PERFSETUP_STRTCNTR (1U) /* Performance Counter Start */
3267#define BITM_CC_PERFSETUP_STRTCNTR (0X00000002U) /* Performance Counter Start */
3268
3269/* ----------------------------------------------------------------------------------------------------
3270 ACCESSCNTR Value Description
3271 ---------------------------------------------------------------------------------------------------- */
3272#define BITP_CC_ACCESSCNTR_CNT (0U) /* Cache Internal Performance Counter */
3273#define BITL_CC_ACCESSCNTR_CNT (32U) /* Cache Internal Performance Counter */
3274#define BITM_CC_ACCESSCNTR_CNT (0XFFFFFFFFU) /* Cache Internal Performance Counter */
3275
3276/* ----------------------------------------------------------------------------------------------------
3277 MSTRSETUP Value Description
3278 ---------------------------------------------------------------------------------------------------- */
3279#define BITP_CC_MSTRSETUP_MSTRNRA (0U) /* No Read Allocate for Master */
3280#define BITL_CC_MSTRSETUP_MSTRNRA (8U) /* No Read Allocate for Master */
3281#define BITM_CC_MSTRSETUP_MSTRNRA (0X000000FFU) /* No Read Allocate for Master */
3282
3283/* ----------------------------------------------------------------------------------------------------
3284 ECCSTAT Value Description
3285 ---------------------------------------------------------------------------------------------------- */
3286#define BITP_CC_ECCSTAT_ECCINTSTA (0U) /* Cache SRAM ECC Error Interrupt Status */
3287#define BITL_CC_ECCSTAT_ECCINTSTA (2U) /* Cache SRAM ECC Error Interrupt Status */
3288#define BITM_CC_ECCSTAT_ECCINTSTA (0X00000003U) /* Cache SRAM ECC Error Interrupt Status */
3289#define BITP_CC_ECCSTAT_ECCHRESPSTA (2U) /* Cache SRAM ECC Error Hresp Status */
3290#define BITL_CC_ECCSTAT_ECCHRESPSTA (2U) /* Cache SRAM ECC Error Hresp Status */
3291#define BITM_CC_ECCSTAT_ECCHRESPSTA (0X0000000CU) /* Cache SRAM ECC Error Hresp Status */
3292#define BITP_CC_ECCSTAT_ECCERRORCNT (4U) /* Cache SRAM ECC Error Counter */
3293#define BITL_CC_ECCSTAT_ECCERRORCNT (3U) /* Cache SRAM ECC Error Counter */
3294#define BITM_CC_ECCSTAT_ECCERRORCNT (0X00000070U) /* Cache SRAM ECC Error Counter */
3295
3296#define ENUM_CC_ECCSTAT_ECCHRESPSTA_NOERROR (0X00000000U) /* No Error */
3297#define ENUM_CC_ECCSTAT_ECCHRESPSTA_ERROR2BIT (0X00000001U) /* 2 Bit Error */
3298#define ENUM_CC_ECCSTAT_ECCHRESPSTA_ERROR1BIT (0X00000002U) /* 1 Bit Error */
3299#define ENUM_CC_ECCSTAT_ECCHRESPSTA_RESERVED (0X00000003U) /* Reserved */
3300#define ENUM_CC_ECCSTAT_ECCINTSTA_NOERROR (0X00000000U) /* No Error */
3301#define ENUM_CC_ECCSTAT_ECCINTSTA_ERROR2BIT (0X00000001U) /* 2 Bit Error */
3302#define ENUM_CC_ECCSTAT_ECCINTSTA_ERROR1BIT (0X00000002U) /* 1 Bit Error */
3303#define ENUM_CC_ECCSTAT_ECCINTSTA_ERROR1OR2BIT (0X00000003U) /* Either 1 Bit Error or 2 Bit Error */
3304
3305/* ----------------------------------------------------------------------------------------------------
3306 ECCADDR Value Description
3307 ---------------------------------------------------------------------------------------------------- */
3308#define BITP_CC_ECCADDR_ECCADDR (0U) /* Cache SRAM ECC Error Interrupt Address */
3309#define BITL_CC_ECCADDR_ECCADDR (11U) /* Cache SRAM ECC Error Interrupt Address */
3310#define BITM_CC_ECCADDR_ECCADDR (0X000007FFU) /* Cache SRAM ECC Error Interrupt Address */
3311
3312#endif /* end ifndef CC_ADDR_RDEF_H_ */
3313
3314
3315#ifndef FLASH_ADDR_RDEF_H_
3316#define FLASH_ADDR_RDEF_H_ /* FLASH: Flash Controller */
3317
3318/* ====================================================================================================
3319 FLASH Module Instances Address and Mask Definitions
3320 ==================================================================================================== */
3321#define INST_FLASH (0X40048000U) /* flash: */
3322
3323#define MASK_FLASH (0XFFFFFFFFU) /* FLASH: Flash Controller */
3324
3325/* ====================================================================================================
3326 FLASH Module Register Address Offset Definitions
3327 ==================================================================================================== */
3328#define IDX_FLASH_FEESTA (0X00000000U) /* Status Register */
3329#define IDX_FLASH_FEECON0 (0X00000004U) /* Command Control Register – Interrupt Enable Register */
3330#define IDX_FLASH_FEECMD (0X00000008U) /* Command Register */
3331#define IDX_FLASH_FEEFLADR (0X0000000CU) /* Flash Address Key - Hole Register */
3332#define IDX_FLASH_FEEFLDATA0 (0X00000010U) /* Flash Data Register - Key - Hole Interface Lower 32 Bits */
3333#define IDX_FLASH_FEEFLDATA1 (0X00000014U) /* Flash Data Register - Key - Hole Interface Upper 32 Bits */
3334#define IDX_FLASH_FEEADR0 (0X00000018U) /* Lower Page Address */
3335#define IDX_FLASH_FEEADR1 (0X0000001CU) /* Upper Page Address */
3336#define IDX_FLASH_FEEKEY (0X00000020U) /* Flash Key Register. */
3337#define IDX_FLASH_FEEPRO0 (0X00000028U) /* Write Protection Register for Flash0 */
3338#define IDX_FLASH_FEEPRO1 (0X0000002CU) /* Write Protection Register for Flash1 */
3339#define IDX_FLASH_FEESIG (0X00000034U) /* Flash Signature */
3340#define IDX_FLASH_FEECON1 (0X00000038U) /* User Setup Register */
3341#define IDX_FLASH_FEEWRADDRA (0X00000040U) /* Write Abort Address Register */
3342#define IDX_FLASH_FEEAEN0 (0X00000048U) /* Lower 32 Bits of the Sys Irq Abort Enable Register. */
3343#define IDX_FLASH_FEEAEN1 (0X0000004CU) /* Middle 32 Bits of the Sys Irq Abort Enable Register. */
3344#define IDX_FLASH_FEEAEN2 (0X00000050U) /* Upper 32 Bits of the Sys Irq Abort Enable Register. */
3345#define IDX_FLASH_FEEECCCONFIG (0X00000064U) /* Configurable ECC Enable/disable, Error Response */
3346#define IDX_FLASH_FEEECCADDRC0 (0X00000074U) /* Flash 0 ECC Error Address via CODE Bus */
3347#define IDX_FLASH_FEEECCADDRC1 (0X00000078U) /* Flash 1 ECC Error Address via CODE Bus */
3348#define IDX_FLASH_FEEECCADDRD0 (0X00000094U) /* Flash 0 ECC Error Address via DMA Bus */
3349#define IDX_FLASH_FEEECCADDRD1 (0X00000098U) /* Flash 1 ECC Error Address via DMA Bus */
3350
3351/* ====================================================================================================
3352 FLASH Module Register ResetValue Definitions
3353 ==================================================================================================== */
3354#define RSTVAL_FLASH_FEESTA (0X0)
3355#define RSTVAL_FLASH_FEECON0 (0X0)
3356#define RSTVAL_FLASH_FEECMD (0X0)
3357#define RSTVAL_FLASH_FEEFLADR (0X0)
3358#define RSTVAL_FLASH_FEEFLDATA0 (0X0)
3359#define RSTVAL_FLASH_FEEFLDATA1 (0X0)
3360#define RSTVAL_FLASH_FEEADR0 (0X0)
3361#define RSTVAL_FLASH_FEEADR1 (0X0)
3362#define RSTVAL_FLASH_FEEKEY (0X0)
3363#define RSTVAL_FLASH_FEEPRO0 (0XFFFFFFFF)
3364#define RSTVAL_FLASH_FEEPRO1 (0XFFFFFFFF)
3365#define RSTVAL_FLASH_FEECON1 (0X0)
3366#define RSTVAL_FLASH_FEEAEN0 (0X0)
3367#define RSTVAL_FLASH_FEEAEN1 (0X0)
3368#define RSTVAL_FLASH_FEEAEN2 (0X0)
3369#define RSTVAL_FLASH_FEEECCCONFIG (0X12)
3370#define RSTVAL_FLASH_FEEECCADDRC0 (0X0)
3371#define RSTVAL_FLASH_FEEECCADDRC1 (0X0)
3372#define RSTVAL_FLASH_FEEECCADDRD0 (0X0)
3373#define RSTVAL_FLASH_FEEECCADDRD1 (0X0)
3374
3375/* ====================================================================================================
3376 FLASH Module Register BitPositions, Lengths, Masks and Enumerations Definitions
3377 ==================================================================================================== */
3378
3379/* ----------------------------------------------------------------------------------------------------
3380 FEESTA Value Description
3381 ---------------------------------------------------------------------------------------------------- */
3382#define BITP_FLASH_FEESTA_CMDBUSY (0U) /* Command Busy. */
3383#define BITL_FLASH_FEESTA_CMDBUSY (1U) /* Command Busy. */
3384#define BITM_FLASH_FEESTA_CMDBUSY (0X00000001U) /* Command Busy. */
3385#define BITP_FLASH_FEESTA_WRCLOSE (1U) /* Key-hole Registers Closed for Access */
3386#define BITL_FLASH_FEESTA_WRCLOSE (1U) /* Key-hole Registers Closed for Access */
3387#define BITM_FLASH_FEESTA_WRCLOSE (0X00000002U) /* Key-hole Registers Closed for Access */
3388#define BITP_FLASH_FEESTA_CMDCOMP (2U) /* Command Complete */
3389#define BITL_FLASH_FEESTA_CMDCOMP (1U) /* Command Complete */
3390#define BITM_FLASH_FEESTA_CMDCOMP (0X00000004U) /* Command Complete */
3391#define BITP_FLASH_FEESTA_WRALCOMP (3U) /* Write Almost Complete – Key-hole Registers Open for Access */
3392#define BITL_FLASH_FEESTA_WRALCOMP (1U) /* Write Almost Complete – Key-hole Registers Open for Access */
3393#define BITM_FLASH_FEESTA_WRALCOMP (0X00000008U) /* Write Almost Complete – Key-hole Registers Open for Access */
3394#define BITP_FLASH_FEESTA_CMDFAIL (4U) /* Command Failed */
3395#define BITL_FLASH_FEESTA_CMDFAIL (2U) /* Command Failed */
3396#define BITM_FLASH_FEESTA_CMDFAIL (0X00000030U) /* Command Failed */
3397#define BITP_FLASH_FEESTA_ECCERRCMD (7U) /* ECC Errors Produced During Signature Commands */
3398#define BITL_FLASH_FEESTA_ECCERRCMD (2U) /* ECC Errors Produced During Signature Commands */
3399#define BITM_FLASH_FEESTA_ECCERRCMD (0X00000180U) /* ECC Errors Produced During Signature Commands */
3400#define BITP_FLASH_FEESTA_ECCREADERRFLSH0 (9U) /* ECC Interrupt Errors During AHB Read to Flash 0. */
3401#define BITL_FLASH_FEESTA_ECCREADERRFLSH0 (2U) /* ECC Interrupt Errors During AHB Read to Flash 0. */
3402#define BITM_FLASH_FEESTA_ECCREADERRFLSH0 (0X00000600U) /* ECC Interrupt Errors During AHB Read to Flash 0. */
3403#define BITP_FLASH_FEESTA_ECCREADERRFLSH1 (11U) /* ECC Interrupt Errors During AHB Read to Flash 1. */
3404#define BITL_FLASH_FEESTA_ECCREADERRFLSH1 (2U) /* ECC Interrupt Errors During AHB Read to Flash 1. */
3405#define BITM_FLASH_FEESTA_ECCREADERRFLSH1 (0X00001800U) /* ECC Interrupt Errors During AHB Read to Flash 1. */
3406#define BITP_FLASH_FEESTA_SIGNERR (13U) /* Initial Signature Check Error on Info Space */
3407#define BITL_FLASH_FEESTA_SIGNERR (1U) /* Initial Signature Check Error on Info Space */
3408#define BITM_FLASH_FEESTA_SIGNERR (0X00002000U) /* Initial Signature Check Error on Info Space */
3409#define BITP_FLASH_FEESTA_INIT (14U) /* Initialization Upload in Progress. */
3410#define BITL_FLASH_FEESTA_INIT (1U) /* Initialization Upload in Progress. */
3411#define BITM_FLASH_FEESTA_INIT (0X00004000U) /* Initialization Upload in Progress. */
3412#define BITP_FLASH_FEESTA_ECCERRINITSIGN (15U) /* ECC Error on Initial Info Signature Check */
3413#define BITL_FLASH_FEESTA_ECCERRINITSIGN (2U) /* ECC Error on Initial Info Signature Check */
3414#define BITM_FLASH_FEESTA_ECCERRINITSIGN (0X00018000U) /* ECC Error on Initial Info Signature Check */
3415#define BITP_FLASH_FEESTA_ECCERRCNTC0 (17U) /* ECC Error Count via CODE Bus of Flash 0 */
3416#define BITL_FLASH_FEESTA_ECCERRCNTC0 (3U) /* ECC Error Count via CODE Bus of Flash 0 */
3417#define BITM_FLASH_FEESTA_ECCERRCNTC0 (0X000E0000U) /* ECC Error Count via CODE Bus of Flash 0 */
3418#define BITP_FLASH_FEESTA_ECCERRCNTD0 (20U) /* ECC Error Count via DMA Bus of Flash 0 */
3419#define BITL_FLASH_FEESTA_ECCERRCNTD0 (2U) /* ECC Error Count via DMA Bus of Flash 0 */
3420#define BITM_FLASH_FEESTA_ECCERRCNTD0 (0X00300000U) /* ECC Error Count via DMA Bus of Flash 0 */
3421#define BITP_FLASH_FEESTA_ECCERRCNTC1 (22U) /* ECC Error Count via CODE Bus of Flash 1 */
3422#define BITL_FLASH_FEESTA_ECCERRCNTC1 (3U) /* ECC Error Count via CODE Bus of Flash 1 */
3423#define BITM_FLASH_FEESTA_ECCERRCNTC1 (0X01C00000U) /* ECC Error Count via CODE Bus of Flash 1 */
3424#define BITP_FLASH_FEESTA_ECCHRESPCODE (25U) /* ECC Error Response on CODE Bus */
3425#define BITL_FLASH_FEESTA_ECCHRESPCODE (2U) /* ECC Error Response on CODE Bus */
3426#define BITM_FLASH_FEESTA_ECCHRESPCODE (0X06000000U) /* ECC Error Response on CODE Bus */
3427#define BITP_FLASH_FEESTA_ECCHRESPDMA (27U) /* ECC Error Response on DMA Bus */
3428#define BITL_FLASH_FEESTA_ECCHRESPDMA (2U) /* ECC Error Response on DMA Bus */
3429#define BITM_FLASH_FEESTA_ECCHRESPDMA (0X18000000U) /* ECC Error Response on DMA Bus */
3430#define BITP_FLASH_FEESTA_ECCERRCNTD1 (29U) /* ECC Error Count via DMA Bus of Flash 1 */
3431#define BITL_FLASH_FEESTA_ECCERRCNTD1 (2U) /* ECC Error Count via DMA Bus of Flash 1 */
3432#define BITM_FLASH_FEESTA_ECCERRCNTD1 (0X60000000U) /* ECC Error Count via DMA Bus of Flash 1 */
3433
3434#define ENUM_FLASH_FEESTA_ECCHRESPDMA_NOERROR (0X00000000U) /* No Error. Successful Read from Program Flash via AHB Bus */
3435#define ENUM_FLASH_FEESTA_ECCHRESPDMA_ERROR2BIT (0X00000001U) /* During AHB Read to Flash, 2 Bit Error Detected, Not Corrected. */
3436#define ENUM_FLASH_FEESTA_ECCHRESPDMA_ERROR1BIT (0X00000002U) /* 1 Bit Error is Corrected for One Flash Location While Doing AHB Read to Program Flash */
3437#define ENUM_FLASH_FEESTA_ECCHRESPDMA_RESERVED (0X00000003U) /* Reserved */
3438#define ENUM_FLASH_FEESTA_ECCHRESPCODE_NOERROR (0X00000000U) /* No Error. Successful Read from Program Flash via AHB Bus */
3439#define ENUM_FLASH_FEESTA_ECCHRESPCODE_ERROR2BIT (0X00000001U) /* During AHB Read to Flash, 2 Bit Error Detected, Not Corrected. */
3440#define ENUM_FLASH_FEESTA_ECCHRESPCODE_ERROR1BIT (0X00000002U) /* 1 Bit Error is Corrected for One Flash Location While Doing AHB Read to Program Flash */
3441#define ENUM_FLASH_FEESTA_ECCHRESPCODE_RESERVED (0X00000003U) /* Reserved */
3442#define ENUM_FLASH_FEESTA_ECCERRINITSIGN_NOERROR (0X00000000U) /* No Error, Successful Flash Read Operation During Initial Signature Check, Page Signature Check */
3443#define ENUM_FLASH_FEESTA_ECCERRINITSIGN_ERROR2BIT (0X00000001U) /* During Initial Signature Check, 2 Bit Error Detected, Not Corrected for at Least One Flash Location */
3444#define ENUM_FLASH_FEESTA_ECCERRINITSIGN_ERROR1BIT (0X00000002U) /* 1 Bit Error is Corrected for One Flash Location While Doing Signature Commands */
3445#define ENUM_FLASH_FEESTA_ECCERRINITSIGN_ERROR1OR2BIT (0X00000003U) /* During Initial Signature Command, 1 Bit Error and 2 Bit Errors are Detected on One or More Flash Locations */
3446#define ENUM_FLASH_FEESTA_ECCREADERRFLSH1_NOERROR (0X00000000U) /* No Error. Successful Read from Data Flash via AHB Bus */
3447#define ENUM_FLASH_FEESTA_ECCREADERRFLSH1_ERROR2BIT (0X00000001U) /* 1 Bit Error is Corrected for One Flash Location While Doing AHB Read to Data Flash */
3448#define ENUM_FLASH_FEESTA_ECCREADERRFLSH1_ERROR1BIT (0X00000002U) /* During AHB Read to Flash, 2 Bit Error Detected, Not Corrected. */
3449#define ENUM_FLASH_FEESTA_ECCREADERRFLSH1_ERROR1OR2BIT (0X00000003U) /* During AHB Read, It is Either ECC Error or ECC Corrected Error Only. but This Condition Can Occur If the Consecutive Access Had AHB HRESP Error Due to ECC Error, Before the Status Register is Read. */
3450#define ENUM_FLASH_FEESTA_ECCREADERRFLSH0_NOERROR (0X00000000U) /* No Error. Successful Read from Program Flash via AHB Bus */
3451#define ENUM_FLASH_FEESTA_ECCREADERRFLSH0_ERROR2BIT (0X00000001U) /* During AHB Read to Flash, 2 Bit Error Detected, Not Corrected. */
3452#define ENUM_FLASH_FEESTA_ECCREADERRFLSH0_ERROR1BIT (0X00000002U) /* 1 Bit Error is Corrected for One Flash Location While Doing AHB Read to Program Flash */
3453#define ENUM_FLASH_FEESTA_ECCREADERRFLSH0_ERROR1OR2BIT (0X00000003U) /* During AHB Read, It is Either ECC Error or ECC Corrected Error Only. but This Condition Can Occur If the Consecutive Access Had AHB HRESP Error Due to ECC Error, Before the Status Register is Read. */
3454#define ENUM_FLASH_FEESTA_ECCERRCMD_NOERROR (0X00000000U) /* No Error, Successful Flash Read Operation During Signature Check */
3455#define ENUM_FLASH_FEESTA_ECCERRCMD_ERROR2BIT (0X00000001U) /* During Signature Commands, 2 Bit Error is Detected on One or More Flash Locations, Not Corrected. */
3456#define ENUM_FLASH_FEESTA_ECCERRCMD_ERROR1BIT (0X00000002U) /* 1 Bit Error is Corrected for One or More Flash Locations While Doing Signature Commands */
3457#define ENUM_FLASH_FEESTA_ECCERRCMD_ERROR1OR2BIT (0X00000003U) /* During Signature Commands, 1 Bit Error and 2 Bit Errors are Detected on One or More Flash Locations */
3458#define ENUM_FLASH_FEESTA_CMDFAIL_SUCCESS (0X00000000U) /* Successful Completion of a Command or a Write */
3459#define ENUM_FLASH_FEESTA_CMDFAIL_DENIED (0X00000001U) /* Attempted Signcheck,write or Erase of a Protected Location or Out of Memory Location. the Command is Ignored. */
3460#define ENUM_FLASH_FEESTA_CMDFAIL_VERIFYERR (0X00000002U) /* Read Verify Error */
3461#define ENUM_FLASH_FEESTA_CMDFAIL_ABORTED (0X00000003U) /* Indicates That a Command or a Write Was Aborted by an Abort Command or a System Interrupt Has Caused an Abort */
3462
3463/* ----------------------------------------------------------------------------------------------------
3464 FEECON0 Value Description
3465 ---------------------------------------------------------------------------------------------------- */
3466#define BITP_FLASH_FEECON0_IENCMD (0U) /* Command Complete Interrupt Enable */
3467#define BITL_FLASH_FEECON0_IENCMD (1U) /* Command Complete Interrupt Enable */
3468#define BITM_FLASH_FEECON0_IENCMD (0X00000001U) /* Command Complete Interrupt Enable */
3469#define BITP_FLASH_FEECON0_IWRALCOMP (1U) /* Write Almost Complete Interrupt Enable */
3470#define BITL_FLASH_FEECON0_IWRALCOMP (1U) /* Write Almost Complete Interrupt Enable */
3471#define BITM_FLASH_FEECON0_IWRALCOMP (0X00000002U) /* Write Almost Complete Interrupt Enable */
3472#define BITP_FLASH_FEECON0_IENERR (2U) /* Command Fail Interrupt Enable */
3473#define BITL_FLASH_FEECON0_IENERR (1U) /* Command Fail Interrupt Enable */
3474#define BITM_FLASH_FEECON0_IENERR (0X00000004U) /* Command Fail Interrupt Enable */
3475
3476/* ----------------------------------------------------------------------------------------------------
3477 FEECMD Value Description
3478 ---------------------------------------------------------------------------------------------------- */
3479#define BITP_FLASH_FEECMD_CMD (0U) /* Commands */
3480#define BITL_FLASH_FEECMD_CMD (5U) /* Commands */
3481#define BITM_FLASH_FEECMD_CMD (0X0000001FU) /* Commands */
3482
3483#define ENUM_FLASH_FEECMD_CMD_IDLE (0X00000000U) /* IDLE */
3484#define ENUM_FLASH_FEECMD_CMD_ERASEPAGE (0X00000001U) /* ERASEPAGE */
3485#define ENUM_FLASH_FEECMD_CMD_SIGN (0X00000002U) /* SIGN */
3486#define ENUM_FLASH_FEECMD_CMD_WRITE (0X00000004U) /* WRITE */
3487#define ENUM_FLASH_FEECMD_CMD_MASSERASE_ACTIVE (0X00000005U) /* MASSERASE_ACTIVE */
3488#define ENUM_FLASH_FEECMD_CMD_MASSERASE_PASSIVE (0X00000006U) /* MASSERASE_PASSIVE */
3489#define ENUM_FLASH_FEECMD_CMD_ABORT (0X00000008U) /* ABORT */
3490
3491/* ----------------------------------------------------------------------------------------------------
3492 FEEFLADR Value Description
3493 ---------------------------------------------------------------------------------------------------- */
3494#define BITP_FLASH_FEEFLADR_FLADDR (3U) /* Memory Mapped Address for the Flash Location */
3495#define BITL_FLASH_FEEFLADR_FLADDR (18U) /* Memory Mapped Address for the Flash Location */
3496#define BITM_FLASH_FEEFLADR_FLADDR (0X001FFFF8U) /* Memory Mapped Address for the Flash Location */
3497
3498/* ----------------------------------------------------------------------------------------------------
3499 FEEFLDATA0 Value Description
3500 ---------------------------------------------------------------------------------------------------- */
3501#define BITP_FLASH_FEEFLDATA0_FLDATA0 (0U) /* Lower 32 Bit of 64 Bit Data to Be Written to Flash */
3502#define BITL_FLASH_FEEFLDATA0_FLDATA0 (32U) /* Lower 32 Bit of 64 Bit Data to Be Written to Flash */
3503#define BITM_FLASH_FEEFLDATA0_FLDATA0 (0XFFFFFFFFU) /* Lower 32 Bit of 64 Bit Data to Be Written to Flash */
3504
3505/* ----------------------------------------------------------------------------------------------------
3506 FEEFLDATA1 Value Description
3507 ---------------------------------------------------------------------------------------------------- */
3508#define BITP_FLASH_FEEFLDATA1_FLDATA1 (0U) /* Upper 32 Bit of 64 Bit Data to Be Written to Flash */
3509#define BITL_FLASH_FEEFLDATA1_FLDATA1 (32U) /* Upper 32 Bit of 64 Bit Data to Be Written to Flash */
3510#define BITM_FLASH_FEEFLDATA1_FLDATA1 (0XFFFFFFFFU) /* Upper 32 Bit of 64 Bit Data to Be Written to Flash */
3511
3512/* ----------------------------------------------------------------------------------------------------
3513 FEEADR0 Value Description
3514 ---------------------------------------------------------------------------------------------------- */
3515#define BITP_FLASH_FEEADR0_PAGEADDR0 (13U) /* Page Address 0 */
3516#define BITL_FLASH_FEEADR0_PAGEADDR0 (8U) /* Page Address 0 */
3517#define BITM_FLASH_FEEADR0_PAGEADDR0 (0X001FE000U) /* Page Address 0 */
3518
3519/* ----------------------------------------------------------------------------------------------------
3520 FEEADR1 Value Description
3521 ---------------------------------------------------------------------------------------------------- */
3522#define BITP_FLASH_FEEADR1_PAGEADDR1 (13U) /* Page Address 1 */
3523#define BITL_FLASH_FEEADR1_PAGEADDR1 (8U) /* Page Address 1 */
3524#define BITM_FLASH_FEEADR1_PAGEADDR1 (0X001FE000U) /* Page Address 1 */
3525
3526/* ----------------------------------------------------------------------------------------------------
3527 FEEKEY Value Description
3528 ---------------------------------------------------------------------------------------------------- */
3529#define BITP_FLASH_FEEKEY_KEY (0U) /* Key Register */
3530#define BITL_FLASH_FEEKEY_KEY (32U) /* Key Register */
3531#define BITM_FLASH_FEEKEY_KEY (0XFFFFFFFFU) /* Key Register */
3532
3533/* ----------------------------------------------------------------------------------------------------
3534 FEEPRO0 Value Description
3535 ---------------------------------------------------------------------------------------------------- */
3536#define BITP_FLASH_FEEPRO0_WRPROT0 (0U) /* Write Protection for Flash0 – 32 Bits. */
3537#define BITL_FLASH_FEEPRO0_WRPROT0 (32U) /* Write Protection for Flash0 – 32 Bits. */
3538#define BITM_FLASH_FEEPRO0_WRPROT0 (0XFFFFFFFFU) /* Write Protection for Flash0 – 32 Bits. */
3539
3540/* ----------------------------------------------------------------------------------------------------
3541 FEEPRO1 Value Description
3542 ---------------------------------------------------------------------------------------------------- */
3543#define BITP_FLASH_FEEPRO1_WRPROT1 (0U) /* Write Protection for Flash1 – 32 Bits. */
3544#define BITL_FLASH_FEEPRO1_WRPROT1 (32U) /* Write Protection for Flash1 – 32 Bits. */
3545#define BITM_FLASH_FEEPRO1_WRPROT1 (0XFFFFFFFFU) /* Write Protection for Flash1 – 32 Bits. */
3546
3547/* ----------------------------------------------------------------------------------------------------
3548 FEESIG Value Description
3549 ---------------------------------------------------------------------------------------------------- */
3550#define BITP_FLASH_FEESIG_SIGN (0U) /* Signature */
3551#define BITL_FLASH_FEESIG_SIGN (24U) /* Signature */
3552#define BITM_FLASH_FEESIG_SIGN (0X00FFFFFFU) /* Signature */
3553
3554/* ----------------------------------------------------------------------------------------------------
3555 FEECON1 Value Description
3556 ---------------------------------------------------------------------------------------------------- */
3557#define BITP_FLASH_FEECON1_JTAGDEBUGEN (0U) /* JTAG Debug Enable */
3558#define BITL_FLASH_FEECON1_JTAGDEBUGEN (1U) /* JTAG Debug Enable */
3559#define BITM_FLASH_FEECON1_JTAGDEBUGEN (0X00000001U) /* JTAG Debug Enable */
3560#define BITP_FLASH_FEECON1_KHDMAEN (1U) /* Key – Hole DMA Enable. */
3561#define BITL_FLASH_FEECON1_KHDMAEN (1U) /* Key – Hole DMA Enable. */
3562#define BITM_FLASH_FEECON1_KHDMAEN (0X00000002U) /* Key – Hole DMA Enable. */
3563#define BITP_FLASH_FEECON1_AUTOINCREN (2U) /* Auto Address Increment for Key Hole Access. */
3564#define BITL_FLASH_FEECON1_AUTOINCREN (1U) /* Auto Address Increment for Key Hole Access. */
3565#define BITM_FLASH_FEECON1_AUTOINCREN (0X00000004U) /* Auto Address Increment for Key Hole Access. */
3566#define BITP_FLASH_FEECON1_SWAPPROGRAMCODE (3U) /* Swap Program Code for MDIO Mode. */
3567#define BITL_FLASH_FEECON1_SWAPPROGRAMCODE (1U) /* Swap Program Code for MDIO Mode. */
3568#define BITM_FLASH_FEECON1_SWAPPROGRAMCODE (0X00000008U) /* Swap Program Code for MDIO Mode. */
3569#define BITP_FLASH_FEECON1_MDIOMODE (4U) /* MDIO Mode */
3570#define BITL_FLASH_FEECON1_MDIOMODE (1U) /* MDIO Mode */
3571#define BITM_FLASH_FEECON1_MDIOMODE (0X00000010U) /* MDIO Mode */
3572#define BITP_FLASH_FEECON1_SWAPFLASH0 (5U) /* Swap Top and Bottom Image Inside Flash 0. */
3573#define BITL_FLASH_FEECON1_SWAPFLASH0 (1U) /* Swap Top and Bottom Image Inside Flash 0. */
3574#define BITM_FLASH_FEECON1_SWAPFLASH0 (0X00000020U) /* Swap Top and Bottom Image Inside Flash 0. */
3575#define BITP_FLASH_FEECON1_SWAPFLASH1 (6U) /* Swap Top and Bottom Image Inside Flash 1. */
3576#define BITL_FLASH_FEECON1_SWAPFLASH1 (1U) /* Swap Top and Bottom Image Inside Flash 1. */
3577#define BITM_FLASH_FEECON1_SWAPFLASH1 (0X00000040U) /* Swap Top and Bottom Image Inside Flash 1. */
3578#define BITP_FLASH_FEECON1_SWAPINFLASHEN (8U) /* Swap Inside Flash Enable */
3579#define BITL_FLASH_FEECON1_SWAPINFLASHEN (1U) /* Swap Inside Flash Enable */
3580#define BITM_FLASH_FEECON1_SWAPINFLASHEN (0X00000100U) /* Swap Inside Flash Enable */
3581
3582/* ----------------------------------------------------------------------------------------------------
3583 FEEWRADDRA Value Description
3584 ---------------------------------------------------------------------------------------------------- */
3585#define BITP_FLASH_FEEWRADDRA_WRABORTADDR (0U) /* Write Abort Address */
3586#define BITL_FLASH_FEEWRADDRA_WRABORTADDR (32U) /* Write Abort Address */
3587#define BITM_FLASH_FEEWRADDRA_WRABORTADDR (0XFFFFFFFFU) /* Write Abort Address */
3588
3589/* ----------------------------------------------------------------------------------------------------
3590 FEEAEN0 Value Description
3591 ---------------------------------------------------------------------------------------------------- */
3592#define BITP_FLASH_FEEAEN0_SYSIRQABORTEN (0U) /* Lower 32 Bits of System Interrupt Abort Enable. */
3593#define BITL_FLASH_FEEAEN0_SYSIRQABORTEN (32U) /* Lower 32 Bits of System Interrupt Abort Enable. */
3594#define BITM_FLASH_FEEAEN0_SYSIRQABORTEN (0XFFFFFFFFU) /* Lower 32 Bits of System Interrupt Abort Enable. */
3595
3596/* ----------------------------------------------------------------------------------------------------
3597 FEEAEN1 Value Description
3598 ---------------------------------------------------------------------------------------------------- */
3599#define BITP_FLASH_FEEAEN1_SYSIRQABORTEN (0U) /* Middle 32 Bits of System Interrupt Abort Enable. */
3600#define BITL_FLASH_FEEAEN1_SYSIRQABORTEN (32U) /* Middle 32 Bits of System Interrupt Abort Enable. */
3601#define BITM_FLASH_FEEAEN1_SYSIRQABORTEN (0XFFFFFFFFU) /* Middle 32 Bits of System Interrupt Abort Enable. */
3602
3603/* ----------------------------------------------------------------------------------------------------
3604 FEEAEN2 Value Description
3605 ---------------------------------------------------------------------------------------------------- */
3606#define BITP_FLASH_FEEAEN2_SYSIRQABORTEN (0U) /* Upper 32 Bits of System Interrupt Abort Enable. */
3607#define BITL_FLASH_FEEAEN2_SYSIRQABORTEN (32U) /* Upper 32 Bits of System Interrupt Abort Enable. */
3608#define BITM_FLASH_FEEAEN2_SYSIRQABORTEN (0XFFFFFFFFU) /* Upper 32 Bits of System Interrupt Abort Enable. */
3609
3610/* ----------------------------------------------------------------------------------------------------
3611 FEEECCCONFIG Value Description
3612 ---------------------------------------------------------------------------------------------------- */
3613#define BITP_FLASH_FEEECCCONFIG_ECCDISABLE (0U) /* ECC Disable Bit. */
3614#define BITL_FLASH_FEEECCCONFIG_ECCDISABLE (1U) /* ECC Disable Bit. */
3615#define BITM_FLASH_FEEECCCONFIG_ECCDISABLE (0X00000001U) /* ECC Disable Bit. */
3616#define BITP_FLASH_FEEECCCONFIG_ECCAHBERROR (1U) /* Signifies How to Generate AHB Error on ECC */
3617#define BITL_FLASH_FEEECCCONFIG_ECCAHBERROR (2U) /* Signifies How to Generate AHB Error on ECC */
3618#define BITM_FLASH_FEEECCCONFIG_ECCAHBERROR (0X00000006U) /* Signifies How to Generate AHB Error on ECC */
3619#define BITP_FLASH_FEEECCCONFIG_ECCINTRERROR (3U) /* Interrupt Enable When a ECC Error Happens During an AHB Read */
3620#define BITL_FLASH_FEEECCCONFIG_ECCINTRERROR (2U) /* Interrupt Enable When a ECC Error Happens During an AHB Read */
3621#define BITM_FLASH_FEEECCCONFIG_ECCINTRERROR (0X00000018U) /* Interrupt Enable When a ECC Error Happens During an AHB Read */
3622#define BITP_FLASH_FEEECCCONFIG_ECCADDRCON (5U) /* ECC Error Address Control Bit. */
3623#define BITL_FLASH_FEEECCCONFIG_ECCADDRCON (2U) /* ECC Error Address Control Bit. */
3624#define BITM_FLASH_FEEECCCONFIG_ECCADDRCON (0X00000060U) /* ECC Error Address Control Bit. */
3625
3626#define ENUM_FLASH_FEEECCCONFIG_ECCADDRCON_NBUFNCLR (0X00000000U) /* ECC Error Address Register Can't Be Cleared Until Reset; Current ECC Error Address Will Be Returned Directly When Reading ECC_ADDR MMR. */
3627#define ENUM_FLASH_FEEECCCONFIG_ECCADDRCON_BUFNCLR (0X00000001U) /* ECC Error Address Register Can't Be Cleared Until Reset; ECC Error Address is Latched on Read of STATUS MMR, and It Will Be Returned When Reading ECC_ADDR MMR. */
3628#define ENUM_FLASH_FEEECCCONFIG_ECCINTRERROR_DISABLE (0X00000000U) /* Interrupt is Not Generated Even If There is an ECC Error While Reading from Flash via AHB. This Applies to Both Flash. */
3629#define ENUM_FLASH_FEEECCCONFIG_ECCINTRERROR_ERROR2BITEN (0X00000001U) /* Interrupt is Generated Only If 2 Bit Error is Detected During AHB Read to Flash 0 or 1. */
3630#define ENUM_FLASH_FEEECCCONFIG_ECCINTRERROR_ERROR1BITEN (0X00000002U) /* Interrupt is Generated Only If 1 Bit Error Corrected During AHB Read to Flash 0 or 1. */
3631#define ENUM_FLASH_FEEECCCONFIG_ECCINTRERROR_ERROR1OR2BITEN (0X00000003U) /* Interrupt is Generated If Either 2 Bit Detected or 1 Bit Error Corrected During AHB Read to Flash 0 or 1. */
3632#define ENUM_FLASH_FEEECCCONFIG_ECCAHBERROR_NOERROR (0X00000000U) /* AHB Error (HRESP = 1) is Not Generated Even If There is an ECC Error While Reading from Flash via AHB. This Applies to Both Flash. */
3633#define ENUM_FLASH_FEEECCCONFIG_ECCAHBERROR_ERROR2BIT (0X00000001U) /* AHB Error (HRESP = 1) is Generated Only If 2 Bit Error is Detected During AHB Read to Flash 0 or 1. */
3634#define ENUM_FLASH_FEEECCCONFIG_ECCAHBERROR_ERROR1BIT (0X00000002U) /* AHB Error (HRESP = 1) is Generated Only If 1 Bit Error Corrected During AHB Read to Flash 0 or 1 */
3635#define ENUM_FLASH_FEEECCCONFIG_ECCAHBERROR_ERROR1OR2BIT (0X00000003U) /* AHB Error (HRESP = 1) is Generated If Either 2 Bit Detected or 1 Bit Error Corrected During AHB Read to Flash 0 or 1 */
3636
3637/* ----------------------------------------------------------------------------------------------------
3638 FEEECCADDRC0 Value Description
3639 ---------------------------------------------------------------------------------------------------- */
3640#define BITP_FLASH_FEEECCADDRC0_FLECCADDRC0 (0U) /* Flash0 Address for Which ECC Error is Detected via CODE Bus. */
3641#define BITL_FLASH_FEEECCADDRC0_FLECCADDRC0 (21U) /* Flash0 Address for Which ECC Error is Detected via CODE Bus. */
3642#define BITM_FLASH_FEEECCADDRC0_FLECCADDRC0 (0X001FFFFFU) /* Flash0 Address for Which ECC Error is Detected via CODE Bus. */
3643
3644/* ----------------------------------------------------------------------------------------------------
3645 FEEECCADDRC1 Value Description
3646 ---------------------------------------------------------------------------------------------------- */
3647#define BITP_FLASH_FEEECCADDRC1_FLECCADDRC1 (0U) /* Flash1 Address for Which ECC Error is Detected via CODE Bus. */
3648#define BITL_FLASH_FEEECCADDRC1_FLECCADDRC1 (21U) /* Flash1 Address for Which ECC Error is Detected via CODE Bus. */
3649#define BITM_FLASH_FEEECCADDRC1_FLECCADDRC1 (0X001FFFFFU) /* Flash1 Address for Which ECC Error is Detected via CODE Bus. */
3650
3651/* ----------------------------------------------------------------------------------------------------
3652 FEEECCADDRD0 Value Description
3653 ---------------------------------------------------------------------------------------------------- */
3654#define BITP_FLASH_FEEECCADDRD0_FLECCADDRD0 (0U) /* Flash0 Address for Which ECC Error is Detected via DMA Bus. */
3655#define BITL_FLASH_FEEECCADDRD0_FLECCADDRD0 (21U) /* Flash0 Address for Which ECC Error is Detected via DMA Bus. */
3656#define BITM_FLASH_FEEECCADDRD0_FLECCADDRD0 (0X001FFFFFU) /* Flash0 Address for Which ECC Error is Detected via DMA Bus. */
3657
3658/* ----------------------------------------------------------------------------------------------------
3659 FEEECCADDRD1 Value Description
3660 ---------------------------------------------------------------------------------------------------- */
3661#define BITP_FLASH_FEEECCADDRD1_FLECCADDRD1 (0U) /* Flash1 Address for Which ECC Error is Detected via DMA Bus. */
3662#define BITL_FLASH_FEEECCADDRD1_FLECCADDRD1 (21U) /* Flash1 Address for Which ECC Error is Detected via DMA Bus. */
3663#define BITM_FLASH_FEEECCADDRD1_FLECCADDRD1 (0X001FFFFFU) /* Flash1 Address for Which ECC Error is Detected via DMA Bus. */
3664
3665#endif /* end ifndef FLASH_ADDR_RDEF_H_ */
3666
3667
3668#ifndef GPIO_ADDR_RDEF_H_
3669#define GPIO_ADDR_RDEF_H_ /* GPIO: GPIO */
3670
3671/* ====================================================================================================
3672 GPIO Module Instances Address and Mask Definitions
3673 ==================================================================================================== */
3674#define INST_GPIO0 (0X40050000U) /* gpio0: */
3675#define INST_GPIO1 (0X40050050U) /* gpio1: */
3676#define INST_GPIO2 (0X400500A0U) /* gpio2: */
3677#define INST_GPIO3 (0X400500F0U) /* gpio3: */
3678#define INST_GPIO4 (0X40050140U) /* gpio4: */
3679#define INST_GPIO5 (0X40050190U) /* gpio5: */
3680
3681#define MASK_GPIO (0XFFFFFFFFU) /* GPIO: GPIO */
3682
3683/* ====================================================================================================
3684 GPIO Module Register Address Offset Definitions
3685 ==================================================================================================== */
3686#define IDX_GPIO_CON (0X00000000U) /* Port Configuration */
3687#define IDX_GPIO_OE (0X00000004U) /* Port Output Enable */
3688#define IDX_GPIO_IE (0X00000008U) /* Port Input Path Enable */
3689#define IDX_GPIO_IN (0X0000000CU) /* Port Registered Data Input */
3690#define IDX_GPIO_OUT (0X00000010U) /* Port Data Output */
3691#define IDX_GPIO_SET (0X00000014U) /* Port Data Out Set */
3692#define IDX_GPIO_CLR (0X00000018U) /* Port Data Out Clear */
3693#define IDX_GPIO_TGL (0X0000001CU) /* Port Pin Toggle */
3694#define IDX_GPIO_ODE (0X00000020U) /* Port Open Drain Enable */
3695#define IDX_GPIO_IS (0X00000024U) /* Port Input Select */
3696#define IDX_GPIO_PE (0X00000028U) /* Port Pull Enable */
3697#define IDX_GPIO_PS (0X0000002CU) /* Port Pull Select */
3698#define IDX_GPIO_SR (0X00000030U) /* Port Slew Rate */
3699#define IDX_GPIO_DS (0X00000034U) /* Port Drive Select */
3700#define IDX_GPIO_PWR (0X00000038U) /* Port Power Select */
3701#define IDX_GPIO_POL (0X0000003CU) /* GPIO Interrupt Polarity Select */
3702#define IDX_GPIO_IENA (0X00000040U) /* InterruptA Enable */
3703#define IDX_GPIO_IENB (0X00000044U) /* InterruptB Enable */
3704#define IDX_GPIO_INT (0X00000048U) /* Interrupt Status */
3705
3706/* ====================================================================================================
3707 GPIO Module Register ResetValue Definitions
3708 ==================================================================================================== */
3709#define RSTVAL_GPIO_CON (0X0)
3710#define RSTVAL_GPIO_OE (0X0)
3711#define RSTVAL_GPIO_IE (0X0)
3712#define RSTVAL_GPIO_IN (0X0)
3713#define RSTVAL_GPIO_OUT (0X0)
3714#define RSTVAL_GPIO_SET (0X0)
3715#define RSTVAL_GPIO_CLR (0X0)
3716#define RSTVAL_GPIO_TGL (0X0)
3717#define RSTVAL_GPIO_ODE (0X0)
3718#define RSTVAL_GPIO_IS (0XFF)
3719#define RSTVAL_GPIO_PE (0X0)
3720#define RSTVAL_GPIO_PS (0XFF)
3721#define RSTVAL_GPIO_SR (0X0)
3722#define RSTVAL_GPIO_DS (0X0)
3723#define RSTVAL_GPIO_PWR (0XFF)
3724#define RSTVAL_GPIO_POL (0X0)
3725#define RSTVAL_GPIO_IENA (0X0)
3726#define RSTVAL_GPIO_IENB (0X0)
3727#define RSTVAL_GPIO_INT (0X0)
3728
3729/* ====================================================================================================
3730 GPIO Module Register BitPositions, Lengths, Masks and Enumerations Definitions
3731 ==================================================================================================== */
3732
3733/* ----------------------------------------------------------------------------------------------------
3734 CON Value Description
3735 ---------------------------------------------------------------------------------------------------- */
3736#define BITP_GPIO_CON_CON0 (0U) /* PIN 0 Configuration Bits */
3737#define BITL_GPIO_CON_CON0 (2U) /* PIN 0 Configuration Bits */
3738#define BITM_GPIO_CON_CON0 (0X0003U) /* PIN 0 Configuration Bits */
3739#define BITP_GPIO_CON_CON1 (2U) /* PIN 1 Configuration Bits */
3740#define BITL_GPIO_CON_CON1 (2U) /* PIN 1 Configuration Bits */
3741#define BITM_GPIO_CON_CON1 (0X000CU) /* PIN 1 Configuration Bits */
3742#define BITP_GPIO_CON_CON2 (4U) /* PIN 2 Configuration Bits */
3743#define BITL_GPIO_CON_CON2 (2U) /* PIN 2 Configuration Bits */
3744#define BITM_GPIO_CON_CON2 (0X0030U) /* PIN 2 Configuration Bits */
3745#define BITP_GPIO_CON_CON3 (6U) /* PIN 3 Configuration Bits */
3746#define BITL_GPIO_CON_CON3 (2U) /* PIN 3 Configuration Bits */
3747#define BITM_GPIO_CON_CON3 (0X00C0U) /* PIN 3 Configuration Bits */
3748#define BITP_GPIO_CON_CON4 (8U) /* PIN 4 Configuration Bits */
3749#define BITL_GPIO_CON_CON4 (2U) /* PIN 4 Configuration Bits */
3750#define BITM_GPIO_CON_CON4 (0X0300U) /* PIN 4 Configuration Bits */
3751#define BITP_GPIO_CON_CON5 (10U) /* PIN 5 Configuration Bits */
3752#define BITL_GPIO_CON_CON5 (2U) /* PIN 5 Configuration Bits */
3753#define BITM_GPIO_CON_CON5 (0X0C00U) /* PIN 5 Configuration Bits */
3754#define BITP_GPIO_CON_CON6 (12U) /* PIN 6 Configuration Bits */
3755#define BITL_GPIO_CON_CON6 (2U) /* PIN 6 Configuration Bits */
3756#define BITM_GPIO_CON_CON6 (0X3000U) /* PIN 6 Configuration Bits */
3757#define BITP_GPIO_CON_CON7 (14U) /* PIN 6 Configuration Bits */
3758#define BITL_GPIO_CON_CON7 (2U) /* PIN 6 Configuration Bits */
3759#define BITM_GPIO_CON_CON7 (0XC000U) /* PIN 6 Configuration Bits */
3760
3761#define ENUM_GPIO_CON_CON7_FUNCTION0 (0X0000U) /* No description provided */
3762#define ENUM_GPIO_CON_CON7_FUNCTION1 (0X0001U) /* No description provided */
3763#define ENUM_GPIO_CON_CON7_FUNCTION2 (0X0002U) /* No description provided */
3764#define ENUM_GPIO_CON_CON7_FUNCTION3 (0X0003U) /* No description provided */
3765#define ENUM_GPIO_CON_CON6_FUNCTION0 (0X0000U) /* No description provided */
3766#define ENUM_GPIO_CON_CON6_FUNCTION1 (0X0001U) /* No description provided */
3767#define ENUM_GPIO_CON_CON6_FUNCTION2 (0X0002U) /* No description provided */
3768#define ENUM_GPIO_CON_CON6_FUNCTION3 (0X0003U) /* No description provided */
3769#define ENUM_GPIO_CON_CON5_FUNCTION0 (0X0000U) /* No description provided */
3770#define ENUM_GPIO_CON_CON5_FUNCTION1 (0X0001U) /* No description provided */
3771#define ENUM_GPIO_CON_CON5_FUNCTION2 (0X0002U) /* No description provided */
3772#define ENUM_GPIO_CON_CON5_FUNCTION3 (0X0003U) /* No description provided */
3773#define ENUM_GPIO_CON_CON4_FUNCTION0 (0X0000U) /* No description provided */
3774#define ENUM_GPIO_CON_CON4_FUNCTION1 (0X0001U) /* No description provided */
3775#define ENUM_GPIO_CON_CON4_FUNCTION2 (0X0002U) /* No description provided */
3776#define ENUM_GPIO_CON_CON4_FUNCTION3 (0X0003U) /* No description provided */
3777#define ENUM_GPIO_CON_CON3_FUNCTION0 (0X0000U) /* No description provided */
3778#define ENUM_GPIO_CON_CON3_FUNCTION1 (0X0001U) /* No description provided */
3779#define ENUM_GPIO_CON_CON3_FUNCTION2 (0X0002U) /* No description provided */
3780#define ENUM_GPIO_CON_CON3_FUNCTION3 (0X0003U) /* No description provided */
3781#define ENUM_GPIO_CON_CON2_FUNCTION0 (0X0000U) /* No description provided */
3782#define ENUM_GPIO_CON_CON2_FUNCTION1 (0X0001U) /* No description provided */
3783#define ENUM_GPIO_CON_CON2_FUNCTION2 (0X0002U) /* No description provided */
3784#define ENUM_GPIO_CON_CON2_FUNCTION3 (0X0003U) /* No description provided */
3785#define ENUM_GPIO_CON_CON1_FUNCTION0 (0X0000U) /* No description provided */
3786#define ENUM_GPIO_CON_CON1_FUNCTION1 (0X0001U) /* No description provided */
3787#define ENUM_GPIO_CON_CON1_FUNCTION2 (0X0002U) /* No description provided */
3788#define ENUM_GPIO_CON_CON1_FUNCTION3 (0X0003U) /* No description provided */
3789#define ENUM_GPIO_CON_CON0_FUNCTION0 (0X0000U) /* No description provided */
3790#define ENUM_GPIO_CON_CON0_FUNCTION1 (0X0001U) /* No description provided */
3791#define ENUM_GPIO_CON_CON0_FUNCTION2 (0X0002U) /* No description provided */
3792#define ENUM_GPIO_CON_CON0_FUNCTION3 (0X0003U) /* No description provided */
3793
3794/* ----------------------------------------------------------------------------------------------------
3795 OE Value Description
3796 ---------------------------------------------------------------------------------------------------- */
3797#define BITP_GPIO_OE_OE (0U) /* Open Drain Enable */
3798#define BITL_GPIO_OE_OE (8U) /* Open Drain Enable */
3799#define BITM_GPIO_OE_OE (0XFFU) /* Open Drain Enable */
3800
3801/* ----------------------------------------------------------------------------------------------------
3802 IE Value Description
3803 ---------------------------------------------------------------------------------------------------- */
3804#define BITP_GPIO_IE_IE (0U) /* Input Enable */
3805#define BITL_GPIO_IE_IE (8U) /* Input Enable */
3806#define BITM_GPIO_IE_IE (0XFFU) /* Input Enable */
3807
3808/* ----------------------------------------------------------------------------------------------------
3809 IN Value Description
3810 ---------------------------------------------------------------------------------------------------- */
3811#define BITP_GPIO_IN_A (0U) /* Diver Data Input */
3812#define BITL_GPIO_IN_A (8U) /* Diver Data Input */
3813#define BITM_GPIO_IN_A (0XFFU) /* Diver Data Input */
3814
3815/* ----------------------------------------------------------------------------------------------------
3816 OUT Value Description
3817 ---------------------------------------------------------------------------------------------------- */
3818#define BITP_GPIO_OUT_Y (0U) /* Input Data from Pad */
3819#define BITL_GPIO_OUT_Y (8U) /* Input Data from Pad */
3820#define BITM_GPIO_OUT_Y (0XFFU) /* Input Data from Pad */
3821
3822/* ----------------------------------------------------------------------------------------------------
3823 SET Value Description
3824 ---------------------------------------------------------------------------------------------------- */
3825#define BITP_GPIO_SET_SETUP (0U) /* Set the Output HIGH for the Pin */
3826#define BITL_GPIO_SET_SETUP (8U) /* Set the Output HIGH for the Pin */
3827#define BITM_GPIO_SET_SETUP (0XFFU) /* Set the Output HIGH for the Pin */
3828
3829/* ----------------------------------------------------------------------------------------------------
3830 CLR Value Description
3831 ---------------------------------------------------------------------------------------------------- */
3832#define BITP_GPIO_CLR_CLR (0U) /* Set the Output Low for the Port Pin */
3833#define BITL_GPIO_CLR_CLR (8U) /* Set the Output Low for the Port Pin */
3834#define BITM_GPIO_CLR_CLR (0XFFU) /* Set the Output Low for the Port Pin */
3835
3836/* ----------------------------------------------------------------------------------------------------
3837 TGL Value Description
3838 ---------------------------------------------------------------------------------------------------- */
3839#define BITP_GPIO_TGL_TGL (0U) /* Toggle the Output of the Port Pin */
3840#define BITL_GPIO_TGL_TGL (8U) /* Toggle the Output of the Port Pin */
3841#define BITM_GPIO_TGL_TGL (0XFFU) /* Toggle the Output of the Port Pin */
3842
3843/* ----------------------------------------------------------------------------------------------------
3844 ODE Value Description
3845 ---------------------------------------------------------------------------------------------------- */
3846#define BITP_GPIO_ODE_ODE (0U) /* Open Drain Enable */
3847#define BITL_GPIO_ODE_ODE (8U) /* Open Drain Enable */
3848#define BITM_GPIO_ODE_ODE (0XFFU) /* Open Drain Enable */
3849
3850/* ----------------------------------------------------------------------------------------------------
3851 IS Value Description
3852 ---------------------------------------------------------------------------------------------------- */
3853#define BITP_GPIO_IS_IS (0U) /* Input Select */
3854#define BITL_GPIO_IS_IS (8U) /* Input Select */
3855#define BITM_GPIO_IS_IS (0XFFU) /* Input Select */
3856
3857/* ----------------------------------------------------------------------------------------------------
3858 PE Value Description
3859 ---------------------------------------------------------------------------------------------------- */
3860#define BITP_GPIO_PE_PE (0U) /* Pull Enable */
3861#define BITL_GPIO_PE_PE (8U) /* Pull Enable */
3862#define BITM_GPIO_PE_PE (0XFFU) /* Pull Enable */
3863
3864/* ----------------------------------------------------------------------------------------------------
3865 PS Value Description
3866 ---------------------------------------------------------------------------------------------------- */
3867#define BITP_GPIO_PS_PS (0U) /* Pull Select */
3868#define BITL_GPIO_PS_PS (8U) /* Pull Select */
3869#define BITM_GPIO_PS_PS (0XFFU) /* Pull Select */
3870
3871/* ----------------------------------------------------------------------------------------------------
3872 SR Value Description
3873 ---------------------------------------------------------------------------------------------------- */
3874#define BITP_GPIO_SR_SR (0U) /* Slew Rate */
3875#define BITL_GPIO_SR_SR (8U) /* Slew Rate */
3876#define BITM_GPIO_SR_SR (0XFFU) /* Slew Rate */
3877
3878/* ----------------------------------------------------------------------------------------------------
3879 DS Value Description
3880 ---------------------------------------------------------------------------------------------------- */
3881#define BITP_GPIO_DS_DS0 (0U) /* PIN 0 Drive Select */
3882#define BITL_GPIO_DS_DS0 (2U) /* PIN 0 Drive Select */
3883#define BITM_GPIO_DS_DS0 (0X0003U) /* PIN 0 Drive Select */
3884#define BITP_GPIO_DS_DS1 (2U) /* PIN 1 Drive Select */
3885#define BITL_GPIO_DS_DS1 (2U) /* PIN 1 Drive Select */
3886#define BITM_GPIO_DS_DS1 (0X000CU) /* PIN 1 Drive Select */
3887#define BITP_GPIO_DS_DS2 (4U) /* PIN 2 Drive Select */
3888#define BITL_GPIO_DS_DS2 (2U) /* PIN 2 Drive Select */
3889#define BITM_GPIO_DS_DS2 (0X0030U) /* PIN 2 Drive Select */
3890#define BITP_GPIO_DS_DS3 (6U) /* PIN 3 Drive Select */
3891#define BITL_GPIO_DS_DS3 (2U) /* PIN 3 Drive Select */
3892#define BITM_GPIO_DS_DS3 (0X00C0U) /* PIN 3 Drive Select */
3893#define BITP_GPIO_DS_DS4 (8U) /* PIN 4 Drive Select */
3894#define BITL_GPIO_DS_DS4 (2U) /* PIN 4 Drive Select */
3895#define BITM_GPIO_DS_DS4 (0X0300U) /* PIN 4 Drive Select */
3896#define BITP_GPIO_DS_DS5 (10U) /* PIN 5 Drive Select */
3897#define BITL_GPIO_DS_DS5 (2U) /* PIN 5 Drive Select */
3898#define BITM_GPIO_DS_DS5 (0X0C00U) /* PIN 5 Drive Select */
3899#define BITP_GPIO_DS_DS6 (12U) /* PIN6 Drive Select */
3900#define BITL_GPIO_DS_DS6 (2U) /* PIN6 Drive Select */
3901#define BITM_GPIO_DS_DS6 (0X3000U) /* PIN6 Drive Select */
3902#define BITP_GPIO_DS_DS7 (14U) /* PIN 7 Drive Select */
3903#define BITL_GPIO_DS_DS7 (2U) /* PIN 7 Drive Select */
3904#define BITM_GPIO_DS_DS7 (0XC000U) /* PIN 7 Drive Select */
3905
3906#define ENUM_GPIO_DS_DS7_STRENGTH1 (0X0000U) /* Drive Strength 1 */
3907#define ENUM_GPIO_DS_DS7_STRENGTH2 (0X0001U) /* Drive Strength 2 */
3908#define ENUM_GPIO_DS_DS7_STRENGTH3 (0X0002U) /* Drive Strength 3 */
3909#define ENUM_GPIO_DS_DS7_STRENGTH4 (0X0003U) /* Drive Strength 4 */
3910#define ENUM_GPIO_DS_DS6_STRENGTH1 (0X0000U) /* Drive Strength 1 */
3911#define ENUM_GPIO_DS_DS6_STRENGTH2 (0X0001U) /* Drive Strength 2 */
3912#define ENUM_GPIO_DS_DS6_STRENGTH3 (0X0002U) /* Drive Strength 3 */
3913#define ENUM_GPIO_DS_DS6_STRENGTH4 (0X0003U) /* Drive Strength 4 */
3914#define ENUM_GPIO_DS_DS5_STRENGTH1 (0X0000U) /* Drive Strength 1 */
3915#define ENUM_GPIO_DS_DS5_STRENGTH2 (0X0001U) /* Drive Strength 2 */
3916#define ENUM_GPIO_DS_DS5_STRENGTH3 (0X0002U) /* Drive Strength 3 */
3917#define ENUM_GPIO_DS_DS5_STRENGTH4 (0X0003U) /* Drive Strength 4 */
3918#define ENUM_GPIO_DS_DS4_STRENGTH1 (0X0000U) /* Drive Strength 1 */
3919#define ENUM_GPIO_DS_DS4_STRENGTH2 (0X0001U) /* Drive Strength 2 */
3920#define ENUM_GPIO_DS_DS4_STRENGTH3 (0X0002U) /* Drive Strength 3 */
3921#define ENUM_GPIO_DS_DS4_STRENGTH4 (0X0003U) /* Drive Strength 4 */
3922#define ENUM_GPIO_DS_DS3_STRENGTH1 (0X0000U) /* Drive Strength 1 */
3923#define ENUM_GPIO_DS_DS3_STRENGTH2 (0X0001U) /* Drive Strength 2 */
3924#define ENUM_GPIO_DS_DS3_STRENGTH3 (0X0002U) /* Drive Strength 3 */
3925#define ENUM_GPIO_DS_DS3_STRENGTH4 (0X0003U) /* Drive Strength 4 */
3926#define ENUM_GPIO_DS_DS2_STRENGTH1 (0X0000U) /* Drive Strength 1 */
3927#define ENUM_GPIO_DS_DS2_STRENGTH2 (0X0001U) /* Drive Strength 2 */
3928#define ENUM_GPIO_DS_DS2_STRENGTH3 (0X0002U) /* Drive Strength 3 */
3929#define ENUM_GPIO_DS_DS2_STRENGTH4 (0X0003U) /* Drive Strength 4 */
3930#define ENUM_GPIO_DS_DS1_STRENGTH1 (0X0000U) /* Drive Strength 1 */
3931#define ENUM_GPIO_DS_DS1_STRENGTH2 (0X0001U) /* Drive Strength 2 */
3932#define ENUM_GPIO_DS_DS1_STRENGTH3 (0X0002U) /* Drive Strength 3 */
3933#define ENUM_GPIO_DS_DS1_STRENGTH4 (0X0003U) /* Drive Strength 4 */
3934#define ENUM_GPIO_DS_DS0_STRENGTH1 (0X0000U) /* Drive Strength 1 */
3935#define ENUM_GPIO_DS_DS0_STRENGTH2 (0X0001U) /* Drive Strength 2 */
3936#define ENUM_GPIO_DS_DS0_STRENGTH3 (0X0002U) /* Drive Strength 3 */
3937#define ENUM_GPIO_DS_DS0_STRENGTH4 (0X0003U) /* Drive Strength 4 */
3938
3939/* ----------------------------------------------------------------------------------------------------
3940 PWR Value Description
3941 ---------------------------------------------------------------------------------------------------- */
3942#define BITP_GPIO_PWR_PWR (0U) /* Pad Power Select */
3943#define BITL_GPIO_PWR_PWR (8U) /* Pad Power Select */
3944#define BITM_GPIO_PWR_PWR (0XFFU) /* Pad Power Select */
3945
3946/* ----------------------------------------------------------------------------------------------------
3947 POL Value Description
3948 ---------------------------------------------------------------------------------------------------- */
3949#define BITP_GPIO_POL_INTPOL (0U) /* Parametric Output */
3950#define BITL_GPIO_POL_INTPOL (8U) /* Parametric Output */
3951#define BITM_GPIO_POL_INTPOL (0XFFU) /* Parametric Output */
3952
3953/* ----------------------------------------------------------------------------------------------------
3954 IENA Value Description
3955 ---------------------------------------------------------------------------------------------------- */
3956#define BITP_GPIO_IENA_INTAEN (0U) /* InterruptA Enable */
3957#define BITL_GPIO_IENA_INTAEN (8U) /* InterruptA Enable */
3958#define BITM_GPIO_IENA_INTAEN (0XFFU) /* InterruptA Enable */
3959
3960/* ----------------------------------------------------------------------------------------------------
3961 IENB Value Description
3962 ---------------------------------------------------------------------------------------------------- */
3963#define BITP_GPIO_IENB_INTBEN (0U) /* InterruptA Enable */
3964#define BITL_GPIO_IENB_INTBEN (8U) /* InterruptA Enable */
3965#define BITM_GPIO_IENB_INTBEN (0XFFU) /* InterruptA Enable */
3966
3967/* ----------------------------------------------------------------------------------------------------
3968 INT Value Description
3969 ---------------------------------------------------------------------------------------------------- */
3970#define BITP_GPIO_INT_INTSTATUS (0U) /* Interrupt Status */
3971#define BITL_GPIO_INT_INTSTATUS (8U) /* Interrupt Status */
3972#define BITM_GPIO_INT_INTSTATUS (0XFFU) /* Interrupt Status */
3973
3974#endif /* end ifndef GPIO_ADDR_RDEF_H_ */
3975
3976
3977#ifndef SPI_ADDR_RDEF_H_
3978#define SPI_ADDR_RDEF_H_ /* SPI: Serial Peripheral Interface */
3979
3980/* ====================================================================================================
3981 SPI Module Instances Address and Mask Definitions
3982 ==================================================================================================== */
3983#define INST_SPI0 (0X40054000U) /* spi0: */
3984#define INST_SPI1 (0X40058000U) /* spi1: */
3985#define INST_SPI2 (0X4005C000U) /* spi2: */
3986
3987#define MASK_SPI (0X000000FFU) /* SPI: Serial Peripheral Interface */
3988
3989/* ====================================================================================================
3990 SPI Module Register Address Offset Definitions
3991 ==================================================================================================== */
3992#define IDX_SPI_STAT (0X00U) /* Status */
3993#define IDX_SPI_RX (0X04U) /* Receive */
3994#define IDX_SPI_TX (0X08U) /* Transmit */
3995#define IDX_SPI_DIV (0X0CU) /* SPI Baud Rate Selection */
3996#define IDX_SPI_CTL (0X10U) /* SPI Configuration 1 */
3997#define IDX_SPI_IEN (0X14U) /* SPI Configuration 2 */
3998#define IDX_SPI_CNT (0X18U) /* Transfer Byte Count */
3999#define IDX_SPI_DMA (0X1CU) /* SPI DMA Enable */
4000#define IDX_SPI_FIFOSTAT (0X20U) /* FIFO Status */
4001#define IDX_SPI_RDCTL (0X24U) /* Read Control */
4002#define IDX_SPI_FLOWCTL (0X28U) /* Flow Control */
4003#define IDX_SPI_WAITTMR (0X2CU) /* Wait Timer for Flow Control */
4004#define IDX_SPI_CSOVERRIDE (0X34U) /* Chip-Select Override */
4005
4006/* ====================================================================================================
4007 SPI Module Register ResetValue Definitions
4008 ==================================================================================================== */
4009#define RSTVAL_SPI_STAT (0X800)
4010#define RSTVAL_SPI_RX (0X0)
4011#define RSTVAL_SPI_TX (0X0)
4012#define RSTVAL_SPI_DIV (0X0)
4013#define RSTVAL_SPI_CTL (0X0)
4014#define RSTVAL_SPI_IEN (0X0)
4015#define RSTVAL_SPI_CNT (0X0)
4016#define RSTVAL_SPI_DMA (0X0)
4017#define RSTVAL_SPI_FIFOSTAT (0X0)
4018#define RSTVAL_SPI_RDCTL (0X0)
4019#define RSTVAL_SPI_FLOWCTL (0X0)
4020#define RSTVAL_SPI_WAITTMR (0X0)
4021#define RSTVAL_SPI_CSOVERRIDE (0X0)
4022
4023/* ====================================================================================================
4024 SPI Module Register BitPositions, Lengths, Masks and Enumerations Definitions
4025 ==================================================================================================== */
4026
4027/* ----------------------------------------------------------------------------------------------------
4028 STAT Value Description
4029 ---------------------------------------------------------------------------------------------------- */
4030#define BITP_SPI_STAT_IRQ (0U) /* SPI Interrupt Status */
4031#define BITL_SPI_STAT_IRQ (1U) /* SPI Interrupt Status */
4032#define BITM_SPI_STAT_IRQ (0X0001U) /* SPI Interrupt Status */
4033#define BITP_SPI_STAT_XFRDONE (1U) /* SPI Transfer Completion */
4034#define BITL_SPI_STAT_XFRDONE (1U) /* SPI Transfer Completion */
4035#define BITM_SPI_STAT_XFRDONE (0X0002U) /* SPI Transfer Completion */
4036#define BITP_SPI_STAT_TXEMPTY (2U) /* SPI Tx FIFO Empty Interrupt */
4037#define BITL_SPI_STAT_TXEMPTY (1U) /* SPI Tx FIFO Empty Interrupt */
4038#define BITM_SPI_STAT_TXEMPTY (0X0004U) /* SPI Tx FIFO Empty Interrupt */
4039#define BITP_SPI_STAT_TXDONE (3U) /* SPI Tx Done in Read Command Mode */
4040#define BITL_SPI_STAT_TXDONE (1U) /* SPI Tx Done in Read Command Mode */
4041#define BITM_SPI_STAT_TXDONE (0X0008U) /* SPI Tx Done in Read Command Mode */
4042#define BITP_SPI_STAT_TXUNDR (4U) /* SPI Tx FIFO Underflow */
4043#define BITL_SPI_STAT_TXUNDR (1U) /* SPI Tx FIFO Underflow */
4044#define BITM_SPI_STAT_TXUNDR (0X0010U) /* SPI Tx FIFO Underflow */
4045#define BITP_SPI_STAT_TXIRQ (5U) /* SPI Tx IRQ */
4046#define BITL_SPI_STAT_TXIRQ (1U) /* SPI Tx IRQ */
4047#define BITM_SPI_STAT_TXIRQ (0X0020U) /* SPI Tx IRQ */
4048#define BITP_SPI_STAT_RXIRQ (6U) /* SPI Rx IRQ */
4049#define BITL_SPI_STAT_RXIRQ (1U) /* SPI Rx IRQ */
4050#define BITM_SPI_STAT_RXIRQ (0X0040U) /* SPI Rx IRQ */
4051#define BITP_SPI_STAT_RXOVR (7U) /* SPI Rx FIFO Overflow */
4052#define BITL_SPI_STAT_RXOVR (1U) /* SPI Rx FIFO Overflow */
4053#define BITM_SPI_STAT_RXOVR (0X0080U) /* SPI Rx FIFO Overflow */
4054#define BITP_SPI_STAT_CS (11U) /* CS Status */
4055#define BITL_SPI_STAT_CS (1U) /* CS Status */
4056#define BITM_SPI_STAT_CS (0X0800U) /* CS Status */
4057#define BITP_SPI_STAT_CSERR (12U) /* Detected a CS Error Condition in Slave Mode */
4058#define BITL_SPI_STAT_CSERR (1U) /* Detected a CS Error Condition in Slave Mode */
4059#define BITM_SPI_STAT_CSERR (0X1000U) /* Detected a CS Error Condition in Slave Mode */
4060#define BITP_SPI_STAT_CSRISE (13U) /* Detected a Rising Edge on CS, in Slave CON Mode */
4061#define BITL_SPI_STAT_CSRISE (1U) /* Detected a Rising Edge on CS, in Slave CON Mode */
4062#define BITM_SPI_STAT_CSRISE (0X2000U) /* Detected a Rising Edge on CS, in Slave CON Mode */
4063#define BITP_SPI_STAT_CSFALL (14U) /* Detected a Falling Edge on CS, in Slave CON Mode */
4064#define BITL_SPI_STAT_CSFALL (1U) /* Detected a Falling Edge on CS, in Slave CON Mode */
4065#define BITM_SPI_STAT_CSFALL (0X4000U) /* Detected a Falling Edge on CS, in Slave CON Mode */
4066#define BITP_SPI_STAT_RDY (15U) /* Detected an Edge on Ready Indicator for Flow-control */
4067#define BITL_SPI_STAT_RDY (1U) /* Detected an Edge on Ready Indicator for Flow-control */
4068#define BITM_SPI_STAT_RDY (0X8000U) /* Detected an Edge on Ready Indicator for Flow-control */
4069
4070/* ----------------------------------------------------------------------------------------------------
4071 RX Value Description
4072 ---------------------------------------------------------------------------------------------------- */
4073#define BITP_SPI_RX_BYTE1 (0U) /* 8-bit Receive Buffer */
4074#define BITL_SPI_RX_BYTE1 (8U) /* 8-bit Receive Buffer */
4075#define BITM_SPI_RX_BYTE1 (0X00FFU) /* 8-bit Receive Buffer */
4076#define BITP_SPI_RX_BYTE2 (8U) /* 8-bit Receive Buffer, Used Only in DMA Modes */
4077#define BITL_SPI_RX_BYTE2 (8U) /* 8-bit Receive Buffer, Used Only in DMA Modes */
4078#define BITM_SPI_RX_BYTE2 (0XFF00U) /* 8-bit Receive Buffer, Used Only in DMA Modes */
4079
4080/* ----------------------------------------------------------------------------------------------------
4081 TX Value Description
4082 ---------------------------------------------------------------------------------------------------- */
4083#define BITP_SPI_TX_BYTE1 (0U) /* 8-bit Transmit Buffer */
4084#define BITL_SPI_TX_BYTE1 (8U) /* 8-bit Transmit Buffer */
4085#define BITM_SPI_TX_BYTE1 (0X00FFU) /* 8-bit Transmit Buffer */
4086#define BITP_SPI_TX_BYTE2 (8U) /* 8-bit Transmit Buffer, Used Only in DMA Modes */
4087#define BITL_SPI_TX_BYTE2 (8U) /* 8-bit Transmit Buffer, Used Only in DMA Modes */
4088#define BITM_SPI_TX_BYTE2 (0XFF00U) /* 8-bit Transmit Buffer, Used Only in DMA Modes */
4089
4090/* ----------------------------------------------------------------------------------------------------
4091 DIV Value Description
4092 ---------------------------------------------------------------------------------------------------- */
4093#define BITP_SPI_DIV_DIV (0U) /* SPI Clock Divider */
4094#define BITL_SPI_DIV_DIV (6U) /* SPI Clock Divider */
4095#define BITM_SPI_DIV_DIV (0X003FU) /* SPI Clock Divider */
4096#define BITP_SPI_DIV_SFR (8U) /* Slave Free Run Mode */
4097#define BITL_SPI_DIV_SFR (1U) /* Slave Free Run Mode */
4098#define BITM_SPI_DIV_SFR (0X0100U) /* Slave Free Run Mode */
4099
4100/* ----------------------------------------------------------------------------------------------------
4101 CTL Value Description
4102 ---------------------------------------------------------------------------------------------------- */
4103#define BITP_SPI_CTL_SPIEN (0U) /* SPI Enable */
4104#define BITL_SPI_CTL_SPIEN (1U) /* SPI Enable */
4105#define BITM_SPI_CTL_SPIEN (0X0001U) /* SPI Enable */
4106#define BITP_SPI_CTL_MASEN (1U) /* Master Mode Enable */
4107#define BITL_SPI_CTL_MASEN (1U) /* Master Mode Enable */
4108#define BITM_SPI_CTL_MASEN (0X0002U) /* Master Mode Enable */
4109#define BITP_SPI_CTL_CPHA (2U) /* Serial Clock Phase Mode */
4110#define BITL_SPI_CTL_CPHA (1U) /* Serial Clock Phase Mode */
4111#define BITM_SPI_CTL_CPHA (0X0004U) /* Serial Clock Phase Mode */
4112#define BITP_SPI_CTL_CPOL (3U) /* Serial Clock Polarity */
4113#define BITL_SPI_CTL_CPOL (1U) /* Serial Clock Polarity */
4114#define BITM_SPI_CTL_CPOL (0X0008U) /* Serial Clock Polarity */
4115#define BITP_SPI_CTL_WOM (4U) /* SPI Wired or Mode */
4116#define BITL_SPI_CTL_WOM (1U) /* SPI Wired or Mode */
4117#define BITM_SPI_CTL_WOM (0X0010U) /* SPI Wired or Mode */
4118#define BITP_SPI_CTL_LSB (5U) /* LSB First Transfer Enable */
4119#define BITL_SPI_CTL_LSB (1U) /* LSB First Transfer Enable */
4120#define BITM_SPI_CTL_LSB (0X0020U) /* LSB First Transfer Enable */
4121#define BITP_SPI_CTL_TIM (6U) /* SPI Transfer and Interrupt Mode */
4122#define BITL_SPI_CTL_TIM (1U) /* SPI Transfer and Interrupt Mode */
4123#define BITM_SPI_CTL_TIM (0X0040U) /* SPI Transfer and Interrupt Mode */
4124#define BITP_SPI_CTL_ZEN (7U) /* Transmit Zeros Enable */
4125#define BITL_SPI_CTL_ZEN (1U) /* Transmit Zeros Enable */
4126#define BITM_SPI_CTL_ZEN (0X0080U) /* Transmit Zeros Enable */
4127#define BITP_SPI_CTL_RXOF (8U) /* RX Overflow Overwrite Enable */
4128#define BITL_SPI_CTL_RXOF (1U) /* RX Overflow Overwrite Enable */
4129#define BITM_SPI_CTL_RXOF (0X0100U) /* RX Overflow Overwrite Enable */
4130#define BITP_SPI_CTL_OEN (9U) /* Slave MISO Output Enable */
4131#define BITL_SPI_CTL_OEN (1U) /* Slave MISO Output Enable */
4132#define BITM_SPI_CTL_OEN (0X0200U) /* Slave MISO Output Enable */
4133#define BITP_SPI_CTL_LOOPBACK (10U) /* Loopback Enable */
4134#define BITL_SPI_CTL_LOOPBACK (1U) /* Loopback Enable */
4135#define BITM_SPI_CTL_LOOPBACK (0X0400U) /* Loopback Enable */
4136#define BITP_SPI_CTL_CON (11U) /* Continuous Transfer Enable */
4137#define BITL_SPI_CTL_CON (1U) /* Continuous Transfer Enable */
4138#define BITM_SPI_CTL_CON (0X0800U) /* Continuous Transfer Enable */
4139#define BITP_SPI_CTL_RFLUSH (12U) /* SPI Rx FIFO Flush Enable */
4140#define BITL_SPI_CTL_RFLUSH (1U) /* SPI Rx FIFO Flush Enable */
4141#define BITM_SPI_CTL_RFLUSH (0X1000U) /* SPI Rx FIFO Flush Enable */
4142#define BITP_SPI_CTL_TFLUSH (13U) /* SPI Tx FIFO Flush Enable */
4143#define BITL_SPI_CTL_TFLUSH (1U) /* SPI Tx FIFO Flush Enable */
4144#define BITM_SPI_CTL_TFLUSH (0X2000U) /* SPI Tx FIFO Flush Enable */
4145#define BITP_SPI_CTL_CSRST (14U) /* Reset Mode for CS Error Bit */
4146#define BITL_SPI_CTL_CSRST (1U) /* Reset Mode for CS Error Bit */
4147#define BITM_SPI_CTL_CSRST (0X4000U) /* Reset Mode for CS Error Bit */
4148
4149/* ----------------------------------------------------------------------------------------------------
4150 IEN Value Description
4151 ---------------------------------------------------------------------------------------------------- */
4152#define BITP_SPI_IEN_IRQMODE (0U) /* SPI IRQ Mode Bits */
4153#define BITL_SPI_IEN_IRQMODE (3U) /* SPI IRQ Mode Bits */
4154#define BITM_SPI_IEN_IRQMODE (0X0007U) /* SPI IRQ Mode Bits */
4155#define BITP_SPI_IEN_CS (8U) /* Enable Interrupt on Every CS Edge in Slave CON Mode */
4156#define BITL_SPI_IEN_CS (1U) /* Enable Interrupt on Every CS Edge in Slave CON Mode */
4157#define BITM_SPI_IEN_CS (0X0100U) /* Enable Interrupt on Every CS Edge in Slave CON Mode */
4158#define BITP_SPI_IEN_TXUNDR (9U) /* Tx-underflow Interrupt Enable */
4159#define BITL_SPI_IEN_TXUNDR (1U) /* Tx-underflow Interrupt Enable */
4160#define BITM_SPI_IEN_TXUNDR (0X0200U) /* Tx-underflow Interrupt Enable */
4161#define BITP_SPI_IEN_RXOVR (10U) /* Rx-overflow Interrupt Enable */
4162#define BITL_SPI_IEN_RXOVR (1U) /* Rx-overflow Interrupt Enable */
4163#define BITM_SPI_IEN_RXOVR (0X0400U) /* Rx-overflow Interrupt Enable */
4164#define BITP_SPI_IEN_RDY (11U) /* Ready Signal Edge Interrupt Enable */
4165#define BITL_SPI_IEN_RDY (1U) /* Ready Signal Edge Interrupt Enable */
4166#define BITM_SPI_IEN_RDY (0X0800U) /* Ready Signal Edge Interrupt Enable */
4167#define BITP_SPI_IEN_TXDONE (12U) /* SPI Transmit Done Interrupt Enable */
4168#define BITL_SPI_IEN_TXDONE (1U) /* SPI Transmit Done Interrupt Enable */
4169#define BITM_SPI_IEN_TXDONE (0X1000U) /* SPI Transmit Done Interrupt Enable */
4170#define BITP_SPI_IEN_XFRDONE (13U) /* SPI Transfer Completion Interrupt Enable */
4171#define BITL_SPI_IEN_XFRDONE (1U) /* SPI Transfer Completion Interrupt Enable */
4172#define BITM_SPI_IEN_XFRDONE (0X2000U) /* SPI Transfer Completion Interrupt Enable */
4173#define BITP_SPI_IEN_TXEMPTY (14U) /* Tx-FIFO Empty Interrupt Enable */
4174#define BITL_SPI_IEN_TXEMPTY (1U) /* Tx-FIFO Empty Interrupt Enable */
4175#define BITM_SPI_IEN_TXEMPTY (0X4000U) /* Tx-FIFO Empty Interrupt Enable */
4176
4177#define ENUM_SPI_IEN_IRQMODE_TX1RX1 (0X0000U) /* Interrupt Occurs After 1 Byte is Transfered or Received */
4178#define ENUM_SPI_IEN_IRQMODE_TX2RX2 (0X0001U) /* Interrupt Occurs After 2 Byte is Transfered or Received */
4179#define ENUM_SPI_IEN_IRQMODE_TX3RX3 (0X0002U) /* Interrupt Occurs After 3 Byte is Transfered or Received */
4180#define ENUM_SPI_IEN_IRQMODE_TX4RX4 (0X0003U) /* Interrupt Occurs After 4 Byte is Transfered or Received */
4181#define ENUM_SPI_IEN_IRQMODE_TX5RX5 (0X0004U) /* Interrupt Occurs After 5 Byte is Transfered or Received */
4182#define ENUM_SPI_IEN_IRQMODE_TX6RX6 (0X0005U) /* Interrupt Occurs After 6 Byte is Transfered or Received */
4183#define ENUM_SPI_IEN_IRQMODE_TX7RX7 (0X0006U) /* Interrupt Occurs After 7 Byte is Transfered or Received */
4184#define ENUM_SPI_IEN_IRQMODE_TX8RX8 (0X0007U) /* Interrupt Occurs After 8 Byte is Transfered or Received */
4185
4186/* ----------------------------------------------------------------------------------------------------
4187 CNT Value Description
4188 ---------------------------------------------------------------------------------------------------- */
4189#define BITP_SPI_CNT_VALUES (0U) /* Transfer Byte Count */
4190#define BITL_SPI_CNT_VALUES (14U) /* Transfer Byte Count */
4191#define BITM_SPI_CNT_VALUES (0X3FFFU) /* Transfer Byte Count */
4192#define BITP_SPI_CNT_FRAMECONT (15U) /* Continue Frame */
4193#define BITL_SPI_CNT_FRAMECONT (1U) /* Continue Frame */
4194#define BITM_SPI_CNT_FRAMECONT (0X8000U) /* Continue Frame */
4195
4196/* ----------------------------------------------------------------------------------------------------
4197 DMA Value Description
4198 ---------------------------------------------------------------------------------------------------- */
4199#define BITP_SPI_DMA_EN (0U) /* Enable DMA for Data Transfer */
4200#define BITL_SPI_DMA_EN (1U) /* Enable DMA for Data Transfer */
4201#define BITM_SPI_DMA_EN (0X0001U) /* Enable DMA for Data Transfer */
4202#define BITP_SPI_DMA_TXEN (1U) /* Enable Transmit DMA Request */
4203#define BITL_SPI_DMA_TXEN (1U) /* Enable Transmit DMA Request */
4204#define BITM_SPI_DMA_TXEN (0X0002U) /* Enable Transmit DMA Request */
4205#define BITP_SPI_DMA_RXEN (2U) /* Enable Receive DMA Request */
4206#define BITL_SPI_DMA_RXEN (1U) /* Enable Receive DMA Request */
4207#define BITM_SPI_DMA_RXEN (0X0004U) /* Enable Receive DMA Request */
4208
4209/* ----------------------------------------------------------------------------------------------------
4210 FIFOSTAT Value Description
4211 ---------------------------------------------------------------------------------------------------- */
4212#define BITP_SPI_FIFOSTAT_TX (0U) /* SPI Tx FIFO Status */
4213#define BITL_SPI_FIFOSTAT_TX (4U) /* SPI Tx FIFO Status */
4214#define BITM_SPI_FIFOSTAT_TX (0X000FU) /* SPI Tx FIFO Status */
4215#define BITP_SPI_FIFOSTAT_RX (8U) /* SPI Rx FIFO Status */
4216#define BITL_SPI_FIFOSTAT_RX (4U) /* SPI Rx FIFO Status */
4217#define BITM_SPI_FIFOSTAT_RX (0X0F00U) /* SPI Rx FIFO Status */
4218
4219#define ENUM_SPI_FIFOSTAT_RX_EMPTY (0X0000U) /* Rx FIFO Empty */
4220#define ENUM_SPI_FIFOSTAT_RX_ONE (0X0001U) /* 1 Valid Byte/half-word in Rx FIFO */
4221#define ENUM_SPI_FIFOSTAT_RX_TWO (0X0002U) /* 2 Valid Bytes/half-words in Rx FIFO */
4222#define ENUM_SPI_FIFOSTAT_RX_THREE (0X0003U) /* 3 Valid Bytes/half-words in Rx FIFO */
4223#define ENUM_SPI_FIFOSTAT_RX_FOUR (0X0004U) /* 4 Valid Bytes/half-words in Rx FIFO */
4224#define ENUM_SPI_FIFOSTAT_RX_FIVE (0X0005U) /* 5 Valid Bytes/half-words in Rx FIFO */
4225#define ENUM_SPI_FIFOSTAT_RX_SIX (0X0006U) /* 6 Valid Bytes/half-words in Rx FIFO */
4226#define ENUM_SPI_FIFOSTAT_RX_SEVEN (0X0007U) /* 7 Valid Bytes/half-words in Rx FIFO */
4227#define ENUM_SPI_FIFOSTAT_RX_FULL (0X0008U) /* 8 Valid Bytes/half-words in Rx FIFO (Rx FIFO Full) */
4228#define ENUM_SPI_FIFOSTAT_TX_EMPTY (0X0000U) /* Tx FIFO Empty */
4229#define ENUM_SPI_FIFOSTAT_TX_ONE (0X0001U) /* 1 Valid Byte/half-word in Tx FIFO */
4230#define ENUM_SPI_FIFOSTAT_TX_TWO (0X0002U) /* 2 Valid Bytes/half-words in Tx FIFO */
4231#define ENUM_SPI_FIFOSTAT_TX_THREE (0X0003U) /* 3 Valid Bytes/half-words in Tx FIFO */
4232#define ENUM_SPI_FIFOSTAT_TX_FOUR (0X0004U) /* 4 Valid Bytes/half-words in Tx FIFO */
4233#define ENUM_SPI_FIFOSTAT_TX_FIVE (0X0005U) /* 5 Valid Bytes/half-words in Tx FIFO */
4234#define ENUM_SPI_FIFOSTAT_TX_SIX (0X0006U) /* 6 Valid Bytes/half-words in Tx FIFO */
4235#define ENUM_SPI_FIFOSTAT_TX_SEVEN (0X0007U) /* 7 Valid Bytes/half-words in Tx FIFO */
4236#define ENUM_SPI_FIFOSTAT_TX_FULL (0X0008U) /* 8 Valid Bytes/half-words in Tx FIFO (Tx FIFO Full) */
4237
4238/* ----------------------------------------------------------------------------------------------------
4239 RDCTL Value Description
4240 ---------------------------------------------------------------------------------------------------- */
4241#define BITP_SPI_RDCTL_CMDEN (0U) /* Read Command Enable */
4242#define BITL_SPI_RDCTL_CMDEN (1U) /* Read Command Enable */
4243#define BITM_SPI_RDCTL_CMDEN (0X0001U) /* Read Command Enable */
4244#define BITP_SPI_RDCTL_OVERLAP (1U) /* Tx/Rx Overlap Mode */
4245#define BITL_SPI_RDCTL_OVERLAP (1U) /* Tx/Rx Overlap Mode */
4246#define BITM_SPI_RDCTL_OVERLAP (0X0002U) /* Tx/Rx Overlap Mode */
4247#define BITP_SPI_RDCTL_TXBYTES (2U) /* Transmit Byte Count Minus 1 for Read Command */
4248#define BITL_SPI_RDCTL_TXBYTES (4U) /* Transmit Byte Count Minus 1 for Read Command */
4249#define BITM_SPI_RDCTL_TXBYTES (0X003CU) /* Transmit Byte Count Minus 1 for Read Command */
4250#define BITP_SPI_RDCTL_THREEPIN (8U) /* Three Pin SPI Mode */
4251#define BITL_SPI_RDCTL_THREEPIN (1U) /* Three Pin SPI Mode */
4252#define BITM_SPI_RDCTL_THREEPIN (0X0100U) /* Three Pin SPI Mode */
4253
4254/* ----------------------------------------------------------------------------------------------------
4255 FLOWCTL Value Description
4256 ---------------------------------------------------------------------------------------------------- */
4257#define BITP_SPI_FLOWCTL_MODE (0U) /* Flow Control Mode */
4258#define BITL_SPI_FLOWCTL_MODE (2U) /* Flow Control Mode */
4259#define BITM_SPI_FLOWCTL_MODE (0X0003U) /* Flow Control Mode */
4260#define BITP_SPI_FLOWCTL_RDYPOL (4U) /* Polarity of RDY/MISO Line */
4261#define BITL_SPI_FLOWCTL_RDYPOL (1U) /* Polarity of RDY/MISO Line */
4262#define BITM_SPI_FLOWCTL_RDYPOL (0X0010U) /* Polarity of RDY/MISO Line */
4263#define BITP_SPI_FLOWCTL_RDBURSTSZ (6U) /* Read Data Burst Size Minus 1 */
4264#define BITL_SPI_FLOWCTL_RDBURSTSZ (10U) /* Read Data Burst Size Minus 1 */
4265#define BITM_SPI_FLOWCTL_RDBURSTSZ (0XFFC0U) /* Read Data Burst Size Minus 1 */
4266
4267#define ENUM_SPI_FLOWCTL_RDYPOL_HIGH (0X0000U) /* Polarity is Active HIGH. SPI Master Waits Until RDY/MISO Becomes HIGH. */
4268#define ENUM_SPI_FLOWCTL_RDYPOL_LOW (0X0001U) /* Polarity is Active LOW. SPI Master Waits Until RDY/MISO Becomes LOW. */
4269#define ENUM_SPI_FLOWCTL_MODE_DISABLE (0X0000U) /* Flow Control is Disabled. */
4270#define ENUM_SPI_FLOWCTL_MODE_TIMER (0X0001U) /* Flow Control is Based on Timer (WAIT_TMR). */
4271#define ENUM_SPI_FLOWCTL_MODE_RDY (0X0002U) /* Flow Control is Based on RDY Signal. */
4272#define ENUM_SPI_FLOWCTL_MODE_MISO (0X0003U) /* Flow Control is Based on MISO Pin. */
4273
4274/* ----------------------------------------------------------------------------------------------------
4275 WAITTMR Value Description
4276 ---------------------------------------------------------------------------------------------------- */
4277#define BITP_SPI_WAITTMR_TRIMS (0U) /* Wait Timer for Flow-control */
4278#define BITL_SPI_WAITTMR_TRIMS (16U) /* Wait Timer for Flow-control */
4279#define BITM_SPI_WAITTMR_TRIMS (0XFFFFU) /* Wait Timer for Flow-control */
4280
4281/* ----------------------------------------------------------------------------------------------------
4282 CSOVERRIDE Value Description
4283 ---------------------------------------------------------------------------------------------------- */
4284#define BITP_SPI_CSOVERRIDE_CTL (0U) /* CS Override Control */
4285#define BITL_SPI_CSOVERRIDE_CTL (2U) /* CS Override Control */
4286#define BITM_SPI_CSOVERRIDE_CTL (0X0003U) /* CS Override Control */
4287
4288#define ENUM_SPI_CSOVERRIDE_CTL_NOTFORCE (0X0000U) /* CS is Not Forced. */
4289#define ENUM_SPI_CSOVERRIDE_CTL_FORCETO1 (0X0001U) /* CS is Forced to Drive 1'b1. */
4290#define ENUM_SPI_CSOVERRIDE_CTL_FORCETO0 (0X0002U) /* CS is Forced to Drive 1'b0. */
4291
4292#endif /* end ifndef SPI_ADDR_RDEF_H_ */
4293
4294
4295#ifndef CLOCK_ADDR_RDEF_H_
4296#define CLOCK_ADDR_RDEF_H_ /* CLOCK: Clock Gating and Other Settings */
4297
4298/* ====================================================================================================
4299 CLOCK Module Instances Address and Mask Definitions
4300 ==================================================================================================== */
4301#define INST_CLK (0X40060000U) /* clk: */
4302
4303#define MASK_CLOCK (0X000003FFU) /* CLOCK: Clock Gating and Other Settings */
4304
4305/* ====================================================================================================
4306 CLOCK Module Register Address Offset Definitions
4307 ==================================================================================================== */
4308#define IDX_CLOCK_CLKCON0 (0X000U) /* Misc Clock Settings Register */
4309#define IDX_CLOCK_CLKCON1 (0X004U) /* Clock Dividers Register */
4310#define IDX_CLOCK_CLKSTAT0 (0X008U) /* Clocking Status */
4311
4312/* ====================================================================================================
4313 CLOCK Module Register ResetValue Definitions
4314 ==================================================================================================== */
4315#define RSTVAL_CLOCK_CLKCON0 (0X43C)
4316#define RSTVAL_CLOCK_CLKCON1 (0X48)
4317#define RSTVAL_CLOCK_CLKSTAT0 (0X0)
4318
4319/* ====================================================================================================
4320 CLOCK Module Register BitPositions, Lengths, Masks and Enumerations Definitions
4321 ==================================================================================================== */
4322
4323/* ----------------------------------------------------------------------------------------------------
4324 CLKCON0 Value Description
4325 ---------------------------------------------------------------------------------------------------- */
4326#define BITP_CLOCK_CLKCON0_CLKMUX (0U) /* Clock Mux Select */
4327#define BITL_CLOCK_CLKCON0_CLKMUX (2U) /* Clock Mux Select */
4328#define BITM_CLOCK_CLKCON0_CLKMUX (0X0003U) /* Clock Mux Select */
4329#define BITP_CLOCK_CLKCON0_CLKOUT (2U) /* GPIO CLK Out Select */
4330#define BITL_CLOCK_CLKCON0_CLKOUT (4U) /* GPIO CLK Out Select */
4331#define BITM_CLOCK_CLKCON0_CLKOUT (0X003CU) /* GPIO CLK Out Select */
4332#define BITP_CLOCK_CLKCON0_ANACLKMUX (7U) /* Mux Selection Analog Clock Source */
4333#define BITL_CLOCK_CLKCON0_ANACLKMUX (2U) /* Mux Selection Analog Clock Source */
4334#define BITM_CLOCK_CLKCON0_ANACLKMUX (0X0180U) /* Mux Selection Analog Clock Source */
4335#define BITP_CLOCK_CLKCON0_SPLLIE (9U) /* PLL Unlock and Lock Interrupt Enable */
4336#define BITL_CLOCK_CLKCON0_SPLLIE (1U) /* PLL Unlock and Lock Interrupt Enable */
4337#define BITM_CLOCK_CLKCON0_SPLLIE (0X0200U) /* PLL Unlock and Lock Interrupt Enable */
4338#define BITP_CLOCK_CLKCON0_ANAROOTCLKMUX (10U) /* Clock Mux Select */
4339#define BITL_CLOCK_CLKCON0_ANAROOTCLKMUX (2U) /* Clock Mux Select */
4340#define BITM_CLOCK_CLKCON0_ANAROOTCLKMUX (0X0C00U) /* Clock Mux Select */
4341
4342#define ENUM_CLOCK_CLKCON0_ANAROOTCLKMUX_OSC16 (0X0000U) /* 16MHz Oscillator Clock */
4343#define ENUM_CLOCK_CLKCON0_ANAROOTCLKMUX_OSC32 (0X0001U) /* 32MHz Oscillator Clock */
4344#define ENUM_CLOCK_CLKCON0_ANAROOTCLKMUX_PLL (0X0002U) /* PLL Clock */
4345#define ENUM_CLOCK_CLKCON0_ANAROOTCLKMUX_GPIO (0X0003U) /* External GPIO Clock */
4346#define ENUM_CLOCK_CLKCON0_SPLLIE_DIS (0X0000U) /* PLL Interrupt Will Not Be Generated */
4347#define ENUM_CLOCK_CLKCON0_SPLLIE_EN (0X0001U) /* PLL Interrupt Will Be Generated */
4348#define ENUM_CLOCK_CLKCON0_ANACLKMUX_HFOSC (0X0000U) /* Internal Oscillator is Selected (HFOSC) */
4349#define ENUM_CLOCK_CLKCON0_ANACLKMUX_GPIOCLK (0X0002U) /* GPIO Clock */
4350#define ENUM_CLOCK_CLKCON0_CLKOUT_HFOSC (0X0000U) /* HFOSC (16 MHz) */
4351#define ENUM_CLOCK_CLKCON0_CLKOUT_ROOT (0X0001U) /* Root Clock */
4352#define ENUM_CLOCK_CLKCON0_CLKOUT_LFOSC (0X0003U) /* 32K OSC */
4353#define ENUM_CLOCK_CLKCON0_CLKOUT_CORE (0X0004U) /* Core Clock */
4354#define ENUM_CLOCK_CLKCON0_CLKOUT_B0_PCLK (0X0005U) /* Bridge 0 Pclk */
4355#define ENUM_CLOCK_CLKCON0_CLKOUT_B1_PCLK (0X0006U) /* Bridge 1 PCLK */
4356#define ENUM_CLOCK_CLKCON0_CLKOUT_B2_PCLK (0X0007U) /* Bridge 2 PCLK */
4357#define ENUM_CLOCK_CLKCON0_CLKOUT_ANA_CLK (0X0008U) /* Analog Test Signal */
4358#define ENUM_CLOCK_CLKCON0_CLKOUT_T0 (0X0009U) /* Timer 0 Clock */
4359#define ENUM_CLOCK_CLKCON0_CLKOUT_WUT (0X000AU) /* Wake up Timer Clock */
4360#define ENUM_CLOCK_CLKCON0_CLKOUT_T3 (0X000BU) /* Timer 3 Clock */
4361#define ENUM_CLOCK_CLKCON0_CLKOUT_HCLKBUS (0X000CU) /* Hclk_bus */
4362#define ENUM_CLOCK_CLKCON0_CLKOUT_SPLL_CLK (0X000DU) /* SPLL clock */
4363#define ENUM_CLOCK_CLKCON0_CLKMUX_HFOSC (0X0000U) /* High Frequency Internal Oscillator (HFOSC) */
4364#define ENUM_CLOCK_CLKCON0_CLKMUX_SPLL (0X0001U) /* System PLL is Selected (160 MHz) */
4365#define ENUM_CLOCK_CLKCON0_CLKMUX_EXTCLK (0X0003U) /* External GPIO Port is Selected (ECLKIN) */
4366
4367/* ----------------------------------------------------------------------------------------------------
4368 CLKCON1 Value Description
4369 ---------------------------------------------------------------------------------------------------- */
4370#define BITP_CLOCK_CLKCON1_CDHCLK (0U) /* HCLK Divide Bits */
4371#define BITL_CLOCK_CLKCON1_CDHCLK (3U) /* HCLK Divide Bits */
4372#define BITM_CLOCK_CLKCON1_CDHCLK (0X0007U) /* HCLK Divide Bits */
4373#define BITP_CLOCK_CLKCON1_CDPCLK0 (3U) /* APB0 PCLK Divide Bits */
4374#define BITL_CLOCK_CLKCON1_CDPCLK0 (3U) /* APB0 PCLK Divide Bits */
4375#define BITM_CLOCK_CLKCON1_CDPCLK0 (0X0038U) /* APB0 PCLK Divide Bits */
4376#define BITP_CLOCK_CLKCON1_CDPCLK1 (6U) /* APB1 PCLK Divide Bits */
4377#define BITL_CLOCK_CLKCON1_CDPCLK1 (3U) /* APB1 PCLK Divide Bits */
4378#define BITM_CLOCK_CLKCON1_CDPCLK1 (0X01C0U) /* APB1 PCLK Divide Bits */
4379#define BITP_CLOCK_CLKCON1_CDADCCLK (9U) /* ADCCLK Divide Bits */
4380#define BITL_CLOCK_CLKCON1_CDADCCLK (3U) /* ADCCLK Divide Bits */
4381#define BITM_CLOCK_CLKCON1_CDADCCLK (0X0E00U) /* ADCCLK Divide Bits */
4382
4383#define ENUM_CLOCK_CLKCON1_CDADCCLK_DIV1 (0X0000U) /* DIV1. Divide by 1 (ADCCLK is Equal to Root Clock) */
4384#define ENUM_CLOCK_CLKCON1_CDADCCLK_DIV2 (0X0001U) /* DIV2. Divide by 2 (ADCCLK is Half the Frequency of Root Clock) */
4385#define ENUM_CLOCK_CLKCON1_CDADCCLK_DIV4 (0X0002U) /* DIV4. Divide by 4 (ADCCLK is Quarter the Frequency of Root Clock, 20 MHz) */
4386#define ENUM_CLOCK_CLKCON1_CDADCCLK_DIV8 (0X0003U) /* DIV8. Divide by 8 */
4387#define ENUM_CLOCK_CLKCON1_CDADCCLK_DIV16 (0X0004U) /* DIV16. Divide by 16 */
4388#define ENUM_CLOCK_CLKCON1_CDADCCLK_DIV32 (0X0005U) /* DIV32. Divide by 32 */
4389#define ENUM_CLOCK_CLKCON1_CDADCCLK_DIV64 (0X0006U) /* DIV64. Divide by 164 */
4390#define ENUM_CLOCK_CLKCON1_CDADCCLK_DIV128 (0X0007U) /* DIV128. Divide by 128 */
4391#define ENUM_CLOCK_CLKCON1_CDPCLK1_DIV1 (0X0000U) /* DIV1. Divide by 1 (PCLK is Equal to Root Clock) */
4392#define ENUM_CLOCK_CLKCON1_CDPCLK1_DIV2 (0X0001U) /* DIV2. Divide by 2 (PCLK is Half the Frequency of Root Clock) */
4393#define ENUM_CLOCK_CLKCON1_CDPCLK1_DIV4 (0X0002U) /* DIV4. Divide by 4 (PCLK is Quarter the Frequency of Root Clock, 20 MHz) */
4394#define ENUM_CLOCK_CLKCON1_CDPCLK1_DIV8 (0X0003U) /* DIV8. Divide by 8 */
4395#define ENUM_CLOCK_CLKCON1_CDPCLK1_DIV16 (0X0004U) /* DIV16. Divide by 16 */
4396#define ENUM_CLOCK_CLKCON1_CDPCLK1_DIV32 (0X0005U) /* DIV32. Divide by 32 */
4397#define ENUM_CLOCK_CLKCON1_CDPCLK1_DIV64 (0X0006U) /* DIV64. Divide by 164 */
4398#define ENUM_CLOCK_CLKCON1_CDPCLK1_DIV128 (0X0007U) /* DIV128. Divide by 128 */
4399#define ENUM_CLOCK_CLKCON1_CDPCLK0_DIV1 (0X0000U) /* DIV1. Divide by 1 (PCLK is Equal to Root Clock) */
4400#define ENUM_CLOCK_CLKCON1_CDPCLK0_DIV2 (0X0001U) /* DIV2. Divide by 2 (PCLK is Half the Frequency of Root Clock) */
4401#define ENUM_CLOCK_CLKCON1_CDPCLK0_DIV4 (0X0002U) /* DIV4. Divide by 4 (PCLK is Quarter the Frequency of Root Clock, 20 MHz) */
4402#define ENUM_CLOCK_CLKCON1_CDPCLK0_DIV8 (0X0003U) /* DIV8. Divide by 8 */
4403#define ENUM_CLOCK_CLKCON1_CDPCLK0_DIV16 (0X0004U) /* DIV16. Divide by 16 */
4404#define ENUM_CLOCK_CLKCON1_CDPCLK0_DIV32 (0X0005U) /* DIV32. Divide by 32 */
4405#define ENUM_CLOCK_CLKCON1_CDPCLK0_DIV64 (0X0006U) /* DIV64. Divide by 164 */
4406#define ENUM_CLOCK_CLKCON1_CDPCLK0_DIV128 (0X0007U) /* DIV128. Divide by 128 */
4407#define ENUM_CLOCK_CLKCON1_CDHCLK_DIV1 (0X0000U) /* DIV1. Divide by 1 (HCLK is Equal to Root Clock) */
4408#define ENUM_CLOCK_CLKCON1_CDHCLK_DIV2 (0X0001U) /* DIV2. Divide by 2 (HCLK is Half the Frequency of Root Clock) */
4409#define ENUM_CLOCK_CLKCON1_CDHCLK_DIV4 (0X0002U) /* DIV4. Divide by 4 (HCLK is Quarter the Frequency of Root Clock) */
4410#define ENUM_CLOCK_CLKCON1_CDHCLK_DIV8 (0X0003U) /* DIV8. Divide by 8 */
4411#define ENUM_CLOCK_CLKCON1_CDHCLK_DIV16 (0X0004U) /* DIV16.Divide by 16 */
4412#define ENUM_CLOCK_CLKCON1_CDHCLK_DIV32 (0X0005U) /* DIV32.Divide by 32 */
4413#define ENUM_CLOCK_CLKCON1_CDHCLK_DIV64 (0X0006U) /* DIV64.Divide by 64 */
4414#define ENUM_CLOCK_CLKCON1_CDHCLK_DIV128 (0X0007U) /* DIV128. Divide by 128 */
4415
4416/* ----------------------------------------------------------------------------------------------------
4417 CLKSTAT0 Value Description
4418 ---------------------------------------------------------------------------------------------------- */
4419#define BITP_CLOCK_CLKSTAT0_SPLLSTATUS (0U) /* System PLL Status */
4420#define BITL_CLOCK_CLKSTAT0_SPLLSTATUS (1U) /* System PLL Status */
4421#define BITM_CLOCK_CLKSTAT0_SPLLSTATUS (0X0001U) /* System PLL Status */
4422#define BITP_CLOCK_CLKSTAT0_SPLLLOCKCLR (1U) /* System PLL Lock */
4423#define BITL_CLOCK_CLKSTAT0_SPLLLOCKCLR (1U) /* System PLL Lock */
4424#define BITM_CLOCK_CLKSTAT0_SPLLLOCKCLR (0X0002U) /* System PLL Lock */
4425#define BITP_CLOCK_CLKSTAT0_SPLLUNLOCKCLR (2U) /* System PLL Unlock */
4426#define BITL_CLOCK_CLKSTAT0_SPLLUNLOCKCLR (1U) /* System PLL Unlock */
4427#define BITM_CLOCK_CLKSTAT0_SPLLUNLOCKCLR (0X0004U) /* System PLL Unlock */
4428#define BITP_CLOCK_CLKSTAT0_SPLLLOCK (3U) /* Sticky System PLL Lock Flag */
4429#define BITL_CLOCK_CLKSTAT0_SPLLLOCK (1U) /* Sticky System PLL Lock Flag */
4430#define BITM_CLOCK_CLKSTAT0_SPLLLOCK (0X0008U) /* Sticky System PLL Lock Flag */
4431#define BITP_CLOCK_CLKSTAT0_SPLLUNLOCK (4U) /* Sticky System PLL Unlock Flag */
4432#define BITL_CLOCK_CLKSTAT0_SPLLUNLOCK (1U) /* Sticky System PLL Unlock Flag */
4433#define BITM_CLOCK_CLKSTAT0_SPLLUNLOCK (0X0010U) /* Sticky System PLL Unlock Flag */
4434
4435#define ENUM_CLOCK_CLKSTAT0_SPLLUNLOCK_UNLOCKED (0X0000U) /* No PLL Lock Event Was Detected */
4436#define ENUM_CLOCK_CLKSTAT0_SPLLUNLOCK_LOCKED (0X0001U) /* A PLL Lock Event Was Detected */
4437#define ENUM_CLOCK_CLKSTAT0_SPLLLOCK_UNLOCKED (0X0000U) /* No PLL Lock Event Was Detected */
4438#define ENUM_CLOCK_CLKSTAT0_SPLLLOCK_LOCKED (0X0001U) /* A PLL Lock Event Was Detected */
4439#define ENUM_CLOCK_CLKSTAT0_SPLLUNLOCKCLR_NOLOSS (0X0000U) /* No Loss of PLL Lock Was Detected */
4440#define ENUM_CLOCK_CLKSTAT0_SPLLUNLOCKCLR_LOSS (0X0001U) /* A PLL Loss of Lock Was Detected */
4441#define ENUM_CLOCK_CLKSTAT0_SPLLLOCKCLR_UNLOCKED (0X0000U) /* No PLL Lock Event Was Detected */
4442#define ENUM_CLOCK_CLKSTAT0_SPLLLOCKCLR_LOCKED (0X0001U) /* A PLL Lock Event Was Detected */
4443#define ENUM_CLOCK_CLKSTAT0_SPLLSTATUS_UNLOCKED (0X0000U) /* The PLL is Not Locked or Not Properly Configured. the PLL is Not Ready for Use as the System Clock Source */
4444#define ENUM_CLOCK_CLKSTAT0_SPLLSTATUS_LOCKED (0X0001U) /* The PLL is Locked and is Ready for Use as the System Clock Source */
4445
4446#endif /* end ifndef CLOCK_ADDR_RDEF_H_ */
4447
4448
4449#ifndef PWM_ADDR_RDEF_H_
4450#define PWM_ADDR_RDEF_H_ /* PWM: PWM MMR */
4451
4452/* ====================================================================================================
4453 PWM Module Instances Address and Mask Definitions
4454 ==================================================================================================== */
4455#define INST_PWM (0X40064000U) /* pwm: */
4456
4457#define MASK_PWM (0XFFFFFFFFU) /* PWM: PWM MMR */
4458
4459/* ====================================================================================================
4460 PWM Module Register Address Offset Definitions
4461 ==================================================================================================== */
4462#define IDX_PWM_PWMCON0 (0X00000000U) /* PWM Control Register */
4463#define IDX_PWM_PWMCON1 (0X00000004U) /* ADC Conversion Start and Trip Control Register */
4464#define IDX_PWM_PWMICLR (0X00000008U) /* Hardware Trip Configuration Register */
4465#define IDX_PWM_PWM0COM0 (0X00000010U) /* Compare Register 0 for PWM0 and PWM1 */
4466#define IDX_PWM_PWM0COM1 (0X00000014U) /* Compare Register 1 for PWM0 and PWM1 */
4467#define IDX_PWM_PWM0COM2 (0X00000018U) /* Compare Register 2 for PWM0 and PWM1 */
4468#define IDX_PWM_PWM0LEN (0X0000001CU) /* Period Value Register for PWM0 and PWM1 */
4469#define IDX_PWM_PWM1COM0 (0X00000020U) /* Compare Register 0 for PWM2 and PWM3 */
4470#define IDX_PWM_PWM1COM1 (0X00000024U) /* Compare Register 1 for PWM2 and PWM3 */
4471#define IDX_PWM_PWM1COM2 (0X00000028U) /* Compare Register 2 for PWM2 and PWM3 */
4472#define IDX_PWM_PWM1LEN (0X0000002CU) /* Period Value Register for PWM2 and PWM3 */
4473#define IDX_PWM_PWM2COM0 (0X00000030U) /* Compare Register 0 for PWM4 and PWM5 */
4474#define IDX_PWM_PWM2COM1 (0X00000034U) /* Compare Register 1 for PWM4 and PWM5 */
4475#define IDX_PWM_PWM2COM2 (0X00000038U) /* Compare Register 2 for PWM4 and PWM5 */
4476#define IDX_PWM_PWM2LEN (0X0000003CU) /* Period Value Register for PWM4 and PWM5 */
4477
4478/* ====================================================================================================
4479 PWM Module Register ResetValue Definitions
4480 ==================================================================================================== */
4481#define RSTVAL_PWM_PWMCON0 (0X12)
4482#define RSTVAL_PWM_PWMCON1 (0X0)
4483#define RSTVAL_PWM_PWMICLR (0X0)
4484#define RSTVAL_PWM_PWM0COM0 (0X0)
4485#define RSTVAL_PWM_PWM0COM1 (0X0)
4486#define RSTVAL_PWM_PWM0COM2 (0X0)
4487#define RSTVAL_PWM_PWM0LEN (0X0)
4488#define RSTVAL_PWM_PWM1COM0 (0X0)
4489#define RSTVAL_PWM_PWM1COM1 (0X0)
4490#define RSTVAL_PWM_PWM1COM2 (0X0)
4491#define RSTVAL_PWM_PWM1LEN (0X0)
4492#define RSTVAL_PWM_PWM2COM0 (0X0)
4493#define RSTVAL_PWM_PWM2COM1 (0X0)
4494#define RSTVAL_PWM_PWM2COM2 (0X0)
4495#define RSTVAL_PWM_PWM2LEN (0X0)
4496
4497/* ====================================================================================================
4498 PWM Module Register BitPositions, Lengths, Masks and Enumerations Definitions
4499 ==================================================================================================== */
4500
4501/* ----------------------------------------------------------------------------------------------------
4502 PWMCON0 Value Description
4503 ---------------------------------------------------------------------------------------------------- */
4504#define BITP_PWM_PWMCON0_PWMEN (0U) /* Master Enable for PWM */
4505#define BITL_PWM_PWMCON0_PWMEN (1U) /* Master Enable for PWM */
4506#define BITM_PWM_PWMCON0_PWMEN (0X0001U) /* Master Enable for PWM */
4507#define BITP_PWM_PWMCON0_HMODE (1U) /* Set to Enable H-bridge Mode */
4508#define BITL_PWM_PWMCON0_HMODE (1U) /* Set to Enable H-bridge Mode */
4509#define BITM_PWM_PWMCON0_HMODE (0X0002U) /* Set to Enable H-bridge Mode */
4510#define BITP_PWM_PWMCON0_HDIR (2U) /* Direction Control When PWM is in H-bridge Mode */
4511#define BITL_PWM_PWMCON0_HDIR (1U) /* Direction Control When PWM is in H-bridge Mode */
4512#define BITM_PWM_PWMCON0_HDIR (0X0004U) /* Direction Control When PWM is in H-bridge Mode */
4513#define BITP_PWM_PWMCON0_LCOMP (3U) /* Signal to Load a New Set of Compare Register Values */
4514#define BITL_PWM_PWMCON0_LCOMP (1U) /* Signal to Load a New Set of Compare Register Values */
4515#define BITM_PWM_PWMCON0_LCOMP (0X0008U) /* Signal to Load a New Set of Compare Register Values */
4516#define BITP_PWM_PWMCON0_HOFF (4U) /* Set to Turn off the High-side for Pair 0/1 in H-bridge Mode */
4517#define BITL_PWM_PWMCON0_HOFF (1U) /* Set to Turn off the High-side for Pair 0/1 in H-bridge Mode */
4518#define BITM_PWM_PWMCON0_HOFF (0X0010U) /* Set to Turn off the High-side for Pair 0/1 in H-bridge Mode */
4519#define BITP_PWM_PWMCON0_POINV (5U) /* Set to Invert PWM Outputs for Pair 0/1 in H-bridge Mode */
4520#define BITL_PWM_PWMCON0_POINV (1U) /* Set to Invert PWM Outputs for Pair 0/1 in H-bridge Mode */
4521#define BITM_PWM_PWMCON0_POINV (0X0020U) /* Set to Invert PWM Outputs for Pair 0/1 in H-bridge Mode */
4522#define BITP_PWM_PWMCON0_PWMCMP (6U) /* PWM Clock Prescaler. Sets UCLK Divider. */
4523#define BITL_PWM_PWMCON0_PWMCMP (3U) /* PWM Clock Prescaler. Sets UCLK Divider. */
4524#define BITM_PWM_PWMCON0_PWMCMP (0X01C0U) /* PWM Clock Prescaler. Sets UCLK Divider. */
4525#define BITP_PWM_PWMCON0_ENA (9U) /* Enable for Pair 0 and 1 When HOFF=0 and HMODE=1 */
4526#define BITL_PWM_PWMCON0_ENA (1U) /* Enable for Pair 0 and 1 When HOFF=0 and HMODE=1 */
4527#define BITM_PWM_PWMCON0_ENA (0X0200U) /* Enable for Pair 0 and 1 When HOFF=0 and HMODE=1 */
4528#define BITP_PWM_PWMCON0_PWMIEN (10U) /* Set to Enable Interrupts for PWM */
4529#define BITL_PWM_PWMCON0_PWMIEN (1U) /* Set to Enable Interrupts for PWM */
4530#define BITM_PWM_PWMCON0_PWMIEN (0X0400U) /* Set to Enable Interrupts for PWM */
4531#define BITP_PWM_PWMCON0_PWM1INV (11U) /* Set to Invert PWM1 Output */
4532#define BITL_PWM_PWMCON0_PWM1INV (1U) /* Set to Invert PWM1 Output */
4533#define BITM_PWM_PWMCON0_PWM1INV (0X0800U) /* Set to Invert PWM1 Output */
4534#define BITP_PWM_PWMCON0_PWM3INV (12U) /* Set to Invert PWM3 Output */
4535#define BITL_PWM_PWMCON0_PWM3INV (1U) /* Set to Invert PWM3 Output */
4536#define BITM_PWM_PWMCON0_PWM3INV (0X1000U) /* Set to Invert PWM3 Output */
4537#define BITP_PWM_PWMCON0_PWM5INV (13U) /* Set to Invert PWM5 Output */
4538#define BITL_PWM_PWMCON0_PWM5INV (1U) /* Set to Invert PWM5 Output */
4539#define BITM_PWM_PWMCON0_PWM5INV (0X2000U) /* Set to Invert PWM5 Output */
4540#define BITP_PWM_PWMCON0_SYNC (15U) /* Set to Enable PWM Synchronization from the SYNC Pin */
4541#define BITL_PWM_PWMCON0_SYNC (1U) /* Set to Enable PWM Synchronization from the SYNC Pin */
4542#define BITM_PWM_PWMCON0_SYNC (0X8000U) /* Set to Enable PWM Synchronization from the SYNC Pin */
4543
4544#define ENUM_PWM_PWMCON0_SYNC_DIS (0X0000U) /* Ignore Transition from the SYNC Pin */
4545#define ENUM_PWM_PWMCON0_SYNC_EN (0X0001U) /* All PWM Counters are Reset on the Next Clock Cycle After Detection of a Falling Edge from SYNC Pin */
4546#define ENUM_PWM_PWMCON0_ENA_DIS (0X0000U) /* Disable Pair 0 and 1 */
4547#define ENUM_PWM_PWMCON0_ENA_EN (0X0001U) /* Enable Pair 0 and 1 */
4548#define ENUM_PWM_PWMCON0_PWMCMP_DIV2 (0X0000U) /* UCLK/2 */
4549#define ENUM_PWM_PWMCON0_PWMCMP_DIV4 (0X0001U) /* UCLK/4 */
4550#define ENUM_PWM_PWMCON0_PWMCMP_DIV8 (0X0002U) /* UCLK/8 */
4551#define ENUM_PWM_PWMCON0_PWMCMP_DIV16 (0X0003U) /* UCLK/16 */
4552#define ENUM_PWM_PWMCON0_PWMCMP_DIV32 (0X0004U) /* UCLK/32 */
4553#define ENUM_PWM_PWMCON0_PWMCMP_DIV64 (0X0005U) /* UCLK/64 */
4554#define ENUM_PWM_PWMCON0_PWMCMP_DIV128 (0X0006U) /* UCLK/128 */
4555#define ENUM_PWM_PWMCON0_PWMCMP_DIV256 (0X0007U) /* UCLK/256 */
4556#define ENUM_PWM_PWMCON0_LCOMP_DIS (0X0000U) /* Use the Values Previously Store in the Compare and Length Registers */
4557#define ENUM_PWM_PWMCON0_LCOMP_EN (0X0001U) /* Load the Internal Compare Registers with Values Stored in the PWMxCOMx and PWMxLEN Registers */
4558#define ENUM_PWM_PWMCON0_HDIR_DIS (0X0000U) /* PWM2 and PWM3 Act as Output Signals While PWM0 and PWM1 are Held Low */
4559#define ENUM_PWM_PWMCON0_HDIR_EN (0X0001U) /* PWM0 and PWM1 Act as Output Signals While PWM2 and PWM3 are Held Low */
4560#define ENUM_PWM_PWMCON0_PWMEN_DIS (0X0000U) /* Disable All PWM Outputs */
4561#define ENUM_PWM_PWMCON0_PWMEN_EN (0X0001U) /* Enable All PWM Outputs */
4562
4563/* ----------------------------------------------------------------------------------------------------
4564 PWMCON1 Value Description
4565 ---------------------------------------------------------------------------------------------------- */
4566#define BITP_PWM_PWMCON1_REVREG0 (4U) /* Reserved */
4567#define BITL_PWM_PWMCON1_REVREG0 (2U) /* Reserved */
4568#define BITM_PWM_PWMCON1_REVREG0 (0X0030U) /* Reserved */
4569#define BITP_PWM_PWMCON1_TRIP_EN (6U) /* Set to Enable PWM Trip Functionality */
4570#define BITL_PWM_PWMCON1_TRIP_EN (1U) /* Set to Enable PWM Trip Functionality */
4571#define BITM_PWM_PWMCON1_TRIP_EN (0X0040U) /* Set to Enable PWM Trip Functionality */
4572#define BITP_PWM_PWMCON1_REVREG1 (8U) /* Reserved. Return 0 on Reads */
4573#define BITL_PWM_PWMCON1_REVREG1 (8U) /* Reserved. Return 0 on Reads */
4574#define BITM_PWM_PWMCON1_REVREG1 (0XFF00U) /* Reserved. Return 0 on Reads */
4575
4576/* ----------------------------------------------------------------------------------------------------
4577 PWMICLR Value Description
4578 ---------------------------------------------------------------------------------------------------- */
4579#define BITP_PWM_PWMICLR_PWM0 (0U) /* Write a 1 to Clear Latched IRQPWM0 Interrupt. */
4580#define BITL_PWM_PWMICLR_PWM0 (1U) /* Write a 1 to Clear Latched IRQPWM0 Interrupt. */
4581#define BITM_PWM_PWMICLR_PWM0 (0X0001U) /* Write a 1 to Clear Latched IRQPWM0 Interrupt. */
4582#define BITP_PWM_PWMICLR_PWM1 (1U) /* Write a 1 to Clear Latched IRQPWM1 Interrupt. */
4583#define BITL_PWM_PWMICLR_PWM1 (1U) /* Write a 1 to Clear Latched IRQPWM1 Interrupt. */
4584#define BITM_PWM_PWMICLR_PWM1 (0X0002U) /* Write a 1 to Clear Latched IRQPWM1 Interrupt. */
4585#define BITP_PWM_PWMICLR_PWM2 (2U) /* Write a 1 to Clear Latched IRQPWM2 Interrupt. */
4586#define BITL_PWM_PWMICLR_PWM2 (1U) /* Write a 1 to Clear Latched IRQPWM2 Interrupt. */
4587#define BITM_PWM_PWMICLR_PWM2 (0X0004U) /* Write a 1 to Clear Latched IRQPWM2 Interrupt. */
4588#define BITP_PWM_PWMICLR_TRIP (4U) /* Write a 1 to Clear Latched IRQPWMTrip Interrupt. */
4589#define BITL_PWM_PWMICLR_TRIP (1U) /* Write a 1 to Clear Latched IRQPWMTrip Interrupt. */
4590#define BITM_PWM_PWMICLR_TRIP (0X0010U) /* Write a 1 to Clear Latched IRQPWMTrip Interrupt. */
4591#define BITP_PWM_PWMICLR_REVREG2 (5U) /* Reserved. Return 0 on Reads */
4592#define BITL_PWM_PWMICLR_REVREG2 (11U) /* Reserved. Return 0 on Reads */
4593#define BITM_PWM_PWMICLR_REVREG2 (0XFFE0U) /* Reserved. Return 0 on Reads */
4594
4595/* ----------------------------------------------------------------------------------------------------
4596 PWM0COM0 Value Description
4597 ---------------------------------------------------------------------------------------------------- */
4598#define BITP_PWM_PWM0COM0_PWM0COM0 (0U) /* Compare Register 0 for PWM0 and PWM1 */
4599#define BITL_PWM_PWM0COM0_PWM0COM0 (16U) /* Compare Register 0 for PWM0 and PWM1 */
4600#define BITM_PWM_PWM0COM0_PWM0COM0 (0XFFFFU) /* Compare Register 0 for PWM0 and PWM1 */
4601
4602/* ----------------------------------------------------------------------------------------------------
4603 PWM0COM1 Value Description
4604 ---------------------------------------------------------------------------------------------------- */
4605#define BITP_PWM_PWM0COM1_PWM0COM1 (0U) /* Compare Register 1 for PWM0 and PWM1 */
4606#define BITL_PWM_PWM0COM1_PWM0COM1 (16U) /* Compare Register 1 for PWM0 and PWM1 */
4607#define BITM_PWM_PWM0COM1_PWM0COM1 (0XFFFFU) /* Compare Register 1 for PWM0 and PWM1 */
4608
4609/* ----------------------------------------------------------------------------------------------------
4610 PWM0COM2 Value Description
4611 ---------------------------------------------------------------------------------------------------- */
4612#define BITP_PWM_PWM0COM2_PWM0COM2 (0U) /* Compare Register 2 for PWM0 and PWM1 */
4613#define BITL_PWM_PWM0COM2_PWM0COM2 (16U) /* Compare Register 2 for PWM0 and PWM1 */
4614#define BITM_PWM_PWM0COM2_PWM0COM2 (0XFFFFU) /* Compare Register 2 for PWM0 and PWM1 */
4615
4616/* ----------------------------------------------------------------------------------------------------
4617 PWM0LEN Value Description
4618 ---------------------------------------------------------------------------------------------------- */
4619#define BITP_PWM_PWM0LEN_PWM0LEN (0U) /* Period Value Register for PWM0 and PWM1 */
4620#define BITL_PWM_PWM0LEN_PWM0LEN (16U) /* Period Value Register for PWM0 and PWM1 */
4621#define BITM_PWM_PWM0LEN_PWM0LEN (0XFFFFU) /* Period Value Register for PWM0 and PWM1 */
4622
4623/* ----------------------------------------------------------------------------------------------------
4624 PWM1COM0 Value Description
4625 ---------------------------------------------------------------------------------------------------- */
4626#define BITP_PWM_PWM1COM0_PWM1COM0 (0U) /* Compare Register 0 for PWM2 and PWM3 */
4627#define BITL_PWM_PWM1COM0_PWM1COM0 (16U) /* Compare Register 0 for PWM2 and PWM3 */
4628#define BITM_PWM_PWM1COM0_PWM1COM0 (0XFFFFU) /* Compare Register 0 for PWM2 and PWM3 */
4629
4630/* ----------------------------------------------------------------------------------------------------
4631 PWM1COM1 Value Description
4632 ---------------------------------------------------------------------------------------------------- */
4633#define BITP_PWM_PWM1COM1_PWM1COM1 (0U) /* Compare Register 1 for PWM2 and PWM3 */
4634#define BITL_PWM_PWM1COM1_PWM1COM1 (16U) /* Compare Register 1 for PWM2 and PWM3 */
4635#define BITM_PWM_PWM1COM1_PWM1COM1 (0XFFFFU) /* Compare Register 1 for PWM2 and PWM3 */
4636
4637/* ----------------------------------------------------------------------------------------------------
4638 PWM1COM2 Value Description
4639 ---------------------------------------------------------------------------------------------------- */
4640#define BITP_PWM_PWM1COM2_PWM1COM2 (0U) /* Compare Register 2 for PWM2 and PWM3 */
4641#define BITL_PWM_PWM1COM2_PWM1COM2 (16U) /* Compare Register 2 for PWM2 and PWM3 */
4642#define BITM_PWM_PWM1COM2_PWM1COM2 (0XFFFFU) /* Compare Register 2 for PWM2 and PWM3 */
4643
4644/* ----------------------------------------------------------------------------------------------------
4645 PWM1LEN Value Description
4646 ---------------------------------------------------------------------------------------------------- */
4647#define BITP_PWM_PWM1LEN_PWM1LEN (0U) /* Period Value Register for PWM2 and PWM3 */
4648#define BITL_PWM_PWM1LEN_PWM1LEN (16U) /* Period Value Register for PWM2 and PWM3 */
4649#define BITM_PWM_PWM1LEN_PWM1LEN (0XFFFFU) /* Period Value Register for PWM2 and PWM3 */
4650
4651/* ----------------------------------------------------------------------------------------------------
4652 PWM2COM0 Value Description
4653 ---------------------------------------------------------------------------------------------------- */
4654#define BITP_PWM_PWM2COM0_PWM2COM0 (0U) /* Compare Register 0 for PWM4 and PWM5 */
4655#define BITL_PWM_PWM2COM0_PWM2COM0 (16U) /* Compare Register 0 for PWM4 and PWM5 */
4656#define BITM_PWM_PWM2COM0_PWM2COM0 (0XFFFFU) /* Compare Register 0 for PWM4 and PWM5 */
4657
4658/* ----------------------------------------------------------------------------------------------------
4659 PWM2COM1 Value Description
4660 ---------------------------------------------------------------------------------------------------- */
4661#define BITP_PWM_PWM2COM1_PWM2COM1 (0U) /* Compare Register 1 for PWM4 and PWM5 */
4662#define BITL_PWM_PWM2COM1_PWM2COM1 (16U) /* Compare Register 1 for PWM4 and PWM5 */
4663#define BITM_PWM_PWM2COM1_PWM2COM1 (0XFFFFU) /* Compare Register 1 for PWM4 and PWM5 */
4664
4665/* ----------------------------------------------------------------------------------------------------
4666 PWM2COM2 Value Description
4667 ---------------------------------------------------------------------------------------------------- */
4668#define BITP_PWM_PWM2COM2_PWM2COM2 (0U) /* Compare Register 2 for PWM4 and PWM5 */
4669#define BITL_PWM_PWM2COM2_PWM2COM2 (16U) /* Compare Register 2 for PWM4 and PWM5 */
4670#define BITM_PWM_PWM2COM2_PWM2COM2 (0XFFFFU) /* Compare Register 2 for PWM4 and PWM5 */
4671
4672/* ----------------------------------------------------------------------------------------------------
4673 PWM2LEN Value Description
4674 ---------------------------------------------------------------------------------------------------- */
4675#define BITP_PWM_PWM2LEN_PWM2LEN (0U) /* Period Value Register for PWM4 and PWM5 */
4676#define BITL_PWM_PWM2LEN_PWM2LEN (16U) /* Period Value Register for PWM4 and PWM5 */
4677#define BITM_PWM_PWM2LEN_PWM2LEN (0XFFFFU) /* Period Value Register for PWM4 and PWM5 */
4678
4679#endif /* end ifndef PWM_ADDR_RDEF_H_ */
4680
4681
4682#ifndef SUBSYS_ADDR_RDEF_H_
4683#define SUBSYS_ADDR_RDEF_H_ /* SUBSYS: Your module description, here. */
4684
4685/* ====================================================================================================
4686 SUBSYS Module Instances Address and Mask Definitions
4687 ==================================================================================================== */
4688#define INST_SRAM (0X40065000U) /* sram: */
4689
4690#define MASK_SUBSYS (0X00000FFFU) /* SUBSYS: Your module description, here. */
4691
4692/* ====================================================================================================
4693 SUBSYS Module Register Address Offset Definitions
4694 ==================================================================================================== */
4695#define IDX_SUBSYS_SRAMCON (0X000U) /* SRAM Control Register */
4696#define IDX_SUBSYS_SRAMECCCON (0X00CU) /* SRAM ECC Control Register */
4697#define IDX_SUBSYS_SRAMECCSTA (0X010U) /* SRAM ECC Status Register */
4698#define IDX_SUBSYS_SRAMECCA0 (0X014U) /* SRAM0 ECC Error Address Register */
4699#define IDX_SUBSYS_SRAMECCD0 (0X018U) /* SRAM0 ECC Error Data Register */
4700#define IDX_SUBSYS_SRAMECCP0 (0X01CU) /* SRAM0 ECC Error Parity Register */
4701#define IDX_SUBSYS_SRAMECCA1 (0X020U) /* SRAM1 ECC Error Address Register */
4702#define IDX_SUBSYS_SRAMECCD1 (0X024U) /* SRAM1 ECC Error Data Register */
4703#define IDX_SUBSYS_SRAMECCP1 (0X028U) /* SRAM1 ECC Error Parity Register */
4704#define IDX_SUBSYS_SRAMECCA2 (0X02CU) /* SRAM2 ECC Error Address Register */
4705#define IDX_SUBSYS_SRAMECCD2 (0X030U) /* SRAM2 ECC Error Data Register */
4706#define IDX_SUBSYS_SRAMECCP2 (0X034U) /* SRAM2 ECC Error Parity Register */
4707
4708/* ====================================================================================================
4709 SUBSYS Module Register ResetValue Definitions
4710 ==================================================================================================== */
4711#define RSTVAL_SUBSYS_SRAMCON (0X2)
4712#define RSTVAL_SUBSYS_SRAMECCCON (0XCF)
4713#define RSTVAL_SUBSYS_SRAMECCSTA (0X0)
4714#define RSTVAL_SUBSYS_SRAMECCA0 (0X0)
4715#define RSTVAL_SUBSYS_SRAMECCD0 (0X0)
4716#define RSTVAL_SUBSYS_SRAMECCP0 (0X0)
4717#define RSTVAL_SUBSYS_SRAMECCA1 (0X0)
4718#define RSTVAL_SUBSYS_SRAMECCD1 (0X0)
4719#define RSTVAL_SUBSYS_SRAMECCP1 (0X0)
4720#define RSTVAL_SUBSYS_SRAMECCA2 (0X0)
4721#define RSTVAL_SUBSYS_SRAMECCD2 (0X0)
4722#define RSTVAL_SUBSYS_SRAMECCP2 (0X0)
4723
4724/* ====================================================================================================
4725 SUBSYS Module Register BitPositions, Lengths, Masks and Enumerations Definitions
4726 ==================================================================================================== */
4727
4728/* ----------------------------------------------------------------------------------------------------
4729 SRAMCON Value Description
4730 ---------------------------------------------------------------------------------------------------- */
4731#define BITP_SUBSYS_SRAMCON_REMAP (0U) /* Using SRAM0 as Instruction SRAM */
4732#define BITL_SUBSYS_SRAMCON_REMAP (1U) /* Using SRAM0 as Instruction SRAM */
4733#define BITM_SUBSYS_SRAMCON_REMAP (0X00000001U) /* Using SRAM0 as Instruction SRAM */
4734#define BITP_SUBSYS_SRAMCON_CSEL (1U) /* Use Cache as a Part of SRAM0 */
4735#define BITL_SUBSYS_SRAMCON_CSEL (1U) /* Use Cache as a Part of SRAM0 */
4736#define BITM_SUBSYS_SRAMCON_CSEL (0X00000002U) /* Use Cache as a Part of SRAM0 */
4737
4738#define ENUM_SUBSYS_SRAMCON_CSEL_CAS (0X00000001U) /* Cache as SRAM */
4739#define ENUM_SUBSYS_SRAMCON_CSEL_NCAS (0X00000000U) /* Cache not as SRAM */
4740#define ENUM_SUBSYS_SRAMCON_REMAP_CODRAM (0X00000000U) /* Using as Code SRAM */
4741#define ENUM_SUBSYS_SRAMCON_REMAP_SYSRAM (0X00000001U) /* Using as System SRAM */
4742
4743/* ----------------------------------------------------------------------------------------------------
4744 SRAMECCCON Value Description
4745 ---------------------------------------------------------------------------------------------------- */
4746#define BITP_SUBSYS_SRAMECCCON_EN (0U) /* ECC Check Enable */
4747#define BITL_SUBSYS_SRAMECCCON_EN (3U) /* ECC Check Enable */
4748#define BITM_SUBSYS_SRAMECCCON_EN (0X00000007U) /* ECC Check Enable */
4749#define BITP_SUBSYS_SRAMECCCON_BUSERRTYPE (3U) /* ECC AHB Bus Error Response Type */
4750#define BITL_SUBSYS_SRAMECCCON_BUSERRTYPE (2U) /* ECC AHB Bus Error Response Type */
4751#define BITM_SUBSYS_SRAMECCCON_BUSERRTYPE (0X00000018U) /* ECC AHB Bus Error Response Type */
4752#define BITP_SUBSYS_SRAMECCCON_INTERRTYPE (5U) /* ECC Interrupt Error Response Type */
4753#define BITL_SUBSYS_SRAMECCCON_INTERRTYPE (2U) /* ECC Interrupt Error Response Type */
4754#define BITM_SUBSYS_SRAMECCCON_INTERRTYPE (0X00000060U) /* ECC Interrupt Error Response Type */
4755#define BITP_SUBSYS_SRAMECCCON_RECERRTYPE (7U) /* ECC Error Address and Data Record Type */
4756#define BITL_SUBSYS_SRAMECCCON_RECERRTYPE (2U) /* ECC Error Address and Data Record Type */
4757#define BITM_SUBSYS_SRAMECCCON_RECERRTYPE (0X00000180U) /* ECC Error Address and Data Record Type */
4758
4759#define ENUM_SUBSYS_SRAMECCCON_RECERRTYPE_CURERR (0X00000000U) /* Return Current Error Address and Data Information */
4760#define ENUM_SUBSYS_SRAMECCCON_RECERRTYPE_STRERR0 (0X00000001U) /* Return Stored Error Address and Data Information */
4761#define ENUM_SUBSYS_SRAMECCCON_INTERRTYPE_NOERR (0X00000000U) /* No Error Report */
4762#define ENUM_SUBSYS_SRAMECCCON_INTERRTYPE_ERR2B (0X00000001U) /* 2 Bits Error Report */
4763#define ENUM_SUBSYS_SRAMECCCON_INTERRTYPE_ERR1B (0X00000002U) /* 1 Bit Error Report */
4764#define ENUM_SUBSYS_SRAMECCCON_INTERRTYPE_ALERR (0X00000003U) /* 1 or 2 Bits Error Report */
4765#define ENUM_SUBSYS_SRAMECCCON_BUSERRTYPE_NOERR (0X00000000U) /* No Error Report */
4766#define ENUM_SUBSYS_SRAMECCCON_BUSERRTYPE_ERR2B (0X00000001U) /* 2 Bits Error Report */
4767#define ENUM_SUBSYS_SRAMECCCON_BUSERRTYPE_ERR1B (0X00000002U) /* 1 Bit Error Report */
4768#define ENUM_SUBSYS_SRAMECCCON_BUSERRTYPE_ALERR (0X00000003U) /* 1 or 2 Bits Error Report */
4769#define ENUM_SUBSYS_SRAMECCCON_EN_EN0 (0X00000001U) /* SRAM0 ECC Enable */
4770#define ENUM_SUBSYS_SRAMECCCON_EN_EN1 (0X00000002U) /* SRAM1 ECC Enable */
4771#define ENUM_SUBSYS_SRAMECCCON_EN_EN2 (0X00000004U) /* SRAM2 ECC Enable */
4772#define ENUM_SUBSYS_SRAMECCCON_EN_EN01 (0X00000003U) /* SRAM0 and SRAM1 ECC Enable */
4773#define ENUM_SUBSYS_SRAMECCCON_EN_EN02 (0X00000005U) /* SRAM0 and SRAM2 ECC Enable */
4774#define ENUM_SUBSYS_SRAMECCCON_EN_EN12 (0X00000006U) /* SRAM1 and SRAM2 ECC Enable */
4775#define ENUM_SUBSYS_SRAMECCCON_EN_EN012 (0X00000007U) /* SRAM0 and SRAM1 and SRAM2 ECC Enable */
4776#define ENUM_SUBSYS_SRAMECCCON_EN_ENNA (0X00000000U) /* None SRAM ECC Enable */
4777
4778/* ----------------------------------------------------------------------------------------------------
4779 SRAMECCSTA Value Description
4780 ---------------------------------------------------------------------------------------------------- */
4781#define BITP_SUBSYS_SRAMECCSTA_S0ERR2B (0U) /* SRAM0 ECC 2 Bits Error */
4782#define BITL_SUBSYS_SRAMECCSTA_S0ERR2B (1U) /* SRAM0 ECC 2 Bits Error */
4783#define BITM_SUBSYS_SRAMECCSTA_S0ERR2B (0X00000001U) /* SRAM0 ECC 2 Bits Error */
4784#define BITP_SUBSYS_SRAMECCSTA_S0ERR1B (1U) /* SRAM0 ECC 1 Bit Error */
4785#define BITL_SUBSYS_SRAMECCSTA_S0ERR1B (1U) /* SRAM0 ECC 1 Bit Error */
4786#define BITM_SUBSYS_SRAMECCSTA_S0ERR1B (0X00000002U) /* SRAM0 ECC 1 Bit Error */
4787#define BITP_SUBSYS_SRAMECCSTA_S1ERR2B (2U) /* SRAM1 ECC 2 Bits Error */
4788#define BITL_SUBSYS_SRAMECCSTA_S1ERR2B (1U) /* SRAM1 ECC 2 Bits Error */
4789#define BITM_SUBSYS_SRAMECCSTA_S1ERR2B (0X00000004U) /* SRAM1 ECC 2 Bits Error */
4790#define BITP_SUBSYS_SRAMECCSTA_S1ERR1B (3U) /* SRAM1 ECC 1 Bit Error */
4791#define BITL_SUBSYS_SRAMECCSTA_S1ERR1B (1U) /* SRAM1 ECC 1 Bit Error */
4792#define BITM_SUBSYS_SRAMECCSTA_S1ERR1B (0X00000008U) /* SRAM1 ECC 1 Bit Error */
4793#define BITP_SUBSYS_SRAMECCSTA_S2ERR2B (4U) /* SRAM2 ECC 2 Bits Error */
4794#define BITL_SUBSYS_SRAMECCSTA_S2ERR2B (1U) /* SRAM2 ECC 2 Bits Error */
4795#define BITM_SUBSYS_SRAMECCSTA_S2ERR2B (0X00000010U) /* SRAM2 ECC 2 Bits Error */
4796#define BITP_SUBSYS_SRAMECCSTA_S2ERR1B (5U) /* SRAM2 ECC 1 Bits Error */
4797#define BITL_SUBSYS_SRAMECCSTA_S2ERR1B (1U) /* SRAM2 ECC 1 Bits Error */
4798#define BITM_SUBSYS_SRAMECCSTA_S2ERR1B (0X00000020U) /* SRAM2 ECC 1 Bits Error */
4799#define BITP_SUBSYS_SRAMECCSTA_ERRCNT (8U) /* ECC Error Counter */
4800#define BITL_SUBSYS_SRAMECCSTA_ERRCNT (3U) /* ECC Error Counter */
4801#define BITM_SUBSYS_SRAMECCSTA_ERRCNT (0X00000700U) /* ECC Error Counter */
4802
4803/* ----------------------------------------------------------------------------------------------------
4804 SRAMECCA0 Value Description
4805 ---------------------------------------------------------------------------------------------------- */
4806#define BITP_SUBSYS_SRAMECCA0_ADDR (0U) /* ECC Error Address */
4807#define BITL_SUBSYS_SRAMECCA0_ADDR (32U) /* ECC Error Address */
4808#define BITM_SUBSYS_SRAMECCA0_ADDR (0XFFFFFFFFU) /* ECC Error Address */
4809
4810/* ----------------------------------------------------------------------------------------------------
4811 SRAMECCD0 Value Description
4812 ---------------------------------------------------------------------------------------------------- */
4813#define BITP_SUBSYS_SRAMECCD0_DATA (0U) /* ECC Error Raw Data */
4814#define BITL_SUBSYS_SRAMECCD0_DATA (32U) /* ECC Error Raw Data */
4815#define BITM_SUBSYS_SRAMECCD0_DATA (0XFFFFFFFFU) /* ECC Error Raw Data */
4816
4817/* ----------------------------------------------------------------------------------------------------
4818 SRAMECCP0 Value Description
4819 ---------------------------------------------------------------------------------------------------- */
4820#define BITP_SUBSYS_SRAMECCP0_PARITY (0U) /* ECC Error Raw Parity */
4821#define BITL_SUBSYS_SRAMECCP0_PARITY (7U) /* ECC Error Raw Parity */
4822#define BITM_SUBSYS_SRAMECCP0_PARITY (0X0000007FU) /* ECC Error Raw Parity */
4823
4824/* ----------------------------------------------------------------------------------------------------
4825 SRAMECCA1 Value Description
4826 ---------------------------------------------------------------------------------------------------- */
4827#define BITP_SUBSYS_SRAMECCA1_ADDR (0U) /* ECC Error Address */
4828#define BITL_SUBSYS_SRAMECCA1_ADDR (32U) /* ECC Error Address */
4829#define BITM_SUBSYS_SRAMECCA1_ADDR (0XFFFFFFFFU) /* ECC Error Address */
4830
4831/* ----------------------------------------------------------------------------------------------------
4832 SRAMECCD1 Value Description
4833 ---------------------------------------------------------------------------------------------------- */
4834#define BITP_SUBSYS_SRAMECCD1_DATA (0U) /* ECC Error Raw Data */
4835#define BITL_SUBSYS_SRAMECCD1_DATA (32U) /* ECC Error Raw Data */
4836#define BITM_SUBSYS_SRAMECCD1_DATA (0XFFFFFFFFU) /* ECC Error Raw Data */
4837
4838/* ----------------------------------------------------------------------------------------------------
4839 SRAMECCP1 Value Description
4840 ---------------------------------------------------------------------------------------------------- */
4841#define BITP_SUBSYS_SRAMECCP1_PARITY (0U) /* ECC Error Raw Parity */
4842#define BITL_SUBSYS_SRAMECCP1_PARITY (7U) /* ECC Error Raw Parity */
4843#define BITM_SUBSYS_SRAMECCP1_PARITY (0X0000007FU) /* ECC Error Raw Parity */
4844
4845/* ----------------------------------------------------------------------------------------------------
4846 SRAMECCA2 Value Description
4847 ---------------------------------------------------------------------------------------------------- */
4848#define BITP_SUBSYS_SRAMECCA2_ADDR (0U) /* ECC Error Address */
4849#define BITL_SUBSYS_SRAMECCA2_ADDR (32U) /* ECC Error Address */
4850#define BITM_SUBSYS_SRAMECCA2_ADDR (0XFFFFFFFFU) /* ECC Error Address */
4851
4852/* ----------------------------------------------------------------------------------------------------
4853 SRAMECCD2 Value Description
4854 ---------------------------------------------------------------------------------------------------- */
4855#define BITP_SUBSYS_SRAMECCD2_DATA (0U) /* ECC Error Raw Data */
4856#define BITL_SUBSYS_SRAMECCD2_DATA (32U) /* ECC Error Raw Data */
4857#define BITM_SUBSYS_SRAMECCD2_DATA (0XFFFFFFFFU) /* ECC Error Raw Data */
4858
4859/* ----------------------------------------------------------------------------------------------------
4860 SRAMECCP2 Value Description
4861 ---------------------------------------------------------------------------------------------------- */
4862#define BITP_SUBSYS_SRAMECCP2_PARITY (0U) /* ECC Error Raw Parity */
4863#define BITL_SUBSYS_SRAMECCP2_PARITY (7U) /* ECC Error Raw Parity */
4864#define BITM_SUBSYS_SRAMECCP2_PARITY (0X0000007FU) /* ECC Error Raw Parity */
4865
4866#endif /* end ifndef SUBSYS_ADDR_RDEF_H_ */
4867
4868
4869#ifndef CRC_ADDR_RDEF_H_
4870#define CRC_ADDR_RDEF_H_ /* CRC: CRC Accelerator */
4871
4872/* ====================================================================================================
4873 CRC Module Instances Address and Mask Definitions
4874 ==================================================================================================== */
4875#define INST_CRC (0X40066000U) /* crc: */
4876
4877#define MASK_CRC (0X000000FFU) /* CRC: CRC Accelerator */
4878
4879/* ====================================================================================================
4880 CRC Module Register Address Offset Definitions
4881 ==================================================================================================== */
4882#define IDX_CRC_CTL (0X00U) /* CRC Control Register */
4883#define IDX_CRC_IPDATA (0X04U) /* Input Data Word Register */
4884#define IDX_CRC_RESULT (0X08U) /* CRC Result Register */
4885#define IDX_CRC_POLY (0X0CU) /* Programmable CRC Polynomial */
4886
4887/* ====================================================================================================
4888 CRC Module Register ResetValue Definitions
4889 ==================================================================================================== */
4890#define RSTVAL_CRC_CTL (0X10000000)
4891#define RSTVAL_CRC_IPDATA (0X0)
4892#define RSTVAL_CRC_RESULT (0X0)
4893#define RSTVAL_CRC_POLY (0X4C11DB7)
4894
4895/* ====================================================================================================
4896 CRC Module Register BitPositions, Lengths, Masks and Enumerations Definitions
4897 ==================================================================================================== */
4898
4899/* ----------------------------------------------------------------------------------------------------
4900 CTL Value Description
4901 ---------------------------------------------------------------------------------------------------- */
4902#define BITP_CRC_CTL_EN (0U) /* CRC Peripheral Enable */
4903#define BITL_CRC_CTL_EN (1U) /* CRC Peripheral Enable */
4904#define BITM_CRC_CTL_EN (0X00000001U) /* CRC Peripheral Enable */
4905#define BITP_CRC_CTL_LSBFIRST (1U) /* LSB First Calculation Order */
4906#define BITL_CRC_CTL_LSBFIRST (1U) /* LSB First Calculation Order */
4907#define BITM_CRC_CTL_LSBFIRST (0X00000002U) /* LSB First Calculation Order */
4908#define BITP_CRC_CTL_BITMIRR (2U) /* Bit Mirroring */
4909#define BITL_CRC_CTL_BITMIRR (1U) /* Bit Mirroring */
4910#define BITM_CRC_CTL_BITMIRR (0X00000004U) /* Bit Mirroring */
4911#define BITP_CRC_CTL_BYTMIRR (3U) /* Byte Mirroring */
4912#define BITL_CRC_CTL_BYTMIRR (1U) /* Byte Mirroring */
4913#define BITM_CRC_CTL_BYTMIRR (0X00000008U) /* Byte Mirroring */
4914#define BITP_CRC_CTL_W16SWP (4U) /* Word16 Swap */
4915#define BITL_CRC_CTL_W16SWP (1U) /* Word16 Swap */
4916#define BITM_CRC_CTL_W16SWP (0X00000010U) /* Word16 Swap */
4917#define BITP_CRC_CTL_REVID (28U) /* Revision ID */
4918#define BITL_CRC_CTL_REVID (4U) /* Revision ID */
4919#define BITM_CRC_CTL_REVID (0XF0000000U) /* Revision ID */
4920
4921/* ----------------------------------------------------------------------------------------------------
4922 IPDATA Value Description
4923 ---------------------------------------------------------------------------------------------------- */
4924#define BITP_CRC_IPDATA_DATA_WORD (0U) /* Data Input. */
4925#define BITL_CRC_IPDATA_DATA_WORD (32U) /* Data Input. */
4926#define BITM_CRC_IPDATA_DATA_WORD (0XFFFFFFFFU) /* Data Input. */
4927
4928/* ----------------------------------------------------------------------------------------------------
4929 RESULT Value Description
4930 ---------------------------------------------------------------------------------------------------- */
4931#define BITP_CRC_RESULT_RESIDUE (0U) /* CRC Residue */
4932#define BITL_CRC_RESULT_RESIDUE (32U) /* CRC Residue */
4933#define BITM_CRC_RESULT_RESIDUE (0XFFFFFFFFU) /* CRC Residue */
4934
4935/* ----------------------------------------------------------------------------------------------------
4936 POLY Value Description
4937 ---------------------------------------------------------------------------------------------------- */
4938#define BITP_CRC_POLY_REDUCTION_POLY (0U) /* CRC Reduction Polynomial */
4939#define BITL_CRC_POLY_REDUCTION_POLY (32U) /* CRC Reduction Polynomial */
4940#define BITM_CRC_POLY_REDUCTION_POLY (0XFFFFFFFFU) /* CRC Reduction Polynomial */
4941
4942#endif /* end ifndef CRC_ADDR_RDEF_H_ */
4943
4944
4945#ifndef ADC_ADDR_RDEF_H_
4946#define ADC_ADDR_RDEF_H_ /* ADC: Your module description, here. */
4947
4948/* ====================================================================================================
4949 ADC Module Instances Address and Mask Definitions
4950 ==================================================================================================== */
4951#define INST_ADC (0X40068000U) /* adc: */
4952
4953#define MASK_ADC (0X000007FFU) /* ADC: Your module description, here. */
4954
4955/* ====================================================================================================
4956 ADC Module Register Address Offset Definitions
4957 ==================================================================================================== */
4958#define IDX_ADC_ADCDAT0 (0X000U) /* ADCx Data and Flags */
4959#define IDX_ADC_ADCDAT1 (0X004U) /* ADCx Data and Flags */
4960#define IDX_ADC_ADCDAT2 (0X008U) /* ADCx Data and Flags */
4961#define IDX_ADC_ADCDAT3 (0X00CU) /* ADCx Data and Flags */
4962#define IDX_ADC_ADCDAT4 (0X010U) /* ADCx Data and Flags */
4963#define IDX_ADC_ADCDAT5 (0X014U) /* ADCx Data and Flags */
4964#define IDX_ADC_ADCDAT6 (0X018U) /* ADCx Data and Flags */
4965#define IDX_ADC_ADCDAT7 (0X01CU) /* ADCx Data and Flags */
4966#define IDX_ADC_ADCDAT8 (0X020U) /* ADCx Data and Flags */
4967#define IDX_ADC_ADCDAT9 (0X024U) /* ADCx Data and Flags */
4968#define IDX_ADC_ADCDAT10 (0X028U) /* ADCx Data and Flags */
4969#define IDX_ADC_ADCDAT11 (0X02CU) /* ADCx Data and Flags */
4970#define IDX_ADC_ADCDAT12 (0X030U) /* ADCx Data and Flags */
4971#define IDX_ADC_ADCDAT13 (0X034U) /* ADCx Data and Flags */
4972#define IDX_ADC_ADCDAT14 (0X038U) /* ADCx Data and Flags */
4973#define IDX_ADC_ADCDAT15 (0X03CU) /* ADCx Data and Flags */
4974#define IDX_ADC_ADCDAT16 (0X040U) /* ADCx Data and Flags */
4975#define IDX_ADC_ADCDAT17 (0X044U) /* ADCx Data and Flags */
4976#define IDX_ADC_ADCDAT18 (0X048U) /* ADCx Data and Flags */
4977#define IDX_ADC_ADCDAT19 (0X04CU) /* ADCx Data and Flags */
4978#define IDX_ADC_ADCDAT20 (0X050U) /* ADCx Data and Flags */
4979#define IDX_ADC_ADCDAT21 (0X054U) /* ADCx Data and Flags */
4980#define IDX_ADC_ADCDAT22 (0X058U) /* ADCx Data and Flags */
4981#define IDX_ADC_ADCDAT23 (0X05CU) /* ADCx Data and Flags */
4982#define IDX_ADC_ADCDAT24 (0X060U) /* ADCx Data and Flags */
4983#define IDX_ADC_ADCDAT25 (0X064U) /* ADCx Data and Flags */
4984#define IDX_ADC_ADCDAT26 (0X068U) /* ADCx Data and Flags */
4985#define IDX_ADC_ADCDAT27 (0X06CU) /* ADCx Data and Flags */
4986#define IDX_ADC_ADCDAT28 (0X070U) /* ADCx Data and Flags */
4987#define IDX_ADC_ADCDAT29 (0X074U) /* ADCx Data and Flags */
4988#define IDX_ADC_ADCCON (0X078U) /* ADC Configuration */
4989#define IDX_ADC_PREBUFCON (0X07CU) /* Pre-charge Buffer Control */
4990#define IDX_ADC_ADCCNVC (0X080U) /* ADC Conversion Cycle for Positive Input Channels */
4991#define IDX_ADC_ADCCNVCSLOW (0X084U) /* ADC Conversion Cycle for Positive Input Channels */
4992#define IDX_ADC_ADCCHA (0X088U) /* ADC Channel Select */
4993#define IDX_ADC_ADCIRQSTAT (0X08CU) /* ADC Interrupt Status */
4994#define IDX_ADC_ADCSEQ (0X090U) /* ADC Sequencer Control */
4995#define IDX_ADC_ADCSEQC (0X094U) /* ADC Sequencer Configuration */
4996#define IDX_ADC_ADCSEQS (0X098U) /* ADC Sequencer Status */
4997#define IDX_ADC_ADCSEQCH (0X09CU) /* ADC Sequencer Channel 0 */
4998#define IDX_ADC_ADCSEQCHMUX0 (0X0A0U) /* ADC Sequencer Channel 1 */
4999#define IDX_ADC_ADCSEQCHMUX1 (0X0A4U) /* ADC Sequencer Channel 1 */
5000#define IDX_ADC_ADCCMP (0X0A8U) /* Digital Comparator 0 Configuration */
5001#define IDX_ADC_ADCCMPIRQSTAT (0X0ACU) /* Digital Comparator Interrupt Status */
5002#define IDX_ADC_ADCOFGNDIFF (0X0B0U) /* ADC Offset Gain Differential Channel Error Correction */
5003#define IDX_ADC_ADCOFTEMP (0X0B4U) /* ADC Offset Gain Temp Sensor Channel Error Correction */
5004#define IDX_ADC_ADCGNTEMP (0X0B8U) /* ADC Offset Gain Temp Sensor Channel Error Correction */
5005#define IDX_ADC_ADCOFGNPGA0 (0X0BCU) /* ADC Offset Gain PGA0 Channel Error Correction */
5006#define IDX_ADC_ADCOFGNPGA1 (0X0C0U) /* ADC Offset Gain PGA1 Channel Error Correction */
5007#define IDX_ADC_ADCOFGNPGA2 (0X0C4U) /* ADC Offset Gain PGA2 Channel Error Correction */
5008#define IDX_ADC_ADCOFGNPGA3 (0X0C8U) /* ADC Offset Gain PGA3 Channel Error Correction */
5009#define IDX_ADC_ADCOFGNPGA0TIA (0X0CCU) /* ADC Offset Gain PGA0 Channel Error Correction */
5010#define IDX_ADC_ADCOFGNPGA1TIA (0X0D0U) /* ADC Offset Gain PGA1 Channel Error Correction */
5011#define IDX_ADC_ADCOFGNPGA2TIA (0X0D4U) /* ADC Offset Gain PGA2 Channel Error Correction */
5012#define IDX_ADC_ADCOFGNPGA3TIA (0X0D8U) /* ADC Offset Gain PGA3 Channel Error Correction */
5013#define IDX_ADC_ADCCMP1 (0X154U) /* Digital Comparator 1 Configuration */
5014#define IDX_ADC_ADCCMP2 (0X158U) /* Digital Comparator 2 Configuration */
5015#define IDX_ADC_ADCCMP3 (0X15CU) /* Digital Comparator 3 Configuration */
5016
5017/* ====================================================================================================
5018 ADC Module Register ResetValue Definitions
5019 ==================================================================================================== */
5020#define RSTVAL_ADC_ADCDAT0 (0X0)
5021#define RSTVAL_ADC_ADCDAT1 (0X0)
5022#define RSTVAL_ADC_ADCDAT2 (0X0)
5023#define RSTVAL_ADC_ADCDAT3 (0X0)
5024#define RSTVAL_ADC_ADCDAT4 (0X0)
5025#define RSTVAL_ADC_ADCDAT5 (0X0)
5026#define RSTVAL_ADC_ADCDAT6 (0X0)
5027#define RSTVAL_ADC_ADCDAT7 (0X0)
5028#define RSTVAL_ADC_ADCDAT8 (0X0)
5029#define RSTVAL_ADC_ADCDAT9 (0X0)
5030#define RSTVAL_ADC_ADCDAT10 (0X0)
5031#define RSTVAL_ADC_ADCDAT11 (0X0)
5032#define RSTVAL_ADC_ADCDAT12 (0X0)
5033#define RSTVAL_ADC_ADCDAT13 (0X0)
5034#define RSTVAL_ADC_ADCDAT14 (0X0)
5035#define RSTVAL_ADC_ADCDAT15 (0X0)
5036#define RSTVAL_ADC_ADCDAT16 (0X0)
5037#define RSTVAL_ADC_ADCDAT17 (0X0)
5038#define RSTVAL_ADC_ADCDAT18 (0X0)
5039#define RSTVAL_ADC_ADCDAT19 (0X0)
5040#define RSTVAL_ADC_ADCDAT20 (0X0)
5041#define RSTVAL_ADC_ADCDAT21 (0X0)
5042#define RSTVAL_ADC_ADCDAT22 (0X0)
5043#define RSTVAL_ADC_ADCDAT23 (0X0)
5044#define RSTVAL_ADC_ADCDAT24 (0X0)
5045#define RSTVAL_ADC_ADCDAT25 (0X0)
5046#define RSTVAL_ADC_ADCDAT26 (0X0)
5047#define RSTVAL_ADC_ADCDAT27 (0X0)
5048#define RSTVAL_ADC_ADCDAT28 (0X0)
5049#define RSTVAL_ADC_ADCDAT29 (0X0)
5050#define RSTVAL_ADC_ADCCON (0X200)
5051#define RSTVAL_ADC_PREBUFCON (0X3)
5052#define RSTVAL_ADC_ADCCNVC (0X10)
5053#define RSTVAL_ADC_ADCCNVCSLOW (0X140)
5054#define RSTVAL_ADC_ADCCHA (0X0)
5055#define RSTVAL_ADC_ADCIRQSTAT (0X0)
5056#define RSTVAL_ADC_ADCSEQ (0X0)
5057#define RSTVAL_ADC_ADCSEQC (0X0)
5058#define RSTVAL_ADC_ADCSEQS (0X0)
5059#define RSTVAL_ADC_ADCSEQCH (0X0)
5060#define RSTVAL_ADC_ADCSEQCHMUX0 (0X0)
5061#define RSTVAL_ADC_ADCSEQCHMUX1 (0X0)
5062#define RSTVAL_ADC_ADCCMP (0X40000)
5063#define RSTVAL_ADC_ADCCMPIRQSTAT (0X0)
5064#define RSTVAL_ADC_ADCOFGNDIFF (0X4000)
5065#define RSTVAL_ADC_ADCOFTEMP (0X0)
5066#define RSTVAL_ADC_ADCGNTEMP (0X80000)
5067#define RSTVAL_ADC_ADCOFGNPGA0 (0X4000)
5068#define RSTVAL_ADC_ADCOFGNPGA1 (0X4000)
5069#define RSTVAL_ADC_ADCOFGNPGA2 (0X4000)
5070#define RSTVAL_ADC_ADCOFGNPGA3 (0X4000)
5071#define RSTVAL_ADC_ADCOFGNPGA0TIA (0X4000)
5072#define RSTVAL_ADC_ADCOFGNPGA1TIA (0X4000)
5073#define RSTVAL_ADC_ADCOFGNPGA2TIA (0X4000)
5074#define RSTVAL_ADC_ADCOFGNPGA3TIA (0X4000)
5075#define RSTVAL_ADC_ADCCMP1 (0X40000)
5076#define RSTVAL_ADC_ADCCMP2 (0X40000)
5077#define RSTVAL_ADC_ADCCMP3 (0X40000)
5078
5079/* ====================================================================================================
5080 ADC Module Register BitPositions, Lengths, Masks and Enumerations Definitions
5081 ==================================================================================================== */
5082
5083/* ----------------------------------------------------------------------------------------------------
5084 ADCDAT0 Value Description
5085 ---------------------------------------------------------------------------------------------------- */
5086#define BITP_ADC_ADCDAT_N__OVF (0U) /* Overflow Flag */
5087#define BITL_ADC_ADCDAT_N__OVF (1U) /* Overflow Flag */
5088#define BITM_ADC_ADCDAT_N__OVF (0X00000001U) /* Overflow Flag */
5089#define BITP_ADC_ADCDAT_N__UVF (1U) /* Underflow Flag */
5090#define BITL_ADC_ADCDAT_N__UVF (1U) /* Underflow Flag */
5091#define BITM_ADC_ADCDAT_N__UVF (0X00000002U) /* Underflow Flag */
5092#define BITP_ADC_ADCDAT_N__RDY (2U) /* Data Read Flag */
5093#define BITL_ADC_ADCDAT_N__RDY (1U) /* Data Read Flag */
5094#define BITM_ADC_ADCDAT_N__RDY (0X00000004U) /* Data Read Flag */
5095#define BITP_ADC_ADCDAT_N__DAT (4U) /* ADCx Data */
5096#define BITL_ADC_ADCDAT_N__DAT (16U) /* ADCx Data */
5097#define BITM_ADC_ADCDAT_N__DAT (0X000FFFF0U) /* ADCx Data */
5098
5099#define ENUM_ADC_ADCDAT_N__RDY_NORDY (0X00000000U) /* Data is Not Ready or Has Been Read Out */
5100#define ENUM_ADC_ADCDAT_N__RDY_RDY (0X00000001U) /* Data is Ready to Be Read */
5101#define ENUM_ADC_ADCDAT_N__UVF_NUNF (0X00000000U) /* Not Underflow */
5102#define ENUM_ADC_ADCDAT_N__UVF_UNF (0X00000001U) /* Underflow */
5103#define ENUM_ADC_ADCDAT_N__OVF_NOVF (0X00000000U) /* Not Overflow */
5104#define ENUM_ADC_ADCDAT_N__OVF_OVF (0X00000001U) /* Overflow */
5105
5106/* ----------------------------------------------------------------------------------------------------
5107 ADCCON Value Description
5108 ---------------------------------------------------------------------------------------------------- */
5109#define BITP_ADC_ADCCON_CONVTYPE (0U) /* ADC Conversion Type Selection */
5110#define BITL_ADC_ADCCON_CONVTYPE (3U) /* ADC Conversion Type Selection */
5111#define BITM_ADC_ADCCON_CONVTYPE (0X00000007U) /* ADC Conversion Type Selection */
5112#define BITP_ADC_ADCCON_CNVDMA (3U) /* DMA Request Enable for ADC Non-sequence Conversion */
5113#define BITL_ADC_ADCCON_CNVDMA (1U) /* DMA Request Enable for ADC Non-sequence Conversion */
5114#define BITM_ADC_ADCCON_CNVDMA (0X00000008U) /* DMA Request Enable for ADC Non-sequence Conversion */
5115#define BITP_ADC_ADCCON_SEQDMA (4U) /* DMA Request Enable for ADC Sequence Conversion */
5116#define BITL_ADC_ADCCON_SEQDMA (1U) /* DMA Request Enable for ADC Sequence Conversion */
5117#define BITM_ADC_ADCCON_SEQDMA (0X00000010U) /* DMA Request Enable for ADC Sequence Conversion */
5118#define BITP_ADC_ADCCON_PINMOD (5U) /* PIN Conversion Mode Selection */
5119#define BITL_ADC_ADCCON_PINMOD (1U) /* PIN Conversion Mode Selection */
5120#define BITM_ADC_ADCCON_PINMOD (0X00000020U) /* PIN Conversion Mode Selection */
5121#define BITP_ADC_ADCCON_RESTARTADC (6U) /* Restart ADC, Reset Analog Part of ADC */
5122#define BITL_ADC_ADCCON_RESTARTADC (1U) /* Restart ADC, Reset Analog Part of ADC */
5123#define BITM_ADC_ADCCON_RESTARTADC (0X00000040U) /* Restart ADC, Reset Analog Part of ADC */
5124#define BITP_ADC_ADCCON_PDREFBUF (7U) /* ADC Refbuf Power Down */
5125#define BITL_ADC_ADCCON_PDREFBUF (1U) /* ADC Refbuf Power Down */
5126#define BITM_ADC_ADCCON_PDREFBUF (0X00000080U) /* ADC Refbuf Power Down */
5127#define BITP_ADC_ADCCON_VDDSEL (8U) /* Select Whether Channel 29 is DVDD Channel or AVDD Channel */
5128#define BITL_ADC_ADCCON_VDDSEL (1U) /* Select Whether Channel 29 is DVDD Channel or AVDD Channel */
5129#define BITM_ADC_ADCCON_VDDSEL (0X00000100U) /* Select Whether Channel 29 is DVDD Channel or AVDD Channel */
5130#define BITP_ADC_ADCCON_PDADC (9U) /* ADC Power Down */
5131#define BITL_ADC_ADCCON_PDADC (1U) /* ADC Power Down */
5132#define BITM_ADC_ADCCON_PDADC (0X00000200U) /* ADC Power Down */
5133#define BITP_ADC_ADCCON_OSR (10U) /* Oversampling Ratio */
5134#define BITL_ADC_ADCCON_OSR (3U) /* Oversampling Ratio */
5135#define BITM_ADC_ADCCON_OSR (0X00001C00U) /* Oversampling Ratio */
5136#define BITP_ADC_ADCCON_CNVIRQEN (14U) /* Enable Conversion Interrupt Generation */
5137#define BITL_ADC_ADCCON_CNVIRQEN (1U) /* Enable Conversion Interrupt Generation */
5138#define BITM_ADC_ADCCON_CNVIRQEN (0X00004000U) /* Enable Conversion Interrupt Generation */
5139#define BITP_ADC_ADCCON_GPTEVENTEN (15U) /* Enable GPT Event to Trigger Conversion */
5140#define BITL_ADC_ADCCON_GPTEVENTEN (5U) /* Enable GPT Event to Trigger Conversion */
5141#define BITM_ADC_ADCCON_GPTEVENTEN (0X000F8000U) /* Enable GPT Event to Trigger Conversion */
5142#define BITP_ADC_ADCCON_GPTTRIGMD (20U) /* Mux Select GP Timer Trigger Mode */
5143#define BITL_ADC_ADCCON_GPTTRIGMD (1U) /* Mux Select GP Timer Trigger Mode */
5144#define BITM_ADC_ADCCON_GPTTRIGMD (0X00100000U) /* Mux Select GP Timer Trigger Mode */
5145
5146#define ENUM_ADC_ADCCON_GPTTRIGMD_MD0 (0X00000000U) /* Two Timeout Events Trigger One Conversion */
5147#define ENUM_ADC_ADCCON_GPTTRIGMD_MD1 (0X00000001U) /* One Timeout Events Trigger One Conversion */
5148#define ENUM_ADC_ADCCON_OSR_OSR_NS1 (0X00000000U) /* Oversampling Disable */
5149#define ENUM_ADC_ADCCON_OSR_OSR2 (0X00000001U) /* Oversampling X2 */
5150#define ENUM_ADC_ADCCON_OSR_OSR4 (0X00000002U) /* Oversampling X4 */
5151#define ENUM_ADC_ADCCON_OSR_OSR8 (0X00000003U) /* Oversampling X8 */
5152#define ENUM_ADC_ADCCON_OSR_OSR16 (0X00000004U) /* Oversampling X16 */
5153#define ENUM_ADC_ADCCON_OSR_OSR_NS32 (0X00000005U) /* Oversampling X32 */
5154#define ENUM_ADC_ADCCON_OSR_OSR_NS64 (0X00000006U) /* Oversampling Disable */
5155#define ENUM_ADC_ADCCON_OSR_OSR_NS128 (0X00000007U) /* Oversampling Disable */
5156#define ENUM_ADC_ADCCON_PDADC_ADCPU (0X00000000U) /* Not Power Down ADC */
5157#define ENUM_ADC_ADCCON_PDADC_ADCPD (0X00000001U) /* Power Down ADC */
5158#define ENUM_ADC_ADCCON_VDDSEL_DVDD (0X00000000U) /* Channel 29 is Half of DVDD Channel */
5159#define ENUM_ADC_ADCCON_VDDSEL_AVSS (0X00000001U) /* Channel 29 is AVSS Channel */
5160#define ENUM_ADC_ADCCON_PDREFBUF_REFBUFPU (0X00000000U) /* Normal Mode */
5161#define ENUM_ADC_ADCCON_PDREFBUF_REFBUFPD (0X00000001U) /* Power Down Reference Mode */
5162#define ENUM_ADC_ADCCON_RESTARTADC_ADCPU (0X00000000U) /* Not Power Down ADC */
5163#define ENUM_ADC_ADCCON_RESTARTADC_ADCPD (0X00000001U) /* Power Down ADC */
5164#define ENUM_ADC_ADCCON_PINMOD_PIN_LVL (0X00000000U) /* CNV is Controlled by PIN Level */
5165#define ENUM_ADC_ADCCON_PINMOD_PIN_EDGE (0X00000001U) /* CNV is Controlled by PIN Edge */
5166#define ENUM_ADC_ADCCON_CONVTYPE_IDLE (0X00000000U) /* No Conversion */
5167#define ENUM_ADC_ADCCON_CONVTYPE_GPIO (0X00000001U) /* ADC Controlled by GPIO Pin */
5168#define ENUM_ADC_ADCCON_CONVTYPE_SINGL (0X00000002U) /* Software Single Conversion */
5169#define ENUM_ADC_ADCCON_CONVTYPE_CONT (0X00000003U) /* Software Continue Conversion */
5170#define ENUM_ADC_ADCCON_CONVTYPE_PLA (0X00000004U) /* PLA Conversion */
5171#define ENUM_ADC_ADCCON_CONVTYPE_GPT (0X00000005U) /* GPT Triggered Conversion */
5172
5173/* ----------------------------------------------------------------------------------------------------
5174 PREBUFCON Value Description
5175 ---------------------------------------------------------------------------------------------------- */
5176#define BITP_ADC_PREBUFCON_PRGBYPP (0U) /* Bypass P Channel Pre_buf */
5177#define BITL_ADC_PREBUFCON_PRGBYPP (1U) /* Bypass P Channel Pre_buf */
5178#define BITM_ADC_PREBUFCON_PRGBYPP (0X00000001U) /* Bypass P Channel Pre_buf */
5179#define BITP_ADC_PREBUFCON_PRGBYPN (1U) /* Bypass N Channel Pre_buf */
5180#define BITL_ADC_PREBUFCON_PRGBYPN (1U) /* Bypass N Channel Pre_buf */
5181#define BITM_ADC_PREBUFCON_PRGBYPN (0X00000002U) /* Bypass N Channel Pre_buf */
5182
5183/* ----------------------------------------------------------------------------------------------------
5184 ADCCNVC Value Description
5185 ---------------------------------------------------------------------------------------------------- */
5186#define BITP_ADC_ADCCNVC_CNVC (0U) /* CNV Frequency Configuration for Positive Channels */
5187#define BITL_ADC_ADCCNVC_CNVC (32U) /* CNV Frequency Configuration for Positive Channels */
5188#define BITM_ADC_ADCCNVC_CNVC (0XFFFFFFFFU) /* CNV Frequency Configuration for Positive Channels */
5189
5190/* ----------------------------------------------------------------------------------------------------
5191 ADCCNVCSLOW Value Description
5192 ---------------------------------------------------------------------------------------------------- */
5193#define BITP_ADC_ADCCNVCSLOW_CNVCSLOW (0U) /* CNV Frequency Configuration for 100KSPS Channels */
5194#define BITL_ADC_ADCCNVCSLOW_CNVCSLOW (32U) /* CNV Frequency Configuration for 100KSPS Channels */
5195#define BITM_ADC_ADCCNVCSLOW_CNVCSLOW (0XFFFFFFFFU) /* CNV Frequency Configuration for 100KSPS Channels */
5196
5197/* ----------------------------------------------------------------------------------------------------
5198 ADCCHA Value Description
5199 ---------------------------------------------------------------------------------------------------- */
5200#define BITP_ADC_ADCCHA_ADCCP (0U) /* ADC P Channel Selection */
5201#define BITL_ADC_ADCCHA_ADCCP (5U) /* ADC P Channel Selection */
5202#define BITM_ADC_ADCCHA_ADCCP (0X0000001FU) /* ADC P Channel Selection */
5203#define BITP_ADC_ADCCHA_ADCCN (5U) /* ADC N Channel Selection */
5204#define BITL_ADC_ADCCHA_ADCCN (4U) /* ADC N Channel Selection */
5205#define BITM_ADC_ADCCHA_ADCCN (0X000001E0U) /* ADC N Channel Selection */
5206
5207#define ENUM_ADC_ADCCHA_ADCCP_AIN0 (0X00000000U) /* No description provided */
5208#define ENUM_ADC_ADCCHA_ADCCP_AIN1 (0X00000001U) /* No description provided */
5209#define ENUM_ADC_ADCCHA_ADCCP_AIN2 (0X00000002U) /* No description provided */
5210#define ENUM_ADC_ADCCHA_ADCCP_AIN3 (0X00000003U) /* No description provided */
5211#define ENUM_ADC_ADCCHA_ADCCP_AIN4 (0X00000004U) /* No description provided */
5212#define ENUM_ADC_ADCCHA_ADCCP_AIN5 (0X00000005U) /* No description provided */
5213#define ENUM_ADC_ADCCHA_ADCCP_AIN6 (0X00000006U) /* No description provided */
5214#define ENUM_ADC_ADCCHA_ADCCP_AIN7 (0X00000007U) /* No description provided */
5215#define ENUM_ADC_ADCCHA_ADCCP_AIN8 (0X00000008U) /* No description provided */
5216#define ENUM_ADC_ADCCHA_ADCCP_AIN9 (0X00000009U) /* No description provided */
5217#define ENUM_ADC_ADCCHA_ADCCP_AIN10 (0X0000000AU) /* No description provided */
5218#define ENUM_ADC_ADCCHA_ADCCP_AIN11 (0X0000000BU) /* No description provided */
5219#define ENUM_ADC_ADCCHA_ADCCP_AIN12 (0X0000000CU) /* No description provided */
5220#define ENUM_ADC_ADCCHA_ADCCP_AIN13 (0X0000000DU) /* No description provided */
5221#define ENUM_ADC_ADCCHA_ADCCP_AIN14 (0X0000000EU) /* No description provided */
5222#define ENUM_ADC_ADCCHA_ADCCP_AIN15 (0X0000000FU) /* No description provided */
5223#define ENUM_ADC_ADCCHA_ADCCP_PGA0 (0X00000010U) /* No description provided */
5224#define ENUM_ADC_ADCCHA_ADCCP_PGA1 (0X00000011U) /* No description provided */
5225#define ENUM_ADC_ADCCHA_ADCCP_PGA2 (0X00000012U) /* No description provided */
5226#define ENUM_ADC_ADCCHA_ADCCP_PGA3 (0X00000013U) /* No description provided */
5227#define ENUM_ADC_ADCCHA_ADCCP_TEMPSNS (0X00000014U) /* No description provided */
5228#define ENUM_ADC_ADCCHA_ADCCP_AVDDDIV2 (0X00000015U) /* No description provided */
5229#define ENUM_ADC_ADCCHA_ADCCP_IOVDD0DIV2 (0X00000016U) /* No description provided */
5230#define ENUM_ADC_ADCCHA_ADCCP_IOVDD1 (0X00000017U) /* No description provided */
5231#define ENUM_ADC_ADCCHA_ADCCP_HVTIA0 (0X00000018U) /* No description provided */
5232#define ENUM_ADC_ADCCHA_ADCCP_HVTIA1 (0X00000019U) /* No description provided */
5233#define ENUM_ADC_ADCCHA_ADCCP_HVTIA2 (0X0000001AU) /* No description provided */
5234#define ENUM_ADC_ADCCHA_ADCCP_HVTIA3 (0X0000001BU) /* No description provided */
5235#define ENUM_ADC_ADCCHA_ADCCP_HVTIA4 (0X0000001CU) /* No description provided */
5236#define ENUM_ADC_ADCCHA_ADCCP_AVSS (0X0000001DU) /* No description provided */
5237
5238/* ----------------------------------------------------------------------------------------------------
5239 ADCIRQSTAT Value Description
5240 ---------------------------------------------------------------------------------------------------- */
5241#define BITP_ADC_ADCIRQSTAT_CNVIRQSTAT (0U) /* Single Conversion IRQ Status */
5242#define BITL_ADC_ADCIRQSTAT_CNVIRQSTAT (1U) /* Single Conversion IRQ Status */
5243#define BITM_ADC_ADCIRQSTAT_CNVIRQSTAT (0X00000001U) /* Single Conversion IRQ Status */
5244#define BITP_ADC_ADCIRQSTAT_SEQIRQSTAT (1U) /* Sequence Conversion IRQ Status */
5245#define BITL_ADC_ADCIRQSTAT_SEQIRQSTAT (1U) /* Sequence Conversion IRQ Status */
5246#define BITM_ADC_ADCIRQSTAT_SEQIRQSTAT (0X00000002U) /* Sequence Conversion IRQ Status */
5247
5248#define ENUM_ADC_ADCIRQSTAT_SEQIRQSTAT_IRQCLR (0X00000000U) /* Interrupt Clear */
5249#define ENUM_ADC_ADCIRQSTAT_SEQIRQSTAT_IRQSET (0X00000001U) /* Interrupt Set */
5250#define ENUM_ADC_ADCIRQSTAT_CNVIRQSTAT_IRQCLR (0X00000000U) /* Interrupt Clear */
5251#define ENUM_ADC_ADCIRQSTAT_CNVIRQSTAT_IRQSET (0X00000001U) /* Interrupt Set */
5252
5253/* ----------------------------------------------------------------------------------------------------
5254 ADCSEQ Value Description
5255 ---------------------------------------------------------------------------------------------------- */
5256#define BITP_ADC_ADCSEQ_SEQEN (0U) /* Sequence Enable */
5257#define BITL_ADC_ADCSEQ_SEQEN (1U) /* Sequence Enable */
5258#define BITM_ADC_ADCSEQ_SEQEN (0X00000001U) /* Sequence Enable */
5259#define BITP_ADC_ADCSEQ_SEQREN (1U) /* Sequence Restart */
5260#define BITL_ADC_ADCSEQ_SEQREN (1U) /* Sequence Restart */
5261#define BITM_ADC_ADCSEQ_SEQREN (0X00000002U) /* Sequence Restart */
5262#define BITP_ADC_ADCSEQ_SEQSTL (2U) /* Sequence Stall */
5263#define BITL_ADC_ADCSEQ_SEQSTL (1U) /* Sequence Stall */
5264#define BITM_ADC_ADCSEQ_SEQSTL (0X00000004U) /* Sequence Stall */
5265#define BITP_ADC_ADCSEQ_SEQIRQEN (3U) /* Enable Sequencer Interrupt Generation */
5266#define BITL_ADC_ADCSEQ_SEQIRQEN (1U) /* Enable Sequencer Interrupt Generation */
5267#define BITM_ADC_ADCSEQ_SEQIRQEN (0X00000008U) /* Enable Sequencer Interrupt Generation */
5268
5269#define ENUM_ADC_ADCSEQ_SEQSTL_SEQNSTALL (0X00000000U) /* Running Sequence */
5270#define ENUM_ADC_ADCSEQ_SEQSTL_SEQSTALL (0X00000001U) /* Stalling Sequence */
5271
5272/* ----------------------------------------------------------------------------------------------------
5273 ADCSEQC Value Description
5274 ---------------------------------------------------------------------------------------------------- */
5275#define BITP_ADC_ADCSEQC_SEQT (0U) /* Repeat Sequence Interval */
5276#define BITL_ADC_ADCSEQC_SEQT (8U) /* Repeat Sequence Interval */
5277#define BITM_ADC_ADCSEQC_SEQT (0X000000FFU) /* Repeat Sequence Interval */
5278
5279/* ----------------------------------------------------------------------------------------------------
5280 ADCSEQS Value Description
5281 ---------------------------------------------------------------------------------------------------- */
5282#define BITP_ADC_ADCSEQS_CNVSTAT (0U) /* ADC Conversion Idle/Busy Flag */
5283#define BITL_ADC_ADCSEQS_CNVSTAT (1U) /* ADC Conversion Idle/Busy Flag */
5284#define BITM_ADC_ADCSEQS_CNVSTAT (0X00000001U) /* ADC Conversion Idle/Busy Flag */
5285#define BITP_ADC_ADCSEQS_SEQSTLSTAT (1U) /* Stall Sequencer Status */
5286#define BITL_ADC_ADCSEQS_SEQSTLSTAT (1U) /* Stall Sequencer Status */
5287#define BITM_ADC_ADCSEQS_SEQSTLSTAT (0X00000002U) /* Stall Sequencer Status */
5288#define BITP_ADC_ADCSEQS_SEQSTAT (2U) /* Sequencer Status */
5289#define BITL_ADC_ADCSEQS_SEQSTAT (1U) /* Sequencer Status */
5290#define BITM_ADC_ADCSEQS_SEQSTAT (0X00000004U) /* Sequencer Status */
5291
5292#define ENUM_ADC_ADCSEQS_SEQSTAT_SEQBUSY (0X00000001U) /* Sequence is Busy */
5293#define ENUM_ADC_ADCSEQS_SEQSTAT_SEQNBUSY (0X00000000U) /* Sequence is Idle */
5294#define ENUM_ADC_ADCSEQS_SEQSTLSTAT_SEQNSTOP (0X00000000U) /* Sequence Still Run */
5295#define ENUM_ADC_ADCSEQS_SEQSTLSTAT_SEQSTOP (0X00000001U) /* Sequence Has Stalled */
5296#define ENUM_ADC_ADCSEQS_CNVSTAT_CNVIDLE (0X00000000U) /* ADC Conversion is Idle */
5297#define ENUM_ADC_ADCSEQS_CNVSTAT_CNVBUSY (0X00000001U) /* ADC Conversion is Busy */
5298
5299/* ----------------------------------------------------------------------------------------------------
5300 ADCSEQCH Value Description
5301 ---------------------------------------------------------------------------------------------------- */
5302#define BITP_ADC_ADCSEQCH_SEQCH (0U) /* Sequence Channel Selection */
5303#define BITL_ADC_ADCSEQCH_SEQCH (30U) /* Sequence Channel Selection */
5304#define BITM_ADC_ADCSEQCH_SEQCH (0X3FFFFFFFU) /* Sequence Channel Selection */
5305
5306/* ----------------------------------------------------------------------------------------------------
5307 ADCSEQCHMUX0 Value Description
5308 ---------------------------------------------------------------------------------------------------- */
5309#define BITP_ADC_ADCSEQCHMUX0_DIF0 (0U) /* When AIN0 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5310#define BITL_ADC_ADCSEQCHMUX0_DIF0 (4U) /* When AIN0 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5311#define BITM_ADC_ADCSEQCHMUX0_DIF0 (0X0000000FU) /* When AIN0 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5312#define BITP_ADC_ADCSEQCHMUX0_DIF1 (4U) /* When AIN1 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5313#define BITL_ADC_ADCSEQCHMUX0_DIF1 (1U) /* When AIN1 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5314#define BITM_ADC_ADCSEQCHMUX0_DIF1 (0X00000010U) /* When AIN1 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5315#define BITP_ADC_ADCSEQCHMUX0_DIF2 (5U) /* When AIN2 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5316#define BITL_ADC_ADCSEQCHMUX0_DIF2 (4U) /* When AIN2 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5317#define BITM_ADC_ADCSEQCHMUX0_DIF2 (0X000001E0U) /* When AIN2 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5318#define BITP_ADC_ADCSEQCHMUX0_DIF3 (9U) /* When AIN3 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5319#define BITL_ADC_ADCSEQCHMUX0_DIF3 (1U) /* When AIN3 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5320#define BITM_ADC_ADCSEQCHMUX0_DIF3 (0X00000200U) /* When AIN3 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5321#define BITP_ADC_ADCSEQCHMUX0_DIF4 (10U) /* When AIN4 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5322#define BITL_ADC_ADCSEQCHMUX0_DIF4 (4U) /* When AIN4 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5323#define BITM_ADC_ADCSEQCHMUX0_DIF4 (0X00003C00U) /* When AIN4 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5324#define BITP_ADC_ADCSEQCHMUX0_DIF5 (14U) /* When AIN5 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5325#define BITL_ADC_ADCSEQCHMUX0_DIF5 (1U) /* When AIN5 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5326#define BITM_ADC_ADCSEQCHMUX0_DIF5 (0X00004000U) /* When AIN5 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5327#define BITP_ADC_ADCSEQCHMUX0_DIF6 (15U) /* When AIN6 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5328#define BITL_ADC_ADCSEQCHMUX0_DIF6 (4U) /* When AIN6 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5329#define BITM_ADC_ADCSEQCHMUX0_DIF6 (0X00078000U) /* When AIN6 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5330#define BITP_ADC_ADCSEQCHMUX0_DIF7 (19U) /* When AIN7 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5331#define BITL_ADC_ADCSEQCHMUX0_DIF7 (1U) /* When AIN7 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5332#define BITM_ADC_ADCSEQCHMUX0_DIF7 (0X00080000U) /* When AIN7 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5333#define BITP_ADC_ADCSEQCHMUX0_DIF8 (20U) /* When AIN8 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5334#define BITL_ADC_ADCSEQCHMUX0_DIF8 (4U) /* When AIN8 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5335#define BITM_ADC_ADCSEQCHMUX0_DIF8 (0X00F00000U) /* When AIN8 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5336#define BITP_ADC_ADCSEQCHMUX0_DIF9 (24U) /* When AIN9 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5337#define BITL_ADC_ADCSEQCHMUX0_DIF9 (1U) /* When AIN9 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5338#define BITM_ADC_ADCSEQCHMUX0_DIF9 (0X01000000U) /* When AIN9 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5339#define BITP_ADC_ADCSEQCHMUX0_DIF10 (25U) /* When AIN10 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5340#define BITL_ADC_ADCSEQCHMUX0_DIF10 (4U) /* When AIN10 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5341#define BITM_ADC_ADCSEQCHMUX0_DIF10 (0X1E000000U) /* When AIN10 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5342#define BITP_ADC_ADCSEQCHMUX0_DIF11 (29U) /* When AIN11 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5343#define BITL_ADC_ADCSEQCHMUX0_DIF11 (1U) /* When AIN11 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5344#define BITM_ADC_ADCSEQCHMUX0_DIF11 (0X20000000U) /* When AIN11 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5345
5346#define ENUM_ADC_ADCSEQCHMUX0_DIF11_REFN (0X00000000U) /* No description provided */
5347#define ENUM_ADC_ADCSEQCHMUX0_DIF11_REFP (0X00000001U) /* No description provided */
5348#define ENUM_ADC_ADCSEQCHMUX0_DIF10_REFN (0X00000000U) /* No description provided */
5349#define ENUM_ADC_ADCSEQCHMUX0_DIF10_REFP (0X00000001U) /* No description provided */
5350#define ENUM_ADC_ADCSEQCHMUX0_DIF10_AIN1 (0X00000002U) /* No description provided */
5351#define ENUM_ADC_ADCSEQCHMUX0_DIF10_AIN3 (0X00000003U) /* No description provided */
5352#define ENUM_ADC_ADCSEQCHMUX0_DIF10_AIN5 (0X00000004U) /* No description provided */
5353#define ENUM_ADC_ADCSEQCHMUX0_DIF10_AIN7 (0X00000005U) /* No description provided */
5354#define ENUM_ADC_ADCSEQCHMUX0_DIF10_AIN9 (0X00000006U) /* No description provided */
5355#define ENUM_ADC_ADCSEQCHMUX0_DIF10_AIN11 (0X00000007U) /* No description provided */
5356#define ENUM_ADC_ADCSEQCHMUX0_DIF10_AIN13 (0X00000008U) /* No description provided */
5357#define ENUM_ADC_ADCSEQCHMUX0_DIF10_AIN15 (0X00000009U) /* No description provided */
5358#define ENUM_ADC_ADCSEQCHMUX0_DIF9_REFN (0X00000000U) /* No description provided */
5359#define ENUM_ADC_ADCSEQCHMUX0_DIF9_REFP (0X00000001U) /* No description provided */
5360#define ENUM_ADC_ADCSEQCHMUX0_DIF8_REFN (0X00000000U) /* No description provided */
5361#define ENUM_ADC_ADCSEQCHMUX0_DIF8_REFP (0X00000001U) /* No description provided */
5362#define ENUM_ADC_ADCSEQCHMUX0_DIF8_AIN1 (0X00000002U) /* No description provided */
5363#define ENUM_ADC_ADCSEQCHMUX0_DIF8_AIN3 (0X00000003U) /* No description provided */
5364#define ENUM_ADC_ADCSEQCHMUX0_DIF8_AIN5 (0X00000004U) /* No description provided */
5365#define ENUM_ADC_ADCSEQCHMUX0_DIF8_AIN7 (0X00000005U) /* No description provided */
5366#define ENUM_ADC_ADCSEQCHMUX0_DIF8_AIN9 (0X00000006U) /* No description provided */
5367#define ENUM_ADC_ADCSEQCHMUX0_DIF8_AIN11 (0X00000007U) /* No description provided */
5368#define ENUM_ADC_ADCSEQCHMUX0_DIF8_AIN13 (0X00000008U) /* No description provided */
5369#define ENUM_ADC_ADCSEQCHMUX0_DIF8_AIN15 (0X00000009U) /* No description provided */
5370#define ENUM_ADC_ADCSEQCHMUX0_DIF7_REFN (0X00000000U) /* No description provided */
5371#define ENUM_ADC_ADCSEQCHMUX0_DIF7_REFP (0X00000001U) /* No description provided */
5372#define ENUM_ADC_ADCSEQCHMUX0_DIF6_REFN (0X00000000U) /* No description provided */
5373#define ENUM_ADC_ADCSEQCHMUX0_DIF6_REFP (0X00000001U) /* No description provided */
5374#define ENUM_ADC_ADCSEQCHMUX0_DIF6_AIN1 (0X00000002U) /* No description provided */
5375#define ENUM_ADC_ADCSEQCHMUX0_DIF6_AIN3 (0X00000003U) /* No description provided */
5376#define ENUM_ADC_ADCSEQCHMUX0_DIF6_AIN5 (0X00000004U) /* No description provided */
5377#define ENUM_ADC_ADCSEQCHMUX0_DIF6_AIN7 (0X00000005U) /* No description provided */
5378#define ENUM_ADC_ADCSEQCHMUX0_DIF6_AIN9 (0X00000006U) /* No description provided */
5379#define ENUM_ADC_ADCSEQCHMUX0_DIF6_AIN11 (0X00000007U) /* No description provided */
5380#define ENUM_ADC_ADCSEQCHMUX0_DIF6_AIN13 (0X00000008U) /* No description provided */
5381#define ENUM_ADC_ADCSEQCHMUX0_DIF6_AIN15 (0X00000009U) /* No description provided */
5382#define ENUM_ADC_ADCSEQCHMUX0_DIF5_REFN (0X00000000U) /* No description provided */
5383#define ENUM_ADC_ADCSEQCHMUX0_DIF5_REFP (0X00000001U) /* No description provided */
5384#define ENUM_ADC_ADCSEQCHMUX0_DIF4_REFN (0X00000000U) /* No description provided */
5385#define ENUM_ADC_ADCSEQCHMUX0_DIF4_REFP (0X00000001U) /* No description provided */
5386#define ENUM_ADC_ADCSEQCHMUX0_DIF4_AIN1 (0X00000002U) /* No description provided */
5387#define ENUM_ADC_ADCSEQCHMUX0_DIF4_AIN3 (0X00000003U) /* No description provided */
5388#define ENUM_ADC_ADCSEQCHMUX0_DIF4_AIN5 (0X00000004U) /* No description provided */
5389#define ENUM_ADC_ADCSEQCHMUX0_DIF4_AIN7 (0X00000005U) /* No description provided */
5390#define ENUM_ADC_ADCSEQCHMUX0_DIF4_AIN9 (0X00000006U) /* No description provided */
5391#define ENUM_ADC_ADCSEQCHMUX0_DIF4_AIN11 (0X00000007U) /* No description provided */
5392#define ENUM_ADC_ADCSEQCHMUX0_DIF4_AIN13 (0X00000008U) /* No description provided */
5393#define ENUM_ADC_ADCSEQCHMUX0_DIF4_AIN15 (0X00000009U) /* No description provided */
5394#define ENUM_ADC_ADCSEQCHMUX0_DIF3_REFN (0X00000000U) /* No description provided */
5395#define ENUM_ADC_ADCSEQCHMUX0_DIF3_REFP (0X00000001U) /* No description provided */
5396#define ENUM_ADC_ADCSEQCHMUX0_DIF2_REFN (0X00000000U) /* No description provided */
5397#define ENUM_ADC_ADCSEQCHMUX0_DIF2_REFP (0X00000001U) /* No description provided */
5398#define ENUM_ADC_ADCSEQCHMUX0_DIF2_AIN1 (0X00000002U) /* No description provided */
5399#define ENUM_ADC_ADCSEQCHMUX0_DIF2_AIN3 (0X00000003U) /* No description provided */
5400#define ENUM_ADC_ADCSEQCHMUX0_DIF2_AIN5 (0X00000004U) /* No description provided */
5401#define ENUM_ADC_ADCSEQCHMUX0_DIF2_AIN7 (0X00000005U) /* No description provided */
5402#define ENUM_ADC_ADCSEQCHMUX0_DIF2_AIN9 (0X00000006U) /* No description provided */
5403#define ENUM_ADC_ADCSEQCHMUX0_DIF2_AIN11 (0X00000007U) /* No description provided */
5404#define ENUM_ADC_ADCSEQCHMUX0_DIF2_AIN13 (0X00000008U) /* No description provided */
5405#define ENUM_ADC_ADCSEQCHMUX0_DIF2_AIN15 (0X00000009U) /* No description provided */
5406#define ENUM_ADC_ADCSEQCHMUX0_DIF1_REFN (0X00000000U) /* No description provided */
5407#define ENUM_ADC_ADCSEQCHMUX0_DIF1_REFP (0X00000001U) /* No description provided */
5408#define ENUM_ADC_ADCSEQCHMUX0_DIF0_REFN (0X00000000U) /* No description provided */
5409#define ENUM_ADC_ADCSEQCHMUX0_DIF0_REFP (0X00000001U) /* No description provided */
5410#define ENUM_ADC_ADCSEQCHMUX0_DIF0_AIN1 (0X00000002U) /* No description provided */
5411#define ENUM_ADC_ADCSEQCHMUX0_DIF0_AIN3 (0X00000003U) /* No description provided */
5412#define ENUM_ADC_ADCSEQCHMUX0_DIF0_AIN5 (0X00000004U) /* No description provided */
5413#define ENUM_ADC_ADCSEQCHMUX0_DIF0_AIN7 (0X00000005U) /* No description provided */
5414#define ENUM_ADC_ADCSEQCHMUX0_DIF0_AIN9 (0X00000006U) /* No description provided */
5415#define ENUM_ADC_ADCSEQCHMUX0_DIF0_AIN11 (0X00000007U) /* No description provided */
5416#define ENUM_ADC_ADCSEQCHMUX0_DIF0_AIN13 (0X00000008U) /* No description provided */
5417#define ENUM_ADC_ADCSEQCHMUX0_DIF0_AIN15 (0X00000009U) /* No description provided */
5418
5419/* ----------------------------------------------------------------------------------------------------
5420 ADCSEQCHMUX1 Value Description
5421 ---------------------------------------------------------------------------------------------------- */
5422#define BITP_ADC_ADCSEQCHMUX1_DIF12 (0U) /* When AIN12 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5423#define BITL_ADC_ADCSEQCHMUX1_DIF12 (4U) /* When AIN12 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5424#define BITM_ADC_ADCSEQCHMUX1_DIF12 (0X0000000FU) /* When AIN12 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5425#define BITP_ADC_ADCSEQCHMUX1_DIF13 (4U) /* When AIN13 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5426#define BITL_ADC_ADCSEQCHMUX1_DIF13 (1U) /* When AIN13 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5427#define BITM_ADC_ADCSEQCHMUX1_DIF13 (0X00000010U) /* When AIN13 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5428#define BITP_ADC_ADCSEQCHMUX1_DIF14 (5U) /* When AIN14 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5429#define BITL_ADC_ADCSEQCHMUX1_DIF14 (4U) /* When AIN14 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5430#define BITM_ADC_ADCSEQCHMUX1_DIF14 (0X000001E0U) /* When AIN14 is P Ch. N Ch. Mux Selection in Sequencer Mode */
5431#define BITP_ADC_ADCSEQCHMUX1_DIF15 (9U) /* When AIN15 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5432#define BITL_ADC_ADCSEQCHMUX1_DIF15 (1U) /* When AIN15 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5433#define BITM_ADC_ADCSEQCHMUX1_DIF15 (0X00000200U) /* When AIN15 is N Ch. P Ch. Mux Selection in Sequencer Mode */
5434
5435#define ENUM_ADC_ADCSEQCHMUX1_DIF15_REFN (0X00000000U) /* No description provided */
5436#define ENUM_ADC_ADCSEQCHMUX1_DIF15_REFP (0X00000001U) /* No description provided */
5437#define ENUM_ADC_ADCSEQCHMUX1_DIF14_REFN (0X00000000U) /* No description provided */
5438#define ENUM_ADC_ADCSEQCHMUX1_DIF14_REFP (0X00000001U) /* No description provided */
5439#define ENUM_ADC_ADCSEQCHMUX1_DIF14_AIN1 (0X00000002U) /* No description provided */
5440#define ENUM_ADC_ADCSEQCHMUX1_DIF14_AIN3 (0X00000003U) /* No description provided */
5441#define ENUM_ADC_ADCSEQCHMUX1_DIF14_AIN5 (0X00000004U) /* No description provided */
5442#define ENUM_ADC_ADCSEQCHMUX1_DIF14_AIN7 (0X00000005U) /* No description provided */
5443#define ENUM_ADC_ADCSEQCHMUX1_DIF14_AIN9 (0X00000006U) /* No description provided */
5444#define ENUM_ADC_ADCSEQCHMUX1_DIF14_AIN11 (0X00000007U) /* No description provided */
5445#define ENUM_ADC_ADCSEQCHMUX1_DIF14_AIN13 (0X00000008U) /* No description provided */
5446#define ENUM_ADC_ADCSEQCHMUX1_DIF14_AIN15 (0X00000009U) /* No description provided */
5447#define ENUM_ADC_ADCSEQCHMUX1_DIF13_REFN (0X00000000U) /* No description provided */
5448#define ENUM_ADC_ADCSEQCHMUX1_DIF13_REFP (0X00000001U) /* No description provided */
5449#define ENUM_ADC_ADCSEQCHMUX1_DIF12_REFN (0X00000000U) /* No description provided */
5450#define ENUM_ADC_ADCSEQCHMUX1_DIF12_REFP (0X00000001U) /* No description provided */
5451#define ENUM_ADC_ADCSEQCHMUX1_DIF12_AIN1 (0X00000002U) /* No description provided */
5452#define ENUM_ADC_ADCSEQCHMUX1_DIF12_AIN3 (0X00000003U) /* No description provided */
5453#define ENUM_ADC_ADCSEQCHMUX1_DIF12_AIN5 (0X00000004U) /* No description provided */
5454#define ENUM_ADC_ADCSEQCHMUX1_DIF12_AIN7 (0X00000005U) /* No description provided */
5455#define ENUM_ADC_ADCSEQCHMUX1_DIF12_AIN9 (0X00000006U) /* No description provided */
5456#define ENUM_ADC_ADCSEQCHMUX1_DIF12_AIN11 (0X00000007U) /* No description provided */
5457#define ENUM_ADC_ADCSEQCHMUX1_DIF12_AIN13 (0X00000008U) /* No description provided */
5458#define ENUM_ADC_ADCSEQCHMUX1_DIF12_AIN15 (0X00000009U) /* No description provided */
5459
5460/* ----------------------------------------------------------------------------------------------------
5461 ADCCMP Value Description
5462 ---------------------------------------------------------------------------------------------------- */
5463#define BITP_ADC_ADCCMP_EN (0U) /* Digital Comparator Enable */
5464#define BITL_ADC_ADCCMP_EN (1U) /* Digital Comparator Enable */
5465#define BITM_ADC_ADCCMP_EN (0X00000001U) /* Digital Comparator Enable */
5466#define BITP_ADC_ADCCMP_CMPDIR (1U) /* Select Digital Comparator Direction */
5467#define BITL_ADC_ADCCMP_CMPDIR (1U) /* Select Digital Comparator Direction */
5468#define BITM_ADC_ADCCMP_CMPDIR (0X00000002U) /* Select Digital Comparator Direction */
5469#define BITP_ADC_ADCCMP_THR (2U) /* Compare Threshold */
5470#define BITL_ADC_ADCCMP_THR (16U) /* Compare Threshold */
5471#define BITM_ADC_ADCCMP_THR (0X0003FFFCU) /* Compare Threshold */
5472#define BITP_ADC_ADCCMP_IRQEN (18U) /* Enable IRQ Generation */
5473#define BITL_ADC_ADCCMP_IRQEN (1U) /* Enable IRQ Generation */
5474#define BITM_ADC_ADCCMP_IRQEN (0X00040000U) /* Enable IRQ Generation */
5475#define BITP_ADC_ADCCMP_CH (19U) /* Channel Index for Data Comparison */
5476#define BITL_ADC_ADCCMP_CH (5U) /* Channel Index for Data Comparison */
5477#define BITM_ADC_ADCCMP_CH (0X00F80000U) /* Channel Index for Data Comparison */
5478
5479/* ----------------------------------------------------------------------------------------------------
5480 ADCCMPIRQSTAT Value Description
5481 ---------------------------------------------------------------------------------------------------- */
5482#define BITP_ADC_ADCCMPIRQSTAT_COMP0IRQSTA (0U) /* Comparator0 Interrupt Status */
5483#define BITL_ADC_ADCCMPIRQSTAT_COMP0IRQSTA (1U) /* Comparator0 Interrupt Status */
5484#define BITM_ADC_ADCCMPIRQSTAT_COMP0IRQSTA (0X00000001U) /* Comparator0 Interrupt Status */
5485#define BITP_ADC_ADCCMPIRQSTAT_COMP1IRQSTA (1U) /* Comparator1 Interrupt Status */
5486#define BITL_ADC_ADCCMPIRQSTAT_COMP1IRQSTA (1U) /* Comparator1 Interrupt Status */
5487#define BITM_ADC_ADCCMPIRQSTAT_COMP1IRQSTA (0X00000002U) /* Comparator1 Interrupt Status */
5488#define BITP_ADC_ADCCMPIRQSTAT_COMP2IRQSTA (2U) /* Comparator2 Interrupt Status */
5489#define BITL_ADC_ADCCMPIRQSTAT_COMP2IRQSTA (1U) /* Comparator2 Interrupt Status */
5490#define BITM_ADC_ADCCMPIRQSTAT_COMP2IRQSTA (0X00000004U) /* Comparator2 Interrupt Status */
5491#define BITP_ADC_ADCCMPIRQSTAT_COMP3IRQSTA (3U) /* Comparator3 Interrupt Status */
5492#define BITL_ADC_ADCCMPIRQSTAT_COMP3IRQSTA (1U) /* Comparator3 Interrupt Status */
5493#define BITM_ADC_ADCCMPIRQSTAT_COMP3IRQSTA (0X00000008U) /* Comparator3 Interrupt Status */
5494#define BITP_ADC_ADCCMPIRQSTAT_COMP0IRQCLR (4U) /* Comparator0 Interrupt Clear */
5495#define BITL_ADC_ADCCMPIRQSTAT_COMP0IRQCLR (1U) /* Comparator0 Interrupt Clear */
5496#define BITM_ADC_ADCCMPIRQSTAT_COMP0IRQCLR (0X00000010U) /* Comparator0 Interrupt Clear */
5497#define BITP_ADC_ADCCMPIRQSTAT_COMP1IRQCLR (5U) /* Comparator1 Interrupt Clear */
5498#define BITL_ADC_ADCCMPIRQSTAT_COMP1IRQCLR (1U) /* Comparator1 Interrupt Clear */
5499#define BITM_ADC_ADCCMPIRQSTAT_COMP1IRQCLR (0X00000020U) /* Comparator1 Interrupt Clear */
5500#define BITP_ADC_ADCCMPIRQSTAT_COMP2IRQCLR (6U) /* Comparator2 Interrupt Clear */
5501#define BITL_ADC_ADCCMPIRQSTAT_COMP2IRQCLR (1U) /* Comparator2 Interrupt Clear */
5502#define BITM_ADC_ADCCMPIRQSTAT_COMP2IRQCLR (0X00000040U) /* Comparator2 Interrupt Clear */
5503#define BITP_ADC_ADCCMPIRQSTAT_COMP3IRQCLR (7U) /* Comparator3 Interrupt Clear */
5504#define BITL_ADC_ADCCMPIRQSTAT_COMP3IRQCLR (1U) /* Comparator3 Interrupt Clear */
5505#define BITM_ADC_ADCCMPIRQSTAT_COMP3IRQCLR (0X00000080U) /* Comparator3 Interrupt Clear */
5506#define BITP_ADC_ADCCMPIRQSTAT_COMP0PLACLR (8U) /* Comparator0 to PLA Clear */
5507#define BITL_ADC_ADCCMPIRQSTAT_COMP0PLACLR (1U) /* Comparator0 to PLA Clear */
5508#define BITM_ADC_ADCCMPIRQSTAT_COMP0PLACLR (0X00000100U) /* Comparator0 to PLA Clear */
5509#define BITP_ADC_ADCCMPIRQSTAT_COMP1PLACLR (9U) /* Comparator1 to PLA Clear */
5510#define BITL_ADC_ADCCMPIRQSTAT_COMP1PLACLR (1U) /* Comparator1 to PLA Clear */
5511#define BITM_ADC_ADCCMPIRQSTAT_COMP1PLACLR (0X00000200U) /* Comparator1 to PLA Clear */
5512#define BITP_ADC_ADCCMPIRQSTAT_COMP2PLACLR (10U) /* Comparator2 to PLA Clear */
5513#define BITL_ADC_ADCCMPIRQSTAT_COMP2PLACLR (1U) /* Comparator2 to PLA Clear */
5514#define BITM_ADC_ADCCMPIRQSTAT_COMP2PLACLR (0X00000400U) /* Comparator2 to PLA Clear */
5515#define BITP_ADC_ADCCMPIRQSTAT_COMP3PLACLR (11U) /* Comparator3 to PLA Clear */
5516#define BITL_ADC_ADCCMPIRQSTAT_COMP3PLACLR (1U) /* Comparator3 to PLA Clear */
5517#define BITM_ADC_ADCCMPIRQSTAT_COMP3PLACLR (0X00000800U) /* Comparator3 to PLA Clear */
5518
5519/* ----------------------------------------------------------------------------------------------------
5520 ADCOFGNDIFF Value Description
5521 ---------------------------------------------------------------------------------------------------- */
5522#define BITP_ADC_ADCOFGNDIFF_GAIN (0U) /* Gain Error Correction */
5523#define BITL_ADC_ADCOFGNDIFF_GAIN (15U) /* Gain Error Correction */
5524#define BITM_ADC_ADCOFGNDIFF_GAIN (0X00007FFFU) /* Gain Error Correction */
5525#define BITP_ADC_ADCOFGNDIFF_OFFSET (15U) /* Offset Error Correction */
5526#define BITL_ADC_ADCOFGNDIFF_OFFSET (17U) /* Offset Error Correction */
5527#define BITM_ADC_ADCOFGNDIFF_OFFSET (0XFFFF8000U) /* Offset Error Correction */
5528
5529/* ----------------------------------------------------------------------------------------------------
5530 ADCOFTEMP Value Description
5531 ---------------------------------------------------------------------------------------------------- */
5532#define BITP_ADC_ADCOFTEMP_OFFSET (0U) /* Offset Error Correction */
5533#define BITL_ADC_ADCOFTEMP_OFFSET (17U) /* Offset Error Correction */
5534#define BITM_ADC_ADCOFTEMP_OFFSET (0X0001FFFFU) /* Offset Error Correction */
5535
5536/* ----------------------------------------------------------------------------------------------------
5537 ADCGNTEMP Value Description
5538 ---------------------------------------------------------------------------------------------------- */
5539#define BITP_ADC_ADCGNTEMP_GAIN (0U) /* Gain Error Correction */
5540#define BITL_ADC_ADCGNTEMP_GAIN (20U) /* Gain Error Correction */
5541#define BITM_ADC_ADCGNTEMP_GAIN (0X000FFFFFU) /* Gain Error Correction */
5542
5543/* ----------------------------------------------------------------------------------------------------
5544 ADCOFGNPGA0 Value Description
5545 ---------------------------------------------------------------------------------------------------- */
5546#define BITP_ADC_ADCOFGNPGA0_GAIN (0U) /* Gain Error Correction */
5547#define BITL_ADC_ADCOFGNPGA0_GAIN (15U) /* Gain Error Correction */
5548#define BITM_ADC_ADCOFGNPGA0_GAIN (0X00007FFFU) /* Gain Error Correction */
5549
5550/* ----------------------------------------------------------------------------------------------------
5551 ADCOFGNPGA1 Value Description
5552 ---------------------------------------------------------------------------------------------------- */
5553#define BITP_ADC_ADCOFGNPGA1_GAIN (0U) /* Gain Error Correction */
5554#define BITL_ADC_ADCOFGNPGA1_GAIN (15U) /* Gain Error Correction */
5555#define BITM_ADC_ADCOFGNPGA1_GAIN (0X00007FFFU) /* Gain Error Correction */
5556
5557/* ----------------------------------------------------------------------------------------------------
5558 ADCOFGNPGA2 Value Description
5559 ---------------------------------------------------------------------------------------------------- */
5560#define BITP_ADC_ADCOFGNPGA2_GAIN (0U) /* Gain Error Correction */
5561#define BITL_ADC_ADCOFGNPGA2_GAIN (15U) /* Gain Error Correction */
5562#define BITM_ADC_ADCOFGNPGA2_GAIN (0X00007FFFU) /* Gain Error Correction */
5563
5564/* ----------------------------------------------------------------------------------------------------
5565 ADCOFGNPGA3 Value Description
5566 ---------------------------------------------------------------------------------------------------- */
5567#define BITP_ADC_ADCOFGNPGA3_GAIN (0U) /* Gain Error Correction */
5568#define BITL_ADC_ADCOFGNPGA3_GAIN (15U) /* Gain Error Correction */
5569#define BITM_ADC_ADCOFGNPGA3_GAIN (0X00007FFFU) /* Gain Error Correction */
5570
5571/* ----------------------------------------------------------------------------------------------------
5572 ADCOFGNPGA0TIA Value Description
5573 ---------------------------------------------------------------------------------------------------- */
5574#define BITP_ADC_ADCOFGNPGA0TIA_GAIN (0U) /* Gain Error Correction */
5575#define BITL_ADC_ADCOFGNPGA0TIA_GAIN (15U) /* Gain Error Correction */
5576#define BITM_ADC_ADCOFGNPGA0TIA_GAIN (0X00007FFFU) /* Gain Error Correction */
5577
5578/* ----------------------------------------------------------------------------------------------------
5579 ADCOFGNPGA1TIA Value Description
5580 ---------------------------------------------------------------------------------------------------- */
5581#define BITP_ADC_ADCOFGNPGA1TIA_GAIN (0U) /* Gain Error Correction */
5582#define BITL_ADC_ADCOFGNPGA1TIA_GAIN (15U) /* Gain Error Correction */
5583#define BITM_ADC_ADCOFGNPGA1TIA_GAIN (0X00007FFFU) /* Gain Error Correction */
5584
5585/* ----------------------------------------------------------------------------------------------------
5586 ADCOFGNPGA2TIA Value Description
5587 ---------------------------------------------------------------------------------------------------- */
5588#define BITP_ADC_ADCOFGNPGA2TIA_GAIN (0U) /* Gain Error Correction */
5589#define BITL_ADC_ADCOFGNPGA2TIA_GAIN (15U) /* Gain Error Correction */
5590#define BITM_ADC_ADCOFGNPGA2TIA_GAIN (0X00007FFFU) /* Gain Error Correction */
5591
5592/* ----------------------------------------------------------------------------------------------------
5593 ADCOFGNPGA3TIA Value Description
5594 ---------------------------------------------------------------------------------------------------- */
5595#define BITP_ADC_ADCOFGNPGA3TIA_GAIN (0U) /* Gain Error Correction */
5596#define BITL_ADC_ADCOFGNPGA3TIA_GAIN (15U) /* Gain Error Correction */
5597#define BITM_ADC_ADCOFGNPGA3TIA_GAIN (0X00007FFFU) /* Gain Error Correction */
5598
5599/* ----------------------------------------------------------------------------------------------------
5600 ADCCMP1 Value Description
5601 ---------------------------------------------------------------------------------------------------- */
5602#define BITP_ADC_ADCCMP1_EN (0U) /* Digital Comparator Enable */
5603#define BITL_ADC_ADCCMP1_EN (1U) /* Digital Comparator Enable */
5604#define BITM_ADC_ADCCMP1_EN (0X00000001U) /* Digital Comparator Enable */
5605#define BITP_ADC_ADCCMP1_CMPDIR (1U) /* Select Digital Comparator Direction */
5606#define BITL_ADC_ADCCMP1_CMPDIR (1U) /* Select Digital Comparator Direction */
5607#define BITM_ADC_ADCCMP1_CMPDIR (0X00000002U) /* Select Digital Comparator Direction */
5608#define BITP_ADC_ADCCMP1_THR (2U) /* Compare Threshold */
5609#define BITL_ADC_ADCCMP1_THR (16U) /* Compare Threshold */
5610#define BITM_ADC_ADCCMP1_THR (0X0003FFFCU) /* Compare Threshold */
5611#define BITP_ADC_ADCCMP1_IRQEN (18U) /* Enable IRQ Generation */
5612#define BITL_ADC_ADCCMP1_IRQEN (1U) /* Enable IRQ Generation */
5613#define BITM_ADC_ADCCMP1_IRQEN (0X00040000U) /* Enable IRQ Generation */
5614#define BITP_ADC_ADCCMP1_CH (19U) /* Channel Index for Data Comparison */
5615#define BITL_ADC_ADCCMP1_CH (5U) /* Channel Index for Data Comparison */
5616#define BITM_ADC_ADCCMP1_CH (0X00F80000U) /* Channel Index for Data Comparison */
5617
5618/* ----------------------------------------------------------------------------------------------------
5619 ADCCMP2 Value Description
5620 ---------------------------------------------------------------------------------------------------- */
5621#define BITP_ADC_ADCCMP2_EN (0U) /* Digital Comparator Enable */
5622#define BITL_ADC_ADCCMP2_EN (1U) /* Digital Comparator Enable */
5623#define BITM_ADC_ADCCMP2_EN (0X00000001U) /* Digital Comparator Enable */
5624#define BITP_ADC_ADCCMP2_CMPDIR (1U) /* Select Digital Comparator Direction */
5625#define BITL_ADC_ADCCMP2_CMPDIR (1U) /* Select Digital Comparator Direction */
5626#define BITM_ADC_ADCCMP2_CMPDIR (0X00000002U) /* Select Digital Comparator Direction */
5627#define BITP_ADC_ADCCMP2_THR (2U) /* Compare Threshold */
5628#define BITL_ADC_ADCCMP2_THR (16U) /* Compare Threshold */
5629#define BITM_ADC_ADCCMP2_THR (0X0003FFFCU) /* Compare Threshold */
5630#define BITP_ADC_ADCCMP2_IRQEN (18U) /* Enable IRQ Generation */
5631#define BITL_ADC_ADCCMP2_IRQEN (1U) /* Enable IRQ Generation */
5632#define BITM_ADC_ADCCMP2_IRQEN (0X00040000U) /* Enable IRQ Generation */
5633#define BITP_ADC_ADCCMP2_CH (19U) /* Channel Index for Data Comparison */
5634#define BITL_ADC_ADCCMP2_CH (5U) /* Channel Index for Data Comparison */
5635#define BITM_ADC_ADCCMP2_CH (0X00F80000U) /* Channel Index for Data Comparison */
5636
5637/* ----------------------------------------------------------------------------------------------------
5638 ADCCMP3 Value Description
5639 ---------------------------------------------------------------------------------------------------- */
5640#define BITP_ADC_ADCCMP3_EN (0U) /* Digital Comparator Enable */
5641#define BITL_ADC_ADCCMP3_EN (1U) /* Digital Comparator Enable */
5642#define BITM_ADC_ADCCMP3_EN (0X00000001U) /* Digital Comparator Enable */
5643#define BITP_ADC_ADCCMP3_CMPDIR (1U) /* Select Digital Comparator Direction */
5644#define BITL_ADC_ADCCMP3_CMPDIR (1U) /* Select Digital Comparator Direction */
5645#define BITM_ADC_ADCCMP3_CMPDIR (0X00000002U) /* Select Digital Comparator Direction */
5646#define BITP_ADC_ADCCMP3_THR (2U) /* Compare Threshold */
5647#define BITL_ADC_ADCCMP3_THR (16U) /* Compare Threshold */
5648#define BITM_ADC_ADCCMP3_THR (0X0003FFFCU) /* Compare Threshold */
5649#define BITP_ADC_ADCCMP3_IRQEN (18U) /* Enable IRQ Generation */
5650#define BITL_ADC_ADCCMP3_IRQEN (1U) /* Enable IRQ Generation */
5651#define BITM_ADC_ADCCMP3_IRQEN (0X00040000U) /* Enable IRQ Generation */
5652#define BITP_ADC_ADCCMP3_CH (19U) /* Channel Index for Data Comparison */
5653#define BITL_ADC_ADCCMP3_CH (5U) /* Channel Index for Data Comparison */
5654#define BITM_ADC_ADCCMP3_CH (0X00F80000U) /* Channel Index for Data Comparison */
5655
5656#endif /* end ifndef ADC_ADDR_RDEF_H_ */
5657
5658
5659#ifndef COMP_ADDR_RDEF_H_
5660#define COMP_ADDR_RDEF_H_ /* COMP: Your module description, here. */
5661
5662/* ====================================================================================================
5663 COMP Module Instances Address and Mask Definitions
5664 ==================================================================================================== */
5665#define INST_COMP (0X40068A00U) /* comp: */
5666
5667#define MASK_COMP (0X000001FFU) /* COMP: Your module description, here. */
5668
5669/* ====================================================================================================
5670 COMP Module Register Address Offset Definitions
5671 ==================================================================================================== */
5672#define IDX_COMP_COMPCON0 (0X000U) /* No description provided */
5673#define IDX_COMP_COMPCON1 (0X004U) /* No description provided */
5674#define IDX_COMP_COMPCON2 (0X008U) /* No description provided */
5675#define IDX_COMP_COMPCON3 (0X00CU) /* No description provided */
5676#define IDX_COMP_COMPIRQSTAT (0X010U) /* No description provided */
5677
5678/* ====================================================================================================
5679 COMP Module Register ResetValue Definitions
5680 ==================================================================================================== */
5681#define RSTVAL_COMP_COMPCON0 (0X60)
5682#define RSTVAL_COMP_COMPCON1 (0X60)
5683#define RSTVAL_COMP_COMPCON2 (0X60)
5684#define RSTVAL_COMP_COMPCON3 (0X60)
5685#define RSTVAL_COMP_COMPIRQSTAT (0X0)
5686
5687/* ====================================================================================================
5688 COMP Module Register BitPositions, Lengths, Masks and Enumerations Definitions
5689 ==================================================================================================== */
5690
5691/* ----------------------------------------------------------------------------------------------------
5692 COMPCON0 Value Description
5693 ---------------------------------------------------------------------------------------------------- */
5694#define BITP_COMP_COMPCON_N__HYS (0U) /* Comp Hysteresis Register */
5695#define BITL_COMP_COMPCON_N__HYS (5U) /* Comp Hysteresis Register */
5696#define BITM_COMP_COMPCON_N__HYS (0X0000001FU) /* Comp Hysteresis Register */
5697#define BITP_COMP_COMPCON_N__INV (7U) /* Select Output Logic State */
5698#define BITL_COMP_COMPCON_N__INV (1U) /* Select Output Logic State */
5699#define BITM_COMP_COMPCON_N__INV (0X00000080U) /* Select Output Logic State */
5700#define BITP_COMP_COMPCON_N__OUT (8U) /* Comp Interrupt Select */
5701#define BITL_COMP_COMPCON_N__OUT (2U) /* Comp Interrupt Select */
5702#define BITM_COMP_COMPCON_N__OUT (0X00000300U) /* Comp Interrupt Select */
5703#define BITP_COMP_COMPCON_N__INNEG (10U) /* Select Comparator Negative Input Source */
5704#define BITL_COMP_COMPCON_N__INNEG (3U) /* Select Comparator Negative Input Source */
5705#define BITM_COMP_COMPCON_N__INNEG (0X00001C00U) /* Select Comparator Negative Input Source */
5706#define BITP_COMP_COMPCON_N__INPOS (13U) /* Select Comparator Positive Input Source */
5707#define BITL_COMP_COMPCON_N__INPOS (3U) /* Select Comparator Positive Input Source */
5708#define BITM_COMP_COMPCON_N__INPOS (0X0000E000U) /* Select Comparator Positive Input Source */
5709#define BITP_COMP_COMPCON_N__HYSTYP (16U) /* Select Hysteresis Type */
5710#define BITL_COMP_COMPCON_N__HYSTYP (1U) /* Select Hysteresis Type */
5711#define BITM_COMP_COMPCON_N__HYSTYP (0X00010000U) /* Select Hysteresis Type */
5712#define BITP_COMP_COMPCON_N__EN (17U) /* Enable Comparator */
5713#define BITL_COMP_COMPCON_N__EN (1U) /* Enable Comparator */
5714#define BITM_COMP_COMPCON_N__EN (0X00020000U) /* Enable Comparator */
5715#define BITP_COMP_COMPCON_N__INTEN (18U) /* Interrupt Enable */
5716#define BITL_COMP_COMPCON_N__INTEN (1U) /* Interrupt Enable */
5717#define BITM_COMP_COMPCON_N__INTEN (0X00040000U) /* Interrupt Enable */
5718#define BITP_COMP_COMPCON_N__INTMODE (19U) /* Interrupt Mode */
5719#define BITL_COMP_COMPCON_N__INTMODE (2U) /* Interrupt Mode */
5720#define BITM_COMP_COMPCON_N__INTMODE (0X00180000U) /* Interrupt Mode */
5721
5722#define ENUM_COMP_COMPCON_N__INTMODE_RISEEDGE (0X00000000U) /* Generate Interrupt if Rising Edge Happens */
5723#define ENUM_COMP_COMPCON_N__INTMODE_FALLEDGE (0X00000001U) /* Generate Interrupt if Falling Edge Happens */
5724#define ENUM_COMP_COMPCON_N__INTMODE_LOWLEVEL (0X00000002U) /* Generate Interrupt if Low Level Happens */
5725#define ENUM_COMP_COMPCON_N__INTMODE_HIGHLEVEL (0X00000003U) /* Generate Interrupt if High Level Happens */
5726#define ENUM_COMP_COMPCON_N__HYSTYP_EXTHYS (0X00000000U) /* Select External Hysteresis */
5727#define ENUM_COMP_COMPCON_N__HYSTYP_INTHYS (0X00000001U) /* Select Internal Hysteresis */
5728#define ENUM_COMP_COMPCON_N__INPOS_NO_INPUT (0X00000000U) /* All Input Switches Off */
5729#define ENUM_COMP_COMPCON_N__INPOS_AINXP (0X00000001U) /* Enable AIN8/10/12/14 for comp 0/1/2/3 */
5730#define ENUM_COMP_COMPCON_N__INPOS_PGAIN (0X00000002U) /* Enable PGA0/1/2/3 for comp 0/1/2/3 */
5731#define ENUM_COMP_COMPCON_N__INPOS_GPIO_ANAIN (0X00000003U) /* Enable GPIO0.6/0.7/2.0/2.1 Analog Signal Input for comp 0/1/2/3 */
5732#define ENUM_COMP_COMPCON_N__INNEG_NO_INPUT (0X00000000U) /* All Input Switches Off */
5733#define ENUM_COMP_COMPCON_N__INNEG_AHIDIV2IN (0X00000001U) /* Enable Half Avdd Input */
5734#define ENUM_COMP_COMPCON_N__INNEG_AINXN (0X00000002U) /* Enable AIN9/11/13/15 for Comp 0/1/2/3 */
5735#define ENUM_COMP_COMPCON_N__INNEG_VDAC8IN (0X00000003U) /* Enable VDAC8 Input */
5736#define ENUM_COMP_COMPCON_N__INNEG_VDAC9IN (0X00000004U) /* Enable VDAC9 Input */
5737#define ENUM_COMP_COMPCON_N__INNEG_VDAC10IN (0X00000005U) /* Enable VDAC10 Input */
5738#define ENUM_COMP_COMPCON_N__INNEG_VDAC11IN (0X00000006U) /* Enable VDAC11 Input */
5739#define ENUM_COMP_COMPCON_N__INNEG_V1P25REFIN (0X00000007U) /* Enable 1.25V Ref Input from AIN15(BUF1) */
5740#define ENUM_COMP_COMPCON_N__OUT_DIS00 (0X00000000U) /* Output to Test Pad Disable */
5741#define ENUM_COMP_COMPCON_N__OUT_DIS01 (0X00000001U) /* Output to Test Pad Disable */
5742#define ENUM_COMP_COMPCON_N__OUT_EN10 (0X00000002U) /* Output to Test Pad Enable */
5743#define ENUM_COMP_COMPCON_N__OUT_DIS11 (0X00000003U) /* Output to Test Pad Disable */
5744#define ENUM_COMP_COMPCON_N__INV_NOM (0X00000000U) /* Output is High if +ve is higher than -ve input */
5745#define ENUM_COMP_COMPCON_N__INV_COV (0X00000001U) /* Output is High if -ve is higher than +ve input */
5746#define ENUM_COMP_COMPCON_N__HYS_DIS (0X00000000U) /* hysteresis disabled */
5747#define ENUM_COMP_COMPCON_N__HYS_EN10MV (0X00000001U) /* 10mv hysteresis enabled */
5748#define ENUM_COMP_COMPCON_N__HYS_EN25MV (0X00000002U) /* 25mv hysteresis */
5749#define ENUM_COMP_COMPCON_N__HYS_EN35MV (0X00000003U) /* 35mv hysteresis */
5750#define ENUM_COMP_COMPCON_N__HYS_EN50MV (0X00000006U) /* 50mv hysteresis */
5751#define ENUM_COMP_COMPCON_N__HYS_EN60MV (0X00000007U) /* 60mv hysteresis */
5752#define ENUM_COMP_COMPCON_N__HYS_EN75MV (0X0000000CU) /* 75mv hysteresis */
5753#define ENUM_COMP_COMPCON_N__HYS_EN85MV (0X0000000DU) /* 85mv hysteresis */
5754#define ENUM_COMP_COMPCON_N__HYS_EN100MV (0X0000000EU) /* 100mv hysteresis */
5755#define ENUM_COMP_COMPCON_N__HYS_EN110MV (0X00000011U) /* 110mv hysteresis */
5756#define ENUM_COMP_COMPCON_N__HYS_EN125MV (0X00000012U) /* 125mv hysteresis */
5757#define ENUM_COMP_COMPCON_N__HYS_EN135MV (0X00000013U) /* 135mv hysteresis */
5758#define ENUM_COMP_COMPCON_N__HYS_EN150MV (0X00000016U) /* 150mv hysteresis */
5759#define ENUM_COMP_COMPCON_N__HYS_EN160MV (0X00000017U) /* 160mv hysteresis */
5760#define ENUM_COMP_COMPCON_N__HYS_EN175MV (0X0000001CU) /* 175mv hysteresis */
5761#define ENUM_COMP_COMPCON_N__HYS_EN185MV (0X0000001DU) /* 185mv hysteresis */
5762#define ENUM_COMP_COMPCON_N__HYS_EN200MV (0X0000001EU) /* 200mv hysteresis */
5763#define ENUM_COMP_COMPCON_N__HYS_EN210MV (0X0000001FU) /* 210mv hysteresis */
5764
5765/* ----------------------------------------------------------------------------------------------------
5766 COMPIRQSTAT Value Description
5767 ---------------------------------------------------------------------------------------------------- */
5768#define BITP_COMP_COMPIRQSTAT_COMP0 (0U) /* Comparator 0 Interrupt Status */
5769#define BITL_COMP_COMPIRQSTAT_COMP0 (1U) /* Comparator 0 Interrupt Status */
5770#define BITM_COMP_COMPIRQSTAT_COMP0 (0X00000001U) /* Comparator 0 Interrupt Status */
5771#define BITP_COMP_COMPIRQSTAT_COMP1 (1U) /* Comparator 1 Interrupt Status */
5772#define BITL_COMP_COMPIRQSTAT_COMP1 (1U) /* Comparator 1 Interrupt Status */
5773#define BITM_COMP_COMPIRQSTAT_COMP1 (0X00000002U) /* Comparator 1 Interrupt Status */
5774#define BITP_COMP_COMPIRQSTAT_COMP2 (2U) /* Comparator 2 Interrupt Status */
5775#define BITL_COMP_COMPIRQSTAT_COMP2 (1U) /* Comparator 2 Interrupt Status */
5776#define BITM_COMP_COMPIRQSTAT_COMP2 (0X00000004U) /* Comparator 2 Interrupt Status */
5777#define BITP_COMP_COMPIRQSTAT_COMP3 (3U) /* Comparator 3 Interrupt Status */
5778#define BITL_COMP_COMPIRQSTAT_COMP3 (1U) /* Comparator 3 Interrupt Status */
5779#define BITM_COMP_COMPIRQSTAT_COMP3 (0X00000008U) /* Comparator 3 Interrupt Status */
5780
5781#endif /* end ifndef COMP_ADDR_RDEF_H_ */
5782
5783
5784#ifndef OSC_MMRS_ADDR_RDEF_H_
5785#define OSC_MMRS_ADDR_RDEF_H_ /* OSC_MMRS: Your module description, here. */
5786
5787/* ====================================================================================================
5788 OSC_MMRS Module Instances Address and Mask Definitions
5789 ==================================================================================================== */
5790#define INST_OSC (0X40068E00U) /* osc: */
5791
5792#define MASK_OSC_MMRS (0X000001FFU) /* OSC_MMRS: Your module description, here. */
5793
5794/* ====================================================================================================
5795 OSC_MMRS Module Register Address Offset Definitions
5796 ==================================================================================================== */
5797#define IDX_OSC_MMRS_HFOSCCTRL (0X004U) /* No description provided */
5798#define IDX_OSC_MMRS_HFXTALCTRL (0X018U) /* No description provided */
5799
5800/* ====================================================================================================
5801 OSC_MMRS Module Register ResetValue Definitions
5802 ==================================================================================================== */
5803#define RSTVAL_OSC_MMRS_HFOSCCTRL (0X0)
5804#define RSTVAL_OSC_MMRS_HFXTALCTRL (0X2)
5805
5806/* ====================================================================================================
5807 OSC_MMRS Module Register BitPositions, Lengths, Masks and Enumerations Definitions
5808 ==================================================================================================== */
5809
5810/* ----------------------------------------------------------------------------------------------------
5811 HFOSCCTRL Value Description
5812 ---------------------------------------------------------------------------------------------------- */
5813#define BITP_OSC_MMRS_HFOSCCTRL_CLKSEL (0U) /* Selects Either Xtal RC */
5814#define BITL_OSC_MMRS_HFOSCCTRL_CLKSEL (2U) /* Selects Either Xtal RC */
5815#define BITM_OSC_MMRS_HFOSCCTRL_CLKSEL (0X00000003U) /* Selects Either Xtal RC */
5816#define BITP_OSC_MMRS_HFOSCCTRL_PDOSC16M (2U) /* Power Down Pin Oscillator */
5817#define BITL_OSC_MMRS_HFOSCCTRL_PDOSC16M (1U) /* Power Down Pin Oscillator */
5818#define BITM_OSC_MMRS_HFOSCCTRL_PDOSC16M (0X00000004U) /* Power Down Pin Oscillator */
5819
5820#define ENUM_OSC_MMRS_HFOSCCTRL_CLKSEL_SELRC (0X00000000U) /* RC clock */
5821#define ENUM_OSC_MMRS_HFOSCCTRL_CLKSEL_SELXTAL (0X00000001U) /* Xtal clock */
5822#define ENUM_OSC_MMRS_HFOSCCTRL_CLKSEL_SELEXT (0X00000002U) /* External Clock */
5823#define ENUM_OSC_MMRS_HFOSCCTRL_CLKSEL_SELGND (0X00000003U) /* gnd */
5824
5825/* ----------------------------------------------------------------------------------------------------
5826 HFXTALCTRL Value Description
5827 ---------------------------------------------------------------------------------------------------- */
5828#define BITP_OSC_MMRS_HFXTALCTRL_ENXTAL (0U) /* Enable Xtal */
5829#define BITL_OSC_MMRS_HFXTALCTRL_ENXTAL (1U) /* Enable Xtal */
5830#define BITM_OSC_MMRS_HFXTALCTRL_ENXTAL (0X00000001U) /* Enable Xtal */
5831
5832#endif /* end ifndef OSC_MMRS_ADDR_RDEF_H_ */
5833
5834
5835#ifndef PGA_ADDR_RDEF_H_
5836#define PGA_ADDR_RDEF_H_ /* PGA: Your module description, here. */
5837
5838/* ====================================================================================================
5839 PGA Module Instances Address and Mask Definitions
5840 ==================================================================================================== */
5841#define INST_PGA (0X40069000U) /* pga: */
5842
5843#define MASK_PGA (0X000001FFU) /* PGA: Your module description, here. */
5844
5845/* ====================================================================================================
5846 PGA Module Register Address Offset Definitions
5847 ==================================================================================================== */
5848#define IDX_PGA_PGABIASCON (0X000U) /* PGA Bias Circuit Control Signal */
5849#define IDX_PGA_PGA0CON (0X020U) /* PGA0 Control Register */
5850#define IDX_PGA_PGA0CHPCON (0X024U) /* PGA0 Chop Function Ctrl */
5851#define IDX_PGA_PGA3CHPCON (0X028U) /* PGA3 Chop Function Ctrl */
5852#define IDX_PGA_PGA1CON (0X070U) /* PGA1 Control Register */
5853#define IDX_PGA_PGA1CHPCON (0X074U) /* PGA1 Chop Function Ctrl */
5854#define IDX_PGA_PGA2CON (0X0A0U) /* PGA2 Control Register */
5855#define IDX_PGA_PGA2CHPCON (0X0A4U) /* PGA2 Chop Function Ctrl */
5856#define IDX_PGA_PGA3CON (0X0D0U) /* PGA3 Control Register */
5857
5858/* ====================================================================================================
5859 PGA Module Register ResetValue Definitions
5860 ==================================================================================================== */
5861#define RSTVAL_PGA_PGABIASCON (0X3F)
5862#define RSTVAL_PGA_PGA0CON (0X19)
5863#define RSTVAL_PGA_PGA0CHPCON (0X1)
5864#define RSTVAL_PGA_PGA3CHPCON (0X1)
5865#define RSTVAL_PGA_PGA1CON (0X11)
5866#define RSTVAL_PGA_PGA1CHPCON (0X1)
5867#define RSTVAL_PGA_PGA2CON (0X19)
5868#define RSTVAL_PGA_PGA2CHPCON (0X1)
5869#define RSTVAL_PGA_PGA3CON (0X11)
5870
5871/* ====================================================================================================
5872 PGA Module Register BitPositions, Lengths, Masks and Enumerations Definitions
5873 ==================================================================================================== */
5874
5875/* ----------------------------------------------------------------------------------------------------
5876 PGABIASCON Value Description
5877 ---------------------------------------------------------------------------------------------------- */
5878#define BITP_PGA_PGABIASCON_PD0BUF0P2 (0U) /* Buf_200mv Power Down */
5879#define BITL_PGA_PGABIASCON_PD0BUF0P2 (1U) /* Buf_200mv Power Down */
5880#define BITM_PGA_PGABIASCON_PD0BUF0P2 (0X00000001U) /* Buf_200mv Power Down */
5881#define BITP_PGA_PGABIASCON_PD1BUF0P2 (1U) /* Buf_200mv Power Down */
5882#define BITL_PGA_PGABIASCON_PD1BUF0P2 (1U) /* Buf_200mv Power Down */
5883#define BITM_PGA_PGABIASCON_PD1BUF0P2 (0X00000002U) /* Buf_200mv Power Down */
5884#define BITP_PGA_PGABIASCON_PD0BUF1P25 (2U) /* BUF1P25 Power Down */
5885#define BITL_PGA_PGABIASCON_PD0BUF1P25 (1U) /* BUF1P25 Power Down */
5886#define BITM_PGA_PGABIASCON_PD0BUF1P25 (0X00000004U) /* BUF1P25 Power Down */
5887#define BITP_PGA_PGABIASCON_PD1BUF1P25 (3U) /* BUF1P25 Power Down */
5888#define BITL_PGA_PGABIASCON_PD1BUF1P25 (1U) /* BUF1P25 Power Down */
5889#define BITM_PGA_PGABIASCON_PD1BUF1P25 (0X00000008U) /* BUF1P25 Power Down */
5890#define BITP_PGA_PGABIASCON_PD2BUF1P25 (4U) /* BUF1P25 Power Down */
5891#define BITL_PGA_PGABIASCON_PD2BUF1P25 (1U) /* BUF1P25 Power Down */
5892#define BITM_PGA_PGABIASCON_PD2BUF1P25 (0X00000010U) /* BUF1P25 Power Down */
5893#define BITP_PGA_PGABIASCON_PD3BUF1P25 (5U) /* BUF1P25 Power Down */
5894#define BITL_PGA_PGABIASCON_PD3BUF1P25 (1U) /* BUF1P25 Power Down */
5895#define BITM_PGA_PGABIASCON_PD3BUF1P25 (0X00000020U) /* BUF1P25 Power Down */
5896
5897#define ENUM_PGA_PGABIASCON_PD3BUF1P25_ENABLE (0X00000000U) /* BUF1p25 Enable */
5898#define ENUM_PGA_PGABIASCON_PD3BUF1P25_OFF (0X00000001U) /* BUF1p25 Power Down */
5899#define ENUM_PGA_PGABIASCON_PD2BUF1P25_ENABLE (0X00000000U) /* BUF1p25 Enable */
5900#define ENUM_PGA_PGABIASCON_PD2BUF1P25_OFF (0X00000001U) /* BUF1p25 Power Down */
5901#define ENUM_PGA_PGABIASCON_PD1BUF1P25_ENABLE (0X00000000U) /* BUF1p25 Enable */
5902#define ENUM_PGA_PGABIASCON_PD1BUF1P25_OFF (0X00000001U) /* BUF1p25 Power Down */
5903#define ENUM_PGA_PGABIASCON_PD0BUF1P25_ENABLE (0X00000000U) /* BUF1p25 Enable */
5904#define ENUM_PGA_PGABIASCON_PD0BUF1P25_OFF (0X00000001U) /* BUF1p25 Power Down */
5905#define ENUM_PGA_PGABIASCON_PD1BUF0P2_ENABLE (0X00000000U) /* Buf_200mV Enable */
5906#define ENUM_PGA_PGABIASCON_PD1BUF0P2_OFF (0X00000001U) /* Buf_200mv Power Down */
5907#define ENUM_PGA_PGABIASCON_PD0BUF0P2_ENABLE (0X00000000U) /* Buf_200mV Enable */
5908#define ENUM_PGA_PGABIASCON_PD0BUF0P2_OFF (0X00000001U) /* Buf_200mv Power Down */
5909
5910/* ----------------------------------------------------------------------------------------------------
5911 PGA0CON Value Description
5912 ---------------------------------------------------------------------------------------------------- */
5913#define BITP_PGA_PGA0CON_PDPGACORE (0U) /* PGA Core Power Down */
5914#define BITL_PGA_PGA0CON_PDPGACORE (1U) /* PGA Core Power Down */
5915#define BITM_PGA_PGA0CON_PDPGACORE (0X00000001U) /* PGA Core Power Down */
5916#define BITP_PGA_PGA0CON_MODE (1U) /* PGA or TIA Mode Selection */
5917#define BITL_PGA_PGA0CON_MODE (1U) /* PGA or TIA Mode Selection */
5918#define BITM_PGA_PGA0CON_MODE (0X00000002U) /* PGA or TIA Mode Selection */
5919#define BITP_PGA_PGA0CON_PGAMODE (2U) /* PGA DC Mode or AC Couple Mode Selection */
5920#define BITL_PGA_PGA0CON_PGAMODE (1U) /* PGA DC Mode or AC Couple Mode Selection */
5921#define BITM_PGA_PGA0CON_PGAMODE (0X00000004U) /* PGA DC Mode or AC Couple Mode Selection */
5922#define BITP_PGA_PGA0CON_CAPBYPASS (3U) /* Bypass the External Cap */
5923#define BITL_PGA_PGA0CON_CAPBYPASS (1U) /* Bypass the External Cap */
5924#define BITM_PGA_PGA0CON_CAPBYPASS (0X00000008U) /* Bypass the External Cap */
5925#define BITP_PGA_PGA0CON_PGAGAIN (5U) /* PGA Gain Configuration */
5926#define BITL_PGA_PGA0CON_PGAGAIN (3U) /* PGA Gain Configuration */
5927#define BITM_PGA_PGA0CON_PGAGAIN (0X000000E0U) /* PGA Gain Configuration */
5928#define BITP_PGA_PGA0CON_TIAGAIN (8U) /* TIA Gain Configuration */
5929#define BITL_PGA_PGA0CON_TIAGAIN (3U) /* TIA Gain Configuration */
5930#define BITM_PGA_PGA0CON_TIAGAIN (0X00000700U) /* TIA Gain Configuration */
5931#define BITP_PGA_PGA0CON_TIAVDACSEL (11U) /* TIA Vbias Selection of VDAC Channel */
5932#define BITL_PGA_PGA0CON_TIAVDACSEL (2U) /* TIA Vbias Selection of VDAC Channel */
5933#define BITM_PGA_PGA0CON_TIAVDACSEL (0X00001800U) /* TIA Vbias Selection of VDAC Channel */
5934#define BITP_PGA_PGA0CON_DRVEN (14U) /* Sink Current Ability Improve */
5935#define BITL_PGA_PGA0CON_DRVEN (1U) /* Sink Current Ability Improve */
5936#define BITM_PGA_PGA0CON_DRVEN (0X00004000U) /* Sink Current Ability Improve */
5937#define BITP_PGA_PGA0CON_TIASRCEN (15U) /* Select Between Source Mode and Sink Mode */
5938#define BITL_PGA_PGA0CON_TIASRCEN (1U) /* Select Between Source Mode and Sink Mode */
5939#define BITM_PGA_PGA0CON_TIASRCEN (0X00008000U) /* Select Between Source Mode and Sink Mode */
5940
5941#define ENUM_PGA_PGA0CON_TIASRCEN_SINKMD (0X00000000U) /* Sink Mode */
5942#define ENUM_PGA_PGA0CON_TIASRCEN_SOURCEMD (0X00000001U) /* Source Mode */
5943#define ENUM_PGA_PGA0CON_DRVEN_DRVDISABLE (0X00000000U) /* Disable Isink Ability Improvement, Normal Drive */
5944#define ENUM_PGA_PGA0CON_DRVEN_DRVENABLE (0X00000001U) /* Enable Isink Ability Improvement */
5945#define ENUM_PGA_PGA0CON_TIAVDACSEL_VDAC8SEL (0X00000000U) /* Select VDAC8 as TIA Vbias */
5946#define ENUM_PGA_PGA0CON_TIAVDACSEL_VDAC9SEL (0X00000001U) /* Select VDAC9 as TIA Vbias */
5947#define ENUM_PGA_PGA0CON_TIAVDACSEL_VDAC10SEL (0X00000002U) /* Select VDAC10 as TIA Vbias */
5948#define ENUM_PGA_PGA0CON_TIAVDACSEL_VDAC11SEL (0X00000003U) /* Select VDAC11 as TIA Vbias */
5949#define ENUM_PGA_PGA0CON_TIAGAIN_RES250 (0X00000000U) /* TIARES=250ohm */
5950#define ENUM_PGA_PGA0CON_TIAGAIN_RES750 (0X00000001U) /* TIARES=750ohm */
5951#define ENUM_PGA_PGA0CON_TIAGAIN_RES2K (0X00000002U) /* TIARES=2kohm */
5952#define ENUM_PGA_PGA0CON_TIAGAIN_RES5K (0X00000003U) /* TIARES=5kohm */
5953#define ENUM_PGA_PGA0CON_TIAGAIN_RES10K (0X00000004U) /* TIARES=10kohm */
5954#define ENUM_PGA_PGA0CON_TIAGAIN_RES20K (0X00000005U) /* TIARES=20kohm */
5955#define ENUM_PGA_PGA0CON_TIAGAIN_RES100K (0X00000006U) /* TIARES=100kohm */
5956#define ENUM_PGA_PGA0CON_PGAGAIN_GAIN1 (0X00000000U) /* Gain=1 */
5957#define ENUM_PGA_PGA0CON_PGAGAIN_GAIN2 (0X00000001U) /* GAIN=2 */
5958#define ENUM_PGA_PGA0CON_PGAGAIN_GAIN4 (0X00000002U) /* GAIN=4 */
5959#define ENUM_PGA_PGA0CON_PGAGAIN_GAIN6 (0X00000003U) /* GAIN=6 */
5960#define ENUM_PGA_PGA0CON_PGAGAIN_GAIN8 (0X00000004U) /* GAIN=8 */
5961#define ENUM_PGA_PGA0CON_PGAGAIN_GAIN10 (0X00000005U) /* GAIN=10 */
5962#define ENUM_PGA_PGA0CON_CAPBYPASS_BYPEN (0X00000001U) /* Bypass the External Cap */
5963#define ENUM_PGA_PGA0CON_CAPBYPASS_BYPDISABLE (0X00000000U) /* Select the External CAP */
5964#define ENUM_PGA_PGA0CON_PGAMODE_DCCOUPLE (0X00000000U) /* PGA DC Mode Enable */
5965#define ENUM_PGA_PGA0CON_PGAMODE_ACCOUPLE (0X00000001U) /* PGA AC Coupling Mode Enable */
5966#define ENUM_PGA_PGA0CON_MODE_PGAMODE (0X00000000U) /* PGA Mode Enable */
5967#define ENUM_PGA_PGA0CON_MODE_TIAMODE (0X00000001U) /* TIA Mode Enable */
5968
5969/* ----------------------------------------------------------------------------------------------------
5970 PGA0CHPCON Value Description
5971 ---------------------------------------------------------------------------------------------------- */
5972#define BITP_PGA_PGA0CHPCON_CHOPOFF (0U) /* Disable Chop Function */
5973#define BITL_PGA_PGA0CHPCON_CHOPOFF (1U) /* Disable Chop Function */
5974#define BITM_PGA_PGA0CHPCON_CHOPOFF (0X00000001U) /* Disable Chop Function */
5975
5976#define ENUM_PGA_PGA0CHPCON_CHOPOFF_CHOPEN (0X00000000U) /* Enable Chop Function */
5977#define ENUM_PGA_PGA0CHPCON_CHOPOFF_CHOPDIS (0X00000001U) /* Disable Chop Function */
5978
5979/* ----------------------------------------------------------------------------------------------------
5980 PGA3CHPCON Value Description
5981 ---------------------------------------------------------------------------------------------------- */
5982#define BITP_PGA_PGA3CHPCON_CHOPOFF (0U) /* Disable Chop Function */
5983#define BITL_PGA_PGA3CHPCON_CHOPOFF (1U) /* Disable Chop Function */
5984#define BITM_PGA_PGA3CHPCON_CHOPOFF (0X00000001U) /* Disable Chop Function */
5985
5986#define ENUM_PGA_PGA3CHPCON_CHOPOFF_CHOPEN (0X00000000U) /* Enable Chop Function */
5987#define ENUM_PGA_PGA3CHPCON_CHOPOFF_CHOPDIS (0X00000001U) /* Disable Chop Function */
5988
5989/* ----------------------------------------------------------------------------------------------------
5990 PGA1CON Value Description
5991 ---------------------------------------------------------------------------------------------------- */
5992#define BITP_PGA_PGA1CON_PDPGACORE (0U) /* PGA Core Power Down */
5993#define BITL_PGA_PGA1CON_PDPGACORE (1U) /* PGA Core Power Down */
5994#define BITM_PGA_PGA1CON_PDPGACORE (0X00000001U) /* PGA Core Power Down */
5995#define BITP_PGA_PGA1CON_MODE (1U) /* PGA or TIA Mode Selection */
5996#define BITL_PGA_PGA1CON_MODE (1U) /* PGA or TIA Mode Selection */
5997#define BITM_PGA_PGA1CON_MODE (0X00000002U) /* PGA or TIA Mode Selection */
5998#define BITP_PGA_PGA1CON_PGAMODE (2U) /* PGA DC Mode or AC Couple Mode Selection */
5999#define BITL_PGA_PGA1CON_PGAMODE (1U) /* PGA DC Mode or AC Couple Mode Selection */
6000#define BITM_PGA_PGA1CON_PGAMODE (0X00000004U) /* PGA DC Mode or AC Couple Mode Selection */
6001#define BITP_PGA_PGA1CON_PGAGAIN (5U) /* PGA Gain Configuration */
6002#define BITL_PGA_PGA1CON_PGAGAIN (3U) /* PGA Gain Configuration */
6003#define BITM_PGA_PGA1CON_PGAGAIN (0X000000E0U) /* PGA Gain Configuration */
6004#define BITP_PGA_PGA1CON_TIAGAIN (8U) /* TIA Gain Configuration */
6005#define BITL_PGA_PGA1CON_TIAGAIN (3U) /* TIA Gain Configuration */
6006#define BITM_PGA_PGA1CON_TIAGAIN (0X00000700U) /* TIA Gain Configuration */
6007#define BITP_PGA_PGA1CON_TIAVDACSEL (11U) /* TIA Vbias Selection of VDAC Channel */
6008#define BITL_PGA_PGA1CON_TIAVDACSEL (2U) /* TIA Vbias Selection of VDAC Channel */
6009#define BITM_PGA_PGA1CON_TIAVDACSEL (0X00001800U) /* TIA Vbias Selection of VDAC Channel */
6010#define BITP_PGA_PGA1CON_DRVEN (14U) /* Sink Current Ability Improve */
6011#define BITL_PGA_PGA1CON_DRVEN (1U) /* Sink Current Ability Improve */
6012#define BITM_PGA_PGA1CON_DRVEN (0X00004000U) /* Sink Current Ability Improve */
6013#define BITP_PGA_PGA1CON_TIASRCEN (15U) /* Select Between Source Mode and Sink Mode */
6014#define BITL_PGA_PGA1CON_TIASRCEN (1U) /* Select Between Source Mode and Sink Mode */
6015#define BITM_PGA_PGA1CON_TIASRCEN (0X00008000U) /* Select Between Source Mode and Sink Mode */
6016
6017#define ENUM_PGA_PGA1CON_TIASRCEN_SINKMD (0X00000000U) /* Sink Mode */
6018#define ENUM_PGA_PGA1CON_TIASRCEN_SOURCEMD (0X00000001U) /* Source Mode */
6019#define ENUM_PGA_PGA1CON_DRVEN_DRVDISABLE (0X00000000U) /* Disable Isink Ability Improvement, Normal Drive */
6020#define ENUM_PGA_PGA1CON_DRVEN_DRVENABLE (0X00000001U) /* Enable Isink Ability Improvement */
6021#define ENUM_PGA_PGA1CON_TIAVDACSEL_VDAC8SEL (0X00000000U) /* Select VDAC8 as TIA Vbias */
6022#define ENUM_PGA_PGA1CON_TIAVDACSEL_VDAC9SEL (0X00000001U) /* Select VDAC9 as TIA Vbias */
6023#define ENUM_PGA_PGA1CON_TIAVDACSEL_VDAC10SEL (0X00000002U) /* Select VDAC10 as TIA Vbias */
6024#define ENUM_PGA_PGA1CON_TIAVDACSEL_VDAC11SEL (0X00000003U) /* Select VDAC11 as TIA Vbias */
6025#define ENUM_PGA_PGA1CON_TIAGAIN_RES250 (0X00000000U) /* TIARES=250ohm */
6026#define ENUM_PGA_PGA1CON_TIAGAIN_RES750 (0X00000001U) /* TIARES=750ohm */
6027#define ENUM_PGA_PGA1CON_TIAGAIN_RES2K (0X00000002U) /* TIARES=2kohm */
6028#define ENUM_PGA_PGA1CON_TIAGAIN_RES5K (0X00000003U) /* TIARES=5kohm */
6029#define ENUM_PGA_PGA1CON_TIAGAIN_RES10K (0X00000004U) /* TIARES=10kohm */
6030#define ENUM_PGA_PGA1CON_TIAGAIN_RES20K (0X00000005U) /* TIARES=20kohm */
6031#define ENUM_PGA_PGA1CON_TIAGAIN_RES100K (0X00000006U) /* TIARES=100kohm */
6032#define ENUM_PGA_PGA1CON_PGAGAIN_GAIN1 (0X00000000U) /* Gain=1 */
6033#define ENUM_PGA_PGA1CON_PGAGAIN_GAIN2 (0X00000001U) /* GAIN=2 */
6034#define ENUM_PGA_PGA1CON_PGAGAIN_GAIN4 (0X00000002U) /* GAIN=4 */
6035#define ENUM_PGA_PGA1CON_PGAGAIN_GAIN6 (0X00000003U) /* GAIN=6 */
6036#define ENUM_PGA_PGA1CON_PGAGAIN_GAIN8 (0X00000004U) /* GAIN=8 */
6037#define ENUM_PGA_PGA1CON_PGAGAIN_GAIN10 (0X00000005U) /* GAIN=10 */
6038#define ENUM_PGA_PGA1CON_PGAMODE_DCCOUPLE (0X00000000U) /* PGA DC Mode Enable */
6039#define ENUM_PGA_PGA1CON_PGAMODE_ACCOUPLE (0X00000001U) /* PGA AC Coupling Mode Enable */
6040#define ENUM_PGA_PGA1CON_MODE_PGAMODE (0X00000000U) /* PGA Mode Enable */
6041#define ENUM_PGA_PGA1CON_MODE_TIAMODE (0X00000001U) /* TIA Mode Enable */
6042
6043/* ----------------------------------------------------------------------------------------------------
6044 PGA1CHPCON Value Description
6045 ---------------------------------------------------------------------------------------------------- */
6046#define BITP_PGA_PGA1CHPCON_CHOPOFF (0U) /* Disable Chop Function */
6047#define BITL_PGA_PGA1CHPCON_CHOPOFF (1U) /* Disable Chop Function */
6048#define BITM_PGA_PGA1CHPCON_CHOPOFF (0X00000001U) /* Disable Chop Function */
6049
6050#define ENUM_PGA_PGA1CHPCON_CHOPOFF_CHOPEN (0X00000000U) /* Enable Chop Function */
6051#define ENUM_PGA_PGA1CHPCON_CHOPOFF_CHOPDIS (0X00000001U) /* Disable Chop Function */
6052
6053/* ----------------------------------------------------------------------------------------------------
6054 PGA2CON Value Description
6055 ---------------------------------------------------------------------------------------------------- */
6056#define BITP_PGA_PGA2CON_PDPGACORE (0U) /* PGA Core Power Down */
6057#define BITL_PGA_PGA2CON_PDPGACORE (1U) /* PGA Core Power Down */
6058#define BITM_PGA_PGA2CON_PDPGACORE (0X00000001U) /* PGA Core Power Down */
6059#define BITP_PGA_PGA2CON_MODE (1U) /* PGA or TIA Mode Selection */
6060#define BITL_PGA_PGA2CON_MODE (1U) /* PGA or TIA Mode Selection */
6061#define BITM_PGA_PGA2CON_MODE (0X00000002U) /* PGA or TIA Mode Selection */
6062#define BITP_PGA_PGA2CON_PGAMODE (2U) /* PGA DC Mode or AC Couple Mode Selection */
6063#define BITL_PGA_PGA2CON_PGAMODE (1U) /* PGA DC Mode or AC Couple Mode Selection */
6064#define BITM_PGA_PGA2CON_PGAMODE (0X00000004U) /* PGA DC Mode or AC Couple Mode Selection */
6065#define BITP_PGA_PGA2CON_CAPBYPASS (3U) /* Bypass the External Cap */
6066#define BITL_PGA_PGA2CON_CAPBYPASS (1U) /* Bypass the External Cap */
6067#define BITM_PGA_PGA2CON_CAPBYPASS (0X00000008U) /* Bypass the External Cap */
6068#define BITP_PGA_PGA2CON_PGAGAIN (5U) /* PGA Gain Configuration */
6069#define BITL_PGA_PGA2CON_PGAGAIN (3U) /* PGA Gain Configuration */
6070#define BITM_PGA_PGA2CON_PGAGAIN (0X000000E0U) /* PGA Gain Configuration */
6071#define BITP_PGA_PGA2CON_TIAGAIN (8U) /* TIA Gain Configuration */
6072#define BITL_PGA_PGA2CON_TIAGAIN (3U) /* TIA Gain Configuration */
6073#define BITM_PGA_PGA2CON_TIAGAIN (0X00000700U) /* TIA Gain Configuration */
6074#define BITP_PGA_PGA2CON_TIAVDACSEL (11U) /* TIA Vbias Selection of VDAC Channel */
6075#define BITL_PGA_PGA2CON_TIAVDACSEL (2U) /* TIA Vbias Selection of VDAC Channel */
6076#define BITM_PGA_PGA2CON_TIAVDACSEL (0X00001800U) /* TIA Vbias Selection of VDAC Channel */
6077#define BITP_PGA_PGA2CON_DRVEN (14U) /* Sink Current Ability Improve */
6078#define BITL_PGA_PGA2CON_DRVEN (1U) /* Sink Current Ability Improve */
6079#define BITM_PGA_PGA2CON_DRVEN (0X00004000U) /* Sink Current Ability Improve */
6080#define BITP_PGA_PGA2CON_TIASRCEN (15U) /* Select Between Source Mode and Sink Mode */
6081#define BITL_PGA_PGA2CON_TIASRCEN (1U) /* Select Between Source Mode and Sink Mode */
6082#define BITM_PGA_PGA2CON_TIASRCEN (0X00008000U) /* Select Between Source Mode and Sink Mode */
6083
6084#define ENUM_PGA_PGA2CON_TIASRCEN_SINKMD (0X00000000U) /* Sink Mode */
6085#define ENUM_PGA_PGA2CON_TIASRCEN_SOURCEMD (0X00000001U) /* Source Mode */
6086#define ENUM_PGA_PGA2CON_DRVEN_DRVDISABLE (0X00000000U) /* Disable Isink Ability Improvement, Normal Drive */
6087#define ENUM_PGA_PGA2CON_DRVEN_DRVENABLE (0X00000001U) /* Enable Isink Ability Improvement */
6088#define ENUM_PGA_PGA2CON_TIAVDACSEL_VDAC8SEL (0X00000000U) /* Select VDAC8 as TIA Vbias */
6089#define ENUM_PGA_PGA2CON_TIAVDACSEL_VDAC9SEL (0X00000001U) /* Select VDAC9 as TIA Vbias */
6090#define ENUM_PGA_PGA2CON_TIAVDACSEL_VDAC10SEL (0X00000002U) /* Select VDAC10 as TIA Vbias */
6091#define ENUM_PGA_PGA2CON_TIAVDACSEL_VDAC11SEL (0X00000003U) /* Select VDAC11 as TIA Vbias */
6092#define ENUM_PGA_PGA2CON_TIAGAIN_RES250 (0X00000000U) /* TIARES=250ohm */
6093#define ENUM_PGA_PGA2CON_TIAGAIN_RES750 (0X00000001U) /* TIARES=750ohm */
6094#define ENUM_PGA_PGA2CON_TIAGAIN_RES2K (0X00000002U) /* TIARES=2kohm */
6095#define ENUM_PGA_PGA2CON_TIAGAIN_RES5K (0X00000003U) /* TIARES=5kohm */
6096#define ENUM_PGA_PGA2CON_TIAGAIN_RES10K (0X00000004U) /* TIARES=10kohm */
6097#define ENUM_PGA_PGA2CON_TIAGAIN_RES20K (0X00000005U) /* TIARES=20kohm */
6098#define ENUM_PGA_PGA2CON_TIAGAIN_RES100K (0X00000006U) /* TIARES=100kohm */
6099#define ENUM_PGA_PGA2CON_PGAGAIN_GAIN1 (0X00000000U) /* Gain=1 */
6100#define ENUM_PGA_PGA2CON_PGAGAIN_GAIN2 (0X00000001U) /* GAIN=2 */
6101#define ENUM_PGA_PGA2CON_PGAGAIN_GAIN4 (0X00000002U) /* GAIN=4 */
6102#define ENUM_PGA_PGA2CON_PGAGAIN_GAIN6 (0X00000003U) /* GAIN=6 */
6103#define ENUM_PGA_PGA2CON_PGAGAIN_GAIN8 (0X00000004U) /* GAIN=8 */
6104#define ENUM_PGA_PGA2CON_PGAGAIN_GAIN10 (0X00000005U) /* GAIN=10 */
6105#define ENUM_PGA_PGA2CON_CAPBYPASS_BYPEN (0X00000001U) /* Bypass the External Cap */
6106#define ENUM_PGA_PGA2CON_CAPBYPASS_BYPDISABLE (0X00000000U) /* Select the External CAP */
6107#define ENUM_PGA_PGA2CON_PGAMODE_DCCOUPLE (0X00000000U) /* PGA DC Mode Enable */
6108#define ENUM_PGA_PGA2CON_PGAMODE_ACCOUPLE (0X00000001U) /* PGA AC Coupling Mode Enable */
6109#define ENUM_PGA_PGA2CON_MODE_PGAMODE (0X00000000U) /* PGA Mode Enable */
6110#define ENUM_PGA_PGA2CON_MODE_TIAMODE (0X00000001U) /* TIA Mode Enable */
6111
6112/* ----------------------------------------------------------------------------------------------------
6113 PGA2CHPCON Value Description
6114 ---------------------------------------------------------------------------------------------------- */
6115#define BITP_PGA_PGA2CHPCON_CHOPOFF (0U) /* Disable Chop Function */
6116#define BITL_PGA_PGA2CHPCON_CHOPOFF (1U) /* Disable Chop Function */
6117#define BITM_PGA_PGA2CHPCON_CHOPOFF (0X00000001U) /* Disable Chop Function */
6118
6119#define ENUM_PGA_PGA2CHPCON_CHOPOFF_CHOPEN (0X00000000U) /* Enable Chop Function */
6120#define ENUM_PGA_PGA2CHPCON_CHOPOFF_CHOPDIS (0X00000001U) /* Disable Chop Function */
6121
6122/* ----------------------------------------------------------------------------------------------------
6123 PGA3CON Value Description
6124 ---------------------------------------------------------------------------------------------------- */
6125#define BITP_PGA_PGA3CON_PDPGACORE (0U) /* PGA Core Power Down */
6126#define BITL_PGA_PGA3CON_PDPGACORE (1U) /* PGA Core Power Down */
6127#define BITM_PGA_PGA3CON_PDPGACORE (0X00000001U) /* PGA Core Power Down */
6128#define BITP_PGA_PGA3CON_MODE (1U) /* PGA or TIA Mode Selection */
6129#define BITL_PGA_PGA3CON_MODE (1U) /* PGA or TIA Mode Selection */
6130#define BITM_PGA_PGA3CON_MODE (0X00000002U) /* PGA or TIA Mode Selection */
6131#define BITP_PGA_PGA3CON_PGAMODE (2U) /* PGA DC Mode or AC Couple Mode Selection */
6132#define BITL_PGA_PGA3CON_PGAMODE (1U) /* PGA DC Mode or AC Couple Mode Selection */
6133#define BITM_PGA_PGA3CON_PGAMODE (0X00000004U) /* PGA DC Mode or AC Couple Mode Selection */
6134#define BITP_PGA_PGA3CON_PGAGAIN (5U) /* PGA Gain Configuration */
6135#define BITL_PGA_PGA3CON_PGAGAIN (3U) /* PGA Gain Configuration */
6136#define BITM_PGA_PGA3CON_PGAGAIN (0X000000E0U) /* PGA Gain Configuration */
6137#define BITP_PGA_PGA3CON_TIAGAIN (8U) /* TIA Gain Configuration */
6138#define BITL_PGA_PGA3CON_TIAGAIN (3U) /* TIA Gain Configuration */
6139#define BITM_PGA_PGA3CON_TIAGAIN (0X00000700U) /* TIA Gain Configuration */
6140#define BITP_PGA_PGA3CON_TIAVDACSEL (11U) /* TIA Vbias Selection of VDAC Channel */
6141#define BITL_PGA_PGA3CON_TIAVDACSEL (2U) /* TIA Vbias Selection of VDAC Channel */
6142#define BITM_PGA_PGA3CON_TIAVDACSEL (0X00001800U) /* TIA Vbias Selection of VDAC Channel */
6143#define BITP_PGA_PGA3CON_DRVEN (14U) /* Sink Current Ability Improve */
6144#define BITL_PGA_PGA3CON_DRVEN (1U) /* Sink Current Ability Improve */
6145#define BITM_PGA_PGA3CON_DRVEN (0X00004000U) /* Sink Current Ability Improve */
6146#define BITP_PGA_PGA3CON_TIASRCEN (15U) /* Select Between Source Mode and Sink Mode */
6147#define BITL_PGA_PGA3CON_TIASRCEN (1U) /* Select Between Source Mode and Sink Mode */
6148#define BITM_PGA_PGA3CON_TIASRCEN (0X00008000U) /* Select Between Source Mode and Sink Mode */
6149
6150#define ENUM_PGA_PGA3CON_TIASRCEN_SINKMD (0X00000000U) /* Sink Mode */
6151#define ENUM_PGA_PGA3CON_TIASRCEN_SOURCEMD (0X00000001U) /* Source Mode */
6152#define ENUM_PGA_PGA3CON_DRVEN_DRVDISABLE (0X00000000U) /* Disable Isink Ability Improvement, Normal Drive */
6153#define ENUM_PGA_PGA3CON_DRVEN_DRVENABLE (0X00000001U) /* Enable Isink Ability Improvement */
6154#define ENUM_PGA_PGA3CON_TIAVDACSEL_VDAC8SEL (0X00000000U) /* Select VDAC8 as TIA Vbias */
6155#define ENUM_PGA_PGA3CON_TIAVDACSEL_VDAC9SEL (0X00000001U) /* Select VDAC9 as TIA Vbias */
6156#define ENUM_PGA_PGA3CON_TIAVDACSEL_VDAC10SEL (0X00000002U) /* Select VDAC10 as TIA Vbias */
6157#define ENUM_PGA_PGA3CON_TIAVDACSEL_VDAC11SEL (0X00000003U) /* Select VDAC11 as TIA Vbias */
6158#define ENUM_PGA_PGA3CON_TIAGAIN_RES250 (0X00000000U) /* TIARES=250ohm */
6159#define ENUM_PGA_PGA3CON_TIAGAIN_RES750 (0X00000001U) /* TIARES=750ohm */
6160#define ENUM_PGA_PGA3CON_TIAGAIN_RES2K (0X00000002U) /* TIARES=2kohm */
6161#define ENUM_PGA_PGA3CON_TIAGAIN_RES5K (0X00000003U) /* TIARES=5kohm */
6162#define ENUM_PGA_PGA3CON_TIAGAIN_RES10K (0X00000004U) /* TIARES=10kohm */
6163#define ENUM_PGA_PGA3CON_TIAGAIN_RES20K (0X00000005U) /* TIARES=20kohm */
6164#define ENUM_PGA_PGA3CON_TIAGAIN_RES100K (0X00000006U) /* TIARES=100kohm */
6165#define ENUM_PGA_PGA3CON_PGAGAIN_GAIN1 (0X00000000U) /* Gain=1 */
6166#define ENUM_PGA_PGA3CON_PGAGAIN_GAIN2 (0X00000001U) /* GAIN=2 */
6167#define ENUM_PGA_PGA3CON_PGAGAIN_GAIN4 (0X00000002U) /* GAIN=4 */
6168#define ENUM_PGA_PGA3CON_PGAGAIN_GAIN6 (0X00000003U) /* GAIN=6 */
6169#define ENUM_PGA_PGA3CON_PGAGAIN_GAIN8 (0X00000004U) /* GAIN=8 */
6170#define ENUM_PGA_PGA3CON_PGAGAIN_GAIN10 (0X00000005U) /* GAIN=10 */
6171#define ENUM_PGA_PGA3CON_PGAMODE_DCCOUPLE (0X00000000U) /* PGA DC Mode Enable */
6172#define ENUM_PGA_PGA3CON_PGAMODE_ACCOUPLE (0X00000001U) /* PGA AC Coupling Mode Enable */
6173#define ENUM_PGA_PGA3CON_MODE_PGAMODE (0X00000000U) /* PGA Mode Enable */
6174#define ENUM_PGA_PGA3CON_MODE_TIAMODE (0X00000001U) /* TIA Mode Enable */
6175
6176#endif /* end ifndef PGA_ADDR_RDEF_H_ */
6177
6178
6179#ifndef PLL_MMRS_ADDR_RDEF_H_
6180#define PLL_MMRS_ADDR_RDEF_H_ /* PLL_MMRS: Your module description, here. */
6181
6182/* ====================================================================================================
6183 PLL_MMRS Module Instances Address and Mask Definitions
6184 ==================================================================================================== */
6185#define INST_PLL (0X40069200U) /* pll: */
6186
6187#define MASK_PLL_MMRS (0X000001FFU) /* PLL_MMRS: Your module description, here. */
6188
6189/* ====================================================================================================
6190 PLL_MMRS Module Register Address Offset Definitions
6191 ==================================================================================================== */
6192#define IDX_PLL_MMRS_PLLPDCTRL (0X000U) /* No description provided */
6193
6194/* ====================================================================================================
6195 PLL_MMRS Module Register ResetValue Definitions
6196 ==================================================================================================== */
6197#define RSTVAL_PLL_MMRS_PLLPDCTRL (0X3F)
6198
6199/* ====================================================================================================
6200 PLL_MMRS Module Register BitPositions, Lengths, Masks and Enumerations Definitions
6201 ==================================================================================================== */
6202
6203/* ----------------------------------------------------------------------------------------------------
6204 PLLPDCTRL Value Description
6205 ---------------------------------------------------------------------------------------------------- */
6206#define BITP_PLL_MMRS_PLLPDCTRL_TOTPDB (6U) /* PDB of PLL All */
6207#define BITL_PLL_MMRS_PLLPDCTRL_TOTPDB (1U) /* PDB of PLL All */
6208#define BITM_PLL_MMRS_PLLPDCTRL_TOTPDB (0X00000040U) /* PDB of PLL All */
6209
6210#endif /* end ifndef PLL_MMRS_ADDR_RDEF_H_ */
6211
6212
6213#ifndef VCM_MMRS_ADDR_RDEF_H_
6214#define VCM_MMRS_ADDR_RDEF_H_ /* VCM_MMRS: Your module description, here. */
6215
6216/* ====================================================================================================
6217 VCM_MMRS Module Instances Address and Mask Definitions
6218 ==================================================================================================== */
6219#define INST_TMPSNS (0X40069600U) /* tmpsns: */
6220
6221#define MASK_VCM_MMRS (0X000001FFU) /* VCM_MMRS: Your module description, here. */
6222
6223/* ====================================================================================================
6224 VCM_MMRS Module Register Address Offset Definitions
6225 ==================================================================================================== */
6226#define IDX_VCM_MMRS_TMPSNSCON (0X000U) /* No description provided */
6227#define IDX_VCM_MMRS_TMPSNSCHPCON (0X004U) /* No description provided */
6228#define IDX_VCM_MMRS_VCMREFCON (0X008U) /* No description provided */
6229#define IDX_VCM_MMRS_VCMBUFCON (0X010U) /* No description provided */
6230
6231/* ====================================================================================================
6232 VCM_MMRS Module Register ResetValue Definitions
6233 ==================================================================================================== */
6234#define RSTVAL_VCM_MMRS_TMPSNSCON (0X2)
6235#define RSTVAL_VCM_MMRS_TMPSNSCHPCON (0X0)
6236#define RSTVAL_VCM_MMRS_VCMREFCON (0X0)
6237#define RSTVAL_VCM_MMRS_VCMBUFCON (0X13)
6238
6239/* ====================================================================================================
6240 VCM_MMRS Module Register BitPositions, Lengths, Masks and Enumerations Definitions
6241 ==================================================================================================== */
6242
6243/* ----------------------------------------------------------------------------------------------------
6244 TMPSNSCON Value Description
6245 ---------------------------------------------------------------------------------------------------- */
6246#define BITP_VCM_MMRS_TMPSNSCON_ENTMPSNS (1U) /* Enable Temp Sensor */
6247#define BITL_VCM_MMRS_TMPSNSCON_ENTMPSNS (1U) /* Enable Temp Sensor */
6248#define BITM_VCM_MMRS_TMPSNSCON_ENTMPSNS (0X00000002U) /* Enable Temp Sensor */
6249
6250/* ----------------------------------------------------------------------------------------------------
6251 TMPSNSCHPCON Value Description
6252 ---------------------------------------------------------------------------------------------------- */
6253#define BITP_VCM_MMRS_TMPSNSCHPCON_CHOFFTMPSNS (0U) /* Chopping Disable = 1 Enable = 0 */
6254#define BITL_VCM_MMRS_TMPSNSCHPCON_CHOFFTMPSNS (1U) /* Chopping Disable = 1 Enable = 0 */
6255#define BITM_VCM_MMRS_TMPSNSCHPCON_CHOFFTMPSNS (0X00000001U) /* Chopping Disable = 1 Enable = 0 */
6256
6257/* ----------------------------------------------------------------------------------------------------
6258 VCMREFCON Value Description
6259 ---------------------------------------------------------------------------------------------------- */
6260#define BITP_VCM_MMRS_VCMREFCON_PGAREFSEL (1U) /* 0.2V or 0.5V Selection for PGA */
6261#define BITL_VCM_MMRS_VCMREFCON_PGAREFSEL (1U) /* 0.2V or 0.5V Selection for PGA */
6262#define BITM_VCM_MMRS_VCMREFCON_PGAREFSEL (0X00000002U) /* 0.2V or 0.5V Selection for PGA */
6263
6264#define ENUM_VCM_MMRS_VCMREFCON_PGAREFSEL_SEL0P2V (0X00000000U) /* Select 0.2V Reference */
6265#define ENUM_VCM_MMRS_VCMREFCON_PGAREFSEL_SEL0P5V (0X00000001U) /* Select 0.5V Reference */
6266
6267/* ----------------------------------------------------------------------------------------------------
6268 VCMBUFCON Value Description
6269 ---------------------------------------------------------------------------------------------------- */
6270#define BITP_VCM_MMRS_VCMBUFCON_PDBUF0 (0U) /* Power Down Unit Gain Buffer0 */
6271#define BITL_VCM_MMRS_VCMBUFCON_PDBUF0 (1U) /* Power Down Unit Gain Buffer0 */
6272#define BITM_VCM_MMRS_VCMBUFCON_PDBUF0 (0X00000001U) /* Power Down Unit Gain Buffer0 */
6273#define BITP_VCM_MMRS_VCMBUFCON_PDBUF1 (1U) /* Power Down Unit Gain Buffer1 */
6274#define BITL_VCM_MMRS_VCMBUFCON_PDBUF1 (1U) /* Power Down Unit Gain Buffer1 */
6275#define BITM_VCM_MMRS_VCMBUFCON_PDBUF1 (0X00000002U) /* Power Down Unit Gain Buffer1 */
6276#define BITP_VCM_MMRS_VCMBUFCON_MUXSEL0 (2U) /* Selection 0=2.5V 1=1.25V */
6277#define BITL_VCM_MMRS_VCMBUFCON_MUXSEL0 (1U) /* Selection 0=2.5V 1=1.25V */
6278#define BITM_VCM_MMRS_VCMBUFCON_MUXSEL0 (0X00000004U) /* Selection 0=2.5V 1=1.25V */
6279#define BITP_VCM_MMRS_VCMBUFCON_MUXSEL1 (4U) /* Selection 0=2.5V 1=1.25V */
6280#define BITL_VCM_MMRS_VCMBUFCON_MUXSEL1 (1U) /* Selection 0=2.5V 1=1.25V */
6281#define BITM_VCM_MMRS_VCMBUFCON_MUXSEL1 (0X00000010U) /* Selection 0=2.5V 1=1.25V */
6282
6283#define ENUM_VCM_MMRS_VCMBUFCON_MUXSEL1_BUF1_2P5 (0X00000000U) /* Buffer1 Input 2.5V */
6284#define ENUM_VCM_MMRS_VCMBUFCON_MUXSEL1_BUF1_1P25 (0X00000001U) /* Buffer1 Input 1.25V */
6285#define ENUM_VCM_MMRS_VCMBUFCON_MUXSEL0_BUF0_2P5 (0X00000000U) /* Input Buffer0 2.5V */
6286#define ENUM_VCM_MMRS_VCMBUFCON_MUXSEL0_BUF0_1P25 (0X00000001U) /* Input Buffer0 1.25V */
6287
6288#endif /* end ifndef VCM_MMRS_ADDR_RDEF_H_ */
6289
6290
6291#ifndef DAC_ADDR_RDEF_H_
6292#define DAC_ADDR_RDEF_H_ /* DAC: Your module description, here. */
6293
6294/* ====================================================================================================
6295 DAC Module Instances Address and Mask Definitions
6296 ==================================================================================================== */
6297#define INST_VDAC (0X40069800U) /* vdac: */
6298
6299#define MASK_DAC (0X000001FFU) /* DAC: Your module description, here. */
6300
6301/* ====================================================================================================
6302 DAC Module Register Address Offset Definitions
6303 ==================================================================================================== */
6304#define IDX_DAC_DACCON0 (0X000U) /* DAC Control Register */
6305#define IDX_DAC_DACCON1 (0X004U) /* DAC Control Register */
6306#define IDX_DAC_DACCON2 (0X008U) /* DAC Control Register */
6307#define IDX_DAC_DACCON3 (0X00CU) /* DAC Control Register */
6308#define IDX_DAC_DACCON4 (0X010U) /* DAC Control Register */
6309#define IDX_DAC_DACCON5 (0X014U) /* DAC Control Register */
6310#define IDX_DAC_DACCON6 (0X018U) /* DAC Control Register */
6311#define IDX_DAC_DACCON7 (0X01CU) /* DAC Control Register */
6312#define IDX_DAC_DACCON8 (0X020U) /* DAC Control Register */
6313#define IDX_DAC_DACCON9 (0X024U) /* DAC Control Register */
6314#define IDX_DAC_DACCON10 (0X028U) /* DAC Control Register */
6315#define IDX_DAC_DACCON11 (0X02CU) /* DAC Control Register */
6316#define IDX_DAC_DACDAT0 (0X030U) /* DAC Data Register */
6317#define IDX_DAC_DACDAT1 (0X034U) /* DAC Data Register */
6318#define IDX_DAC_DACDAT2 (0X038U) /* DAC Data Register */
6319#define IDX_DAC_DACDAT3 (0X03CU) /* DAC Data Register */
6320#define IDX_DAC_DACDAT4 (0X040U) /* DAC Data Register */
6321#define IDX_DAC_DACDAT5 (0X044U) /* DAC Data Register */
6322#define IDX_DAC_DACDAT6 (0X048U) /* DAC Data Register */
6323#define IDX_DAC_DACDAT7 (0X04CU) /* DAC Data Register */
6324#define IDX_DAC_DACDAT8 (0X050U) /* DAC Data Register */
6325#define IDX_DAC_DACDAT9 (0X054U) /* DAC Data Register */
6326#define IDX_DAC_DACDAT10 (0X058U) /* DAC Data Register */
6327#define IDX_DAC_DACDAT11 (0X05CU) /* DAC Data Register */
6328
6329/* ====================================================================================================
6330 DAC Module Register ResetValue Definitions
6331 ==================================================================================================== */
6332#define RSTVAL_DAC_DACCON0 (0XD02)
6333#define RSTVAL_DAC_DACCON1 (0XD02)
6334#define RSTVAL_DAC_DACCON2 (0XD02)
6335#define RSTVAL_DAC_DACCON3 (0XD02)
6336#define RSTVAL_DAC_DACCON4 (0XD02)
6337#define RSTVAL_DAC_DACCON5 (0XD02)
6338#define RSTVAL_DAC_DACCON6 (0XD02)
6339#define RSTVAL_DAC_DACCON7 (0XD02)
6340#define RSTVAL_DAC_DACCON8 (0XD02)
6341#define RSTVAL_DAC_DACCON9 (0XD02)
6342#define RSTVAL_DAC_DACCON10 (0XD02)
6343#define RSTVAL_DAC_DACCON11 (0XD02)
6344#define RSTVAL_DAC_DACDAT0 (0X0)
6345#define RSTVAL_DAC_DACDAT1 (0X0)
6346#define RSTVAL_DAC_DACDAT2 (0X0)
6347#define RSTVAL_DAC_DACDAT3 (0X0)
6348#define RSTVAL_DAC_DACDAT4 (0X0)
6349#define RSTVAL_DAC_DACDAT5 (0X0)
6350#define RSTVAL_DAC_DACDAT6 (0X0)
6351#define RSTVAL_DAC_DACDAT7 (0X0)
6352#define RSTVAL_DAC_DACDAT8 (0X0)
6353#define RSTVAL_DAC_DACDAT9 (0X0)
6354#define RSTVAL_DAC_DACDAT10 (0X0)
6355#define RSTVAL_DAC_DACDAT11 (0X0)
6356
6357/* ====================================================================================================
6358 DAC Module Register BitPositions, Lengths, Masks and Enumerations Definitions
6359 ==================================================================================================== */
6360
6361/* ----------------------------------------------------------------------------------------------------
6362 DACCON0 Value Description
6363 ---------------------------------------------------------------------------------------------------- */
6364#define BITP_DAC_DACCON_N__EN (4U) /* DAC Input Data Clear, Won't Be Controlled by Sync Mode. */
6365#define BITL_DAC_DACCON_N__EN (1U) /* DAC Input Data Clear, Won't Be Controlled by Sync Mode. */
6366#define BITM_DAC_DACCON_N__EN (0X00000010U) /* DAC Input Data Clear, Won't Be Controlled by Sync Mode. */
6367#define BITP_DAC_DACCON_N__FSLVL (5U) /* Select Output Full Scale */
6368#define BITL_DAC_DACCON_N__FSLVL (1U) /* Select Output Full Scale */
6369#define BITM_DAC_DACCON_N__FSLVL (0X00000020U) /* Select Output Full Scale */
6370#define BITP_DAC_DACCON_N__PD (8U) /* DAC Top Power Down */
6371#define BITL_DAC_DACCON_N__PD (1U) /* DAC Top Power Down */
6372#define BITM_DAC_DACCON_N__PD (0X00000100U) /* DAC Top Power Down */
6373#define BITP_DAC_DACCON_N__DRV (9U) /* Drive Ability Boost Enable, Can Drive 10mA Load. */
6374#define BITL_DAC_DACCON_N__DRV (1U) /* Drive Ability Boost Enable, Can Drive 10mA Load. */
6375#define BITM_DAC_DACCON_N__DRV (0X00000200U) /* Drive Ability Boost Enable, Can Drive 10mA Load. */
6376
6377#define ENUM_DAC_DACCON_N__DRV_NORMAL (0X00000000U) /* Normal Work Mode */
6378#define ENUM_DAC_DACCON_N__DRV_DRIVEBOOST (0X00000001U) /* Drive Ability Boost Mode */
6379#define ENUM_DAC_DACCON_N__PD_DACON (0X00000000U) /* DAC Top Enable */
6380#define ENUM_DAC_DACCON_N__PD_DACOFF (0X00000001U) /* DAC TOP Power Down */
6381#define ENUM_DAC_DACCON_N__FSLVL_OUT2P5 (0X00000000U) /* Full Scale is 2.5V */
6382#define ENUM_DAC_DACCON_N__FSLVL_OUT3V3 (0X00000001U) /* Full Scale is 3.3V */
6383#define ENUM_DAC_DACCON_N__EN_CLEAR (0X00000000U) /* DAC DATA Clear */
6384#define ENUM_DAC_DACCON_N__EN_CLEAROFF (0X00000001U) /* DAC DATA Normal Input */
6385
6386/* ----------------------------------------------------------------------------------------------------
6387 DACDAT0 Value Description
6388 ---------------------------------------------------------------------------------------------------- */
6389#define BITP_DAC_DACDAT_N__DATAIN (12U) /* DAC Input Data */
6390#define BITL_DAC_DACDAT_N__DATAIN (16U) /* DAC Input Data */
6391#define BITM_DAC_DACDAT_N__DATAIN (0X0FFFF000U) /* DAC Input Data */
6392
6393#endif /* end ifndef DAC_ADDR_RDEF_H_ */
6394
6395/*! ========================================================================
6396 * \struct ADI_TMR_TypeDef
6397 * \brief GPT0
6398 * ======================================================================== */
6399typedef struct _ADI_TMR_TypeDef
6400{
6401 volatile uint16_t LD; /**< 0 16-bit Load Value Register */
6402 volatile const uint8_t RESERVED0[2];
6403 volatile const uint16_t VAL; /**< 4 16-bit Timer Value Register */
6404 volatile const uint8_t RESERVED1[2];
6405 volatile uint16_t CON; /**< 8 Control Register */
6406 volatile const uint8_t RESERVED2[2];
6407 volatile uint16_t CLRI; /**< C Clear Interrupt Register */
6408 volatile const uint8_t RESERVED3[14];
6409 volatile const uint16_t STA; /**< 1C Status Register */
6410} ADI_TMR_TypeDef;
6411
6412/*! ========================================================================
6413 * \struct ADI_TIMER_TypeDef
6414 * \brief Timer
6415 * ======================================================================== */
6416typedef struct _ADI_TIMER_TypeDef
6417{
6418 volatile uint32_t CTL; /**< 0 Timer Control */
6419 volatile uint32_t CNT; /**< 4 Count Value */
6420 volatile uint32_t STATUS; /**< 8 Timer Status */
6421 volatile const uint8_t RESERVED0[4];
6422 volatile uint32_t CFG0; /**< 10 Capture Compare Configuration */
6423 volatile uint32_t CFG1; /**< 14 Capture Compare Configuration */
6424 volatile uint32_t CFG2; /**< 18 Capture Compare Configuration */
6425 volatile uint32_t CFG3; /**< 1C Capture Compare Configuration */
6426 volatile uint32_t CC0; /**< 20 Compare and Capture Value */
6427 volatile uint32_t CC1; /**< 24 Compare and Capture Value */
6428 volatile uint32_t CC2; /**< 28 Compare and Capture Value */
6429 volatile uint32_t CC3; /**< 2C Compare and Capture Value */
6430} ADI_TIMER_TypeDef;
6431
6432/*! ========================================================================
6433 * \struct ADI_MISC16_TypeDef
6434 * \brief Your module description, here.
6435 * ======================================================================== */
6436typedef struct _ADI_MISC16_TypeDef
6437{
6438 volatile const uint8_t RESERVED0[32];
6439 volatile const uint32_t ADIID; /**< 20 ADI ID */
6440 volatile const uint32_t CHIPID; /**< 24 Chip ID */
6441 volatile const uint8_t RESERVED1[268];
6442 volatile uint32_t USERKEY; /**< 134 Open to Customer to Protect Important Registers */
6443} ADI_MISC16_TypeDef;
6444
6445/*! ========================================================================
6446 * \struct ADI_WUT_TypeDef
6447 * \brief WUT
6448 * ======================================================================== */
6449typedef struct _ADI_WUT_TypeDef
6450{
6451 volatile const uint16_t T4VAL0; /**< 0 Current Count Value - LS 16 Bits */
6452 volatile const uint8_t RESERVED0[2];
6453 volatile const uint16_t T4VAL1; /**< 4 Current Count Value - MS 16 Bits */
6454 volatile const uint8_t RESERVED1[2];
6455 volatile uint16_t T4CON; /**< 8 Control Register */
6456 volatile const uint8_t RESERVED2[2];
6457 volatile uint16_t T4INC; /**< C 12-bit Interval for Wakeup Field a */
6458 volatile const uint8_t RESERVED3[2];
6459 volatile uint16_t T4WUFB0; /**< 10 Wakeup Field B - LS 16 Bits */
6460 volatile const uint8_t RESERVED4[2];
6461 volatile uint16_t T4WUFB1; /**< 14 Wakeup Field B - MS 16 Bits */
6462 volatile const uint8_t RESERVED5[2];
6463 volatile uint16_t T4WUFC0; /**< 18 Wakeup Field C - LS 16 Bits */
6464 volatile const uint8_t RESERVED6[2];
6465 volatile uint16_t T4WUFC1; /**< 1C Wakeup Field C - MS 16 Bits */
6466 volatile const uint8_t RESERVED7[2];
6467 volatile uint16_t T4WUFD0; /**< 20 Wakeup Field D - LS 16 Bits */
6468 volatile const uint8_t RESERVED8[2];
6469 volatile uint16_t T4WUFD1; /**< 24 Wakeup Field D - MS 16 Bits */
6470 volatile const uint8_t RESERVED9[2];
6471 volatile uint16_t T4IEN; /**< 28 Interrupt Enable Register */
6472 volatile const uint8_t RESERVED10[2];
6473 volatile const uint16_t T4STA; /**< 2C Status Register */
6474 volatile const uint8_t RESERVED11[2];
6475 volatile uint16_t T4CLRI; /**< 30 Clear Interrupt Register */
6476 volatile const uint8_t RESERVED12[10];
6477 volatile uint16_t T4WUFA0; /**< 3C Wakeup Field a - LS 16 Bits */
6478 volatile const uint8_t RESERVED13[2];
6479 volatile uint16_t T4WUFA1; /**< 40 Wakeup Field a - MS 16 Bits */
6480} ADI_WUT_TypeDef;
6481
6482/*! ========================================================================
6483 * \struct ADI_WDT_TypeDef
6484 * \brief Watchdog Timer Register Map
6485 * ======================================================================== */
6486typedef struct _ADI_WDT_TypeDef
6487{
6488 volatile uint16_t LD; /**< 0 Watchdog Timer Load Value */
6489 volatile const uint8_t RESERVED0[2];
6490 volatile const uint16_t VALS; /**< 4 Current Count Value */
6491 volatile const uint8_t RESERVED1[2];
6492 volatile uint16_t CON; /**< 8 Watchdog Timer Control Register */
6493 volatile const uint8_t RESERVED2[2];
6494 volatile uint16_t CLRI; /**< C Refresh Watchdog Register */
6495 volatile const uint8_t RESERVED3[10];
6496 volatile const uint16_t STA; /**< 18 Timer Status */
6497 volatile const uint8_t RESERVED4[2];
6498 volatile uint16_t MINLD; /**< 1C Minimum Load Value */
6499} ADI_WDT_TypeDef;
6500
6501/*! ========================================================================
6502 * \struct ADI_ALWAYS_ON_TypeDef
6503 * \brief Always on clock, reset, power management and test
6504 * ======================================================================== */
6505typedef struct _ADI_ALWAYS_ON_TypeDef
6506{
6507 volatile uint16_t PWRMOD; /**< 0 Power Modes */
6508 volatile const uint8_t RESERVED0[2];
6509 volatile uint16_t PWRKEY; /**< 4 Key Protection for PWRMOD */
6510 volatile const uint8_t RESERVED1[2];
6511 volatile uint16_t RSTCFG; /**< 8 Reset Configuration */
6512 volatile const uint8_t RESERVED2[2];
6513 volatile uint16_t RSTKEY; /**< C Key Protection for RSTCFG */
6514 volatile const uint8_t RESERVED3[18];
6515 volatile uint16_t EI0CFG; /**< 20 External Interrupt Configuration 0 */
6516 volatile const uint8_t RESERVED4[2];
6517 volatile uint16_t EI1CFG; /**< 24 External Interrupt Configuration 1 */
6518 volatile const uint8_t RESERVED5[2];
6519 volatile uint16_t EI2CFG; /**< 28 External Interrupt Configuration 2 */
6520 volatile const uint8_t RESERVED6[6];
6521 volatile uint16_t EICLR; /**< 30 External Interrupt Clear */
6522 volatile const uint8_t RESERVED7[14];
6523 volatile uint16_t RSTSTA; /**< 40 Reset Status */
6524} ADI_ALWAYS_ON_TypeDef;
6525
6526/*! ========================================================================
6527 * \struct ADI_PLA_TypeDef
6528 * \brief PLA Register Map
6529 * ======================================================================== */
6530typedef struct _ADI_PLA_TypeDef
6531{
6532 volatile uint16_t PLA_ELEM0; /**< 0 ELEMx Configuration Register */
6533 volatile const uint8_t RESERVED0[2];
6534 volatile uint16_t PLA_ELEM1; /**< 4 ELEMx Configuration Register */
6535 volatile const uint8_t RESERVED1[2];
6536 volatile uint16_t PLA_ELEM2; /**< 8 ELEMx Configuration Register */
6537 volatile const uint8_t RESERVED2[2];
6538 volatile uint16_t PLA_ELEM3; /**< C ELEMx Configuration Register */
6539 volatile const uint8_t RESERVED3[2];
6540 volatile uint16_t PLA_ELEM4; /**< 10 ELEMx Configuration Register */
6541 volatile const uint8_t RESERVED4[2];
6542 volatile uint16_t PLA_ELEM5; /**< 14 ELEMx Configuration Register */
6543 volatile const uint8_t RESERVED5[2];
6544 volatile uint16_t PLA_ELEM6; /**< 18 ELEMx Configuration Register */
6545 volatile const uint8_t RESERVED6[2];
6546 volatile uint16_t PLA_ELEM7; /**< 1C ELEMx Configuration Register */
6547 volatile const uint8_t RESERVED7[2];
6548 volatile uint16_t PLA_ELEM8; /**< 20 ELEMx Configuration Register */
6549 volatile const uint8_t RESERVED8[2];
6550 volatile uint16_t PLA_ELEM9; /**< 24 ELEMx Configuration Register */
6551 volatile const uint8_t RESERVED9[2];
6552 volatile uint16_t PLA_ELEM10; /**< 28 ELEMx Configuration Register */
6553 volatile const uint8_t RESERVED10[2];
6554 volatile uint16_t PLA_ELEM11; /**< 2C ELEMx Configuration Register */
6555 volatile const uint8_t RESERVED11[2];
6556 volatile uint16_t PLA_ELEM12; /**< 30 ELEMx Configuration Register */
6557 volatile const uint8_t RESERVED12[2];
6558 volatile uint16_t PLA_ELEM13; /**< 34 ELEMx Configuration Register */
6559 volatile const uint8_t RESERVED13[2];
6560 volatile uint16_t PLA_ELEM14; /**< 38 ELEMx Configuration Register */
6561 volatile const uint8_t RESERVED14[2];
6562 volatile uint16_t PLA_ELEM15; /**< 3C ELEMx Configuration Register */
6563 volatile const uint8_t RESERVED15[2];
6564 volatile uint16_t PLA_ELEM16; /**< 40 ELEMx Configuration Register */
6565 volatile const uint8_t RESERVED16[2];
6566 volatile uint16_t PLA_ELEM17; /**< 44 ELEMx Configuration Register */
6567 volatile const uint8_t RESERVED17[2];
6568 volatile uint16_t PLA_ELEM18; /**< 48 ELEMx Configuration Register */
6569 volatile const uint8_t RESERVED18[2];
6570 volatile uint16_t PLA_ELEM19; /**< 4C ELEMx Configuration Register */
6571 volatile const uint8_t RESERVED19[2];
6572 volatile uint16_t PLA_ELEM20; /**< 50 ELEMx Configuration Register */
6573 volatile const uint8_t RESERVED20[2];
6574 volatile uint16_t PLA_ELEM21; /**< 54 ELEMx Configuration Register */
6575 volatile const uint8_t RESERVED21[2];
6576 volatile uint16_t PLA_ELEM22; /**< 58 ELEMx Configuration Register */
6577 volatile const uint8_t RESERVED22[2];
6578 volatile uint16_t PLA_ELEM23; /**< 5C ELEMx Configuration Register */
6579 volatile const uint8_t RESERVED23[2];
6580 volatile uint16_t PLA_ELEM24; /**< 60 ELEMx Configuration Register */
6581 volatile const uint8_t RESERVED24[2];
6582 volatile uint16_t PLA_ELEM25; /**< 64 ELEMx Configuration Register */
6583 volatile const uint8_t RESERVED25[2];
6584 volatile uint16_t PLA_ELEM26; /**< 68 ELEMx Configuration Register */
6585 volatile const uint8_t RESERVED26[2];
6586 volatile uint16_t PLA_ELEM27; /**< 6C ELEMx Configuration Register */
6587 volatile const uint8_t RESERVED27[2];
6588 volatile uint16_t PLA_ELEM28; /**< 70 ELEMx Configuration Register */
6589 volatile const uint8_t RESERVED28[2];
6590 volatile uint16_t PLA_ELEM29; /**< 74 ELEMx Configuration Register */
6591 volatile const uint8_t RESERVED29[2];
6592 volatile uint16_t PLA_ELEM30; /**< 78 ELEMx Configuration Register */
6593 volatile const uint8_t RESERVED30[2];
6594 volatile uint16_t PLA_ELEM31; /**< 7C ELEMx Configuration Register */
6595 volatile const uint8_t RESERVED31[2];
6596 volatile uint16_t PLA_CLK; /**< 80 PLA Clock Select */
6597 volatile const uint8_t RESERVED32[2];
6598 volatile uint16_t PLA_IRQ0; /**< 84 Interrupt Register for Block 0 */
6599 volatile const uint8_t RESERVED33[2];
6600 volatile uint16_t PLA_IRQ1; /**< 88 Interrupt Register for Block1 */
6601 volatile const uint8_t RESERVED34[2];
6602 volatile uint16_t PLA_ADC; /**< 8C ADC Configuration Register */
6603 volatile const uint8_t RESERVED35[2];
6604 volatile int16_t PLA_DIN0; /**< 90 AMBA Bus Data Input for Block 0 */
6605 volatile const uint8_t RESERVED36[6];
6606 volatile const uint16_t PLA_DOUT0; /**< 98 AMBA Bus Data Output for Block 0 */
6607 volatile const uint8_t RESERVED37[2];
6608 volatile const uint16_t PLA_DOUT1; /**< 9C AMBA Bus Data Output for Block1 */
6609 volatile const uint8_t RESERVED38[2];
6610 volatile uint16_t PLA_LCK; /**< A0 Write Lock Register. */
6611 volatile const uint8_t RESERVED39[2];
6612 volatile uint16_t PLA_IRQTYPE; /**< A4 PLA Interrupt Request and DMA Request Type */
6613} ADI_PLA_TypeDef;
6614
6615/*! ========================================================================
6616 * \struct ADI_DMAREQ_TypeDef
6617 * \brief Your module description, here.
6618 * ======================================================================== */
6619typedef struct _ADI_DMAREQ_TypeDef
6620{
6621 volatile uint8_t REQEN; /**< 0 GPT/GPT32 and PLA DMA Request Enable */
6622 volatile const uint8_t RESERVED0[3];
6623 volatile uint8_t REQ0SEL; /**< 4 GPT/GPT32 and PLA DMA Request 0 Select */
6624 volatile const uint8_t RESERVED1[3];
6625 volatile uint8_t REQ1SEL; /**< 8 GPT/GPT32 and PLA DMA Request 1 Select */
6626 volatile const uint8_t RESERVED2[3];
6627 volatile uint8_t PLAREQEN; /**< C PLA DMA Requests Enable */
6628 volatile const uint8_t RESERVED3[3];
6629 volatile uint8_t GPTREQEN; /**< 10 GPT/GPT32 DMA Requests Enable */
6630 volatile const uint8_t RESERVED4[3];
6631 volatile uint16_t GPT_MDA_REQ_TTYPE; /**< 14 GPT and GPT32 Require Type */
6632} ADI_DMAREQ_TypeDef;
6633
6634/*! ========================================================================
6635 * \struct ADI_UART_TypeDef
6636 * \brief Universal Asynchronous Receiver/Transmitter
6637 * ======================================================================== */
6638typedef struct _ADI_UART_TypeDef
6639{
6640 union {
6641 volatile const uint16_t RX; /*!< Receive Buffer Register */
6642 volatile uint16_t TX; /*!< Transmit Holding Register */
6643 };
6644 volatile const uint8_t RESERVED0[2];
6645 volatile uint16_t IEN; /**< 4 Interrupt Enable */
6646 volatile const uint8_t RESERVED1[2];
6647 volatile const uint16_t IIR; /**< 8 Interrupt ID */
6648 volatile const uint8_t RESERVED2[2];
6649 volatile uint16_t LCR; /**< C Line Control */
6650 volatile const uint8_t RESERVED3[2];
6651 volatile uint16_t MCR; /**< 10 Modem Control */
6652 volatile const uint8_t RESERVED4[2];
6653 volatile const uint16_t LSR; /**< 14 Line Status */
6654 volatile const uint8_t RESERVED5[2];
6655 volatile const uint16_t MSR; /**< 18 Modem Status */
6656 volatile const uint8_t RESERVED6[2];
6657 volatile uint16_t SCR; /**< 1C Scratch Buffer */
6658 volatile const uint8_t RESERVED7[2];
6659 volatile uint16_t FCR; /**< 20 FIFO Control */
6660 volatile const uint8_t RESERVED8[2];
6661 volatile uint16_t FBR; /**< 24 Fractional Baud Rate */
6662 volatile const uint8_t RESERVED9[2];
6663 volatile uint16_t DIV; /**< 28 Baudrate Divider */
6664 volatile const uint8_t RESERVED10[2];
6665 volatile uint16_t LCR2; /**< 2C Second Line Control */
6666 volatile const uint8_t RESERVED11[2];
6667 volatile uint16_t CTL; /**< 30 UART Control Register */
6668 volatile const uint8_t RESERVED12[2];
6669 volatile const uint16_t RFC; /**< 34 RX FIFO Byte Count */
6670 volatile const uint8_t RESERVED13[2];
6671 volatile const uint16_t TFC; /**< 38 TX FIFO Byte Count */
6672 volatile const uint8_t RESERVED14[2];
6673 volatile uint16_t RSC; /**< 3C RS485 Half-duplex Control */
6674 volatile const uint8_t RESERVED15[2];
6675 volatile uint16_t ACR; /**< 40 Auto Baud Control */
6676 volatile const uint8_t RESERVED16[2];
6677 volatile const uint16_t ASRL; /**< 44 Auto Baud Status (Low) */
6678 volatile const uint8_t RESERVED17[2];
6679 volatile const uint16_t ASRH; /**< 48 Auto Baud Status (High) */
6680} ADI_UART_TypeDef;
6681
6682/*! ========================================================================
6683 * \struct ADI_I2C_TypeDef
6684 * \brief I2C Master/Slave
6685 * ======================================================================== */
6686typedef struct _ADI_I2C_TypeDef
6687{
6688 volatile uint16_t MCTL; /**< 0 Master Control */
6689 volatile const uint8_t RESERVED0[2];
6690 volatile uint16_t MSTAT; /**< 4 Master Status */
6691 volatile const uint8_t RESERVED1[2];
6692 volatile const uint16_t MRX; /**< 8 Master Receive Data */
6693 volatile const uint8_t RESERVED2[2];
6694 volatile uint16_t MTX; /**< C Master Transmit Data */
6695 volatile const uint8_t RESERVED3[2];
6696 volatile uint16_t MRXCNT; /**< 10 Master Receive Data Count */
6697 volatile const uint8_t RESERVED4[2];
6698 volatile const uint16_t MCRXCNT; /**< 14 Master Current Receive Data Count */
6699 volatile const uint8_t RESERVED5[2];
6700 volatile uint16_t ADDR0; /**< 18 1st Master Address Byte */
6701 volatile const uint8_t RESERVED6[2];
6702 volatile uint16_t ADDR1; /**< 1C 2nd Master Address Byte */
6703 volatile const uint8_t RESERVED7[2];
6704 volatile uint16_t BYT; /**< 20 Start Byte */
6705 volatile const uint8_t RESERVED8[2];
6706 volatile uint16_t DIV; /**< 24 Serial Clock Period Divisor */
6707 volatile const uint8_t RESERVED9[2];
6708 volatile uint16_t SCTL; /**< 28 Slave Control */
6709 volatile const uint8_t RESERVED10[2];
6710 volatile uint16_t SSTAT; /**< 2C Slave I2C Status/Error/IRQ */
6711 volatile const uint8_t RESERVED11[2];
6712 volatile const uint16_t SRX; /**< 30 Slave Receive */
6713 volatile const uint8_t RESERVED12[2];
6714 volatile uint16_t STX; /**< 34 Slave Transmit */
6715 volatile const uint8_t RESERVED13[2];
6716 volatile uint16_t ALT; /**< 38 Hardware General Call ID */
6717 volatile const uint8_t RESERVED14[2];
6718 volatile uint16_t ID0; /**< 3C 1st Slave Address Device ID */
6719 volatile const uint8_t RESERVED15[2];
6720 volatile uint16_t ID1; /**< 40 2nd Slave Address Device ID */
6721 volatile const uint8_t RESERVED16[2];
6722 volatile uint16_t ID2; /**< 44 3rd Slave Address Device ID */
6723 volatile const uint8_t RESERVED17[2];
6724 volatile uint16_t ID3; /**< 48 4th Slave Address Device ID */
6725 volatile const uint8_t RESERVED18[2];
6726 volatile uint16_t STAT; /**< 4C Master and Slave FIFO Status */
6727 volatile const uint8_t RESERVED19[2];
6728 volatile uint16_t SHCTL; /**< 50 Shared Control */
6729 volatile const uint8_t RESERVED20[2];
6730 volatile uint16_t TCTL; /**< 54 Timing Control Register */
6731 volatile const uint8_t RESERVED21[2];
6732 volatile uint16_t ASTRETCH_SCL; /**< 58 Automatic Stretch SCL Register */
6733 volatile const uint8_t RESERVED22[2];
6734 volatile uint16_t IDFSTA; /**< 5C ID FIFO Status Register */
6735 volatile const uint8_t RESERVED23[2];
6736 volatile uint16_t SLV_ADDR1; /**< 60 Slave 10 Bits Address 1st Byte. */
6737 volatile const uint8_t RESERVED24[2];
6738 volatile uint16_t SLV_ADDR2; /**< 64 Slave 10 Bits Address 2nd Byte. */
6739 volatile const uint8_t RESERVED25[2];
6740 volatile const uint16_t SSTAT2; /**< 68 Slave I2C Status/IRQ 2 */
6741} ADI_I2C_TypeDef;
6742
6743/*! ========================================================================
6744 * \struct ADI_MDIO_TypeDef
6745 * \brief MDIO Interface
6746 * ======================================================================== */
6747typedef struct _ADI_MDIO_TypeDef
6748{
6749 volatile uint16_t MDCON; /**< 0 MDIO Block Control */
6750 volatile const uint8_t RESERVED0[2];
6751 volatile const uint16_t MDFRM; /**< 4 MDIO Received Frame Control Information */
6752 volatile const uint8_t RESERVED1[2];
6753 volatile const uint16_t MDRXD; /**< 8 MDIO Received Data */
6754 volatile const uint8_t RESERVED2[2];
6755 volatile const uint16_t MDADR; /**< C MDIO Received Address */
6756 volatile const uint8_t RESERVED3[2];
6757 volatile uint16_t MDTXD; /**< 10 MDIO Data for Transmission */
6758 volatile const uint8_t RESERVED4[2];
6759 volatile uint16_t MDPHY; /**< 14 MDIO PHYADDR Software Values and Selection and DEVADD */
6760 volatile const uint8_t RESERVED5[2];
6761 volatile const uint16_t MDSTA; /**< 18 MDIO Progress Signaling Through Frame */
6762 volatile const uint8_t RESERVED6[2];
6763 volatile uint16_t MDIEN; /**< 1C MDIO Interrupt Enables */
6764 volatile const uint8_t RESERVED7[2];
6765 volatile const uint16_t MDPIN; /**< 20 MDIO Read PHYADDR Pins */
6766 volatile const uint8_t RESERVED8[6];
6767 volatile uint16_t DMAEN; /**< 28 MDIO DMA Enable */
6768 volatile const uint8_t RESERVED9[2];
6769 volatile uint16_t MDTESTCON; /**< 2C MDIO Test Controller Protected by Test Key */
6770} ADI_MDIO_TypeDef;
6771
6772/*! ========================================================================
6773 * \struct ADI_DMA_TypeDef
6774 * \brief DMA
6775 * ======================================================================== */
6776typedef struct _ADI_DMA_TypeDef
6777{
6778 volatile const uint32_t STAT; /**< 0 DMA Status */
6779 volatile uint32_t CFG; /**< 4 DMA Configuration */
6780 volatile uint32_t PDBPTR; /**< 8 DMA Channel Primary Control Data Base Pointer */
6781 volatile const uint32_t ADBPTR; /**< C DMA Channel Alternate Control Data Base Pointer */
6782 volatile const uint8_t RESERVED0[4];
6783 volatile uint32_t SWREQ; /**< 14 DMA Channel Software Request */
6784 volatile const uint8_t RESERVED1[8];
6785 volatile uint32_t RMSKSET; /**< 20 DMA Channel Request Mask Set */
6786 volatile uint32_t RMSKCLR; /**< 24 DMA Channel Request Mask Clear */
6787 volatile uint32_t ENSET; /**< 28 DMA Channel Enable Set */
6788 volatile uint32_t ENCLR; /**< 2C DMA Channel Enable Clear */
6789 volatile uint32_t ALTSET; /**< 30 DMA Channel Primary-alternate Set */
6790 volatile uint32_t ALTCLR; /**< 34 DMA Channel Primary-alternate Clear */
6791 volatile uint32_t PRISET; /**< 38 DMA Channel Priority Set */
6792 volatile uint32_t PRICLR; /**< 3C DMA Channel Priority Clear */
6793 volatile const uint8_t RESERVED2[8];
6794 volatile uint32_t ERRCHNLCLR; /**< 48 DMA per Channel Error Clear */
6795 volatile uint32_t ERRCLR; /**< 4C DMA Bus Error Clear */
6796 volatile uint32_t INVALIDDESCCLR; /**< 50 DMA per Channel Invalid Descriptor Clear */
6797 volatile const uint8_t RESERVED3[1964];
6798 volatile uint32_t BSSET; /**< 800 DMA Channel Bytes Swap Enable Set */
6799 volatile uint32_t BSCLR; /**< 804 DMA Channel Bytes Swap Enable Clear */
6800 volatile const uint8_t RESERVED4[8];
6801 volatile uint32_t SRCADDRSET; /**< 810 DMA Channel Source Address Decrement Enable Set */
6802 volatile uint32_t SRCADDRCLR; /**< 814 DMA Channel Source Address Decrement Enable Clear */
6803 volatile uint32_t DSTADDRSET; /**< 818 DMA Channel Destination Address Decrement Enable Set */
6804 volatile uint32_t DSTADDRCLR; /**< 81C DMA Channel Destination Address Decrement Enable Clear */
6805 volatile const uint8_t RESERVED5[1984];
6806 volatile const uint32_t REVID; /**< FE0 DMA Controller Revision ID */
6807} ADI_DMA_TypeDef;
6808
6809/*! ========================================================================
6810 * \struct ADI_CC_TypeDef
6811 * \brief Cache Controller
6812 * ======================================================================== */
6813typedef struct _ADI_CC_TypeDef
6814{
6815 volatile const uint32_t STAT; /**< 0 Cache Status Register */
6816 volatile uint32_t SETUP; /**< 4 Cache Setup Register */
6817 volatile uint32_t KEY; /**< 8 Cache Key Register */
6818 volatile uint32_t PERFSETUP; /**< C Cache Performance Monitor Setup Register */
6819 volatile const uint32_t ACCESSCNTR; /**< 10 Cache Miss Counter */
6820 volatile const uint8_t RESERVED0[16];
6821 volatile uint32_t MSTRSETUP; /**< 24 Cache Master Setup Register */
6822 volatile const uint8_t RESERVED1[12];
6823 volatile const uint32_t ECCSTAT; /**< 34 Cache SRAM ECC Status Register */
6824 volatile const uint32_t ECCADDR; /**< 38 Cache SRAM ECC Address Register */
6825} ADI_CC_TypeDef;
6826
6827/*! ========================================================================
6828 * \struct ADI_FLASH_TypeDef
6829 * \brief Flash Controller
6830 * ======================================================================== */
6831typedef struct _ADI_FLASH_TypeDef
6832{
6833 volatile const uint32_t FEESTA; /**< 0 Status Register */
6834 volatile uint32_t FEECON0; /**< 4 Command Control Register – Interrupt Enable Register */
6835 volatile uint32_t FEECMD; /**< 8 Command Register */
6836 volatile uint32_t FEEFLADR; /**< C Flash Address Key - Hole Register */
6837 volatile uint32_t FEEFLDATA0; /**< 10 Flash Data Register - Key - Hole Interface Lower 32 Bits */
6838 volatile uint32_t FEEFLDATA1; /**< 14 Flash Data Register - Key - Hole Interface Upper 32 Bits */
6839 volatile uint32_t FEEADR0; /**< 18 Lower Page Address */
6840 volatile uint32_t FEEADR1; /**< 1C Upper Page Address */
6841 volatile uint32_t FEEKEY; /**< 20 Flash Key Register. */
6842 volatile const uint8_t RESERVED0[4];
6843 volatile uint32_t FEEPRO0; /**< 28 Write Protection Register for Flash0 */
6844 volatile uint32_t FEEPRO1; /**< 2C Write Protection Register for Flash1 */
6845 volatile const uint8_t RESERVED1[4];
6846 volatile const uint32_t FEESIG; /**< 34 Flash Signature */
6847 volatile uint32_t FEECON1; /**< 38 User Setup Register */
6848 volatile const uint8_t RESERVED2[4];
6849 volatile const uint32_t FEEWRADDRA; /**< 40 Write Abort Address Register */
6850 volatile const uint8_t RESERVED3[4];
6851 volatile uint32_t FEEAEN0; /**< 48 Lower 32 Bits of the Sys Irq Abort Enable Register. */
6852 volatile uint32_t FEEAEN1; /**< 4C Middle 32 Bits of the Sys Irq Abort Enable Register. */
6853 volatile uint32_t FEEAEN2; /**< 50 Upper 32 Bits of the Sys Irq Abort Enable Register. */
6854 volatile const uint8_t RESERVED4[16];
6855 volatile uint32_t FEEECCCONFIG; /**< 64 Configurable ECC Enable/disable, Error Response */
6856 volatile const uint8_t RESERVED5[12];
6857 volatile const uint32_t FEEECCADDRC0; /**< 74 Flash 0 ECC Error Address via CODE Bus */
6858 volatile const uint32_t FEEECCADDRC1; /**< 78 Flash 1 ECC Error Address via CODE Bus */
6859 volatile const uint8_t RESERVED6[24];
6860 volatile const uint32_t FEEECCADDRD0; /**< 94 Flash 0 ECC Error Address via DMA Bus */
6861 volatile const uint32_t FEEECCADDRD1; /**< 98 Flash 1 ECC Error Address via DMA Bus */
6862} ADI_FLASH_TypeDef;
6863
6864/*! ========================================================================
6865 * \struct ADI_GPIO_TypeDef
6866 * \brief GPIO
6867 * ======================================================================== */
6868typedef struct _ADI_GPIO_TypeDef
6869{
6870 volatile uint16_t CON; /**< 0 Port Configuration */
6871 volatile const uint8_t RESERVED0[2];
6872 volatile uint8_t OE; /**< 4 Port Output Enable */
6873 volatile const uint8_t RESERVED1[3];
6874 volatile uint8_t IE; /**< 8 Port Input Path Enable */
6875 volatile const uint8_t RESERVED2[3];
6876 volatile const uint8_t IN; /**< C Port Registered Data Input */
6877 volatile const uint8_t RESERVED3[3];
6878 volatile uint8_t OUT; /**< 10 Port Data Output */
6879 volatile const uint8_t RESERVED4[3];
6880 volatile uint8_t SET; /**< 14 Port Data Out Set */
6881 volatile const uint8_t RESERVED5[3];
6882 volatile uint8_t CLR; /**< 18 Port Data Out Clear */
6883 volatile const uint8_t RESERVED6[3];
6884 volatile uint8_t TGL; /**< 1C Port Pin Toggle */
6885 volatile const uint8_t RESERVED7[3];
6886 volatile uint8_t ODE; /**< 20 Port Open Drain Enable */
6887 volatile const uint8_t RESERVED8[3];
6888 volatile uint8_t IS; /**< 24 Port Input Select */
6889 volatile const uint8_t RESERVED9[3];
6890 volatile uint8_t PE; /**< 28 Port Pull Enable */
6891 volatile const uint8_t RESERVED10[3];
6892 volatile uint8_t PS; /**< 2C Port Pull Select */
6893 volatile const uint8_t RESERVED11[3];
6894 volatile uint8_t SR; /**< 30 Port Slew Rate */
6895 volatile const uint8_t RESERVED12[3];
6896 volatile uint16_t DS; /**< 34 Port Drive Select */
6897 volatile const uint8_t RESERVED13[2];
6898 volatile uint8_t PWR; /**< 38 Port Power Select */
6899 volatile const uint8_t RESERVED14[3];
6900 volatile uint8_t POL; /**< 3C GPIO Interrupt Polarity Select */
6901 volatile const uint8_t RESERVED15[3];
6902 volatile uint8_t IENA; /**< 40 InterruptA Enable */
6903 volatile const uint8_t RESERVED16[3];
6904 volatile uint8_t IENB; /**< 44 InterruptB Enable */
6905 volatile const uint8_t RESERVED17[3];
6906 volatile uint8_t INT; /**< 48 Interrupt Status */
6907 volatile const uint8_t RESERVED18[3];
6908} ADI_GPIO_TypeDef;
6909
6910/*! ========================================================================
6911 * \struct ADI_SPI_TypeDef
6912 * \brief Serial Peripheral Interface
6913 * ======================================================================== */
6914typedef struct _ADI_SPI_TypeDef
6915{
6916 volatile uint16_t STAT; /**< 0 Status */
6917 volatile const uint8_t RESERVED0[2];
6918 volatile const uint16_t RX; /**< 4 Receive */
6919 volatile const uint8_t RESERVED1[2];
6920 volatile uint16_t TX; /**< 8 Transmit */
6921 volatile const uint8_t RESERVED2[2];
6922 volatile uint16_t DIV; /**< C SPI Baud Rate Selection */
6923 volatile const uint8_t RESERVED3[2];
6924 volatile uint16_t CTL; /**< 10 SPI Configuration 1 */
6925 volatile const uint8_t RESERVED4[2];
6926 volatile uint16_t IEN; /**< 14 SPI Configuration 2 */
6927 volatile const uint8_t RESERVED5[2];
6928 volatile uint16_t CNT; /**< 18 Transfer Byte Count */
6929 volatile const uint8_t RESERVED6[2];
6930 volatile uint16_t DMA; /**< 1C SPI DMA Enable */
6931 volatile const uint8_t RESERVED7[2];
6932 volatile const uint16_t FIFOSTAT; /**< 20 FIFO Status */
6933 volatile const uint8_t RESERVED8[2];
6934 volatile uint16_t RDCTL; /**< 24 Read Control */
6935 volatile const uint8_t RESERVED9[2];
6936 volatile uint16_t FLOWCTL; /**< 28 Flow Control */
6937 volatile const uint8_t RESERVED10[2];
6938 volatile uint16_t WAITTMR; /**< 2C Wait Timer for Flow Control */
6939 volatile const uint8_t RESERVED11[6];
6940 volatile uint16_t CSOVERRIDE; /**< 34 Chip-Select Override */
6941} ADI_SPI_TypeDef;
6942
6943/*! ========================================================================
6944 * \struct ADI_CLOCK_TypeDef
6945 * \brief Clock Gating and Other Settings
6946 * ======================================================================== */
6947typedef struct _ADI_CLOCK_TypeDef
6948{
6949 volatile uint16_t CLKCON0; /**< 0 Misc Clock Settings Register */
6950 volatile const uint8_t RESERVED0[2];
6951 volatile uint16_t CLKCON1; /**< 4 Clock Dividers Register */
6952 volatile const uint8_t RESERVED1[2];
6953 volatile uint16_t CLKSTAT0; /**< 8 Clocking Status */
6954} ADI_CLOCK_TypeDef;
6955
6956/*! ========================================================================
6957 * \struct ADI_PWM_TypeDef
6958 * \brief PWM MMR
6959 * ======================================================================== */
6960typedef struct _ADI_PWM_TypeDef
6961{
6962 volatile uint16_t PWMCON0; /**< 0 PWM Control Register */
6963 volatile const uint8_t RESERVED0[2];
6964 volatile uint16_t PWMCON1; /**< 4 ADC Conversion Start and Trip Control Register */
6965 volatile const uint8_t RESERVED1[2];
6966 volatile uint16_t PWMICLR; /**< 8 Hardware Trip Configuration Register */
6967 volatile const uint8_t RESERVED2[6];
6968 volatile uint16_t PWM0COM0; /**< 10 Compare Register 0 for PWM0 and PWM1 */
6969 volatile const uint8_t RESERVED3[2];
6970 volatile uint16_t PWM0COM1; /**< 14 Compare Register 1 for PWM0 and PWM1 */
6971 volatile const uint8_t RESERVED4[2];
6972 volatile uint16_t PWM0COM2; /**< 18 Compare Register 2 for PWM0 and PWM1 */
6973 volatile const uint8_t RESERVED5[2];
6974 volatile uint16_t PWM0LEN; /**< 1C Period Value Register for PWM0 and PWM1 */
6975 volatile const uint8_t RESERVED6[2];
6976 volatile uint16_t PWM1COM0; /**< 20 Compare Register 0 for PWM2 and PWM3 */
6977 volatile const uint8_t RESERVED7[2];
6978 volatile uint16_t PWM1COM1; /**< 24 Compare Register 1 for PWM2 and PWM3 */
6979 volatile const uint8_t RESERVED8[2];
6980 volatile uint16_t PWM1COM2; /**< 28 Compare Register 2 for PWM2 and PWM3 */
6981 volatile const uint8_t RESERVED9[2];
6982 volatile uint16_t PWM1LEN; /**< 2C Period Value Register for PWM2 and PWM3 */
6983 volatile const uint8_t RESERVED10[2];
6984 volatile uint16_t PWM2COM0; /**< 30 Compare Register 0 for PWM4 and PWM5 */
6985 volatile const uint8_t RESERVED11[2];
6986 volatile uint16_t PWM2COM1; /**< 34 Compare Register 1 for PWM4 and PWM5 */
6987 volatile const uint8_t RESERVED12[2];
6988 volatile uint16_t PWM2COM2; /**< 38 Compare Register 2 for PWM4 and PWM5 */
6989 volatile const uint8_t RESERVED13[2];
6990 volatile uint16_t PWM2LEN; /**< 3C Period Value Register for PWM4 and PWM5 */
6991} ADI_PWM_TypeDef;
6992
6993/*! ========================================================================
6994 * \struct ADI_SUBSYS_TypeDef
6995 * \brief Your module description, here.
6996 * ======================================================================== */
6997typedef struct _ADI_SUBSYS_TypeDef
6998{
6999 volatile uint32_t SRAMCON; /**< 0 SRAM Control Register */
7000 volatile const uint8_t RESERVED0[8];
7001 volatile uint32_t SRAMECCCON; /**< C SRAM ECC Control Register */
7002 volatile const uint32_t SRAMECCSTA; /**< 10 SRAM ECC Status Register */
7003 volatile const uint32_t SRAMECCA0; /**< 14 SRAM0 ECC Error Address Register */
7004 volatile const uint32_t SRAMECCD0; /**< 18 SRAM0 ECC Error Data Register */
7005 volatile const uint32_t SRAMECCP0; /**< 1C SRAM0 ECC Error Parity Register */
7006 volatile const uint32_t SRAMECCA1; /**< 20 SRAM1 ECC Error Address Register */
7007 volatile const uint32_t SRAMECCD1; /**< 24 SRAM1 ECC Error Data Register */
7008 volatile const uint32_t SRAMECCP1; /**< 28 SRAM1 ECC Error Parity Register */
7009 volatile const uint32_t SRAMECCA2; /**< 2C SRAM2 ECC Error Address Register */
7010 volatile const uint32_t SRAMECCD2; /**< 30 SRAM2 ECC Error Data Register */
7011 volatile const uint32_t SRAMECCP2; /**< 34 SRAM2 ECC Error Parity Register */
7012} ADI_SUBSYS_TypeDef;
7013
7014/*! ========================================================================
7015 * \struct ADI_CRC_TypeDef
7016 * \brief CRC Accelerator
7017 * ======================================================================== */
7018typedef struct _ADI_CRC_TypeDef
7019{
7020 volatile uint32_t CTL; /**< 0 CRC Control Register */
7021 volatile int32_t IPDATA; /**< 4 Input Data Word Register */
7022 volatile int32_t RESULT; /**< 8 CRC Result Register */
7023 volatile uint32_t POLY; /**< C Programmable CRC Polynomial */
7024} ADI_CRC_TypeDef;
7025
7026/*! ========================================================================
7027 * \struct ADI_ADC_TypeDef
7028 * \brief Your module description, here.
7029 * ======================================================================== */
7030typedef struct _ADI_ADC_TypeDef
7031{
7032 volatile const uint32_t ADCDAT0; /**< 0 ADCx Data and Flags */
7033 volatile const uint32_t ADCDAT1; /**< 4 ADCx Data and Flags */
7034 volatile const uint32_t ADCDAT2; /**< 8 ADCx Data and Flags */
7035 volatile const uint32_t ADCDAT3; /**< C ADCx Data and Flags */
7036 volatile const uint32_t ADCDAT4; /**< 10 ADCx Data and Flags */
7037 volatile const uint32_t ADCDAT5; /**< 14 ADCx Data and Flags */
7038 volatile const uint32_t ADCDAT6; /**< 18 ADCx Data and Flags */
7039 volatile const uint32_t ADCDAT7; /**< 1C ADCx Data and Flags */
7040 volatile const uint32_t ADCDAT8; /**< 20 ADCx Data and Flags */
7041 volatile const uint32_t ADCDAT9; /**< 24 ADCx Data and Flags */
7042 volatile const uint32_t ADCDAT10; /**< 28 ADCx Data and Flags */
7043 volatile const uint32_t ADCDAT11; /**< 2C ADCx Data and Flags */
7044 volatile const uint32_t ADCDAT12; /**< 30 ADCx Data and Flags */
7045 volatile const uint32_t ADCDAT13; /**< 34 ADCx Data and Flags */
7046 volatile const uint32_t ADCDAT14; /**< 38 ADCx Data and Flags */
7047 volatile const uint32_t ADCDAT15; /**< 3C ADCx Data and Flags */
7048 volatile const uint32_t ADCDAT16; /**< 40 ADCx Data and Flags */
7049 volatile const uint32_t ADCDAT17; /**< 44 ADCx Data and Flags */
7050 volatile const uint32_t ADCDAT18; /**< 48 ADCx Data and Flags */
7051 volatile const uint32_t ADCDAT19; /**< 4C ADCx Data and Flags */
7052 volatile const uint32_t ADCDAT20; /**< 50 ADCx Data and Flags */
7053 volatile const uint32_t ADCDAT21; /**< 54 ADCx Data and Flags */
7054 volatile const uint32_t ADCDAT22; /**< 58 ADCx Data and Flags */
7055 volatile const uint32_t ADCDAT23; /**< 5C ADCx Data and Flags */
7056 volatile const uint32_t ADCDAT24; /**< 60 ADCx Data and Flags */
7057 volatile const uint32_t ADCDAT25; /**< 64 ADCx Data and Flags */
7058 volatile const uint32_t ADCDAT26; /**< 68 ADCx Data and Flags */
7059 volatile const uint32_t ADCDAT27; /**< 6C ADCx Data and Flags */
7060 volatile const uint32_t ADCDAT28; /**< 70 ADCx Data and Flags */
7061 volatile const uint32_t ADCDAT29; /**< 74 ADCx Data and Flags */
7062 volatile uint32_t ADCCON; /**< 78 ADC Configuration */
7063 volatile uint32_t PREBUFCON; /**< 7C Pre-charge Buffer Control */
7064 volatile uint32_t ADCCNVC; /**< 80 ADC Conversion Cycle for Positive Input Channels */
7065 volatile uint32_t ADCCNVCSLOW; /**< 84 ADC Conversion Cycle for Positive Input Channels */
7066 volatile uint32_t ADCCHA; /**< 88 ADC Channel Select */
7067 volatile const uint32_t ADCIRQSTAT; /**< 8C ADC Interrupt Status */
7068 volatile uint32_t ADCSEQ; /**< 90 ADC Sequencer Control */
7069 volatile uint32_t ADCSEQC; /**< 94 ADC Sequencer Configuration */
7070 volatile const uint32_t ADCSEQS; /**< 98 ADC Sequencer Status */
7071 volatile uint32_t ADCSEQCH; /**< 9C ADC Sequencer Channel 0 */
7072 volatile uint32_t ADCSEQCHMUX0; /**< A0 ADC Sequencer Channel 1 */
7073 volatile uint32_t ADCSEQCHMUX1; /**< A4 ADC Sequencer Channel 1 */
7074 volatile uint32_t ADCCMP; /**< A8 Digital Comparator 0 Configuration */
7075 volatile uint32_t ADCCMPIRQSTAT; /**< AC Digital Comparator Interrupt Status */
7076 volatile uint32_t ADCOFGNDIFF; /**< B0 ADC Offset Gain Differential Channel Error Correction */
7077 volatile uint32_t ADCOFTEMP; /**< B4 ADC Offset Gain Temp Sensor Channel Error Correction */
7078 volatile uint32_t ADCGNTEMP; /**< B8 ADC Offset Gain Temp Sensor Channel Error Correction */
7079 volatile uint32_t ADCOFGNPGA0; /**< BC ADC Offset Gain PGA0 Channel Error Correction */
7080 volatile uint32_t ADCOFGNPGA1; /**< C0 ADC Offset Gain PGA1 Channel Error Correction */
7081 volatile uint32_t ADCOFGNPGA2; /**< C4 ADC Offset Gain PGA2 Channel Error Correction */
7082 volatile uint32_t ADCOFGNPGA3; /**< C8 ADC Offset Gain PGA3 Channel Error Correction */
7083 volatile uint32_t ADCOFGNPGA0TIA; /**< CC ADC Offset Gain PGA0 Channel Error Correction */
7084 volatile uint32_t ADCOFGNPGA1TIA; /**< D0 ADC Offset Gain PGA1 Channel Error Correction */
7085 volatile uint32_t ADCOFGNPGA2TIA; /**< D4 ADC Offset Gain PGA2 Channel Error Correction */
7086 volatile uint32_t ADCOFGNPGA3TIA; /**< D8 ADC Offset Gain PGA3 Channel Error Correction */
7087 volatile const uint8_t RESERVED0[120];
7088 volatile uint32_t ADCCMP1; /**< 154 Digital Comparator 1 Configuration */
7089 volatile uint32_t ADCCMP2; /**< 158 Digital Comparator 2 Configuration */
7090 volatile uint32_t ADCCMP3; /**< 15C Digital Comparator 3 Configuration */
7091} ADI_ADC_TypeDef;
7092
7093/*! ========================================================================
7094 * \struct ADI_COMP_TypeDef
7095 * \brief Your module description, here.
7096 * ======================================================================== */
7097typedef struct _ADI_COMP_TypeDef
7098{
7099 volatile uint32_t COMPCON0; /**< 0 No description provided */
7100 volatile uint32_t COMPCON1; /**< 4 No description provided */
7101 volatile uint32_t COMPCON2; /**< 8 No description provided */
7102 volatile uint32_t COMPCON3; /**< C No description provided */
7103 volatile const uint32_t COMPIRQSTAT; /**< 10 No description provided */
7104} ADI_COMP_TypeDef;
7105
7106/*! ========================================================================
7107 * \struct ADI_OSC_MMRS_TypeDef
7108 * \brief Your module description, here.
7109 * ======================================================================== */
7110typedef struct _ADI_OSC_MMRS_TypeDef
7111{
7112 volatile const uint8_t RESERVED0[3];
7113 volatile uint32_t HFOSCCTRL; /**< 4 No description provided */
7114 volatile const uint8_t RESERVED1[16];
7115 volatile uint32_t HFXTALCTRL; /**< 18 No description provided */
7116} ADI_OSC_MMRS_TypeDef;
7117
7118/*! ========================================================================
7119 * \struct ADI_PGA_TypeDef
7120 * \brief Your module description, here.
7121 * ======================================================================== */
7122typedef struct _ADI_PGA_TypeDef
7123{
7124 volatile uint32_t PGABIASCON; /**< 0 PGA Bias Circuit Control Signal */
7125 volatile const uint8_t RESERVED0[28];
7126 volatile uint32_t PGA0CON; /**< 20 PGA0 Control Register */
7127 volatile uint32_t PGA0CHPCON; /**< 24 PGA0 Chop Function Ctrl */
7128 volatile uint32_t PGA3CHPCON; /**< 28 PGA3 Chop Function Ctrl */
7129 volatile const uint8_t RESERVED1[68];
7130 volatile uint32_t PGA1CON; /**< 70 PGA1 Control Register */
7131 volatile uint32_t PGA1CHPCON; /**< 74 PGA1 Chop Function Ctrl */
7132 volatile const uint8_t RESERVED2[40];
7133 volatile uint32_t PGA2CON; /**< A0 PGA2 Control Register */
7134 volatile uint32_t PGA2CHPCON; /**< A4 PGA2 Chop Function Ctrl */
7135 volatile const uint8_t RESERVED3[40];
7136 volatile uint32_t PGA3CON; /**< D0 PGA3 Control Register */
7137} ADI_PGA_TypeDef;
7138
7139/*! ========================================================================
7140 * \struct ADI_PLL_MMRS_TypeDef
7141 * \brief Your module description, here.
7142 * ======================================================================== */
7143typedef struct _ADI_PLL_MMRS_TypeDef
7144{
7145 volatile uint32_t PLLPDCTRL; /**< 0 No description provided */
7146} ADI_PLL_MMRS_TypeDef;
7147
7148/*! ========================================================================
7149 * \struct ADI_VCM_MMRS_TypeDef
7150 * \brief Your module description, here.
7151 * ======================================================================== */
7152typedef struct _ADI_VCM_MMRS_TypeDef
7153{
7154 volatile uint32_t TMPSNSCON; /**< 0 No description provided */
7155 volatile uint32_t TMPSNSCHPCON; /**< 4 No description provided */
7156 volatile uint32_t VCMREFCON; /**< 8 No description provided */
7157 volatile const uint8_t RESERVED0[4];
7158 volatile uint32_t VCMBUFCON; /**< 10 No description provided */
7159} ADI_VCM_MMRS_TypeDef;
7160
7161/*! ========================================================================
7162 * \struct ADI_DAC_TypeDef
7163 * \brief Your module description, here.
7164 * ======================================================================== */
7165typedef struct _ADI_DAC_TypeDef
7166{
7167 volatile uint32_t DACCON0; /**< 0 DAC Control Register */
7168 volatile uint32_t DACCON1; /**< 4 DAC Control Register */
7169 volatile uint32_t DACCON2; /**< 8 DAC Control Register */
7170 volatile uint32_t DACCON3; /**< C DAC Control Register */
7171 volatile uint32_t DACCON4; /**< 10 DAC Control Register */
7172 volatile uint32_t DACCON5; /**< 14 DAC Control Register */
7173 volatile uint32_t DACCON6; /**< 18 DAC Control Register */
7174 volatile uint32_t DACCON7; /**< 1C DAC Control Register */
7175 volatile uint32_t DACCON8; /**< 20 DAC Control Register */
7176 volatile uint32_t DACCON9; /**< 24 DAC Control Register */
7177 volatile uint32_t DACCON10; /**< 28 DAC Control Register */
7178 volatile uint32_t DACCON11; /**< 2C DAC Control Register */
7179 volatile uint32_t DACDAT0; /**< 30 DAC Data Register */
7180 volatile uint32_t DACDAT1; /**< 34 DAC Data Register */
7181 volatile uint32_t DACDAT2; /**< 38 DAC Data Register */
7182 volatile uint32_t DACDAT3; /**< 3C DAC Data Register */
7183 volatile uint32_t DACDAT4; /**< 40 DAC Data Register */
7184 volatile uint32_t DACDAT5; /**< 44 DAC Data Register */
7185 volatile uint32_t DACDAT6; /**< 48 DAC Data Register */
7186 volatile uint32_t DACDAT7; /**< 4C DAC Data Register */
7187 volatile uint32_t DACDAT8; /**< 50 DAC Data Register */
7188 volatile uint32_t DACDAT9; /**< 54 DAC Data Register */
7189 volatile uint32_t DACDAT10; /**< 58 DAC Data Register */
7190 volatile uint32_t DACDAT11; /**< 5C DAC Data Register */
7191} ADI_DAC_TypeDef;
7192
7193
7194/* =========================================================================
7195 * Peripheral Memory Map Declarations
7196 * ========================================================================= */
7197
7198#define ADI_GPT0_BASE (0x40000000U) /* Base address of gpt0: */
7199#define ADI_GPT1_BASE (0x40000400U) /* Base address of gpt1: */
7200#define ADI_GPT2_BASE (0x40000800U) /* Base address of gpt2: */
7201#define ADI_GPTH0_BASE (0x40000C00U) /* Base address of gpth0: */
7202#define ADI_GPTH1_BASE (0x40001000U) /* Base address of gpth1: */
7203#define ADI_MISC_BASE (0x40002000U) /* Base address of misc: */
7204#define ADI_WUT_BASE (0x40003000U) /* Base address of wut: */
7205#define ADI_WDT_BASE (0x40004000U) /* Base address of wdt: */
7206#define ADI_ALLON_BASE (0x40005000U) /* Base address of allon: */
7207#define ADI_PLA_BASE (0x40006000U) /* Base address of pla: */
7208#define ADI_DMAREQ_BASE (0x40007000U) /* Base address of dmareq: */
7209#define ADI_UART0_BASE (0x40020000U) /* Base address of uart0: */
7210#define ADI_UART1_BASE (0x40020400U) /* Base address of uart1: */
7211#define ADI_I2C0_BASE (0x40020800U) /* Base address of i2c0: */
7212#define ADI_I2C1_BASE (0x40020C00U) /* Base address of i2c1: */
7213#define ADI_I2C2_BASE (0x40021000U) /* Base address of i2c2: */
7214#define ADI_MDIO_BASE (0x40022000U) /* Base address of mdio: */
7215#define ADI_DMA_BASE (0x40040000U) /* Base address of dma: */
7216#define ADI_CACHE_BASE (0x40044000U) /* Base address of cache: */
7217#define ADI_FLASH_BASE (0x40048000U) /* Base address of flash: */
7218#define ADI_GPIO0_BASE (0x40050000U) /* Base address of gpio0: */
7219#define ADI_GPIO1_BASE (0x40050050U) /* Base address of gpio1: */
7220#define ADI_GPIO2_BASE (0x400500A0U) /* Base address of gpio2: */
7221#define ADI_GPIO3_BASE (0x400500F0U) /* Base address of gpio3: */
7222#define ADI_GPIO4_BASE (0x40050140U) /* Base address of gpio4: */
7223#define ADI_GPIO5_BASE (0x40050190U) /* Base address of gpio5: */
7224#define ADI_SPI0_BASE (0x40054000U) /* Base address of spi0: */
7225#define ADI_SPI1_BASE (0x40058000U) /* Base address of spi1: */
7226#define ADI_SPI2_BASE (0x4005C000U) /* Base address of spi2: */
7227#define ADI_CLK_BASE (0x40060000U) /* Base address of clk: */
7228#define ADI_PWM_BASE (0x40064000U) /* Base address of pwm: */
7229#define ADI_SRAM_BASE (0x40065000U) /* Base address of sram: */
7230#define ADI_CRC_BASE (0x40066000U) /* Base address of crc: */
7231#define ADI_ADC_BASE (0x40068000U) /* Base address of adc: */
7232#define ADI_COMP_BASE (0x40068A00U) /* Base address of comp: */
7233#define ADI_OSC_BASE (0x40068E00U) /* Base address of osc: */
7234#define ADI_PGA_BASE (0x40069000U) /* Base address of pga: */
7235#define ADI_PLL_BASE (0x40069200U) /* Base address of pll: */
7236#define ADI_TMPSNS_BASE (0x40069600U) /* Base address of tmpsns: */
7237#define ADI_VDAC_BASE (0x40069800U) /* Base address of vdac: */
7238
7239
7240/* =========================================================================
7241 * Peripheral Pointer Declarations
7242 * ========================================================================= */
7243
7244#define pADI_GPT0 ((ADI_TMR_TypeDef *) ADI_GPT0_BASE) /* Pointer to (gpt0)*/
7245#define pADI_GPT1 ((ADI_TMR_TypeDef *) ADI_GPT1_BASE) /* Pointer to (gpt1)*/
7246#define pADI_GPT2 ((ADI_TMR_TypeDef *) ADI_GPT2_BASE) /* Pointer to (gpt2)*/
7247#define pADI_GPTH0 ((ADI_TIMER_TypeDef *) ADI_GPTH0_BASE) /* Pointer to (gpth0)*/
7248#define pADI_GPTH1 ((ADI_TIMER_TypeDef *) ADI_GPTH1_BASE) /* Pointer to (gpth1)*/
7249#define pADI_MISC ((ADI_MISC16_TypeDef *) ADI_MISC_BASE) /* Pointer to (misc)*/
7250#define pADI_WUT ((ADI_WUT_TypeDef *) ADI_WUT_BASE) /* Pointer to (wut)*/
7251#define pADI_WDT ((ADI_WDT_TypeDef *) ADI_WDT_BASE) /* Pointer to (wdt)*/
7252#define pADI_ALLON ((ADI_ALWAYS_ON_TypeDef *) ADI_ALLON_BASE) /* Pointer to (allon)*/
7253#define pADI_PLA ((ADI_PLA_TypeDef *) ADI_PLA_BASE) /* Pointer to (pla)*/
7254#define pADI_DMAREQ ((ADI_DMAREQ_TypeDef *) ADI_DMAREQ_BASE) /* Pointer to (dmareq)*/
7255#define pADI_UART0 ((ADI_UART_TypeDef *) ADI_UART0_BASE) /* Pointer to (uart0)*/
7256#define pADI_UART1 ((ADI_UART_TypeDef *) ADI_UART1_BASE) /* Pointer to (uart1)*/
7257#define pADI_I2C0 ((ADI_I2C_TypeDef *) ADI_I2C0_BASE) /* Pointer to (i2c0)*/
7258#define pADI_I2C1 ((ADI_I2C_TypeDef *) ADI_I2C1_BASE) /* Pointer to (i2c1)*/
7259#define pADI_I2C2 ((ADI_I2C_TypeDef *) ADI_I2C2_BASE) /* Pointer to (i2c2)*/
7260#define pADI_MDIO ((ADI_MDIO_TypeDef *) ADI_MDIO_BASE) /* Pointer to (mdio)*/
7261#define pADI_DMA ((ADI_DMA_TypeDef *) ADI_DMA_BASE) /* Pointer to (dma)*/
7262#define pADI_CACHE ((ADI_CC_TypeDef *) ADI_CACHE_BASE) /* Pointer to (cache)*/
7263#define pADI_FLASH ((ADI_FLASH_TypeDef *) ADI_FLASH_BASE) /* Pointer to (flash)*/
7264#define pADI_GPIO0 ((ADI_GPIO_TypeDef *) ADI_GPIO0_BASE) /* Pointer to (gpio0)*/
7265#define pADI_GPIO1 ((ADI_GPIO_TypeDef *) ADI_GPIO1_BASE) /* Pointer to (gpio1)*/
7266#define pADI_GPIO2 ((ADI_GPIO_TypeDef *) ADI_GPIO2_BASE) /* Pointer to (gpio2)*/
7267#define pADI_GPIO3 ((ADI_GPIO_TypeDef *) ADI_GPIO3_BASE) /* Pointer to (gpio3)*/
7268#define pADI_GPIO4 ((ADI_GPIO_TypeDef *) ADI_GPIO4_BASE) /* Pointer to (gpio4)*/
7269#define pADI_GPIO5 ((ADI_GPIO_TypeDef *) ADI_GPIO5_BASE) /* Pointer to (gpio5)*/
7270#define pADI_SPI0 ((ADI_SPI_TypeDef *) ADI_SPI0_BASE) /* Pointer to (spi0)*/
7271#define pADI_SPI1 ((ADI_SPI_TypeDef *) ADI_SPI1_BASE) /* Pointer to (spi1)*/
7272#define pADI_SPI2 ((ADI_SPI_TypeDef *) ADI_SPI2_BASE) /* Pointer to (spi2)*/
7273#define pADI_CLK ((ADI_CLOCK_TypeDef *) ADI_CLK_BASE) /* Pointer to (clk)*/
7274#define pADI_PWM ((ADI_PWM_TypeDef *) ADI_PWM_BASE) /* Pointer to (pwm)*/
7275#define pADI_SRAM ((ADI_SUBSYS_TypeDef *) ADI_SRAM_BASE) /* Pointer to (sram)*/
7276#define pADI_CRC ((ADI_CRC_TypeDef *) ADI_CRC_BASE) /* Pointer to (crc)*/
7277#define pADI_ADC ((ADI_ADC_TypeDef *) ADI_ADC_BASE) /* Pointer to (adc)*/
7278#define pADI_COMP ((ADI_COMP_TypeDef *) ADI_COMP_BASE) /* Pointer to (comp)*/
7279#define pADI_OSC ((ADI_OSC_MMRS_TypeDef *) ADI_OSC_BASE) /* Pointer to (osc)*/
7280#define pADI_PGA ((ADI_PGA_TypeDef *) ADI_PGA_BASE) /* Pointer to (pga)*/
7281#define pADI_PLL ((ADI_PLL_MMRS_TypeDef *) ADI_PLL_BASE) /* Pointer to (pll)*/
7282#define pADI_TMPSNS ((ADI_VCM_MMRS_TypeDef *) ADI_TMPSNS_BASE) /* Pointer to (tmpsns)*/
7283#define pADI_VDAC ((ADI_DAC_TypeDef *) ADI_VDAC_BASE) /* Pointer to (vdac)*/
7284
7285/* =========================================================================
7286 *! \enum DMA_CHANn_TypeDef
7287 *! \brief DMAChannel Number Assignments
7288 * ========================================================================= */
7289
7290typedef enum
7291{
7292 SPI0_TX_CHANn = 0, /*!<* SPI0_TX */
7293 SPI0_RX_CHANn = 1, /*!<* SPI0_RX */
7294 SPI1_TX_CHANn = 2, /*!<* SPI1_TX */
7295 SPI1_RX_CHANn = 3, /*!<* SPI1_RX */
7296 SPI2_TX_CHANn = 4, /*!<* SPI2_TX */
7297 SPI2_RX_CHANn = 5, /*!<* SPI2_RX */
7298 UART0_TX_CHANn = 6, /*!<* UART0_TX */
7299 UART0_RX_CHANn = 7, /*!<* UART0_RX */
7300 UART1_TX_CHANn = 8, /*!<* UART1_TX */
7301 UART1_RX_CHANn = 9, /*!<* UART1_RX */
7302 I2C0S_TX_CHANn = 10, /*!<* I2C0S_TX */
7303 I2C0S_RX_CHANn = 11, /*!<* I2C0S_RX */
7304 I2C0M_CHANn = 12, /*!<* I2C0M */
7305 I2C1S_TX_CHANn = 13, /*!<* I2C1S_TX */
7306 I2C1S_RX_CHANn = 14, /*!<* I2C1S_RX */
7307 I2C1M_CHANn = 15, /*!<* I2C1M */
7308 I2C2S_TX_CHANn = 16, /*!<* I2C2S_TX */
7309 I2C2S_RX_CHANn = 17, /*!<* I2C2S_RX */
7310 I2C2M_CHANn = 18, /*!<* I2C2M */
7311 MDIO_TX_CHANn = 19, /*!<* MDIO_TX */
7312 MDIO_RX_CHANn = 20, /*!<* MDIO_RX */
7313 FLASH_KHWR_CHANn = 21, /*!<* FLASH_KHWR */
7314 ADC_RD_CHANn = 22, /*!<* ADC_RD */
7315 sys_Trig0_CHANn = 27, /*!<* sys_Trig0 */
7316 sys_Trig1_CHANn = 28, /*!<* sys_Trig1 */
7317 sys_SW0_CHANn = 29, /*!<* sys_SW0 */
7318 sys_SW1_CHANn = 30, /*!<* sys_SW1 */
7319} DMA_CHANn_TypeDef; /* typedef name for fixed DMA channel assignment */
7320
7321
7322#ifdef __cplusplus
7323}
7324#endif
7325
7326#endif // __ADUCM410_H__
7327
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 20:19:18 +0100