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-rw-r--r--lib/chibios/os/common/ports/e200/chcore.c54
-rw-r--r--lib/chibios/os/common/ports/e200/chcore.h722
-rw-r--r--lib/chibios/os/common/ports/e200/compilers/CW/chcoreasm.s119
-rw-r--r--lib/chibios/os/common/ports/e200/compilers/CW/chtypes.h97
-rw-r--r--lib/chibios/os/common/ports/e200/compilers/CW/ivor.s205
-rw-r--r--lib/chibios/os/common/ports/e200/compilers/GCC/chcoreasm.S113
-rw-r--r--lib/chibios/os/common/ports/e200/compilers/GCC/chtypes.h97
-rw-r--r--lib/chibios/os/common/ports/e200/compilers/GCC/ivor.S263
-rw-r--r--lib/chibios/os/common/ports/e200/compilers/GCC/mk/port.mk13
-rw-r--r--lib/chibios/os/common/ports/e200/compilers/GHS/chcoreasm.s107
-rw-r--r--lib/chibios/os/common/ports/e200/compilers/GHS/chtypes.h97
-rw-r--r--lib/chibios/os/common/ports/e200/compilers/GHS/ivor.s265
-rw-r--r--lib/chibios/os/common/ports/e200/compilers/GHS/mk/port.mk13
13 files changed, 2165 insertions, 0 deletions
diff --git a/lib/chibios/os/common/ports/e200/chcore.c b/lib/chibios/os/common/ports/e200/chcore.c
new file mode 100644
index 000000000..2f2860015
--- /dev/null
+++ b/lib/chibios/os/common/ports/e200/chcore.c
@@ -0,0 +1,54 @@
1/*
2 ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,2011,2012,2013,2014,
3 2015,2016,2017,2018,2019,2020,2021 Giovanni Di Sirio.
4
5 This file is part of ChibiOS.
6
7 ChibiOS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation version 3 of the License.
10
11 ChibiOS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
18*/
19
20/**
21 * @file e200/chcore.c
22 * @brief Power e200 port code.
23 *
24 * @addtogroup PPC_CORE
25 * @{
26 */
27
28#include "ch.h"
29
30/*===========================================================================*/
31/* Module local definitions. */
32/*===========================================================================*/
33
34/*===========================================================================*/
35/* Module exported variables. */
36/*===========================================================================*/
37
38/*===========================================================================*/
39/* Module local types. */
40/*===========================================================================*/
41
42/*===========================================================================*/
43/* Module local variables. */
44/*===========================================================================*/
45
46/*===========================================================================*/
47/* Module local functions. */
48/*===========================================================================*/
49
50/*===========================================================================*/
51/* Module exported functions. */
52/*===========================================================================*/
53
54/** @} */
diff --git a/lib/chibios/os/common/ports/e200/chcore.h b/lib/chibios/os/common/ports/e200/chcore.h
new file mode 100644
index 000000000..a1f0bd79a
--- /dev/null
+++ b/lib/chibios/os/common/ports/e200/chcore.h
@@ -0,0 +1,722 @@
1/*
2 ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,2011,2012,2013,2014,
3 2015,2016,2017,2018,2019,2020,2021 Giovanni Di Sirio.
4
5 This file is part of ChibiOS.
6
7 ChibiOS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation version 3 of the License.
10
11 ChibiOS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
18*/
19
20/**
21 * @file PPC/chcore.h
22 * @brief Power e200 port macros and structures.
23 *
24 * @addtogroup PPC_CORE
25 * @{
26 */
27
28#ifndef CHCORE_H
29#define CHCORE_H
30
31#if defined(__ghs__) && !defined(_FROM_ASM_)
32#include <ppc_ghs.h>
33#endif
34
35#include "intc.h"
36
37/*===========================================================================*/
38/* Module constants. */
39/*===========================================================================*/
40
41/**
42 * @name Port Capabilities and Constants
43 * @{
44 */
45/**
46 * @brief This port supports a realtime counter.
47 */
48#define PORT_SUPPORTS_RT FALSE
49
50/**
51 * @brief Natural alignment constant.
52 * @note It is the minimum alignment for pointer-size variables.
53 */
54#define PORT_NATURAL_ALIGN sizeof (void *)
55
56/**
57 * @brief Stack alignment constant.
58 * @note It is the alignment required for the stack pointer.
59 */
60#define PORT_STACK_ALIGN sizeof (stkalign_t)
61
62/**
63 * @brief Working Areas alignment constant.
64 * @note It is the alignment to be enforced for thread working areas.
65 */
66#define PORT_WORKING_AREA_ALIGN sizeof (stkalign_t)
67/** @} */
68
69/**
70 * @name Architecture and Compiler
71 * @{
72 */
73/**
74 * @brief Macro defining an PPC architecture.
75 */
76#define PORT_ARCHITECTURE_PPC
77
78/**
79 * @brief Macro defining the specific PPC architecture.
80 */
81#define PORT_ARCHITECTURE_PPC_E200
82
83/**
84 * @brief Name of the implemented architecture.
85 */
86#define PORT_ARCHITECTURE_NAME "Power Architecture e200"
87
88/**
89 * @brief Compiler name and version.
90 */
91#if (defined(__GNUC__) && !defined(__ghs__)) || defined(__DOXYGEN__)
92#define PORT_COMPILER_NAME "GCC " __VERSION__
93
94#elif defined(__MWERKS__)
95#define PORT_COMPILER_NAME "CW"
96
97#elif defined(__ghs__)
98#define PORT_COMPILER_NAME "GHS"
99
100#else
101#error "unsupported compiler"
102#endif
103/** @} */
104
105/**
106 * @name E200 core variants
107 * @{
108 */
109#define PPC_VARIANT_e200z0 200
110#define PPC_VARIANT_e200z2 202
111#define PPC_VARIANT_e200z3 203
112#define PPC_VARIANT_e200z4 204
113/** @} */
114
115/* Inclusion of the PPC implementation specific parameters.*/
116#include "ppcparams.h"
117#include "vectors.h"
118
119/*===========================================================================*/
120/* Module pre-compile time settings. */
121/*===========================================================================*/
122
123/**
124 * @brief Stack size for the system idle thread.
125 * @details This size depends on the idle thread implementation, usually
126 * the idle thread should take no more space than those reserved
127 * by @p PORT_INT_REQUIRED_STACK.
128 * @note In this port it is set to 32 because the idle thread does have
129 * a stack frame when compiling without optimizations. You may
130 * reduce this value to zero when compiling with optimizations.
131 */
132#if !defined(PORT_IDLE_THREAD_STACK_SIZE) || defined(__DOXYGEN__)
133#define PORT_IDLE_THREAD_STACK_SIZE 32
134#endif
135
136/**
137 * @brief Per-thread stack overhead for interrupts servicing.
138 * @details This constant is used in the calculation of the correct working
139 * area size.
140 * @note In this port this value is conservatively is set to 256 because
141 * there is no separate interrupts stack (yet).
142 */
143#if !defined(PORT_INT_REQUIRED_STACK) || defined(__DOXYGEN__)
144#define PORT_INT_REQUIRED_STACK 256
145#endif
146
147/**
148 * @brief Enables an alternative timer implementation.
149 * @details Usually the port uses a timer interface defined in the file
150 * @p chcore_timer.h, if this option is enabled then the file
151 * @p chcore_timer_alt.h is included instead.
152 */
153#if !defined(PORT_USE_ALT_TIMER) || defined(__DOXYGEN__)
154#define PORT_USE_ALT_TIMER FALSE
155#endif
156
157/**
158 * @brief Use VLE instruction set.
159 * @note This parameter is usually set in the Makefile.
160 */
161#if !defined(PPC_USE_VLE) || defined(__DOXYGEN__)
162#define PPC_USE_VLE TRUE
163#endif
164
165/**
166 * @brief Enables the use of the @p WFI instruction.
167 */
168#if !defined(PPC_ENABLE_WFI_IDLE) || defined(__DOXYGEN__)
169#define PPC_ENABLE_WFI_IDLE FALSE
170#endif
171
172/*===========================================================================*/
173/* Derived constants and error checks. */
174/*===========================================================================*/
175
176#if PPC_USE_VLE && !PPC_SUPPORTS_VLE
177#error "the selected MCU does not support VLE instructions set"
178#endif
179
180#if !PPC_USE_VLE && !PPC_SUPPORTS_BOOKE
181#error "the selected MCU does not support BookE instructions set"
182#endif
183
184/**
185 * @brief Name of the architecture variant.
186 */
187#if (PPC_VARIANT == PPC_VARIANT_e200z0) || defined(__DOXYGEN__)
188
189#if !defined(CH_CUSTOMER_LIC_PORT_E200Z0)
190#error "CH_CUSTOMER_LIC_PORT_E200Z0 not defined"
191#endif
192
193#if CH_CUSTOMER_LIC_PORT_E200Z0 == FALSE
194#error "ChibiOS Power e200z0 port not licensed"
195#endif
196
197#define PORT_CORE_VARIANT_NAME "e200z0"
198
199#elif PPC_VARIANT == PPC_VARIANT_e200z2
200
201#if !defined(CH_CUSTOMER_LIC_PORT_E200Z2)
202#error "CH_CUSTOMER_LIC_PORT_E200Z2 not defined"
203#endif
204
205#if CH_CUSTOMER_LIC_PORT_E200Z2 == FALSE
206#error "ChibiOS Power e200z2 port not licensed"
207#endif
208
209#define PORT_CORE_VARIANT_NAME "e200z2"
210
211#elif PPC_VARIANT == PPC_VARIANT_e200z3
212
213#if !defined(CH_CUSTOMER_LIC_PORT_E200Z3)
214#error "CH_CUSTOMER_LIC_PORT_E200Z3 not defined"
215#endif
216
217#if CH_CUSTOMER_LIC_PORT_E200Z3 == FALSE
218#error "ChibiOS Power e200z3 port not licensed"
219#endif
220
221#define PORT_CORE_VARIANT_NAME "e200z3"
222
223#elif PPC_VARIANT == PPC_VARIANT_e200z4
224
225#if !defined(CH_CUSTOMER_LIC_PORT_E200Z4)
226#error "CH_CUSTOMER_LIC_PORT_E200Z4 not defined"
227#endif
228
229#if CH_CUSTOMER_LIC_PORT_E200Z4 == FALSE
230#error "ChibiOS Power e200z4 port not licensed"
231#endif
232
233#define PORT_CORE_VARIANT_NAME "e200z4"
234
235#else
236#error "unknown or unsupported PowerPC variant specified"
237#endif
238
239/**
240 * @brief Port-specific information string.
241 */
242#if PPC_USE_VLE
243#define PORT_INFO "VLE mode"
244#else
245#define PORT_INFO "Book-E mode"
246#endif
247
248/*===========================================================================*/
249/* Module data structures and types. */
250/*===========================================================================*/
251
252/* The following code is not processed when the file is included from an
253 asm module.*/
254#if !defined(_FROM_ASM_)
255
256/**
257 * @brief Type of stack and memory alignment enforcement.
258 * @note In this architecture the stack alignment is enforced to 64 bits.
259 */
260typedef uint64_t stkalign_t;
261
262/**
263 * @brief Generic PPC register.
264 */
265typedef void *regppc_t;
266
267/**
268 * @brief Mandatory part of a stack frame.
269 */
270struct port_eabi_frame {
271 uint32_t slink; /**< Stack back link. */
272 uint32_t shole; /**< Stack hole for LR storage. */
273};
274
275/**
276 * @brief Interrupt saved context.
277 * @details This structure represents the stack frame saved during a
278 * preemption-capable interrupt handler.
279 * @note R2 and R13 are not saved because those are assumed to be immutable
280 * during the system life cycle.
281 */
282struct port_extctx {
283 struct port_eabi_frame frame;
284 /* Start of the e_stmvsrrw frame (offset 8).*/
285 regppc_t pc;
286 regppc_t msr;
287 /* Start of the e_stmvsprw frame (offset 16).*/
288 regppc_t cr;
289 regppc_t lr;
290 regppc_t ctr;
291 regppc_t xer;
292 /* Start of the e_stmvgprw frame (offset 32).*/
293 regppc_t r0;
294 regppc_t r3;
295 regppc_t r4;
296 regppc_t r5;
297 regppc_t r6;
298 regppc_t r7;
299 regppc_t r8;
300 regppc_t r9;
301 regppc_t r10;
302 regppc_t r11;
303 regppc_t r12;
304 regppc_t padding;
305};
306
307/**
308 * @brief System saved context.
309 * @details This structure represents the inner stack frame during a context
310 * switching.
311 * @note R2 and R13 are not saved because those are assumed to be immutable
312 * during the system life cycle.
313 * @note LR is stored in the caller context so it is not present in this
314 * structure.
315 */
316struct port_intctx {
317 regppc_t cr; /* Part of it is not volatile... */
318 regppc_t r14;
319 regppc_t r15;
320 regppc_t r16;
321 regppc_t r17;
322 regppc_t r18;
323 regppc_t r19;
324 regppc_t r20;
325 regppc_t r21;
326 regppc_t r22;
327 regppc_t r23;
328 regppc_t r24;
329 regppc_t r25;
330 regppc_t r26;
331 regppc_t r27;
332 regppc_t r28;
333 regppc_t r29;
334 regppc_t r30;
335 regppc_t r31;
336 regppc_t padding;
337};
338
339/**
340 * @brief Platform dependent part of the @p thread_t structure.
341 * @details This structure usually contains just the saved stack pointer
342 * defined as a pointer to a @p port_intctx structure.
343 */
344struct port_context {
345 struct port_intctx *sp;
346};
347
348#endif /* !defined(_FROM_ASM_) */
349
350/*===========================================================================*/
351/* Module macros. */
352/*===========================================================================*/
353
354/**
355 * @brief Platform dependent part of the @p chThdCreateI() API.
356 * @details This code usually setup the context switching frame represented
357 * by an @p port_intctx structure.
358 */
359#define PORT_SETUP_CONTEXT(tp, wbase, wtop, pf, arg) { \
360 uint8_t *sp = (uint8_t *)(wtop) - sizeof(struct port_eabi_frame); \
361 ((struct port_eabi_frame *)sp)->slink = 0; \
362 ((struct port_eabi_frame *)sp)->shole = (uint32_t)_port_thread_start; \
363 (tp)->ctx.sp = (struct port_intctx *)(sp - sizeof(struct port_intctx)); \
364 (tp)->ctx.sp->r31 = (regppc_t)(arg); \
365 (tp)->ctx.sp->r30 = (regppc_t)(pf); \
366}
367
368/**
369 * @brief Computes the thread working area global size.
370 * @note There is no need to perform alignments in this macro.
371 */
372#define PORT_WA_SIZE(n) (sizeof(struct port_intctx) + \
373 sizeof(struct port_extctx) + \
374 ((size_t)(n)) + ((size_t)(PORT_INT_REQUIRED_STACK)))
375
376/**
377 * @brief Static working area allocation.
378 * @details This macro is used to allocate a static thread working area
379 * aligned as both position and size.
380 *
381 * @param[in] s the name to be assigned to the stack array
382 * @param[in] n the stack size to be assigned to the thread
383 */
384#define PORT_WORKING_AREA(s, n) \
385 stkalign_t s[THD_WORKING_AREA_SIZE(n) / sizeof (stkalign_t)]
386
387/**
388 * @brief IRQ prologue code.
389 * @details This macro must be inserted at the start of all IRQ handlers
390 * enabled to invoke system APIs.
391 */
392#define PORT_IRQ_PROLOGUE()
393
394/**
395 * @brief IRQ epilogue code.
396 * @details This macro must be inserted at the end of all IRQ handlers
397 * enabled to invoke system APIs.
398 */
399#define PORT_IRQ_EPILOGUE()
400
401/**
402 * @brief IRQ handler function declaration.
403 * @note @p id can be a function name or a vector number depending on the
404 * port implementation.
405 */
406#ifdef __cplusplus
407#define PORT_IRQ_HANDLER(id) extern "C" void id(void)
408#else
409#define PORT_IRQ_HANDLER(id) void id(void)
410#endif
411
412/**
413 * @brief Fast IRQ handler function declaration.
414 * @note @p id can be a function name or a vector number depending on the
415 * port implementation.
416 */
417#ifdef __cplusplus
418#define PORT_FAST_IRQ_HANDLER(id) extern "C" void id(void)
419#else
420#define PORT_FAST_IRQ_HANDLER(id) void id(void)
421#endif
422
423/**
424 * @brief Priority level verification macro.
425 */
426#define PORT_IRQ_IS_VALID_PRIORITY(n) \
427 (((n) >= 0U) && ((n) < INTC_PRIORITY_LEVELS))
428
429/**
430 * @brief Priority level verification macro.
431 */
432#define PORT_IRQ_IS_VALID_KERNEL_PRIORITY(n) \
433 (((n) >= 0U) && ((n) < INTC_PRIORITY_LEVELS))
434
435/**
436 * @brief Performs a context switch between two threads.
437 * @details This is the most critical code in any port, this function
438 * is responsible for the context switch between 2 threads.
439 * @note The implementation of this code affects <b>directly</b> the context
440 * switch performance so optimize here as much as you can.
441 *
442 * @param[in] ntp the thread to be switched in
443 * @param[in] otp the thread to be switched out
444 */
445#if !CH_DBG_ENABLE_STACK_CHECK || defined(__DOXYGEN__)
446#define port_switch(ntp, otp) _port_switch(ntp, otp)
447#else
448#define port_switch(ntp, otp) { \
449 register struct port_intctx *sp asm ("%r1"); \
450 if ((stkalign_t *)(sp - 1) < otp->wabase) \
451 chSysHalt("stack overflow"); \
452 _port_switch(ntp, otp); \
453}
454#endif
455
456/**
457 * @brief Writes to a special register.
458 *
459 * @param[in] spr special register number
460 * @param[in] val value to be written, must be an automatic variable
461 */
462#if !defined(__ghs__) || defined(__DOXYGEN__)
463#define port_write_spr(spr, val) \
464 asm volatile ("mtspr %[p0], %[p1]" : : [p0] "n" (spr), [p1] "r" (val))
465#else
466#define port_write_spr(spr, val) \
467 __MTSPR(spr, val);
468#endif
469
470/**
471 * @brief Reads a special register.
472 *
473 * @param[in] spr special register number
474 * @param[in] val returned value, must be an automatic variable
475 */
476#if !defined(__ghs__) || defined(__DOXYGEN__)
477#define port_read_spr(spr, val) \
478 asm volatile ("mfspr %[p0], %[p1]" : [p0] "=r" (val) : [p1] "n" (spr))
479#else
480#define port_read_spr(spr, val) \
481 val = __MFSPR(spr)
482#endif
483
484/*===========================================================================*/
485/* External declarations. */
486/*===========================================================================*/
487
488/* The following code is not processed when the file is included from an
489 asm module.*/
490#if !defined(_FROM_ASM_)
491
492#ifdef __cplusplus
493extern "C" {
494#endif
495 void _port_switch(thread_t *ntp, thread_t *otp);
496 void _port_thread_start(void);
497#ifdef __cplusplus
498}
499#endif
500
501#endif /* !defined(_FROM_ASM_) */
502
503/*===========================================================================*/
504/* Module inline functions. */
505/*===========================================================================*/
506
507/* The following code is not processed when the file is included from an
508 asm module.*/
509#if !defined(_FROM_ASM_)
510
511extern void _IVOR4(void);
512extern void _IVOR10(void);
513
514/**
515 * @brief Kernel port layer initialization.
516 * @details IVOR4 and IVOR10 initialization.
517 */
518static inline void port_init(void) {
519 uint32_t n;
520 unsigned i;
521
522 /* Initializing the SPRG0 register to zero, it is required for interrupts
523 handling.*/
524 n = 0;
525 port_write_spr(272, n);
526
527#if PPC_SUPPORTS_IVORS
528 {
529 /* The CPU supports IVOR registers, the kernel requires IVOR4 and IVOR10
530 and the initialization is performed here.*/
531 port_write_spr(404, (uint32_t)_IVOR4);
532
533#if PPC_SUPPORTS_DECREMENTER
534 port_write_spr(410, (uint32_t)_IVOR10);
535#endif
536 }
537#endif
538
539 /* INTC initialization, software vector mode, 4 bytes vectors, starting
540 at priority 0.*/
541 INTC_BCR = 0;
542 for (i = 0; i < PPC_CORE_NUMBER; i++) {
543 INTC_CPR(i) = 0;
544 INTC_IACKR(i) = (uint32_t)_vectors;
545 }
546}
547
548/**
549 * @brief Returns a word encoding the current interrupts status.
550 *
551 * @return The interrupts status.
552 */
553static inline syssts_t port_get_irq_status(void) {
554 uint32_t sts;
555
556#if defined(__ghs__)
557 sts = __GETSR();
558#else
559 asm volatile ("mfmsr %[p0]" : [p0] "=r" (sts) :);
560#endif
561
562 return sts;
563}
564
565/**
566 * @brief Checks the interrupt status.
567 *
568 * @param[in] sts the interrupt status word
569 *
570 * @return The interrupt status.
571 * @retval false the word specified a disabled interrupts status.
572 * @retval true the word specified an enabled interrupts status.
573 */
574static inline bool port_irq_enabled(syssts_t sts) {
575
576 return (bool)((sts & (1 << 15)) != 0);
577}
578
579/**
580 * @brief Determines the current execution context.
581 *
582 * @return The execution context.
583 * @retval false not running in ISR mode.
584 * @retval true running in ISR mode.
585 */
586static inline bool port_is_isr_context(void) {
587 uint32_t sprg0;
588
589 /* The SPRG0 register is increased before entering interrupt handlers and
590 decreased at the end.*/
591 port_read_spr(272, sprg0);
592 return (bool)(sprg0 > 0);
593}
594
595/**
596 * @brief Kernel-lock action.
597 * @note Implemented as global interrupt disable.
598 */
599static inline void port_lock(void) {
600
601#if defined(__ghs__)
602 __DI();
603#else
604 asm volatile ("wrteei 0" : : : "memory");
605#endif
606}
607
608/**
609 * @brief Kernel-unlock action.
610 * @note Implemented as global interrupt enable.
611 */
612static inline void port_unlock(void) {
613
614#if defined(__ghs__)
615 __EI();
616#else
617 asm volatile("wrteei 1" : : : "memory");
618#endif
619}
620
621/**
622 * @brief Kernel-lock action from an interrupt handler.
623 * @note Implementation not needed.
624 */
625static inline void port_lock_from_isr(void) {
626
627}
628
629/**
630 * @brief Kernel-unlock action from an interrupt handler.
631 * @note Implementation not needed.
632 */
633static inline void port_unlock_from_isr(void) {
634
635}
636
637/**
638 * @brief Disables all the interrupt sources.
639 * @note Implemented as global interrupt disable.
640 */
641static inline void port_disable(void) {
642
643#if defined(__ghs__)
644 __DI();
645#else
646 asm volatile ("wrteei 0" : : : "memory");
647#endif
648}
649
650/**
651 * @brief Disables the interrupt sources below kernel-level priority.
652 * @note Same as @p port_disable() in this port, there is no difference
653 * between the two states.
654 */
655static inline void port_suspend(void) {
656
657#if defined(__ghs__)
658 __DI();
659#else
660 asm volatile ("wrteei 0" : : : "memory");
661#endif
662}
663
664/**
665 * @brief Enables all the interrupt sources.
666 * @note Implemented as global interrupt enable.
667 */
668static inline void port_enable(void) {
669
670#if defined(__ghs__)
671 __EI();
672#else
673 asm volatile ("wrteei 1" : : : "memory");
674#endif
675}
676
677/**
678 * @brief Enters an architecture-dependent IRQ-waiting mode.
679 * @details The function is meant to return when an interrupt becomes pending.
680 * The simplest implementation is an empty function or macro but this
681 * would not take advantage of architecture-specific power saving
682 * modes.
683 * @note Implemented as an inlined @p wait instruction.
684 */
685static inline void port_wait_for_interrupt(void) {
686
687#if PPC_ENABLE_WFI_IDLE
688 asm volatile ("wait" : : : "memory");
689#endif
690}
691
692/**
693 * @brief Returns the current value of the realtime counter.
694 *
695 * @return The realtime counter value.
696 */
697static inline rtcnt_t port_rt_get_counter_value(void) {
698
699 return 0;
700}
701
702#endif /* !defined(_FROM_ASM_) */
703
704/*===========================================================================*/
705/* Module late inclusions. */
706/*===========================================================================*/
707
708#if !defined(_FROM_ASM_)
709
710#if CH_CFG_ST_TIMEDELTA > 0
711#if !PORT_USE_ALT_TIMER
712#include "chcore_timer.h"
713#else /* PORT_USE_ALT_TIMER */
714#include "chcore_timer_alt.h"
715#endif /* PORT_USE_ALT_TIMER */
716#endif /* CH_CFG_ST_TIMEDELTA > 0 */
717
718#endif /* !defined(_FROM_ASM_) */
719
720#endif /* CHCORE_H */
721
722/** @} */
diff --git a/lib/chibios/os/common/ports/e200/compilers/CW/chcoreasm.s b/lib/chibios/os/common/ports/e200/compilers/CW/chcoreasm.s
new file mode 100644
index 000000000..058a0cb87
--- /dev/null
+++ b/lib/chibios/os/common/ports/e200/compilers/CW/chcoreasm.s
@@ -0,0 +1,119 @@
1/*
2 ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,2011,2012,2013,2014,
3 2015,2016,2017,2018,2019,2020,2021 Giovanni Di Sirio.
4
5 This file is part of ChibiOS.
6
7 ChibiOS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation version 3 of the License.
10
11 ChibiOS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
18*/
19
20/**
21 * @file e200/compilers/GCC/chcoreasm.s
22 * @brief Power Architecture port low level code.
23 *
24 * @addtogroup PPC_GCC_CORE
25 * @{
26 */
27
28/*===========================================================================*/
29/* Module constants. */
30/*===========================================================================*/
31
32#if !defined(FALSE) || defined(__DOXYGEN__)
33#define FALSE 0
34#endif
35
36#if !defined(TRUE) || defined(__DOXYGEN__)
37#define TRUE 1
38#endif
39
40/*===========================================================================*/
41/* Code section. */
42/*===========================================================================*/
43
44/*
45 * Imports the PPC configuration headers.
46 */
47#define _FROM_ASM_
48#include "chlicense.h"
49#include "chconf.h"
50#include "chcore.h"
51
52#if !defined(__DOXYGEN__)
53
54/*
55 * RTOS-specific context offset.
56 */
57#if defined(_CHIBIOS_RT_CONF_)
58#define CONTEXT_OFFSET 12
59#elif defined(_CHIBIOS_NIL_CONF_)
60#define CONTEXT_OFFSET 0
61#else
62#error "invalid chconf.h"
63#endif
64
65#if defined(_CHIBIOS_RT_CONF_)
66 .extern chThdExit
67#endif
68
69#if PPC_USE_VLE == TRUE
70 .section .text_vle, 16
71
72 .align 2
73 .globl _port_switch
74 .type _port_switch, @function
75_port_switch:
76 e_subi r1, r1, 80
77 se_mflr r0
78 e_stw r0, 84(r1)
79 mfcr r0
80 se_stw r0, 0(r1)
81 e_stmw r14, 4(r1)
82
83 se_stw r1, 12(r4)
84 se_lwz r1, 12(r3)
85
86 e_lmw r14, 4(r1)
87 se_lwz r0, 0(r1)
88 mtcr r0
89 e_lwz r0, 84(r1)
90 se_mtlr r0
91 e_addi r1, r1, 80
92 se_blr
93
94 .align 2
95 .globl _port_thread_start
96 .type _port_thread_start, @function
97_port_thread_start:
98#if CH_DBG_SYSTEM_STATE_CHECK
99 bl _dbg_check_unlock
100#endif
101#if CH_DBG_STATISTICS
102 bl _stats_stop_measure_crit_thd
103#endif
104 wrteei 1
105 mr r3, r31
106 mtctr r30
107 se_bctrl
108 se_li r0, 0
109 e_bl chThdExit
110
111#else /* PPC_USE_VLE == FALSE */
112
113#error "non-VLE mode not yet implemented"
114
115#endif /* PPC_USE_VLE == FALSE */
116
117#endif /* !defined(__DOXYGEN__) */
118
119/** @} */
diff --git a/lib/chibios/os/common/ports/e200/compilers/CW/chtypes.h b/lib/chibios/os/common/ports/e200/compilers/CW/chtypes.h
new file mode 100644
index 000000000..656b90557
--- /dev/null
+++ b/lib/chibios/os/common/ports/e200/compilers/CW/chtypes.h
@@ -0,0 +1,97 @@
1/*
2 ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,2011,2012,2013,2014,
3 2015,2016,2017,2018,2019,2020,2021 Giovanni Di Sirio.
4
5 This file is part of ChibiOS.
6
7 ChibiOS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation version 3 of the License.
10
11 ChibiOS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
18*/
19
20/**
21 * @file e200/compilers/CW/chtypes.h
22 * @brief Power e200 port system types.
23 *
24 * @addtogroup PPC_CW_CORE
25 * @{
26 */
27
28#ifndef CHTYPES_H
29#define CHTYPES_H
30
31#include <stddef.h>
32#include <stdint.h>
33#include <stdbool.h>
34
35/**
36 * @name Kernel types
37 * @{
38 */
39typedef uint32_t rtcnt_t; /**< Realtime counter. */
40typedef uint64_t rttime_t; /**< Realtime accumulator. */
41typedef uint32_t syssts_t; /**< System status word. */
42typedef uint8_t tmode_t; /**< Thread flags. */
43typedef uint8_t tstate_t; /**< Thread state. */
44typedef uint8_t trefs_t; /**< Thread references counter. */
45typedef uint8_t tslices_t; /**< Thread time slices counter.*/
46typedef uint32_t tprio_t; /**< Thread priority. */
47typedef int32_t msg_t; /**< Inter-thread message. */
48typedef int32_t eventid_t; /**< Numeric event identifier. */
49typedef uint32_t eventmask_t; /**< Mask of event identifiers. */
50typedef uint32_t eventflags_t; /**< Mask of event flags. */
51typedef int32_t cnt_t; /**< Generic signed counter. */
52typedef uint32_t ucnt_t; /**< Generic unsigned counter. */
53/** @} */
54
55/**
56 * @brief ROM constant modifier.
57 * @note It is set to use the "const" keyword in this port.
58 */
59#define ROMCONST const
60
61/**
62 * @brief Makes functions not inlineable.
63 * @note If the compiler does not support such attribute then some
64 * time-dependent services could be degraded.
65 */
66#define NOINLINE __attribute__((noinline))
67
68/**
69 * @brief Optimized thread function declaration macro.
70 */
71#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg)
72
73/**
74 * @brief Packed variable specifier.
75 */
76#define PACKED_VAR __attribute__((packed))
77
78/**
79 * @brief Memory alignment enforcement for variables.
80 */
81#define ALIGNED_VAR(n) __attribute__((aligned(n)))
82
83/**
84 * @brief Size of a pointer.
85 * @note To be used where the sizeof operator cannot be used, preprocessor
86 * expressions for example.
87 */
88#define SIZEOF_PTR 4
89
90/**
91 * @brief True if alignment is low-high in current architecture.
92 */
93#define REVERSE_ORDER 0
94
95#endif /* CHTYPES_H */
96
97/** @} */
diff --git a/lib/chibios/os/common/ports/e200/compilers/CW/ivor.s b/lib/chibios/os/common/ports/e200/compilers/CW/ivor.s
new file mode 100644
index 000000000..7c546f28f
--- /dev/null
+++ b/lib/chibios/os/common/ports/e200/compilers/CW/ivor.s
@@ -0,0 +1,205 @@
1/*
2 ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,2011,2012,2013,2014,
3 2015,2016,2017,2018,2019,2020,2021 Giovanni Di Sirio.
4
5 This file is part of ChibiOS.
6
7 ChibiOS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation version 3 of the License.
10
11 ChibiOS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
18*/
19
20/**
21 * @file ivor.s
22 * @brief Kernel ISRs.
23 *
24 * @addtogroup PPC_CORE
25 * @{
26 */
27
28/*===========================================================================*/
29/* Module constants. */
30/*===========================================================================*/
31
32#if !defined(FALSE) || defined(__DOXYGEN__)
33#define FALSE 0
34#endif
35
36#if !defined(TRUE) || defined(__DOXYGEN__)
37#define TRUE 1
38#endif
39
40/*===========================================================================*/
41/* Code section. */
42/*===========================================================================*/
43
44/*
45 * Imports the PPC configuration headers.
46 */
47#define _FROM_ASM_
48#include "chlicense.h"
49#include "chconf.h"
50#include "chcore.h"
51
52#if !defined(__DOXYGEN__)
53
54 .extern _stats_start_measure_crit_thd
55 .extern _stats_stop_measure_crit_thd
56 .extern _dbg_check_lock
57 .extern _dbg_check_unlock
58 .extern chSchIsPreemptionRequired
59 .extern chSchDoReschedule
60 .extern chSysTimerHandlerI
61
62 .section .handlers, text_vle
63
64#if PPC_USE_VLE == TRUE
65
66#if PPC_SUPPORTS_DECREMENTER
67 /*
68 * _IVOR10 handler (Book-E decrementer).
69 */
70 .align 16
71 .globl _IVOR10
72 .type _IVOR10, @function
73_IVOR10:
74 /* Saving the external context (port_extctx structure).*/
75 e_stwu r1, -80(r1)
76 e_stmvsrrw 8(r1) /* Saves PC, MSR. */
77 e_stmvsprw 16(r1) /* Saves CR, LR, CTR, XER. */
78 e_stmvgprw 32(r1) /* Saves GPR0, GPR3...GPR12. */
79
80 /* Increasing the SPGR0 register.*/
81 mfspr r0, 272
82 se_addi r0, 1
83 mtspr 272, r0
84
85 /* Reset DIE bit in TSR register.*/
86 e_lis r3, 0x0800 /* DIS bit mask. */
87 mtspr 336, r3 /* TSR register. */
88
89 /* Restoring pre-IRQ MSR register value.*/
90 mfSRR1 r0
91#if !PPC_USE_IRQ_PREEMPTION
92 /* No preemption, keeping EE disabled.*/
93 se_bclri r0, 16 /* EE = bit 16. */
94#endif
95 mtMSR r0
96
97#if CH_DBG_SYSTEM_STATE_CHECK
98 bl _dbg_check_enter_isr
99 bl _dbg_check_lock_from_isr
100#endif
101 /* System tick handler invocation.*/
102 e_bl chSysTimerHandlerI
103#if CH_DBG_SYSTEM_STATE_CHECK
104 bl _dbg_check_unlock_from_isr
105 bl _dbg_check_leave_isr
106#endif
107
108#if PPC_USE_IRQ_PREEMPTION
109 /* Prevents preemption again.*/
110 wrteei 0
111#endif
112
113 /* Jumps to the common IVOR epilogue code.*/
114 se_b _ivor_exit
115#endif /* PPC_SUPPORTS_DECREMENTER */
116
117 /*
118 * _IVOR4 handler (Book-E external interrupt).
119 */
120 .align 16
121 .globl _IVOR4
122 .type _IVOR4, @function
123_IVOR4:
124 /* Saving the external context (port_extctx structure).*/
125 e_stwu r1, -80(r1)
126 e_stmvsrrw 8(r1) /* Saves PC, MSR. */
127 e_stmvsprw 16(r1) /* Saves CR, LR, CTR, XER. */
128 e_stmvgprw 32(r1) /* Saves GPR0, GPR3...GPR12. */
129
130 /* Increasing the SPGR0 register.*/
131 mfspr r0, 272
132 se_addi r0, 1
133 mtspr 272, r0
134
135 /* Software vector address from the INTC register.*/
136 e_lis r3, INTC_IACKR_ADDR@h
137 e_or2i r3, INTC_IACKR_ADDR@l /* IACKR register address. */
138 se_lwz r3, 0(r3) /* IACKR register value. */
139 se_lwz r3, 0(r3)
140 mtCTR r3 /* Software handler address. */
141
142 /* Restoring pre-IRQ MSR register value.*/
143 mfSRR1 r0
144#if !PPC_USE_IRQ_PREEMPTION
145 /* No preemption, keeping EE disabled.*/
146 se_bclri r0, 16 /* EE = bit 16. */
147#endif
148 mtMSR r0
149
150 /* Exectes the software handler.*/
151 se_bctrl
152
153#if PPC_USE_IRQ_PREEMPTION
154 /* Prevents preemption again.*/
155 wrteei 0
156#endif
157
158 /* Informs the INTC that the interrupt has been served.*/
159 mbar 0
160 e_lis r3, INTC_EOIR_ADDR@h
161 e_or2i r3, INTC_EOIR_ADDR@l
162 se_stw r3, 0(r3) /* Writing any value should do. */
163
164 /* Common IVOR epilogue code, context restore.*/
165 .globl _ivor_exit
166_ivor_exit:
167 /* Decreasing the SPGR0 register.*/
168 mfspr r0, 272
169 se_subi r0, 1
170 mtspr 272, r0
171
172#if CH_DBG_STATISTICS
173 e_bl _stats_start_measure_crit_thd
174#endif
175#if CH_DBG_SYSTEM_STATE_CHECK
176 e_bl _dbg_check_lock
177#endif
178 e_bl chSchIsPreemptionRequired
179 e_cmpli cr0, r3, 0
180 se_beq .noresch
181 e_bl chSchDoReschedule
182.noresch:
183#if CH_DBG_SYSTEM_STATE_CHECK
184 e_bl _dbg_check_unlock
185#endif
186#if CH_DBG_STATISTICS
187 e_bl _stats_stop_measure_crit_thd
188#endif
189
190 /* Restoring the external context.*/
191 e_lmvgprw 32(r1) /* Restores GPR0, GPR3...GPR12. */
192 e_lmvsprw 16(r1) /* Restores CR, LR, CTR, XER. */
193 e_lmvsrrw 8(r1) /* Restores PC, MSR. */
194 e_addi r1, r1, 80 /* Back to the previous frame. */
195 se_rfi
196
197#else /* PPC_USE_VLE == FALSE */
198
199#error "non-VLE mode not yet implemented"
200
201#endif /* PPC_USE_VLE == FALSE */
202
203#endif /* !defined(__DOXYGEN__) */
204
205/** @} */
diff --git a/lib/chibios/os/common/ports/e200/compilers/GCC/chcoreasm.S b/lib/chibios/os/common/ports/e200/compilers/GCC/chcoreasm.S
new file mode 100644
index 000000000..008c09785
--- /dev/null
+++ b/lib/chibios/os/common/ports/e200/compilers/GCC/chcoreasm.S
@@ -0,0 +1,113 @@
1/*
2 ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,2011,2012,2013,2014,
3 2015,2016,2017,2018,2019,2020,2021 Giovanni Di Sirio.
4
5 This file is part of ChibiOS.
6
7 ChibiOS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation version 3 of the License.
10
11 ChibiOS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
18*/
19
20/**
21 * @file e200/compilers/GCC/chcoreasm.S
22 * @brief Power Architecture port low level code.
23 *
24 * @addtogroup PPC_GCC_CORE
25 * @{
26 */
27
28/*===========================================================================*/
29/* Module constants. */
30/*===========================================================================*/
31
32#if !defined(FALSE) || defined(__DOXYGEN__)
33#define FALSE 0
34#endif
35
36#if !defined(TRUE) || defined(__DOXYGEN__)
37#define TRUE 1
38#endif
39
40/*===========================================================================*/
41/* Code section. */
42/*===========================================================================*/
43
44#define _FROM_ASM_
45#include "chlicense.h"
46#include "chconf.h"
47#include "chcore.h"
48
49#if defined(__HIGHTEC__)
50#define e_subi subi
51#endif
52
53#if !defined(__DOXYGEN__)
54
55/*
56 * RTOS-specific context offset.
57 */
58#if defined(_CHIBIOS_RT_CONF_)
59#define CONTEXT_OFFSET 12
60#elif defined(_CHIBIOS_NIL_CONF_)
61#define CONTEXT_OFFSET 0
62#else
63#error "invalid chconf.h"
64#endif
65
66#if PPC_USE_VLE == TRUE
67 .section .text_vle, "ax"
68#else
69 .section .text, "ax"
70#endif
71
72 .align 2
73 .globl _port_switch
74 .type _port_switch, @function
75_port_switch:
76 e_subi sp, sp, 80
77 mflr r0
78 e_stw r0, 84(sp)
79 mfcr r0
80 se_stw r0, 0(sp)
81 e_stmw r14, 4(sp)
82
83 se_stw sp, CONTEXT_OFFSET(r4)
84 se_lwz sp, CONTEXT_OFFSET(r3)
85
86 e_lmw r14, 4(sp)
87 se_lwz r0, 0(sp)
88 mtcr r0
89 e_lwz r0, 84(sp)
90 mtlr r0
91 e_addi sp, sp, 80
92 se_blr
93
94 .align 2
95 .globl _port_thread_start
96 .type _port_thread_start, @function
97_port_thread_start:
98#if CH_DBG_SYSTEM_STATE_CHECK
99 e_bl _dbg_check_unlock
100#endif
101#if CH_DBG_STATISTICS
102 e_bl _stats_stop_measure_crit_thd
103#endif
104 wrteei 1
105 mr r3, r31
106 mtctr r30
107 se_bctrl
108 e_li r0, 0
109 e_bl chThdExit
110
111#endif /* !defined(__DOXYGEN__) */
112
113/** @} */
diff --git a/lib/chibios/os/common/ports/e200/compilers/GCC/chtypes.h b/lib/chibios/os/common/ports/e200/compilers/GCC/chtypes.h
new file mode 100644
index 000000000..d0f3d08c3
--- /dev/null
+++ b/lib/chibios/os/common/ports/e200/compilers/GCC/chtypes.h
@@ -0,0 +1,97 @@
1/*
2 ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,2011,2012,2013,2014,
3 2015,2016,2017,2018,2019,2020,2021 Giovanni Di Sirio.
4
5 This file is part of ChibiOS.
6
7 ChibiOS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation version 3 of the License.
10
11 ChibiOS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
18*/
19
20/**
21 * @file e200/compilers/GCC/chtypes.h
22 * @brief Power e200 port system types.
23 *
24 * @addtogroup PPC_GCC_CORE
25 * @{
26 */
27
28#ifndef CHTYPES_H
29#define CHTYPES_H
30
31#include <stddef.h>
32#include <stdint.h>
33#include <stdbool.h>
34
35/**
36 * @name Kernel types
37 * @{
38 */
39typedef uint32_t rtcnt_t; /**< Realtime counter. */
40typedef uint64_t rttime_t; /**< Realtime accumulator. */
41typedef uint32_t syssts_t; /**< System status word. */
42typedef uint8_t tmode_t; /**< Thread flags. */
43typedef uint8_t tstate_t; /**< Thread state. */
44typedef uint8_t trefs_t; /**< Thread references counter. */
45typedef uint8_t tslices_t; /**< Thread time slices counter.*/
46typedef uint32_t tprio_t; /**< Thread priority. */
47typedef int32_t msg_t; /**< Inter-thread message. */
48typedef int32_t eventid_t; /**< Numeric event identifier. */
49typedef uint32_t eventmask_t; /**< Mask of event identifiers. */
50typedef uint32_t eventflags_t; /**< Mask of event flags. */
51typedef int32_t cnt_t; /**< Generic signed counter. */
52typedef uint32_t ucnt_t; /**< Generic unsigned counter. */
53/** @} */
54
55/**
56 * @brief ROM constant modifier.
57 * @note It is set to use the "const" keyword in this port.
58 */
59#define ROMCONST const
60
61/**
62 * @brief Makes functions not inlineable.
63 * @note If the compiler does not support such attribute then some
64 * time-dependent services could be degraded.
65 */
66#define NOINLINE __attribute__((noinline))
67
68/**
69 * @brief Optimized thread function declaration macro.
70 */
71#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg)
72
73/**
74 * @brief Packed variable specifier.
75 */
76#define PACKED_VAR __attribute__((packed))
77
78/**
79 * @brief Memory alignment enforcement for variables.
80 */
81#define ALIGNED_VAR(n) __attribute__((aligned(n)))
82
83/**
84 * @brief Size of a pointer.
85 * @note To be used where the sizeof operator cannot be used, preprocessor
86 * expressions for example.
87 */
88#define SIZEOF_PTR 4
89
90/**
91 * @brief True if alignment is low-high in current architecture.
92 */
93#define REVERSE_ORDER 0
94
95#endif /* CHTYPES_H */
96
97/** @} */
diff --git a/lib/chibios/os/common/ports/e200/compilers/GCC/ivor.S b/lib/chibios/os/common/ports/e200/compilers/GCC/ivor.S
new file mode 100644
index 000000000..8014ea995
--- /dev/null
+++ b/lib/chibios/os/common/ports/e200/compilers/GCC/ivor.S
@@ -0,0 +1,263 @@
1/*
2 ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,2011,2012,2013,2014,
3 2015,2016,2017,2018,2019,2020,2021 Giovanni Di Sirio.
4
5 This file is part of ChibiOS.
6
7 ChibiOS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation version 3 of the License.
10
11 ChibiOS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
18*/
19
20/**
21 * @file GCC/ivor.S
22 * @brief Kernel ISRs.
23 *
24 * @addtogroup PPC_CORE
25 * @{
26 */
27
28#if !defined(FALSE) || defined(__DOXYGEN__)
29#define FALSE 0
30#endif
31
32#if !defined(TRUE) || defined(__DOXYGEN__)
33#define TRUE 1
34#endif
35
36/*
37 * Imports the PPC configuration headers.
38 */
39#define _FROM_ASM_
40#include "chlicense.h"
41#include "chconf.h"
42#include "chcore.h"
43
44#if defined(__HIGHTEC__)
45#define se_beq beq
46#endif
47
48#if !defined(__DOXYGEN__)
49
50 .section .handlers, "ax"
51
52#if PPC_SUPPORTS_DECREMENTER
53 /*
54 * _IVOR10 handler (Book-E decrementer).
55 */
56 .align 4
57 .globl _IVOR10
58 .type _IVOR10, @function
59_IVOR10:
60 /* Saving the external context (port_extctx structure).*/
61 e_stwu sp, -80(sp)
62#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
63 e_stmvsrrw 8(sp) /* Saves PC, MSR. */
64 e_stmvsprw 16(sp) /* Saves CR, LR, CTR, XER. */
65 e_stmvgprw 32(sp) /* Saves GPR0, GPR3...GPR12. */
66#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
67 se_stw r0, 32(sp) /* Saves GPR0. */
68 mfSRR0 r0
69 se_stw r0, 8(sp) /* Saves PC. */
70 mfSRR1 r0
71 se_stw r0, 12(sp) /* Saves MSR. */
72 mfCR r0
73 se_stw r0, 16(sp) /* Saves CR. */
74 mfLR r0
75 se_stw r0, 20(sp) /* Saves LR. */
76 mfCTR r0
77 se_stw r0, 24(sp) /* Saves CTR. */
78 mfXER r0
79 se_stw r0, 28(sp) /* Saves XER. */
80 se_stw r3, 36(sp) /* Saves GPR3...GPR12. */
81 se_stw r4, 40(sp)
82 se_stw r5, 44(sp)
83 se_stw r6, 48(sp)
84 se_stw r7, 52(sp)
85 e_stw r8, 56(sp)
86 e_stw r9, 60(sp)
87 e_stw r10, 64(sp)
88 e_stw r11, 68(sp)
89 e_stw r12, 72(sp)
90#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
91
92 /* Increasing the SPGR0 register.*/
93 mfspr r0, 272
94 se_addi r0, 1
95 mtspr 272, r0
96
97 /* Reset DIE bit in TSR register.*/
98 e_lis r3, 0x0800 /* DIS bit mask. */
99 mtspr 336, r3 /* TSR register. */
100
101 /* Restoring pre-IRQ MSR register value.*/
102 mfSRR1 r0
103#if !PPC_USE_IRQ_PREEMPTION
104 /* No preemption, keeping EE disabled.*/
105 se_bclri r0, 16 /* EE = bit 16. */
106#endif
107 mtMSR r0
108
109#if CH_DBG_SYSTEM_STATE_CHECK
110 e_bl _dbg_check_enter_isr
111 e_bl _dbg_check_lock_from_isr
112#endif
113 /* System tick handler invocation.*/
114 e_bl chSysTimerHandlerI
115#if CH_DBG_SYSTEM_STATE_CHECK
116 e_bl _dbg_check_unlock_from_isr
117 e_bl _dbg_check_leave_isr
118#endif
119
120#if PPC_USE_IRQ_PREEMPTION
121 /* Prevents preemption again.*/
122 wrteei 0
123#endif
124
125 /* Jumps to the common IVOR epilogue code.*/
126 e_b _ivor_exit
127#endif /* PPC_SUPPORTS_DECREMENTER */
128
129 /*
130 * _IVOR4 handler (Book-E external interrupt).
131 */
132 .align 4
133 .globl _IVOR4
134 .type _IVOR4, @function
135_IVOR4:
136 /* Saving the external context (port_extctx structure).*/
137 e_stwu sp, -80(sp)
138#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
139 e_stmvsrrw 8(sp) /* Saves PC, MSR. */
140 e_stmvsprw 16(sp) /* Saves CR, LR, CTR, XER. */
141 e_stmvgprw 32(sp) /* Saves GPR0, GPR3...GPR12. */
142#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
143 se_stw r0, 32(sp) /* Saves GPR0. */
144 mfSRR0 r0
145 se_stw r0, 8(sp) /* Saves PC. */
146 mfSRR1 r0
147 se_stw r0, 12(sp) /* Saves MSR. */
148 mfCR r0
149 se_stw r0, 16(sp) /* Saves CR. */
150 mfLR r0
151 se_stw r0, 20(sp) /* Saves LR. */
152 mfCTR r0
153 se_stw r0, 24(sp) /* Saves CTR. */
154 mfXER r0
155 se_stw r0, 28(sp) /* Saves XER. */
156 se_stw r3, 36(sp) /* Saves GPR3...GPR12. */
157 se_stw r4, 40(sp)
158 se_stw r5, 44(sp)
159 se_stw r6, 48(sp)
160 se_stw r7, 52(sp)
161 e_stw r8, 56(sp)
162 e_stw r9, 60(sp)
163 e_stw r10, 64(sp)
164 e_stw r11, 68(sp)
165 e_stw r12, 72(sp)
166#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
167
168 /* Increasing the SPGR0 register.*/
169 mfspr r0, 272
170 se_addi r0, 1
171 mtspr 272, r0
172
173 /* Software vector address from the INTC register.*/
174 e_lis r3, INTC_IACKR_ADDR@h
175 e_or2i r3, INTC_IACKR_ADDR@l /* IACKR register address. */
176 e_lwz r3, 0(r3) /* IACKR register value. */
177 e_lwz r3, 0(r3)
178 mtCTR r3 /* Software handler address. */
179
180 /* Restoring pre-IRQ MSR register value.*/
181 mfSRR1 r0
182#if !PPC_USE_IRQ_PREEMPTION
183 /* No preemption, keeping EE disabled.*/
184 se_bclri r0, 16 /* EE = bit 16. */
185#endif
186 mtMSR r0
187
188 /* Exectes the software handler.*/
189 se_bctrl
190
191#if PPC_USE_IRQ_PREEMPTION
192 /* Prevents preemption again.*/
193 wrteei 0
194#endif
195
196 /* Informs the INTC that the interrupt has been served.*/
197 mbar 0
198 e_lis r3, INTC_EOIR_ADDR@h
199 e_or2i r3, INTC_EOIR_ADDR@l
200 se_stw r3, 0(r3) /* Writing any value should do. */
201
202 /* Common IVOR epilogue code, context restore.*/
203 .globl _ivor_exit
204_ivor_exit:
205 /* Decreasing the SPGR0 register.*/
206 mfspr r0, 272
207 se_subi r0, 1
208 mtspr 272, r0
209
210#if CH_DBG_STATISTICS
211 e_bl _stats_start_measure_crit_thd
212#endif
213#if CH_DBG_SYSTEM_STATE_CHECK
214 e_bl _dbg_check_lock
215#endif
216 e_bl chSchIsPreemptionRequired
217 se_cmpi r3, 0
218 se_beq .noresch
219 e_bl chSchDoReschedule
220.noresch:
221#if CH_DBG_SYSTEM_STATE_CHECK
222 e_bl _dbg_check_unlock
223#endif
224#if CH_DBG_STATISTICS
225 e_bl _stats_stop_measure_crit_thd
226#endif
227
228 /* Restoring the external context.*/
229#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
230 e_lmvgprw 32(sp) /* Restores GPR0, GPR3...GPR12. */
231 e_lmvsprw 16(sp) /* Restores CR, LR, CTR, XER. */
232 e_lmvsrrw 8(sp) /* Restores PC, MSR. */
233#else /*!(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
234 se_lwz r3, 36(sp) /* Restores GPR3...GPR12. */
235 se_lwz r4, 40(sp)
236 se_lwz r5, 44(sp)
237 se_lwz r6, 48(sp)
238 se_lwz r7, 52(sp)
239 e_lwz r8, 56(sp)
240 e_lwz r9, 60(sp)
241 e_lwz r10, 64(sp)
242 e_lwz r11, 68(sp)
243 e_lwz r12, 72(sp)
244 se_lwz r0, 8(sp)
245 mtSRR0 r0 /* Restores PC. */
246 se_lwz r0, 12(sp)
247 mtSRR1 r0 /* Restores MSR. */
248 se_lwz r0, 16(sp)
249 mtCR r0 /* Restores CR. */
250 se_lwz r0, 20(sp)
251 mtLR r0 /* Restores LR. */
252 se_lwz r0, 24(sp)
253 mtCTR r0 /* Restores CTR. */
254 se_lwz r0, 28(sp)
255 mtXER r0 /* Restores XER. */
256 se_lwz r0, 32(sp) /* Restores GPR0. */
257#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
258 e_addi sp, sp, 80 /* Back to the previous frame. */
259 se_rfi
260
261#endif /* !defined(__DOXYGEN__) */
262
263/** @} */
diff --git a/lib/chibios/os/common/ports/e200/compilers/GCC/mk/port.mk b/lib/chibios/os/common/ports/e200/compilers/GCC/mk/port.mk
new file mode 100644
index 000000000..3bd08cdc0
--- /dev/null
+++ b/lib/chibios/os/common/ports/e200/compilers/GCC/mk/port.mk
@@ -0,0 +1,13 @@
1# List of the ChibiOS/RT e200 generic port files.
2PORTSRC = $(CHIBIOS)/os/common/ports/e200/chcore.c
3
4PORTASM = $(CHIBIOS)/os/common/ports/e200/compilers/GCC/ivor.S \
5 $(CHIBIOS)/os/common/ports/e200/compilers/GCC/chcoreasm.S
6
7PORTINC = $(CHIBIOS)/os/common/ports/e200 \
8 $(CHIBIOS)/os/common/ports/e200/compilers/GCC
9
10# Shared variables
11ALLXASMSRC += $(PORTASM)
12ALLCSRC += $(PORTSRC)
13ALLINC += $(PORTINC)
diff --git a/lib/chibios/os/common/ports/e200/compilers/GHS/chcoreasm.s b/lib/chibios/os/common/ports/e200/compilers/GHS/chcoreasm.s
new file mode 100644
index 000000000..d409f7556
--- /dev/null
+++ b/lib/chibios/os/common/ports/e200/compilers/GHS/chcoreasm.s
@@ -0,0 +1,107 @@
1/*
2 ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,2011,2012,2013,2014,
3 2015,2016,2017,2018,2019,2020,2021 Giovanni Di Sirio.
4
5 This file is part of ChibiOS.
6
7 ChibiOS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation version 3 of the License.
10
11 ChibiOS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
18*/
19
20/**
21 * @file e200/compilers/GHS/chcoreasm.S
22 * @brief Power Architecture port low level code.
23 *
24 * @addtogroup PPC_GHS_CORE
25 * @{
26 */
27
28/*===========================================================================*/
29/* Module constants. */
30/*===========================================================================*/
31
32#if !defined(FALSE) || defined(__DOXYGEN__)
33#define FALSE 0
34#endif
35
36#if !defined(TRUE) || defined(__DOXYGEN__)
37#define TRUE 1
38#endif
39
40/*===========================================================================*/
41/* Code section. */
42/*===========================================================================*/
43
44#define _FROM_ASM_
45#include "chlicense.h"
46#include "chconf.h"
47#include "chcore.h"
48
49#if !defined(__DOXYGEN__)
50
51/*
52 * RTOS-specific context offset.
53 */
54#if defined(_CHIBIOS_RT_CONF_)
55#define CONTEXT_OFFSET 12
56#elif defined(_CHIBIOS_NIL_CONF_)
57#define CONTEXT_OFFSET 0
58#else
59#error "invalid chconf.h"
60#endif
61
62 .vle
63
64 .section .vletext, "axv"
65
66 .align 2
67 .globl _port_switch
68 .type _port_switch, @function
69_port_switch:
70 e_subi sp, sp, 80
71 mflr r0
72 e_stw r0, 84(sp)
73 mfcr r0
74 se_stw r0, 0(sp)
75 e_stmw r14, 4(sp)
76
77 se_stw sp, CONTEXT_OFFSET(r4)
78 se_lwz sp, CONTEXT_OFFSET(r3)
79
80 e_lmw r14, 4(sp)
81 se_lwz r0, 0(sp)
82 mtcr r0
83 e_lwz r0, 84(sp)
84 mtlr r0
85 e_addi sp, sp, 80
86 se_blr
87
88 .align 2
89 .globl _port_thread_start
90 .type _port_thread_start, @function
91_port_thread_start:
92#if CH_DBG_SYSTEM_STATE_CHECK
93 e_bl _dbg_check_unlock
94#endif
95#if CH_DBG_STATISTICS
96 e_bl _stats_stop_measure_crit_thd
97#endif
98 wrteei 1
99 mr r3, r31
100 mtctr r30
101 se_bctrl
102 e_li r0, 0
103 e_bl chThdExit
104
105#endif /* !defined(__DOXYGEN__) */
106
107/** @} */
diff --git a/lib/chibios/os/common/ports/e200/compilers/GHS/chtypes.h b/lib/chibios/os/common/ports/e200/compilers/GHS/chtypes.h
new file mode 100644
index 000000000..d0f3d08c3
--- /dev/null
+++ b/lib/chibios/os/common/ports/e200/compilers/GHS/chtypes.h
@@ -0,0 +1,97 @@
1/*
2 ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,2011,2012,2013,2014,
3 2015,2016,2017,2018,2019,2020,2021 Giovanni Di Sirio.
4
5 This file is part of ChibiOS.
6
7 ChibiOS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation version 3 of the License.
10
11 ChibiOS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
18*/
19
20/**
21 * @file e200/compilers/GCC/chtypes.h
22 * @brief Power e200 port system types.
23 *
24 * @addtogroup PPC_GCC_CORE
25 * @{
26 */
27
28#ifndef CHTYPES_H
29#define CHTYPES_H
30
31#include <stddef.h>
32#include <stdint.h>
33#include <stdbool.h>
34
35/**
36 * @name Kernel types
37 * @{
38 */
39typedef uint32_t rtcnt_t; /**< Realtime counter. */
40typedef uint64_t rttime_t; /**< Realtime accumulator. */
41typedef uint32_t syssts_t; /**< System status word. */
42typedef uint8_t tmode_t; /**< Thread flags. */
43typedef uint8_t tstate_t; /**< Thread state. */
44typedef uint8_t trefs_t; /**< Thread references counter. */
45typedef uint8_t tslices_t; /**< Thread time slices counter.*/
46typedef uint32_t tprio_t; /**< Thread priority. */
47typedef int32_t msg_t; /**< Inter-thread message. */
48typedef int32_t eventid_t; /**< Numeric event identifier. */
49typedef uint32_t eventmask_t; /**< Mask of event identifiers. */
50typedef uint32_t eventflags_t; /**< Mask of event flags. */
51typedef int32_t cnt_t; /**< Generic signed counter. */
52typedef uint32_t ucnt_t; /**< Generic unsigned counter. */
53/** @} */
54
55/**
56 * @brief ROM constant modifier.
57 * @note It is set to use the "const" keyword in this port.
58 */
59#define ROMCONST const
60
61/**
62 * @brief Makes functions not inlineable.
63 * @note If the compiler does not support such attribute then some
64 * time-dependent services could be degraded.
65 */
66#define NOINLINE __attribute__((noinline))
67
68/**
69 * @brief Optimized thread function declaration macro.
70 */
71#define PORT_THD_FUNCTION(tname, arg) void tname(void *arg)
72
73/**
74 * @brief Packed variable specifier.
75 */
76#define PACKED_VAR __attribute__((packed))
77
78/**
79 * @brief Memory alignment enforcement for variables.
80 */
81#define ALIGNED_VAR(n) __attribute__((aligned(n)))
82
83/**
84 * @brief Size of a pointer.
85 * @note To be used where the sizeof operator cannot be used, preprocessor
86 * expressions for example.
87 */
88#define SIZEOF_PTR 4
89
90/**
91 * @brief True if alignment is low-high in current architecture.
92 */
93#define REVERSE_ORDER 0
94
95#endif /* CHTYPES_H */
96
97/** @} */
diff --git a/lib/chibios/os/common/ports/e200/compilers/GHS/ivor.s b/lib/chibios/os/common/ports/e200/compilers/GHS/ivor.s
new file mode 100644
index 000000000..e6ef4b9b6
--- /dev/null
+++ b/lib/chibios/os/common/ports/e200/compilers/GHS/ivor.s
@@ -0,0 +1,265 @@
1/*
2 ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,2011,2012,2013,2014,
3 2015,2016,2017,2018,2019,2020,2021 Giovanni Di Sirio.
4
5 This file is part of ChibiOS.
6
7 ChibiOS is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation version 3 of the License.
10
11 ChibiOS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>.
18*/
19
20/**
21 * @file e200/compilers/GHS/ivor.S
22 * @brief Kernel ISRs.
23 *
24 * @addtogroup PPC_GHS_CORE
25 * @{
26 */
27
28#if !defined(FALSE) || defined(__DOXYGEN__)
29#define FALSE 0
30#endif
31
32#if !defined(TRUE) || defined(__DOXYGEN__)
33#define TRUE 1
34#endif
35
36/*
37 * Imports the PPC configuration headers.
38 */
39#define _FROM_ASM_
40#include "chlicense.h"
41#include "chconf.h"
42#include "chcore.h"
43
44#if defined(__HIGHTEC__)
45#define se_beq beq
46#endif
47
48#if !defined(__DOXYGEN__)
49
50 .vle
51
52 .section .handlers, "axv"
53
54#if PPC_SUPPORTS_DECREMENTER
55 /*
56 * _IVOR10 handler (Book-E decrementer).
57 */
58 .align 4
59 .globl _IVOR10
60 .type _IVOR10, @function
61_IVOR10:
62 /* Saving the external context (port_extctx structure).*/
63 e_stwu sp, -80(sp)
64#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
65 e_stmvsrrw 8(sp) /* Saves PC, MSR. */
66 e_stmvsprw 16(sp) /* Saves CR, LR, CTR, XER. */
67 e_stmvgprw 32(sp) /* Saves GPR0, GPR3...GPR12. */
68#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
69 se_stw r0, 32(sp) /* Saves GPR0. */
70 mfSRR0 r0
71 se_stw r0, 8(sp) /* Saves PC. */
72 mfSRR1 r0
73 se_stw r0, 12(sp) /* Saves MSR. */
74 mfCR r0
75 se_stw r0, 16(sp) /* Saves CR. */
76 mfLR r0
77 se_stw r0, 20(sp) /* Saves LR. */
78 mfCTR r0
79 se_stw r0, 24(sp) /* Saves CTR. */
80 mfXER r0
81 se_stw r0, 28(sp) /* Saves XER. */
82 se_stw r3, 36(sp) /* Saves GPR3...GPR12. */
83 se_stw r4, 40(sp)
84 se_stw r5, 44(sp)
85 se_stw r6, 48(sp)
86 se_stw r7, 52(sp)
87 e_stw r8, 56(sp)
88 e_stw r9, 60(sp)
89 e_stw r10, 64(sp)
90 e_stw r11, 68(sp)
91 e_stw r12, 72(sp)
92#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
93
94 /* Increasing the SPGR0 register.*/
95 mfspr r0, 272
96 se_addi r0, 1
97 mtspr 272, r0
98
99 /* Reset DIE bit in TSR register.*/
100 e_lis r3, 0x0800 /* DIS bit mask. */
101 mtspr 336, r3 /* TSR register. */
102
103 /* Restoring pre-IRQ MSR register value.*/
104 mfSRR1 r0
105#if !PPC_USE_IRQ_PREEMPTION
106 /* No preemption, keeping EE disabled.*/
107 se_bclri r0, 16 /* EE = bit 16. */
108#endif
109 mtMSR r0
110
111#if CH_DBG_SYSTEM_STATE_CHECK
112 e_bl _dbg_check_enter_isr
113 e_bl _dbg_check_lock_from_isr
114#endif
115 /* System tick handler invocation.*/
116 e_bl chSysTimerHandlerI
117#if CH_DBG_SYSTEM_STATE_CHECK
118 e_bl _dbg_check_unlock_from_isr
119 e_bl _dbg_check_leave_isr
120#endif
121
122#if PPC_USE_IRQ_PREEMPTION
123 /* Prevents preemption again.*/
124 wrteei 0
125#endif
126
127 /* Jumps to the common IVOR epilogue code.*/
128 e_b _ivor_exit
129#endif /* PPC_SUPPORTS_DECREMENTER */
130
131 /*
132 * _IVOR4 handler (Book-E external interrupt).
133 */
134 .align 4
135 .globl _IVOR4
136 .type _IVOR4, @function
137_IVOR4:
138 /* Saving the external context (port_extctx structure).*/
139 e_stwu sp, -80(sp)
140#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
141 e_stmvsrrw 8(sp) /* Saves PC, MSR. */
142 e_stmvsprw 16(sp) /* Saves CR, LR, CTR, XER. */
143 e_stmvgprw 32(sp) /* Saves GPR0, GPR3...GPR12. */
144#else /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
145 se_stw r0, 32(sp) /* Saves GPR0. */
146 mfSRR0 r0
147 se_stw r0, 8(sp) /* Saves PC. */
148 mfSRR1 r0
149 se_stw r0, 12(sp) /* Saves MSR. */
150 mfCR r0
151 se_stw r0, 16(sp) /* Saves CR. */
152 mfLR r0
153 se_stw r0, 20(sp) /* Saves LR. */
154 mfCTR r0
155 se_stw r0, 24(sp) /* Saves CTR. */
156 mfXER r0
157 se_stw r0, 28(sp) /* Saves XER. */
158 se_stw r3, 36(sp) /* Saves GPR3...GPR12. */
159 se_stw r4, 40(sp)
160 se_stw r5, 44(sp)
161 se_stw r6, 48(sp)
162 se_stw r7, 52(sp)
163 e_stw r8, 56(sp)
164 e_stw r9, 60(sp)
165 e_stw r10, 64(sp)
166 e_stw r11, 68(sp)
167 e_stw r12, 72(sp)
168#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
169
170 /* Increasing the SPGR0 register.*/
171 mfspr r0, 272
172 se_addi r0, 1
173 mtspr 272, r0
174
175 /* Software vector address from the INTC register.*/
176 e_lis r3, INTC_IACKR_ADDR@h
177 e_or2i r3, INTC_IACKR_ADDR@l /* IACKR register address. */
178 e_lwz r3, 0(r3) /* IACKR register value. */
179 e_lwz r3, 0(r3)
180 mtCTR r3 /* Software handler address. */
181
182 /* Restoring pre-IRQ MSR register value.*/
183 mfSRR1 r0
184#if !PPC_USE_IRQ_PREEMPTION
185 /* No preemption, keeping EE disabled.*/
186 se_bclri r0, 16 /* EE = bit 16. */
187#endif
188 mtMSR r0
189
190 /* Exectes the software handler.*/
191 se_bctrl
192
193#if PPC_USE_IRQ_PREEMPTION
194 /* Prevents preemption again.*/
195 wrteei 0
196#endif
197
198 /* Informs the INTC that the interrupt has been served.*/
199 mbar 0
200 e_lis r3, INTC_EOIR_ADDR@h
201 e_or2i r3, INTC_EOIR_ADDR@l
202 se_stw r3, 0(r3) /* Writing any value should do. */
203
204 /* Common IVOR epilogue code, context restore.*/
205 .globl _ivor_exit
206_ivor_exit:
207 /* Decreasing the SPGR0 register.*/
208 mfspr r0, 272
209 se_subi r0, 1
210 mtspr 272, r0
211
212#if CH_DBG_STATISTICS
213 e_bl _stats_start_measure_crit_thd
214#endif
215#if CH_DBG_SYSTEM_STATE_CHECK
216 e_bl _dbg_check_lock
217#endif
218 e_bl chSchIsPreemptionRequired
219 se_cmpi r3, 0
220 se_beq .noresch
221 e_bl chSchDoReschedule
222.noresch:
223#if CH_DBG_SYSTEM_STATE_CHECK
224 e_bl _dbg_check_unlock
225#endif
226#if CH_DBG_STATISTICS
227 e_bl _stats_stop_measure_crit_thd
228#endif
229
230 /* Restoring the external context.*/
231#if PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI
232 e_lmvgprw 32(sp) /* Restores GPR0, GPR3...GPR12. */
233 e_lmvsprw 16(sp) /* Restores CR, LR, CTR, XER. */
234 e_lmvsrrw 8(sp) /* Restores PC, MSR. */
235#else /*!(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
236 se_lwz r3, 36(sp) /* Restores GPR3...GPR12. */
237 se_lwz r4, 40(sp)
238 se_lwz r5, 44(sp)
239 se_lwz r6, 48(sp)
240 se_lwz r7, 52(sp)
241 e_lwz r8, 56(sp)
242 e_lwz r9, 60(sp)
243 e_lwz r10, 64(sp)
244 e_lwz r11, 68(sp)
245 e_lwz r12, 72(sp)
246 se_lwz r0, 8(sp)
247 mtSRR0 r0 /* Restores PC. */
248 se_lwz r0, 12(sp)
249 mtSRR1 r0 /* Restores MSR. */
250 se_lwz r0, 16(sp)
251 mtCR r0 /* Restores CR. */
252 se_lwz r0, 20(sp)
253 mtLR r0 /* Restores LR. */
254 se_lwz r0, 24(sp)
255 mtCTR r0 /* Restores CTR. */
256 se_lwz r0, 28(sp)
257 mtXER r0 /* Restores XER. */
258 se_lwz r0, 32(sp) /* Restores GPR0. */
259#endif /* !(PPC_USE_VLE && PPC_SUPPORTS_VLE_MULTI) */
260 e_addi sp, sp, 80 /* Back to the previous frame. */
261 se_rfi
262
263#endif /* !defined(__DOXYGEN__) */
264
265/** @} */
diff --git a/lib/chibios/os/common/ports/e200/compilers/GHS/mk/port.mk b/lib/chibios/os/common/ports/e200/compilers/GHS/mk/port.mk
new file mode 100644
index 000000000..c6c412c17
--- /dev/null
+++ b/lib/chibios/os/common/ports/e200/compilers/GHS/mk/port.mk
@@ -0,0 +1,13 @@
1# List of the ChibiOS/RT e200 generic port files.
2PORTSRC = $(CHIBIOS)/os/common/ports/e200/chcore.c
3
4PORTASM = $(CHIBIOS)/os/common/ports/e200/compilers/GHS/ivor.s \
5 $(CHIBIOS)/os/common/ports/e200/compilers/GHS/chcoreasm.s
6
7PORTINC = $(CHIBIOS)/os/common/ports/e200 \
8 $(CHIBIOS)/os/common/ports/e200/compilers/GHS
9
10# Shared variables
11ALLASMSRC += $(PORTASM)
12ALLCSRC += $(PORTSRC)
13ALLINC += $(PORTINC)
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 00:44:30 +0100