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diff --git a/lib/chibios/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S b/lib/chibios/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S
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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file crt0_v6m.S
19 * @brief Generic ARMv6-M (Cortex-M0/M1) startup file for ChibiOS.
20 *
21 * @addtogroup ARMCMx_GCC_STARTUP_V6M
22 * @{
23 */
24
25/*===========================================================================*/
26/* Module constants. */
27/*===========================================================================*/
28
29#if !defined(FALSE) || defined(__DOXYGEN__)
30#define FALSE 0
31#endif
32
33#if !defined(TRUE) || defined(__DOXYGEN__)
34#define TRUE 1
35#endif
36
37#define CONTROL_MODE_PRIVILEGED 0
38#define CONTROL_MODE_UNPRIVILEGED 1
39#define CONTROL_USE_MSP 0
40#define CONTROL_USE_PSP 2
41
42#define SCB_VTOR 0xE000ED08
43
44/*===========================================================================*/
45/* Module pre-compile time settings. */
46/*===========================================================================*/
47
48/**
49 * @brief Enforces initialization of MSP.
50 * @note This is required if the boot process is not reliable for whatever
51 * reason (bad ROMs, bad bootloaders, bad debuggers=.
52 */
53#if !defined(CRT0_FORCE_MSP_INIT) || defined(__DOXYGEN__)
54#define CRT0_FORCE_MSP_INIT TRUE
55#endif
56
57/**
58 * @brief VTOR special register initialization.
59 * @details VTOR is initialized to point to the vectors table.
60 * @note This option can only be enabled on Cortex-M0+ cores.
61 */
62#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
63#define CRT0_VTOR_INIT FALSE
64#endif
65
66/**
67 * @brief Control special register initialization value.
68 * @details The system is setup to run in privileged mode using the PSP
69 * stack (dual stack mode).
70 */
71#if !defined(CRT0_CONTROL_INIT) || defined(__DOXYGEN__)
72#define CRT0_CONTROL_INIT (CONTROL_USE_PSP | \
73 CONTROL_MODE_PRIVILEGED)
74#endif
75
76/**
77 * @brief Core initialization switch.
78 */
79#if !defined(CRT0_INIT_CORE) || defined(__DOXYGEN__)
80#define CRT0_INIT_CORE TRUE
81#endif
82
83/**
84 * @brief Stack segments initialization switch.
85 */
86#if !defined(CRT0_STACKS_FILL_PATTERN) || defined(__DOXYGEN__)
87#define CRT0_STACKS_FILL_PATTERN 0x55555555
88#endif
89
90/**
91 * @brief Stack segments initialization switch.
92 */
93#if !defined(CRT0_INIT_STACKS) || defined(__DOXYGEN__)
94#define CRT0_INIT_STACKS TRUE
95#endif
96
97/**
98 * @brief DATA segment initialization switch.
99 */
100#if !defined(CRT0_INIT_DATA) || defined(__DOXYGEN__)
101#define CRT0_INIT_DATA TRUE
102#endif
103
104/**
105 * @brief BSS segment initialization switch.
106 */
107#if !defined(CRT0_INIT_BSS) || defined(__DOXYGEN__)
108#define CRT0_INIT_BSS TRUE
109#endif
110
111/**
112 * @brief RAM areas initialization switch.
113 */
114#if !defined(CRT0_INIT_RAM_AREAS) || defined(__DOXYGEN__)
115#define CRT0_INIT_RAM_AREAS TRUE
116#endif
117
118/**
119 * @brief Constructors invocation switch.
120 */
121#if !defined(CRT0_CALL_CONSTRUCTORS) || defined(__DOXYGEN__)
122#define CRT0_CALL_CONSTRUCTORS TRUE
123#endif
124
125/**
126 * @brief Destructors invocation switch.
127 */
128#if !defined(CRT0_CALL_DESTRUCTORS) || defined(__DOXYGEN__)
129#define CRT0_CALL_DESTRUCTORS TRUE
130#endif
131
132/*===========================================================================*/
133/* Code section. */
134/*===========================================================================*/
135
136#if !defined(__DOXYGEN__)
137
138 .cpu cortex-m0
139 .fpu softvfp
140 .syntax unified
141 .thumb
142 .text
143
144/*
145 * CRT0 entry point.
146 */
147 .align 2
148 .thumb_func
149 .global _crt0_entry
150_crt0_entry:
151 /* Interrupts are globally masked initially.*/
152 cpsid i
153
154#if CRT0_FORCE_MSP_INIT == TRUE
155 /* MSP stack pointers initialization.*/
156 ldr r0, =__main_stack_end__
157 msr MSP, r0
158#endif
159
160 /* PSP stack pointers initialization.*/
161 ldr r0, =__process_stack_end__
162 msr PSP, r0
163
164 /* CPU mode initialization as configured.*/
165 movs r0, #CRT0_CONTROL_INIT
166 msr CONTROL, r0
167 isb
168
169#if CRT0_VTOR_INIT == TRUE
170 ldr r0, =_vectors
171 ldr r1, =SCB_VTOR
172 str r0, [r1]
173#endif
174
175#if CRT0_INIT_CORE == TRUE
176 /* Core initialization.*/
177 bl __core_init
178#endif
179
180 /* Early initialization..*/
181 bl __early_init
182
183#if CRT0_INIT_STACKS == TRUE
184 ldr r0, =CRT0_STACKS_FILL_PATTERN
185 /* Main Stack initialization. Note, it assumes that the
186 stack size is a multiple of 4 so the linker file must
187 ensure this.*/
188 ldr r1, =__main_stack_base__
189 ldr r2, =__main_stack_end__
190msloop:
191 cmp r1, r2
192 bge endmsloop
193 str r0, [r1]
194 adds r1, #4
195 b msloop
196endmsloop:
197 /* Process Stack initialization. Note, it assumes that the
198 stack size is a multiple of 4 so the linker file must
199 ensure this.*/
200 ldr r1, =__process_stack_base__
201 ldr r2, =__process_stack_end__
202psloop:
203 cmp r1, r2
204 bge endpsloop
205 str r0, [r1]
206 adds r1, #4
207 b psloop
208endpsloop:
209#endif
210
211#if CRT0_INIT_DATA == TRUE
212 /* Data initialization. Note, it assumes that the DATA size
213 is a multiple of 4 so the linker file must ensure this.*/
214 ldr r1, =__textdata_base__
215 ldr r2, =__data_base__
216 ldr r3, =__data_end__
217dloop:
218 cmp r2, r3
219 bge enddloop
220 ldr r0, [r1]
221 str r0, [r2]
222 adds r1, #4
223 adds r2, #4
224 b dloop
225enddloop:
226#endif
227
228#if CRT0_INIT_BSS == TRUE
229 /* BSS initialization. Note, it assumes that the DATA size
230 is a multiple of 4 so the linker file must ensure this.*/
231 movs r0, #0
232 ldr r1, =__bss_base__
233 ldr r2, =__bss_end__
234bloop:
235 cmp r1, r2
236 bge endbloop
237 str r0, [r1]
238 adds r1, #4
239 b bloop
240endbloop:
241#endif
242
243#if CRT0_INIT_RAM_AREAS == TRUE
244 /* RAM areas initialization.*/
245 bl __init_ram_areas
246#endif
247
248 /* Late initialization..*/
249 bl __late_init
250
251#if CRT0_CALL_CONSTRUCTORS == TRUE
252 /* Constructors invocation.*/
253 ldr r4, =__init_array_base__
254 ldr r5, =__init_array_end__
255initloop:
256 cmp r4, r5
257 bge endinitloop
258 ldr r1, [r4]
259 blx r1
260 adds r4, #4
261 b initloop
262endinitloop:
263#endif
264
265 /* Main program invocation, r0 contains the returned value.*/
266 bl main
267
268#if CRT0_CALL_DESTRUCTORS == TRUE
269 /* Destructors invocation.*/
270 ldr r4, =__fini_array_base__
271 ldr r5, =__fini_array_end__
272finiloop:
273 cmp r4, r5
274 bge endfiniloop
275 ldr r1, [r4]
276 blx r1
277 adds r4, #4
278 b finiloop
279endfiniloop:
280#endif
281
282 /* Branching to the defined exit handler.*/
283 ldr r1, =__default_exit
284 bx r1
285
286#endif
287
288/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 09:59:13 +0100