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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560BCxx/boot.s
19 * @brief SPC560BCxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if defined(__HIGHTEC__)
28#define se_bge bge
29#endif
30
31#if !defined(__DOXYGEN__)
32
33 /* BAM record.*/
34 .section .boot, "ax"
35
36 .long 0x015A0000
37 .long _reset_address
38
39 .align 2
40 .globl _reset_address
41 .type _reset_address, @function
42_reset_address:
43#if BOOT_PERFORM_CORE_INIT
44 e_bl _coreinit
45#endif
46 e_bl _ivinit
47
48#if BOOT_RELOCATE_IN_RAM
49 /*
50 * Image relocation in RAM.
51 */
52 e_lis r4, __ram_reloc_start__@h
53 e_or2i r4, __ram_reloc_start__@l
54 e_lis r5, __ram_reloc_dest__@h
55 e_or2i r5, __ram_reloc_dest__@l
56 e_lis r6, __ram_reloc_end__@h
57 e_or2i r6, r6, __ram_reloc_end__@l
58.relloop:
59 se_cmpl r4, r6
60 se_bge .relend
61 se_lwz r7, 0(r4)
62 se_addi r4, 4
63 se_stw r7, 0(r5)
64 se_addi r5, 4
65 se_b .relloop
66.relend:
67 e_lis r3, _boot_address@h
68 e_or2i r3, _boot_address@l
69 mtctr r3
70 se_bctrl
71#else
72 e_b _boot_address
73#endif
74
75#if BOOT_PERFORM_CORE_INIT
76 .align 2
77_coreinit:
78 /*
79 * RAM clearing, this device requires a write to all RAM location in
80 * order to initialize the ECC detection hardware, this is going to
81 * slow down the startup but there is no way around.
82 */
83 xor r0, r0, r0
84 xor r1, r1, r1
85 xor r2, r2, r2
86 xor r3, r3, r3
87 xor r4, r4, r4
88 xor r5, r5, r5
89 xor r6, r6, r6
90 xor r7, r7, r7
91 xor r8, r8, r8
92 xor r9, r9, r9
93 xor r10, r10, r10
94 xor r11, r11, r11
95 xor r12, r12, r12
96 xor r13, r13, r13
97 xor r14, r14, r14
98 xor r15, r15, r15
99 xor r16, r16, r16
100 xor r17, r17, r17
101 xor r18, r18, r18
102 xor r19, r19, r19
103 xor r20, r20, r20
104 xor r21, r21, r21
105 xor r22, r22, r22
106 xor r23, r23, r23
107 xor r24, r24, r24
108 xor r25, r25, r25
109 xor r26, r26, r26
110 xor r27, r27, r27
111 xor r28, r28, r28
112 xor r29, r29, r29
113 xor r30, r30, r30
114 xor r31, r31, r31
115 e_lis r4, __ram_start__@h
116 e_or2i r4, __ram_start__@l
117 e_lis r5, __ram_end__@h
118 e_or2i r5, __ram_end__@l
119.cleareccloop:
120 se_cmpl r4, r5
121 se_bge .cleareccend
122 e_stmw r16, 0(r4)
123 e_addi r4, r4, 64
124 se_b .cleareccloop
125.cleareccend:
126
127 /*
128 * Branch prediction enabled.
129 */
130 e_li r3, BOOT_BUCSR_DEFAULT
131 mtspr 1013, r3 /* BUCSR */
132
133 se_blr
134#endif /* BOOT_PERFORM_CORE_INIT */
135
136 /*
137 * Exception vectors initialization.
138 */
139 .align 2
140_ivinit:
141 /* MSR initialization.*/
142 e_lis r3, BOOT_MSR_DEFAULT@h
143 e_or2i r3, BOOT_MSR_DEFAULT@l
144 mtMSR r3
145
146 /* IVPR initialization.*/
147 e_lis r3, __ivpr_base__@h
148 e_or2i r3, __ivpr_base__@l
149 mtIVPR r3
150
151 se_blr
152
153 .section .ivors, "ax"
154
155 .globl IVORS
156IVORS:
157 e_b _IVOR0
158 .align 4
159 e_b _IVOR1
160 .align 4
161 e_b _IVOR2
162 .align 4
163 e_b _IVOR3
164 .align 4
165 e_b _IVOR4
166 .align 4
167 e_b _IVOR5
168 .align 4
169 e_b _IVOR6
170 .align 4
171 e_b _IVOR7
172 .align 4
173 e_b _IVOR8
174 .align 4
175 e_b _IVOR9
176 .align 4
177 e_b _IVOR10
178 .align 4
179 e_b _IVOR11
180 .align 4
181 e_b _IVOR12
182 .align 4
183 e_b _IVOR13
184 .align 4
185 e_b _IVOR14
186 .align 4
187 e_b _IVOR15
188
189 .section .handlers, "ax"
190
191 /*
192 * Default IVOR handlers.
193 */
194 .align 2
195 .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
196 .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
197 .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
198_IVOR0:
199_IVOR1:
200_IVOR2:
201_IVOR3:
202_IVOR5:
203_IVOR6:
204_IVOR7:
205_IVOR8:
206_IVOR9:
207_IVOR11:
208_IVOR12:
209_IVOR13:
210_IVOR14:
211_IVOR15:
212 .global _unhandled_exception
213_unhandled_exception:
214 se_b _unhandled_exception
215
216#endif /* !defined(__DOXYGEN__) */
217
218/** @} */
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