aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios/os/common/startup/e200/devices
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios/os/common/startup/e200/devices')
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560BCxx/boot.S218
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560BCxx/boot.h114
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560BCxx/intc.h93
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560BCxx/ppcparams.h83
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Bxx/boot.S218
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Bxx/boot.h114
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Bxx/intc.h93
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Bxx/ppcparams.h83
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot.S218
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot.h114
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot_cw.s200
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot_ghs.s216
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Dxx/intc.h93
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Dxx/ppcparams.h83
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.S218
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.h114
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Pxx/intc.h93
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC560Pxx/ppcparams.h83
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC563Mxx/boot.S192
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC563Mxx/boot.h119
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC563Mxx/intc.h93
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC563Mxx/ppcparams.h83
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC564Axx/boot.S357
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC564Axx/boot.h242
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC564Axx/intc.h93
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC564Axx/ppcparams.h83
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot.S408
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot.h248
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot_cw.s400
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot_ghs.s405
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ECxx/intc.h95
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ECxx/ppcparams.h83
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.S409
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.h248
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ELxx/intc.h93
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h83
36 files changed, 6182 insertions, 0 deletions
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560BCxx/boot.S b/lib/chibios/os/common/startup/e200/devices/SPC560BCxx/boot.S
new file mode 100644
index 000000000..47e67e346
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560BCxx/boot.S
@@ -0,0 +1,218 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560BCxx/boot.s
19 * @brief SPC560BCxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if defined(__HIGHTEC__)
28#define se_bge bge
29#endif
30
31#if !defined(__DOXYGEN__)
32
33 /* BAM record.*/
34 .section .boot, "ax"
35
36 .long 0x015A0000
37 .long _reset_address
38
39 .align 2
40 .globl _reset_address
41 .type _reset_address, @function
42_reset_address:
43#if BOOT_PERFORM_CORE_INIT
44 e_bl _coreinit
45#endif
46 e_bl _ivinit
47
48#if BOOT_RELOCATE_IN_RAM
49 /*
50 * Image relocation in RAM.
51 */
52 e_lis r4, __ram_reloc_start__@h
53 e_or2i r4, __ram_reloc_start__@l
54 e_lis r5, __ram_reloc_dest__@h
55 e_or2i r5, __ram_reloc_dest__@l
56 e_lis r6, __ram_reloc_end__@h
57 e_or2i r6, r6, __ram_reloc_end__@l
58.relloop:
59 se_cmpl r4, r6
60 se_bge .relend
61 se_lwz r7, 0(r4)
62 se_addi r4, 4
63 se_stw r7, 0(r5)
64 se_addi r5, 4
65 se_b .relloop
66.relend:
67 e_lis r3, _boot_address@h
68 e_or2i r3, _boot_address@l
69 mtctr r3
70 se_bctrl
71#else
72 e_b _boot_address
73#endif
74
75#if BOOT_PERFORM_CORE_INIT
76 .align 2
77_coreinit:
78 /*
79 * RAM clearing, this device requires a write to all RAM location in
80 * order to initialize the ECC detection hardware, this is going to
81 * slow down the startup but there is no way around.
82 */
83 xor r0, r0, r0
84 xor r1, r1, r1
85 xor r2, r2, r2
86 xor r3, r3, r3
87 xor r4, r4, r4
88 xor r5, r5, r5
89 xor r6, r6, r6
90 xor r7, r7, r7
91 xor r8, r8, r8
92 xor r9, r9, r9
93 xor r10, r10, r10
94 xor r11, r11, r11
95 xor r12, r12, r12
96 xor r13, r13, r13
97 xor r14, r14, r14
98 xor r15, r15, r15
99 xor r16, r16, r16
100 xor r17, r17, r17
101 xor r18, r18, r18
102 xor r19, r19, r19
103 xor r20, r20, r20
104 xor r21, r21, r21
105 xor r22, r22, r22
106 xor r23, r23, r23
107 xor r24, r24, r24
108 xor r25, r25, r25
109 xor r26, r26, r26
110 xor r27, r27, r27
111 xor r28, r28, r28
112 xor r29, r29, r29
113 xor r30, r30, r30
114 xor r31, r31, r31
115 e_lis r4, __ram_start__@h
116 e_or2i r4, __ram_start__@l
117 e_lis r5, __ram_end__@h
118 e_or2i r5, __ram_end__@l
119.cleareccloop:
120 se_cmpl r4, r5
121 se_bge .cleareccend
122 e_stmw r16, 0(r4)
123 e_addi r4, r4, 64
124 se_b .cleareccloop
125.cleareccend:
126
127 /*
128 * Branch prediction enabled.
129 */
130 e_li r3, BOOT_BUCSR_DEFAULT
131 mtspr 1013, r3 /* BUCSR */
132
133 se_blr
134#endif /* BOOT_PERFORM_CORE_INIT */
135
136 /*
137 * Exception vectors initialization.
138 */
139 .align 2
140_ivinit:
141 /* MSR initialization.*/
142 e_lis r3, BOOT_MSR_DEFAULT@h
143 e_or2i r3, BOOT_MSR_DEFAULT@l
144 mtMSR r3
145
146 /* IVPR initialization.*/
147 e_lis r3, __ivpr_base__@h
148 e_or2i r3, __ivpr_base__@l
149 mtIVPR r3
150
151 se_blr
152
153 .section .ivors, "ax"
154
155 .globl IVORS
156IVORS:
157 e_b _IVOR0
158 .align 4
159 e_b _IVOR1
160 .align 4
161 e_b _IVOR2
162 .align 4
163 e_b _IVOR3
164 .align 4
165 e_b _IVOR4
166 .align 4
167 e_b _IVOR5
168 .align 4
169 e_b _IVOR6
170 .align 4
171 e_b _IVOR7
172 .align 4
173 e_b _IVOR8
174 .align 4
175 e_b _IVOR9
176 .align 4
177 e_b _IVOR10
178 .align 4
179 e_b _IVOR11
180 .align 4
181 e_b _IVOR12
182 .align 4
183 e_b _IVOR13
184 .align 4
185 e_b _IVOR14
186 .align 4
187 e_b _IVOR15
188
189 .section .handlers, "ax"
190
191 /*
192 * Default IVOR handlers.
193 */
194 .align 2
195 .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
196 .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
197 .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
198_IVOR0:
199_IVOR1:
200_IVOR2:
201_IVOR3:
202_IVOR5:
203_IVOR6:
204_IVOR7:
205_IVOR8:
206_IVOR9:
207_IVOR11:
208_IVOR12:
209_IVOR13:
210_IVOR14:
211_IVOR15:
212 .global _unhandled_exception
213_unhandled_exception:
214 se_b _unhandled_exception
215
216#endif /* !defined(__DOXYGEN__) */
217
218/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560BCxx/boot.h b/lib/chibios/os/common/startup/e200/devices/SPC560BCxx/boot.h
new file mode 100644
index 000000000..f3bdd6cbc
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560BCxx/boot.h
@@ -0,0 +1,114 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file boot.h
19 * @brief Boot parameters for the SPC560BCxx.
20 * @{
21 */
22
23#ifndef BOOT_H
24#define BOOT_H
25
26/*===========================================================================*/
27/* Module constants. */
28/*===========================================================================*/
29
30/**
31 * @name BUCSR registers definitions
32 * @{
33 */
34#define BUCSR_BPEN 0x00000001
35#define BUCSR_BALLOC_BFI 0x00000200
36/** @} */
37
38/**
39 * @name MSR register definitions
40 * @{
41 */
42#define MSR_WE 0x00040000
43#define MSR_CE 0x00020000
44#define MSR_EE 0x00008000
45#define MSR_PR 0x00004000
46#define MSR_ME 0x00001000
47#define MSR_DE 0x00000200
48#define MSR_IS 0x00000020
49#define MSR_DS 0x00000010
50#define MSR_RI 0x00000002
51/** @} */
52
53/*===========================================================================*/
54/* Module pre-compile time settings. */
55/*===========================================================================*/
56
57/*
58 * BUCSR default settings.
59 */
60#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
61#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
62#endif
63
64/*
65 * MSR default settings.
66 */
67#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
68#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
69#endif
70
71/*
72 * Boot default settings.
73 */
74#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
75#define BOOT_PERFORM_CORE_INIT 1
76#endif
77
78/*
79 * VLE mode default settings.
80 */
81#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
82#define BOOT_USE_VLE 1
83#endif
84
85/*
86 * RAM relocation flag.
87 */
88#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
89#define BOOT_RELOCATE_IN_RAM 0
90#endif
91
92/*===========================================================================*/
93/* Derived constants and error checks. */
94/*===========================================================================*/
95
96/*===========================================================================*/
97/* Module data structures and types. */
98/*===========================================================================*/
99
100/*===========================================================================*/
101/* Module macros. */
102/*===========================================================================*/
103
104/*===========================================================================*/
105/* External declarations. */
106/*===========================================================================*/
107
108/*===========================================================================*/
109/* Module inline functions. */
110/*===========================================================================*/
111
112#endif /* BOOT_H */
113
114/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560BCxx/intc.h b/lib/chibios/os/common/startup/e200/devices/SPC560BCxx/intc.h
new file mode 100644
index 000000000..fc00873b7
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560BCxx/intc.h
@@ -0,0 +1,93 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560BCxx/intc.h
19 * @brief SPC560BCxx INTC module header.
20 *
21 * @addtogroup INTC
22 * @{
23 */
24
25#ifndef INTC_H
26#define INTC_H
27
28/*===========================================================================*/
29/* Module constants. */
30/*===========================================================================*/
31
32/**
33 * @name INTC addresses
34 * @{
35 */
36#define INTC_BASE 0xFFF48000
37#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
38#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
39/** @} */
40
41/**
42 * @brief INTC priority levels.
43 */
44#define INTC_PRIORITY_LEVELS 16U
45
46/*===========================================================================*/
47/* Module pre-compile time settings. */
48/*===========================================================================*/
49
50/*===========================================================================*/
51/* Derived constants and error checks. */
52/*===========================================================================*/
53
54/*===========================================================================*/
55/* Module data structures and types. */
56/*===========================================================================*/
57
58/*===========================================================================*/
59/* Module macros. */
60/*===========================================================================*/
61
62/**
63 * @name INTC-related macros
64 * @{
65 */
66#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
67#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
68#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
69#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
70#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
71/** @} */
72
73/**
74 * @brief Core selection macros for PSR register.
75 */
76#define INTC_PSR_CORE0 0x00
77
78/**
79 * @brief PSR register content helper
80 */
81#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
82
83/*===========================================================================*/
84/* External declarations. */
85/*===========================================================================*/
86
87/*===========================================================================*/
88/* Module inline functions. */
89/*===========================================================================*/
90
91#endif /* INTC_H */
92
93/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560BCxx/ppcparams.h b/lib/chibios/os/common/startup/e200/devices/SPC560BCxx/ppcparams.h
new file mode 100644
index 000000000..e14437e05
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560BCxx/ppcparams.h
@@ -0,0 +1,83 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560BCxx/ppcparams.h
19 * @brief PowerPC parameters for the SPC560BCxx.
20 *
21 * @defgroup PPC_SPC560BCxx SPC560BCxx Specific Parameters
22 * @ingroup PPC_SPECIFIC
23 * @details This file contains the PowerPC specific parameters for the
24 * SPC560BCxx platform.
25 * @{
26 */
27
28#ifndef PPCPARAMS_H
29#define PPCPARAMS_H
30
31/**
32 * @brief Family identification macro.
33 */
34#define PPC_SPC560BCxx
35
36/**
37 * @brief PPC core model.
38 */
39#define PPC_VARIANT PPC_VARIANT_e200z0
40
41/**
42 * @brief Number of cores.
43 */
44#define PPC_CORE_NUMBER 1
45
46/**
47 * @brief Number of writable bits in IVPR register.
48 */
49#define PPC_IVPR_BITS 20
50
51/**
52 * @brief IVORx registers support.
53 */
54#define PPC_SUPPORTS_IVORS FALSE
55
56/**
57 * @brief Book E instruction set support.
58 */
59#define PPC_SUPPORTS_BOOKE FALSE
60
61/**
62 * @brief VLE instruction set support.
63 */
64#define PPC_SUPPORTS_VLE TRUE
65
66/**
67 * @brief Supports VLS Load/Store Multiple Volatile instructions.
68 */
69#define PPC_SUPPORTS_VLE_MULTI TRUE
70
71/**
72 * @brief Supports the decrementer timer.
73 */
74#define PPC_SUPPORTS_DECREMENTER FALSE
75
76/**
77 * @brief Number of interrupt sources.
78 */
79#define PPC_NUM_VECTORS 217
80
81#endif /* PPCPARAMS_H */
82
83/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Bxx/boot.S b/lib/chibios/os/common/startup/e200/devices/SPC560Bxx/boot.S
new file mode 100644
index 000000000..3de9e21b9
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Bxx/boot.S
@@ -0,0 +1,218 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560Bxx/boot.s
19 * @brief SPC560Bxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if defined(__HIGHTEC__)
28#define se_bge bge
29#endif
30
31#if !defined(__DOXYGEN__)
32
33 /* BAM record.*/
34 .section .boot, "ax"
35
36 .long 0x015A0000
37 .long _reset_address
38
39 .align 2
40 .globl _reset_address
41 .type _reset_address, @function
42_reset_address:
43#if BOOT_PERFORM_CORE_INIT
44 e_bl _coreinit
45#endif
46 e_bl _ivinit
47
48#if BOOT_RELOCATE_IN_RAM
49 /*
50 * Image relocation in RAM.
51 */
52 e_lis r4, __ram_reloc_start__@h
53 e_or2i r4, __ram_reloc_start__@l
54 e_lis r5, __ram_reloc_dest__@h
55 e_or2i r5, __ram_reloc_dest__@l
56 e_lis r6, __ram_reloc_end__@h
57 e_or2i r6, r6, __ram_reloc_end__@l
58.relloop:
59 se_cmpl r4, r6
60 se_bge .relend
61 se_lwz r7, 0(r4)
62 se_addi r4, 4
63 se_stw r7, 0(r5)
64 se_addi r5, 4
65 se_b .relloop
66.relend:
67 e_lis r3, _boot_address@h
68 e_or2i r3, _boot_address@l
69 mtctr r3
70 se_bctrl
71#else
72 e_b _boot_address
73#endif
74
75#if BOOT_PERFORM_CORE_INIT
76 .align 2
77_coreinit:
78 /*
79 * RAM clearing, this device requires a write to all RAM location in
80 * order to initialize the ECC detection hardware, this is going to
81 * slow down the startup but there is no way around.
82 */
83 xor r0, r0, r0
84 xor r1, r1, r1
85 xor r2, r2, r2
86 xor r3, r3, r3
87 xor r4, r4, r4
88 xor r5, r5, r5
89 xor r6, r6, r6
90 xor r7, r7, r7
91 xor r8, r8, r8
92 xor r9, r9, r9
93 xor r10, r10, r10
94 xor r11, r11, r11
95 xor r12, r12, r12
96 xor r13, r13, r13
97 xor r14, r14, r14
98 xor r15, r15, r15
99 xor r16, r16, r16
100 xor r17, r17, r17
101 xor r18, r18, r18
102 xor r19, r19, r19
103 xor r20, r20, r20
104 xor r21, r21, r21
105 xor r22, r22, r22
106 xor r23, r23, r23
107 xor r24, r24, r24
108 xor r25, r25, r25
109 xor r26, r26, r26
110 xor r27, r27, r27
111 xor r28, r28, r28
112 xor r29, r29, r29
113 xor r30, r30, r30
114 xor r31, r31, r31
115 e_lis r4, __ram_start__@h
116 e_or2i r4, __ram_start__@l
117 e_lis r5, __ram_end__@h
118 e_or2i r5, __ram_end__@l
119.cleareccloop:
120 se_cmpl r4, r5
121 se_bge .cleareccend
122 e_stmw r16, 0(r4)
123 e_addi r4, r4, 64
124 se_b .cleareccloop
125.cleareccend:
126
127 /*
128 * Branch prediction enabled.
129 */
130 e_li r3, BOOT_BUCSR_DEFAULT
131 mtspr 1013, r3 /* BUCSR */
132
133 se_blr
134#endif /* BOOT_PERFORM_CORE_INIT */
135
136 /*
137 * Exception vectors initialization.
138 */
139 .align 2
140_ivinit:
141 /* MSR initialization.*/
142 e_lis r3, BOOT_MSR_DEFAULT@h
143 e_or2i r3, BOOT_MSR_DEFAULT@l
144 mtMSR r3
145
146 /* IVPR initialization.*/
147 e_lis r3, __ivpr_base__@h
148 e_or2i r3, __ivpr_base__@l
149 mtIVPR r3
150
151 se_blr
152
153 .section .ivors, "ax"
154
155 .globl IVORS
156IVORS:
157 e_b _IVOR0
158 .align 4
159 e_b _IVOR1
160 .align 4
161 e_b _IVOR2
162 .align 4
163 e_b _IVOR3
164 .align 4
165 e_b _IVOR4
166 .align 4
167 e_b _IVOR5
168 .align 4
169 e_b _IVOR6
170 .align 4
171 e_b _IVOR7
172 .align 4
173 e_b _IVOR8
174 .align 4
175 e_b _IVOR9
176 .align 4
177 e_b _IVOR10
178 .align 4
179 e_b _IVOR11
180 .align 4
181 e_b _IVOR12
182 .align 4
183 e_b _IVOR13
184 .align 4
185 e_b _IVOR14
186 .align 4
187 e_b _IVOR15
188
189 .section .handlers, "ax"
190
191 /*
192 * Default IVOR handlers.
193 */
194 .align 2
195 .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
196 .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
197 .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
198_IVOR0:
199_IVOR1:
200_IVOR2:
201_IVOR3:
202_IVOR5:
203_IVOR6:
204_IVOR7:
205_IVOR8:
206_IVOR9:
207_IVOR11:
208_IVOR12:
209_IVOR13:
210_IVOR14:
211_IVOR15:
212 .global _unhandled_exception
213_unhandled_exception:
214 se_b _unhandled_exception
215
216#endif /* !defined(__DOXYGEN__) */
217
218/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Bxx/boot.h b/lib/chibios/os/common/startup/e200/devices/SPC560Bxx/boot.h
new file mode 100644
index 000000000..c60af003c
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Bxx/boot.h
@@ -0,0 +1,114 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file boot.h
19 * @brief Boot parameters for the SPC560Bxx.
20 * @{
21 */
22
23#ifndef BOOT_H
24#define BOOT_H
25
26/*===========================================================================*/
27/* Module constants. */
28/*===========================================================================*/
29
30/**
31 * @name BUCSR registers definitions
32 * @{
33 */
34#define BUCSR_BPEN 0x00000001
35#define BUCSR_BALLOC_BFI 0x00000200
36/** @} */
37
38/**
39 * @name MSR register definitions
40 * @{
41 */
42#define MSR_WE 0x00040000
43#define MSR_CE 0x00020000
44#define MSR_EE 0x00008000
45#define MSR_PR 0x00004000
46#define MSR_ME 0x00001000
47#define MSR_DE 0x00000200
48#define MSR_IS 0x00000020
49#define MSR_DS 0x00000010
50#define MSR_RI 0x00000002
51/** @} */
52
53/*===========================================================================*/
54/* Module pre-compile time settings. */
55/*===========================================================================*/
56
57/*
58 * BUCSR default settings.
59 */
60#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
61#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
62#endif
63
64/*
65 * MSR default settings.
66 */
67#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
68#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
69#endif
70
71/*
72 * Boot default settings.
73 */
74#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
75#define BOOT_PERFORM_CORE_INIT 1
76#endif
77
78/*
79 * VLE mode default settings.
80 */
81#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
82#define BOOT_USE_VLE 1
83#endif
84
85/*
86 * RAM relocation flag.
87 */
88#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
89#define BOOT_RELOCATE_IN_RAM 0
90#endif
91
92/*===========================================================================*/
93/* Derived constants and error checks. */
94/*===========================================================================*/
95
96/*===========================================================================*/
97/* Module data structures and types. */
98/*===========================================================================*/
99
100/*===========================================================================*/
101/* Module macros. */
102/*===========================================================================*/
103
104/*===========================================================================*/
105/* External declarations. */
106/*===========================================================================*/
107
108/*===========================================================================*/
109/* Module inline functions. */
110/*===========================================================================*/
111
112#endif /* BOOT_H */
113
114/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Bxx/intc.h b/lib/chibios/os/common/startup/e200/devices/SPC560Bxx/intc.h
new file mode 100644
index 000000000..bd2f541fe
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Bxx/intc.h
@@ -0,0 +1,93 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560Bxx/intc.h
19 * @brief SPC560Bxx INTC module header.
20 *
21 * @addtogroup INTC
22 * @{
23 */
24
25#ifndef INTC_H
26#define INTC_H
27
28/*===========================================================================*/
29/* Module constants. */
30/*===========================================================================*/
31
32/**
33 * @name INTC addresses
34 * @{
35 */
36#define INTC_BASE 0xFFF48000
37#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
38#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
39/** @} */
40
41/**
42 * @brief INTC priority levels.
43 */
44#define INTC_PRIORITY_LEVELS 16U
45
46/*===========================================================================*/
47/* Module pre-compile time settings. */
48/*===========================================================================*/
49
50/*===========================================================================*/
51/* Derived constants and error checks. */
52/*===========================================================================*/
53
54/*===========================================================================*/
55/* Module data structures and types. */
56/*===========================================================================*/
57
58/*===========================================================================*/
59/* Module macros. */
60/*===========================================================================*/
61
62/**
63 * @name INTC-related macros
64 * @{
65 */
66#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
67#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
68#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
69#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
70#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
71/** @} */
72
73/**
74 * @brief Core selection macros for PSR register.
75 */
76#define INTC_PSR_CORE0 0x00
77
78/**
79 * @brief PSR register content helper
80 */
81#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
82
83/*===========================================================================*/
84/* External declarations. */
85/*===========================================================================*/
86
87/*===========================================================================*/
88/* Module inline functions. */
89/*===========================================================================*/
90
91#endif /* INTC_H */
92
93/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Bxx/ppcparams.h b/lib/chibios/os/common/startup/e200/devices/SPC560Bxx/ppcparams.h
new file mode 100644
index 000000000..f7fcea409
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Bxx/ppcparams.h
@@ -0,0 +1,83 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560Bxx/ppcparams.h
19 * @brief PowerPC parameters for the SPC560Bxx.
20 *
21 * @defgroup PPC_SPC560Bxx SPC560Bxx Specific Parameters
22 * @ingroup PPC_SPECIFIC
23 * @details This file contains the PowerPC specific parameters for the
24 * SPC560Bxx platform.
25 * @{
26 */
27
28#ifndef PPCPARAMS_H
29#define PPCPARAMS_H
30
31/**
32 * @brief Family identification macro.
33 */
34#define PPC_SPC560Bxx
35
36/**
37 * @brief PPC core model.
38 */
39#define PPC_VARIANT PPC_VARIANT_e200z0
40
41/**
42 * @brief Number of cores.
43 */
44#define PPC_CORE_NUMBER 1
45
46/**
47 * @brief Number of writable bits in IVPR register.
48 */
49#define PPC_IVPR_BITS 20
50
51/**
52 * @brief IVORx registers support.
53 */
54#define PPC_SUPPORTS_IVORS FALSE
55
56/**
57 * @brief Book E instruction set support.
58 */
59#define PPC_SUPPORTS_BOOKE FALSE
60
61/**
62 * @brief VLE instruction set support.
63 */
64#define PPC_SUPPORTS_VLE TRUE
65
66/**
67 * @brief Supports VLS Load/Store Multiple Volatile instructions.
68 */
69#define PPC_SUPPORTS_VLE_MULTI TRUE
70
71/**
72 * @brief Supports the decrementer timer.
73 */
74#define PPC_SUPPORTS_DECREMENTER FALSE
75
76/**
77 * @brief Number of interrupt sources.
78 */
79#define PPC_NUM_VECTORS 234
80
81#endif /* PPCPARAMS_H */
82
83/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot.S b/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot.S
new file mode 100644
index 000000000..47c5a4537
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot.S
@@ -0,0 +1,218 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560Dxx/boot.s
19 * @brief SPC560Dxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if defined(__HIGHTEC__)
28#define se_bge bge
29#endif
30
31#if !defined(__DOXYGEN__)
32
33 /* BAM record.*/
34 .section .boot, "ax"
35
36 .long 0x015A0000
37 .long _reset_address
38
39 .align 2
40 .globl _reset_address
41 .type _reset_address, @function
42_reset_address:
43#if BOOT_PERFORM_CORE_INIT
44 e_bl _coreinit
45#endif
46 e_bl _ivinit
47
48#if BOOT_RELOCATE_IN_RAM
49 /*
50 * Image relocation in RAM.
51 */
52 e_lis r4, __ram_reloc_start__@h
53 e_or2i r4, __ram_reloc_start__@l
54 e_lis r5, __ram_reloc_dest__@h
55 e_or2i r5, __ram_reloc_dest__@l
56 e_lis r6, __ram_reloc_end__@h
57 e_or2i r6, __ram_reloc_end__@l
58.relloop:
59 se_cmpl r4, r6
60 se_bge .relend
61 se_lwz r7, 0(r4)
62 se_addi r4, 4
63 se_stw r7, 0(r5)
64 se_addi r5, 4
65 se_b .relloop
66.relend:
67 e_lis r3, _boot_address@h
68 e_or2i r3, _boot_address@l
69 mtctr r3
70 se_bctrl
71#else
72 e_b _boot_address
73#endif
74
75#if BOOT_PERFORM_CORE_INIT
76 .align 2
77_coreinit:
78 /*
79 * RAM clearing, this device requires a write to all RAM location in
80 * order to initialize the ECC detection hardware, this is going to
81 * slow down the startup but there is no way around.
82 */
83 xor r0, r0, r0
84 xor r1, r1, r1
85 xor r2, r2, r2
86 xor r3, r3, r3
87 xor r4, r4, r4
88 xor r5, r5, r5
89 xor r6, r6, r6
90 xor r7, r7, r7
91 xor r8, r8, r8
92 xor r9, r9, r9
93 xor r10, r10, r10
94 xor r11, r11, r11
95 xor r12, r12, r12
96 xor r13, r13, r13
97 xor r14, r14, r14
98 xor r15, r15, r15
99 xor r16, r16, r16
100 xor r17, r17, r17
101 xor r18, r18, r18
102 xor r19, r19, r19
103 xor r20, r20, r20
104 xor r21, r21, r21
105 xor r22, r22, r22
106 xor r23, r23, r23
107 xor r24, r24, r24
108 xor r25, r25, r25
109 xor r26, r26, r26
110 xor r27, r27, r27
111 xor r28, r28, r28
112 xor r29, r29, r29
113 xor r30, r30, r30
114 xor r31, r31, r31
115 e_lis r4, __ram_start__@h
116 e_or2i r4, __ram_start__@l
117 e_lis r5, __ram_end__@h
118 e_or2i r5, __ram_end__@l
119.cleareccloop:
120 se_cmpl r4, r5
121 se_bge .cleareccend
122 e_stmw r16, 0(r4)
123 e_addi r4, r4, 64
124 se_b .cleareccloop
125.cleareccend:
126
127 /*
128 * Branch prediction enabled.
129 */
130 e_li r3, BOOT_BUCSR_DEFAULT
131 mtspr 1013, r3 /* BUCSR */
132
133 se_blr
134#endif /* BOOT_PERFORM_CORE_INIT */
135
136 /*
137 * Exception vectors initialization.
138 */
139 .align 2
140_ivinit:
141 /* MSR initialization.*/
142 e_lis r3, BOOT_MSR_DEFAULT@h
143 e_or2i r3, BOOT_MSR_DEFAULT@l
144 mtMSR r3
145
146 /* IVPR initialization.*/
147 e_lis r3, __ivpr_base__@h
148 e_or2i r3, __ivpr_base__@l
149 mtIVPR r3
150
151 se_blr
152
153 .section .ivors, "ax"
154
155 .globl IVORS
156IVORS:
157 e_b _IVOR0
158 .align 4
159 e_b _IVOR1
160 .align 4
161 e_b _IVOR2
162 .align 4
163 e_b _IVOR3
164 .align 4
165 e_b _IVOR4
166 .align 4
167 e_b _IVOR5
168 .align 4
169 e_b _IVOR6
170 .align 4
171 e_b _IVOR7
172 .align 4
173 e_b _IVOR8
174 .align 4
175 e_b _IVOR9
176 .align 4
177 e_b _IVOR10
178 .align 4
179 e_b _IVOR11
180 .align 4
181 e_b _IVOR12
182 .align 4
183 e_b _IVOR13
184 .align 4
185 e_b _IVOR14
186 .align 4
187 e_b _IVOR15
188
189 .section .handlers, "ax"
190
191 /*
192 * Default IVOR handlers.
193 */
194 .align 2
195 .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
196 .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
197 .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
198_IVOR0:
199_IVOR1:
200_IVOR2:
201_IVOR3:
202_IVOR5:
203_IVOR6:
204_IVOR7:
205_IVOR8:
206_IVOR9:
207_IVOR11:
208_IVOR12:
209_IVOR13:
210_IVOR14:
211_IVOR15:
212 .global _unhandled_exception
213_unhandled_exception:
214 e_b _unhandled_exception
215
216#endif /* !defined(__DOXYGEN__) */
217
218/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot.h b/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot.h
new file mode 100644
index 000000000..053c563db
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot.h
@@ -0,0 +1,114 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file boot.h
19 * @brief Boot parameters for the SPC560Dxx.
20 * @{
21 */
22
23#ifndef BOOT_H
24#define BOOT_H
25
26/*===========================================================================*/
27/* Module constants. */
28/*===========================================================================*/
29
30/**
31 * @name BUCSR registers definitions
32 * @{
33 */
34#define BUCSR_BPEN 0x00000001
35#define BUCSR_BALLOC_BFI 0x00000200
36/** @} */
37
38/**
39 * @name MSR register definitions
40 * @{
41 */
42#define MSR_WE 0x00040000
43#define MSR_CE 0x00020000
44#define MSR_EE 0x00008000
45#define MSR_PR 0x00004000
46#define MSR_ME 0x00001000
47#define MSR_DE 0x00000200
48#define MSR_IS 0x00000020
49#define MSR_DS 0x00000010
50#define MSR_RI 0x00000002
51/** @} */
52
53/*===========================================================================*/
54/* Module pre-compile time settings. */
55/*===========================================================================*/
56
57/*
58 * BUCSR default settings.
59 */
60#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
61#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
62#endif
63
64/*
65 * MSR default settings.
66 */
67#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
68#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
69#endif
70
71/*
72 * Boot default settings.
73 */
74#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
75#define BOOT_PERFORM_CORE_INIT 1
76#endif
77
78/*
79 * VLE mode default settings.
80 */
81#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
82#define BOOT_USE_VLE 1
83#endif
84
85/*
86 * RAM relocation flag.
87 */
88#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
89#define BOOT_RELOCATE_IN_RAM 0
90#endif
91
92/*===========================================================================*/
93/* Derived constants and error checks. */
94/*===========================================================================*/
95
96/*===========================================================================*/
97/* Module data structures and types. */
98/*===========================================================================*/
99
100/*===========================================================================*/
101/* Module macros. */
102/*===========================================================================*/
103
104/*===========================================================================*/
105/* External declarations. */
106/*===========================================================================*/
107
108/*===========================================================================*/
109/* Module inline functions. */
110/*===========================================================================*/
111
112#endif /* BOOT_H */
113
114/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot_cw.s b/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot_cw.s
new file mode 100644
index 000000000..499fc7189
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot_cw.s
@@ -0,0 +1,200 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560Dxx/boot.s
19 * @brief SPC560Dxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if !defined(__DOXYGEN__)
28
29 .extern _boot_address
30 .extern __ram_start__
31 .extern __ram_end__
32 .extern __ivpr_base__
33
34 .extern _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
35 .extern _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
36 .extern _IVOR12, _IVOR13, _IVOR14, _IVOR15
37
38 /* BAM record.*/
39 .section .boot, 16
40
41 .long 0x015A0000
42 .long _reset_address
43
44 .align 4
45 .globl _reset_address
46 .type _reset_address, @function
47_reset_address:
48#if BOOT_PERFORM_CORE_INIT
49 se_bl _coreinit
50#endif
51 se_bl _ivinit
52
53#if BOOT_RELOCATE_IN_RAM
54 /*
55 * Image relocation in RAM.
56 */
57 e_lis r4, __ram_reloc_start__@h
58 e_or2i r4, r4, __ram_reloc_start__@l
59 e_lis r5, __ram_reloc_dest__@h
60 e_or2i r5, r5, __ram_reloc_dest__@l
61 e_lis r6, __ram_reloc_end__@h
62 e_or2i r6, r6, __ram_reloc_end__@l
63.relloop:
64 se_cmpl r4, r6
65 se_bge .relend
66 se_lwz r7, 0(r4)
67 se_addi r4, 4
68 se_stw r7, 0(r5)
69 se_addi r5, 4
70 se_b .relloop
71.relend:
72 e_lis r3, _boot_address@h
73 e_or2i r3, _boot_address@l
74 mtctr r3
75 se_bctrl
76#else
77 e_b _boot_address
78#endif
79
80#if BOOT_PERFORM_CORE_INIT
81 .align 4
82_coreinit:
83 /*
84 * RAM clearing, this device requires a write to all RAM location in
85 * order to initialize the ECC detection hardware, this is going to
86 * slow down the startup but there is no way around.
87 */
88 xor r0, r0, r0
89 xor r1, r1, r1
90 xor r2, r2, r2
91 xor r3, r3, r3
92 xor r4, r4, r4
93 xor r5, r5, r5
94 xor r6, r6, r6
95 xor r7, r7, r7
96 xor r8, r8, r8
97 xor r9, r9, r9
98 xor r10, r10, r10
99 xor r11, r11, r11
100 xor r12, r12, r12
101 xor r13, r13, r13
102 xor r14, r14, r14
103 xor r15, r15, r15
104 xor r16, r16, r16
105 xor r17, r17, r17
106 xor r18, r18, r18
107 xor r19, r19, r19
108 xor r20, r20, r20
109 xor r21, r21, r21
110 xor r22, r22, r22
111 xor r23, r23, r23
112 xor r24, r24, r24
113 xor r25, r25, r25
114 xor r26, r26, r26
115 xor r27, r27, r27
116 xor r28, r28, r28
117 xor r29, r29, r29
118 xor r30, r30, r30
119 xor r31, r31, r31
120 e_lis r4, __ram_start__@h
121 e_or2i r4, __ram_start__@l
122 e_lis r5, __ram_end__@h
123 e_or2i r5, __ram_end__@l
124.cleareccloop:
125 se_cmpl r4, r5
126 se_bge .cleareccend
127 e_stmw r16, 0(r4)
128 e_addi r4, r4, 64
129 se_b .cleareccloop
130.cleareccend:
131
132 /*
133 * Branch prediction enabled.
134 */
135 e_li r3, BOOT_BUCSR_DEFAULT
136 mtspr 1013, r3 /* BUCSR */
137
138 se_blr
139#endif /* BOOT_PERFORM_CORE_INIT */
140
141 /*
142 * Exception vectors initialization.
143 */
144 .align 4
145_ivinit:
146 /* MSR initialization.*/
147 e_lis r3, BOOT_MSR_DEFAULT@h
148 e_ori r3, r3, BOOT_MSR_DEFAULT@l
149 mtMSR r3
150
151 /* IVPR initialization.*/
152 e_lis r3, __ivpr_base__@h
153 e_or2i r3, __ivpr_base__@l
154 mtIVPR r3
155
156 se_blr
157
158 .section .ivors, text_vle
159 .align 16
160 .globl IVORS
161IVORS:
162 e_b _IVOR0
163 .align 16
164 e_b _IVOR1
165 .align 16
166 e_b _IVOR2
167 .align 16
168 e_b _IVOR3
169 .align 16
170 e_b _IVOR4
171 .align 16
172 e_b _IVOR5
173 .align 16
174 e_b _IVOR6
175 .align 16
176 e_b _IVOR7
177 .align 16
178 e_b _IVOR8
179 .align 16
180 e_b _IVOR9
181 .align 16
182 e_b _IVOR10
183 .align 16
184 e_b _IVOR11
185 .align 16
186 e_b _IVOR12
187 .align 16
188 e_b _IVOR13
189 .align 16
190 e_b _IVOR14
191 .align 16
192 e_b _IVOR15
193
194 .section .handlers, text_vle
195 .align 16
196
197
198#endif /* !defined(__DOXYGEN__) */
199
200/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot_ghs.s b/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot_ghs.s
new file mode 100644
index 000000000..2ab167c13
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/boot_ghs.s
@@ -0,0 +1,216 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560Dxx/boot_ghs.s
19 * @brief SPC560Dxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if !defined(__DOXYGEN__)
28
29 .vle
30
31 /* BAM record.*/
32 .section .boot, "axv"
33
34 .long 0x015A0000
35 .long _reset_address
36
37 .align 2
38 .globl _reset_address
39 .type _reset_address, @function
40_reset_address:
41#if BOOT_PERFORM_CORE_INIT
42 e_bl _coreinit
43#endif
44 e_bl _ivinit
45
46#if BOOT_RELOCATE_IN_RAM
47 /*
48 * Image relocation in RAM.
49 */
50 e_lis r4, __ram_reloc_start__@h
51 e_or2i r4, __ram_reloc_start__@l
52 e_lis r5, __ram_reloc_dest__@h
53 e_or2i r5, __ram_reloc_dest__@l
54 e_lis r6, __ram_reloc_end__@h
55 e_or2i r6, __ram_reloc_end__@l
56.relloop:
57 se_cmpl r4, r6
58 se_bge .relend
59 se_lwz r7, 0(r4)
60 se_addi r4, 4
61 se_stw r7, 0(r5)
62 se_addi r5, 4
63 se_b .relloop
64.relend:
65 e_lis r3, _boot_address@h
66 e_or2i r3, _boot_address@l
67 mtctr r3
68 se_bctrl
69#else
70 e_b _boot_address
71#endif
72
73#if BOOT_PERFORM_CORE_INIT
74 .align 2
75_coreinit:
76 /*
77 * RAM clearing, this device requires a write to all RAM location in
78 * order to initialize the ECC detection hardware, this is going to
79 * slow down the startup but there is no way around.
80 */
81 xor r0, r0, r0
82 xor r1, r1, r1
83 xor r2, r2, r2
84 xor r3, r3, r3
85 xor r4, r4, r4
86 xor r5, r5, r5
87 xor r6, r6, r6
88 xor r7, r7, r7
89 xor r8, r8, r8
90 xor r9, r9, r9
91 xor r10, r10, r10
92 xor r11, r11, r11
93 xor r12, r12, r12
94 xor r13, r13, r13
95 xor r14, r14, r14
96 xor r15, r15, r15
97 xor r16, r16, r16
98 xor r17, r17, r17
99 xor r18, r18, r18
100 xor r19, r19, r19
101 xor r20, r20, r20
102 xor r21, r21, r21
103 xor r22, r22, r22
104 xor r23, r23, r23
105 xor r24, r24, r24
106 xor r25, r25, r25
107 xor r26, r26, r26
108 xor r27, r27, r27
109 xor r28, r28, r28
110 xor r29, r29, r29
111 xor r30, r30, r30
112 xor r31, r31, r31
113 e_lis r4, __ram_start__@h
114 e_or2i r4, __ram_start__@l
115 e_lis r5, __ram_end__@h
116 e_or2i r5, __ram_end__@l
117.cleareccloop:
118 se_cmpl r4, r5
119 se_bge .cleareccend
120 e_stmw r16, 0(r4)
121 e_addi r4, r4, 64
122 se_b .cleareccloop
123.cleareccend:
124
125 /*
126 * Branch prediction enabled.
127 */
128 e_li r3, BOOT_BUCSR_DEFAULT
129 mtspr 1013, r3 /* BUCSR */
130
131 se_blr
132#endif /* BOOT_PERFORM_CORE_INIT */
133
134 /*
135 * Exception vectors initialization.
136 */
137 .align 2
138_ivinit:
139 /* MSR initialization.*/
140 e_lis r3, BOOT_MSR_DEFAULT@h
141 e_or2i r3, BOOT_MSR_DEFAULT@l
142 mtMSR r3
143
144 /* IVPR initialization.*/
145 e_lis r3, __ivpr_base__@h
146 e_or2i r3, __ivpr_base__@l
147 mtIVPR r3
148
149 se_blr
150
151 .section .ivors, "axv"
152
153 .globl IVORS
154IVORS:
155 e_b _IVOR0
156 .align 4
157 e_b _IVOR1
158 .align 4
159 e_b _IVOR2
160 .align 4
161 e_b _IVOR3
162 .align 4
163 e_b _IVOR4
164 .align 4
165 e_b _IVOR5
166 .align 4
167 e_b _IVOR6
168 .align 4
169 e_b _IVOR7
170 .align 4
171 e_b _IVOR8
172 .align 4
173 e_b _IVOR9
174 .align 4
175 e_b _IVOR10
176 .align 4
177 e_b _IVOR11
178 .align 4
179 e_b _IVOR12
180 .align 4
181 e_b _IVOR13
182 .align 4
183 e_b _IVOR14
184 .align 4
185 e_b _IVOR15
186
187 .section .handlers, "axv"
188
189 /*
190 * Default IVOR handlers.
191 */
192 .align 2
193 .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
194 .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
195 .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
196_IVOR0:
197_IVOR1:
198_IVOR2:
199_IVOR3:
200_IVOR5:
201_IVOR6:
202_IVOR7:
203_IVOR8:
204_IVOR9:
205_IVOR11:
206_IVOR12:
207_IVOR13:
208_IVOR14:
209_IVOR15:
210 .global _unhandled_exception
211_unhandled_exception:
212 e_b _unhandled_exception
213
214#endif /* !defined(__DOXYGEN__) */
215
216/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/intc.h b/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/intc.h
new file mode 100644
index 000000000..d507b3611
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/intc.h
@@ -0,0 +1,93 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560Dxx/intc.h
19 * @brief SPC560Dxx INTC module header.
20 *
21 * @addtogroup INTC
22 * @{
23 */
24
25#ifndef INTC_H
26#define INTC_H
27
28/*===========================================================================*/
29/* Module constants. */
30/*===========================================================================*/
31
32/**
33 * @name INTC addresses
34 * @{
35 */
36#define INTC_BASE 0xFFF48000
37#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
38#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
39/** @} */
40
41/**
42 * @brief INTC priority levels.
43 */
44#define INTC_PRIORITY_LEVELS 16U
45
46/*===========================================================================*/
47/* Module pre-compile time settings. */
48/*===========================================================================*/
49
50/*===========================================================================*/
51/* Derived constants and error checks. */
52/*===========================================================================*/
53
54/*===========================================================================*/
55/* Module data structures and types. */
56/*===========================================================================*/
57
58/*===========================================================================*/
59/* Module macros. */
60/*===========================================================================*/
61
62/**
63 * @name INTC-related macros
64 * @{
65 */
66#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
67#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
68#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
69#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
70#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
71/** @} */
72
73/**
74 * @brief Core selection macros for PSR register.
75 */
76#define INTC_PSR_CORE0 0x00
77
78/**
79 * @brief PSR register content helper
80 */
81#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
82
83/*===========================================================================*/
84/* External declarations. */
85/*===========================================================================*/
86
87/*===========================================================================*/
88/* Module inline functions. */
89/*===========================================================================*/
90
91#endif /* INTC_H */
92
93/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/ppcparams.h b/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/ppcparams.h
new file mode 100644
index 000000000..1bb5ac4b7
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Dxx/ppcparams.h
@@ -0,0 +1,83 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560Dxx/ppcparams.h
19 * @brief PowerPC parameters for the SPC560Dxx.
20 *
21 * @defgroup PPC_SPC560Dxx SPC560Dxx Specific Parameters
22 * @ingroup PPC_SPECIFIC
23 * @details This file contains the PowerPC specific parameters for the
24 * SPC560Dxx platform.
25 * @{
26 */
27
28#ifndef PPCPARAMS_H
29#define PPCPARAMS_H
30
31/**
32 * @brief Family identification macro.
33 */
34#define PPC_SPC560Dxx
35
36/**
37 * @brief PPC core model.
38 */
39#define PPC_VARIANT PPC_VARIANT_e200z0
40
41/**
42 * @brief Number of cores.
43 */
44#define PPC_CORE_NUMBER 1
45
46/**
47 * @brief Number of writable bits in IVPR register.
48 */
49#define PPC_IVPR_BITS 20
50
51/**
52 * @brief IVORx registers support.
53 */
54#define PPC_SUPPORTS_IVORS FALSE
55
56/**
57 * @brief Book E instruction set support.
58 */
59#define PPC_SUPPORTS_BOOKE FALSE
60
61/**
62 * @brief VLE instruction set support.
63 */
64#define PPC_SUPPORTS_VLE TRUE
65
66/**
67 * @brief Supports VLS Load/Store Multiple Volatile instructions.
68 */
69#define PPC_SUPPORTS_VLE_MULTI TRUE
70
71/**
72 * @brief Supports the decrementer timer.
73 */
74#define PPC_SUPPORTS_DECREMENTER FALSE
75
76/**
77 * @brief Number of interrupt sources.
78 */
79#define PPC_NUM_VECTORS 155
80
81#endif /* PPCPARAMS_H */
82
83/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.S b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.S
new file mode 100644
index 000000000..4d16c7ac6
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.S
@@ -0,0 +1,218 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560Pxx/boot.s
19 * @brief SPC560Pxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if defined(__HIGHTEC__)
28#define se_bge bge
29#endif
30
31#if !defined(__DOXYGEN__)
32
33 /* BAM record.*/
34 .section .boot, "ax"
35
36 .long 0x015A0000
37 .long _reset_address
38
39 .align 2
40 .globl _reset_address
41 .type _reset_address, @function
42_reset_address:
43#if BOOT_PERFORM_CORE_INIT
44 e_bl _coreinit
45#endif
46 e_bl _ivinit
47
48#if BOOT_RELOCATE_IN_RAM
49 /*
50 * Image relocation in RAM.
51 */
52 e_lis r4, __ram_reloc_start__@h
53 e_or2i r4, __ram_reloc_start__@l
54 e_lis r5, __ram_reloc_dest__@h
55 e_or2i r5, __ram_reloc_dest__@l
56 e_lis r6, __ram_reloc_end__@h
57 e_or2i r6, r6, __ram_reloc_end__@l
58.relloop:
59 se_cmpl r4, r6
60 se_bge .relend
61 se_lwz r7, 0(r4)
62 se_addi r4, 4
63 se_stw r7, 0(r5)
64 se_addi r5, 4
65 se_b .relloop
66.relend:
67 e_lis r3, _boot_address@h
68 e_or2i r3, _boot_address@l
69 mtctr r3
70 se_bctrl
71#else
72 e_b _boot_address
73#endif
74
75#if BOOT_PERFORM_CORE_INIT
76 .align 2
77_coreinit:
78 /*
79 * RAM clearing, this device requires a write to all RAM location in
80 * order to initialize the ECC detection hardware, this is going to
81 * slow down the startup but there is no way around.
82 */
83 xor r0, r0, r0
84 xor r1, r1, r1
85 xor r2, r2, r2
86 xor r3, r3, r3
87 xor r4, r4, r4
88 xor r5, r5, r5
89 xor r6, r6, r6
90 xor r7, r7, r7
91 xor r8, r8, r8
92 xor r9, r9, r9
93 xor r10, r10, r10
94 xor r11, r11, r11
95 xor r12, r12, r12
96 xor r13, r13, r13
97 xor r14, r14, r14
98 xor r15, r15, r15
99 xor r16, r16, r16
100 xor r17, r17, r17
101 xor r18, r18, r18
102 xor r19, r19, r19
103 xor r20, r20, r20
104 xor r21, r21, r21
105 xor r22, r22, r22
106 xor r23, r23, r23
107 xor r24, r24, r24
108 xor r25, r25, r25
109 xor r26, r26, r26
110 xor r27, r27, r27
111 xor r28, r28, r28
112 xor r29, r29, r29
113 xor r30, r30, r30
114 xor r31, r31, r31
115 e_lis r4, __ram_start__@h
116 e_or2i r4, __ram_start__@l
117 e_lis r5, __ram_end__@h
118 e_or2i r5, __ram_end__@l
119.cleareccloop:
120 se_cmpl r4, r5
121 se_bge .cleareccend
122 e_stmw r16, 0(r4)
123 e_addi r4, r4, 64
124 se_b .cleareccloop
125.cleareccend:
126
127 /*
128 * Branch prediction enabled.
129 */
130 e_li r3, BOOT_BUCSR_DEFAULT
131 mtspr 1013, r3 /* BUCSR */
132
133 se_blr
134#endif /* BOOT_PERFORM_CORE_INIT */
135
136 /*
137 * Exception vectors initialization.
138 */
139 .align 2
140_ivinit:
141 /* MSR initialization.*/
142 e_lis r3, BOOT_MSR_DEFAULT@h
143 e_or2i r3, BOOT_MSR_DEFAULT@l
144 mtMSR r3
145
146 /* IVPR initialization.*/
147 e_lis r3, __ivpr_base__@h
148 e_or2i r3, __ivpr_base__@l
149 mtIVPR r3
150
151 se_blr
152
153 .section .ivors, "ax"
154
155 .globl IVORS
156IVORS:
157 e_b _IVOR0
158 .align 4
159 e_b _IVOR1
160 .align 4
161 e_b _IVOR2
162 .align 4
163 e_b _IVOR3
164 .align 4
165 e_b _IVOR4
166 .align 4
167 e_b _IVOR5
168 .align 4
169 e_b _IVOR6
170 .align 4
171 e_b _IVOR7
172 .align 4
173 e_b _IVOR8
174 .align 4
175 e_b _IVOR9
176 .align 4
177 e_b _IVOR10
178 .align 4
179 e_b _IVOR11
180 .align 4
181 e_b _IVOR12
182 .align 4
183 e_b _IVOR13
184 .align 4
185 e_b _IVOR14
186 .align 4
187 e_b _IVOR15
188
189 .section .handlers, "ax"
190
191 /*
192 * Default IVOR handlers.
193 */
194 .align 2
195 .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5
196 .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11
197 .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15
198_IVOR0:
199_IVOR1:
200_IVOR2:
201_IVOR3:
202_IVOR5:
203_IVOR6:
204_IVOR7:
205_IVOR8:
206_IVOR9:
207_IVOR11:
208_IVOR12:
209_IVOR13:
210_IVOR14:
211_IVOR15:
212 .global _unhandled_exception
213_unhandled_exception:
214 se_b _unhandled_exception
215
216#endif /* !defined(__DOXYGEN__) */
217
218/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.h b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.h
new file mode 100644
index 000000000..be9217c65
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.h
@@ -0,0 +1,114 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file boot.h
19 * @brief Boot parameters for the SPC560Pxx.
20 * @{
21 */
22
23#ifndef BOOT_H
24#define BOOT_H
25
26/*===========================================================================*/
27/* Module constants. */
28/*===========================================================================*/
29
30/**
31 * @name BUCSR registers definitions
32 * @{
33 */
34#define BUCSR_BPEN 0x00000001
35#define BUCSR_BALLOC_BFI 0x00000200
36/** @} */
37
38/**
39 * @name MSR register definitions
40 * @{
41 */
42#define MSR_WE 0x00040000
43#define MSR_CE 0x00020000
44#define MSR_EE 0x00008000
45#define MSR_PR 0x00004000
46#define MSR_ME 0x00001000
47#define MSR_DE 0x00000200
48#define MSR_IS 0x00000020
49#define MSR_DS 0x00000010
50#define MSR_RI 0x00000002
51/** @} */
52
53/*===========================================================================*/
54/* Module pre-compile time settings. */
55/*===========================================================================*/
56
57/*
58 * BUCSR default settings.
59 */
60#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
61#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
62#endif
63
64/*
65 * MSR default settings.
66 */
67#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
68#define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME)
69#endif
70
71/*
72 * Boot default settings.
73 */
74#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
75#define BOOT_PERFORM_CORE_INIT 1
76#endif
77
78/*
79 * VLE mode default settings.
80 */
81#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
82#define BOOT_USE_VLE 1
83#endif
84
85/*
86 * RAM relocation flag.
87 */
88#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
89#define BOOT_RELOCATE_IN_RAM 0
90#endif
91
92/*===========================================================================*/
93/* Derived constants and error checks. */
94/*===========================================================================*/
95
96/*===========================================================================*/
97/* Module data structures and types. */
98/*===========================================================================*/
99
100/*===========================================================================*/
101/* Module macros. */
102/*===========================================================================*/
103
104/*===========================================================================*/
105/* External declarations. */
106/*===========================================================================*/
107
108/*===========================================================================*/
109/* Module inline functions. */
110/*===========================================================================*/
111
112#endif /* BOOT_H */
113
114/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/intc.h b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/intc.h
new file mode 100644
index 000000000..c47cb5b8d
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/intc.h
@@ -0,0 +1,93 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560Pxx/intc.h
19 * @brief SPC560Pxx INTC module header.
20 *
21 * @addtogroup INTC
22 * @{
23 */
24
25#ifndef INTC_H
26#define INTC_H
27
28/*===========================================================================*/
29/* Module constants. */
30/*===========================================================================*/
31
32/**
33 * @name INTC addresses
34 * @{
35 */
36#define INTC_BASE 0xFFF48000
37#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
38#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
39/** @} */
40
41/**
42 * @brief INTC priority levels.
43 */
44#define INTC_PRIORITY_LEVELS 16U
45
46/*===========================================================================*/
47/* Module pre-compile time settings. */
48/*===========================================================================*/
49
50/*===========================================================================*/
51/* Derived constants and error checks. */
52/*===========================================================================*/
53
54/*===========================================================================*/
55/* Module data structures and types. */
56/*===========================================================================*/
57
58/*===========================================================================*/
59/* Module macros. */
60/*===========================================================================*/
61
62/**
63 * @name INTC-related macros
64 * @{
65 */
66#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
67#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
68#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
69#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
70#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
71/** @} */
72
73/**
74 * @brief Core selection macros for PSR register.
75 */
76#define INTC_PSR_CORE0 0x00
77
78/**
79 * @brief PSR register content helper
80 */
81#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
82
83/*===========================================================================*/
84/* External declarations. */
85/*===========================================================================*/
86
87/*===========================================================================*/
88/* Module inline functions. */
89/*===========================================================================*/
90
91#endif /* INTC_H */
92
93/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/ppcparams.h b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/ppcparams.h
new file mode 100644
index 000000000..1a6fb998d
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/ppcparams.h
@@ -0,0 +1,83 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC560Pxx/ppcparams.h
19 * @brief PowerPC parameters for the SPC560Pxx.
20 *
21 * @defgroup PPC_SPC560Pxx SPC560Pxx Specific Parameters
22 * @ingroup PPC_SPECIFIC
23 * @details This file contains the PowerPC specific parameters for the
24 * SPC560Pxx platform.
25 * @{
26 */
27
28#ifndef PPCPARAMS_H
29#define PPCPARAMS_H
30
31/**
32 * @brief Family identification macro.
33 */
34#define PPC_SPC560Pxx
35
36/**
37 * @brief PPC core model.
38 */
39#define PPC_VARIANT PPC_VARIANT_e200z0
40
41/**
42 * @brief Number of cores.
43 */
44#define PPC_CORE_NUMBER 1
45
46/**
47 * @brief Number of writable bits in IVPR register.
48 */
49#define PPC_IVPR_BITS 20
50
51/**
52 * @brief IVORx registers support.
53 */
54#define PPC_SUPPORTS_IVORS FALSE
55
56/**
57 * @brief Book E instruction set support.
58 */
59#define PPC_SUPPORTS_BOOKE FALSE
60
61/**
62 * @brief VLE instruction set support.
63 */
64#define PPC_SUPPORTS_VLE TRUE
65
66/**
67 * @brief Supports VLS Load/Store Multiple Volatile instructions.
68 */
69#define PPC_SUPPORTS_VLE_MULTI TRUE
70
71/**
72 * @brief Supports the decrementer timer.
73 */
74#define PPC_SUPPORTS_DECREMENTER FALSE
75
76/**
77 * @brief Number of interrupt sources.
78 */
79#define PPC_NUM_VECTORS 261
80
81#endif /* PPCPARAMS_H */
82
83/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC563Mxx/boot.S b/lib/chibios/os/common/startup/e200/devices/SPC563Mxx/boot.S
new file mode 100644
index 000000000..c59fc095b
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC563Mxx/boot.S
@@ -0,0 +1,192 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC563Mxx/boot.s
19 * @brief SPC563Mxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if defined(__HIGHTEC__)
28#define se_bge bge
29#endif
30
31#if !defined(__DOXYGEN__)
32
33 /* BAM record.*/
34 .section .boot, "ax"
35
36#if BOOT_USE_VLE
37 .long 0x015A0000
38#else
39 .long 0x005A0000
40#endif
41 .long _reset_address
42
43 .align 2
44 .globl _reset_address
45 .type _reset_address, @function
46_reset_address:
47#if BOOT_PERFORM_CORE_INIT
48 e_bl _coreinit
49#endif
50 e_bl _ivinit
51
52#if BOOT_RELOCATE_IN_RAM
53 /*
54 * Image relocation in RAM.
55 */
56 e_lis r4, __ram_reloc_start__@h
57 e_or2i r4, __ram_reloc_start__@l
58 e_lis r5, __ram_reloc_dest__@h
59 e_or2i r5, __ram_reloc_dest__@l
60 e_lis r6, __ram_reloc_end__@h
61 e_or2i r6, r6, __ram_reloc_end__@l
62.relloop:
63 se_cmpl r4, r6
64 se_bge .relend
65 se_lwz r7, 0(r4)
66 se_addi r4, 4
67 se_stw r7, 0(r5)
68 se_addi r5, 4
69 se_b .relloop
70.relend:
71 e_lis r3, _boot_address@h
72 e_or2i r3, _boot_address@l
73 mtctr r3
74 se_bctrl
75#else
76 e_b _boot_address
77#endif
78
79#if BOOT_PERFORM_CORE_INIT
80 .align 2
81_coreinit:
82 /*
83 * RAM clearing, this device requires a write to all RAM location in
84 * order to initialize the ECC detection hardware, this is going to
85 * slow down the startup but there is no way around.
86 */
87 xor r0, r0, r0
88 xor r1, r1, r1
89 xor r2, r2, r2
90 xor r3, r3, r3
91 xor r4, r4, r4
92 xor r5, r5, r5
93 xor r6, r6, r6
94 xor r7, r7, r7
95 xor r8, r8, r8
96 xor r9, r9, r9
97 xor r10, r10, r10
98 xor r11, r11, r11
99 xor r12, r12, r12
100 xor r13, r13, r13
101 xor r14, r14, r14
102 xor r15, r15, r15
103 xor r16, r16, r16
104 xor r17, r17, r17
105 xor r18, r18, r18
106 xor r19, r19, r19
107 xor r20, r20, r20
108 xor r21, r21, r21
109 xor r22, r22, r22
110 xor r23, r23, r23
111 xor r24, r24, r24
112 xor r25, r25, r25
113 xor r26, r26, r26
114 xor r27, r27, r27
115 xor r28, r28, r28
116 xor r29, r29, r29
117 xor r30, r30, r30
118 xor r31, r31, r31
119 e_lis r4, __ram_start__@h
120 e_or2i r4, __ram_start__@l
121 e_lis r5, __ram_end__@h
122 e_or2i r5, __ram_end__@l
123.cleareccloop:
124 se_cmpl r4, r5
125 se_bge .cleareccend
126 e_stmw r16, 0(r4)
127 e_addi r4, r4, 64
128 se_b .cleareccloop
129.cleareccend:
130
131 /*
132 * Branch prediction enabled.
133 */
134 e_li r3, BOOT_BUCSR_DEFAULT
135 mtspr 1013, r3 /* BUCSR */
136
137 se_blr
138#endif /* BOOT_PERFORM_CORE_INIT */
139
140 /*
141 * Exception vectors initialization.
142 */
143_ivinit:
144 /* MSR initialization.*/
145 e_lis r3, BOOT_MSR_DEFAULT@h
146 e_or2i r3, BOOT_MSR_DEFAULT@l
147 mtMSR r3
148
149 /* IVPR initialization.*/
150 e_lis r3, __ivpr_base__@h
151 e_or2i r3, __ivpr_base__@l
152 mtIVPR r3
153
154 /* IVORs initialization.*/
155 e_lis r3, _unhandled_exception@h
156 e_or2i r3, _unhandled_exception@l
157
158 mtspr 400, r3 /* IVOR0-15 */
159 mtspr 401, r3
160 mtspr 402, r3
161 mtspr 403, r3
162 mtspr 404, r3
163 mtspr 405, r3
164 mtspr 406, r3
165 mtspr 407, r3
166 mtspr 408, r3
167 mtspr 409, r3
168 mtspr 410, r3
169 mtspr 411, r3
170 mtspr 412, r3
171 mtspr 413, r3
172 mtspr 414, r3
173 mtspr 415, r3
174 mtspr 528, r3 /* IVOR32-34 */
175 mtspr 529, r3
176 mtspr 530, r3
177
178 se_blr
179
180 .section .handlers, "ax"
181
182 /*
183 * Unhandled exceptions handler.
184 */
185 .weak _unhandled_exception
186 .type _unhandled_exception, @function
187_unhandled_exception:
188 se_b _unhandled_exception
189
190#endif /* !defined(__DOXYGEN__) */
191
192/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC563Mxx/boot.h b/lib/chibios/os/common/startup/e200/devices/SPC563Mxx/boot.h
new file mode 100644
index 000000000..c1a298365
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC563Mxx/boot.h
@@ -0,0 +1,119 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file boot.h
19 * @brief Boot parameters for the SPC563Mxx.
20 * @{
21 */
22
23#ifndef BOOT_H
24#define BOOT_H
25
26/*===========================================================================*/
27/* Module constants. */
28/*===========================================================================*/
29
30/**
31 * @name BUCSR registers definitions
32 * @{
33 */
34#define BUCSR_BPEN 0x00000001
35#define BUCSR_BALLOC_BFI 0x00000200
36/** @} */
37
38/**
39 * @name MSR register definitions
40 * @{
41 */
42#define MSR_UCLE 0x04000000
43#define MSR_SPE 0x02000000
44#define MSR_WE 0x00040000
45#define MSR_CE 0x00020000
46#define MSR_EE 0x00008000
47#define MSR_PR 0x00004000
48#define MSR_FP 0x00002000
49#define MSR_ME 0x00001000
50#define MSR_FE0 0x00000800
51#define MSR_DE 0x00000200
52#define MSR_FE1 0x00000100
53#define MSR_IS 0x00000020
54#define MSR_DS 0x00000010
55#define MSR_RI 0x00000002
56/** @} */
57
58/*===========================================================================*/
59/* Module pre-compile time settings. */
60/*===========================================================================*/
61
62/*
63 * BUCSR default settings.
64 */
65#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
66#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI)
67#endif
68
69/*
70 * MSR default settings.
71 */
72#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
73#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
74#endif
75
76/*
77 * Boot default settings.
78 */
79#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
80#define BOOT_PERFORM_CORE_INIT 1
81#endif
82
83/*
84 * VLE mode default settings.
85 */
86#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
87#define BOOT_USE_VLE 1
88#endif
89
90/*
91 * RAM relocation flag.
92 */
93#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
94#define BOOT_RELOCATE_IN_RAM 0
95#endif
96
97/*===========================================================================*/
98/* Derived constants and error checks. */
99/*===========================================================================*/
100
101/*===========================================================================*/
102/* Module data structures and types. */
103/*===========================================================================*/
104
105/*===========================================================================*/
106/* Module macros. */
107/*===========================================================================*/
108
109/*===========================================================================*/
110/* External declarations. */
111/*===========================================================================*/
112
113/*===========================================================================*/
114/* Module inline functions. */
115/*===========================================================================*/
116
117#endif /* BOOT_H */
118
119/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC563Mxx/intc.h b/lib/chibios/os/common/startup/e200/devices/SPC563Mxx/intc.h
new file mode 100644
index 000000000..5578deea6
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC563Mxx/intc.h
@@ -0,0 +1,93 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC563Mxx/intc.h
19 * @brief SPC563Mxx INTC module header.
20 *
21 * @addtogroup INTC
22 * @{
23 */
24
25#ifndef INTC_H
26#define INTC_H
27
28/*===========================================================================*/
29/* Module constants. */
30/*===========================================================================*/
31
32/**
33 * @name INTC addresses
34 * @{
35 */
36#define INTC_BASE 0xFFF48000
37#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
38#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
39/** @} */
40
41/**
42 * @brief INTC priority levels.
43 */
44#define INTC_PRIORITY_LEVELS 16U
45
46/*===========================================================================*/
47/* Module pre-compile time settings. */
48/*===========================================================================*/
49
50/*===========================================================================*/
51/* Derived constants and error checks. */
52/*===========================================================================*/
53
54/*===========================================================================*/
55/* Module data structures and types. */
56/*===========================================================================*/
57
58/*===========================================================================*/
59/* Module macros. */
60/*===========================================================================*/
61
62/**
63 * @name INTC-related macros
64 * @{
65 */
66#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
67#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
68#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
69#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
70#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
71/** @} */
72
73/**
74 * @brief Core selection macros for PSR register.
75 */
76#define INTC_PSR_CORE0 0x00
77
78/**
79 * @brief PSR register content helper
80 */
81#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
82
83/*===========================================================================*/
84/* External declarations. */
85/*===========================================================================*/
86
87/*===========================================================================*/
88/* Module inline functions. */
89/*===========================================================================*/
90
91#endif /* INTC_H */
92
93/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC563Mxx/ppcparams.h b/lib/chibios/os/common/startup/e200/devices/SPC563Mxx/ppcparams.h
new file mode 100644
index 000000000..350d41d26
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC563Mxx/ppcparams.h
@@ -0,0 +1,83 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC563Mxx/ppcparams.h
19 * @brief PowerPC parameters for the SPC563Mxx.
20 *
21 * @defgroup PPC_SPC563Mxx SPC563Mxx Specific Parameters
22 * @ingroup PPC_SPECIFIC
23 * @details This file contains the PowerPC specific parameters for the
24 * SPC563Mxx platform.
25 * @{
26 */
27
28#ifndef PPCPARAMS_H
29#define PPCPARAMS_H
30
31/**
32 * @brief Family identification macro.
33 */
34#define PPC_SPC563Mxx
35
36/**
37 * @brief PPC core model.
38 */
39#define PPC_VARIANT PPC_VARIANT_e200z3
40
41/**
42 * @brief Number of cores.
43 */
44#define PPC_CORE_NUMBER 1
45
46/**
47 * @brief Number of writable bits in IVPR register.
48 */
49#define PPC_IVPR_BITS 16
50
51/**
52 * @brief IVORx registers support.
53 */
54#define PPC_SUPPORTS_IVORS TRUE
55
56/**
57 * @brief Book E instruction set support.
58 */
59#define PPC_SUPPORTS_BOOKE TRUE
60
61/**
62 * @brief VLE instruction set support.
63 */
64#define PPC_SUPPORTS_VLE TRUE
65
66/**
67 * @brief Supports VLS Load/Store Multiple Volatile instructions.
68 */
69#define PPC_SUPPORTS_VLE_MULTI TRUE
70
71/**
72 * @brief Supports the decrementer timer.
73 */
74#define PPC_SUPPORTS_DECREMENTER TRUE
75
76/**
77 * @brief Number of interrupt sources.
78 */
79#define PPC_NUM_VECTORS 360
80
81#endif /* PPCPARAMS_H */
82
83/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC564Axx/boot.S b/lib/chibios/os/common/startup/e200/devices/SPC564Axx/boot.S
new file mode 100644
index 000000000..57b42d0f7
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC564Axx/boot.S
@@ -0,0 +1,357 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC564Axx/boot.s
19 * @brief SPC564Axx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if defined(__HIGHTEC__)
28#define se_bge bge
29#endif
30
31#if !defined(__DOXYGEN__)
32
33 /* BAM record.*/
34 .section .boot, "ax"
35
36#if BOOT_USE_VLE
37 .long 0x015A0000
38#else
39 .long 0x005A0000
40#endif
41 .long _reset_address
42
43 .align 2
44 .globl _reset_address
45 .type _reset_address, @function
46_reset_address:
47#if BOOT_PERFORM_CORE_INIT
48 e_bl _coreinit
49#endif
50 e_bl _ivinit
51
52#if BOOT_RELOCATE_IN_RAM
53 /*
54 * Image relocation in RAM.
55 */
56 e_lis r4, __ram_reloc_start__@h
57 e_or2i r4, __ram_reloc_start__@l
58 e_lis r5, __ram_reloc_dest__@h
59 e_or2i r5, __ram_reloc_dest__@l
60 e_lis r6, __ram_reloc_end__@h
61 e_or2i r6, r6, __ram_reloc_end__@l
62.relloop:
63 se_cmpl r4, r6
64 se_bge .relend
65 se_lwz r7, 0(r4)
66 se_addi r4, 4
67 se_stw r7, 0(r5)
68 se_addi r5, 4
69 se_b .relloop
70.relend:
71 e_lis r3, _boot_address@h
72 e_or2i r3, _boot_address@l
73 mtctr r3
74 se_bctrl
75#else
76 e_b _boot_address
77#endif
78
79#if BOOT_PERFORM_CORE_INIT
80 .align 2
81_ramcode:
82 tlbwe
83 se_isync
84 se_blr
85
86 .align 2
87_coreinit:
88 /*
89 * Invalidating all TLBs except TLB1.
90 */
91 e_lis r3, 0
92 mtspr 625, r3 /* MAS1 */
93 mtspr 626, r3 /* MAS2 */
94 mtspr 627, r3 /* MAS3 */
95 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(0))@h
96 mtspr 624, r3 /* MAS0 */
97 tlbwe
98 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
99 mtspr 624, r3 /* MAS0 */
100 tlbwe
101 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
102 mtspr 624, r3 /* MAS0 */
103 tlbwe
104 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
105 mtspr 624, r3 /* MAS0 */
106 tlbwe
107 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
108 mtspr 624, r3 /* MAS0 */
109 tlbwe
110 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
111 mtspr 624, r3 /* MAS0 */
112 tlbwe
113 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
114 mtspr 624, r3 /* MAS0 */
115 tlbwe
116 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
117 mtspr 624, r3 /* MAS0 */
118 tlbwe
119 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
120 mtspr 624, r3 /* MAS0 */
121 tlbwe
122 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
123 mtspr 624, r3 /* MAS0 */
124 tlbwe
125 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
126 mtspr 624, r3 /* MAS0 */
127 tlbwe
128 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
129 mtspr 624, r3 /* MAS0 */
130 tlbwe
131 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
132 mtspr 624, r3 /* MAS0 */
133 tlbwe
134 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
135 mtspr 624, r3 /* MAS0 */
136 tlbwe
137 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
138 mtspr 624, r3 /* MAS0 */
139 tlbwe
140
141 /*
142 * TLB0 allocated to internal RAM.
143 */
144 e_lis r3, TLB0_MAS0@h
145 mtspr 624, r3 /* MAS0 */
146 e_lis r3, TLB0_MAS1@h
147 e_or2i r3, TLB0_MAS1@l
148 mtspr 625, r3 /* MAS1 */
149 e_lis r3, TLB0_MAS2@h
150 e_or2i r3, TLB0_MAS2@l
151 mtspr 626, r3 /* MAS2 */
152 e_lis r3, TLB0_MAS3@h
153 e_or2i r3, TLB0_MAS3@l
154 mtspr 627, r3 /* MAS3 */
155 tlbwe
156
157 /*
158 * TLB2 allocated to internal Peripherals Bridge A.
159 */
160 e_lis r3, TLB2_MAS0@h
161 mtspr 624, r3 /* MAS0 */
162 e_lis r3, TLB2_MAS1@h
163 e_or2i r3, TLB2_MAS1@l
164 mtspr 625, r3 /* MAS1 */
165 e_lis r3, TLB2_MAS2@h
166 e_or2i r3, TLB2_MAS2@l
167 mtspr 626, r3 /* MAS2 */
168 e_lis r3, TLB2_MAS3@h
169 e_or2i r3, TLB2_MAS3@l
170 mtspr 627, r3 /* MAS3 */
171 tlbwe
172
173 /*
174 * TLB3 allocated to internal Peripherals Bridge B.
175 */
176 e_lis r3, TLB3_MAS0@h
177 mtspr 624, r3 /* MAS0 */
178 e_lis r3, TLB3_MAS1@h
179 e_or2i r3, TLB3_MAS1@l
180 mtspr 625, r3 /* MAS1 */
181 e_lis r3, TLB3_MAS2@h
182 e_or2i r3, TLB3_MAS2@l
183 mtspr 626, r3 /* MAS2 */
184 e_lis r3, TLB3_MAS3@h
185 e_or2i r3, TLB3_MAS3@l
186 mtspr 627, r3 /* MAS3 */
187 tlbwe
188
189 /*
190 * TLB4 allocated to on-platform peripherals.
191 */
192 e_lis r3, TLB4_MAS0@h
193 mtspr 624, r3 /* MAS0 */
194 e_lis r3, TLB4_MAS1@h
195 e_or2i r3, TLB4_MAS1@l
196 mtspr 625, r3 /* MAS1 */
197 e_lis r3, TLB4_MAS2@h
198 e_or2i r3, TLB4_MAS2@l
199 mtspr 626, r3 /* MAS2 */
200 e_lis r3, TLB4_MAS3@h
201 e_or2i r3, TLB4_MAS3@l
202 mtspr 627, r3 /* MAS3 */
203 tlbwe
204
205 /*
206 * RAM clearing, this device requires a write to all RAM location in
207 * order to initialize the ECC detection hardware, this is going to
208 * slow down the startup but there is no way around.
209 */
210 xor r0, r0, r0
211 xor r1, r1, r1
212 xor r2, r2, r2
213 xor r3, r3, r3
214 xor r4, r4, r4
215 xor r5, r5, r5
216 xor r6, r6, r6
217 xor r7, r7, r7
218 xor r8, r8, r8
219 xor r9, r9, r9
220 xor r10, r10, r10
221 xor r11, r11, r11
222 xor r12, r12, r12
223 xor r13, r13, r13
224 xor r14, r14, r14
225 xor r15, r15, r15
226 xor r16, r16, r16
227 xor r17, r17, r17
228 xor r18, r18, r18
229 xor r19, r19, r19
230 xor r20, r20, r20
231 xor r21, r21, r21
232 xor r22, r22, r22
233 xor r23, r23, r23
234 xor r24, r24, r24
235 xor r25, r25, r25
236 xor r26, r26, r26
237 xor r27, r27, r27
238 xor r28, r28, r28
239 xor r29, r29, r29
240 xor r30, r30, r30
241 xor r31, r31, r31
242 e_lis r4, __ram_start__@h
243 e_or2i r4, __ram_start__@l
244 e_lis r5, __ram_end__@h
245 e_or2i r5, __ram_end__@l
246.cleareccloop:
247 se_cmpl r4, r5
248 se_bge .cleareccend
249 e_stmw r16, 0(r4)
250 e_addi r4, r4, 64
251 se_b .cleareccloop
252.cleareccend:
253
254 /*
255 * *Finally* the TLB1 is re-allocated to flash, note, the final phase
256 * is executed from RAM.
257 */
258 e_lis r3, TLB1_MAS0@h
259 mtspr 624, r3 /* MAS0 */
260 e_lis r3, TLB1_MAS1@h
261 e_or2i r3, TLB1_MAS1@l
262 mtspr 625, r3 /* MAS1 */
263 e_lis r3, TLB1_MAS2@h
264 e_or2i r3, TLB1_MAS2@l
265 mtspr 626, r3 /* MAS2 */
266 e_lis r3, TLB1_MAS3@h
267 e_or2i r3, TLB1_MAS3@l
268 mtspr 627, r3 /* MAS3 */
269 mflr r4
270 e_lis r6, _ramcode@h
271 e_or2i r6, _ramcode@l
272 e_lis r7, 0x40010000@h
273 mtctr r7
274 se_lwz r3, 0(r6)
275 se_stw r3, 0(r7)
276 se_lwz r3, 4(r6)
277 se_stw r3, 4(r7)
278 se_lwz r3, 8(r6)
279 se_stw r3, 8(r7)
280 se_bctrl
281 mtlr r4
282
283 /*
284 * Branch prediction enabled.
285 */
286 e_li r3, BOOT_BUCSR_DEFAULT
287 mtspr 1013, r3 /* BUCSR */
288
289 /*
290 * Cache invalidated and then enabled.
291 */
292 e_li r3, LICSR1_ICINV
293 mtspr 1011, r3 /* LICSR1 */
294.inv: mfspr r3, 1011 /* LICSR1 */
295 e_and2i. r3, LICSR1_ICINV
296 se_bne .inv
297 e_lis r3, BOOT_LICSR1_DEFAULT@h
298 e_or2i r3, BOOT_LICSR1_DEFAULT@l
299 mtspr 1011, r3 /* LICSR1 */
300
301 se_blr
302#endif /* BOOT_PERFORM_CORE_INIT */
303
304 /*
305 * Exception vectors initialization.
306 */
307 .align 2
308_ivinit:
309 /* MSR initialization.*/
310 e_lis r3, BOOT_MSR_DEFAULT@h
311 e_or2i r3, BOOT_MSR_DEFAULT@l
312 mtMSR r3
313
314 /* IVPR initialization.*/
315 e_lis r3, __ivpr_base__@h
316 e_or2i r3, __ivpr_base__@l
317 mtIVPR r3
318
319 /* IVORs initialization.*/
320 e_lis r3, _unhandled_exception@h
321 e_or2i r3, _unhandled_exception@l
322
323 mtspr 400, r3 /* IVOR0-15 */
324 mtspr 401, r3
325 mtspr 402, r3
326 mtspr 403, r3
327 mtspr 404, r3
328 mtspr 405, r3
329 mtspr 406, r3
330 mtspr 407, r3
331 mtspr 408, r3
332 mtspr 409, r3
333 mtspr 410, r3
334 mtspr 411, r3
335 mtspr 412, r3
336 mtspr 413, r3
337 mtspr 414, r3
338 mtspr 415, r3
339 mtspr 528, r3 /* IVOR32-34 */
340 mtspr 529, r3
341 mtspr 530, r3
342
343 se_blr
344
345 .section .handlers, "ax"
346
347 /*
348 * Unhandled exceptions handler.
349 */
350 .weak _unhandled_exception
351 .type _unhandled_exception, @function
352_unhandled_exception:
353 se_b _unhandled_exception
354
355#endif /* !defined(__DOXYGEN__) */
356
357/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC564Axx/boot.h b/lib/chibios/os/common/startup/e200/devices/SPC564Axx/boot.h
new file mode 100644
index 000000000..cb61f703c
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC564Axx/boot.h
@@ -0,0 +1,242 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file boot.h
19 * @brief Boot parameters for the SPC564Axx.
20 * @{
21 */
22
23#ifndef BOOT_H
24#define BOOT_H
25
26/*===========================================================================*/
27/* Module constants. */
28/*===========================================================================*/
29
30/**
31 * @name MASx registers definitions
32 * @{
33 */
34#define MAS0_TBLMAS_TBL 0x10000000
35#define MAS0_ESEL_MASK 0x000F0000
36#define MAS0_ESEL(n) ((n) << 16)
37
38#define MAS1_VALID 0x80000000
39#define MAS1_IPROT 0x40000000
40#define MAS1_TID_MASK 0x00FF0000
41#define MAS1_TS 0x00001000
42#define MAS1_TSISE_MASK 0x00000F80
43#define MAS1_TSISE_1K 0x00000000
44#define MAS1_TSISE_2K 0x00000080
45#define MAS1_TSISE_4K 0x00000100
46#define MAS1_TSISE_8K 0x00000180
47#define MAS1_TSISE_16K 0x00000200
48#define MAS1_TSISE_32K 0x00000280
49#define MAS1_TSISE_64K 0x00000300
50#define MAS1_TSISE_128K 0x00000380
51#define MAS1_TSISE_256K 0x00000400
52#define MAS1_TSISE_512K 0x00000480
53#define MAS1_TSISE_1M 0x00000500
54#define MAS1_TSISE_2M 0x00000580
55#define MAS1_TSISE_4M 0x00000600
56#define MAS1_TSISE_8M 0x00000680
57#define MAS1_TSISE_16M 0x00000700
58#define MAS1_TSISE_32M 0x00000780
59#define MAS1_TSISE_64M 0x00000800
60#define MAS1_TSISE_128M 0x00000880
61#define MAS1_TSISE_256M 0x00000900
62#define MAS1_TSISE_512M 0x00000980
63#define MAS1_TSISE_1G 0x00000A00
64#define MAS1_TSISE_2G 0x00000A80
65#define MAS1_TSISE_4G 0x00000B00
66
67#define MAS2_EPN_MASK 0xFFFFFC00
68#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
69#define MAS2_EBOOK 0x00000000
70#define MAS2_VLE 0x00000020
71#define MAS2_W 0x00000010
72#define MAS2_I 0x00000008
73#define MAS2_M 0x00000004
74#define MAS2_G 0x00000002
75#define MAS2_E 0x00000001
76
77#define MAS3_RPN_MASK 0xFFFFFC00
78#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
79#define MAS3_U0 0x00000200
80#define MAS3_U1 0x00000100
81#define MAS3_U2 0x00000080
82#define MAS3_U3 0x00000040
83#define MAS3_UX 0x00000020
84#define MAS3_SX 0x00000010
85#define MAS3_UW 0x00000008
86#define MAS3_SW 0x00000004
87#define MAS3_UR 0x00000002
88#define MAS3_SR 0x00000001
89/** @} */
90
91/**
92 * @name BUCSR registers definitions
93 * @{
94 */
95#define BUCSR_BPEN 0x00000001
96#define BUCSR_BPRED_MASK 0x00000006
97#define BUCSR_BPRED_0 0x00000000
98#define BUCSR_BPRED_1 0x00000002
99#define BUCSR_BPRED_2 0x00000004
100#define BUCSR_BPRED_3 0x00000006
101#define BUCSR_BALLOC_MASK 0x00000030
102#define BUCSR_BALLOC_0 0x00000000
103#define BUCSR_BALLOC_1 0x00000010
104#define BUCSR_BALLOC_2 0x00000020
105#define BUCSR_BALLOC_3 0x00000030
106#define BUCSR_BALLOC_BFI 0x00000200
107/** @} */
108
109/**
110 * @name LICSR1 registers definitions
111 * @{
112 */
113#define LICSR1_ICE 0x00000001
114#define LICSR1_ICINV 0x00000002
115#define LICSR1_ICORG 0x00000010
116/** @} */
117
118/**
119 * @name MSR register definitions
120 * @{
121 */
122#define MSR_UCLE 0x04000000
123#define MSR_SPE 0x02000000
124#define MSR_WE 0x00040000
125#define MSR_CE 0x00020000
126#define MSR_EE 0x00008000
127#define MSR_PR 0x00004000
128#define MSR_FP 0x00002000
129#define MSR_ME 0x00001000
130#define MSR_FE0 0x00000800
131#define MSR_DE 0x00000200
132#define MSR_FE1 0x00000100
133#define MSR_IS 0x00000020
134#define MSR_DS 0x00000010
135#define MSR_RI 0x00000002
136/** @} */
137
138/*===========================================================================*/
139/* Module pre-compile time settings. */
140/*===========================================================================*/
141
142/*
143 * TLB default settings.
144 */
145#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
146#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
147#define TLB0_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
148#define TLB0_MAS3 (MAS3_RPN(0x40000000) | \
149 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
150 MAS3_UR | MAS3_SR)
151
152#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
153#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
154#define TLB1_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
155#define TLB1_MAS3 (MAS3_RPN(0x00000000) | \
156 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
157 MAS3_UR | MAS3_SR)
158
159#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
160#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
161#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
162#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
163 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
164
165#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
166#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
167#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
168#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
169 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
170
171#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
172#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
173#define TLB4_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
174#define TLB4_MAS3 (MAS3_RPN(0xFFF00000) | \
175 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
176
177/*
178 * BUCSR default settings.
179 */
180#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
181#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
182 BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
183#endif
184
185/*
186 * LICSR1 default settings.
187 */
188#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
189#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
190#endif
191
192/*
193 * MSR default settings.
194 */
195#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
196#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
197#endif
198
199/*
200 * Boot default settings.
201 */
202#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
203#define BOOT_PERFORM_CORE_INIT 1
204#endif
205
206/*
207 * VLE mode default settings.
208 */
209#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
210#define BOOT_USE_VLE 1
211#endif
212
213/*
214 * RAM relocation flag.
215 */
216#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
217#define BOOT_RELOCATE_IN_RAM 0
218#endif
219
220/*===========================================================================*/
221/* Derived constants and error checks. */
222/*===========================================================================*/
223
224/*===========================================================================*/
225/* Module data structures and types. */
226/*===========================================================================*/
227
228/*===========================================================================*/
229/* Module macros. */
230/*===========================================================================*/
231
232/*===========================================================================*/
233/* External declarations. */
234/*===========================================================================*/
235
236/*===========================================================================*/
237/* Module inline functions. */
238/*===========================================================================*/
239
240#endif /* BOOT_H */
241
242/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC564Axx/intc.h b/lib/chibios/os/common/startup/e200/devices/SPC564Axx/intc.h
new file mode 100644
index 000000000..cd7a673e5
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC564Axx/intc.h
@@ -0,0 +1,93 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC564Axx/intc.h
19 * @brief SPC564Axx INTC module header.
20 *
21 * @addtogroup INTC
22 * @{
23 */
24
25#ifndef INTC_H
26#define INTC_H
27
28/*===========================================================================*/
29/* Module constants. */
30/*===========================================================================*/
31
32/**
33 * @name INTC addresses
34 * @{
35 */
36#define INTC_BASE 0xFFF48000
37#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
38#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
39/** @} */
40
41/**
42 * @brief INTC priority levels.
43 */
44#define INTC_PRIORITY_LEVELS 16U
45
46/*===========================================================================*/
47/* Module pre-compile time settings. */
48/*===========================================================================*/
49
50/*===========================================================================*/
51/* Derived constants and error checks. */
52/*===========================================================================*/
53
54/*===========================================================================*/
55/* Module data structures and types. */
56/*===========================================================================*/
57
58/*===========================================================================*/
59/* Module macros. */
60/*===========================================================================*/
61
62/**
63 * @name INTC-related macros
64 * @{
65 */
66#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
67#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
68#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
69#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
70#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
71/** @} */
72
73/**
74 * @brief Core selection macros for PSR register.
75 */
76#define INTC_PSR_CORE0 0x00
77
78/**
79 * @brief PSR register content helper
80 */
81#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
82
83/*===========================================================================*/
84/* External declarations. */
85/*===========================================================================*/
86
87/*===========================================================================*/
88/* Module inline functions. */
89/*===========================================================================*/
90
91#endif /* INTC_H */
92
93/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC564Axx/ppcparams.h b/lib/chibios/os/common/startup/e200/devices/SPC564Axx/ppcparams.h
new file mode 100644
index 000000000..35d0aaabc
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC564Axx/ppcparams.h
@@ -0,0 +1,83 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC564Axx/ppcparams.h
19 * @brief PowerPC parameters for the SPC564Axx.
20 *
21 * @defgroup PPC_SPC564Axx SPC564Axx Specific Parameters
22 * @ingroup PPC_SPECIFIC
23 * @details This file contains the PowerPC specific parameters for the
24 * SPC564Axx platform.
25 * @{
26 */
27
28#ifndef PPCPARAMS_H
29#define PPCPARAMS_H
30
31/**
32 * @brief Family identification macro.
33 */
34#define PPC_SPC564Axx
35
36/**
37 * @brief PPC core model.
38 */
39#define PPC_VARIANT PPC_VARIANT_e200z4
40
41/**
42 * @brief Number of cores.
43 */
44#define PPC_CORE_NUMBER 1
45
46/**
47 * @brief Number of writable bits in IVPR register.
48 */
49#define PPC_IVPR_BITS 16
50
51/**
52 * @brief IVORx registers support.
53 */
54#define PPC_SUPPORTS_IVORS TRUE
55
56/**
57 * @brief Book E instruction set support.
58 */
59#define PPC_SUPPORTS_BOOKE TRUE
60
61/**
62 * @brief VLE instruction set support.
63 */
64#define PPC_SUPPORTS_VLE TRUE
65
66/**
67 * @brief Supports VLS Load/Store Multiple Volatile instructions.
68 */
69#define PPC_SUPPORTS_VLE_MULTI TRUE
70
71/**
72 * @brief Supports the decrementer timer.
73 */
74#define PPC_SUPPORTS_DECREMENTER TRUE
75
76/**
77 * @brief Number of interrupt sources.
78 */
79#define PPC_NUM_VECTORS 486
80
81#endif /* PPCPARAMS_H */
82
83/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot.S b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot.S
new file mode 100644
index 000000000..83d8ce192
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot.S
@@ -0,0 +1,408 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ECxx/boot.s
19 * @brief SPC56ECxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if defined(__HIGHTEC__)
28#define se_bge bge
29#define se_bne bne
30#endif
31
32#if !defined(__DOXYGEN__)
33
34 /* BAM record.*/
35 .section .boot, "ax"
36
37#if BOOT_USE_VLE
38 .long 0x015A0000
39#else
40 .long 0x005A0000
41#endif
42 .long _reset_address
43
44 .align 2
45 .globl _reset_address
46 .type _reset_address, @function
47_reset_address:
48#if BOOT_PERFORM_CORE_INIT
49 e_bl _coreinit
50#endif
51 e_bl _ivinit
52
53#if BOOT_RELOCATE_IN_RAM
54 /*
55 * Image relocation in RAM.
56 */
57 e_lis r4, __ram_reloc_start__@h
58 e_or2i r4, __ram_reloc_start__@l
59 e_lis r5, __ram_reloc_dest__@h
60 e_or2i r5, __ram_reloc_dest__@l
61 e_lis r6, __ram_reloc_end__@h
62 e_or2i r6, r6, __ram_reloc_end__@l
63.relloop:
64 se_cmpl r4, r6
65 se_bge .relend
66 se_lwz r7, 0(r4)
67 se_addi r4, 4
68 se_stw r7, 0(r5)
69 se_addi r5, 4
70 se_b .relloop
71.relend:
72 e_lis r3, _boot_address@h
73 e_or2i r3, _boot_address@l
74 mtctr r3
75 se_bctrl
76#else
77 e_b _boot_address
78#endif
79
80#if BOOT_PERFORM_CORE_INIT
81 .align 2
82_ramcode:
83 tlbwe
84 se_isync
85 se_blr
86
87 .align 2
88_coreinit:
89 /*
90 * Invalidating all TLBs except TLB0.
91 */
92 e_lis r3, 0
93 mtspr 625, r3 /* MAS1 */
94 mtspr 626, r3 /* MAS2 */
95 mtspr 627, r3 /* MAS3 */
96 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
97 mtspr 624, r3 /* MAS0 */
98 tlbwe
99 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
100 mtspr 624, r3 /* MAS0 */
101 tlbwe
102 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
103 mtspr 624, r3 /* MAS0 */
104 tlbwe
105 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
106 mtspr 624, r3 /* MAS0 */
107 tlbwe
108 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
109 mtspr 624, r3 /* MAS0 */
110 tlbwe
111 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
112 mtspr 624, r3 /* MAS0 */
113 tlbwe
114 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
115 mtspr 624, r3 /* MAS0 */
116 tlbwe
117 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
118 mtspr 624, r3 /* MAS0 */
119 tlbwe
120 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
121 mtspr 624, r3 /* MAS0 */
122 tlbwe
123 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
124 mtspr 624, r3 /* MAS0 */
125 tlbwe
126 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
127 mtspr 624, r3 /* MAS0 */
128 tlbwe
129 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
130 mtspr 624, r3 /* MAS0 */
131 tlbwe
132 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
133 mtspr 624, r3 /* MAS0 */
134 tlbwe
135 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
136 mtspr 624, r3 /* MAS0 */
137 tlbwe
138 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
139 mtspr 624, r3 /* MAS0 */
140 tlbwe
141
142 /*
143 * TLB1 allocated to internal RAM.
144 */
145 e_lis r3, TLB1_MAS0@h
146 mtspr 624, r3 /* MAS0 */
147 e_lis r3, TLB1_MAS1@h
148 e_or2i r3, TLB1_MAS1@l
149 mtspr 625, r3 /* MAS1 */
150 e_lis r3, TLB1_MAS2@h
151 e_or2i r3, TLB1_MAS2@l
152 mtspr 626, r3 /* MAS2 */
153 e_lis r3, TLB1_MAS3@h
154 e_or2i r3, TLB1_MAS3@l
155 mtspr 627, r3 /* MAS3 */
156 tlbwe
157
158 /*
159 * TLB2 allocated to internal Peripherals Bridge A.
160 */
161 e_lis r3, TLB2_MAS0@h
162 mtspr 624, r3 /* MAS0 */
163 e_lis r3, TLB2_MAS1@h
164 e_or2i r3, TLB2_MAS1@l
165 mtspr 625, r3 /* MAS1 */
166 e_lis r3, TLB2_MAS2@h
167 e_or2i r3, TLB2_MAS2@l
168 mtspr 626, r3 /* MAS2 */
169 e_lis r3, TLB2_MAS3@h
170 e_or2i r3, TLB2_MAS3@l
171 mtspr 627, r3 /* MAS3 */
172 tlbwe
173
174 /*
175 * TLB3 allocated to internal Peripherals Bridge B.
176 */
177 e_lis r3, TLB3_MAS0@h
178 mtspr 624, r3 /* MAS0 */
179 e_lis r3, TLB3_MAS1@h
180 e_or2i r3, TLB3_MAS1@l
181 mtspr 625, r3 /* MAS1 */
182 e_lis r3, TLB3_MAS2@h
183 e_or2i r3, TLB3_MAS2@l
184 mtspr 626, r3 /* MAS2 */
185 e_lis r3, TLB3_MAS3@h
186 e_or2i r3, TLB3_MAS3@l
187 mtspr 627, r3 /* MAS3 */
188 tlbwe
189
190 /*
191 * TLB4 allocated to on-platform peripherals.
192 */
193 e_lis r3, TLB4_MAS0@h
194 mtspr 624, r3 /* MAS0 */
195 e_lis r3, TLB4_MAS1@h
196 e_or2i r3, TLB4_MAS1@l
197 mtspr 625, r3 /* MAS1 */
198 e_lis r3, TLB4_MAS2@h
199 e_or2i r3, TLB4_MAS2@l
200 mtspr 626, r3 /* MAS2 */
201 e_lis r3, TLB4_MAS3@h
202 e_or2i r3, TLB4_MAS3@l
203 mtspr 627, r3 /* MAS3 */
204 tlbwe
205
206 /*
207 * TLB5 allocated to on-platform peripherals.
208 */
209 e_lis r3, TLB5_MAS0@h
210 mtspr 624, r3 /* MAS0 */
211 e_lis r3, TLB5_MAS1@h
212 e_or2i r3, TLB5_MAS1@l
213 mtspr 625, r3 /* MAS1 */
214 e_lis r3, TLB5_MAS2@h
215 e_or2i r3, TLB5_MAS2@l
216 mtspr 626, r3 /* MAS2 */
217 e_lis r3, TLB5_MAS3@h
218 e_or2i r3, TLB5_MAS3@l
219 mtspr 627, r3 /* MAS3 */
220 tlbwe
221
222 /*
223 * RAM clearing, this device requires a write to all RAM location in
224 * order to initialize the ECC detection hardware, this is going to
225 * slow down the startup but there is no way around.
226 */
227 xor r0, r0, r0
228 xor r1, r1, r1
229 xor r2, r2, r2
230 xor r3, r3, r3
231 xor r4, r4, r4
232 xor r5, r5, r5
233 xor r6, r6, r6
234 xor r7, r7, r7
235 xor r8, r8, r8
236 xor r9, r9, r9
237 xor r10, r10, r10
238 xor r11, r11, r11
239 xor r12, r12, r12
240 xor r13, r13, r13
241 xor r14, r14, r14
242 xor r15, r15, r15
243 xor r16, r16, r16
244 xor r17, r17, r17
245 xor r18, r18, r18
246 xor r19, r19, r19
247 xor r20, r20, r20
248 xor r21, r21, r21
249 xor r22, r22, r22
250 xor r23, r23, r23
251 xor r24, r24, r24
252 xor r25, r25, r25
253 xor r26, r26, r26
254 xor r27, r27, r27
255 xor r28, r28, r28
256 xor r29, r29, r29
257 xor r30, r30, r30
258 xor r31, r31, r31
259 e_lis r4, __ram_start__@h
260 e_or2i r4, __ram_start__@l
261 e_lis r5, __ram_end__@h
262 e_or2i r5, __ram_end__@l
263.cleareccloop:
264 se_cmpl r4, r5
265 se_bge .cleareccend
266 e_stmw r16, 0(r4)
267 e_addi r4, r4, 64
268 se_b .cleareccloop
269.cleareccend:
270
271 /*
272 * Special function registers clearing, required in order to avoid
273 * possible problems with lockstep mode.
274 */
275 mtcrf 0xFF, r31
276 mtspr 9, r31 /* CTR */
277 mtspr 22, r31 /* DEC */
278 mtspr 26, r31 /* SRR0-1 */
279 mtspr 27, r31
280 mtspr 54, r31 /* DECAR */
281 mtspr 58, r31 /* CSRR0-1 */
282 mtspr 59, r31
283 mtspr 61, r31 /* DEAR */
284 mtspr 256, r31 /* USPRG0 */
285 mtspr 272, r31 /* SPRG1-7 */
286 mtspr 273, r31
287 mtspr 274, r31
288 mtspr 275, r31
289 mtspr 276, r31
290 mtspr 277, r31
291 mtspr 278, r31
292 mtspr 279, r31
293 mtspr 285, r31 /* TBU */
294 mtspr 284, r31 /* TBL */
295#if 0
296 mtspr 318, r31 /* DVC1-2 */
297 mtspr 319, r31
298#endif
299 mtspr 562, r31 /* DBCNT */
300 mtspr 570, r31 /* MCSRR0 */
301 mtspr 571, r31 /* MCSRR1 */
302 mtspr 604, r31 /* SPRG8-9 */
303 mtspr 605, r31
304
305 /*
306 * *Finally* the TLB0 is re-allocated to flash, note, the final phase
307 * is executed from RAM.
308 */
309 e_lis r3, TLB0_MAS0@h
310 mtspr 624, r3 /* MAS0 */
311 e_lis r3, TLB0_MAS1@h
312 e_or2i r3, TLB0_MAS1@l
313 mtspr 625, r3 /* MAS1 */
314 e_lis r3, TLB0_MAS2@h
315 e_or2i r3, TLB0_MAS2@l
316 mtspr 626, r3 /* MAS2 */
317 e_lis r3, TLB0_MAS3@h
318 e_or2i r3, TLB0_MAS3@l
319 mtspr 627, r3 /* MAS3 */
320 mflr r4
321 e_lis r6, _ramcode@h
322 e_or2i r6, _ramcode@l
323 e_lis r7, 0x40010000@h
324 mtctr r7
325 se_lwz r3, 0(r6)
326 se_stw r3, 0(r7)
327 se_lwz r3, 4(r6)
328 se_stw r3, 4(r7)
329 se_lwz r3, 8(r6)
330 se_stw r3, 8(r7)
331 se_bctrl
332 mtlr r4
333
334 /*
335 * Branch prediction enabled.
336 */
337 e_li r3, BOOT_BUCSR_DEFAULT
338 mtspr 1013, r3 /* BUCSR */
339
340 /*
341 * Cache invalidated and then enabled.
342 */
343 e_li r3, LICSR1_ICINV
344 mtspr 1011, r3 /* LICSR1 */
345.inv: mfspr r3, 1011 /* LICSR1 */
346 e_and2i. r3, LICSR1_ICINV
347 se_bne .inv
348 e_lis r3, BOOT_LICSR1_DEFAULT@h
349 e_or2i r3, BOOT_LICSR1_DEFAULT@l
350 mtspr 1011, r3 /* LICSR1 */
351
352 se_blr
353#endif /* BOOT_PERFORM_CORE_INIT */
354
355 /*
356 * Exception vectors initialization.
357 */
358 .align 2
359_ivinit:
360 /* MSR initialization.*/
361 e_lis r3, BOOT_MSR_DEFAULT@h
362 e_or2i r3, BOOT_MSR_DEFAULT@l
363 mtMSR r3
364
365 /* IVPR initialization.*/
366 e_lis r3, __ivpr_base__@h
367 e_or2i r3, __ivpr_base__@l
368 mtIVPR r3
369
370 /* IVORs initialization.*/
371 e_lis r3, _unhandled_exception@h
372 e_or2i r3, _unhandled_exception@l
373
374 mtspr 400, r3 /* IVOR0-15 */
375 mtspr 401, r3
376 mtspr 402, r3
377 mtspr 403, r3
378 mtspr 404, r3
379 mtspr 405, r3
380 mtspr 406, r3
381 mtspr 407, r3
382 mtspr 408, r3
383 mtspr 409, r3
384 mtspr 410, r3
385 mtspr 411, r3
386 mtspr 412, r3
387 mtspr 413, r3
388 mtspr 414, r3
389 mtspr 415, r3
390 mtspr 528, r3 /* IVOR32-34 */
391 mtspr 529, r3
392 mtspr 530, r3
393
394 se_blr
395
396 .section .handlers, "ax"
397
398 /*
399 * Unhandled exceptions handler.
400 */
401 .weak _unhandled_exception
402 .type _unhandled_exception, @function
403_unhandled_exception:
404 se_b _unhandled_exception
405
406#endif /* !defined(__DOXYGEN__) */
407
408/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot.h b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot.h
new file mode 100644
index 000000000..ec92f8309
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot.h
@@ -0,0 +1,248 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file boot.h
19 * @brief Boot parameters for the SPC56ECxx.
20 * @{
21 */
22
23#ifndef BOOT_H
24#define BOOT_H
25
26/*===========================================================================*/
27/* Module constants. */
28/*===========================================================================*/
29
30/**
31 * @name MASx registers definitions
32 * @{
33 */
34#define MAS0_TBLMAS_TBL 0x10000000
35#define MAS0_ESEL_MASK 0x000F0000
36#define MAS0_ESEL(n) ((n) << 16)
37
38#define MAS1_VALID 0x80000000
39#define MAS1_IPROT 0x40000000
40#define MAS1_TID_MASK 0x00FF0000
41#define MAS1_TS 0x00001000
42#define MAS1_TSISE_MASK 0x00000F80
43#define MAS1_TSISE_1K 0x00000000
44#define MAS1_TSISE_2K 0x00000080
45#define MAS1_TSISE_4K 0x00000100
46#define MAS1_TSISE_8K 0x00000180
47#define MAS1_TSISE_16K 0x00000200
48#define MAS1_TSISE_32K 0x00000280
49#define MAS1_TSISE_64K 0x00000300
50#define MAS1_TSISE_128K 0x00000380
51#define MAS1_TSISE_256K 0x00000400
52#define MAS1_TSISE_512K 0x00000480
53#define MAS1_TSISE_1M 0x00000500
54#define MAS1_TSISE_2M 0x00000580
55#define MAS1_TSISE_4M 0x00000600
56#define MAS1_TSISE_8M 0x00000680
57#define MAS1_TSISE_16M 0x00000700
58#define MAS1_TSISE_32M 0x00000780
59#define MAS1_TSISE_64M 0x00000800
60#define MAS1_TSISE_128M 0x00000880
61#define MAS1_TSISE_256M 0x00000900
62#define MAS1_TSISE_512M 0x00000980
63#define MAS1_TSISE_1G 0x00000A00
64#define MAS1_TSISE_2G 0x00000A80
65#define MAS1_TSISE_4G 0x00000B00
66
67#define MAS2_EPN_MASK 0xFFFFFC00
68#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
69#define MAS2_EBOOK 0x00000000
70#define MAS2_VLE 0x00000020
71#define MAS2_W 0x00000010
72#define MAS2_I 0x00000008
73#define MAS2_M 0x00000004
74#define MAS2_G 0x00000002
75#define MAS2_E 0x00000001
76
77#define MAS3_RPN_MASK 0xFFFFFC00
78#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
79#define MAS3_U0 0x00000200
80#define MAS3_U1 0x00000100
81#define MAS3_U2 0x00000080
82#define MAS3_U3 0x00000040
83#define MAS3_UX 0x00000020
84#define MAS3_SX 0x00000010
85#define MAS3_UW 0x00000008
86#define MAS3_SW 0x00000004
87#define MAS3_UR 0x00000002
88#define MAS3_SR 0x00000001
89/** @} */
90
91/**
92 * @name BUCSR registers definitions
93 * @{
94 */
95#define BUCSR_BPEN 0x00000001
96#define BUCSR_BPRED_MASK 0x00000006
97#define BUCSR_BPRED_0 0x00000000
98#define BUCSR_BPRED_1 0x00000002
99#define BUCSR_BPRED_2 0x00000004
100#define BUCSR_BPRED_3 0x00000006
101#define BUCSR_BALLOC_MASK 0x00000030
102#define BUCSR_BALLOC_0 0x00000000
103#define BUCSR_BALLOC_1 0x00000010
104#define BUCSR_BALLOC_2 0x00000020
105#define BUCSR_BALLOC_3 0x00000030
106#define BUCSR_BALLOC_BFI 0x00000200
107/** @} */
108
109/**
110 * @name LICSR1 registers definitions
111 * @{
112 */
113#define LICSR1_ICE 0x00000001
114#define LICSR1_ICINV 0x00000002
115#define LICSR1_ICORG 0x00000010
116/** @} */
117
118/**
119 * @name MSR register definitions
120 * @{
121 */
122#define MSR_UCLE 0x04000000
123#define MSR_SPE 0x02000000
124#define MSR_WE 0x00040000
125#define MSR_CE 0x00020000
126#define MSR_EE 0x00008000
127#define MSR_PR 0x00004000
128#define MSR_FP 0x00002000
129#define MSR_ME 0x00001000
130#define MSR_FE0 0x00000800
131#define MSR_DE 0x00000200
132#define MSR_FE1 0x00000100
133#define MSR_IS 0x00000020
134#define MSR_DS 0x00000010
135#define MSR_RI 0x00000002
136/** @} */
137
138/*===========================================================================*/
139/* Module pre-compile time settings. */
140/*===========================================================================*/
141
142/*
143 * TLB default settings.
144 */
145#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
146#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_4M)
147#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
148#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \
149 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
150 MAS3_UR | MAS3_SR)
151
152#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
153#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
154#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
155#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \
156 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
157 MAS3_UR | MAS3_SR)
158
159#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
160#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
161#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
162#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
163 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
164
165#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
166#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
167#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
168#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
169 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
170
171#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
172#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
173#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I)
174#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \
175 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
176
177#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
178#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
179#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
180#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \
181 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
182
183/*
184 * BUCSR default settings.
185 */
186#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
187#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
188 BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
189#endif
190
191/*
192 * LICSR1 default settings.
193 */
194#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
195#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
196#endif
197
198/*
199 * MSR default settings.
200 */
201#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
202#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
203#endif
204
205/*
206 * Boot default settings.
207 */
208#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
209#define BOOT_PERFORM_CORE_INIT 1
210#endif
211
212/*
213 * VLE mode default settings.
214 */
215#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
216#define BOOT_USE_VLE 1
217#endif
218
219/*
220 * RAM relocation flag.
221 */
222#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
223#define BOOT_RELOCATE_IN_RAM 0
224#endif
225
226/*===========================================================================*/
227/* Derived constants and error checks. */
228/*===========================================================================*/
229
230/*===========================================================================*/
231/* Module data structures and types. */
232/*===========================================================================*/
233
234/*===========================================================================*/
235/* Module macros. */
236/*===========================================================================*/
237
238/*===========================================================================*/
239/* External declarations. */
240/*===========================================================================*/
241
242/*===========================================================================*/
243/* Module inline functions. */
244/*===========================================================================*/
245
246#endif /* BOOT_H */
247
248/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot_cw.s b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot_cw.s
new file mode 100644
index 000000000..4604bbbcb
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot_cw.s
@@ -0,0 +1,400 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ECxx/boot.s
19 * @brief SPC56ECxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if !defined(__DOXYGEN__)
28
29 .extern _boot_address
30 .extern __ram_start__
31 .extern __ram_end__
32 .extern __ivpr_base__
33
34 .extern _unhandled_exception
35
36 /* BAM record.*/
37 .section .boot, 16
38
39#if BOOT_USE_VLE
40 .long 0x015A0000
41#else
42 .long 0x005A0000
43#endif
44 .long _reset_address
45
46 .align 4
47 .globl _reset_address
48 .type _reset_address, @function
49_reset_address:
50#if BOOT_PERFORM_CORE_INIT
51 e_bl _coreinit
52#endif
53 e_bl _ivinit
54
55#if BOOT_RELOCATE_IN_RAM
56 /*
57 * Image relocation in RAM.
58 */
59 e_lis r4, __ram_reloc_start__@h
60 e_or2i r4, r4, __ram_reloc_start__@l
61 e_lis r5, __ram_reloc_dest__@h
62 e_or2i r5, r5, __ram_reloc_dest__@l
63 e_lis r6, __ram_reloc_end__@h
64 e_or2i r6, r6, __ram_reloc_end__@l
65.relloop:
66 se_cmpl r4, r6
67 se_bge .relend
68 se_lwz r7, 0(r4)
69 se_addi r4, 4
70 se_stw r7, 0(r5)
71 se_addi r5, 4
72 se_b .relloop
73.relend:
74 e_lis r3, _boot_address@h
75 e_or2i r3, _boot_address@l
76 mtctr r3
77 se_bctrl
78#else
79 e_b _boot_address
80#endif
81
82#if BOOT_PERFORM_CORE_INIT
83 .align 4
84_ramcode:
85 tlbwe
86 se_isync
87 se_blr
88
89 .align 2
90_coreinit:
91 /*
92 * Invalidating all TLBs except TLB0.
93 */
94 e_lis r3, 0
95 mtspr 625, r3 /* MAS1 */
96 mtspr 626, r3 /* MAS2 */
97 mtspr 627, r3 /* MAS3 */
98 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
99 mtspr 624, r3 /* MAS0 */
100 tlbwe
101 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
102 mtspr 624, r3 /* MAS0 */
103 tlbwe
104 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
105 mtspr 624, r3 /* MAS0 */
106 tlbwe
107 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
108 mtspr 624, r3 /* MAS0 */
109 tlbwe
110 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
111 mtspr 624, r3 /* MAS0 */
112 tlbwe
113 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
114 mtspr 624, r3 /* MAS0 */
115 tlbwe
116 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
117 mtspr 624, r3 /* MAS0 */
118 tlbwe
119 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
120 mtspr 624, r3 /* MAS0 */
121 tlbwe
122 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
123 mtspr 624, r3 /* MAS0 */
124 tlbwe
125 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
126 mtspr 624, r3 /* MAS0 */
127 tlbwe
128 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
129 mtspr 624, r3 /* MAS0 */
130 tlbwe
131 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
132 mtspr 624, r3 /* MAS0 */
133 tlbwe
134 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
135 mtspr 624, r3 /* MAS0 */
136 tlbwe
137 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
138 mtspr 624, r3 /* MAS0 */
139 tlbwe
140 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
141 mtspr 624, r3 /* MAS0 */
142 tlbwe
143
144 /*
145 * TLB1 allocated to internal RAM.
146 */
147 e_lis r3, TLB1_MAS0@h
148 mtspr 624, r3 /* MAS0 */
149 e_lis r3, TLB1_MAS1@h
150 e_or2i r3, TLB1_MAS1@l
151 mtspr 625, r3 /* MAS1 */
152 e_lis r3, TLB1_MAS2@h
153 e_or2i r3, TLB1_MAS2@l
154 mtspr 626, r3 /* MAS2 */
155 e_lis r3, TLB1_MAS3@h
156 e_or2i r3, TLB1_MAS3@l
157 mtspr 627, r3 /* MAS3 */
158 tlbwe
159
160 /*
161 * TLB2 allocated to internal Peripherals Bridge A.
162 */
163 e_lis r3, TLB2_MAS0@h
164 mtspr 624, r3 /* MAS0 */
165 e_lis r3, TLB2_MAS1@h
166 e_or2i r3, TLB2_MAS1@l
167 mtspr 625, r3 /* MAS1 */
168 e_lis r3, TLB2_MAS2@h
169 e_or2i r3, TLB2_MAS2@l
170 mtspr 626, r3 /* MAS2 */
171 e_lis r3, TLB2_MAS3@h
172 e_or2i r3, TLB2_MAS3@l
173 mtspr 627, r3 /* MAS3 */
174 tlbwe
175
176 /*
177 * TLB3 allocated to internal Peripherals Bridge B.
178 */
179 e_lis r3, TLB3_MAS0@h
180 mtspr 624, r3 /* MAS0 */
181 e_lis r3, TLB3_MAS1@h
182 e_or2i r3, TLB3_MAS1@l
183 mtspr 625, r3 /* MAS1 */
184 e_lis r3, TLB3_MAS2@h
185 e_or2i r3, TLB3_MAS2@l
186 mtspr 626, r3 /* MAS2 */
187 e_lis r3, TLB3_MAS3@h
188 e_or2i r3, TLB3_MAS3@l
189 mtspr 627, r3 /* MAS3 */
190 tlbwe
191
192 /*
193 * TLB4 allocated to on-platform peripherals.
194 */
195 e_lis r3, TLB4_MAS0@h
196 mtspr 624, r3 /* MAS0 */
197 e_lis r3, TLB4_MAS1@h
198 e_or2i r3, TLB4_MAS1@l
199 mtspr 625, r3 /* MAS1 */
200 e_lis r3, TLB4_MAS2@h
201 e_or2i r3, TLB4_MAS2@l
202 mtspr 626, r3 /* MAS2 */
203 e_lis r3, TLB4_MAS3@h
204 e_or2i r3, TLB4_MAS3@l
205 mtspr 627, r3 /* MAS3 */
206 tlbwe
207
208 /*
209 * TLB5 allocated to on-platform peripherals.
210 */
211 e_lis r3, TLB5_MAS0@h
212 mtspr 624, r3 /* MAS0 */
213 e_lis r3, TLB5_MAS1@h
214 e_or2i r3, TLB5_MAS1@l
215 mtspr 625, r3 /* MAS1 */
216 e_lis r3, TLB5_MAS2@h
217 e_or2i r3, TLB5_MAS2@l
218 mtspr 626, r3 /* MAS2 */
219 e_lis r3, TLB5_MAS3@h
220 e_or2i r3, TLB5_MAS3@l
221 mtspr 627, r3 /* MAS3 */
222 tlbwe
223
224 /*
225 * RAM clearing, this device requires a write to all RAM location in
226 * order to initialize the ECC detection hardware, this is going to
227 * slow down the startup but there is no way around.
228 */
229 xor r0, r0, r0
230 xor r1, r1, r1
231 xor r2, r2, r2
232 xor r3, r3, r3
233 xor r4, r4, r4
234 xor r5, r5, r5
235 xor r6, r6, r6
236 xor r7, r7, r7
237 xor r8, r8, r8
238 xor r9, r9, r9
239 xor r10, r10, r10
240 xor r11, r11, r11
241 xor r12, r12, r12
242 xor r13, r13, r13
243 xor r14, r14, r14
244 xor r15, r15, r15
245 xor r16, r16, r16
246 xor r17, r17, r17
247 xor r18, r18, r18
248 xor r19, r19, r19
249 xor r20, r20, r20
250 xor r21, r21, r21
251 xor r22, r22, r22
252 xor r23, r23, r23
253 xor r24, r24, r24
254 xor r25, r25, r25
255 xor r26, r26, r26
256 xor r27, r27, r27
257 xor r28, r28, r28
258 xor r29, r29, r29
259 xor r30, r30, r30
260 xor r31, r31, r31
261 e_lis r4, __ram_start__@h
262 e_or2i r4, __ram_start__@l
263 e_lis r5, __ram_end__@h
264 e_or2i r5, __ram_end__@l
265.cleareccloop:
266 se_cmpl r4, r5
267 se_bge .cleareccend
268 e_stmw r16, 0(r4)
269 e_addi r4, r4, 64
270 se_b .cleareccloop
271.cleareccend:
272
273 /*
274 * Special function registers clearing, required in order to avoid
275 * possible problems with lockstep mode.
276 */
277 mtcrf 0xFF, r31
278 mtspr 9, r31 /* CTR */
279 mtspr 22, r31 /* DEC */
280 mtspr 26, r31 /* SRR0-1 */
281 mtspr 27, r31
282 mtspr 54, r31 /* DECAR */
283 mtspr 58, r31 /* CSRR0-1 */
284 mtspr 59, r31
285 mtspr 61, r31 /* DEAR */
286 mtspr 256, r31 /* USPRG0 */
287 mtspr 272, r31 /* SPRG1-7 */
288 mtspr 273, r31
289 mtspr 274, r31
290 mtspr 275, r31
291 mtspr 276, r31
292 mtspr 277, r31
293 mtspr 278, r31
294 mtspr 279, r31
295 mtspr 285, r31 /* TBU */
296 mtspr 284, r31 /* TBL */
297#if 0
298 mtspr 318, r31 /* DVC1-2 */
299 mtspr 319, r31
300#endif
301 mtspr 562, r31 /* DBCNT */
302 mtspr 570, r31 /* MCSRR0 */
303 mtspr 571, r31 /* MCSRR1 */
304 mtspr 604, r31 /* SPRG8-9 */
305 mtspr 605, r31
306
307 /*
308 * *Finally* the TLB0 is re-allocated to flash, note, the final phase
309 * is executed from RAM.
310 */
311 e_lis r3, TLB0_MAS0@h
312 mtspr 624, r3 /* MAS0 */
313 e_lis r3, TLB0_MAS1@h
314 e_or2i r3, TLB0_MAS1@l
315 mtspr 625, r3 /* MAS1 */
316 e_lis r3, TLB0_MAS2@h
317 e_or2i r3, TLB0_MAS2@l
318 mtspr 626, r3 /* MAS2 */
319 e_lis r3, TLB0_MAS3@h
320 e_or2i r3, TLB0_MAS3@l
321 mtspr 627, r3 /* MAS3 */
322 se_mflr r4
323 e_lis r6, _ramcode@h
324 e_or2i r6, _ramcode@l
325 e_lis r7, 0x40010000@h
326 mtctr r7
327 se_lwz r3, 0(r6)
328 se_stw r3, 0(r7)
329 se_lwz r3, 4(r6)
330 se_stw r3, 4(r7)
331 se_lwz r3, 8(r6)
332 se_stw r3, 8(r7)
333 se_bctrl
334 mtlr r4
335
336 /*
337 * Branch prediction enabled.
338 */
339 e_li r3, BOOT_BUCSR_DEFAULT
340 mtspr 1013, r3 /* BUCSR */
341
342 /*
343 * Cache invalidated and then enabled.
344 */
345 se_li r3, LICSR1_ICINV
346 mtspr 1011, r3 /* LICSR1 */
347.inv: mfspr r3, 1011 /* LICSR1 */
348 e_andi. r3, r3, LICSR1_ICINV
349 se_bne .inv
350 e_lis r3, BOOT_LICSR1_DEFAULT@h
351 e_or2i r3, BOOT_LICSR1_DEFAULT@l
352 mtspr 1011, r3 /* LICSR1 */
353
354 se_blr
355#endif /* BOOT_PERFORM_CORE_INIT */
356
357 /*
358 * Exception vectors initialization.
359 */
360 .align 4
361_ivinit:
362 /* MSR initialization.*/
363 e_lis r3, BOOT_MSR_DEFAULT@h
364 e_ori r3, r3, BOOT_MSR_DEFAULT@l
365 mtMSR r3
366
367 /* IVPR initialization.*/
368 e_lis r3, __ivpr_base__@h
369 e_or2i r3, __ivpr_base__@l
370 mtIVPR r3
371
372 /* IVORs initialization.*/
373 e_lis r3, _unhandled_exception@h
374 e_or2i r3, _unhandled_exception@l
375
376 mtspr 400, r3 /* IVOR0-15 */
377 mtspr 401, r3
378 mtspr 402, r3
379 mtspr 403, r3
380 mtspr 404, r3
381 mtspr 405, r3
382 mtspr 406, r3
383 mtspr 407, r3
384 mtspr 408, r3
385 mtspr 409, r3
386 mtspr 410, r3
387 mtspr 411, r3
388 mtspr 412, r3
389 mtspr 413, r3
390 mtspr 414, r3
391 mtspr 415, r3
392 mtspr 528, r3 /* IVOR32-34 */
393 mtspr 529, r3
394 mtspr 530, r3
395
396 se_blr
397
398#endif /* !defined(__DOXYGEN__) */
399
400/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot_ghs.s b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot_ghs.s
new file mode 100644
index 000000000..cff8475bf
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot_ghs.s
@@ -0,0 +1,405 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ECxx/boot_ghs.s
19 * @brief SPC56ECxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if !defined(__DOXYGEN__)
28
29 .vle
30
31 /* BAM record.*/
32 .section .boot, "axv"
33
34#if BOOT_USE_VLE
35 .long 0x015A0000
36#else
37 .long 0x005A0000
38#endif
39 .long _reset_address
40
41 .align 2
42 .globl _reset_address
43 .type _reset_address, @function
44_reset_address:
45#if BOOT_PERFORM_CORE_INIT
46 se_bl _coreinit
47#endif
48 se_bl _ivinit
49
50#if BOOT_RELOCATE_IN_RAM
51 /*
52 * Image relocation in RAM.
53 */
54 e_lis r4, __ram_reloc_start__@h
55 e_or2i r4, __ram_reloc_start__@l
56 e_lis r5, __ram_reloc_dest__@h
57 e_or2i r5, __ram_reloc_dest__@l
58 e_lis r6, __ram_reloc_end__@h
59 e_or2i r6, r6, __ram_reloc_end__@l
60.relloop:
61 se_cmpl r4, r6
62 se_bge .relend
63 se_lwz r7, 0(r4)
64 se_addi r4, 4
65 se_stw r7, 0(r5)
66 se_addi r5, 4
67 se_b .relloop
68.relend:
69 e_lis r3, _boot_address@h
70 e_or2i r3, _boot_address@l
71 mtctr r3
72 se_bctrl
73#else
74 e_b _boot_address
75#endif
76
77#if BOOT_PERFORM_CORE_INIT
78 .align 2
79_ramcode:
80 tlbwe
81 se_isync
82 se_blr
83
84 .align 2
85_coreinit:
86 /*
87 * Invalidating all TLBs except TLB0.
88 */
89 e_lis r3, 0
90 mtspr 625, r3 /* MAS1 */
91 mtspr 626, r3 /* MAS2 */
92 mtspr 627, r3 /* MAS3 */
93 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
94 mtspr 624, r3 /* MAS0 */
95 tlbwe
96 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
97 mtspr 624, r3 /* MAS0 */
98 tlbwe
99 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
100 mtspr 624, r3 /* MAS0 */
101 tlbwe
102 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
103 mtspr 624, r3 /* MAS0 */
104 tlbwe
105 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
106 mtspr 624, r3 /* MAS0 */
107 tlbwe
108 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
109 mtspr 624, r3 /* MAS0 */
110 tlbwe
111 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
112 mtspr 624, r3 /* MAS0 */
113 tlbwe
114 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
115 mtspr 624, r3 /* MAS0 */
116 tlbwe
117 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
118 mtspr 624, r3 /* MAS0 */
119 tlbwe
120 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
121 mtspr 624, r3 /* MAS0 */
122 tlbwe
123 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
124 mtspr 624, r3 /* MAS0 */
125 tlbwe
126 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
127 mtspr 624, r3 /* MAS0 */
128 tlbwe
129 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
130 mtspr 624, r3 /* MAS0 */
131 tlbwe
132 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
133 mtspr 624, r3 /* MAS0 */
134 tlbwe
135 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
136 mtspr 624, r3 /* MAS0 */
137 tlbwe
138
139 /*
140 * TLB1 allocated to internal RAM.
141 */
142 e_lis r3, TLB1_MAS0@h
143 mtspr 624, r3 /* MAS0 */
144 e_lis r3, TLB1_MAS1@h
145 e_or2i r3, TLB1_MAS1@l
146 mtspr 625, r3 /* MAS1 */
147 e_lis r3, TLB1_MAS2@h
148 e_or2i r3, TLB1_MAS2@l
149 mtspr 626, r3 /* MAS2 */
150 e_lis r3, TLB1_MAS3@h
151 e_or2i r3, TLB1_MAS3@l
152 mtspr 627, r3 /* MAS3 */
153 tlbwe
154
155 /*
156 * TLB2 allocated to internal Peripherals Bridge A.
157 */
158 e_lis r3, TLB2_MAS0@h
159 mtspr 624, r3 /* MAS0 */
160 e_lis r3, TLB2_MAS1@h
161 e_or2i r3, TLB2_MAS1@l
162 mtspr 625, r3 /* MAS1 */
163 e_lis r3, TLB2_MAS2@h
164 e_or2i r3, TLB2_MAS2@l
165 mtspr 626, r3 /* MAS2 */
166 e_lis r3, TLB2_MAS3@h
167 e_or2i r3, TLB2_MAS3@l
168 mtspr 627, r3 /* MAS3 */
169 tlbwe
170
171 /*
172 * TLB3 allocated to internal Peripherals Bridge B.
173 */
174 e_lis r3, TLB3_MAS0@h
175 mtspr 624, r3 /* MAS0 */
176 e_lis r3, TLB3_MAS1@h
177 e_or2i r3, TLB3_MAS1@l
178 mtspr 625, r3 /* MAS1 */
179 e_lis r3, TLB3_MAS2@h
180 e_or2i r3, TLB3_MAS2@l
181 mtspr 626, r3 /* MAS2 */
182 e_lis r3, TLB3_MAS3@h
183 e_or2i r3, TLB3_MAS3@l
184 mtspr 627, r3 /* MAS3 */
185 tlbwe
186
187 /*
188 * TLB4 allocated to on-platform peripherals.
189 */
190 e_lis r3, TLB4_MAS0@h
191 mtspr 624, r3 /* MAS0 */
192 e_lis r3, TLB4_MAS1@h
193 e_or2i r3, TLB4_MAS1@l
194 mtspr 625, r3 /* MAS1 */
195 e_lis r3, TLB4_MAS2@h
196 e_or2i r3, TLB4_MAS2@l
197 mtspr 626, r3 /* MAS2 */
198 e_lis r3, TLB4_MAS3@h
199 e_or2i r3, TLB4_MAS3@l
200 mtspr 627, r3 /* MAS3 */
201 tlbwe
202
203 /*
204 * TLB5 allocated to on-platform peripherals.
205 */
206 e_lis r3, TLB5_MAS0@h
207 mtspr 624, r3 /* MAS0 */
208 e_lis r3, TLB5_MAS1@h
209 e_or2i r3, TLB5_MAS1@l
210 mtspr 625, r3 /* MAS1 */
211 e_lis r3, TLB5_MAS2@h
212 e_or2i r3, TLB5_MAS2@l
213 mtspr 626, r3 /* MAS2 */
214 e_lis r3, TLB5_MAS3@h
215 e_or2i r3, TLB5_MAS3@l
216 mtspr 627, r3 /* MAS3 */
217 tlbwe
218
219 /*
220 * RAM clearing, this device requires a write to all RAM location in
221 * order to initialize the ECC detection hardware, this is going to
222 * slow down the startup but there is no way around.
223 */
224 xor r0, r0, r0
225 xor r1, r1, r1
226 xor r2, r2, r2
227 xor r3, r3, r3
228 xor r4, r4, r4
229 xor r5, r5, r5
230 xor r6, r6, r6
231 xor r7, r7, r7
232 xor r8, r8, r8
233 xor r9, r9, r9
234 xor r10, r10, r10
235 xor r11, r11, r11
236 xor r12, r12, r12
237 xor r13, r13, r13
238 xor r14, r14, r14
239 xor r15, r15, r15
240 xor r16, r16, r16
241 xor r17, r17, r17
242 xor r18, r18, r18
243 xor r19, r19, r19
244 xor r20, r20, r20
245 xor r21, r21, r21
246 xor r22, r22, r22
247 xor r23, r23, r23
248 xor r24, r24, r24
249 xor r25, r25, r25
250 xor r26, r26, r26
251 xor r27, r27, r27
252 xor r28, r28, r28
253 xor r29, r29, r29
254 xor r30, r30, r30
255 xor r31, r31, r31
256 e_lis r4, __ram_start__@h
257 e_or2i r4, __ram_start__@l
258 e_lis r5, __ram_end__@h
259 e_or2i r5, __ram_end__@l
260.cleareccloop:
261 se_cmpl r4, r5
262 se_bge .cleareccend
263 e_stmw r16, 0(r4)
264 e_addi r4, r4, 64
265 se_b .cleareccloop
266.cleareccend:
267
268 /*
269 * Special function registers clearing, required in order to avoid
270 * possible problems with lockstep mode.
271 */
272 mtcrf 0xFF, r31
273 mtspr 9, r31 /* CTR */
274 mtspr 22, r31 /* DEC */
275 mtspr 26, r31 /* SRR0-1 */
276 mtspr 27, r31
277 mtspr 54, r31 /* DECAR */
278 mtspr 58, r31 /* CSRR0-1 */
279 mtspr 59, r31
280 mtspr 61, r31 /* DEAR */
281 mtspr 256, r31 /* USPRG0 */
282 mtspr 272, r31 /* SPRG1-7 */
283 mtspr 273, r31
284 mtspr 274, r31
285 mtspr 275, r31
286 mtspr 276, r31
287 mtspr 277, r31
288 mtspr 278, r31
289 mtspr 279, r31
290 mtspr 285, r31 /* TBU */
291 mtspr 284, r31 /* TBL */
292#if 0
293 mtspr 318, r31 /* DVC1-2 */
294 mtspr 319, r31
295#endif
296 mtspr 562, r31 /* DBCNT */
297 mtspr 570, r31 /* MCSRR0 */
298 mtspr 571, r31 /* MCSRR1 */
299 mtspr 604, r31 /* SPRG8-9 */
300 mtspr 605, r31
301
302 /*
303 * *Finally* the TLB0 is re-allocated to flash, note, the final phase
304 * is executed from RAM.
305 */
306 e_lis r3, TLB0_MAS0@h
307 mtspr 624, r3 /* MAS0 */
308 e_lis r3, TLB0_MAS1@h
309 e_or2i r3, TLB0_MAS1@l
310 mtspr 625, r3 /* MAS1 */
311 e_lis r3, TLB0_MAS2@h
312 e_or2i r3, TLB0_MAS2@l
313 mtspr 626, r3 /* MAS2 */
314 e_lis r3, TLB0_MAS3@h
315 e_or2i r3, TLB0_MAS3@l
316 mtspr 627, r3 /* MAS3 */
317 mflr r4
318 e_lis r6, _ramcode@h
319 e_or2i r6, _ramcode@l
320 e_lis r7, 0x40010000@h
321 mtctr r7
322 se_lwz r3, 0(r6)
323 se_stw r3, 0(r7)
324 se_lwz r3, 4(r6)
325 se_stw r3, 4(r7)
326 se_lwz r3, 8(r6)
327 se_stw r3, 8(r7)
328 se_bctrl
329 mtlr r4
330
331 /*
332 * Branch prediction enabled.
333 */
334 e_li r3, BOOT_BUCSR_DEFAULT
335 mtspr 1013, r3 /* BUCSR */
336
337 /*
338 * Cache invalidated and then enabled.
339 */
340 e_li r3, LICSR1_ICINV
341 mtspr 1011, r3 /* LICSR1 */
342.inv: mfspr r3, 1011 /* LICSR1 */
343 e_and2i. r3, LICSR1_ICINV
344 se_bne .inv
345 e_lis r3, BOOT_LICSR1_DEFAULT@h
346 e_or2i r3, BOOT_LICSR1_DEFAULT@l
347 mtspr 1011, r3 /* LICSR1 */
348
349 se_blr
350#endif /* BOOT_PERFORM_CORE_INIT */
351
352 /*
353 * Exception vectors initialization.
354 */
355 .align 2
356_ivinit:
357 /* MSR initialization.*/
358 e_lis r3, BOOT_MSR_DEFAULT@h
359 e_or2i r3, BOOT_MSR_DEFAULT@l
360 mtMSR r3
361
362 /* IVPR initialization.*/
363 e_lis r3, __ivpr_base__@h
364 e_or2i r3, __ivpr_base__@l
365 mtIVPR r3
366
367 /* IVORs initialization.*/
368 e_lis r3, _unhandled_exception@h
369 e_or2i r3, _unhandled_exception@l
370
371 mtspr 400, r3 /* IVOR0-15 */
372 mtspr 401, r3
373 mtspr 402, r3
374 mtspr 403, r3
375 mtspr 404, r3
376 mtspr 405, r3
377 mtspr 406, r3
378 mtspr 407, r3
379 mtspr 408, r3
380 mtspr 409, r3
381 mtspr 410, r3
382 mtspr 411, r3
383 mtspr 412, r3
384 mtspr 413, r3
385 mtspr 414, r3
386 mtspr 415, r3
387 mtspr 528, r3 /* IVOR32-34 */
388 mtspr 529, r3
389 mtspr 530, r3
390
391 se_blr
392
393 .section .handlers, "axv"
394
395 /*
396 * Unhandled exceptions handler.
397 */
398 .weak _unhandled_exception
399 .type _unhandled_exception, @function
400_unhandled_exception:
401 se_b _unhandled_exception
402
403#endif /* !defined(__DOXYGEN__) */
404
405/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/intc.h b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/intc.h
new file mode 100644
index 000000000..bbf3cde88
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/intc.h
@@ -0,0 +1,95 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ECxx/intc.h
19 * @brief SPC56ECxx INTC module header.
20 *
21 * @addtogroup INTC
22 * @{
23 */
24
25#ifndef INTC_H
26#define INTC_H
27
28/*===========================================================================*/
29/* Module constants. */
30/*===========================================================================*/
31
32/**
33 * @name INTC addresses
34 * @{
35 */
36#define INTC_BASE 0xFFF48000
37#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
38#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
39/** @} */
40
41/**
42 * @brief INTC priority levels.
43 */
44#define INTC_PRIORITY_LEVELS 16U
45
46/*===========================================================================*/
47/* Module pre-compile time settings. */
48/*===========================================================================*/
49
50/*===========================================================================*/
51/* Derived constants and error checks. */
52/*===========================================================================*/
53
54/*===========================================================================*/
55/* Module data structures and types. */
56/*===========================================================================*/
57
58/*===========================================================================*/
59/* Module macros. */
60/*===========================================================================*/
61
62/**
63 * @name INTC-related macros
64 * @{
65 */
66#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
67#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
68#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
69#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
70#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
71/** @} */
72
73/**
74 * @brief Core selection macros for PSR register.
75 */
76#define INTC_PSR_CORE0 0x00
77#define INTC_PSR_CORE1 0xC0
78#define INTC_PSR_CORES01 0x40
79
80/**
81 * @brief PSR register content helper
82 */
83#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
84
85/*===========================================================================*/
86/* External declarations. */
87/*===========================================================================*/
88
89/*===========================================================================*/
90/* Module inline functions. */
91/*===========================================================================*/
92
93#endif /* INTC_H */
94
95/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/ppcparams.h b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/ppcparams.h
new file mode 100644
index 000000000..9b5f9e08c
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/ppcparams.h
@@ -0,0 +1,83 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ECxx/ppcparams.h
19 * @brief PowerPC parameters for the SPC56ECxx.
20 *
21 * @defgroup PPC_SPC56ECxx SPC56ECxx Specific Parameters
22 * @ingroup PPC_SPECIFIC
23 * @details This file contains the PowerPC specific parameters for the
24 * SPC56ECxx platform.
25 * @{
26 */
27
28#ifndef PPCPARAMS_H
29#define PPCPARAMS_H
30
31/**
32 * @brief Family identification macro.
33 */
34#define PPC_SPC56ECxx
35
36/**
37 * @brief PPC core model.
38 */
39#define PPC_VARIANT PPC_VARIANT_e200z4
40
41/**
42 * @brief Number of cores.
43 */
44#define PPC_CORE_NUMBER 1
45
46/**
47 * @brief Number of writable bits in IVPR register.
48 */
49#define PPC_IVPR_BITS 16
50
51/**
52 * @brief IVORx registers support.
53 */
54#define PPC_SUPPORTS_IVORS TRUE
55
56/**
57 * @brief Book E instruction set support.
58 */
59#define PPC_SUPPORTS_BOOKE TRUE
60
61/**
62 * @brief VLE instruction set support.
63 */
64#define PPC_SUPPORTS_VLE TRUE
65
66/**
67 * @brief Supports VLS Load/Store Multiple Volatile instructions.
68 */
69#define PPC_SUPPORTS_VLE_MULTI TRUE
70
71/**
72 * @brief Supports the decrementer timer.
73 */
74#define PPC_SUPPORTS_DECREMENTER TRUE
75
76/**
77 * @brief Number of interrupt sources.
78 */
79#define PPC_NUM_VECTORS 279
80
81#endif /* PPCPARAMS_H */
82
83/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.S b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.S
new file mode 100644
index 000000000..56e59fe93
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.S
@@ -0,0 +1,409 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ELxx/boot.s
19 * @brief SPC56ELxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if defined(__HIGHTEC__)
28#define se_bge bge
29#endif
30
31#if !defined(__DOXYGEN__)
32
33 /* BAM record.*/
34 .section .boot, "ax"
35
36#if BOOT_USE_VLE
37 .long 0x015A0000
38#else
39 .long 0x005A0000
40#endif
41 .long _reset_address
42
43 .align 2
44 .globl _reset_address
45 .type _reset_address, @function
46_reset_address:
47 e_bl _coreinit
48 e_bl _ivinit
49
50#if BOOT_RELOCATE_IN_RAM
51 /*
52 * Image relocation in RAM.
53 */
54 e_lis r4, __ram_reloc_start__@h
55 e_or2i r4, __ram_reloc_start__@l
56 e_lis r5, __ram_reloc_dest__@h
57 e_or2i r5, __ram_reloc_dest__@l
58 e_lis r6, __ram_reloc_end__@h
59 e_or2i r6, r6, __ram_reloc_end__@l
60.relloop:
61 se_cmpl r4, r6
62 se_bge .relend
63 se_lwz r7, 0(r4)
64 se_addi r4, 4
65 se_stw r7, 0(r5)
66 se_addi r5, 4
67 se_b .relloop
68.relend:
69 e_lis r3, _boot_address@h
70 e_or2i r3, _boot_address@l
71 mtctr r3
72 se_bctrl
73#else
74 e_b _boot_address
75#endif
76
77#if BOOT_PERFORM_CORE_INIT
78 .align 2
79_ramcode:
80 tlbwe
81 se_isync
82 se_blr
83#endif /* BOOT_PERFORM_CORE_INIT */
84
85 .align 2
86_coreinit:
87#if BOOT_PERFORM_CORE_INIT
88 /*
89 * Invalidating all TLBs except TLB0.
90 */
91 e_lis r3, 0
92 mtspr 625, r3 /* MAS1 */
93 mtspr 626, r3 /* MAS2 */
94 mtspr 627, r3 /* MAS3 */
95 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
96 mtspr 624, r3 /* MAS0 */
97 tlbwe
98 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
99 mtspr 624, r3 /* MAS0 */
100 tlbwe
101 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
102 mtspr 624, r3 /* MAS0 */
103 tlbwe
104 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
105 mtspr 624, r3 /* MAS0 */
106 tlbwe
107 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
108 mtspr 624, r3 /* MAS0 */
109 tlbwe
110 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
111 mtspr 624, r3 /* MAS0 */
112 tlbwe
113 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
114 mtspr 624, r3 /* MAS0 */
115 tlbwe
116 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
117 mtspr 624, r3 /* MAS0 */
118 tlbwe
119 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
120 mtspr 624, r3 /* MAS0 */
121 tlbwe
122 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
123 mtspr 624, r3 /* MAS0 */
124 tlbwe
125 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
126 mtspr 624, r3 /* MAS0 */
127 tlbwe
128 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
129 mtspr 624, r3 /* MAS0 */
130 tlbwe
131 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
132 mtspr 624, r3 /* MAS0 */
133 tlbwe
134 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
135 mtspr 624, r3 /* MAS0 */
136 tlbwe
137 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
138 mtspr 624, r3 /* MAS0 */
139 tlbwe
140
141 /*
142 * TLB1 allocated to internal RAM.
143 */
144 e_lis r3, TLB1_MAS0@h
145 mtspr 624, r3 /* MAS0 */
146 e_lis r3, TLB1_MAS1@h
147 e_or2i r3, TLB1_MAS1@l
148 mtspr 625, r3 /* MAS1 */
149 e_lis r3, TLB1_MAS2@h
150 e_or2i r3, TLB1_MAS2@l
151 mtspr 626, r3 /* MAS2 */
152 e_lis r3, TLB1_MAS3@h
153 e_or2i r3, TLB1_MAS3@l
154 mtspr 627, r3 /* MAS3 */
155 tlbwe
156
157 /*
158 * TLB2 allocated to internal Peripherals Bridge A.
159 */
160 e_lis r3, TLB2_MAS0@h
161 mtspr 624, r3 /* MAS0 */
162 e_lis r3, TLB2_MAS1@h
163 e_or2i r3, TLB2_MAS1@l
164 mtspr 625, r3 /* MAS1 */
165 e_lis r3, TLB2_MAS2@h
166 e_or2i r3, TLB2_MAS2@l
167 mtspr 626, r3 /* MAS2 */
168 e_lis r3, TLB2_MAS3@h
169 e_or2i r3, TLB2_MAS3@l
170 mtspr 627, r3 /* MAS3 */
171 tlbwe
172
173 /*
174 * TLB3 allocated to internal Peripherals Bridge B.
175 */
176 e_lis r3, TLB3_MAS0@h
177 mtspr 624, r3 /* MAS0 */
178 e_lis r3, TLB3_MAS1@h
179 e_or2i r3, TLB3_MAS1@l
180 mtspr 625, r3 /* MAS1 */
181 e_lis r3, TLB3_MAS2@h
182 e_or2i r3, TLB3_MAS2@l
183 mtspr 626, r3 /* MAS2 */
184 e_lis r3, TLB3_MAS3@h
185 e_or2i r3, TLB3_MAS3@l
186 mtspr 627, r3 /* MAS3 */
187 tlbwe
188
189 /*
190 * TLB4 allocated to on-platform peripherals.
191 */
192 e_lis r3, TLB4_MAS0@h
193 mtspr 624, r3 /* MAS0 */
194 e_lis r3, TLB4_MAS1@h
195 e_or2i r3, TLB4_MAS1@l
196 mtspr 625, r3 /* MAS1 */
197 e_lis r3, TLB4_MAS2@h
198 e_or2i r3, TLB4_MAS2@l
199 mtspr 626, r3 /* MAS2 */
200 e_lis r3, TLB4_MAS3@h
201 e_or2i r3, TLB4_MAS3@l
202 mtspr 627, r3 /* MAS3 */
203 tlbwe
204
205 /*
206 * TLB5 allocated to on-platform peripherals.
207 */
208 e_lis r3, TLB5_MAS0@h
209 mtspr 624, r3 /* MAS0 */
210 e_lis r3, TLB5_MAS1@h
211 e_or2i r3, TLB5_MAS1@l
212 mtspr 625, r3 /* MAS1 */
213 e_lis r3, TLB5_MAS2@h
214 e_or2i r3, TLB5_MAS2@l
215 mtspr 626, r3 /* MAS2 */
216 e_lis r3, TLB5_MAS3@h
217 e_or2i r3, TLB5_MAS3@l
218 mtspr 627, r3 /* MAS3 */
219 tlbwe
220
221 /*
222 * RAM clearing, this device requires a write to all RAM location in
223 * order to initialize the ECC detection hardware, this is going to
224 * slow down the startup but there is no way around.
225 */
226 xor r0, r0, r0
227 xor r1, r1, r1
228 xor r2, r2, r2
229 xor r3, r3, r3
230 xor r4, r4, r4
231 xor r5, r5, r5
232 xor r6, r6, r6
233 xor r7, r7, r7
234 xor r8, r8, r8
235 xor r9, r9, r9
236 xor r10, r10, r10
237 xor r11, r11, r11
238 xor r12, r12, r12
239 xor r13, r13, r13
240 xor r14, r14, r14
241 xor r15, r15, r15
242 xor r16, r16, r16
243 xor r17, r17, r17
244 xor r18, r18, r18
245 xor r19, r19, r19
246 xor r20, r20, r20
247 xor r21, r21, r21
248 xor r22, r22, r22
249 xor r23, r23, r23
250 xor r24, r24, r24
251 xor r25, r25, r25
252 xor r26, r26, r26
253 xor r27, r27, r27
254 xor r28, r28, r28
255 xor r29, r29, r29
256 xor r30, r30, r30
257 xor r31, r31, r31
258 e_lis r4, __ram_start__@h
259 e_or2i r4, __ram_start__@l
260 e_lis r5, __ram_end__@h
261 e_or2i r5, __ram_end__@l
262.cleareccloop:
263 se_cmpl r4, r5
264 se_bge .cleareccend
265 e_stmw r16, 0(r4)
266 e_addi r4, r4, 64
267 se_b .cleareccloop
268.cleareccend:
269#endif /* BOOT_PERFORM_CORE_INIT */
270
271 /*
272 * Special function registers clearing, required in order to avoid
273 * possible problems with lockstep mode.
274 */
275 mtcrf 0xFF, r31
276 mtspr 9, r31 /* CTR */
277 mtspr 22, r31 /* DEC */
278 mtspr 26, r31 /* SRR0-1 */
279 mtspr 27, r31
280 mtspr 54, r31 /* DECAR */
281 mtspr 58, r31 /* CSRR0-1 */
282 mtspr 59, r31
283 mtspr 61, r31 /* DEAR */
284 mtspr 256, r31 /* USPRG0 */
285 mtspr 272, r31 /* SPRG1-7 */
286 mtspr 273, r31
287 mtspr 274, r31
288 mtspr 275, r31
289 mtspr 276, r31
290 mtspr 277, r31
291 mtspr 278, r31
292 mtspr 279, r31
293 mtspr 285, r31 /* TBU */
294 mtspr 284, r31 /* TBL */
295#if 0
296 mtspr 318, r31 /* DVC1-2 */
297 mtspr 319, r31
298#endif
299 mtspr 562, r31 /* DBCNT */
300 mtspr 570, r31 /* MCSRR0 */
301 mtspr 571, r31 /* MCSRR1 */
302 mtspr 604, r31 /* SPRG8-9 */
303 mtspr 605, r31
304
305#if BOOT_PERFORM_CORE_INIT
306 /*
307 * *Finally* the TLB0 is re-allocated to flash, note, the final phase
308 * is executed from RAM.
309 */
310 e_lis r3, TLB0_MAS0@h
311 mtspr 624, r3 /* MAS0 */
312 e_lis r3, TLB0_MAS1@h
313 e_or2i r3, TLB0_MAS1@l
314 mtspr 625, r3 /* MAS1 */
315 e_lis r3, TLB0_MAS2@h
316 e_or2i r3, TLB0_MAS2@l
317 mtspr 626, r3 /* MAS2 */
318 e_lis r3, TLB0_MAS3@h
319 e_or2i r3, TLB0_MAS3@l
320 mtspr 627, r3 /* MAS3 */
321 mflr r4
322 e_lis r6, _ramcode@h
323 e_or2i r6, _ramcode@l
324 e_lis r7, 0x40010000@h
325 mtctr r7
326 se_lwz r3, 0(r6)
327 se_stw r3, 0(r7)
328 se_lwz r3, 4(r6)
329 se_stw r3, 4(r7)
330 se_lwz r3, 8(r6)
331 se_stw r3, 8(r7)
332 se_bctrl
333 mtlr r4
334#endif /* BOOT_PERFORM_CORE_INIT */
335
336 /*
337 * Branch prediction enabled.
338 */
339 e_li r3, BOOT_BUCSR_DEFAULT
340 mtspr 1013, r3 /* BUCSR */
341
342 /*
343 * Cache invalidated and then enabled.
344 */
345 e_li r3, LICSR1_ICINV
346 mtspr 1011, r3 /* LICSR1 */
347.inv: mfspr r3, 1011 /* LICSR1 */
348 e_and2i. r3, LICSR1_ICINV
349 se_bne .inv
350 e_lis r3, BOOT_LICSR1_DEFAULT@h
351 e_or2i r3, BOOT_LICSR1_DEFAULT@l
352 mtspr 1011, r3 /* LICSR1 */
353
354 se_blr
355
356 /*
357 * Exception vectors initialization.
358 */
359 .align 2
360_ivinit:
361 /* MSR initialization.*/
362 e_lis r3, BOOT_MSR_DEFAULT@h
363 e_or2i r3, BOOT_MSR_DEFAULT@l
364 mtMSR r3
365
366 /* IVPR initialization.*/
367 e_lis r3, __ivpr_base__@h
368 e_or2i r3, __ivpr_base__@l
369 mtIVPR r3
370
371 /* IVORs initialization.*/
372 e_lis r3, _unhandled_exception@h
373 e_or2i r3, _unhandled_exception@l
374
375 mtspr 400, r3 /* IVOR0-15 */
376 mtspr 401, r3
377 mtspr 402, r3
378 mtspr 403, r3
379 mtspr 404, r3
380 mtspr 405, r3
381 mtspr 406, r3
382 mtspr 407, r3
383 mtspr 408, r3
384 mtspr 409, r3
385 mtspr 410, r3
386 mtspr 411, r3
387 mtspr 412, r3
388 mtspr 413, r3
389 mtspr 414, r3
390 mtspr 415, r3
391 mtspr 528, r3 /* IVOR32-34 */
392 mtspr 529, r3
393 mtspr 530, r3
394
395 se_blr
396
397 .section .handlers, "ax"
398
399 /*
400 * Unhandled exceptions handler.
401 */
402 .weak _unhandled_exception
403 .type _unhandled_exception, @function
404_unhandled_exception:
405 se_b _unhandled_exception
406
407#endif /* !defined(__DOXYGEN__) */
408
409/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.h b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.h
new file mode 100644
index 000000000..ee2767a83
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.h
@@ -0,0 +1,248 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file boot.h
19 * @brief Boot parameters for the SPC56ELxx.
20 * @{
21 */
22
23#ifndef BOOT_H
24#define BOOT_H
25
26/*===========================================================================*/
27/* Module constants. */
28/*===========================================================================*/
29
30/**
31 * @name MASx registers definitions
32 * @{
33 */
34#define MAS0_TBLMAS_TBL 0x10000000
35#define MAS0_ESEL_MASK 0x000F0000
36#define MAS0_ESEL(n) ((n) << 16)
37
38#define MAS1_VALID 0x80000000
39#define MAS1_IPROT 0x40000000
40#define MAS1_TID_MASK 0x00FF0000
41#define MAS1_TS 0x00001000
42#define MAS1_TSISE_MASK 0x00000F80
43#define MAS1_TSISE_1K 0x00000000
44#define MAS1_TSISE_2K 0x00000080
45#define MAS1_TSISE_4K 0x00000100
46#define MAS1_TSISE_8K 0x00000180
47#define MAS1_TSISE_16K 0x00000200
48#define MAS1_TSISE_32K 0x00000280
49#define MAS1_TSISE_64K 0x00000300
50#define MAS1_TSISE_128K 0x00000380
51#define MAS1_TSISE_256K 0x00000400
52#define MAS1_TSISE_512K 0x00000480
53#define MAS1_TSISE_1M 0x00000500
54#define MAS1_TSISE_2M 0x00000580
55#define MAS1_TSISE_4M 0x00000600
56#define MAS1_TSISE_8M 0x00000680
57#define MAS1_TSISE_16M 0x00000700
58#define MAS1_TSISE_32M 0x00000780
59#define MAS1_TSISE_64M 0x00000800
60#define MAS1_TSISE_128M 0x00000880
61#define MAS1_TSISE_256M 0x00000900
62#define MAS1_TSISE_512M 0x00000980
63#define MAS1_TSISE_1G 0x00000A00
64#define MAS1_TSISE_2G 0x00000A80
65#define MAS1_TSISE_4G 0x00000B00
66
67#define MAS2_EPN_MASK 0xFFFFFC00
68#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
69#define MAS2_EBOOK 0x00000000
70#define MAS2_VLE 0x00000020
71#define MAS2_W 0x00000010
72#define MAS2_I 0x00000008
73#define MAS2_M 0x00000004
74#define MAS2_G 0x00000002
75#define MAS2_E 0x00000001
76
77#define MAS3_RPN_MASK 0xFFFFFC00
78#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
79#define MAS3_U0 0x00000200
80#define MAS3_U1 0x00000100
81#define MAS3_U2 0x00000080
82#define MAS3_U3 0x00000040
83#define MAS3_UX 0x00000020
84#define MAS3_SX 0x00000010
85#define MAS3_UW 0x00000008
86#define MAS3_SW 0x00000004
87#define MAS3_UR 0x00000002
88#define MAS3_SR 0x00000001
89/** @} */
90
91/**
92 * @name BUCSR registers definitions
93 * @{
94 */
95#define BUCSR_BPEN 0x00000001
96#define BUCSR_BPRED_MASK 0x00000006
97#define BUCSR_BPRED_0 0x00000000
98#define BUCSR_BPRED_1 0x00000002
99#define BUCSR_BPRED_2 0x00000004
100#define BUCSR_BPRED_3 0x00000006
101#define BUCSR_BALLOC_MASK 0x00000030
102#define BUCSR_BALLOC_0 0x00000000
103#define BUCSR_BALLOC_1 0x00000010
104#define BUCSR_BALLOC_2 0x00000020
105#define BUCSR_BALLOC_3 0x00000030
106#define BUCSR_BALLOC_BFI 0x00000200
107/** @} */
108
109/**
110 * @name LICSR1 registers definitions
111 * @{
112 */
113#define LICSR1_ICE 0x00000001
114#define LICSR1_ICINV 0x00000002
115#define LICSR1_ICORG 0x00000010
116/** @} */
117
118/**
119 * @name MSR register definitions
120 * @{
121 */
122#define MSR_UCLE 0x04000000
123#define MSR_SPE 0x02000000
124#define MSR_WE 0x00040000
125#define MSR_CE 0x00020000
126#define MSR_EE 0x00008000
127#define MSR_PR 0x00004000
128#define MSR_FP 0x00002000
129#define MSR_ME 0x00001000
130#define MSR_FE0 0x00000800
131#define MSR_DE 0x00000200
132#define MSR_FE1 0x00000100
133#define MSR_IS 0x00000020
134#define MSR_DS 0x00000010
135#define MSR_RI 0x00000002
136/** @} */
137
138/*===========================================================================*/
139/* Module pre-compile time settings. */
140/*===========================================================================*/
141
142/*
143 * TLB default settings.
144 */
145#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
146#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M)
147#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
148#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \
149 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
150 MAS3_UR | MAS3_SR)
151
152#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
153#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
154#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
155#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \
156 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
157 MAS3_UR | MAS3_SR)
158
159#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
160#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
161#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
162#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
163 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
164
165#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
166#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
167#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
168#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
169 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
170
171#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
172#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
173#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I)
174#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \
175 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
176
177#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
178#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
179#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
180#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \
181 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
182
183/*
184 * BUCSR default settings.
185 */
186#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
187#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
188 BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
189#endif
190
191/*
192 * LICSR1 default settings.
193 */
194#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
195#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
196#endif
197
198/*
199 * MSR default settings.
200 */
201#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
202#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
203#endif
204
205/*
206 * Boot default settings.
207 */
208#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
209#define BOOT_PERFORM_CORE_INIT 1
210#endif
211
212/*
213 * VLE mode default settings.
214 */
215#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
216#define BOOT_USE_VLE 1
217#endif
218
219/*
220 * RAM relocation flag.
221 */
222#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
223#define BOOT_RELOCATE_IN_RAM 0
224#endif
225
226/*===========================================================================*/
227/* Derived constants and error checks. */
228/*===========================================================================*/
229
230/*===========================================================================*/
231/* Module data structures and types. */
232/*===========================================================================*/
233
234/*===========================================================================*/
235/* Module macros. */
236/*===========================================================================*/
237
238/*===========================================================================*/
239/* External declarations. */
240/*===========================================================================*/
241
242/*===========================================================================*/
243/* Module inline functions. */
244/*===========================================================================*/
245
246#endif /* BOOT_H */
247
248/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/intc.h b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/intc.h
new file mode 100644
index 000000000..52fed877b
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/intc.h
@@ -0,0 +1,93 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ELxx/intc.h
19 * @brief SPC56ELxx INTC module header.
20 *
21 * @addtogroup INTC
22 * @{
23 */
24
25#ifndef INTC_H
26#define INTC_H
27
28/*===========================================================================*/
29/* Module constants. */
30/*===========================================================================*/
31
32/**
33 * @name INTC addresses
34 * @{
35 */
36#define INTC_BASE 0xFFF48000
37#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
38#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
39/** @} */
40
41/**
42 * @brief INTC priority levels.
43 */
44#define INTC_PRIORITY_LEVELS 16U
45
46/*===========================================================================*/
47/* Module pre-compile time settings. */
48/*===========================================================================*/
49
50/*===========================================================================*/
51/* Derived constants and error checks. */
52/*===========================================================================*/
53
54/*===========================================================================*/
55/* Module data structures and types. */
56/*===========================================================================*/
57
58/*===========================================================================*/
59/* Module macros. */
60/*===========================================================================*/
61
62/**
63 * @name INTC-related macros
64 * @{
65 */
66#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
67#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
68#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
69#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
70#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
71/** @} */
72
73/**
74 * @brief Core selection macros for PSR register.
75 */
76#define INTC_PSR_CORE0 0x00
77
78/**
79 * @brief PSR register content helper
80 */
81#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
82
83/*===========================================================================*/
84/* External declarations. */
85/*===========================================================================*/
86
87/*===========================================================================*/
88/* Module inline functions. */
89/*===========================================================================*/
90
91#endif /* INTC_H */
92
93/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h
new file mode 100644
index 000000000..450a58b0b
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h
@@ -0,0 +1,83 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ELxx/ppcparams.h
19 * @brief PowerPC parameters for the SPC56ELxx.
20 *
21 * @defgroup PPC_SPC56ELxx SPC56ELxx Specific Parameters
22 * @ingroup PPC_SPECIFIC
23 * @details This file contains the PowerPC specific parameters for the
24 * SPC56ELxx platform.
25 * @{
26 */
27
28#ifndef PPCPARAMS_H
29#define PPCPARAMS_H
30
31/**
32 * @brief Family identification macro.
33 */
34#define PPC_SPC56ELxx
35
36/**
37 * @brief PPC core model.
38 */
39#define PPC_VARIANT PPC_VARIANT_e200z4
40
41/**
42 * @brief Number of cores.
43 */
44#define PPC_CORE_NUMBER 1
45
46/**
47 * @brief Number of writable bits in IVPR register.
48 */
49#define PPC_IVPR_BITS 16
50
51/**
52 * @brief IVORx registers support.
53 */
54#define PPC_SUPPORTS_IVORS TRUE
55
56/**
57 * @brief Book E instruction set support.
58 */
59#define PPC_SUPPORTS_BOOKE TRUE
60
61/**
62 * @brief VLE instruction set support.
63 */
64#define PPC_SUPPORTS_VLE TRUE
65
66/**
67 * @brief Supports VLS Load/Store Multiple Volatile instructions.
68 */
69#define PPC_SUPPORTS_VLE_MULTI TRUE
70
71/**
72 * @brief Supports the decrementer timer.
73 */
74#define PPC_SUPPORTS_DECREMENTER TRUE
75
76/**
77 * @brief Number of interrupt sources.
78 */
79#define PPC_NUM_VECTORS 256
80
81#endif /* PPCPARAMS_H */
82
83/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 13:27:42 +0100