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diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot_ghs.s b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot_ghs.s
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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ECxx/boot_ghs.s
19 * @brief SPC56ECxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if !defined(__DOXYGEN__)
28
29 .vle
30
31 /* BAM record.*/
32 .section .boot, "axv"
33
34#if BOOT_USE_VLE
35 .long 0x015A0000
36#else
37 .long 0x005A0000
38#endif
39 .long _reset_address
40
41 .align 2
42 .globl _reset_address
43 .type _reset_address, @function
44_reset_address:
45#if BOOT_PERFORM_CORE_INIT
46 se_bl _coreinit
47#endif
48 se_bl _ivinit
49
50#if BOOT_RELOCATE_IN_RAM
51 /*
52 * Image relocation in RAM.
53 */
54 e_lis r4, __ram_reloc_start__@h
55 e_or2i r4, __ram_reloc_start__@l
56 e_lis r5, __ram_reloc_dest__@h
57 e_or2i r5, __ram_reloc_dest__@l
58 e_lis r6, __ram_reloc_end__@h
59 e_or2i r6, r6, __ram_reloc_end__@l
60.relloop:
61 se_cmpl r4, r6
62 se_bge .relend
63 se_lwz r7, 0(r4)
64 se_addi r4, 4
65 se_stw r7, 0(r5)
66 se_addi r5, 4
67 se_b .relloop
68.relend:
69 e_lis r3, _boot_address@h
70 e_or2i r3, _boot_address@l
71 mtctr r3
72 se_bctrl
73#else
74 e_b _boot_address
75#endif
76
77#if BOOT_PERFORM_CORE_INIT
78 .align 2
79_ramcode:
80 tlbwe
81 se_isync
82 se_blr
83
84 .align 2
85_coreinit:
86 /*
87 * Invalidating all TLBs except TLB0.
88 */
89 e_lis r3, 0
90 mtspr 625, r3 /* MAS1 */
91 mtspr 626, r3 /* MAS2 */
92 mtspr 627, r3 /* MAS3 */
93 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
94 mtspr 624, r3 /* MAS0 */
95 tlbwe
96 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
97 mtspr 624, r3 /* MAS0 */
98 tlbwe
99 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
100 mtspr 624, r3 /* MAS0 */
101 tlbwe
102 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
103 mtspr 624, r3 /* MAS0 */
104 tlbwe
105 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
106 mtspr 624, r3 /* MAS0 */
107 tlbwe
108 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
109 mtspr 624, r3 /* MAS0 */
110 tlbwe
111 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
112 mtspr 624, r3 /* MAS0 */
113 tlbwe
114 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
115 mtspr 624, r3 /* MAS0 */
116 tlbwe
117 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
118 mtspr 624, r3 /* MAS0 */
119 tlbwe
120 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
121 mtspr 624, r3 /* MAS0 */
122 tlbwe
123 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
124 mtspr 624, r3 /* MAS0 */
125 tlbwe
126 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
127 mtspr 624, r3 /* MAS0 */
128 tlbwe
129 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
130 mtspr 624, r3 /* MAS0 */
131 tlbwe
132 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
133 mtspr 624, r3 /* MAS0 */
134 tlbwe
135 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
136 mtspr 624, r3 /* MAS0 */
137 tlbwe
138
139 /*
140 * TLB1 allocated to internal RAM.
141 */
142 e_lis r3, TLB1_MAS0@h
143 mtspr 624, r3 /* MAS0 */
144 e_lis r3, TLB1_MAS1@h
145 e_or2i r3, TLB1_MAS1@l
146 mtspr 625, r3 /* MAS1 */
147 e_lis r3, TLB1_MAS2@h
148 e_or2i r3, TLB1_MAS2@l
149 mtspr 626, r3 /* MAS2 */
150 e_lis r3, TLB1_MAS3@h
151 e_or2i r3, TLB1_MAS3@l
152 mtspr 627, r3 /* MAS3 */
153 tlbwe
154
155 /*
156 * TLB2 allocated to internal Peripherals Bridge A.
157 */
158 e_lis r3, TLB2_MAS0@h
159 mtspr 624, r3 /* MAS0 */
160 e_lis r3, TLB2_MAS1@h
161 e_or2i r3, TLB2_MAS1@l
162 mtspr 625, r3 /* MAS1 */
163 e_lis r3, TLB2_MAS2@h
164 e_or2i r3, TLB2_MAS2@l
165 mtspr 626, r3 /* MAS2 */
166 e_lis r3, TLB2_MAS3@h
167 e_or2i r3, TLB2_MAS3@l
168 mtspr 627, r3 /* MAS3 */
169 tlbwe
170
171 /*
172 * TLB3 allocated to internal Peripherals Bridge B.
173 */
174 e_lis r3, TLB3_MAS0@h
175 mtspr 624, r3 /* MAS0 */
176 e_lis r3, TLB3_MAS1@h
177 e_or2i r3, TLB3_MAS1@l
178 mtspr 625, r3 /* MAS1 */
179 e_lis r3, TLB3_MAS2@h
180 e_or2i r3, TLB3_MAS2@l
181 mtspr 626, r3 /* MAS2 */
182 e_lis r3, TLB3_MAS3@h
183 e_or2i r3, TLB3_MAS3@l
184 mtspr 627, r3 /* MAS3 */
185 tlbwe
186
187 /*
188 * TLB4 allocated to on-platform peripherals.
189 */
190 e_lis r3, TLB4_MAS0@h
191 mtspr 624, r3 /* MAS0 */
192 e_lis r3, TLB4_MAS1@h
193 e_or2i r3, TLB4_MAS1@l
194 mtspr 625, r3 /* MAS1 */
195 e_lis r3, TLB4_MAS2@h
196 e_or2i r3, TLB4_MAS2@l
197 mtspr 626, r3 /* MAS2 */
198 e_lis r3, TLB4_MAS3@h
199 e_or2i r3, TLB4_MAS3@l
200 mtspr 627, r3 /* MAS3 */
201 tlbwe
202
203 /*
204 * TLB5 allocated to on-platform peripherals.
205 */
206 e_lis r3, TLB5_MAS0@h
207 mtspr 624, r3 /* MAS0 */
208 e_lis r3, TLB5_MAS1@h
209 e_or2i r3, TLB5_MAS1@l
210 mtspr 625, r3 /* MAS1 */
211 e_lis r3, TLB5_MAS2@h
212 e_or2i r3, TLB5_MAS2@l
213 mtspr 626, r3 /* MAS2 */
214 e_lis r3, TLB5_MAS3@h
215 e_or2i r3, TLB5_MAS3@l
216 mtspr 627, r3 /* MAS3 */
217 tlbwe
218
219 /*
220 * RAM clearing, this device requires a write to all RAM location in
221 * order to initialize the ECC detection hardware, this is going to
222 * slow down the startup but there is no way around.
223 */
224 xor r0, r0, r0
225 xor r1, r1, r1
226 xor r2, r2, r2
227 xor r3, r3, r3
228 xor r4, r4, r4
229 xor r5, r5, r5
230 xor r6, r6, r6
231 xor r7, r7, r7
232 xor r8, r8, r8
233 xor r9, r9, r9
234 xor r10, r10, r10
235 xor r11, r11, r11
236 xor r12, r12, r12
237 xor r13, r13, r13
238 xor r14, r14, r14
239 xor r15, r15, r15
240 xor r16, r16, r16
241 xor r17, r17, r17
242 xor r18, r18, r18
243 xor r19, r19, r19
244 xor r20, r20, r20
245 xor r21, r21, r21
246 xor r22, r22, r22
247 xor r23, r23, r23
248 xor r24, r24, r24
249 xor r25, r25, r25
250 xor r26, r26, r26
251 xor r27, r27, r27
252 xor r28, r28, r28
253 xor r29, r29, r29
254 xor r30, r30, r30
255 xor r31, r31, r31
256 e_lis r4, __ram_start__@h
257 e_or2i r4, __ram_start__@l
258 e_lis r5, __ram_end__@h
259 e_or2i r5, __ram_end__@l
260.cleareccloop:
261 se_cmpl r4, r5
262 se_bge .cleareccend
263 e_stmw r16, 0(r4)
264 e_addi r4, r4, 64
265 se_b .cleareccloop
266.cleareccend:
267
268 /*
269 * Special function registers clearing, required in order to avoid
270 * possible problems with lockstep mode.
271 */
272 mtcrf 0xFF, r31
273 mtspr 9, r31 /* CTR */
274 mtspr 22, r31 /* DEC */
275 mtspr 26, r31 /* SRR0-1 */
276 mtspr 27, r31
277 mtspr 54, r31 /* DECAR */
278 mtspr 58, r31 /* CSRR0-1 */
279 mtspr 59, r31
280 mtspr 61, r31 /* DEAR */
281 mtspr 256, r31 /* USPRG0 */
282 mtspr 272, r31 /* SPRG1-7 */
283 mtspr 273, r31
284 mtspr 274, r31
285 mtspr 275, r31
286 mtspr 276, r31
287 mtspr 277, r31
288 mtspr 278, r31
289 mtspr 279, r31
290 mtspr 285, r31 /* TBU */
291 mtspr 284, r31 /* TBL */
292#if 0
293 mtspr 318, r31 /* DVC1-2 */
294 mtspr 319, r31
295#endif
296 mtspr 562, r31 /* DBCNT */
297 mtspr 570, r31 /* MCSRR0 */
298 mtspr 571, r31 /* MCSRR1 */
299 mtspr 604, r31 /* SPRG8-9 */
300 mtspr 605, r31
301
302 /*
303 * *Finally* the TLB0 is re-allocated to flash, note, the final phase
304 * is executed from RAM.
305 */
306 e_lis r3, TLB0_MAS0@h
307 mtspr 624, r3 /* MAS0 */
308 e_lis r3, TLB0_MAS1@h
309 e_or2i r3, TLB0_MAS1@l
310 mtspr 625, r3 /* MAS1 */
311 e_lis r3, TLB0_MAS2@h
312 e_or2i r3, TLB0_MAS2@l
313 mtspr 626, r3 /* MAS2 */
314 e_lis r3, TLB0_MAS3@h
315 e_or2i r3, TLB0_MAS3@l
316 mtspr 627, r3 /* MAS3 */
317 mflr r4
318 e_lis r6, _ramcode@h
319 e_or2i r6, _ramcode@l
320 e_lis r7, 0x40010000@h
321 mtctr r7
322 se_lwz r3, 0(r6)
323 se_stw r3, 0(r7)
324 se_lwz r3, 4(r6)
325 se_stw r3, 4(r7)
326 se_lwz r3, 8(r6)
327 se_stw r3, 8(r7)
328 se_bctrl
329 mtlr r4
330
331 /*
332 * Branch prediction enabled.
333 */
334 e_li r3, BOOT_BUCSR_DEFAULT
335 mtspr 1013, r3 /* BUCSR */
336
337 /*
338 * Cache invalidated and then enabled.
339 */
340 e_li r3, LICSR1_ICINV
341 mtspr 1011, r3 /* LICSR1 */
342.inv: mfspr r3, 1011 /* LICSR1 */
343 e_and2i. r3, LICSR1_ICINV
344 se_bne .inv
345 e_lis r3, BOOT_LICSR1_DEFAULT@h
346 e_or2i r3, BOOT_LICSR1_DEFAULT@l
347 mtspr 1011, r3 /* LICSR1 */
348
349 se_blr
350#endif /* BOOT_PERFORM_CORE_INIT */
351
352 /*
353 * Exception vectors initialization.
354 */
355 .align 2
356_ivinit:
357 /* MSR initialization.*/
358 e_lis r3, BOOT_MSR_DEFAULT@h
359 e_or2i r3, BOOT_MSR_DEFAULT@l
360 mtMSR r3
361
362 /* IVPR initialization.*/
363 e_lis r3, __ivpr_base__@h
364 e_or2i r3, __ivpr_base__@l
365 mtIVPR r3
366
367 /* IVORs initialization.*/
368 e_lis r3, _unhandled_exception@h
369 e_or2i r3, _unhandled_exception@l
370
371 mtspr 400, r3 /* IVOR0-15 */
372 mtspr 401, r3
373 mtspr 402, r3
374 mtspr 403, r3
375 mtspr 404, r3
376 mtspr 405, r3
377 mtspr 406, r3
378 mtspr 407, r3
379 mtspr 408, r3
380 mtspr 409, r3
381 mtspr 410, r3
382 mtspr 411, r3
383 mtspr 412, r3
384 mtspr 413, r3
385 mtspr 414, r3
386 mtspr 415, r3
387 mtspr 528, r3 /* IVOR32-34 */
388 mtspr 529, r3
389 mtspr 530, r3
390
391 se_blr
392
393 .section .handlers, "axv"
394
395 /*
396 * Unhandled exceptions handler.
397 */
398 .weak _unhandled_exception
399 .type _unhandled_exception, @function
400_unhandled_exception:
401 se_b _unhandled_exception
402
403#endif /* !defined(__DOXYGEN__) */
404
405/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-31 13:23:11 +0100