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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ECxx/boot.s
19 * @brief SPC56ECxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if defined(__HIGHTEC__)
28#define se_bge bge
29#define se_bne bne
30#endif
31
32#if !defined(__DOXYGEN__)
33
34 /* BAM record.*/
35 .section .boot, "ax"
36
37#if BOOT_USE_VLE
38 .long 0x015A0000
39#else
40 .long 0x005A0000
41#endif
42 .long _reset_address
43
44 .align 2
45 .globl _reset_address
46 .type _reset_address, @function
47_reset_address:
48#if BOOT_PERFORM_CORE_INIT
49 e_bl _coreinit
50#endif
51 e_bl _ivinit
52
53#if BOOT_RELOCATE_IN_RAM
54 /*
55 * Image relocation in RAM.
56 */
57 e_lis r4, __ram_reloc_start__@h
58 e_or2i r4, __ram_reloc_start__@l
59 e_lis r5, __ram_reloc_dest__@h
60 e_or2i r5, __ram_reloc_dest__@l
61 e_lis r6, __ram_reloc_end__@h
62 e_or2i r6, r6, __ram_reloc_end__@l
63.relloop:
64 se_cmpl r4, r6
65 se_bge .relend
66 se_lwz r7, 0(r4)
67 se_addi r4, 4
68 se_stw r7, 0(r5)
69 se_addi r5, 4
70 se_b .relloop
71.relend:
72 e_lis r3, _boot_address@h
73 e_or2i r3, _boot_address@l
74 mtctr r3
75 se_bctrl
76#else
77 e_b _boot_address
78#endif
79
80#if BOOT_PERFORM_CORE_INIT
81 .align 2
82_ramcode:
83 tlbwe
84 se_isync
85 se_blr
86
87 .align 2
88_coreinit:
89 /*
90 * Invalidating all TLBs except TLB0.
91 */
92 e_lis r3, 0
93 mtspr 625, r3 /* MAS1 */
94 mtspr 626, r3 /* MAS2 */
95 mtspr 627, r3 /* MAS3 */
96 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
97 mtspr 624, r3 /* MAS0 */
98 tlbwe
99 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
100 mtspr 624, r3 /* MAS0 */
101 tlbwe
102 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
103 mtspr 624, r3 /* MAS0 */
104 tlbwe
105 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
106 mtspr 624, r3 /* MAS0 */
107 tlbwe
108 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
109 mtspr 624, r3 /* MAS0 */
110 tlbwe
111 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
112 mtspr 624, r3 /* MAS0 */
113 tlbwe
114 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
115 mtspr 624, r3 /* MAS0 */
116 tlbwe
117 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
118 mtspr 624, r3 /* MAS0 */
119 tlbwe
120 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
121 mtspr 624, r3 /* MAS0 */
122 tlbwe
123 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
124 mtspr 624, r3 /* MAS0 */
125 tlbwe
126 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
127 mtspr 624, r3 /* MAS0 */
128 tlbwe
129 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
130 mtspr 624, r3 /* MAS0 */
131 tlbwe
132 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
133 mtspr 624, r3 /* MAS0 */
134 tlbwe
135 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
136 mtspr 624, r3 /* MAS0 */
137 tlbwe
138 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
139 mtspr 624, r3 /* MAS0 */
140 tlbwe
141
142 /*
143 * TLB1 allocated to internal RAM.
144 */
145 e_lis r3, TLB1_MAS0@h
146 mtspr 624, r3 /* MAS0 */
147 e_lis r3, TLB1_MAS1@h
148 e_or2i r3, TLB1_MAS1@l
149 mtspr 625, r3 /* MAS1 */
150 e_lis r3, TLB1_MAS2@h
151 e_or2i r3, TLB1_MAS2@l
152 mtspr 626, r3 /* MAS2 */
153 e_lis r3, TLB1_MAS3@h
154 e_or2i r3, TLB1_MAS3@l
155 mtspr 627, r3 /* MAS3 */
156 tlbwe
157
158 /*
159 * TLB2 allocated to internal Peripherals Bridge A.
160 */
161 e_lis r3, TLB2_MAS0@h
162 mtspr 624, r3 /* MAS0 */
163 e_lis r3, TLB2_MAS1@h
164 e_or2i r3, TLB2_MAS1@l
165 mtspr 625, r3 /* MAS1 */
166 e_lis r3, TLB2_MAS2@h
167 e_or2i r3, TLB2_MAS2@l
168 mtspr 626, r3 /* MAS2 */
169 e_lis r3, TLB2_MAS3@h
170 e_or2i r3, TLB2_MAS3@l
171 mtspr 627, r3 /* MAS3 */
172 tlbwe
173
174 /*
175 * TLB3 allocated to internal Peripherals Bridge B.
176 */
177 e_lis r3, TLB3_MAS0@h
178 mtspr 624, r3 /* MAS0 */
179 e_lis r3, TLB3_MAS1@h
180 e_or2i r3, TLB3_MAS1@l
181 mtspr 625, r3 /* MAS1 */
182 e_lis r3, TLB3_MAS2@h
183 e_or2i r3, TLB3_MAS2@l
184 mtspr 626, r3 /* MAS2 */
185 e_lis r3, TLB3_MAS3@h
186 e_or2i r3, TLB3_MAS3@l
187 mtspr 627, r3 /* MAS3 */
188 tlbwe
189
190 /*
191 * TLB4 allocated to on-platform peripherals.
192 */
193 e_lis r3, TLB4_MAS0@h
194 mtspr 624, r3 /* MAS0 */
195 e_lis r3, TLB4_MAS1@h
196 e_or2i r3, TLB4_MAS1@l
197 mtspr 625, r3 /* MAS1 */
198 e_lis r3, TLB4_MAS2@h
199 e_or2i r3, TLB4_MAS2@l
200 mtspr 626, r3 /* MAS2 */
201 e_lis r3, TLB4_MAS3@h
202 e_or2i r3, TLB4_MAS3@l
203 mtspr 627, r3 /* MAS3 */
204 tlbwe
205
206 /*
207 * TLB5 allocated to on-platform peripherals.
208 */
209 e_lis r3, TLB5_MAS0@h
210 mtspr 624, r3 /* MAS0 */
211 e_lis r3, TLB5_MAS1@h
212 e_or2i r3, TLB5_MAS1@l
213 mtspr 625, r3 /* MAS1 */
214 e_lis r3, TLB5_MAS2@h
215 e_or2i r3, TLB5_MAS2@l
216 mtspr 626, r3 /* MAS2 */
217 e_lis r3, TLB5_MAS3@h
218 e_or2i r3, TLB5_MAS3@l
219 mtspr 627, r3 /* MAS3 */
220 tlbwe
221
222 /*
223 * RAM clearing, this device requires a write to all RAM location in
224 * order to initialize the ECC detection hardware, this is going to
225 * slow down the startup but there is no way around.
226 */
227 xor r0, r0, r0
228 xor r1, r1, r1
229 xor r2, r2, r2
230 xor r3, r3, r3
231 xor r4, r4, r4
232 xor r5, r5, r5
233 xor r6, r6, r6
234 xor r7, r7, r7
235 xor r8, r8, r8
236 xor r9, r9, r9
237 xor r10, r10, r10
238 xor r11, r11, r11
239 xor r12, r12, r12
240 xor r13, r13, r13
241 xor r14, r14, r14
242 xor r15, r15, r15
243 xor r16, r16, r16
244 xor r17, r17, r17
245 xor r18, r18, r18
246 xor r19, r19, r19
247 xor r20, r20, r20
248 xor r21, r21, r21
249 xor r22, r22, r22
250 xor r23, r23, r23
251 xor r24, r24, r24
252 xor r25, r25, r25
253 xor r26, r26, r26
254 xor r27, r27, r27
255 xor r28, r28, r28
256 xor r29, r29, r29
257 xor r30, r30, r30
258 xor r31, r31, r31
259 e_lis r4, __ram_start__@h
260 e_or2i r4, __ram_start__@l
261 e_lis r5, __ram_end__@h
262 e_or2i r5, __ram_end__@l
263.cleareccloop:
264 se_cmpl r4, r5
265 se_bge .cleareccend
266 e_stmw r16, 0(r4)
267 e_addi r4, r4, 64
268 se_b .cleareccloop
269.cleareccend:
270
271 /*
272 * Special function registers clearing, required in order to avoid
273 * possible problems with lockstep mode.
274 */
275 mtcrf 0xFF, r31
276 mtspr 9, r31 /* CTR */
277 mtspr 22, r31 /* DEC */
278 mtspr 26, r31 /* SRR0-1 */
279 mtspr 27, r31
280 mtspr 54, r31 /* DECAR */
281 mtspr 58, r31 /* CSRR0-1 */
282 mtspr 59, r31
283 mtspr 61, r31 /* DEAR */
284 mtspr 256, r31 /* USPRG0 */
285 mtspr 272, r31 /* SPRG1-7 */
286 mtspr 273, r31
287 mtspr 274, r31
288 mtspr 275, r31
289 mtspr 276, r31
290 mtspr 277, r31
291 mtspr 278, r31
292 mtspr 279, r31
293 mtspr 285, r31 /* TBU */
294 mtspr 284, r31 /* TBL */
295#if 0
296 mtspr 318, r31 /* DVC1-2 */
297 mtspr 319, r31
298#endif
299 mtspr 562, r31 /* DBCNT */
300 mtspr 570, r31 /* MCSRR0 */
301 mtspr 571, r31 /* MCSRR1 */
302 mtspr 604, r31 /* SPRG8-9 */
303 mtspr 605, r31
304
305 /*
306 * *Finally* the TLB0 is re-allocated to flash, note, the final phase
307 * is executed from RAM.
308 */
309 e_lis r3, TLB0_MAS0@h
310 mtspr 624, r3 /* MAS0 */
311 e_lis r3, TLB0_MAS1@h
312 e_or2i r3, TLB0_MAS1@l
313 mtspr 625, r3 /* MAS1 */
314 e_lis r3, TLB0_MAS2@h
315 e_or2i r3, TLB0_MAS2@l
316 mtspr 626, r3 /* MAS2 */
317 e_lis r3, TLB0_MAS3@h
318 e_or2i r3, TLB0_MAS3@l
319 mtspr 627, r3 /* MAS3 */
320 mflr r4
321 e_lis r6, _ramcode@h
322 e_or2i r6, _ramcode@l
323 e_lis r7, 0x40010000@h
324 mtctr r7
325 se_lwz r3, 0(r6)
326 se_stw r3, 0(r7)
327 se_lwz r3, 4(r6)
328 se_stw r3, 4(r7)
329 se_lwz r3, 8(r6)
330 se_stw r3, 8(r7)
331 se_bctrl
332 mtlr r4
333
334 /*
335 * Branch prediction enabled.
336 */
337 e_li r3, BOOT_BUCSR_DEFAULT
338 mtspr 1013, r3 /* BUCSR */
339
340 /*
341 * Cache invalidated and then enabled.
342 */
343 e_li r3, LICSR1_ICINV
344 mtspr 1011, r3 /* LICSR1 */
345.inv: mfspr r3, 1011 /* LICSR1 */
346 e_and2i. r3, LICSR1_ICINV
347 se_bne .inv
348 e_lis r3, BOOT_LICSR1_DEFAULT@h
349 e_or2i r3, BOOT_LICSR1_DEFAULT@l
350 mtspr 1011, r3 /* LICSR1 */
351
352 se_blr
353#endif /* BOOT_PERFORM_CORE_INIT */
354
355 /*
356 * Exception vectors initialization.
357 */
358 .align 2
359_ivinit:
360 /* MSR initialization.*/
361 e_lis r3, BOOT_MSR_DEFAULT@h
362 e_or2i r3, BOOT_MSR_DEFAULT@l
363 mtMSR r3
364
365 /* IVPR initialization.*/
366 e_lis r3, __ivpr_base__@h
367 e_or2i r3, __ivpr_base__@l
368 mtIVPR r3
369
370 /* IVORs initialization.*/
371 e_lis r3, _unhandled_exception@h
372 e_or2i r3, _unhandled_exception@l
373
374 mtspr 400, r3 /* IVOR0-15 */
375 mtspr 401, r3
376 mtspr 402, r3
377 mtspr 403, r3
378 mtspr 404, r3
379 mtspr 405, r3
380 mtspr 406, r3
381 mtspr 407, r3
382 mtspr 408, r3
383 mtspr 409, r3
384 mtspr 410, r3
385 mtspr 411, r3
386 mtspr 412, r3
387 mtspr 413, r3
388 mtspr 414, r3
389 mtspr 415, r3
390 mtspr 528, r3 /* IVOR32-34 */
391 mtspr 529, r3
392 mtspr 530, r3
393
394 se_blr
395
396 .section .handlers, "ax"
397
398 /*
399 * Unhandled exceptions handler.
400 */
401 .weak _unhandled_exception
402 .type _unhandled_exception, @function
403_unhandled_exception:
404 se_b _unhandled_exception
405
406#endif /* !defined(__DOXYGEN__) */
407
408/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 13:57:12 +0100