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diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot_cw.s b/lib/chibios/os/common/startup/e200/devices/SPC56ECxx/boot_cw.s
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1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ECxx/boot.s
19 * @brief SPC56ECxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if !defined(__DOXYGEN__)
28
29 .extern _boot_address
30 .extern __ram_start__
31 .extern __ram_end__
32 .extern __ivpr_base__
33
34 .extern _unhandled_exception
35
36 /* BAM record.*/
37 .section .boot, 16
38
39#if BOOT_USE_VLE
40 .long 0x015A0000
41#else
42 .long 0x005A0000
43#endif
44 .long _reset_address
45
46 .align 4
47 .globl _reset_address
48 .type _reset_address, @function
49_reset_address:
50#if BOOT_PERFORM_CORE_INIT
51 e_bl _coreinit
52#endif
53 e_bl _ivinit
54
55#if BOOT_RELOCATE_IN_RAM
56 /*
57 * Image relocation in RAM.
58 */
59 e_lis r4, __ram_reloc_start__@h
60 e_or2i r4, r4, __ram_reloc_start__@l
61 e_lis r5, __ram_reloc_dest__@h
62 e_or2i r5, r5, __ram_reloc_dest__@l
63 e_lis r6, __ram_reloc_end__@h
64 e_or2i r6, r6, __ram_reloc_end__@l
65.relloop:
66 se_cmpl r4, r6
67 se_bge .relend
68 se_lwz r7, 0(r4)
69 se_addi r4, 4
70 se_stw r7, 0(r5)
71 se_addi r5, 4
72 se_b .relloop
73.relend:
74 e_lis r3, _boot_address@h
75 e_or2i r3, _boot_address@l
76 mtctr r3
77 se_bctrl
78#else
79 e_b _boot_address
80#endif
81
82#if BOOT_PERFORM_CORE_INIT
83 .align 4
84_ramcode:
85 tlbwe
86 se_isync
87 se_blr
88
89 .align 2
90_coreinit:
91 /*
92 * Invalidating all TLBs except TLB0.
93 */
94 e_lis r3, 0
95 mtspr 625, r3 /* MAS1 */
96 mtspr 626, r3 /* MAS2 */
97 mtspr 627, r3 /* MAS3 */
98 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
99 mtspr 624, r3 /* MAS0 */
100 tlbwe
101 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
102 mtspr 624, r3 /* MAS0 */
103 tlbwe
104 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
105 mtspr 624, r3 /* MAS0 */
106 tlbwe
107 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
108 mtspr 624, r3 /* MAS0 */
109 tlbwe
110 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
111 mtspr 624, r3 /* MAS0 */
112 tlbwe
113 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
114 mtspr 624, r3 /* MAS0 */
115 tlbwe
116 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
117 mtspr 624, r3 /* MAS0 */
118 tlbwe
119 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
120 mtspr 624, r3 /* MAS0 */
121 tlbwe
122 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
123 mtspr 624, r3 /* MAS0 */
124 tlbwe
125 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
126 mtspr 624, r3 /* MAS0 */
127 tlbwe
128 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
129 mtspr 624, r3 /* MAS0 */
130 tlbwe
131 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
132 mtspr 624, r3 /* MAS0 */
133 tlbwe
134 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
135 mtspr 624, r3 /* MAS0 */
136 tlbwe
137 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
138 mtspr 624, r3 /* MAS0 */
139 tlbwe
140 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
141 mtspr 624, r3 /* MAS0 */
142 tlbwe
143
144 /*
145 * TLB1 allocated to internal RAM.
146 */
147 e_lis r3, TLB1_MAS0@h
148 mtspr 624, r3 /* MAS0 */
149 e_lis r3, TLB1_MAS1@h
150 e_or2i r3, TLB1_MAS1@l
151 mtspr 625, r3 /* MAS1 */
152 e_lis r3, TLB1_MAS2@h
153 e_or2i r3, TLB1_MAS2@l
154 mtspr 626, r3 /* MAS2 */
155 e_lis r3, TLB1_MAS3@h
156 e_or2i r3, TLB1_MAS3@l
157 mtspr 627, r3 /* MAS3 */
158 tlbwe
159
160 /*
161 * TLB2 allocated to internal Peripherals Bridge A.
162 */
163 e_lis r3, TLB2_MAS0@h
164 mtspr 624, r3 /* MAS0 */
165 e_lis r3, TLB2_MAS1@h
166 e_or2i r3, TLB2_MAS1@l
167 mtspr 625, r3 /* MAS1 */
168 e_lis r3, TLB2_MAS2@h
169 e_or2i r3, TLB2_MAS2@l
170 mtspr 626, r3 /* MAS2 */
171 e_lis r3, TLB2_MAS3@h
172 e_or2i r3, TLB2_MAS3@l
173 mtspr 627, r3 /* MAS3 */
174 tlbwe
175
176 /*
177 * TLB3 allocated to internal Peripherals Bridge B.
178 */
179 e_lis r3, TLB3_MAS0@h
180 mtspr 624, r3 /* MAS0 */
181 e_lis r3, TLB3_MAS1@h
182 e_or2i r3, TLB3_MAS1@l
183 mtspr 625, r3 /* MAS1 */
184 e_lis r3, TLB3_MAS2@h
185 e_or2i r3, TLB3_MAS2@l
186 mtspr 626, r3 /* MAS2 */
187 e_lis r3, TLB3_MAS3@h
188 e_or2i r3, TLB3_MAS3@l
189 mtspr 627, r3 /* MAS3 */
190 tlbwe
191
192 /*
193 * TLB4 allocated to on-platform peripherals.
194 */
195 e_lis r3, TLB4_MAS0@h
196 mtspr 624, r3 /* MAS0 */
197 e_lis r3, TLB4_MAS1@h
198 e_or2i r3, TLB4_MAS1@l
199 mtspr 625, r3 /* MAS1 */
200 e_lis r3, TLB4_MAS2@h
201 e_or2i r3, TLB4_MAS2@l
202 mtspr 626, r3 /* MAS2 */
203 e_lis r3, TLB4_MAS3@h
204 e_or2i r3, TLB4_MAS3@l
205 mtspr 627, r3 /* MAS3 */
206 tlbwe
207
208 /*
209 * TLB5 allocated to on-platform peripherals.
210 */
211 e_lis r3, TLB5_MAS0@h
212 mtspr 624, r3 /* MAS0 */
213 e_lis r3, TLB5_MAS1@h
214 e_or2i r3, TLB5_MAS1@l
215 mtspr 625, r3 /* MAS1 */
216 e_lis r3, TLB5_MAS2@h
217 e_or2i r3, TLB5_MAS2@l
218 mtspr 626, r3 /* MAS2 */
219 e_lis r3, TLB5_MAS3@h
220 e_or2i r3, TLB5_MAS3@l
221 mtspr 627, r3 /* MAS3 */
222 tlbwe
223
224 /*
225 * RAM clearing, this device requires a write to all RAM location in
226 * order to initialize the ECC detection hardware, this is going to
227 * slow down the startup but there is no way around.
228 */
229 xor r0, r0, r0
230 xor r1, r1, r1
231 xor r2, r2, r2
232 xor r3, r3, r3
233 xor r4, r4, r4
234 xor r5, r5, r5
235 xor r6, r6, r6
236 xor r7, r7, r7
237 xor r8, r8, r8
238 xor r9, r9, r9
239 xor r10, r10, r10
240 xor r11, r11, r11
241 xor r12, r12, r12
242 xor r13, r13, r13
243 xor r14, r14, r14
244 xor r15, r15, r15
245 xor r16, r16, r16
246 xor r17, r17, r17
247 xor r18, r18, r18
248 xor r19, r19, r19
249 xor r20, r20, r20
250 xor r21, r21, r21
251 xor r22, r22, r22
252 xor r23, r23, r23
253 xor r24, r24, r24
254 xor r25, r25, r25
255 xor r26, r26, r26
256 xor r27, r27, r27
257 xor r28, r28, r28
258 xor r29, r29, r29
259 xor r30, r30, r30
260 xor r31, r31, r31
261 e_lis r4, __ram_start__@h
262 e_or2i r4, __ram_start__@l
263 e_lis r5, __ram_end__@h
264 e_or2i r5, __ram_end__@l
265.cleareccloop:
266 se_cmpl r4, r5
267 se_bge .cleareccend
268 e_stmw r16, 0(r4)
269 e_addi r4, r4, 64
270 se_b .cleareccloop
271.cleareccend:
272
273 /*
274 * Special function registers clearing, required in order to avoid
275 * possible problems with lockstep mode.
276 */
277 mtcrf 0xFF, r31
278 mtspr 9, r31 /* CTR */
279 mtspr 22, r31 /* DEC */
280 mtspr 26, r31 /* SRR0-1 */
281 mtspr 27, r31
282 mtspr 54, r31 /* DECAR */
283 mtspr 58, r31 /* CSRR0-1 */
284 mtspr 59, r31
285 mtspr 61, r31 /* DEAR */
286 mtspr 256, r31 /* USPRG0 */
287 mtspr 272, r31 /* SPRG1-7 */
288 mtspr 273, r31
289 mtspr 274, r31
290 mtspr 275, r31
291 mtspr 276, r31
292 mtspr 277, r31
293 mtspr 278, r31
294 mtspr 279, r31
295 mtspr 285, r31 /* TBU */
296 mtspr 284, r31 /* TBL */
297#if 0
298 mtspr 318, r31 /* DVC1-2 */
299 mtspr 319, r31
300#endif
301 mtspr 562, r31 /* DBCNT */
302 mtspr 570, r31 /* MCSRR0 */
303 mtspr 571, r31 /* MCSRR1 */
304 mtspr 604, r31 /* SPRG8-9 */
305 mtspr 605, r31
306
307 /*
308 * *Finally* the TLB0 is re-allocated to flash, note, the final phase
309 * is executed from RAM.
310 */
311 e_lis r3, TLB0_MAS0@h
312 mtspr 624, r3 /* MAS0 */
313 e_lis r3, TLB0_MAS1@h
314 e_or2i r3, TLB0_MAS1@l
315 mtspr 625, r3 /* MAS1 */
316 e_lis r3, TLB0_MAS2@h
317 e_or2i r3, TLB0_MAS2@l
318 mtspr 626, r3 /* MAS2 */
319 e_lis r3, TLB0_MAS3@h
320 e_or2i r3, TLB0_MAS3@l
321 mtspr 627, r3 /* MAS3 */
322 se_mflr r4
323 e_lis r6, _ramcode@h
324 e_or2i r6, _ramcode@l
325 e_lis r7, 0x40010000@h
326 mtctr r7
327 se_lwz r3, 0(r6)
328 se_stw r3, 0(r7)
329 se_lwz r3, 4(r6)
330 se_stw r3, 4(r7)
331 se_lwz r3, 8(r6)
332 se_stw r3, 8(r7)
333 se_bctrl
334 mtlr r4
335
336 /*
337 * Branch prediction enabled.
338 */
339 e_li r3, BOOT_BUCSR_DEFAULT
340 mtspr 1013, r3 /* BUCSR */
341
342 /*
343 * Cache invalidated and then enabled.
344 */
345 se_li r3, LICSR1_ICINV
346 mtspr 1011, r3 /* LICSR1 */
347.inv: mfspr r3, 1011 /* LICSR1 */
348 e_andi. r3, r3, LICSR1_ICINV
349 se_bne .inv
350 e_lis r3, BOOT_LICSR1_DEFAULT@h
351 e_or2i r3, BOOT_LICSR1_DEFAULT@l
352 mtspr 1011, r3 /* LICSR1 */
353
354 se_blr
355#endif /* BOOT_PERFORM_CORE_INIT */
356
357 /*
358 * Exception vectors initialization.
359 */
360 .align 4
361_ivinit:
362 /* MSR initialization.*/
363 e_lis r3, BOOT_MSR_DEFAULT@h
364 e_ori r3, r3, BOOT_MSR_DEFAULT@l
365 mtMSR r3
366
367 /* IVPR initialization.*/
368 e_lis r3, __ivpr_base__@h
369 e_or2i r3, __ivpr_base__@l
370 mtIVPR r3
371
372 /* IVORs initialization.*/
373 e_lis r3, _unhandled_exception@h
374 e_or2i r3, _unhandled_exception@l
375
376 mtspr 400, r3 /* IVOR0-15 */
377 mtspr 401, r3
378 mtspr 402, r3
379 mtspr 403, r3
380 mtspr 404, r3
381 mtspr 405, r3
382 mtspr 406, r3
383 mtspr 407, r3
384 mtspr 408, r3
385 mtspr 409, r3
386 mtspr 410, r3
387 mtspr 411, r3
388 mtspr 412, r3
389 mtspr 413, r3
390 mtspr 414, r3
391 mtspr 415, r3
392 mtspr 528, r3 /* IVOR32-34 */
393 mtspr 529, r3
394 mtspr 530, r3
395
396 se_blr
397
398#endif /* !defined(__DOXYGEN__) */
399
400/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 21:25:47 +0100