diff options
Diffstat (limited to 'lib/chibios/os/common/startup/e200/devices/SPC560Pxx')
4 files changed, 508 insertions, 0 deletions
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.S b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.S new file mode 100644 index 000000000..4d16c7ac6 --- /dev/null +++ b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.S | |||
@@ -0,0 +1,218 @@ | |||
1 | /* | ||
2 | ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio | ||
3 | |||
4 | Licensed under the Apache License, Version 2.0 (the "License"); | ||
5 | you may not use this file except in compliance with the License. | ||
6 | You may obtain a copy of the License at | ||
7 | |||
8 | http://www.apache.org/licenses/LICENSE-2.0 | ||
9 | |||
10 | Unless required by applicable law or agreed to in writing, software | ||
11 | distributed under the License is distributed on an "AS IS" BASIS, | ||
12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
13 | See the License for the specific language governing permissions and | ||
14 | limitations under the License. | ||
15 | */ | ||
16 | |||
17 | /** | ||
18 | * @file SPC560Pxx/boot.s | ||
19 | * @brief SPC560Pxx boot-related code. | ||
20 | * | ||
21 | * @addtogroup PPC_BOOT | ||
22 | * @{ | ||
23 | */ | ||
24 | |||
25 | #include "boot.h" | ||
26 | |||
27 | #if defined(__HIGHTEC__) | ||
28 | #define se_bge bge | ||
29 | #endif | ||
30 | |||
31 | #if !defined(__DOXYGEN__) | ||
32 | |||
33 | /* BAM record.*/ | ||
34 | .section .boot, "ax" | ||
35 | |||
36 | .long 0x015A0000 | ||
37 | .long _reset_address | ||
38 | |||
39 | .align 2 | ||
40 | .globl _reset_address | ||
41 | .type _reset_address, @function | ||
42 | _reset_address: | ||
43 | #if BOOT_PERFORM_CORE_INIT | ||
44 | e_bl _coreinit | ||
45 | #endif | ||
46 | e_bl _ivinit | ||
47 | |||
48 | #if BOOT_RELOCATE_IN_RAM | ||
49 | /* | ||
50 | * Image relocation in RAM. | ||
51 | */ | ||
52 | e_lis r4, __ram_reloc_start__@h | ||
53 | e_or2i r4, __ram_reloc_start__@l | ||
54 | e_lis r5, __ram_reloc_dest__@h | ||
55 | e_or2i r5, __ram_reloc_dest__@l | ||
56 | e_lis r6, __ram_reloc_end__@h | ||
57 | e_or2i r6, r6, __ram_reloc_end__@l | ||
58 | .relloop: | ||
59 | se_cmpl r4, r6 | ||
60 | se_bge .relend | ||
61 | se_lwz r7, 0(r4) | ||
62 | se_addi r4, 4 | ||
63 | se_stw r7, 0(r5) | ||
64 | se_addi r5, 4 | ||
65 | se_b .relloop | ||
66 | .relend: | ||
67 | e_lis r3, _boot_address@h | ||
68 | e_or2i r3, _boot_address@l | ||
69 | mtctr r3 | ||
70 | se_bctrl | ||
71 | #else | ||
72 | e_b _boot_address | ||
73 | #endif | ||
74 | |||
75 | #if BOOT_PERFORM_CORE_INIT | ||
76 | .align 2 | ||
77 | _coreinit: | ||
78 | /* | ||
79 | * RAM clearing, this device requires a write to all RAM location in | ||
80 | * order to initialize the ECC detection hardware, this is going to | ||
81 | * slow down the startup but there is no way around. | ||
82 | */ | ||
83 | xor r0, r0, r0 | ||
84 | xor r1, r1, r1 | ||
85 | xor r2, r2, r2 | ||
86 | xor r3, r3, r3 | ||
87 | xor r4, r4, r4 | ||
88 | xor r5, r5, r5 | ||
89 | xor r6, r6, r6 | ||
90 | xor r7, r7, r7 | ||
91 | xor r8, r8, r8 | ||
92 | xor r9, r9, r9 | ||
93 | xor r10, r10, r10 | ||
94 | xor r11, r11, r11 | ||
95 | xor r12, r12, r12 | ||
96 | xor r13, r13, r13 | ||
97 | xor r14, r14, r14 | ||
98 | xor r15, r15, r15 | ||
99 | xor r16, r16, r16 | ||
100 | xor r17, r17, r17 | ||
101 | xor r18, r18, r18 | ||
102 | xor r19, r19, r19 | ||
103 | xor r20, r20, r20 | ||
104 | xor r21, r21, r21 | ||
105 | xor r22, r22, r22 | ||
106 | xor r23, r23, r23 | ||
107 | xor r24, r24, r24 | ||
108 | xor r25, r25, r25 | ||
109 | xor r26, r26, r26 | ||
110 | xor r27, r27, r27 | ||
111 | xor r28, r28, r28 | ||
112 | xor r29, r29, r29 | ||
113 | xor r30, r30, r30 | ||
114 | xor r31, r31, r31 | ||
115 | e_lis r4, __ram_start__@h | ||
116 | e_or2i r4, __ram_start__@l | ||
117 | e_lis r5, __ram_end__@h | ||
118 | e_or2i r5, __ram_end__@l | ||
119 | .cleareccloop: | ||
120 | se_cmpl r4, r5 | ||
121 | se_bge .cleareccend | ||
122 | e_stmw r16, 0(r4) | ||
123 | e_addi r4, r4, 64 | ||
124 | se_b .cleareccloop | ||
125 | .cleareccend: | ||
126 | |||
127 | /* | ||
128 | * Branch prediction enabled. | ||
129 | */ | ||
130 | e_li r3, BOOT_BUCSR_DEFAULT | ||
131 | mtspr 1013, r3 /* BUCSR */ | ||
132 | |||
133 | se_blr | ||
134 | #endif /* BOOT_PERFORM_CORE_INIT */ | ||
135 | |||
136 | /* | ||
137 | * Exception vectors initialization. | ||
138 | */ | ||
139 | .align 2 | ||
140 | _ivinit: | ||
141 | /* MSR initialization.*/ | ||
142 | e_lis r3, BOOT_MSR_DEFAULT@h | ||
143 | e_or2i r3, BOOT_MSR_DEFAULT@l | ||
144 | mtMSR r3 | ||
145 | |||
146 | /* IVPR initialization.*/ | ||
147 | e_lis r3, __ivpr_base__@h | ||
148 | e_or2i r3, __ivpr_base__@l | ||
149 | mtIVPR r3 | ||
150 | |||
151 | se_blr | ||
152 | |||
153 | .section .ivors, "ax" | ||
154 | |||
155 | .globl IVORS | ||
156 | IVORS: | ||
157 | e_b _IVOR0 | ||
158 | .align 4 | ||
159 | e_b _IVOR1 | ||
160 | .align 4 | ||
161 | e_b _IVOR2 | ||
162 | .align 4 | ||
163 | e_b _IVOR3 | ||
164 | .align 4 | ||
165 | e_b _IVOR4 | ||
166 | .align 4 | ||
167 | e_b _IVOR5 | ||
168 | .align 4 | ||
169 | e_b _IVOR6 | ||
170 | .align 4 | ||
171 | e_b _IVOR7 | ||
172 | .align 4 | ||
173 | e_b _IVOR8 | ||
174 | .align 4 | ||
175 | e_b _IVOR9 | ||
176 | .align 4 | ||
177 | e_b _IVOR10 | ||
178 | .align 4 | ||
179 | e_b _IVOR11 | ||
180 | .align 4 | ||
181 | e_b _IVOR12 | ||
182 | .align 4 | ||
183 | e_b _IVOR13 | ||
184 | .align 4 | ||
185 | e_b _IVOR14 | ||
186 | .align 4 | ||
187 | e_b _IVOR15 | ||
188 | |||
189 | .section .handlers, "ax" | ||
190 | |||
191 | /* | ||
192 | * Default IVOR handlers. | ||
193 | */ | ||
194 | .align 2 | ||
195 | .weak _IVOR0, _IVOR1, _IVOR2, _IVOR3, _IVOR4, _IVOR5 | ||
196 | .weak _IVOR6, _IVOR7, _IVOR8, _IVOR9, _IVOR10, _IVOR11 | ||
197 | .weak _IVOR12, _IVOR13, _IVOR14, _IVOR15 | ||
198 | _IVOR0: | ||
199 | _IVOR1: | ||
200 | _IVOR2: | ||
201 | _IVOR3: | ||
202 | _IVOR5: | ||
203 | _IVOR6: | ||
204 | _IVOR7: | ||
205 | _IVOR8: | ||
206 | _IVOR9: | ||
207 | _IVOR11: | ||
208 | _IVOR12: | ||
209 | _IVOR13: | ||
210 | _IVOR14: | ||
211 | _IVOR15: | ||
212 | .global _unhandled_exception | ||
213 | _unhandled_exception: | ||
214 | se_b _unhandled_exception | ||
215 | |||
216 | #endif /* !defined(__DOXYGEN__) */ | ||
217 | |||
218 | /** @} */ | ||
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.h b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.h new file mode 100644 index 000000000..be9217c65 --- /dev/null +++ b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/boot.h | |||
@@ -0,0 +1,114 @@ | |||
1 | /* | ||
2 | ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio | ||
3 | |||
4 | Licensed under the Apache License, Version 2.0 (the "License"); | ||
5 | you may not use this file except in compliance with the License. | ||
6 | You may obtain a copy of the License at | ||
7 | |||
8 | http://www.apache.org/licenses/LICENSE-2.0 | ||
9 | |||
10 | Unless required by applicable law or agreed to in writing, software | ||
11 | distributed under the License is distributed on an "AS IS" BASIS, | ||
12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
13 | See the License for the specific language governing permissions and | ||
14 | limitations under the License. | ||
15 | */ | ||
16 | |||
17 | /** | ||
18 | * @file boot.h | ||
19 | * @brief Boot parameters for the SPC560Pxx. | ||
20 | * @{ | ||
21 | */ | ||
22 | |||
23 | #ifndef BOOT_H | ||
24 | #define BOOT_H | ||
25 | |||
26 | /*===========================================================================*/ | ||
27 | /* Module constants. */ | ||
28 | /*===========================================================================*/ | ||
29 | |||
30 | /** | ||
31 | * @name BUCSR registers definitions | ||
32 | * @{ | ||
33 | */ | ||
34 | #define BUCSR_BPEN 0x00000001 | ||
35 | #define BUCSR_BALLOC_BFI 0x00000200 | ||
36 | /** @} */ | ||
37 | |||
38 | /** | ||
39 | * @name MSR register definitions | ||
40 | * @{ | ||
41 | */ | ||
42 | #define MSR_WE 0x00040000 | ||
43 | #define MSR_CE 0x00020000 | ||
44 | #define MSR_EE 0x00008000 | ||
45 | #define MSR_PR 0x00004000 | ||
46 | #define MSR_ME 0x00001000 | ||
47 | #define MSR_DE 0x00000200 | ||
48 | #define MSR_IS 0x00000020 | ||
49 | #define MSR_DS 0x00000010 | ||
50 | #define MSR_RI 0x00000002 | ||
51 | /** @} */ | ||
52 | |||
53 | /*===========================================================================*/ | ||
54 | /* Module pre-compile time settings. */ | ||
55 | /*===========================================================================*/ | ||
56 | |||
57 | /* | ||
58 | * BUCSR default settings. | ||
59 | */ | ||
60 | #if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__) | ||
61 | #define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BALLOC_BFI) | ||
62 | #endif | ||
63 | |||
64 | /* | ||
65 | * MSR default settings. | ||
66 | */ | ||
67 | #if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__) | ||
68 | #define BOOT_MSR_DEFAULT (MSR_WE | MSR_CE | MSR_ME) | ||
69 | #endif | ||
70 | |||
71 | /* | ||
72 | * Boot default settings. | ||
73 | */ | ||
74 | #if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__) | ||
75 | #define BOOT_PERFORM_CORE_INIT 1 | ||
76 | #endif | ||
77 | |||
78 | /* | ||
79 | * VLE mode default settings. | ||
80 | */ | ||
81 | #if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__) | ||
82 | #define BOOT_USE_VLE 1 | ||
83 | #endif | ||
84 | |||
85 | /* | ||
86 | * RAM relocation flag. | ||
87 | */ | ||
88 | #if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__) | ||
89 | #define BOOT_RELOCATE_IN_RAM 0 | ||
90 | #endif | ||
91 | |||
92 | /*===========================================================================*/ | ||
93 | /* Derived constants and error checks. */ | ||
94 | /*===========================================================================*/ | ||
95 | |||
96 | /*===========================================================================*/ | ||
97 | /* Module data structures and types. */ | ||
98 | /*===========================================================================*/ | ||
99 | |||
100 | /*===========================================================================*/ | ||
101 | /* Module macros. */ | ||
102 | /*===========================================================================*/ | ||
103 | |||
104 | /*===========================================================================*/ | ||
105 | /* External declarations. */ | ||
106 | /*===========================================================================*/ | ||
107 | |||
108 | /*===========================================================================*/ | ||
109 | /* Module inline functions. */ | ||
110 | /*===========================================================================*/ | ||
111 | |||
112 | #endif /* BOOT_H */ | ||
113 | |||
114 | /** @} */ | ||
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/intc.h b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/intc.h new file mode 100644 index 000000000..c47cb5b8d --- /dev/null +++ b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/intc.h | |||
@@ -0,0 +1,93 @@ | |||
1 | /* | ||
2 | ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio | ||
3 | |||
4 | Licensed under the Apache License, Version 2.0 (the "License"); | ||
5 | you may not use this file except in compliance with the License. | ||
6 | You may obtain a copy of the License at | ||
7 | |||
8 | http://www.apache.org/licenses/LICENSE-2.0 | ||
9 | |||
10 | Unless required by applicable law or agreed to in writing, software | ||
11 | distributed under the License is distributed on an "AS IS" BASIS, | ||
12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
13 | See the License for the specific language governing permissions and | ||
14 | limitations under the License. | ||
15 | */ | ||
16 | |||
17 | /** | ||
18 | * @file SPC560Pxx/intc.h | ||
19 | * @brief SPC560Pxx INTC module header. | ||
20 | * | ||
21 | * @addtogroup INTC | ||
22 | * @{ | ||
23 | */ | ||
24 | |||
25 | #ifndef INTC_H | ||
26 | #define INTC_H | ||
27 | |||
28 | /*===========================================================================*/ | ||
29 | /* Module constants. */ | ||
30 | /*===========================================================================*/ | ||
31 | |||
32 | /** | ||
33 | * @name INTC addresses | ||
34 | * @{ | ||
35 | */ | ||
36 | #define INTC_BASE 0xFFF48000 | ||
37 | #define INTC_IACKR_ADDR (INTC_BASE + 0x10) | ||
38 | #define INTC_EOIR_ADDR (INTC_BASE + 0x18) | ||
39 | /** @} */ | ||
40 | |||
41 | /** | ||
42 | * @brief INTC priority levels. | ||
43 | */ | ||
44 | #define INTC_PRIORITY_LEVELS 16U | ||
45 | |||
46 | /*===========================================================================*/ | ||
47 | /* Module pre-compile time settings. */ | ||
48 | /*===========================================================================*/ | ||
49 | |||
50 | /*===========================================================================*/ | ||
51 | /* Derived constants and error checks. */ | ||
52 | /*===========================================================================*/ | ||
53 | |||
54 | /*===========================================================================*/ | ||
55 | /* Module data structures and types. */ | ||
56 | /*===========================================================================*/ | ||
57 | |||
58 | /*===========================================================================*/ | ||
59 | /* Module macros. */ | ||
60 | /*===========================================================================*/ | ||
61 | |||
62 | /** | ||
63 | * @name INTC-related macros | ||
64 | * @{ | ||
65 | */ | ||
66 | #define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0))) | ||
67 | #define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t))))) | ||
68 | #define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t))))) | ||
69 | #define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t))))) | ||
70 | #define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t))))) | ||
71 | /** @} */ | ||
72 | |||
73 | /** | ||
74 | * @brief Core selection macros for PSR register. | ||
75 | */ | ||
76 | #define INTC_PSR_CORE0 0x00 | ||
77 | |||
78 | /** | ||
79 | * @brief PSR register content helper | ||
80 | */ | ||
81 | #define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio)) | ||
82 | |||
83 | /*===========================================================================*/ | ||
84 | /* External declarations. */ | ||
85 | /*===========================================================================*/ | ||
86 | |||
87 | /*===========================================================================*/ | ||
88 | /* Module inline functions. */ | ||
89 | /*===========================================================================*/ | ||
90 | |||
91 | #endif /* INTC_H */ | ||
92 | |||
93 | /** @} */ | ||
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/ppcparams.h b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/ppcparams.h new file mode 100644 index 000000000..1a6fb998d --- /dev/null +++ b/lib/chibios/os/common/startup/e200/devices/SPC560Pxx/ppcparams.h | |||
@@ -0,0 +1,83 @@ | |||
1 | /* | ||
2 | ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio | ||
3 | |||
4 | Licensed under the Apache License, Version 2.0 (the "License"); | ||
5 | you may not use this file except in compliance with the License. | ||
6 | You may obtain a copy of the License at | ||
7 | |||
8 | http://www.apache.org/licenses/LICENSE-2.0 | ||
9 | |||
10 | Unless required by applicable law or agreed to in writing, software | ||
11 | distributed under the License is distributed on an "AS IS" BASIS, | ||
12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
13 | See the License for the specific language governing permissions and | ||
14 | limitations under the License. | ||
15 | */ | ||
16 | |||
17 | /** | ||
18 | * @file SPC560Pxx/ppcparams.h | ||
19 | * @brief PowerPC parameters for the SPC560Pxx. | ||
20 | * | ||
21 | * @defgroup PPC_SPC560Pxx SPC560Pxx Specific Parameters | ||
22 | * @ingroup PPC_SPECIFIC | ||
23 | * @details This file contains the PowerPC specific parameters for the | ||
24 | * SPC560Pxx platform. | ||
25 | * @{ | ||
26 | */ | ||
27 | |||
28 | #ifndef PPCPARAMS_H | ||
29 | #define PPCPARAMS_H | ||
30 | |||
31 | /** | ||
32 | * @brief Family identification macro. | ||
33 | */ | ||
34 | #define PPC_SPC560Pxx | ||
35 | |||
36 | /** | ||
37 | * @brief PPC core model. | ||
38 | */ | ||
39 | #define PPC_VARIANT PPC_VARIANT_e200z0 | ||
40 | |||
41 | /** | ||
42 | * @brief Number of cores. | ||
43 | */ | ||
44 | #define PPC_CORE_NUMBER 1 | ||
45 | |||
46 | /** | ||
47 | * @brief Number of writable bits in IVPR register. | ||
48 | */ | ||
49 | #define PPC_IVPR_BITS 20 | ||
50 | |||
51 | /** | ||
52 | * @brief IVORx registers support. | ||
53 | */ | ||
54 | #define PPC_SUPPORTS_IVORS FALSE | ||
55 | |||
56 | /** | ||
57 | * @brief Book E instruction set support. | ||
58 | */ | ||
59 | #define PPC_SUPPORTS_BOOKE FALSE | ||
60 | |||
61 | /** | ||
62 | * @brief VLE instruction set support. | ||
63 | */ | ||
64 | #define PPC_SUPPORTS_VLE TRUE | ||
65 | |||
66 | /** | ||
67 | * @brief Supports VLS Load/Store Multiple Volatile instructions. | ||
68 | */ | ||
69 | #define PPC_SUPPORTS_VLE_MULTI TRUE | ||
70 | |||
71 | /** | ||
72 | * @brief Supports the decrementer timer. | ||
73 | */ | ||
74 | #define PPC_SUPPORTS_DECREMENTER FALSE | ||
75 | |||
76 | /** | ||
77 | * @brief Number of interrupt sources. | ||
78 | */ | ||
79 | #define PPC_NUM_VECTORS 261 | ||
80 | |||
81 | #endif /* PPCPARAMS_H */ | ||
82 | |||
83 | /** @} */ | ||