aboutsummaryrefslogtreecommitdiff
path: root/lib/chibios/os/common/startup/e200/devices/SPC56ELxx
diff options
context:
space:
mode:
Diffstat (limited to 'lib/chibios/os/common/startup/e200/devices/SPC56ELxx')
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.S409
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.h248
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ELxx/intc.h93
-rw-r--r--lib/chibios/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h83
4 files changed, 833 insertions, 0 deletions
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.S b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.S
new file mode 100644
index 000000000..56e59fe93
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.S
@@ -0,0 +1,409 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ELxx/boot.s
19 * @brief SPC56ELxx boot-related code.
20 *
21 * @addtogroup PPC_BOOT
22 * @{
23 */
24
25#include "boot.h"
26
27#if defined(__HIGHTEC__)
28#define se_bge bge
29#endif
30
31#if !defined(__DOXYGEN__)
32
33 /* BAM record.*/
34 .section .boot, "ax"
35
36#if BOOT_USE_VLE
37 .long 0x015A0000
38#else
39 .long 0x005A0000
40#endif
41 .long _reset_address
42
43 .align 2
44 .globl _reset_address
45 .type _reset_address, @function
46_reset_address:
47 e_bl _coreinit
48 e_bl _ivinit
49
50#if BOOT_RELOCATE_IN_RAM
51 /*
52 * Image relocation in RAM.
53 */
54 e_lis r4, __ram_reloc_start__@h
55 e_or2i r4, __ram_reloc_start__@l
56 e_lis r5, __ram_reloc_dest__@h
57 e_or2i r5, __ram_reloc_dest__@l
58 e_lis r6, __ram_reloc_end__@h
59 e_or2i r6, r6, __ram_reloc_end__@l
60.relloop:
61 se_cmpl r4, r6
62 se_bge .relend
63 se_lwz r7, 0(r4)
64 se_addi r4, 4
65 se_stw r7, 0(r5)
66 se_addi r5, 4
67 se_b .relloop
68.relend:
69 e_lis r3, _boot_address@h
70 e_or2i r3, _boot_address@l
71 mtctr r3
72 se_bctrl
73#else
74 e_b _boot_address
75#endif
76
77#if BOOT_PERFORM_CORE_INIT
78 .align 2
79_ramcode:
80 tlbwe
81 se_isync
82 se_blr
83#endif /* BOOT_PERFORM_CORE_INIT */
84
85 .align 2
86_coreinit:
87#if BOOT_PERFORM_CORE_INIT
88 /*
89 * Invalidating all TLBs except TLB0.
90 */
91 e_lis r3, 0
92 mtspr 625, r3 /* MAS1 */
93 mtspr 626, r3 /* MAS2 */
94 mtspr 627, r3 /* MAS3 */
95 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(1))@h
96 mtspr 624, r3 /* MAS0 */
97 tlbwe
98 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(2))@h
99 mtspr 624, r3 /* MAS0 */
100 tlbwe
101 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(3))@h
102 mtspr 624, r3 /* MAS0 */
103 tlbwe
104 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(4))@h
105 mtspr 624, r3 /* MAS0 */
106 tlbwe
107 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(5))@h
108 mtspr 624, r3 /* MAS0 */
109 tlbwe
110 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(6))@h
111 mtspr 624, r3 /* MAS0 */
112 tlbwe
113 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(7))@h
114 mtspr 624, r3 /* MAS0 */
115 tlbwe
116 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(8))@h
117 mtspr 624, r3 /* MAS0 */
118 tlbwe
119 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(9))@h
120 mtspr 624, r3 /* MAS0 */
121 tlbwe
122 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(10))@h
123 mtspr 624, r3 /* MAS0 */
124 tlbwe
125 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(11))@h
126 mtspr 624, r3 /* MAS0 */
127 tlbwe
128 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(12))@h
129 mtspr 624, r3 /* MAS0 */
130 tlbwe
131 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(13))@h
132 mtspr 624, r3 /* MAS0 */
133 tlbwe
134 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(14))@h
135 mtspr 624, r3 /* MAS0 */
136 tlbwe
137 e_lis r3, (MAS0_TBLMAS_TBL | MAS0_ESEL(15))@h
138 mtspr 624, r3 /* MAS0 */
139 tlbwe
140
141 /*
142 * TLB1 allocated to internal RAM.
143 */
144 e_lis r3, TLB1_MAS0@h
145 mtspr 624, r3 /* MAS0 */
146 e_lis r3, TLB1_MAS1@h
147 e_or2i r3, TLB1_MAS1@l
148 mtspr 625, r3 /* MAS1 */
149 e_lis r3, TLB1_MAS2@h
150 e_or2i r3, TLB1_MAS2@l
151 mtspr 626, r3 /* MAS2 */
152 e_lis r3, TLB1_MAS3@h
153 e_or2i r3, TLB1_MAS3@l
154 mtspr 627, r3 /* MAS3 */
155 tlbwe
156
157 /*
158 * TLB2 allocated to internal Peripherals Bridge A.
159 */
160 e_lis r3, TLB2_MAS0@h
161 mtspr 624, r3 /* MAS0 */
162 e_lis r3, TLB2_MAS1@h
163 e_or2i r3, TLB2_MAS1@l
164 mtspr 625, r3 /* MAS1 */
165 e_lis r3, TLB2_MAS2@h
166 e_or2i r3, TLB2_MAS2@l
167 mtspr 626, r3 /* MAS2 */
168 e_lis r3, TLB2_MAS3@h
169 e_or2i r3, TLB2_MAS3@l
170 mtspr 627, r3 /* MAS3 */
171 tlbwe
172
173 /*
174 * TLB3 allocated to internal Peripherals Bridge B.
175 */
176 e_lis r3, TLB3_MAS0@h
177 mtspr 624, r3 /* MAS0 */
178 e_lis r3, TLB3_MAS1@h
179 e_or2i r3, TLB3_MAS1@l
180 mtspr 625, r3 /* MAS1 */
181 e_lis r3, TLB3_MAS2@h
182 e_or2i r3, TLB3_MAS2@l
183 mtspr 626, r3 /* MAS2 */
184 e_lis r3, TLB3_MAS3@h
185 e_or2i r3, TLB3_MAS3@l
186 mtspr 627, r3 /* MAS3 */
187 tlbwe
188
189 /*
190 * TLB4 allocated to on-platform peripherals.
191 */
192 e_lis r3, TLB4_MAS0@h
193 mtspr 624, r3 /* MAS0 */
194 e_lis r3, TLB4_MAS1@h
195 e_or2i r3, TLB4_MAS1@l
196 mtspr 625, r3 /* MAS1 */
197 e_lis r3, TLB4_MAS2@h
198 e_or2i r3, TLB4_MAS2@l
199 mtspr 626, r3 /* MAS2 */
200 e_lis r3, TLB4_MAS3@h
201 e_or2i r3, TLB4_MAS3@l
202 mtspr 627, r3 /* MAS3 */
203 tlbwe
204
205 /*
206 * TLB5 allocated to on-platform peripherals.
207 */
208 e_lis r3, TLB5_MAS0@h
209 mtspr 624, r3 /* MAS0 */
210 e_lis r3, TLB5_MAS1@h
211 e_or2i r3, TLB5_MAS1@l
212 mtspr 625, r3 /* MAS1 */
213 e_lis r3, TLB5_MAS2@h
214 e_or2i r3, TLB5_MAS2@l
215 mtspr 626, r3 /* MAS2 */
216 e_lis r3, TLB5_MAS3@h
217 e_or2i r3, TLB5_MAS3@l
218 mtspr 627, r3 /* MAS3 */
219 tlbwe
220
221 /*
222 * RAM clearing, this device requires a write to all RAM location in
223 * order to initialize the ECC detection hardware, this is going to
224 * slow down the startup but there is no way around.
225 */
226 xor r0, r0, r0
227 xor r1, r1, r1
228 xor r2, r2, r2
229 xor r3, r3, r3
230 xor r4, r4, r4
231 xor r5, r5, r5
232 xor r6, r6, r6
233 xor r7, r7, r7
234 xor r8, r8, r8
235 xor r9, r9, r9
236 xor r10, r10, r10
237 xor r11, r11, r11
238 xor r12, r12, r12
239 xor r13, r13, r13
240 xor r14, r14, r14
241 xor r15, r15, r15
242 xor r16, r16, r16
243 xor r17, r17, r17
244 xor r18, r18, r18
245 xor r19, r19, r19
246 xor r20, r20, r20
247 xor r21, r21, r21
248 xor r22, r22, r22
249 xor r23, r23, r23
250 xor r24, r24, r24
251 xor r25, r25, r25
252 xor r26, r26, r26
253 xor r27, r27, r27
254 xor r28, r28, r28
255 xor r29, r29, r29
256 xor r30, r30, r30
257 xor r31, r31, r31
258 e_lis r4, __ram_start__@h
259 e_or2i r4, __ram_start__@l
260 e_lis r5, __ram_end__@h
261 e_or2i r5, __ram_end__@l
262.cleareccloop:
263 se_cmpl r4, r5
264 se_bge .cleareccend
265 e_stmw r16, 0(r4)
266 e_addi r4, r4, 64
267 se_b .cleareccloop
268.cleareccend:
269#endif /* BOOT_PERFORM_CORE_INIT */
270
271 /*
272 * Special function registers clearing, required in order to avoid
273 * possible problems with lockstep mode.
274 */
275 mtcrf 0xFF, r31
276 mtspr 9, r31 /* CTR */
277 mtspr 22, r31 /* DEC */
278 mtspr 26, r31 /* SRR0-1 */
279 mtspr 27, r31
280 mtspr 54, r31 /* DECAR */
281 mtspr 58, r31 /* CSRR0-1 */
282 mtspr 59, r31
283 mtspr 61, r31 /* DEAR */
284 mtspr 256, r31 /* USPRG0 */
285 mtspr 272, r31 /* SPRG1-7 */
286 mtspr 273, r31
287 mtspr 274, r31
288 mtspr 275, r31
289 mtspr 276, r31
290 mtspr 277, r31
291 mtspr 278, r31
292 mtspr 279, r31
293 mtspr 285, r31 /* TBU */
294 mtspr 284, r31 /* TBL */
295#if 0
296 mtspr 318, r31 /* DVC1-2 */
297 mtspr 319, r31
298#endif
299 mtspr 562, r31 /* DBCNT */
300 mtspr 570, r31 /* MCSRR0 */
301 mtspr 571, r31 /* MCSRR1 */
302 mtspr 604, r31 /* SPRG8-9 */
303 mtspr 605, r31
304
305#if BOOT_PERFORM_CORE_INIT
306 /*
307 * *Finally* the TLB0 is re-allocated to flash, note, the final phase
308 * is executed from RAM.
309 */
310 e_lis r3, TLB0_MAS0@h
311 mtspr 624, r3 /* MAS0 */
312 e_lis r3, TLB0_MAS1@h
313 e_or2i r3, TLB0_MAS1@l
314 mtspr 625, r3 /* MAS1 */
315 e_lis r3, TLB0_MAS2@h
316 e_or2i r3, TLB0_MAS2@l
317 mtspr 626, r3 /* MAS2 */
318 e_lis r3, TLB0_MAS3@h
319 e_or2i r3, TLB0_MAS3@l
320 mtspr 627, r3 /* MAS3 */
321 mflr r4
322 e_lis r6, _ramcode@h
323 e_or2i r6, _ramcode@l
324 e_lis r7, 0x40010000@h
325 mtctr r7
326 se_lwz r3, 0(r6)
327 se_stw r3, 0(r7)
328 se_lwz r3, 4(r6)
329 se_stw r3, 4(r7)
330 se_lwz r3, 8(r6)
331 se_stw r3, 8(r7)
332 se_bctrl
333 mtlr r4
334#endif /* BOOT_PERFORM_CORE_INIT */
335
336 /*
337 * Branch prediction enabled.
338 */
339 e_li r3, BOOT_BUCSR_DEFAULT
340 mtspr 1013, r3 /* BUCSR */
341
342 /*
343 * Cache invalidated and then enabled.
344 */
345 e_li r3, LICSR1_ICINV
346 mtspr 1011, r3 /* LICSR1 */
347.inv: mfspr r3, 1011 /* LICSR1 */
348 e_and2i. r3, LICSR1_ICINV
349 se_bne .inv
350 e_lis r3, BOOT_LICSR1_DEFAULT@h
351 e_or2i r3, BOOT_LICSR1_DEFAULT@l
352 mtspr 1011, r3 /* LICSR1 */
353
354 se_blr
355
356 /*
357 * Exception vectors initialization.
358 */
359 .align 2
360_ivinit:
361 /* MSR initialization.*/
362 e_lis r3, BOOT_MSR_DEFAULT@h
363 e_or2i r3, BOOT_MSR_DEFAULT@l
364 mtMSR r3
365
366 /* IVPR initialization.*/
367 e_lis r3, __ivpr_base__@h
368 e_or2i r3, __ivpr_base__@l
369 mtIVPR r3
370
371 /* IVORs initialization.*/
372 e_lis r3, _unhandled_exception@h
373 e_or2i r3, _unhandled_exception@l
374
375 mtspr 400, r3 /* IVOR0-15 */
376 mtspr 401, r3
377 mtspr 402, r3
378 mtspr 403, r3
379 mtspr 404, r3
380 mtspr 405, r3
381 mtspr 406, r3
382 mtspr 407, r3
383 mtspr 408, r3
384 mtspr 409, r3
385 mtspr 410, r3
386 mtspr 411, r3
387 mtspr 412, r3
388 mtspr 413, r3
389 mtspr 414, r3
390 mtspr 415, r3
391 mtspr 528, r3 /* IVOR32-34 */
392 mtspr 529, r3
393 mtspr 530, r3
394
395 se_blr
396
397 .section .handlers, "ax"
398
399 /*
400 * Unhandled exceptions handler.
401 */
402 .weak _unhandled_exception
403 .type _unhandled_exception, @function
404_unhandled_exception:
405 se_b _unhandled_exception
406
407#endif /* !defined(__DOXYGEN__) */
408
409/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.h b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.h
new file mode 100644
index 000000000..ee2767a83
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/boot.h
@@ -0,0 +1,248 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file boot.h
19 * @brief Boot parameters for the SPC56ELxx.
20 * @{
21 */
22
23#ifndef BOOT_H
24#define BOOT_H
25
26/*===========================================================================*/
27/* Module constants. */
28/*===========================================================================*/
29
30/**
31 * @name MASx registers definitions
32 * @{
33 */
34#define MAS0_TBLMAS_TBL 0x10000000
35#define MAS0_ESEL_MASK 0x000F0000
36#define MAS0_ESEL(n) ((n) << 16)
37
38#define MAS1_VALID 0x80000000
39#define MAS1_IPROT 0x40000000
40#define MAS1_TID_MASK 0x00FF0000
41#define MAS1_TS 0x00001000
42#define MAS1_TSISE_MASK 0x00000F80
43#define MAS1_TSISE_1K 0x00000000
44#define MAS1_TSISE_2K 0x00000080
45#define MAS1_TSISE_4K 0x00000100
46#define MAS1_TSISE_8K 0x00000180
47#define MAS1_TSISE_16K 0x00000200
48#define MAS1_TSISE_32K 0x00000280
49#define MAS1_TSISE_64K 0x00000300
50#define MAS1_TSISE_128K 0x00000380
51#define MAS1_TSISE_256K 0x00000400
52#define MAS1_TSISE_512K 0x00000480
53#define MAS1_TSISE_1M 0x00000500
54#define MAS1_TSISE_2M 0x00000580
55#define MAS1_TSISE_4M 0x00000600
56#define MAS1_TSISE_8M 0x00000680
57#define MAS1_TSISE_16M 0x00000700
58#define MAS1_TSISE_32M 0x00000780
59#define MAS1_TSISE_64M 0x00000800
60#define MAS1_TSISE_128M 0x00000880
61#define MAS1_TSISE_256M 0x00000900
62#define MAS1_TSISE_512M 0x00000980
63#define MAS1_TSISE_1G 0x00000A00
64#define MAS1_TSISE_2G 0x00000A80
65#define MAS1_TSISE_4G 0x00000B00
66
67#define MAS2_EPN_MASK 0xFFFFFC00
68#define MAS2_EPN(n) ((n) & MAS2_EPN_MASK)
69#define MAS2_EBOOK 0x00000000
70#define MAS2_VLE 0x00000020
71#define MAS2_W 0x00000010
72#define MAS2_I 0x00000008
73#define MAS2_M 0x00000004
74#define MAS2_G 0x00000002
75#define MAS2_E 0x00000001
76
77#define MAS3_RPN_MASK 0xFFFFFC00
78#define MAS3_RPN(n) ((n) & MAS3_RPN_MASK)
79#define MAS3_U0 0x00000200
80#define MAS3_U1 0x00000100
81#define MAS3_U2 0x00000080
82#define MAS3_U3 0x00000040
83#define MAS3_UX 0x00000020
84#define MAS3_SX 0x00000010
85#define MAS3_UW 0x00000008
86#define MAS3_SW 0x00000004
87#define MAS3_UR 0x00000002
88#define MAS3_SR 0x00000001
89/** @} */
90
91/**
92 * @name BUCSR registers definitions
93 * @{
94 */
95#define BUCSR_BPEN 0x00000001
96#define BUCSR_BPRED_MASK 0x00000006
97#define BUCSR_BPRED_0 0x00000000
98#define BUCSR_BPRED_1 0x00000002
99#define BUCSR_BPRED_2 0x00000004
100#define BUCSR_BPRED_3 0x00000006
101#define BUCSR_BALLOC_MASK 0x00000030
102#define BUCSR_BALLOC_0 0x00000000
103#define BUCSR_BALLOC_1 0x00000010
104#define BUCSR_BALLOC_2 0x00000020
105#define BUCSR_BALLOC_3 0x00000030
106#define BUCSR_BALLOC_BFI 0x00000200
107/** @} */
108
109/**
110 * @name LICSR1 registers definitions
111 * @{
112 */
113#define LICSR1_ICE 0x00000001
114#define LICSR1_ICINV 0x00000002
115#define LICSR1_ICORG 0x00000010
116/** @} */
117
118/**
119 * @name MSR register definitions
120 * @{
121 */
122#define MSR_UCLE 0x04000000
123#define MSR_SPE 0x02000000
124#define MSR_WE 0x00040000
125#define MSR_CE 0x00020000
126#define MSR_EE 0x00008000
127#define MSR_PR 0x00004000
128#define MSR_FP 0x00002000
129#define MSR_ME 0x00001000
130#define MSR_FE0 0x00000800
131#define MSR_DE 0x00000200
132#define MSR_FE1 0x00000100
133#define MSR_IS 0x00000020
134#define MSR_DS 0x00000010
135#define MSR_RI 0x00000002
136/** @} */
137
138/*===========================================================================*/
139/* Module pre-compile time settings. */
140/*===========================================================================*/
141
142/*
143 * TLB default settings.
144 */
145#define TLB0_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(0))
146#define TLB0_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_2M)
147#define TLB0_MAS2 (MAS2_EPN(0x00000000) | MAS2_VLE)
148#define TLB0_MAS3 (MAS3_RPN(0x00000000) | \
149 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
150 MAS3_UR | MAS3_SR)
151
152#define TLB1_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(1))
153#define TLB1_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_256K)
154#define TLB1_MAS2 (MAS2_EPN(0x40000000) | MAS2_VLE)
155#define TLB1_MAS3 (MAS3_RPN(0x40000000) | \
156 MAS3_UX | MAS3_SX | MAS3_UW | MAS3_SW | \
157 MAS3_UR | MAS3_SR)
158
159#define TLB2_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(2))
160#define TLB2_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
161#define TLB2_MAS2 (MAS2_EPN(0xC3F00000) | MAS2_I)
162#define TLB2_MAS3 (MAS3_RPN(0xC3F00000) | \
163 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
164
165#define TLB3_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(3))
166#define TLB3_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
167#define TLB3_MAS2 (MAS2_EPN(0xFFE00000) | MAS2_I)
168#define TLB3_MAS3 (MAS3_RPN(0xFFE00000) | \
169 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
170
171#define TLB4_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(4))
172#define TLB4_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
173#define TLB4_MAS2 (MAS2_EPN(0x8FF00000) | MAS2_I)
174#define TLB4_MAS3 (MAS3_RPN(0x8FF00000) | \
175 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
176
177#define TLB5_MAS0 (MAS0_TBLMAS_TBL | MAS0_ESEL(5))
178#define TLB5_MAS1 (MAS1_VALID | MAS1_IPROT | MAS1_TSISE_1M)
179#define TLB5_MAS2 (MAS2_EPN(0xFFF00000) | MAS2_I)
180#define TLB5_MAS3 (MAS3_RPN(0xFFF00000) | \
181 MAS3_UW | MAS3_SW | MAS3_UR | MAS3_SR)
182
183/*
184 * BUCSR default settings.
185 */
186#if !defined(BOOT_BUCSR_DEFAULT) || defined(__DOXYGEN__)
187#define BOOT_BUCSR_DEFAULT (BUCSR_BPEN | BUCSR_BPRED_0 | \
188 BUCSR_BALLOC_0 | BUCSR_BALLOC_BFI)
189#endif
190
191/*
192 * LICSR1 default settings.
193 */
194#if !defined(BOOT_LICSR1_DEFAULT) || defined(__DOXYGEN__)
195#define BOOT_LICSR1_DEFAULT (LICSR1_ICE | LICSR1_ICORG)
196#endif
197
198/*
199 * MSR default settings.
200 */
201#if !defined(BOOT_MSR_DEFAULT) || defined(__DOXYGEN__)
202#define BOOT_MSR_DEFAULT (MSR_SPE | MSR_WE | MSR_CE | MSR_ME)
203#endif
204
205/*
206 * Boot default settings.
207 */
208#if !defined(BOOT_PERFORM_CORE_INIT) || defined(__DOXYGEN__)
209#define BOOT_PERFORM_CORE_INIT 1
210#endif
211
212/*
213 * VLE mode default settings.
214 */
215#if !defined(BOOT_USE_VLE) || defined(__DOXYGEN__)
216#define BOOT_USE_VLE 1
217#endif
218
219/*
220 * RAM relocation flag.
221 */
222#if !defined(BOOT_RELOCATE_IN_RAM) || defined(__DOXYGEN__)
223#define BOOT_RELOCATE_IN_RAM 0
224#endif
225
226/*===========================================================================*/
227/* Derived constants and error checks. */
228/*===========================================================================*/
229
230/*===========================================================================*/
231/* Module data structures and types. */
232/*===========================================================================*/
233
234/*===========================================================================*/
235/* Module macros. */
236/*===========================================================================*/
237
238/*===========================================================================*/
239/* External declarations. */
240/*===========================================================================*/
241
242/*===========================================================================*/
243/* Module inline functions. */
244/*===========================================================================*/
245
246#endif /* BOOT_H */
247
248/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/intc.h b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/intc.h
new file mode 100644
index 000000000..52fed877b
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/intc.h
@@ -0,0 +1,93 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ELxx/intc.h
19 * @brief SPC56ELxx INTC module header.
20 *
21 * @addtogroup INTC
22 * @{
23 */
24
25#ifndef INTC_H
26#define INTC_H
27
28/*===========================================================================*/
29/* Module constants. */
30/*===========================================================================*/
31
32/**
33 * @name INTC addresses
34 * @{
35 */
36#define INTC_BASE 0xFFF48000
37#define INTC_IACKR_ADDR (INTC_BASE + 0x10)
38#define INTC_EOIR_ADDR (INTC_BASE + 0x18)
39/** @} */
40
41/**
42 * @brief INTC priority levels.
43 */
44#define INTC_PRIORITY_LEVELS 16U
45
46/*===========================================================================*/
47/* Module pre-compile time settings. */
48/*===========================================================================*/
49
50/*===========================================================================*/
51/* Derived constants and error checks. */
52/*===========================================================================*/
53
54/*===========================================================================*/
55/* Module data structures and types. */
56/*===========================================================================*/
57
58/*===========================================================================*/
59/* Module macros. */
60/*===========================================================================*/
61
62/**
63 * @name INTC-related macros
64 * @{
65 */
66#define INTC_BCR (*((volatile uint32_t *)(INTC_BASE + 0)))
67#define INTC_CPR(n) (*((volatile uint32_t *)(INTC_BASE + 8 + ((n) * sizeof (uint32_t)))))
68#define INTC_IACKR(n) (*((volatile uint32_t *)(INTC_BASE + 0x10 + ((n) * sizeof (uint32_t)))))
69#define INTC_EOIR(n) (*((volatile uint32_t *)(INTC_BASE + 0x18 + ((n) * sizeof (uint32_t)))))
70#define INTC_PSR(n) (*((volatile uint8_t *)(INTC_BASE + 0x40 + ((n) * sizeof (uint8_t)))))
71/** @} */
72
73/**
74 * @brief Core selection macros for PSR register.
75 */
76#define INTC_PSR_CORE0 0x00
77
78/**
79 * @brief PSR register content helper
80 */
81#define INTC_PSR_ENABLE(cores, prio) ((uint32_t)(cores) | (uint32_t)(prio))
82
83/*===========================================================================*/
84/* External declarations. */
85/*===========================================================================*/
86
87/*===========================================================================*/
88/* Module inline functions. */
89/*===========================================================================*/
90
91#endif /* INTC_H */
92
93/** @} */
diff --git a/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h
new file mode 100644
index 000000000..450a58b0b
--- /dev/null
+++ b/lib/chibios/os/common/startup/e200/devices/SPC56ELxx/ppcparams.h
@@ -0,0 +1,83 @@
1/*
2 ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file SPC56ELxx/ppcparams.h
19 * @brief PowerPC parameters for the SPC56ELxx.
20 *
21 * @defgroup PPC_SPC56ELxx SPC56ELxx Specific Parameters
22 * @ingroup PPC_SPECIFIC
23 * @details This file contains the PowerPC specific parameters for the
24 * SPC56ELxx platform.
25 * @{
26 */
27
28#ifndef PPCPARAMS_H
29#define PPCPARAMS_H
30
31/**
32 * @brief Family identification macro.
33 */
34#define PPC_SPC56ELxx
35
36/**
37 * @brief PPC core model.
38 */
39#define PPC_VARIANT PPC_VARIANT_e200z4
40
41/**
42 * @brief Number of cores.
43 */
44#define PPC_CORE_NUMBER 1
45
46/**
47 * @brief Number of writable bits in IVPR register.
48 */
49#define PPC_IVPR_BITS 16
50
51/**
52 * @brief IVORx registers support.
53 */
54#define PPC_SUPPORTS_IVORS TRUE
55
56/**
57 * @brief Book E instruction set support.
58 */
59#define PPC_SUPPORTS_BOOKE TRUE
60
61/**
62 * @brief VLE instruction set support.
63 */
64#define PPC_SUPPORTS_VLE TRUE
65
66/**
67 * @brief Supports VLS Load/Store Multiple Volatile instructions.
68 */
69#define PPC_SUPPORTS_VLE_MULTI TRUE
70
71/**
72 * @brief Supports the decrementer timer.
73 */
74#define PPC_SUPPORTS_DECREMENTER TRUE
75
76/**
77 * @brief Number of interrupt sources.
78 */
79#define PPC_NUM_VECTORS 256
80
81#endif /* PPCPARAMS_H */
82
83/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 21:16:56 +0100